From: Jani Nikula <jani.nikula@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, ville.syrjala@linux.intel.com, manasi.d.navare@intel.com Subject: [PATCH v3 07/13] drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates Date: Thu, 9 Sep 2021 15:51:59 +0300 [thread overview] Message-ID: <723b29223dc570c8b63c3c6fe5fb772d9db06c0d.1631191763.git.jani.nikula@intel.com> (raw) In-Reply-To: <cover.1631191763.git.jani.nikula@intel.com> 128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b TPS2 for channel equalization. v2: Use intel_dp_is_uhbr Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 508a514c5e37..36b35239da83 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -602,9 +602,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, } /* - * Pick training pattern for channel equalization. Training pattern 4 for HBR3 - * or for 1.4 devices that support it, training Pattern 3 for HBR2 - * or 1.2 devices that support it, Training Pattern 2 otherwise. + * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 + * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or + * 1.2 devices that support it, TPS2 otherwise. */ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, @@ -612,6 +612,10 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, { bool source_tps3, sink_tps3, source_tps4, sink_tps4; + /* UHBR+ use separate 128b/132b TPS2 */ + if (intel_dp_is_uhbr(crtc_state)) + return DP_TRAINING_PATTERN_2; + /* * Intel platforms that support HBR3 also support TPS4. It is mandatory * for all downstream devices that support HBR3. There are no known eDP -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Jani Nikula <jani.nikula@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, ville.syrjala@linux.intel.com, manasi.d.navare@intel.com Subject: [Intel-gfx] [PATCH v3 07/13] drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates Date: Thu, 9 Sep 2021 15:51:59 +0300 [thread overview] Message-ID: <723b29223dc570c8b63c3c6fe5fb772d9db06c0d.1631191763.git.jani.nikula@intel.com> (raw) In-Reply-To: <cover.1631191763.git.jani.nikula@intel.com> 128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b TPS2 for channel equalization. v2: Use intel_dp_is_uhbr Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 508a514c5e37..36b35239da83 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -602,9 +602,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, } /* - * Pick training pattern for channel equalization. Training pattern 4 for HBR3 - * or for 1.4 devices that support it, training Pattern 3 for HBR2 - * or 1.2 devices that support it, Training Pattern 2 otherwise. + * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 + * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or + * 1.2 devices that support it, TPS2 otherwise. */ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, @@ -612,6 +612,10 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, { bool source_tps3, sink_tps3, source_tps4, sink_tps4; + /* UHBR+ use separate 128b/132b TPS2 */ + if (intel_dp_is_uhbr(crtc_state)) + return DP_TRAINING_PATTERN_2; + /* * Intel platforms that support HBR3 also support TPS4. It is mandatory * for all downstream devices that support HBR3. There are no known eDP -- 2.30.2
next prev parent reply other threads:[~2021-09-09 12:53 UTC|newest] Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-09 12:51 [PATCH v3 00/13] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula 2021-09-09 12:51 ` [Intel-gfx] " Jani Nikula 2021-09-09 12:51 ` [PATCH v3 01/13] drm/dp: add DP 2.0 UHBR link rate and bw code conversions Jani Nikula 2021-09-09 12:51 ` [Intel-gfx] " Jani Nikula 2021-09-17 12:40 ` Ville Syrjälä 2021-09-17 12:40 ` [Intel-gfx] " Ville Syrjälä 2021-09-09 12:51 ` [PATCH v3 02/13] drm/dp: use more of the extended receiver cap Jani Nikula 2021-09-09 12:51 ` [Intel-gfx] " Jani Nikula 2021-09-09 16:18 ` Lyude Paul 2021-09-09 16:18 ` Lyude Paul 2021-09-09 16:18 ` Lyude Paul 2021-09-09 16:18 ` [Intel-gfx] " Lyude Paul 2021-09-09 12:51 ` [PATCH v3 03/13] drm/dp: add LTTPR DP 2.0 DPCD addresses Jani Nikula 2021-09-09 12:51 ` [Intel-gfx] " Jani Nikula 2021-09-21 22:58 ` Nathan Chancellor 2021-09-22 0:45 ` Stephen Rothwell 2021-09-22 11:10 ` Jani Nikula 2021-09-22 13:49 ` Alex Deucher 2021-09-22 13:49 ` Alex Deucher 2021-09-22 17:32 ` [PATCH] drm/amd/display: Only define DP 2.0 symbols if not already defined Harry Wentland 2021-09-22 17:32 ` [Intel-gfx] " Harry Wentland 2021-09-09 12:51 ` [PATCH v3 04/13] drm/dp: add helper for extracting adjust 128b/132b TX FFE preset Jani Nikula 2021-09-09 12:51 ` [Intel-gfx] " Jani Nikula 2021-09-09 12:51 ` [PATCH v3 05/13] drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode Jani Nikula 2021-09-09 12:51 ` [Intel-gfx] " Jani Nikula 2021-09-17 12:54 ` Ville Syrjälä 2021-09-17 12:54 ` [Intel-gfx] " Ville Syrjälä 2021-09-09 12:51 ` [PATCH v3 06/13] drm/i915/dp: add helper for checking for UHBR link rate Jani Nikula 2021-09-09 12:51 ` [Intel-gfx] " Jani Nikula 2021-09-17 12:41 ` Ville Syrjälä 2021-09-17 12:41 ` [Intel-gfx] " Ville Syrjälä 2021-09-09 12:51 ` Jani Nikula [this message] 2021-09-09 12:51 ` [Intel-gfx] [PATCH v3 07/13] drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates Jani Nikula 2021-09-09 12:52 ` [PATCH v3 08/13] drm/i915/dp: select 128b/132b channel encoding for UHBR rates Jani Nikula 2021-09-09 12:52 ` [Intel-gfx] " Jani Nikula 2021-09-09 12:52 ` [PATCH v3 09/13] drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 Jani Nikula 2021-09-09 12:52 ` [Intel-gfx] " Jani Nikula 2021-09-09 12:52 ` [PATCH v3 10/13] drm/i915/dp: add HAS_DP20 macro Jani Nikula 2021-09-09 12:52 ` [Intel-gfx] " Jani Nikula 2021-09-17 12:42 ` Ville Syrjälä 2021-09-17 12:42 ` [Intel-gfx] " Ville Syrjälä 2021-09-09 12:52 ` [PATCH v3 11/13] drm/i915/dg2: use 128b/132b transcoder DDI mode Jani Nikula 2021-09-09 12:52 ` [Intel-gfx] " Jani Nikula 2021-09-17 12:51 ` Ville Syrjälä 2021-09-17 12:51 ` [Intel-gfx] " Ville Syrjälä 2021-09-09 12:52 ` [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b Jani Nikula 2021-09-09 12:52 ` [Intel-gfx] " Jani Nikula 2021-09-17 12:53 ` [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} " Ville Syrjälä 2021-09-17 12:53 ` [Intel-gfx] [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} " Ville Syrjälä 2021-09-21 8:44 ` Jani Nikula 2021-09-21 8:44 ` [Intel-gfx] " Jani Nikula 2021-09-09 12:52 ` [PATCH v3 13/13] drm/i915/dg2: update link training " Jani Nikula 2021-09-09 12:52 ` [Intel-gfx] " Jani Nikula 2021-09-09 13:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: dp 2.0 enabling prep work (rev3) Patchwork 2021-09-09 13:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-09-09 14:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-09-09 16:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-09-17 12:54 ` [PATCH v3 00/13] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula 2021-09-17 12:54 ` [Intel-gfx] " Jani Nikula 2021-09-17 16:56 ` Maxime Ripard 2021-09-17 16:56 ` [Intel-gfx] " Maxime Ripard 2021-09-21 8:44 ` Jani Nikula 2021-09-21 8:44 ` [Intel-gfx] " Jani Nikula 2021-09-22 12:54 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dp: dp 2.0 enabling prep work (rev4) Patchwork 2021-09-22 18:24 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dp: dp 2.0 enabling prep work (rev5) Patchwork
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