From: "Víctor Colombo" <victor.colombo@eldorado.org.br>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Alistair Francis <alistair23@gmail.com>,
Frank Chang <frank.chang@sifive.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: Re: [PATCH 1/5] target/riscv: Fix "G" extension expansion typing
Date: Mon, 16 May 2022 14:22:33 -0300 [thread overview]
Message-ID: <75b10b8f-b3e0-ca48-f5ef-bf8a4fc5c0ee@eldorado.org.br> (raw)
In-Reply-To: <07e4f9011587dc8023b616477ecdf02282fe6232.1652435138.git.research_trasio@irq.a4lg.com>
On 13/05/2022 06:45, Tsukasa OI wrote:
> [E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de e-mail suspeito entre imediatamente em contato com o DTI.
>
> Because ext_? members are in bool type, operator `&&' should be used
> instead of `&'.
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
> ---
> target/riscv/cpu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ccacdee215..00bf26ec8b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -596,8 +596,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
> - cpu->cfg.ext_a & cpu->cfg.ext_f &
> + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
> + cpu->cfg.ext_a && cpu->cfg.ext_f &&
> cpu->cfg.ext_d)) {
> warn_report("Setting G will also set IMAFD");
> cpu->cfg.ext_i = true;
> --
> 2.34.1
>
>
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
--
Víctor Cora Colombo
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
next prev parent reply other threads:[~2022-05-16 17:45 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-13 9:45 [PATCH 0/5] target/riscv: Enhanced ISA extension checks Tsukasa OI
2022-05-13 9:45 ` [PATCH 1/5] target/riscv: Fix "G" extension expansion typing Tsukasa OI
2022-05-16 17:22 ` Víctor Colombo [this message]
2022-05-13 9:45 ` [PATCH 2/5] target/riscv: Disable "G" by default Tsukasa OI
2022-05-17 0:39 ` Alistair Francis
2022-05-13 9:45 ` [PATCH 3/5] target/riscv: Change "G" expansion Tsukasa OI
2022-05-13 9:45 ` [PATCH 4/5] target/riscv: FP extension requirements Tsukasa OI
2022-05-13 9:45 ` [PATCH 5/5] target/riscv: Move/refactor ISA extension checks Tsukasa OI
2022-05-15 2:56 ` [PATCH v2 0/5] target/riscv: Enhanced " Tsukasa OI
2022-05-15 2:56 ` [PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion Tsukasa OI
2022-05-16 17:56 ` Víctor Colombo
2022-05-17 0:38 ` Alistair Francis
2022-05-15 2:56 ` [PATCH v2 2/5] target/riscv: Disable "G" by default Tsukasa OI
2022-05-16 18:04 ` Víctor Colombo
2022-05-24 9:07 ` Tsukasa OI
2022-05-24 15:48 ` Víctor Colombo
2022-05-15 2:56 ` [PATCH v2 3/5] target/riscv: Change "G" expansion Tsukasa OI
2022-05-17 0:40 ` Alistair Francis
2022-05-15 2:56 ` [PATCH v2 4/5] target/riscv: FP extension requirements Tsukasa OI
2022-05-15 14:37 ` Weiwei Li
2022-05-15 14:45 ` Tsukasa OI
2022-05-15 15:23 ` Weiwei Li
2022-05-17 0:52 ` Alistair Francis
2022-05-15 2:56 ` [PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks Tsukasa OI
2022-05-16 3:12 ` Weiwei Li
2022-05-17 1:37 ` Alistair Francis
2022-05-17 2:17 ` [PATCH 0/5] target/riscv: Enhanced " Alistair Francis
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