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From: Alistair Francis <alistair23@gmail.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Frank Chang <frank.chang@sifive.com>,
	 "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH v2 4/5] target/riscv: FP extension requirements
Date: Tue, 17 May 2022 10:52:21 +1000	[thread overview]
Message-ID: <CAKmqyKPUZ5gH=XSJ_C=7uU8DnNgo31qor_sn5x15c9ZBrF-2zw@mail.gmail.com> (raw)
In-Reply-To: <00e7b1c6060dab32ac7d49813b1ca84d3eb63298.1652583332.git.research_trasio@irq.a4lg.com>

On Sun, May 15, 2022 at 12:56 PM Tsukasa OI
<research_trasio@irq.a4lg.com> wrote:
>
> QEMU allowed inconsistent configurations that made floating point
> arithmetic effectively unusable.
>
> This commit adds certain checks for consistent FP arithmetic:
>
> -   F requires Zicsr
> -   Zfinx requires Zicsr
> -   Zfh/Zfhmin require F
> -   D requires F
> -   V requires D
>
> Because F/D/Zicsr are enabled by default (and an error will not occur unless
> we manually disable one or more of prerequisites), this commit just enforces
> the user to give consistent combinations.
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0854ca9103..f910a41407 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -610,11 +610,36 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>              cpu->cfg.ext_ifencei = true;
>          }
>
> +        if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
> +            error_setg(errp, "F extension requires Zicsr");
> +            return;
> +        }
> +
> +        if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
> +            error_setg(errp, "Zfh/Zfhmin extensions require F extension");
> +            return;
> +        }
> +
> +        if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
> +            error_setg(errp, "D extension requires F extension");
> +            return;
> +        }
> +
> +        if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
> +            error_setg(errp, "V extension requires D extension");
> +            return;
> +        }
> +
>          if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
>              cpu->cfg.ext_zhinxmin) {
>              cpu->cfg.ext_zfinx = true;
>          }
>
> +        if (cpu->cfg.ext_zfinx && !cpu->cfg.ext_icsr) {
> +            error_setg(errp, "Zfinx extension requires Zicsr");
> +            return;
> +        }
> +
>          if (cpu->cfg.ext_zk) {
>              cpu->cfg.ext_zkn = true;
>              cpu->cfg.ext_zkr = true;
> --
> 2.34.1
>


  parent reply	other threads:[~2022-05-17  0:54 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-13  9:45 [PATCH 0/5] target/riscv: Enhanced ISA extension checks Tsukasa OI
2022-05-13  9:45 ` [PATCH 1/5] target/riscv: Fix "G" extension expansion typing Tsukasa OI
2022-05-16 17:22   ` Víctor Colombo
2022-05-13  9:45 ` [PATCH 2/5] target/riscv: Disable "G" by default Tsukasa OI
2022-05-17  0:39   ` Alistair Francis
2022-05-13  9:45 ` [PATCH 3/5] target/riscv: Change "G" expansion Tsukasa OI
2022-05-13  9:45 ` [PATCH 4/5] target/riscv: FP extension requirements Tsukasa OI
2022-05-13  9:45 ` [PATCH 5/5] target/riscv: Move/refactor ISA extension checks Tsukasa OI
2022-05-15  2:56 ` [PATCH v2 0/5] target/riscv: Enhanced " Tsukasa OI
2022-05-15  2:56   ` [PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion Tsukasa OI
2022-05-16 17:56     ` Víctor Colombo
2022-05-17  0:38     ` Alistair Francis
2022-05-15  2:56   ` [PATCH v2 2/5] target/riscv: Disable "G" by default Tsukasa OI
2022-05-16 18:04     ` Víctor Colombo
2022-05-24  9:07       ` Tsukasa OI
2022-05-24 15:48         ` Víctor Colombo
2022-05-15  2:56   ` [PATCH v2 3/5] target/riscv: Change "G" expansion Tsukasa OI
2022-05-17  0:40     ` Alistair Francis
2022-05-15  2:56   ` [PATCH v2 4/5] target/riscv: FP extension requirements Tsukasa OI
2022-05-15 14:37     ` Weiwei Li
2022-05-15 14:45       ` Tsukasa OI
2022-05-15 15:23         ` Weiwei Li
2022-05-17  0:52     ` Alistair Francis [this message]
2022-05-15  2:56   ` [PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks Tsukasa OI
2022-05-16  3:12     ` Weiwei Li
2022-05-17  1:37     ` Alistair Francis
2022-05-17  2:17 ` [PATCH 0/5] target/riscv: Enhanced " Alistair Francis

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