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From: Alistair Francis <alistair23@gmail.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Frank Chang <frank.chang@sifive.com>,
	 "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion
Date: Tue, 17 May 2022 10:38:02 +1000	[thread overview]
Message-ID: <CAKmqyKO4sMK0tgPNh_DaN77CvJ-ChPt1sxsTnVOzn2+Zm7F6XQ@mail.gmail.com> (raw)
In-Reply-To: <91633f8349253656dd08bc8dc36498a9c7538b10.1652583332.git.research_trasio@irq.a4lg.com>

On Sun, May 15, 2022 at 12:56 PM Tsukasa OI
<research_trasio@irq.a4lg.com> wrote:
>
> Because ext_? members are boolean variables, operator `&&' should be
> used instead of `&'.
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ccacdee215..00bf26ec8b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -596,8 +596,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>              return;
>          }
>
> -        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
> -                                cpu->cfg.ext_a & cpu->cfg.ext_f &
> +        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
> +                                cpu->cfg.ext_a && cpu->cfg.ext_f &&
>                                  cpu->cfg.ext_d)) {
>              warn_report("Setting G will also set IMAFD");
>              cpu->cfg.ext_i = true;
> --
> 2.34.1
>


  parent reply	other threads:[~2022-05-17  0:39 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-13  9:45 [PATCH 0/5] target/riscv: Enhanced ISA extension checks Tsukasa OI
2022-05-13  9:45 ` [PATCH 1/5] target/riscv: Fix "G" extension expansion typing Tsukasa OI
2022-05-16 17:22   ` Víctor Colombo
2022-05-13  9:45 ` [PATCH 2/5] target/riscv: Disable "G" by default Tsukasa OI
2022-05-17  0:39   ` Alistair Francis
2022-05-13  9:45 ` [PATCH 3/5] target/riscv: Change "G" expansion Tsukasa OI
2022-05-13  9:45 ` [PATCH 4/5] target/riscv: FP extension requirements Tsukasa OI
2022-05-13  9:45 ` [PATCH 5/5] target/riscv: Move/refactor ISA extension checks Tsukasa OI
2022-05-15  2:56 ` [PATCH v2 0/5] target/riscv: Enhanced " Tsukasa OI
2022-05-15  2:56   ` [PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion Tsukasa OI
2022-05-16 17:56     ` Víctor Colombo
2022-05-17  0:38     ` Alistair Francis [this message]
2022-05-15  2:56   ` [PATCH v2 2/5] target/riscv: Disable "G" by default Tsukasa OI
2022-05-16 18:04     ` Víctor Colombo
2022-05-24  9:07       ` Tsukasa OI
2022-05-24 15:48         ` Víctor Colombo
2022-05-15  2:56   ` [PATCH v2 3/5] target/riscv: Change "G" expansion Tsukasa OI
2022-05-17  0:40     ` Alistair Francis
2022-05-15  2:56   ` [PATCH v2 4/5] target/riscv: FP extension requirements Tsukasa OI
2022-05-15 14:37     ` Weiwei Li
2022-05-15 14:45       ` Tsukasa OI
2022-05-15 15:23         ` Weiwei Li
2022-05-17  0:52     ` Alistair Francis
2022-05-15  2:56   ` [PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks Tsukasa OI
2022-05-16  3:12     ` Weiwei Li
2022-05-17  1:37     ` Alistair Francis
2022-05-17  2:17 ` [PATCH 0/5] target/riscv: Enhanced " Alistair Francis

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