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From: "Víctor Colombo" <victor.colombo@eldorado.org.br>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
	Alistair Francis <alistair23@gmail.com>,
	Frank Chang <frank.chang@sifive.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: Re: [PATCH v2 2/5] target/riscv: Disable "G" by default
Date: Mon, 16 May 2022 15:04:36 -0300	[thread overview]
Message-ID: <e803a275-c54b-bc9c-430a-1bbbf5b14115@eldorado.org.br> (raw)
In-Reply-To: <cab7205f1d7668f642fa242386543334af6bc1bd.1652583332.git.research_trasio@irq.a4lg.com>

On 14/05/2022 23:56, Tsukasa OI wrote:
> Because "G" virtual extension expands to "IMAFD", we cannot separately
> disable extensions like "F" or "D" without disabling "G".  Because all
> "IMAFD" are enabled by default, it's harmless to disable "G" by default.
> 
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
> ---
>   target/riscv/cpu.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 00bf26ec8b..3ea68d5cd7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -812,7 +812,7 @@ static Property riscv_cpu_properties[] = {
>       /* Defaults for standard extensions */
>       DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
>       DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
> -    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
> +    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
>       DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
>       DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
>       DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
> --
> 2.34.1
> 
> 

I think the logic looks ok, and (with my limited understanding of the
code) I agree on the reasoning for the changes in patches 2 and 3.
Just some clarification needed: where is the value of 'g' checked?
can the behavior change in this patch cause a situation where
IMAFD_Zicsr_Zifencei is set but 'g' is not, or does patch 3
guarantee that in this case 'g' will be set?

Thanks!

-- 
Víctor Cora Colombo
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>


  reply	other threads:[~2022-05-16 18:06 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-13  9:45 [PATCH 0/5] target/riscv: Enhanced ISA extension checks Tsukasa OI
2022-05-13  9:45 ` [PATCH 1/5] target/riscv: Fix "G" extension expansion typing Tsukasa OI
2022-05-16 17:22   ` Víctor Colombo
2022-05-13  9:45 ` [PATCH 2/5] target/riscv: Disable "G" by default Tsukasa OI
2022-05-17  0:39   ` Alistair Francis
2022-05-13  9:45 ` [PATCH 3/5] target/riscv: Change "G" expansion Tsukasa OI
2022-05-13  9:45 ` [PATCH 4/5] target/riscv: FP extension requirements Tsukasa OI
2022-05-13  9:45 ` [PATCH 5/5] target/riscv: Move/refactor ISA extension checks Tsukasa OI
2022-05-15  2:56 ` [PATCH v2 0/5] target/riscv: Enhanced " Tsukasa OI
2022-05-15  2:56   ` [PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion Tsukasa OI
2022-05-16 17:56     ` Víctor Colombo
2022-05-17  0:38     ` Alistair Francis
2022-05-15  2:56   ` [PATCH v2 2/5] target/riscv: Disable "G" by default Tsukasa OI
2022-05-16 18:04     ` Víctor Colombo [this message]
2022-05-24  9:07       ` Tsukasa OI
2022-05-24 15:48         ` Víctor Colombo
2022-05-15  2:56   ` [PATCH v2 3/5] target/riscv: Change "G" expansion Tsukasa OI
2022-05-17  0:40     ` Alistair Francis
2022-05-15  2:56   ` [PATCH v2 4/5] target/riscv: FP extension requirements Tsukasa OI
2022-05-15 14:37     ` Weiwei Li
2022-05-15 14:45       ` Tsukasa OI
2022-05-15 15:23         ` Weiwei Li
2022-05-17  0:52     ` Alistair Francis
2022-05-15  2:56   ` [PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks Tsukasa OI
2022-05-16  3:12     ` Weiwei Li
2022-05-17  1:37     ` Alistair Francis
2022-05-17  2:17 ` [PATCH 0/5] target/riscv: Enhanced " Alistair Francis

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