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From: Alistair Francis <alistair23@gmail.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Frank Chang <frank.chang@sifive.com>,
	 "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH 2/5] target/riscv: Disable "G" by default
Date: Tue, 17 May 2022 10:39:39 +1000	[thread overview]
Message-ID: <CAKmqyKPy+E2ABMPnWfEBd2ASy8u1bZ7RC1HtwsK=EHfAjozfhw@mail.gmail.com> (raw)
In-Reply-To: <def2b95c85943a5a2fa7406dcafbb82fe78bceb4.1652435138.git.research_trasio@irq.a4lg.com>

On Fri, May 13, 2022 at 7:46 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Because "G" virtual extension expands to "IMAFD", we cannot separately
> disable extensions like "F" or "D" without disabling "G".  Because all
> "IMAFD" are enabled by default, it's harmless to disable "G" by default.
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 00bf26ec8b..3ea68d5cd7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -812,7 +812,7 @@ static Property riscv_cpu_properties[] = {
>      /* Defaults for standard extensions */
>      DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
>      DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
> -    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
> +    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
>      DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
>      DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
>      DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
> --
> 2.34.1
>


  reply	other threads:[~2022-05-17  0:41 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-13  9:45 [PATCH 0/5] target/riscv: Enhanced ISA extension checks Tsukasa OI
2022-05-13  9:45 ` [PATCH 1/5] target/riscv: Fix "G" extension expansion typing Tsukasa OI
2022-05-16 17:22   ` Víctor Colombo
2022-05-13  9:45 ` [PATCH 2/5] target/riscv: Disable "G" by default Tsukasa OI
2022-05-17  0:39   ` Alistair Francis [this message]
2022-05-13  9:45 ` [PATCH 3/5] target/riscv: Change "G" expansion Tsukasa OI
2022-05-13  9:45 ` [PATCH 4/5] target/riscv: FP extension requirements Tsukasa OI
2022-05-13  9:45 ` [PATCH 5/5] target/riscv: Move/refactor ISA extension checks Tsukasa OI
2022-05-15  2:56 ` [PATCH v2 0/5] target/riscv: Enhanced " Tsukasa OI
2022-05-15  2:56   ` [PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion Tsukasa OI
2022-05-16 17:56     ` Víctor Colombo
2022-05-17  0:38     ` Alistair Francis
2022-05-15  2:56   ` [PATCH v2 2/5] target/riscv: Disable "G" by default Tsukasa OI
2022-05-16 18:04     ` Víctor Colombo
2022-05-24  9:07       ` Tsukasa OI
2022-05-24 15:48         ` Víctor Colombo
2022-05-15  2:56   ` [PATCH v2 3/5] target/riscv: Change "G" expansion Tsukasa OI
2022-05-17  0:40     ` Alistair Francis
2022-05-15  2:56   ` [PATCH v2 4/5] target/riscv: FP extension requirements Tsukasa OI
2022-05-15 14:37     ` Weiwei Li
2022-05-15 14:45       ` Tsukasa OI
2022-05-15 15:23         ` Weiwei Li
2022-05-17  0:52     ` Alistair Francis
2022-05-15  2:56   ` [PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks Tsukasa OI
2022-05-16  3:12     ` Weiwei Li
2022-05-17  1:37     ` Alistair Francis
2022-05-17  2:17 ` [PATCH 0/5] target/riscv: Enhanced " Alistair Francis

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