From: Thomas Gleixner <tglx@linutronix.de> To: Fenghua Yu <fenghua.yu@intel.com>, Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>, Peter Zijlstra <peterz@infradead.org>, Andy Lutomirski <luto@kernel.org>, Dave Hansen <dave.hansen@intel.com>, Tony Luck <tony.luck@intel.com>, Lu Baolu <baolu.lu@linux.intel.com>, Joerg Roedel <joro@8bytes.org>, Josh Poimboeuf <jpoimboe@redhat.com>, Dave Jiang <dave.jiang@intel.com>, Jacob Jun Pan <jacob.jun.pan@intel.com>, Ashok Raj <ashok.raj@intel.com>, Ravi V Shankar <ravi.v.shankar@intel.com> Cc: iommu@lists.linux-foundation.org, x86 <x86@kernel.org>, linux-kernel <linux-kernel@vger.kernel.org>, Fenghua Yu <fenghua.yu@intel.com> Subject: Re: [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Date: Thu, 23 Sep 2021 13:31:29 +0200 [thread overview] Message-ID: <875yurh6jy.ffs@tglx> (raw) In-Reply-To: <20210920192349.2602141-5-fenghua.yu@intel.com> On Mon, Sep 20 2021 at 19:23, Fenghua Yu wrote: > diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c > index c8def1b7f8fb..8a89b2cecd77 100644 > --- a/arch/x86/kernel/fpu/xstate.c > +++ b/arch/x86/kernel/fpu/xstate.c > @@ -1289,3 +1289,62 @@ int proc_pid_arch_status(struct seq_file *m, struct pid_namespace *ns, > return 0; > } > #endif /* CONFIG_PROC_PID_ARCH_STATUS */ > + > +#ifdef CONFIG_INTEL_IOMMU_SVM > +/** > + * fpu__pasid_write - Write the current task's PASID state/MSR. > + * @pasid: the PASID > + * > + * The PASID is written to the IA32_PASID MSR directly if the MSR is active. > + * Otherwise it's written to the PASID. The IA32_PASID MSR should contain written to the PASID? What's 'the PASID' ? > + * the PASID after returning to the user. > + * > + * This is called only when ENQCMD is enabled. Well, yes, but it does not explain why it is called and from which context. > + */ > +void fpu__pasid_write(u32 pasid) > +{ > + struct xregs_state *xsave = ¤t->thread.fpu.state.xsave; > + u64 msr_val = pasid | MSR_IA32_PASID_VALID; > + struct fpu *fpu = ¤t->thread.fpu; > + > + /* > + * ENQCMD always uses the compacted XSAVE format. Ensure the buffer > + * has space for the PASID. > + */ > + BUG_ON(!(xsave->header.xcomp_bv & XFEATURE_MASK_PASID)); > + > + fpregs_lock(); > + > + /* > + * If the task's FPU doesn't need to be loaded or is valid, directly > + * write the IA32_PASID MSR. Otherwise, write the PASID state and > + * the MSR will be loaded from the PASID state before returning to > + * the user. > + */ > + if (!test_thread_flag(TIF_NEED_FPU_LOAD) || > + fpregs_state_valid(fpu, smp_processor_id())) { > + wrmsrl(MSR_IA32_PASID, msr_val); > + } else { > + struct ia32_pasid_state *ppasid_state; > + /* > + * Mark XFEATURE_PASID as non-init in the XSAVE buffer. > + * This ensures that a subsequent XRSTOR will see the new > + * value instead of writing the init value to the MSR. > + */ This and the above wrmsrl() assume that @pasid is valid which might be correct, but I don't see any information about pasid lifetime. I assume that there is no way to drop a PASID, right? > + xsave->header.xfeatures |= XFEATURE_MASK_PASID; > + ppasid_state = get_xsave_addr(xsave, XFEATURE_PASID); > + /* > + * ppasid_state shouldn't be NULL because XFEATURE_PASID > + * was set just now. > + * > + * Please note that the following operation is a "write only" > + * operation on the PASID state and it writes the *ENTIRE* > + * state component. Please don't blindly copy this code to > + * modify other XSAVE states. > + */ > + ppasid_state->pasid = msr_val; > + } > + > + fpregs_unlock(); > +} > +#endif /* CONFIG_INTEL_IOMMU_SVM */ > diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c > index a58800973aed..a25d738ae839 100644 > --- a/arch/x86/kernel/traps.c > +++ b/arch/x86/kernel/traps.c > > +static bool fixup_pasid_exception(void) > +{ > + if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) > + return false; > + > + return __fixup_pasid_exception(); > +} Ok, so here is the hook into #GP which then calls out into: > --- a/drivers/iommu/intel/svm.c > +++ b/drivers/iommu/intel/svm.c > @@ -1179,3 +1179,35 @@ int intel_svm_page_response(struct device *dev, > mutex_unlock(&pasid_mutex); > return ret; > } > + > +/* > + * Try to figure out if there is a PASID MSR value to propagate to the > + * thread taking the #GP. > + */ > +bool __fixup_pasid_exception(void) > +{ > + u32 pasid; > + > + /* > + * This function is called only when this #GP was triggered from user > + * space. So the mm cannot be NULL. > + */ > + pasid = current->mm->pasid; > + > + /* If no PASID is allocated, there is nothing to propagate. */ > + if (pasid == PASID_DISABLED) > + return false; > + > + /* > + * If the current task already has a valid PASID MSR, then the #GP > + * fault must be for some non-ENQCMD related reason. > + */ > + if (current->has_valid_pasid) > + return false; > + > + /* Fix up the MSR by the PASID in the mm. */ > + fpu__pasid_write(pasid); > + current->has_valid_pasid = 1; > + > + return true; > +} What is INTEL SVM specific on this? Nothing at all. If there is a valid PASID in current->mm and the MSR has not been updated yet, write it. Otherwise bail. Thanks, tglx
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de> To: Fenghua Yu <fenghua.yu@intel.com>, Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>, Peter Zijlstra <peterz@infradead.org>, Andy Lutomirski <luto@kernel.org>, Dave Hansen <dave.hansen@intel.com>, Tony Luck <tony.luck@intel.com>, Lu Baolu <baolu.lu@linux.intel.com>, Joerg Roedel <joro@8bytes.org>, Josh Poimboeuf <jpoimboe@redhat.com>, Dave Jiang <dave.jiang@intel.com>, Jacob Jun Pan <jacob.jun.pan@intel.com>, Ashok Raj <ashok.raj@intel.com>, Ravi V Shankar <ravi.v.shankar@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com>, iommu@lists.linux-foundation.org, x86 <x86@kernel.org>, linux-kernel <linux-kernel@vger.kernel.org> Subject: Re: [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Date: Thu, 23 Sep 2021 13:31:29 +0200 [thread overview] Message-ID: <875yurh6jy.ffs@tglx> (raw) In-Reply-To: <20210920192349.2602141-5-fenghua.yu@intel.com> On Mon, Sep 20 2021 at 19:23, Fenghua Yu wrote: > diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c > index c8def1b7f8fb..8a89b2cecd77 100644 > --- a/arch/x86/kernel/fpu/xstate.c > +++ b/arch/x86/kernel/fpu/xstate.c > @@ -1289,3 +1289,62 @@ int proc_pid_arch_status(struct seq_file *m, struct pid_namespace *ns, > return 0; > } > #endif /* CONFIG_PROC_PID_ARCH_STATUS */ > + > +#ifdef CONFIG_INTEL_IOMMU_SVM > +/** > + * fpu__pasid_write - Write the current task's PASID state/MSR. > + * @pasid: the PASID > + * > + * The PASID is written to the IA32_PASID MSR directly if the MSR is active. > + * Otherwise it's written to the PASID. The IA32_PASID MSR should contain written to the PASID? What's 'the PASID' ? > + * the PASID after returning to the user. > + * > + * This is called only when ENQCMD is enabled. Well, yes, but it does not explain why it is called and from which context. > + */ > +void fpu__pasid_write(u32 pasid) > +{ > + struct xregs_state *xsave = ¤t->thread.fpu.state.xsave; > + u64 msr_val = pasid | MSR_IA32_PASID_VALID; > + struct fpu *fpu = ¤t->thread.fpu; > + > + /* > + * ENQCMD always uses the compacted XSAVE format. Ensure the buffer > + * has space for the PASID. > + */ > + BUG_ON(!(xsave->header.xcomp_bv & XFEATURE_MASK_PASID)); > + > + fpregs_lock(); > + > + /* > + * If the task's FPU doesn't need to be loaded or is valid, directly > + * write the IA32_PASID MSR. Otherwise, write the PASID state and > + * the MSR will be loaded from the PASID state before returning to > + * the user. > + */ > + if (!test_thread_flag(TIF_NEED_FPU_LOAD) || > + fpregs_state_valid(fpu, smp_processor_id())) { > + wrmsrl(MSR_IA32_PASID, msr_val); > + } else { > + struct ia32_pasid_state *ppasid_state; > + /* > + * Mark XFEATURE_PASID as non-init in the XSAVE buffer. > + * This ensures that a subsequent XRSTOR will see the new > + * value instead of writing the init value to the MSR. > + */ This and the above wrmsrl() assume that @pasid is valid which might be correct, but I don't see any information about pasid lifetime. I assume that there is no way to drop a PASID, right? > + xsave->header.xfeatures |= XFEATURE_MASK_PASID; > + ppasid_state = get_xsave_addr(xsave, XFEATURE_PASID); > + /* > + * ppasid_state shouldn't be NULL because XFEATURE_PASID > + * was set just now. > + * > + * Please note that the following operation is a "write only" > + * operation on the PASID state and it writes the *ENTIRE* > + * state component. Please don't blindly copy this code to > + * modify other XSAVE states. > + */ > + ppasid_state->pasid = msr_val; > + } > + > + fpregs_unlock(); > +} > +#endif /* CONFIG_INTEL_IOMMU_SVM */ > diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c > index a58800973aed..a25d738ae839 100644 > --- a/arch/x86/kernel/traps.c > +++ b/arch/x86/kernel/traps.c > > +static bool fixup_pasid_exception(void) > +{ > + if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) > + return false; > + > + return __fixup_pasid_exception(); > +} Ok, so here is the hook into #GP which then calls out into: > --- a/drivers/iommu/intel/svm.c > +++ b/drivers/iommu/intel/svm.c > @@ -1179,3 +1179,35 @@ int intel_svm_page_response(struct device *dev, > mutex_unlock(&pasid_mutex); > return ret; > } > + > +/* > + * Try to figure out if there is a PASID MSR value to propagate to the > + * thread taking the #GP. > + */ > +bool __fixup_pasid_exception(void) > +{ > + u32 pasid; > + > + /* > + * This function is called only when this #GP was triggered from user > + * space. So the mm cannot be NULL. > + */ > + pasid = current->mm->pasid; > + > + /* If no PASID is allocated, there is nothing to propagate. */ > + if (pasid == PASID_DISABLED) > + return false; > + > + /* > + * If the current task already has a valid PASID MSR, then the #GP > + * fault must be for some non-ENQCMD related reason. > + */ > + if (current->has_valid_pasid) > + return false; > + > + /* Fix up the MSR by the PASID in the mm. */ > + fpu__pasid_write(pasid); > + current->has_valid_pasid = 1; > + > + return true; > +} What is INTEL SVM specific on this? Nothing at all. If there is a valid PASID in current->mm and the MSR has not been updated yet, write it. Otherwise bail. Thanks, tglx _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2021-09-23 11:31 UTC|newest] Thread overview: 154+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-20 19:23 [PATCH 0/8] Re-enable ENQCMD and PASID MSR Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-20 19:23 ` [PATCH 1/8] iommu/vt-d: Clean up unused PASID updating functions Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-29 7:34 ` Lu Baolu 2021-09-29 7:34 ` Lu Baolu 2021-09-30 0:40 ` Fenghua Yu 2021-09-30 0:40 ` Fenghua Yu 2021-09-20 19:23 ` [PATCH 2/8] x86/process: Clear PASID state for a newly forked/cloned thread Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-20 19:23 ` [PATCH 3/8] sched: Define and initialize a flag to identify valid PASID in the task Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-20 19:23 ` [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-22 21:07 ` Peter Zijlstra 2021-09-22 21:07 ` Peter Zijlstra 2021-09-22 21:11 ` Peter Zijlstra 2021-09-22 21:11 ` Peter Zijlstra 2021-09-22 21:26 ` Luck, Tony 2021-09-22 21:26 ` Luck, Tony 2021-09-23 7:03 ` Peter Zijlstra 2021-09-23 7:03 ` Peter Zijlstra 2021-09-22 21:33 ` Dave Hansen 2021-09-22 21:33 ` Dave Hansen 2021-09-23 7:05 ` Peter Zijlstra 2021-09-23 7:05 ` Peter Zijlstra 2021-09-22 21:36 ` Fenghua Yu 2021-09-22 21:36 ` Fenghua Yu 2021-09-22 23:39 ` Fenghua Yu 2021-09-22 23:39 ` Fenghua Yu 2021-09-23 17:14 ` Luck, Tony 2021-09-23 17:14 ` Luck, Tony 2021-09-24 13:37 ` Peter Zijlstra 2021-09-24 13:37 ` Peter Zijlstra 2021-09-24 15:39 ` Luck, Tony 2021-09-24 15:39 ` Luck, Tony 2021-09-29 9:00 ` Peter Zijlstra 2021-09-29 9:00 ` Peter Zijlstra 2021-09-23 11:31 ` Thomas Gleixner [this message] 2021-09-23 11:31 ` Thomas Gleixner 2021-09-23 23:17 ` Andy Lutomirski 2021-09-23 23:17 ` Andy Lutomirski 2021-09-24 2:56 ` Fenghua Yu 2021-09-24 2:56 ` Fenghua Yu 2021-09-24 5:12 ` Andy Lutomirski 2021-09-24 5:12 ` Andy Lutomirski 2021-09-27 21:02 ` Luck, Tony 2021-09-27 21:02 ` Luck, Tony 2021-09-27 23:51 ` Dave Hansen 2021-09-27 23:51 ` Dave Hansen 2021-09-28 18:50 ` Luck, Tony 2021-09-28 18:50 ` Luck, Tony 2021-09-28 19:19 ` Dave Hansen 2021-09-28 19:19 ` Dave Hansen 2021-09-28 20:28 ` Luck, Tony 2021-09-28 20:28 ` Luck, Tony 2021-09-28 20:55 ` Dave Hansen 2021-09-28 20:55 ` Dave Hansen 2021-09-28 23:10 ` Luck, Tony 2021-09-28 23:10 ` Luck, Tony 2021-09-28 23:50 ` Fenghua Yu 2021-09-28 23:50 ` Fenghua Yu 2021-09-29 0:08 ` Luck, Tony 2021-09-29 0:08 ` Luck, Tony 2021-09-29 0:26 ` Yu, Fenghua 2021-09-29 0:26 ` Yu, Fenghua 2021-09-29 1:06 ` Luck, Tony 2021-09-29 1:06 ` Luck, Tony 2021-09-29 1:16 ` Fenghua Yu 2021-09-29 1:16 ` Fenghua Yu 2021-09-29 2:11 ` Luck, Tony 2021-09-29 2:11 ` Luck, Tony 2021-09-29 1:56 ` Yu, Fenghua 2021-09-29 1:56 ` Yu, Fenghua 2021-09-29 2:15 ` Luck, Tony 2021-09-29 2:15 ` Luck, Tony 2021-09-29 16:58 ` Andy Lutomirski 2021-09-29 16:58 ` Andy Lutomirski 2021-09-29 17:07 ` Luck, Tony 2021-09-29 17:07 ` Luck, Tony 2021-09-29 17:48 ` Andy Lutomirski 2021-09-29 17:48 ` Andy Lutomirski 2021-09-20 19:23 ` [PATCH 5/8] x86/mmu: Add mm-based PASID refcounting Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-23 5:43 ` Lu Baolu 2021-09-23 5:43 ` Lu Baolu 2021-09-30 0:44 ` Fenghua Yu 2021-09-30 0:44 ` Fenghua Yu 2021-09-23 14:36 ` Thomas Gleixner 2021-09-23 14:36 ` Thomas Gleixner 2021-09-23 16:40 ` Luck, Tony 2021-09-23 16:40 ` Luck, Tony 2021-09-23 17:48 ` Thomas Gleixner 2021-09-23 17:48 ` Thomas Gleixner 2021-09-24 13:18 ` Thomas Gleixner 2021-09-24 13:18 ` Thomas Gleixner 2021-09-24 16:12 ` Luck, Tony 2021-09-24 16:12 ` Luck, Tony 2021-09-24 23:03 ` Andy Lutomirski 2021-09-24 23:03 ` Andy Lutomirski 2021-09-24 23:11 ` Luck, Tony 2021-09-24 23:11 ` Luck, Tony 2021-09-29 9:54 ` Peter Zijlstra 2021-09-29 9:54 ` Peter Zijlstra 2021-09-29 12:28 ` Thomas Gleixner 2021-09-29 12:28 ` Thomas Gleixner 2021-09-29 16:51 ` Luck, Tony 2021-09-29 16:51 ` Luck, Tony 2021-09-29 17:07 ` Fenghua Yu 2021-09-29 17:07 ` Fenghua Yu 2021-09-29 16:59 ` Andy Lutomirski 2021-09-29 16:59 ` Andy Lutomirski 2021-09-29 17:15 ` Thomas Gleixner 2021-09-29 17:15 ` Thomas Gleixner 2021-09-29 17:41 ` Luck, Tony 2021-09-29 17:41 ` Luck, Tony 2021-09-29 17:46 ` Andy Lutomirski 2021-09-29 17:46 ` Andy Lutomirski 2021-09-29 18:07 ` Fenghua Yu 2021-09-29 18:07 ` Fenghua Yu 2021-09-29 18:31 ` Luck, Tony 2021-09-29 18:31 ` Luck, Tony 2021-09-29 20:07 ` Thomas Gleixner 2021-09-29 20:07 ` Thomas Gleixner 2021-09-24 16:12 ` Fenghua Yu 2021-09-24 16:12 ` Fenghua Yu 2021-09-25 23:13 ` Thomas Gleixner 2021-09-25 23:13 ` Thomas Gleixner 2021-09-28 16:36 ` Fenghua Yu 2021-09-28 16:36 ` Fenghua Yu 2021-09-23 23:09 ` Andy Lutomirski 2021-09-23 23:09 ` Andy Lutomirski 2021-09-23 23:22 ` Luck, Tony 2021-09-23 23:22 ` Luck, Tony 2021-09-24 5:17 ` Andy Lutomirski 2021-09-24 5:17 ` Andy Lutomirski 2021-09-20 19:23 ` [PATCH 6/8] x86/cpufeatures: Re-enable ENQCMD Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-20 19:23 ` [PATCH 7/8] tools/objtool: Check for use of the ENQCMD instruction in the kernel Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-22 21:03 ` Peter Zijlstra 2021-09-22 21:03 ` Peter Zijlstra 2021-09-22 23:44 ` Fenghua Yu 2021-09-22 23:44 ` Fenghua Yu 2021-09-23 7:17 ` Peter Zijlstra 2021-09-23 7:17 ` Peter Zijlstra 2021-09-23 15:26 ` Fenghua Yu 2021-09-23 15:26 ` Fenghua Yu 2021-09-24 0:55 ` Josh Poimboeuf 2021-09-24 0:55 ` Josh Poimboeuf 2021-09-24 0:57 ` Fenghua Yu 2021-09-24 0:57 ` Fenghua Yu 2021-09-20 19:23 ` [PATCH 8/8] docs: x86: Change documentation for SVA (Shared Virtual Addressing) Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu
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