From: Peter Zijlstra <peterz@infradead.org> To: Dave Hansen <dave.hansen@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com>, Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>, Andy Lutomirski <luto@kernel.org>, Tony Luck <tony.luck@intel.com>, Lu Baolu <baolu.lu@linux.intel.com>, Joerg Roedel <joro@8bytes.org>, Josh Poimboeuf <jpoimboe@redhat.com>, Dave Jiang <dave.jiang@intel.com>, Jacob Jun Pan <jacob.jun.pan@intel.com>, Ashok Raj <ashok.raj@intel.com>, Ravi V Shankar <ravi.v.shankar@intel.com>, iommu@lists.linux-foundation.org, x86 <x86@kernel.org>, linux-kernel <linux-kernel@vger.kernel.org> Subject: Re: [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Date: Thu, 23 Sep 2021 09:05:00 +0200 [thread overview] Message-ID: <YUwnHDUKfvNKQgPF@hirez.programming.kicks-ass.net> (raw) In-Reply-To: <a5944e66-0552-d919-bd11-d9eced48bb45@intel.com> On Wed, Sep 22, 2021 at 02:33:09PM -0700, Dave Hansen wrote: > On 9/22/21 2:11 PM, Peter Zijlstra wrote: > >>> +static bool fixup_pasid_exception(void) > >>> +{ > >>> + if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) > >>> + return false; > >>> + > >>> + return __fixup_pasid_exception(); > >>> +} > > That is, shouldn't the above at the very least decode the instruction > > causing the #GP and check it's this ENQCMD thing? > > To reiterate: on systems with no X86_FEATURE_ENQCMD, there is basically > no additional overhead. It isn't worth doing decoding there. Well, they won't get past the X86_FEATURE check anyway, so who cares. > On systems with X86_FEATURE_ENQCMD, but where it is unused, the #GP > handler gets some new overhead on every #GP. Basically: > > > + pasid = current->mm->pasid; > > + if (pasid == PASID_DISABLED) > > + return false; > > That's still pretty cheap. Probably not worth doing decoding there either. > > So, that leaves us with if you are: > 1. On system with X86_FEATURE_ENQCMD > 2. In a process/mm that has an allocated pasid > 3. Your *task* does not have the MSR set > 4. You get a #GP for some other reason > > Then, you'll do this double-#GP dance. > > So, instruction decoding could absolutely be added between steps 3 and > 4. It would absolutely save doing the double-#GP in cases where 1/2/3 > are met. But, I wouldn't move it up above and of the 1/2/3 checks > because they're way cheaper than instruction decoding. > > In the end, it didn't seem worth it to me to be optimizing a relatively > rare path which 99% of the time ends up in a crash. > > If you want instruction decoding in here, though, just say the word. :) Instruction deoding makes it obvious you only consume your own #GP, the alternative is a comment that explains this reasoning. Having neither gets you confusion as per this thread.
WARNING: multiple messages have this Message-ID (diff)
From: Peter Zijlstra <peterz@infradead.org> To: Dave Hansen <dave.hansen@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com>, Tony Luck <tony.luck@intel.com>, Dave Jiang <dave.jiang@intel.com>, Ashok Raj <ashok.raj@intel.com>, Ravi V Shankar <ravi.v.shankar@intel.com>, x86 <x86@kernel.org>, linux-kernel <linux-kernel@vger.kernel.org>, iommu@lists.linux-foundation.org, Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>, Jacob Jun Pan <jacob.jun.pan@intel.com>, Andy Lutomirski <luto@kernel.org>, Josh Poimboeuf <jpoimboe@redhat.com>, Thomas Gleixner <tglx@linutronix.de> Subject: Re: [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Date: Thu, 23 Sep 2021 09:05:00 +0200 [thread overview] Message-ID: <YUwnHDUKfvNKQgPF@hirez.programming.kicks-ass.net> (raw) In-Reply-To: <a5944e66-0552-d919-bd11-d9eced48bb45@intel.com> On Wed, Sep 22, 2021 at 02:33:09PM -0700, Dave Hansen wrote: > On 9/22/21 2:11 PM, Peter Zijlstra wrote: > >>> +static bool fixup_pasid_exception(void) > >>> +{ > >>> + if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) > >>> + return false; > >>> + > >>> + return __fixup_pasid_exception(); > >>> +} > > That is, shouldn't the above at the very least decode the instruction > > causing the #GP and check it's this ENQCMD thing? > > To reiterate: on systems with no X86_FEATURE_ENQCMD, there is basically > no additional overhead. It isn't worth doing decoding there. Well, they won't get past the X86_FEATURE check anyway, so who cares. > On systems with X86_FEATURE_ENQCMD, but where it is unused, the #GP > handler gets some new overhead on every #GP. Basically: > > > + pasid = current->mm->pasid; > > + if (pasid == PASID_DISABLED) > > + return false; > > That's still pretty cheap. Probably not worth doing decoding there either. > > So, that leaves us with if you are: > 1. On system with X86_FEATURE_ENQCMD > 2. In a process/mm that has an allocated pasid > 3. Your *task* does not have the MSR set > 4. You get a #GP for some other reason > > Then, you'll do this double-#GP dance. > > So, instruction decoding could absolutely be added between steps 3 and > 4. It would absolutely save doing the double-#GP in cases where 1/2/3 > are met. But, I wouldn't move it up above and of the 1/2/3 checks > because they're way cheaper than instruction decoding. > > In the end, it didn't seem worth it to me to be optimizing a relatively > rare path which 99% of the time ends up in a crash. > > If you want instruction decoding in here, though, just say the word. :) Instruction deoding makes it obvious you only consume your own #GP, the alternative is a comment that explains this reasoning. Having neither gets you confusion as per this thread. _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2021-09-23 7:05 UTC|newest] Thread overview: 154+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-20 19:23 [PATCH 0/8] Re-enable ENQCMD and PASID MSR Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-20 19:23 ` [PATCH 1/8] iommu/vt-d: Clean up unused PASID updating functions Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-29 7:34 ` Lu Baolu 2021-09-29 7:34 ` Lu Baolu 2021-09-30 0:40 ` Fenghua Yu 2021-09-30 0:40 ` Fenghua Yu 2021-09-20 19:23 ` [PATCH 2/8] x86/process: Clear PASID state for a newly forked/cloned thread Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-20 19:23 ` [PATCH 3/8] sched: Define and initialize a flag to identify valid PASID in the task Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-20 19:23 ` [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-22 21:07 ` Peter Zijlstra 2021-09-22 21:07 ` Peter Zijlstra 2021-09-22 21:11 ` Peter Zijlstra 2021-09-22 21:11 ` Peter Zijlstra 2021-09-22 21:26 ` Luck, Tony 2021-09-22 21:26 ` Luck, Tony 2021-09-23 7:03 ` Peter Zijlstra 2021-09-23 7:03 ` Peter Zijlstra 2021-09-22 21:33 ` Dave Hansen 2021-09-22 21:33 ` Dave Hansen 2021-09-23 7:05 ` Peter Zijlstra [this message] 2021-09-23 7:05 ` Peter Zijlstra 2021-09-22 21:36 ` Fenghua Yu 2021-09-22 21:36 ` Fenghua Yu 2021-09-22 23:39 ` Fenghua Yu 2021-09-22 23:39 ` Fenghua Yu 2021-09-23 17:14 ` Luck, Tony 2021-09-23 17:14 ` Luck, Tony 2021-09-24 13:37 ` Peter Zijlstra 2021-09-24 13:37 ` Peter Zijlstra 2021-09-24 15:39 ` Luck, Tony 2021-09-24 15:39 ` Luck, Tony 2021-09-29 9:00 ` Peter Zijlstra 2021-09-29 9:00 ` Peter Zijlstra 2021-09-23 11:31 ` Thomas Gleixner 2021-09-23 11:31 ` Thomas Gleixner 2021-09-23 23:17 ` Andy Lutomirski 2021-09-23 23:17 ` Andy Lutomirski 2021-09-24 2:56 ` Fenghua Yu 2021-09-24 2:56 ` Fenghua Yu 2021-09-24 5:12 ` Andy Lutomirski 2021-09-24 5:12 ` Andy Lutomirski 2021-09-27 21:02 ` Luck, Tony 2021-09-27 21:02 ` Luck, Tony 2021-09-27 23:51 ` Dave Hansen 2021-09-27 23:51 ` Dave Hansen 2021-09-28 18:50 ` Luck, Tony 2021-09-28 18:50 ` Luck, Tony 2021-09-28 19:19 ` Dave Hansen 2021-09-28 19:19 ` Dave Hansen 2021-09-28 20:28 ` Luck, Tony 2021-09-28 20:28 ` Luck, Tony 2021-09-28 20:55 ` Dave Hansen 2021-09-28 20:55 ` Dave Hansen 2021-09-28 23:10 ` Luck, Tony 2021-09-28 23:10 ` Luck, Tony 2021-09-28 23:50 ` Fenghua Yu 2021-09-28 23:50 ` Fenghua Yu 2021-09-29 0:08 ` Luck, Tony 2021-09-29 0:08 ` Luck, Tony 2021-09-29 0:26 ` Yu, Fenghua 2021-09-29 0:26 ` Yu, Fenghua 2021-09-29 1:06 ` Luck, Tony 2021-09-29 1:06 ` Luck, Tony 2021-09-29 1:16 ` Fenghua Yu 2021-09-29 1:16 ` Fenghua Yu 2021-09-29 2:11 ` Luck, Tony 2021-09-29 2:11 ` Luck, Tony 2021-09-29 1:56 ` Yu, Fenghua 2021-09-29 1:56 ` Yu, Fenghua 2021-09-29 2:15 ` Luck, Tony 2021-09-29 2:15 ` Luck, Tony 2021-09-29 16:58 ` Andy Lutomirski 2021-09-29 16:58 ` Andy Lutomirski 2021-09-29 17:07 ` Luck, Tony 2021-09-29 17:07 ` Luck, Tony 2021-09-29 17:48 ` Andy Lutomirski 2021-09-29 17:48 ` Andy Lutomirski 2021-09-20 19:23 ` [PATCH 5/8] x86/mmu: Add mm-based PASID refcounting Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-23 5:43 ` Lu Baolu 2021-09-23 5:43 ` Lu Baolu 2021-09-30 0:44 ` Fenghua Yu 2021-09-30 0:44 ` Fenghua Yu 2021-09-23 14:36 ` Thomas Gleixner 2021-09-23 14:36 ` Thomas Gleixner 2021-09-23 16:40 ` Luck, Tony 2021-09-23 16:40 ` Luck, Tony 2021-09-23 17:48 ` Thomas Gleixner 2021-09-23 17:48 ` Thomas Gleixner 2021-09-24 13:18 ` Thomas Gleixner 2021-09-24 13:18 ` Thomas Gleixner 2021-09-24 16:12 ` Luck, Tony 2021-09-24 16:12 ` Luck, Tony 2021-09-24 23:03 ` Andy Lutomirski 2021-09-24 23:03 ` Andy Lutomirski 2021-09-24 23:11 ` Luck, Tony 2021-09-24 23:11 ` Luck, Tony 2021-09-29 9:54 ` Peter Zijlstra 2021-09-29 9:54 ` Peter Zijlstra 2021-09-29 12:28 ` Thomas Gleixner 2021-09-29 12:28 ` Thomas Gleixner 2021-09-29 16:51 ` Luck, Tony 2021-09-29 16:51 ` Luck, Tony 2021-09-29 17:07 ` Fenghua Yu 2021-09-29 17:07 ` Fenghua Yu 2021-09-29 16:59 ` Andy Lutomirski 2021-09-29 16:59 ` Andy Lutomirski 2021-09-29 17:15 ` Thomas Gleixner 2021-09-29 17:15 ` Thomas Gleixner 2021-09-29 17:41 ` Luck, Tony 2021-09-29 17:41 ` Luck, Tony 2021-09-29 17:46 ` Andy Lutomirski 2021-09-29 17:46 ` Andy Lutomirski 2021-09-29 18:07 ` Fenghua Yu 2021-09-29 18:07 ` Fenghua Yu 2021-09-29 18:31 ` Luck, Tony 2021-09-29 18:31 ` Luck, Tony 2021-09-29 20:07 ` Thomas Gleixner 2021-09-29 20:07 ` Thomas Gleixner 2021-09-24 16:12 ` Fenghua Yu 2021-09-24 16:12 ` Fenghua Yu 2021-09-25 23:13 ` Thomas Gleixner 2021-09-25 23:13 ` Thomas Gleixner 2021-09-28 16:36 ` Fenghua Yu 2021-09-28 16:36 ` Fenghua Yu 2021-09-23 23:09 ` Andy Lutomirski 2021-09-23 23:09 ` Andy Lutomirski 2021-09-23 23:22 ` Luck, Tony 2021-09-23 23:22 ` Luck, Tony 2021-09-24 5:17 ` Andy Lutomirski 2021-09-24 5:17 ` Andy Lutomirski 2021-09-20 19:23 ` [PATCH 6/8] x86/cpufeatures: Re-enable ENQCMD Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-20 19:23 ` [PATCH 7/8] tools/objtool: Check for use of the ENQCMD instruction in the kernel Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu 2021-09-22 21:03 ` Peter Zijlstra 2021-09-22 21:03 ` Peter Zijlstra 2021-09-22 23:44 ` Fenghua Yu 2021-09-22 23:44 ` Fenghua Yu 2021-09-23 7:17 ` Peter Zijlstra 2021-09-23 7:17 ` Peter Zijlstra 2021-09-23 15:26 ` Fenghua Yu 2021-09-23 15:26 ` Fenghua Yu 2021-09-24 0:55 ` Josh Poimboeuf 2021-09-24 0:55 ` Josh Poimboeuf 2021-09-24 0:57 ` Fenghua Yu 2021-09-24 0:57 ` Fenghua Yu 2021-09-20 19:23 ` [PATCH 8/8] docs: x86: Change documentation for SVA (Shared Virtual Addressing) Fenghua Yu 2021-09-20 19:23 ` Fenghua Yu
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