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From: "Luck, Tony" <tony.luck@intel.com>
To: Andy Lutomirski <luto@kernel.org>
Cc: Fenghua Yu <fenghua.yu@intel.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	"Peter Zijlstra (Intel)" <peterz@infradead.org>,
	Dave Hansen <dave.hansen@intel.com>,
	Lu Baolu <baolu.lu@linux.intel.com>,
	Joerg Roedel <joro@8bytes.org>,
	Josh Poimboeuf <jpoimboe@redhat.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Jacob Jun Pan <jacob.jun.pan@intel.com>,
	Raj Ashok <ashok.raj@intel.com>,
	"Shankar, Ravi V" <ravi.v.shankar@intel.com>,
	iommu@lists.linux-foundation.org,
	the arch/x86 maintainers <x86@kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP
Date: Mon, 27 Sep 2021 14:02:48 -0700	[thread overview]
Message-ID: <YVIxeBh3IKYYK711@agluck-desk2.amr.corp.intel.com> (raw)
In-Reply-To: <1aae375d-3cd4-4ab8-9c64-9e387916e6c0@www.fastmail.com>

On Thu, Sep 23, 2021 at 04:17:05PM -0700, Andy Lutomirski wrote:
> > +	fpregs_lock();
> > +
> > +	/*
> > +	 * If the task's FPU doesn't need to be loaded or is valid, directly
> > +	 * write the IA32_PASID MSR. Otherwise, write the PASID state and
> > +	 * the MSR will be loaded from the PASID state before returning to
> > +	 * the user.
> > +	 */
> > +	if (!test_thread_flag(TIF_NEED_FPU_LOAD) ||
> > +	    fpregs_state_valid(fpu, smp_processor_id())) {
> > +		wrmsrl(MSR_IA32_PASID, msr_val);
> 
> Let me try to decode this.
> 
> If the current task's FPU state is live or if the state is in memory but the CPU regs just happen to match the copy in memory, then write the MSR.  Else write the value to memory.
> 
> This is wrong.  If !TIF_NEED_FPU_LOAD && fpregs_state_valid, you MUST NOT MODIFY FPU STATE.  This is not negotiable -- you will break coherence between CPU regs and the memory image.  The way you modify the current task's state is either you modify it in CPU regs (if the kernel knows that the CPU regs are the one and only source of truth) OR you modify it in memory and invalidate any preserved copies (by zapping last_cpu). 
> 
> In any event, that particular bit of logic really doesn't belong in here -- it belongs in some helper that gets it right, once.

Andy,

A helper sounds like a good idea. Can you flesh out what
you would like that to look like?

Is it just the "where is the live register state?" so the
above could be written:

	if (xsave_state_in_memory(args ...))
		update pasid bit of xsave state in memory
	else
		wrmsrl(MSR_IA32_PASID, msr_val);

Or are you thinking of a helper that does both the check
and the update ... so the code here could be:

	update_one_xsave_feature(XFEATURE_PASID, &msr_val, sizeof(msr_val));

With the helper being something like:

void update_one_xsave_feature(enum xfeature xfeature, void *data, size_t size)
{
	if (xsave_state_in_memory(args ...)) {
		addr = get_xsave_addr(xsave, xfeature);
		memcpy(addr, data, size);
		xsave->header.xfeatures |= (1 << xfeature);
		return;
	}

	switch (xfeature) {
	case XFEATURE_PASID:
		wrmsrl(MSR_IA32_PASID, *(u64 *)data);
		break;

	case each_of_the_other_XFEATURE_enums:
		code to update registers for that XFEATURE
	}
}

either way needs the definitive correct coding for xsave_state_in_memory()

-Tony

WARNING: multiple messages have this Message-ID (diff)
From: "Luck, Tony" <tony.luck@intel.com>
To: Andy Lutomirski <luto@kernel.org>
Cc: Fenghua Yu <fenghua.yu@intel.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Raj Ashok <ashok.raj@intel.com>,
	"Shankar, Ravi V" <ravi.v.shankar@intel.com>,
	"Peter Zijlstra \(Intel\)" <peterz@infradead.org>,
	the arch/x86 maintainers <x86@kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Dave Hansen <dave.hansen@intel.com>,
	iommu@lists.linux-foundation.org, Ingo Molnar <mingo@redhat.com>,
	Borislav Petkov <bp@alien8.de>,
	Jacob Jun Pan <jacob.jun.pan@intel.com>,
	Josh Poimboeuf <jpoimboe@redhat.com>,
	Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP
Date: Mon, 27 Sep 2021 14:02:48 -0700	[thread overview]
Message-ID: <YVIxeBh3IKYYK711@agluck-desk2.amr.corp.intel.com> (raw)
In-Reply-To: <1aae375d-3cd4-4ab8-9c64-9e387916e6c0@www.fastmail.com>

On Thu, Sep 23, 2021 at 04:17:05PM -0700, Andy Lutomirski wrote:
> > +	fpregs_lock();
> > +
> > +	/*
> > +	 * If the task's FPU doesn't need to be loaded or is valid, directly
> > +	 * write the IA32_PASID MSR. Otherwise, write the PASID state and
> > +	 * the MSR will be loaded from the PASID state before returning to
> > +	 * the user.
> > +	 */
> > +	if (!test_thread_flag(TIF_NEED_FPU_LOAD) ||
> > +	    fpregs_state_valid(fpu, smp_processor_id())) {
> > +		wrmsrl(MSR_IA32_PASID, msr_val);
> 
> Let me try to decode this.
> 
> If the current task's FPU state is live or if the state is in memory but the CPU regs just happen to match the copy in memory, then write the MSR.  Else write the value to memory.
> 
> This is wrong.  If !TIF_NEED_FPU_LOAD && fpregs_state_valid, you MUST NOT MODIFY FPU STATE.  This is not negotiable -- you will break coherence between CPU regs and the memory image.  The way you modify the current task's state is either you modify it in CPU regs (if the kernel knows that the CPU regs are the one and only source of truth) OR you modify it in memory and invalidate any preserved copies (by zapping last_cpu). 
> 
> In any event, that particular bit of logic really doesn't belong in here -- it belongs in some helper that gets it right, once.

Andy,

A helper sounds like a good idea. Can you flesh out what
you would like that to look like?

Is it just the "where is the live register state?" so the
above could be written:

	if (xsave_state_in_memory(args ...))
		update pasid bit of xsave state in memory
	else
		wrmsrl(MSR_IA32_PASID, msr_val);

Or are you thinking of a helper that does both the check
and the update ... so the code here could be:

	update_one_xsave_feature(XFEATURE_PASID, &msr_val, sizeof(msr_val));

With the helper being something like:

void update_one_xsave_feature(enum xfeature xfeature, void *data, size_t size)
{
	if (xsave_state_in_memory(args ...)) {
		addr = get_xsave_addr(xsave, xfeature);
		memcpy(addr, data, size);
		xsave->header.xfeatures |= (1 << xfeature);
		return;
	}

	switch (xfeature) {
	case XFEATURE_PASID:
		wrmsrl(MSR_IA32_PASID, *(u64 *)data);
		break;

	case each_of_the_other_XFEATURE_enums:
		code to update registers for that XFEATURE
	}
}

either way needs the definitive correct coding for xsave_state_in_memory()

-Tony
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

  parent reply	other threads:[~2021-09-27 21:02 UTC|newest]

Thread overview: 154+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-20 19:23 [PATCH 0/8] Re-enable ENQCMD and PASID MSR Fenghua Yu
2021-09-20 19:23 ` Fenghua Yu
2021-09-20 19:23 ` [PATCH 1/8] iommu/vt-d: Clean up unused PASID updating functions Fenghua Yu
2021-09-20 19:23   ` Fenghua Yu
2021-09-29  7:34   ` Lu Baolu
2021-09-29  7:34     ` Lu Baolu
2021-09-30  0:40     ` Fenghua Yu
2021-09-30  0:40       ` Fenghua Yu
2021-09-20 19:23 ` [PATCH 2/8] x86/process: Clear PASID state for a newly forked/cloned thread Fenghua Yu
2021-09-20 19:23   ` Fenghua Yu
2021-09-20 19:23 ` [PATCH 3/8] sched: Define and initialize a flag to identify valid PASID in the task Fenghua Yu
2021-09-20 19:23   ` Fenghua Yu
2021-09-20 19:23 ` [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Fenghua Yu
2021-09-20 19:23   ` Fenghua Yu
2021-09-22 21:07   ` Peter Zijlstra
2021-09-22 21:07     ` Peter Zijlstra
2021-09-22 21:11     ` Peter Zijlstra
2021-09-22 21:11       ` Peter Zijlstra
2021-09-22 21:26       ` Luck, Tony
2021-09-22 21:26         ` Luck, Tony
2021-09-23  7:03         ` Peter Zijlstra
2021-09-23  7:03           ` Peter Zijlstra
2021-09-22 21:33       ` Dave Hansen
2021-09-22 21:33         ` Dave Hansen
2021-09-23  7:05         ` Peter Zijlstra
2021-09-23  7:05           ` Peter Zijlstra
2021-09-22 21:36       ` Fenghua Yu
2021-09-22 21:36         ` Fenghua Yu
2021-09-22 23:39     ` Fenghua Yu
2021-09-22 23:39       ` Fenghua Yu
2021-09-23 17:14     ` Luck, Tony
2021-09-23 17:14       ` Luck, Tony
2021-09-24 13:37       ` Peter Zijlstra
2021-09-24 13:37         ` Peter Zijlstra
2021-09-24 15:39         ` Luck, Tony
2021-09-24 15:39           ` Luck, Tony
2021-09-29  9:00           ` Peter Zijlstra
2021-09-29  9:00             ` Peter Zijlstra
2021-09-23 11:31   ` Thomas Gleixner
2021-09-23 11:31     ` Thomas Gleixner
2021-09-23 23:17   ` Andy Lutomirski
2021-09-23 23:17     ` Andy Lutomirski
2021-09-24  2:56     ` Fenghua Yu
2021-09-24  2:56       ` Fenghua Yu
2021-09-24  5:12       ` Andy Lutomirski
2021-09-24  5:12         ` Andy Lutomirski
2021-09-27 21:02     ` Luck, Tony [this message]
2021-09-27 21:02       ` Luck, Tony
2021-09-27 23:51       ` Dave Hansen
2021-09-27 23:51         ` Dave Hansen
2021-09-28 18:50         ` Luck, Tony
2021-09-28 18:50           ` Luck, Tony
2021-09-28 19:19           ` Dave Hansen
2021-09-28 19:19             ` Dave Hansen
2021-09-28 20:28             ` Luck, Tony
2021-09-28 20:28               ` Luck, Tony
2021-09-28 20:55               ` Dave Hansen
2021-09-28 20:55                 ` Dave Hansen
2021-09-28 23:10                 ` Luck, Tony
2021-09-28 23:10                   ` Luck, Tony
2021-09-28 23:50                   ` Fenghua Yu
2021-09-28 23:50                     ` Fenghua Yu
2021-09-29  0:08                     ` Luck, Tony
2021-09-29  0:08                       ` Luck, Tony
2021-09-29  0:26                       ` Yu, Fenghua
2021-09-29  0:26                         ` Yu, Fenghua
2021-09-29  1:06                         ` Luck, Tony
2021-09-29  1:06                           ` Luck, Tony
2021-09-29  1:16                           ` Fenghua Yu
2021-09-29  1:16                             ` Fenghua Yu
2021-09-29  2:11                             ` Luck, Tony
2021-09-29  2:11                               ` Luck, Tony
2021-09-29  1:56                       ` Yu, Fenghua
2021-09-29  1:56                         ` Yu, Fenghua
2021-09-29  2:15                         ` Luck, Tony
2021-09-29  2:15                           ` Luck, Tony
2021-09-29 16:58                   ` Andy Lutomirski
2021-09-29 16:58                     ` Andy Lutomirski
2021-09-29 17:07                     ` Luck, Tony
2021-09-29 17:07                       ` Luck, Tony
2021-09-29 17:48                       ` Andy Lutomirski
2021-09-29 17:48                         ` Andy Lutomirski
2021-09-20 19:23 ` [PATCH 5/8] x86/mmu: Add mm-based PASID refcounting Fenghua Yu
2021-09-20 19:23   ` Fenghua Yu
2021-09-23  5:43   ` Lu Baolu
2021-09-23  5:43     ` Lu Baolu
2021-09-30  0:44     ` Fenghua Yu
2021-09-30  0:44       ` Fenghua Yu
2021-09-23 14:36   ` Thomas Gleixner
2021-09-23 14:36     ` Thomas Gleixner
2021-09-23 16:40     ` Luck, Tony
2021-09-23 16:40       ` Luck, Tony
2021-09-23 17:48       ` Thomas Gleixner
2021-09-23 17:48         ` Thomas Gleixner
2021-09-24 13:18         ` Thomas Gleixner
2021-09-24 13:18           ` Thomas Gleixner
2021-09-24 16:12           ` Luck, Tony
2021-09-24 16:12             ` Luck, Tony
2021-09-24 23:03             ` Andy Lutomirski
2021-09-24 23:03               ` Andy Lutomirski
2021-09-24 23:11               ` Luck, Tony
2021-09-24 23:11                 ` Luck, Tony
2021-09-29  9:54               ` Peter Zijlstra
2021-09-29  9:54                 ` Peter Zijlstra
2021-09-29 12:28                 ` Thomas Gleixner
2021-09-29 12:28                   ` Thomas Gleixner
2021-09-29 16:51                   ` Luck, Tony
2021-09-29 16:51                     ` Luck, Tony
2021-09-29 17:07                     ` Fenghua Yu
2021-09-29 17:07                       ` Fenghua Yu
2021-09-29 16:59                   ` Andy Lutomirski
2021-09-29 16:59                     ` Andy Lutomirski
2021-09-29 17:15                     ` Thomas Gleixner
2021-09-29 17:15                       ` Thomas Gleixner
2021-09-29 17:41                       ` Luck, Tony
2021-09-29 17:41                         ` Luck, Tony
2021-09-29 17:46                         ` Andy Lutomirski
2021-09-29 17:46                           ` Andy Lutomirski
2021-09-29 18:07                         ` Fenghua Yu
2021-09-29 18:07                           ` Fenghua Yu
2021-09-29 18:31                           ` Luck, Tony
2021-09-29 18:31                             ` Luck, Tony
2021-09-29 20:07                             ` Thomas Gleixner
2021-09-29 20:07                               ` Thomas Gleixner
2021-09-24 16:12           ` Fenghua Yu
2021-09-24 16:12             ` Fenghua Yu
2021-09-25 23:13             ` Thomas Gleixner
2021-09-25 23:13               ` Thomas Gleixner
2021-09-28 16:36               ` Fenghua Yu
2021-09-28 16:36                 ` Fenghua Yu
2021-09-23 23:09   ` Andy Lutomirski
2021-09-23 23:09     ` Andy Lutomirski
2021-09-23 23:22     ` Luck, Tony
2021-09-23 23:22       ` Luck, Tony
2021-09-24  5:17       ` Andy Lutomirski
2021-09-24  5:17         ` Andy Lutomirski
2021-09-20 19:23 ` [PATCH 6/8] x86/cpufeatures: Re-enable ENQCMD Fenghua Yu
2021-09-20 19:23   ` Fenghua Yu
2021-09-20 19:23 ` [PATCH 7/8] tools/objtool: Check for use of the ENQCMD instruction in the kernel Fenghua Yu
2021-09-20 19:23   ` Fenghua Yu
2021-09-22 21:03   ` Peter Zijlstra
2021-09-22 21:03     ` Peter Zijlstra
2021-09-22 23:44     ` Fenghua Yu
2021-09-22 23:44       ` Fenghua Yu
2021-09-23  7:17       ` Peter Zijlstra
2021-09-23  7:17         ` Peter Zijlstra
2021-09-23 15:26         ` Fenghua Yu
2021-09-23 15:26           ` Fenghua Yu
2021-09-24  0:55           ` Josh Poimboeuf
2021-09-24  0:55             ` Josh Poimboeuf
2021-09-24  0:57             ` Fenghua Yu
2021-09-24  0:57               ` Fenghua Yu
2021-09-20 19:23 ` [PATCH 8/8] docs: x86: Change documentation for SVA (Shared Virtual Addressing) Fenghua Yu
2021-09-20 19:23   ` Fenghua Yu

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