* [PATCH 1/8] drm/amdgpu:Use register UVD_SCRATCH9 for VCN ring/ib test
@ 2018-09-25 19:55 James Zhu
[not found] ` <1537905323-27071-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 15+ messages in thread
From: James Zhu @ 2018-09-25 19:55 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo
Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers
can't be directly accessed under DPG(Dynamic Power Gate) mode.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index a73674f..27262a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -264,7 +264,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 3);
if (r) {
DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
@@ -272,11 +272,11 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
return r;
}
amdgpu_ring_write(ring,
- PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0));
amdgpu_ring_write(ring, 0xDEADBEEF);
amdgpu_ring_commit(ring);
for (i = 0; i < adev->usec_timeout; i++) {
- tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
+ tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
if (tmp == 0xDEADBEEF)
break;
DRM_UDELAY(1);
@@ -616,7 +616,7 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 3);
if (r) {
@@ -626,12 +626,12 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
}
amdgpu_ring_write(ring,
- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0, 0, 0));
+ PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, 0));
amdgpu_ring_write(ring, 0xDEADBEEF);
amdgpu_ring_commit(ring);
for (i = 0; i < adev->usec_timeout; i++) {
- tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
+ tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
if (tmp == 0xDEADBEEF)
break;
DRM_UDELAY(1);
@@ -665,7 +665,7 @@ static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
ib = &job->ibs[0];
- ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH), 0, 0, PACKETJ_TYPE0);
+ ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, PACKETJ_TYPE0);
ib->ptr[1] = 0xDEADBEEF;
for (i = 2; i < 16; i += 2) {
ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
@@ -714,7 +714,7 @@ int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = 0;
for (i = 0; i < adev->usec_timeout; i++) {
- tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH));
+ tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
if (tmp == 0xDEADBEEF)
break;
DRM_UDELAY(1);
--
2.7.4
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^ permalink raw reply related [flat|nested] 15+ messages in thread[parent not found: <1537905323-27071-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>]
* [PATCH 2/8] drm/amdgpu:Add new register offset/mask to support VCN DPG mode [not found] ` <1537905323-27071-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-09-25 19:55 ` James Zhu 2018-09-25 19:55 ` [PATCH 3/8] drm/amdgpu:Add DPG support flag James Zhu ` (5 subsequent siblings) 6 siblings, 0 replies; 15+ messages in thread From: James Zhu @ 2018-09-25 19:55 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo New register offset/mask need to be added to support VCN DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> --- .../drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 8 +++++++ .../drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 25 ++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h index 216a401..4b7da58 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h @@ -33,6 +33,14 @@ #define mmUVD_POWER_STATUS_BASE_IDX 1 #define mmCC_UVD_HARVESTING 0x00c7 #define mmCC_UVD_HARVESTING_BASE_IDX 1 +#define mmUVD_DPG_LMA_CTL 0x00d1 +#define mmUVD_DPG_LMA_CTL_BASE_IDX 1 +#define mmUVD_DPG_LMA_DATA 0x00d2 +#define mmUVD_DPG_LMA_DATA_BASE_IDX 1 +#define mmUVD_DPG_LMA_MASK 0x00d3 +#define mmUVD_DPG_LMA_MASK_BASE_IDX 1 +#define mmUVD_DPG_PAUSE 0x00d4 +#define mmUVD_DPG_PAUSE_BASE_IDX 1 #define mmUVD_SCRATCH1 0x00d5 #define mmUVD_SCRATCH1_BASE_IDX 1 #define mmUVD_SCRATCH2 0x00d6 diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h index 124383d..26382f5 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h @@ -87,6 +87,26 @@ //CC_UVD_HARVESTING #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L +//UVD_DPG_LMA_CTL +#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 +#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 +#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 +#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 +#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 +#define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L +#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L +#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L +#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L +#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L +//UVD_DPG_PAUSE +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L //UVD_SCRATCH1 #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL @@ -983,6 +1003,7 @@ #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L //UVD_SYS_INT_EN +#define UVD_SYS_INT_EN__UVD_JRBC_EN__SHIFT 0x4 #define UVD_SYS_INT_EN__UVD_JRBC_EN_MASK 0x00000010L //JPEG_CGC_CTRL #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 @@ -1138,7 +1159,11 @@ #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL //UVD_VCPU_CNTL #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 +#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L +#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L //UVD_SOFT_RESET #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/8] drm/amdgpu:Add DPG support flag [not found] ` <1537905323-27071-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-09-25 19:55 ` [PATCH 2/8] drm/amdgpu:Add new register offset/mask to support VCN DPG mode James Zhu @ 2018-09-25 19:55 ` James Zhu [not found] ` <1537905323-27071-3-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-09-25 19:55 ` [PATCH 4/8] drm/amdgpu:Add DPG mode read/write macro James Zhu ` (4 subsequent siblings) 6 siblings, 1 reply; 15+ messages in thread From: James Zhu @ 2018-09-25 19:55 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo Add DPG support flag for VCN DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> --- drivers/gpu/drm/amd/include/amd_shared.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 86b167e..2f6bdf1 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -110,6 +110,8 @@ enum amd_powergating_state { #define AMD_PG_SUPPORT_MMHUB (1 << 13) #define AMD_PG_SUPPORT_VCN (1 << 14) +#define AMD_PG_SUPPORT_DPG (1 << 15) + enum PP_FEATURE_MASK { PP_SCLK_DPM_MASK = 0x1, PP_MCLK_DPM_MASK = 0x2, -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
[parent not found: <1537905323-27071-3-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 3/8] drm/amdgpu:Add DPG support flag [not found] ` <1537905323-27071-3-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-09-25 20:06 ` Alex Deucher 2018-09-26 8:02 ` Christian König 1 sibling, 0 replies; 15+ messages in thread From: Alex Deucher @ 2018-09-25 20:06 UTC (permalink / raw) To: James Zhu; +Cc: James Zhu, amd-gfx list On Tue, Sep 25, 2018 at 4:04 PM James Zhu <jzhums@gmail.com> wrote: > > Add DPG support flag for VCN DPG mode. > > Signed-off-by: James Zhu <James.Zhu@amd.com> > --- > drivers/gpu/drm/amd/include/amd_shared.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h > index 86b167e..2f6bdf1 100644 > --- a/drivers/gpu/drm/amd/include/amd_shared.h > +++ b/drivers/gpu/drm/amd/include/amd_shared.h > @@ -110,6 +110,8 @@ enum amd_powergating_state { > #define AMD_PG_SUPPORT_MMHUB (1 << 13) > #define AMD_PG_SUPPORT_VCN (1 << 14) > > +#define AMD_PG_SUPPORT_DPG (1 << 15) Please drop the new line before this define. Also, rename it VCN_DPG so it's clear it's a VCN feature. Alex > + > enum PP_FEATURE_MASK { > PP_SCLK_DPM_MASK = 0x1, > PP_MCLK_DPM_MASK = 0x2, > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/8] drm/amdgpu:Add DPG support flag [not found] ` <1537905323-27071-3-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-09-25 20:06 ` Alex Deucher @ 2018-09-26 8:02 ` Christian König [not found] ` <44a25354-4329-c942-8f86-0528a0b2ce84-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 1 sibling, 1 reply; 15+ messages in thread From: Christian König @ 2018-09-26 8:02 UTC (permalink / raw) To: James Zhu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo Am 25.09.2018 um 21:55 schrieb James Zhu: > Add DPG support flag for VCN DPG mode. > > Signed-off-by: James Zhu <James.Zhu@amd.com> > --- > drivers/gpu/drm/amd/include/amd_shared.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h > index 86b167e..2f6bdf1 100644 > --- a/drivers/gpu/drm/amd/include/amd_shared.h > +++ b/drivers/gpu/drm/amd/include/amd_shared.h > @@ -110,6 +110,8 @@ enum amd_powergating_state { > #define AMD_PG_SUPPORT_MMHUB (1 << 13) > #define AMD_PG_SUPPORT_VCN (1 << 14) > Looks like you added an extra empty line between AMD_PG_SUPPORT_VCN and the new entry, was that intentional? Apart from that the patches look good to me, but can't judge if that is really correct. Acked-by: Christian König <christian.koenig@amd.com> for the series. Regards, Christian. > +#define AMD_PG_SUPPORT_DPG (1 << 15) > + > enum PP_FEATURE_MASK { > PP_SCLK_DPM_MASK = 0x1, > PP_MCLK_DPM_MASK = 0x2, _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
[parent not found: <44a25354-4329-c942-8f86-0528a0b2ce84-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 3/8] drm/amdgpu:Add DPG support flag [not found] ` <44a25354-4329-c942-8f86-0528a0b2ce84-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2018-09-26 12:55 ` James Zhu 0 siblings, 0 replies; 15+ messages in thread From: James Zhu @ 2018-09-26 12:55 UTC (permalink / raw) To: christian.koenig-5C7GfCeVMHo, James Zhu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: james.zhu-5C7GfCeVMHo On 2018-09-26 04:02 AM, Christian König wrote: > Am 25.09.2018 um 21:55 schrieb James Zhu: >> Add DPG support flag for VCN DPG mode. >> >> Signed-off-by: James Zhu <James.Zhu@amd.com> >> --- >> drivers/gpu/drm/amd/include/amd_shared.h | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h >> b/drivers/gpu/drm/amd/include/amd_shared.h >> index 86b167e..2f6bdf1 100644 >> --- a/drivers/gpu/drm/amd/include/amd_shared.h >> +++ b/drivers/gpu/drm/amd/include/amd_shared.h >> @@ -110,6 +110,8 @@ enum amd_powergating_state { >> #define AMD_PG_SUPPORT_MMHUB (1 << 13) >> #define AMD_PG_SUPPORT_VCN (1 << 14) > > Looks like you added an extra empty line between AMD_PG_SUPPORT_VCN > and the new entry, was that intentional? Already fixed with Alex's comments. James > > Apart from that the patches look good to me, but can't judge if that > is really correct. > > Acked-by: Christian König <christian.koenig@amd.com> for the series. > > Regards, > Christian. > >> +#define AMD_PG_SUPPORT_DPG (1 << 15) >> + >> enum PP_FEATURE_MASK { >> PP_SCLK_DPM_MASK = 0x1, >> PP_MCLK_DPM_MASK = 0x2, > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 4/8] drm/amdgpu:Add DPG mode read/write macro [not found] ` <1537905323-27071-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-09-25 19:55 ` [PATCH 2/8] drm/amdgpu:Add new register offset/mask to support VCN DPG mode James Zhu 2018-09-25 19:55 ` [PATCH 3/8] drm/amdgpu:Add DPG support flag James Zhu @ 2018-09-25 19:55 ` James Zhu 2018-09-25 19:55 ` [PATCH 5/8] drm/amdgpu:Add DPG mode support for vcn 1.0 James Zhu ` (3 subsequent siblings) 6 siblings, 0 replies; 15+ messages in thread From: James Zhu @ 2018-09-25 19:55 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo Some registers read/write needs program through SDRAM pool under DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> --- drivers/gpu/drm/amd/amdgpu/soc15_common.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index f5d6025..d35fac5 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -64,6 +64,26 @@ } \ } while (0) +#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \ + ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ + WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \ + UVD_DPG_LMA_CTL__MASK_EN_MASK | \ + ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ + << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ + (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ + RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); }) + +#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \ + do { \ + WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \ + WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ + WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \ + UVD_DPG_LMA_CTL__READ_WRITE_MASK | \ + ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ + << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ + (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ + } while (0) + #endif -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 5/8] drm/amdgpu:Add DPG mode support for vcn 1.0 [not found] ` <1537905323-27071-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> ` (2 preceding siblings ...) 2018-09-25 19:55 ` [PATCH 4/8] drm/amdgpu:Add DPG mode read/write macro James Zhu @ 2018-09-25 19:55 ` James Zhu [not found] ` <1537905323-27071-5-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-09-25 19:55 ` [PATCH 6/8] drm/amdgpu:Add DPG pause state James Zhu ` (2 subsequent siblings) 6 siblings, 1 reply; 15+ messages in thread From: James Zhu @ 2018-09-25 19:55 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo Add DPG mode start/stop/mc_resume/clock_gating to support vcn 1.0 DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 319 +++++++++++++++++++++++++++++++++- 1 file changed, 313 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 2cde0b4..19bd40c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -198,7 +198,8 @@ static int vcn_v1_0_hw_init(void *handle) done: if (!r) - DRM_INFO("VCN decode and encode initialized successfully.\n"); + DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", + (adev->pg_flags & AMD_PG_SUPPORT_DPG)?"DPG Mode":"SPG Mode"); return r; } @@ -266,13 +267,13 @@ static int vcn_v1_0_resume(void *handle) } /** - * vcn_v1_0_mc_resume - memory controller programming + * vcn_v1_0_mc_resume_pg_mode - memory controller programming * * @adev: amdgpu_device pointer * * Let the VCN memory controller know it's offsets */ -static void vcn_v1_0_mc_resume(struct amdgpu_device *adev) +static void vcn_v1_0_mc_resume_pg_mode(struct amdgpu_device *adev) { uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); uint32_t offset; @@ -319,6 +320,65 @@ static void vcn_v1_0_mc_resume(struct amdgpu_device *adev) adev->gfx.config.gb_addr_config); } +static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) +{ + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); + uint32_t offset; + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), + 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), + 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, + 0xFFFFFFFF, 0); + offset = 0; + } else { + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0); + offset = size; + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, + AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); + } + + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); + + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, + 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE, + 0xFFFFFFFF, 0); + + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE), + 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE), + 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, + AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40), + 0xFFFFFFFF, 0); + + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); +} + /** * vcn_v1_0_disable_clock_gating - disable VCN clock gating * @@ -519,6 +579,62 @@ static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); } +static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) +{ + uint32_t reg_data = 0; + + /* disable JPEG CGC */ + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) + reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + else + reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; + reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; + WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); + + WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); + + /* enable sw clock gating control */ + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) + reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + else + reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; + reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); + + reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | + UVD_CGC_CTRL__UDEC_CM_MODE_MASK | + UVD_CGC_CTRL__UDEC_IT_MODE_MASK | + UVD_CGC_CTRL__UDEC_DB_MODE_MASK | + UVD_CGC_CTRL__UDEC_MP_MODE_MASK | + UVD_CGC_CTRL__SYS_MODE_MASK | + UVD_CGC_CTRL__UDEC_MODE_MASK | + UVD_CGC_CTRL__MPEG2_MODE_MASK | + UVD_CGC_CTRL__REGS_MODE_MASK | + UVD_CGC_CTRL__RBC_MODE_MASK | + UVD_CGC_CTRL__LMI_MC_MODE_MASK | + UVD_CGC_CTRL__LMI_UMC_MODE_MASK | + UVD_CGC_CTRL__IDCT_MODE_MASK | + UVD_CGC_CTRL__MPRD_MODE_MASK | + UVD_CGC_CTRL__MPC_MODE_MASK | + UVD_CGC_CTRL__LBSI_MODE_MASK | + UVD_CGC_CTRL__LRBBM_MODE_MASK | + UVD_CGC_CTRL__WCB_MODE_MASK | + UVD_CGC_CTRL__VCPU_MODE_MASK | + UVD_CGC_CTRL__SCPU_MODE_MASK); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); + + /* turn off clock gating */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); + + /* turn on SUVD clock gating */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); + + /* turn on sw mode in UVD_SUVD_CGC_CTRL */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); +} + static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) { uint32_t data = 0; @@ -614,7 +730,7 @@ static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) * * Setup and start the VCN block */ -static int vcn_v1_0_start(struct amdgpu_device *adev) +static int vcn_v1_0_start_pg_mode(struct amdgpu_device *adev) { struct amdgpu_ring *ring = &adev->vcn.ring_dec; uint32_t rb_bufsz, tmp; @@ -628,7 +744,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) /* disable clock gating */ vcn_v1_0_disable_clock_gating(adev); - vcn_v1_0_mc_resume(adev); + vcn_v1_0_mc_resume_pg_mode(adev); /* disable interupt */ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, @@ -799,6 +915,170 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) return 0; } +static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->vcn.ring_dec; + uint32_t rb_bufsz, tmp, reg_data; + uint32_t lmi_swap_cntl; + + /* disable byte swapping */ + lmi_swap_cntl = 0; + + vcn_1_0_enable_static_power_gating(adev); + + /* enable dynamic power gating mode */ + reg_data = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); + reg_data |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; + reg_data |= UVD_POWER_STATUS__UVD_PG_EN_MASK; + WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data); + + /* enable clock gating */ + vcn_v1_0_clock_gating_dpg_mode(adev, 0); + + /* enable VCPU clock */ + reg_data = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); + reg_data |= UVD_VCPU_CNTL__CLK_EN_MASK; + reg_data |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, reg_data, 0xFFFFFFFF, 0); + + /* disable interupt */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, + 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); + + /* stall UMC and register bus before resetting VCPU */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, + UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); + + /* put LMI, VCPU, RBC etc... into reset */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, + UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | + UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | + UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | + UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | + UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | + UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | + UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, + 0xFFFFFFFF, 0); + + /* initialize VCN memory controller */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, + (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__REQ_MODE_MASK | + 0x00100000L, 0xFFFFFFFF, 0); + +#ifdef __BIG_ENDIAN + /* swap (8 in 32) RB and IB */ + lmi_swap_cntl = 0xa; +#endif + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); + + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040, 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0, 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040, 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0, 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_ALU, 0, 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 0x88, 0xFFFFFFFF, 0); + + vcn_v1_0_mc_resume_dpg_mode(adev); + + /* take all subblocks out of reset, except VCPU */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0xFFFFFFFF, 0); + + /* enable VCPU clock */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, + UVD_VCPU_CNTL__CLK_EN_MASK, 0xFFFFFFFF, 0); + + /* enable UMC */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, + 0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); + + /* boot up the VCPU */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); + + /* enable master interrupt */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, + (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), + (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 0); + + vcn_v1_0_clock_gating_dpg_mode(adev, 1); + /* setup mmUVD_LMI_CTRL */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, + (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | + UVD_LMI_CTRL__CRC_RESET_MASK | + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | + (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | + 0x00100000L), 0xFFFFFFFF, 1); + + tmp = adev->gfx.config.gb_addr_config; + /* setup VCN global tiling registers */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); + + /* enable System Interrupt for JRBC */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN, + UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); + + /* force RBC into idle state */ + rb_bufsz = order_base_2(ring->ring_size); + tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); + + /* set the write pointer delay */ + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); + + /* set the wb address */ + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, + (upper_32_bits(ring->gpu_addr) >> 2)); + + /* programm the RB_BASE for ring buffer */ + WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, + lower_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, + upper_32_bits(ring->gpu_addr)); + + /* Initialize the ring buffer's read and write pointers */ + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); + + ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, + lower_32_bits(ring->wptr)); + + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, + ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); + + /* initialize wptr */ + ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); + + /* copy patch commands to the jpeg ring */ + vcn_v1_0_jpeg_ring_set_patch_ring(ring, + (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission)); + + return 0; +} + +static int vcn_v1_0_start(struct amdgpu_device *adev) +{ + int r; + + if (adev->pg_flags & AMD_PG_SUPPORT_DPG) + r = vcn_v1_0_start_dpg_mode(adev); + else + r = vcn_v1_0_start_pg_mode(adev); + return r; +} + /** * vcn_v1_0_stop - stop VCN block * @@ -806,7 +1086,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) * * stop the VCN block */ -static int vcn_v1_0_stop(struct amdgpu_device *adev) +static int vcn_v1_0_stop_pg_mode(struct amdgpu_device *adev) { /* force RBC into idle state */ WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101); @@ -836,6 +1116,33 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev) return 0; } +static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) +{ + int ret_code; + + /* Wait for power status to be 1 */ + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); + + /* disable dynamic power gating mode */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, + ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); + + return 0; +} + +static int vcn_v1_0_stop(struct amdgpu_device *adev) +{ + int r; + + if (adev->pg_flags & AMD_PG_SUPPORT_DPG) + r = vcn_v1_0_stop_dpg_mode(adev); + else + r = vcn_v1_0_stop_pg_mode(adev); + + return r; +} + static bool vcn_v1_0_is_idle(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
[parent not found: <1537905323-27071-5-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 5/8] drm/amdgpu:Add DPG mode support for vcn 1.0 [not found] ` <1537905323-27071-5-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-09-25 20:09 ` Alex Deucher 0 siblings, 0 replies; 15+ messages in thread From: Alex Deucher @ 2018-09-25 20:09 UTC (permalink / raw) To: James Zhu; +Cc: James Zhu, amd-gfx list On Tue, Sep 25, 2018 at 4:04 PM James Zhu <jzhums@gmail.com> wrote: > > Add DPG mode start/stop/mc_resume/clock_gating to > support vcn 1.0 DPG mode. > > Signed-off-by: James Zhu <James.Zhu@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 319 +++++++++++++++++++++++++++++++++- > 1 file changed, 313 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > index 2cde0b4..19bd40c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > @@ -198,7 +198,8 @@ static int vcn_v1_0_hw_init(void *handle) > > done: > if (!r) > - DRM_INFO("VCN decode and encode initialized successfully.\n"); > + DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", > + (adev->pg_flags & AMD_PG_SUPPORT_DPG)?"DPG Mode":"SPG Mode"); > > return r; > } > @@ -266,13 +267,13 @@ static int vcn_v1_0_resume(void *handle) > } > > /** > - * vcn_v1_0_mc_resume - memory controller programming > + * vcn_v1_0_mc_resume_pg_mode - memory controller programming > * > * @adev: amdgpu_device pointer > * > * Let the VCN memory controller know it's offsets > */ > -static void vcn_v1_0_mc_resume(struct amdgpu_device *adev) > +static void vcn_v1_0_mc_resume_pg_mode(struct amdgpu_device *adev) Maybe call this vcn_v1_0_mc_resume_spg_mode for clarity? > { > uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); > uint32_t offset; > @@ -319,6 +320,65 @@ static void vcn_v1_0_mc_resume(struct amdgpu_device *adev) > adev->gfx.config.gb_addr_config); > } > > +static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) > +{ > + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); > + uint32_t offset; > + > + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, > + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), > + 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, > + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), > + 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, > + 0xFFFFFFFF, 0); > + offset = 0; > + } else { > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, > + lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, > + upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0); > + offset = size; > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, > + AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); > + } > + > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); > + > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, > + lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, > + upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, > + 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE, > + 0xFFFFFFFF, 0); > + > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, > + lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE), > + 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, > + upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE), > + 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, > + AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40), > + 0xFFFFFFFF, 0); > + > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, > + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, > + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, > + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, > + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, > + adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); > +} > + > /** > * vcn_v1_0_disable_clock_gating - disable VCN clock gating > * > @@ -519,6 +579,62 @@ static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) > WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); > } > > +static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) > +{ > + uint32_t reg_data = 0; > + > + /* disable JPEG CGC */ > + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) > + reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; > + else > + reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; > + reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; > + reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; > + WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); > + > + WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); > + > + /* enable sw clock gating control */ > + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) > + reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; > + else > + reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; > + reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; > + reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); > + > + reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | > + UVD_CGC_CTRL__UDEC_CM_MODE_MASK | > + UVD_CGC_CTRL__UDEC_IT_MODE_MASK | > + UVD_CGC_CTRL__UDEC_DB_MODE_MASK | > + UVD_CGC_CTRL__UDEC_MP_MODE_MASK | > + UVD_CGC_CTRL__SYS_MODE_MASK | > + UVD_CGC_CTRL__UDEC_MODE_MASK | > + UVD_CGC_CTRL__MPEG2_MODE_MASK | > + UVD_CGC_CTRL__REGS_MODE_MASK | > + UVD_CGC_CTRL__RBC_MODE_MASK | > + UVD_CGC_CTRL__LMI_MC_MODE_MASK | > + UVD_CGC_CTRL__LMI_UMC_MODE_MASK | > + UVD_CGC_CTRL__IDCT_MODE_MASK | > + UVD_CGC_CTRL__MPRD_MODE_MASK | > + UVD_CGC_CTRL__MPC_MODE_MASK | > + UVD_CGC_CTRL__LBSI_MODE_MASK | > + UVD_CGC_CTRL__LRBBM_MODE_MASK | > + UVD_CGC_CTRL__WCB_MODE_MASK | > + UVD_CGC_CTRL__VCPU_MODE_MASK | > + UVD_CGC_CTRL__SCPU_MODE_MASK); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); > + > + /* turn off clock gating */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); > + > + /* turn on SUVD clock gating */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); > + > + /* turn on sw mode in UVD_SUVD_CGC_CTRL */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); > +} > + > static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) > { > uint32_t data = 0; > @@ -614,7 +730,7 @@ static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) > * > * Setup and start the VCN block > */ > -static int vcn_v1_0_start(struct amdgpu_device *adev) > +static int vcn_v1_0_start_pg_mode(struct amdgpu_device *adev) Same comment here. With that fixed: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > { > struct amdgpu_ring *ring = &adev->vcn.ring_dec; > uint32_t rb_bufsz, tmp; > @@ -628,7 +744,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) > /* disable clock gating */ > vcn_v1_0_disable_clock_gating(adev); > > - vcn_v1_0_mc_resume(adev); > + vcn_v1_0_mc_resume_pg_mode(adev); > > /* disable interupt */ > WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, > @@ -799,6 +915,170 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) > return 0; > } > > +static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) > +{ > + struct amdgpu_ring *ring = &adev->vcn.ring_dec; > + uint32_t rb_bufsz, tmp, reg_data; > + uint32_t lmi_swap_cntl; > + > + /* disable byte swapping */ > + lmi_swap_cntl = 0; > + > + vcn_1_0_enable_static_power_gating(adev); > + > + /* enable dynamic power gating mode */ > + reg_data = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); > + reg_data |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; > + reg_data |= UVD_POWER_STATUS__UVD_PG_EN_MASK; > + WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data); > + > + /* enable clock gating */ > + vcn_v1_0_clock_gating_dpg_mode(adev, 0); > + > + /* enable VCPU clock */ > + reg_data = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); > + reg_data |= UVD_VCPU_CNTL__CLK_EN_MASK; > + reg_data |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, reg_data, 0xFFFFFFFF, 0); > + > + /* disable interupt */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, > + 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); > + > + /* stall UMC and register bus before resetting VCPU */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, > + UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); > + > + /* put LMI, VCPU, RBC etc... into reset */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, > + UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | > + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | > + UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | > + UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | > + UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | > + UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | > + UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | > + UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, > + 0xFFFFFFFF, 0); > + > + /* initialize VCN memory controller */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, > + (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | > + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | > + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | > + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | > + UVD_LMI_CTRL__REQ_MODE_MASK | > + 0x00100000L, 0xFFFFFFFF, 0); > + > +#ifdef __BIG_ENDIAN > + /* swap (8 in 32) RB and IB */ > + lmi_swap_cntl = 0xa; > +#endif > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); > + > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040, 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0, 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040, 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0, 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_ALU, 0, 0xFFFFFFFF, 0); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 0x88, 0xFFFFFFFF, 0); > + > + vcn_v1_0_mc_resume_dpg_mode(adev); > + > + /* take all subblocks out of reset, except VCPU */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, > + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0xFFFFFFFF, 0); > + > + /* enable VCPU clock */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, > + UVD_VCPU_CNTL__CLK_EN_MASK, 0xFFFFFFFF, 0); > + > + /* enable UMC */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, > + 0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); > + > + /* boot up the VCPU */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); > + > + /* enable master interrupt */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, > + (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), > + (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 0); > + > + vcn_v1_0_clock_gating_dpg_mode(adev, 1); > + /* setup mmUVD_LMI_CTRL */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, > + (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | > + UVD_LMI_CTRL__CRC_RESET_MASK | > + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | > + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | > + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | > + (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | > + 0x00100000L), 0xFFFFFFFF, 1); > + > + tmp = adev->gfx.config.gb_addr_config; > + /* setup VCN global tiling registers */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); > + > + /* enable System Interrupt for JRBC */ > + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN, > + UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); > + > + /* force RBC into idle state */ > + rb_bufsz = order_base_2(ring->ring_size); > + tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); > + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); > + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); > + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); > + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); > + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); > + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); > + > + /* set the write pointer delay */ > + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); > + > + /* set the wb address */ > + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, > + (upper_32_bits(ring->gpu_addr) >> 2)); > + > + /* programm the RB_BASE for ring buffer */ > + WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, > + lower_32_bits(ring->gpu_addr)); > + WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, > + upper_32_bits(ring->gpu_addr)); > + > + /* Initialize the ring buffer's read and write pointers */ > + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); > + > + ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); > + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, > + lower_32_bits(ring->wptr)); > + > + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, > + ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); > + > + /* initialize wptr */ > + ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); > + > + /* copy patch commands to the jpeg ring */ > + vcn_v1_0_jpeg_ring_set_patch_ring(ring, > + (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission)); > + > + return 0; > +} > + > +static int vcn_v1_0_start(struct amdgpu_device *adev) > +{ > + int r; > + > + if (adev->pg_flags & AMD_PG_SUPPORT_DPG) > + r = vcn_v1_0_start_dpg_mode(adev); > + else > + r = vcn_v1_0_start_pg_mode(adev); > + return r; > +} > + > /** > * vcn_v1_0_stop - stop VCN block > * > @@ -806,7 +1086,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) > * > * stop the VCN block > */ > -static int vcn_v1_0_stop(struct amdgpu_device *adev) > +static int vcn_v1_0_stop_pg_mode(struct amdgpu_device *adev) > { > /* force RBC into idle state */ > WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101); > @@ -836,6 +1116,33 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev) > return 0; > } > > +static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) > +{ > + int ret_code; > + > + /* Wait for power status to be 1 */ > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, > + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > + > + /* disable dynamic power gating mode */ > + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, > + ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); > + > + return 0; > +} > + > +static int vcn_v1_0_stop(struct amdgpu_device *adev) > +{ > + int r; > + > + if (adev->pg_flags & AMD_PG_SUPPORT_DPG) > + r = vcn_v1_0_stop_dpg_mode(adev); > + else > + r = vcn_v1_0_stop_pg_mode(adev); > + > + return r; > +} > + > static bool vcn_v1_0_is_idle(void *handle) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 6/8] drm/amdgpu:Add DPG pause state [not found] ` <1537905323-27071-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> ` (3 preceding siblings ...) 2018-09-25 19:55 ` [PATCH 5/8] drm/amdgpu:Add DPG mode support for vcn 1.0 James Zhu @ 2018-09-25 19:55 ` James Zhu 2018-09-25 19:55 ` [PATCH 7/8] drm/amdgpu:Add DPG pause mode support James Zhu 2018-09-25 19:55 ` [PATCH 8/8] drm/amdgpu:Enable DPG mode on PCO James Zhu 6 siblings, 0 replies; 15+ messages in thread From: James Zhu @ 2018-09-25 19:55 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo Add DPG pause state to support VCN DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index d2219ab..0b88a46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -56,6 +56,16 @@ enum engine_status_constants { UVD_STATUS__RBC_BUSY = 0x1, }; +enum internal_dpg_state { + VCN_DPG_STATE__UNPAUSE = 0, + VCN_DPG_STATE__PAUSE, +}; + +struct dpg_pause_state { + enum internal_dpg_state fw_based; + enum internal_dpg_state jpeg; +}; + struct amdgpu_vcn { struct amdgpu_bo *vcpu_bo; void *cpu_addr; @@ -70,6 +80,7 @@ struct amdgpu_vcn { struct amdgpu_irq_src irq; unsigned num_enc_rings; enum amd_powergating_state cur_state; + struct dpg_pause_state pause_state; }; int amdgpu_vcn_sw_init(struct amdgpu_device *adev); -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 7/8] drm/amdgpu:Add DPG pause mode support [not found] ` <1537905323-27071-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> ` (4 preceding siblings ...) 2018-09-25 19:55 ` [PATCH 6/8] drm/amdgpu:Add DPG pause state James Zhu @ 2018-09-25 19:55 ` James Zhu [not found] ` <1537905323-27071-7-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-09-25 19:55 ` [PATCH 8/8] drm/amdgpu:Enable DPG mode on PCO James Zhu 6 siblings, 1 reply; 15+ messages in thread From: James Zhu @ 2018-09-25 19:55 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo Add fucntions to support VCN DPG pause mode. Signed-off-by: James Zhu <James.Zhu@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 161 +++++++++++++++++++++++++++++++- 1 file changed, 159 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 27262a8..9d59cd2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -36,6 +36,7 @@ #include "soc15_common.h" #include "vcn/vcn_1_0_offset.h" +#include "vcn/vcn_1_0_sh_mask.h" /* 1 second timeout */ #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000) @@ -212,18 +213,158 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev) return 0; } +static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev, + struct dpg_pause_state *new_state) +{ + int ret_code; + uint32_t reg_data = 0; + uint32_t reg_data2 = 0; + struct amdgpu_ring *ring; + + /* pause/unpause if state is changed */ + if (adev->vcn.pause_state.fw_based != new_state->fw_based) { + DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", + adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, + new_state->fw_based, new_state->jpeg); + + reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & + (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); + + if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { + ret_code = 0; + + if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); + + if (!ret_code) { + /* pause DPG non-jpeg */ + reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); + + /* Restore */ + ring = &adev->vcn.ring_enc[0]; + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); + WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); + + ring = &adev->vcn.ring_enc[1]; + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); + WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); + + ring = &adev->vcn.ring_dec; + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, + lower_32_bits(ring->wptr) | 0x80000000); + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, + UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); + } + } else { + /* unpause dpg non-jpeg, no need to wait */ + reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); + } + adev->vcn.pause_state.fw_based = new_state->fw_based; + } + + /* pause/unpause if state is changed */ + if (adev->vcn.pause_state.jpeg != new_state->jpeg) { + DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", + adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, + new_state->fw_based, new_state->jpeg); + + reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & + (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); + + if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { + ret_code = 0; + + if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); + + if (!ret_code) { + /* Make sure JPRG Snoop is disabled before sending the pause */ + reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); + reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; + WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); + + /* pause DPG jpeg */ + reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, + UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, + UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); + + /* Restore */ + ring = &adev->vcn.ring_jpeg; + WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000001L | 0x00000002L); + WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, + lower_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, + upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); + + ring = &adev->vcn.ring_dec; + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, + lower_32_bits(ring->wptr) | 0x80000000); + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, + UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); + } + } else { + /* unpause dpg jpeg, no need to wait */ + reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); + } + adev->vcn.pause_state.jpeg = new_state->jpeg; + } + + return 0; +} + static void amdgpu_vcn_idle_work_handler(struct work_struct *work) { struct amdgpu_device *adev = container_of(work, struct amdgpu_device, vcn.idle_work.work); - unsigned fences = amdgpu_fence_count_emitted(&adev->vcn.ring_dec); - unsigned i; + unsigned int fences = 0; + unsigned int i; for (i = 0; i < adev->vcn.num_enc_rings; ++i) { fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]); } + if (adev->pg_flags & AMD_PG_SUPPORT_DPG) { + struct dpg_pause_state new_state; + + if (fences) + new_state.fw_based = VCN_DPG_STATE__PAUSE; + else + new_state.fw_based = VCN_DPG_STATE__UNPAUSE; + + if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg)) + new_state.jpeg = VCN_DPG_STATE__PAUSE; + else + new_state.jpeg = VCN_DPG_STATE__UNPAUSE; + + amdgpu_vcn_pause_dpg_mode(adev, &new_state); + } + fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg); + fences += amdgpu_fence_count_emitted(&adev->vcn.ring_dec); if (fences == 0) { amdgpu_gfx_off_ctrl(adev, true); @@ -250,6 +391,22 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, AMD_PG_STATE_UNGATE); } + + if (adev->pg_flags & AMD_PG_SUPPORT_DPG) { + struct dpg_pause_state new_state; + + if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) + new_state.fw_based = VCN_DPG_STATE__PAUSE; + else + new_state.fw_based = adev->vcn.pause_state.fw_based; + + if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) + new_state.jpeg = VCN_DPG_STATE__PAUSE; + else + new_state.jpeg = adev->vcn.pause_state.jpeg; + + amdgpu_vcn_pause_dpg_mode(adev, &new_state); + } } void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
[parent not found: <1537905323-27071-7-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 7/8] drm/amdgpu:Add DPG pause mode support [not found] ` <1537905323-27071-7-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-09-25 20:12 ` Alex Deucher 0 siblings, 0 replies; 15+ messages in thread From: Alex Deucher @ 2018-09-25 20:12 UTC (permalink / raw) To: James Zhu; +Cc: James Zhu, amd-gfx list On Tue, Sep 25, 2018 at 4:04 PM James Zhu <jzhums@gmail.com> wrote: > > Add fucntions to support VCN DPG pause mode. fucntions -> functions With that fixed: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > > Signed-off-by: James Zhu <James.Zhu@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 161 +++++++++++++++++++++++++++++++- > 1 file changed, 159 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > index 27262a8..9d59cd2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > @@ -36,6 +36,7 @@ > #include "soc15_common.h" > > #include "vcn/vcn_1_0_offset.h" > +#include "vcn/vcn_1_0_sh_mask.h" > > /* 1 second timeout */ > #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000) > @@ -212,18 +213,158 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev) > return 0; > } > > +static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev, > + struct dpg_pause_state *new_state) > +{ > + int ret_code; > + uint32_t reg_data = 0; > + uint32_t reg_data2 = 0; > + struct amdgpu_ring *ring; > + > + /* pause/unpause if state is changed */ > + if (adev->vcn.pause_state.fw_based != new_state->fw_based) { > + DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", > + adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, > + new_state->fw_based, new_state->jpeg); > + > + reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & > + (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); > + > + if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { > + ret_code = 0; > + > + if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, > + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, > + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > + > + if (!ret_code) { > + /* pause DPG non-jpeg */ > + reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; > + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, > + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, > + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); > + > + /* Restore */ > + ring = &adev->vcn.ring_enc[0]; > + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); > + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); > + WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); > + WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); > + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); > + > + ring = &adev->vcn.ring_enc[1]; > + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); > + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); > + WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); > + WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); > + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); > + > + ring = &adev->vcn.ring_dec; > + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, > + lower_32_bits(ring->wptr) | 0x80000000); > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, > + UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, > + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > + } > + } else { > + /* unpause dpg non-jpeg, no need to wait */ > + reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; > + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); > + } > + adev->vcn.pause_state.fw_based = new_state->fw_based; > + } > + > + /* pause/unpause if state is changed */ > + if (adev->vcn.pause_state.jpeg != new_state->jpeg) { > + DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", > + adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, > + new_state->fw_based, new_state->jpeg); > + > + reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & > + (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); > + > + if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { > + ret_code = 0; > + > + if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, > + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, > + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > + > + if (!ret_code) { > + /* Make sure JPRG Snoop is disabled before sending the pause */ > + reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); > + reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; > + WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); > + > + /* pause DPG jpeg */ > + reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; > + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, > + UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, > + UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); > + > + /* Restore */ > + ring = &adev->vcn.ring_jpeg; > + WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); > + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000001L | 0x00000002L); > + WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, > + lower_32_bits(ring->gpu_addr)); > + WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, > + upper_32_bits(ring->gpu_addr)); > + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); > + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); > + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); > + > + ring = &adev->vcn.ring_dec; > + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, > + lower_32_bits(ring->wptr) | 0x80000000); > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, > + UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, > + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > + } > + } else { > + /* unpause dpg jpeg, no need to wait */ > + reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; > + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); > + } > + adev->vcn.pause_state.jpeg = new_state->jpeg; > + } > + > + return 0; > +} > + > static void amdgpu_vcn_idle_work_handler(struct work_struct *work) > { > struct amdgpu_device *adev = > container_of(work, struct amdgpu_device, vcn.idle_work.work); > - unsigned fences = amdgpu_fence_count_emitted(&adev->vcn.ring_dec); > - unsigned i; > + unsigned int fences = 0; > + unsigned int i; > > for (i = 0; i < adev->vcn.num_enc_rings; ++i) { > fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]); > } > > + if (adev->pg_flags & AMD_PG_SUPPORT_DPG) { > + struct dpg_pause_state new_state; > + > + if (fences) > + new_state.fw_based = VCN_DPG_STATE__PAUSE; > + else > + new_state.fw_based = VCN_DPG_STATE__UNPAUSE; > + > + if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg)) > + new_state.jpeg = VCN_DPG_STATE__PAUSE; > + else > + new_state.jpeg = VCN_DPG_STATE__UNPAUSE; > + > + amdgpu_vcn_pause_dpg_mode(adev, &new_state); > + } > + > fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg); > + fences += amdgpu_fence_count_emitted(&adev->vcn.ring_dec); > > if (fences == 0) { > amdgpu_gfx_off_ctrl(adev, true); > @@ -250,6 +391,22 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) > amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, > AMD_PG_STATE_UNGATE); > } > + > + if (adev->pg_flags & AMD_PG_SUPPORT_DPG) { > + struct dpg_pause_state new_state; > + > + if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) > + new_state.fw_based = VCN_DPG_STATE__PAUSE; > + else > + new_state.fw_based = adev->vcn.pause_state.fw_based; > + > + if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) > + new_state.jpeg = VCN_DPG_STATE__PAUSE; > + else > + new_state.jpeg = adev->vcn.pause_state.jpeg; > + > + amdgpu_vcn_pause_dpg_mode(adev, &new_state); > + } > } > > void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 8/8] drm/amdgpu:Enable DPG mode on PCO [not found] ` <1537905323-27071-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> ` (5 preceding siblings ...) 2018-09-25 19:55 ` [PATCH 7/8] drm/amdgpu:Add DPG pause mode support James Zhu @ 2018-09-25 19:55 ` James Zhu [not found] ` <1537905323-27071-8-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> 6 siblings, 1 reply; 15+ messages in thread From: James Zhu @ 2018-09-25 19:55 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: james.zhu-5C7GfCeVMHo Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso Signed-off-by: James Zhu <James.Zhu@amd.com> --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 138c481..9f462c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -739,7 +739,8 @@ static int soc15_common_early_init(void *handle) adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_MMHUB | - AMD_PG_SUPPORT_VCN; + AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_DPG; } else { adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS | -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
[parent not found: <1537905323-27071-8-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 8/8] drm/amdgpu:Enable DPG mode on PCO [not found] ` <1537905323-27071-8-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-09-25 20:15 ` Alex Deucher [not found] ` <CADnq5_O22AkJy3tT1ba5pUEPo5LsQuh992V7kizFgh6noS93uw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 15+ messages in thread From: Alex Deucher @ 2018-09-25 20:15 UTC (permalink / raw) To: James Zhu; +Cc: James Zhu, amd-gfx list On Tue, Sep 25, 2018 at 4:04 PM James Zhu <jzhums@gmail.com> wrote: > > Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso > > Signed-off-by: James Zhu <James.Zhu@amd.com> I made some comments on a few of the patches, the rest are: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c > index 138c481..9f462c0 100644 > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c > @@ -739,7 +739,8 @@ static int soc15_common_early_init(void *handle) > > adev->pg_flags = AMD_PG_SUPPORT_SDMA | > AMD_PG_SUPPORT_MMHUB | > - AMD_PG_SUPPORT_VCN; > + AMD_PG_SUPPORT_VCN | > + AMD_PG_SUPPORT_DPG; > } else { > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | > AMD_CG_SUPPORT_GFX_MGLS | > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
[parent not found: <CADnq5_O22AkJy3tT1ba5pUEPo5LsQuh992V7kizFgh6noS93uw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 8/8] drm/amdgpu:Enable DPG mode on PCO [not found] ` <CADnq5_O22AkJy3tT1ba5pUEPo5LsQuh992V7kizFgh6noS93uw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2018-09-25 23:02 ` James Zhu 0 siblings, 0 replies; 15+ messages in thread From: James Zhu @ 2018-09-25 23:02 UTC (permalink / raw) To: Alex Deucher, James Zhu; +Cc: James Zhu, amd-gfx list On 2018-09-25 04:15 PM, Alex Deucher wrote: > On Tue, Sep 25, 2018 at 4:04 PM James Zhu <jzhums@gmail.com> wrote: >> Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso >> >> Signed-off-by: James Zhu <James.Zhu@amd.com> > I made some comments on a few of the patches, the rest are: > Reviewed-by: Alex Deucher <alexander.deucher@amd.com> All fixed will be included in the v2 patches. James >> --- >> drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c >> index 138c481..9f462c0 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c >> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c >> @@ -739,7 +739,8 @@ static int soc15_common_early_init(void *handle) >> >> adev->pg_flags = AMD_PG_SUPPORT_SDMA | >> AMD_PG_SUPPORT_MMHUB | >> - AMD_PG_SUPPORT_VCN; >> + AMD_PG_SUPPORT_VCN | >> + AMD_PG_SUPPORT_DPG; >> } else { >> adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | >> AMD_CG_SUPPORT_GFX_MGLS | >> -- >> 2.7.4 >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-09-26 12:55 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-09-25 19:55 [PATCH 1/8] drm/amdgpu:Use register UVD_SCRATCH9 for VCN ring/ib test James Zhu
[not found] ` <1537905323-27071-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-25 19:55 ` [PATCH 2/8] drm/amdgpu:Add new register offset/mask to support VCN DPG mode James Zhu
2018-09-25 19:55 ` [PATCH 3/8] drm/amdgpu:Add DPG support flag James Zhu
[not found] ` <1537905323-27071-3-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-25 20:06 ` Alex Deucher
2018-09-26 8:02 ` Christian König
[not found] ` <44a25354-4329-c942-8f86-0528a0b2ce84-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-09-26 12:55 ` James Zhu
2018-09-25 19:55 ` [PATCH 4/8] drm/amdgpu:Add DPG mode read/write macro James Zhu
2018-09-25 19:55 ` [PATCH 5/8] drm/amdgpu:Add DPG mode support for vcn 1.0 James Zhu
[not found] ` <1537905323-27071-5-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-25 20:09 ` Alex Deucher
2018-09-25 19:55 ` [PATCH 6/8] drm/amdgpu:Add DPG pause state James Zhu
2018-09-25 19:55 ` [PATCH 7/8] drm/amdgpu:Add DPG pause mode support James Zhu
[not found] ` <1537905323-27071-7-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-25 20:12 ` Alex Deucher
2018-09-25 19:55 ` [PATCH 8/8] drm/amdgpu:Enable DPG mode on PCO James Zhu
[not found] ` <1537905323-27071-8-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-09-25 20:15 ` Alex Deucher
[not found] ` <CADnq5_O22AkJy3tT1ba5pUEPo5LsQuh992V7kizFgh6noS93uw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-09-25 23:02 ` James Zhu
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