From: Hans de Goede <hdegoede@redhat.com> To: Chen-Yu Tsai <wens@csie.org>, Ulf Hansson <ulf.hansson@linaro.org>, Maxime Ripard <maxime.ripard@free-electrons.com> Cc: linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/3] mmc: sunxi: Fix DDR MMC timings for A80 Date: Mon, 30 May 2016 13:34:42 +0200 [thread overview] Message-ID: <99d78ff3-db4d-45cc-024a-d94583b56f35@redhat.com> (raw) In-Reply-To: <1464505484-3661-3-git-send-email-wens@csie.org> Hi, On 29-05-16 09:04, Chen-Yu Tsai wrote: > The MMC clock timings were incorrectly calculated, when the conversion > from delay value to delay phase was done. > > The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR > unusable. Unfortunately it seems different controllers on the same SoC > have different timings. The new settings are taken from mmc2, which is > commonly used with eMMC. Hmm, I'm not really all that familiar with mmc, but can't an external sdcard connected to mmc0 use DDR too ? Assuming the answer is yes, then we really need to update the driver to use the right per controller timings. > The settings for the slower timing modes seem to work despite being > wrong, so leave them be. If you're sure the timings are wrong, please fix them. Sometimes wrong timings do seem to work, but lead to unreliable communication, or turn out to work on some boards and not on others due to routing differences. Thanks & Regards, Hans > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > drivers/mmc/host/sunxi-mmc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c > index 7fc8b7aa83f0..5873dc344ab2 100644 > --- a/drivers/mmc/host/sunxi-mmc.c > +++ b/drivers/mmc/host/sunxi-mmc.c > @@ -970,8 +970,8 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { > [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, > [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, > [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, > - [SDXC_CLK_50M_DDR] = { .output = 90, .sample = 120 }, > - [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 120 }, > + [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, > + [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, > }; > > static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, >
WARNING: multiple messages have this Message-ID (diff)
From: hdegoede@redhat.com (Hans de Goede) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] mmc: sunxi: Fix DDR MMC timings for A80 Date: Mon, 30 May 2016 13:34:42 +0200 [thread overview] Message-ID: <99d78ff3-db4d-45cc-024a-d94583b56f35@redhat.com> (raw) In-Reply-To: <1464505484-3661-3-git-send-email-wens@csie.org> Hi, On 29-05-16 09:04, Chen-Yu Tsai wrote: > The MMC clock timings were incorrectly calculated, when the conversion > from delay value to delay phase was done. > > The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR > unusable. Unfortunately it seems different controllers on the same SoC > have different timings. The new settings are taken from mmc2, which is > commonly used with eMMC. Hmm, I'm not really all that familiar with mmc, but can't an external sdcard connected to mmc0 use DDR too ? Assuming the answer is yes, then we really need to update the driver to use the right per controller timings. > The settings for the slower timing modes seem to work despite being > wrong, so leave them be. If you're sure the timings are wrong, please fix them. Sometimes wrong timings do seem to work, but lead to unreliable communication, or turn out to work on some boards and not on others due to routing differences. Thanks & Regards, Hans > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > drivers/mmc/host/sunxi-mmc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c > index 7fc8b7aa83f0..5873dc344ab2 100644 > --- a/drivers/mmc/host/sunxi-mmc.c > +++ b/drivers/mmc/host/sunxi-mmc.c > @@ -970,8 +970,8 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { > [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, > [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, > [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, > - [SDXC_CLK_50M_DDR] = { .output = 90, .sample = 120 }, > - [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 120 }, > + [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, > + [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, > }; > > static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, >
next prev parent reply other threads:[~2016-05-30 11:34 UTC|newest] Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-05-29 7:04 [PATCH 0/3] mmc: sunxi: Fix MMC DDR modes for Allwinner A80 Chen-Yu Tsai 2016-05-29 7:04 ` Chen-Yu Tsai 2016-05-29 7:04 ` [PATCH 1/3] mmc: fix mmc mode selection for HS-DDR and higher Chen-Yu Tsai 2016-05-29 7:04 ` Chen-Yu Tsai 2016-05-31 9:30 ` Krzysztof Kozlowski 2016-05-31 9:30 ` Krzysztof Kozlowski 2016-06-01 1:25 ` Jaehoon Chung 2016-06-01 1:25 ` Jaehoon Chung 2016-06-01 2:36 ` Shawn Lin 2016-06-01 2:36 ` Shawn Lin 2016-06-01 9:19 ` Marcel Ziswiler 2016-06-01 9:19 ` Marcel Ziswiler 2016-06-01 18:58 ` Bjorn Andersson 2016-06-01 18:58 ` Bjorn Andersson 2016-06-02 8:08 ` Chen-Yu Tsai 2016-06-02 8:08 ` Chen-Yu Tsai 2016-06-02 8:31 ` Ulf Hansson 2016-06-02 8:31 ` Ulf Hansson 2016-06-02 8:31 ` Ulf Hansson 2016-06-02 9:35 ` Krzysztof Kozlowski 2016-06-02 9:35 ` Krzysztof Kozlowski 2016-06-02 9:35 ` Krzysztof Kozlowski 2016-06-02 15:01 ` Ulf Hansson 2016-06-02 15:01 ` Ulf Hansson 2016-06-02 15:01 ` Ulf Hansson 2016-05-29 7:04 ` [PATCH 2/3] mmc: sunxi: Fix DDR MMC timings for A80 Chen-Yu Tsai 2016-05-29 7:04 ` Chen-Yu Tsai 2016-05-30 11:34 ` Hans de Goede [this message] 2016-05-30 11:34 ` Hans de Goede 2016-05-30 12:59 ` Chen-Yu Tsai 2016-05-30 12:59 ` Chen-Yu Tsai 2016-05-30 15:38 ` Chen-Yu Tsai 2016-05-30 15:38 ` Chen-Yu Tsai 2016-05-30 18:05 ` Hans de Goede 2016-05-30 18:05 ` Hans de Goede 2016-05-29 7:04 ` [PATCH 3/3] mmc: sunxi: Re-enable eMMC HS-DDR modes on Allwinner A80 Chen-Yu Tsai 2016-05-29 7:04 ` Chen-Yu Tsai
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