* [PATCH v5 01/21] ppc440_bamboo: Remove unnecessary memsets
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 02/21] ppc4xx: Introduce Ppc4xxSdramBank struct BALATON Zoltan
` (20 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
In ppc4xx_sdram_init() the struct is allocated with g_new0() so no
need to clear its elements. In the bamboo machine init memset can be
replaced with array initialiser which is shorter.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc440_bamboo.c | 6 ++----
hw/ppc/ppc4xx_devs.c | 8 ++------
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index ea945a1c99..5ec82fa8c2 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -169,8 +169,8 @@ static void bamboo_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
- hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
- hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
+ hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS] = {0};
+ hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS] = {0};
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
@@ -205,8 +205,6 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- memset(ram_bases, 0, sizeof(ram_bases));
- memset(ram_sizes, 0, sizeof(ram_sizes));
ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index ce38ae65e6..b4cd10f735 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -363,12 +363,8 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
sdram->irq = irq;
sdram->nbanks = nbanks;
sdram->ram_memories = ram_memories;
- memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
- memcpy(sdram->ram_bases, ram_bases,
- nbanks * sizeof(hwaddr));
- memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
- memcpy(sdram->ram_sizes, ram_sizes,
- nbanks * sizeof(hwaddr));
+ memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr));
+ memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr));
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 02/21] ppc4xx: Introduce Ppc4xxSdramBank struct
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 01/21] ppc440_bamboo: Remove unnecessary memsets BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 03/21] ppc4xx_sdram: Get rid of the init RAM hack BALATON Zoltan
` (19 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Instead of storing sdram bank parameters in unrelated arrays put them
in a struct so it's clear they belong to the same bank and simplify
the state struct using this bank type.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/ppc/ppc440_uc.c | 49 +++++++++++++++++-----------------
hw/ppc/ppc4xx_devs.c | 59 ++++++++++++++++++++---------------------
include/hw/ppc/ppc4xx.h | 8 ++++++
3 files changed, 61 insertions(+), 55 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 53e981ddf4..db33334e29 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -16,7 +16,7 @@
#include "qemu/module.h"
#include "hw/irq.h"
#include "exec/memory.h"
-#include "hw/ppc/ppc.h"
+#include "hw/ppc/ppc4xx.h"
#include "hw/qdev-properties.h"
#include "hw/pci/pci.h"
#include "sysemu/block-backend.h"
@@ -485,11 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
typedef struct ppc440_sdram_t {
uint32_t addr;
int nbanks;
- MemoryRegion containers[4]; /* used for clipping */
- MemoryRegion *ram_memories;
- hwaddr ram_bases[4];
- hwaddr ram_sizes[4];
- uint32_t bcr[4];
+ Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
enum {
@@ -570,23 +566,23 @@ static uint64_t sdram_size(uint32_t bcr)
static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
uint32_t bcr, int enabled)
{
- if (sdram->bcr[i] & 1) {
+ if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
memory_region_del_subregion(get_system_memory(),
- &sdram->containers[i]);
- memory_region_del_subregion(&sdram->containers[i],
- &sdram->ram_memories[i]);
- object_unparent(OBJECT(&sdram->containers[i]));
+ &sdram->bank[i].container);
+ memory_region_del_subregion(&sdram->bank[i].container,
+ &sdram->bank[i].ram);
+ object_unparent(OBJECT(&sdram->bank[i].container));
}
- sdram->bcr[i] = bcr & 0xffe0ffc1;
+ sdram->bank[i].bcr = bcr & 0xffe0ffc1;
if (enabled && (bcr & 1)) {
- memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
+ memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
sdram_size(bcr));
- memory_region_add_subregion(&sdram->containers[i], 0,
- &sdram->ram_memories[i]);
+ memory_region_add_subregion(&sdram->bank[i].container, 0,
+ &sdram->bank[i].ram);
memory_region_add_subregion(get_system_memory(),
sdram_base(bcr),
- &sdram->containers[i]);
+ &sdram->bank[i].container);
}
}
@@ -595,9 +591,9 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->ram_sizes[i] != 0) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i],
- sdram->ram_sizes[i]), 1);
+ if (sdram->bank[i].size != 0) {
+ sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
sdram_set_bcr(sdram, i, 0, 0);
}
@@ -614,9 +610,9 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
case SDRAM_R1BAS:
case SDRAM_R2BAS:
case SDRAM_R3BAS:
- if (sdram->ram_sizes[dcrn - SDRAM_R0BAS]) {
- ret = sdram_bcr(sdram->ram_bases[dcrn - SDRAM_R0BAS],
- sdram->ram_sizes[dcrn - SDRAM_R0BAS]);
+ if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
+ ret = sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
+ sdram->bank[dcrn - SDRAM_R0BAS].size);
}
break;
case SDRAM_CONF1HB:
@@ -701,12 +697,15 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
int do_init)
{
ppc440_sdram_t *sdram;
+ int i;
sdram = g_malloc0(sizeof(*sdram));
sdram->nbanks = nbanks;
- sdram->ram_memories = ram_memories;
- memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr));
- memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr));
+ for (i = 0; i < nbanks; i++) {
+ sdram->bank[i].ram = ram_memories[i];
+ sdram->bank[i].base = ram_bases[i];
+ sdram->bank[i].size = ram_sizes[i];
+ }
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index b4cd10f735..1226ec4aa9 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -42,10 +42,7 @@ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
struct ppc4xx_sdram_t {
uint32_t addr;
int nbanks;
- MemoryRegion containers[4]; /* used for clipping */
- MemoryRegion *ram_memories;
- hwaddr ram_bases[4];
- hwaddr ram_sizes[4];
+ Ppc4xxSdramBank bank[4];
uint32_t besr0;
uint32_t besr1;
uint32_t bear;
@@ -53,7 +50,6 @@ struct ppc4xx_sdram_t {
uint32_t status;
uint32_t rtr;
uint32_t pmit;
- uint32_t bcr[4];
uint32_t tr;
uint32_t ecccfg;
uint32_t eccesr;
@@ -131,26 +127,26 @@ static target_ulong sdram_size(uint32_t bcr)
static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
uint32_t bcr, int enabled)
{
- if (sdram->bcr[i] & 0x00000001) {
+ if (sdram->bank[i].bcr & 0x00000001) {
/* Unmap RAM */
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]),
- sdram_size(sdram->bcr[i]));
+ trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
+ sdram_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
- &sdram->containers[i]);
- memory_region_del_subregion(&sdram->containers[i],
- &sdram->ram_memories[i]);
- object_unparent(OBJECT(&sdram->containers[i]));
+ &sdram->bank[i].container);
+ memory_region_del_subregion(&sdram->bank[i].container,
+ &sdram->bank[i].ram);
+ object_unparent(OBJECT(&sdram->bank[i].container));
}
- sdram->bcr[i] = bcr & 0xFFDEE001;
+ sdram->bank[i].bcr = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
- memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
+ memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
sdram_size(bcr));
- memory_region_add_subregion(&sdram->containers[i], 0,
- &sdram->ram_memories[i]);
+ memory_region_add_subregion(&sdram->bank[i].container, 0,
+ &sdram->bank[i].ram);
memory_region_add_subregion(get_system_memory(),
sdram_base(bcr),
- &sdram->containers[i]);
+ &sdram->bank[i].container);
}
}
@@ -159,9 +155,9 @@ static void sdram_map_bcr(ppc4xx_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->ram_sizes[i] != 0) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i],
- sdram->ram_sizes[i]), 1);
+ if (sdram->bank[i].size != 0) {
+ sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
sdram_set_bcr(sdram, i, 0x00000000, 0);
}
@@ -173,10 +169,10 @@ static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]),
- sdram_size(sdram->bcr[i]));
+ trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
+ sdram_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
- &sdram->ram_memories[i]);
+ &sdram->bank[i].ram);
}
}
@@ -214,16 +210,16 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
ret = sdram->pmit;
break;
case 0x40: /* SDRAM_B0CR */
- ret = sdram->bcr[0];
+ ret = sdram->bank[0].bcr;
break;
case 0x44: /* SDRAM_B1CR */
- ret = sdram->bcr[1];
+ ret = sdram->bank[1].bcr;
break;
case 0x48: /* SDRAM_B2CR */
- ret = sdram->bcr[2];
+ ret = sdram->bank[2].bcr;
break;
case 0x4C: /* SDRAM_B3CR */
- ret = sdram->bcr[3];
+ ret = sdram->bank[3].bcr;
break;
case 0x80: /* SDRAM_TR */
ret = -1; /* ? */
@@ -358,13 +354,16 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
int do_init)
{
ppc4xx_sdram_t *sdram;
+ int i;
sdram = g_new0(ppc4xx_sdram_t, 1);
sdram->irq = irq;
sdram->nbanks = nbanks;
- sdram->ram_memories = ram_memories;
- memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr));
- memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr));
+ for (i = 0; i < nbanks; i++) {
+ sdram->bank[i].ram = ram_memories[i];
+ sdram->bank[i].base = ram_bases[i];
+ sdram->bank[i].size = ram_sizes[i];
+ }
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index a1781afa8e..2af0d60577 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -29,6 +29,14 @@
#include "exec/memory.h"
#include "hw/sysbus.h"
+typedef struct {
+ MemoryRegion ram;
+ MemoryRegion container; /* used for clipping */
+ hwaddr base;
+ hwaddr size;
+ uint32_t bcr;
+} Ppc4xxSdramBank;
+
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
MemoryRegion ram_memories[],
hwaddr ram_bases[], hwaddr ram_sizes[],
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 03/21] ppc4xx_sdram: Get rid of the init RAM hack
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 01/21] ppc440_bamboo: Remove unnecessary memsets BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 02/21] ppc4xx: Introduce Ppc4xxSdramBank struct BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 04/21] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() BALATON Zoltan
` (18 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
The do_init parameter of ppc4xx_sdram_init() is used to map memory
regions that is normally done by the firmware by programming the SDRAM
controller. Do this from board code emulating what firmware would do
when booting a kernel directly from -kernel without a firmware so we
can get rid of this do_init hack.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
v5: Add function to enable sdram controller
v2: Fix ref405ep boot with -kernel and U-Boot
hw/ppc/ppc405.h | 1 -
hw/ppc/ppc405_boards.c | 3 +--
hw/ppc/ppc405_uc.c | 4 +---
hw/ppc/ppc440_bamboo.c | 4 +++-
hw/ppc/ppc4xx_devs.c | 12 +++++++-----
include/hw/ppc/ppc4xx.h | 5 +++--
6 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 1e558c7831..756865621b 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -169,7 +169,6 @@ struct Ppc405SoCState {
/* Public */
MemoryRegion ram_banks[2];
hwaddr ram_bases[2], ram_sizes[2];
- bool do_dram_init;
MemoryRegion *dram_mr;
hwaddr ram_size;
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 083f12b23e..1eaeca8806 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -288,8 +288,6 @@ static void ppc405_init(MachineState *machine)
machine->ram_size, &error_fatal);
object_property_set_link(OBJECT(&ppc405->soc), "dram",
OBJECT(machine->ram), &error_abort);
- object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
- kernel_filename != NULL, &error_abort);
object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
&error_abort);
qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
@@ -349,6 +347,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) {
+ ppc4xx_sdram_enable(&ppc405->soc.cpu.env);
boot_from_kernel(machine, &ppc405->soc.cpu);
}
}
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 2ca42fdef6..1e02347e57 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1081,8 +1081,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
s->ram_bases[0], s->ram_sizes[0]);
ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->ram_banks, s->ram_bases, s->ram_sizes,
- s->do_dram_init);
+ s->ram_banks, s->ram_bases, s->ram_sizes);
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@@ -1160,7 +1159,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
- DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 5ec82fa8c2..409a8840da 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -211,7 +211,9 @@ static void bamboo_init(MachineState *machine)
ppc4xx_sdram_init(env,
qdev_get_gpio_in(uicdev, 14),
PPC440EP_SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes, 1);
+ ram_bases, ram_sizes);
+ /* Enable SDRAM memory regions, this should be done by the firmware */
+ ppc4xx_sdram_enable(env);
/* PCI */
dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 1226ec4aa9..3475589679 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -350,8 +350,7 @@ static void sdram_reset(void *opaque)
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion *ram_memories,
hwaddr *ram_bases,
- hwaddr *ram_sizes,
- int do_init)
+ hwaddr *ram_sizes)
{
ppc4xx_sdram_t *sdram;
int i;
@@ -369,9 +368,12 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
sdram, &dcr_read_sdram, &dcr_write_sdram);
- if (do_init) {
- sdram_map_bcr(sdram);
- }
+}
+
+void ppc4xx_sdram_enable(CPUPPCState *env)
+{
+ ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20);
+ ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000);
}
/*
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 2af0d60577..13b3229851 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -37,6 +37,8 @@ typedef struct {
uint32_t bcr;
} Ppc4xxSdramBank;
+void ppc4xx_sdram_enable(CPUPPCState *env);
+
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
MemoryRegion ram_memories[],
hwaddr ram_bases[], hwaddr ram_sizes[],
@@ -45,8 +47,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion ram_memories[],
hwaddr *ram_bases,
- hwaddr *ram_sizes,
- int do_init);
+ hwaddr *ram_sizes);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 04/21] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (2 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 03/21] ppc4xx_sdram: Get rid of the init RAM hack BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 05/21] ppc440_bamboo: Add missing 4 MiB valid memory size BALATON Zoltan
` (17 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead
of the separate arrays and adjust ppc4xx_sdram_init() and
ppc440_sdram_init() accordingly as well as machines using these.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
v2: Use pointer for ram_banks in the prototype of the init funcs as
an array of struct seems to confuse gcc 12.2.1 and provoke a warning
hw/ppc/ppc405.h | 4 +---
hw/ppc/ppc405_uc.c | 10 +++++-----
hw/ppc/ppc440.h | 5 ++---
hw/ppc/ppc440_bamboo.c | 15 ++++++---------
hw/ppc/ppc440_uc.c | 9 ++++-----
hw/ppc/ppc4xx_devs.c | 21 +++++++++------------
hw/ppc/sam460ex.c | 15 +++++----------
include/hw/ppc/ppc4xx.h | 9 +++------
8 files changed, 35 insertions(+), 53 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 756865621b..ca0972b88b 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -167,9 +167,7 @@ struct Ppc405SoCState {
DeviceState parent_obj;
/* Public */
- MemoryRegion ram_banks[2];
- hwaddr ram_bases[2], ram_sizes[2];
-
+ Ppc4xxSdramBank ram_banks[2];
MemoryRegion *dram_mr;
hwaddr ram_size;
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 1e02347e57..bcbf35bc14 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1074,14 +1074,14 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
- s->ram_bases[0] = 0;
- s->ram_sizes[0] = s->ram_size;
- memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
+ s->ram_banks[0].base = 0;
+ s->ram_banks[0].size = s->ram_size;
+ memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s),
"ppc405.sdram0", s->dram_mr,
- s->ram_bases[0], s->ram_sizes[0]);
+ s->ram_banks[0].base, s->ram_banks[0].size);
ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->ram_banks, s->ram_bases, s->ram_sizes);
+ s->ram_banks);
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 7cef936125..e6c905b7d6 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -11,14 +11,13 @@
#ifndef PPC440_H
#define PPC440_H
-#include "hw/ppc/ppc.h"
+#include "hw/ppc/ppc4xx.h"
void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram_memories,
- hwaddr *ram_bases, hwaddr *ram_sizes,
+ Ppc4xxSdramBank *ram_banks,
int do_init);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 409a8840da..edfb8c9709 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -168,9 +168,8 @@ static void bamboo_init(MachineState *machine)
unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
- MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
- hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS] = {0};
- hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS] = {0};
+ Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank,
+ PPC440EP_SDRAM_NR_BANKS);
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
@@ -205,13 +204,11 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
+ ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks,
+ ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
- ppc4xx_sdram_init(env,
- qdev_get_gpio_in(uicdev, 14),
- PPC440EP_SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes);
+ ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
+ PPC440EP_SDRAM_NR_BANKS, ram_banks);
/* Enable SDRAM memory regions, this should be done by the firmware */
ppc4xx_sdram_enable(env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index db33334e29..8eae4ad9f0 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -692,8 +692,7 @@ static void sdram_reset(void *opaque)
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram_memories,
- hwaddr *ram_bases, hwaddr *ram_sizes,
+ Ppc4xxSdramBank *ram_banks,
int do_init)
{
ppc440_sdram_t *sdram;
@@ -702,9 +701,9 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
sdram = g_malloc0(sizeof(*sdram));
sdram->nbanks = nbanks;
for (i = 0; i < nbanks; i++) {
- sdram->bank[i].ram = ram_memories[i];
- sdram->bank[i].base = ram_bases[i];
- sdram->bank[i].size = ram_sizes[i];
+ sdram->bank[i].ram = ram_banks[i].ram;
+ sdram->bank[i].base = ram_banks[i].base;
+ sdram->bank[i].size = ram_banks[i].size;
}
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 3475589679..fcbda57c55 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -348,9 +348,7 @@ static void sdram_reset(void *opaque)
}
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion *ram_memories,
- hwaddr *ram_bases,
- hwaddr *ram_sizes)
+ Ppc4xxSdramBank *ram_banks)
{
ppc4xx_sdram_t *sdram;
int i;
@@ -359,9 +357,9 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
sdram->irq = irq;
sdram->nbanks = nbanks;
for (i = 0; i < nbanks; i++) {
- sdram->bank[i].ram = ram_memories[i];
- sdram->bank[i].base = ram_bases[i];
- sdram->bank[i].size = ram_sizes[i];
+ sdram->bank[i].ram = ram_banks[i].ram;
+ sdram->bank[i].base = ram_banks[i].base;
+ sdram->bank[i].size = ram_banks[i].size;
}
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
@@ -387,8 +385,7 @@ void ppc4xx_sdram_enable(CPUPPCState *env)
* sizes varies by SoC.
*/
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
- MemoryRegion ram_memories[],
- hwaddr ram_bases[], hwaddr ram_sizes[],
+ Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[])
{
ram_addr_t size_left = memory_region_size(ram);
@@ -403,13 +400,13 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
if (bank_size <= size_left) {
char name[32];
- ram_bases[i] = base;
- ram_sizes[i] = bank_size;
+ ram_banks[i].base = base;
+ ram_banks[i].size = bank_size;
base += bank_size;
size_left -= bank_size;
snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
- memory_region_init_alias(&ram_memories[i], NULL, name, ram,
- ram_bases[i], ram_sizes[i]);
+ memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram,
+ ram_banks[i].base, ram_banks[i].size);
break;
}
}
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 850bb3b817..f4c2a693fb 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -73,7 +73,6 @@
#define OPB_FREQ 115000000
#define EBC_FREQ 115000000
#define UART_FREQ 11059200
-#define SDRAM_NR_BANKS 4
/* The SoC could also handle 4 GiB but firmware does not work with that. */
/* Maybe it overflows a signed 32 bit number somewhere? */
@@ -274,9 +273,7 @@ static void sam460ex_init(MachineState *machine)
{
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
- MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
- hwaddr ram_bases[SDRAM_NR_BANKS] = {0};
- hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
+ Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank, 1);
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
DeviceState *uic[4];
int i;
@@ -345,20 +342,18 @@ static void sam460ex_init(MachineState *machine)
/* SDRAM controller */
/* put all RAM on first bank because board has one slot
* and firmware only checks that */
- ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes,
- ppc460ex_sdram_bank_sizes);
+ ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes);
/* FIXME: does 460EX have ECC interrupts? */
- ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes, 1);
+ ppc440_sdram_init(env, 1, ram_banks, 1);
/* IIC controllers and devices */
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
qdev_get_gpio_in(uic[0], 2));
i2c = PPC4xx_I2C(dev)->bus;
/* SPD EEPROM on RAM module */
- spd_data = spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2,
- ram_sizes[0]);
+ spd_data = spd_data_generate(ram_banks->size < 128 * MiB ? DDR : DDR2,
+ ram_banks->size);
spd_data[20] = 4; /* SO-DIMM module */
smbus_eeprom_init_one(i2c, 0x50, spd_data);
/* RTC */
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 13b3229851..a7b41c7eaa 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -40,14 +40,11 @@ typedef struct {
void ppc4xx_sdram_enable(CPUPPCState *env);
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
- MemoryRegion ram_memories[],
- hwaddr ram_bases[], hwaddr ram_sizes[],
+ Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[]);
-void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion ram_memories[],
- hwaddr *ram_bases,
- hwaddr *ram_sizes);
+void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
+ Ppc4xxSdramBank *ram_banks);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 05/21] ppc440_bamboo: Add missing 4 MiB valid memory size
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (3 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 04/21] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 06/21] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() BALATON Zoltan
` (16 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc440_bamboo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index edfb8c9709..7ec7c7c43d 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -51,7 +51,7 @@
#define PPC440EP_SDRAM_NR_BANKS 4
static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
- 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
+ 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
};
static hwaddr entry;
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 06/21] ppc4xx_sdram: Move size check to ppc4xx_sdram_init()
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (4 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 05/21] ppc440_bamboo: Add missing 4 MiB valid memory size BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 07/21] ppc4xx_sdram: QOM'ify BALATON Zoltan
` (15 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/ppc/ppc405.h | 2 --
hw/ppc/ppc405_boards.c | 10 ----------
hw/ppc/ppc405_uc.c | 11 ++---------
hw/ppc/ppc440_bamboo.c | 10 +---------
hw/ppc/ppc4xx_devs.c | 14 ++++++--------
include/hw/ppc/ppc4xx.h | 2 +-
6 files changed, 10 insertions(+), 39 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ca0972b88b..ad54dff542 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -167,9 +167,7 @@ struct Ppc405SoCState {
DeviceState parent_obj;
/* Public */
- Ppc4xxSdramBank ram_banks[2];
MemoryRegion *dram_mr;
- hwaddr ram_size;
PowerPCCPU cpu;
PPCUIC uic;
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 1eaeca8806..824acf7a80 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -271,21 +271,11 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
static void ppc405_init(MachineState *machine)
{
Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
- MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
MemoryRegion *sysmem = get_system_memory();
- if (machine->ram_size != mc->default_ram_size) {
- char *sz = size_to_str(mc->default_ram_size);
- error_report("Invalid RAM size, should be %s", sz);
- g_free(sz);
- exit(EXIT_FAILURE);
- }
-
object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
TYPE_PPC405_SOC);
- object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
- machine->ram_size, &error_fatal);
object_property_set_link(OBJECT(&ppc405->soc), "dram",
OBJECT(machine->ram), &error_abort);
object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index bcbf35bc14..e1c7188e61 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1073,15 +1073,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- /* XXX 405EP has no ECC interrupt */
- s->ram_banks[0].base = 0;
- s->ram_banks[0].size = s->ram_size;
- memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s),
- "ppc405.sdram0", s->dram_mr,
- s->ram_banks[0].base, s->ram_banks[0].size);
-
+ /* XXX 405EP has no ECC interrupt */
ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->ram_banks);
+ s->dram_mr);
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@@ -1159,7 +1153,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
- DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 7ec7c7c43d..91d9a4eef3 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -50,10 +50,6 @@
#define PPC440EP_SDRAM_NR_BANKS 4
-static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
- 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
-};
-
static hwaddr entry;
static int bamboo_load_device_tree(hwaddr addr,
@@ -168,8 +164,6 @@ static void bamboo_init(MachineState *machine)
unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
- Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank,
- PPC440EP_SDRAM_NR_BANKS);
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
@@ -204,11 +198,9 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks,
- ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
- PPC440EP_SDRAM_NR_BANKS, ram_banks);
+ PPC440EP_SDRAM_NR_BANKS, machine->ram);
/* Enable SDRAM memory regions, this should be done by the firmware */
ppc4xx_sdram_enable(env);
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index fcbda57c55..2e0343970f 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -41,7 +41,7 @@
typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
struct ppc4xx_sdram_t {
uint32_t addr;
- int nbanks;
+ int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
Ppc4xxSdramBank bank[4];
uint32_t besr0;
uint32_t besr1;
@@ -348,19 +348,17 @@ static void sdram_reset(void *opaque)
}
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- Ppc4xxSdramBank *ram_banks)
+ MemoryRegion *ram)
{
ppc4xx_sdram_t *sdram;
- int i;
+ const ram_addr_t valid_bank_sizes[] = {
+ 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
+ };
sdram = g_new0(ppc4xx_sdram_t, 1);
sdram->irq = irq;
sdram->nbanks = nbanks;
- for (i = 0; i < nbanks; i++) {
- sdram->bank[i].ram = ram_banks[i].ram;
- sdram->bank[i].base = ram_banks[i].base;
- sdram->bank[i].size = ram_banks[i].size;
- }
+ ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes);
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index a7b41c7eaa..1d41db9b30 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -44,7 +44,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
const ram_addr_t sdram_bank_sizes[]);
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- Ppc4xxSdramBank *ram_banks);
+ MemoryRegion *ram);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 07/21] ppc4xx_sdram: QOM'ify
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (5 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 06/21] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 08/21] ppc4xx_sdram: Drop extra zeros for readability BALATON Zoltan
` (14 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Change the ppc4xx_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly
modelling the DDR SDRAM controller found in the 440EP (used on the
bamboo board) but also backward compatible with the older DDR
controllers on some 405 SoCs so we also use it for those now. This
likely does not cause problems for guests we run as the new features
are just not accessed but to model 405 SoC accurately some features
may have to be disabled or the model split between 440 and older.
Newer SoCs (regardless of their PPC core, e.g. 405EX) may have an
updated DDR2 SDRAM controller implemented by the ppc440_sdram model
(only partially, enough for the 460EX on the sam460ex) that is not yet
QOM'ified in this patch. That is intended to become ppc4xx-sdram-ddr2
when QOM'ified later.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 3 +-
hw/ppc/ppc405_boards.c | 2 +-
hw/ppc/ppc405_uc.c | 22 +++++----
hw/ppc/ppc440_bamboo.c | 12 +++--
hw/ppc/ppc4xx_devs.c | 105 ++++++++++++++++++++++------------------
include/hw/ppc/ppc4xx.h | 31 ++++++++++--
6 files changed, 105 insertions(+), 70 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ad54dff542..9a4312691e 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -167,8 +167,6 @@ struct Ppc405SoCState {
DeviceState parent_obj;
/* Public */
- MemoryRegion *dram_mr;
-
PowerPCCPU cpu;
PPCUIC uic;
Ppc405CpcState cpc;
@@ -182,6 +180,7 @@ struct Ppc405SoCState {
Ppc405PobState pob;
Ppc4xxPlbState plb;
Ppc4xxMalState mal;
+ Ppc4xxSdramDdrState sdram;
};
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 824acf7a80..b59393d4bd 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -337,7 +337,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) {
- ppc4xx_sdram_enable(&ppc405->soc.cpu.env);
+ ppc4xx_sdram_enable(&ppc405->soc.sdram);
boot_from_kernel(machine, &ppc405->soc.cpu);
}
}
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index e1c7188e61..c973cfb04e 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1016,6 +1016,9 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "plb", &s->plb, TYPE_PPC4xx_PLB);
object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
+
+ object_initialize_child(obj, "sdram", &s->sdram, TYPE_PPC4xx_SDRAM_DDR);
+ object_property_add_alias(obj, "dram", OBJECT(&s->sdram), "dram");
}
static void ppc405_reset(void *opaque)
@@ -1073,9 +1076,17 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
+ /*
+ * We use the 440 DDR SDRAM controller which has more regs and features
+ * but it's compatible enough for now
+ */
+ object_property_set_int(OBJECT(&s->sdram), "nbanks", 2, &error_abort);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->sdram), &s->cpu, errp)) {
+ return;
+ }
/* XXX 405EP has no ECC interrupt */
- ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->dram_mr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdram), 0,
+ qdev_get_gpio_in(DEVICE(&s->uic), 17));
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@@ -1150,12 +1161,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* Uses UIC IRQs 9, 15, 17 */
}
-static Property ppc405_soc_properties[] = {
- DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
- MemoryRegion *),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void ppc405_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -1163,7 +1168,6 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
dc->realize = ppc405_soc_realize;
/* Reason: only works as part of a ppc405 board/machine */
dc->user_creatable = false;
- device_class_set_props(dc, ppc405_soc_properties);
}
static const TypeInfo ppc405_types[] = {
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 91d9a4eef3..5c35ba6086 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -48,8 +48,6 @@
#define PPC440EP_PCI_IO 0xe8000000
#define PPC440EP_PCI_IOLEN 0x00010000
-#define PPC440EP_SDRAM_NR_BANKS 4
-
static hwaddr entry;
static int bamboo_load_device_tree(hwaddr addr,
@@ -198,11 +196,15 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
+ dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR);
+ object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
+ &error_abort);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
- ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
- PPC440EP_SDRAM_NR_BANKS, machine->ram);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(uicdev, 14));
/* Enable SDRAM memory regions, this should be done by the firmware */
- ppc4xx_sdram_enable(env);
+ ppc4xx_sdram_enable(PPC4xx_SDRAM_DDR(dev));
/* PCI */
dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 2e0343970f..3d700e5c85 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -38,24 +38,6 @@
/*****************************************************************************/
/* SDRAM controller */
-typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
-struct ppc4xx_sdram_t {
- uint32_t addr;
- int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
- Ppc4xxSdramBank bank[4];
- uint32_t besr0;
- uint32_t besr1;
- uint32_t bear;
- uint32_t cfg;
- uint32_t status;
- uint32_t rtr;
- uint32_t pmit;
- uint32_t tr;
- uint32_t ecccfg;
- uint32_t eccesr;
- qemu_irq irq;
-};
-
enum {
SDRAM0_CFGADDR = 0x010,
SDRAM0_CFGDATA = 0x011,
@@ -66,7 +48,7 @@ enum {
* there are type inconsistencies, mixing hwaddr, target_ulong
* and uint32_t
*/
-static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
+static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -124,7 +106,7 @@ static target_ulong sdram_size(uint32_t bcr)
return size;
}
-static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
+static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 0x00000001) {
@@ -150,21 +132,21 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
}
}
-static void sdram_map_bcr(ppc4xx_sdram_t *sdram)
+static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size != 0) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
+ sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
sdram_set_bcr(sdram, i, 0x00000000, 0);
}
}
}
-static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram)
+static void sdram_unmap_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
@@ -176,12 +158,11 @@ static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram)
}
}
-static uint32_t dcr_read_sdram(void *opaque, int dcrn)
+static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
{
- ppc4xx_sdram_t *sdram;
+ Ppc4xxSdramDdrState *sdram = opaque;
uint32_t ret;
- sdram = opaque;
switch (dcrn) {
case SDRAM0_CFGADDR:
ret = sdram->addr;
@@ -244,11 +225,10 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
return ret;
}
-static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
+static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_sdram_t *sdram;
+ Ppc4xxSdramDdrState *sdram = opaque;
- sdram = opaque;
switch (dcrn) {
case SDRAM0_CFGADDR:
sdram->addr = val;
@@ -327,11 +307,10 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
}
}
-static void sdram_reset(void *opaque)
+static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
{
- ppc4xx_sdram_t *sdram;
+ Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
- sdram = opaque;
sdram->addr = 0x00000000;
sdram->bear = 0x00000000;
sdram->besr0 = 0x00000000; /* No error */
@@ -347,29 +326,54 @@ static void sdram_reset(void *opaque)
sdram->cfg = 0x00800000;
}
-void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion *ram)
+static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_sdram_t *sdram;
+ Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
const ram_addr_t valid_bank_sizes[] = {
256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
};
- sdram = g_new0(ppc4xx_sdram_t, 1);
- sdram->irq = irq;
- sdram->nbanks = nbanks;
- ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes);
- qemu_register_reset(&sdram_reset, sdram);
- ppc_dcr_register(env, SDRAM0_CFGADDR,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
- ppc_dcr_register(env, SDRAM0_CFGDATA,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ if (s->nbanks < 1 || s->nbanks > 4) {
+ error_setg(errp, "Invalid number of RAM banks");
+ return;
+ }
+ if (!s->dram_mr) {
+ error_setg(errp, "Missing dram memory region");
+ return;
+ }
+ ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
+
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
+ s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
+ s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
}
-void ppc4xx_sdram_enable(CPUPPCState *env)
+static Property ppc4xx_sdram_ddr_props[] = {
+ DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_sdram_ddr_realize;
+ dc->reset = ppc4xx_sdram_ddr_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_sdram_ddr_props);
+}
+
+void ppc4xx_sdram_enable(Ppc4xxSdramDdrState *s)
{
- ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20);
- ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000);
+ sdram_ddr_dcr_write(s, SDRAM0_CFGADDR, 0x20);
+ sdram_ddr_dcr_write(s, SDRAM0_CFGDATA, 0x80000000);
}
/*
@@ -959,6 +963,11 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc4xx_types[] = {
{
+ .name = TYPE_PPC4xx_SDRAM_DDR,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxSdramDdrState),
+ .class_init = ppc4xx_sdram_ddr_class_init,
+ }, {
.name = TYPE_PPC4xx_MAL,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc4xxMalState),
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 1d41db9b30..558500fb97 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -37,15 +37,10 @@ typedef struct {
uint32_t bcr;
} Ppc4xxSdramBank;
-void ppc4xx_sdram_enable(CPUPPCState *env);
-
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[]);
-void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion *ram);
-
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
/*
@@ -115,4 +110,30 @@ struct Ppc4xxEbcState {
uint32_t cfg;
};
+/* SDRAM DDR controller */
+#define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR);
+struct Ppc4xxSdramDdrState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ MemoryRegion *dram_mr;
+ uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
+ Ppc4xxSdramBank bank[4];
+ qemu_irq irq;
+
+ uint32_t addr;
+ uint32_t besr0;
+ uint32_t besr1;
+ uint32_t bear;
+ uint32_t cfg;
+ uint32_t status;
+ uint32_t rtr;
+ uint32_t pmit;
+ uint32_t tr;
+ uint32_t ecccfg;
+ uint32_t eccesr;
+};
+
+void ppc4xx_sdram_enable(Ppc4xxSdramDdrState *s);
+
#endif /* PPC4XX_H */
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 08/21] ppc4xx_sdram: Drop extra zeros for readability
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (6 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 07/21] ppc4xx_sdram: QOM'ify BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 09/21] ppc440_sdram: Split off map/unmap of sdram banks for later reuse BALATON Zoltan
` (13 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Constants that are written zero padded for no good reason are hard to
read, it's easier to see what is meant if it's just 0 or 1 instead.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/ppc/ppc4xx_devs.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 3d700e5c85..02ac8ff335 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -54,31 +54,31 @@ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
switch (ram_size) {
case 4 * MiB:
- bcr = 0x00000000;
+ bcr = 0;
break;
case 8 * MiB:
- bcr = 0x00020000;
+ bcr = 0x20000;
break;
case 16 * MiB:
- bcr = 0x00040000;
+ bcr = 0x40000;
break;
case 32 * MiB:
- bcr = 0x00060000;
+ bcr = 0x60000;
break;
case 64 * MiB:
- bcr = 0x00080000;
+ bcr = 0x80000;
break;
case 128 * MiB:
- bcr = 0x000A0000;
+ bcr = 0xA0000;
break;
case 256 * MiB:
- bcr = 0x000C0000;
+ bcr = 0xC0000;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
ram_size);
- return 0x00000000;
+ return 0;
}
bcr |= ram_base & 0xFF800000;
bcr |= 1;
@@ -109,7 +109,7 @@ static target_ulong sdram_size(uint32_t bcr)
static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
uint32_t bcr, int enabled)
{
- if (sdram->bank[i].bcr & 0x00000001) {
+ if (sdram->bank[i].bcr & 1) {
/* Unmap RAM */
trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
sdram_size(sdram->bank[i].bcr));
@@ -120,7 +120,7 @@ static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
object_unparent(OBJECT(&sdram->bank[i].container));
}
sdram->bank[i].bcr = bcr & 0xFFDEE001;
- if (enabled && (bcr & 0x00000001)) {
+ if (enabled && (bcr & 1)) {
trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
sdram_size(bcr));
@@ -141,7 +141,7 @@ static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
- sdram_set_bcr(sdram, i, 0x00000000, 0);
+ sdram_set_bcr(sdram, i, 0, 0);
}
}
}
@@ -218,7 +218,7 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
break;
default:
/* Avoid gcc warning */
- ret = 0x00000000;
+ ret = 0;
break;
}
@@ -311,18 +311,18 @@ static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
{
Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
- sdram->addr = 0x00000000;
- sdram->bear = 0x00000000;
- sdram->besr0 = 0x00000000; /* No error */
- sdram->besr1 = 0x00000000; /* No error */
- sdram->cfg = 0x00000000;
- sdram->ecccfg = 0x00000000; /* No ECC */
- sdram->eccesr = 0x00000000; /* No error */
+ sdram->addr = 0;
+ sdram->bear = 0;
+ sdram->besr0 = 0; /* No error */
+ sdram->besr1 = 0; /* No error */
+ sdram->cfg = 0;
+ sdram->ecccfg = 0; /* No ECC */
+ sdram->eccesr = 0; /* No error */
sdram->pmit = 0x07C00000;
sdram->rtr = 0x05F00000;
sdram->tr = 0x00854009;
/* We pre-initialize RAM banks */
- sdram->status = 0x00000000;
+ sdram->status = 0;
sdram->cfg = 0x00800000;
}
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 09/21] ppc440_sdram: Split off map/unmap of sdram banks for later reuse
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (7 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 08/21] ppc4xx_sdram: Drop extra zeros for readability BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:35 ` Philippe Mathieu-Daudé via
2022-09-18 20:24 ` [PATCH v5 10/21] ppc440_sdram: Implement enable bit in the DDR2 SDRAM BALATON Zoltan
` (12 subsequent siblings)
21 siblings, 1 reply; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc440_uc.c | 33 +++++++++++++++++++++------------
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 8eae4ad9f0..900b7ab998 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -23,6 +23,7 @@
#include "sysemu/reset.h"
#include "ppc440.h"
#include "qom/object.h"
+#include "trace.h"
/*****************************************************************************/
/* L2 Cache as SRAM */
@@ -563,26 +564,34 @@ static uint64_t sdram_size(uint32_t bcr)
return size;
}
+static void sdram_bank_map(Ppc4xxSdramBank *bank)
+{
+ memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
+ memory_region_add_subregion(&bank->container, 0, &bank->ram);
+ memory_region_add_subregion(get_system_memory(), bank->base,
+ &bank->container);
+}
+
+static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
+{
+ memory_region_del_subregion(get_system_memory(), &bank->container);
+ memory_region_del_subregion(&bank->container, &bank->ram);
+ object_unparent(OBJECT(&bank->container));
+}
+
static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
- memory_region_del_subregion(get_system_memory(),
- &sdram->bank[i].container);
- memory_region_del_subregion(&sdram->bank[i].container,
- &sdram->bank[i].ram);
- object_unparent(OBJECT(&sdram->bank[i].container));
+ trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
+ sdram_size(sdram->bank[i].bcr));
+ sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
if (enabled && (bcr & 1)) {
- memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
- sdram_size(bcr));
- memory_region_add_subregion(&sdram->bank[i].container, 0,
- &sdram->bank[i].ram);
- memory_region_add_subregion(get_system_memory(),
- sdram_base(bcr),
- &sdram->bank[i].container);
+ trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
+ sdram_bank_map(&sdram->bank[i]);
}
}
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 10/21] ppc440_sdram: Implement enable bit in the DDR2 SDRAM
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (8 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 09/21] ppc440_sdram: Split off map/unmap of sdram banks for later reuse BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 11/21] ppc440_sdram: Get rid of the init RAM hack BALATON Zoltan
` (11 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
To allow removing the do_init hack we need to improve the DDR2 SDRAM
controller model to handle the enable/disable bit that it ignored so
far.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc440_uc.c | 34 ++++++++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 900b7ab998..3fbfe4ad13 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -485,6 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
/* SDRAM controller */
typedef struct ppc440_sdram_t {
uint32_t addr;
+ uint32_t mcopt2;
int nbanks;
Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
@@ -600,7 +601,7 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size != 0) {
+ if (sdram->bank[i].size) {
sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
@@ -609,6 +610,17 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
}
}
+static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
+{
+ int i;
+
+ for (i = 0; i < sdram->nbanks; i++) {
+ if (sdram->bank[i].size) {
+ sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+ }
+ }
+}
+
static uint32_t dcr_read_sdram(void *opaque, int dcrn)
{
ppc440_sdram_t *sdram = opaque;
@@ -640,7 +652,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
ret = 0x80000000;
break;
case 0x21: /* SDRAM_MCOPT2 */
- ret = 0x08000000;
+ ret = sdram->mcopt2;
break;
case 0x40: /* SDRAM_MB0CF */
ret = 0x00008001;
@@ -662,6 +674,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
return ret;
}
+#define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
+
static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
{
ppc440_sdram_t *sdram = opaque;
@@ -684,6 +698,21 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
switch (sdram->addr) {
case 0x00: /* B0CR */
break;
+ case 0x21: /* SDRAM_MCOPT2 */
+ if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
+ (val & SDRAM_DDR2_MCOPT2_DCEN)) {
+ trace_ppc4xx_sdram_enable("enable");
+ /* validate all RAM mappings */
+ sdram_map_bcr(sdram);
+ sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
+ } else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
+ !(val & SDRAM_DDR2_MCOPT2_DCEN)) {
+ trace_ppc4xx_sdram_enable("disable");
+ /* invalidate all RAM mappings */
+ sdram_unmap_bcr(sdram);
+ sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
+ }
+ break;
default:
break;
}
@@ -698,6 +727,7 @@ static void sdram_reset(void *opaque)
ppc440_sdram_t *sdram = opaque;
sdram->addr = 0;
+ sdram->mcopt2 = SDRAM_DDR2_MCOPT2_DCEN;
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 11/21] ppc440_sdram: Get rid of the init RAM hack
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (9 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 10/21] ppc440_sdram: Implement enable bit in the DDR2 SDRAM BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 12/21] ppc440_sdram: Rename local variable for readability BALATON Zoltan
` (10 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Remove the do_init parameter of ppc440_sdram_init and enable SDRAM
controller from the board. Firmware does this so it may only be needed
when booting with -kernel without firmware but we enable SDRAM
unconditionally to preserve previous behaviour.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
v5: Add function to enable sdram controller
hw/ppc/ppc440.h | 3 +--
hw/ppc/ppc440_uc.c | 15 +++++++++------
hw/ppc/sam460ex.c | 4 +++-
include/hw/ppc/ppc4xx.h | 2 ++
4 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index e6c905b7d6..01d76b8000 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -17,8 +17,7 @@ void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks,
- int do_init);
+ Ppc4xxSdramBank *ram_banks);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 3fbfe4ad13..e8bc088c8f 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -16,6 +16,7 @@
#include "qemu/module.h"
#include "hw/irq.h"
#include "exec/memory.h"
+#include "cpu.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/qdev-properties.h"
#include "hw/pci/pci.h"
@@ -727,12 +728,11 @@ static void sdram_reset(void *opaque)
ppc440_sdram_t *sdram = opaque;
sdram->addr = 0;
- sdram->mcopt2 = SDRAM_DDR2_MCOPT2_DCEN;
+ sdram->mcopt2 = 0;
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks,
- int do_init)
+ Ppc4xxSdramBank *ram_banks)
{
ppc440_sdram_t *sdram;
int i;
@@ -749,9 +749,6 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
sdram, &dcr_read_sdram, &dcr_write_sdram);
- if (do_init) {
- sdram_map_bcr(sdram);
- }
ppc_dcr_register(env, SDRAM_R0BAS,
sdram, &dcr_read_sdram, &dcr_write_sdram);
@@ -773,6 +770,12 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
sdram, &dcr_read_sdram, &dcr_write_sdram);
}
+void ppc440_sdram_enable(CPUPPCState *env)
+{
+ ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21);
+ ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000);
+}
+
/*****************************************************************************/
/* PLB to AHB bridge */
enum {
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index f4c2a693fb..9c01211b20 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -345,7 +345,9 @@ static void sam460ex_init(MachineState *machine)
ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes);
/* FIXME: does 460EX have ECC interrupts? */
- ppc440_sdram_init(env, 1, ram_banks, 1);
+ ppc440_sdram_init(env, 1, ram_banks);
+ /* Enable SDRAM memory regions as we may boot without firmware */
+ ppc440_sdram_enable(env);
/* IIC controllers and devices */
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 558500fb97..78a845399e 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -37,6 +37,8 @@ typedef struct {
uint32_t bcr;
} Ppc4xxSdramBank;
+void ppc440_sdram_enable(CPUPPCState *env);
+
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[]);
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 12/21] ppc440_sdram: Rename local variable for readability
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (10 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 11/21] ppc440_sdram: Get rid of the init RAM hack BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 13/21] ppc4xx_sdram: Rename functions to prevent name clashes BALATON Zoltan
` (9 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Rename local sdram variable in ppc440_sdram_init to s for readability.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc440_uc.c | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index e8bc088c8f..97e6d5f5b2 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -734,40 +734,40 @@ static void sdram_reset(void *opaque)
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
Ppc4xxSdramBank *ram_banks)
{
- ppc440_sdram_t *sdram;
+ ppc440_sdram_t *s;
int i;
- sdram = g_malloc0(sizeof(*sdram));
- sdram->nbanks = nbanks;
+ s = g_malloc0(sizeof(*s));
+ s->nbanks = nbanks;
for (i = 0; i < nbanks; i++) {
- sdram->bank[i].ram = ram_banks[i].ram;
- sdram->bank[i].base = ram_banks[i].base;
- sdram->bank[i].size = ram_banks[i].size;
+ s->bank[i].ram = ram_banks[i].ram;
+ s->bank[i].base = ram_banks[i].base;
+ s->bank[i].size = ram_banks[i].size;
}
- qemu_register_reset(&sdram_reset, sdram);
+ qemu_register_reset(&sdram_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R0BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R1BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R2BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R3BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_CONF1HB,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_PLBADDULL,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_CONF1LL,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_CONFPATHB,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_PLBADDUHB,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
}
void ppc440_sdram_enable(CPUPPCState *env)
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 13/21] ppc4xx_sdram: Rename functions to prevent name clashes
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (11 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 12/21] ppc440_sdram: Rename local variable for readability BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 14/21] ppc440_sdram: Move RAM size check to ppc440_sdram_init BALATON Zoltan
` (8 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Rename functions to avoid name clashes when moving the DDR2 controller
model currently called ppc440_sdram to ppc4xx_devs. This also more
clearly shows which function belongs to which model.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/ppc/ppc405_boards.c | 2 +-
hw/ppc/ppc440_bamboo.c | 2 +-
hw/ppc/ppc440_uc.c | 67 +++++++++++++++++++++--------------------
hw/ppc/ppc4xx_devs.c | 46 ++++++++++++++--------------
hw/ppc/sam460ex.c | 2 +-
include/hw/ppc/ppc4xx.h | 4 +--
6 files changed, 62 insertions(+), 61 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index b59393d4bd..4092ebc1ab 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -337,7 +337,7 @@ static void ppc405_init(MachineState *machine)
/* Load ELF kernel and rootfs.cpio */
} else if (kernel_filename && !machine->firmware) {
- ppc4xx_sdram_enable(&ppc405->soc.sdram);
+ ppc4xx_sdram_ddr_enable(&ppc405->soc.sdram);
boot_from_kernel(machine, &ppc405->soc.cpu);
}
}
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 5c35ba6086..56f47e7509 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -204,7 +204,7 @@ static void bamboo_init(MachineState *machine)
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(uicdev, 14));
/* Enable SDRAM memory regions, this should be done by the firmware */
- ppc4xx_sdram_enable(PPC4xx_SDRAM_DDR(dev));
+ ppc4xx_sdram_ddr_enable(PPC4xx_SDRAM_DDR(dev));
/* PCI */
dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 97e6d5f5b2..edd0781eb7 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -505,7 +505,7 @@ enum {
SDRAM_PLBADDUHB = 0x50,
};
-static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
+static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -550,12 +550,12 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
return bcr;
}
-static inline hwaddr sdram_base(uint32_t bcr)
+static inline hwaddr sdram_ddr2_base(uint32_t bcr)
{
return (bcr & 0xffe00000) << 2;
}
-static uint64_t sdram_size(uint32_t bcr)
+static uint64_t sdram_ddr2_size(uint32_t bcr)
{
uint64_t size;
int sh;
@@ -581,48 +581,49 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
object_unparent(OBJECT(&bank->container));
}
-static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
- uint32_t bcr, int enabled)
+static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
+ uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+ trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
+ sdram_ddr2_size(sdram->bank[i].bcr));
sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
+ trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
sdram_bank_map(&sdram->bank[i]);
}
}
-static void sdram_map_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
+ sdram_ddr2_set_bcr(sdram, i,
+ sdram_ddr2_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
- sdram_set_bcr(sdram, i, 0, 0);
+ sdram_ddr2_set_bcr(sdram, i, 0, 0);
}
}
}
-static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size) {
- sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+ sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
}
}
}
-static uint32_t dcr_read_sdram(void *opaque, int dcrn)
+static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
ppc440_sdram_t *sdram = opaque;
uint32_t ret = 0;
@@ -633,8 +634,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
case SDRAM_R2BAS:
case SDRAM_R3BAS:
if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
- ret = sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
- sdram->bank[dcrn - SDRAM_R0BAS].size);
+ ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
+ sdram->bank[dcrn - SDRAM_R0BAS].size);
}
break;
case SDRAM_CONF1HB:
@@ -677,7 +678,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
#define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
-static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
+static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
ppc440_sdram_t *sdram = opaque;
@@ -704,13 +705,13 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
(val & SDRAM_DDR2_MCOPT2_DCEN)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_map_bcr(sdram);
+ sdram_ddr2_map_bcr(sdram);
sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
} else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
!(val & SDRAM_DDR2_MCOPT2_DCEN)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_unmap_bcr(sdram);
+ sdram_ddr2_unmap_bcr(sdram);
sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
}
break;
@@ -723,7 +724,7 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
}
}
-static void sdram_reset(void *opaque)
+static void sdram_ddr2_reset(void *opaque)
{
ppc440_sdram_t *sdram = opaque;
@@ -744,33 +745,33 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
s->bank[i].base = ram_banks[i].base;
s->bank[i].size = ram_banks[i].size;
}
- qemu_register_reset(&sdram_reset, s);
+ qemu_register_reset(&sdram_ddr2_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM0_CFGDATA,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R0BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R1BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R2BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R3BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_CONF1HB,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_PLBADDULL,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_CONF1LL,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_CONFPATHB,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_PLBADDUHB,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
}
-void ppc440_sdram_enable(CPUPPCState *env)
+void ppc4xx_sdram_ddr2_enable(CPUPPCState *env)
{
ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21);
ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000);
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 02ac8ff335..12af90f244 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -86,12 +86,12 @@ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
return bcr;
}
-static inline hwaddr sdram_base(uint32_t bcr)
+static inline hwaddr sdram_ddr_base(uint32_t bcr)
{
return bcr & 0xFF800000;
}
-static target_ulong sdram_size(uint32_t bcr)
+static target_ulong sdram_ddr_size(uint32_t bcr)
{
target_ulong size;
int sh;
@@ -106,13 +106,13 @@ static target_ulong sdram_size(uint32_t bcr)
return size;
}
-static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
- uint32_t bcr, int enabled)
+static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
+ uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* Unmap RAM */
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+ trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
+ sdram_ddr_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
&sdram->bank[i].container);
memory_region_del_subregion(&sdram->bank[i].container,
@@ -121,38 +121,38 @@ static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
}
sdram->bank[i].bcr = bcr & 0xFFDEE001;
if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
+ trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr));
memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
- sdram_size(bcr));
+ sdram_ddr_size(bcr));
memory_region_add_subregion(&sdram->bank[i].container, 0,
&sdram->bank[i].ram);
memory_region_add_subregion(get_system_memory(),
- sdram_base(bcr),
+ sdram_ddr_base(bcr),
&sdram->bank[i].container);
}
}
-static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
+static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size != 0) {
- sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
+ sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
- sdram_set_bcr(sdram, i, 0, 0);
+ sdram_ddr_set_bcr(sdram, i, 0, 0);
}
}
}
-static void sdram_unmap_bcr(Ppc4xxSdramDdrState *sdram)
+static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+ trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
+ sdram_ddr_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
&sdram->bank[i].ram);
}
@@ -249,12 +249,12 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_map_bcr(sdram);
+ sdram_ddr_map_bcr(sdram);
sdram->status &= ~0x80000000;
} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_unmap_bcr(sdram);
+ sdram_ddr_unmap_bcr(sdram);
sdram->status |= 0x80000000;
}
if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) {
@@ -274,16 +274,16 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
sdram->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
- sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
break;
case 0x44: /* SDRAM_B1CR */
- sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
break;
case 0x48: /* SDRAM_B2CR */
- sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
break;
case 0x4C: /* SDRAM_B3CR */
- sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
break;
case 0x80: /* SDRAM_TR */
sdram->tr = val & 0x018FC01F;
@@ -370,7 +370,7 @@ static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
device_class_set_props(dc, ppc4xx_sdram_ddr_props);
}
-void ppc4xx_sdram_enable(Ppc4xxSdramDdrState *s)
+void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s)
{
sdram_ddr_dcr_write(s, SDRAM0_CFGADDR, 0x20);
sdram_ddr_dcr_write(s, SDRAM0_CFGDATA, 0x80000000);
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 9c01211b20..b318521b01 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -347,7 +347,7 @@ static void sam460ex_init(MachineState *machine)
/* FIXME: does 460EX have ECC interrupts? */
ppc440_sdram_init(env, 1, ram_banks);
/* Enable SDRAM memory regions as we may boot without firmware */
- ppc440_sdram_enable(env);
+ ppc4xx_sdram_ddr2_enable(env);
/* IIC controllers and devices */
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 78a845399e..fd0b3ca82a 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -37,7 +37,7 @@ typedef struct {
uint32_t bcr;
} Ppc4xxSdramBank;
-void ppc440_sdram_enable(CPUPPCState *env);
+void ppc4xx_sdram_ddr2_enable(CPUPPCState *env);
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
Ppc4xxSdramBank ram_banks[],
@@ -136,6 +136,6 @@ struct Ppc4xxSdramDdrState {
uint32_t eccesr;
};
-void ppc4xx_sdram_enable(Ppc4xxSdramDdrState *s);
+void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s);
#endif /* PPC4XX_H */
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 14/21] ppc440_sdram: Move RAM size check to ppc440_sdram_init
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (12 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 13/21] ppc4xx_sdram: Rename functions to prevent name clashes BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 15/21] ppc440_sdram: QOM'ify BALATON Zoltan
` (7 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Move the check for valid memory sizes from board to sdram controller
init. This adds the missing valid memory sizes of 4 GiB, 16 and 8 MiB
to the DoC and the board now only checks for additional restrictions
imposed by its firmware then sdram init checks for valid sizes for SoC.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc440.h | 4 ++--
hw/ppc/ppc440_uc.c | 15 +++++++--------
hw/ppc/sam460ex.c | 32 +++++++++++++++++---------------
3 files changed, 26 insertions(+), 25 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 01d76b8000..29f6f14ed7 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -11,13 +11,13 @@
#ifndef PPC440_H
#define PPC440_H
-#include "hw/ppc/ppc4xx.h"
+#include "hw/ppc/ppc.h"
void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks);
+ MemoryRegion *ram);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index edd0781eb7..2b9d666b71 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -487,7 +487,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
typedef struct ppc440_sdram_t {
uint32_t addr;
uint32_t mcopt2;
- int nbanks;
+ int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
@@ -733,18 +733,17 @@ static void sdram_ddr2_reset(void *opaque)
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks)
+ MemoryRegion *ram)
{
ppc440_sdram_t *s;
- int i;
+ const ram_addr_t valid_bank_sizes[] = {
+ 4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
+ 32 * MiB, 16 * MiB, 8 * MiB, 0
+ };
s = g_malloc0(sizeof(*s));
s->nbanks = nbanks;
- for (i = 0; i < nbanks; i++) {
- s->bank[i].ram = ram_banks[i].ram;
- s->bank[i].base = ram_banks[i].base;
- s->bank[i].size = ram_banks[i].size;
- }
+ ppc4xx_sdram_banks(ram, s->nbanks, s->bank, valid_bank_sizes);
qemu_register_reset(&sdram_ddr2_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index b318521b01..13055a8916 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -74,13 +74,6 @@
#define EBC_FREQ 115000000
#define UART_FREQ 11059200
-/* The SoC could also handle 4 GiB but firmware does not work with that. */
-/* Maybe it overflows a signed 32 bit number somewhere? */
-static const ram_addr_t ppc460ex_sdram_bank_sizes[] = {
- 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
- 32 * MiB, 0
-};
-
struct boot_info {
uint32_t dt_base;
uint32_t dt_size;
@@ -273,7 +266,6 @@ static void sam460ex_init(MachineState *machine)
{
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
- Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank, 1);
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
DeviceState *uic[4];
int i;
@@ -340,12 +332,22 @@ static void sam460ex_init(MachineState *machine)
}
/* SDRAM controller */
- /* put all RAM on first bank because board has one slot
- * and firmware only checks that */
- ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes);
-
+ /* The SoC could also handle 4 GiB but firmware does not work with that. */
+ if (machine->ram_size > 2 * GiB) {
+ error_report("Memory over 2 GiB is not supported");
+ exit(1);
+ }
+ /* Firmware needs at least 64 MiB */
+ if (machine->ram_size < 64 * MiB) {
+ error_report("Memory below 64 MiB is not supported");
+ exit(1);
+ }
+ /*
+ * Put all RAM on first bank because board has one slot
+ * and firmware only checks that
+ */
+ ppc440_sdram_init(env, 1, machine->ram);
/* FIXME: does 460EX have ECC interrupts? */
- ppc440_sdram_init(env, 1, ram_banks);
/* Enable SDRAM memory regions as we may boot without firmware */
ppc4xx_sdram_ddr2_enable(env);
@@ -354,8 +356,8 @@ static void sam460ex_init(MachineState *machine)
qdev_get_gpio_in(uic[0], 2));
i2c = PPC4xx_I2C(dev)->bus;
/* SPD EEPROM on RAM module */
- spd_data = spd_data_generate(ram_banks->size < 128 * MiB ? DDR : DDR2,
- ram_banks->size);
+ spd_data = spd_data_generate(machine->ram_size < 128 * MiB ? DDR : DDR2,
+ machine->ram_size);
spd_data[20] = 4; /* SO-DIMM module */
smbus_eeprom_init_one(i2c, 0x50, spd_data);
/* RTC */
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 15/21] ppc440_sdram: QOM'ify
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (13 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 14/21] ppc440_sdram: Move RAM size check to ppc440_sdram_init BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together BALATON Zoltan
` (6 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Change the ppc440_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly
modelling the DDR2 SDRAM controller found in the 460EX (used on the
sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX)
may have this controller but we only emulate enough of it for the
sam460ex u-boot firmware.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc440.h | 2 -
hw/ppc/ppc440_uc.c | 121 ++++++++++++++++++++++++----------------
hw/ppc/sam460ex.c | 9 ++-
include/hw/ppc/ppc4xx.h | 18 +++++-
4 files changed, 97 insertions(+), 53 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 29f6f14ed7..7c24db8504 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -16,8 +16,6 @@
void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
-void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 2b9d666b71..46daecab19 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -484,13 +484,6 @@ void ppc4xx_sdr_init(CPUPPCState *env)
/*****************************************************************************/
/* SDRAM controller */
-typedef struct ppc440_sdram_t {
- uint32_t addr;
- uint32_t mcopt2;
- int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
- Ppc4xxSdramBank bank[4];
-} ppc440_sdram_t;
-
enum {
SDRAM0_CFGADDR = 0x10,
SDRAM0_CFGDATA,
@@ -581,7 +574,7 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
object_unparent(OBJECT(&bank->container));
}
-static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
+static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
@@ -597,7 +590,7 @@ static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
}
}
-static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram)
{
int i;
@@ -612,7 +605,7 @@ static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
}
}
-static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
{
int i;
@@ -625,7 +618,7 @@ static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
- ppc440_sdram_t *sdram = opaque;
+ Ppc4xxSdramDdr2State *sdram = opaque;
uint32_t ret = 0;
switch (dcrn) {
@@ -680,7 +673,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
- ppc440_sdram_t *sdram = opaque;
+ Ppc4xxSdramDdr2State *sdram = opaque;
switch (dcrn) {
case SDRAM_R0BAS:
@@ -724,58 +717,92 @@ static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
}
}
-static void sdram_ddr2_reset(void *opaque)
+static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
{
- ppc440_sdram_t *sdram = opaque;
+ Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev);
sdram->addr = 0;
sdram->mcopt2 = 0;
}
-void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram)
+static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
{
- ppc440_sdram_t *s;
+ Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
const ram_addr_t valid_bank_sizes[] = {
4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
32 * MiB, 16 * MiB, 8 * MiB, 0
};
- s = g_malloc0(sizeof(*s));
- s->nbanks = nbanks;
- ppc4xx_sdram_banks(ram, s->nbanks, s->bank, valid_bank_sizes);
- qemu_register_reset(&sdram_ddr2_reset, s);
- ppc_dcr_register(env, SDRAM0_CFGADDR,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM0_CFGDATA,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-
- ppc_dcr_register(env, SDRAM_R0BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_R1BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_R2BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_R3BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_CONF1HB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_PLBADDULL,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_CONF1LL,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_CONFPATHB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_PLBADDUHB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ if (s->nbanks < 1 || s->nbanks > 4) {
+ error_setg(errp, "Invalid number of RAM banks");
+ return;
+ }
+ if (!s->dram_mr) {
+ error_setg(errp, "Missing dram memory region");
+ return;
+ }
+ ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+
+ ppc4xx_dcr_register(dcr, SDRAM_R0BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R1BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R2BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R3BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONF1HB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONF1LL,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+}
+
+static Property ppc4xx_sdram_ddr2_props[] = {
+ DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_sdram_ddr2_realize;
+ dc->reset = ppc4xx_sdram_ddr2_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_sdram_ddr2_props);
}
-void ppc4xx_sdram_ddr2_enable(CPUPPCState *env)
+void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s)
{
- ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21);
- ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000);
+ sdram_ddr2_dcr_write(s, SDRAM0_CFGADDR, 0x21);
+ sdram_ddr2_dcr_write(s, SDRAM0_CFGDATA, 0x08000000);
}
+static const TypeInfo ppc4xx_types[] = {
+ {
+ .name = TYPE_PPC4xx_SDRAM_DDR2,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxSdramDdr2State),
+ .class_init = ppc4xx_sdram_ddr2_class_init,
+ }
+};
+DEFINE_TYPES(ppc4xx_types)
+
/*****************************************************************************/
/* PLB to AHB bridge */
enum {
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 13055a8916..f03cdc9ecc 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -342,14 +342,19 @@ static void sam460ex_init(MachineState *machine)
error_report("Memory below 64 MiB is not supported");
exit(1);
}
+ dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2);
+ object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
+ &error_abort);
/*
* Put all RAM on first bank because board has one slot
* and firmware only checks that
*/
- ppc440_sdram_init(env, 1, machine->ram);
+ object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* FIXME: does 460EX have ECC interrupts? */
/* Enable SDRAM memory regions as we may boot without firmware */
- ppc4xx_sdram_ddr2_enable(env);
+ ppc4xx_sdram_ddr2_enable(PPC4xx_SDRAM_DDR2(dev));
/* IIC controllers and devices */
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index fd0b3ca82a..ff88385ac0 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -37,8 +37,6 @@ typedef struct {
uint32_t bcr;
} Ppc4xxSdramBank;
-void ppc4xx_sdram_ddr2_enable(CPUPPCState *env);
-
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[]);
@@ -138,4 +136,20 @@ struct Ppc4xxSdramDdrState {
void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s);
+/* SDRAM DDR2 controller */
+#define TYPE_PPC4xx_SDRAM_DDR2 "ppc4xx-sdram-ddr2"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdr2State, PPC4xx_SDRAM_DDR2);
+struct Ppc4xxSdramDdr2State {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ MemoryRegion *dram_mr;
+ uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
+ Ppc4xxSdramBank bank[4];
+
+ uint32_t addr;
+ uint32_t mcopt2;
+};
+
+void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s);
+
#endif /* PPC4XX_H */
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (14 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 15/21] ppc440_sdram: QOM'ify BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 21:02 ` Philippe Mathieu-Daudé via
2022-09-18 20:24 ` [PATCH v5 17/21] ppc4xx_sdram: Use hwaddr for memory bank size BALATON Zoltan
` (5 subsequent siblings)
21 siblings, 1 reply; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Move the PPC4xx DDR and DDR2 SDRAM contrller models into a new file
called ppc4xx_sdram to separate from other device models and put them
in one place allowing sharing some code between them.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/meson.build | 3 +-
hw/ppc/ppc440_uc.c | 332 -----------------
hw/ppc/ppc4xx_devs.c | 414 ---------------------
hw/ppc/ppc4xx_sdram.c | 771 ++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/ppc4xx.h | 24 +-
5 files changed, 785 insertions(+), 759 deletions(-)
create mode 100644 hw/ppc/ppc4xx_sdram.c
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index 62801923f3..74720dd1e1 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -59,8 +59,9 @@ ppc_ss.add(when: 'CONFIG_PPC440', if_true: files(
'ppc440_bamboo.c',
'ppc440_pcix.c', 'ppc440_uc.c'))
ppc_ss.add(when: 'CONFIG_PPC4XX', if_true: files(
+ 'ppc4xx_devs.c',
'ppc4xx_pci.c',
- 'ppc4xx_devs.c'))
+ 'ppc4xx_sdram.c'))
ppc_ss.add(when: 'CONFIG_SAM460EX', if_true: files('sam460ex.c'))
# PReP
ppc_ss.add(when: 'CONFIG_PREP', if_true: files('prep.c'))
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 46daecab19..651263926e 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -10,21 +10,14 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
-#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qemu/log.h"
-#include "qemu/module.h"
#include "hw/irq.h"
-#include "exec/memory.h"
-#include "cpu.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/qdev-properties.h"
#include "hw/pci/pci.h"
-#include "sysemu/block-backend.h"
#include "sysemu/reset.h"
#include "ppc440.h"
-#include "qom/object.h"
-#include "trace.h"
/*****************************************************************************/
/* L2 Cache as SRAM */
@@ -380,10 +373,6 @@ enum {
PESDR1_RSTSTA = 0x365,
};
-#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29)
-#define SDR0_DDR0_DDRM_DDR1 0x20000000
-#define SDR0_DDR0_DDRM_DDR2 0x40000000
-
static uint32_t dcr_read_sdr(void *opaque, int dcrn)
{
ppc4xx_sdr_t *sdr = opaque;
@@ -482,327 +471,6 @@ void ppc4xx_sdr_init(CPUPPCState *env)
sdr, &dcr_read_sdr, &dcr_write_sdr);
}
-/*****************************************************************************/
-/* SDRAM controller */
-enum {
- SDRAM0_CFGADDR = 0x10,
- SDRAM0_CFGDATA,
- SDRAM_R0BAS = 0x40,
- SDRAM_R1BAS,
- SDRAM_R2BAS,
- SDRAM_R3BAS,
- SDRAM_CONF1HB = 0x45,
- SDRAM_PLBADDULL = 0x4a,
- SDRAM_CONF1LL = 0x4b,
- SDRAM_CONFPATHB = 0x4f,
- SDRAM_PLBADDUHB = 0x50,
-};
-
-static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
-{
- uint32_t bcr;
-
- switch (ram_size) {
- case (8 * MiB):
- bcr = 0xffc0;
- break;
- case (16 * MiB):
- bcr = 0xff80;
- break;
- case (32 * MiB):
- bcr = 0xff00;
- break;
- case (64 * MiB):
- bcr = 0xfe00;
- break;
- case (128 * MiB):
- bcr = 0xfc00;
- break;
- case (256 * MiB):
- bcr = 0xf800;
- break;
- case (512 * MiB):
- bcr = 0xf000;
- break;
- case (1 * GiB):
- bcr = 0xe000;
- break;
- case (2 * GiB):
- bcr = 0xc000;
- break;
- case (4 * GiB):
- bcr = 0x8000;
- break;
- default:
- error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
- return 0;
- }
- bcr |= ram_base >> 2 & 0xffe00000;
- bcr |= 1;
-
- return bcr;
-}
-
-static inline hwaddr sdram_ddr2_base(uint32_t bcr)
-{
- return (bcr & 0xffe00000) << 2;
-}
-
-static uint64_t sdram_ddr2_size(uint32_t bcr)
-{
- uint64_t size;
- int sh;
-
- sh = 1024 - ((bcr >> 6) & 0x3ff);
- size = 8 * MiB * sh;
-
- return size;
-}
-
-static void sdram_bank_map(Ppc4xxSdramBank *bank)
-{
- memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
- memory_region_add_subregion(&bank->container, 0, &bank->ram);
- memory_region_add_subregion(get_system_memory(), bank->base,
- &bank->container);
-}
-
-static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
-{
- memory_region_del_subregion(get_system_memory(), &bank->container);
- memory_region_del_subregion(&bank->container, &bank->ram);
- object_unparent(OBJECT(&bank->container));
-}
-
-static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i,
- uint32_t bcr, int enabled)
-{
- if (sdram->bank[i].bcr & 1) {
- /* First unmap RAM if enabled */
- trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
- sdram_ddr2_size(sdram->bank[i].bcr));
- sdram_bank_unmap(&sdram->bank[i]);
- }
- sdram->bank[i].bcr = bcr & 0xffe0ffc1;
- if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
- sdram_bank_map(&sdram->bank[i]);
- }
-}
-
-static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size) {
- sdram_ddr2_set_bcr(sdram, i,
- sdram_ddr2_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
- } else {
- sdram_ddr2_set_bcr(sdram, i, 0, 0);
- }
- }
-}
-
-static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size) {
- sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
- }
- }
-}
-
-static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
-{
- Ppc4xxSdramDdr2State *sdram = opaque;
- uint32_t ret = 0;
-
- switch (dcrn) {
- case SDRAM_R0BAS:
- case SDRAM_R1BAS:
- case SDRAM_R2BAS:
- case SDRAM_R3BAS:
- if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
- ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
- sdram->bank[dcrn - SDRAM_R0BAS].size);
- }
- break;
- case SDRAM_CONF1HB:
- case SDRAM_CONF1LL:
- case SDRAM_CONFPATHB:
- case SDRAM_PLBADDULL:
- case SDRAM_PLBADDUHB:
- break;
- case SDRAM0_CFGADDR:
- ret = sdram->addr;
- break;
- case SDRAM0_CFGDATA:
- switch (sdram->addr) {
- case 0x14: /* SDRAM_MCSTAT (405EX) */
- case 0x1F:
- ret = 0x80000000;
- break;
- case 0x21: /* SDRAM_MCOPT2 */
- ret = sdram->mcopt2;
- break;
- case 0x40: /* SDRAM_MB0CF */
- ret = 0x00008001;
- break;
- case 0x7A: /* SDRAM_DLCR */
- ret = 0x02000000;
- break;
- case 0xE1: /* SDR0_DDR0 */
- ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
-
- return ret;
-}
-
-#define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
-
-static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
-{
- Ppc4xxSdramDdr2State *sdram = opaque;
-
- switch (dcrn) {
- case SDRAM_R0BAS:
- case SDRAM_R1BAS:
- case SDRAM_R2BAS:
- case SDRAM_R3BAS:
- case SDRAM_CONF1HB:
- case SDRAM_CONF1LL:
- case SDRAM_CONFPATHB:
- case SDRAM_PLBADDULL:
- case SDRAM_PLBADDUHB:
- break;
- case SDRAM0_CFGADDR:
- sdram->addr = val;
- break;
- case SDRAM0_CFGDATA:
- switch (sdram->addr) {
- case 0x00: /* B0CR */
- break;
- case 0x21: /* SDRAM_MCOPT2 */
- if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
- (val & SDRAM_DDR2_MCOPT2_DCEN)) {
- trace_ppc4xx_sdram_enable("enable");
- /* validate all RAM mappings */
- sdram_ddr2_map_bcr(sdram);
- sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
- } else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
- !(val & SDRAM_DDR2_MCOPT2_DCEN)) {
- trace_ppc4xx_sdram_enable("disable");
- /* invalidate all RAM mappings */
- sdram_ddr2_unmap_bcr(sdram);
- sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
- }
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
-}
-
-static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
-{
- Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev);
-
- sdram->addr = 0;
- sdram->mcopt2 = 0;
-}
-
-static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
-{
- Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
- Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
- const ram_addr_t valid_bank_sizes[] = {
- 4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
- 32 * MiB, 16 * MiB, 8 * MiB, 0
- };
-
- if (s->nbanks < 1 || s->nbanks > 4) {
- error_setg(errp, "Invalid number of RAM banks");
- return;
- }
- if (!s->dram_mr) {
- error_setg(errp, "Missing dram memory region");
- return;
- }
- ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
-
- ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-
- ppc4xx_dcr_register(dcr, SDRAM_R0BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_R1BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_R2BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_R3BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_CONF1HB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_CONF1LL,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-}
-
-static Property ppc4xx_sdram_ddr2_props[] = {
- DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION,
- MemoryRegion *),
- DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc4xx_sdram_ddr2_realize;
- dc->reset = ppc4xx_sdram_ddr2_reset;
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
- device_class_set_props(dc, ppc4xx_sdram_ddr2_props);
-}
-
-void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s)
-{
- sdram_ddr2_dcr_write(s, SDRAM0_CFGADDR, 0x21);
- sdram_ddr2_dcr_write(s, SDRAM0_CFGDATA, 0x08000000);
-}
-
-static const TypeInfo ppc4xx_types[] = {
- {
- .name = TYPE_PPC4xx_SDRAM_DDR2,
- .parent = TYPE_PPC4xx_DCR_DEVICE,
- .instance_size = sizeof(Ppc4xxSdramDdr2State),
- .class_init = ppc4xx_sdram_ddr2_class_init,
- }
-};
-DEFINE_TYPES(ppc4xx_types)
-
/*****************************************************************************/
/* PLB to AHB bridge */
enum {
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 12af90f244..c1d111465d 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -23,419 +23,10 @@
*/
#include "qemu/osdep.h"
-#include "qemu/units.h"
-#include "sysemu/reset.h"
#include "cpu.h"
-#include "hw/irq.h"
-#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/qdev-properties.h"
-#include "qemu/log.h"
-#include "exec/address-spaces.h"
-#include "qemu/error-report.h"
#include "qapi/error.h"
-#include "trace.h"
-
-/*****************************************************************************/
-/* SDRAM controller */
-enum {
- SDRAM0_CFGADDR = 0x010,
- SDRAM0_CFGDATA = 0x011,
-};
-
-/*
- * XXX: TOFIX: some patches have made this code become inconsistent:
- * there are type inconsistencies, mixing hwaddr, target_ulong
- * and uint32_t
- */
-static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
-{
- uint32_t bcr;
-
- switch (ram_size) {
- case 4 * MiB:
- bcr = 0;
- break;
- case 8 * MiB:
- bcr = 0x20000;
- break;
- case 16 * MiB:
- bcr = 0x40000;
- break;
- case 32 * MiB:
- bcr = 0x60000;
- break;
- case 64 * MiB:
- bcr = 0x80000;
- break;
- case 128 * MiB:
- bcr = 0xA0000;
- break;
- case 256 * MiB:
- bcr = 0xC0000;
- break;
- default:
- qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
- ram_size);
- return 0;
- }
- bcr |= ram_base & 0xFF800000;
- bcr |= 1;
-
- return bcr;
-}
-
-static inline hwaddr sdram_ddr_base(uint32_t bcr)
-{
- return bcr & 0xFF800000;
-}
-
-static target_ulong sdram_ddr_size(uint32_t bcr)
-{
- target_ulong size;
- int sh;
-
- sh = (bcr >> 17) & 0x7;
- if (sh == 7) {
- size = -1;
- } else {
- size = (4 * MiB) << sh;
- }
-
- return size;
-}
-
-static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
- uint32_t bcr, int enabled)
-{
- if (sdram->bank[i].bcr & 1) {
- /* Unmap RAM */
- trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
- sdram_ddr_size(sdram->bank[i].bcr));
- memory_region_del_subregion(get_system_memory(),
- &sdram->bank[i].container);
- memory_region_del_subregion(&sdram->bank[i].container,
- &sdram->bank[i].ram);
- object_unparent(OBJECT(&sdram->bank[i].container));
- }
- sdram->bank[i].bcr = bcr & 0xFFDEE001;
- if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr));
- memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
- sdram_ddr_size(bcr));
- memory_region_add_subregion(&sdram->bank[i].container, 0,
- &sdram->bank[i].ram);
- memory_region_add_subregion(get_system_memory(),
- sdram_ddr_base(bcr),
- &sdram->bank[i].container);
- }
-}
-
-static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size != 0) {
- sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
- } else {
- sdram_ddr_set_bcr(sdram, i, 0, 0);
- }
- }
-}
-
-static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
- sdram_ddr_size(sdram->bank[i].bcr));
- memory_region_del_subregion(get_system_memory(),
- &sdram->bank[i].ram);
- }
-}
-
-static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
-{
- Ppc4xxSdramDdrState *sdram = opaque;
- uint32_t ret;
-
- switch (dcrn) {
- case SDRAM0_CFGADDR:
- ret = sdram->addr;
- break;
- case SDRAM0_CFGDATA:
- switch (sdram->addr) {
- case 0x00: /* SDRAM_BESR0 */
- ret = sdram->besr0;
- break;
- case 0x08: /* SDRAM_BESR1 */
- ret = sdram->besr1;
- break;
- case 0x10: /* SDRAM_BEAR */
- ret = sdram->bear;
- break;
- case 0x20: /* SDRAM_CFG */
- ret = sdram->cfg;
- break;
- case 0x24: /* SDRAM_STATUS */
- ret = sdram->status;
- break;
- case 0x30: /* SDRAM_RTR */
- ret = sdram->rtr;
- break;
- case 0x34: /* SDRAM_PMIT */
- ret = sdram->pmit;
- break;
- case 0x40: /* SDRAM_B0CR */
- ret = sdram->bank[0].bcr;
- break;
- case 0x44: /* SDRAM_B1CR */
- ret = sdram->bank[1].bcr;
- break;
- case 0x48: /* SDRAM_B2CR */
- ret = sdram->bank[2].bcr;
- break;
- case 0x4C: /* SDRAM_B3CR */
- ret = sdram->bank[3].bcr;
- break;
- case 0x80: /* SDRAM_TR */
- ret = -1; /* ? */
- break;
- case 0x94: /* SDRAM_ECCCFG */
- ret = sdram->ecccfg;
- break;
- case 0x98: /* SDRAM_ECCESR */
- ret = sdram->eccesr;
- break;
- default: /* Error */
- ret = -1;
- break;
- }
- break;
- default:
- /* Avoid gcc warning */
- ret = 0;
- break;
- }
-
- return ret;
-}
-
-static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
-{
- Ppc4xxSdramDdrState *sdram = opaque;
-
- switch (dcrn) {
- case SDRAM0_CFGADDR:
- sdram->addr = val;
- break;
- case SDRAM0_CFGDATA:
- switch (sdram->addr) {
- case 0x00: /* SDRAM_BESR0 */
- sdram->besr0 &= ~val;
- break;
- case 0x08: /* SDRAM_BESR1 */
- sdram->besr1 &= ~val;
- break;
- case 0x10: /* SDRAM_BEAR */
- sdram->bear = val;
- break;
- case 0x20: /* SDRAM_CFG */
- val &= 0xFFE00000;
- if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
- trace_ppc4xx_sdram_enable("enable");
- /* validate all RAM mappings */
- sdram_ddr_map_bcr(sdram);
- sdram->status &= ~0x80000000;
- } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
- trace_ppc4xx_sdram_enable("disable");
- /* invalidate all RAM mappings */
- sdram_ddr_unmap_bcr(sdram);
- sdram->status |= 0x80000000;
- }
- if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) {
- sdram->status |= 0x40000000;
- } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) {
- sdram->status &= ~0x40000000;
- }
- sdram->cfg = val;
- break;
- case 0x24: /* SDRAM_STATUS */
- /* Read-only register */
- break;
- case 0x30: /* SDRAM_RTR */
- sdram->rtr = val & 0x3FF80000;
- break;
- case 0x34: /* SDRAM_PMIT */
- sdram->pmit = (val & 0xF8000000) | 0x07C00000;
- break;
- case 0x40: /* SDRAM_B0CR */
- sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
- break;
- case 0x44: /* SDRAM_B1CR */
- sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
- break;
- case 0x48: /* SDRAM_B2CR */
- sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
- break;
- case 0x4C: /* SDRAM_B3CR */
- sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
- break;
- case 0x80: /* SDRAM_TR */
- sdram->tr = val & 0x018FC01F;
- break;
- case 0x94: /* SDRAM_ECCCFG */
- sdram->ecccfg = val & 0x00F00000;
- break;
- case 0x98: /* SDRAM_ECCESR */
- val &= 0xFFF0F000;
- if (sdram->eccesr == 0 && val != 0) {
- qemu_irq_raise(sdram->irq);
- } else if (sdram->eccesr != 0 && val == 0) {
- qemu_irq_lower(sdram->irq);
- }
- sdram->eccesr = val;
- break;
- default: /* Error */
- break;
- }
- break;
- }
-}
-
-static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
-{
- Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
-
- sdram->addr = 0;
- sdram->bear = 0;
- sdram->besr0 = 0; /* No error */
- sdram->besr1 = 0; /* No error */
- sdram->cfg = 0;
- sdram->ecccfg = 0; /* No ECC */
- sdram->eccesr = 0; /* No error */
- sdram->pmit = 0x07C00000;
- sdram->rtr = 0x05F00000;
- sdram->tr = 0x00854009;
- /* We pre-initialize RAM banks */
- sdram->status = 0;
- sdram->cfg = 0x00800000;
-}
-
-static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
-{
- Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
- Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
- const ram_addr_t valid_bank_sizes[] = {
- 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
- };
-
- if (s->nbanks < 1 || s->nbanks > 4) {
- error_setg(errp, "Invalid number of RAM banks");
- return;
- }
- if (!s->dram_mr) {
- error_setg(errp, "Missing dram memory region");
- return;
- }
- ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
-
- sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
-
- ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
- s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
- s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
-}
-
-static Property ppc4xx_sdram_ddr_props[] = {
- DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION,
- MemoryRegion *),
- DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc4xx_sdram_ddr_realize;
- dc->reset = ppc4xx_sdram_ddr_reset;
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
- device_class_set_props(dc, ppc4xx_sdram_ddr_props);
-}
-
-void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s)
-{
- sdram_ddr_dcr_write(s, SDRAM0_CFGADDR, 0x20);
- sdram_ddr_dcr_write(s, SDRAM0_CFGDATA, 0x80000000);
-}
-
-/*
- * Split RAM between SDRAM banks.
- *
- * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
- * and must be 0-terminated.
- *
- * The 4xx SDRAM controller supports a small number of banks, and each bank
- * must be one of a small set of sizes. The number of banks and the supported
- * sizes varies by SoC.
- */
-void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
- Ppc4xxSdramBank ram_banks[],
- const ram_addr_t sdram_bank_sizes[])
-{
- ram_addr_t size_left = memory_region_size(ram);
- ram_addr_t base = 0;
- ram_addr_t bank_size;
- int i;
- int j;
-
- for (i = 0; i < nr_banks; i++) {
- for (j = 0; sdram_bank_sizes[j] != 0; j++) {
- bank_size = sdram_bank_sizes[j];
- if (bank_size <= size_left) {
- char name[32];
-
- ram_banks[i].base = base;
- ram_banks[i].size = bank_size;
- base += bank_size;
- size_left -= bank_size;
- snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
- memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram,
- ram_banks[i].base, ram_banks[i].size);
- break;
- }
- }
- if (!size_left) {
- /* No need to use the remaining banks. */
- break;
- }
- }
-
- if (size_left) {
- ram_addr_t used_size = memory_region_size(ram) - size_left;
- GString *s = g_string_new(NULL);
-
- for (i = 0; sdram_bank_sizes[i]; i++) {
- g_string_append_printf(s, "%" PRIi64 "%s",
- sdram_bank_sizes[i] / MiB,
- sdram_bank_sizes[i + 1] ? ", " : "");
- }
- error_report("at most %d bank%s of %s MiB each supported",
- nr_banks, nr_banks == 1 ? "" : "s", s->str);
- error_printf("Possible valid RAM size: %" PRIi64 " MiB\n",
- used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
-
- g_string_free(s, true);
- exit(EXIT_FAILURE);
- }
-}
/*****************************************************************************/
/* MAL */
@@ -963,11 +554,6 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc4xx_types[] = {
{
- .name = TYPE_PPC4xx_SDRAM_DDR,
- .parent = TYPE_PPC4xx_DCR_DEVICE,
- .instance_size = sizeof(Ppc4xxSdramDdrState),
- .class_init = ppc4xx_sdram_ddr_class_init,
- }, {
.name = TYPE_PPC4xx_MAL,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc4xxMalState),
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
new file mode 100644
index 0000000000..fe91b0ca82
--- /dev/null
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -0,0 +1,771 @@
+/*
+ * QEMU PowerPC 4xx embedded processors SDRAM controller emulation
+ *
+ * DDR SDRAM controller:
+ * Copyright (c) 2007 Jocelyn Mayer
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * DDR2 SDRAM controller:
+ * Copyright (c) 2012 François Revol
+ * Copyright (c) 2016-2019 BALATON Zoltan
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "exec/address-spaces.h" /* get_system_memory() */
+#include "exec/cpu-defs.h" /* target_ulong */
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "hw/ppc/ppc4xx.h"
+#include "trace.h"
+
+/*****************************************************************************/
+/* Shared functions */
+
+/*
+ * Split RAM between SDRAM banks.
+ *
+ * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
+ * and must be 0-terminated.
+ *
+ * The 4xx SDRAM controller supports a small number of banks, and each bank
+ * must be one of a small set of sizes. The number of banks and the supported
+ * sizes varies by SoC.
+ */
+static void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
+ Ppc4xxSdramBank ram_banks[],
+ const ram_addr_t sdram_bank_sizes[])
+{
+ ram_addr_t size_left = memory_region_size(ram);
+ ram_addr_t base = 0;
+ ram_addr_t bank_size;
+ int i;
+ int j;
+
+ for (i = 0; i < nr_banks; i++) {
+ for (j = 0; sdram_bank_sizes[j] != 0; j++) {
+ bank_size = sdram_bank_sizes[j];
+ if (bank_size <= size_left) {
+ char name[32];
+
+ ram_banks[i].base = base;
+ ram_banks[i].size = bank_size;
+ base += bank_size;
+ size_left -= bank_size;
+ snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
+ memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram,
+ ram_banks[i].base, ram_banks[i].size);
+ break;
+ }
+ }
+ if (!size_left) {
+ /* No need to use the remaining banks. */
+ break;
+ }
+ }
+
+ if (size_left) {
+ ram_addr_t used_size = memory_region_size(ram) - size_left;
+ GString *s = g_string_new(NULL);
+
+ for (i = 0; sdram_bank_sizes[i]; i++) {
+ g_string_append_printf(s, "%" PRIi64 "%s",
+ sdram_bank_sizes[i] / MiB,
+ sdram_bank_sizes[i + 1] ? ", " : "");
+ }
+ error_report("at most %d bank%s of %s MiB each supported",
+ nr_banks, nr_banks == 1 ? "" : "s", s->str);
+ error_printf("Possible valid RAM size: %" PRIi64 " MiB\n",
+ used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
+
+ g_string_free(s, true);
+ exit(EXIT_FAILURE);
+ }
+}
+
+static void sdram_bank_map(Ppc4xxSdramBank *bank)
+{
+ memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
+ memory_region_add_subregion(&bank->container, 0, &bank->ram);
+ memory_region_add_subregion(get_system_memory(), bank->base,
+ &bank->container);
+}
+
+static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
+{
+ memory_region_del_subregion(get_system_memory(), &bank->container);
+ memory_region_del_subregion(&bank->container, &bank->ram);
+ object_unparent(OBJECT(&bank->container));
+}
+
+enum {
+ SDRAM0_CFGADDR = 0x010,
+ SDRAM0_CFGDATA = 0x011,
+};
+
+/*****************************************************************************/
+/* DDR SDRAM controller */
+/*
+ * XXX: TOFIX: some patches have made this code become inconsistent:
+ * there are type inconsistencies, mixing hwaddr, target_ulong
+ * and uint32_t
+ */
+static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
+{
+ uint32_t bcr;
+
+ switch (ram_size) {
+ case 4 * MiB:
+ bcr = 0;
+ break;
+ case 8 * MiB:
+ bcr = 0x20000;
+ break;
+ case 16 * MiB:
+ bcr = 0x40000;
+ break;
+ case 32 * MiB:
+ bcr = 0x60000;
+ break;
+ case 64 * MiB:
+ bcr = 0x80000;
+ break;
+ case 128 * MiB:
+ bcr = 0xA0000;
+ break;
+ case 256 * MiB:
+ bcr = 0xC0000;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
+ ram_size);
+ return 0;
+ }
+ bcr |= ram_base & 0xFF800000;
+ bcr |= 1;
+
+ return bcr;
+}
+
+static inline hwaddr sdram_ddr_base(uint32_t bcr)
+{
+ return bcr & 0xFF800000;
+}
+
+static target_ulong sdram_ddr_size(uint32_t bcr)
+{
+ target_ulong size;
+ int sh;
+
+ sh = (bcr >> 17) & 0x7;
+ if (sh == 7) {
+ size = -1;
+ } else {
+ size = (4 * MiB) << sh;
+ }
+
+ return size;
+}
+
+static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
+ uint32_t bcr, int enabled)
+{
+ if (sdram->bank[i].bcr & 1) {
+ /* Unmap RAM */
+ trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
+ sdram_ddr_size(sdram->bank[i].bcr));
+ memory_region_del_subregion(get_system_memory(),
+ &sdram->bank[i].container);
+ memory_region_del_subregion(&sdram->bank[i].container,
+ &sdram->bank[i].ram);
+ object_unparent(OBJECT(&sdram->bank[i].container));
+ }
+ sdram->bank[i].bcr = bcr & 0xFFDEE001;
+ if (enabled && (bcr & 1)) {
+ trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr));
+ memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
+ sdram_ddr_size(bcr));
+ memory_region_add_subregion(&sdram->bank[i].container, 0,
+ &sdram->bank[i].ram);
+ memory_region_add_subregion(get_system_memory(),
+ sdram_ddr_base(bcr),
+ &sdram->bank[i].container);
+ }
+}
+
+static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram)
+{
+ int i;
+
+ for (i = 0; i < sdram->nbanks; i++) {
+ if (sdram->bank[i].size != 0) {
+ sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
+ } else {
+ sdram_ddr_set_bcr(sdram, i, 0, 0);
+ }
+ }
+}
+
+static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
+{
+ int i;
+
+ for (i = 0; i < sdram->nbanks; i++) {
+ trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
+ sdram_ddr_size(sdram->bank[i].bcr));
+ memory_region_del_subregion(get_system_memory(),
+ &sdram->bank[i].ram);
+ }
+}
+
+static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
+{
+ Ppc4xxSdramDdrState *sdram = opaque;
+ uint32_t ret;
+
+ switch (dcrn) {
+ case SDRAM0_CFGADDR:
+ ret = sdram->addr;
+ break;
+ case SDRAM0_CFGDATA:
+ switch (sdram->addr) {
+ case 0x00: /* SDRAM_BESR0 */
+ ret = sdram->besr0;
+ break;
+ case 0x08: /* SDRAM_BESR1 */
+ ret = sdram->besr1;
+ break;
+ case 0x10: /* SDRAM_BEAR */
+ ret = sdram->bear;
+ break;
+ case 0x20: /* SDRAM_CFG */
+ ret = sdram->cfg;
+ break;
+ case 0x24: /* SDRAM_STATUS */
+ ret = sdram->status;
+ break;
+ case 0x30: /* SDRAM_RTR */
+ ret = sdram->rtr;
+ break;
+ case 0x34: /* SDRAM_PMIT */
+ ret = sdram->pmit;
+ break;
+ case 0x40: /* SDRAM_B0CR */
+ ret = sdram->bank[0].bcr;
+ break;
+ case 0x44: /* SDRAM_B1CR */
+ ret = sdram->bank[1].bcr;
+ break;
+ case 0x48: /* SDRAM_B2CR */
+ ret = sdram->bank[2].bcr;
+ break;
+ case 0x4C: /* SDRAM_B3CR */
+ ret = sdram->bank[3].bcr;
+ break;
+ case 0x80: /* SDRAM_TR */
+ ret = -1; /* ? */
+ break;
+ case 0x94: /* SDRAM_ECCCFG */
+ ret = sdram->ecccfg;
+ break;
+ case 0x98: /* SDRAM_ECCESR */
+ ret = sdram->eccesr;
+ break;
+ default: /* Error */
+ ret = -1;
+ break;
+ }
+ break;
+ default:
+ /* Avoid gcc warning */
+ ret = 0;
+ break;
+ }
+
+ return ret;
+}
+
+static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
+{
+ Ppc4xxSdramDdrState *sdram = opaque;
+
+ switch (dcrn) {
+ case SDRAM0_CFGADDR:
+ sdram->addr = val;
+ break;
+ case SDRAM0_CFGDATA:
+ switch (sdram->addr) {
+ case 0x00: /* SDRAM_BESR0 */
+ sdram->besr0 &= ~val;
+ break;
+ case 0x08: /* SDRAM_BESR1 */
+ sdram->besr1 &= ~val;
+ break;
+ case 0x10: /* SDRAM_BEAR */
+ sdram->bear = val;
+ break;
+ case 0x20: /* SDRAM_CFG */
+ val &= 0xFFE00000;
+ if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
+ trace_ppc4xx_sdram_enable("enable");
+ /* validate all RAM mappings */
+ sdram_ddr_map_bcr(sdram);
+ sdram->status &= ~0x80000000;
+ } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
+ trace_ppc4xx_sdram_enable("disable");
+ /* invalidate all RAM mappings */
+ sdram_ddr_unmap_bcr(sdram);
+ sdram->status |= 0x80000000;
+ }
+ if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) {
+ sdram->status |= 0x40000000;
+ } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) {
+ sdram->status &= ~0x40000000;
+ }
+ sdram->cfg = val;
+ break;
+ case 0x24: /* SDRAM_STATUS */
+ /* Read-only register */
+ break;
+ case 0x30: /* SDRAM_RTR */
+ sdram->rtr = val & 0x3FF80000;
+ break;
+ case 0x34: /* SDRAM_PMIT */
+ sdram->pmit = (val & 0xF8000000) | 0x07C00000;
+ break;
+ case 0x40: /* SDRAM_B0CR */
+ sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
+ break;
+ case 0x44: /* SDRAM_B1CR */
+ sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
+ break;
+ case 0x48: /* SDRAM_B2CR */
+ sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
+ break;
+ case 0x4C: /* SDRAM_B3CR */
+ sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
+ break;
+ case 0x80: /* SDRAM_TR */
+ sdram->tr = val & 0x018FC01F;
+ break;
+ case 0x94: /* SDRAM_ECCCFG */
+ sdram->ecccfg = val & 0x00F00000;
+ break;
+ case 0x98: /* SDRAM_ECCESR */
+ val &= 0xFFF0F000;
+ if (sdram->eccesr == 0 && val != 0) {
+ qemu_irq_raise(sdram->irq);
+ } else if (sdram->eccesr != 0 && val == 0) {
+ qemu_irq_lower(sdram->irq);
+ }
+ sdram->eccesr = val;
+ break;
+ default: /* Error */
+ break;
+ }
+ break;
+ }
+}
+
+static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
+{
+ Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
+
+ sdram->addr = 0;
+ sdram->bear = 0;
+ sdram->besr0 = 0; /* No error */
+ sdram->besr1 = 0; /* No error */
+ sdram->cfg = 0;
+ sdram->ecccfg = 0; /* No ECC */
+ sdram->eccesr = 0; /* No error */
+ sdram->pmit = 0x07C00000;
+ sdram->rtr = 0x05F00000;
+ sdram->tr = 0x00854009;
+ /* We pre-initialize RAM banks */
+ sdram->status = 0;
+ sdram->cfg = 0x00800000;
+}
+
+static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
+{
+ Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+ const ram_addr_t valid_bank_sizes[] = {
+ 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
+ };
+
+ if (s->nbanks < 1 || s->nbanks > 4) {
+ error_setg(errp, "Invalid number of RAM banks");
+ return;
+ }
+ if (!s->dram_mr) {
+ error_setg(errp, "Missing dram memory region");
+ return;
+ }
+ ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
+
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
+ s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
+ s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
+}
+
+static Property ppc4xx_sdram_ddr_props[] = {
+ DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_sdram_ddr_realize;
+ dc->reset = ppc4xx_sdram_ddr_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_sdram_ddr_props);
+}
+
+void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s)
+{
+ sdram_ddr_dcr_write(s, SDRAM0_CFGADDR, 0x20);
+ sdram_ddr_dcr_write(s, SDRAM0_CFGDATA, 0x80000000);
+}
+
+/*****************************************************************************/
+/* DDR2 SDRAM controller */
+enum {
+ SDRAM_R0BAS = 0x40,
+ SDRAM_R1BAS,
+ SDRAM_R2BAS,
+ SDRAM_R3BAS,
+ SDRAM_CONF1HB = 0x45,
+ SDRAM_PLBADDULL = 0x4a,
+ SDRAM_CONF1LL = 0x4b,
+ SDRAM_CONFPATHB = 0x4f,
+ SDRAM_PLBADDUHB = 0x50,
+};
+
+static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
+{
+ uint32_t bcr;
+
+ switch (ram_size) {
+ case 8 * MiB:
+ bcr = 0xffc0;
+ break;
+ case 16 * MiB:
+ bcr = 0xff80;
+ break;
+ case 32 * MiB:
+ bcr = 0xff00;
+ break;
+ case 64 * MiB:
+ bcr = 0xfe00;
+ break;
+ case 128 * MiB:
+ bcr = 0xfc00;
+ break;
+ case 256 * MiB:
+ bcr = 0xf800;
+ break;
+ case 512 * MiB:
+ bcr = 0xf000;
+ break;
+ case 1 * GiB:
+ bcr = 0xe000;
+ break;
+ case 2 * GiB:
+ bcr = 0xc000;
+ break;
+ case 4 * GiB:
+ bcr = 0x8000;
+ break;
+ default:
+ error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
+ return 0;
+ }
+ bcr |= ram_base >> 2 & 0xffe00000;
+ bcr |= 1;
+
+ return bcr;
+}
+
+static inline hwaddr sdram_ddr2_base(uint32_t bcr)
+{
+ return (bcr & 0xffe00000) << 2;
+}
+
+static uint64_t sdram_ddr2_size(uint32_t bcr)
+{
+ uint64_t size;
+ int sh;
+
+ sh = 1024 - ((bcr >> 6) & 0x3ff);
+ size = 8 * MiB * sh;
+
+ return size;
+}
+
+static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i,
+ uint32_t bcr, int enabled)
+{
+ if (sdram->bank[i].bcr & 1) {
+ /* First unmap RAM if enabled */
+ trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
+ sdram_ddr2_size(sdram->bank[i].bcr));
+ sdram_bank_unmap(&sdram->bank[i]);
+ }
+ sdram->bank[i].bcr = bcr & 0xffe0ffc1;
+ if (enabled && (bcr & 1)) {
+ trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
+ sdram_bank_map(&sdram->bank[i]);
+ }
+}
+
+static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram)
+{
+ int i;
+
+ for (i = 0; i < sdram->nbanks; i++) {
+ if (sdram->bank[i].size) {
+ sdram_ddr2_set_bcr(sdram, i,
+ sdram_ddr2_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
+ } else {
+ sdram_ddr2_set_bcr(sdram, i, 0, 0);
+ }
+ }
+}
+
+static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
+{
+ int i;
+
+ for (i = 0; i < sdram->nbanks; i++) {
+ if (sdram->bank[i].size) {
+ sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+ }
+ }
+}
+
+static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
+{
+ Ppc4xxSdramDdr2State *sdram = opaque;
+ uint32_t ret = 0;
+
+ switch (dcrn) {
+ case SDRAM_R0BAS:
+ case SDRAM_R1BAS:
+ case SDRAM_R2BAS:
+ case SDRAM_R3BAS:
+ if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
+ ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
+ sdram->bank[dcrn - SDRAM_R0BAS].size);
+ }
+ break;
+ case SDRAM_CONF1HB:
+ case SDRAM_CONF1LL:
+ case SDRAM_CONFPATHB:
+ case SDRAM_PLBADDULL:
+ case SDRAM_PLBADDUHB:
+ break;
+ case SDRAM0_CFGADDR:
+ ret = sdram->addr;
+ break;
+ case SDRAM0_CFGDATA:
+ switch (sdram->addr) {
+ case 0x14: /* SDRAM_MCSTAT (405EX) */
+ case 0x1F:
+ ret = 0x80000000;
+ break;
+ case 0x21: /* SDRAM_MCOPT2 */
+ ret = sdram->mcopt2;
+ break;
+ case 0x40: /* SDRAM_MB0CF */
+ ret = 0x00008001;
+ break;
+ case 0x7A: /* SDRAM_DLCR */
+ ret = 0x02000000;
+ break;
+ case 0xE1: /* SDR0_DDR0 */
+ ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+#define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
+
+static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
+{
+ Ppc4xxSdramDdr2State *sdram = opaque;
+
+ switch (dcrn) {
+ case SDRAM_R0BAS:
+ case SDRAM_R1BAS:
+ case SDRAM_R2BAS:
+ case SDRAM_R3BAS:
+ case SDRAM_CONF1HB:
+ case SDRAM_CONF1LL:
+ case SDRAM_CONFPATHB:
+ case SDRAM_PLBADDULL:
+ case SDRAM_PLBADDUHB:
+ break;
+ case SDRAM0_CFGADDR:
+ sdram->addr = val;
+ break;
+ case SDRAM0_CFGDATA:
+ switch (sdram->addr) {
+ case 0x00: /* B0CR */
+ break;
+ case 0x21: /* SDRAM_MCOPT2 */
+ if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
+ (val & SDRAM_DDR2_MCOPT2_DCEN)) {
+ trace_ppc4xx_sdram_enable("enable");
+ /* validate all RAM mappings */
+ sdram_ddr2_map_bcr(sdram);
+ sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
+ } else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
+ !(val & SDRAM_DDR2_MCOPT2_DCEN)) {
+ trace_ppc4xx_sdram_enable("disable");
+ /* invalidate all RAM mappings */
+ sdram_ddr2_unmap_bcr(sdram);
+ sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
+{
+ Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev);
+
+ sdram->addr = 0;
+ sdram->mcopt2 = 0;
+}
+
+static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
+{
+ Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+ const ram_addr_t valid_bank_sizes[] = {
+ 4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
+ 32 * MiB, 16 * MiB, 8 * MiB, 0
+ };
+
+ if (s->nbanks < 1 || s->nbanks > 4) {
+ error_setg(errp, "Invalid number of RAM banks");
+ return;
+ }
+ if (!s->dram_mr) {
+ error_setg(errp, "Missing dram memory region");
+ return;
+ }
+ ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+
+ ppc4xx_dcr_register(dcr, SDRAM_R0BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R1BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R2BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R3BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONF1HB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONF1LL,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+}
+
+static Property ppc4xx_sdram_ddr2_props[] = {
+ DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_sdram_ddr2_realize;
+ dc->reset = ppc4xx_sdram_ddr2_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_sdram_ddr2_props);
+}
+
+void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s)
+{
+ sdram_ddr2_dcr_write(s, SDRAM0_CFGADDR, 0x21);
+ sdram_ddr2_dcr_write(s, SDRAM0_CFGDATA, 0x08000000);
+}
+
+static const TypeInfo ppc4xx_sdram_types[] = {
+ {
+ .name = TYPE_PPC4xx_SDRAM_DDR,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxSdramDdrState),
+ .class_init = ppc4xx_sdram_ddr_class_init,
+ }, {
+ .name = TYPE_PPC4xx_SDRAM_DDR2,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxSdramDdr2State),
+ .class_init = ppc4xx_sdram_ddr2_class_init,
+ }
+};
+
+DEFINE_TYPES(ppc4xx_sdram_types)
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index ff88385ac0..f8c86e09ec 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -29,18 +29,6 @@
#include "exec/memory.h"
#include "hw/sysbus.h"
-typedef struct {
- MemoryRegion ram;
- MemoryRegion container; /* used for clipping */
- hwaddr base;
- hwaddr size;
- uint32_t bcr;
-} Ppc4xxSdramBank;
-
-void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
- Ppc4xxSdramBank ram_banks[],
- const ram_addr_t sdram_bank_sizes[]);
-
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
/*
@@ -111,6 +99,18 @@ struct Ppc4xxEbcState {
};
/* SDRAM DDR controller */
+typedef struct {
+ MemoryRegion ram;
+ MemoryRegion container; /* used for clipping */
+ hwaddr base;
+ hwaddr size;
+ uint32_t bcr;
+} Ppc4xxSdramBank;
+
+#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29)
+#define SDR0_DDR0_DDRM_DDR1 0x20000000
+#define SDR0_DDR0_DDRM_DDR2 0x40000000
+
#define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR);
struct Ppc4xxSdramDdrState {
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v5 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together
2022-09-18 20:24 ` [PATCH v5 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together BALATON Zoltan
@ 2022-09-18 21:02 ` Philippe Mathieu-Daudé via
2022-09-18 21:24 ` BALATON Zoltan
0 siblings, 1 reply; 28+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-09-18 21:02 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: clg, Daniel Henrique Barboza, Peter Maydell
Hi Zoltan,
On 18/9/22 22:24, BALATON Zoltan wrote:
> Move the PPC4xx DDR and DDR2 SDRAM contrller models into a new file
> called ppc4xx_sdram to separate from other device models and put them
> in one place allowing sharing some code between them.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/meson.build | 3 +-
> hw/ppc/ppc440_uc.c | 332 -----------------
> hw/ppc/ppc4xx_devs.c | 414 ---------------------
> hw/ppc/ppc4xx_sdram.c | 771 ++++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/ppc4xx.h | 24 +-
> 5 files changed, 785 insertions(+), 759 deletions(-)
This seems a proper cleanup, but even using `git-diff
--color-moved=dimmed-zebra` I'm having hard time reviewing this single
patch.
Looking at the changes in the ppc4xx_sdram_types[] array, it
seems we can be move one model at a time, right?
[...]
> +static const TypeInfo ppc4xx_sdram_types[] = {
> + {
> + .name = TYPE_PPC4xx_SDRAM_DDR,
> + .parent = TYPE_PPC4xx_DCR_DEVICE,
> + .instance_size = sizeof(Ppc4xxSdramDdrState),
> + .class_init = ppc4xx_sdram_ddr_class_init,
> + }, {
> + .name = TYPE_PPC4xx_SDRAM_DDR2,
> + .parent = TYPE_PPC4xx_DCR_DEVICE,
> + .instance_size = sizeof(Ppc4xxSdramDdr2State),
> + .class_init = ppc4xx_sdram_ddr2_class_init,
> + }
> +};
> +
> +DEFINE_TYPES(ppc4xx_sdram_types)
[...]
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v5 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together
2022-09-18 21:02 ` Philippe Mathieu-Daudé via
@ 2022-09-18 21:24 ` BALATON Zoltan
2022-09-18 21:36 ` Philippe Mathieu-Daudé via
0 siblings, 1 reply; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 21:24 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, qemu-ppc, clg, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 2054 bytes --]
On Sun, 18 Sep 2022, Philippe Mathieu-Daudé wrote:
> Hi Zoltan,
>
> On 18/9/22 22:24, BALATON Zoltan wrote:
>> Move the PPC4xx DDR and DDR2 SDRAM contrller models into a new file
>> called ppc4xx_sdram to separate from other device models and put them
>> in one place allowing sharing some code between them.
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> hw/ppc/meson.build | 3 +-
>> hw/ppc/ppc440_uc.c | 332 -----------------
>> hw/ppc/ppc4xx_devs.c | 414 ---------------------
>> hw/ppc/ppc4xx_sdram.c | 771 ++++++++++++++++++++++++++++++++++++++++
>> include/hw/ppc/ppc4xx.h | 24 +-
>> 5 files changed, 785 insertions(+), 759 deletions(-)
>
> This seems a proper cleanup, but even using `git-diff
> --color-moved=dimmed-zebra` I'm having hard time reviewing this single
> patch.
> Looking at the changes in the ppc4xx_sdram_types[] array, it
> seems we can be move one model at a time, right?
I could try to break this patch up some more if absolutely necessary but
I've already spent a lot of time rebasing this series as every little
change in earlier patch leads to conflicts later then patches get squashed
during rebase and I have to redo it again to separate them. So if you
can't review it looking at it some more I could try a v6 but don't want if
can be avoided. I'll wait for Cédric's comments too in any case to only do
as many respins as needed.
Regards,
BALATON Zoltan
> [...]
>> +static const TypeInfo ppc4xx_sdram_types[] = {
>> + {
>> + .name = TYPE_PPC4xx_SDRAM_DDR,
>> + .parent = TYPE_PPC4xx_DCR_DEVICE,
>> + .instance_size = sizeof(Ppc4xxSdramDdrState),
>> + .class_init = ppc4xx_sdram_ddr_class_init,
>> + }, {
>> + .name = TYPE_PPC4xx_SDRAM_DDR2,
>> + .parent = TYPE_PPC4xx_DCR_DEVICE,
>> + .instance_size = sizeof(Ppc4xxSdramDdr2State),
>> + .class_init = ppc4xx_sdram_ddr2_class_init,
>> + }
>> +};
>> +
>> +DEFINE_TYPES(ppc4xx_sdram_types)
> [...]
>
>
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v5 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together
2022-09-18 21:24 ` BALATON Zoltan
@ 2022-09-18 21:36 ` Philippe Mathieu-Daudé via
0 siblings, 0 replies; 28+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-09-18 21:36 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-devel, qemu-ppc, clg, Daniel Henrique Barboza, Peter Maydell
On 18/9/22 23:24, BALATON Zoltan wrote:
> On Sun, 18 Sep 2022, Philippe Mathieu-Daudé wrote:
>> Hi Zoltan,
>>
>> On 18/9/22 22:24, BALATON Zoltan wrote:
>>> Move the PPC4xx DDR and DDR2 SDRAM contrller models into a new file
>>> called ppc4xx_sdram to separate from other device models and put them
>>> in one place allowing sharing some code between them.
>>>
>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>> ---
>>> hw/ppc/meson.build | 3 +-
>>> hw/ppc/ppc440_uc.c | 332 -----------------
>>> hw/ppc/ppc4xx_devs.c | 414 ---------------------
>>> hw/ppc/ppc4xx_sdram.c | 771 ++++++++++++++++++++++++++++++++++++++++
>>> include/hw/ppc/ppc4xx.h | 24 +-
>>> 5 files changed, 785 insertions(+), 759 deletions(-)
>>
>> This seems a proper cleanup, but even using `git-diff
>> --color-moved=dimmed-zebra` I'm having hard time reviewing this single
>> patch.
>> Looking at the changes in the ppc4xx_sdram_types[] array, it
>> seems we can be move one model at a time, right?
>
> I could try to break this patch up some more if absolutely necessary but
> I've already spent a lot of time rebasing this series as every little
> change in earlier patch leads to conflicts later then patches get
> squashed during rebase and I have to redo it again to separate them. So
> if you can't review it looking at it some more I could try a v6 but
> don't want if can be avoided. I'll wait for Cédric's comments too in any
> case to only do as many respins as needed.
Sure, I totally understand. Let see first if someone is willing to
review it as it.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v5 17/21] ppc4xx_sdram: Use hwaddr for memory bank size
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (15 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 16/21] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 18/21] ppc4xx_sdram: Rename local state variable for brevity BALATON Zoltan
` (4 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
This resolves the target_ulong dependency that's clearly wrong and was
also noted in a fixme comment.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/ppc/ppc4xx_sdram.c | 14 ++++----------
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index fe91b0ca82..3ec2edeb17 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -34,7 +34,6 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "exec/address-spaces.h" /* get_system_memory() */
-#include "exec/cpu-defs.h" /* target_ulong */
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
@@ -127,11 +126,6 @@ enum {
/*****************************************************************************/
/* DDR SDRAM controller */
-/*
- * XXX: TOFIX: some patches have made this code become inconsistent:
- * there are type inconsistencies, mixing hwaddr, target_ulong
- * and uint32_t
- */
static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -175,9 +169,9 @@ static inline hwaddr sdram_ddr_base(uint32_t bcr)
return bcr & 0xFF800000;
}
-static target_ulong sdram_ddr_size(uint32_t bcr)
+static hwaddr sdram_ddr_size(uint32_t bcr)
{
- target_ulong size;
+ hwaddr size;
int sh;
sh = (bcr >> 17) & 0x7;
@@ -524,9 +518,9 @@ static inline hwaddr sdram_ddr2_base(uint32_t bcr)
return (bcr & 0xffe00000) << 2;
}
-static uint64_t sdram_ddr2_size(uint32_t bcr)
+static hwaddr sdram_ddr2_size(uint32_t bcr)
{
- uint64_t size;
+ hwaddr size;
int sh;
sh = 1024 - ((bcr >> 6) & 0x3ff);
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 18/21] ppc4xx_sdram: Rename local state variable for brevity
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (16 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 17/21] ppc4xx_sdram: Use hwaddr for memory bank size BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:51 ` Philippe Mathieu-Daudé via
2022-09-18 20:24 ` [PATCH v5 19/21] ppc4xx_sdram: Generalise bank setup BALATON Zoltan
` (3 subsequent siblings)
21 siblings, 1 reply; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Rename the sdram local state variable to s in dcr read/write functions
and reset methods for better readability and to match realize methods.
Other places not converted will be changed or removed in subsequent
patches.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc4xx_sdram.c | 158 +++++++++++++++++++++---------------------
1 file changed, 79 insertions(+), 79 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index 3ec2edeb17..3b2d01a144 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -238,56 +238,56 @@ static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
{
- Ppc4xxSdramDdrState *sdram = opaque;
+ Ppc4xxSdramDdrState *s = opaque;
uint32_t ret;
switch (dcrn) {
case SDRAM0_CFGADDR:
- ret = sdram->addr;
+ ret = s->addr;
break;
case SDRAM0_CFGDATA:
- switch (sdram->addr) {
+ switch (s->addr) {
case 0x00: /* SDRAM_BESR0 */
- ret = sdram->besr0;
+ ret = s->besr0;
break;
case 0x08: /* SDRAM_BESR1 */
- ret = sdram->besr1;
+ ret = s->besr1;
break;
case 0x10: /* SDRAM_BEAR */
- ret = sdram->bear;
+ ret = s->bear;
break;
case 0x20: /* SDRAM_CFG */
- ret = sdram->cfg;
+ ret = s->cfg;
break;
case 0x24: /* SDRAM_STATUS */
- ret = sdram->status;
+ ret = s->status;
break;
case 0x30: /* SDRAM_RTR */
- ret = sdram->rtr;
+ ret = s->rtr;
break;
case 0x34: /* SDRAM_PMIT */
- ret = sdram->pmit;
+ ret = s->pmit;
break;
case 0x40: /* SDRAM_B0CR */
- ret = sdram->bank[0].bcr;
+ ret = s->bank[0].bcr;
break;
case 0x44: /* SDRAM_B1CR */
- ret = sdram->bank[1].bcr;
+ ret = s->bank[1].bcr;
break;
case 0x48: /* SDRAM_B2CR */
- ret = sdram->bank[2].bcr;
+ ret = s->bank[2].bcr;
break;
case 0x4C: /* SDRAM_B3CR */
- ret = sdram->bank[3].bcr;
+ ret = s->bank[3].bcr;
break;
case 0x80: /* SDRAM_TR */
ret = -1; /* ? */
break;
case 0x94: /* SDRAM_ECCCFG */
- ret = sdram->ecccfg;
+ ret = s->ecccfg;
break;
case 0x98: /* SDRAM_ECCESR */
- ret = sdram->eccesr;
+ ret = s->eccesr;
break;
default: /* Error */
ret = -1;
@@ -305,78 +305,78 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
{
- Ppc4xxSdramDdrState *sdram = opaque;
+ Ppc4xxSdramDdrState *s = opaque;
switch (dcrn) {
case SDRAM0_CFGADDR:
- sdram->addr = val;
+ s->addr = val;
break;
case SDRAM0_CFGDATA:
- switch (sdram->addr) {
+ switch (s->addr) {
case 0x00: /* SDRAM_BESR0 */
- sdram->besr0 &= ~val;
+ s->besr0 &= ~val;
break;
case 0x08: /* SDRAM_BESR1 */
- sdram->besr1 &= ~val;
+ s->besr1 &= ~val;
break;
case 0x10: /* SDRAM_BEAR */
- sdram->bear = val;
+ s->bear = val;
break;
case 0x20: /* SDRAM_CFG */
val &= 0xFFE00000;
- if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
+ if (!(s->cfg & 0x80000000) && (val & 0x80000000)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_ddr_map_bcr(sdram);
- sdram->status &= ~0x80000000;
- } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
+ sdram_ddr_map_bcr(s);
+ s->status &= ~0x80000000;
+ } else if ((s->cfg & 0x80000000) && !(val & 0x80000000)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_ddr_unmap_bcr(sdram);
- sdram->status |= 0x80000000;
+ sdram_ddr_unmap_bcr(s);
+ s->status |= 0x80000000;
}
- if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) {
- sdram->status |= 0x40000000;
- } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) {
- sdram->status &= ~0x40000000;
+ if (!(s->cfg & 0x40000000) && (val & 0x40000000)) {
+ s->status |= 0x40000000;
+ } else if ((s->cfg & 0x40000000) && !(val & 0x40000000)) {
+ s->status &= ~0x40000000;
}
- sdram->cfg = val;
+ s->cfg = val;
break;
case 0x24: /* SDRAM_STATUS */
/* Read-only register */
break;
case 0x30: /* SDRAM_RTR */
- sdram->rtr = val & 0x3FF80000;
+ s->rtr = val & 0x3FF80000;
break;
case 0x34: /* SDRAM_PMIT */
- sdram->pmit = (val & 0xF8000000) | 0x07C00000;
+ s->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
- sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(s, 0, val, s->cfg & 0x80000000);
break;
case 0x44: /* SDRAM_B1CR */
- sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(s, 1, val, s->cfg & 0x80000000);
break;
case 0x48: /* SDRAM_B2CR */
- sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(s, 2, val, s->cfg & 0x80000000);
break;
case 0x4C: /* SDRAM_B3CR */
- sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(s, 3, val, s->cfg & 0x80000000);
break;
case 0x80: /* SDRAM_TR */
- sdram->tr = val & 0x018FC01F;
+ s->tr = val & 0x018FC01F;
break;
case 0x94: /* SDRAM_ECCCFG */
- sdram->ecccfg = val & 0x00F00000;
+ s->ecccfg = val & 0x00F00000;
break;
case 0x98: /* SDRAM_ECCESR */
val &= 0xFFF0F000;
- if (sdram->eccesr == 0 && val != 0) {
- qemu_irq_raise(sdram->irq);
- } else if (sdram->eccesr != 0 && val == 0) {
- qemu_irq_lower(sdram->irq);
+ if (s->eccesr == 0 && val != 0) {
+ qemu_irq_raise(s->irq);
+ } else if (s->eccesr != 0 && val == 0) {
+ qemu_irq_lower(s->irq);
}
- sdram->eccesr = val;
+ s->eccesr = val;
break;
default: /* Error */
break;
@@ -387,21 +387,21 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
{
- Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
-
- sdram->addr = 0;
- sdram->bear = 0;
- sdram->besr0 = 0; /* No error */
- sdram->besr1 = 0; /* No error */
- sdram->cfg = 0;
- sdram->ecccfg = 0; /* No ECC */
- sdram->eccesr = 0; /* No error */
- sdram->pmit = 0x07C00000;
- sdram->rtr = 0x05F00000;
- sdram->tr = 0x00854009;
+ Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
+
+ s->addr = 0;
+ s->bear = 0;
+ s->besr0 = 0; /* No error */
+ s->besr1 = 0; /* No error */
+ s->cfg = 0;
+ s->ecccfg = 0; /* No ECC */
+ s->eccesr = 0; /* No error */
+ s->pmit = 0x07C00000;
+ s->rtr = 0x05F00000;
+ s->tr = 0x00854009;
/* We pre-initialize RAM banks */
- sdram->status = 0;
- sdram->cfg = 0x00800000;
+ s->status = 0;
+ s->cfg = 0x00800000;
}
static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
@@ -573,7 +573,7 @@ static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
- Ppc4xxSdramDdr2State *sdram = opaque;
+ Ppc4xxSdramDdr2State *s = opaque;
uint32_t ret = 0;
switch (dcrn) {
@@ -581,9 +581,9 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
case SDRAM_R1BAS:
case SDRAM_R2BAS:
case SDRAM_R3BAS:
- if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
- ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
- sdram->bank[dcrn - SDRAM_R0BAS].size);
+ if (s->bank[dcrn - SDRAM_R0BAS].size) {
+ ret = sdram_ddr2_bcr(s->bank[dcrn - SDRAM_R0BAS].base,
+ s->bank[dcrn - SDRAM_R0BAS].size);
}
break;
case SDRAM_CONF1HB:
@@ -593,16 +593,16 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
case SDRAM_PLBADDUHB:
break;
case SDRAM0_CFGADDR:
- ret = sdram->addr;
+ ret = s->addr;
break;
case SDRAM0_CFGDATA:
- switch (sdram->addr) {
+ switch (s->addr) {
case 0x14: /* SDRAM_MCSTAT (405EX) */
case 0x1F:
ret = 0x80000000;
break;
case 0x21: /* SDRAM_MCOPT2 */
- ret = sdram->mcopt2;
+ ret = s->mcopt2;
break;
case 0x40: /* SDRAM_MB0CF */
ret = 0x00008001;
@@ -628,7 +628,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
- Ppc4xxSdramDdr2State *sdram = opaque;
+ Ppc4xxSdramDdr2State *s = opaque;
switch (dcrn) {
case SDRAM_R0BAS:
@@ -642,25 +642,25 @@ static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
case SDRAM_PLBADDUHB:
break;
case SDRAM0_CFGADDR:
- sdram->addr = val;
+ s->addr = val;
break;
case SDRAM0_CFGDATA:
- switch (sdram->addr) {
+ switch (s->addr) {
case 0x00: /* B0CR */
break;
case 0x21: /* SDRAM_MCOPT2 */
- if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
+ if (!(s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
(val & SDRAM_DDR2_MCOPT2_DCEN)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_ddr2_map_bcr(sdram);
- sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
- } else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
+ sdram_ddr2_map_bcr(s);
+ s->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
+ } else if ((s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
!(val & SDRAM_DDR2_MCOPT2_DCEN)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_ddr2_unmap_bcr(sdram);
- sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
+ sdram_ddr2_unmap_bcr(s);
+ s->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
}
break;
default:
@@ -674,10 +674,10 @@ static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
{
- Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev);
+ Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
- sdram->addr = 0;
- sdram->mcopt2 = 0;
+ s->addr = 0;
+ s->mcopt2 = 0;
}
static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v5 18/21] ppc4xx_sdram: Rename local state variable for brevity
2022-09-18 20:24 ` [PATCH v5 18/21] ppc4xx_sdram: Rename local state variable for brevity BALATON Zoltan
@ 2022-09-18 20:51 ` Philippe Mathieu-Daudé via
0 siblings, 0 replies; 28+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-09-18 20:51 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: clg, Daniel Henrique Barboza, Peter Maydell
On 18/9/22 22:24, BALATON Zoltan wrote:
> Rename the sdram local state variable to s in dcr read/write functions
> and reset methods for better readability and to match realize methods.
> Other places not converted will be changed or removed in subsequent
> patches.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/ppc4xx_sdram.c | 158 +++++++++++++++++++++---------------------
> 1 file changed, 79 insertions(+), 79 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v5 19/21] ppc4xx_sdram: Generalise bank setup
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (17 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 18/21] ppc4xx_sdram: Rename local state variable for brevity BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 20/21] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling BALATON Zoltan
` (2 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Currently only base and size are set on initial bank creation and bcr
value is computed on mapping the region. Set bcr at init so the bcr
encoding method becomes local to the controller model and mapping and
unmapping can operate on the bank so it can be shared between
different controller models. This patch converts the DDR2 controller.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc4xx_sdram.c | 91 ++++++++++++++++++++++---------------------
hw/ppc/trace-events | 1 +
2 files changed, 48 insertions(+), 44 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index 3b2d01a144..0d4b4f398f 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -106,6 +106,7 @@ static void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
static void sdram_bank_map(Ppc4xxSdramBank *bank)
{
+ trace_ppc4xx_sdram_map(bank->base, bank->size);
memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
memory_region_add_subregion(&bank->container, 0, &bank->ram);
memory_region_add_subregion(get_system_memory(), bank->base,
@@ -114,11 +115,26 @@ static void sdram_bank_map(Ppc4xxSdramBank *bank)
static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
{
+ trace_ppc4xx_sdram_unmap(bank->base, bank->size);
memory_region_del_subregion(get_system_memory(), &bank->container);
memory_region_del_subregion(&bank->container, &bank->ram);
object_unparent(OBJECT(&bank->container));
}
+static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr,
+ hwaddr base, hwaddr size, int enabled)
+{
+ if (memory_region_is_mapped(&bank->container)) {
+ sdram_bank_unmap(bank);
+ }
+ bank->bcr = bcr;
+ bank->base = base;
+ bank->size = size;
+ if (enabled && (bcr & 1)) {
+ sdram_bank_map(bank);
+ }
+}
+
enum {
SDRAM0_CFGADDR = 0x010,
SDRAM0_CFGDATA = 0x011,
@@ -456,6 +472,8 @@ void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s)
/*****************************************************************************/
/* DDR2 SDRAM controller */
+#define SDRAM_DDR2_BCR_MASK 0xffe0ffc1
+
enum {
SDRAM_R0BAS = 0x40,
SDRAM_R1BAS,
@@ -529,48 +547,6 @@ static hwaddr sdram_ddr2_size(uint32_t bcr)
return size;
}
-static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i,
- uint32_t bcr, int enabled)
-{
- if (sdram->bank[i].bcr & 1) {
- /* First unmap RAM if enabled */
- trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
- sdram_ddr2_size(sdram->bank[i].bcr));
- sdram_bank_unmap(&sdram->bank[i]);
- }
- sdram->bank[i].bcr = bcr & 0xffe0ffc1;
- if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
- sdram_bank_map(&sdram->bank[i]);
- }
-}
-
-static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size) {
- sdram_ddr2_set_bcr(sdram, i,
- sdram_ddr2_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
- } else {
- sdram_ddr2_set_bcr(sdram, i, 0, 0);
- }
- }
-}
-
-static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size) {
- sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
- }
- }
-}
-
static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
Ppc4xxSdramDdr2State *s = opaque;
@@ -629,6 +605,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
Ppc4xxSdramDdr2State *s = opaque;
+ int i;
switch (dcrn) {
case SDRAM_R0BAS:
@@ -653,13 +630,25 @@ static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
(val & SDRAM_DDR2_MCOPT2_DCEN)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_ddr2_map_bcr(s);
+ for (i = 0; i < s->nbanks; i++) {
+ if (s->bank[i].size) {
+ sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
+ s->bank[i].base, s->bank[i].size,
+ 1);
+ }
+ }
s->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
} else if ((s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
!(val & SDRAM_DDR2_MCOPT2_DCEN)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_ddr2_unmap_bcr(s);
+ for (i = 0; i < s->nbanks; i++) {
+ if (s->bank[i].size) {
+ sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
+ s->bank[i].base, s->bank[i].size,
+ 0);
+ }
+ }
s->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
}
break;
@@ -688,6 +677,7 @@ static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
32 * MiB, 16 * MiB, 8 * MiB, 0
};
+ int i;
if (s->nbanks < 1 || s->nbanks > 4) {
error_setg(errp, "Invalid number of RAM banks");
@@ -698,6 +688,19 @@ static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
return;
}
ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+ for (i = 0; i < s->nbanks; i++) {
+ if (s->bank[i].size) {
+ s->bank[i].bcr = sdram_ddr2_bcr(s->bank[i].base, s->bank[i].size);
+ s->bank[i].bcr &= SDRAM_DDR2_BCR_MASK;
+ sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
+ s->bank[i].base, s->bank[i].size, 0);
+ } else {
+ sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0);
+ }
+ trace_ppc4xx_sdram_init(sdram_ddr2_base(s->bank[i].bcr),
+ sdram_ddr2_size(s->bank[i].bcr),
+ s->bank[i].bcr);
+ }
ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index a07d5aca0f..3b3e4211d4 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -179,3 +179,4 @@ ppc405ep_clocks_setup(const char *trace) "%s"
ppc4xx_sdram_enable(const char *trace) "%s SDRAM controller"
ppc4xx_sdram_unmap(uint64_t addr, uint64_t size) "Unmap RAM area 0x%" PRIx64 " size 0x%" PRIx64
ppc4xx_sdram_map(uint64_t addr, uint64_t size) "Map RAM area 0x%" PRIx64 " size 0x%" PRIx64
+ppc4xx_sdram_init(uint64_t base, uint64_t size, uint32_t bcr) "Init RAM area 0x%" PRIx64 " size 0x%" PRIx64 " bcr 0x%x"
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 20/21] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (18 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 19/21] ppc4xx_sdram: Generalise bank setup BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:24 ` [PATCH v5 21/21] ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks() BALATON Zoltan
2022-09-18 20:33 ` [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups Philippe Mathieu-Daudé via
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Use the generic bank handling introduced in previous patch in the DDR
SDRAM controller too. This also fixes previously broken region unmap
due to sdram_ddr_unmap_bcr() ignoring container region so it crashed
with an assert when the guest tried to disable the controller.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc4xx_sdram.c | 98 ++++++++++++++++---------------------------
1 file changed, 37 insertions(+), 61 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index 0d4b4f398f..2ef363d5e6 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -142,6 +142,8 @@ enum {
/*****************************************************************************/
/* DDR SDRAM controller */
+#define SDRAM_DDR_BCR_MASK 0xFFDEE001
+
static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -200,58 +202,6 @@ static hwaddr sdram_ddr_size(uint32_t bcr)
return size;
}
-static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
- uint32_t bcr, int enabled)
-{
- if (sdram->bank[i].bcr & 1) {
- /* Unmap RAM */
- trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
- sdram_ddr_size(sdram->bank[i].bcr));
- memory_region_del_subregion(get_system_memory(),
- &sdram->bank[i].container);
- memory_region_del_subregion(&sdram->bank[i].container,
- &sdram->bank[i].ram);
- object_unparent(OBJECT(&sdram->bank[i].container));
- }
- sdram->bank[i].bcr = bcr & 0xFFDEE001;
- if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr));
- memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
- sdram_ddr_size(bcr));
- memory_region_add_subregion(&sdram->bank[i].container, 0,
- &sdram->bank[i].ram);
- memory_region_add_subregion(get_system_memory(),
- sdram_ddr_base(bcr),
- &sdram->bank[i].container);
- }
-}
-
-static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size != 0) {
- sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
- } else {
- sdram_ddr_set_bcr(sdram, i, 0, 0);
- }
- }
-}
-
-static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
- sdram_ddr_size(sdram->bank[i].bcr));
- memory_region_del_subregion(get_system_memory(),
- &sdram->bank[i].ram);
- }
-}
-
static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
{
Ppc4xxSdramDdrState *s = opaque;
@@ -322,6 +272,7 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
{
Ppc4xxSdramDdrState *s = opaque;
+ int i;
switch (dcrn) {
case SDRAM0_CFGADDR:
@@ -343,12 +294,24 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
if (!(s->cfg & 0x80000000) && (val & 0x80000000)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_ddr_map_bcr(s);
+ for (i = 0; i < s->nbanks; i++) {
+ if (s->bank[i].size) {
+ sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
+ s->bank[i].base, s->bank[i].size,
+ 1);
+ }
+ }
s->status &= ~0x80000000;
} else if ((s->cfg & 0x80000000) && !(val & 0x80000000)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_ddr_unmap_bcr(s);
+ for (i = 0; i < s->nbanks; i++) {
+ if (s->bank[i].size) {
+ sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
+ s->bank[i].base, s->bank[i].size,
+ 0);
+ }
+ }
s->status |= 0x80000000;
}
if (!(s->cfg & 0x40000000) && (val & 0x40000000)) {
@@ -368,16 +331,16 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
s->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
- sdram_ddr_set_bcr(s, 0, val, s->cfg & 0x80000000);
- break;
case 0x44: /* SDRAM_B1CR */
- sdram_ddr_set_bcr(s, 1, val, s->cfg & 0x80000000);
- break;
case 0x48: /* SDRAM_B2CR */
- sdram_ddr_set_bcr(s, 2, val, s->cfg & 0x80000000);
- break;
case 0x4C: /* SDRAM_B3CR */
- sdram_ddr_set_bcr(s, 3, val, s->cfg & 0x80000000);
+ i = (s->addr - 0x40) / 4;
+ val &= SDRAM_DDR_BCR_MASK;
+ if (s->bank[i].size) {
+ sdram_bank_set_bcr(&s->bank[i], val,
+ sdram_ddr_base(val), sdram_ddr_size(val),
+ s->cfg & 0x80000000);
+ }
break;
case 0x80: /* SDRAM_TR */
s->tr = val & 0x018FC01F;
@@ -427,6 +390,7 @@ static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
const ram_addr_t valid_bank_sizes[] = {
256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
};
+ int i;
if (s->nbanks < 1 || s->nbanks > 4) {
error_setg(errp, "Invalid number of RAM banks");
@@ -437,6 +401,18 @@ static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
return;
}
ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+ for (i = 0; i < s->nbanks; i++) {
+ if (s->bank[i].size) {
+ s->bank[i].bcr = sdram_ddr_bcr(s->bank[i].base, s->bank[i].size);
+ sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
+ s->bank[i].base, s->bank[i].size, 0);
+ } else {
+ sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0);
+ }
+ trace_ppc4xx_sdram_init(sdram_ddr_base(s->bank[i].bcr),
+ sdram_ddr_size(s->bank[i].bcr),
+ s->bank[i].bcr);
+ }
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 21/21] ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks()
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (19 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 20/21] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling BALATON Zoltan
@ 2022-09-18 20:24 ` BALATON Zoltan
2022-09-18 20:33 ` [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups Philippe Mathieu-Daudé via
21 siblings, 0 replies; 28+ messages in thread
From: BALATON Zoltan @ 2022-09-18 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Do not exit from ppc4xx_sdram_banks() but report error via an errp
parameter instead.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/ppc/ppc4xx_sdram.c | 28 +++++++++++++++++++---------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index 2ef363d5e6..543d47aec3 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -53,10 +53,12 @@
* must be one of a small set of sizes. The number of banks and the supported
* sizes varies by SoC.
*/
-static void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
+static bool ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
Ppc4xxSdramBank ram_banks[],
- const ram_addr_t sdram_bank_sizes[])
+ const ram_addr_t sdram_bank_sizes[],
+ Error **errp)
{
+ ERRP_GUARD();
ram_addr_t size_left = memory_region_size(ram);
ram_addr_t base = 0;
ram_addr_t bank_size;
@@ -94,14 +96,16 @@ static void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
sdram_bank_sizes[i] / MiB,
sdram_bank_sizes[i + 1] ? ", " : "");
}
- error_report("at most %d bank%s of %s MiB each supported",
- nr_banks, nr_banks == 1 ? "" : "s", s->str);
- error_printf("Possible valid RAM size: %" PRIi64 " MiB\n",
- used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
+ error_setg(errp, "Invalid SDRAM banks");
+ error_append_hint(errp, "at most %d bank%s of %s MiB each supported\n",
+ nr_banks, nr_banks == 1 ? "" : "s", s->str);
+ error_append_hint(errp, "Possible valid RAM size: %" PRIi64 " MiB\n",
+ used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
g_string_free(s, true);
- exit(EXIT_FAILURE);
+ return false;
}
+ return true;
}
static void sdram_bank_map(Ppc4xxSdramBank *bank)
@@ -400,7 +404,10 @@ static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
error_setg(errp, "Missing dram memory region");
return;
}
- ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+ if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank,
+ valid_bank_sizes, errp)) {
+ return;
+ }
for (i = 0; i < s->nbanks; i++) {
if (s->bank[i].size) {
s->bank[i].bcr = sdram_ddr_bcr(s->bank[i].base, s->bank[i].size);
@@ -663,7 +670,10 @@ static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
error_setg(errp, "Missing dram memory region");
return;
}
- ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+ if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank,
+ valid_bank_sizes, errp)) {
+ return;
+ }
for (i = 0; i < s->nbanks; i++) {
if (s->bank[i].size) {
s->bank[i].bcr = sdram_ddr2_bcr(s->bank[i].base, s->bank[i].size);
--
2.30.4
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups
2022-09-18 20:24 [PATCH v5 00/21] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (20 preceding siblings ...)
2022-09-18 20:24 ` [PATCH v5 21/21] ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks() BALATON Zoltan
@ 2022-09-18 20:33 ` Philippe Mathieu-Daudé via
21 siblings, 0 replies; 28+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-09-18 20:33 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: clg, Daniel Henrique Barboza, Peter Maydell
On 18/9/22 22:24, BALATON Zoltan wrote:
> This is the end of the QOMify series started by Cédric. This series
> handles the SDRAM controller models to clean them up, QOMify and unify
> them and at least partially clean up the mess that has accumulated
> around these in the past. This includes the not yet merged patches
> from the last series and new ones that change the DDR2 version used by
> sam460ex.
>
> v5: Add functions the enable sdram controller and call it from boards
> v4: address more review comments
> v3: Fix patches that got squashed during rebase
> v2: address some review comments and try to avoid compile problem with
> gcc 12.2 (untested)
When respining a large series with various patches already ready, you
could mention "missing review: patches F, L, N..." in the cover letter
so we directly go look at those.
^ permalink raw reply [flat|nested] 28+ messages in thread