* Re: [PATCH v2 0/4] ASoC: qcom: display port changes
2024-05-24 12:50 0% ` Srinivas Kandagatla
@ 2024-05-25 7:12 0% ` Xilin Wu
0 siblings, 0 replies; 200+ results
From: Xilin Wu @ 2024-05-25 7:12 UTC (permalink / raw)
To: Srinivas Kandagatla, broonie
Cc: perex, tiwai, lgirdwood, alsa-devel, linux-kernel
Hi Srini,
On 2024/5/24 20:50, Srinivas Kandagatla wrote:
> Hi Xilin,
>
> On 23/05/2024 05:09, Xilin Wu wrote:
>>>
>>> Srinivas Kandagatla (4):
>>> ASoC: qcom: q6dsp: parse Display port tokens
>>> ASoC: qcom: common: add Display port Jack function
>>> ASoC: qcom: sc8280xp: add Display port Jack
>>> ASoC: qcom: sm8250: fix a typo in function name
>>>
>>> sound/soc/qcom/common.c | 29 +++++++++++++++++++++++++++++
>>> sound/soc/qcom/common.h | 3 +++
>>> sound/soc/qcom/qdsp6/topology.c | 26 ++++++++++++++++++++++++++
>>> sound/soc/qcom/sc8280xp.c | 14 ++++++++++++++
>>> sound/soc/qcom/sm8250.c | 4 ++--
>>> 5 files changed, 74 insertions(+), 2 deletions(-)
>>>
>>
>> Hi Srini,
>>
>> I tested this series on SM8550 with tplg in [1] and ucm in [2]. But
>> the kernel output errors attached below. Headphone does work properly
>> without DisplayPort in the ucm.
>>
>> What could be the possible cause of this? Is there any significant
>> change from sc8280xp to sm8550?
>>
>> --
>> Thanks,
>> Xilin Wu
>>
>> [1]
>> https://github.com/edk2-porting/audioreach-topology/blob/sakuramist/QCS8550-AYN-ODIN2.m4
>> [2]
>> https://github.com/strongtz/alsa-ucm-conf/blob/odin2/ucm2/Qualcomm/sm8550/HiFi.conf
>>
>> [ 1552.313713] qcom-apm gprsvc:service:2:1: Error (1) Processing
>> 0x01001000 cmd
>> [ 1552.313730] qcom-apm gprsvc:service:2:1: DSP returned error[1001000] 1
>> [ 1552.314455] qcom-apm gprsvc:service:2:1: Error (1) Processing
>
> Is the DP cable connected?
I'm sure that the cable is connected and I have desktop on external display.
If it's not connected, kernel gives the following error when using aplay:
hdmi-audio-codec hdmi-audio-codec.1.auto: ASoC: error at
snd_soc_dai_hw_params on i2s-hifi: -22
>
> if its not connected the dsp will throw this error.
>
> due to this issue I did workaround this issue by modeling it as
> conflicting device to Speaker in x13s ucm.
>
> I see in your ucm setup its not the case.
> which is why you might be hitting this issue.
>
> Can you try
> amixer -c 0 cset iface=MIXER,name='DISPLAY_PORT_RX_0 Audio Mixer
> MultiMedia2' 1
> aplay -D plughw:0,1 some-wav-file.wav
>
> both with and without display connected.
>
aplay always gives the following error:
Playing WAVE 'Summer.wav' : Signed 16 bit Little Endian, Rate 44100 Hz,
Stereo
aplay: set_params:1456: Unable to install hw params:
ACCESS: RW_INTERLEAVED
FORMAT: S16_LE
SUBFORMAT: STD
SAMPLE_BITS: 16
FRAME_BITS: 32
CHANNELS: 2
RATE: 44100
PERIOD_TIME: (42666 42667)
PERIOD_SIZE: (1881 1882)
PERIOD_BYTES: (7524 7528)
PERIODS: (3 5)
BUFFER_TIME: (170657 170658)
BUFFER_SIZE: 7526
BUFFER_BYTES: 30104
TICK_TIME: 0
and kernel gives the following when display is connected:
[drm:dp_catalog_audio_config_sdp] sdp_cfg = 0x100066
[drm:dp_catalog_audio_config_sdp] sdp_cfg2 = 0x1b800004
[drm:dp_audio_hw_params] Header Byte 1: value = 0xce020000, parity_byte
= 0xce
[drm:dp_audio_hw_params] Header Byte 2: value = 0x67010000, parity_byte
= 0x0
[drm:dp_audio_hw_params] Header Byte 3: value = 0x67010000, parity_byte
= 0x67
[drm:dp_audio_hw_params] Header Byte 1: value = 0x67010000, parity_byte
= 0x67
[drm:dp_audio_hw_params] Header Byte 2: value = 0x33443517, parity_byte
= 0x35
[drm:dp_audio_hw_params] Header Byte 3: value = 0x33443517, parity_byte
= 0x33
[drm:dp_audio_hw_params] Header Byte 1: value = 0x84840000, parity_byte
= 0x84
[drm:dp_audio_hw_params] Header Byte 2: value = 0x3344d71b, parity_byte
= 0xd7
[drm:dp_audio_hw_params] Header Byte 3: value = 0x44, parity_byte = 0x33
[drm:dp_audio_hw_params] Header Byte 1: value = 0xd8050000, parity_byte
= 0xd8
[drm:dp_audio_hw_params] Header Byte 2: value = 0x4b0f, parity_byte = 0x4b
[drm:dp_audio_hw_params] Header Byte 3: value = 0x4b0f, parity_byte = 0x0
[drm:dp_audio_hw_params] Header Byte 1: value = 0x71060000, parity_byte
= 0x71
[drm:dp_audio_hw_params] Header Byte 2: value = 0x4b0f, parity_byte = 0x4b
[drm:dp_catalog_audio_config_acr] select: 0x3, acr_ctrl: 0x80004130
[drm:dp_catalog_audio_sfe_level] mainlink_level = 0xa08,
safe_to_exit_level = 0x8
[drm:dp_catalog_audio_enable] dp_audio_cfg = 0xc1
qcom-apm gprsvc:service:2:1: Error (1) Processing 0x01001006 cmd
qcom-apm gprsvc:service:2:1: DSP returned error[1001006] 1
qcom-apm gprsvc:service:2:1: Error (1) Processing 0x01001006 cmd
qcom-apm gprsvc:service:2:1: DSP returned error[1001006] 1
qcom-apm gprsvc:service:2:1: Error (1) Processing 0x01001001 cmd
qcom-apm gprsvc:service:2:1: DSP returned error[1001001] 1
q6apm-lpass-dais 30000000.remoteproc:glink-edge:gpr:service@1:bedais:
Failed to prepare Graph -22
q6apm-lpass-dais 30000000.remoteproc:glink-edge:gpr:service@1:bedais:
ASoC: error at snd_soc_pcm_dai_prepare on DISPLAY_PORT_RX_0: -22
[drm:dp_catalog_audio_enable] dp_audio_cfg = 0xc0
>
> --srini
>
>
>
>> 0x01001006 cmd
>> [ 1552.314463] qcom-apm gprsvc:service:2:1: DSP returned error[1001006] 1
>> [ 1552.315496] qcom-apm gprsvc:service:2:1: Error (1) Processing
>> 0x01001006 cmd
>> [ 1552.315506] qcom-apm gprsvc:service:2:1: DSP returned error[1001006] 1
>> [ 1552.316033] qcom-apm gprsvc:service:2:1: Error (1) Processing
>> 0x01001001 cmd
>> [ 1552.316042] qcom-apm gprsvc:service:2:1: DSP returned error[1001001] 1
>> [ 1552.316045] q6apm-lpass-dais
>> 30000000.remoteproc:glink-edge:gpr:service@1:bedais: Failed to prepare
>> Graph -22
>> [ 1552.316047] q6apm-lpass-dais
>> 30000000.remoteproc:glink-edge:gpr:service@1:bedais: ASoC: error at
>> snd_soc_pcm_dai_prepare on DISPLAY_PORT_RX_0: -22
--
Thanks,
Xilin Wu
^ permalink raw reply [relevance 0%]
* [PATCH v10 4/5] iommu/arm-smmu: add ACTLR data and support for SM8550
2024-05-24 13:17 5% ` Bibek Kumar Patro
@ 2024-05-24 13:17 14% ` Bibek Kumar Patro
-1 siblings, 0 replies; 200+ results
From: Bibek Kumar Patro @ 2024-05-24 13:17 UTC (permalink / raw)
To: robdclark, will, robin.murphy, joro, jgg, jsnitsel, robh,
krzysztof.kozlowski, quic_c_gdjako, dmitry.baryshkov,
konrad.dybcio
Cc: iommu, linux-arm-msm, linux-arm-kernel, linux-kernel, Bibek Kumar Patro
Add ACTLR data table for SM8550 along with support for
same including SM8550 specific implementation operations.
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 89 ++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 77c9abffe07d..b4521471ffe9 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -23,6 +23,85 @@
#define CPRE (1 << 1)
#define CMTLB (1 << 0)
+#define PREFETCH_SHIFT 8
+#define PREFETCH_DEFAULT 0
+#define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT)
+#define PREFETCH_MODERATE (2 << PREFETCH_SHIFT)
+#define PREFETCH_DEEP (3 << PREFETCH_SHIFT)
+
+static const struct actlr_config sm8550_apps_actlr_cfg[] = {
+ { 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x0800, 0x0020, PREFETCH_DEFAULT | CMTLB },
+ { 0x1800, 0x00c0, PREFETCH_DEFAULT | CMTLB },
+ { 0x1820, 0x0000, PREFETCH_DEFAULT | CMTLB },
+ { 0x1860, 0x0000, PREFETCH_DEFAULT | CMTLB },
+ { 0x0c01, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c02, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c03, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c04, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c05, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c06, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c07, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c08, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c09, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c0c, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c0d, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c0e, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c0f, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1961, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1962, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1963, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1964, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1965, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1966, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1967, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1968, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1969, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x196c, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x196d, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x196e, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x196f, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c1, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c2, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c3, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c4, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c5, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c6, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c7, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c8, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c9, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19cc, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19cd, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19ce, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19cf, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1c00, 0x0002, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1c01, 0x0000, PREFETCH_DEFAULT | CMTLB },
+ { 0x1920, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1923, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1924, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1940, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1941, 0x0004, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1943, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1944, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1947, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+};
+
+static const struct actlr_config sm8550_gfx_actlr_cfg[] = {
+ { 0x0000, 0x03ff, PREFETCH_DEEP | CPRE | CMTLB },
+};
+
+static const struct actlr_variant sm8550_actlr[] = {
+ {
+ .io_start = 0x15000000,
+ .actlrcfg = sm8550_apps_actlr_cfg,
+ .num_actlrcfg = ARRAY_SIZE(sm8550_apps_actlr_cfg)
+ }, {
+ .io_start = 0x03da0000,
+ .actlrcfg = sm8550_gfx_actlr_cfg,
+ .num_actlrcfg = ARRAY_SIZE(sm8550_gfx_actlr_cfg)
+ },
+};
static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
{
@@ -606,6 +685,15 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
/* Also no debug configuration. */
};
+
+static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = {
+ .impl = &qcom_smmu_500_impl,
+ .adreno_impl = &qcom_adreno_smmu_500_impl,
+ .cfg = &qcom_smmu_impl0_cfg,
+ .actlrvar = sm8550_actlr,
+ .num_smmu = ARRAY_SIZE(sm8550_actlr),
+};
+
static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
.impl = &qcom_smmu_500_impl,
.adreno_impl = &qcom_adreno_smmu_500_impl,
@@ -640,6 +728,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm8550-smmu-500", .data = &sm8550_smmu_500_impl0_data },
{ .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
{ }
};
--
2.34.1
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^ permalink raw reply related [relevance 14%]
* [PATCH v10 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs
@ 2024-05-24 13:17 5% ` Bibek Kumar Patro
0 siblings, 0 replies; 200+ results
From: Bibek Kumar Patro @ 2024-05-24 13:17 UTC (permalink / raw)
To: robdclark, will, robin.murphy, joro, jgg, jsnitsel, robh,
krzysztof.kozlowski, quic_c_gdjako, dmitry.baryshkov,
konrad.dybcio
Cc: iommu, linux-arm-msm, linux-arm-kernel, linux-kernel, Bibek Kumar Patro
This patch series consist of five parts and covers the following:
1. Re-enable context caching for Qualcomm SoCs to retain prefetcher
settings during reset and runtime suspend.
2. Remove cfg inside qcom_smmu structure and replace it with single
pointer to qcom_smmu_match_data avoiding replication of multiple
members from same.
3. Introduce intital set of driver changes to implement ACTLR register
for custom prefetcher settings in Qualcomm SoCs.
4. Add ACTLR data and implementation operations for SM8550.
5. Add ACTLR data and implementation operations for SC7280.
Changes in v10 from v9:
- Added reviewed-by tags 1/5,2/5,3/5.
Changes incorporated:
- Remove redundant PRR bit setting from gfx actlr table(patch 4/5,5/5)
as this bit needs special handling in the gfx driver along with
the associated register settings.
Link to discussion on PRR bit:
https://lore.kernel.org/all/f2222714-1e00-424e-946d-c314d55541b8@quicinc.com/
Link to v9:
https://lore.kernel.org/all/20240123144543.9405-1-quic_bibekkum@quicinc.com/
Changes in v9 from v8:
Changes to incorporate suggestions from Konrad as follows:
- Re-wrap struct members of actlr_variant in patch 4/5,5/5
in a cleaner way.
- Move actlr_config members to the header.
Link to v8:
https://lore.kernel.org/all/20240116150411.23876-1-quic_bibekkum@quicinc.com/
Changes in v8 from v7:
- Added reviewed-by tags on patch 1/5, 2/5.
Changes to incorporate suggestions from Pavan and Konrad:
- Remove non necessary extra lines.
- Use num_smmu and num_actlrcfg to store the array size and use the
same to traverse the table and save on sentinel space along with
indentation levels.
- Refactor blocks containing qcom_smmu_set_actlr to remove block
repetition in patch 3/5.
- Change copyright year from 2023 to 2022-2023 in patch 3/5.
- Modify qcom_smmu_match_data.actlrvar and actlr_variant.actlrcfg to
const pointer to a const resource.
- use C99 designated initializers and put the address first.
Link to v7:
https://lore.kernel.org/all/20240109114220.30243-1-quic_bibekkum@quicinc.com/
Changes in v7 from v6:
Changes to incorporate suggestions from Dmitry as follows:
- Use io_start address instead of compatible string to identify the
correct instance by comparing with smmu start address and check for
which smmu the corresponding actlr table is to be picked.
Link to v6:
https://lore.kernel.org/all/20231220133808.5654-1-quic_bibekkum@quicinc.com/
Changes in v6 from v5:
- Remove extra Suggested-by tags.
- Add return check for arm_mmu500_reset in 1/5 as discussed.
Link to v5:
https://lore.kernel.org/all/20231219135947.1623-1-quic_bibekkum@quicinc.com/
Changes in v5 from v4:
New addition:
- Modify copyright year in arm-smmu-qcom.h to 2023 from 2022.
Changes to incorporate suggestions from Dmitry as follows:
- Modify the defines for prefetch in (foo << bar) format
as suggested.(FIELD_PREP could not be used in defines
is not inside any block/function)
Changes to incorporate suggestions from Konrad as follows:
- Shift context caching enablement patch as 1/5 instead of 5/5 to
be picked up as independent patch.
- Fix the codestyle to orient variables in reverse xmas tree format
for patch 1/5.
- Fix variable name in patch 1/5 as suggested.
Link to v4:
https://lore.kernel.org/all/20231215101827.30549-1-quic_bibekkum@quicinc.com/
Changes in v4 from v3:
New addition:
- Remove actlrcfg_size and use NULL end element instead to traverse
the actlr table, as this would be a cleaner approach by removing
redundancy of actlrcfg_size.
- Renaming of actlr set function to arm_smmu_qcom based proprietary
convention.
- break from loop once sid is found and ACTLR value is initialized
in qcom_smmu_set_actlr.
- Modify the GFX prefetch value separating into 2 sensible defines.
- Modify comments for prefetch defines as per SMMU-500 TRM.
Changes to incorporate suggestions from Konrad as follows:
- Use Reverse-Christmas-tree sorting wherever applicable.
- Pass arguments directly to arm_smmu_set_actlr instead of creating
duplicate variables.
- Use array indexing instead of direct pointer addressed by new
addition of eliminating actlrcfg_size.
- Switch the HEX value's case from upper to lower case in SC7280
actlrcfg table.
Changes to incorporate suggestions from Dmitry as follows:
- Separate changes not related to ACTLR support to different commit
with patch 5/5.
- Using pointer to struct for arguments in smr_is_subset().
Changes to incorporate suggestions from Bjorn as follows:
- fix the commit message for patch 2/5 to properly document the
value space to avoid confusion.
Fixed build issues reported by kernel test robot [1] for
arm64-allyesconfig [2].
[1]: https://lore.kernel.org/all/202312011750.Pwca3TWE-lkp@intel.com/
[2]:
https://download.01.org/0day-ci/archive/20231201/202312011750.Pwca3TWE-lkp@intel.com/config
Link to v3:
https://lore.kernel.org/all/20231127145412.3981-1-quic_bibekkum@quicinc.com/
Changes in v3 from v2:
New addition:
- Include patch 3/4 for adding ACTLR support and data for SC7280.
- Add driver changes for actlr support in gpu smmu.
- Add target wise actlr data and implementation ops for gpu smmu.
Changes to incorporate suggestions from Robin as follows:
- Match the ACTLR values with individual corresponding SID instead
of assuming that any SMR will be programmed to match a superset of
the data.
- Instead of replicating each elements from qcom_smmu_match_data to
qcom_smmu structre during smmu device creation, replace the
replicated members with qcom_smmu_match_data structure inside
qcom_smmu structre and handle the dereference in places that
requires them.
Changes to incorporate suggestions from Dmitry and Konrad as follows:
- Maintain actlr table inside a single structure instead of
nested structure.
- Rename prefetch defines to more appropriately describe their
behavior.
- Remove SM8550 specific implementation ops and roll back to default
qcom_smmu_500_impl implementation ops.
- Add back the removed comments which are NAK.
- Fix commit description for patch 4/4.
Link to v2:
https://lore.kernel.org/all/20231114135654.30475-1-quic_bibekkum@quicinc.com/
Changes in v2 from v1:
- Incorporated suggestions on v1 from Dmitry,Konrad,Pratyush.
- Added defines for ACTLR values.
- Linked sm8550 implementation structure to corresponding
compatible string.
- Repackaged actlr value set implementation to separate function.
- Fixed indentation errors.
- Link to v1:
https://lore.kernel.org/all/20231103215124.1095-1-quic_bibekkum@quicinc.com/
Changes in v1 from RFC:
- Incorporated suggestion form Robin on RFC
- Moved the actlr data table into driver, instead of maintaining
it inside soc specific DT and piggybacking on exisiting iommus
property (iommu = <SID, MASK, ACTLR>) to set this value during
smmu probe.
- Link to RFC:
https://lore.kernel.org/all/a01e7e60-6ead-4a9e-ba90-22a8a6bbd03f@quicinc.com/
Bibek Kumar Patro (5):
iommu/arm-smmu: re-enable context caching in smmu reset operation
iommu/arm-smmu: refactor qcom_smmu structure to include single pointer
iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings
iommu/arm-smmu: add ACTLR data and support for SM8550
iommu/arm-smmu: add ACTLR data and support for SC7280
.../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 2 +-
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 223 +++++++++++++++++-
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 18 +-
drivers/iommu/arm/arm-smmu/arm-smmu.c | 5 +-
drivers/iommu/arm/arm-smmu/arm-smmu.h | 5 +
5 files changed, 243 insertions(+), 10 deletions(-)
--
2.34.1
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [relevance 5%]
* [PATCH v10 4/5] iommu/arm-smmu: add ACTLR data and support for SM8550
@ 2024-05-24 13:17 14% ` Bibek Kumar Patro
0 siblings, 0 replies; 200+ results
From: Bibek Kumar Patro @ 2024-05-24 13:17 UTC (permalink / raw)
To: robdclark, will, robin.murphy, joro, jgg, jsnitsel, robh,
krzysztof.kozlowski, quic_c_gdjako, dmitry.baryshkov,
konrad.dybcio
Cc: iommu, linux-arm-msm, linux-arm-kernel, linux-kernel, Bibek Kumar Patro
Add ACTLR data table for SM8550 along with support for
same including SM8550 specific implementation operations.
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 89 ++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 77c9abffe07d..b4521471ffe9 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -23,6 +23,85 @@
#define CPRE (1 << 1)
#define CMTLB (1 << 0)
+#define PREFETCH_SHIFT 8
+#define PREFETCH_DEFAULT 0
+#define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT)
+#define PREFETCH_MODERATE (2 << PREFETCH_SHIFT)
+#define PREFETCH_DEEP (3 << PREFETCH_SHIFT)
+
+static const struct actlr_config sm8550_apps_actlr_cfg[] = {
+ { 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x0800, 0x0020, PREFETCH_DEFAULT | CMTLB },
+ { 0x1800, 0x00c0, PREFETCH_DEFAULT | CMTLB },
+ { 0x1820, 0x0000, PREFETCH_DEFAULT | CMTLB },
+ { 0x1860, 0x0000, PREFETCH_DEFAULT | CMTLB },
+ { 0x0c01, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c02, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c03, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c04, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c05, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c06, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c07, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c08, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c09, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c0c, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c0d, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c0e, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x0c0f, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1961, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1962, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1963, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1964, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1965, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1966, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1967, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1968, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1969, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x196c, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x196d, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x196e, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x196f, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c1, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c2, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c3, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c4, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c5, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c6, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c7, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c8, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19c9, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19cc, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19cd, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19ce, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x19cf, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+ { 0x1c00, 0x0002, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1c01, 0x0000, PREFETCH_DEFAULT | CMTLB },
+ { 0x1920, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1923, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1924, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1940, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1941, 0x0004, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1943, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1944, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+ { 0x1947, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+};
+
+static const struct actlr_config sm8550_gfx_actlr_cfg[] = {
+ { 0x0000, 0x03ff, PREFETCH_DEEP | CPRE | CMTLB },
+};
+
+static const struct actlr_variant sm8550_actlr[] = {
+ {
+ .io_start = 0x15000000,
+ .actlrcfg = sm8550_apps_actlr_cfg,
+ .num_actlrcfg = ARRAY_SIZE(sm8550_apps_actlr_cfg)
+ }, {
+ .io_start = 0x03da0000,
+ .actlrcfg = sm8550_gfx_actlr_cfg,
+ .num_actlrcfg = ARRAY_SIZE(sm8550_gfx_actlr_cfg)
+ },
+};
static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
{
@@ -606,6 +685,15 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
/* Also no debug configuration. */
};
+
+static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = {
+ .impl = &qcom_smmu_500_impl,
+ .adreno_impl = &qcom_adreno_smmu_500_impl,
+ .cfg = &qcom_smmu_impl0_cfg,
+ .actlrvar = sm8550_actlr,
+ .num_smmu = ARRAY_SIZE(sm8550_actlr),
+};
+
static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
.impl = &qcom_smmu_500_impl,
.adreno_impl = &qcom_adreno_smmu_500_impl,
@@ -640,6 +728,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
+ { .compatible = "qcom,sm8550-smmu-500", .data = &sm8550_smmu_500_impl0_data },
{ .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
{ }
};
--
2.34.1
^ permalink raw reply related [relevance 14%]
* [PATCH v10 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs
@ 2024-05-24 13:17 5% ` Bibek Kumar Patro
0 siblings, 0 replies; 200+ results
From: Bibek Kumar Patro @ 2024-05-24 13:17 UTC (permalink / raw)
To: robdclark, will, robin.murphy, joro, jgg, jsnitsel, robh,
krzysztof.kozlowski, quic_c_gdjako, dmitry.baryshkov,
konrad.dybcio
Cc: iommu, linux-arm-msm, linux-arm-kernel, linux-kernel, Bibek Kumar Patro
This patch series consist of five parts and covers the following:
1. Re-enable context caching for Qualcomm SoCs to retain prefetcher
settings during reset and runtime suspend.
2. Remove cfg inside qcom_smmu structure and replace it with single
pointer to qcom_smmu_match_data avoiding replication of multiple
members from same.
3. Introduce intital set of driver changes to implement ACTLR register
for custom prefetcher settings in Qualcomm SoCs.
4. Add ACTLR data and implementation operations for SM8550.
5. Add ACTLR data and implementation operations for SC7280.
Changes in v10 from v9:
- Added reviewed-by tags 1/5,2/5,3/5.
Changes incorporated:
- Remove redundant PRR bit setting from gfx actlr table(patch 4/5,5/5)
as this bit needs special handling in the gfx driver along with
the associated register settings.
Link to discussion on PRR bit:
https://lore.kernel.org/all/f2222714-1e00-424e-946d-c314d55541b8@quicinc.com/
Link to v9:
https://lore.kernel.org/all/20240123144543.9405-1-quic_bibekkum@quicinc.com/
Changes in v9 from v8:
Changes to incorporate suggestions from Konrad as follows:
- Re-wrap struct members of actlr_variant in patch 4/5,5/5
in a cleaner way.
- Move actlr_config members to the header.
Link to v8:
https://lore.kernel.org/all/20240116150411.23876-1-quic_bibekkum@quicinc.com/
Changes in v8 from v7:
- Added reviewed-by tags on patch 1/5, 2/5.
Changes to incorporate suggestions from Pavan and Konrad:
- Remove non necessary extra lines.
- Use num_smmu and num_actlrcfg to store the array size and use the
same to traverse the table and save on sentinel space along with
indentation levels.
- Refactor blocks containing qcom_smmu_set_actlr to remove block
repetition in patch 3/5.
- Change copyright year from 2023 to 2022-2023 in patch 3/5.
- Modify qcom_smmu_match_data.actlrvar and actlr_variant.actlrcfg to
const pointer to a const resource.
- use C99 designated initializers and put the address first.
Link to v7:
https://lore.kernel.org/all/20240109114220.30243-1-quic_bibekkum@quicinc.com/
Changes in v7 from v6:
Changes to incorporate suggestions from Dmitry as follows:
- Use io_start address instead of compatible string to identify the
correct instance by comparing with smmu start address and check for
which smmu the corresponding actlr table is to be picked.
Link to v6:
https://lore.kernel.org/all/20231220133808.5654-1-quic_bibekkum@quicinc.com/
Changes in v6 from v5:
- Remove extra Suggested-by tags.
- Add return check for arm_mmu500_reset in 1/5 as discussed.
Link to v5:
https://lore.kernel.org/all/20231219135947.1623-1-quic_bibekkum@quicinc.com/
Changes in v5 from v4:
New addition:
- Modify copyright year in arm-smmu-qcom.h to 2023 from 2022.
Changes to incorporate suggestions from Dmitry as follows:
- Modify the defines for prefetch in (foo << bar) format
as suggested.(FIELD_PREP could not be used in defines
is not inside any block/function)
Changes to incorporate suggestions from Konrad as follows:
- Shift context caching enablement patch as 1/5 instead of 5/5 to
be picked up as independent patch.
- Fix the codestyle to orient variables in reverse xmas tree format
for patch 1/5.
- Fix variable name in patch 1/5 as suggested.
Link to v4:
https://lore.kernel.org/all/20231215101827.30549-1-quic_bibekkum@quicinc.com/
Changes in v4 from v3:
New addition:
- Remove actlrcfg_size and use NULL end element instead to traverse
the actlr table, as this would be a cleaner approach by removing
redundancy of actlrcfg_size.
- Renaming of actlr set function to arm_smmu_qcom based proprietary
convention.
- break from loop once sid is found and ACTLR value is initialized
in qcom_smmu_set_actlr.
- Modify the GFX prefetch value separating into 2 sensible defines.
- Modify comments for prefetch defines as per SMMU-500 TRM.
Changes to incorporate suggestions from Konrad as follows:
- Use Reverse-Christmas-tree sorting wherever applicable.
- Pass arguments directly to arm_smmu_set_actlr instead of creating
duplicate variables.
- Use array indexing instead of direct pointer addressed by new
addition of eliminating actlrcfg_size.
- Switch the HEX value's case from upper to lower case in SC7280
actlrcfg table.
Changes to incorporate suggestions from Dmitry as follows:
- Separate changes not related to ACTLR support to different commit
with patch 5/5.
- Using pointer to struct for arguments in smr_is_subset().
Changes to incorporate suggestions from Bjorn as follows:
- fix the commit message for patch 2/5 to properly document the
value space to avoid confusion.
Fixed build issues reported by kernel test robot [1] for
arm64-allyesconfig [2].
[1]: https://lore.kernel.org/all/202312011750.Pwca3TWE-lkp@intel.com/
[2]:
https://download.01.org/0day-ci/archive/20231201/202312011750.Pwca3TWE-lkp@intel.com/config
Link to v3:
https://lore.kernel.org/all/20231127145412.3981-1-quic_bibekkum@quicinc.com/
Changes in v3 from v2:
New addition:
- Include patch 3/4 for adding ACTLR support and data for SC7280.
- Add driver changes for actlr support in gpu smmu.
- Add target wise actlr data and implementation ops for gpu smmu.
Changes to incorporate suggestions from Robin as follows:
- Match the ACTLR values with individual corresponding SID instead
of assuming that any SMR will be programmed to match a superset of
the data.
- Instead of replicating each elements from qcom_smmu_match_data to
qcom_smmu structre during smmu device creation, replace the
replicated members with qcom_smmu_match_data structure inside
qcom_smmu structre and handle the dereference in places that
requires them.
Changes to incorporate suggestions from Dmitry and Konrad as follows:
- Maintain actlr table inside a single structure instead of
nested structure.
- Rename prefetch defines to more appropriately describe their
behavior.
- Remove SM8550 specific implementation ops and roll back to default
qcom_smmu_500_impl implementation ops.
- Add back the removed comments which are NAK.
- Fix commit description for patch 4/4.
Link to v2:
https://lore.kernel.org/all/20231114135654.30475-1-quic_bibekkum@quicinc.com/
Changes in v2 from v1:
- Incorporated suggestions on v1 from Dmitry,Konrad,Pratyush.
- Added defines for ACTLR values.
- Linked sm8550 implementation structure to corresponding
compatible string.
- Repackaged actlr value set implementation to separate function.
- Fixed indentation errors.
- Link to v1:
https://lore.kernel.org/all/20231103215124.1095-1-quic_bibekkum@quicinc.com/
Changes in v1 from RFC:
- Incorporated suggestion form Robin on RFC
- Moved the actlr data table into driver, instead of maintaining
it inside soc specific DT and piggybacking on exisiting iommus
property (iommu = <SID, MASK, ACTLR>) to set this value during
smmu probe.
- Link to RFC:
https://lore.kernel.org/all/a01e7e60-6ead-4a9e-ba90-22a8a6bbd03f@quicinc.com/
Bibek Kumar Patro (5):
iommu/arm-smmu: re-enable context caching in smmu reset operation
iommu/arm-smmu: refactor qcom_smmu structure to include single pointer
iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings
iommu/arm-smmu: add ACTLR data and support for SM8550
iommu/arm-smmu: add ACTLR data and support for SC7280
.../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 2 +-
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 223 +++++++++++++++++-
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 18 +-
drivers/iommu/arm/arm-smmu/arm-smmu.c | 5 +-
drivers/iommu/arm/arm-smmu/arm-smmu.h | 5 +
5 files changed, 243 insertions(+), 10 deletions(-)
--
2.34.1
^ permalink raw reply [relevance 5%]
* Re: [PATCH v2 0/4] ASoC: qcom: display port changes
2024-05-23 4:09 6% ` Xilin Wu
@ 2024-05-24 12:50 0% ` Srinivas Kandagatla
2024-05-25 7:12 0% ` Xilin Wu
0 siblings, 1 reply; 200+ results
From: Srinivas Kandagatla @ 2024-05-24 12:50 UTC (permalink / raw)
To: Xilin Wu, broonie; +Cc: perex, tiwai, lgirdwood, alsa-devel, linux-kernel
Hi Xilin,
On 23/05/2024 05:09, Xilin Wu wrote:
>>
>> Srinivas Kandagatla (4):
>> ASoC: qcom: q6dsp: parse Display port tokens
>> ASoC: qcom: common: add Display port Jack function
>> ASoC: qcom: sc8280xp: add Display port Jack
>> ASoC: qcom: sm8250: fix a typo in function name
>>
>> sound/soc/qcom/common.c | 29 +++++++++++++++++++++++++++++
>> sound/soc/qcom/common.h | 3 +++
>> sound/soc/qcom/qdsp6/topology.c | 26 ++++++++++++++++++++++++++
>> sound/soc/qcom/sc8280xp.c | 14 ++++++++++++++
>> sound/soc/qcom/sm8250.c | 4 ++--
>> 5 files changed, 74 insertions(+), 2 deletions(-)
>>
>
> Hi Srini,
>
> I tested this series on SM8550 with tplg in [1] and ucm in [2]. But the
> kernel output errors attached below. Headphone does work properly
> without DisplayPort in the ucm.
>
> What could be the possible cause of this? Is there any significant
> change from sc8280xp to sm8550?
>
> --
> Thanks,
> Xilin Wu
>
> [1]
> https://github.com/edk2-porting/audioreach-topology/blob/sakuramist/QCS8550-AYN-ODIN2.m4
> [2]
> https://github.com/strongtz/alsa-ucm-conf/blob/odin2/ucm2/Qualcomm/sm8550/HiFi.conf
>
> [ 1552.313713] qcom-apm gprsvc:service:2:1: Error (1) Processing
> 0x01001000 cmd
> [ 1552.313730] qcom-apm gprsvc:service:2:1: DSP returned error[1001000] 1
> [ 1552.314455] qcom-apm gprsvc:service:2:1: Error (1) Processing
Is the DP cable connected?
if its not connected the dsp will throw this error.
due to this issue I did workaround this issue by modeling it as
conflicting device to Speaker in x13s ucm.
I see in your ucm setup its not the case.
which is why you might be hitting this issue.
Can you try
amixer -c 0 cset iface=MIXER,name='DISPLAY_PORT_RX_0 Audio Mixer
MultiMedia2' 1
aplay -D plughw:0,1 some-wav-file.wav
both with and without display connected.
--srini
> 0x01001006 cmd
> [ 1552.314463] qcom-apm gprsvc:service:2:1: DSP returned error[1001006] 1
> [ 1552.315496] qcom-apm gprsvc:service:2:1: Error (1) Processing
> 0x01001006 cmd
> [ 1552.315506] qcom-apm gprsvc:service:2:1: DSP returned error[1001006] 1
> [ 1552.316033] qcom-apm gprsvc:service:2:1: Error (1) Processing
> 0x01001001 cmd
> [ 1552.316042] qcom-apm gprsvc:service:2:1: DSP returned error[1001001] 1
> [ 1552.316045] q6apm-lpass-dais
> 30000000.remoteproc:glink-edge:gpr:service@1:bedais: Failed to prepare
> Graph -22
> [ 1552.316047] q6apm-lpass-dais
> 30000000.remoteproc:glink-edge:gpr:service@1:bedais: ASoC: error at
> snd_soc_pcm_dai_prepare on DISPLAY_PORT_RX_0: -22
^ permalink raw reply [relevance 0%]
* [PATCH v2 2/2] ASoC: qcom: sc8280xp: Add support for QCM6490 and QCS6490
@ 2024-05-24 3:53 7% ` Mohammad Rafi Shaik
0 siblings, 0 replies; 200+ results
From: Mohammad Rafi Shaik @ 2024-05-24 3:53 UTC (permalink / raw)
To: Srinivas Kandagatla, Banajit Goswami, Liam Girdwood, Mark Brown,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela,
Takashi Iwai
Cc: alsa-devel, linux-arm-msm, linux-sound, devicetree, linux-kernel,
quic_rohkumar, quic_pkumpatl, Mohammad Rafi Shaik
Add compatibles for sound card on Qualcomm QCM6490 IDP and
QCS6490 RB3Gen2 boards.
Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
sound/soc/qcom/sc8280xp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c
index b7fd503a1666..09c949e01479 100644
--- a/sound/soc/qcom/sc8280xp.c
+++ b/sound/soc/qcom/sc8280xp.c
@@ -169,6 +169,8 @@ static int sc8280xp_platform_probe(struct platform_device *pdev)
}
static const struct of_device_id snd_sc8280xp_dt_match[] = {
+ {.compatible = "qcom,qcm6490-sndcard", "qcm6490"},
+ {.compatible = "qcom,qcs6490-rb3gen2-sndcard", "qcs6490"},
{.compatible = "qcom,sc8280xp-sndcard", "sc8280xp"},
{.compatible = "qcom,sm8450-sndcard", "sm8450"},
{.compatible = "qcom,sm8550-sndcard", "sm8550"},
--
2.25.1
^ permalink raw reply related [relevance 7%]
* Re: [PATCH v2 0/4] ASoC: qcom: display port changes
@ 2024-05-23 4:09 6% ` Xilin Wu
2024-05-24 12:50 0% ` Srinivas Kandagatla
0 siblings, 1 reply; 200+ results
From: Xilin Wu @ 2024-05-23 4:09 UTC (permalink / raw)
To: srinivas.kandagatla, broonie
Cc: perex, tiwai, lgirdwood, alsa-devel, linux-kernel
On 2024/4/22 21:43, srinivas.kandagatla@linaro.org wrote:
> From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
>
> This patchset adds support for.
> 1. parse Display Port module tokens from ASoC topology
> 2. add support to DP/HDMI Jack events.
> 3. fixes a typo in function name in sm8250
>
> Verified these patches on X13s along with changes to tplg in
> https://git.codelinaro.org/linaro/qcomlt/audioreach-topology/-/tree/topic/x13s-dp?ref_type=heads
> and ucm changes from https://github.com/Srinivas-Kandagatla/alsa-ucm-conf/tree/topic/x13s-dp
>
> Thanks,
> Srini
>
> Changes since v1:
> - Fixed unused variable warning.
> - fixed warning 'break;' to avoid fall-through
>
> Srinivas Kandagatla (4):
> ASoC: qcom: q6dsp: parse Display port tokens
> ASoC: qcom: common: add Display port Jack function
> ASoC: qcom: sc8280xp: add Display port Jack
> ASoC: qcom: sm8250: fix a typo in function name
>
> sound/soc/qcom/common.c | 29 +++++++++++++++++++++++++++++
> sound/soc/qcom/common.h | 3 +++
> sound/soc/qcom/qdsp6/topology.c | 26 ++++++++++++++++++++++++++
> sound/soc/qcom/sc8280xp.c | 14 ++++++++++++++
> sound/soc/qcom/sm8250.c | 4 ++--
> 5 files changed, 74 insertions(+), 2 deletions(-)
>
Hi Srini,
I tested this series on SM8550 with tplg in [1] and ucm in [2]. But the
kernel output errors attached below. Headphone does work properly
without DisplayPort in the ucm.
What could be the possible cause of this? Is there any significant
change from sc8280xp to sm8550?
--
Thanks,
Xilin Wu
[1]
https://github.com/edk2-porting/audioreach-topology/blob/sakuramist/QCS8550-AYN-ODIN2.m4
[2]
https://github.com/strongtz/alsa-ucm-conf/blob/odin2/ucm2/Qualcomm/sm8550/HiFi.conf
[ 1552.313713] qcom-apm gprsvc:service:2:1: Error (1) Processing
0x01001000 cmd
[ 1552.313730] qcom-apm gprsvc:service:2:1: DSP returned error[1001000] 1
[ 1552.314455] qcom-apm gprsvc:service:2:1: Error (1) Processing
0x01001006 cmd
[ 1552.314463] qcom-apm gprsvc:service:2:1: DSP returned error[1001006] 1
[ 1552.315496] qcom-apm gprsvc:service:2:1: Error (1) Processing
0x01001006 cmd
[ 1552.315506] qcom-apm gprsvc:service:2:1: DSP returned error[1001006] 1
[ 1552.316033] qcom-apm gprsvc:service:2:1: Error (1) Processing
0x01001001 cmd
[ 1552.316042] qcom-apm gprsvc:service:2:1: DSP returned error[1001001] 1
[ 1552.316045] q6apm-lpass-dais
30000000.remoteproc:glink-edge:gpr:service@1:bedais: Failed to prepare
Graph -22
[ 1552.316047] q6apm-lpass-dais
30000000.remoteproc:glink-edge:gpr:service@1:bedais: ASoC: error at
snd_soc_pcm_dai_prepare on DISPLAY_PORT_RX_0: -22
^ permalink raw reply [relevance 6%]
* Re: [PATCH v1 1/1] spi: Remove unneded check for orig_nents
2024-05-22 15:12 0% ` Nícolas F. R. A. Prado
@ 2024-05-22 15:24 0% ` Andy Shevchenko
0 siblings, 0 replies; 200+ results
From: Andy Shevchenko @ 2024-05-22 15:24 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Neil Armstrong, Mark Brown, linux-spi, linux-kernel, linux-arm-msm
On Wed, May 22, 2024 at 11:12:43AM -0400, Nícolas F. R. A. Prado wrote:
> On Wed, May 22, 2024 at 05:24:40PM +0300, Andy Shevchenko wrote:
> > On Wed, May 22, 2024 at 03:18:18PM +0200, Neil Armstrong wrote:
> > > On 22/05/2024 13:53, Neil Armstrong wrote:
> > > > On 22/05/2024 13:33, Andy Shevchenko wrote:
> > > > > On Wed, May 22, 2024 at 12:03:33PM +0200, Neil Armstrong wrote:
> > > > > > On 15/05/2024 23:09, Nícolas F. R. A. Prado wrote:
> > > > > > > On Tue, May 07, 2024 at 11:10:27PM +0300, Andy Shevchenko wrote:
> > > > > > > > Both dma_unmap_sgtable() and sg_free_table() in spi_unmap_buf_attrs()
> > > > > > > > have checks for orig_nents against 0. No need to duplicate this.
> > > > > > > > All the same applies to other DMA mapping API calls.
> > > > > > > >
> > > > > > > > Also note, there is no other user in the kernel that does this kind of
> > > > > > > > checks.
> > > > > > > >
> > > > > > > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > > > > > >
> > > > > > > Hi,
> > > > > > >
> > > > > > > this commit caused a regression which I reported here:
> > > > > > >
> > > > > > > https://lore.kernel.org/all/d3679496-2e4e-4a7c-97ed-f193bd53af1d@notapiano
> > > > > > >
> > > > > > > along with some thoughts on the cause and a possible solution, though I'm not
> > > > > > > familiar with this code base at all and would really appreciate any feedback you
> > > > > > > may have.
> > > > > >
> > > > > > I also see the same regression on the SM8550 and SM8650 platforms,
> > > > > > please CC linux-arm-msm@vger.kernel.org and me for a potential fix to test on those platforms.
> > > > >
> > > > > There is still no answer from IOMMU patch author. Do you have the same trace
> > > > > due to IOMMU calls? Anyway, I guess it would be nice to see it.
> [..]
> > > > >
> > > > > Meanwhile, I have three changes I posted in the replies to the initial report,
> > > > > can you combine them all and test? This will be a plan B (? or A, depending on
> > > > > the culprit).
> > > > >
> > > >
> > > > I'll try to apply them and test.
> > >
> > > I stacked the 3 changes, and it works:
> > > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
> >
> > Thank you!
> >
> > I will try to develop and submit a fix against IOMMU which I believe is the
> > correct place to address this. So, this one will be plan B in case the IOMMU
> > folks will refuse the other one.
>
> Hi,
>
> that change did not work for me. Stack trace follows at the end.
>
> But adding the following on top did fix it:
>
> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index 0851c5e1fd1f..5d3972d9d1da 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -1253,8 +1253,13 @@ static int __spi_map_msg(struct spi_controller *ctlr, struct spi_message *msg)
> /* The sync is done before each transfer. */
> unsigned long attrs = DMA_ATTR_SKIP_CPU_SYNC;
>
> - if (!ctlr->can_dma(ctlr, msg->spi, xfer))
> + if (!ctlr->can_dma(ctlr, msg->spi, xfer)) {
> + memset(&xfer->tx_sg, 0, sizeof(xfer->tx_sg));
> + xfer->tx_sg.sgl = &dummy_sg;
> + memset(&xfer->rx_sg, 0, sizeof(xfer->rx_sg));
> + xfer->rx_sg.sgl = &dummy_sg;
> continue;
> + }
>
> if (xfer->tx_buf != NULL) {
> ret = spi_map_buf_attrs(ctlr, tx_dev, &xfer->tx_sg,
>
>
> The thing is that even with all the previous changes applied, if one of the
> transfers inside the message doesn't support DMA, the null pointer would still
> be passed to the DMA API.
Ah, indeed, the conditionals also can be translated to
can_dma = can_dma();
if (can_dma && _buf)
...
else
...
but...
> Alternatively, I think a better way to achieve the same is (I have verified this
> also works):
I agree that this one is much better approach. I will clean it up and send
as a quick fix. IOMMU will still be on the table as I think it's wrong to
dereference SG when nents = 0.
> I'll let you decide what is the best fix for the issue (what has been posted so
> far in this thread or another fix in IOMMU). If you go with this, feel free to
> add my
>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thank you!
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [relevance 0%]
* Re: [PATCH v1 1/1] spi: Remove unneded check for orig_nents
2024-05-22 14:24 0% ` Andy Shevchenko
@ 2024-05-22 15:12 0% ` Nícolas F. R. A. Prado
2024-05-22 15:24 0% ` Andy Shevchenko
0 siblings, 1 reply; 200+ results
From: Nícolas F. R. A. Prado @ 2024-05-22 15:12 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Neil Armstrong, Mark Brown, linux-spi, linux-kernel, linux-arm-msm
On Wed, May 22, 2024 at 05:24:40PM +0300, Andy Shevchenko wrote:
> On Wed, May 22, 2024 at 03:18:18PM +0200, Neil Armstrong wrote:
> > On 22/05/2024 13:53, Neil Armstrong wrote:
> > > On 22/05/2024 13:33, Andy Shevchenko wrote:
> > > > On Wed, May 22, 2024 at 12:03:33PM +0200, Neil Armstrong wrote:
> > > > > On 15/05/2024 23:09, Nícolas F. R. A. Prado wrote:
> > > > > > On Tue, May 07, 2024 at 11:10:27PM +0300, Andy Shevchenko wrote:
> > > > > > > Both dma_unmap_sgtable() and sg_free_table() in spi_unmap_buf_attrs()
> > > > > > > have checks for orig_nents against 0. No need to duplicate this.
> > > > > > > All the same applies to other DMA mapping API calls.
> > > > > > >
> > > > > > > Also note, there is no other user in the kernel that does this kind of
> > > > > > > checks.
> > > > > > >
> > > > > > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > > > > >
> > > > > > Hi,
> > > > > >
> > > > > > this commit caused a regression which I reported here:
> > > > > >
> > > > > > https://lore.kernel.org/all/d3679496-2e4e-4a7c-97ed-f193bd53af1d@notapiano
> > > > > >
> > > > > > along with some thoughts on the cause and a possible solution, though I'm not
> > > > > > familiar with this code base at all and would really appreciate any feedback you
> > > > > > may have.
> > > > >
> > > > > I also see the same regression on the SM8550 and SM8650 platforms,
> > > > > please CC linux-arm-msm@vger.kernel.org and me for a potential fix to test on those platforms.
> > > >
> > > > There is still no answer from IOMMU patch author. Do you have the same trace
> > > > due to IOMMU calls? Anyway, I guess it would be nice to see it.
[..]
> > > >
> > > > Meanwhile, I have three changes I posted in the replies to the initial report,
> > > > can you combine them all and test? This will be a plan B (? or A, depending on
> > > > the culprit).
> > > >
> > >
> > > I'll try to apply them and test.
> >
> > I stacked the 3 changes, and it works:
> > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
>
> Thank you!
>
> I will try to develop and submit a fix against IOMMU which I believe is the
> correct place to address this. So, this one will be plan B in case the IOMMU
> folks will refuse the other one.
Hi,
that change did not work for me. Stack trace follows at the end.
But adding the following on top did fix it:
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 0851c5e1fd1f..5d3972d9d1da 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1253,8 +1253,13 @@ static int __spi_map_msg(struct spi_controller *ctlr, struct spi_message *msg)
/* The sync is done before each transfer. */
unsigned long attrs = DMA_ATTR_SKIP_CPU_SYNC;
- if (!ctlr->can_dma(ctlr, msg->spi, xfer))
+ if (!ctlr->can_dma(ctlr, msg->spi, xfer)) {
+ memset(&xfer->tx_sg, 0, sizeof(xfer->tx_sg));
+ xfer->tx_sg.sgl = &dummy_sg;
+ memset(&xfer->rx_sg, 0, sizeof(xfer->rx_sg));
+ xfer->rx_sg.sgl = &dummy_sg;
continue;
+ }
if (xfer->tx_buf != NULL) {
ret = spi_map_buf_attrs(ctlr, tx_dev, &xfer->tx_sg,
The thing is that even with all the previous changes applied, if one of the
transfers inside the message doesn't support DMA, the null pointer would still
be passed to the DMA API.
Alternatively, I think a better way to achieve the same is (I have verified this
also works):
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 0851c5e1fd1f..3f2ee70d080a 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1322,7 +1322,7 @@ static int __spi_unmap_msg(struct spi_controller *ctlr, struct spi_message *msg)
return 0;
}
-static void spi_dma_sync_for_device(struct spi_controller *ctlr,
+static void spi_dma_sync_for_device(struct spi_controller *ctlr, struct spi_message *msg,
struct spi_transfer *xfer)
{
struct device *rx_dev = ctlr->cur_rx_dma_dev;
@@ -1331,11 +1331,14 @@ static void spi_dma_sync_for_device(struct spi_controller *ctlr,
if (!ctlr->cur_msg_mapped)
return;
+ if (!ctlr->can_dma(ctlr, msg->spi, xfer))
+ return;
+
dma_sync_sgtable_for_device(tx_dev, &xfer->tx_sg, DMA_TO_DEVICE);
dma_sync_sgtable_for_device(rx_dev, &xfer->rx_sg, DMA_FROM_DEVICE);
}
-static void spi_dma_sync_for_cpu(struct spi_controller *ctlr,
+static void spi_dma_sync_for_cpu(struct spi_controller *ctlr, struct spi_message *msg,
struct spi_transfer *xfer)
{
struct device *rx_dev = ctlr->cur_rx_dma_dev;
@@ -1344,6 +1347,9 @@ static void spi_dma_sync_for_cpu(struct spi_controller *ctlr,
if (!ctlr->cur_msg_mapped)
return;
+ if (!ctlr->can_dma(ctlr, msg->spi, xfer))
+ return;
+
dma_sync_sgtable_for_cpu(rx_dev, &xfer->rx_sg, DMA_FROM_DEVICE);
dma_sync_sgtable_for_cpu(tx_dev, &xfer->tx_sg, DMA_TO_DEVICE);
}
@@ -1637,10 +1643,10 @@ static int spi_transfer_one_message(struct spi_controller *ctlr,
reinit_completion(&ctlr->xfer_completion);
fallback_pio:
- spi_dma_sync_for_device(ctlr, xfer);
+ spi_dma_sync_for_device(ctlr, msg, xfer);
ret = ctlr->transfer_one(ctlr, msg->spi, xfer);
if (ret < 0) {
- spi_dma_sync_for_cpu(ctlr, xfer);
+ spi_dma_sync_for_cpu(ctlr, msg, xfer);
if (ctlr->cur_msg_mapped &&
(xfer->error & SPI_TRANS_FAIL_NO_START)) {
@@ -1665,7 +1671,7 @@ static int spi_transfer_one_message(struct spi_controller *ctlr,
msg->status = ret;
}
- spi_dma_sync_for_cpu(ctlr, xfer);
+ spi_dma_sync_for_cpu(ctlr, msg, xfer);
} else {
if (xfer->len)
dev_err(&msg->spi->dev,
I'll let you decide what is the best fix for the issue (what has been posted so
far in this thread or another fix in IOMMU). If you go with this, feel free to
add my
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
Stack trace:
[ 3.086173] Unable to handle kernel NULL pointer dereference at virtual address 000000000000001c
[ 3.103002] Mem abort info:
[ 3.105885] ESR = 0x0000000096000004
[ 3.109738] EC = 0x25: DABT (current EL), IL = 32 bits
[ 3.115198] SET = 0, FnV = 0
[ 3.118342] EA = 0, S1PTW = 0
[ 3.121570] FSC = 0x04: level 0 translation fault
[ 3.126584] Data abort info:
[ 3.129545] ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
[ 3.135188] CM = 0, WnR = 0, TnD = 0, TagAccess = 0
[ 3.140383] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
[ 3.145837] [000000000000001c] user address but active_mm is swapper
[ 3.152369] Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP
[ 3.156423] input: cros_ec as /devices/platform/soc@0/ac0000.geniqup/a80000.spi/spi_master/spi6/spi6.0/a80000.spi:ec@0:keyboard-controller/input/input0
[ 3.158806] Modules linked in:
[ 3.158812] CPU: 6 PID: 68 Comm: kworker/u32:2 Not tainted 6.9.0-next-20240515-00005-gad5f430e51d2 #424
[ 3.158820] Hardware name: Google Kingoftown (DT)
[ 3.158823] Workqueue: events_unbound deferred_probe_work_func
[ 3.175091] input: cros_ec_buttons as /devices/platform/soc@0/ac0000.geniqup/a80000.spi/spi_master/spi6/spi6.0/a80000.spi:ec@0:keyboard-controller/input/input1
[ 3.175859]
[ 3.175861] pstate: 80400009 (Nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 3.186858] cros-ec-spi spi6.0: Chrome EC device registered
[ 3.190317] pc : iommu_dma_sync_sg_for_device+0x28/0x100
[ 3.190327] lr : __dma_sync_sg_for_device+0x28/0x4c
[ 3.211853] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.70/cr50_v2.0.3361-b70f24b1b
[ 3.212461] sp : ffff800080942dc0
[ 3.212464] x29: ffff800080942dc0 x28: ffff7eb103be2000 x27: ffff7eb101012010
[ 3.257562] x26: ffff800080943008 x25: ffff7eb103be2480 x24: ffffb819fada5180
[ 3.264887] x23: ffff7eb101012010 x22: 0000000000000001 x21: 0000000000000000
[ 3.272213] x20: ffffb819fb10c718 x19: 0000000000000000 x18: ffffb819fbde8988
[ 3.279539] x17: 0000000000010108 x16: 0000000000000000 x15: 0000000000000002
[ 3.286863] x14: 0000000000000001 x13: 000000000016356d x12: 0000000000000001
[ 3.294188] x11: ffff800080942cd0 x10: ffff7eb103c74ff8 x9 : ffff7eb103be2469
[ 3.301515] x8 : ffff7eb10101cf04 x7 : 00000000ffffffff x6 : 0000000000000001
[ 3.308849] x5 : ffffb819fa51a780 x4 : ffffb819f9704acc x3 : 0000000000000001
[ 3.316182] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff7eb101012010
[ 3.323509] Call trace:
[ 3.326023] iommu_dma_sync_sg_for_device+0x28/0x100
[ 3.331125] __dma_sync_sg_for_device+0x28/0x4c
[ 3.335790] spi_transfer_one_message+0x378/0x6e4
[ 3.340634] __spi_pump_transfer_message+0x1e4/0x504
[ 3.345737] __spi_sync+0x2a0/0x3c4
[ 3.349334] spi_sync+0x30/0x54
[ 3.352568] spi_mem_exec_op+0x26c/0x41c
[ 3.356610] spi_nor_spimem_read_data+0x148/0x158
[ 3.361454] spi_nor_read_data+0x30/0x3c
[ 3.365494] spi_nor_read_sfdp+0x74/0xe4
[ 3.369532] spi_nor_parse_sfdp+0x120/0x11d0
[ 3.373921] spi_nor_sfdp_init_params_deprecated+0x3c/0x8c
[ 3.379562] spi_nor_scan+0x7ac/0xef8
[ 3.383336] spi_nor_probe+0x94/0x2ec
[ 3.387109] spi_mem_probe+0x6c/0xac
[ 3.390796] spi_probe+0x84/0xe4
[ 3.394119] really_probe+0xbc/0x2a0
[ 3.397793] __driver_probe_device+0x78/0x12c
[ 3.402270] driver_probe_device+0x40/0x160
[ 3.406569] __device_attach_driver+0xb8/0x134
[ 3.411144] bus_for_each_drv+0x84/0xe0
[ 3.415091] __device_attach+0xa8/0x1b0
[ 3.419040] device_initial_probe+0x14/0x20
[ 3.423340] bus_probe_device+0xa8/0xac
[ 3.427288] device_add+0x590/0x750
[ 3.430872] __spi_add_device+0x138/0x208
[ 3.434999] of_register_spi_device+0x394/0x57c
[ 3.439656] spi_register_controller+0x394/0x760
[ 3.444399] qcom_qspi_probe+0x328/0x390
[ 3.448442] platform_probe+0x68/0xd8
[ 3.452216] really_probe+0xbc/0x2a0
[ 3.455898] __driver_probe_device+0x78/0x12c
[ 3.460382] driver_probe_device+0x40/0x160
[ 3.464682] __device_attach_driver+0xb8/0x134
[ 3.469246] bus_for_each_drv+0x84/0xe0
[ 3.473193] __device_attach+0xa8/0x1b0
[ 3.477137] device_initial_probe+0x14/0x20
[ 3.481435] bus_probe_device+0xa8/0xac
[ 3.485383] deferred_probe_work_func+0x88/0xc0
[ 3.490044] process_one_work+0x154/0x298
[ 3.494172] worker_thread+0x304/0x408
[ 3.498035] kthread+0x118/0x11c
[ 3.501358] ret_from_fork+0x10/0x20
[ 3.505046] Code: 2a0203f5 2a0303f6 a90363f7 aa0003f7 (b9401c20)
[ 3.511301] ---[ end trace 0000000000000000 ]---
^ permalink raw reply related [relevance 0%]
* [GIT PULL] Char/Misc driver changes for 6.10-rc1
@ 2024-05-22 14:51 1% Greg KH
0 siblings, 0 replies; 200+ results
From: Greg KH @ 2024-05-22 14:51 UTC (permalink / raw)
To: Linus Torvalds; +Cc: Andrew Morton, Arnd Bergmann, linux-kernel
The following changes since commit dd5a440a31fae6e459c0d6271dddd62825505361:
Linux 6.9-rc7 (2024-05-05 14:06:01 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git tags/char-misc-6.10-rc1
for you to fetch changes up to f5b335dc025cfee90957efa90dc72fada0d5abb4:
misc: ntsync: mark driver as "broken" to prevent from building (2024-05-15 17:34:41 +0200)
----------------------------------------------------------------
Char/Misc and other driver subsystem changes for 6.10-rc1
Here is the big set of char/misc and other driver subsystem updates for
6.10-rc1. Nothing major here, just lots of new drivers and updates for
apis and new hardware types. Included in here are:
- big IIO driver updates with more devices and drivers added
- fpga driver updates
- hyper-v driver updates
- uio_pruss driver removal, no one uses it, other drivers control the
same hardware now
- binder minor updates
- mhi driver updates
- excon driver updates
- counter driver updates
- accessability driver updates
- coresight driver updates
- other hwtracing driver updates
- nvmem driver updates
- slimbus driver updates
- spmi driver updates
- other smaller misc and char driver updates
All of these have been in linux-next for a while with no reported
issues.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----------------------------------------------------------------
Abel Vesa (7):
dt-bindings: spmi: Add X1E80100 SPMI PMIC ARB schema
dt-bindings: spmi: Deprecate qcom,bus-id
spmi: pmic-arb: Fix some compile warnings about members not being described
spmi: pmic-arb: Make the APID init a version operation
spmi: pmic-arb: Make core resources acquiring a version operation
spmi: pmic-arb: Register controller for bus instead of arbiter
spmi: pmic-arb: Add multi bus support
Alexander Shishkin (6):
intel_th: pci: Add Granite Rapids support
intel_th: pci: Add Granite Rapids SOC support
intel_th: pci: Add Sapphire Rapids SOC support
intel_th: pci: Add Meteor Lake-S support
intel_th: pci: Add Meteor Lake-S CPU support
intel_th: pci: Add Lunar Lake support
Andrew Davis (1):
uio: pruss: Remove this driver
Andy Shevchenko (15):
w1: gpio: Make use of device properties
w1: gpio: Switch to use dev_err_probe()
w1: gpio: Use sizeof(*pointer) instead of sizeof(type)
w1: gpio: Remove duplicate NULL checks
w1: gpio: Don't use "proxy" headers
iio: adc: spear_adc: Make use of device properties
iio: core: Leave private pointer NULL when no private data supplied
iio: core: Calculate alloc_size only once in iio_device_alloc()
iio: adc: twl4030-madc: Make use of device properties
counter: Don't use "proxy" headers
fpga: ice40-spi: Don't use "proxy" headers
iio: light: stk3310: Drop most likely fake ACPI ID
extcon: intel-mrfld: Switch to use dev_err_probe()
extcon: intel-mrfld: Don't shadow error from devm_extcon_dev_allocate()
extcon: realtek: Remove unused of_gpio.h
Anshuman Khandual (12):
coresight: etm4x: Fix unbalanced pm_runtime_enable()
coresight: stm: Extract device name from AMBA pid based table lookup
coresight: tmc: Extract device properties from AMBA pid based table lookup
coresight: Add helpers registering/removing both AMBA and platform drivers
coresight: replicator: Move ACPI support from AMBA driver to platform driver
coresight: funnel: Move ACPI support from AMBA driver to platform driver
coresight: catu: Move ACPI support from AMBA driver to platform driver
coresight: tpiu: Move ACPI support from AMBA driver to platform driver
coresight: tmc: Move ACPI support from AMBA driver to platform driver
coresight: stm: Move ACPI support from AMBA driver to platform driver
coresight: debug: Move ACPI support from AMBA driver to platform driver
coresight: tmc: Enable SG capability on ACPI based SoC-400 TMC ETR devices
Arnd Bergmann (1):
parport: mfc3: avoid empty-body warning
Atin Bainada (1):
misc: ti-st: st_kim: remove unnecessary (void*) conversions
Baochen Qiang (1):
bus: mhi: host: Add mhi_power_down_keep_dev() API to support system suspend/hibernation
Bird, Tim (1):
scripts/spdxcheck: Add count of missing files to stats output
Carlos Llamas (1):
binder: fix max_thread type inconsistency
Charles Perry (4):
fpga: xilinx-spi: extract a common driver core
dt-bindings: fpga: xlnx,fpga-selectmap: add DT schema
fpga: xilinx-selectmap: add new driver
fpga: xilinx-core: add new gpio names for prog and init
Chris Morgan (1):
dt-bindings: iio: adc: Add GPADC for Allwinner H616
Chris Packham (3):
uio_pdrv_genirq: convert to use device_property APIs
uio: use threaded interrupts
uio: update kerneldoc comments for interrupt functions
Christophe JAILLET (3):
iio: pressure: hsc030pa: Use spi_read()
fpga: altera-cvp: Remove an unused field in struct altera_cvp_conf
VMCI: Fix an error handling path in vmci_guest_probe_device()
Colin Ian King (3):
iio: accel: adxl367: Remove second semicolon
comedi: remove unused helper function dma_chain_flag_bits
intel_th: Remove redundant initialization of pointer outp
Dan Carpenter (4):
iio: light: apds9306: Fix off by one in apds9306_sampling_freq_get()
iio: adc: ad7173: Fix ! vs ~ typo in ad7173_sel_clk()
iio: dac: adi-axi: fix a mistake in axi_dac_ext_info_set()
stm class: Fix a double free in stm_register_device()
David Collins (1):
dt-bindings: nvmem: qcom,spmi-sdam: update maintainer
David Lechner (13):
dt-bindings: iio: adc: add ad7944 ADCs
iio: adc: ad7944: add driver for AD7944/AD7985/AD7986
iio: adc: ad7944: Add support for "3-wire mode"
MAINTAINERS: add Documentation/iio/ to IIO subsystem
docs: iio: new docs for ad7944 driver
iio: adc: ad7944: simplify adi,spi-mode property parsing
iio: adc: ad7944: use spi_optimize_message()
iio: adc: ad7944: Consolidate spi_sync() wrapper
iio: adc: ad7266: don't set masklength
iio: adc: mxs-lradc-adc: don't set masklength
iio: buffer: initialize masklength accumulator to 0
iio: adc: ad7944: add support for chain mode
docs: iio: ad7944: add documentation for chain mode
Dimitri Fedrau (1):
iio: temperature: mcp9600: Fix temperature reading for negative values
Dumitru Ceclan (6):
dt-bindings: adc: add AD7173
iio: adc: ad_sigma_delta: Add optional irq selection
iio: adc: ad7173: add AD7173 driver
dt-bindings: adc: ad7173: add support for additional models
iio: adc: ad7173: improve chip id's defines
iio: adc: ad7173: add support for additional models
Elizabeth Figura (3):
ntsync: Introduce the ntsync driver and character device.
ntsync: Introduce NTSYNC_IOC_CREATE_SEM.
ntsync: Introduce NTSYNC_IOC_SEM_POST.
Fabrice Gasnier (11):
counter: Introduce the COUNTER_COMP_FREQUENCY() macro
counter: stm32-timer-cnt: rename quadrature signal
counter: stm32-timer-cnt: rename counter
counter: stm32-timer-cnt: adopt signal definitions
counter: stm32-timer-cnt: introduce clock signal
counter: stm32-timer-cnt: add counter prescaler extension
counter: stm32-timer-cnt: add checks on quadrature encoder capability
counter: stm32-timer-cnt: introduce channels
counter: stm32-timer-cnt: probe number of channels from registers
counter: stm32-timer-cnt: add support for overflow events
counter: stm32-timer-cnt: add support for capture events
Gabriel Schwartz (1):
iio: adc: rtq6056: Use automated cleanup for mode handling in write_raw
Greg Kroah-Hartman (15):
Merge tag 'counter-updates-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter into char-misc-next
Merge 6.9-rc5 into char-misc-next
Merge tag 'iio-for-6.10a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
Merge tag 'peci-next-6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/iwi/linux into char-misc-next
Merge tag 'w1-drv-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1 into char-misc-next
Merge tag 'counter-updates-for-6.10b' of git://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter into char-misc-next
Merge tag 'fpga-for-6.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga into char-misc-next
Merge tag 'mhi-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi into char-misc-next
Merge tag 'coresight-next-v6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
nvmem: core: switch to use device_add_groups()
Merge tag 'icc-6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
Merge tag 'iio-for-6.10b-take2' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
Merge 6.9-rc7 into char-misc-testing
Merge tag 'extcon-next-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon into char-misc-next
misc: ntsync: mark driver as "broken" to prevent from building
Gustavo A. R. Silva (1):
mei: Avoid a bunch of -Wflex-array-member-not-at-end warnings
Gustavo Rodrigues (3):
iio: adc: ad799x: change 'unsigned' to 'unsigned int' declaration
iio: adc: ad799x: add blank line to avoid warning messages
iio: adc: ad799x: Prefer to use octal permission
Hagar Gamal Halim Hemdan (1):
vmci: prevent speculation leaks by sanitizing event in event_deliver()
Hans de Goede (4):
iio: core: Add iio_read_acpi_mount_matrix() helper function
iio: accel: kxcjk-1013: Use new iio_read_acpi_mount_matrix() helper
iio: bmc150-accel-core: Use iio_read_acpi_mount_matrix() helper
iio: accel: mxc4005: Read orientation matrix from ACPI ROTM method
Huai-Yuan Liu (1):
ppdev: Add an error check in register_device
Javier Carrasco (8):
io: light: st_uvis25: drop casting to void in dev_set_drvdata
iio: humidity: hts211: drop casting to void in dev_set_drvdata
iio: imu: st_lsm6dsx: drop casting to void in dev_set_drvdata
iio: humidity: hdc3020: add power management
dt-bindings: iio: humidity: hdc3020: add reset-gpios
iio: humidity: hdc3020: add reset management
dt-bindings: iio: health: maxim,max30102: add max30101
iio: health: max30102: add support for max30101
Jean-Baptiste Maneyrol (10):
iio: imu: inv_mpu6050: add WoM (Wake-on-Motion) sensor
iio: imu: inv_mpu6050: add WoM event as accel event
iio: imu: inv_mpu6050: add new interrupt handler for WoM events
iio: imu: inv_mpu6050: add WoM suspend wakeup with low-power mode
dt-bindings: iio: imu: add icm42688 inside inv_icm42600
iio: imu: inv_icm42600: add support of ICM-42688-P
dt-bindings: iio: imu: add icm42686 inside inv_icm42600
iio: imu: inv_icm42600: add support of ICM-42686-P
iio: invensense: fix interrupt timestamp alignment
iio: invensense: fix timestamp glitches when switching frequency
Jiapeng Chong (2):
coresight: stm: Remove duplicate linux/acpi.h header
coresight: Remove duplicate linux/amba/bus.h header
Johan Hovold (2):
dt-bindings: spmi: hisilicon,hisi-spmi-controller: fix binding references
dt-bindings: spmi: hisilicon,hisi-spmi-controller: clean up example
Jonathan Cameron (32):
device property: Move fwnode_handle_put() into property.h
device property: Add cleanup.h based fwnode_handle_put() scope based cleanup.
device property: Introduce device_for_each_child_node_scoped()
iio: adc: max11410: Use device_for_each_child_node_scoped()
iio: addac: ad74413r: Use device_for_each_child_node_scoped()
iio: dac: ltc2688: Use device_for_each_child_node_scoped()
iio: adc: fsl-imx25-gcq: Switch from of specific handing to fwnode based.
iio: adc: fsl-imx25-gcq: Use devm_* and dev_err_probe() to simplify probe
iio: adc: ad7124: Switch from of specific to fwnode based property handling
iio: adc: ad7292: Switch from of specific to fwnode property handling
iio: adc: ad7192: Convert from of specific to fwnode property handling
iio: accel: mma8452: Switch from of specific to fwnode property handling.
iio: accel: fxls8962af: Switch from of specific to fwnode based properties.
iio: adc: hx711: Switch from of specific to fwnode property handling.
iio: temp: ltc2983: Use __free(fwnode_handle) and device_for_each_node_scoped()
iio: adc: rzg2l_adc: Use device_for_each_child_node_scoped()
iio: adc: rcar-gyroadc: use for_each_available_child_node_scoped()
iio: dac: ad3552r: Use device_for_each_child_node_scoped()
iio: dac: ad5770r: Use device_for_each_child_node_scoped()
iio: adc: ab8500-gpadc: Fix kernel-doc parameter names.
iio: adc: ab8500-gpadc: Use device_for_each_child_node_scoped() to simplify erorr paths.
iio: adc: ad4130: Use device_for_each_child_node_scoped() to simplify error paths.
iio: adc: ad7173: Use device_for_each_child_node_scoped() to simplify error paths.
iio: frequency: admfm2000: Use device_for_each_child_node_scoped() to simplify error paths.
iio: dac: ad3552: Use __free(fwnode_handle) to simplify error handling.
iio: adc: pac1934: Use device_for_each_available_child_node_scoped() to simplify error handling.
iio: adc: stm32: Fixing err code to not indicate success
iio: adc: stm32: Use device_for_each_child_node_scoped()
iio: adc: qcom-spmi-adc5: Use device_for_each_child_node_scoped()
iio: adc: mcp3564: Use device_for_each_child_node_scoped()
Documentation: ABI + trace: hisi_ptt: update paths to bus/event_source
hwtracing: hisi_ptt: Assign parent for event_source device
Konrad Dybcio (3):
interconnect: qcom: sm6115: Unspaghettify SNoC QoS port numbering
interconnect: qcom: qcm2290: Fix mas_snoc_bimc QoS port assignment
dt-bindings: nvmem: Add compatible for SC8280XP
Krzysztof Kozlowski (12):
fpga: altera: drop driver owner assignment
iio: dac: ad5755: make use of of_device_id table
dt-bindings: arm: qcom,coresight-tpda: drop redundant type from ports
dt-bindings: arm: qcom,coresight-tpda: fix indentation in the example
eeprom: at25: drop unneeded MODULE_ALIAS
eeprom: 93xx46: drop unneeded MODULE_ALIAS
nvmem: layouts: store owner from modules with nvmem_layout_driver_register()
nvmem: layouts: onie-tlv: drop driver owner initialization
nvmem: layouts: sl28vpd: drop driver owner initialization
nvmem: sc27xx: fix module autoloading
nvmem: sprd: fix module autoloading
slimbus: qcom-ctrl: fix module autoloading
Kunwu Chan (2):
mei: bus: constify the struct mei_cl_bus_type usage
tifm: constify the struct tifm_bus_type usage
Laurent Pinchart (2):
dt-bindings: iio: dac: ti,dac5571: Add DAC081C081 support
iio: dac: ti-dac5571: Add DAC081C081 support
Li Zhijian (1):
intel_th: Convert sprintf/snprintf to sysfs_emit
Lincoln Yuji (1):
iio: adc: ti-ads1015: use device_for_each_child_node_scoped()
Lorenzo Bertin Salvador (1):
iio: adc: ti-ads131e08: Use device_for_each_child_node_scoped() to simplify error paths.
Lothar Rubusch (8):
iio: accel: adxl345: Make data_range obsolete
iio: accel: adxl345: Group bus configuration
iio: accel: adxl345: Move defines to header
dt-bindings: iio: accel: adxl345: Add spi-3wire
iio: accel: adxl345: Pass function pointer to core
iio: accel: adxl345: Reorder probe initialization
iio: accel: adxl345: Add comment to probe
iio: accel: adxl345: Add spi-3wire option
Luca Weiss (2):
Documentation: ABI: document in_temp_input file
dt-bindings: iio: imu: mpu6050: Improve i2c-gate disallow list
Marco Pagani (4):
fpga: manager: add owner module and take its refcount
fpga: bridge: add owner module and take its refcount
fpga: tests: use KUnit devices instead of platform devices
fpga: region: add owner module and take its refcount
Marius Cristea (1):
iio: adc: PAC1934: fix accessing out of bounds array index
Markus Elfring (1):
spmi: pmic-arb: Replace three IS_ERR() calls by null pointer checks in spmi_pmic_arb_probe()
Mikhail Lappo (3):
stm class: Add source type
stm class: Propagate source type to protocols
stm class: sys-t: Improve ftrace source handling
Mukesh Ojha (2):
dt-bindings: nvmem: Add compatible for sm8450, sm8550 and sm8650
nvmem: meson-mx-efuse: Remove nvmem_device from efuse struct
Niklas Schnelle (1):
/dev/port: don't compile file operations without CONFIG_DEVPORT
Nuno Sa (21):
iio: core: move to cleanup.h magic
iio: trigger: move to the cleanup.h magic
iio: buffer: iio: core: move to the cleanup.h magic
iio: inkern: move to the cleanup.h magic
dt-bindings: iio: temperature: ltc2983: document power supply
iio: temperature: ltc2983: support vdd regulator
iio: buffer-dma: add iio_dmaengine_buffer_setup()
dt-bindings: iio: dac: add docs for AXI DAC IP
dt-bindings: iio: dac: add docs for AD9739A
iio: backend: add new functionality
iio: dac: add support for AXI DAC IP core
iio: dac: support the ad9739a RF DAC
iio: adc: adi-axi-adc: only error out in major version mismatch
dt-bindings: adc: axi-adc: add clocks property
iio: adc: axi-adc: make sure AXI clock is enabled
iio: backend: change docs padding
iio: backend: add API for interface tuning
iio: adc: adi-axi-adc: remove regmap max register
iio: adc: adi-axi-adc: support digital interface calibration
iio: adc: ad9467: support digital interface calibration
iio: dac: ad9739a: write complete MU_CNT1 register during lock
Paul Cercueil (4):
iio: buffer-dma: Rename iio_dma_buffer_data_available()
iio: buffer-dma: Enable buffer write support
iio: buffer-dmaengine: Support specifying buffer direction
iio: buffer-dmaengine: Enable write support
Peter Colberg (2):
fpga: dfl: remove unused function is_dfl_feature_present()
fpga: dfl: remove unused member pdata from struct dfl_{afu,fme}
Prasad Pandit (2):
misc: sgi_gru: indent SGI_GRU option help text
misc: sgi_gru: remove default attribute of LATTICE_ECP3_CONFIG
Qiang Yu (3):
bus: mhi: host: Add sysfs entry to force device to enter EDL
bus: mhi: host: Add a new API for getting channel doorbell offset
bus: mhi: host: pci_generic: Add generic edl_trigger to allow devices to enter EDL mode
Ramona Gradinariu (1):
docs: iio: adis16475: fix device files tables
Randy Dunlap (3):
counter: linux/counter.h: fix Excess kernel-doc description warning
intel_th: msu: Fix kernel-doc warnings
extcon: max8997: select IRQ_DOMAIN instead of depending on it
Remington Brasga (1):
coresight: Docs/ABI/testing/sysfs-bus-coresight-devices: Fix spelling errors
Ricardo B. Marliere (6):
counter: make counter_bus_type const
counter: constify the struct device_type usage
peci: Make peci_bus_type const
peci: constify the struct device_type usage
intel_th: Constify the struct device_type usage
spmi: make spmi_bus_type const
Ricky Wu (1):
misc: rtsx: do clear express reg every SD_INT
Samuel Thibault (1):
speakup: Turn i18n files utf-8
Saurabh Sengar (7):
Drivers: hv: vmbus: Add utility function for querying ring size
uio_hv_generic: Query the ringbuffer size for device
uio_hv_generic: Enable interrupt for low speed VMBus devices
tools: hv: Add vmbus_bufring
tools: hv: Add new fcopy application based on uio driver
Drivers: hv: Remove fcopy driver
uio_hv_generic: Remove use of PAGE_SIZE
Sean Anderson (1):
misc: ds1682: Add NVMEM support
Sicong Huang (1):
greybus: Fix use-after-free bug in gb_interface_release due to race condition.
Subhajit Ghosh (7):
dt-bindings: iio: light: Merge APDS9300 and APDS9960 schemas
dt-bindings: iio: light: adps9300: Add missing vdd-supply
dt-bindings: iio: light: adps9300: Update interrupt definitions
dt-bindings: iio: light: Avago APDS9306
iio: light: Add support for APDS9306 Light Sensor
iio: light: apds9306: Improve apds9306_write_event_config()
iio: light: apds9306: Fix input arguments to in_range()
Suzuki K Poulose (4):
coresight: etm4x: Do not hardcode IOMEM access for register restore
coresight: etm4x: Do not save/restore Data trace control registers
coresight: etm4x: Safe access for TRCQCLTR
coresight: etm4x: Fix access to resource selector registers
Thomas Haemmerle (4):
iio: pressure: dps310: support negative temperature values
iio: pressure: dps310: introduce consistent error handling
iio: pressure: dps310: consistently check return value of `regmap_read`
iio: pressure: dps310: simplify scale factor reading
Thomas Weißschuh (3):
misc/pvpanic: use bit macros
misc/pvpanic: add shutdown event definition
misc/pvpanic: add support for normal shutdowns
Thorsten Blum (1):
virt: acrn: Fix typos
Uwe Kleine-König (23):
counter: ti-ecap-capture: Convert to platform remove callback returning void
counter: ti-eqep: Convert to platform remove callback returning void
uio: fsl_elbc_gpcm: Convert to platform remove callback returning void
ndtest: Convert to platform remove callback returning void
powerpc/powernv: Convert to platform remove callback returning void
sonypi: Convert to platform remove callback returning void
cdx: Convert to platform remove callback returning void
coresight: catu: Convert to platform remove callback returning void
coresight: debug: Convert to platform remove callback returning void
coresight: stm: Convert to platform remove callback returning void
coresight: tmc: Convert to platform remove callback returning void
coresight: tpiu: Convert to platform remove callback returning void
mcb: lpc: Convert to platform remove callback returning void
nvmem: lpc18xx_eeprom: Convert to platform remove callback returning void
slimbus: Convert to platform remove callback returning void
intel_th: Convert to platform remove callback returning void
extcon: adc-jack: Convert to platform remove callback returning void
extcon: intel-cht-wc: Convert to platform remove callback returning void
extcon: intel-mrfld: Convert to platform remove callback returning void
extcon: max3355: Convert to platform remove callback returning void
extcon: max77843: Convert to platform remove callback returning void
extcon: usb-gpio: Convert to platform remove callback returning void
extcon: usbc-cros-ec: Convert to platform remove callback returning void
Vamshi Gajjela (1):
spmi: hisi-spmi-controller: Do not override device identifier
Vasileios Amoiridis (1):
iio: pressure: BMP280 core driver headers sorting
Viken Dadhaniya (1):
slimbus: qcom-ngd-ctrl: Reduce auto suspend delay
William Breathitt Gray (2):
MAINTAINERS: Update email addresses for William Breathitt Gray
counter: ti-ecap-capture: Utilize COUNTER_COMP_FREQUENCY macro
Wolfram Sang (8):
iio: adc: ad_sigma_delta: use 'time_left' variable with wait_for_completion_timeout()
iio: adc: exynos_adc: use 'time_left' variable with wait_for_completion_timeout()
iio: adc: fsl-imx25-gcq: use 'time_left' variable with wait_for_completion_interruptible_timeout()
iio: adc: intel_mrfld_adc: use 'time_left' variable with wait_for_completion_interruptible_timeout()
iio: adc: stm32-adc: use 'time_left' variable with wait_for_completion_interruptible_timeout()
iio: adc: stm32-dfsdm-adc: use 'time_left' variable with wait_for_completion_interruptible_timeout()
iio: adc: twl6030-gpadc: use 'time_left' variable with wait_for_completion_interruptible_timeout()
iio: pressure: zpa2326: use 'time_left' variable with wait_for_completion_interruptible_timeout()
Yang Li (1):
extcon: adc-jack: Document missing struct members
Documentation/ABI/stable/sysfs-bus-mhi | 13 +
.../ABI/testing/sysfs-bus-coresight-devices-etm3x | 2 +-
.../ABI/testing/sysfs-bus-coresight-devices-tmc | 2 +-
.../ABI/testing/sysfs-bus-coresight-devices-tpdm | 2 +-
...ptt => sysfs-bus-event_source-devices-hisi_ptt} | 12 +-
Documentation/ABI/testing/sysfs-bus-iio | 3 +-
Documentation/ABI/testing/sysfs-bus-iio-ad9739a | 19 +
.../bindings/arm/qcom,coresight-tpda.yaml | 34 +-
.../bindings/fpga/xlnx,fpga-selectmap.yaml | 86 ++
.../devicetree/bindings/iio/accel/adi,adxl345.yaml | 2 +
.../devicetree/bindings/iio/adc/adi,ad7173.yaml | 279 ++++
.../devicetree/bindings/iio/adc/adi,ad7944.yaml | 213 +++
.../devicetree/bindings/iio/adc/adi,axi-adc.yaml | 5 +
.../iio/adc/allwinner,sun20i-d1-gpadc.yaml | 9 +-
.../devicetree/bindings/iio/dac/adi,ad9739a.yaml | 95 ++
.../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 62 +
.../devicetree/bindings/iio/dac/ti,dac5571.yaml | 1 +
.../bindings/iio/health/maxim,max30102.yaml | 12 +-
.../bindings/iio/humidity/ti,hdc3020.yaml | 5 +
.../bindings/iio/imu/invensense,icm42600.yaml | 2 +
.../bindings/iio/imu/invensense,mpu6050.yaml | 17 +-
.../bindings/iio/light/avago,apds9300.yaml | 20 +-
.../bindings/iio/light/avago,apds9960.yaml | 44 -
.../bindings/iio/temperature/adi,ltc2983.yaml | 4 +
.../devicetree/bindings/nvmem/qcom,qfprom.yaml | 4 +
.../devicetree/bindings/nvmem/qcom,spmi-sdam.yaml | 2 +-
.../spmi/hisilicon,hisi-spmi-controller.yaml | 17 +-
.../bindings/spmi/qcom,spmi-pmic-arb.yaml | 1 +
.../bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml | 136 ++
Documentation/driver-api/fpga/fpga-bridge.rst | 7 +-
Documentation/driver-api/fpga/fpga-mgr.rst | 34 +-
Documentation/driver-api/fpga/fpga-region.rst | 13 +-
Documentation/iio/ad7944.rst | 156 +++
Documentation/iio/adis16475.rst | 8 +-
Documentation/iio/index.rst | 1 +
Documentation/trace/hisi-ptt.rst | 4 +-
Documentation/userspace-api/ioctl/ioctl-number.rst | 2 +
MAINTAINERS | 60 +-
drivers/accessibility/speakup/devsynth.c | 57 +-
drivers/accessibility/speakup/speakup.h | 2 +
drivers/accessibility/speakup/synth.c | 92 +-
drivers/acpi/arm64/amba.c | 8 -
drivers/android/binder.c | 2 +-
drivers/android/binder_internal.h | 2 +-
drivers/base/property.c | 14 -
drivers/bus/mhi/host/init.c | 41 +-
drivers/bus/mhi/host/internal.h | 4 +-
drivers/bus/mhi/host/main.c | 16 +
drivers/bus/mhi/host/pci_generic.c | 45 +
drivers/bus/mhi/host/pm.c | 42 +-
drivers/cdx/controller/cdx_controller.c | 6 +-
drivers/char/mem.c | 6 +-
drivers/char/powernv-op-panel.c | 5 +-
drivers/char/ppdev.c | 15 +-
drivers/char/sonypi.c | 6 +-
drivers/comedi/drivers/cb_pcidas64.c | 5 -
drivers/counter/counter-core.c | 4 +-
drivers/counter/stm32-timer-cnt.c | 461 ++++++-
drivers/counter/ti-ecap-capture.c | 8 +-
drivers/counter/ti-eqep.c | 6 +-
drivers/extcon/Kconfig | 3 +-
drivers/extcon/extcon-adc-jack.c | 8 +-
drivers/extcon/extcon-intel-cht-wc.c | 6 +-
drivers/extcon/extcon-intel-mrfld.c | 26 +-
drivers/extcon/extcon-max3355.c | 6 +-
drivers/extcon/extcon-max77843.c | 6 +-
drivers/extcon/extcon-rtk-type-c.c | 1 -
drivers/extcon/extcon-usb-gpio.c | 6 +-
drivers/extcon/extcon-usbc-cros-ec.c | 6 +-
drivers/fpga/Kconfig | 12 +
drivers/fpga/Makefile | 2 +
drivers/fpga/altera-cvp.c | 1 -
drivers/fpga/altera-ps-spi.c | 1 -
drivers/fpga/dfl-afu-main.c | 2 -
drivers/fpga/dfl-afu.h | 3 -
drivers/fpga/dfl-fme-main.c | 2 -
drivers/fpga/dfl-fme.h | 2 -
drivers/fpga/dfl.h | 5 -
drivers/fpga/fpga-bridge.c | 57 +-
drivers/fpga/fpga-mgr.c | 82 +-
drivers/fpga/fpga-region.c | 24 +-
drivers/fpga/ice40-spi.c | 4 +-
drivers/fpga/tests/fpga-bridge-test.c | 33 +-
drivers/fpga/tests/fpga-mgr-test.c | 16 +-
drivers/fpga/tests/fpga-region-test.c | 41 +-
drivers/fpga/xilinx-core.c | 229 ++++
drivers/fpga/xilinx-core.h | 27 +
drivers/fpga/xilinx-selectmap.c | 95 ++
drivers/fpga/xilinx-spi.c | 224 +---
drivers/greybus/interface.c | 1 +
drivers/hv/Makefile | 2 +-
drivers/hv/channel_mgmt.c | 15 +-
drivers/hv/hv_fcopy.c | 427 ------
drivers/hv/hv_util.c | 12 -
drivers/hv/hyperv_vmbus.h | 5 +
drivers/hwtracing/coresight/coresight-catu.c | 137 +-
drivers/hwtracing/coresight/coresight-catu.h | 1 +
drivers/hwtracing/coresight/coresight-core.c | 29 +
drivers/hwtracing/coresight/coresight-cpu-debug.c | 137 +-
drivers/hwtracing/coresight/coresight-etm4x-core.c | 29 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 31 +-
drivers/hwtracing/coresight/coresight-funnel.c | 87 +-
drivers/hwtracing/coresight/coresight-priv.h | 10 +
drivers/hwtracing/coresight/coresight-replicator.c | 82 +-
drivers/hwtracing/coresight/coresight-stm.c | 114 +-
drivers/hwtracing/coresight/coresight-tmc-core.c | 181 ++-
drivers/hwtracing/coresight/coresight-tmc.h | 2 +
drivers/hwtracing/coresight/coresight-tpiu.c | 120 +-
drivers/hwtracing/intel_th/acpi.c | 6 +-
drivers/hwtracing/intel_th/core.c | 8 +-
drivers/hwtracing/intel_th/gth.c | 8 +-
drivers/hwtracing/intel_th/msu.c | 12 +-
drivers/hwtracing/intel_th/pci.c | 30 +
drivers/hwtracing/intel_th/sth.c | 2 +-
drivers/hwtracing/ptt/hisi_ptt.c | 1 +
drivers/hwtracing/stm/console.c | 1 +
drivers/hwtracing/stm/core.c | 19 +-
drivers/hwtracing/stm/ftrace.c | 1 +
drivers/hwtracing/stm/heartbeat.c | 1 +
drivers/hwtracing/stm/p_basic.c | 3 +-
drivers/hwtracing/stm/p_sys-t.c | 93 +-
drivers/hwtracing/stm/stm.h | 2 +-
drivers/iio/Makefile | 1 +
drivers/iio/accel/adxl345.h | 36 +-
drivers/iio/accel/adxl345_core.c | 92 +-
drivers/iio/accel/adxl345_i2c.c | 2 +-
drivers/iio/accel/adxl345_spi.c | 10 +-
drivers/iio/accel/adxl367.c | 2 +-
drivers/iio/accel/bmc150-accel-core.c | 44 +-
drivers/iio/accel/fxls8962af-core.c | 10 +-
drivers/iio/accel/kxcjk-1013.c | 80 +-
drivers/iio/accel/mma8452.c | 6 +-
drivers/iio/accel/mxc4005.c | 22 +
drivers/iio/adc/Kconfig | 27 +
drivers/iio/adc/Makefile | 2 +
drivers/iio/adc/ab8500-gpadc.c | 8 +-
drivers/iio/adc/ad4130.c | 7 +-
drivers/iio/adc/ad7124.c | 55 +-
drivers/iio/adc/ad7173.c | 1180 +++++++++++++++++
drivers/iio/adc/ad7192.c | 38 +-
drivers/iio/adc/ad7266.c | 1 -
drivers/iio/adc/ad7292.c | 13 +-
drivers/iio/adc/ad7944.c | 690 ++++++++++
drivers/iio/adc/ad799x.c | 7 +-
drivers/iio/adc/ad9467.c | 374 +++++-
drivers/iio/adc/ad_sigma_delta.c | 29 +-
drivers/iio/adc/adi-axi-adc.c | 147 ++-
drivers/iio/adc/exynos_adc.c | 16 +-
drivers/iio/adc/fsl-imx25-gcq.c | 150 +--
drivers/iio/adc/hx711.c | 5 +-
drivers/iio/adc/intel_mrfld_adc.c | 12 +-
drivers/iio/adc/max11410.c | 27 +-
drivers/iio/adc/mcp3564.c | 16 +-
drivers/iio/adc/mxs-lradc-adc.c | 1 -
drivers/iio/adc/pac1934.c | 86 +-
drivers/iio/adc/qcom-spmi-adc5.c | 7 +-
drivers/iio/adc/rcar-gyroadc.c | 21 +-
drivers/iio/adc/rtq6056.c | 34 +-
drivers/iio/adc/rzg2l_adc.c | 11 +-
drivers/iio/adc/spear_adc.c | 25 +-
drivers/iio/adc/stm32-adc.c | 71 +-
drivers/iio/adc/stm32-dfsdm-adc.c | 12 +-
drivers/iio/adc/ti-ads1015.c | 5 +-
drivers/iio/adc/ti-ads131e08.c | 12 +-
drivers/iio/adc/twl4030-madc.c | 19 +-
drivers/iio/adc/twl6030-gpadc.c | 8 +-
drivers/iio/addac/ad74413r.c | 10 +-
drivers/iio/buffer/industrialio-buffer-dma.c | 100 +-
drivers/iio/buffer/industrialio-buffer-dmaengine.c | 86 +-
.../iio/common/inv_sensors/inv_sensors_timestamp.c | 33 +-
drivers/iio/dac/Kconfig | 37 +
drivers/iio/dac/Makefile | 2 +
drivers/iio/dac/ad3552r.c | 110 +-
drivers/iio/dac/ad5755.c | 24 +-
drivers/iio/dac/ad5770r.c | 19 +-
drivers/iio/dac/ad9739a.c | 464 +++++++
drivers/iio/dac/adi-axi-dac.c | 635 +++++++++
drivers/iio/dac/ltc2688.c | 28 +-
drivers/iio/dac/ti-dac5571.c | 3 +
drivers/iio/frequency/admfm2000.c | 24 +-
drivers/iio/health/max30102.c | 2 +
drivers/iio/humidity/hdc3020.c | 111 +-
drivers/iio/humidity/hts221_core.c | 2 +-
drivers/iio/imu/inv_icm42600/inv_icm42600.h | 37 +
drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c | 75 +-
drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c | 31 +-
drivers/iio/imu/inv_icm42600/inv_icm42600_core.c | 26 +
drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c | 84 +-
drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c | 6 +
drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c | 6 +
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c | 542 +++++++-
drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h | 36 +-
drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c | 19 +-
drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c | 83 +-
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 2 +-
drivers/iio/industrialio-acpi.c | 85 ++
drivers/iio/industrialio-backend.c | 305 ++++-
drivers/iio/industrialio-buffer.c | 124 +-
drivers/iio/industrialio-core.c | 49 +-
drivers/iio/industrialio-trigger.c | 71 +-
drivers/iio/inkern.c | 263 ++--
drivers/iio/light/Kconfig | 12 +
drivers/iio/light/Makefile | 1 +
drivers/iio/light/apds9306.c | 1361 ++++++++++++++++++++
drivers/iio/light/st_uvis25_core.c | 2 +-
drivers/iio/light/stk3310.c | 1 -
drivers/iio/pressure/bmp280-core.c | 16 +-
drivers/iio/pressure/dps310.c | 138 +-
drivers/iio/pressure/hsc030pa_spi.c | 7 +-
drivers/iio/pressure/zpa2326.c | 10 +-
drivers/iio/temperature/ltc2983.c | 142 +-
drivers/iio/temperature/mcp9600.c | 3 +-
drivers/interconnect/qcom/qcm2290.c | 2 +-
drivers/interconnect/qcom/sm6115.c | 33 +-
drivers/mcb/mcb-lpc.c | 6 +-
drivers/misc/Kconfig | 31 +-
drivers/misc/Makefile | 1 +
drivers/misc/cardreader/rtsx_pcr.c | 12 +-
drivers/misc/ds1682.c | 37 +
drivers/misc/eeprom/at25.c | 1 -
drivers/misc/eeprom/eeprom_93xx46.c | 2 -
drivers/misc/mei/bus.c | 2 +-
drivers/misc/mei/hw.h | 2 -
drivers/misc/ntsync.c | 249 ++++
drivers/misc/pvpanic/pvpanic.c | 43 +-
drivers/misc/ti-st/st_kim.c | 4 +-
drivers/misc/tifm_core.c | 2 +-
drivers/misc/vmw_vmci/vmci_event.c | 6 +-
drivers/misc/vmw_vmci/vmci_guest.c | 10 +-
drivers/nvmem/core.c | 2 +-
drivers/nvmem/layouts.c | 6 +-
drivers/nvmem/layouts/onie-tlv.c | 1 -
drivers/nvmem/layouts/sl28vpd.c | 1 -
drivers/nvmem/lpc18xx_eeprom.c | 6 +-
drivers/nvmem/meson-mx-efuse.c | 6 +-
drivers/nvmem/sc27xx-efuse.c | 1 +
drivers/nvmem/sprd-efuse.c | 1 +
drivers/parport/parport_mfc3.c | 3 +-
drivers/peci/core.c | 4 +-
drivers/peci/device.c | 2 +-
drivers/peci/internal.h | 6 +-
drivers/slimbus/qcom-ctrl.c | 6 +-
drivers/slimbus/qcom-ngd-ctrl.c | 14 +-
drivers/spmi/hisi-spmi-controller.c | 1 -
drivers/spmi/spmi-pmic-arb.c | 980 ++++++++------
drivers/spmi/spmi.c | 2 +-
drivers/uio/Kconfig | 18 -
drivers/uio/Makefile | 1 -
drivers/uio/uio.c | 24 +-
drivers/uio/uio_fsl_elbc_gpcm.c | 6 +-
drivers/uio/uio_hv_generic.c | 19 +-
drivers/uio/uio_pdrv_genirq.c | 10 +-
drivers/uio/uio_pruss.c | 255 ----
drivers/w1/masters/w1-gpio.c | 62 +-
include/linux/coresight.h | 6 +
include/linux/counter.h | 7 +-
include/linux/fpga/fpga-bridge.h | 10 +-
include/linux/fpga/fpga-mgr.h | 26 +-
include/linux/fpga/fpga-region.h | 13 +-
include/linux/hyperv.h | 2 +
include/linux/iio/adc/ad_sigma_delta.h | 3 +
include/linux/iio/backend.h | 107 +-
include/linux/iio/buffer-dma.h | 4 +-
include/linux/iio/buffer-dmaengine.h | 24 +-
include/linux/iio/common/inv_sensors_timestamp.h | 3 +-
include/linux/iio/iio.h | 13 +
include/linux/mfd/stm32-timers.h | 13 +
include/linux/mhi.h | 29 +-
include/linux/nvmem-provider.h | 5 +-
include/linux/platform_data/uio_pruss.h | 18 -
include/linux/property.h | 22 +-
include/linux/stm.h | 12 +
include/uapi/linux/ntsync.h | 23 +
include/uapi/misc/pvpanic.h | 7 +-
samples/acrn/vm-sample.c | 4 +-
scripts/spdxcheck.py | 3 +
tools/hv/Build | 3 +-
tools/hv/Makefile | 14 +-
tools/hv/hv_fcopy_daemon.c | 266 ----
tools/hv/hv_fcopy_uio_daemon.c | 490 +++++++
tools/hv/vmbus_bufring.c | 318 +++++
tools/hv/vmbus_bufring.h | 158 +++
tools/testing/nvdimm/test/ndtest.c | 5 +-
283 files changed, 12915 insertions(+), 3995 deletions(-)
rename Documentation/ABI/testing/{sysfs-devices-hisi_ptt => sysfs-bus-event_source-devices-hisi_ptt} (90%)
create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-ad9739a
create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml
create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad7173.yaml
create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad7944.yaml
create mode 100644 Documentation/devicetree/bindings/iio/dac/adi,ad9739a.yaml
create mode 100644 Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml
delete mode 100644 Documentation/devicetree/bindings/iio/light/avago,apds9960.yaml
create mode 100644 Documentation/devicetree/bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml
create mode 100644 Documentation/iio/ad7944.rst
create mode 100644 drivers/fpga/xilinx-core.c
create mode 100644 drivers/fpga/xilinx-core.h
create mode 100644 drivers/fpga/xilinx-selectmap.c
delete mode 100644 drivers/hv/hv_fcopy.c
create mode 100644 drivers/iio/adc/ad7173.c
create mode 100644 drivers/iio/adc/ad7944.c
create mode 100644 drivers/iio/dac/ad9739a.c
create mode 100644 drivers/iio/dac/adi-axi-dac.c
create mode 100644 drivers/iio/industrialio-acpi.c
create mode 100644 drivers/iio/light/apds9306.c
create mode 100644 drivers/misc/ntsync.c
delete mode 100644 drivers/uio/uio_pruss.c
delete mode 100644 include/linux/platform_data/uio_pruss.h
create mode 100644 include/uapi/linux/ntsync.h
delete mode 100644 tools/hv/hv_fcopy_daemon.c
create mode 100644 tools/hv/hv_fcopy_uio_daemon.c
create mode 100644 tools/hv/vmbus_bufring.c
create mode 100644 tools/hv/vmbus_bufring.h
^ permalink raw reply [relevance 1%]
* [GIT PULL] USB/Thunderbolt driver changes for 6.10-rc1
@ 2024-05-22 14:49 1% Greg KH
0 siblings, 0 replies; 200+ results
From: Greg KH @ 2024-05-22 14:49 UTC (permalink / raw)
To: Linus Torvalds; +Cc: Andrew Morton, linux-kernel, linux-usb
The following changes since commit dd5a440a31fae6e459c0d6271dddd62825505361:
Linux 6.9-rc7 (2024-05-05 14:06:01 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git tags/usb-6.10-rc1
for you to fetch changes up to 51474ab44abf907023a8a875e799b07de461e466:
drm/bridge: aux-hpd-bridge: correct devm_drm_dp_hpd_bridge_add() stub (2024-05-11 13:02:14 +0100)
----------------------------------------------------------------
USB / Thunderbolt changes for 6.10-rc1
Here is the big set of USB and Thunderbolt changes for 6.10-rc1.
Nothing hugely earth-shattering, just constant forward progress for
hardware support of new devices and cleanups over the drivers.
Included in here are:
- Thunderbolt / USB 4 driver updates
- typec driver updates
- dwc3 driver updates
- gadget driver updates
- uss720 driver id additions and fixes (people use USB->arallel port
devices still!)
- onboard-hub driver rename and additions for new hardware
- xhci driver updates
- other small USB driver updates and additions for quirks and api
changes
All of these have been in linux-next for a while with no reported
problems.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----------------------------------------------------------------
Alex Henrie (4):
usb: misc: uss720: point pp->dev to usbdev->dev
usb: misc: uss720: document the names of the compatible devices
usb: misc: uss720: add support for another variant of the Belkin F5U002
usb: misc: uss720: check for incompatible versions of the Belkin F5U002
Alex James (1):
thunderbolt: Enable NVM upgrade support on Intel Maple Ridge
Anand Moon (5):
usb: ehci-exynos: Use devm_clk_get_enabled() helpers
usb: ehci-exynos: Use DEFINE_SIMPLE_DEV_PM_OPS for PM functions
usb: ohci-exynos: Use devm_clk_get_enabled() helpers
usb: ohci-exynos: Use DEFINE_SIMPLE_DEV_PM_OPS for PM functions
usb: dwc3: exynos: Use DEFINE_SIMPLE_DEV_PM_OPS for PM functions
André Draszik (2):
dt-bindings: usb: samsung,exynos-dwc3: add gs101 compatible
usb: dwc3: exynos: add support for Google Tensor gs101
Andy Shevchenko (6):
xhci: pci: Use full names in PCI IDs for Intel platforms
xhci: pci: Group out Thunderbolt xHCI IDs
xhci: pci: Use PCI_VENDOR_ID_RENESAS
usb: phy: tegra: Replace of_gpio.h by proper one
usb: fotg210: Use *-y instead of *-objs in Makefile
usb: fotg210: Add missing kernel doc description
Arnd Bergmann (1):
usb: gadget: omap_udc: remove unused variable
Biju Das (6):
dt-bindings: usb: renesas,usbhs: Document RZ/G2L family compatible
usb: renesas_usbhs: Simplify obtaining device data
usb: renesas_usbhs: Improve usbhsc_default_pipe[] for isochronous transfers
usb: renesas_usbhs: Update usbhs pipe configuration for RZ/G2L family
usb: renesas_usbhs: Remove trailing comma in the terminator entry for OF table
arm64: dts: renesas: r9a07g0{43,44,54}: Update RZ/G2L family compatible
Bo Liu (1):
usb: typec: stusb160x: convert to use maple tree register cache
Chris Wulff (2):
usb: gadget: u_audio: Fix race condition use of controls after free during gadget unbind.
usb: gadget: u_audio: Clear uac pointer when freed.
Christian A. Ehrhardt (3):
usb: typec: ucsi: Stop abuse of bit definitions from ucsi.h
usb: typec: ucsi: Never send a lone connector change ack
usb: typec: ucsi_acpi: Remove Dell quirk
Christophe JAILLET (6):
usb: dwc2: Remove cat_printf()
usb: gadget: u_audio: Fix the size of a buffer in a strscpy() call
usb: gadget: u_audio: Use the 2-argument version of strscpy()
usb: gadget: u_audio: Use snprintf() instead of sprintf()
usb: gadget: function: Remove usage of the deprecated ida_simple_xx() API
usb: core: Remove the useless struct usb_devmap which is just a bitmap
Dingyan Li (1):
USB: Use EHCI control transfer pid macros instead of constant values.
Diogo Ivo (1):
usb: typec: ucsi: Only enable supported notifications
Dmitry Baryshkov (22):
usb: typec: ucsi: allow non-partner GET_PDOS for Qualcomm devices
usb: typec: ucsi: limit the UCSI_NO_PARTNER_PDOS even further
usb: typec: ucsi: properly register partner's PD device
usb: typec: ucsi: always register a link to USB PD device
usb: typec: ucsi: simplify partner's PD caps registration
usb: typec: ucsi: extract code to read PD caps
usb: typec: ucsi: support delaying GET_PDOS for device
usb: typec: ucsi_glink: rework quirks implementation
usb: typec: ucsi_glink: enable the UCSI_DELAY_DEVICE_PDOS quirk
soc: qcom: pmic_glink: reenable UCSI on sc8280xp
soc: qcom: pmic_glink: enable UCSI on sc8180x
usb: typec: ucsi_glink: enable the UCSI_DELAY_DEVICE_PDOS quirk on qcm6490
usb: typec: ucsi_glink: drop NO_PARTNER_PDOS quirk for sm8550 / sm8650
usb: typec: ucsi_glink: drop special handling for CCI_BUSY
usb: typec: ucsi: add callback for connector status updates
usb: typec: ucsi: glink: move GPIO reading into connector_status callback
usb: typec: ucsi: glink: use typec_set_orientation
usb: typec: ucsi: add update_connector callback
usb: typec: ucsi: glink: set orientation aware if supported
dt-bindings: usb: qcom,pmic-typec: update example to follow connector schema
usb: typec: qcom-pmic-typec: split HPD bridge alloc and registration
drm/bridge: aux-hpd-bridge: correct devm_drm_dp_hpd_bridge_add() stub
Dr. David Alan Gilbert (1):
usb: musc: Remove unused list 'buffers'
Fabio Estevam (2):
dt-bindings: usb: Document the Microchip USB2514 hub
dt-bindings: usb: hx3: Remove unneeded dr_mode
Francesco Dolcini (1):
usb: typec: mux: gpio-sbu: Allow GPIO operations to sleep
Geert Uytterhoeven (1):
usb: renesas_usbhs: Remove renesas_usbhs_get_info() wrapper
Gil Fine (4):
thunderbolt: Fix calculation of consumed USB3 bandwidth on a path
thunderbolt: Allow USB3 bandwidth to be lower than maximum supported
thunderbolt: Fix uninitialized variable in tb_tunnel_alloc_usb3()
thunderbolt: Fix kernel-doc for tb_tunnel_alloc_dp()
Greg Kroah-Hartman (4):
Merge 6.9-rc2 into usb-next
Merge 6.9-rc5 into usb-next
Merge 6.9-rc7 into usb-next
Merge tag 'thunderbolt-for-v6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt into usb-next
Guenter Roeck (1):
MAINTAINERS: Remove {ehci,uhci}-platform.c from ARM/VT8500 entry
Hans de Goede (1):
usb: dwc3: pci: Don't set "linux,phy_charger_detect" property on Lenovo Yoga Tab2 1380
Hardik Gajjar (1):
usb: gadget: f_fs: Add the missing get_alt callback
Heikki Krogerus (1):
usb: typec: ucsi: displayport: Fix potential deadlock
Inochi Amaoto (2):
dt-bindings: usb: dwc2: Add support for Sophgo CV18XX/SG200X series SoC
usb: dwc2: add support for Sophgo CV18XX/SG200X series SoC
Javier Carrasco (11):
usb: misc: onboard_hub: use device supply names
usb: misc: onboard_hub: rename to onboard_dev
drm: ci: arm64.config: update ONBOARD_USB_HUB to ONBOARD_USB_DEV
arm64: defconfig: update ONBOARD_USB_HUB to ONBOARD_USB_DEV
ARM: multi_v7_defconfig: update ONBOARD_USB_HUB to ONBOAD_USB_DEV
usb: misc: onboard_dev: add support for non-hub devices
ASoC: dt-bindings: xmos,xvf3500: add XMOS XVF3500 voice processor
usb: misc: onboard_dev: add support for XMOS XVF3500
usb: typec: tipd: fix event checking for tps25750
usb: typec: tipd: fix event checking for tps6598x
usb: typec: tipd: rely on i2c_get_match_data()
Johan Hovold (1):
dt-bindings: usb: qcom,dwc3: fix interrupt max items
Justin Stitt (2):
usb: gadget: u_ether: replace deprecated strncpy with strscpy
usb: gadget: mv_u3d: replace deprecated strncpy with strscpy
Komal Bajaj (1):
dt-bindings: usb: dwc3: Add QDU1000 compatible
Krishna Kurapati (11):
dt-bindings: usb: Add bindings for multiport properties on DWC3 controller
usb: dwc3: core: Access XHCI address space temporarily to read port info
usb: dwc3: core: Skip setting event buffers for host only controllers
usb: dwc3: core: Refactor PHY logic to support Multiport Controller
dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport
usb: dwc3: qcom: Add helper function to request wakeup interrupts
usb: dwc3: qcom: Refactor IRQ handling in glue driver
usb: dwc3: qcom: Enable wakeup for applicable ports of multiport
usb: dwc3: qcom: Add multiport suspend/resume support for wrapper
usb: dwc3: core: Fix compile warning on s390 gcc in dwc3_get_phy call
usb: dwc3: core: Fix unused variable warning in core driver
Krzysztof Kozlowski (3):
usb: phy: fsl-usb: drop driver owner assignment
usb: typec: nvidia: drop driver owner assignment
usb: typec: displayport: drop driver owner assignment
Luca Weiss (2):
usb: typec: ptn36502: switch to DRM_AUX_BRIDGE
dt-bindings: usb: qcom,pmic-typec: Add support for the PM7250B PMIC
Marcello Sylvester Bauer (2):
usb: gadget: dummy_hcd: Switch to hrtimer transfer scheduler
usb: gadget: dummy_hcd: Set transfer interval to 1 microframe
Mathias Nyman (4):
xhci: stored cached port capability values in one place
xhci: remove xhci_check_usb2_port_capability helper
xhci: improve PORTSC register debugging output
xhci: remove XHCI_TRUST_TX_LENGTH quirk
Michael Grzeschik (4):
usb: gadget: uvc: fix try format returns on uncompressed formats
usb: gadget: uvc: configfs: ensure guid to be valid before set
usb: phy-generic: add short delay after pulling the reset pin
usb: chipidea: move ci_ulpi_init after the phy initialization
Mika Westerberg (6):
thunderbolt: Use correct error code with ERROR_NOT_SUPPORTED
thunderbolt: Get rid of TB_CFG_PKG_PREPARE_TO_SLEEP
thunderbolt: Increase sideband access polling delay
thunderbolt: No need to loop over all retimers if access fails
thunderbolt: There are only 5 basic router registers in pre-USB4 routers
thunderbolt: Correct trace output of firmware connection manager packets
Minas Harutyunyan (7):
usb: dwc2: Add core new versions definition
usb: dwc2: New bit definition in GOTGCTL register
usb: dwc2: Add new parameter eusb2_disc
usb: dwc2: Add eUSB2 PHY disconnect flow support
usb: dwc2: New bit definition in GPWRDN register
usb: dwc2: Add hibernation updates for ULPI PHY
usb: dwc2: New bitfield definition and programming in GRSTCTL
Mohammad Shehar Yaar Tausif (1):
dt-bindings: usb: uhci: convert to dt schema
Nathan Chancellor (1):
usb: typec: ptn36502: Only select DRM_AUX_BRIDGE with OF
Niklas Neronin (11):
usb: xhci: check if 'requested segments' exceeds ERST capacity
usb: xhci: improve debug message in xhci_ring_expansion_needed()
usb: xhci: address off-by-one in xhci_num_trbs_free()
usb: xhci: remove redundant variable 'erst_size'
usb: xhci: use array_size() when allocating and freeing memory
usb: xhci: prevent potential failure in handle_tx_event() for Transfer events without TRB
usb: xhci: remove 'handling_skipped_tds' from handle_tx_event()
usb: xhci: replace goto with return when possible in handle_tx_event()
usb: xhci: remove goto 'cleanup' in handle_tx_event()
usb: xhci: remove duplicate TRB_TO_SLOT_ID() calls
usb: xhci: compact 'trb_in_td()' arguments
Oliver Neukum (1):
USB: usb_parse_endpoint: ignore reserved bits
Pavan Holla (1):
usb: typec: ucsi: Wait 20ms before reading CCI after a reset
Prashanth K (1):
usb: dwc3: Wait unconditionally after issuing EndXfer command
Roy Luo (1):
USB: gadget: core: create sysfs link between udc and gadget
Stephen Rothwell (1):
USB: fix up for "usb: misc: onboard_hub: rename to onboard_dev"
Thinh Nguyen (1):
usb: dwc3: Select 2.0 or 3.0 clk base on maximum_speed
Uwe Kleine-König (1):
usb: chipidea: npcm: Convert to platform remove callback returning void
Xu Yang (4):
usb: chipidea: ci_hdrc_imx: align usb wakeup clock name with dt-bindings
dt-bindings: usb: chipidea,usb2-imx: move imx parts to dedicated schema
dt-bindings: usb: ci-hdrc-usb2-imx: add restrictions for reg, interrupts, clock and clock-names properties
dt-bindings: usb: ci-hdrc-usb2-imx: add compatible and clock-names restriction for imx93
...-usb-hub => sysfs-bus-platform-onboard-usb-dev} | 3 +-
.../devicetree/bindings/sound/xmos,xvf3500.yaml | 63 +++
.../bindings/usb/chipidea,usb2-common.yaml | 200 ++++++++
.../devicetree/bindings/usb/chipidea,usb2-imx.yaml | 287 +++++++++++
.../devicetree/bindings/usb/ci-hdrc-usb2.yaml | 360 +-------------
.../devicetree/bindings/usb/cypress,hx3.yaml | 1 -
Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
.../devicetree/bindings/usb/microchip,usb2514.yaml | 63 +++
.../devicetree/bindings/usb/qcom,dwc3.yaml | 41 +-
.../devicetree/bindings/usb/qcom,pmic-typec.yaml | 35 +-
.../devicetree/bindings/usb/renesas,usbhs.yaml | 6 +-
.../bindings/usb/samsung,exynos-dwc3.yaml | 18 +
.../devicetree/bindings/usb/snps,dwc3.yaml | 13 +-
Documentation/devicetree/bindings/usb/usb-uhci.txt | 18 -
.../devicetree/bindings/usb/usb-uhci.yaml | 75 +++
MAINTAINERS | 6 +-
arch/arm/configs/multi_v7_defconfig | 2 +-
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 2 +-
arch/arm64/configs/defconfig | 2 +-
drivers/gpu/drm/ci/arm64.config | 4 +-
drivers/soc/qcom/pmic_glink.c | 5 -
drivers/thunderbolt/debugfs.c | 2 +-
drivers/thunderbolt/icm.c | 1 +
drivers/thunderbolt/retimer.c | 12 +-
drivers/thunderbolt/tb.c | 9 +-
drivers/thunderbolt/tb_msgs.h | 6 -
drivers/thunderbolt/trace.h | 13 +-
drivers/thunderbolt/tunnel.c | 39 +-
drivers/thunderbolt/usb4.c | 22 +-
drivers/thunderbolt/xdomain.c | 2 +-
drivers/usb/chipidea/ci_hdrc_imx.c | 2 +-
drivers/usb/chipidea/ci_hdrc_npcm.c | 6 +-
drivers/usb/chipidea/core.c | 8 +-
drivers/usb/chipidea/ulpi.c | 5 -
drivers/usb/core/Makefile | 4 +-
drivers/usb/core/config.c | 8 +-
drivers/usb/core/hcd.c | 4 +-
drivers/usb/core/hub.c | 17 +-
drivers/usb/core/hub.h | 2 +-
drivers/usb/dwc2/core.c | 42 ++
drivers/usb/dwc2/core.h | 8 +
drivers/usb/dwc2/core_intr.c | 26 +-
drivers/usb/dwc2/debugfs.c | 1 +
drivers/usb/dwc2/gadget.c | 28 +-
drivers/usb/dwc2/hcd.c | 10 +
drivers/usb/dwc2/hcd_queue.c | 52 +-
drivers/usb/dwc2/hw.h | 14 +
drivers/usb/dwc2/params.c | 43 ++
drivers/usb/dwc3/core.c | 320 +++++++++---
drivers/usb/dwc3/core.h | 20 +-
drivers/usb/dwc3/drd.c | 15 +-
drivers/usb/dwc3/dwc3-exynos.c | 22 +-
drivers/usb/dwc3/dwc3-pci.c | 8 +-
drivers/usb/dwc3/dwc3-qcom.c | 265 ++++++----
drivers/usb/dwc3/gadget.c | 4 +-
drivers/usb/fotg210/Makefile | 10 +-
drivers/usb/fotg210/fotg210-core.c | 1 +
drivers/usb/gadget/function/f_fs.c | 20 +-
drivers/usb/gadget/function/f_hid.c | 6 +-
drivers/usb/gadget/function/f_printer.c | 6 +-
drivers/usb/gadget/function/rndis.c | 4 +-
drivers/usb/gadget/function/u_audio.c | 32 +-
drivers/usb/gadget/function/u_ether.c | 2 +-
drivers/usb/gadget/function/uvc_configfs.c | 14 +-
drivers/usb/gadget/function/uvc_v4l2.c | 24 +-
drivers/usb/gadget/udc/core.c | 9 +
drivers/usb/gadget/udc/dummy_hcd.c | 37 +-
drivers/usb/gadget/udc/mv_u3d_core.c | 4 +-
drivers/usb/gadget/udc/omap_udc.c | 10 +-
drivers/usb/host/ehci-dbg.c | 10 +-
drivers/usb/host/ehci-exynos.c | 27 +-
drivers/usb/host/ehci-q.c | 20 +-
drivers/usb/host/ehci.h | 8 +-
drivers/usb/host/ohci-exynos.c | 27 +-
drivers/usb/host/xhci-dbgcap.c | 2 +-
drivers/usb/host/xhci-mem.c | 48 +-
drivers/usb/host/xhci-pci.c | 49 +-
drivers/usb/host/xhci-rcar.c | 6 +-
drivers/usb/host/xhci-ring.c | 138 +++---
drivers/usb/host/xhci.c | 38 +-
drivers/usb/host/xhci.h | 28 +-
drivers/usb/misc/Kconfig | 16 +-
drivers/usb/misc/Makefile | 2 +-
drivers/usb/misc/onboard_usb_dev.c | 550 +++++++++++++++++++++
.../misc/{onboard_usb_hub.h => onboard_usb_dev.h} | 62 ++-
...ard_usb_hub_pdevs.c => onboard_usb_dev_pdevs.c} | 47 +-
drivers/usb/misc/onboard_usb_hub.c | 507 -------------------
drivers/usb/misc/uss720.c | 42 +-
drivers/usb/musb/musb_gadget.c | 9 -
drivers/usb/phy/phy-fsl-usb.c | 1 -
drivers/usb/phy/phy-generic.c | 1 +
drivers/usb/renesas_usbhs/common.c | 41 +-
drivers/usb/renesas_usbhs/rza.h | 1 +
drivers/usb/renesas_usbhs/rza2.c | 13 +
drivers/usb/typec/altmodes/displayport.c | 1 -
drivers/usb/typec/altmodes/nvidia.c | 1 -
drivers/usb/typec/mux/Kconfig | 2 +-
drivers/usb/typec/mux/gpio-sbu-mux.c | 8 +-
drivers/usb/typec/mux/ptn36502.c | 44 +-
drivers/usb/typec/stusb160x.c | 2 +-
drivers/usb/typec/tcpm/qcom/qcom_pmic_typec.c | 10 +-
drivers/usb/typec/tipd/core.c | 56 ++-
drivers/usb/typec/tipd/tps6598x.h | 11 +
drivers/usb/typec/ucsi/displayport.c | 4 -
drivers/usb/typec/ucsi/ucsi.c | 225 +++++----
drivers/usb/typec/ucsi/ucsi.h | 8 +-
drivers/usb/typec/ucsi/ucsi_acpi.c | 56 +--
drivers/usb/typec/ucsi/ucsi_glink.c | 92 ++--
drivers/usb/typec/ucsi/ucsi_stm32g0.c | 1 +
include/drm/bridge/aux-bridge.h | 2 +-
include/linux/thunderbolt.h | 1 -
include/linux/usb.h | 7 +-
include/linux/usb/onboard_dev.h | 18 +
include/linux/usb/onboard_hub.h | 18 -
include/linux/usb/renesas_usbhs.h | 5 -
include/linux/usb/tegra_usb_phy.h | 3 +-
118 files changed, 2755 insertions(+), 1941 deletions(-)
rename Documentation/ABI/testing/{sysfs-bus-platform-onboard-usb-hub => sysfs-bus-platform-onboard-usb-dev} (74%)
create mode 100644 Documentation/devicetree/bindings/sound/xmos,xvf3500.yaml
create mode 100644 Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml
create mode 100644 Documentation/devicetree/bindings/usb/chipidea,usb2-imx.yaml
create mode 100644 Documentation/devicetree/bindings/usb/microchip,usb2514.yaml
delete mode 100644 Documentation/devicetree/bindings/usb/usb-uhci.txt
create mode 100644 Documentation/devicetree/bindings/usb/usb-uhci.yaml
create mode 100644 drivers/usb/misc/onboard_usb_dev.c
rename drivers/usb/misc/{onboard_usb_hub.h => onboard_usb_dev.h} (56%)
rename drivers/usb/misc/{onboard_usb_hub_pdevs.c => onboard_usb_dev_pdevs.c} (68%)
delete mode 100644 drivers/usb/misc/onboard_usb_hub.c
create mode 100644 include/linux/usb/onboard_dev.h
delete mode 100644 include/linux/usb/onboard_hub.h
^ permalink raw reply [relevance 1%]
* Re: [PATCH v1 1/1] spi: Remove unneded check for orig_nents
2024-05-22 13:18 0% ` Neil Armstrong
@ 2024-05-22 14:24 0% ` Andy Shevchenko
2024-05-22 15:12 0% ` Nícolas F. R. A. Prado
0 siblings, 1 reply; 200+ results
From: Andy Shevchenko @ 2024-05-22 14:24 UTC (permalink / raw)
To: Neil Armstrong
Cc: Nícolas F. R. A. Prado, Mark Brown, linux-spi, linux-kernel,
linux-arm-msm
On Wed, May 22, 2024 at 03:18:18PM +0200, Neil Armstrong wrote:
> On 22/05/2024 13:53, Neil Armstrong wrote:
> > On 22/05/2024 13:33, Andy Shevchenko wrote:
> > > On Wed, May 22, 2024 at 12:03:33PM +0200, Neil Armstrong wrote:
> > > > On 15/05/2024 23:09, Nícolas F. R. A. Prado wrote:
> > > > > On Tue, May 07, 2024 at 11:10:27PM +0300, Andy Shevchenko wrote:
> > > > > > Both dma_unmap_sgtable() and sg_free_table() in spi_unmap_buf_attrs()
> > > > > > have checks for orig_nents against 0. No need to duplicate this.
> > > > > > All the same applies to other DMA mapping API calls.
> > > > > >
> > > > > > Also note, there is no other user in the kernel that does this kind of
> > > > > > checks.
> > > > > >
> > > > > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > > > >
> > > > > Hi,
> > > > >
> > > > > this commit caused a regression which I reported here:
> > > > >
> > > > > https://lore.kernel.org/all/d3679496-2e4e-4a7c-97ed-f193bd53af1d@notapiano
> > > > >
> > > > > along with some thoughts on the cause and a possible solution, though I'm not
> > > > > familiar with this code base at all and would really appreciate any feedback you
> > > > > may have.
> > > >
> > > > I also see the same regression on the SM8550 and SM8650 platforms,
> > > > please CC linux-arm-msm@vger.kernel.org and me for a potential fix to test on those platforms.
> > >
> > > There is still no answer from IOMMU patch author. Do you have the same trace
> > > due to IOMMU calls? Anyway, I guess it would be nice to see it.
> >
> > Yes :
> > [ 6.404623] Unable to handle kernel NULL pointer dereference at virtual address 000000000000001c
> > <snip>
> > [ 6.641597] lr : __dma_sync_sg_for_device+0x3c/0x40
> > <snip>
> > [ 6.688286] Call trace:
> > [ 6.688287] iommu_dma_sync_sg_for_device+0x28/0x100
> > [ 6.717582] __dma_sync_sg_for_device+0x3c/0x40
> > [ 6.717585] spi_transfer_one_message+0x358/0x680
> > [ 6.732229] __spi_pump_transfer_message+0x188/0x494
> > [ 6.732232] __spi_sync+0x2a8/0x3c4
> > [ 6.732234] spi_sync+0x30/0x54
> > [ 6.732236] goodix_berlin_spi_write+0xf8/0x164 [goodix_berlin_spi]
> > [ 6.739854] _regmap_raw_write_impl+0x538/0x674
> > [ 6.750053] _regmap_raw_write+0xb4/0x144
> > [ 6.750056] regmap_raw_write+0x7c/0xc0
> > [ 6.750058] goodix_berlin_power_on+0xb0/0x1b0 [goodix_berlin_core]
> > [ 6.765520] goodix_berlin_probe+0xc0/0x660 [goodix_berlin_core]
> > [ 6.765522] goodix_berlin_spi_probe+0x12c/0x14c [goodix_berlin_spi]
> > [ 6.772339] spi_probe+0x84/0xe4
> > [ 6.772342] really_probe+0xbc/0x29c
> > [ 6.784313] __driver_probe_device+0x78/0x12c
> > [ 6.784316] driver_probe_device+0x3c/0x15c
> > [ 6.784319] __driver_attach+0x90/0x19c
> > [ 6.784322] bus_for_each_dev+0x7c/0xdc
> > [ 6.794520] driver_attach+0x24/0x30
> > [ 6.794523] bus_add_driver+0xe4/0x208
> > [ 6.794526] driver_register+0x5c/0x124
> > [ 6.802586] __spi_register_driver+0xa4/0xe4
> > [ 6.802589] goodix_berlin_spi_driver_init+0x20/0x1000 [goodix_berlin_spi]
> > [ 6.802591] do_one_initcall+0x80/0x1c8
> > [ 6.902310] do_init_module+0x60/0x218
> > [ 6.921988] load_module+0x1bcc/0x1d8c
> > [ 6.925847] init_module_from_file+0x88/0xcc
> > [ 6.930238] __arm64_sys_finit_module+0x1dc/0x2e4
> > [ 6.935074] invoke_syscall+0x48/0x114
> > [ 6.938944] el0_svc_common.constprop.0+0xc0/0xe0
> > [ 6.943781] do_el0_svc+0x1c/0x28
> > [ 6.947195] el0_svc+0x34/0xd8
> > [ 6.950348] el0t_64_sync_handler+0x120/0x12c
> > [ 6.954833] el0t_64_sync+0x190/0x194
> > [ 6.958600] Code: 2a0203f5 2a0303f6 a90363f7 aa0003f7 (b9401c2
> >
> > Reverting 8cc3bad9d9d6 ("spi: Remove unneded check for orig_nents") removes the crash.
> >
> > >
> > > Meanwhile, I have three changes I posted in the replies to the initial report,
> > > can you combine them all and test? This will be a plan B (? or A, depending on
> > > the culprit).
> > >
> >
> > I'll try to apply them and test.
>
> I stacked the 3 changes, and it works:
> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Thank you!
I will try to develop and submit a fix against IOMMU which I believe is the
correct place to address this. So, this one will be plan B in case the IOMMU
folks will refuse the other one.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [relevance 0%]
* Re: [PATCH v1 1/1] spi: Remove unneded check for orig_nents
2024-05-22 11:53 0% ` Neil Armstrong
@ 2024-05-22 13:18 0% ` Neil Armstrong
2024-05-22 14:24 0% ` Andy Shevchenko
0 siblings, 1 reply; 200+ results
From: Neil Armstrong @ 2024-05-22 13:18 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Nícolas F. R. A. Prado, Mark Brown, linux-spi, linux-kernel,
linux-arm-msm
Hi,
On 22/05/2024 13:53, Neil Armstrong wrote:
> On 22/05/2024 13:33, Andy Shevchenko wrote:
>> On Wed, May 22, 2024 at 12:03:33PM +0200, Neil Armstrong wrote:
>>> On 15/05/2024 23:09, Nícolas F. R. A. Prado wrote:
>>>> On Tue, May 07, 2024 at 11:10:27PM +0300, Andy Shevchenko wrote:
>>>>> Both dma_unmap_sgtable() and sg_free_table() in spi_unmap_buf_attrs()
>>>>> have checks for orig_nents against 0. No need to duplicate this.
>>>>> All the same applies to other DMA mapping API calls.
>>>>>
>>>>> Also note, there is no other user in the kernel that does this kind of
>>>>> checks.
>>>>>
>>>>> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>>>>
>>>> Hi,
>>>>
>>>> this commit caused a regression which I reported here:
>>>>
>>>> https://lore.kernel.org/all/d3679496-2e4e-4a7c-97ed-f193bd53af1d@notapiano
>>>>
>>>> along with some thoughts on the cause and a possible solution, though I'm not
>>>> familiar with this code base at all and would really appreciate any feedback you
>>>> may have.
>>>
>>> I also see the same regression on the SM8550 and SM8650 platforms,
>>> please CC linux-arm-msm@vger.kernel.org and me for a potential fix to test on those platforms.
>>
>> There is still no answer from IOMMU patch author. Do you have the same trace
>> due to IOMMU calls? Anyway, I guess it would be nice to see it.
>
> Yes :
> [ 6.404623] Unable to handle kernel NULL pointer dereference at virtual address 000000000000001c
> <snip>
> [ 6.641597] lr : __dma_sync_sg_for_device+0x3c/0x40
> <snip>
> [ 6.688286] Call trace:
> [ 6.688287] iommu_dma_sync_sg_for_device+0x28/0x100
> [ 6.717582] __dma_sync_sg_for_device+0x3c/0x40
> [ 6.717585] spi_transfer_one_message+0x358/0x680
> [ 6.732229] __spi_pump_transfer_message+0x188/0x494
> [ 6.732232] __spi_sync+0x2a8/0x3c4
> [ 6.732234] spi_sync+0x30/0x54
> [ 6.732236] goodix_berlin_spi_write+0xf8/0x164 [goodix_berlin_spi]
> [ 6.739854] _regmap_raw_write_impl+0x538/0x674
> [ 6.750053] _regmap_raw_write+0xb4/0x144
> [ 6.750056] regmap_raw_write+0x7c/0xc0
> [ 6.750058] goodix_berlin_power_on+0xb0/0x1b0 [goodix_berlin_core]
> [ 6.765520] goodix_berlin_probe+0xc0/0x660 [goodix_berlin_core]
> [ 6.765522] goodix_berlin_spi_probe+0x12c/0x14c [goodix_berlin_spi]
> [ 6.772339] spi_probe+0x84/0xe4
> [ 6.772342] really_probe+0xbc/0x29c
> [ 6.784313] __driver_probe_device+0x78/0x12c
> [ 6.784316] driver_probe_device+0x3c/0x15c
> [ 6.784319] __driver_attach+0x90/0x19c
> [ 6.784322] bus_for_each_dev+0x7c/0xdc
> [ 6.794520] driver_attach+0x24/0x30
> [ 6.794523] bus_add_driver+0xe4/0x208
> [ 6.794526] driver_register+0x5c/0x124
> [ 6.802586] __spi_register_driver+0xa4/0xe4
> [ 6.802589] goodix_berlin_spi_driver_init+0x20/0x1000 [goodix_berlin_spi]
> [ 6.802591] do_one_initcall+0x80/0x1c8
> [ 6.902310] do_init_module+0x60/0x218
> [ 6.921988] load_module+0x1bcc/0x1d8c
> [ 6.925847] init_module_from_file+0x88/0xcc
> [ 6.930238] __arm64_sys_finit_module+0x1dc/0x2e4
> [ 6.935074] invoke_syscall+0x48/0x114
> [ 6.938944] el0_svc_common.constprop.0+0xc0/0xe0
> [ 6.943781] do_el0_svc+0x1c/0x28
> [ 6.947195] el0_svc+0x34/0xd8
> [ 6.950348] el0t_64_sync_handler+0x120/0x12c
> [ 6.954833] el0t_64_sync+0x190/0x194
> [ 6.958600] Code: 2a0203f5 2a0303f6 a90363f7 aa0003f7 (b9401c2
>
> Reverting 8cc3bad9d9d6 ("spi: Remove unneded check for orig_nents") removes the crash.
>
>>
>> Meanwhile, I have three changes I posted in the replies to the initial report,
>> can you combine them all and test? This will be a plan B (? or A, depending on
>> the culprit).
>>
>
> I'll try to apply them and test.
I stacked the 3 changes, and it works:
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
For reference, the changeset looks like:
============><============================================================================================
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 289feccca376..0851c5e1fd1f 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1220,6 +1220,11 @@ void spi_unmap_buf(struct spi_controller *ctlr, struct device *dev,
spi_unmap_buf_attrs(ctlr, dev, sgt, dir, 0);
}
+/* Dummy SG for unidirect transfers */
+static struct scatterlist dummy_sg = {
+ .page_link = SG_END,
+};
+
static int __spi_map_msg(struct spi_controller *ctlr, struct spi_message *msg)
{
struct device *tx_dev, *rx_dev;
@@ -1243,6 +1248,7 @@ static int __spi_map_msg(struct spi_controller *ctlr, struct spi_message *msg)
else
rx_dev = ctlr->dev.parent;
+ ret = -ENOMSG;
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
/* The sync is done before each transfer. */
unsigned long attrs = DMA_ATTR_SKIP_CPU_SYNC;
@@ -1257,6 +1263,9 @@ static int __spi_map_msg(struct spi_controller *ctlr, struct spi_message *msg)
attrs);
if (ret != 0)
return ret;
+ } else {
+ memset(&xfer->tx_sg, 0, sizeof(xfer->tx_sg));
+ xfer->tx_sg.sgl = &dummy_sg;
}
if (xfer->rx_buf != NULL) {
@@ -1270,8 +1279,14 @@ static int __spi_map_msg(struct spi_controller *ctlr, struct spi_message *msg)
return ret;
}
+ } else {
+ memset(&xfer->rx_sg, 0, sizeof(xfer->rx_sg));
+ xfer->rx_sg.sgl = &dummy_sg;
}
}
+ /* No transfer has been mapped, bail out with success */
+ if (ret)
+ return 0;
ctlr->cur_rx_dma_dev = rx_dev;
ctlr->cur_tx_dma_dev = tx_dev;
============><============================================================================================
Thanks,
Neil
>
> Neil
>
^ permalink raw reply related [relevance 0%]
* Re: [PATCH 1/5] dt-bindings: remoteproc: qcom,sm8550-pas: Document the SA8775p ADSP, CDSP and GPDSP
2024-05-22 13:06 4% ` neil.armstrong
@ 2024-05-22 13:08 4% ` Bartosz Golaszewski
0 siblings, 0 replies; 200+ results
From: Bartosz Golaszewski @ 2024-05-22 13:08 UTC (permalink / raw)
To: neil.armstrong
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Manivannan Sadhasivam, Jassi Brar, Bartosz Golaszewski,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
Tengfei Fan, Srini Kandagatla, Alex Elder
On Wed, May 22, 2024 at 3:06 PM <neil.armstrong@linaro.org> wrote:
>
> On 22/05/2024 15:04, Bartosz Golaszewski wrote:
> > On Wed, May 22, 2024 at 2:42 PM <neil.armstrong@linaro.org> wrote:
> >>
> >> On 22/05/2024 14:08, Bartosz Golaszewski wrote:
> >>> From: Tengfei Fan <quic_tengfan@quicinc.com>
> >>>
> >>> Document the compatibles for the components used to boot the ADSP, CDSP0,
> >>> CDSP1, GPDSP0 and GPDSP1 on the SA8775p SoC.
> >>>
> >>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> >>> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> >>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> >>> ---
> >>> .../bindings/remoteproc/qcom,sm8550-pas.yaml | 76 +++++++++++++++++++++-
> >>> 1 file changed, 75 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
> >>> index 73fda7565cd1..9d3a862c39e1 100644
> >>> --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
> >>> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
> >>> @@ -16,6 +16,11 @@ description:
> >>> properties:
> >>> compatible:
> >>> enum:
> >>> + - qcom,sa8775p-adsp-pas
> >>> + - qcom,sa8775p-cdsp0-pas
> >>> + - qcom,sa8775p-cdsp1-pas
> >>> + - qcom,sa8775p-gpdsp0-pas
> >>> + - qcom,sa8775p-gpdsp1-pas
> >>> - qcom,sm8550-adsp-pas
> >>> - qcom,sm8550-cdsp-pas
> >>> - qcom,sm8550-mpss-pas
> >>> @@ -44,12 +49,13 @@ properties:
> >>>
> >>> firmware-name:
> >>> $ref: /schemas/types.yaml#/definitions/string-array
> >>> + minItems: 1
> >>
> >> This will allow a single firmware name for all compatible,
> >> which is wrong
> >>
> >
> > So increasing the limit from the default under allOf doesn't seem to
> > work, should I instead keep this and make the lower limit stricter for
> > all other models?
>
> Yes add minItems in all the allOf:if: and add the missing allOf:if: for
> the new compatibles to set the minItems, same for memory-region.
>
> Or you may simply spin off a new yaml, this one is getting quite large.
>
Yeah, maybe that's a better idea.
Bart
> Neil
>
> >
> > Bart
> >
> >>> items:
> >>> - description: Firmware name of the Hexagon core
> >>> - description: Firmware name of the Hexagon Devicetree
> >>>
> >>> memory-region:
> >>> - minItems: 2
> >>> + minItems: 1
> >>
> >> Same here
> >>
> >>> items:
> >>> - description: Memory region for main Firmware authentication
> >>> - description: Memory region for Devicetree Firmware authentication
> >>> @@ -81,6 +87,21 @@ allOf:
> >>> maxItems: 5
> >>> memory-region:
> >>> maxItems: 2
> >>> + - if:
> >>> + properties:
> >>> + compatible:
> >>> + enum:
> >>> + - qcom,sa8775p-adsp-pas
> >>> + - qcom,sa8775p-cdsp0-pas
> >>> + - qcom,sa8775p-cdsp1-pas
> >>> + - qcom,sa8775p-gpdsp0-pas
> >>> + - qcom,sa8775p-gpdsp1-pas
> >>> + then:
> >>> + properties:
> >>> + interrupts:
> >>> + maxItems: 5
> >>> + interrupt-names:
> >>> + maxItems: 5
> >>> - if:
> >>> properties:
> >>> compatible:
> >>> @@ -128,6 +149,7 @@ allOf:
> >>> properties:
> >>> compatible:
> >>> enum:
> >>> + - qcom,sa8775p-adsp-pas
> >>> - qcom,sm8550-adsp-pas
> >>> - qcom,sm8650-adsp-pas
> >>> - qcom,x1e80100-adsp-pas
> >>> @@ -177,6 +199,58 @@ allOf:
> >>> - const: cx
> >>> - const: mxc
> >>> - const: nsp
> >>> + - if:
> >>> + properties:
> >>> + compatible:
> >>> + enum:
> >>> + - qcom,sa8775p-cdsp-pas
> >>> + then:
> >>> + properties:
> >>> + power-domains:
> >>> + items:
> >>> + - description: CX power domain
> >>> + - description: MXC power domain
> >>> + - description: NSP0 power domain
> >>> + power-domain-names:
> >>> + items:
> >>> + - const: cx
> >>> + - const: mxc
> >>> + - const: nsp0
> >>> +
> >>> + - if:
> >>> + properties:
> >>> + compatible:
> >>> + enum:
> >>> + - qcom,sa8775p-cdsp1-pas
> >>> + then:
> >>> + properties:
> >>> + power-domains:
> >>> + items:
> >>> + - description: CX power domain
> >>> + - description: MXC power domain
> >>> + - description: NSP1 power domain
> >>> + power-domain-names:
> >>> + items:
> >>> + - const: cx
> >>> + - const: mxc
> >>> + - const: nsp1
> >>> +
> >>> + - if:
> >>> + properties:
> >>> + compatible:
> >>> + enum:
> >>> + - qcom,sa8775p-gpdsp0-pas
> >>> + - qcom,sa8775p-gpdsp1-pas
> >>> + then:
> >>> + properties:
> >>> + power-domains:
> >>> + items:
> >>> + - description: CX power domain
> >>> + - description: MXC power domain
> >>> + power-domain-names:
> >>> + items:
> >>> + - const: cx
> >>> + - const: mxc
> >>>
> >>> unevaluatedProperties: false
> >>>
> >>>
> >>
>
^ permalink raw reply [relevance 4%]
* Re: [PATCH 1/5] dt-bindings: remoteproc: qcom,sm8550-pas: Document the SA8775p ADSP, CDSP and GPDSP
2024-05-22 13:04 4% ` Bartosz Golaszewski
@ 2024-05-22 13:06 4% ` neil.armstrong
2024-05-22 13:08 4% ` Bartosz Golaszewski
0 siblings, 1 reply; 200+ results
From: neil.armstrong @ 2024-05-22 13:06 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Manivannan Sadhasivam, Jassi Brar, Bartosz Golaszewski,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
Tengfei Fan, Srini Kandagatla, Alex Elder
On 22/05/2024 15:04, Bartosz Golaszewski wrote:
> On Wed, May 22, 2024 at 2:42 PM <neil.armstrong@linaro.org> wrote:
>>
>> On 22/05/2024 14:08, Bartosz Golaszewski wrote:
>>> From: Tengfei Fan <quic_tengfan@quicinc.com>
>>>
>>> Document the compatibles for the components used to boot the ADSP, CDSP0,
>>> CDSP1, GPDSP0 and GPDSP1 on the SA8775p SoC.
>>>
>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>>> ---
>>> .../bindings/remoteproc/qcom,sm8550-pas.yaml | 76 +++++++++++++++++++++-
>>> 1 file changed, 75 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
>>> index 73fda7565cd1..9d3a862c39e1 100644
>>> --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
>>> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
>>> @@ -16,6 +16,11 @@ description:
>>> properties:
>>> compatible:
>>> enum:
>>> + - qcom,sa8775p-adsp-pas
>>> + - qcom,sa8775p-cdsp0-pas
>>> + - qcom,sa8775p-cdsp1-pas
>>> + - qcom,sa8775p-gpdsp0-pas
>>> + - qcom,sa8775p-gpdsp1-pas
>>> - qcom,sm8550-adsp-pas
>>> - qcom,sm8550-cdsp-pas
>>> - qcom,sm8550-mpss-pas
>>> @@ -44,12 +49,13 @@ properties:
>>>
>>> firmware-name:
>>> $ref: /schemas/types.yaml#/definitions/string-array
>>> + minItems: 1
>>
>> This will allow a single firmware name for all compatible,
>> which is wrong
>>
>
> So increasing the limit from the default under allOf doesn't seem to
> work, should I instead keep this and make the lower limit stricter for
> all other models?
Yes add minItems in all the allOf:if: and add the missing allOf:if: for
the new compatibles to set the minItems, same for memory-region.
Or you may simply spin off a new yaml, this one is getting quite large.
Neil
>
> Bart
>
>>> items:
>>> - description: Firmware name of the Hexagon core
>>> - description: Firmware name of the Hexagon Devicetree
>>>
>>> memory-region:
>>> - minItems: 2
>>> + minItems: 1
>>
>> Same here
>>
>>> items:
>>> - description: Memory region for main Firmware authentication
>>> - description: Memory region for Devicetree Firmware authentication
>>> @@ -81,6 +87,21 @@ allOf:
>>> maxItems: 5
>>> memory-region:
>>> maxItems: 2
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + enum:
>>> + - qcom,sa8775p-adsp-pas
>>> + - qcom,sa8775p-cdsp0-pas
>>> + - qcom,sa8775p-cdsp1-pas
>>> + - qcom,sa8775p-gpdsp0-pas
>>> + - qcom,sa8775p-gpdsp1-pas
>>> + then:
>>> + properties:
>>> + interrupts:
>>> + maxItems: 5
>>> + interrupt-names:
>>> + maxItems: 5
>>> - if:
>>> properties:
>>> compatible:
>>> @@ -128,6 +149,7 @@ allOf:
>>> properties:
>>> compatible:
>>> enum:
>>> + - qcom,sa8775p-adsp-pas
>>> - qcom,sm8550-adsp-pas
>>> - qcom,sm8650-adsp-pas
>>> - qcom,x1e80100-adsp-pas
>>> @@ -177,6 +199,58 @@ allOf:
>>> - const: cx
>>> - const: mxc
>>> - const: nsp
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + enum:
>>> + - qcom,sa8775p-cdsp-pas
>>> + then:
>>> + properties:
>>> + power-domains:
>>> + items:
>>> + - description: CX power domain
>>> + - description: MXC power domain
>>> + - description: NSP0 power domain
>>> + power-domain-names:
>>> + items:
>>> + - const: cx
>>> + - const: mxc
>>> + - const: nsp0
>>> +
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + enum:
>>> + - qcom,sa8775p-cdsp1-pas
>>> + then:
>>> + properties:
>>> + power-domains:
>>> + items:
>>> + - description: CX power domain
>>> + - description: MXC power domain
>>> + - description: NSP1 power domain
>>> + power-domain-names:
>>> + items:
>>> + - const: cx
>>> + - const: mxc
>>> + - const: nsp1
>>> +
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + enum:
>>> + - qcom,sa8775p-gpdsp0-pas
>>> + - qcom,sa8775p-gpdsp1-pas
>>> + then:
>>> + properties:
>>> + power-domains:
>>> + items:
>>> + - description: CX power domain
>>> + - description: MXC power domain
>>> + power-domain-names:
>>> + items:
>>> + - const: cx
>>> + - const: mxc
>>>
>>> unevaluatedProperties: false
>>>
>>>
>>
^ permalink raw reply [relevance 4%]
* Re: [PATCH 1/5] dt-bindings: remoteproc: qcom,sm8550-pas: Document the SA8775p ADSP, CDSP and GPDSP
2024-05-22 12:42 4% ` neil.armstrong
@ 2024-05-22 13:04 4% ` Bartosz Golaszewski
2024-05-22 13:06 4% ` neil.armstrong
0 siblings, 1 reply; 200+ results
From: Bartosz Golaszewski @ 2024-05-22 13:04 UTC (permalink / raw)
To: neil.armstrong
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Manivannan Sadhasivam, Jassi Brar, Bartosz Golaszewski,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
Tengfei Fan, Srini Kandagatla, Alex Elder
On Wed, May 22, 2024 at 2:42 PM <neil.armstrong@linaro.org> wrote:
>
> On 22/05/2024 14:08, Bartosz Golaszewski wrote:
> > From: Tengfei Fan <quic_tengfan@quicinc.com>
> >
> > Document the compatibles for the components used to boot the ADSP, CDSP0,
> > CDSP1, GPDSP0 and GPDSP1 on the SA8775p SoC.
> >
> > Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> > Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> > ---
> > .../bindings/remoteproc/qcom,sm8550-pas.yaml | 76 +++++++++++++++++++++-
> > 1 file changed, 75 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
> > index 73fda7565cd1..9d3a862c39e1 100644
> > --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
> > +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
> > @@ -16,6 +16,11 @@ description:
> > properties:
> > compatible:
> > enum:
> > + - qcom,sa8775p-adsp-pas
> > + - qcom,sa8775p-cdsp0-pas
> > + - qcom,sa8775p-cdsp1-pas
> > + - qcom,sa8775p-gpdsp0-pas
> > + - qcom,sa8775p-gpdsp1-pas
> > - qcom,sm8550-adsp-pas
> > - qcom,sm8550-cdsp-pas
> > - qcom,sm8550-mpss-pas
> > @@ -44,12 +49,13 @@ properties:
> >
> > firmware-name:
> > $ref: /schemas/types.yaml#/definitions/string-array
> > + minItems: 1
>
> This will allow a single firmware name for all compatible,
> which is wrong
>
So increasing the limit from the default under allOf doesn't seem to
work, should I instead keep this and make the lower limit stricter for
all other models?
Bart
> > items:
> > - description: Firmware name of the Hexagon core
> > - description: Firmware name of the Hexagon Devicetree
> >
> > memory-region:
> > - minItems: 2
> > + minItems: 1
>
> Same here
>
> > items:
> > - description: Memory region for main Firmware authentication
> > - description: Memory region for Devicetree Firmware authentication
> > @@ -81,6 +87,21 @@ allOf:
> > maxItems: 5
> > memory-region:
> > maxItems: 2
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - qcom,sa8775p-adsp-pas
> > + - qcom,sa8775p-cdsp0-pas
> > + - qcom,sa8775p-cdsp1-pas
> > + - qcom,sa8775p-gpdsp0-pas
> > + - qcom,sa8775p-gpdsp1-pas
> > + then:
> > + properties:
> > + interrupts:
> > + maxItems: 5
> > + interrupt-names:
> > + maxItems: 5
> > - if:
> > properties:
> > compatible:
> > @@ -128,6 +149,7 @@ allOf:
> > properties:
> > compatible:
> > enum:
> > + - qcom,sa8775p-adsp-pas
> > - qcom,sm8550-adsp-pas
> > - qcom,sm8650-adsp-pas
> > - qcom,x1e80100-adsp-pas
> > @@ -177,6 +199,58 @@ allOf:
> > - const: cx
> > - const: mxc
> > - const: nsp
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - qcom,sa8775p-cdsp-pas
> > + then:
> > + properties:
> > + power-domains:
> > + items:
> > + - description: CX power domain
> > + - description: MXC power domain
> > + - description: NSP0 power domain
> > + power-domain-names:
> > + items:
> > + - const: cx
> > + - const: mxc
> > + - const: nsp0
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - qcom,sa8775p-cdsp1-pas
> > + then:
> > + properties:
> > + power-domains:
> > + items:
> > + - description: CX power domain
> > + - description: MXC power domain
> > + - description: NSP1 power domain
> > + power-domain-names:
> > + items:
> > + - const: cx
> > + - const: mxc
> > + - const: nsp1
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - qcom,sa8775p-gpdsp0-pas
> > + - qcom,sa8775p-gpdsp1-pas
> > + then:
> > + properties:
> > + power-domains:
> > + items:
> > + - description: CX power domain
> > + - description: MXC power domain
> > + power-domain-names:
> > + items:
> > + - const: cx
> > + - const: mxc
> >
> > unevaluatedProperties: false
> >
> >
>
^ permalink raw reply [relevance 4%]
* Re: [PATCH 1/5] dt-bindings: remoteproc: qcom,sm8550-pas: Document the SA8775p ADSP, CDSP and GPDSP
2024-05-22 12:08 23% ` [PATCH 1/5] dt-bindings: remoteproc: qcom,sm8550-pas: Document the SA8775p " Bartosz Golaszewski
@ 2024-05-22 12:42 4% ` neil.armstrong
2024-05-22 13:04 4% ` Bartosz Golaszewski
0 siblings, 1 reply; 200+ results
From: neil.armstrong @ 2024-05-22 12:42 UTC (permalink / raw)
To: Bartosz Golaszewski, Bjorn Andersson, Mathieu Poirier,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Manivannan Sadhasivam, Jassi Brar
Cc: Bartosz Golaszewski, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Tengfei Fan, Srini Kandagatla, Alex Elder
On 22/05/2024 14:08, Bartosz Golaszewski wrote:
> From: Tengfei Fan <quic_tengfan@quicinc.com>
>
> Document the compatibles for the components used to boot the ADSP, CDSP0,
> CDSP1, GPDSP0 and GPDSP1 on the SA8775p SoC.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
> .../bindings/remoteproc/qcom,sm8550-pas.yaml | 76 +++++++++++++++++++++-
> 1 file changed, 75 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
> index 73fda7565cd1..9d3a862c39e1 100644
> --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
> @@ -16,6 +16,11 @@ description:
> properties:
> compatible:
> enum:
> + - qcom,sa8775p-adsp-pas
> + - qcom,sa8775p-cdsp0-pas
> + - qcom,sa8775p-cdsp1-pas
> + - qcom,sa8775p-gpdsp0-pas
> + - qcom,sa8775p-gpdsp1-pas
> - qcom,sm8550-adsp-pas
> - qcom,sm8550-cdsp-pas
> - qcom,sm8550-mpss-pas
> @@ -44,12 +49,13 @@ properties:
>
> firmware-name:
> $ref: /schemas/types.yaml#/definitions/string-array
> + minItems: 1
This will allow a single firmware name for all compatible,
which is wrong
> items:
> - description: Firmware name of the Hexagon core
> - description: Firmware name of the Hexagon Devicetree
>
> memory-region:
> - minItems: 2
> + minItems: 1
Same here
> items:
> - description: Memory region for main Firmware authentication
> - description: Memory region for Devicetree Firmware authentication
> @@ -81,6 +87,21 @@ allOf:
> maxItems: 5
> memory-region:
> maxItems: 2
> + - if:
> + properties:
> + compatible:
> + enum:
> + - qcom,sa8775p-adsp-pas
> + - qcom,sa8775p-cdsp0-pas
> + - qcom,sa8775p-cdsp1-pas
> + - qcom,sa8775p-gpdsp0-pas
> + - qcom,sa8775p-gpdsp1-pas
> + then:
> + properties:
> + interrupts:
> + maxItems: 5
> + interrupt-names:
> + maxItems: 5
> - if:
> properties:
> compatible:
> @@ -128,6 +149,7 @@ allOf:
> properties:
> compatible:
> enum:
> + - qcom,sa8775p-adsp-pas
> - qcom,sm8550-adsp-pas
> - qcom,sm8650-adsp-pas
> - qcom,x1e80100-adsp-pas
> @@ -177,6 +199,58 @@ allOf:
> - const: cx
> - const: mxc
> - const: nsp
> + - if:
> + properties:
> + compatible:
> + enum:
> + - qcom,sa8775p-cdsp-pas
> + then:
> + properties:
> + power-domains:
> + items:
> + - description: CX power domain
> + - description: MXC power domain
> + - description: NSP0 power domain
> + power-domain-names:
> + items:
> + - const: cx
> + - const: mxc
> + - const: nsp0
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - qcom,sa8775p-cdsp1-pas
> + then:
> + properties:
> + power-domains:
> + items:
> + - description: CX power domain
> + - description: MXC power domain
> + - description: NSP1 power domain
> + power-domain-names:
> + items:
> + - const: cx
> + - const: mxc
> + - const: nsp1
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - qcom,sa8775p-gpdsp0-pas
> + - qcom,sa8775p-gpdsp1-pas
> + then:
> + properties:
> + power-domains:
> + items:
> + - description: CX power domain
> + - description: MXC power domain
> + power-domain-names:
> + items:
> + - const: cx
> + - const: mxc
>
> unevaluatedProperties: false
>
>
^ permalink raw reply [relevance 4%]
* [PATCH 1/5] dt-bindings: remoteproc: qcom,sm8550-pas: Document the SA8775p ADSP, CDSP and GPDSP
2024-05-22 12:08 5% [PATCH 0/5] arm64: qcom: sa8775p: enable remoteprocs - ADSP, CDSP and GPDSP Bartosz Golaszewski
@ 2024-05-22 12:08 23% ` Bartosz Golaszewski
2024-05-22 12:42 4% ` neil.armstrong
0 siblings, 1 reply; 200+ results
From: Bartosz Golaszewski @ 2024-05-22 12:08 UTC (permalink / raw)
To: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Manivannan Sadhasivam, Jassi Brar
Cc: Bartosz Golaszewski, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Tengfei Fan, Srini Kandagatla, Alex Elder
From: Tengfei Fan <quic_tengfan@quicinc.com>
Document the compatibles for the components used to boot the ADSP, CDSP0,
CDSP1, GPDSP0 and GPDSP1 on the SA8775p SoC.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
.../bindings/remoteproc/qcom,sm8550-pas.yaml | 76 +++++++++++++++++++++-
1 file changed, 75 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
index 73fda7565cd1..9d3a862c39e1 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
@@ -16,6 +16,11 @@ description:
properties:
compatible:
enum:
+ - qcom,sa8775p-adsp-pas
+ - qcom,sa8775p-cdsp0-pas
+ - qcom,sa8775p-cdsp1-pas
+ - qcom,sa8775p-gpdsp0-pas
+ - qcom,sa8775p-gpdsp1-pas
- qcom,sm8550-adsp-pas
- qcom,sm8550-cdsp-pas
- qcom,sm8550-mpss-pas
@@ -44,12 +49,13 @@ properties:
firmware-name:
$ref: /schemas/types.yaml#/definitions/string-array
+ minItems: 1
items:
- description: Firmware name of the Hexagon core
- description: Firmware name of the Hexagon Devicetree
memory-region:
- minItems: 2
+ minItems: 1
items:
- description: Memory region for main Firmware authentication
- description: Memory region for Devicetree Firmware authentication
@@ -81,6 +87,21 @@ allOf:
maxItems: 5
memory-region:
maxItems: 2
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sa8775p-adsp-pas
+ - qcom,sa8775p-cdsp0-pas
+ - qcom,sa8775p-cdsp1-pas
+ - qcom,sa8775p-gpdsp0-pas
+ - qcom,sa8775p-gpdsp1-pas
+ then:
+ properties:
+ interrupts:
+ maxItems: 5
+ interrupt-names:
+ maxItems: 5
- if:
properties:
compatible:
@@ -128,6 +149,7 @@ allOf:
properties:
compatible:
enum:
+ - qcom,sa8775p-adsp-pas
- qcom,sm8550-adsp-pas
- qcom,sm8650-adsp-pas
- qcom,x1e80100-adsp-pas
@@ -177,6 +199,58 @@ allOf:
- const: cx
- const: mxc
- const: nsp
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sa8775p-cdsp-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: CX power domain
+ - description: MXC power domain
+ - description: NSP0 power domain
+ power-domain-names:
+ items:
+ - const: cx
+ - const: mxc
+ - const: nsp0
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sa8775p-cdsp1-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: CX power domain
+ - description: MXC power domain
+ - description: NSP1 power domain
+ power-domain-names:
+ items:
+ - const: cx
+ - const: mxc
+ - const: nsp1
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sa8775p-gpdsp0-pas
+ - qcom,sa8775p-gpdsp1-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: CX power domain
+ - description: MXC power domain
+ power-domain-names:
+ items:
+ - const: cx
+ - const: mxc
unevaluatedProperties: false
--
2.43.0
^ permalink raw reply related [relevance 23%]
* [PATCH 0/5] arm64: qcom: sa8775p: enable remoteprocs - ADSP, CDSP and GPDSP
@ 2024-05-22 12:08 5% Bartosz Golaszewski
2024-05-22 12:08 23% ` [PATCH 1/5] dt-bindings: remoteproc: qcom,sm8550-pas: Document the SA8775p " Bartosz Golaszewski
0 siblings, 1 reply; 200+ results
From: Bartosz Golaszewski @ 2024-05-22 12:08 UTC (permalink / raw)
To: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Manivannan Sadhasivam, Jassi Brar
Cc: Bartosz Golaszewski, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Tengfei Fan, Srini Kandagatla, Alex Elder
Add DT bindings, relevant DT defines, DTS nodes and driver changes
required to enable the remoteprocs on sa8775p.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
Bartosz Golaszewski (1):
arm64: dts: qcom: sa8775p-ride: enable remoteprocs
Tengfei Fan (4):
dt-bindings: remoteproc: qcom,sm8550-pas: Document the SA8775p ADSP, CDSP and GPDSP
dt-bindings: mailbox: qcom-ipcc: Add GPDSP0 and GPDSP1 clients
remoteproc: qcom_q6v5_pas: Add support for SA8775p ADSP, CDSP and GPDSP
arm64: dts: qcom: sa8775p: add ADSP, CDSP and GPDSP nodes
.../bindings/remoteproc/qcom,sm8550-pas.yaml | 76 ++++-
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 25 ++
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 332 +++++++++++++++++++++
drivers/remoteproc/qcom_q6v5_pas.c | 92 ++++++
include/dt-bindings/mailbox/qcom-ipcc.h | 2 +
5 files changed, 526 insertions(+), 1 deletion(-)
---
base-commit: 124cfbcd6d185d4f50be02d5f5afe61578916773
change-id: 20240507-topic-lemans-iot-remoteproc-6647b50281e2
Best regards,
--
Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
^ permalink raw reply [relevance 5%]
* Re: [PATCH v1 1/1] spi: Remove unneded check for orig_nents
2024-05-22 11:33 0% ` Andy Shevchenko
@ 2024-05-22 11:53 0% ` Neil Armstrong
2024-05-22 13:18 0% ` Neil Armstrong
0 siblings, 1 reply; 200+ results
From: Neil Armstrong @ 2024-05-22 11:53 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Nícolas F. R. A. Prado, Mark Brown, linux-spi, linux-kernel,
linux-arm-msm
On 22/05/2024 13:33, Andy Shevchenko wrote:
> On Wed, May 22, 2024 at 12:03:33PM +0200, Neil Armstrong wrote:
>> On 15/05/2024 23:09, Nícolas F. R. A. Prado wrote:
>>> On Tue, May 07, 2024 at 11:10:27PM +0300, Andy Shevchenko wrote:
>>>> Both dma_unmap_sgtable() and sg_free_table() in spi_unmap_buf_attrs()
>>>> have checks for orig_nents against 0. No need to duplicate this.
>>>> All the same applies to other DMA mapping API calls.
>>>>
>>>> Also note, there is no other user in the kernel that does this kind of
>>>> checks.
>>>>
>>>> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>>>
>>> Hi,
>>>
>>> this commit caused a regression which I reported here:
>>>
>>> https://lore.kernel.org/all/d3679496-2e4e-4a7c-97ed-f193bd53af1d@notapiano
>>>
>>> along with some thoughts on the cause and a possible solution, though I'm not
>>> familiar with this code base at all and would really appreciate any feedback you
>>> may have.
>>
>> I also see the same regression on the SM8550 and SM8650 platforms,
>> please CC linux-arm-msm@vger.kernel.org and me for a potential fix to test on those platforms.
>
> There is still no answer from IOMMU patch author. Do you have the same trace
> due to IOMMU calls? Anyway, I guess it would be nice to see it.
Yes :
[ 6.404623] Unable to handle kernel NULL pointer dereference at virtual address 000000000000001c
<snip>
[ 6.641597] lr : __dma_sync_sg_for_device+0x3c/0x40
<snip>
[ 6.688286] Call trace:
[ 6.688287] iommu_dma_sync_sg_for_device+0x28/0x100
[ 6.717582] __dma_sync_sg_for_device+0x3c/0x40
[ 6.717585] spi_transfer_one_message+0x358/0x680
[ 6.732229] __spi_pump_transfer_message+0x188/0x494
[ 6.732232] __spi_sync+0x2a8/0x3c4
[ 6.732234] spi_sync+0x30/0x54
[ 6.732236] goodix_berlin_spi_write+0xf8/0x164 [goodix_berlin_spi]
[ 6.739854] _regmap_raw_write_impl+0x538/0x674
[ 6.750053] _regmap_raw_write+0xb4/0x144
[ 6.750056] regmap_raw_write+0x7c/0xc0
[ 6.750058] goodix_berlin_power_on+0xb0/0x1b0 [goodix_berlin_core]
[ 6.765520] goodix_berlin_probe+0xc0/0x660 [goodix_berlin_core]
[ 6.765522] goodix_berlin_spi_probe+0x12c/0x14c [goodix_berlin_spi]
[ 6.772339] spi_probe+0x84/0xe4
[ 6.772342] really_probe+0xbc/0x29c
[ 6.784313] __driver_probe_device+0x78/0x12c
[ 6.784316] driver_probe_device+0x3c/0x15c
[ 6.784319] __driver_attach+0x90/0x19c
[ 6.784322] bus_for_each_dev+0x7c/0xdc
[ 6.794520] driver_attach+0x24/0x30
[ 6.794523] bus_add_driver+0xe4/0x208
[ 6.794526] driver_register+0x5c/0x124
[ 6.802586] __spi_register_driver+0xa4/0xe4
[ 6.802589] goodix_berlin_spi_driver_init+0x20/0x1000 [goodix_berlin_spi]
[ 6.802591] do_one_initcall+0x80/0x1c8
[ 6.902310] do_init_module+0x60/0x218
[ 6.921988] load_module+0x1bcc/0x1d8c
[ 6.925847] init_module_from_file+0x88/0xcc
[ 6.930238] __arm64_sys_finit_module+0x1dc/0x2e4
[ 6.935074] invoke_syscall+0x48/0x114
[ 6.938944] el0_svc_common.constprop.0+0xc0/0xe0
[ 6.943781] do_el0_svc+0x1c/0x28
[ 6.947195] el0_svc+0x34/0xd8
[ 6.950348] el0t_64_sync_handler+0x120/0x12c
[ 6.954833] el0t_64_sync+0x190/0x194
[ 6.958600] Code: 2a0203f5 2a0303f6 a90363f7 aa0003f7 (b9401c2
Reverting 8cc3bad9d9d6 ("spi: Remove unneded check for orig_nents") removes the crash.
>
> Meanwhile, I have three changes I posted in the replies to the initial report,
> can you combine them all and test? This will be a plan B (? or A, depending on
> the culprit).
>
I'll try to apply them and test.
Neil
^ permalink raw reply [relevance 0%]
* Re: [PATCH v1 1/1] spi: Remove unneded check for orig_nents
2024-05-22 10:03 4% ` Neil Armstrong
@ 2024-05-22 11:33 0% ` Andy Shevchenko
2024-05-22 11:53 0% ` Neil Armstrong
0 siblings, 1 reply; 200+ results
From: Andy Shevchenko @ 2024-05-22 11:33 UTC (permalink / raw)
To: Neil Armstrong
Cc: Nícolas F. R. A. Prado, Mark Brown, linux-spi, linux-kernel,
linux-arm-msm
On Wed, May 22, 2024 at 12:03:33PM +0200, Neil Armstrong wrote:
> On 15/05/2024 23:09, Nícolas F. R. A. Prado wrote:
> > On Tue, May 07, 2024 at 11:10:27PM +0300, Andy Shevchenko wrote:
> > > Both dma_unmap_sgtable() and sg_free_table() in spi_unmap_buf_attrs()
> > > have checks for orig_nents against 0. No need to duplicate this.
> > > All the same applies to other DMA mapping API calls.
> > >
> > > Also note, there is no other user in the kernel that does this kind of
> > > checks.
> > >
> > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> >
> > Hi,
> >
> > this commit caused a regression which I reported here:
> >
> > https://lore.kernel.org/all/d3679496-2e4e-4a7c-97ed-f193bd53af1d@notapiano
> >
> > along with some thoughts on the cause and a possible solution, though I'm not
> > familiar with this code base at all and would really appreciate any feedback you
> > may have.
>
> I also see the same regression on the SM8550 and SM8650 platforms,
> please CC linux-arm-msm@vger.kernel.org and me for a potential fix to test on those platforms.
There is still no answer from IOMMU patch author. Do you have the same trace
due to IOMMU calls? Anyway, I guess it would be nice to see it.
Meanwhile, I have three changes I posted in the replies to the initial report,
can you combine them all and test? This will be a plan B (? or A, depending on
the culprit).
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [relevance 0%]
* Re: [PATCH v1 1/1] spi: Remove unneded check for orig_nents
@ 2024-05-22 10:03 4% ` Neil Armstrong
2024-05-22 11:33 0% ` Andy Shevchenko
0 siblings, 1 reply; 200+ results
From: Neil Armstrong @ 2024-05-22 10:03 UTC (permalink / raw)
To: Nícolas F. R. A. Prado, Andy Shevchenko
Cc: Mark Brown, linux-spi, linux-kernel, linux-arm-msm
Hi,
On 15/05/2024 23:09, Nícolas F. R. A. Prado wrote:
> On Tue, May 07, 2024 at 11:10:27PM +0300, Andy Shevchenko wrote:
>> Both dma_unmap_sgtable() and sg_free_table() in spi_unmap_buf_attrs()
>> have checks for orig_nents against 0. No need to duplicate this.
>> All the same applies to other DMA mapping API calls.
>>
>> Also note, there is no other user in the kernel that does this kind of
>> checks.
>>
>> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Hi,
>
> this commit caused a regression which I reported here:
>
> https://lore.kernel.org/all/d3679496-2e4e-4a7c-97ed-f193bd53af1d@notapiano
>
> along with some thoughts on the cause and a possible solution, though I'm not
> familiar with this code base at all and would really appreciate any feedback you
> may have.
I also see the same regression on the SM8550 and SM8650 platforms,
please CC linux-arm-msm@vger.kernel.org and me for a potential fix to test on those platforms.
Thanks,
Neil
>
> Thanks,
> Nícolas
>
^ permalink raw reply [relevance 4%]
* Re: [REGRESSION] boot regression on linux-next on sc7180 platforms - null pointer dereference on iommu_dma_sync_sg_for_device
@ 2024-05-22 10:00 4% ` Neil Armstrong
0 siblings, 0 replies; 200+ results
From: Neil Armstrong @ 2024-05-22 10:00 UTC (permalink / raw)
To: Nícolas F. R. A. Prado, regressions; +Cc: linux-kernel, kernel
Hi,
On 14/05/2024 18:41, Nícolas F. R. A. Prado wrote:
> Hi,
>
> KernelCI has identified a new boot regression on linux-next. It affects the
> following platforms:
> * sc7180-trogdor-kingoftown
> * sc7180-trogdor-lazor-limozeen
I also see the regression on:
- SM8550-QRD
- SM8560-QRD
reverting commit 8cc3bad9d9d6 ("spi: Remove unneded check for orig_nents") removes the issue.
Thanks for reporting this,
Neil
[ 6.404623] Unable to handle kernel NULL pointer dereference at virtual address 000000000000001c
[ 6.413685] Mem abort info:
[ 6.416574] ESR = 0x0000000096000006
[ 6.420436] EC = 0x25: DABT (current EL), IL = 32 bits
[ 6.425901] SET = 0, FnV = 0
[ 6.429046] EA = 0, S1PTW = 0
[ 6.432293] FSC = 0x06: level 2 translation fault
[ 6.437320] Data abort info:
[ 6.440289] ISV = 0, ISS = 0x00000006, ISS2 = 0x00000000
[ 6.445927] CM = 0, WnR = 0, TnD = 0, TagAccess = 0
[ 6.451121] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
[ 6.456585] user pgtable: 4k pages, 48-bit VAs, pgdp=000000088f68b000
[ 6.463208] [000000000000001c] pgd=080000088f68d003, p4d=080000088f68d003, pud=080000088f68e003, pmd=0000000000000000
[ 6.474108] Internal error: Oops: 0000000096000006 [#1] PREEMPT SMP
[ 6.480542] Modules linked in: ucsi_glink pmic_glink_altmode goodix_berlin_spi(+) nb7vpq904m wcd939x_usbss qcom_battmgr typec_ucsi aux_hpd_bridge goodix_berlin_core crct10dif_ce hci_uart rtc_pm8xxx leds_qcom_lpg led_class_multicolor qcom_pon nvmem_qcom_spmi_sdam sm3_ce qcom_pbs btqca snd_soc_wcd939x snd_soc_sc8280xp snd_soc_wcd939x_sdw phy_qcom_eusb2_repeater snd_soc_qcom_sdw regmap_sdw qcom_spmi_temp_alarm snd_soc_qcom_common btbcm snd_soc_wcd_mbhc sm3 qcom_stats snd_soc_wcd_classh drm_dp_aux_bus sha3_ce gpu_sched sha512_ce sha512_arm64 drm_exec bluetooth qcom_q6v5_pas phy_qcom_qmp_combo qcrypto soundwire_qcom qcom_pil_info snd_soc_lpass_va_macro pinctrl_sm8650_lpass_lpi authenc snd_soc_lpass_tx_macro aux_bridge cfg80211 spi_geni_qcom i2c_qcom_geni snd_soc_lpass_rx_macro rfkill phy_qcom_snps_eusb2 dispcc_sm8650 drm_display_helper pinctrl_lpass_lpi gpi snd_soc_lpass_wsa_macro snd_soc_lpass_macro_common slimbus drm_kms_helper gpucc_sm8650 ipa qcom_q6v5 qrtr libdes phy_qcom_qmp_ufs qcom_sysmon qcom_common
[ 6.480602] qcom_glink_smem
[ 6.571649] soundwire_bus mdt_loader pmic_glink qcom_rng phy_qcom_qmp_pcie llcc_qcom ufs_qcom icc_bwmon typec rmtfs_mem pdr_interface qmi_helpers nvmem_reboot_mode socinfo fuse drm backlight ipv6
[ 6.597201] CPU: 4 PID: 241 Comm: (udev-worker) Tainted: G S 6.9.0-next-20240521 #1
[ 6.606488] Hardware name: Qualcomm Technologies, Inc. SM8650 QRD (DT)
[ 6.613189] pstate: 63400005 (nZCv daif +PAN -UAO +TCO +DIT -SSBS BTYPE=--)
[ 6.641597] lr : __dma_sync_sg_for_device+0x3c/0x40
[ 6.646632] sp : ffff800081bf3260
[ 6.660650] x26: ffff59520fbd1c80 x25: 0000000000000000 x24: ffffb46fccd24988
[ 6.660653] x23: ffff595201628410 x22: 0000000000000002 x21: 0000000000000000
[ 6.660655] x20: ffff800081bf33f0 x19: 0000000000000000 x18: 0000000000000001
[ 6.660656] x17: 0000000000000018 x16: 0000000000000100 x15: 0000000000000002
[ 6.688275] x14: 0000000000000001 x13: ffff595200995180 x12: 000000000025a5c8
[ 6.688277] x11: 0000000000000820 x10: 0000000000000001 x9 : ffff59520fbd1c69
[ 6.688279] x8 : ffff595202169704 x7 : 00000000ffffffff x6 : 0000000000000001
[ 6.688281] x5 : fffffdffbf7a8cc0 x4 : ffffb46fcc0232a4 x3 : 0000000000000002
[ 6.688283] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff595201628410
[ 6.688286] Call trace:
[ 6.688287] iommu_dma_sync_sg_for_device+0x28/0x100
[ 6.717582] __dma_sync_sg_for_device+0x3c/0x40
[ 6.717585] spi_transfer_one_message+0x358/0x680
[ 6.732229] __spi_pump_transfer_message+0x188/0x494
[ 6.732232] __spi_sync+0x2a8/0x3c4
[ 6.732234] spi_sync+0x30/0x54
[ 6.732236] goodix_berlin_spi_write+0xf8/0x164 [goodix_berlin_spi]
[ 6.739854] _regmap_raw_write_impl+0x538/0x674
[ 6.750053] _regmap_raw_write+0xb4/0x144
[ 6.750056] regmap_raw_write+0x7c/0xc0
[ 6.750058] goodix_berlin_power_on+0xb0/0x1b0 [goodix_berlin_core]
[ 6.765520] goodix_berlin_probe+0xc0/0x660 [goodix_berlin_core]
[ 6.765522] goodix_berlin_spi_probe+0x12c/0x14c [goodix_berlin_spi]
[ 6.772339] spi_probe+0x84/0xe4
[ 6.772342] really_probe+0xbc/0x29c
[ 6.784313] __driver_probe_device+0x78/0x12c
[ 6.784316] driver_probe_device+0x3c/0x15c
[ 6.784319] __driver_attach+0x90/0x19c
[ 6.784322] bus_for_each_dev+0x7c/0xdc
[ 6.794520] driver_attach+0x24/0x30
[ 6.794523] bus_add_driver+0xe4/0x208
[ 6.794526] driver_register+0x5c/0x124
[ 6.802586] __spi_register_driver+0xa4/0xe4
[ 6.802589] goodix_berlin_spi_driver_init+0x20/0x1000 [goodix_berlin_spi]
[ 6.802591] do_one_initcall+0x80/0x1c8
[ 6.902310] do_init_module+0x60/0x218
[ 6.921988] load_module+0x1bcc/0x1d8c
[ 6.925847] init_module_from_file+0x88/0xcc
[ 6.930238] __arm64_sys_finit_module+0x1dc/0x2e4
[ 6.935074] invoke_syscall+0x48/0x114
[ 6.938944] el0_svc_common.constprop.0+0xc0/0xe0
[ 6.943781] do_el0_svc+0x1c/0x28
[ 6.947195] el0_svc+0x34/0xd8
[ 6.950348] el0t_64_sync_handler+0x120/0x12c
[ 6.954833] el0t_64_sync+0x190/0x194
[ 6.958600] Code: 2a0203f5 2a0303f6 a90363f7 aa0003f7 (b9401c20)
[ 6.964859] ---[ end trace 0000000000000000 ]---
>
> The regression was introduced in next-20240509, and still affects today's
> (next-20240514) release.
>
> The config used was the upstream arm64 defconfig with a config fragment on top
> [1].
>
> The following stack traces are produced during boot and a usable shell is never
> reached:
>
> [ 0.381981] Unable to handle kernel NULL pointer dereference at virtual address 000000000000001c
> [ 0.381989] Mem abort info:
> [ 0.381991] ESR = 0x0000000096000004
> [ 0.381994] EC = 0x25: DABT (current EL), IL = 32 bits
> [ 0.381997] SET = 0, FnV = 0
> [ 0.382000] EA = 0, S1PTW = 0
> [ 0.382003] FSC = 0x04: level 0 translation fault
> [ 0.382006] Data abort info:
> [ 0.382008] ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
> [ 0.382011] CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> [ 0.382014] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> [ 0.382017] [000000000000001c] user address but active_mm is swapper
> [ 0.382021] Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP
> [ 0.382025] Modules linked in:
> [ 0.382032] CPU: 4 PID: 68 Comm: kworker/u32:2 Not tainted 6.9.0-next-20240514-dirty #380
> [ 0.382038] Hardware name: Google Kingoftown (DT)
> [ 0.382042] Workqueue: async async_run_entry_fn
> [ 0.382055] pstate: 80400009 (Nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [ 0.382061] pc : iommu_dma_sync_sg_for_device+0x28/0x100
> [ 0.382070] lr : __dma_sync_sg_for_device+0x28/0x4c
> [ 0.382080] sp : ffff800080943740
> [ 0.382082] x29: ffff800080943740 x28: ffff36ee44280000 x27: ffff36ee40bd7810
> [ 0.382092] x26: ffff800080943998 x25: ffff36ee44280480 x24: ffffb54600bcf0e8
> [ 0.382101] x23: ffff36ee40bd7810 x22: 0000000000000001 x21: 0000000000000000
> [ 0.382110] x20: ffffb54600f3d098 x19: 0000000000000000 x18: ffffb54601c1a210
> [ 0.382118] x17: 000000040044ffff x16: 0000000000000000 x15: ffff36efb6d95580
> [ 0.382126] x14: ffff36ee409156c0 x13: 0000000000001797 x12: 0000000000000002
> [ 0.382134] x11: 0000000000000004 x10: ffff36ee4308b3d8 x9 : ffff36ee44280469
> [ 0.382143] x8 : ffff36ee4308b304 x7 : 00000000ffffffff x6 : 0000000000000001
> [ 0.382151] x5 : ffffb5460033a740 x4 : ffffb545ff50375c x3 : 0000000000000001
> [ 0.382159] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff36ee40bd7810
> [ 0.382167] Call trace:
> [ 0.382170] iommu_dma_sync_sg_for_device+0x28/0x100
> [ 0.382176] __dma_sync_sg_for_device+0x28/0x4c
> [ 0.382183] spi_transfer_one_message+0x378/0x6e4
> [ 0.382193] __spi_pump_transfer_message+0x190/0x4a4
> [ 0.382199] __spi_sync+0x2a0/0x3c4
> [ 0.382205] spi_sync_locked+0x10/0x1c
> [ 0.382211] tpm_tis_spi_transfer_full+0x160/0x2fc
> [ 0.382217] tpm_tis_spi_transfer+0x34/0x40
> [ 0.382221] tpm_tis_spi_cr50_read_bytes+0x5c/0x90
> [ 0.382226] tpm_tis_core_init+0xfc/0x7e0
> [ 0.382231] tpm_tis_spi_init+0x54/0x70
> [ 0.382236] cr50_spi_probe+0xf4/0x27c
> [ 0.382241] tpm_tis_spi_driver_probe+0x34/0x64
> [ 0.382245] spi_probe+0x84/0xe4
> [ 0.382251] really_probe+0xbc/0x2a0
> [ 0.382258] __driver_probe_device+0x78/0x12c
> [ 0.382264] driver_probe_device+0x40/0x160
> [ 0.382269] __device_attach_driver+0xb8/0x134
> [ 0.382275] bus_for_each_drv+0x84/0xe0
> [ 0.382280] __device_attach_async_helper+0xac/0xd0
> [ 0.382286] async_run_entry_fn+0x34/0xe0
> [ 0.382291] process_one_work+0x154/0x298
> [ 0.382300] worker_thread+0x304/0x408
> [ 0.382307] kthread+0x118/0x11c
> [ 0.382313] ret_from_fork+0x10/0x20
> [ 0.382324] Code: 2a0203f5 2a0303f6 a90363f7 aa0003f7 (b9401c20)
> [ 0.382328] ---[ end trace 0000000000000000 ]---
>
> [ 0.393379] spi_master spi6: will run message pump with realtime priority
> [ 0.393896] Unable to handle kernel NULL pointer dereference at virtual address 000000000000001c
> [ 0.393903] Mem abort info:
> [ 0.393905] ESR = 0x0000000096000004
> [ 0.393908] EC = 0x25: DABT (current EL), IL = 32 bits
> [ 0.393912] SET = 0, FnV = 0
> [ 0.393915] EA = 0, S1PTW = 0
> [ 0.393917] FSC = 0x04: level 0 translation fault
> [ 0.393920] Data abort info:
> [ 0.393922] ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
> [ 0.393925] CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> [ 0.393928] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> [ 0.393931] [000000000000001c] user address but active_mm is swapper
> [ 0.393935] Internal error: Oops: 0000000096000004 [#2] PREEMPT SMP
> [ 0.393939] Modules linked in:
> [ 0.393946] CPU: 2 PID: 103 Comm: cros_ec_spi_hig Tainted: G D 6.9.0-next-20240514-dirty #380
> [ 0.393953] Hardware name: Google Kingoftown (DT)
> [ 0.393956] pstate: 80400009 (Nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [ 0.393962] pc : iommu_dma_sync_sg_for_device+0x28/0x100
> [ 0.393975] lr : __dma_sync_sg_for_device+0x28/0x4c
> [ 0.393985] sp : ffff800080de3aa0
> [ 0.393988] x29: ffff800080de3aa0 x28: ffff36ee44281800 x27: ffff36ee40ff8010
> [ 0.393997] x26: ffff800080de3cf8 x25: ffff36ee44281c80 x24: ffffb54600bcf0e8
> [ 0.394006] x23: ffff36ee40ff8010 x22: 0000000000000001 x21: 0000000000000000
> [ 0.394014] x20: ffffb54600f3d3d8 x19: 0000000000000000 x18: ffffb54601c1a210
> [ 0.394023] x17: 0000000000010108 x16: 0000000000000000 x15: 000000000000000c
> [ 0.394031] x14: 0000000000000000 x13: ffff36ee40b962b0 x12: 0000000000000000
> [ 0.394039] x11: 0000000000000000 x10: 0000000000003fff x9 : ffff36ee44281c69
> [ 0.394047] x8 : ffff36ee4103e704 x7 : 00000000ffffffff x6 : 0000000000000001
> [ 0.394055] x5 : ffffb5460033a740 x4 : ffffb545ff50375c x3 : 0000000000000001
> [ 0.394063] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff36ee40ff8010
> [ 0.394071] Call trace:
> [ 0.394074] iommu_dma_sync_sg_for_device+0x28/0x100
> [ 0.394081] __dma_sync_sg_for_device+0x28/0x4c
> [ 0.394088] spi_transfer_one_message+0x378/0x6e4
> [ 0.394096] __spi_pump_transfer_message+0x190/0x4a4
> [ 0.394103] __spi_sync+0x2a0/0x3c4
> [ 0.394109] spi_sync_locked+0x10/0x1c
> [ 0.394115] do_cros_ec_pkt_xfer_spi+0x108/0x530
> [ 0.394122] cros_ec_xfer_high_pri_work+0x20/0x34
> [ 0.394127] kthread_worker_fn+0xcc/0x184
> [ 0.394134] kthread+0x118/0x11c
> [ 0.394140] ret_from_fork+0x10/0x20
> [ 0.394150] Code: 2a0203f5 2a0303f6 a90363f7 aa0003f7 (b9401c20)
> [ 0.394154] ---[ end trace 0000000000000000 ]---
>
> [ 3.654117] Unable to handle kernel NULL pointer dereference at virtual address 000000000000001c
> [ 3.663154] Mem abort info:
> [ 3.666032] ESR = 0x0000000096000004
> [ 3.669943] EC = 0x25: DABT (current EL), IL = 32 bits
> [ 3.675417] SET = 0, FnV = 0
> [ 3.678563] EA = 0, S1PTW = 0
> [ 3.681792] FSC = 0x04: level 0 translation fault
> [ 3.686808] Data abort info:
> [ 3.689765] ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
> [ 3.695399] CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> [ 3.700592] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> [ 3.706050] [000000000000001c] user address but active_mm is swapper
> [ 3.712576] Internal error: Oops: 0000000096000004 [#3] PREEMPT SMP
> [ 3.719017] Modules linked in:
> [ 3.722162] CPU: 6 PID: 11 Comm: kworker/u32:0 Tainted: G D 6.9.0-next-20240514-dirty #380
> [ 3.732067] Hardware name: Google Kingoftown (DT)
> [ 3.736904] Workqueue: events_unbound deferred_probe_work_func
> [ 3.742907] pstate: 80400009 (Nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [ 3.750052] pc : iommu_dma_sync_sg_for_device+0x28/0x100
> [ 3.755526] lr : __dma_sync_sg_for_device+0x28/0x4c
> [ 3.760548] sp : ffff8000800ab0b0
> [ 3.763953] x29: ffff8000800ab0b0 x28: ffff36ee43a6a000 x27: ffff36ee41012010
> [ 3.771279] x26: ffff8000800ab2e8 x25: ffff36ee43a6a480 x24: ffffb54600bcf0e8
> [ 3.778604] x23: ffff36ee41012010 x22: 0000000000000001 x21: 0000000000000000
> [ 3.785928] x20: ffffb54600f3d718 x19: 0000000000000000 x18: ffffb54601c19c48
> [ 3.793258] x17: 0000000000010108 x16: 0000000000000000 x15: 000000000000000c
> [ 3.800589] x14: 0000000000000000 x13: ffff36ee40b962b0 x12: 0000000000000000
> [ 3.807921] x11: 071c71c71c71c71c x10: 0000000000003fff x9 : ffff36ee43a6a469
> [ 3.815254] x8 : ffff36ee4101cf04 x7 : 00000000ffffffff x6 : 0000000000000001
> [ 3.822587] x5 : ffffb5460033a740 x4 : ffffb545ff50375c x3 : 0000000000000001
> [ 3.829910] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff36ee41012010
> [ 3.837234] Call trace:
> [ 3.839750] iommu_dma_sync_sg_for_device+0x28/0x100
> [ 3.844853] __dma_sync_sg_for_device+0x28/0x4c
> [ 3.849517] spi_transfer_one_message+0x378/0x6e4
> [ 3.854360] __spi_pump_transfer_message+0x190/0x4a4
> [ 3.859462] __spi_sync+0x2a0/0x3c4
> [ 3.863048] spi_sync+0x30/0x54
> [ 3.866283] spi_mem_exec_op+0x26c/0x41c
> [ 3.870321] spi_nor_read_id+0x7c/0xc4
> [ 3.874180] spi_nor_detect+0x34/0x158
> [ 3.878039] spi_nor_scan+0x1f0/0xef8
> [ 3.881813] spi_nor_probe+0x94/0x2ec
> [ 3.885587] spi_mem_probe+0x6c/0xac
> [ 3.889262] spi_probe+0x84/0xe4
> [ 3.892579] really_probe+0xbc/0x2a0
> [ 3.896262] __driver_probe_device+0x78/0x12c
> [ 3.900747] driver_probe_device+0x40/0x160
> [ 3.905046] __device_attach_driver+0xb8/0x134
> [ 3.909619] bus_for_each_drv+0x84/0xe0
> [ 3.913568] __device_attach+0xa8/0x1b0
> [ 3.917515] device_initial_probe+0x14/0x20
> [ 3.921814] bus_probe_device+0xa8/0xac
> [ 3.925761] device_add+0x590/0x750
> [ 3.929351] __spi_add_device+0x138/0x208
> [ 3.933476] of_register_spi_device+0x394/0x57c
> [ 3.938139] spi_register_controller+0x394/0x760
> [ 3.942888] qcom_qspi_probe+0x328/0x390
> [ 3.946928] platform_probe+0x68/0xd8
> [ 3.950701] really_probe+0xbc/0x2a0
> [ 3.954384] __driver_probe_device+0x78/0x12c
> [ 3.958869] driver_probe_device+0x40/0x160
> [ 3.963169] __device_attach_driver+0xb8/0x134
> [ 3.967734] bus_for_each_drv+0x84/0xe0
> [ 3.971682] __device_attach+0xa8/0x1b0
> [ 3.975628] device_initial_probe+0x14/0x20
> [ 3.979927] bus_probe_device+0xa8/0xac
> [ 3.983873] deferred_probe_work_func+0x88/0xc0
> [ 3.988536] process_one_work+0x154/0x298
> [ 3.992663] worker_thread+0x304/0x408
> [ 3.996525] kthread+0x118/0x11c
> [ 3.999847] ret_from_fork+0x10/0x20
> [ 4.003534] Code: 2a0203f5 2a0303f6 a90363f7 aa0003f7 (b9401c20)
> [ 4.009788] ---[ end trace 0000000000000000 ]---
>
> Searching on lore I could only find the following series that caused another
> regression, and its subsequent fix:
> https://lore.kernel.org/lkml/20240507112026.1803778-1-aleksander.lobakin@intel.com/
> https://lore.kernel.org/all/20240509144616.938519-1-aleksander.lobakin@intel.com/
>
> But even after reverting both the issue was still there, so I've concluded
> that's unrelated.
>
> Thanks,
> Nícolas
>
> #regzbot introduced: next-20240509
>
> [1] https://pastebin.com/raw/sx4bPAa6
>
^ permalink raw reply [relevance 4%]
* [PATCH RFC v3 7/9] arm64: boot: dts: qcom: Use phandles for thermal_zones
2024-05-21 18:37 6% ` Elliot Berman
@ 2024-05-21 18:38 9% ` Elliot Berman
-1 siblings, 0 replies; 200+ results
From: Elliot Berman @ 2024-05-21 18:38 UTC (permalink / raw)
To: Rob Herring, Frank Rowand, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Amrit Anand, Peter Griffin, Caleb Connolly, Andy Gross,
Konrad Dybcio, Doug Anderson, Simon Glass, Chen-Yu Tsai,
Julius Werner, Humphreys, Jonathan, Sumit Garg, Jon Hunter,
Michal Simek, boot-architecture, devicetree, linux-kernel,
linux-arm-kernel, linux-arm-msm, Elliot Berman
In preparation for converting sm8550 to use devicetree overlays, use
phandles for thermal_zones.
Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
---
arch/arm64/boot/dts/qcom/pm8010.dtsi | 62 ++++++++--------
arch/arm64/boot/dts/qcom/pm8550.dtsi | 32 ++++----
arch/arm64/boot/dts/qcom/pm8550b.dtsi | 36 +++++----
arch/arm64/boot/dts/qcom/pm8550ve.dtsi | 38 +++++-----
arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 128 ++++++++++++++++----------------
arch/arm64/boot/dts/qcom/pmr735d_a.dtsi | 38 +++++-----
arch/arm64/boot/dts/qcom/pmr735d_b.dtsi | 38 +++++-----
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
9 files changed, 181 insertions(+), 195 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/pm8010.dtsi b/arch/arm64/boot/dts/qcom/pm8010.dtsi
index 0ea641e12209..a889df2f2f25 100644
--- a/arch/arm64/boot/dts/qcom/pm8010.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8010.dtsi
@@ -6,47 +6,45 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pm8010-m-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
+&thermal_zones {
+ pm8010-m-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
- thermal-sensors = <&pm8010_m_temp_alarm>;
+ thermal-sensors = <&pm8010_m_temp_alarm>;
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
+ };
- pm8010-n-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
+ pm8010-n-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
- thermal-sensors = <&pm8010_n_temp_alarm>;
+ thermal-sensors = <&pm8010_n_temp_alarm>;
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi
index 797a18c249a4..cb5e70b28445 100644
--- a/arch/arm64/boot/dts/qcom/pm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi
@@ -6,26 +6,24 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pm8550-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
+&thermal_zones {
+ pm8550-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
- thermal-sensors = <&pm8550_temp_alarm>;
+ thermal-sensors = <&pm8550_temp_alarm>;
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/pm8550b.dtsi b/arch/arm64/boot/dts/qcom/pm8550b.dtsi
index 72609f31c890..b3cfa030679a 100644
--- a/arch/arm64/boot/dts/qcom/pm8550b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550b.dtsi
@@ -6,26 +6,24 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pm8550b-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
-
- thermal-sensors = <&pm8550b_temp_alarm>;
-
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+&thermal_zones {
+ pm8550b-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8550b_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi
index 4dc1f03ab2c7..8ef57a51b5cd 100644
--- a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi
@@ -6,26 +6,24 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pm8550ve-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
-
- thermal-sensors = <&pm8550ve_temp_alarm>;
-
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
-
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+&thermal_zones {
+ pm8550ve-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8550ve_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi
index 97b1c18aa7d8..258526abcc21 100644
--- a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi
@@ -6,89 +6,87 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pm8550vs-c-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
-
- thermal-sensors = <&pm8550vs_c_temp_alarm>;
-
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
-
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+&thermal_zones {
+ pm8550vs-c-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8550vs_c_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
+ };
- pm8550vs-d-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
+ pm8550vs-d-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
- thermal-sensors = <&pm8550vs_d_temp_alarm>;
+ thermal-sensors = <&pm8550vs_d_temp_alarm>;
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
+ };
- pm8550vs-e-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
+ pm8550vs-e-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
- thermal-sensors = <&pm8550vs_e_temp_alarm>;
+ thermal-sensors = <&pm8550vs_e_temp_alarm>;
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
+ };
- pm8550vs-g-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
+ pm8550vs-g-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
- thermal-sensors = <&pm8550vs_g_temp_alarm>;
+ thermal-sensors = <&pm8550vs_g_temp_alarm>;
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi b/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi
index 37daaefe3431..251a16424d84 100644
--- a/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi
@@ -6,26 +6,24 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pmr735d-k-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
-
- thermal-sensors = <&pmr735d_k_temp_alarm>;
-
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
-
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+&thermal_zones {
+ pmr735d-k-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pmr735d_k_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi b/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi
index 3b470f6ac46f..dbcfeb53d8ec 100644
--- a/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi
@@ -6,26 +6,24 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pmr735d-l-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
-
- thermal-sensors = <&pmr735d_l_temp_alarm>;
-
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
-
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+&thermal_zones {
+ pmr735d-l-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pmr735d_l_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index ee1ba5a8c8fc..c68e08747b6f 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -4452,7 +4452,7 @@ compute-cb@8 {
};
};
- thermal-zones {
+ thermal_zones: thermal-zones {
aoss0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 2df77123a8c7..32198bf3cf7c 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5030,7 +5030,7 @@ compute-cb@8 {
};
};
- thermal-zones {
+ thermal_zones: thermal-zones {
aoss0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
--
2.34.1
^ permalink raw reply related [relevance 9%]
* [PATCH RFC v3 8/9] arm64: boot: dts: qcom: sm8550: Split into overlays
2024-05-21 18:37 6% ` Elliot Berman
@ 2024-05-21 18:38 42% ` Elliot Berman
-1 siblings, 0 replies; 200+ results
From: Elliot Berman @ 2024-05-21 18:38 UTC (permalink / raw)
To: Rob Herring, Frank Rowand, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Amrit Anand, Peter Griffin, Caleb Connolly, Andy Gross,
Konrad Dybcio, Doug Anderson, Simon Glass, Chen-Yu Tsai,
Julius Werner, Humphreys, Jonathan, Sumit Garg, Jon Hunter,
Michal Simek, boot-architecture, devicetree, linux-kernel,
linux-arm-kernel, linux-arm-msm, Elliot Berman
Generic sm8550 devicetree is split into a dtsi. Move it into its own DTB
and preserve the boards as overlays.
When not using overlays, 264 KB needed to store the sm8550-mtp.dtb and
sm8550-qrd.dtb. When using overlays, 188 KB is needed to store
sm8550.dtb, sm8550-mtp.dtbo, and sm8550-qrd.dtbo; where the overlays are
~36 KB.
Also add the board-ids for these DTBs.
This change is not intended to be merged, it breaks aliases and I doubt
it boots correct. The intent here is to show how board-id could be used
with a DTB and DTBO.
Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
---
arch/arm64/boot/dts/qcom/Makefile | 4 ++++
.../dts/qcom/{sm8550-mtp.dts => sm8550-mtp.dtso} | 24 ++++++++++++++++++++--
.../dts/qcom/{sm8550-qrd.dts => sm8550-qrd.dtso} | 22 +++++++++++++++++---
.../boot/dts/qcom/{sm8550.dtsi => sm8550.dts} | 8 ++++++++
4 files changed, 53 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 39889d5f8e12..7f137f274d8c 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -233,6 +233,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
+
+sm8550-mtp-dtbs := sm8550.dtb sm8550-mtp.dtbo
+sm8550-qrd-dtbs := sm8550.dtb sm8550-qrd.dtbo
+
dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dtso
similarity index 98%
rename from arch/arm64/boot/dts/qcom/sm8550-mtp.dts
rename to arch/arm64/boot/dts/qcom/sm8550-mtp.dtso
index c1135ad5fa69..0ee4614719ca 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dtso
@@ -4,9 +4,12 @@
*/
/dts-v1/;
+/plugin/;
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include "sm8550.dtsi"
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "pm8010.dtsi"
#include "pm8550.dtsi"
#include "pm8550b.dtsi"
@@ -17,13 +20,30 @@
#include "pmr735d_a.dtsi"
#include "pmr735d_b.dtsi"
+#define BOARD_ID qcom,soc = <QCOM_ID_SM8550>; \
+ qcom,platform-type = <QCOM_BOARD_ID_MTP 0>
+
/ {
+ board-id {
+ BOARD_ID;
+ };
+};
+
+&{/} {
model = "Qualcomm Technologies, Inc. SM8550 MTP";
compatible = "qcom,sm8550-mtp", "qcom,sm8550";
chassis-type = "handset";
+ /**
+ * Redefine the overlay in the DTBO so the sm8550-mtp.dtb that Kbuild
+ * generates has accurate board-id.
+ */
+ board-id {
+ BOARD_ID;
+ };
+
aliases {
- serial0 = &uart7;
+ // serial0 = &uart7;
};
wcd938x: audio-codec {
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dtso
similarity index 98%
rename from arch/arm64/boot/dts/qcom/sm8550-qrd.dts
rename to arch/arm64/boot/dts/qcom/sm8550-qrd.dtso
index d401d63e5c4d..f756c50a80b9 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dtso
@@ -4,10 +4,14 @@
*/
/dts-v1/;
+/plugin/;
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include "sm8550.dtsi"
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "pm8010.dtsi"
#include "pm8550.dtsi"
#include "pm8550b.dtsi"
@@ -19,13 +23,25 @@
#include "pmr735d_b.dtsi"
/ {
+ board-id {
+ qcom,soc = <QCOM_ID_SM8550>;
+ qcom,platform = <QCOM_BOARD_ID_QRD>;
+ };
+};
+
+&{/} {
model = "Qualcomm Technologies, Inc. SM8550 QRD";
compatible = "qcom,sm8550-qrd", "qcom,sm8550";
chassis-type = "handset";
+ board-id {
+ qcom,soc = <QCOM_ID_SM8550>;
+ qcom,platform = <QCOM_BOARD_ID_QRD>;
+ };
+
aliases {
- serial0 = &uart7;
- serial1 = &uart14;
+ // serial0 = &uart7;
+ // serial1 = &uart14;
};
wcd938x: audio-codec {
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dts
similarity index 99%
rename from arch/arm64/boot/dts/qcom/sm8550.dtsi
rename to arch/arm64/boot/dts/qcom/sm8550.dts
index c68e08747b6f..3546ea4b96f1 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dts
@@ -3,6 +3,9 @@
* Copyright (c) 2022, Linaro Limited
*/
+/dts-v1/;
+
+#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
#include <dt-bindings/clock/qcom,sm8550-camcc.h>
@@ -32,6 +35,11 @@ / {
chosen { };
+ board_id: board-id {
+ qcom,soc-version = <QCOM_ID_SM8550 QCOM_SOC_REVISION(1)>,
+ <QCOM_ID_SM8550 QCOM_SOC_REVISION(2)>;
+ };
+
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
--
2.34.1
^ permalink raw reply related [relevance 42%]
* [PATCH RFC v3 0/9] dt-bindings: hwinfo: Introduce board-id
@ 2024-05-21 18:37 6% ` Elliot Berman
0 siblings, 0 replies; 200+ results
From: Elliot Berman @ 2024-05-21 18:37 UTC (permalink / raw)
To: Rob Herring, Frank Rowand, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Amrit Anand, Peter Griffin, Caleb Connolly, Andy Gross,
Konrad Dybcio, Doug Anderson, Simon Glass, Chen-Yu Tsai,
Julius Werner, Humphreys, Jonathan, Sumit Garg, Jon Hunter,
Michal Simek, boot-architecture, devicetree, linux-kernel,
linux-arm-kernel, linux-arm-msm, Elliot Berman
Device manufacturers frequently ship multiple boards or SKUs under a
single software package. These software packages will ship multiple
devicetree blobs and require some mechanism to pick the correct DTB for
the board the software package was deployed. Introduce a common
definition for adding board identifiers to device trees. board-id
provides a mechanism for bootloaders to select the appropriate DTB which
is vendor/OEM-agnostic.
This series is based off a talk I gave at EOSS NA 2024 [1]. There is
some further discussion about how to do devicetree selection in the
boot-architecture mailing list [2].
[1]: https://sched.co/1aBFy
[2]: https://lists.linaro.org/archives/list/boot-architecture@lists.linaro.org/thread/DZCZSOCRH5BN7YOXEL2OQKSDIY7DCW2M/
Quick summary
-------------
This series introduces a new subnode in the root:
/ {
board-id {
some-hw-id = <value>;
other-hw-id = <val1>, <val2>;
};
};
Firmware provides a mechanism to fetch the values of "some-hw-id" and
"other-hw-id" based on the property name. I'd like to leave exact
mechanism data out of the scope of this proposal to keep this proposal
flexible because it seems architecture specific, although I think we we
should discuss possible approaches. A DTB matches if firmware can
provide a matching value for every one of the properties under
/board-id. In the above example, val1 and val2 are both valid values and
firmware only provides the one that actually describes the board.
It's expected that devicetree's board-id don't describe all the
properties firmware could provide. For instance, a devicetree overlay
may only care about "other-hw-id" and not "some-hw-id". Thus, it need
only mention "other-hw-id" in its board-id node.
Isn't that what the compatible property is for?
-----------------------------------------------
The compatible property can be used for board matching, but requires
bootloaders and/or firmware to maintain a database of possible strings
to match against or implement complex compatible string matching.
Compatible string matching becomes complicated when there are multiple
versions of board: the device tree selector should recognize a DTB that
cares to distinguish between v1/v2 and a DTB that doesn't make the
distinction. An eeprom either needs to store the compatible strings
that could match against the board or the bootloader needs to have
vendor-specific decoding logic for the compatible string. Neither
increasing eeprom storage nor adding vendor-specific decoding logic is
desirable.
How is this better than Qualcomm's qcom,msm-id/qcom,board-id?
-------------------------------------------------------------
The selection process for devicetrees was Qualcomm-specific and not
useful for other devices and bootloaders that were not developed by
Qualcomm because a complex algorithm was used to implement. Board-ids
provide a matching solution that can be implemented by bootloaders
without introducing vendor-specific code. Qualcomm uses three
devicetree properties: msm-id (interchangeably: soc-id), board-id, and
pmic-id. This does not scale well for use casese which use identifiers,
for example, to distinguish between a display panel. For a display
panel, an approach could be to add a new property: display-id, but now
bootloaders need to be updated to also read this property. We want to
avoid requiring to update bootloaders with new hardware identifiers: a
bootloader need only recognize the identifiers it can handle.
Notes about the patches
-----------------------
In my opinion, most of the patches in this series should be submitted to
libfdt and/or dtschema project. I've made them apply on the kernel tree
to be easier for other folks to pick them up and play with them. As the
patches evolve, I can send them to the appropriate projects.
Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
---
Changes in v3:
- Follow new "/board-id {}" approach, which uses key-value pairs
- Add match algorithm in libfdt and some examples to demo how the
selection could work in tools/board-id
Changes in V2:
- Addressed few comments related to board-id, and DDR type.
- Link to V2: https://lore.kernel.org/all/a930a3d6-0846-a709-8fe9-44335fec92ca@quicinc.com/#r
---
Amrit Anand (1):
dt-bindings: arm: qcom: Update Devicetree identifiers
Elliot Berman (8):
libfdt: board-id: Implement board-id scoring
dt-bindings: board: Introduce board-id
fdt-select-board: Add test tool for selecting dtbs based on board-id
dt-bindings: board: Document board-ids for Qualcomm devices
arm64: boot: dts: sm8650: Add board-id
arm64: boot: dts: qcom: Use phandles for thermal_zones
arm64: boot: dts: qcom: sm8550: Split into overlays
tools: board-id: Add test suite
.../devicetree/bindings/board/board-id.yaml | 24 ++++
.../devicetree/bindings/board/qcom,board-id.yaml | 144 ++++++++++++++++++++
arch/arm64/boot/dts/qcom/Makefile | 4 +
arch/arm64/boot/dts/qcom/pm8010.dtsi | 62 ++++-----
arch/arm64/boot/dts/qcom/pm8550.dtsi | 32 ++---
arch/arm64/boot/dts/qcom/pm8550b.dtsi | 36 +++--
arch/arm64/boot/dts/qcom/pm8550ve.dtsi | 38 +++---
arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 128 +++++++++--------
arch/arm64/boot/dts/qcom/pmr735d_a.dtsi | 38 +++---
arch/arm64/boot/dts/qcom/pmr735d_b.dtsi | 38 +++---
.../dts/qcom/{sm8550-mtp.dts => sm8550-mtp.dtso} | 24 +++-
.../dts/qcom/{sm8550-qrd.dts => sm8550-qrd.dtso} | 22 ++-
.../boot/dts/qcom/{sm8550.dtsi => sm8550.dts} | 10 +-
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 6 +
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 +
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
include/dt-bindings/arm/qcom,ids.h | 86 ++++++++++--
scripts/dtc/.gitignore | 1 +
scripts/dtc/Makefile | 3 +-
scripts/dtc/fdt-select-board.c | 126 +++++++++++++++++
scripts/dtc/libfdt/fdt_ro.c | 76 +++++++++++
scripts/dtc/libfdt/libfdt.h | 54 ++++++++
tools/board-id/test.py | 151 +++++++++++++++++++++
23 files changed, 901 insertions(+), 210 deletions(-)
---
base-commit: e8f897f4afef0031fe618a8e94127a0934896aba
change-id: 20240112-board-ids-809ff0281ee5
Best regards,
--
Elliot Berman <quic_eberman@quicinc.com>
^ permalink raw reply [relevance 6%]
* [PATCH RFC v3 6/9] arm64: boot: dts: sm8650: Add board-id
2024-05-21 18:37 6% ` Elliot Berman
@ 2024-05-21 18:38 5% ` Elliot Berman
-1 siblings, 0 replies; 200+ results
From: Elliot Berman @ 2024-05-21 18:38 UTC (permalink / raw)
To: Rob Herring, Frank Rowand, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Amrit Anand, Peter Griffin, Caleb Connolly, Andy Gross,
Konrad Dybcio, Doug Anderson, Simon Glass, Chen-Yu Tsai,
Julius Werner, Humphreys, Jonathan, Sumit Garg, Jon Hunter,
Michal Simek, boot-architecture, devicetree, linux-kernel,
linux-arm-kernel, linux-arm-msm, Elliot Berman
Add board-id to match sm8650 MTPs and QRDs.
Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 6 ++++++
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index be133a3d5cbe..ceaf7cc270af 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8650.dtsi"
#include "pm8010.dtsi"
@@ -28,6 +29,11 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ board-id {
+ qcom,soc = <QCOM_ID_SM8650>;
+ qcom,platform = <QCOM_BOARD_ID_MTP>;
+ };
+
pmic-glink {
compatible = "qcom,sm8650-pmic-glink",
"qcom,sm8550-pmic-glink",
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index b9151c2ddf2e..672ffcd0eaf0 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8650.dtsi"
@@ -26,6 +27,11 @@ aliases {
serial1 = &uart14;
};
+ board-id {
+ qcom,soc = <QCOM_ID_SM8650>;
+ qcom,platform = <QCOM_BOARD_ID_QRD>;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
--
2.34.1
^ permalink raw reply related [relevance 5%]
* [PATCH RFC v3 9/9] tools: board-id: Add test suite
2024-05-21 18:37 6% ` Elliot Berman
@ 2024-05-21 18:38 6% ` Elliot Berman
-1 siblings, 0 replies; 200+ results
From: Elliot Berman @ 2024-05-21 18:38 UTC (permalink / raw)
To: Rob Herring, Frank Rowand, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Amrit Anand, Peter Griffin, Caleb Connolly, Andy Gross,
Konrad Dybcio, Doug Anderson, Simon Glass, Chen-Yu Tsai,
Julius Werner, Humphreys, Jonathan, Sumit Garg, Jon Hunter,
Michal Simek, boot-architecture, devicetree, linux-kernel,
linux-arm-kernel, linux-arm-msm, Elliot Berman
Add a short test suite to demonstrate board-id selection and scoring.
This patch isn't intended to be merged here.
After compiling the kernel (esp. arch/arm64/boot/dts/qcom DTBs), run
tools/board-id/test.py.
The test cases provide a hypothetical firmware-provied board-id and
compares expected output for which DTBs gets matched.
Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
---
tools/board-id/test.py | 151 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 151 insertions(+)
diff --git a/tools/board-id/test.py b/tools/board-id/test.py
new file mode 100644
index 000000000000..687b31ad73d2
--- /dev/null
+++ b/tools/board-id/test.py
@@ -0,0 +1,151 @@
+from collections import namedtuple
+import glob
+import os
+import subprocess
+from tempfile import NamedTemporaryFile
+import unittest
+
+
+LINUX_ROOT = os.path.abspath(os.path.join(__file__, "..", "..", ".."))
+ENV_WITH_DTC = {
+ "PATH": os.path.join(LINUX_ROOT, "scripts", "dtc") + os.pathsep + os.environ["PATH"]
+}
+
+
+TestCase = namedtuple("TestCase", ["score_all", "board_id", "output"])
+
+test_cases = [
+ TestCase(
+ # A board_id that could be provided by firmware
+ board_id="""
+ qcom,soc = <QCOM_ID_SM8650>;
+ qcom,soc-version = <QCOM_ID_SM8650 QCOM_SOC_REVISION(1)>;
+ qcom,platform = <QCOM_BOARD_ID_MTP>;
+ qcom,platform-type = <QCOM_BOARD_ID_MTP 0>;
+ qcom,platform-version = <QCOM_BOARD_ID_MTP 0 0x0100>;
+ qcom,boot-device = <QCOM_BOARD_BOOT_UFS>;
+ """,
+ score_all=False,
+ output="""
+ qcom/sm8650-mtp.dtb
+ """,
+ ),
+ TestCase(
+ # A board_id that could be provided by firmware
+ board_id="""
+ qcom,soc = <QCOM_ID_SM8550>;
+ qcom,soc-version = <QCOM_ID_SM8550 QCOM_SOC_REVISION(1)>;
+ qcom,platform = <QCOM_BOARD_ID_MTP>;
+ qcom,platform-type = <QCOM_BOARD_ID_MTP 0>;
+ qcom,platform-version = <QCOM_BOARD_ID_MTP 0 0x0100>;
+ qcom,boot-device = <QCOM_BOARD_BOOT_UFS>;
+ """,
+ score_all=True,
+ output="""
+ qcom/sm8550.dtb: 1
+ qcom/sm8550-mtp.dtb: 3
+ qcom/sm8550-mtp.dtbo: 2
+ """,
+ ),
+]
+
+
+def compile_board_id(board_id: str):
+ dts = f"""
+ /dts-v1/;
+
+ #include <dt-bindings/arm/qcom,ids.h>
+
+ / {{
+ compatible = "linux,dummy";
+ board-id {{
+ {board_id}
+ }};
+ }};
+ """
+ dts_processed = subprocess.run(
+ [
+ "gcc",
+ "-E",
+ "-nostdinc",
+ f"-I{os.path.join(LINUX_ROOT, 'scripts', 'dtc', 'include-prefixes')}",
+ "-undef",
+ "-D__DTS__",
+ "-x",
+ "assembler-with-cpp",
+ "-o" "-",
+ "-",
+ ],
+ stdout=subprocess.PIPE,
+ input=dts.encode("utf-8"),
+ check=True,
+ )
+ dtc = subprocess.run(
+ ["dtc", "-I", "dts", "-O", "dtb", "-o", "-", "-"],
+ stdout=subprocess.PIPE,
+ input=dts_processed.stdout,
+ env=ENV_WITH_DTC,
+ )
+ return dtc.stdout
+
+
+def select_boards(score_all, fwdtb):
+ with NamedTemporaryFile() as fwdtb_file:
+ fwdtb_file.write(fwdtb)
+ fwdtb_file.flush()
+ root_dir = os.path.join(LINUX_ROOT, "arch", "arm64", "boot", "dts")
+ return subprocess.run(
+ filter(
+ bool,
+ [
+ "fdt-select-board",
+ "-a" if score_all else None,
+ "-r",
+ fwdtb_file.name,
+ *glob.glob(
+ "qcom/*.dtb*",
+ root_dir=root_dir,
+ ),
+ ],
+ ),
+ stdout=subprocess.PIPE,
+ text=True,
+ cwd=root_dir,
+ env=ENV_WITH_DTC,
+ stderr=subprocess.STDOUT,
+ )
+
+
+def fixup_lines(s):
+ return '\n'.join(filter(bool, sorted(_s.strip() for _s in s.split('\n'))))
+
+
+class TestBoardIds(unittest.TestCase):
+ def __init__(self, index: int, args: TestCase) -> None:
+ super().__init__()
+ self.args = args
+ self.index = index
+
+ def runTest(self):
+ fwdtb = compile_board_id(self.args.board_id)
+ output = select_boards(self.args.score_all, fwdtb)
+ if output.stderr:
+ self.assertMultiLineEqual(output.stderr, "")
+ expected = fixup_lines(self.args.output)
+ actual = fixup_lines(output.stdout)
+ self.assertMultiLineEqual(expected, actual)
+
+ def __str__(self):
+ return f"Test case {self.index}"
+
+
+def suite():
+ suite = unittest.TestSuite()
+ for idx, test in enumerate(test_cases):
+ suite.addTest(TestBoardIds(idx + 1, test))
+ return suite
+
+
+if __name__ == "__main__":
+ runner = unittest.TextTestRunner()
+ runner.run(suite())
--
2.34.1
^ permalink raw reply related [relevance 6%]
* [PATCH RFC v3 7/9] arm64: boot: dts: qcom: Use phandles for thermal_zones
@ 2024-05-21 18:38 9% ` Elliot Berman
0 siblings, 0 replies; 200+ results
From: Elliot Berman @ 2024-05-21 18:38 UTC (permalink / raw)
To: Rob Herring, Frank Rowand, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Amrit Anand, Peter Griffin, Caleb Connolly, Andy Gross,
Konrad Dybcio, Doug Anderson, Simon Glass, Chen-Yu Tsai,
Julius Werner, Humphreys, Jonathan, Sumit Garg, Jon Hunter,
Michal Simek, boot-architecture, devicetree, linux-kernel,
linux-arm-kernel, linux-arm-msm, Elliot Berman
In preparation for converting sm8550 to use devicetree overlays, use
phandles for thermal_zones.
Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
---
arch/arm64/boot/dts/qcom/pm8010.dtsi | 62 ++++++++--------
arch/arm64/boot/dts/qcom/pm8550.dtsi | 32 ++++----
arch/arm64/boot/dts/qcom/pm8550b.dtsi | 36 +++++----
arch/arm64/boot/dts/qcom/pm8550ve.dtsi | 38 +++++-----
arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 128 ++++++++++++++++----------------
arch/arm64/boot/dts/qcom/pmr735d_a.dtsi | 38 +++++-----
arch/arm64/boot/dts/qcom/pmr735d_b.dtsi | 38 +++++-----
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
9 files changed, 181 insertions(+), 195 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/pm8010.dtsi b/arch/arm64/boot/dts/qcom/pm8010.dtsi
index 0ea641e12209..a889df2f2f25 100644
--- a/arch/arm64/boot/dts/qcom/pm8010.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8010.dtsi
@@ -6,47 +6,45 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pm8010-m-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
+&thermal_zones {
+ pm8010-m-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
- thermal-sensors = <&pm8010_m_temp_alarm>;
+ thermal-sensors = <&pm8010_m_temp_alarm>;
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
+ };
- pm8010-n-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
+ pm8010-n-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
- thermal-sensors = <&pm8010_n_temp_alarm>;
+ thermal-sensors = <&pm8010_n_temp_alarm>;
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi
index 797a18c249a4..cb5e70b28445 100644
--- a/arch/arm64/boot/dts/qcom/pm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi
@@ -6,26 +6,24 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pm8550-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
+&thermal_zones {
+ pm8550-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
- thermal-sensors = <&pm8550_temp_alarm>;
+ thermal-sensors = <&pm8550_temp_alarm>;
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/pm8550b.dtsi b/arch/arm64/boot/dts/qcom/pm8550b.dtsi
index 72609f31c890..b3cfa030679a 100644
--- a/arch/arm64/boot/dts/qcom/pm8550b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550b.dtsi
@@ -6,26 +6,24 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pm8550b-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
-
- thermal-sensors = <&pm8550b_temp_alarm>;
-
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+&thermal_zones {
+ pm8550b-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8550b_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi
index 4dc1f03ab2c7..8ef57a51b5cd 100644
--- a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi
@@ -6,26 +6,24 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pm8550ve-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
-
- thermal-sensors = <&pm8550ve_temp_alarm>;
-
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
-
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+&thermal_zones {
+ pm8550ve-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8550ve_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi
index 97b1c18aa7d8..258526abcc21 100644
--- a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi
@@ -6,89 +6,87 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pm8550vs-c-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
-
- thermal-sensors = <&pm8550vs_c_temp_alarm>;
-
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
-
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+&thermal_zones {
+ pm8550vs-c-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8550vs_c_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
+ };
- pm8550vs-d-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
+ pm8550vs-d-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
- thermal-sensors = <&pm8550vs_d_temp_alarm>;
+ thermal-sensors = <&pm8550vs_d_temp_alarm>;
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
+ };
- pm8550vs-e-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
+ pm8550vs-e-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
- thermal-sensors = <&pm8550vs_e_temp_alarm>;
+ thermal-sensors = <&pm8550vs_e_temp_alarm>;
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
+ };
- pm8550vs-g-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
+ pm8550vs-g-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
- thermal-sensors = <&pm8550vs_g_temp_alarm>;
+ thermal-sensors = <&pm8550vs_g_temp_alarm>;
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi b/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi
index 37daaefe3431..251a16424d84 100644
--- a/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi
@@ -6,26 +6,24 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pmr735d-k-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
-
- thermal-sensors = <&pmr735d_k_temp_alarm>;
-
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
-
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+&thermal_zones {
+ pmr735d-k-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pmr735d_k_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi b/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi
index 3b470f6ac46f..dbcfeb53d8ec 100644
--- a/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi
@@ -6,26 +6,24 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-/ {
- thermal-zones {
- pmr735d-l-thermal {
- polling-delay-passive = <100>;
- polling-delay = <0>;
-
- thermal-sensors = <&pmr735d_l_temp_alarm>;
-
- trips {
- trip0 {
- temperature = <95000>;
- hysteresis = <0>;
- type = "passive";
- };
-
- trip1 {
- temperature = <115000>;
- hysteresis = <0>;
- type = "hot";
- };
+&thermal_zones {
+ pmr735d-l-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pmr735d_l_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
};
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index ee1ba5a8c8fc..c68e08747b6f 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -4452,7 +4452,7 @@ compute-cb@8 {
};
};
- thermal-zones {
+ thermal_zones: thermal-zones {
aoss0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 2df77123a8c7..32198bf3cf7c 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5030,7 +5030,7 @@ compute-cb@8 {
};
};
- thermal-zones {
+ thermal_zones: thermal-zones {
aoss0-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
--
2.34.1
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 9%]
* [PATCH RFC v3 8/9] arm64: boot: dts: qcom: sm8550: Split into overlays
@ 2024-05-21 18:38 42% ` Elliot Berman
0 siblings, 0 replies; 200+ results
From: Elliot Berman @ 2024-05-21 18:38 UTC (permalink / raw)
To: Rob Herring, Frank Rowand, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Amrit Anand, Peter Griffin, Caleb Connolly, Andy Gross,
Konrad Dybcio, Doug Anderson, Simon Glass, Chen-Yu Tsai,
Julius Werner, Humphreys, Jonathan, Sumit Garg, Jon Hunter,
Michal Simek, boot-architecture, devicetree, linux-kernel,
linux-arm-kernel, linux-arm-msm, Elliot Berman
Generic sm8550 devicetree is split into a dtsi. Move it into its own DTB
and preserve the boards as overlays.
When not using overlays, 264 KB needed to store the sm8550-mtp.dtb and
sm8550-qrd.dtb. When using overlays, 188 KB is needed to store
sm8550.dtb, sm8550-mtp.dtbo, and sm8550-qrd.dtbo; where the overlays are
~36 KB.
Also add the board-ids for these DTBs.
This change is not intended to be merged, it breaks aliases and I doubt
it boots correct. The intent here is to show how board-id could be used
with a DTB and DTBO.
Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
---
arch/arm64/boot/dts/qcom/Makefile | 4 ++++
.../dts/qcom/{sm8550-mtp.dts => sm8550-mtp.dtso} | 24 ++++++++++++++++++++--
.../dts/qcom/{sm8550-qrd.dts => sm8550-qrd.dtso} | 22 +++++++++++++++++---
.../boot/dts/qcom/{sm8550.dtsi => sm8550.dts} | 8 ++++++++
4 files changed, 53 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 39889d5f8e12..7f137f274d8c 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -233,6 +233,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
+
+sm8550-mtp-dtbs := sm8550.dtb sm8550-mtp.dtbo
+sm8550-qrd-dtbs := sm8550.dtb sm8550-qrd.dtbo
+
dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dtso
similarity index 98%
rename from arch/arm64/boot/dts/qcom/sm8550-mtp.dts
rename to arch/arm64/boot/dts/qcom/sm8550-mtp.dtso
index c1135ad5fa69..0ee4614719ca 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dtso
@@ -4,9 +4,12 @@
*/
/dts-v1/;
+/plugin/;
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include "sm8550.dtsi"
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "pm8010.dtsi"
#include "pm8550.dtsi"
#include "pm8550b.dtsi"
@@ -17,13 +20,30 @@
#include "pmr735d_a.dtsi"
#include "pmr735d_b.dtsi"
+#define BOARD_ID qcom,soc = <QCOM_ID_SM8550>; \
+ qcom,platform-type = <QCOM_BOARD_ID_MTP 0>
+
/ {
+ board-id {
+ BOARD_ID;
+ };
+};
+
+&{/} {
model = "Qualcomm Technologies, Inc. SM8550 MTP";
compatible = "qcom,sm8550-mtp", "qcom,sm8550";
chassis-type = "handset";
+ /**
+ * Redefine the overlay in the DTBO so the sm8550-mtp.dtb that Kbuild
+ * generates has accurate board-id.
+ */
+ board-id {
+ BOARD_ID;
+ };
+
aliases {
- serial0 = &uart7;
+ // serial0 = &uart7;
};
wcd938x: audio-codec {
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dtso
similarity index 98%
rename from arch/arm64/boot/dts/qcom/sm8550-qrd.dts
rename to arch/arm64/boot/dts/qcom/sm8550-qrd.dtso
index d401d63e5c4d..f756c50a80b9 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dtso
@@ -4,10 +4,14 @@
*/
/dts-v1/;
+/plugin/;
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include "sm8550.dtsi"
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "pm8010.dtsi"
#include "pm8550.dtsi"
#include "pm8550b.dtsi"
@@ -19,13 +23,25 @@
#include "pmr735d_b.dtsi"
/ {
+ board-id {
+ qcom,soc = <QCOM_ID_SM8550>;
+ qcom,platform = <QCOM_BOARD_ID_QRD>;
+ };
+};
+
+&{/} {
model = "Qualcomm Technologies, Inc. SM8550 QRD";
compatible = "qcom,sm8550-qrd", "qcom,sm8550";
chassis-type = "handset";
+ board-id {
+ qcom,soc = <QCOM_ID_SM8550>;
+ qcom,platform = <QCOM_BOARD_ID_QRD>;
+ };
+
aliases {
- serial0 = &uart7;
- serial1 = &uart14;
+ // serial0 = &uart7;
+ // serial1 = &uart14;
};
wcd938x: audio-codec {
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dts
similarity index 99%
rename from arch/arm64/boot/dts/qcom/sm8550.dtsi
rename to arch/arm64/boot/dts/qcom/sm8550.dts
index c68e08747b6f..3546ea4b96f1 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dts
@@ -3,6 +3,9 @@
* Copyright (c) 2022, Linaro Limited
*/
+/dts-v1/;
+
+#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
#include <dt-bindings/clock/qcom,sm8550-camcc.h>
@@ -32,6 +35,11 @@ / {
chosen { };
+ board_id: board-id {
+ qcom,soc-version = <QCOM_ID_SM8550 QCOM_SOC_REVISION(1)>,
+ <QCOM_ID_SM8550 QCOM_SOC_REVISION(2)>;
+ };
+
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 42%]
* [PATCH RFC v3 0/9] dt-bindings: hwinfo: Introduce board-id
@ 2024-05-21 18:37 6% ` Elliot Berman
0 siblings, 0 replies; 200+ results
From: Elliot Berman @ 2024-05-21 18:37 UTC (permalink / raw)
To: Rob Herring, Frank Rowand, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Amrit Anand, Peter Griffin, Caleb Connolly, Andy Gross,
Konrad Dybcio, Doug Anderson, Simon Glass, Chen-Yu Tsai,
Julius Werner, Humphreys, Jonathan, Sumit Garg, Jon Hunter,
Michal Simek, boot-architecture, devicetree, linux-kernel,
linux-arm-kernel, linux-arm-msm, Elliot Berman
Device manufacturers frequently ship multiple boards or SKUs under a
single software package. These software packages will ship multiple
devicetree blobs and require some mechanism to pick the correct DTB for
the board the software package was deployed. Introduce a common
definition for adding board identifiers to device trees. board-id
provides a mechanism for bootloaders to select the appropriate DTB which
is vendor/OEM-agnostic.
This series is based off a talk I gave at EOSS NA 2024 [1]. There is
some further discussion about how to do devicetree selection in the
boot-architecture mailing list [2].
[1]: https://sched.co/1aBFy
[2]: https://lists.linaro.org/archives/list/boot-architecture@lists.linaro.org/thread/DZCZSOCRH5BN7YOXEL2OQKSDIY7DCW2M/
Quick summary
-------------
This series introduces a new subnode in the root:
/ {
board-id {
some-hw-id = <value>;
other-hw-id = <val1>, <val2>;
};
};
Firmware provides a mechanism to fetch the values of "some-hw-id" and
"other-hw-id" based on the property name. I'd like to leave exact
mechanism data out of the scope of this proposal to keep this proposal
flexible because it seems architecture specific, although I think we we
should discuss possible approaches. A DTB matches if firmware can
provide a matching value for every one of the properties under
/board-id. In the above example, val1 and val2 are both valid values and
firmware only provides the one that actually describes the board.
It's expected that devicetree's board-id don't describe all the
properties firmware could provide. For instance, a devicetree overlay
may only care about "other-hw-id" and not "some-hw-id". Thus, it need
only mention "other-hw-id" in its board-id node.
Isn't that what the compatible property is for?
-----------------------------------------------
The compatible property can be used for board matching, but requires
bootloaders and/or firmware to maintain a database of possible strings
to match against or implement complex compatible string matching.
Compatible string matching becomes complicated when there are multiple
versions of board: the device tree selector should recognize a DTB that
cares to distinguish between v1/v2 and a DTB that doesn't make the
distinction. An eeprom either needs to store the compatible strings
that could match against the board or the bootloader needs to have
vendor-specific decoding logic for the compatible string. Neither
increasing eeprom storage nor adding vendor-specific decoding logic is
desirable.
How is this better than Qualcomm's qcom,msm-id/qcom,board-id?
-------------------------------------------------------------
The selection process for devicetrees was Qualcomm-specific and not
useful for other devices and bootloaders that were not developed by
Qualcomm because a complex algorithm was used to implement. Board-ids
provide a matching solution that can be implemented by bootloaders
without introducing vendor-specific code. Qualcomm uses three
devicetree properties: msm-id (interchangeably: soc-id), board-id, and
pmic-id. This does not scale well for use casese which use identifiers,
for example, to distinguish between a display panel. For a display
panel, an approach could be to add a new property: display-id, but now
bootloaders need to be updated to also read this property. We want to
avoid requiring to update bootloaders with new hardware identifiers: a
bootloader need only recognize the identifiers it can handle.
Notes about the patches
-----------------------
In my opinion, most of the patches in this series should be submitted to
libfdt and/or dtschema project. I've made them apply on the kernel tree
to be easier for other folks to pick them up and play with them. As the
patches evolve, I can send them to the appropriate projects.
Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
---
Changes in v3:
- Follow new "/board-id {}" approach, which uses key-value pairs
- Add match algorithm in libfdt and some examples to demo how the
selection could work in tools/board-id
Changes in V2:
- Addressed few comments related to board-id, and DDR type.
- Link to V2: https://lore.kernel.org/all/a930a3d6-0846-a709-8fe9-44335fec92ca@quicinc.com/#r
---
Amrit Anand (1):
dt-bindings: arm: qcom: Update Devicetree identifiers
Elliot Berman (8):
libfdt: board-id: Implement board-id scoring
dt-bindings: board: Introduce board-id
fdt-select-board: Add test tool for selecting dtbs based on board-id
dt-bindings: board: Document board-ids for Qualcomm devices
arm64: boot: dts: sm8650: Add board-id
arm64: boot: dts: qcom: Use phandles for thermal_zones
arm64: boot: dts: qcom: sm8550: Split into overlays
tools: board-id: Add test suite
.../devicetree/bindings/board/board-id.yaml | 24 ++++
.../devicetree/bindings/board/qcom,board-id.yaml | 144 ++++++++++++++++++++
arch/arm64/boot/dts/qcom/Makefile | 4 +
arch/arm64/boot/dts/qcom/pm8010.dtsi | 62 ++++-----
arch/arm64/boot/dts/qcom/pm8550.dtsi | 32 ++---
arch/arm64/boot/dts/qcom/pm8550b.dtsi | 36 +++--
arch/arm64/boot/dts/qcom/pm8550ve.dtsi | 38 +++---
arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 128 +++++++++--------
arch/arm64/boot/dts/qcom/pmr735d_a.dtsi | 38 +++---
arch/arm64/boot/dts/qcom/pmr735d_b.dtsi | 38 +++---
.../dts/qcom/{sm8550-mtp.dts => sm8550-mtp.dtso} | 24 +++-
.../dts/qcom/{sm8550-qrd.dts => sm8550-qrd.dtso} | 22 ++-
.../boot/dts/qcom/{sm8550.dtsi => sm8550.dts} | 10 +-
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 6 +
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 +
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
include/dt-bindings/arm/qcom,ids.h | 86 ++++++++++--
scripts/dtc/.gitignore | 1 +
scripts/dtc/Makefile | 3 +-
scripts/dtc/fdt-select-board.c | 126 +++++++++++++++++
scripts/dtc/libfdt/fdt_ro.c | 76 +++++++++++
scripts/dtc/libfdt/libfdt.h | 54 ++++++++
tools/board-id/test.py | 151 +++++++++++++++++++++
23 files changed, 901 insertions(+), 210 deletions(-)
---
base-commit: e8f897f4afef0031fe618a8e94127a0934896aba
change-id: 20240112-board-ids-809ff0281ee5
Best regards,
--
Elliot Berman <quic_eberman@quicinc.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 6%]
* [PATCH RFC v3 6/9] arm64: boot: dts: sm8650: Add board-id
@ 2024-05-21 18:38 5% ` Elliot Berman
0 siblings, 0 replies; 200+ results
From: Elliot Berman @ 2024-05-21 18:38 UTC (permalink / raw)
To: Rob Herring, Frank Rowand, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Amrit Anand, Peter Griffin, Caleb Connolly, Andy Gross,
Konrad Dybcio, Doug Anderson, Simon Glass, Chen-Yu Tsai,
Julius Werner, Humphreys, Jonathan, Sumit Garg, Jon Hunter,
Michal Simek, boot-architecture, devicetree, linux-kernel,
linux-arm-kernel, linux-arm-msm, Elliot Berman
Add board-id to match sm8650 MTPs and QRDs.
Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 6 ++++++
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index be133a3d5cbe..ceaf7cc270af 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8650.dtsi"
#include "pm8010.dtsi"
@@ -28,6 +29,11 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ board-id {
+ qcom,soc = <QCOM_ID_SM8650>;
+ qcom,platform = <QCOM_BOARD_ID_MTP>;
+ };
+
pmic-glink {
compatible = "qcom,sm8650-pmic-glink",
"qcom,sm8550-pmic-glink",
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index b9151c2ddf2e..672ffcd0eaf0 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8650.dtsi"
@@ -26,6 +27,11 @@ aliases {
serial1 = &uart14;
};
+ board-id {
+ qcom,soc = <QCOM_ID_SM8650>;
+ qcom,platform = <QCOM_BOARD_ID_QRD>;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
--
2.34.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* [PATCH RFC v3 9/9] tools: board-id: Add test suite
@ 2024-05-21 18:38 6% ` Elliot Berman
0 siblings, 0 replies; 200+ results
From: Elliot Berman @ 2024-05-21 18:38 UTC (permalink / raw)
To: Rob Herring, Frank Rowand, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: Amrit Anand, Peter Griffin, Caleb Connolly, Andy Gross,
Konrad Dybcio, Doug Anderson, Simon Glass, Chen-Yu Tsai,
Julius Werner, Humphreys, Jonathan, Sumit Garg, Jon Hunter,
Michal Simek, boot-architecture, devicetree, linux-kernel,
linux-arm-kernel, linux-arm-msm, Elliot Berman
Add a short test suite to demonstrate board-id selection and scoring.
This patch isn't intended to be merged here.
After compiling the kernel (esp. arch/arm64/boot/dts/qcom DTBs), run
tools/board-id/test.py.
The test cases provide a hypothetical firmware-provied board-id and
compares expected output for which DTBs gets matched.
Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
---
tools/board-id/test.py | 151 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 151 insertions(+)
diff --git a/tools/board-id/test.py b/tools/board-id/test.py
new file mode 100644
index 000000000000..687b31ad73d2
--- /dev/null
+++ b/tools/board-id/test.py
@@ -0,0 +1,151 @@
+from collections import namedtuple
+import glob
+import os
+import subprocess
+from tempfile import NamedTemporaryFile
+import unittest
+
+
+LINUX_ROOT = os.path.abspath(os.path.join(__file__, "..", "..", ".."))
+ENV_WITH_DTC = {
+ "PATH": os.path.join(LINUX_ROOT, "scripts", "dtc") + os.pathsep + os.environ["PATH"]
+}
+
+
+TestCase = namedtuple("TestCase", ["score_all", "board_id", "output"])
+
+test_cases = [
+ TestCase(
+ # A board_id that could be provided by firmware
+ board_id="""
+ qcom,soc = <QCOM_ID_SM8650>;
+ qcom,soc-version = <QCOM_ID_SM8650 QCOM_SOC_REVISION(1)>;
+ qcom,platform = <QCOM_BOARD_ID_MTP>;
+ qcom,platform-type = <QCOM_BOARD_ID_MTP 0>;
+ qcom,platform-version = <QCOM_BOARD_ID_MTP 0 0x0100>;
+ qcom,boot-device = <QCOM_BOARD_BOOT_UFS>;
+ """,
+ score_all=False,
+ output="""
+ qcom/sm8650-mtp.dtb
+ """,
+ ),
+ TestCase(
+ # A board_id that could be provided by firmware
+ board_id="""
+ qcom,soc = <QCOM_ID_SM8550>;
+ qcom,soc-version = <QCOM_ID_SM8550 QCOM_SOC_REVISION(1)>;
+ qcom,platform = <QCOM_BOARD_ID_MTP>;
+ qcom,platform-type = <QCOM_BOARD_ID_MTP 0>;
+ qcom,platform-version = <QCOM_BOARD_ID_MTP 0 0x0100>;
+ qcom,boot-device = <QCOM_BOARD_BOOT_UFS>;
+ """,
+ score_all=True,
+ output="""
+ qcom/sm8550.dtb: 1
+ qcom/sm8550-mtp.dtb: 3
+ qcom/sm8550-mtp.dtbo: 2
+ """,
+ ),
+]
+
+
+def compile_board_id(board_id: str):
+ dts = f"""
+ /dts-v1/;
+
+ #include <dt-bindings/arm/qcom,ids.h>
+
+ / {{
+ compatible = "linux,dummy";
+ board-id {{
+ {board_id}
+ }};
+ }};
+ """
+ dts_processed = subprocess.run(
+ [
+ "gcc",
+ "-E",
+ "-nostdinc",
+ f"-I{os.path.join(LINUX_ROOT, 'scripts', 'dtc', 'include-prefixes')}",
+ "-undef",
+ "-D__DTS__",
+ "-x",
+ "assembler-with-cpp",
+ "-o" "-",
+ "-",
+ ],
+ stdout=subprocess.PIPE,
+ input=dts.encode("utf-8"),
+ check=True,
+ )
+ dtc = subprocess.run(
+ ["dtc", "-I", "dts", "-O", "dtb", "-o", "-", "-"],
+ stdout=subprocess.PIPE,
+ input=dts_processed.stdout,
+ env=ENV_WITH_DTC,
+ )
+ return dtc.stdout
+
+
+def select_boards(score_all, fwdtb):
+ with NamedTemporaryFile() as fwdtb_file:
+ fwdtb_file.write(fwdtb)
+ fwdtb_file.flush()
+ root_dir = os.path.join(LINUX_ROOT, "arch", "arm64", "boot", "dts")
+ return subprocess.run(
+ filter(
+ bool,
+ [
+ "fdt-select-board",
+ "-a" if score_all else None,
+ "-r",
+ fwdtb_file.name,
+ *glob.glob(
+ "qcom/*.dtb*",
+ root_dir=root_dir,
+ ),
+ ],
+ ),
+ stdout=subprocess.PIPE,
+ text=True,
+ cwd=root_dir,
+ env=ENV_WITH_DTC,
+ stderr=subprocess.STDOUT,
+ )
+
+
+def fixup_lines(s):
+ return '\n'.join(filter(bool, sorted(_s.strip() for _s in s.split('\n'))))
+
+
+class TestBoardIds(unittest.TestCase):
+ def __init__(self, index: int, args: TestCase) -> None:
+ super().__init__()
+ self.args = args
+ self.index = index
+
+ def runTest(self):
+ fwdtb = compile_board_id(self.args.board_id)
+ output = select_boards(self.args.score_all, fwdtb)
+ if output.stderr:
+ self.assertMultiLineEqual(output.stderr, "")
+ expected = fixup_lines(self.args.output)
+ actual = fixup_lines(output.stdout)
+ self.assertMultiLineEqual(expected, actual)
+
+ def __str__(self):
+ return f"Test case {self.index}"
+
+
+def suite():
+ suite = unittest.TestSuite()
+ for idx, test in enumerate(test_cases):
+ suite.addTest(TestBoardIds(idx + 1, test))
+ return suite
+
+
+if __name__ == "__main__":
+ runner = unittest.TextTestRunner()
+ runner.run(suite())
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 6%]
* Re: [PATCH 01/12] soc: qcom: add firmware name helper
2024-05-21 9:52 0% ` neil.armstrong
@ 2024-05-21 10:01 0% ` Dmitry Baryshkov
0 siblings, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-05-21 10:01 UTC (permalink / raw)
To: neil.armstrong
Cc: Bjorn Andersson, Konrad Dybcio, Loic Poulain, Kalle Valo,
Mathieu Poirier, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-kernel, linux-arm-msm, wcn36xx, linux-wireless,
linux-remoteproc, devicetree, Arnd Bergmann
On Tue, 21 May 2024 at 12:52, <neil.armstrong@linaro.org> wrote:
>
> On 21/05/2024 11:45, Dmitry Baryshkov wrote:
> > Qualcomm platforms have different sets of the firmware files, which
> > differ from platform to platform (and from board to board, due to the
> > embedded signatures). Rather than listing all the firmware files,
> > including full paths, in the DT, provide a way to determine firmware
> > path based on the root DT node compatible.
>
> Ok this looks quite over-engineered but necessary to handle the legacy,
> but I really think we should add a way to look for a board-specific path
> first and fallback to those SoC specific paths.
Again, CONFIG_FW_LOADER_USER_HELPER => delays.
>
> Neil
>
> >
> > Suggested-by: Arnd Bergmann <arnd@arndb.de>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/soc/qcom/Kconfig | 5 +++
> > drivers/soc/qcom/Makefile | 1 +
> > drivers/soc/qcom/qcom_fw_helper.c | 86 ++++++++++++++++++++++++++++++++++++++
> > include/linux/soc/qcom/fw_helper.h | 10 +++++
> > 4 files changed, 102 insertions(+)
> >
> > diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> > index 5af33b0e3470..b663774d65f8 100644
> > --- a/drivers/soc/qcom/Kconfig
> > +++ b/drivers/soc/qcom/Kconfig
> > @@ -62,6 +62,11 @@ config QCOM_MDT_LOADER
> > tristate
> > select QCOM_SCM
> >
> > +config QCOM_FW_HELPER
> > + tristate "NONE FW HELPER"
> > + help
> > + Helpers to return platform-specific location for the firmware files.
> > +
> > config QCOM_OCMEM
> > tristate "Qualcomm On Chip Memory (OCMEM) driver"
> > depends on ARCH_QCOM
> > diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> > index ca0bece0dfff..e612bee5b955 100644
> > --- a/drivers/soc/qcom/Makefile
> > +++ b/drivers/soc/qcom/Makefile
> > @@ -6,6 +6,7 @@ obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
> > obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o
> > obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
> > obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
> > +obj-$(CONFIG_QCOM_FW_HELPER) += qcom_fw_helper.o
> > obj-$(CONFIG_QCOM_OCMEM) += ocmem.o
> > obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o
> > obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink.o
> > diff --git a/drivers/soc/qcom/qcom_fw_helper.c b/drivers/soc/qcom/qcom_fw_helper.c
> > new file mode 100644
> > index 000000000000..13123c2514b8
> > --- /dev/null
> > +++ b/drivers/soc/qcom/qcom_fw_helper.c
> > @@ -0,0 +1,86 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Qualcomm Firmware loading data
> > + *
> > + * Copyright (C) 2024 Linaro Ltd
> > + */
> > +
> > +#include <linux/cleanup.h>
> > +#include <linux/device.h>
> > +#include <linux/mutex.h>
> > +#include <linux/of.h>
> > +#include <linux/soc/qcom/fw_helper.h>
> > +
> > +static DEFINE_MUTEX(qcom_fw_mutex);
> > +static const char *fw_path;
> > +
> > +static const struct of_device_id qcom_fw_paths[] = {
> > + /* device-specific entries */
> > + { .compatible = "thundercomm,db845c", .data = "qcom/sdm845/Thundercomm/db845c", },
> > + { .compatible = "qcom,qrb5165-rb5", .data = "qcom/sm8250/Thundercomm/RB5", },
> > + /* SoC default entries */
> > + { .compatible = "qcom,apq8016", .data = "qcom/apq8016", },
> > + { .compatible = "qcom,apq8096", .data = "qcom/apq8096", },
> > + { .compatible = "qcom,sdm845", .data = "qcom/sdm845", },
> > + { .compatible = "qcom,sm8250", .data = "qcom/sm8250", },
> > + { .compatible = "qcom,sm8350", .data = "qcom/sm8350", },
> > + { .compatible = "qcom,sm8450", .data = "qcom/sm8450", },
> > + { .compatible = "qcom,sm8550", .data = "qcom/sm8550", },
> > + { .compatible = "qcom,sm8650", .data = "qcom/sm8650", },
> > + {},
> > +};
> > +
> > +static int qcom_fw_ensure_init(void)
> > +{
> > + const struct of_device_id *match;
> > + struct device_node *root;
> > +
> > + if (fw_path)
> > + return 0;
> > +
> > + root = of_find_node_by_path("/");
> > + if (!root)
> > + return -ENODEV;
> > +
> > + match = of_match_node(qcom_fw_paths, root);
> > + of_node_put(root);
> > + if (!match || !match->data) {
> > + pr_notice("Platform not supported by qcom_fw_helper\n");
> > + return -ENODEV;
> > + }
> > +
> > + fw_path = match->data;
> > +
> > + return 0;
> > +}
> > +
> > +const char *qcom_get_board_fw(const char *firmware)
> > +{
> > + if (strchr(firmware, '/'))
> > + return kstrdup(firmware, GFP_KERNEL);
> > +
> > + scoped_guard(mutex, &qcom_fw_mutex) {
> > + if (!qcom_fw_ensure_init())
> > + return kasprintf(GFP_KERNEL, "%s/%s", fw_path, firmware);
> > + }
> > +
> > + return kstrdup(firmware, GFP_KERNEL);
> > +}
> > +EXPORT_SYMBOL_GPL(qcom_get_board_fw);
> > +
> > +const char *devm_qcom_get_board_fw(struct device *dev, const char *firmware)
> > +{
> > + if (strchr(firmware, '/'))
> > + return devm_kstrdup(dev, firmware, GFP_KERNEL);
> > +
> > + scoped_guard(mutex, &qcom_fw_mutex) {
> > + if (!qcom_fw_ensure_init())
> > + return devm_kasprintf(dev, GFP_KERNEL, "%s/%s", fw_path, firmware);
> > + }
> > +
> > + return devm_kstrdup(dev, firmware, GFP_KERNEL);
> > +}
> > +EXPORT_SYMBOL_GPL(devm_qcom_get_board_fw);
> > +
> > +MODULE_DESCRIPTION("Firmware helpers for Qualcomm devices");
> > +MODULE_LICENSE("GPL");
> > diff --git a/include/linux/soc/qcom/fw_helper.h b/include/linux/soc/qcom/fw_helper.h
> > new file mode 100644
> > index 000000000000..755645386bba
> > --- /dev/null
> > +++ b/include/linux/soc/qcom/fw_helper.h
> > @@ -0,0 +1,10 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +#ifndef __QCOM_FW_HELPER_H__
> > +#define __QCOM_FW_HELPER_H__
> > +
> > +struct device;
> > +
> > +const char *qcom_get_board_fw(const char *firmware);
> > +const char *devm_qcom_get_board_fw(struct device *dev, const char *firmware);
> > +
> > +#endif
> >
>
--
With best wishes
Dmitry
^ permalink raw reply [relevance 0%]
* Re: [PATCH 01/12] soc: qcom: add firmware name helper
2024-05-21 9:45 6% ` [PATCH 01/12] soc: qcom: add firmware name helper Dmitry Baryshkov
@ 2024-05-21 9:52 0% ` neil.armstrong
2024-05-21 10:01 0% ` Dmitry Baryshkov
0 siblings, 1 reply; 200+ results
From: neil.armstrong @ 2024-05-21 9:52 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Konrad Dybcio, Loic Poulain,
Kalle Valo, Mathieu Poirier, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-kernel, linux-arm-msm, wcn36xx, linux-wireless,
linux-remoteproc, devicetree, Arnd Bergmann
On 21/05/2024 11:45, Dmitry Baryshkov wrote:
> Qualcomm platforms have different sets of the firmware files, which
> differ from platform to platform (and from board to board, due to the
> embedded signatures). Rather than listing all the firmware files,
> including full paths, in the DT, provide a way to determine firmware
> path based on the root DT node compatible.
Ok this looks quite over-engineered but necessary to handle the legacy,
but I really think we should add a way to look for a board-specific path
first and fallback to those SoC specific paths.
Neil
>
> Suggested-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/soc/qcom/Kconfig | 5 +++
> drivers/soc/qcom/Makefile | 1 +
> drivers/soc/qcom/qcom_fw_helper.c | 86 ++++++++++++++++++++++++++++++++++++++
> include/linux/soc/qcom/fw_helper.h | 10 +++++
> 4 files changed, 102 insertions(+)
>
> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> index 5af33b0e3470..b663774d65f8 100644
> --- a/drivers/soc/qcom/Kconfig
> +++ b/drivers/soc/qcom/Kconfig
> @@ -62,6 +62,11 @@ config QCOM_MDT_LOADER
> tristate
> select QCOM_SCM
>
> +config QCOM_FW_HELPER
> + tristate "NONE FW HELPER"
> + help
> + Helpers to return platform-specific location for the firmware files.
> +
> config QCOM_OCMEM
> tristate "Qualcomm On Chip Memory (OCMEM) driver"
> depends on ARCH_QCOM
> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> index ca0bece0dfff..e612bee5b955 100644
> --- a/drivers/soc/qcom/Makefile
> +++ b/drivers/soc/qcom/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
> obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o
> obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
> obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
> +obj-$(CONFIG_QCOM_FW_HELPER) += qcom_fw_helper.o
> obj-$(CONFIG_QCOM_OCMEM) += ocmem.o
> obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o
> obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink.o
> diff --git a/drivers/soc/qcom/qcom_fw_helper.c b/drivers/soc/qcom/qcom_fw_helper.c
> new file mode 100644
> index 000000000000..13123c2514b8
> --- /dev/null
> +++ b/drivers/soc/qcom/qcom_fw_helper.c
> @@ -0,0 +1,86 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Qualcomm Firmware loading data
> + *
> + * Copyright (C) 2024 Linaro Ltd
> + */
> +
> +#include <linux/cleanup.h>
> +#include <linux/device.h>
> +#include <linux/mutex.h>
> +#include <linux/of.h>
> +#include <linux/soc/qcom/fw_helper.h>
> +
> +static DEFINE_MUTEX(qcom_fw_mutex);
> +static const char *fw_path;
> +
> +static const struct of_device_id qcom_fw_paths[] = {
> + /* device-specific entries */
> + { .compatible = "thundercomm,db845c", .data = "qcom/sdm845/Thundercomm/db845c", },
> + { .compatible = "qcom,qrb5165-rb5", .data = "qcom/sm8250/Thundercomm/RB5", },
> + /* SoC default entries */
> + { .compatible = "qcom,apq8016", .data = "qcom/apq8016", },
> + { .compatible = "qcom,apq8096", .data = "qcom/apq8096", },
> + { .compatible = "qcom,sdm845", .data = "qcom/sdm845", },
> + { .compatible = "qcom,sm8250", .data = "qcom/sm8250", },
> + { .compatible = "qcom,sm8350", .data = "qcom/sm8350", },
> + { .compatible = "qcom,sm8450", .data = "qcom/sm8450", },
> + { .compatible = "qcom,sm8550", .data = "qcom/sm8550", },
> + { .compatible = "qcom,sm8650", .data = "qcom/sm8650", },
> + {},
> +};
> +
> +static int qcom_fw_ensure_init(void)
> +{
> + const struct of_device_id *match;
> + struct device_node *root;
> +
> + if (fw_path)
> + return 0;
> +
> + root = of_find_node_by_path("/");
> + if (!root)
> + return -ENODEV;
> +
> + match = of_match_node(qcom_fw_paths, root);
> + of_node_put(root);
> + if (!match || !match->data) {
> + pr_notice("Platform not supported by qcom_fw_helper\n");
> + return -ENODEV;
> + }
> +
> + fw_path = match->data;
> +
> + return 0;
> +}
> +
> +const char *qcom_get_board_fw(const char *firmware)
> +{
> + if (strchr(firmware, '/'))
> + return kstrdup(firmware, GFP_KERNEL);
> +
> + scoped_guard(mutex, &qcom_fw_mutex) {
> + if (!qcom_fw_ensure_init())
> + return kasprintf(GFP_KERNEL, "%s/%s", fw_path, firmware);
> + }
> +
> + return kstrdup(firmware, GFP_KERNEL);
> +}
> +EXPORT_SYMBOL_GPL(qcom_get_board_fw);
> +
> +const char *devm_qcom_get_board_fw(struct device *dev, const char *firmware)
> +{
> + if (strchr(firmware, '/'))
> + return devm_kstrdup(dev, firmware, GFP_KERNEL);
> +
> + scoped_guard(mutex, &qcom_fw_mutex) {
> + if (!qcom_fw_ensure_init())
> + return devm_kasprintf(dev, GFP_KERNEL, "%s/%s", fw_path, firmware);
> + }
> +
> + return devm_kstrdup(dev, firmware, GFP_KERNEL);
> +}
> +EXPORT_SYMBOL_GPL(devm_qcom_get_board_fw);
> +
> +MODULE_DESCRIPTION("Firmware helpers for Qualcomm devices");
> +MODULE_LICENSE("GPL");
> diff --git a/include/linux/soc/qcom/fw_helper.h b/include/linux/soc/qcom/fw_helper.h
> new file mode 100644
> index 000000000000..755645386bba
> --- /dev/null
> +++ b/include/linux/soc/qcom/fw_helper.h
> @@ -0,0 +1,10 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __QCOM_FW_HELPER_H__
> +#define __QCOM_FW_HELPER_H__
> +
> +struct device;
> +
> +const char *qcom_get_board_fw(const char *firmware);
> +const char *devm_qcom_get_board_fw(struct device *dev, const char *firmware);
> +
> +#endif
>
^ permalink raw reply [relevance 0%]
* [PATCH 01/12] soc: qcom: add firmware name helper
@ 2024-05-21 9:45 6% ` Dmitry Baryshkov
2024-05-21 9:52 0% ` neil.armstrong
0 siblings, 1 reply; 200+ results
From: Dmitry Baryshkov @ 2024-05-21 9:45 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Loic Poulain, Kalle Valo,
Mathieu Poirier, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel, linux-arm-msm, wcn36xx, linux-wireless,
linux-remoteproc, devicetree, Arnd Bergmann, Dmitry Baryshkov
Qualcomm platforms have different sets of the firmware files, which
differ from platform to platform (and from board to board, due to the
embedded signatures). Rather than listing all the firmware files,
including full paths, in the DT, provide a way to determine firmware
path based on the root DT node compatible.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/soc/qcom/Kconfig | 5 +++
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/qcom_fw_helper.c | 86 ++++++++++++++++++++++++++++++++++++++
include/linux/soc/qcom/fw_helper.h | 10 +++++
4 files changed, 102 insertions(+)
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 5af33b0e3470..b663774d65f8 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -62,6 +62,11 @@ config QCOM_MDT_LOADER
tristate
select QCOM_SCM
+config QCOM_FW_HELPER
+ tristate "NONE FW HELPER"
+ help
+ Helpers to return platform-specific location for the firmware files.
+
config QCOM_OCMEM
tristate "Qualcomm On Chip Memory (OCMEM) driver"
depends on ARCH_QCOM
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index ca0bece0dfff..e612bee5b955 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
+obj-$(CONFIG_QCOM_FW_HELPER) += qcom_fw_helper.o
obj-$(CONFIG_QCOM_OCMEM) += ocmem.o
obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o
obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink.o
diff --git a/drivers/soc/qcom/qcom_fw_helper.c b/drivers/soc/qcom/qcom_fw_helper.c
new file mode 100644
index 000000000000..13123c2514b8
--- /dev/null
+++ b/drivers/soc/qcom/qcom_fw_helper.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Qualcomm Firmware loading data
+ *
+ * Copyright (C) 2024 Linaro Ltd
+ */
+
+#include <linux/cleanup.h>
+#include <linux/device.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/soc/qcom/fw_helper.h>
+
+static DEFINE_MUTEX(qcom_fw_mutex);
+static const char *fw_path;
+
+static const struct of_device_id qcom_fw_paths[] = {
+ /* device-specific entries */
+ { .compatible = "thundercomm,db845c", .data = "qcom/sdm845/Thundercomm/db845c", },
+ { .compatible = "qcom,qrb5165-rb5", .data = "qcom/sm8250/Thundercomm/RB5", },
+ /* SoC default entries */
+ { .compatible = "qcom,apq8016", .data = "qcom/apq8016", },
+ { .compatible = "qcom,apq8096", .data = "qcom/apq8096", },
+ { .compatible = "qcom,sdm845", .data = "qcom/sdm845", },
+ { .compatible = "qcom,sm8250", .data = "qcom/sm8250", },
+ { .compatible = "qcom,sm8350", .data = "qcom/sm8350", },
+ { .compatible = "qcom,sm8450", .data = "qcom/sm8450", },
+ { .compatible = "qcom,sm8550", .data = "qcom/sm8550", },
+ { .compatible = "qcom,sm8650", .data = "qcom/sm8650", },
+ {},
+};
+
+static int qcom_fw_ensure_init(void)
+{
+ const struct of_device_id *match;
+ struct device_node *root;
+
+ if (fw_path)
+ return 0;
+
+ root = of_find_node_by_path("/");
+ if (!root)
+ return -ENODEV;
+
+ match = of_match_node(qcom_fw_paths, root);
+ of_node_put(root);
+ if (!match || !match->data) {
+ pr_notice("Platform not supported by qcom_fw_helper\n");
+ return -ENODEV;
+ }
+
+ fw_path = match->data;
+
+ return 0;
+}
+
+const char *qcom_get_board_fw(const char *firmware)
+{
+ if (strchr(firmware, '/'))
+ return kstrdup(firmware, GFP_KERNEL);
+
+ scoped_guard(mutex, &qcom_fw_mutex) {
+ if (!qcom_fw_ensure_init())
+ return kasprintf(GFP_KERNEL, "%s/%s", fw_path, firmware);
+ }
+
+ return kstrdup(firmware, GFP_KERNEL);
+}
+EXPORT_SYMBOL_GPL(qcom_get_board_fw);
+
+const char *devm_qcom_get_board_fw(struct device *dev, const char *firmware)
+{
+ if (strchr(firmware, '/'))
+ return devm_kstrdup(dev, firmware, GFP_KERNEL);
+
+ scoped_guard(mutex, &qcom_fw_mutex) {
+ if (!qcom_fw_ensure_init())
+ return devm_kasprintf(dev, GFP_KERNEL, "%s/%s", fw_path, firmware);
+ }
+
+ return devm_kstrdup(dev, firmware, GFP_KERNEL);
+}
+EXPORT_SYMBOL_GPL(devm_qcom_get_board_fw);
+
+MODULE_DESCRIPTION("Firmware helpers for Qualcomm devices");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/soc/qcom/fw_helper.h b/include/linux/soc/qcom/fw_helper.h
new file mode 100644
index 000000000000..755645386bba
--- /dev/null
+++ b/include/linux/soc/qcom/fw_helper.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __QCOM_FW_HELPER_H__
+#define __QCOM_FW_HELPER_H__
+
+struct device;
+
+const char *qcom_get_board_fw(const char *firmware);
+const char *devm_qcom_get_board_fw(struct device *dev, const char *firmware);
+
+#endif
--
2.39.2
^ permalink raw reply related [relevance 6%]
* [linux-linus test] 186047: tolerable FAIL - PUSHED
@ 2024-05-21 1:19 2% osstest service owner
0 siblings, 0 replies; 200+ results
From: osstest service owner @ 2024-05-21 1:19 UTC (permalink / raw)
To: xen-devel
flight 186047 linux-linus real [real]
flight 186051 linux-linus real-retest [real]
http://logs.test-lab.xenproject.org/osstest/logs/186047/
http://logs.test-lab.xenproject.org/osstest/logs/186051/
Failures :-/ but no regressions.
Tests which are failing intermittently (not blocking):
test-armhf-armhf-xl-credit1 8 xen-boot fail pass in 186051-retest
Tests which did not succeed, but are not blocking:
test-armhf-armhf-xl-credit1 15 migrate-support-check fail in 186051 never pass
test-armhf-armhf-xl-credit1 16 saverestore-support-check fail in 186051 never pass
test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stop fail like 186036
test-amd64-amd64-xl-qemuu-win7-amd64 19 guest-stop fail like 186036
test-amd64-amd64-xl-qemuu-ws16-amd64 19 guest-stop fail like 186036
test-armhf-armhf-libvirt 16 saverestore-support-check fail like 186036
test-amd64-amd64-qemuu-nested-amd 20 debian-hvm-install/l1/l2 fail like 186036
test-amd64-amd64-xl-qemut-ws16-amd64 19 guest-stop fail like 186036
test-amd64-amd64-libvirt 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-xsm 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass
test-arm64-arm64-xl 15 migrate-support-check fail never pass
test-arm64-arm64-xl 16 saverestore-support-check fail never pass
test-arm64-arm64-libvirt-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-libvirt-xsm 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-xl-xsm 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit1 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit1 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit2 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit2 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-thunderx 15 migrate-support-check fail never pass
test-arm64-arm64-xl-thunderx 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-rtds 15 migrate-support-check fail never pass
test-armhf-armhf-xl-rtds 16 saverestore-support-check fail never pass
test-amd64-amd64-libvirt-qcow2 14 migrate-support-check fail never pass
test-amd64-amd64-libvirt-raw 14 migrate-support-check fail never pass
test-armhf-armhf-xl-arndale 15 migrate-support-check fail never pass
test-armhf-armhf-xl-arndale 16 saverestore-support-check fail never pass
test-amd64-amd64-libvirt-vhd 14 migrate-support-check fail never pass
test-armhf-armhf-xl-qcow2 14 migrate-support-check fail never pass
test-armhf-armhf-xl-qcow2 15 saverestore-support-check fail never pass
test-arm64-arm64-xl-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-xl-vhd 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-credit2 15 migrate-support-check fail never pass
test-armhf-armhf-xl-credit2 16 saverestore-support-check fail never pass
test-armhf-armhf-libvirt-vhd 14 migrate-support-check fail never pass
test-armhf-armhf-libvirt-vhd 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-multivcpu 15 migrate-support-check fail never pass
test-armhf-armhf-xl-multivcpu 16 saverestore-support-check fail never pass
test-armhf-armhf-xl 15 migrate-support-check fail never pass
test-armhf-armhf-xl 16 saverestore-support-check fail never pass
test-armhf-armhf-libvirt 15 migrate-support-check fail never pass
test-arm64-arm64-libvirt-raw 14 migrate-support-check fail never pass
test-arm64-arm64-libvirt-raw 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-raw 14 migrate-support-check fail never pass
test-armhf-armhf-xl-raw 15 saverestore-support-check fail never pass
version targeted for testing:
linux eb6a9339efeb6f3d2b5c86fdf2382cdc293eca2c
baseline version:
linux 25f4874662fb0d43fc1d934dd7802b740ed2ab5f
Last test of basis 186036 2024-05-18 21:13:52 Z 2 days
Failing since 186038 2024-05-19 03:51:42 Z 1 days 5 attempts
Testing same since 186044 2024-05-20 05:14:37 Z 0 days 2 attempts
------------------------------------------------------------
People who touched revisions under test:
"Chen, Tim C" <tim.c.chen@intel.com>
"Huang, Ying" <ying.huang@intel.com>
"King, Colin" <colin.king@intel.com>
Adrian Hunter <adrian.hunter@intel.com>
Aleksandr Aprelkov <aaprelkov@usergate.com>
Alex Rusuf <yorha.op@gmail.com>
Alex Shi (tencent) <alexs@kernel.org>
Alex Shi <alexs@kernel.org>
Alexander Potapenko <glider@google.com>
Alexandre Ghiti <alexghiti@rivosinc.com
Alexei Starovoitov <ast@kernel.org>
Alexey Dobriyan <adobriyan@gmail.com>
Andrew Morton <akpm@linux-foundation.org>
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Aneesh Kumar K.V (IBM) <aneesh.kumar@kernel.org>
Arnaldo Carvalho de Melo <acme@redhat.com>
Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann <arnd@kernel.org>
Axel Rasmussen <axelrasmussen@google.com>
Baokun Li <libaokun1@huawei.com>
Baolin Wang <baolin.wang@linux.alibaba.com>
Baoquan He <bhe@redhat.com>
Barry Song <v-songbaohua@oppo.com>
Bart Van Assche <bvanassche@acm.org>
Borislav Petkov (AMD) <bp@alien8.de>
Borislav Petkov <bp@suse.de>
Breno Leitao <leitao@debian.org>
Brian Foster <bfoster@redhat.com>
Brian Geffon <bgeffon@google.com>
Catalin Marinas <catalin.marinas@arm.com>
Chang S. Bae <chang.seok.bae@intel.com>
Cheng Yu <serein.chengyu@huawei.com>
Chris Li <chrisl@kernel.org>
Christian Loehle <christian.loehle@arm.com>
Christoph Hellwig <hch@lst.de>
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Christophe Leroy <christophe.leroy@csgroup.eu>
Chuck Lever <chuck.lever@oracle.com>
Colin Ian King <colin.i.king@gmail.com>
Dan Carpenter <dan.carpenter@linaro.org>
Daniel Hill <daniel@gluo.nz>
Daniel Thompson <daniel.thompson@linaro.org>
Dave Hansen <dave.hansen@linux.intel.com>
David Hildenbrand <david@redhat.com>
Dawei Li <daweilics@gmail.com>
Dennis Zhou <dennis@kernel.org>
Dev Jain <dev.jain@arm.com>
Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
Dietmar Eggemann <dietmar.eggemann@arm.com>
Disha Goel <disgoel@linux.ibm.com>
Donet Tom <donettom@linux.ibm.com>
Douglas Anderson <dianders@chromium.org>
Duoming Zhou <duoming@zju.edu.cn>
Edward Liaw <edliaw@google.com>
Eric Sandeen <sandeen@redhat.com>
Florian Rommel <mail@florommel.de>
Frank van der Linden <fvdl@google.com>
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Guenter Roeck <linux@roeck-us.net>
Guoqing Jiang <guoqing.jiang@linux.dev>
Hao Ge <gehao@kylinos.cn>
Hao Xiang <hao.xiang@bytedance.com>
Hariom Panthi <hariom1.p@samsung.com>
Helge Deller <deller@gmx.de>
Helge Deller <deller@gmx.de> [parisc]
Heming Zhao <heming.zhao@suse.com>
Ho-Ren (Jack) Chuang <horenchuang@bytedance.com>
Hongbo Li <lihongbo22@huawei.com>
Honggyu Kim <honggyu.kim@sk.com>
Huang Shijie <shijie@os.amperecomputing.com>
Huang Ying <ying.huang@intel.com>
Ingo Molnar <mingo@kernel.org>
James Houghton <jthoughton@google.com>
Jan Kara <jack@suse.cz>
Jan Kara <jack@suse.cz> [jbd2]
Jeff Layton <jlayton@kernel.org>
Jinjiang Tu <tujinjiang@huawei.com>
Joe Perches <joe@perches.com>
Joel Granados <j.granados@samsung.com>
Johannes Weiner <hannes@cmpxchg.org>
John Hubbard <jhubbard@nvidia.com>
Joseph Qi <joseph.qi@linux.alibaba.com>
Justin Stitt <justinstitt@google.com>
K Prateek Nayak <kprateek.nayak@amd.com>
Kairui Song <kasong@tencent.com>
Kees Cook <keescook@chromium.org>
Kefeng Wang <wangkefeng.wang@huawei.com>
Kemeng Shi <shikemeng@huaweicloud.com>
Kent Overstreet <kent.overstreet@linux.dev>
Klara Modin <klarasmodin@gmail.com>
Konrad Dybcio <konrad.dybcio@linaro.org> # QC SM8550 QRD
Kuan-Wei Chiu <visitorckw@gmail.com>
Lance Yang <ioworker0@gmail.com>
Len Brown <len.brown@intel.com>
Li kunyu <kunyu@nfschina.com>
Liam R. Howlett <Liam.Howlett@oracle.com>
linke li <lilinke99@qq.com>
Linus Torvalds <torvalds@linux-foundation.org>
Liu Shixin <liushixin2@huawei.com>
Long Li <leo.lilong@huawei.com>
Lorenzo Bianconi <lorenzo@kernel.org>
Lucas Stach <l.stach@pengutronix.de>
Luis Henriques <lhenriques@suse.de>
Lukas Bulwahn <lbulwahn@redhat.com>
Lukas Bulwahn <lukas.bulwahn@redhat.com>
Matthew Wilcox (Oracle) <willy@infradead.org>
Matthew Wilcox <willy@infradead.org>
Max Kellermann <max.kellermann@ionos.com>
Mel Gorman <mgorman@techsingularity.net>
Miaohe Lin <linmiaohe@huawei.com>
Michael Ellerman <mpe@ellerman.id.au>
Michael Ellerman <mpe@ellerman.id.au> (powerpc)
Michael Forney <mforney@mforney.org>
Michal Hocko <mhocko@suse.com>
Miguel Ojeda <ojeda@kernel.org>
Nathan Chancellor <nathan@kernel.org>
NeilBrown <neilb@suse.de>
Nhat Pham <nphamcs@gmail.com>
Niklas Schnelle <schnelle@linux.ibm.com>
OGAWA Hirofumi <hirofumi@mail.parknet.co.jp>
Oscar Salvador <osalvador@suse.de>
Palmer Dabbelt <palmer@rivosinc.com> [RISC-V]
Pankaj Raghav <p.raghav@samsung.com>
Patryk Wlazlyn <patryk.wlazlyn@linux.intel.com>
Peter Xu <peterx@redhat.com>
Petr Vorel <pvorel@suse.cz>
Phillip Lougher <phillip@squashfs.org.uk>
Randy Dunlap <rdunlap@infradead.org>
Rasmus Villemoes <linux@rasmusvillemoes.dk>
Ricardo B. Marliere <ricardo@marliere.net>
Rick Edgecombe <rick.p.edgecombe@intel.com>
Rik van Riel <riel@surriel.com>
Ritesh Harjani (IBM) <ritesh.list@gmail.com>
Roman Gushchin <roman.gushchin@linux.dev>
rulinhuang <rulin.huang@intel.com>
Ryan Roberts <ryan.roberts@arm.com>
Ryusuke Konishi <konishi.ryusuke@gmail.com>
Saurav Shah <sauravshah.31@gmail.com>
Sean Christopherson <seanjc@google.com> [KVM]
SeongJae Park <sj@kernel.org>
Sergey Senozhatsky <senozhatsky@chromium.org>
Shakeel Butt <shakeel.butt@linux.dev>
Sidhartha Kumar <sidhartha.kumar@oracle.com>
Song Liu <song@kernel.org>
Stephen Smalley <stephen.smalley.work@gmail.com>
Steve French <stfrench@microsoft.com>
Su Yue <glass.su@suse.com>
Sudeep Holla <sudeep.holla@arm.com>
Suren Baghdasaryan <surenb@google.com>
Tejun Heo <tj@kernel.org>
Theodore Ts'o <tytso@mit.edu>
Thomas Bertschinger <tahbertschinger@gmail.com>
Thorsten Blum <thorsten.blum@toblux.com>
Trond Myklebust <trond.myklebust@hammerspace.com>
Usama Arif <usamaarif642@gmail.com>
Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Vincent Guittot <vincent.guittot@linaro.org>
Vishal Moola (Oracle) <vishal.moola@gmail.com>
Vishal Verma <vishal.l.verma@intel.com>
Vitalii Bursov <vitaly@bursov.com>
Vladimir Benes <vbenes@redhat.com>
Vlastimil Babka <vbabka@suse.cz>
Waiman Long <longman@redhat.com>
Wei Yang <richard.weiyang@gmail.com>
Xining Xu <mac.xxn@outlook.com>
Xiu Jianfeng <xiujianfeng@huawei.com>
Yajun Deng <yajun.deng@linux.dev>
Yang Li <yang.lee@linux.alibaba.com>
Ye Bin <yebin10@huawei.com>
York Jasper Niebuhr <yjnworkstation@gmail.com>
Yosry Ahmed <yosryahmed@google.com>
Youling Tang <tangyouling@kylinos.cn>
Yu Zhao <yuzhao@google.com>
Zhang Qiao <zhangqiao22@huawei.com>
Zhang Rui <rui.zhang@intel.com>
Zhang Yi <yi.zhang@huawei.com>
ZhangPeng <zhangpeng362@huawei.com>
Zi Yan <ziy@nvidia.com>
jobs:
build-amd64-xsm pass
build-arm64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-arm64 pass
build-armhf pass
build-i386 pass
build-amd64-libvirt pass
build-arm64-libvirt pass
build-armhf-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-arm64-pvops pass
build-armhf-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl pass
test-amd64-coresched-amd64-xl pass
test-arm64-arm64-xl pass
test-armhf-armhf-xl pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-stubdom-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-debianhvm-i386-xsm pass
test-amd64-amd64-xl-qemuu-debianhvm-i386-xsm pass
test-amd64-amd64-libvirt-xsm pass
test-arm64-arm64-libvirt-xsm pass
test-amd64-amd64-xl-xsm pass
test-arm64-arm64-xl-xsm pass
test-amd64-amd64-qemuu-nested-amd fail
test-amd64-amd64-xl-pvhv2-amd pass
test-amd64-amd64-dom0pvh-xl-amd pass
test-amd64-amd64-xl-qemut-debianhvm-amd64 pass
test-amd64-amd64-xl-qemuu-debianhvm-amd64 pass
test-amd64-amd64-qemuu-freebsd11-amd64 pass
test-amd64-amd64-qemuu-freebsd12-amd64 pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-amd64-xl-qemut-win7-amd64 fail
test-amd64-amd64-xl-qemuu-win7-amd64 fail
test-amd64-amd64-xl-qemut-ws16-amd64 fail
test-amd64-amd64-xl-qemuu-ws16-amd64 fail
test-armhf-armhf-xl-arndale pass
test-amd64-amd64-examine-bios pass
test-amd64-amd64-xl-credit1 pass
test-arm64-arm64-xl-credit1 pass
test-armhf-armhf-xl-credit1 fail
test-amd64-amd64-xl-credit2 pass
test-arm64-arm64-xl-credit2 pass
test-armhf-armhf-xl-credit2 pass
test-amd64-amd64-xl-qemuu-dmrestrict-amd64-dmrestrict pass
test-amd64-amd64-examine pass
test-arm64-arm64-examine pass
test-armhf-armhf-examine pass
test-amd64-amd64-qemuu-nested-intel pass
test-amd64-amd64-xl-pvhv2-intel pass
test-amd64-amd64-dom0pvh-xl-intel pass
test-amd64-amd64-libvirt pass
test-armhf-armhf-libvirt pass
test-amd64-amd64-xl-multivcpu pass
test-armhf-armhf-xl-multivcpu pass
test-amd64-amd64-pair pass
test-amd64-amd64-libvirt-pair pass
test-amd64-amd64-xl-pvshim pass
test-amd64-amd64-pygrub pass
test-amd64-amd64-libvirt-qcow2 pass
test-amd64-amd64-xl-qcow2 pass
test-armhf-armhf-xl-qcow2 pass
test-amd64-amd64-libvirt-raw pass
test-arm64-arm64-libvirt-raw pass
test-amd64-amd64-xl-raw pass
test-armhf-armhf-xl-raw pass
test-amd64-amd64-xl-rtds pass
test-armhf-armhf-xl-rtds pass
test-amd64-amd64-xl-qemuu-debianhvm-amd64-shadow pass
test-amd64-amd64-xl-shadow pass
test-arm64-arm64-xl-thunderx pass
test-amd64-amd64-examine-uefi pass
test-amd64-amd64-libvirt-vhd pass
test-armhf-armhf-libvirt-vhd pass
test-amd64-amd64-xl-vhd pass
test-arm64-arm64-xl-vhd pass
------------------------------------------------------------
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
Pushing revision :
hint: The 'hooks/update' hook was ignored because it's not set as executable.
hint: You can disable this warning with `git config advice.ignoredHook false`.
hint: The 'hooks/post-receive' hook was ignored because it's not set as executable.
hint: You can disable this warning with `git config advice.ignoredHook false`.
hint: The 'hooks/post-update' hook was ignored because it's not set as executable.
hint: You can disable this warning with `git config advice.ignoredHook false`.
To xenbits.xen.org:/home/xen/git/linux-pvops.git
25f4874662fb..eb6a9339efeb eb6a9339efeb6f3d2b5c86fdf2382cdc293eca2c -> tested/linux-linus
^ permalink raw reply [relevance 2%]
* [PATCH v5 4/5] arm64: dts: qcom: sm8550: Add Broadcast_AND register in LLCC block
2024-05-20 21:00 6% [PATCH v5 0/5] LLCC: Support for Broadcast_AND region Unnathi Chalicheemala
2024-05-20 21:00 9% ` [PATCH v5 1/5] dt-bindings: arm: msm: Add llcc Broadcast_AND register Unnathi Chalicheemala
@ 2024-05-20 21:00 17% ` Unnathi Chalicheemala
1 sibling, 0 replies; 200+ results
From: Unnathi Chalicheemala @ 2024-05-20 21:00 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Unnathi Chalicheemala, linux-arm-msm, devicetree, linux-kernel, kernel
Chipsets before SM8450 have only one broadcast register (Broadcast_OR)
which is used to broadcast writes and check for status bit 0 only in
all channels.
From SM8450 onwards, a new Broadcast_AND region was added
which checks for status bit 1. This hasn't been updated and Broadcast_OR
region was wrongly being used to check for status bit 1 all along.
Hence mapping Broadcast_AND region's address space to LLCC in SM8550.
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 3904348075f6..ee387e6f9832 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -4263,12 +4263,14 @@ system-cache-controller@25000000 {
<0 0x25200000 0 0x200000>,
<0 0x25400000 0 0x200000>,
<0 0x25600000 0 0x200000>,
- <0 0x25800000 0 0x200000>;
+ <0 0x25800000 0 0x200000>,
+ <0 0x25a00000 0 0x200000>;
reg-names = "llcc0_base",
"llcc1_base",
"llcc2_base",
"llcc3_base",
- "llcc_broadcast_base";
+ "llcc_broadcast_base",
+ "llcc_broadcast_and_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
--
2.34.1
^ permalink raw reply related [relevance 17%]
* [PATCH v5 1/5] dt-bindings: arm: msm: Add llcc Broadcast_AND register
2024-05-20 21:00 6% [PATCH v5 0/5] LLCC: Support for Broadcast_AND region Unnathi Chalicheemala
@ 2024-05-20 21:00 9% ` Unnathi Chalicheemala
2024-05-20 21:00 17% ` [PATCH v5 4/5] arm64: dts: qcom: sm8550: Add Broadcast_AND register in LLCC block Unnathi Chalicheemala
1 sibling, 0 replies; 200+ results
From: Unnathi Chalicheemala @ 2024-05-20 21:00 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Unnathi Chalicheemala, linux-arm-msm, devicetree, linux-kernel,
kernel, Krzysztof Kozlowski
The LLCC block in SM8450, SM8550 and SM8650 have a new register
space for Broadcast_AND region. This is used to check that all
channels have bit set to "1", mainly in SCID activation/deactivation.
Previously we were mapping only the Broadcast_OR region assuming
there was only one broadcast register region. Now we also map
Broadcast_AND region.
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../devicetree/bindings/cache/qcom,llcc.yaml | 27 ++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index 07ccbda4a0ab..a6237028957f 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -141,8 +141,31 @@ allOf:
- qcom,sm8150-llcc
- qcom,sm8250-llcc
- qcom,sm8350-llcc
+ then:
+ properties:
+ reg:
+ items:
+ - description: LLCC0 base register region
+ - description: LLCC1 base register region
+ - description: LLCC2 base register region
+ - description: LLCC3 base register region
+ - description: LLCC broadcast base register region
+ reg-names:
+ items:
+ - const: llcc0_base
+ - const: llcc1_base
+ - const: llcc2_base
+ - const: llcc3_base
+ - const: llcc_broadcast_base
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,sm8450-llcc
- qcom,sm8550-llcc
+ - qcom,sm8650-llcc
then:
properties:
reg:
@@ -151,7 +174,8 @@ allOf:
- description: LLCC1 base register region
- description: LLCC2 base register region
- description: LLCC3 base register region
- - description: LLCC broadcast base register region
+ - description: LLCC broadcast OR register region
+ - description: LLCC broadcast AND register region
reg-names:
items:
- const: llcc0_base
@@ -159,6 +183,7 @@ allOf:
- const: llcc2_base
- const: llcc3_base
- const: llcc_broadcast_base
+ - const: llcc_broadcast_and_base
additionalProperties: false
--
2.34.1
^ permalink raw reply related [relevance 9%]
* [PATCH v5 0/5] LLCC: Support for Broadcast_AND region
@ 2024-05-20 21:00 6% Unnathi Chalicheemala
2024-05-20 21:00 9% ` [PATCH v5 1/5] dt-bindings: arm: msm: Add llcc Broadcast_AND register Unnathi Chalicheemala
2024-05-20 21:00 17% ` [PATCH v5 4/5] arm64: dts: qcom: sm8550: Add Broadcast_AND register in LLCC block Unnathi Chalicheemala
0 siblings, 2 replies; 200+ results
From: Unnathi Chalicheemala @ 2024-05-20 21:00 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Unnathi Chalicheemala, linux-arm-msm, devicetree, linux-kernel, kernel
This series adds:
1. Device tree register mapping for Broadcast_AND region in SM8450,
SM8550, SM8650.
2. LLCC driver updates to reflect addition of Broadcast_AND regmap.
To support CSR programming, a broadcast interface is used to program all
channels in a single command. Until SM8450 there was only one broadcast
region (Broadcast_OR) used to broadcast write and check for status bit
0. From SM8450 onwards another broadcast region (Broadcast_AND) has been
added which checks for status bit 1.
This series updates the device trees from SM8450 onwards to have a
mapping to this Broadcast_AND region. It also updates the llcc_drv_data
structure with a regmap for Broadcast_AND region and corrects the
broadcast region used to check for status bit 1.
Changes in v5:
- Add additional check to remove warning from devres.c on older
chipsets.
- Carried over Bjorn's and Krzysztof's R-b tags from v4.
Changes in v4:
- Updated Devicetree patches' commit messages to make problem statement
clearer
- Resolved Konrad's comments on driver code patch
- Updated v3 changelog to include dropped R-b tag
Changes in v3:
- Removed new example in dt-bindings patch and ran 'make
DT_CHECKER_FLAGS=-m dt_binding_check'
- Dropped Krzysztof's R-b tag on dt-bindings patch
- Use of ternary operator in llcc_update_act_ctrl()
- Add comment before initialization of Broadcast_AND regmap in probe
- Move DeviceTree patches to the end
Changes in v2:
- Added an additional check in the case old DT files are used for
above mentioned chipsets for backwards compatibility
- Moved addition of if check in llcc_update_act_ctrl() to a separate
"Fixes" patch; not part of this series
Link to v4: https://lore.kernel.org/all/20240329-llcc-broadcast-and-v4-0-107c76fd8ceb@quicinc.com/
Link to v3: https://lore.kernel.org/all/cover.1708551850.git.quic_uchalich@quicinc.com/
Link to v2: https://lore.kernel.org/all/cover.1707202761.git.quic_uchalich@quicinc.com/
Link to v1: https://lore.kernel.org/all/cover.1706296015.git.quic_uchalich@quicinc.com/
Unnathi Chalicheemala (5):
dt-bindings: arm: msm: Add llcc Broadcast_AND register
soc: qcom: llcc: Add regmap for Broadcast_AND region
arm64: dts: qcom: sm8450: Add Broadcast_AND register in LLCC block
arm64: dts: qcom: sm8550: Add Broadcast_AND register in LLCC block
arm64: dts: qcom: sm8650: Add Broadcast_AND register in LLCC block
.../devicetree/bindings/cache/qcom,llcc.yaml | 27 ++++++++++++++++++-
arch/arm64/boot/dts/qcom/sm8450.dtsi | 5 ++--
arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++--
arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +++--
drivers/soc/qcom/llcc-qcom.c | 16 ++++++++++-
include/linux/soc/qcom/llcc-qcom.h | 4 ++-
6 files changed, 55 insertions(+), 9 deletions(-)
--
2.34.1
^ permalink raw reply [relevance 6%]
* [linux-linus test] 186044: regressions - FAIL
@ 2024-05-20 14:59 2% osstest service owner
0 siblings, 0 replies; 200+ results
From: osstest service owner @ 2024-05-20 14:59 UTC (permalink / raw)
To: xen-devel
flight 186044 linux-linus real [real]
flight 186045 linux-linus real-retest [real]
http://logs.test-lab.xenproject.org/osstest/logs/186044/
http://logs.test-lab.xenproject.org/osstest/logs/186045/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-armhf-armhf-xl-credit1 8 xen-boot fail REGR. vs. 186036
test-armhf-armhf-libvirt 8 xen-boot fail REGR. vs. 186036
Tests which are failing intermittently (not blocking):
test-armhf-armhf-xl-arndale 8 xen-boot fail pass in 186045-retest
test-armhf-armhf-xl-qcow2 8 xen-boot fail pass in 186045-retest
test-armhf-armhf-xl-raw 8 xen-boot fail pass in 186045-retest
test-armhf-armhf-xl-multivcpu 8 xen-boot fail pass in 186045-retest
Regressions which are regarded as allowable (not blocking):
test-armhf-armhf-xl-rtds 12 debian-install fail REGR. vs. 186036
Tests which did not succeed, but are not blocking:
test-armhf-armhf-xl-arndale 15 migrate-support-check fail in 186045 never pass
test-armhf-armhf-xl-arndale 16 saverestore-support-check fail in 186045 never pass
test-armhf-armhf-xl-multivcpu 15 migrate-support-check fail in 186045 never pass
test-armhf-armhf-xl-multivcpu 16 saverestore-support-check fail in 186045 never pass
test-armhf-armhf-xl-qcow2 14 migrate-support-check fail in 186045 never pass
test-armhf-armhf-xl-qcow2 15 saverestore-support-check fail in 186045 never pass
test-armhf-armhf-xl-raw 14 migrate-support-check fail in 186045 never pass
test-armhf-armhf-xl-raw 15 saverestore-support-check fail in 186045 never pass
test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stop fail like 186036
test-amd64-amd64-xl-qemuu-win7-amd64 19 guest-stop fail like 186036
test-amd64-amd64-xl-qemuu-ws16-amd64 19 guest-stop fail like 186036
test-amd64-amd64-qemuu-nested-amd 20 debian-hvm-install/l1/l2 fail like 186036
test-amd64-amd64-xl-qemut-ws16-amd64 19 guest-stop fail like 186036
test-amd64-amd64-libvirt 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-xsm 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass
test-arm64-arm64-xl 15 migrate-support-check fail never pass
test-arm64-arm64-xl 16 saverestore-support-check fail never pass
test-arm64-arm64-libvirt-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-libvirt-xsm 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-xl-xsm 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit1 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit1 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit2 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit2 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-thunderx 15 migrate-support-check fail never pass
test-arm64-arm64-xl-thunderx 16 saverestore-support-check fail never pass
test-amd64-amd64-libvirt-qcow2 14 migrate-support-check fail never pass
test-amd64-amd64-libvirt-raw 14 migrate-support-check fail never pass
test-amd64-amd64-libvirt-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-xl-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-xl-vhd 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-credit2 15 migrate-support-check fail never pass
test-armhf-armhf-xl-credit2 16 saverestore-support-check fail never pass
test-armhf-armhf-libvirt-vhd 14 migrate-support-check fail never pass
test-armhf-armhf-libvirt-vhd 15 saverestore-support-check fail never pass
test-armhf-armhf-xl 15 migrate-support-check fail never pass
test-armhf-armhf-xl 16 saverestore-support-check fail never pass
test-arm64-arm64-libvirt-raw 14 migrate-support-check fail never pass
test-arm64-arm64-libvirt-raw 15 saverestore-support-check fail never pass
version targeted for testing:
linux eb6a9339efeb6f3d2b5c86fdf2382cdc293eca2c
baseline version:
linux 25f4874662fb0d43fc1d934dd7802b740ed2ab5f
Last test of basis 186036 2024-05-18 21:13:52 Z 1 days
Failing since 186038 2024-05-19 03:51:42 Z 1 days 4 attempts
Testing same since 186044 2024-05-20 05:14:37 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
"Chen, Tim C" <tim.c.chen@intel.com>
"Huang, Ying" <ying.huang@intel.com>
"King, Colin" <colin.king@intel.com>
Adrian Hunter <adrian.hunter@intel.com>
Aleksandr Aprelkov <aaprelkov@usergate.com>
Alex Rusuf <yorha.op@gmail.com>
Alex Shi (tencent) <alexs@kernel.org>
Alex Shi <alexs@kernel.org>
Alexander Potapenko <glider@google.com>
Alexandre Ghiti <alexghiti@rivosinc.com
Alexei Starovoitov <ast@kernel.org>
Alexey Dobriyan <adobriyan@gmail.com>
Andrew Morton <akpm@linux-foundation.org>
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Aneesh Kumar K.V (IBM) <aneesh.kumar@kernel.org>
Arnaldo Carvalho de Melo <acme@redhat.com>
Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann <arnd@kernel.org>
Axel Rasmussen <axelrasmussen@google.com>
Baokun Li <libaokun1@huawei.com>
Baolin Wang <baolin.wang@linux.alibaba.com>
Baoquan He <bhe@redhat.com>
Barry Song <v-songbaohua@oppo.com>
Bart Van Assche <bvanassche@acm.org>
Borislav Petkov (AMD) <bp@alien8.de>
Borislav Petkov <bp@suse.de>
Breno Leitao <leitao@debian.org>
Brian Foster <bfoster@redhat.com>
Brian Geffon <bgeffon@google.com>
Catalin Marinas <catalin.marinas@arm.com>
Chang S. Bae <chang.seok.bae@intel.com>
Cheng Yu <serein.chengyu@huawei.com>
Chris Li <chrisl@kernel.org>
Christian Loehle <christian.loehle@arm.com>
Christoph Hellwig <hch@lst.de>
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Christophe Leroy <christophe.leroy@csgroup.eu>
Chuck Lever <chuck.lever@oracle.com>
Colin Ian King <colin.i.king@gmail.com>
Dan Carpenter <dan.carpenter@linaro.org>
Daniel Hill <daniel@gluo.nz>
Daniel Thompson <daniel.thompson@linaro.org>
Dave Hansen <dave.hansen@linux.intel.com>
David Hildenbrand <david@redhat.com>
Dawei Li <daweilics@gmail.com>
Dennis Zhou <dennis@kernel.org>
Dev Jain <dev.jain@arm.com>
Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
Dietmar Eggemann <dietmar.eggemann@arm.com>
Disha Goel <disgoel@linux.ibm.com>
Donet Tom <donettom@linux.ibm.com>
Douglas Anderson <dianders@chromium.org>
Duoming Zhou <duoming@zju.edu.cn>
Edward Liaw <edliaw@google.com>
Eric Sandeen <sandeen@redhat.com>
Florian Rommel <mail@florommel.de>
Frank van der Linden <fvdl@google.com>
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Guenter Roeck <linux@roeck-us.net>
Guoqing Jiang <guoqing.jiang@linux.dev>
Hao Ge <gehao@kylinos.cn>
Hao Xiang <hao.xiang@bytedance.com>
Hariom Panthi <hariom1.p@samsung.com>
Helge Deller <deller@gmx.de>
Helge Deller <deller@gmx.de> [parisc]
Heming Zhao <heming.zhao@suse.com>
Ho-Ren (Jack) Chuang <horenchuang@bytedance.com>
Hongbo Li <lihongbo22@huawei.com>
Honggyu Kim <honggyu.kim@sk.com>
Huang Shijie <shijie@os.amperecomputing.com>
Huang Ying <ying.huang@intel.com>
Ingo Molnar <mingo@kernel.org>
James Houghton <jthoughton@google.com>
Jan Kara <jack@suse.cz>
Jan Kara <jack@suse.cz> [jbd2]
Jeff Layton <jlayton@kernel.org>
Jinjiang Tu <tujinjiang@huawei.com>
Joe Perches <joe@perches.com>
Joel Granados <j.granados@samsung.com>
Johannes Weiner <hannes@cmpxchg.org>
John Hubbard <jhubbard@nvidia.com>
Joseph Qi <joseph.qi@linux.alibaba.com>
Justin Stitt <justinstitt@google.com>
K Prateek Nayak <kprateek.nayak@amd.com>
Kairui Song <kasong@tencent.com>
Kees Cook <keescook@chromium.org>
Kefeng Wang <wangkefeng.wang@huawei.com>
Kemeng Shi <shikemeng@huaweicloud.com>
Kent Overstreet <kent.overstreet@linux.dev>
Klara Modin <klarasmodin@gmail.com>
Konrad Dybcio <konrad.dybcio@linaro.org> # QC SM8550 QRD
Kuan-Wei Chiu <visitorckw@gmail.com>
Lance Yang <ioworker0@gmail.com>
Len Brown <len.brown@intel.com>
Li kunyu <kunyu@nfschina.com>
Liam R. Howlett <Liam.Howlett@oracle.com>
linke li <lilinke99@qq.com>
Linus Torvalds <torvalds@linux-foundation.org>
Liu Shixin <liushixin2@huawei.com>
Long Li <leo.lilong@huawei.com>
Lorenzo Bianconi <lorenzo@kernel.org>
Lucas Stach <l.stach@pengutronix.de>
Luis Henriques <lhenriques@suse.de>
Lukas Bulwahn <lbulwahn@redhat.com>
Lukas Bulwahn <lukas.bulwahn@redhat.com>
Matthew Wilcox (Oracle) <willy@infradead.org>
Matthew Wilcox <willy@infradead.org>
Max Kellermann <max.kellermann@ionos.com>
Mel Gorman <mgorman@techsingularity.net>
Miaohe Lin <linmiaohe@huawei.com>
Michael Ellerman <mpe@ellerman.id.au>
Michael Ellerman <mpe@ellerman.id.au> (powerpc)
Michael Forney <mforney@mforney.org>
Michal Hocko <mhocko@suse.com>
Miguel Ojeda <ojeda@kernel.org>
Nathan Chancellor <nathan@kernel.org>
NeilBrown <neilb@suse.de>
Nhat Pham <nphamcs@gmail.com>
Niklas Schnelle <schnelle@linux.ibm.com>
OGAWA Hirofumi <hirofumi@mail.parknet.co.jp>
Oscar Salvador <osalvador@suse.de>
Palmer Dabbelt <palmer@rivosinc.com> [RISC-V]
Pankaj Raghav <p.raghav@samsung.com>
Patryk Wlazlyn <patryk.wlazlyn@linux.intel.com>
Peter Xu <peterx@redhat.com>
Petr Vorel <pvorel@suse.cz>
Phillip Lougher <phillip@squashfs.org.uk>
Randy Dunlap <rdunlap@infradead.org>
Rasmus Villemoes <linux@rasmusvillemoes.dk>
Ricardo B. Marliere <ricardo@marliere.net>
Rick Edgecombe <rick.p.edgecombe@intel.com>
Rik van Riel <riel@surriel.com>
Ritesh Harjani (IBM) <ritesh.list@gmail.com>
Roman Gushchin <roman.gushchin@linux.dev>
rulinhuang <rulin.huang@intel.com>
Ryan Roberts <ryan.roberts@arm.com>
Ryusuke Konishi <konishi.ryusuke@gmail.com>
Saurav Shah <sauravshah.31@gmail.com>
Sean Christopherson <seanjc@google.com> [KVM]
SeongJae Park <sj@kernel.org>
Sergey Senozhatsky <senozhatsky@chromium.org>
Shakeel Butt <shakeel.butt@linux.dev>
Sidhartha Kumar <sidhartha.kumar@oracle.com>
Song Liu <song@kernel.org>
Stephen Smalley <stephen.smalley.work@gmail.com>
Steve French <stfrench@microsoft.com>
Su Yue <glass.su@suse.com>
Sudeep Holla <sudeep.holla@arm.com>
Suren Baghdasaryan <surenb@google.com>
Tejun Heo <tj@kernel.org>
Theodore Ts'o <tytso@mit.edu>
Thomas Bertschinger <tahbertschinger@gmail.com>
Thorsten Blum <thorsten.blum@toblux.com>
Trond Myklebust <trond.myklebust@hammerspace.com>
Usama Arif <usamaarif642@gmail.com>
Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Vincent Guittot <vincent.guittot@linaro.org>
Vishal Moola (Oracle) <vishal.moola@gmail.com>
Vishal Verma <vishal.l.verma@intel.com>
Vitalii Bursov <vitaly@bursov.com>
Vladimir Benes <vbenes@redhat.com>
Vlastimil Babka <vbabka@suse.cz>
Waiman Long <longman@redhat.com>
Wei Yang <richard.weiyang@gmail.com>
Xining Xu <mac.xxn@outlook.com>
Xiu Jianfeng <xiujianfeng@huawei.com>
Yajun Deng <yajun.deng@linux.dev>
Yang Li <yang.lee@linux.alibaba.com>
Ye Bin <yebin10@huawei.com>
York Jasper Niebuhr <yjnworkstation@gmail.com>
Yosry Ahmed <yosryahmed@google.com>
Youling Tang <tangyouling@kylinos.cn>
Yu Zhao <yuzhao@google.com>
Zhang Qiao <zhangqiao22@huawei.com>
Zhang Rui <rui.zhang@intel.com>
Zhang Yi <yi.zhang@huawei.com>
ZhangPeng <zhangpeng362@huawei.com>
Zi Yan <ziy@nvidia.com>
jobs:
build-amd64-xsm pass
build-arm64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-arm64 pass
build-armhf pass
build-i386 pass
build-amd64-libvirt pass
build-arm64-libvirt pass
build-armhf-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-arm64-pvops pass
build-armhf-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl pass
test-amd64-coresched-amd64-xl pass
test-arm64-arm64-xl pass
test-armhf-armhf-xl pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-stubdom-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-debianhvm-i386-xsm pass
test-amd64-amd64-xl-qemuu-debianhvm-i386-xsm pass
test-amd64-amd64-libvirt-xsm pass
test-arm64-arm64-libvirt-xsm pass
test-amd64-amd64-xl-xsm pass
test-arm64-arm64-xl-xsm pass
test-amd64-amd64-qemuu-nested-amd fail
test-amd64-amd64-xl-pvhv2-amd pass
test-amd64-amd64-dom0pvh-xl-amd pass
test-amd64-amd64-xl-qemut-debianhvm-amd64 pass
test-amd64-amd64-xl-qemuu-debianhvm-amd64 pass
test-amd64-amd64-qemuu-freebsd11-amd64 pass
test-amd64-amd64-qemuu-freebsd12-amd64 pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-amd64-xl-qemut-win7-amd64 fail
test-amd64-amd64-xl-qemuu-win7-amd64 fail
test-amd64-amd64-xl-qemut-ws16-amd64 fail
test-amd64-amd64-xl-qemuu-ws16-amd64 fail
test-armhf-armhf-xl-arndale fail
test-amd64-amd64-examine-bios pass
test-amd64-amd64-xl-credit1 pass
test-arm64-arm64-xl-credit1 pass
test-armhf-armhf-xl-credit1 fail
test-amd64-amd64-xl-credit2 pass
test-arm64-arm64-xl-credit2 pass
test-armhf-armhf-xl-credit2 pass
test-amd64-amd64-xl-qemuu-dmrestrict-amd64-dmrestrict pass
test-amd64-amd64-examine pass
test-arm64-arm64-examine pass
test-armhf-armhf-examine pass
test-amd64-amd64-qemuu-nested-intel pass
test-amd64-amd64-xl-pvhv2-intel pass
test-amd64-amd64-dom0pvh-xl-intel pass
test-amd64-amd64-libvirt pass
test-armhf-armhf-libvirt fail
test-amd64-amd64-xl-multivcpu pass
test-armhf-armhf-xl-multivcpu fail
test-amd64-amd64-pair pass
test-amd64-amd64-libvirt-pair pass
test-amd64-amd64-xl-pvshim pass
test-amd64-amd64-pygrub pass
test-amd64-amd64-libvirt-qcow2 pass
test-amd64-amd64-xl-qcow2 pass
test-armhf-armhf-xl-qcow2 fail
test-amd64-amd64-libvirt-raw pass
test-arm64-arm64-libvirt-raw pass
test-amd64-amd64-xl-raw pass
test-armhf-armhf-xl-raw fail
test-amd64-amd64-xl-rtds pass
test-armhf-armhf-xl-rtds fail
test-amd64-amd64-xl-qemuu-debianhvm-amd64-shadow pass
test-amd64-amd64-xl-shadow pass
test-arm64-arm64-xl-thunderx pass
test-amd64-amd64-examine-uefi pass
test-amd64-amd64-libvirt-vhd pass
test-armhf-armhf-libvirt-vhd pass
test-amd64-amd64-xl-vhd pass
test-arm64-arm64-xl-vhd pass
------------------------------------------------------------
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
Not pushing.
(No revision log; it would be 20845 lines long.)
^ permalink raw reply [relevance 2%]
* [linux-linus test] 186041: regressions - FAIL
@ 2024-05-20 5:11 2% osstest service owner
0 siblings, 0 replies; 200+ results
From: osstest service owner @ 2024-05-20 5:11 UTC (permalink / raw)
To: xen-devel
flight 186041 linux-linus real [real]
flight 186043 linux-linus real-retest [real]
http://logs.test-lab.xenproject.org/osstest/logs/186041/
http://logs.test-lab.xenproject.org/osstest/logs/186043/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-armhf-armhf-libvirt 8 xen-boot fail REGR. vs. 186036
test-armhf-armhf-examine 8 reboot fail REGR. vs. 186036
Tests which are failing intermittently (not blocking):
test-armhf-armhf-xl-qcow2 8 xen-boot fail pass in 186043-retest
test-armhf-armhf-xl 8 xen-boot fail pass in 186043-retest
Tests which did not succeed, but are not blocking:
test-armhf-armhf-xl 15 migrate-support-check fail in 186043 never pass
test-armhf-armhf-xl 16 saverestore-support-check fail in 186043 never pass
test-armhf-armhf-xl-qcow2 14 migrate-support-check fail in 186043 never pass
test-armhf-armhf-xl-qcow2 15 saverestore-support-check fail in 186043 never pass
test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stop fail like 186036
test-amd64-amd64-xl-qemuu-win7-amd64 19 guest-stop fail like 186036
test-amd64-amd64-xl-qemuu-ws16-amd64 19 guest-stop fail like 186036
test-amd64-amd64-qemuu-nested-amd 20 debian-hvm-install/l1/l2 fail like 186036
test-amd64-amd64-xl-qemut-ws16-amd64 19 guest-stop fail like 186036
test-amd64-amd64-libvirt 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-xsm 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass
test-arm64-arm64-xl 15 migrate-support-check fail never pass
test-arm64-arm64-xl 16 saverestore-support-check fail never pass
test-arm64-arm64-libvirt-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-libvirt-xsm 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-xl-xsm 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit1 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit1 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit2 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit2 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-thunderx 15 migrate-support-check fail never pass
test-arm64-arm64-xl-thunderx 16 saverestore-support-check fail never pass
test-amd64-amd64-libvirt-qcow2 14 migrate-support-check fail never pass
test-amd64-amd64-libvirt-raw 14 migrate-support-check fail never pass
test-armhf-armhf-xl-arndale 15 migrate-support-check fail never pass
test-armhf-armhf-xl-arndale 16 saverestore-support-check fail never pass
test-amd64-amd64-libvirt-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-xl-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-xl-vhd 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-credit2 15 migrate-support-check fail never pass
test-armhf-armhf-xl-credit2 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-rtds 15 migrate-support-check fail never pass
test-armhf-armhf-libvirt-vhd 14 migrate-support-check fail never pass
test-armhf-armhf-xl-rtds 16 saverestore-support-check fail never pass
test-armhf-armhf-libvirt-vhd 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-multivcpu 15 migrate-support-check fail never pass
test-armhf-armhf-xl-multivcpu 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-credit1 15 migrate-support-check fail never pass
test-armhf-armhf-xl-credit1 16 saverestore-support-check fail never pass
test-arm64-arm64-libvirt-raw 14 migrate-support-check fail never pass
test-arm64-arm64-libvirt-raw 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-raw 14 migrate-support-check fail never pass
test-armhf-armhf-xl-raw 15 saverestore-support-check fail never pass
version targeted for testing:
linux a90f1cd105c6c5c246f07ca371d873d35b78c7d9
baseline version:
linux 25f4874662fb0d43fc1d934dd7802b740ed2ab5f
Last test of basis 186036 2024-05-18 21:13:52 Z 1 days
Failing since 186038 2024-05-19 03:51:42 Z 1 days 3 attempts
Testing same since 186041 2024-05-19 20:13:42 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
"Chen, Tim C" <tim.c.chen@intel.com>
"Huang, Ying" <ying.huang@intel.com>
"King, Colin" <colin.king@intel.com>
Adrian Hunter <adrian.hunter@intel.com>
Aleksandr Aprelkov <aaprelkov@usergate.com>
Alex Rusuf <yorha.op@gmail.com>
Alex Shi (tencent) <alexs@kernel.org>
Alex Shi <alexs@kernel.org>
Alexandre Ghiti <alexghiti@rivosinc.com
Alexei Starovoitov <ast@kernel.org>
Andrew Morton <akpm@linux-foundation.org>
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Aneesh Kumar K.V (IBM) <aneesh.kumar@kernel.org>
Arnd Bergmann <arnd@arndb.de>
Axel Rasmussen <axelrasmussen@google.com>
Baokun Li <libaokun1@huawei.com>
Baolin Wang <baolin.wang@linux.alibaba.com>
Baoquan He <bhe@redhat.com>
Barry Song <v-songbaohua@oppo.com>
Borislav Petkov (AMD) <bp@alien8.de>
Borislav Petkov <bp@suse.de>
Breno Leitao <leitao@debian.org>
Brian Geffon <bgeffon@google.com>
Catalin Marinas <catalin.marinas@arm.com>
Chang S. Bae <chang.seok.bae@intel.com>
Cheng Yu <serein.chengyu@huawei.com>
Chris Li <chrisl@kernel.org>
Christian Loehle <christian.loehle@arm.com>
Christoph Hellwig <hch@lst.de>
Christophe Leroy <christophe.leroy@csgroup.eu>
Chuck Lever <chuck.lever@oracle.com>
Colin Ian King <colin.i.king@gmail.com>
Dan Carpenter <dan.carpenter@linaro.org>
Daniel Thompson <daniel.thompson@linaro.org>
Dave Hansen <dave.hansen@linux.intel.com>
David Hildenbrand <david@redhat.com>
Dawei Li <daweilics@gmail.com>
Dennis Zhou <dennis@kernel.org>
Dev Jain <dev.jain@arm.com>
Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
Dietmar Eggemann <dietmar.eggemann@arm.com>
Disha Goel <disgoel@linux.ibm.com>
Donet Tom <donettom@linux.ibm.com>
Duoming Zhou <duoming@zju.edu.cn>
Frank van der Linden <fvdl@google.com>
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Guenter Roeck <linux@roeck-us.net>
Guoqing Jiang <guoqing.jiang@linux.dev>
Hao Ge <gehao@kylinos.cn>
Hao Xiang <hao.xiang@bytedance.com>
Hariom Panthi <hariom1.p@samsung.com>
Helge Deller <deller@gmx.de>
Helge Deller <deller@gmx.de> [parisc]
Ho-Ren (Jack) Chuang <horenchuang@bytedance.com>
Honggyu Kim <honggyu.kim@sk.com>
Huang Ying <ying.huang@intel.com>
Ingo Molnar <mingo@kernel.org>
James Houghton <jthoughton@google.com>
Jan Kara <jack@suse.cz>
Jan Kara <jack@suse.cz> [jbd2]
Jeff Layton <jlayton@kernel.org>
Jinjiang Tu <tujinjiang@huawei.com>
Joel Granados <j.granados@samsung.com>
Johannes Weiner <hannes@cmpxchg.org>
John Hubbard <jhubbard@nvidia.com>
Justin Stitt <justinstitt@google.com>
K Prateek Nayak <kprateek.nayak@amd.com>
Kairui Song <kasong@tencent.com>
Kees Cook <keescook@chromium.org>
Kefeng Wang <wangkefeng.wang@huawei.com>
Kemeng Shi <shikemeng@huaweicloud.com>
Kent Overstreet <kent.overstreet@linux.dev>
Klara Modin <klarasmodin@gmail.com>
Konrad Dybcio <konrad.dybcio@linaro.org> # QC SM8550 QRD
Lance Yang <ioworker0@gmail.com>
Len Brown <len.brown@intel.com>
Li kunyu <kunyu@nfschina.com>
Liam R. Howlett <Liam.Howlett@oracle.com>
linke li <lilinke99@qq.com>
Linus Torvalds <torvalds@linux-foundation.org>
Liu Shixin <liushixin2@huawei.com>
Long Li <leo.lilong@huawei.com>
Lorenzo Bianconi <lorenzo@kernel.org>
Lucas Stach <l.stach@pengutronix.de>
Luis Henriques <lhenriques@suse.de>
Lukas Bulwahn <lukas.bulwahn@redhat.com>
Matthew Wilcox (Oracle) <willy@infradead.org>
Matthew Wilcox <willy@infradead.org>
Max Kellermann <max.kellermann@ionos.com>
Mel Gorman <mgorman@techsingularity.net>
Miaohe Lin <linmiaohe@huawei.com>
Michael Ellerman <mpe@ellerman.id.au>
Michael Ellerman <mpe@ellerman.id.au> (powerpc)
Michael Forney <mforney@mforney.org>
Michal Hocko <mhocko@suse.com>
Miguel Ojeda <ojeda@kernel.org>
Nathan Chancellor <nathan@kernel.org>
NeilBrown <neilb@suse.de>
Nhat Pham <nphamcs@gmail.com>
Oscar Salvador <osalvador@suse.de>
Pankaj Raghav <p.raghav@samsung.com>
Patryk Wlazlyn <patryk.wlazlyn@linux.intel.com>
Peter Xu <peterx@redhat.com>
Randy Dunlap <rdunlap@infradead.org>
Rick Edgecombe <rick.p.edgecombe@intel.com>
Ritesh Harjani (IBM) <ritesh.list@gmail.com>
Roman Gushchin <roman.gushchin@linux.dev>
rulinhuang <rulin.huang@intel.com>
Ryan Roberts <ryan.roberts@arm.com>
Saurav Shah <sauravshah.31@gmail.com>
Sean Christopherson <seanjc@google.com> [KVM]
SeongJae Park <sj@kernel.org>
Sergey Senozhatsky <senozhatsky@chromium.org>
Shakeel Butt <shakeel.butt@linux.dev>
Sidhartha Kumar <sidhartha.kumar@oracle.com>
Stephen Smalley <stephen.smalley.work@gmail.com>
Steve French <stfrench@microsoft.com>
Sudeep Holla <sudeep.holla@arm.com>
Suren Baghdasaryan <surenb@google.com>
Tejun Heo <tj@kernel.org>
Theodore Ts'o <tytso@mit.edu>
Thorsten Blum <thorsten.blum@toblux.com>
Trond Myklebust <trond.myklebust@hammerspace.com>
Usama Arif <usamaarif642@gmail.com>
Vincent Guittot <vincent.guittot@linaro.org>
Vishal Moola (Oracle) <vishal.moola@gmail.com>
Vishal Verma <vishal.l.verma@intel.com>
Vitalii Bursov <vitaly@bursov.com>
Vladimir Benes <vbenes@redhat.com>
Vlastimil Babka <vbabka@suse.cz>
Waiman Long <longman@redhat.com>
Wei Yang <richard.weiyang@gmail.com>
Xiu Jianfeng <xiujianfeng@huawei.com>
Yajun Deng <yajun.deng@linux.dev>
Ye Bin <yebin10@huawei.com>
York Jasper Niebuhr <yjnworkstation@gmail.com>
Yosry Ahmed <yosryahmed@google.com>
Yu Zhao <yuzhao@google.com>
Zhang Qiao <zhangqiao22@huawei.com>
Zhang Rui <rui.zhang@intel.com>
Zhang Yi <yi.zhang@huawei.com>
ZhangPeng <zhangpeng362@huawei.com>
Zi Yan <ziy@nvidia.com>
jobs:
build-amd64-xsm pass
build-arm64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-arm64 pass
build-armhf pass
build-i386 pass
build-amd64-libvirt pass
build-arm64-libvirt pass
build-armhf-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-arm64-pvops pass
build-armhf-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl pass
test-amd64-coresched-amd64-xl pass
test-arm64-arm64-xl pass
test-armhf-armhf-xl fail
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-stubdom-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-debianhvm-i386-xsm pass
test-amd64-amd64-xl-qemuu-debianhvm-i386-xsm pass
test-amd64-amd64-libvirt-xsm pass
test-arm64-arm64-libvirt-xsm pass
test-amd64-amd64-xl-xsm pass
test-arm64-arm64-xl-xsm pass
test-amd64-amd64-qemuu-nested-amd fail
test-amd64-amd64-xl-pvhv2-amd pass
test-amd64-amd64-dom0pvh-xl-amd pass
test-amd64-amd64-xl-qemut-debianhvm-amd64 pass
test-amd64-amd64-xl-qemuu-debianhvm-amd64 pass
test-amd64-amd64-qemuu-freebsd11-amd64 pass
test-amd64-amd64-qemuu-freebsd12-amd64 pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-amd64-xl-qemut-win7-amd64 fail
test-amd64-amd64-xl-qemuu-win7-amd64 fail
test-amd64-amd64-xl-qemut-ws16-amd64 fail
test-amd64-amd64-xl-qemuu-ws16-amd64 fail
test-armhf-armhf-xl-arndale pass
test-amd64-amd64-examine-bios pass
test-amd64-amd64-xl-credit1 pass
test-arm64-arm64-xl-credit1 pass
test-armhf-armhf-xl-credit1 pass
test-amd64-amd64-xl-credit2 pass
test-arm64-arm64-xl-credit2 pass
test-armhf-armhf-xl-credit2 pass
test-amd64-amd64-xl-qemuu-dmrestrict-amd64-dmrestrict pass
test-amd64-amd64-examine pass
test-arm64-arm64-examine pass
test-armhf-armhf-examine fail
test-amd64-amd64-qemuu-nested-intel pass
test-amd64-amd64-xl-pvhv2-intel pass
test-amd64-amd64-dom0pvh-xl-intel pass
test-amd64-amd64-libvirt pass
test-armhf-armhf-libvirt fail
test-amd64-amd64-xl-multivcpu pass
test-armhf-armhf-xl-multivcpu pass
test-amd64-amd64-pair pass
test-amd64-amd64-libvirt-pair pass
test-amd64-amd64-xl-pvshim pass
test-amd64-amd64-pygrub pass
test-amd64-amd64-libvirt-qcow2 pass
test-amd64-amd64-xl-qcow2 pass
test-armhf-armhf-xl-qcow2 fail
test-amd64-amd64-libvirt-raw pass
test-arm64-arm64-libvirt-raw pass
test-amd64-amd64-xl-raw pass
test-armhf-armhf-xl-raw pass
test-amd64-amd64-xl-rtds pass
test-armhf-armhf-xl-rtds pass
test-amd64-amd64-xl-qemuu-debianhvm-amd64-shadow pass
test-amd64-amd64-xl-shadow pass
test-arm64-arm64-xl-thunderx pass
test-amd64-amd64-examine-uefi pass
test-amd64-amd64-libvirt-vhd pass
test-armhf-armhf-libvirt-vhd pass
test-amd64-amd64-xl-vhd pass
test-arm64-arm64-xl-vhd pass
------------------------------------------------------------
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
Not pushing.
(No revision log; it would be 17098 lines long.)
^ permalink raw reply [relevance 2%]
* [linux-linus test] 186036: tolerable FAIL - PUSHED
@ 2024-05-19 3:48 2% osstest service owner
0 siblings, 0 replies; 200+ results
From: osstest service owner @ 2024-05-19 3:48 UTC (permalink / raw)
To: xen-devel
flight 186036 linux-linus real [real]
http://logs.test-lab.xenproject.org/osstest/logs/186036/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stop fail like 186035
test-amd64-amd64-xl-qemuu-win7-amd64 19 guest-stop fail like 186035
test-amd64-amd64-xl-qemuu-ws16-amd64 19 guest-stop fail like 186035
test-armhf-armhf-libvirt 16 saverestore-support-check fail like 186035
test-amd64-amd64-qemuu-nested-amd 20 debian-hvm-install/l1/l2 fail like 186035
test-amd64-amd64-xl-qemut-ws16-amd64 19 guest-stop fail like 186035
test-amd64-amd64-libvirt 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-xsm 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass
test-arm64-arm64-xl 15 migrate-support-check fail never pass
test-arm64-arm64-xl 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit2 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit2 16 saverestore-support-check fail never pass
test-arm64-arm64-libvirt-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-libvirt-xsm 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-xl-xsm 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit1 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit1 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-arndale 15 migrate-support-check fail never pass
test-armhf-armhf-xl-arndale 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-thunderx 15 migrate-support-check fail never pass
test-arm64-arm64-xl-thunderx 16 saverestore-support-check fail never pass
test-amd64-amd64-libvirt-qcow2 14 migrate-support-check fail never pass
test-amd64-amd64-libvirt-raw 14 migrate-support-check fail never pass
test-amd64-amd64-libvirt-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-xl-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-xl-vhd 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-credit2 15 migrate-support-check fail never pass
test-armhf-armhf-xl-credit2 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-rtds 15 migrate-support-check fail never pass
test-armhf-armhf-xl-rtds 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-multivcpu 15 migrate-support-check fail never pass
test-armhf-armhf-xl-multivcpu 16 saverestore-support-check fail never pass
test-armhf-armhf-xl 15 migrate-support-check fail never pass
test-armhf-armhf-xl 16 saverestore-support-check fail never pass
test-armhf-armhf-libvirt 15 migrate-support-check fail never pass
test-armhf-armhf-xl-credit1 15 migrate-support-check fail never pass
test-armhf-armhf-xl-credit1 16 saverestore-support-check fail never pass
test-armhf-armhf-libvirt-vhd 14 migrate-support-check fail never pass
test-armhf-armhf-libvirt-vhd 15 saverestore-support-check fail never pass
test-arm64-arm64-libvirt-raw 14 migrate-support-check fail never pass
test-arm64-arm64-libvirt-raw 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-qcow2 14 migrate-support-check fail never pass
test-armhf-armhf-xl-qcow2 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-raw 14 migrate-support-check fail never pass
test-armhf-armhf-xl-raw 15 saverestore-support-check fail never pass
version targeted for testing:
linux 25f4874662fb0d43fc1d934dd7802b740ed2ab5f
baseline version:
linux 4b377b4868ef17b040065bd468668c707d2477a5
Last test of basis 186035 2024-05-18 13:41:54 Z 0 days
Testing same since 186036 2024-05-18 21:13:52 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
Abel Vesa <abel.vesa@linaro.org>
Aleksandr Aprelkov <aaprelkov@usergate.com>
Alexandre Mergnat <amergnat@baylibre.com>
Andrew Davis <afd@ti.com>
André Draszik <andre.draszik@linaro.org>
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Ard Biesheuvel <ardb@kernel.org>
Arnd Bergmann <arnd@arndb.de>
Babis Chalios <bchalios@amazon.es>
Bagas Sanjaya <bagasdotme@gmail.com>
Binbin Zhou <zhoubinbin@loongson.cn>
Bjorn Andersson <andersson@kernel.org>
Bob Pearson <rpearsonhpe@gmail.com>
Boshi Yu <boshiyu@linux.alibaba.com>
Breno Leitao <leitao@debian.org>
Catalin Marinas <catalin.marinas@arm.com>
Catalin Popescu <catalin.popescu@leica-geosystems.com>
Chengchang Tang <tangchengchang@huawei.com>
Chiara Meiohas <cmeiohas@nvidia.com>
Christian Marangi <ansuelsmth@gmail.com>
Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Colin Ian King <colin.i.king@gmail.com>
Cong Dang <cong.dang.xn@renesas.com>
Conor Dooley <conor.dooley@microchip.com>
Cristian Marussi <cristian.marussi@arm.com>
David Jander <david@protonic.nl>
David Rientjes <rientjes@google.com>
Dimitri Sivanich <sivanich@hpe.com>
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Dmitry Rokosov <ddrokosov@salutedevices.com>
Emil Renner Berthing <emil.renner.berthing@canonical.com>
Erick Archer <erick.archer@outlook.com>
Fabio Estevam <festevam@denx.de>
Frank Oltmanns <frank@oltmanns.dev>
Gabor Juhos <j4g8y7@gmail.com>
Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Geert Uytterhoeven <geert+renesas@glider.be>
Georgi Djakov <quic_c_gdjako@quicinc.com>
Günther Noack <gnoack@google.com>
Hanjun Guo <guohanjun@huawei.com>
Heiko Stuebner <heiko@sntech.de>
Helge Deller <deller@gmx.de>
Herman van Hazendonk <github.com@herrie.org>
Huacai Chen <chenhuacai@loongson.cn>
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Inochi Amaoto <inochiama@outlook.com>
Ivanov Mikhail <ivanov.mikhail1@huawei-partners.com>
Jaewon Kim <jaewon02.kim@samsung.com>
Jakub Kicinski <kuba@kernel.org>
Jason A. Donenfeld <Jason@zx2c4.com>
Jason Gunthorpe <jgg@nvidia.com>
Jens Axboe <axboe@kernel.dk>
Jernej Skrabec <jernej.skrabec@gmail.com>
Jerome Brunet <jbrunet@baylibre.com>
Jingqi Liu <Jingqi.liu@intel.com>
Joerg Roedel <jroedel@suse.de>
John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Jules Irenge <jbi.octave@gmail.com>
Junxian Huang <huangjunxian6@hisilicon.com>
Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Klara Modin <klarasmodin@gmail.com>
Konstantin Taranov <kotaranov@microsoft.com>
Krzysztof Kozlowski <krzk@kernel.org>
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Leon Romanovsky <leon@kernel.org>
Leon Romanovsky <leonro@nvidia.com>
Linus Torvalds <torvalds@linux-foundation.org>
Lorenzo Bianconi <lorenzo@kernel.org>
Lu Baolu <baolu.lu@linux.intel.com>
Luca Weiss <luca.weiss@fairphone.com>
Luca Weiss <luca@z3ntu.xyz>
Lucas Stach <l.stach@pengutronix.de>
Marc Gonzalez <mgonzalez@freebox.fr>
Marek Szyprowski <m.szyprowski@samsung.com>
Masahiro Yamada <masahiroy@kernel.org>
Michael Guralnik <michaelgur@nvidia.com>
Michael Margolin <mrgolin@amazon.com>
Michael Shavit <mshavit@google.com>
Michal Schmidt <mschmidt@redhat.com>
Mickaël Salaün <mic@digikod.net>
Nathan Chancellor <nathan@kernel.org>
Neil Armstrong <neil.armstrong@linaro.org>
Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Nick Desaulniers <ndesaulniers@google.com> # Boot
Nicolin Chen <nicolinc@nvidia.com>
Niklas Schnelle <schnelle@linux.ibm.com>
Nícolas F. R. A. Prado <nfraprado@collabora.com>
Or Har-Toov <ohartoov@nvidia.com>
Pasha Tatashin <pasha.tatashin@soleen.com>
Paul Barker <paul.barker.ct@bp.renesas.com>
Peng Fan <peng.fan@nxp.com>
Peter Griffin <peter.griffin@linaro.org>
Rob Herring (Arm) <robh@kernel.org>
Rob Herring <robh@kernel.org>
Roberto Sassu <roberto.sassu@huawei.com>
Robin Murphy <robin.murphy@arm.com>
Sam Protsenko <semen.protsenko@linaro.org>
Sascha Hauer <s.hauer@pengutronix.de>
Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Sebastian Reichel <sebastian.reichel@collabora.com>
Selvin Xavier <selvin.xavier@broadcom.com>
Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Shengjiu Wang <shengjiu.wang@nxp.com>
Shreeya Patel <shreeya.patel@collabora.com>
Stephen Boyd <sboyd@kernel.org>
Sudan Landge <sudanl@amazon.com>
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Thanh Le <thanh.le.xv@renesas.com>
Thanh Quan <thanh.quan.xn@renesas.com>
Thierry Reding <treding@nvidia.com>
Thomas Weißschuh <linux@weissschuh.net>
Thorsten Leemhuis <linux@leemhuis.info>
Tina Zhang <tina.zhang@intel.com>
Tudor Ambarus <tudor.ambarus@linaro.org>
Tzung-Bi Shih <tzungbi@kernel.org>
Uros Bizjak <ubizjak@gmail.com>
Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Vasant Hegde <vasant.hegde@amd.com>
Vladimir Zapolskiy <vz@mleia.com>
Wang Yao <wangyao@lemote.com>
Wei Huang <wei.huang2@amd.com>
Wei Lei <quic_leiwei@quicinc.com>
Wenchao Hao <haowenchao2@huawei.com>
wenglianfa <wenglianfa@huawei.com>
Will Deacon <will@kernel.org>
Yangyang Li <liyangyang20@huawei.com>
Yi Liu <yi.l.liu@intel.com>
Zhengchao Shao <shaozhengchao@huawei.com>
Zhengping Zhang <zhengping.zhang@airoha.com>
Zhu Yanjun <yanjun.zhu@linux.dev>
jobs:
build-amd64-xsm pass
build-arm64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-arm64 pass
build-armhf pass
build-i386 pass
build-amd64-libvirt pass
build-arm64-libvirt pass
build-armhf-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-arm64-pvops pass
build-armhf-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl pass
test-amd64-coresched-amd64-xl pass
test-arm64-arm64-xl pass
test-armhf-armhf-xl pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-stubdom-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-debianhvm-i386-xsm pass
test-amd64-amd64-xl-qemuu-debianhvm-i386-xsm pass
test-amd64-amd64-libvirt-xsm pass
test-arm64-arm64-libvirt-xsm pass
test-amd64-amd64-xl-xsm pass
test-arm64-arm64-xl-xsm pass
test-amd64-amd64-qemuu-nested-amd fail
test-amd64-amd64-xl-pvhv2-amd pass
test-amd64-amd64-dom0pvh-xl-amd pass
test-amd64-amd64-xl-qemut-debianhvm-amd64 pass
test-amd64-amd64-xl-qemuu-debianhvm-amd64 pass
test-amd64-amd64-qemuu-freebsd11-amd64 pass
test-amd64-amd64-qemuu-freebsd12-amd64 pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-amd64-xl-qemut-win7-amd64 fail
test-amd64-amd64-xl-qemuu-win7-amd64 fail
test-amd64-amd64-xl-qemut-ws16-amd64 fail
test-amd64-amd64-xl-qemuu-ws16-amd64 fail
test-armhf-armhf-xl-arndale pass
test-amd64-amd64-examine-bios pass
test-amd64-amd64-xl-credit1 pass
test-arm64-arm64-xl-credit1 pass
test-armhf-armhf-xl-credit1 pass
test-amd64-amd64-xl-credit2 pass
test-arm64-arm64-xl-credit2 pass
test-armhf-armhf-xl-credit2 pass
test-amd64-amd64-xl-qemuu-dmrestrict-amd64-dmrestrict pass
test-amd64-amd64-examine pass
test-arm64-arm64-examine pass
test-armhf-armhf-examine pass
test-amd64-amd64-qemuu-nested-intel pass
test-amd64-amd64-xl-pvhv2-intel pass
test-amd64-amd64-dom0pvh-xl-intel pass
test-amd64-amd64-libvirt pass
test-armhf-armhf-libvirt pass
test-amd64-amd64-xl-multivcpu pass
test-armhf-armhf-xl-multivcpu pass
test-amd64-amd64-pair pass
test-amd64-amd64-libvirt-pair pass
test-amd64-amd64-xl-pvshim pass
test-amd64-amd64-pygrub pass
test-amd64-amd64-libvirt-qcow2 pass
test-amd64-amd64-xl-qcow2 pass
test-armhf-armhf-xl-qcow2 pass
test-amd64-amd64-libvirt-raw pass
test-arm64-arm64-libvirt-raw pass
test-amd64-amd64-xl-raw pass
test-armhf-armhf-xl-raw pass
test-amd64-amd64-xl-rtds pass
test-armhf-armhf-xl-rtds pass
test-amd64-amd64-xl-qemuu-debianhvm-amd64-shadow pass
test-amd64-amd64-xl-shadow pass
test-arm64-arm64-xl-thunderx pass
test-amd64-amd64-examine-uefi pass
test-amd64-amd64-libvirt-vhd pass
test-armhf-armhf-libvirt-vhd pass
test-amd64-amd64-xl-vhd pass
test-arm64-arm64-xl-vhd pass
------------------------------------------------------------
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
Pushing revision :
hint: The 'hooks/update' hook was ignored because it's not set as executable.
hint: You can disable this warning with `git config advice.ignoredHook false`.
hint: The 'hooks/post-receive' hook was ignored because it's not set as executable.
hint: You can disable this warning with `git config advice.ignoredHook false`.
hint: The 'hooks/post-update' hook was ignored because it's not set as executable.
hint: You can disable this warning with `git config advice.ignoredHook false`.
To xenbits.xen.org:/home/xen/git/linux-pvops.git
4b377b4868ef..25f4874662fb 25f4874662fb0d43fc1d934dd7802b740ed2ab5f -> tested/linux-linus
^ permalink raw reply [relevance 2%]
* [linux-6.1 test] 186028: tolerable FAIL - PUSHED
@ 2024-05-17 22:27 1% osstest service owner
0 siblings, 0 replies; 200+ results
From: osstest service owner @ 2024-05-17 22:27 UTC (permalink / raw)
To: xen-devel
flight 186028 linux-6.1 real [real]
http://logs.test-lab.xenproject.org/osstest/logs/186028/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-armhf-armhf-libvirt 16 saverestore-support-check fail like 185901
test-amd64-amd64-xl-qemuu-win7-amd64 19 guest-stop fail like 185901
test-amd64-amd64-xl-qemuu-ws16-amd64 19 guest-stop fail like 185901
test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stop fail like 185901
test-amd64-amd64-xl-qemut-ws16-amd64 19 guest-stop fail like 185901
test-amd64-amd64-qemuu-nested-amd 20 debian-hvm-install/l1/l2 fail like 185901
test-arm64-arm64-xl-thunderx 15 migrate-support-check fail never pass
test-arm64-arm64-xl-thunderx 16 saverestore-support-check fail never pass
test-amd64-amd64-libvirt 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-xsm 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-qcow2 14 migrate-support-check fail never pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass
test-amd64-amd64-libvirt-raw 14 migrate-support-check fail never pass
test-amd64-amd64-libvirt-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-xl 15 migrate-support-check fail never pass
test-arm64-arm64-xl 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit2 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit2 16 saverestore-support-check fail never pass
test-arm64-arm64-libvirt-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-libvirt-xsm 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-raw 14 migrate-support-check fail never pass
test-armhf-armhf-xl-raw 15 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit1 15 migrate-support-check fail never pass
test-arm64-arm64-xl-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit1 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-xsm 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-rtds 15 migrate-support-check fail never pass
test-armhf-armhf-xl-credit2 15 migrate-support-check fail never pass
test-armhf-armhf-xl-rtds 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-credit2 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-credit1 15 migrate-support-check fail never pass
test-armhf-armhf-xl-multivcpu 15 migrate-support-check fail never pass
test-armhf-armhf-xl-credit1 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-multivcpu 16 saverestore-support-check fail never pass
test-armhf-armhf-libvirt 15 migrate-support-check fail never pass
test-armhf-armhf-xl 15 migrate-support-check fail never pass
test-armhf-armhf-xl 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-arndale 15 migrate-support-check fail never pass
test-armhf-armhf-xl-arndale 16 saverestore-support-check fail never pass
test-arm64-arm64-libvirt-raw 14 migrate-support-check fail never pass
test-arm64-arm64-libvirt-raw 15 saverestore-support-check fail never pass
test-arm64-arm64-xl-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-xl-vhd 15 saverestore-support-check fail never pass
test-armhf-armhf-libvirt-vhd 14 migrate-support-check fail never pass
test-armhf-armhf-libvirt-vhd 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-qcow2 14 migrate-support-check fail never pass
test-armhf-armhf-xl-qcow2 15 saverestore-support-check fail never pass
version targeted for testing:
linux 4078fa637fcd80c8487680ec2e4ef7c58308e9aa
baseline version:
linux 909ba1f1b4146de529469910c1bd0b1248964536
Last test of basis 185901 2024-05-02 15:12:21 Z 15 days
Testing same since 186028 2024-05-17 10:16:47 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
Adam Goldman <adamg@pobox.com>
Al Viro <viro@zeniv.linux.org.uk>
Alan Stern <stern@rowland.harvard.edu>
Aleksa Savic <savicaleksa83@gmail.com>
Alex Deucher <alexander.deucher@amd.com>
Alexander Gordeev <agordeev@linux.ibm.com>
Alexander Potapenko <glider@google.com>
Alexander Stein <alexander.stein@ew.tq-group.com>
Alexander Usyskin <alexander.usyskin@intel.com>
Alexandra Winter <wintera@linux.ibm.com>
Alexei Starovoitov <ast@kernel.org>
Allen Pais <apais@linux.microsoft.com>
Aman Dhoot <amandhoot12@gmail.com>
Amit Sunil Dhamne <amitsd@google.com>
Anand Jain <anand.jain@oracle.com>
Andrea Righi <andrea.righi@canonical.com>
Andrea Righi <andrea.righi@canonical.com> # non-hostprogs
Andreas Gruenbacher <agruenba@redhat.com>
Andrei Matei <andreimatei1@gmail.com>
Andrew Donnellan <ajd@linux.ibm.com>
Andrew Morton <akpm@linux-foundation.org>
Andrew Price <anprice@redhat.com>
Andrey Ryabinin <ryabinin.a.a@gmail.com>
Andrii Nakryiko <andrii@kernel.org>
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Anton Protopopov <aspsk@isovalent.com>
Arjan van de Ven <arjan@linux.intel.com>
Arnaldo Carvalho de Melo <acme@redhat.com>
Arnd Bergmann <arnd@arndb.de>
Asahi Lina <lina@asahilina.net>
Asbjørn Sloth Tønnesen <ast@fiberby.net>
Aurabindo Pillai <aurabindo.pillai@amd.com>
Badhri Jagan Sridharan <badhri@google.com>
Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Benno Lossin <benno.lossin@proton.me>
Billy Tsai <billy_tsai@aspeedtech.com>
Boris Burkov <boris@bur.io>
Borislav Petkov (AMD) <bp@alien8.de>
Boy Wu <boy.wu@mediatek.com>
Boy.Wu <boy.wu@mediatek.com>
Bui Quang Minh <minhquangbui99@gmail.com>
Bumyong Lee <bumyong.lee@samsung.com>
Chad Wagner <wagnerch42@gmail.com>
Chen Ni <nichen@iscas.ac.cn>
Chen-Yu Tsai <wenst@chromium.org>
Chris Wulff <chris.wulff@biamp.com>
Christian A. Ehrhardt <lk@c--e.de>
Christian König <christian.koenig@amd.com>
Christoph Paasch <cpaasch@apple.com>
Claudio Imbrenda <imbrenda@linux.ibm.com>
Conor Dooley <conor.dooley@microchip.com>
Damien Le Moal <dlemoal@kernel.org>
Dan Carpenter <dan.carpenter@linaro.org>
Daniel Borkmann <daniel@iogearbox.net>
Daniel Okazaki <dtokazaki@google.com>
Daniel Wheeler <daniel.wheeler@amd.com>
Daniel Xu <dxu@dxuuu.xyz>
David Bauer <mail@david-bauer.net>
David Lechner <dlechner@baylibre.com>
David Rientjes <rientjes@google.com>
David S. Miller <davem@davemloft.net>
David Sterba <dsterba@suse.com>
Devyn Liu <liudingyuan@huawei.com>
Dmitry Antipov <dmantipov@yandex.ru>
Dominique Martinet <dominique.martinet@atmark-techno.com>
Doug Berger <opendmb@gmail.com>
Doug Smythies <dsmythies@telus.net>
Douglas Anderson <dianders@chromium.org>
Duoming Zhou <duoming@zju.edu.cn>
Eric Curtin <ecurtin@redhat.com>
Eric Dumazet <edumazet@google.com>
Eric Van Hensbergen <ericvh@kernel.org>
Felix Fietkau <nbd@nbd.name>
Florian Fainelli <f.fainelli@gmail.com>
Florian Fainelli <florian.fainelli@broadcom.com>
Gabe Teeger <gabe.teeger@amd.com>
Gaurav Batra <gbatra@linux.ibm.com>
Geert Uytterhoeven <geert+renesas@glider.be>
George Shen <george.shen@amd.com>
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Guenter Roeck <linux@roeck-us.net>
Guillaume Nault <gnault@redhat.com>
Hans de Goede <hdegoede@redhat.com>
Heiko Carstens <hca@linux.ibm.com>
Heiner Kallweit <hkallweit1@gmail.com>
Igor Artemiev <Igor.A.Artemiev@mcst.ru>
Ivan Babrou <ivan@cloudflare.com>
Jakub Kicinski <kuba@kernel.org>
James Chapman <jchapman@katalix.com>
Jan Dakinevich <jan.dakinevich@salutedevices.com>
Jarkko Sakkinen <jarkko@kernel.org>
Jason Xing <kernelxing@tencent.com>
Javier Carrasco <javier.carrasco.cruz@gmail.com>
Jeff Johnson <quic_jjohnson@quicinc.com>
Jeff Layton <jlayton@kernel.org>
Jens Axboe <axboe@kernel.dk>
Jens Remus <jremus@linux.ibm.com>
Jeremy Bongio <jbongio@google.com>
Jernej Skrabec <jernej.skrabec@gmail.com>
Jerome Brunet <jbrunet@baylibre.com>
Jesper Dangaard Brouer <hawk@kernel.org>
Jian Shen <shenjian15@huawei.com>
Jiaxun Yang <jiaxun.yang@flygoat.com>
Jijie Shao <shaojijie@huawei.com>
Jim Cromie <jim.cromie@gmail.com>
Joakim Sindholt <opensource@zhasha.com>
Joao Paulo Goncalves <joao.goncalves@toradex.com>
Joerg Roedel <jroedel@suse.de>
Johan Hovold <johan+linaro@kernel.org>
Johannes Berg <johannes.berg@intel.com>
John Stultz <jstultz@google.com>
Jon Hunter <jonathanh@nvidia.com>
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Josef Bacik <josef@toxicpanda.com>
Julian Taylor <julian.taylor@1und1.de>
Justin Ernst <justin.ernst@hpe.com>
Justin Tee <justin.tee@broadcom.com>
Karthikeyan Ramasubramanian <kramasub@chromium.org>
Kefeng Wang <wangkefeng.wang@huawei.com>
Keith Busch <kbusch@kernel.org>
Kent Gibson <warthog618@gmail.com>
kernelci.org bot <bot@kernelci.org>
Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Krzysztof Kozlowski <krzk@kernel.org>
Kuniyuki Iwashima <kuniyu@amazon.com>
Lakshmi Yadlapati <lakshmiy@us.ibm.com>
Leah Rumancik <leah.rumancik@gmail.com>
Len Brown <len.brown@intel.com>
Li Nan <linan122@huawei.com>
Li Zetao <lizetao1@huawei.com>
Lijo Lazar <lijo.lazar@amd.com>
linke li <lilinke99@qq.com>
Linus Torvalds <torvalds@linux-foundation.org>
Linus Walleij <linus.walleij@linaro.org>
Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Lukasz Majewski <lukma@denx.de>
Lyude Paul <lyude@redhat.com>
Maarten Vanraes <maarten@rmail.be>
Mans Rullgard <mans@mansr.com>
Marc Zyngier <maz@kernel.org>
Marek Behún <kabel@kernel.org>
Marek Vasut <marex@denx.de>
Mario Limonciello <mario.limonciello@amd.com>
Marius Zachmann <mail@mariuszachmann.de>
Mark Brown <broonie@kernel.org>
Martin K. Petersen <martin.petersen@oracle.com>
Martin KaFai Lau <martin.lau@kernel.org>
Martin Rodriguez Reboredo <yakoyoku@gmail.com>
Masahiro Yamada <masahiroy@kernel.org>
Matthieu Baerts (NGI0) <matttbe@kernel.org>
Matti Vaittinen <mazziesaccount@gmail.com>
Maurizio Lombardi <mlombard@redhat.com>
Maxime Ripard <mripard@kernel.org>
Miaohe Lin <linmiaohe@huawei.com>
Michael Ellerman <mpe@ellerman.id.au>
Michael Kelley <mhklinux@outlook.com>
Miguel Ojeda <ojeda@kernel.org>
Mika Westerberg <mika.westerberg@linux.intel.com>
Mike Kravetz <mike.kravetz@oracle.com>
Mike Rapoport (IBM) <rppt@kernel.org>
Nageswara R Sastry <rnsastry@linux.ibm.com>
Namhyung Kim <namhyung@kernel.org>
Namjae Jeon <linkinjeon@kernel.org>
Nayna Jain <nayna@linux.ibm.com>
Neal Cardwell <ncardwell@google.com>
Neil Armstrong <neil.armstrong@linaro.org>
Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Nikhil Rao <nikhil.rao@intel.com>
Nikolay Aleksandrov <razor@blackwall.org>
Nilesh Javali <njavali@marvell.com>
Oliver Upton <oliver.upton@linux.dev>
Oscar Salvador <osalvador@suse.de>
Paolo Abeni <pabeni@redhat.com>
Paul Davey <paul.davey@alliedtelesis.co.nz>
Paul Menzel <pmenzel@molgen.mpg.de> # Dell XPS 13
Pavel Machek (CIP) <pavel@denx.de>
Peiyang Wang <wangpeiyang1@huawei.com>
Peng Liu <liupeng17@lenovo.com>
Peter Korsgaard <peter@korsgaard.com>
Peter Ujfalusi <peter.ujfalusi@gmail.com>
Peter Wang <peter.wang@mediatek.com>
Peter Xu <peterx@redhat.com>
Phil Elwell <phil@raspberrypi.com>
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Qu Wenruo <wqu@suse.com>
Ramona Gradinariu <ramona.bolboaca13@gmail.com>
Raphael Nestler <raphael.nestler@gmail.com> # non-hostprogs
Richard Gobert <richardbgobert@gmail.com>
Rick Edgecombe <rick.p.edgecombe@intel.com>
Rik van Riel <riel@surriel.com>
Roded Zats <rzats@paloaltonetworks.com>
Rodrigo Vivi <rodrigo.vivi@intel.com>
Ron Economos <re@w6rz.net>
Ronald Wahl <ronald.wahl@raritan.com> # KS8851 SPI
Russell Currey <ruscur@russell.cc>
Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Rémi Denis-Courmont <courmisch@gmail.com>
Salvatore Bonaccorso <carnil@debian.org>
Sameer Pujar <spujar@nvidia.com>
Sasha Levin <sashal@kernel.org>
Saurav Kashyap <skashyap@marvell.com>
Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Sebastian Reichel <sebastian.reichel@collabora.com>
SeongJae Park <sj@kernel.org>
Shin'ichiro Kawasaki <shinichiro.kawasaki@wdc.com>
Shuah Khan <skhan@linuxfoundation.org>
Shyam Prasad N <sprasad@microsoft.com>
Sidhartha Kumar <sidhartha.kumar@oracle.com>
Silvio Gissi <sifonsec@amazon.com>
Song Liu <song@kernel.org>
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Stanislav Fomichev <sdf@google.com>
Steffen Klassert <steffen.klassert@secunet.com>
Stephen Boyd <sboyd@kernel.org>
Steve French <stfrench@microsoft.com>
Sungwoo Kim <iam@sung-woo.kim>
Takashi Iwai <tiwai@suse.de>
Takashi Sakamoto <o-takashi@sakamocchi.jp>
Tejun Heo <tj@kernel.org>
Thadeu Lima de Souza Cascardo <cascardo@igalia.com>
Thanassis Avgerinos <thanassis.avgerinos@gmail.com>
Thierry Reding <treding@nvidia.com>
Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Thomas Bertschinger <tahbertschinger@gmail.com>
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Gleixner <tglx@linutronix.de>
Tim Jiang <quic_tjiang@quicinc.com>
Toke Høiland-Jørgensen <toke@redhat.com>
Tomas Winkler <tomas.winkler@intel.com>
Tony Luck <tony.luck@intel.com>
Trond Myklebust <trond.myklebust@hammerspace.com>
Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Vanillan Wang <vanillanwang@163.com>
Viken Dadhaniya <quic_vdadhani@quicinc.com>
Ville Syrjälä <ville.syrjala@linux.intel.com>
Vinod Koul <vkoul@kernel.org>
Vlastimil Babka <vbabka@suse.cz>
Wedson Almeida Filho <walmeida@microsoft.com>
Wei Liu <wei.liu@kernel.org>
Wei Yang <richard.weiyang@gmail.com>
Wen Gu <guwen@linux.alibaba.com>
Wyes Karny <wyes.karny@amd.com>
Xin Long <lucien.xin@gmail.com>
Xu Kuohai <xukuohai@huawei.com>
Yang Yingliang <yangyingliang@huawei.com>
Yann Sionneau <ysionneau@kalrayinc.com>
Yann Sionneau<ysionneau@kalrayinc.com>
Yi Zhang <yi.zhang@redhat.com>
Yonglong Liu <liuyonglong@huawei.com>
Zack Rusin <zack.rusin@broadcom.com>
Zeng Heng <zengheng4@huawei.com>
jobs:
build-amd64-xsm pass
build-arm64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-arm64 pass
build-armhf pass
build-i386 pass
build-amd64-libvirt pass
build-arm64-libvirt pass
build-armhf-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-arm64-pvops pass
build-armhf-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl pass
test-amd64-coresched-amd64-xl pass
test-arm64-arm64-xl pass
test-armhf-armhf-xl pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-stubdom-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-debianhvm-i386-xsm pass
test-amd64-amd64-xl-qemuu-debianhvm-i386-xsm pass
test-amd64-amd64-libvirt-xsm pass
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test-amd64-amd64-qemuu-nested-amd fail
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------------------------------------------------------------
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^ permalink raw reply [relevance 1%]
* [GIT PULL] clk changes for the merge window
@ 2024-05-17 1:31 3% Stephen Boyd
0 siblings, 0 replies; 200+ results
From: Stephen Boyd @ 2024-05-17 1:31 UTC (permalink / raw)
To: Linus Torvalds; +Cc: Michael Turquette, linux-clk, linux-kernel
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 24587 bytes --]
The following changes since commit 01aea123b11c7ebbdd64b2df3a4a5a7ad86a460d:
dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit (2024-04-29 19:06:57 +0200)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git tags/clk-for-linus
for you to fetch changes up to 03be434863b9606435be9ef43651d4c0cbbe6788:
Merge branches 'clk-microchip', 'clk-samsung' and 'clk-qcom' into clk-next (2024-05-16 18:09:14 -0700)
----------------------------------------------------------------
I'm actually surprised this time. There aren't any new Qualcomm SoC clk
drivers. And there's zero diff in the core clk framework. Instead we have new
clk drivers for STM and Sophgo, with Samsung^WGoogle in third for the diffstat
because they introduced HSI0 and HSI2 clk drivers for Google's GS101 SoC (high
speed interface things like PCIe, UFS, and MMC). Beyond those big diffs there's
the usual updates to various clk drivers for incorrect parent descriptions or
mising MODULE_DEVICE_TABLE()s, etc. Nothing in particular stands out as super
interesting here.
New Drivers:
- STM32MP257 SoC clk driver
- Airoha EN7581 SoC clk driver
- Sophgo CV1800B, CV1812H and SG2000 SoC clk driver
- Loongson-2k0500 and Loongson-2k2000 SoC clk driver
- Add HSI0 and HSI2 clock controllers for Google GS101
- Add i.MX95 BLK CTL clock driver
Updates:
- Allocate clk_ops dynamically for SCMI clk driver
- Add support in qcom RCG and RCG2 for multiple configurations for the same frequency
- Use above support for IPQ8074 NSS port 5 and 6 clocks to resolve issues
- Fix the Qualcomm APSS IPQ5018 PLL to fix boot failures of some boards
- Cleanups and fixes for Qualcomm Stromer PLLs
- Reduce max CPU frequency on Qualcomm APSS IPQ5018
- Fix Kconfig dependencies of Qualcomm SM8650 GPU and SC8280XP camera
clk drivers
- Make Qualcomm MSM8998 Venus clocks functional
- Cleanup downstream remnants related to DisplayPort across Qualcomm
SM8450, SM6350, SM8550, and SM8650
- Reuse the Huayra APSS register map on Qualcomm MSM8996 CBF PLL
- Use a specific Qualcomm QCS404 compatible for the otherwise generic
HFPLL
- Remove Qualcomm SM8150 CPUSS AHB clk as it is unused
- Remove an unused field in the Qualcomm RPM clk driver
- Add missing MODULE_DEVICE_TABLE to Qualcomm MSM8917 and MSM8953
global clock controller drivers
- Allow choice of manual or firmware-driven control over PLLs, needed
to fully implement CPU clock controllers on Exynos850
- Correct PLL clock IDs on ExynosAutov9
- Propagate certain clock rates to allow setting proper SPI clock
rates on Google GS101
- Mark certain Google GS101 clocks critical
- Convert old S3C64xx clock controller bindings to DT schema
- Add new PLL rate and missing mux on Rockchip rk3568
- Add missing reset line on Rockchip rk3588
- Removal of an unused field in struct rockchip_mmc_clock
- Amlogic s4/a1: add regmap maximum register for proper debugfs dump
- Amlogic s4: add MODULE_DEVICE_TABLE() on pll and periph controllers
- Amlogic pll driver: print clock name on lock error to help debug
- Amlogic vclk: finish dsi clock path support
- Amlogic license: fix occurence "GPL v2" as reported by checkpatch
- Add PM runtime support to i.MX8MP Audiomix
- Add DT schema for i.MX95 Display Master Block Control
- Convert to platform remove callback returning void for i.MX8MP
Audiomix
- Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on Renesas R-Car V4M
- Add interrupt controller (PLIC) clock and reset on Renesas RZ/Five
- Prepare power domain support for Renesas RZ/G2L family members, and add
actual support on Renesas RZ/G3S SoC
- Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on Renesas R-Car V4M
- Add additional constraints to Allwinner A64 PLL MIPI clock
- Fix autoloading sunxi-ng clocks when build as a module
----------------------------------------------------------------
Abel Vesa (1):
clk: qcom: clk-alpha-pll: Skip reconfiguring the running Lucid Evo
Alexandre Mergnat (1):
clk: mediatek: mt8365-mm: fix DPI0 parent
André Draszik (2):
clk: samsung: gs101: add support for cmu_hsi0
clk: samsung: gs101: mark some apm UASC and XIU clocks critical
Arnd Bergmann (2):
clk: ti: dpll: fix incorrect #ifdef checks
clk: sophgo: avoid open-coded 64-bit division
Binbin Zhou (6):
dt-bindings: clock: Add Loongson-2K expand clock index
clk: clk-loongson2: Refactor driver for adding new platforms
dt-bindings: clock: loongson2: Add Loongson-2K0500 compatible
clk: clk-loongson2: Add Loongson-2K0500 clock support
dt-bindings: clock: loongson2: Add Loongson-2K2000 compatible
clk: clk-loongson2: Add Loongson-2K2000 clock support
Bjorn Andersson (1):
Merge branch '20240315-apss-ipq-pll-ipq5018-hang-v2-1-6fe30ada2009@gmail.com' into clk-for-6.10
Catalin Popescu (1):
clk: rs9: fix wrong default value for clock amplitude
Christian Marangi (3):
clk: qcom: clk-rcg: introduce support for multiple conf for same freq
clk: qcom: clk-rcg2: add support for rcg2 freq multi ops
clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf
Christophe JAILLET (6):
clk: nxp: Remove an unused field in struct lpc18xx_pll
clk: highbank: Remove an unused field in struct hb_clk
clk: gemini: Remove an unused field in struct clk_gemini_pci
clk: qcom: rpm: Remove an unused field in struct rpm_cc
clk: renesas: r8a7740: Remove unused div4_clk.flags field
clk: rockchip: Remove an unused field in struct rockchip_mmc_clock
Claudiu Beznea (7):
dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
dt-bindings: clock: r9a07g044-cpg: Add power domain IDs
dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
dt-bindings: clock: r9a08g045-cpg: Add power domain IDs
dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S
clk: renesas: rzg2l: Extend power domain support
clk: renesas: r9a08g045: Add support for power domains
Cong Dang (2):
clk: renesas: r8a779h0: Add MSIOF clocks
clk: renesas: r8a779h0: Add INTC-EX clock
Conor Dooley (2):
clock, reset: microchip: move all mpfs reset code to the reset subsystem
clk, reset: microchip: mpfs: fix incorrect preprocessor conditions
Cristian Marussi (5):
clk: scmi: Allocate CLK operations dynamically
clk: scmi: Add support for state control restricted clocks
clk: scmi: Add support for rate change restricted clocks
clk: scmi: Add support for re-parenting restricted clocks
clk: scmi: Add support for get/set duty_cycle operations
David Jander (1):
clk: rockchip: rk3568: Add missing USB480M_PHY mux
Dmitry Baryshkov (4):
clk: qcom: dispcc-sm8450: fix DisplayPort clocks
clk: qcom: dispcc-sm6350: fix DisplayPort clocks
clk: qcom: dispcc-sm8550: fix DisplayPort clocks
clk: qcom: dispcc-sm8650: fix DisplayPort clocks
Dmitry Rokosov (5):
clk: meson: a1: peripherals: determine maximum register in regmap config
clk: meson: a1: pll: determine maximum register in regmap config
clk: meson: s4: peripherals: determine maximum register in regmap config
clk: meson: s4: pll: determine maximum register in regmap config
clk: meson: pll: print out pll name when unable to lock it
Fabio Estevam (1):
clk: imx: imx8mp: Switch to RUNTIME_PM_OPS()
Frank Oltmanns (2):
clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rate
clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate
Gabor Juhos (11):
clk: qcom: clk-alpha-pll: remove invalid Stromer register offset
clk: qcom: clk-alpha-pll: reorder Stromer register offsets
clk: qcom: clk-alpha-pll: fix kerneldoc of struct clk_alpha_pll
clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure
clk: qcom: apss-ipq-pll: reuse Stromer reg offsets from 'clk_alpha_pll_regs'
clk: qcom: apss-ipq-pll: move Huayra register map to 'clk_alpha_pll_regs'
clk: qcom: apss-ipq-pll: constify match data structures
clk: qcom: apss-ipq-pll: constify clk_init_data structures
clk: qcom: clk-cbf-8996: use HUAYRA_APSS register map for cbf_pll
clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs
Gabriel Fernandez (4):
clk: stm32mp13: use platform device APIs
dt-bindings: clocks: stm32mp25: add description of all parents
clk: stm32: introduce clocks for STM32MP257 platform
dt-bindings: clocks: stm32mp25: add access-controllers description
Geert Uytterhoeven (5):
dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks
clk: renesas: r8a779h0: Add thermal clock
clk: renesas: r8a779h0: Add SCIF clocks
clk: renesas: r8a779a0: Fix CANFD parent clock
clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT
Heiko Stuebner (1):
Merge branch 'v6.10-shared/clkids' into v6.10-clk/next
Inochi Amaoto (5):
dt-bindings: clock: sophgo: Add clock controller of SG2000 series SoC
clk: sophgo: Add clock support for CV1800 SoC
clk: sophgo: Add clock support for CV1810 SoC
clk: sophgo: Add clock support for SG2000 SoC
clk: sophgo: Make synthesizer struct static
Jaewon Kim (1):
clk: samsung: exynosautov9: fix wrong pll clock id value
Krzysztof Kozlowski (6):
dt-bindings: clock: samsung,s3c6400-clock: convert to DT Schema
clk: qcom: fix module autoloading
clk: sunxi-ng: fix module autoloading
Merge branch 'for-v6.10/clk-gs101-bindings' into next/clk
clk: meson: s4: fix module autoloading
clk: samsung: gs101: drop unused HSI2 clock parent data
Lad Prabhakar (1):
clk: renesas: r9a07g043: Add clock and reset entry for PLIC
Lorenzo Bianconi (3):
dt-bindings: clock: airoha: add EN7581 binding
clk: en7523: Add en_clk_soc_data data structure
clk: en7523: Add EN7581 support
Luca Weiss (2):
dt-bindings: clock: qcom,hfpll: Convert to YAML
clk: qcom: hfpll: Add QCS404-specific compatible
Lucas Stach (1):
clk: rockchip: rk3568: Add PLL rate for 724 MHz
Marc Gonzalez (1):
clk: qcom: mmcc-msm8998: fix venus clock issue
Marek Szyprowski (1):
clk: samsung: Don't register clkdev lookup for the fixed rate clocks
Nathan Chancellor (4):
clk: bcm: dvp: Assign ->num before accessing ->hws
clk: bcm: rpi: Assign ->num before accessing ->hws
clk: qcom: Fix SC_CAMCC_8280XP dependencies
clk: qcom: Fix SM_GPUCC_8650 dependencies
Neil Armstrong (3):
clk: meson: add vclk driver
clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF
clk: meson: fix module license to GPL only
Nícolas F. R. A. Prado (1):
clk: mediatek: pllfh: Don't log error for missing fhctl node
Paul Barker (2):
clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const
clk: renesas: r9a07g044: Mark resets array as const
Peng Fan (4):
dt-bindings: clock: add i.MX95 clock header
dt-bindings: clock: support i.MX95 BLK CTL module
dt-bindings: clock: support i.MX95 Display Master CSR module
clk: imx: add i.MX95 BLK CTL clk driver
Peter Griffin (1):
clk: samsung: gs101: add support for cmu_hsi2
Rob Herring (Arm) (1):
dt-bindings: clock: fixed: Define a preferred node name
Sam Protsenko (2):
clk: samsung: Implement manual PLL control for ARM64 SoCs
clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1
Sascha Hauer (1):
dt-bindings: clock: rockchip: add USB480M_PHY mux
Satya Priya Kakitapalli (1):
clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src
Shengjiu Wang (1):
clk: imx: imx8mp: Add pm_runtime support for power saving
Shreeya Patel (2):
dt-bindings: reset: Define reset id used for HDMI Receiver
clk: rockchip: rk3588: Add reset line for HDMI Receiver
Stephen Boyd (12):
Merge tag 'renesas-clk-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Merge tag 'sunxi-clk-for-6.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Merge tag 'renesas-clk-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Merge tag 'clk-imx-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Merge tag 'clk-meson-v6.10-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Merge tag 'v6.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Merge tag 'samsung-clk-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Merge tag 'qcom-clk-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Merge branches 'clk-cleanup', 'clk-airoha', 'clk-mediatek', 'clk-sophgo' and 'clk-loongson' into clk-next
Merge branches 'clk-stm', 'clk-renesas', 'clk-scmi' and 'clk-allwinner' into clk-next
Merge branches 'clk-counted', 'clk-imx', 'clk-amlogic', 'clk-binding' and 'clk-rockchip' into clk-next
Merge branches 'clk-microchip', 'clk-samsung' and 'clk-qcom' into clk-next
Thanh Quan (1):
clk: renesas: r8a779h0: Add timer clocks
Tudor Ambarus (2):
clk: samsung: gs101: propagate PERIC0 USI SPI clock rate
clk: samsung: gs101: propagate PERIC1 USI SPI clock rate
Uwe Kleine-König (1):
clk: imx: imx8mp: Convert to platform remove callback returning void
.../bindings/clock/airoha,en7523-scu.yaml | 31 +-
.../devicetree/bindings/clock/fixed-clock.yaml | 9 +
.../bindings/clock/fixed-factor-clock.yaml | 9 +
.../bindings/clock/loongson,ls2k-clk.yaml | 4 +-
.../bindings/clock/nxp,imx95-blk-ctl.yaml | 56 +
.../clock/nxp,imx95-display-master-csr.yaml | 64 +
.../devicetree/bindings/clock/qcom,hfpll.txt | 63 -
.../devicetree/bindings/clock/qcom,hfpll.yaml | 69 +
.../bindings/clock/renesas,rzg2l-cpg.yaml | 18 +-
.../bindings/clock/samsung,s3c6400-clock.yaml | 57 +
.../bindings/clock/samsung,s3c64xx-clock.txt | 76 -
.../bindings/clock/sophgo,cv1800-clk.yaml | 3 +-
.../bindings/clock/st,stm32mp25-rcc.yaml | 172 +-
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/bcm/clk-bcm2711-dvp.c | 3 +-
drivers/clk/bcm/clk-raspberrypi.c | 2 +-
drivers/clk/clk-en7523.c | 191 +-
drivers/clk/clk-gemini.c | 2 -
drivers/clk/clk-highbank.c | 1 -
drivers/clk/clk-loongson2.c | 584 +++---
drivers/clk/clk-renesas-pcie.c | 10 +-
drivers/clk/clk-scmi.c | 249 ++-
drivers/clk/imx/Kconfig | 7 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx8mp-audiomix.c | 155 +-
drivers/clk/imx/clk-imx95-blk-ctl.c | 438 +++++
drivers/clk/mediatek/clk-mt8365-mm.c | 2 +-
drivers/clk/mediatek/clk-pllfh.c | 2 +-
drivers/clk/meson/Kconfig | 5 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/a1-peripherals.c | 1 +
drivers/clk/meson/a1-pll.c | 1 +
drivers/clk/meson/axg-aoclk.c | 2 +-
drivers/clk/meson/axg-audio.c | 2 +-
drivers/clk/meson/axg.c | 2 +-
drivers/clk/meson/clk-cpu-dyndiv.c | 2 +-
drivers/clk/meson/clk-dualdiv.c | 2 +-
drivers/clk/meson/clk-mpll.c | 2 +-
drivers/clk/meson/clk-phase.c | 2 +-
drivers/clk/meson/clk-pll.c | 6 +-
drivers/clk/meson/clk-regmap.c | 2 +-
drivers/clk/meson/g12a-aoclk.c | 2 +-
drivers/clk/meson/g12a.c | 78 +-
drivers/clk/meson/gxbb-aoclk.c | 2 +-
drivers/clk/meson/gxbb.c | 2 +-
drivers/clk/meson/meson-aoclk.c | 2 +-
drivers/clk/meson/meson-eeclk.c | 2 +-
drivers/clk/meson/s4-peripherals.c | 2 +
drivers/clk/meson/s4-pll.c | 2 +
drivers/clk/meson/sclk-div.c | 2 +-
drivers/clk/meson/vclk.c | 141 ++
drivers/clk/meson/vclk.h | 51 +
drivers/clk/meson/vid-pll-div.c | 2 +-
drivers/clk/microchip/clk-mpfs.c | 92 +-
drivers/clk/nxp/clk-lpc18xx-cgu.c | 1 -
drivers/clk/qcom/Kconfig | 2 +
drivers/clk/qcom/apss-ipq-pll.c | 79 +-
drivers/clk/qcom/clk-alpha-pll.c | 24 +-
drivers/clk/qcom/clk-alpha-pll.h | 5 +-
drivers/clk/qcom/clk-cbf-8996.c | 13 +-
drivers/clk/qcom/clk-rcg.h | 24 +-
drivers/clk/qcom/clk-rcg2.c | 166 ++
drivers/clk/qcom/clk-rpm.c | 1 -
drivers/clk/qcom/common.c | 18 +
drivers/clk/qcom/common.h | 2 +
drivers/clk/qcom/dispcc-sm6350.c | 11 +-
drivers/clk/qcom/dispcc-sm8450.c | 20 +-
drivers/clk/qcom/dispcc-sm8550.c | 20 +-
drivers/clk/qcom/dispcc-sm8650.c | 20 +-
drivers/clk/qcom/gcc-ipq8074.c | 120 +-
drivers/clk/qcom/gcc-msm8917.c | 1 +
drivers/clk/qcom/gcc-msm8953.c | 1 +
drivers/clk/qcom/gcc-sm8150.c | 61 -
drivers/clk/qcom/hfpll.c | 6 +-
drivers/clk/qcom/mmcc-msm8998.c | 8 +
drivers/clk/renesas/clk-r8a73a4.c | 2 -
drivers/clk/renesas/clk-r8a7740.c | 27 +-
drivers/clk/renesas/clk-sh73a0.c | 2 -
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a779h0-cpg-mssr.c | 21 +
drivers/clk/renesas/r9a07g043-cpg.c | 13 +-
drivers/clk/renesas/r9a07g044-cpg.c | 2 +-
drivers/clk/renesas/r9a08g045-cpg.c | 41 +
drivers/clk/renesas/rzg2l-cpg.c | 199 ++-
drivers/clk/renesas/rzg2l-cpg.h | 67 +
drivers/clk/rockchip/clk-mmc-phase.c | 1 -
drivers/clk/rockchip/clk-rk3568.c | 5 +
drivers/clk/rockchip/rst-rk3588.c | 1 +
drivers/clk/samsung/clk-exynos-arm64.c | 56 +-
drivers/clk/samsung/clk-exynos850.c | 440 ++++-
drivers/clk/samsung/clk-exynosautov9.c | 8 +-
drivers/clk/samsung/clk-gs101.c | 1192 +++++++++++--
drivers/clk/samsung/clk.c | 11 +-
drivers/clk/samsung/clk.h | 15 +-
drivers/clk/sophgo/Kconfig | 11 +
drivers/clk/sophgo/Makefile | 7 +
drivers/clk/sophgo/clk-cv1800.c | 1537 ++++++++++++++++
drivers/clk/sophgo/clk-cv1800.h | 123 ++
drivers/clk/sophgo/clk-cv18xx-common.c | 66 +
drivers/clk/sophgo/clk-cv18xx-common.h | 81 +
drivers/clk/sophgo/clk-cv18xx-ip.c | 887 +++++++++
drivers/clk/sophgo/clk-cv18xx-ip.h | 261 +++
drivers/clk/sophgo/clk-cv18xx-pll.c | 419 +++++
drivers/clk/sophgo/clk-cv18xx-pll.h | 118 ++
drivers/clk/stm32/Kconfig | 7 +
drivers/clk/stm32/Makefile | 1 +
drivers/clk/stm32/clk-stm32-core.c | 11 +-
drivers/clk/stm32/clk-stm32mp13.c | 72 +-
drivers/clk/stm32/clk-stm32mp25.c | 1875 ++++++++++++++++++++
drivers/clk/stm32/reset-stm32.c | 59 +-
drivers/clk/stm32/reset-stm32.h | 7 +
drivers/clk/stm32/stm32mp25_rcc.h | 712 ++++++++
drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c | 1 +
drivers/clk/sunxi-ng/ccu-sun20i-d1.c | 1 +
drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 1 +
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 1 +
drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 1 +
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 13 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 1 +
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 1 +
drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1 +
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 1 +
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 1 +
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 1 +
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c | 1 +
drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 1 +
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 1 +
drivers/clk/sunxi-ng/ccu_nkm.c | 21 +
drivers/clk/sunxi-ng/ccu_nkm.h | 2 +
drivers/clk/ti/dpll.c | 10 +-
drivers/reset/reset-mpfs.c | 95 +-
include/dt-bindings/clock/loongson,ls2k-clk.h | 54 +-
include/dt-bindings/clock/nxp,imx95-clock.h | 28 +
include/dt-bindings/clock/r9a07g043-cpg.h | 58 +-
include/dt-bindings/clock/r9a07g044-cpg.h | 58 +
include/dt-bindings/clock/r9a07g054-cpg.h | 58 +
include/dt-bindings/clock/r9a08g045-cpg.h | 70 +
include/dt-bindings/clock/rk3568-cru.h | 1 +
include/dt-bindings/reset/rockchip,rk3588-cru.h | 2 +
include/dt-bindings/reset/st,stm32mp25-rcc.h | 2 +-
include/soc/microchip/mpfs.h | 10 +-
150 files changed, 10956 insertions(+), 1200 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
create mode 100644 Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.yaml
create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c6400-clock.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
create mode 100644 drivers/clk/imx/clk-imx95-blk-ctl.c
create mode 100644 drivers/clk/meson/vclk.c
create mode 100644 drivers/clk/meson/vclk.h
create mode 100644 drivers/clk/sophgo/Kconfig
create mode 100644 drivers/clk/sophgo/Makefile
create mode 100644 drivers/clk/sophgo/clk-cv1800.c
create mode 100644 drivers/clk/sophgo/clk-cv1800.h
create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.c
create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.h
create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.c
create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.h
create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.c
create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.h
create mode 100644 drivers/clk/stm32/clk-stm32mp25.c
create mode 100644 drivers/clk/stm32/stm32mp25_rcc.h
create mode 100644 include/dt-bindings/clock/nxp,imx95-clock.h
--
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git
^ permalink raw reply [relevance 3%]
* [tip: sched/urgent] arch/topology: Fix variable naming to avoid shadowing
2024-04-30 12:19 4% ` Konrad Dybcio
@ 2024-05-15 8:27 4% ` tip-bot2 for Vincent Guittot
1 sibling, 0 replies; 200+ results
From: tip-bot2 for Vincent Guittot @ 2024-05-15 8:27 UTC (permalink / raw)
To: linux-tip-commits
Cc: kernel test robot, Vincent Guittot, Ingo Molnar, Lukasz Luba,
Konrad Dybcio, Sudeep Holla, Linus Torvalds, x86, linux-kernel
The following commit has been merged into the sched/urgent branch of tip:
Commit-ID: e5bc44e47c531860be96ac615314b1ab23d5aa2b
Gitweb: https://git.kernel.org/tip/e5bc44e47c531860be96ac615314b1ab23d5aa2b
Author: Vincent Guittot <vincent.guittot@linaro.org>
AuthorDate: Thu, 25 Apr 2024 09:37:09 +02:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Wed, 15 May 2024 10:22:16 +02:00
arch/topology: Fix variable naming to avoid shadowing
Using 'hw_pressure' for local variable name is confusing in regard to the
per-CPU 'hw_pressure' variable that uses the same name:
include/linux/arch_topology.h:DECLARE_PER_CPU(unsigned long, hw_pressure);
... which puts it into a global scope for all code that includes
<linux/topology.h>, shadowing the local variable.
Rename it to avoid compiler confusion & Sparse warnings.
[ mingo: Expanded the changelog. ]
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/20240425073709.379016-1-vincent.guittot@linaro.org
Closes: https://lore.kernel.org/oe-kbuild-all/202404250740.VhQQoD7N-lkp@intel.com/
Fixes: d4dbc991714e ("sched/cpufreq: Rename arch_update_thermal_pressure() => arch_update_hw_pressure()")
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # QC SM8550 QRD
---
drivers/base/arch_topology.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
index 0248912..c66d070 100644
--- a/drivers/base/arch_topology.c
+++ b/drivers/base/arch_topology.c
@@ -179,7 +179,7 @@ DEFINE_PER_CPU(unsigned long, hw_pressure);
void topology_update_hw_pressure(const struct cpumask *cpus,
unsigned long capped_freq)
{
- unsigned long max_capacity, capacity, hw_pressure;
+ unsigned long max_capacity, capacity, pressure;
u32 max_freq;
int cpu;
@@ -196,12 +196,12 @@ void topology_update_hw_pressure(const struct cpumask *cpus,
else
capacity = mult_frac(max_capacity, capped_freq, max_freq);
- hw_pressure = max_capacity - capacity;
+ pressure = max_capacity - capacity;
- trace_hw_pressure_update(cpu, hw_pressure);
+ trace_hw_pressure_update(cpu, pressure);
for_each_cpu(cpu, cpus)
- WRITE_ONCE(per_cpu(hw_pressure, cpu), hw_pressure);
+ WRITE_ONCE(per_cpu(hw_pressure, cpu), pressure);
}
EXPORT_SYMBOL_GPL(topology_update_hw_pressure);
^ permalink raw reply related [relevance 4%]
* [PATCH 1/1] Squashed 'dts/upstream/' changes from b35b9bd1d4ee..7e08733c96c8
@ 2024-05-14 16:42 4% Tom Rini
0 siblings, 0 replies; 200+ results
From: Tom Rini @ 2024-05-14 16:42 UTC (permalink / raw)
To: u-boot
Cc: Adam Ford, Apurva Nandan, Beniamino Galvani, Biju Das,
Bryan Brattlof, Caleb Connolly, Christian Hewitt,
Cogent Embedded, Inc.,
Dave Purdy, Evgeni Dobrev, Fabio Estevam, Jason Cooper,
Jorge Ramirez-Ortiz, Lad Prabhakar, Luka Perkov, Marcel Ziswiler,
Marek Vasut, Masakazu Mochizuki, Michael Walle, Neil Armstrong,
Nobuhiro Iwamatsu, Paul Barker, Peng Fan, Ramon Fried,
Siddarth Gore, Simon Guinot, Stefan Herbrechtsmeier,
Stefan Roese, Sumit Garg, Tim Harvey, Tony Dinh,
Vignesh Raghavendra, Vyacheslav Bocharov, Wadim Egorov,
Walter Schweizer, u-boot-amlogic, u-boot-qcom
7e08733c96c8 Merge tag 'v6.9-dts-raw'
ccdce3340fc5 Merge tag 'net-6.9-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
cb4ccb79bf49 dt-bindings: net: mediatek: remove wrongly added clocks and SerDes
6bd14595bb37 Merge tag 'soc-fixes-6.9-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
a6d12fb4ba6f Merge tag 'qcom-arm64-fixes-for-6.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
71c2fe626e53 Merge tag 'v6.9-rc7-dts-raw'
62d74bd1c58f Merge tag 'char-misc-6.9-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
bdc631c5b7eb arm64: dts: mediatek: mt8183-pico6: Fix bluetooth node
9818a367c6b8 Merge tag 'sound-6.9-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
c861ae2b0770 Merge tag 'pinctrl-v6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
c9551dbd4ea4 Merge tag 'v6.9-rc6-dts-raw'
17c632b49122 Merge tag 'i2c-for-6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
a1bf8545a7b4 Merge tag 'soc-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
d13e05c0fe9b Merge tag 'arc-6.9-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
83b7bf1bdd47 Merge tag 'imx-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into for-next
3a940d011934 Merge tag 'mtk-dts64-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into for-next
6eeb1be299fc Merge tag 'at91-fixes-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into for-next
733db5273cb7 Merge tag 'qcom-arm64-fixes-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into for-next
76a235f6ef02 Merge branch 'v6.9-armsoc/dtsfixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into for-next
a4916498fb4a Merge tag 'at24-fixes-for-v6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-current
6ee8c2d34ea8 ARM: dts: imx6ull-tarragon: fix USB over-current polarity
c3ee365cb940 Merge tag 'iio-fixes-for-6.9a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-linus
bb3b0f6bb688 Merge tag 'v6.9-rc5-dts-raw'
ca2b45c908c0 arm64: dts: imx8mp: Fix assigned-clocks for second CSI2
b91b30ccdb82 Merge tag 'tty-6.9-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
9e347843c73f ARM: dts: microchip: at91-sama7g54_curiosity: Replace regulator-suspend-voltage with the valid property
a6e3d2cb9d6d ARM: dts: microchip: at91-sama7g5ek: Replace regulator-suspend-voltage with the valid property
01c2febb3cdb arm64: dts: qcom: sa8155p-adp: fix SDHC2 CD pin configuration
460856d18366 arm64: dts: rockchip: Fix USB interface compatible string on kobol-helios64
e91f447c8573 Merge tag 'pwm/for-6.9-rc5-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
b362458a0941 dt-bindings: eeprom: at24: Fix ST M24C64-D compatible schema
4c77f098d193 ARC: [plat-hsdk]: Remove misplaced interrupt-cells property
bc5665bd550f dt-bindings: pwm: mediatek,pwm-disp: Document power-domains property
bdb049c4d14f Merge tag 'v6.9-rc4-dts-raw'
ea20dda12f5b Merge tag 'soc-fixes-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
c43f5bbe57fe arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller
09bbdcd84ac2 arm64: dts: qcom: sm8650: Fix the msi-map entries
864783541376 arm64: dts: qcom: sm8550: Fix the msi-map entries
ddedda592d70 arm64: dts: qcom: sm8450: Fix the msi-map entries
960336e0e880 arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
eb57b8e07fd7 arm64: dts: qcom: x1e80100: Fix the compatible for cluster idle states
64b22344a08d arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocs
3d4da9353d8a Merge tag 'drm-fixes-2024-04-12' of https://gitlab.freedesktop.org/drm/kernel
94d5ae8ffd5b Merge tag 'drm-msm-next-2024-04-11' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
45ab49b70c99 LoongArch: Update dts for Loongson-2K2000 to support GMAC/GNET
e5f2765cdef5 LoongArch: Update dts for Loongson-2K2000 to support PCI-MSI
65d54f215c81 LoongArch: Update dts for Loongson-2K2000 to support ISA/LPC
05bddcf85f2c LoongArch: Update dts for Loongson-2K1000 to support ISA/LPC
e32b794a9062 arm64: dts: rockchip: regulator for sd needs to be always on for BPI-R2Pro
cf90790de0b2 dt-bindings: rockchip: grf: Add missing type to 'pcie-phy' node
ad6402eb7acc arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 2
ace753017ab4 arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 1
24eae3d76a2b arm64: dts: rockchip: drop redundant pcie-reset-suspend in Scarlet Dumo
6ddbc8e4f612 arm64: dts: rockchip: mark system power controller and fix typo on orangepi-5-plus
7d1e92c191e5 arm64: dts: rockchip: Designate the system power controller on QuartzPro64
b2f8ee07aa8e ASoC: dt-bindings: rt5645: add cbj sleeve gpio property
39841e784daa MAINTAINERS: mailmap: update Richard Genoud's email address
10c6631c86d1 Merge tag 'v6.9-rc3-dts-raw'
4ea847a91dd6 Merge tag 'devicetree-fixes-for-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
446b3564a952 arm64: dts: mediatek: mt2712: fix validation errors
65d0eb62f0f1 arm64: dts: mediatek: mt7986: prefix BPI-R3 cooling maps with "map-"
a2ac24e9a4dc arm64: dts: mediatek: mt7986: drop invalid thermal block clock
7d65b24f6c7b arm64: dts: mediatek: mt7986: drop "#reset-cells" from Ethernet controller
6674a5ba09ef arm64: dts: mediatek: mt7986: drop invalid properties from ethsys
fb0a8e849646 dt-bindings: timer: narrow regex for unit address to hex numbers
cb1b6952348f dt-bindings: soc: fsl: narrow regex for unit address to hex numbers
27c8017d28c8 dt-bindings: remoteproc: ti,davinci: remove unstable remark
9095a10d281f dt-bindings: clock: ti: remove unstable remark
3f61301c1488 dt-bindings: clock: keystone: remove unstable remark
31b1ce263042 arm64: dts: imx8qm-ss-dma: fix can lpcg indices
743b20b5d4db arm64: dts: imx8-ss-dma: fix can lpcg indices
d8f0818c58bc arm64: dts: imx8-ss-dma: fix adc lpcg indices
2349133feee2 arm64: dts: imx8-ss-dma: fix pwm lpcg indices
a18420af419e arm64: dts: imx8-ss-dma: fix spi lpcg indices
d6d2add292ae arm64: dts: imx8-ss-conn: fix usb lpcg indices
fc19a9596662 arm64: dts: imx8-ss-lsio: fix pwm lpcg indices
64a1c4a72a08 arm64: dts: mediatek: mt7622: drop "reset-names" from thermal block
f91467bb0e7c arm64: dts: mediatek: mt7622: fix ethernet controller "compatible"
8e632e3e98df arm64: dts: mediatek: mt7622: fix IR nodename
1472eb8a5653 arm64: dts: mediatek: mt7622: fix clock controllers
5802f95e74db arm64: dts: mediatek: mt8186-corsola: Update min voltage constraint for Vgpu
6cb73d686d58 arm64: dts: mediatek: mt8183-kukui: Use default min voltage for MT6358
cd3a14e0479e arm64: dts: mediatek: mt8195-cherry: Update min voltage constraint for MT6315
2814659a8a80 arm64: dts: mediatek: mt8192-asurada: Update min voltage constraint for MT6315
3ea180fa00c5 arm64: dts: mediatek: cherry: Describe CPU supplies
c452106eb835 arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex1
5893bd804364 arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex
ad1660ce46c3 arm64: dts: mediatek: mt8195: Add missing gce-client-reg to vpp/vdosys
744724419d4c arm64: dts: mediatek: mt8192: Add missing gce-client-reg to mutex
902cad91425f arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg
7b49bc388147 ARM: dts: imx7s-warp: Pass OV2680 link-frequencies
bd5623d08b6c ARM: dts: imx7-mba7: Use 'no-mmc' property
51b8028c7925 arm64: dts: imx8-ss-conn: fix usdhc wrong lpcg clock order
6beeed742637 dt-bindings: display/msm: sm8150-mdss: add DP node
954f369b81da ARC: Fix typos
3d2c4d764916 arm64: dts: rockchip: drop panel port unit address in GRU Scarlet
fa6ab1a0c8a1 arm64: dts: rockchip: Remove unsupported node from the Pinebook Pro dts
7f80622495d4 arm64: dts: qcom: sc7180-trogdor: mark bluetooth address as broken
92953647265f dt-bindings: bluetooth: add 'qcom,local-bd-address-broken'
6421f94d75f4 arm64: dts: freescale: imx8mp-venice-gw73xx-2x: fix USB vbus regulator
4bb321df9164 arm64: dts: freescale: imx8mp-venice-gw72xx-2x: fix USB vbus regulator
f37161a9cf0c dt-bindings: ufs: qcom: document SM6125 UFS
b2a26b71ae7d dt-bindings: ufs: qcom: document SC7180 UFS
1cb1e2605d33 dt-bindings: ufs: qcom: document SC8180X UFS
6bd77a407d2e dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' properties
2639a0e2fdbd Merge tag 'v6.9-rc1-dts-raw'
15eca7b21493 docs: dt-bindings: add missing address/size-cells to example
9ace491cae40 arm64: dts: rockchip: Fix the i2c address of es8316 on Cool Pi CM5
d8bdab44b3fe arm64: dts: rockchip: add regulators for PCIe on RK3399 Puma Haikou
1331876fe9c8 arm64: dts: rockchip: enable internal pull-up on PCIE_WAKE# for RK3399 Puma
57878497676a arm64: dts: rockchip: enable internal pull-up on Q7_USB_ID for RK3399 Puma
a9686a9d2878 arm64: dts: rockchip: fix alphabetical ordering RK3399 puma
6125abd98f94 arm64: dts: rockchip: enable internal pull-up for Q7_THRM# on RK3399 Puma
e51b8871e6a8 arm64: dts: rockchip: set PHY address of MT7531 switch to 0x1f
8c7a1135d13d dt-bindings: iio: health: maxim,max30102: fix compatible check
7eea89692b5a Merge tag 'timers-core-2024-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
665795c05a77 Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
9497bb8a116e Merge tag 'spi-fix-v6.9-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
6aef9b1ef737 Merge tag 'sound-fix2-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
17cde028ffcc Merge tag 'i2c-for-6.9-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
7bbd20ac15d0 Merge tag 'rtc-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
b2bb86451efb Merge tag 'ubifs-for-linus-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs
203aa834e5f2 Merge tag 'char-misc-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
9125147fa946 Merge tag 'tty-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
e5738ce51174 Merge tag 'usb-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
d4a1391985cc Merge tag 'rproc-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
b3632b121e0d Merge tag 'asoc-fix-v6.9-merge-window' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
4a7dcd8c3a18 dt-bindings: i2c: qcom,i2c-cci: Fix OV7251 'data-lanes' entries
f76fa412f9a8 Merge tag 'i2c-host-6.9-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
8cd35b85c4b0 Merge tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
f6c32d4a4ede Merge tag 'thermal-6.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
6630f47c5f9a spi: Merge up v6.8 release
ec2e44a038f5 Merge tag 'timers-v6.9-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core
ef0c6b10c2da Merge tag 'i3c/for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
6defc064e93e Merge tag 'linux-watchdog-6.9-rc1' of git://www.linux-watchdog.org/linux-watchdog
72fe2cde7b8a Merge tag 'input-for-v6.9-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
a546e7273d2d Merge tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
3972e256bfa2 Merge tag 'v6.9-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
a355cc2d4dcb Merge tag 'mips_6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
aefedca6e1b1 Merge tag 'devicetree-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
8eb838e35ade Merge tag 'mtd/for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
7497080a0eda Merge tag 'dmaengine-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
571f27ef129d Merge tag 'i2c-for-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
fb60e6d58b2d dt-bindings: input: samsung,s3c6410-keypad: convert to DT Schema
34598dab4724 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
9d67b3ce96cb Merge tag 'media/v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
3fe3426bca72 dt-bindings: soc: imx: fsl,imx-anatop: add imx6q regulators
7311bc58c158 Merge tag 'nand/for-6.9' into mtd/next
146d9a6f3ded dt-bindings: atmel-nand: add microchip,sam9x7-pmecc
e2a5c7c3959b arm64: dts: broadcom: bcmbca: Update router boards
1bd13f3b7695 arm64: dts: broadcom: bcmbca: Add NAND controller node
cc519333e3cf ARM: dts: broadcom: bcmbca: Add NAND controller node
c1e4264b6d55 Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
6371c24fe180 Merge tag 'sound-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
98c06b3a9483 Merge tag 'pci-v6.9-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
7fa73443a89b Merge tag 'platform-drivers-x86-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86
e76bc30ffbd6 Merge tag 'leds-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
19186d59b259 Merge tag 'backlight-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight
75c5518e62b1 Merge tag 'mfd-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
099699809967 Merge tag 'pinctrl-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
8e49bd3cbb58 Merge tag 'auxdisplay-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-auxdisplay
a775511def90 Merge tag 'drm-next-2024-03-13' of https://gitlab.freedesktop.org/drm/kernel
4d3acb15ed8a Merge tag 'spi-nor/for-6.9' into mtd/next
51591c70d1ca Merge branches 'clk-samsung', 'clk-imx', 'clk-rockchip', 'clk-clkdev' and 'clk-rate-exclusive' into clk-next
0c05d2bca0f7 Merge tag 'thermal-v6.9-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thermal/linux
a55648d846e7 Merge branches 'clk-remove', 'clk-amlogic', 'clk-qcom', 'clk-parent' and 'clk-microchip' into clk-next
749f625e4547 Merge branches 'clk-aspeed', 'clk-keystone', 'clk-mobileye' and 'clk-allwinner' into clk-next
82d0f90167fc Merge branches 'clk-renesas', 'clk-cleanup', 'clk-hisilicon', 'clk-mediatek' and 'clk-bulk' into clk-next
6526c4a4b4e5 Merge tag 'tpmdd-v6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd
1da1a2503cbc Merge tag 'mailbox-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
cecb3b4fdac3 Merge tag 'pm-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
49c8db52641c Merge tag 'pmdomain-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
b15efb2ec6a3 Merge tag 'hwmon-for-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
51da5c0be9f6 ASoC: Merge up release
82088fb378a1 Merge tag 'gpio-updates-for-v6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
08aa0ae1911b Merge tag 'spi-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
4a3bf9f36d1e Merge tag 'regulator-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
c77ca2066932 Merge tag 'mmc-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
c5d224537c1b Merge tag 'pwm/for-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
4915b8cd98b1 Merge tag 'ata-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
087aaa6a3b72 Merge tag 'iommu-updates-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
8a195fe51ba1 Merge tag 'net-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
80731b204b02 Merge tag 'soc-drivers-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
ba13a7bc46d2 Merge tag 'soc-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
8bdef0681554 Merge branch 'pci/controller/qcom'
5ad36cd7e767 riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
8ecbb51f81c3 dt-bindings: riscv: Add Andes PMU extension description
9b464e19669d riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
7d51e7e2e08f dt-bindings: riscv: Add Andes interrupt controller compatible string
9ff0305a8ca8 ASoC: dt-bindings: cirrus,cs42l43: Fix 'gpio-ranges' schema
9527f40e46b6 Input: allocate keycode for Display refresh rate toggle
62e63d55bebc Merge tag 'i2c-host-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
9570e92757ae dt-bindings: tpm: Add compatible string atmel,attpm20p
7cfac8b79d64 Merge tag 'irq-core-2024-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
432d7edb5952 dt-bindings: thermal: rcar-gen3-thermal: Add r8a779h0 support
338820b14493 dt-bindings: thermal-zones: Don't require polling-delay(-passive)
586ddb37a9a4 dt-bindings: thermal: sun8i: Add H616 THS controller
167b4b5a2247 dt-bindings: thermal: qoriq-thermal: Adjust fsl,tmu-range min/maxItems
97f8ab2a1af7 Merge tag 'opp-updates-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm into pm
6478cc89c8f9 Merge tag 'asoc-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
ac6125bb95c2 mips: dts: ralink: mt7621: add cell count properties to usb
c5bb691ccc3e mips: dts: ralink: mt7621: add serial1 and serial2 nodes
7b09814959b2 mips: dts: ralink: mt7621: reorder serial0 properties
ec836787ded4 mips: dts: ralink: mt7621: associate uart1_pins with serial0
7d9359e47208 Merge tag 'riscv-dt-fixes-for-v6.8-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
078fe0b4bda8 Merge tag 'arm-soc/for-6.9/drivers' of https://github.com/Broadcom/stblinux into soc/late
a851536f7d1f Merge tag 'arm-soc/for-6.9/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/late
63fbbfa8e739 dt-bindings: opp: drop maxItems from inner items
54c13b3c325d dt-bindings: mailbox: fsl,mu: add i.MX95 Generic/ELE/V2X MU compatible
4950062963d6 dt-bindings: input: imagis: Document touch keys
cfb6e7e4aab8 dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller
c779c938fb22 dt-bindings: pinctrl: qcom: update compatible name for match with driver
98b8ca8bcb74 dt-bindings: input: atmel,captouch: convert bindings to YAML
f4627ef4c35c dt-bindings: i2c: nomadik: add mobileye,eyeq5-i2c bindings and example
e6a7453cf514 Merge tag 'wireless-next-2024-03-08' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
826587e76776 dt-bindings: PCI: qcom: Do not require 'msi-map-mask'
e776ecb01509 dt-bindings: PCI: qcom: Allow 'required-opps'
41c94df7b508 dt-bindings: auxdisplay: Add bindings for generic 7-segment LED
51ec88485bd0 dt-bindings: rtc: zynqmp: Add support for Versal/Versal NET SoCs
4a0688c342c5 dt-bindings: rtc: abx80x: Improve checks on trickle charger constraints
09ed5b86a7c0 Merge branches 'arm/mediatek', 'arm/renesas', 'arm/smmu', 'x86/vt-d', 'x86/amd' and 'core' into next
1ca49df08091 dt-bindings: net: dp83822: change ti,rmii-mode description
9e691f2ca146 Merge tag 'drm-msm-next-2024-03-07' of https://gitlab.freedesktop.org/drm/msm into drm-next
cfe04ff5f8c9 dt-bindings: serial: stm32: add power-domains property
b072a75f7faf dt-bindings: nvmem: add common definition of nvmem-cell-cells
be64edb74cf7 dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml
baca151add1c nvmem: fixed-cell: Simplify nested if/then schema
1c0b231f57e0 dt-bindings: hwmon: Support Aspeed g6 PWM TACH Control
a0c034ed370f dt-bindings: hwmon: fan: Add fan binding to schema
5f3df8a26d1e dt-bindings: hwmon: tda38640: Add interrupt & regulator properties
ea5fd00e7566 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
1cd0ddec1f0e dt-bindings: timer: mediatek: Convert to json-schema
4a513c9ee434 ASoC: codecs: ES8326: change support for ES8326
9428855666bf dt-bindings: backlight: qcom-wled: Fix bouncing email addresses
ded680d1011e dt-bindings: leds: Add NCP5623 multi-LED Controller
36c053ec1940 dt-bindings: leds: qcom-lpg: Narrow nvmem for other variants
86d79b6e9034 dt-bindings: leds: qcom-lpg: Drop redundant qcom,pm8550-pwm in if:then:
0d9351b5397b dt-bindings: leds: Add LED_FUNCTION_WAN_ONLINE for Internet access
00b899276322 dt-bindings: leds: Add FUNCTION defines for per-band WLANs
0d85184c07f6 dt-bindings: leds: leds-qcom-lpg: Add support for LPG PPG
b4ab63101636 Merge branches 'ib-qcom-leds-6.9' and 'ib-leds-backlight-6.9' into ibs-for-leds-merged
3555e8d0b9fc dt-bindings: backlight: Add Kinetic KTD2801 binding
a8c949969077 Merge branch 'ib-nomadik-gpio' into devel
62c3262f7fe3 dt-bindings: net: renesas,etheravb: Add support for R-Car V4M
918ae23afab4 dt-bindings: interrupt-controller: fsl,intmux: Include power-domains support
e53ec66488c1 Merge tag 'icc-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
1f0e4fc46ee7 Merge tag 'qcom-arm64-for-6.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
ea75705aeacc Merge tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/late
584c83fce20d dt-bindings: remoteproc: qcom,sm8550-pas: document the X1E80100 aDSP & cDSP
c04e94fc3b79 dt-bindings: remoteproc: do not override firmware-name $ref
4b39a7e1c39f dt-bindings: remoteproc: qcom,glink-rpm-edge: drop redundant type from label
e6ec88170ffc dt-bindings: pinctrl: Add bindings for Awinic AW9523/AW9523B
fc76e2ec0af9 spi: dt-bindings: introduce FIFO depth properties
649423f8a081 ASoC: dt-bindings: rt1015: Convert to dtschema
7a4e8175bafb riscv: dts: starfive: jh7100: fix root clock names
eed1e7dce0c5 Merge tag 'ath-next-20240305' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath
b77c6d6ecd26 Merge tag 'v6.8-rc7' into gpio/for-next
b6f4257e837d dt-bindings: input: allwinner,sun4i-a10-lrad: drop redundant type from label
ab13fd756619 dt-bindings: fsl-imx-sdma: fix HDMI audio index
8183e8af3de8 dt-bindings: soc: imx: fsl,imx-iomuxc-gpr: add imx6
364eb93f21bc dt-bindings: soc: imx: fsl,imx-anatop: add binding
0d6b9633b62c dt-bindings: input: touchscreen: fsl,imx6ul-tsc convert to YAML
e24d180df3e3 dt-bindings: pinctrl: fsl,imx6ul-pinctrl: convert to YAML
c6cb9528755c Merge tag 'v6.9-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
1541b5f7169a dt-bindings: usb: typec-tcpci: add tcpci fallback binding
30cfb408e45f dt-bindings: usb: Add downstream facing ports to realtek binding
ba19f225f401 dt-bindings: usb: Add binding for TI USB8020B hub controller
c3251302f8d3 dt-bindings: usb: analogix,anx7411: drop redundant connector properties
c6425032f69e dt-bindings: usb: add hisilicon,hi3798mv200-dwc3
a1bd84637b96 dt-bindings: mmc: hisilicon,hi3798cv200-dw-mshc: add Hi3798MV200 binding
7fc53b04c1ea dt-bindings: mmc: dw-mshc-hi3798cv200: convert to YAML
f1338ec7ac44 dt-bindings: i2c: mpc: use proper binding for transfer timeouts
78ad26b5f48f dt-bindings: interrupt-controller: Convert Atmel AIC to json-schema
99d17f43c09c Merge tag 'reset-for-v6.9' of git://git.pengutronix.de/pza/linux into soc/late
14c572ddf1f9 Merge tag 'omap-for-v6.9/dt-warnings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/late
04cdefa63030 Merge tag 'vexpress-update-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
8100aecad25e ARM: dts: samsung: exynos4412: decrease memory to account for unusable region
44ffff36c17a Merge tag 'ti-keystone-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
38d2af77456f Merge tag 'memory-controller-drv-6.9-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
4b3d3727fe21 Merge tag 'qcom-drivers-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
1390bca92db4 spi: dt-bindings: samsung: make dma properties not required
f3f062800bf5 dt-bindings: perf: starfive: Add JH8100 StarLink PMU
8ade2ed03067 dt-bindings: usb: qcom,pmic-typec: add support for the PM4125 block
ffd54b03300e dt-bindings: leds: pwm-multicolour: re-allow active-low
2bd3e3e38b19 dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string
a1a33ad5df89 dt-bindings: imx6q-pcie: Add imx95 pcie compatible string
d5b3866ee39c dt-bindings: imx6q-pcie: Restruct reg and reg-name
17964120885e dt-bindings: imx6q-pcie: Clean up duplicate clocks check
b2e87666166c Merge tag 'qcom-arm32-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
d6f0d6fbd771 Merge tag 'v6.9-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
9beae6e4f5b2 Merge tag 'v6.9-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
bfa16e672f23 Merge tag 'riscv-sophgo-dt-for-v6.9' of https://github.com/sophgo/linux into soc/dt
b9a523277cff Merge tag 'mvebu-dt64-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
472acadc4b85 Merge tag 'mvebu-dt-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
a1c9c09fe4c6 Merge tag 'renesas-dt-bindings-for-v6.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
ed9768f823d1 Merge tag 'stm32-dt-for-v6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
a93afb6c68a1 arm64: dts: qcom: sm8250-xiaomi-elish: set rotation
c1d25c9b315c arm64: dts: qcom: sm8650: Fix SPMI channels size
f203c283f5bb arm64: dts: qcom: sm8550: Fix SPMI channels size
6b3cdc5e247c Merge tag 'drm-misc-next-2024-02-29' into msm-next
0ccaa0050371 dt-bindings: input/touchscreen: imagis: add compatible for IST3032C
f4cd9022dce6 dt-bindings: input/touchscreen: Add compatible for IST3038B
147eff3c7cff dt-bindings: watchdog: sama5d4-wdt: add compatible for sam9x7-wdt
3a9200687cf7 dt-bindings: watchdog: sprd,sp9860-wdt: convert to YAML
cbe08f41aa59 dt-bindings: watchdog: starfive,jh7100-wdt: Add compatible for JH8100
be02d67086d9 dt-bindings: watchdog: arm,sp805: document the reset signal
201c69876dc6 dt-bindings: watchdog: renesas-wdt: Add support for R-Car V4M
653594df87d5 dt-bindings: serial: convert st,asc to DT schema
1a0b7e8acef8 powerpc: dts: akebono: Harmonize EHCI/OHCI DT nodes name
8d179c0b54fb dt-bindings: usb: qcom,dwc3: fix a typo in interrupts' description
c630e9b5a72f arm64: dts: qcom: pm6150: define USB-C related blocks
da1d13674619 dt-bindings: usb: qcom,pmic-typec: Add support for the PM6150 PMIC
d3864961a639 Merge tag 'w1-drv-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1 into tty-next
8f130bd54c7b Merge tag 'iio-for-6.9b' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
20d54e06e2a3 Merge tag 'coresight-next-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
c326cc675c68 arm64: dts: rockchip: Fix name for UART pin header on qnap-ts433
3965a283125e dt-bindings: pwm: amlogic: Add a new binding for meson8 pwm types
d397107f4e3a dt-bindings: pwm: amlogic: fix s4 bindings
6d25cc8fd5da dt-bindings: i2c: Remove obsolete i2c.txt
59488a1b3652 dt-bindings: arm: syna: remove unstable remark
1d325ff1ed92 dt-bindings: net: bluetooth: qualcomm: Fix bouncing @codeaurora
9f1d679268ba dt-bindings: watchdog: drop obsolete brcm,bcm2835-pm-wdt bindings
090fc268fac4 dt-bindings: watchdog: qcom-wdt: Update maintainer to Rajendra Nayak
0451b0796a61 dt-bindings: hwmon: lm75: use common hwmon schema
371142306400 Merge tag 'amlogic-arm64-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
0e7fe10bc9e6 Merge tag 'amlogic-arm-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
d0cb807cfef4 Merge tag 'omap-for-v6.9/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt
3578f1b6dbed Merge tag 'ti-k3-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
d68c28418b67 riscv: dts: starfive: jh7110: Add camera subsystem nodes
aa86c303373a arm: dts: marvell: clearfog-gtr-l8: align port numbers with enclosure
ae315320f5d1 arm: dts: marvell: clearfog-gtr-l8: add support for second sfp connector
6330d58dd4fe dt-bindings: soc: renesas: renesas-soc: Add pattern for gray-hawk
1a4325f9d215 Merge tag 'arm-smmu-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu
6d23cfa8897b Merge tag 'at91-dt-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
7632a364f33e Merge tag 'zynqmp-dt-for-6.9' of https://github.com/Xilinx/linux-xlnx into soc/dt
02eba1b4512a Merge tag 'sgx-for-v6.9-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt
c0d63be31667 Merge tag 'imx-dt64-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
0d1bd814646e Merge tag 'imx-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
fcd3ba0ec7e6 Merge tag 'imx-bindings-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
911a0e5da311 Merge tag 'socfpga_dts_updates_for_v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
fec957a967a1 dt-bindings: rng: atmel,at91-trng: add sam9x7 TRNG
f25a9445fef8 dt-bindings: crypto: add sam9x7 in Atmel TDES
8790f16edade dt-bindings: crypto: add sam9x7 in Atmel SHA
44266f1d25b2 dt-bindings: crypto: add sam9x7 in Atmel AES
2b1ebc6d769d Merge tag 'qcom-arm64-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
43a56bf3bdaf Merge tag 'sunxi-dt-for-6.9-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
e19434848bd8 Merge tag 'drm-msm-next-2024-02-29' of https://gitlab.freedesktop.org/drm/msm into drm-next
01321d44f1ec dt-bindings: net: brcm,asp-v2.0: Add asp-v2.2
d5a543a359ce dt-bindings: net: brcm,unimac-mdio: Add asp-v2.2
089e8a0b0394 dt-bindings: gpio: aspeed,ast2400-gpio: Convert to DT schema
925e183d1d3e Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
c44ea78dc972 dt-bindings: rtc: abx80x: convert to yaml
3a25f24b71ce dt-bindings: at91rm9260-rtt: add sam9x7 compatible
6ae5f27fcef7 dt-bindings: rtc: convert MT7622 RTC to the json-schema
8e6eb376128e dt-bindings: rtc: convert MT2717 RTC to the json-schema
dffd03e7b3c3 Merge branch 'icc-sm7150' into icc-next
f8afb1ebc676 dt-bindings: interconnect: Add Qualcomm SM7150 DT bindings
253a470f5420 dt-bindings: mfd: syscon: Add ti,am62-usb-phy-ctrl compatible
f689de1b40f9 dt-bindings: mfd: dlg,da9063: Make #interrupt-cells required
a029ec8c35c4 Merge tag 'tegra-for-6.9-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
cbda1f9ca478 Merge tag 'tegra-for-6.9-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
061a7ef8ce88 Merge tag 'tegra-for-6.9-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
2788cdbbf836 Merge tag 'renesas-dts-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
af467f28aa2e Merge tag 'renesas-dt-bindings-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
e422e34ebe7a Merge tag 'v6.9-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
15643f4b8b71 Merge tag 'v6.9-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
3b71bcf355d9 Merge tag 'versatile-dts-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt
d73cece0601b Merge tag 'gemini-dts-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt
d5e822510e6a Merge tag 'mtk-dts64-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
88c6586d8ddc Merge tag 'dt-cleanup-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
485c27391cf2 Merge tag 'samsung-dt-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
9a55de21e5e8 Merge tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
7fe0c3cf50e7 Merge tag 'renesas-dts-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
a28ccc2c8a1e Merge tag 'renesas-dt-bindings-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
3a1d10b8a7ea dt-bindings: pinctrl: at91: add sam9x7
25fa45a7091a arm64: dts: st: add video encoder support to stm32mp255
374df3f7a69d arm64: dts: st: add video decoder support to stm32mp255
f1523e3d07c3 dt-bindings: gpio: nomadik: add optional reset property
7c456af0e520 dt-bindings: gpio: nomadik: add mobileye,eyeq5-gpio compatible
6412671654fb dt-bindings: gpio: nomadik: add optional ngpios property
33796ff4220d dt-bindings: gpio: nomadik: convert into yaml format
e5443d45c0ec ARM: dts: stm32: enable crypto accelerator on stm32mp135f-dk
fdf13e6831f2 ARM: dts: stm32: enable CRC on stm32mp135f-dk
b5c98471fd1a ARM: dts: stm32: add CRC on stm32mp131
f454b7a85920 dt-bindings: pinctrl: mobileye,eyeq5-pinctrl: add bindings
e03c12f18d62 ARM: dts: add stm32f769-disco-mb1166-reva09
690f4c3b681a ARM: dts: stm32: add display support on stm32f769-disco
4cb81b91ac87 ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco
82d1ed24df95 ARM: dts: stm32: add DSI support on stm32f769
c8114c09da2c dt-bindings: mfd: stm32f7: Add binding definition for DSI
363d4a9715e5 dt-bindings: nt35510: document 'port' property
9059c18b6d10 dt-bindings: iio: gyroscope: bosch,bmg160: add spi-max-frequency
ebcb39d7a66e dt-bindings: iio: adc: imx93: drop the 4th interrupt
2f1ec66e6c94 dt-bindings: iio: adc: drop redundant type from label
d24619ffe43c dt-bindings: iio: ti,tmp117: add optional label property
633fffb7c377 dt-bindings: iio: magnetometer: Add Voltafield AF8133J
a36a9e62abdf dt-bindings: vendor-prefix: Add prefix for Voltafield
2ef6443e1743 dt-bindings: iio: light: vishay,veml6075: make vdd-supply required
c9c055c5470f dt-bindings: iio: adc: adding support for PAC193X
a288cab1e5a6 dt-bindings: iio: hmc425a: add entry for LTC6373
43172d694644 dt-bindings: iio: hmc425a: add conditional GPIO array size constraints
42707bcbabe0 dt-bindings: iio: humidity: hdc20x0: add optional interrupts property
49676274cbd7 dt-bindings: iio: ti,tmp117: add vcc supply binding
6dafe28e7298 dt-bindings: mmc: fsl-imx-mmc: Document the required clocks
620fcff9d53c spi: dt-bindings: atmel,at91rm9200-spi: remove 9x60 compatible from list
22502bd8725d dt-bindings: mmc: fsl-imx-esdhc: add default and 100mhz state
a3da0bec1dd6 arm64: dts: rockchip: Add basic support for QNAP TS-433
e5d58e2bc9d5 dt-bindings: arm: rockchip: Add QNAP TS-433
78b9bf1a6128 arm64: dts: rockchip: add Haikou baseboard with RK3588-Q7 SoM
2ffa10c5e5ad arm64: dts: rockchip: add RK3588-Q7 (Tiger) SoM
7009dfbb88d7 dt-bindings: arm: rockchip: Add Theobroma-Systems RK3588 Q7 with baseboard
2516daa7bde5 arm64: dts: rockchip: drop rockchip,trcm-sync-tx-only from rk3588 i2s
fc876128d301 dt-bindings: net: ethernet-controller: drop redundant type from label
13ab34ef0793 arm64: dts: rockchip: fix reset-names for rk356x i2s2 controller
883bb3a0ffc9 arm64: dts: rockchip: add missing interrupt-names for rk356x vdpu
eec8be52f681 arm64: dts: rockchip: add clock to vo1-grf syscon on rk3588
103ec967103c dt-bindings: net: dsa: realtek: add reset controller
3018a826c97d dt-bindings: net: dsa: realtek: reset-gpios is not required
6dc9f167486c dt-bindings: arm: rockchip: Add Toybrick TB-RK3588X
a181bc600877 arm64: dts: rockchip: Add devicetree support for TB-RK3588X board
cc35d14ce704 ARM: dts: rockchip: Wifi improvements for Sonoff iHost
d3e564c6f34a ARM: dts: rockchip: mmc aliases for Sonoff iHost
ca5df862ea65 arm64: dts: rockchip: adjust vendor on orangepi rk3399 board
ed51c83e418c arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board
cff456e5f266 dt-bindings: arm: rockchip: Correct vendor for Banana Pi R2 Pro
3522950a8c39 dt-bindings: arm: rockchip: Correct vendor for Orange Pi RK3399 board
82a17c8827d1 arm64: dts: rockchip: Add HDMI0 PHY to rk3588
e66d1e81aed1 arm64: dts: armada-ap807: update thermal compatible
1d32f2a19cc3 arm64: dts: marvell: reorder crypto interrupts on Armada SoCs
35290ca22165 arm64: dts: ac5: add mmc node and clock
f5ba7df64a26 arm: dts: marvell: clearfog-gtr: add missing pinctrl for all used gpios
a64c072c8b1d arm: dts: marvell: clearfog-gtr: sort pinctrl nodes alphabetically
57a80269cb6c arm: dts: marvell: clearfog-gtr: add board-specific compatible strings
9f7d319ef30b arm: dts: marvell: clearfog: add pro variant compatible in legacy dts
ee29a2404550 dt-bindings: marvell: a38x: add solidrun armada 385 clearfog gtr boards
a94644e247d1 dt-bindings: marvell: a38x: add kobol helios-4 board
977f211a8ee3 dt-bindings: marvell: a38x: add solidrun armada 388 clearfog boards
6fe97bf74341 dt-bindings: marvell: a38x: convert soc compatibles to yaml
313957b8c112 Merge branch 'v6.9-shared/clkids' into v6.9-armsoc/dts64
e0f54133c394 dt-bindings: clock: rk3588: add missing PCLK_VO1GRF
e32d677022ca dt-bindings: clock: rk3588: drop CLK_NR_CLKS
4b58a7ccfd97 Merge tag 'mt76-for-kvalo-2024-02-22' of https://github.com/nbd168/wireless
479c5ca5c8ae dt-bindings: arm: amlogic: add Neil, Martin and Jerome as maintainers
39d812837cdd dt-bindings: arm: amlogic: remove unstable remark
54469d99a2af dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo CV1800B and SG2002 support
f4bffe85d2e7 dt-bindings: arm: qcom,coresight-tpdm: Rename qcom,dsb-element-size
7c2c6922effb dt-bindings: memory-controller: st,stm32: add MP25 support
b3f6be88f1f5 Merge 6.8-rc6 into tty-next
f4288db518a8 dt-bindings: net: cdns,macb: add sam9x7 ethernet interface
5315d5ea1db7 dt-bindings: i2c: at91: Add sam9x7 compatible string
b99dd7ccd5b8 dt-bindings: i2c: imx-lpi2c: add i.MX95 LPI2C
d377e1b8336c Convert some regulator drivers to GPIO descriptors
d5220c4662fe dt-bindings: auxdisplay: Add Maxim MAX6958/6959
2f25ffe9d998 dt-bindings: arm-smmu: Document SM8650 GPU SMMU
b4c3aaf580d9 dt-bindings: arm-smmu: fix SM8[45]50 GPU SMMU if condition
0abc1ff2be4e dt-bindings: display/msm/gmu: Document Adreno 750 GMU
ec4f0c02c1ec dt-bindings: display/msm: gpu: Allow multiple digits for patchid
49915776f063 dt-bindings: lcdif: Do not require power-domains for i.MX6ULL
a2a81ebc850d dt-bindings: timer: Add support for cadence TTC PWM
0a54c5eb5a02 Merge tag 'renesas-pinctrl-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
f12177200edc dt-bindings: interrupt-controller: Add starfive,jh8100-intc
99b3211ce73c regulator: dt-bindings: gpio-regulator: Fix "gpios-states" and "states" array bounds
ca5cca640867 ARM: dts: omap4-panda-common: Enable powering off the device
6b4a8eca637d ARM: dts: omap-embt2ws: system-power-controller for bt200
87c4cebd8708 ARM: dts: omap: Switch over to https:// url
80adf5afe7f6 ARM: dts: ti: omap: add missing abb_{mpu,ivahd,dspeve,gpu} unit addresses for dra7 SoC
a446d52725b5 ARM: dts: ti: omap: add missing sys_32k_ck unit address for dra7 SoC
4d96b742cb3e ARM: dts: ti: omap: add missing phy_gmii_sel unit address for dra7 SoC
7f22c5d06f8d dt-bindings: net: dp83822: support configuring RMII master/slave mode
5a411c0575cc ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift
43768eba3fa4 ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift
0f8d14846135 Merge v6.8-rc6 into drm-next
5ac99b57e27a dt-bindings: mtd: brcmnand: Add ecc strap property
d973f6e60329 dt-bindings: mtd: brcmnand: Add WP pin connection property
e8cf96a62e99 dt-bindings: mtd: brcmnand: Updates for bcmbca SoCs
4284b95c3a7d dt-bindings: mtd: st,stm32: add MP25 support
5ffc0c6588e1 dt-bindings: mtd: update references from partition.txt to mtd.yaml
079feabfa500 arm64: dts: ti: hummingboard-t: add overlays for m.2 pci-e and usb-3
77aac4df148c arm64: dts: add description for solidrun am642 som and evaluation board
bab419b95c2c dt-bindings: arm: ti: Add bindings for SolidRun AM642 HummingBoard-T
bc85817742eb dt-bindings: mtd: spi-nor: add optional interrupts property
201ac0128678 dt-bindings: pwm: opencores: Add compatible for StarFive JH8100
c0aae9685a91 dt-bindings: riscv: cpus: reg matches hart ID
8e0b9c610742 dt-bindings: bus: imx-weim: convert to YAML
c622150ed65c Merge v6.8-rc6 into usb-next
09994ac519e2 arm64: dts: imx8mm-kontron-bl-osm-s: Fix Ethernet PHY compatible
c8b82b8dd480 arm64: dts: imx8-apalis-v1.1: Remove reset-names from ethernet-phy
20cdb2916423 ARM: dts: nxp: imx: fix weim node name
064185347fff ARM: dts: nxp: imx6ul: fix touchscreen node name
42a236fd930d ARM: dts: nxp: imx6ul: xnur-gpio -> xnur-gpios
d9725dc952ee ARM: dts: imx6ul: Remove fsl,anatop from usbotg1
6cc27853e1c4 ARM: dts: imx6ull: fix pinctrl node name
c23b15b18c81 ARM: dts: imx1-apf9328: Fix Ethernet node name
7c8b8cf4dd15 ARM: dts: imx28-evk: Use 'eeprom' as the node name
102744f8003d ARM: dts: ls1021a: Enable usb3-lpm-capable for usb3 node
4822eab2af53 Merge branch 'icc-cleanup' into icc-next
0b20018b1dbc dt-bindings: mtd: ubi-volume: allow UBI volumes to provide NVMEM
5d1f49b1b6b0 dt-bindings: mtd: add basic bindings for UBI
9a35e12f4b1a dt-bindings: hwmon: reference common hwmon schema
3d36f23ac624 dt-bindings: hwmon: lltc,ltc4286: use common hwmon schema
798f72d666b8 dt-bindings: hwmon: adi,adm1275: use common hwmon schema
809baabdec34 dt-bindings: hwmon: ti,ina2xx: use common hwmon schema
42d06958b709 dt-bindings: hwmon: add common properties
f567e7a0ce93 regulator: dt-bindings: promote infineon buck converters to their own binding
b1715c2bbc33 dt-bindings: hwmon/pmbus: ti,lm25066: document regulators
0c5601d53cce dt-bindings: hwmon: nuvoton,nct6775: Add compatible value for NCT6799
fb5eada36609 dt-bindings: trivial-devices: add Astera Labs PT5161L
7d3134823476 dt-bindings: vendor-prefixes: add asteralabs
c75f1a591ccd dt-bindings: hwmon: Add Amphenol ChipCap 2
737f7b7c7c23 dt-bindings: vendor-prefixes: add Amphenol
380e45011084 dt-bindings: Add MPQ8785 voltage regulator device
adb144c788f3 dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1
77ced3f45487 dt-bindings: arm: add UNI-T UTi260B
521023b8972b dt-bindings: vendor-prefixes: add UNI-T
10a08d63eb50 arm64: dts: imx8mp-evk: Fix hdmi@3d node
96099eef1a2c arm64: dts: imx93-var-som: Remove phy-supply from eqos
0ee187cdb35f Merge tag 'iio-for-6.9a' of http://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
9aa0ba8c3e6a arm64: dts: imx8mp-phyboard-pollux: Disable pull-up for CD GPIO
195bcec93c44 arm64: dts: imx8mp-phyboard-pollux: Reduce drive strength for eqos tx lines
adb0eb622cec arm64: dts: imx8mp-phyboard-pollux: Set debug uart muxing to 0x140
8032acfdf1a8 arm64: dts: imx8mp-phyboard-pollux: Add and update rtc devicetree node
9ffab265f1ac arm64: dts: imx8mm-evk: Add spdif sound card support
3f1b2e8d9e29 arm64: dts: mba8xx: Add missing #interrupt-cells
dd5af1f60a28 arm64: dts: imx8mp: Set SPI NOR to max 40 MHz on Data Modul i.MX8M Plus eDM SBC
f461418b3107 ARM: dts: imx6dl-yapp4: Move the internal switch PHYs under the switch node
dbaddd2cc383 ARM: dts: imx6dl-yapp4: Fix typo in the QCA switch register address
6a28d56cd75a arm64: dts: imx8mn: tqma8mqnl-mba8mx: Add USB DR overlay
68f02dd7e55f arm64: dts: imx8mq: tqma8mq-mba8mx: Add missing USB vbus supply
06e63f07db24 arm64: dts: freescale: imx8mm/imx8mq: mba8mx: Use PCIe clock generator
65f27cc9ca1b arm64: dts: imx8mn-beacon: Remove unnecessary clock configuration
ec091103f662 arm64: dts: imx8mn: Slow default video_pll clock rate
f3ed68d12445 arm64: dts: imx8mp-beacon: Configure multiple queues on eqos
825a35212289 arm64: dts: imx8mp-beacon: Enable Bluetooth
e32a570a61aa ARM: dts: imx6ul: Set macaddress location in ocotp
48b05a3282bd arm64: dts: freescale: minor whitespace cleanup
4b0cf920e774 arm64: dts: allwinner: h616: Add thermal sensor and zones
d0665f60cec0 ARM: dts: sun8i: Open FETA40i-C regulator aldo1
f0c099b60ae3 arm64: dts: allwinner: h616: Add Sipeed Longan SoM 3H and Pi 3H board support
01ae6c03a880 dt-bindings: arm: sunxi: Add Sipeed Longan Module 3H and Longan Pi 3H
c763b1cf0ca7 arm64: dts: allwinner: h616: minor whitespace cleanup
fba9e58bbd03 arm64: dts: allwinner: use capital "OR" for multiple licenses in SPDX
c6b7cf5d4b69 arm64: dts: allwinner: Transpeed 8K618-T: add WiFi nodes
13d73fcac8c9 arm64: dts: allwinner: h616: Add 32K fanout pin
05bdbb1eb3fd arm64: dts: allwinner: Add Jide Remix Mini PC support
0df51b232403 dt-bindings: arm: sunxi: document Remix Mini PC name
898b36322bb2 dt-bindings: vendor-prefixes: add Jide
70e735bb236e arm64: dts: allwinner: h616: Add SPDIF device node
10969c04cb6e arm64: dts: allwinner: h616: Add DMA controller and DMA channels
c5182cdc0aa8 arm64: dts: allwinner: h6: Add RX DMA channel for SPDIF
e31d5ca612d6 dt-bindings: sram: narrow regex for unit address to hex numbers
013b1096017d ARM: dts: microchip: sama7g5: add sama7g5 compatible
782f527e1b30 ARM: dts: microchip: sam9x60: align dmas to the opening '<'
d08950521775 ARM: dts: microchip: sama7g5: align dmas to the opening '<'
c9cdb533541e ARM: dts: microchip: sama7g54_curiosity: Add initial device tree of the board
28a13f689e75 ARM: dts: microchip: sama7g5: Add flexcom 10 node
57fb3296fc2d ASoC: dt-bindings: microchip: add sam9x7
81a8f19d991d ASoC: dt-bindings: atmel-classd: add sam9x7 compatible
c1e8427eb3df dt-bindings: ARM: at91: Document Microchip SAMA7G54 Curiosity
708077cf30a4 arm64: tegra: Remove Jetson Orin NX and Jetson Orin Nano DTSI
14b1c490371e arm64: tegra: Add audio support for Jetson Orin NX and Jetson Orin Nano
5bdc0a8fed68 arm64: tegra: Define missing IO ports
8ff1bf770a0c arm64: tegra: Move AHUB ports to SoC DTSI
9fd53de0ed30 arm64: tegra: Add USB Type-C controller for Jetson AGX Xavier
6c9a92242095 arm64: tegra: Add USB device support for Jetson AGX Xavier
495a87da7a47 arm64: tegra: Add current monitors for Jetson Xavier
426c1ddbd76b arm64: tegra: Add AXI configuration for Tegra234 MGBE
134b7a20eea2 dt-bindings: mfd: Convert atmel-flexcom to json-schema
7268c6969288 dt-bindings: mfd: cros-ec: Add properties for GPIO controller
a5c0c33c25f1 dt-bindings: mfd: ti,twl: Document system-power-controller
507cf9210c91 dt-bindings: net: wireless: qcom: Update maintainers
a9219f105d93 dt-bindings: mfd: syscon: Add ti,am654-serdes-ctrl compatible
37c3dbbbca5d dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible
ef9712ce90c9 dt-bindings: mfd: atmel,hlcdc: Convert to DT schema format
fc3911fb624f dt-bindings: mfd: qcom,tcsr: Add compatibles for QCM2290 and SM6115
bcc7a549de96 dt-bindings: mfd: iqs62x: Do not override firmware-name $ref
e3889bfdf9d5 dt-bindings: media: rkisp1: Add i.MX8MP ISP to compatible
e7d16b884c9d dt-bindings: timer: add Ralink SoCs system tick counter
f4535baea464 dt-bindings: PCI: qcom,pcie-sa8775p: Move SA8775p to dedicated schema
169fa31aecaa dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema
9a6e22b46113 dt-bindings: PCI: qcom,pcie-sc8180x: Move SC8180X to dedicated schema
e114fb24a186 dt-bindings: PCI: qcom,pcie-sc8280xp: Move SC8280XP to dedicated schema
88e9e05efe99 dt-bindings: PCI: qcom,pcie-sm8350: Move SM8350 to dedicated schema
977832dca6ab dt-bindings: PCI: qcom,pcie-sm8150: Move SM8150 to dedicated schema
53908f6ff54c dt-bindings: PCI: qcom,pcie-sm8250: Move SM8250 to dedicated schema
96931e6b08ab dt-bindings: PCI: qcom,pcie-sm8450: Move SM8450 to dedicated schema
3c9f28bcffc2 dt-bindings: PCI: qcom,pcie-sm8550: Move SM8550 to dedicated schema
c2f1d4a9447a arm64: dts: renesas: rzg2l-smarc: Enable DU and link with DSI
b39f9a0e920d arm64: dts: renesas: r9a07g054: Add DU node
3ecd2f1980c9 arm64: dts: renesas: r9a07g044: Add DU node
93d319ea783c arm64: dts: lx2160a: Fix DTS for full PL011 UART
8365edf2f65e arm64: dts: ls1088a: Add the PME interrupt for PCIe EP node
084a47a95058 arm64: dts: imx8qm: add i2c1 for imx8qm-mek board
d84b45a3c712 arm64: dts: imx8qm: add i2c4 and i2c4_lpcg node
9d3bb1c53622 ASoC: Revert "ASoC: dt-bindings: Update example for enabling USB offload on SM8250"
7ada2cb724f2 riscv: dts: add resets property for uart node
a034d20d33af riscv: dts: add reset generator for Sophgo SG2042 SoC
b312f7c28451 ARM: dts: imx53-qsb: add support for the HDMI expander
65d763356aad arm64: dts: imx8mp: Enable SAI audio on Data Modul i.MX8M Plus eDM SBC
c3b757a52529 arm64: dts: imx8: Fix lpuart DMA channel order
a9c570888e1c arm64: dts: freescale: imx8-ss-dma: Fix edma3's location
1880684dfc18 arm64: dts: imx8dxl update edma0 information
95a51114540e arm64: dts: imx8dxl: add fsl-dma.h dt-binding header file
87cc839ce871 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
595539769055 dt-bindings: vendor-prefixes: Add missing prefixes used in compatibles
2b8f61f2af78 dt-bindings: display: convert Atmel's HLCDC to DT schema
d4e9fb508b98 dt-bindings: display/msm: Document MDSS on X1E80100
26ae54a934e7 dt-bindings: display/msm: Document the DPU for X1E80100
eec4611e4fa5 dt-bindings: arm-smmu: Document SM8650 GPU SMMU
011fc2593f52 dt-bindings: arm-smmu: Fix SM8[45]50 GPU SMMU 'if' condition
f45f80911a1e ARM: tegra: Add device-tree for LG Optimus 4X HD (P880)
c99ab6147bdd ARM: tegra: Add device-tree for LG Optimus Vu (P895)
9668ead0c4a9 ARM: tegra: nexus7: Add missing clock binding into sound node
1a7c7ca1209d dt-bindings: arm: tegra: Add LG Optimus Vu P895 and Optimus 4X P880
55fa85648879 arm64: dts: Add gpio_intc node for Amlogic-T7 SoCs
3040579f9058 dt-bindings: interrupt-controller: Add support for Amlogic-T7 SoCs
ac30a4ade02e dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts
cf713971ea71 dt-bindings: arm-smmu: Add QCM2290 GPU SMMU
cfbcf932a683 arm64: dts: renesas: gray-hawk-single: Add QSPI FLASH support
7b0d1d64e101 arm64: dts: renesas: r8a779h0: Add RPC node
cf8ea631a9d7 arm64: dts: renesas: r8a779h0: Add DMA support
44de0122e321 arm64: dts: renesas: gray-hawk-single: Add eMMC support
697c226a4355 arm64: dts: renesas: r8a779h0: Add SD/MMC node
bc3ce3810946 ARM: dts: renesas: r8a7778: Add missing reg-names to sound node
59d2898af1c8 arm64: dts: renesas: rzg2ul-smarc: Enable CRU, CSI support
e4684cc943fe arm64: dts: renesas: gray-hawk-single: Add Ethernet support
08896ba8e650 arm64: dts: renesas: r8a779h0: Add Ethernet-AVB support
fe2d22e4ae91 arm64: dts: renesas: r8a779g0: Correct avb[01] reg sizes
4c2e92819772 arm64: dts: renesas: r8a779a0: Correct avb[01] reg sizes
d857aea85b27 arm64: dts: renesas: r9a08g045: Add PSCI support
ac45f97b1f9c arm64: dts: renesas: rzg3s-smarc-som: Guard Ethernet IRQ GPIO hogs
aef97a58051b arm64: dts: renesas: r9a08g045: Add missing interrupts to IRQC node
68b5a3b20687 arm64: dts: renesas: rzg2l: Add missing interrupts to IRQC nodes
5a4108c215f6 arm64: dts: renesas: r8a779h0: Add CA76 operating points
bd25260cfef9 arm64: dts: renesas: r8a779h0: Add CPU core clocks
291552f30777 arm64: dts: renesas: r8a779h0: Add CPUIdle support
20170eff3c40 arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores
4c3851d7302a arm64: dts: renesas: r8a779h0: Add L3 cache controller
149125c48481 arm64: dts: renesas: r8a779h0: Add GPIO nodes
e6842397bea1 arm64: dts: renesas: gray-hawk-single: Add I2C0 and EEPROMs
4ab7a0fae505 arm64: dts: renesas: r8a779h0: Add I2C nodes
4f678406736f arm64: dts: renesas: ulcb-kf: Adapt sound 5v regulator to schematics
ab5123a5fcbb arm64: dts: renesas: ulcb-kf: Adapt 1.8V HDMI regulator to schematics
36bd3f79100c arm64: dts: renesas: ulcb-kf: Add regulators for PCIe ch1
d79c233e5296 arm64: dts: renesas: gray-hawk-single: Add serial console pin control
adb055f45503 arm64: dts: renesas: r8a779h0: Add pinctrl device node
393149daa9ec dt-bindings: net: wireless: mt76: allow all 4 interrupts for MT7981
abc93201d108 dt-bindings: net: wireless: mt76: add interrupts description for MT7986
6ff46183ee46 dt-bindings: memory: renesas,rpc-if: Document R-Car V4M support
caaf33bab010 dt-bindings: reset: mobileye,eyeq5-reset: add bindings
d627a28b5d6f dt-bindings: clock: mobileye,eyeq5-clk: add bindings
ebd3bcd073ce dt-bindings: clock: ast2600: Add FSI clock
d19d06cdbb21 dt-bindings: reset: mediatek: add MT7988 infracfg reset IDs
f907dd749888 dt-bindings: clock: mediatek: convert SSUSBSYS to the json-schema clock
77f559281267 dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clock
5776acd8f40b dt-bindings: clock: mediatek: convert hifsys to the json-schema clock
2b71a4051c65 dt-bindings: arm: realview: Spelling s/ARM 11/Arm11/, s/Cortex A-/Cortex-A/
d5d9be3159cd ARM: dts: integrator: Fix up VGA connector
e7ff0fa9dc10 ARM: dts: versatile: Fix up VGA connector
5cc0ca358e86 ARM: dts: arm: realview: Fix development chip ROM compatible value
17690d898c6b arm64: dts: ti: k3-am62p: Add Wave5 Video Encoder/Decoder Node
1a04d9e2ea04 arm64: dts: ti: k3-j721s2-main: Add Wave5 Video Encoder/Decoder Node
037f82133c88 arm64: dts: ti: k3-j784s4: Add Wave5 Video Encoder/Decoder Node
b9b4934fd72d arm64: dts: ti: k3-am69-sk: Add support for OSPI flash
54bdd26cd110 arm64: dts: ti: k3-am69-sk: Enable CAN interfaces for AM69 SK board
5ddb529be866 arm64: dts: ti: k3-am62p: Add nodes for CSI-RX
2bc64591456d arm64: dts: ti: k3-am62p: Add DMASS1 for CSI
fb6e8cb37b07 arm64: dts: ti: k3-am62p: Fix memory ranges for DMSS
4a664d32a079 arm64: dts: ti: k3-j722s-evm: Enable OSPI NOR support
0a3c08b6205b arm64: dts: ti: k3-j722s-evm: Enable CPSW3G RGMII1
6d9068d2f3e7 arm64: dts: ti: k3-j784s4-main: Fix mux-reg-masks in serdes_ln_ctrl
8f04b7849578 arm64: dts: ti: k3-j721e: Fix mux-reg-masks in hbmc_mux
c3982938ea86 dt-bindings: display: renesas,rzg2l-du: Document RZ/V2L DU bindings
62d59754ec63 dt-bindings: display: Document Renesas RZ/G2L DU bindings
b9138e8af159 arm64: tegra: Use consistent SD/MMC aliases on Tegra234
dcff839661ba arm64: dts: amlogic: add fbx8am DT overlays
0d16b6bd5803 ARM: dts: gemini: Fix switch node names on Vitesse switches
81e1d1cfd2f9 ARM: dts: gemini: Map reset keys to KEY_RESTART
915ebb1bf1e0 ARM: dts: gemini: Fix wiligear compatible strings
d8869f38c863 ARM: dts: gemini: Fix switch node names in the DIR-685
4466332a360b ASoC: dt-bindings: qcom,wsa8840: Add reset-gpios for shared line
8d8332ce62c5 dt-bindings: reset: sophgo: support SG2042
357d5bbac5af ASoC: Intel: avs: Fixes and new platforms support
ed4851e1d924 regulator: dt-bindings: qcom,usb-vbus-regulator: add support for PM4125
bcf5ae8600f6 regulator: dt-bindings: qcom,usb-vbus-regulator: add support for PM4125
90ad8fbfa7f9 Merge tag 'memory-controller-drv-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
6a8fb7b89e73 arm64: dts: qcom: sm6115: fix USB PHY configuration
0dc3ecab7183 Merge tag 'linux-can-next-for-6.9-20240220' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next
f923d17647b5 MIPS: mobileye: Add EPM5 device tree
885d1e731299 MIPS: mobileye: Add EyeQ5 dtsi
7fb9ce7c1dde dt-bindings: mips: Add bindings for Mobileye SoCs
e3797e6a3708 dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core
9a705909b63d dt-bindings: mips: cpus: Sort the entries
e0340332869b dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd.
011bf078c7bc dt-bindings: pinctrl: renesas,pfc: Document R-Car V4M support
49888873d596 dt-bindings: net: fec: add iommus property
80733980e6ba dt-bindings: iio: adc: ti-ads1298: Add bindings
26a3005ca5c0 dt-bindings: iio: pressure: honeywell,hsc030pa.yaml add spi props
d64846638639 dt-bindings: adc: axi-adc: update bindings for backend framework
a3fc6ec1428b dt-bindings: adc: ad9467: add new io-backend property
c0d436471a5f regulator: Merge up v6.8-rc5
52dcafce5828 dt-bindings: regulator: qcom,usb-vbus-regulator: Add PM6150 compatible
66f7b7966dfc arm64: dts: ti: Add common1 register space for AM62A SoC
6b911cea73bb arm64: dts: ti: Add common1 register space for AM62x SoC
bb6e999b30ab arm64: dts: ti: Add common1 register space for AM65x SoC
2a98a4ff884d arm64: dts: mt8195-cherry-tomato: change watchdog reset boot flow
b5c66885729f dt-bindings: display: simple: Add boe,bp082wx1-100 8.2" panel
0b9a359a81b7 dt-bindings: display: ti,am65x-dss: Add support for common1 region
0033e16adcd4 dt-bindings: renesas: Document preferred compatible naming
1771fa16d31e dt-bindings: ata: convert MediaTek controller to the json-schema
127ae13f4e5e arm64: dts: mt7986: add port@5 as CPU port
57f255ff84ed arm64: dts: mt7622: add port@5 as CPU port
1e471beb8eea ARM: dts: meson8b: fix &hwrng node compatible string
320da6153b8a ARM: dts: meson8: fix &hwrng node compatible string
9625cfa0c727 ARM: dts: meson: fix bus node names
f496b04c1652 arm64: dts: amlogic: add fbx8am board
686e2be425fd dt-bindings: arm: amlogic: add fbx8am binding
48371b0670ac dt-bindings: vendor-prefixes: add freebox
471f9b9dd5e2 arm64: dts: amlogic: replace underscores in node names
6e0fb3cc9b68 arm64: dts: ti: k3-am642-evm: add overlay for ICSSG1 2nd port
7526121625ee dt-bindings: interconnect: qcom,rpmh: Fix bouncing @codeaurora address
fcda7c3e7ef7 Merge 6.8-rc5 into usb-next
670cbcdfbb09 arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support
cea3277e3b5e arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes
eb0aea3a7c5a Merge 6.8-rc5 into tty-next
c07c11c8be59 arm64: dts: ti: k3-am6*: Add bootph-all property in MMC node
59d465b82cb4 arm64: dts: ti: k3-am6*: Fix bus-width property in MMC nodes
16af8c673aff arm64: dts: ti: k3-am6*: Fix ti,clkbuf-sel property in MMC nodes
87f154491e63 arm64: dts: ti: k3-am6*: Remove DLL properties for soft PHYs
722bd88c8fab arm64: dts: ti: k3-am62p: Add ITAP/OTAP values for MMC
18c8263c1ec1 arm64: dts: ti: k3-am64-main: Fix ITAP/OTAP values for MMC
73f1cbbcb198 arm64: dts: ti: k3-am62a7-sk: Enable eMMC support
973681d9002a arm64: dts: ti: k3-am62a-main: Add sdhci2 instance
4430a5c5a0ec arm64: dts: ti: k3-am62a-main: Add sdhci0 instance
be340f86aaf1 arm64: dts: sm8650: Add msi-map-mask for PCIe nodes
49cf8bb8b63f arm64: dts: qcom: replace underscores in node names
8f9d0aa368d0 ARM: dts: qcom: samsung-matisse-common: Add UART
ce30f2d31d9c ARM: dts: qcom: Add support for Samsung Galaxy Tab 4 10.1 LTE (SM-T535)
afbdd6233c4a ARM: dts: qcom: samsung-matisse-common: Add initial common device tree
6a80ca4b242a dt-bindings: arm: qcom: Add Samsung Galaxy Tab 4 10.1 LTE
3cef33d6916c dt-bindings: soc: qcom: qcom,saw2: add msm8226 l2 compatible
e4d2d663cf96 arm64: dts: ti: k3-j784s4-evm: Remove Pinmux for CTS and RTS in wkup_uart0
d43ac341179d arm64: dts: ti: k3-j721s2-common-proc-board: Remove Pinmux for CTS and RTS in wkup_uart0
80e20b3b69c9 arm64: dts: ti: k3-j7200-common-proc-board: Remove clock-frequency from mcu_uart0
35877fcaea3a arm64: dts: ti: k3-j7200-common-proc-board: Modify Pinmux for wkup_uart0 and mcu_uart0
cac67785c0a6 arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219
b1d7814ca372 arm64: dts: ti: k3-j784s4-main: Add CSI2RX capture nodes
b6b2d86e2411 arm64: dts: ti: k3-j721s2-main: Add CSI2RX capture nodes
58403c60add6 arm64: dts: ti: k3-j721e-main: Add CSI2RX capture nodes
4796014c5f92 arm64: dts: ti: k3-j721e-sk: Model CSI2RX connector mux
b599ef1ba8ff arm64: dts: ti: k3-am69-sk: Enable camera peripherals
248c870c7bd6 arm64: dts: ti: k3-am68-sk-base-board: Enable camera peripherals
a5f6b550f77b arm64: dts: ti: k3-j784s4-evm: Enable camera peripherals
f70c4ae50ecf arm64: dts: ti: k3-j721s2-common-proc-board: Enable camera peripherals
4141c6b09a96 dt-bindings: i3c: drop "master" node name suffix
f3ca3a16bd19 dt-bindings: timer: nxp,sysctr-timer: support i.MX95
19b1a141c8dd dt-bindings: usb: qcom,pmic-typec: add support for the PMI632 block
15c348192cc2 dt-bindings: regulator: qcom,usb-vbus-regulator: add support for PMI632
3c201cdbc89a dt-bindings: iio: humidity: hdc3020: add interrupt bindings in example
0fc77339f456 dt-bindings: iio: afe: voltage-divider: Add io-channel-cells
7adf6f669393 dt-bindings: iio: imu: st_lsm6dsx: add asm330lhhxg1
bd37e5428ced dt-bindings: iio: frequency: add admfm2000
f6c7124a3d91 dt-bindings: usb/ti,am62-usb.yaml: Add PHY2 register space
3102faf7d698 dt-bindings: usb: microchip,usb5744: Remove peer-hub as requirement
d403cb0d5128 arm64: dts: qcom: qcm6490-fairphone-fp5: Add PMIC GLINK
7ab947b60396 dt-bindings: usb: dwc3: drop 'snps,host-vbus-glitches-quirk'
e007ca0c7920 ASoC: dt-bindings: Update example for enabling USB offload on SM8250
14bd5c629408 ASoC: dt-bindings: Add Q6USB backend
86b2f37571d9 arm64: dts: ti: Add reserved memory for watchdog
0ffb30594139 arm64: dts: qcom: pm4125: define USB-C related blocks
437f7c2c748a arm64: dts: qcom: sa8540p-ride: disable pcie2a node
ddc97b021a4f arm64: dts: qcom: sc7280: add slimbus DT node
174b19d0a453 dt-bindings: display: ltk500hd1829: add variant compatible for ltk101b4029w
9990fd362767 dt-bindings: display: panel-lvds: Add compatible for admatec 9904370 panel
3a9936a295c2 dt-bindings: vendor-prefixes: add prefix for admatec GmbH
11b2a690403f arm64: dts: qcom: sc7280: Add capacity and DPC properties
23437543023d ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices
cabc075cf325 ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices
484c003d94ab ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device
6445cb8886be ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device
98ba5545146c ARM: dts: qcom: msm8960: declare SAW2 regulators
b54dea12770f ARM: dts: qcom: apq8064: declare SAW2 regulators
4dce2cf9f83d ARM: dts: qcom: ipq8064: rename SAW nodes to power-manager
5b13a9611268 ARM: dts: qcom: ipq4019: rename SAW nodes to power-manager
0ec0f547bc86 ARM: dts: qcom: msm8974: rename SAW nodes to power-manager
9c6828f9c895 ARM: dts: qcom: msm8960: rename SAW nodes to power-manager
d5acf25ed148 ARM: dts: qcom: apq8084: rename SAW nodes to power-manager
643db1cecca9 ARM: dts: qcom: apq8064: rename SAW nodes to power-manager
4de620145e88 ARM: dts: qcom: ipq8064: use SoC-specific compatibles for SAW2 devices
c44fb47e47a5 ARM: dts: qcom: ipq4019: use SoC-specific compatibles for SAW2 devices
5e99522aa387 ARM: dts: qcom: msm8960: use SoC-specific compatibles for SAW2 devices
75a6d010f715 ARM: dts: qcom: msm8974: use new compat string for L2 SAW2 unit
9eb4395e3cbc ARM: dts: qcom: apq8084: use new compat string for L2 SAW2 unit
0cc21b045573 arm64: dts: qcom: pmi632: Add PBS client and use in LPG node
adaff156bd89 arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1
567a4e2c1bfd arm64: dts: qcom: sm8150: correct PCIe wake-gpios
aff4851c71af arm64: dts: qcom: sdm845-db845c: correct PCIe wake-gpios
d12e2e81b378 dt-bindings: soc: qcom: qcom,saw2: define optional regulator node
87cb0efb080c dt-bindings: soc: qcom: qcom,saw2: add missing compatible strings
78779d5162e9 dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml
90689200835c arm64: dts: qcom: sm7225-fairphone-fp4: Enable display and GPU
49fc8baa3dd8 arm64: dts: qcom: sm6350: Remove "disabled" state of GMU
3bb88ee4bafc dt-bindings: clk: qcom: drop the SC7180 Modem subsystem clock controller
08488eb0c95c arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add fuel gauge
9230383364ef arm64: dts: qcom: sm6350: Add interconnect for MDSS
93d1070a237b dt-bindings: can: xilinx_can: Add 'xlnx,has-ecc' optional property
09c2905a6449 dt-bindings: renesas,rcar-dmac: Add r8a779h0 support
8500691f667d dt-bindings: dma: convert MediaTek High-Speed controller to the json-schema
7b382eea018b arm64: tegra: Enable cros-ec-spi as wake source
73f09474de21 ARM: tegra: Enable cros-ec-spi as wake source
9c3c23577ad9 dt-bindings: tegra: pmc: Update scratch as an optional aperture
296aea7e0f2a dt-bindings: display: panel: Add Himax HX83112A
5b0ce634f06d dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema
01f41446bb7f Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
87dd58b7c6ca dt-bindings: mmc: renesas,sdhi: Document R-Car V4M support
ec136bb18fcc arm64: dts: ti: Add support for TI J722S Evaluation Module
4dd9e11aa40f arm64: dts: ti: Introduce J722S family of SoCs
1339c374a4c1 dt-bindings: arm: ti: Add bindings for J722S SoCs
723c10f0bd63 arm64: dts: ti: iot2050: Support IOT2050-SM variant
4a95da5a5df9 arm64: dts: ti: iot2050: Annotate LED nodes
a2119b7f92bd arm64: dts: ti: iot2050: Factor out DP related bits
a3f672abd86f arm64: dts: ti: iot2050: Factor out enabling of USB3 support
0f7fd425cef9 arm64: dts: ti: iot2050: Factor out arduino connector bits
326a69a3e459 arm64: dts: ti: iot2050: Disable R5 lockstep for all PG2 boards
9f6227cced13 dt-bindings: arm: ti: Add binding for Siemens IOT2050 SM variant
4c8ad6e37e97 arm64: dts: ti: k3-am62-main: disable usb lpm
58003d5a29e5 arm64: dts: ti: verdin-am62: Set VDD CORE minimum voltage to 0.75V
09148e5825bc arm64: dts: ti: k3-am62-wakeup: Configure ti-sysc for wkup_uart0
8d7152a47403 arm64: dts: ti: am62-phyboard-lyra: Add overlay to enable a GPIO fan
16c636f5b152 arm64: dts: ti: k3-j721e-sk: fix PMIC interrupt number
2932b4306805 arm64: dts: ti: k3-am69-sk: fix PMIC interrupt number
f6c375e9f85d arm64: dts: ti: verdin-am62: add support for Verdin USB1 interface
309045be68da arm64: dts: ti: Add DT overlay for PCIe + USB3.0 SERDES personality card
2979217a850f arm64: dts: ti: Add DT overlay for PCIe + USB2.0 SERDES personality card
b70ff6a5d411 dt-bindings: w1: UART 1-Wire bus
21e00d907bfb dt-bindings: serial: allow onewire as child node
1f162c88f711 dt-bindings: pwm: mediatek,mt2712: add compatible for MT7988
b69225cd6653 dt-bindings: atmel,hlcdc: convert pwm bindings to json-schema
4fc4f31db241 dt-bindings: pxa-pwm: Convert to YAML
61f4ac7c5c90 ARM: dts: vexpress: Set stdout-path to serial0 in the chosen node
199bf4b635e6 arm64: dts: mediatek: Replace deprecated extcon-usb-gpio id-gpio/vbus-gpio properties
73d46717fb3d ARM: dts: qcom: msm8226: Add watchdog node
01815a93d9ab dt-bindings: auxdisplay: hit,hd44780: use defines for GPIO flags
41e657a00f9c dt-bindings: auxdisplay: adjust example indentation and use generic node names
81b0dd090434 arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add initial device trees
3fa556edfd69 arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2
8761bb9477f3 arm64: dts: qcom: sc8180x: describe all PCI MSI interrupts
3419b50ca541 arm64: dts: qcom: minor whitespace cleanup
1a30651d27f6 arm64: dts: qcom: ssm7125-xiaomi: drop incorrect UFS phy max current
8f644a3c370b arm64: dts: qcom: x1e80100-crd: add sound card
22e29ff5c4c3 arm64: dts: x1e80100: correct DMIC2 and DMIC3 pin config node names
b32ccff427b3 arm64: dts: sm8650: correct DMIC2 and DMIC3 pin config node names
8b41c24a5900 arm64: dts: sm8550: correct DMIC2 and DMIC3 pin config node names
d0bad83ec278 arm64: dts: sm8450: correct DMIC2 and DMIC3 pin config node names
736ebb0686f6 arm64: dts: sc8280xp: correct DMIC2 and DMIC3 pin config node names
33ef3b7fb778 dt-bindings: can: tcan4x5x: Document the wakeup-source flag
11322433ed0f dt-bindings: net: dp83826: support TX data voltage tuning
a745442704dd ARM: dts: stm32: lxa-tac: reduce RGMII interface drive strength
bdbd2fbe2a1f arm64: dts: mediatek: replace underscores in node names
bb7b4de1613f pmdomain: Merge branch dt into next
20b8bae8b8eb arm64: dts: ti: k3-am62a: Make the main_conf node a simple-bus
e42f80bc5bcf arm64: dts: ti: k3-am62: Make the main_conf node a simple-bus
8ba7dd15abdd arm64: dts: ti: k3-j7200: Make the FSS node a simple-bus
42ed47d60a80 arm64: dts: ti: k3-j721s2: Convert serdes_ln_ctrl node into reg-mux
bf6f8e6f98e5 arm64: dts: ti: k3-j721s2: Convert usb_serdes_mux node into reg-mux
0167a788d9c5 arm64: dts: ti: k3-j721e: Convert usb_serdes_mux node into reg-mux
124c59a52517 arm64: dts: ti: k3-j721e: Convert serdes_ln_ctrl node into reg-mux
ebb5990bd126 arm64: dts: ti: k3-j7200: Convert usb_serdes_mux node into reg-mux
c0c92c3b24bd arm64: dts: ti: k3-j7200: Convert serdes_ln_ctrl node into reg-mux
8c7e27a256ed arm64: dts: ti: k3-am64: Convert serdes_ln_ctrl node into reg-mux
ecaaf99dee6f arm64: dts: mediatek: mt8186: Add missing xhci clock to usb controllers
546dd2b71775 arm64: dts: mediatek: mt8186: Add missing clocks to ssusb power domains
845392fb2a8c ARM: dts: qcom: msm8960: expressatt: Add mXT224S touchscreen
a5fc0fcda8d3 ARM: dts: qcom: msm8960: Add gsbi3 node
e5357a45e304 ARM: dts: qcom: msm8226: Add CPU and SAW/ACC nodes
df98c13b52f1 ARM: dts: qcom: msm8226: Sort and clean up nodes
4250f1c8ff79 ARM: dts: qcom: msm8974: correct qfprom node size
7d8cff577be7 dt-bindings: arm: qcom,ids: Add IDs for SM8475 family
ee8caed03c87 arm64: dts: qcom: sdm845: Enable cros-ec-spi as wake source
6eef1cbc79c9 arm64: dts: qcom: sc7280: Enable cros-ec-spi as wake source
097f3128d091 arm64: dts: qcom: sc7180: Enable cros-ec-spi as wake source
1a1c9101358c arm64: dts: qcom: sdm845: Use the Low Power Island CX/MX for SLPI
292108e317ec arm64: dts: qcom: msm8996: Define UFS UniPro clock limits
71aab956985a arm64: dts: qcom: qcs6490-rb3gen2: Declare GCC clocks protected
5a7b32324b50 arm64: dts: qcom: sc8280xp-pmics: Define adc for temp-alarms
c7cdefde3890 arm64: dts: qcom: sc8280xp-crd: Add PMIC die-temp vadc channels
fc4657cf641c dt-bindings: net: qca,ar9331: convert to DT schema
f8930a53d1df arm64: dts: rockchip: Add USB3.0 to Indiedroid Nova
5e1a3b5538e5 arm64: dts: rockchip: adjust phy-handle name on rock-pi-e
67a655c02d0c arm64: dts: rockchip: fix rk3399 hdmi ports node
1ce4f570403a arm64: dts: rockchip: fix rk3328 hdmi ports node
fe75fb3e4156 ARM: dts: rockchip: fix rk322x hdmi ports node
d8715fea4366 ARM: dts: rockchip: fix rk3288 hdmi ports node
3693fdfce256 dt-bindings: display: rockchip,dw-hdmi: add power-domains property
a3f511793cc1 dt-bindings: display: rockchip: rockchip,dw-hdmi: remove port property
fdad3ea0d962 arm64: dts: rockchip: remove redundant cd-gpios from rk3588 sdmmc nodes
1619cbd3e975 arm64: dts: rockchip: add rs485 support on uart5 of px30-ringneck-haikou
2134fa3eaa7f arm64: dts: rockchip: add rs485 support on uart2 of rk3399-puma-haikou
7a4285c5d69e arm64: dts: rockchip: Add Powkiddy RGB10MAX3
b9b257004011 dt-bindings: arm: rockchip: Add Powkiddy RGB10MAX3
a3adfa889806 arm64: dts: rockchip: Update powkiddy rk2023 dtsi for RGB10MAX3
8c24e7309a68 dt-bindings: display: rocktech,jh057n00900: Document panel rotation
46ed672258f7 dt-bindings: display: Add Powkiddy RGB10MAX3 panel
01125f93dff3 dt-bindings: soc: rockchip: add rk3588 USB3 syscon
f12733bf8794 dt-bindings: soc: rockchip: add clock to RK3588 VO grf
94e3c5a3f928 docs: dt: writing-schema: document expectations on example DTS
fe91d6f4b5e3 docs: dt: writing-schema: explain additional/unevaluatedProperties
4a3d3359c02d docs: dt: writing-schema: clarify that schema should describe hardware
d91bf686801b dt-bindings: use capital "OR" for multiple licenses in SPDX
496c29b2e9a6 dt-bindings: vendor-prefixes: add smartrg
24ffa3c14c93 dt-bindings: misc: qcom,fastrpc: Compute callbacks can be DMA coherent
0723544f32df dt-bindings: soc: renesas: Preserve the order of SoCs based on their part numbers
a6d969083d23 clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks
1c22386104aa ASoC: dt-bindings: fsl,imx-asrc: convert to YAML
0a4520722599 dt-bindings: timer: renesas: ostm: Document RZ/Five SoC
82515ffc20b0 dt-bindings: mmc: fsl-imx-esdhc: add iommus property
54b4d099b066 dt-bindings: mmc: fsl-imx-esdhc: add i.MX95 compatible string
878060d5ab93 dt-bindings: power: rpmpd: Add MSM8974 power domains
ba7f2dd56d71 arm64: dts: amlogic: t7: minor whitespace cleanup
0e3777330164 Merge tag 'renesas-pinctrl-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
2b637c08d90d arm64: dts: amlogic: axg: initialize default SoC capacitance
56b8815ee298 arm64: dts: amlogic: axg: move cpu cooling-cells to common dtsi
38e9d49495a7 arch: arm64: dts: meson: a1: add assigned-clocks for usb node
04303030d8a7 arm64: dts: amlogic: meson-g12-common: Set the rates of the clocks for the NPU
96f1514933cd arm64: dts: amlogic: add reset controller for Amlogic C3 SoC
b6cee0d8e50c dt-bindings: i2c: mux: i2c-demux-pinctrl: Define "i2c-parent" constraints
cbcbd116c3bb dt-bindings: i2c: mux: i2c-demux-pinctrl: Drop i2c-mux.yaml reference
d21de1b0f205 dt-bindings: can: fsl,flexcan: add i.MX95 compatible string
18dd617a729c ASoC: dt-bindings: cs35l45: Add interrupts
d649337cab0d ASoC: dt-bindings: qcom,sm8250: Allow up to 8 codec DAIs
168cf4050131 arm64: dts: fsd: Add fifosize for UART in Device Tree
c49f54ab8258 arm64: dts: exynos: gs101: minor whitespace cleanup
761c7555e3a6 arm64: dts: mediatek: mt7622: add missing "device_type" to memory nodes
feb82cd75ca1 arm64: dts: mediatek: mt7986: reorder nodes
afeb2b683c6a arm64: dts: mediatek: mt7986: reorder properties
1f41c46b7784 arm64: dts: mediatek: Add Acelink EW-7886CAX
a9e4cb01cbbd dt-bindings: arm64: dts: mediatek: Add Acelink EW-7886CAX access point
a0d0e301bacb dt-bindings: vendor-prefixes: add acelink
6355f4d21fe2 arm64: dts: mediatek: Introduce the MT8395 Radxa NIO 12L board
ad8297de07f0 dt-bindings: arm64: mediatek: Add MT8395 Radxa NIO 12L board compatible
c878dc2878b8 arm64: dts: mediatek: mt8186: Add video decoder device nodes
86ae11dcbfb0 arm64: dts: mediatek: mt8195: Add MTU3 nodes and correctly describe USB
a1bccd014f43 arm64: dts: mediatek: Add MT8186 Magneton Chromebooks
f06a044c7c87 arm64: dts: mediatek: Add MT8186 Steelix platform based Rusty
3d00e9da10ee arm64: dts: mediatek: Introduce MT8186 Steelix
2047c128ed63 arm64: dts: mediatek: Add MT8186 Krabby platform based Tentacruel / Tentacool
0526f7bc6fb8 dt-bindings: arm: mediatek: Add MT8186 Magneton Chromebooks
089e49677706 dt-bindings: arm: mediatek: Add MT8186 Rusty Chromebook
f9d037124e77 dt-bindings: arm: mediatek: Add MT8186 Steelix Chromebook
f5956f4a6314 dt-bindings: arm: mediatek: Add MT8186 Tentacruel / Tentacool Chromebooks
38bba08bb5f5 dt-bindings: arm: mediatek: Sort entries by SoC then board compatibles
ae447c85bffd arm64: dts: mediatek: mt8186: Add jpgenc node
2ee45888f0f1 dt-bindings: media: mediatek-jpeg-encoder: change max iommus count
9dd1d78b9108 arm64: dts: mediatek: mt8186: Add venc node
928e533f64ce arm64: dts: mediatek: mt8186: fix VENC power domain clocks
10ccafc6dfc8 dt-bindings: media: mtk-vcodec-encoder: add compatible for mt8186
a26c81acaef4 arm64: dts: mediatek: mt8192: fix vencoder clock name
6d5ecd0c0bf1 dt-bindings: media: mtk-vcodec-encoder: fix non-vp8 clock name
44858bf6309d arm64: dts: mediatek: Add socinfo efuses to MT8173/83/96/92/95 SoCs
87674b38b34a arm64: dts: mediatek: mt8195: Enable cros-ec-spi as wake source
a5e0493deb44 arm64: dts: mediatek: mt8192: Enable cros-ec-spi as wake source
d8de0db07270 arm64: dts: mediatek: mt8183: Enable cros-ec-spi as wake source
e62bf57bf4ce arm64: dts: mediatek: mt8173: Enable cros-ec-spi as wake source
80f419da8e71 arm64: dts: mediatek: mt7988: add clock controllers
0da54052e647 arm64: dts: mediatek: Add initial MT7988A and BPI-R4
17df9b07965f dt-bindings: arm64: mediatek: Add MT7988A and BPI-R4
58b0724c52ef arm64: dts: mediatek: Add initial MT7981B and Xiaomi AX3000T
f2654823e7da dt-bindings: arm64: mediatek: Add MT7981B and Xiaomi AX3000T
ec60c59a2f5a arm64: dts: mediatek: mt8192-asurada: Remove CrosEC base detection node
4cc812e03139 arm64: dts: mediatek: mt7986: add "#reset-cells" to infracfg
a70fe7a32743 arm64: dts: mediatek: mt7986: drop "#clock-cells" from PWM
08e6a51e82bf arm64: dts: mediatek: mt7986: fix SPI nodename
0ce82b652753 arm64: dts: mediatek: mt7986: fix SPI bus width properties
1654679b7b86 arm64: dts: mediatek: mt7986: drop crypto's unneeded/invalid clock name
0db4b3814808 arm64: dts: mediatek: mt7986: fix reference to PWM in fan node
e14ff64a492a arm64: dts: mt8183: Move CrosEC base detection node to kukui-based DTs
5af22a48d387 dt-bindings: net: qcom,ethqos: add binding doc for safety IRQ for sa8775p
f0efaf410576 dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR register
a31e6ce97f3b dt-bindings: arm: qcom,coresight-tpdm: Add support for CMB element size
42aa700e6b6a Merge tag 'v6.8-rc4' into gpio/for-next
28ff43a9c5cf dt-bindings: hwmon: Add LTC4282 bindings
946976867e95 dt-bindings: hwmon: ina2xx: Describe ina260 chip
60a5255306fa dt-bindings: hwmon: ina2xx: Describe #io-channel-cells property
ccda6b1eb4cb dt-bindings: hwmon: ina2xx: Add label property
29abc2d8cf78 dt-bindings: display: msm: sm8650-mdss: Add missing explicit "additionalProperties"
ca193aa48798 dt-bindings: msm: qcom, mdss: Include ommited fam-b compatible
fb87bba01a93 dt-bindings: dsi-controller-main: Document missing msm8976 compatible
6e32138572e8 dt-bindings: net: Document Qcom QCA807x PHY package
d65891d631e7 dt-bindings: net: document ethernet PHY package nodes
05327165c680 arm64: dts: qcom: qrb4210-rb2: enable USB-C port handling
c48cf2ca774b arm64: dts: qcom: sm6115: drop pipe clock selection
0529c70be68e arm64: dts: qcom: pmi632: define USB-C related blocks
8f3c2d458408 arm64: dts: qcom: qcs6490-rb3gen2: Correct the voltage setting for vph_pwr
f077c9e8cdcc arm64: dts: qcom: qcm6490-idp: Correct the voltage setting for vph_pwr
ed36b9e79976 dt-bindings/perf: Add Arm CoreSight PMU
6bea5f945518 dt-bindings: pinctrl: cy8c95x0: Update gpio-reserved-ranges
ff6ea0429974 dt-bindings: pinctrl: nvidia,tegra234-pinmux: Restructure common schema
f8a5525e9f69 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
b64c0f80d53a spi: get rid of some legacy macros
adfae82db04a spi: dt-bindings: samsung: add google,gs101-spi compatible
7d4159bca342 dt-bindings: mfd: dlg,da9063: Convert da9062 to json-schema
84465d53e06e dt-bindings: mfd: dlg,da9063: Sort child devices
a5d5c9ca95f6 dt-bindings: thermal: Convert da906{1,2} thermal to json-schema
9491d890e23c dt-bindings: input: Convert da906{1,2,3} onkey to json-schema
bf94a53ad831 dt-bindings: mfd: dlg,da9063: Update watchdog child node
5d2f1ff23c1f dt-bindings: mfd: da9062: Update watchdog description
6d63119dedee dt-bindings: soc: qcom: qcom,pmic-glink: document QCM6490 compatible
eadfdbf7cfd7 dt-bindings: i2c: renesas,rcar-i2c: Add r8a779h0 support
506140c4b36b dt-bindings: i2c: pca954x: Add custom properties for MAX7357
a3cf64f59235 arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole
66fd6a721305 arm64: dts: exynos: gs101: define USI12 with I2C configuration
bc3a8ffe73f6 arm64: dts: exynos: gs101: enable cmu-peric1 clock controller
85f5d68af4a0 Merge tag 'samsung-dt-bindings-clk-6.9-3' into next/dt64
eff597e8d6d7 Merge branch '20240131-ufs-phy-clock-v3-3-58a49d2f4605@linaro.org' into clk-for-6.9
9d58463252f8 Merge branch '20240125-msm8953-mdss-reset-v2-1-fd7824559426@z3ntu.xyz' into clk-for-6.9
53156f9a9b8b dt-bindings: samsung: exynos-sysreg: gs101-peric0/1 require a clock
f0fc02f810bc Merge tag 'samsung-dt-bindings-clk-6.9-3' into next/clk
3a17e325742d dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
f8f976624cd6 ASoC: dt-bindings: atmel,asoc-wm8904: Convert to json-schema
e07e6605bd92 ARM: dts: samsung: exynos5420-galaxy-tab-common: add wifi node
833d20d41eff dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
0aff1be67191 dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200
61354e32b738 dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1
0ed441cb60fc Merge drm/drm-next into drm-misc-next
fa4e28b76a28 dt-bindings: phy: qmp-ufs: Fix PHY clocks
edf14e92f825 dt-bindings: fsl-dma: fsl-edma: add fsl,imx95-edma5 compatible string
db56af9d1adc dt-bindings: mmp-dma: convert to YAML
69f5e9afcf9a arm64: dts: qcom: sc8280xp: Introduce additional tsens instances
d34aa18b328e arm64: dts: qcom: sm8550-hdk: correct WCD9385 route and port mapping
c5ac3bf2b9e9 arm64: dts: qcom: sm8650: Fix UFS PHY clocks
960dc14fb417 arm64: dts: qcom: sm8550: Fix UFS PHY clocks
5b487a71e59a arm64: dts: qcom: sm8350: Fix UFS PHY clocks
1019d3b3dd76 arm64: dts: qcom: sc8280xp: Fix UFS PHY clocks
d909cc2c57f0 arm64: dts: qcom: sc8180x: Fix UFS PHY clocks
32798a824479 Merge branch '20240131-ufs-phy-clock-v3-3-58a49d2f4605@linaro.org' into HEAD
647fc2ed0999 dt-bindings: trivial-devices: sort entries alphanumerically
d87ada5ab8a5 arm64: dts: qcom: sm8250: Fix UFS PHY clocks
71ea2327fa6f arm64: dts: qcom: sm8150: Fix UFS PHY clocks
64da7648e2cd arm64: dts: qcom: sm6350: Fix UFS PHY clocks
fd0f61fefaf5 arm64: dts: qcom: sm6125: Fix UFS PHY clocks
4d7ec8559332 arm64: dts: qcom: sm6115: Fix UFS PHY clocks
1b77533e4915 arm64: dts: qcom: sdm845: Fix UFS PHY clocks
18872b4ddd5f arm64: dts: qcom: msm8998: Fix UFS PHY clocks
9a197a6489bc arm64: dts: qcom: msm8996: Fix UFS PHY clocks
1c92660aee2a dt-bindings: clock: qcom: Add missing UFS QREF clocks
a20d2718cc23 arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node
6ed4e54f3d0a arm64: dts: qcom: qrb2210-rb1: disable cluster power domains
1816222d14d0 arm64: dts: qcom: msm8953: Add GPU
289d949a2fa0 arm64: dts: qcom: msm8953: Add GPU IOMMU
d8789c7d4887 arm64: dts: qcom: msm8953: add reset for display subsystem
e3e73e0578cb Merge branch '20240125-msm8953-mdss-reset-v2-1-fd7824559426@z3ntu.xyz' into arm64-for-6.9
6beb0be6d4fc dt-bindings: clock: gcc-msm8953: add more resets
f84a5b88e932 arm64: dts: qcom: sm8650-mtp: add Audio sound card node
92c1bbcc400a arm64: dts: qcom: sm8650-qrd: add Audio nodes
b0e0830701c8 arm64: dts: qcom: sm8650: Add dma-coherent property
d16840039a98 arm64: dts: qcom: sm8550: Add dma-coherent property
f515a57656b3 arm64: dts: qcom: sm8650-qrd: add PM8010 regulators
03371084ea86 arm64: dts: qcom: sm8650-mtp: add PM8010 regulators
a5d205597cdb arm64: dts: qcom: ipq6018: add thermal zones
a536a392c199 arm64: dts: qcom: ipq6018: add tsens node
93475982136a arm64: dts: qcom: sm8550-mtp: add correct analogue microphones
94d226438171 arm64: dts: qcom: sm8550-qrd: add correct analogue microphones
da9e6dd17060 arm64: dts: qcom: sm8550-mtp: correct WCD9385 TX port mapping
19f3548ab2ee arm64: dts: qcom: sm8550-qrd: correct WCD9385 TX port mapping
70387c1a6e20 arm64: dts: qcom: sm6350: Add tsens thermal zones
14a45c7e6691 arm64: dts: qcom: sm6115: declare VLS CLAMP register for USB3 PHY
62ceca9a978f arm64: dts: qcom: qcm2290: declare VLS CLAMP register for USB3 PHY
1243c8cd7c3d arm64: dts: qcom: msm8998: declare VLS CLAMP register for USB3 PHY
41b532e3d8fb arm64: dts: qcom: sc7280: Update domain-idle-states for cluster sleep
9067770d28da arm64: dts: qcom: sdm630-nile: Enable and configure PM660L WLED
59950318f199 dt-bindings: arm: qcom: drop the superfluous device compatibility schema
5906b6dbb4b8 arm64: dts: qcom: sm8650: add missing qlink_logging reserved memory for mpss
1a5594201259 arm64: dts: qcom: ipq9574: Enable Inline Crypto Engine for MMC
6c5dcfe50eeb arm64: dts: qcom: x1e80100-crd: add WSA8845 speakers
641aa52f01a1 arm64: dts: qcom: x1e80100-crd: add WCD9385 Audio Codec
adad71a77e32 arm64: dts: qcom: x1e80100: add Soundwire controllers
fcb540f3e31d arm64: dts: qcom: x1e80100: add ADSP audio codec macros
fe7149ac0fe1 arm64: dts: qcom: x1e80100: add LPASS LPI pin controller
89656eaec676 arm64: dts: qcom: x1e80100: add ADSP GPR
a24c8ba00dac dt-bindings: remoteproc: qcom,sm8550-pas: document the SM8650 PAS
552c8b9c51bd riscv: dts: microchip: add specific compatible for mpfs pdma
0359a2873d27 arm64: dts: qcom: ipq6018: add QUP5 I2C node
2109082a047e arm64: dts: qcom: x1e80100-qcp: Fix supplies for LDOs 3E and 2J
ad5e70a893a6 arm64: dts: qcom: x1e80100-qcp: Enable more support
70e1e5caf55a arm64: dts: qcom: x1e80100-crd: Enable more support
e7f823deb502 arm64: dts: qcom: x1e80100: Add display nodes
09888df4cabf arm64: dts: qcom: x1e80100: Add PCIe nodes
113e1447c4b7 arm64: dts: qcom: x1e80100: Add USB nodes
d042016c875e arm64: dts: qcom: x1e80100: Add TCSR node
1e12a915f76a arm64: dts: qcom: x1e80100: Add ADSP/CDSP remoteproc nodes
21784a99d799 arm64: dts: qcom: x1e80100: Add QMP AOSS node
adac34e54b92 arm64: dts: qcom: x1e80100: Add SMP2P nodes
f6ae972c7d7a arm64: dts: qcom: x1e80100: Add IPCC node
f858f5571e59 Merge branch '20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org' into arm64-for-6.9
16f9c84b0c9a Merge branch '20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org' into clk-for-6.9
77ff05b89311 dt-bindings: clock: qcom: Document the X1E80100 Camera Clock Controller
9b09558a4d02 dt-bindings: clock: qcom: Document the X1E80100 TCSR Clock Controller
009188ad89c1 dt-bindings: clock: qcom: Document the X1E80100 GPU Clock Controller
619f14d3ee00 dt-bindings: clock: qcom: Document the X1E80100 Display Clock Controller
5c691ea9dfde dt-bindings: clock: Drop the SM8650 DISPCC dedicated schema
fd99a9349fc8 dt-bindings: soc: qcom: qcom,pmic-glink: document X1E80100 compatible
3de725e88fb0 arm64: dts: qcom: sa8775p: Add new memory map updates to SA8775P
62872aebbbd8 dt-bindings: soc: imx: add missing clock and power-domains to imx8mp-hdmi-blk-ctrl
4ff28e3e2d94 ASoC: dt-bindings: atmel,sam9x5-wm8731: Convert to json-schema
906cab843596 riscv: dts: microchip: add missing CAN bus clocks
70bee5f22413 dt-bindings: can: mpfs: add missing required clock
91d53111ca13 dt-bindings: clock: mpfs: add more MSSPLL output definitions
7564dfecdf9e Revert "media: ov08x40: Reduce start streaming time"
230eabe62cac arm64: dts: ti: iot2050*: Clarify GPL-2.0 as GPL-2.0-only
81c25598663e arm64: dts: ti: phycore*: Add MIT license along with GPL-2.0
49ad241d7ba0 arm64: dts: ti: beagle*: Add MIT license along with GPL-2.0
af13011bc32a arm64: dts: ti: k3-serdes: Add MIT license along with GPL-2.0
97f615d94c52 arm64: dts: ti: k3-pinctrl: Add MIT license along with GPL-2.0
fb7c92cfa0d7 arm64: dts: ti: k3-j784s4: Add MIT license along with GPL-2.0
ef720a09d820 arm64: dts: ti: k3-j721s2: Add MIT license along with GPL-2.0
b5d3132ac896 arm64: dts: ti: k3-j721e: Add MIT license along with GPL-2.0
a08b6e3c500d arm64: dts: ti: k3-j7200: Add MIT license along with GPL-2.0
67b92cb4a9b8 arm64: dts: ti: k3-am65: Add MIT license along with GPL-2.0
4270ef124316 arm64: dts: ti: k3-am64: Add MIT license along with GPL-2.0
6bbb88ff7998 arm64: dts: ti: k3-am62p: Add MIT license along with GPL-2.0
0ffeaa9662f1 arm64: dts: ti: k3-am625: Add MIT license along with GPL-2.0
5db4fd731c54 arm64: dts: ti: k3-am62a7: Add MIT license along with GPL-2.0
99e9047746eb arm64: dts: ti: Use https for urls
3fa55a728a3d arm64: dts: imx8mn-evk: Add PDM micphone sound card support
8d8a62fd968d arm64: dts: imx8mm-evk: Add PDM micphone sound card support
151935e24c16 arm64: dts: imx8qm: add smmu stream id information
7ca27214673d arm64: dts: imx8qm: add smmu node
b9f9b709c278 arm64: dts: imx8dxl-evk: add flexcan2 and flecan3
f42aa20f9119 arm64: dts: imx8dxl-evk: add i2c3 and its children nodes
93d6366b8356 arm64: dts: imx8dxl: update flexcan[1-3] interrupt number
c5d90c61def2 arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support
16c8d47dc262 arm64: dts: imx8mn-rve-gateway: remove redundant company name
b08765c243bb dt-bindings: arm: fsl: remove redundant company name
65cffffa0551 ARM: dts: samsung: exynos5420-galaxy-tab: decrease available memory
d01b22a61768 dt-bindings: ata: atmel: remove at91 compact flash documentation
d242043d9d60 arm64: dts: renesas: gray-hawk-single: Enable watchdog timer
2e8d8e405f93 arm64: dts: renesas: r8a779h0: Add RWDT node
35665cd38eb8 arm64: dts: renesas: Improve TMU interrupt descriptions
6c5ee3279bcd ARM: dts: renesas: Improve TMU interrupt descriptions
78e358d25cba ARM: dts: imx6ull-dhcom: Remove /omit-if-no-ref/ from node usdhc1-pwrseq
f53c235dce4f arm64: dts: freescale: imx8qm: add apalis eval v1.2 carrier board
c6a20bf4953d dt-bindings: arm: fsl: add imx8qm apalis eval v1.2 carrier board
4a2797e6299b dt-bindings: display: imx: add binding for i.MX8MP HDMI TX
46daefc82714 arm64: dts: exynos: Add SPI nodes for Exynos850
864d0966e626 ARM: dts: imx: Add support for Apalis Evaluation Board v1.2
ab38fa94e38c dt-bindings: arm: fsl: Add toradex,apalis_imx6q-eval-v1.2 board
79c6446e27a7 ARM: dts: imx6: skov: add aliases for all ethernet nodes
00cba1b18156 arm64: dts: imx93: Add phyBOARD-Segin-i.MX93 support
ee42eae10f7a dt-bindings: arm: fsl: Add phyBOARD-Segin-i.MX93
1dcb02c43ac3 arm64: dts: imx8mp: Enable PCIe to Data Modul i.MX8M Plus eDM SBC
c35148dd66cc dt-bindings: firmware: xilinx: Describe soc-nvmem subnode
e4d158a009f2 arm64: dts: ls1012a: fix DWC3 USB VBUS glitch issue
2cc69dbdcc3b arm64: dts: ls1012a: add gpio for i2c bus recovery
86f029cb9916 arm64: dts: ls1012a: add big-endian property for PCIe nodes
1344dd97c94d arm64: dts: ls1012a: correct the size of dcfg block
eebf4e8a4de5 arm64: dts: ti: k3-j7200: use ti,j7200-padconf compatible
b2c927e92eb5 arm64: dts: ti: k3-am62p-mcu/wakeup: Disable MCU and wakeup R5FSS nodes
1ed877819eca arm64: dts: ti: k3-am69-sk: remove assigned-clock-parents for unused VP
b2e13a92bcd3 dt-bindings: drm/bridge: ti-sn65dsi86: Fix bouncing @codeaurora address
5aafe0eb29a5 dt-bindings: mux: restrict node name suffixes
959645b1cb6f ARM: dts: keystone: Replace http urls with https
9c307f485cc5 arm64: dts: ti: k3-am62a7-sk: Add HDMI support
33aa21cb5f84 arm64: dts: ti: k3-am62a-main: Add node for Display SubSystem (DSS)
e197413922a3 arm64: dts: ti: phycore-am64: Add ADC
cbb614f03fe0 arm64: dts: ti: k3-j784s4: Fix power domain for VTM node
4979495296af arm64: dts: ti: k3-j721s2: Fix power domain for VTM node
66f98925474a arm64: dts: ti: k3-am62p5-sk: Enable CPSW MDIO node
8af95677c0a4 arm64: dts: ti: k3-j7200: Add support for multiple CAN instances
3416ecb8c84b arm64: dts: ti: k3-j7200-som-p0: Add support for CAN instance 0 in main domain
b190cdb39a78 arm64: dts: ti: k3-j7200: Add support for CAN nodes
049925dbe4ef arm64: dts: ti: verdin-am62: mallow: add TPM device
d18d4a279eac arm64: dts: ti: k3-am64: Remove PCIe endpoint node
45e8e613d391 arm64: dts: ti: k3-am65: Remove PCIe endpoint nodes
9482566d8484 arm64: dts: ti: k3-j7200: Remove PCIe endpoint node
f2db5b44a21b arm64: dts: ti: k3-j7200: Enable PCIe nodes at the board level
1b1b2953ae47 arm64: dts: ti: k3-j721s2-som-p0: Do not split single items
1ab381b19847 arm64: dts: ti: k3-j721e-som-p0: Do not split single items
3bbf314c8e51 arm64: dts: ti: k3-j721e-sk: Do not split single items
9982ca1fa62d arm64: dts: ti: k3-j721e-beagleboneai64: Do not split single items
685e4624960e arm64: dts: ti: k3-j7200-som-p0: Do not split single items
bb743de0d3fe arm64: dts: ti: k3-am69-sk: Do not split single items
6081c21a3e9b arm64: dts: ti: k3-am68-sk-som: Do not split single items
7aebe586ccdc arm64: dts: ti: k3-am654-base-board: Do not split single items
756750059f96 arm64: dts: ti: iot2050: Do not split single items
83cac2593e26 arm64: dts: ti: k3-am642-sk: Do not split single items
c266381d0608 arm64: dts: ti: k3-am642-evm: Do not split single items
ff6e034104fc arm64: dts: ti: k3-am642-phyboard-electra: Add TPM support
986edbf094b5 arm64: dts: ti: Disable clock output of the ethernet PHY
140c5468b668 arm64: dts: ti: Add phase tags for memory node on J784S4 EVM and AM69 SK
fb6ffd10b764 arm64: dts: ti: k3-am625-beagleplay: Use the builtin mdio bus
abed090f1e99 arm64: dts: ti: k3-am625-beagleplay: Add boot phase tags for USB0
0424a17ecb7a arm64: dts: ti: k3-am625-sk: Add boot phase tags for USB0
ac8143f3b013 dt-bindings: mtd: avoid automatically select from mtd.yaml
828b9467f60f media: dt-bindings: techwell,tw9900: Fix port schema ref
2b2619e4c6c5 dt-bindings: display: imx: add binding for i.MX8MP HDMI PVI
141f2102cc12 ARM: dts: imx6qdl-hummingboard: Add rtc0 and rtc1 aliases to fix hctosys
ffe7dc298435 arm64: dts: imx93: drop "master" I3C node name suffix
99af7a0dae65 ARM: dts: imx6dl: Add support for Sielaff i.MX6 Solo board
ff6929d462c4 dt-bindings: arm: fsl: Add Sielaff i.MX6 Solo board
d3413ad34a12 arm64: dts: freescale: tqma9352: Update I2C eeprom compatible
ad2d1ba26a13 arm64: dts: imx8mp: reparent MEDIA_MIPI_PHY1_REF to CLK_24M
3b589ade448f dt-bindings: gpio: pca9570: Add label property
11eb3d98d38b dt-bindings: gpio: mvebu: Fix "unevaluatedProperties" to be false
9c0a4b40a3ac ARM: dts: imx6ul: Add missing #thermal-sensor-cells to tempmon
fee43501308a arm64: dts: imx8mp-verdin: Label ldo5 and link to usdhc2
b8d7d5f3690b arm64: dts: imx93-var-som: Add Variscite VAR-SOM-MX93
188a8bb94d35 dt-bindings: arm: fsl: Add VAR-SOM-MX93 with Symphony
fecb422bac6a arm64: dts: ls1046a: Remove big-endian from thermal
78343d7acd50 ARM: dts: imx6sl-tolino-shine2hd: fix touchscreen rotation
e57037e98946 ARM: dts: imx6ull-dhcor: Remove 900MHz operating point
31d9e29f0d8e Merge tag 'drm-misc-next-2024-01-11' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
e6d71526460e dt-bindings: misc: xlnx,sd-fec: convert bindings to yaml
01b5de94aa82 Merge 6.8-rc3 into tty-next
7030aa5067b6 Merge 6.8-rc3 into usb-next
5f856030cc8b arm64: dts: rockchip: Add devicetree for Pine64 PineTab2
c87344c32c61 dt-bindings: arm64: rockchip: Add Pine64 PineTab2
6944e5df2f35 arm64: dts: rockchip: Add Touch to Anbernic RG-ARC D
9a90efccd7ee ARM: dts: microchip: gardena-smart-gateway: Use DMA for USART3
9a2b5d99e0ff ARM: dts: microchip: at91sam9x5ek: Use DMA for DBGU serial port
7051d52cf5b9 arm64: dts: imx8mp-venice-gw71xx: add TPM device
4ecbc5946cc5 arm64: dts: imx8mm-venice-gw71xx: add TPM device
3c805459dfd7 arm64: dts: imx8mm-venice-gw71xx: fix USB OTG VBUS
af9118771e3c arm64: dts: imx8mm-venice-gw7901: add TPM device
bcc4aff9ee00 arm64: dts: imx8mm-venice-gw7901: add digital I/O direction control GPIO's
6ea0c6a49b64 ARM: dts: imx7-tqma7: Fix PMIC v33 rail voltage range
2482c75bff8e ARM: dts: imx7-mba7: Add missing vcc supply to i2c devices
4d19ec066c6b ARM: dts: imx7-tqma7: Add missing vcc supply to i2c eeproms
fda2672c8e68 ARM: dts: imx7d-mba7: Remove USB OTG related properties on USB node
f71b70123d20 ARM: dts: imx7-tqma7: rename node for SE97BTP
56382af8168e ARM: dts: imx7-tqma7: mark system data eeprom as read-only
59c9c040a0db ARM: dts: imx7-tqma7: remove superfluous status property
ac9f05a3b8ee ARM: dts: imx7-tqma7: restrict usdhc interface modes
54b93adb1393 ARM: dts: imx7-mba7: restrict usdhc interface modes
6980af2d9f17 ARM: dts: imx7-tqma7: Fix iomuxc node names
efad19cdde77 ARM: dts: imx7-mba7: Fix iomuxc node names
fe330835b74e ARM: dts: imx7-tqma7: fix EEPROM compatible for SE97BTP
77f6e05fdfa1 ARM: dts: imx7-mba7: Add i2c bus recovery
8f9993282d52 ARM: dts: imx7-tqma7: Add i2c bus recovery
4065cdaa82bd ARM: dts: imx7-mba7: Add SPI1_SS0 as chip select 3
10cde7452d93 ARM: dts: imx7-mba7: Add RTC aliases
67c6d0e81520 ARM: dts: imx7-mba7: Enable SNVS power key
2ccae767cb74 ARM: dts: imx7-mba7: Mark gpio-buttons as wakeup-source
235e861d016e ARM: dts: imx7[d]-mba7: hog Mini PCIe signals
cd553893ac90 ARM: dts: imx7[d]-mba7: disable PCIe interface
2faa76d25aef ARM: dts: imx7[d]-mba7: disable USB OC on USB host and USB OTG2
f9152233518d ARM: dts: imx7[d]-mba7: Move ethernet PHY reset into PHY node
0d8f0cba144c ARM: dts: imx7-tqma7/mba7: convert fsl,pins to uint32-matrix
c09e630c5912 arm64: dts: qcom: qcm6490-idp: Include PM7250B
edd0bc8b8d0b arm64: dts: qcom: sm8650: Use GIC-ITS for PCIe0 and PCIe1
4fe52e68f13c arm64: dts: qcom: qcm6490-idp: Add definition for three LEDs
cc592e051541 arm64: dts: qcom: sm8650-qrd: add USB-C Altmode Support
b789944a89fc arm64: dts: qcom: sm8550-qrd: enable Touchscreen
200b0b3875ef dt-bindings: clock: qcom: Fix @codeaurora email in Q6SSTOP
5eaa8712fb96 dt-bindings: visionox-rm69299: Update maintainers
ae0b823f0536 dt-bindings: gpio: renesas,rcar-gpio: Add r8a779h0 support
d4458c6492e6 dt-bindings: net: ti: Update maintainers list
a3fa7f3f82f7 dt-bindings: net: ipq4019-mdio: document now supported clock-frequency
9c3280cd3020 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
19adc3b90590 Merge branch '20240201204421.16992-2-quic_amelende@quicinc.com' into drivers-for-6.9
b5c560279d08 dt-bindings: soc: qcom: Add qcom,pbs bindings
08d014730db7 regulator: dt-bindings: microchip,mcp16502: convert to YAML
bdef327947f5 arm64: dts: intel: agilex5: drop "master" I3C node name suffix
1c0d4ea255ee media: ov08x40: Reduce start streaming time
7d92af412d2e arm64: dts: exynos: Add PDMA node for Exynos850
1868ee800d4c arm64: dts: exynos: gs101: use correct clocks for usi_uart
5d5769f28954 arm64: dts: exynos: gs101: use correct clocks for usi8
dc00c7274ea6 dt-bindings: net: dsa: Add KSZ8567 switch support
58475bd50ec5 media: arm64: dts: st: add video encoder support to stm32mp255
380408454fb2 media: arm64: dts: st: add video decoder support to stm32mp255
4eea1b53e82e media: dt-bindings: media: Document STM32MP25 VDEC & VENC video codecs
39ecce7ee54a arm64: dts: imx8qxp: add GPU nodes
b206b48e8a91 arm64: dts: imx8qm: Correct edma3 power-domains and interrupt numbers
7a74326b4893 arm64: dts: imx8qm: Align edma3 power-domains resources indentation
0be926d25dbc arm64: dts: imx8qxp: mba8xx: Add analog audio output on MBa8Xx
43aab34e5e0c arm64: dts: imx8qxp: Add mclkout clock gates
8c7666d283be arm64: dts: imx8qxp: Add audio SAI nodes
a12fa3d0c150 arm64: dts: imx8qxp: Add audio clock mux node
6c44f7583fd5 arm64: dts: imx8qxp: Add ACM input clock gates
cf7ea553fe5a arm64: dts: freescale: add initial device tree for TQMa8Xx
98de130e34e4 dt-bindings: arm: add TQMa8Xx boards
dc089f5f4bb0 arm64: dts: imx: add imx8dxp support
a5a40554f207 dt-bindings: net: qcom,ipa: do not override firmware-name $ref
927f00767ef5 arm64: dts: imx8mm-kontron: Refactor devicetree for OSM-S module and board
dc0c1bca1831 arm64: dts: imx8mm-kontron: Add I2C EEPROM on OSM-S Kontron i.MX8MM
071edd561a01 arm64: dts: imx8mm-kontron: Remove useless trickle-diode-disable from RTC node
bc9a25d78a35 arm64: dts: imx8mm-kontron: Disable uneffective PUE bit in SDIO IOMUX
48e6dc42724c arm64: dts: imx8mm-kontron: Fix OSM-S devicetrees to match latest hardware
1749a50ca797 arm64: dts: imx8mm-kontron: Fix interrupt for RTC on OSM-S i.MX8MM module
6985d8cd5c40 arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL board
688fff06ac4e arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL OSM-S board
4b8efdb73a46 arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL board
123efe05e212 arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL OSM-S board
9f02292756b9 arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on SL/BL i.MX8MM
928dc77f0003 arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on OSM-S i.MX8MM
c2b4ecb58452 dt-bindings: fpga: Convert fpga-region binding to yaml
85d6c583d5f5 MAINTAINERS: Drop my "+dt" sub-address
0f6ed4032e99 dt-bindings: timer: renesas,tmu: Document input capture interrupt
05c9f46083ba arm64: dts: renesas: r9a07g043u: Add CSI and CRU nodes
aa403cfc2a6c arm64: dts: renesas: Add Gray Hawk Single board support
82a8a0a3e608 arm64: dts: renesas: Add Renesas R8A779H0 SoC support
356004f72bd0 Merge tag 'renesas-r8a779h0-dt-binding-defs-tag' into renesas-dts-for-v6.9
1200029387ce arm64: dts: renesas: rzg3s-smarc-som: Enable the watchdog interface
d58eb8846937 arm64: dts: renesas: r9a08g045: Add watchdog node
b1de14ce277c arm64: dts: renesas: r8a779g0: Add missing SCIF_CLK2
fe98cda6e099 dt-bindings: soc: renesas: Document R-Car V4M Gray Hawk Single
bcdc951ea508 dt-bindings: reset: renesas,rst: Document R-Car V4M support
55647b66aba2 pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28
fc9d9f1cfef8 dt-bindings: interconnect: Remove bogus interconnect nodes
47509af4504a soundwire/SOF: add SoundWire Interface support for
f521b204bcd2 dt-bindings: interconnect: Add Qualcomm MSM8909 DT bindings
72ececa06e31 riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio
0279da4a6715 riscv: dts: starfive: visionfive-v1: Setup ethernet phy
19f7725fe372 riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac
d05053a8b239 riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes
921e5e1327ef dt-bindings: net: starfive,jh7110-dwmac: Add JH7100 SoC compatible
7020ebc26757 dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions
35d633af4efc dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support
1de76ced2497 dt-bindings: soc: xilinx: Add support for KV260 CC
c9aeb5c33863 dt-bindings: soc: xilinx: Add support for K26 rev2 SOMs
e36f379d8c82 dt-bindings: pinctr: pinctrl-zynq: Fix compatible string
c7a574ba2a6c dt-bindings: pinctrl: nuvoton,npcm845: Drop redundant type for "slew-rate"
da1b37add707 dt-bindings: pinctrl: Unify "input-debounce" schema
234d836b6a1a dt-bindings: input: document Goodix Berlin Touchscreen IC
8df2aa5a1297 arm64: dts: qcom: Add support for Xiaomi Redmi Note 9S
5c09bd2b6ce1 arm64: dts: qcom: sm7125-xiaomi-common: Add UFS nodes
5c38e796a3a1 arm64: dts: qcom: sc7180: Add UFS nodes
307cdcc3f9c2 dt-bindings: arm: qcom: Add Xiaomi Redmi Note 9S
d9eda103eb64 ARM: dts: qcom: apq8026-lg-lenok: Add vibrator support
2590e420cf2c ARM: dts: qcom: msm8960: expressatt: Add gpio-keys
9d906fe262e0 arm64: dts: qcom: sda660-ifc6560: enable USB 3.0 PHY
6b10b59bd1db arm64: dts: qcom: sdm630: add USB QMP PHY support
329fb714e840 arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definition
ca14c11bb9a4 arm64: dts: qcom: sc8280xp: camss: Add CCI definitions
5ce7895c7b2b dt-bindings: clock: qcom: Allow VDD_GFX supply to GX
3a9a9247f661 arm64: dts: qcom: sa8295p-adp: Enable GPU
08f93d65d530 arm64: dts: qcom: sa8295p-adp: add max20411
1129eea99cc1 arm64: dts: qcom: sa8540p: Drop gfx.lvl as power-domain for gpucc
14bc12ecdfe3 dt-bindings: interrupt-controller: convert MediaTek sysirq to the json-schema
77a4323bd64f dt-bindings: dma: allwinner,sun50i-a64-dma: Add compatible for H616
82bf0037e8d8 dt-bindings: power: Add r8a779h0 SYSC power domain definitions
d98d5e6ce56e dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support
5ee26dab625b dt-bindings: bus: Document Broadcom GISB arbiter 74165 compatible
c6234d82a072 arm64: dts: broadcom: bcmbca: bcm4908: drop invalid switch cells
bc4ef25abdc1 arm64: dts: broadcom: bcmbca: bcm4908: use NVMEM layout for Asus GT-AC5300
b6e08822ed8c arm64: dts: renesas: r8a779g2: Add White Hawk Single support
7e3862db4c62 arm64: dts: renesas: Add Renesas R8A779G2 SoC support
51fc2376ba1d arm64: dts: renesas: white-hawk: Factor out common parts
a248c1746935 arm64: dts: renesas: white-hawk-cpu: Factor out common parts
fdea5d785497 arm64: dts: renesas: white-hawk: Add SoC name to top-level comment
a77e323e0dc2 arm64: dts: renesas: white-hawk: Drop SoC parts from sub boards
3e8f05b2b81d arm64: dts: renesas: white-hawk-cpu: Restore sort order
e90ffb9d53b7 arm64: dts: renesas: r8a779g0: Add standalone White Hawk CPU support
eccddc31dfa9 arm64: dts: renesas: ulcb-kf: Add node for GNSS
3d3e628e12d6 arm64: dts: renesas: ulcb-kf: Drop duplicate 3.3v regulators
bf721e67a7fb Merge drm/drm-next into drm-misc-next
351548ba8841 dt-bindings: soc: renesas: Document R-Car V4H White Hawk Single
ad352af0d46f dt-bindings: nfc: ti,trf7970a: fix usage example
d4d212c5cf34 dt-bindings: display: panel-simple: add ETML1010G3DRA
6aee668021fc arm64: dts: qcom: sm7225-fairphone-fp4: Switch firmware ext to .mbn
aa54779772ae arm64: dts: qcom: rename PM2250 to PM4125
dbcb19ed3275 arm64: dts: qcom: qcm6490-fairphone-fp5: Add PMIC GLINK
dc376fa4a27c arm64: dts: qcom: sdm845-oneplus-common: improve DAI node naming
048423deb9a5 arm64: dts: qcom: qcm6490-fairphone-fp5: Add missing reserved-memory
b4d0c1c61afa arm64: dts: qcom: sc7280: Add static properties to cryptobam
f3f780c01899 arm64: dts: qcom: sa8775p: enable safety IRQ
fd61cbbd53a9 dt-bindings: clock: qcom,gcc-sm8150: Add gcc video resets for sm8150
30e2fa95b585 dt-bindings: arm: qcom,ids: add SoC ID for QCM8550 and QCS8550
27f4e6aa609c dt-bindings: Add reference to rs485.yaml
5e11848e4c98 dt-bindings: serial: renesas,hscif: Document r8a779h0 bindings
c7aaa6160c61 dt-bindings: serial: fsl-lpuart: support i.MX95
3ee8c19304d9 dt-bindings: serial: samsung: do not allow reg-io-width for gs101
d70fdb79f945 arm64: dts: qcom: apq8016-sbc-d3-camera: Use more generic node names
95830229bcb5 ARM: dts: qcom: msm8960: drop 2nd clock frequency from timer
4f433e3e9a04 ARM: dts: qcom: ipq4019-ap.dk01.1: align flash node with bindings
39065990752b ARM: dts: qcom: ipq4019-ap.dk01.1: use existing labels for nodes
a6106c8748a7 arm64: dts: qcom: split PCIe interrupt-names entries per lines
f1ac2340280d arm64: dts: qcom: sm8650: describe all PCI MSI interrupts
653638c9dceb arm64: dts: qcom: sm8550: describe all PCI MSI interrupts
90840a974369 arm64: dts: qcom: sm8450: describe all PCI MSI interrupts
c681c8ad796c arm64: dts: qcom: sm8350: describe all PCI MSI interrupts
9186fa649278 arm64: dts: qcom: sm8250: describe all PCI MSI interrupts
a2e5b5e27b91 arm64: dts: qcom: sm8150: describe all PCI MSI interrupts
ed0b4f3e69ba ARM: dts: qcom: msm8926-htc-memul: Add rmtfs memory node
3556e0895e7a dt-bindings: usb: dwc3: Add snps,host-vbus-glitches-quirk avoid vbus glitch
75bae0c78ef3 dt-bindings: usb: usb-nop-xceiv: Repurpose vbus-regulator
20e5fb946959 dt-bindings: usb: mtu3: Add MT8195 MTU3 ip-sleep support
0145e6824861 dt-bindings: usb: Clean-up "usb-phy" constraints
eb9bdcaff280 dt-bindings: usb: add common Type-C USB Switch schema
a67690a90fb9 dt-bindings: usb: Add Marvell ac5
59434babb8e4 arm64: dts: qcom: sm8450: Add missing interconnects to serial
6b60607aa5cc dt-bindings: usb: Introduce ITE IT5205 Alt. Mode Passive MUX
fe0ce9c54778 dt-bindings: pinctrl: amlogic: narrow regex for unit address to hex numbers
8c58779baca1 dt-bindings: qcom: Document new msm8916-samsung devices
1438aadecf94 arm64: dts: qcom: sm8450-hdk: correct AMIC4 and AMIC5 microphones
b4d502118ad4 arm64: dts: qcom: sm8150: add necessary ref clock to PCIe
018a13d36a57 arm64: dts: qcom: sdm630: Hook up GPU cooling device
2b51fa0934c8 arm64: dts: qcom: sm8550: Hook up GPU cooling device
15018cdc0470 arm64: dts: qcom: sm8450: Hook up GPU cooling device
f5906fc26422 arm64: dts: qcom: sm8350: Hook up GPU cooling device
9df3c73a8511 arm64: dts: qcom: sm8250: Hook up GPU cooling device
257e0300ca3a arm64: dts: qcom: sm8150: Hook up GPU cooling device
b16301e27866 arm64: dts: qcom: sm6115: Mark GPU @ 125C critical
ccc769ffd9fa arm64: dts: qcom: sm6115: Hook up GPU cooling device
cf4e80b514f2 arm64: dts: qcom: sdm845: Hook up GPU cooling device
6ddaa894ac00 arm64: dts: qcom: sc8180x: Hook up GPU cooling device
1a13cc6e08c9 arm64: dts: qcom: msm8939: Hook up GPU cooling device
04962e8ee80d arm64: dts: qcom: msm8916: Hook up GPU cooling device
de58665d5a86 arm64: dts: qcom: x1e80100: Flush RSC sleep & wake votes
5792135ff692 arm64: dts: qcom: x1e80100: Add missing system-wide PSCI power domain
7dddf3cf2c2d dt-bindings: soc/qcom: Add size constraints on "qcom,rpm-msg-ram"
f3e26b603762 arm64: dts: qcom: Add missing interrupts for qcs404/ipq5332
d2eb087d6a3f arm64: dts: qcom: Fix hs_phy_irq for SDM670/SDM845/SM6350
e912f5a885bc arm64: dts: qcom: Fix hs_phy_irq for non-QUSB2 targets
cc58f6b02229 arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
ed2747597b2e arm64: dts: qcom: sm8550: add support for the SM8550-HDK board
0beb12a79761 dt-bindings: arm: qcom: Document the HDK8550 board
1182dc50de01 dt-bindings: net: Document QCA808x PHYs
8869fe2b8c59 dt-bindings: net: phy: Document LED inactive high impedance mode
8a5d470f446f dt-bindings: net: phy: Make LED active-low property common
ee170c770dce ASoC: dt-bindings: audio-graph-port: Drop type from "clocks"
52dc7498eed1 ASoC: dt-bindings: samsung,tm2: Correct "audio-codec" constraints
2294f77ec0a5 ARM: dts: sti: minor whitespace cleanup around '='
e8f034522bd8 arm64: dts: exynos: gs101: sysreg_peric0 needs a clock
d7849025c947 ARM: dts: da850: add MMD SDIO interrupts
f831c925b07a ARM: dts: marvell: dove-cubox: fix si5351 node names
70e16db126d5 arm: dts: marvell: Fix maxium->maxim typo in brownstone dts
29fba2976ec3 dt-bindings: crypto: ice: Document SC7180 inline crypto engine
3d331a17e8c9 dt-bindings: qcom-qce: Add compatible for SM6350
4fd1499f0d02 arm64: dts: ti: k3-am654-main: Add device tree entry for SGX GPU
459e64009a83 ARM: dts: DRA7xx: Add device tree entry for SGX GPU
33828a263695 ARM: dts: AM437x: Add device tree entry for SGX GPU
b812a94b3a14 ARM: dts: AM33xx: Add device tree entry for SGX GPU
a43b7f4412c3 ARM: dts: omap5: Add device tree entry for SGX GPU
26a571cb3312 ARM: dts: omap4: Add device tree entry for SGX GPU
0590991057c3 ARM: dts: omap3: Add device tree entry for SGX GPU
6cfc912186fd dt-bindings: gpu: Add PowerVR Series5 SGX GPUs
ecd5e84cb911 dt-bindings: gpu: Rename img,powervr to img,powervr-rogue
674fba836cdb arm64: dts: rockchip: fix nanopc-t6 sdmmc regulator
33b030710624 arm64: dts: rockchip: remove duplicate SPI aliases for helios64
7c0fd87b35a8 arm64: dts: rockchip: add spi controller aliases on rk3399
774db835de8a arm64: dts: rockchip: Add support for NanoPi R6C
245ed9f66edb arm64: dts: rockchip: Add support for NanoPi R6S
7ed25d8d0d24 dt-bindings: arm: rockchip: Add NanoPi R6 series boards
4fc6e0686faf arm64: dts: rockchip: Increase maximum frequency of SPI flash for ROCK Pi 4A/B/C
47aafd8512e1 arm64: dts: rockchip: add sdmmc card detect to the nanopc-t6
5bdf0ecf003d arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3399
3d67b6c2a2af ARM: dts: rockchip: Enable HDMI output for XPI-3128
8ac6f9cf696a ARM: dts: rockchip: Add HDMI node for RK3128
06cbcacf56ad ARM: dts: rockchip: Add display subsystem for RK3128
9a9dc5b9e06a arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b
c7f1c6bb420a arm64: dts: rockchip: enable NanoPC-T6 MiniPCIe power
9604142e6a0d arm64: dts: rockchip: Add LED_GREEN for edgeble-neu6a
cbd461ded362 arm64: dts: rockchip: Add Edgeble NCM6A-IO USB2
051aa218e679 arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 B-Key, E-Key
e24b6c90f78b arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key
c04566174738 arm64: dts: rockchip: Add Edgeble NCM6A-IO 2.5G ETH
1696541973b9 arm64: dts: rockchip: Add vdd_cpu_big reg to rk3588-edgeble-ncm6
fed4b47f48ac arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 Overlay
648060033a16 arm64: dts: rockchip: Add common DT for edgeble-neu6b-io
14b26b2835cb arm64: dts: rockchip: Add edgeble-neu6a-common DT
8360c7a53f95 arm64: dts: rockchip: Drop edgeble-neu6b dcdc-reg4 regulator-init-microvolt
e497dc0158dd arm64: dts: rockchip: add missing definition of pmu io domains 1 and 2 on ringneck
f1cb710d9302 arm64: dts: rockchip: add Anbernic RG-ARC S and RG-ARC D
351c26e7934f dt-bindings: arm: rockchip: Add Anbernic RG-Arc
294dd835c5d0 arm64: dts: rockchip: Move device specific properties
e8f6b6072ce6 dt-bindings: soc: rockchip: Add rk3588 hdptxphy syscon
663d347eb7a7 ARM: dts: stm32: fix DSI peripheral clock on stm32mp15 boards
6e307e6bd72d dt-bindings: memory-controllers: narrow regex for unit address to hex numbers
ef93727c9def spi: dt-bindings: samsung: Add Exynos850 SPI
c714a4c1273b ARM: dts: qcom: use defines for interrupts
7f37d45ff70d ARM: dts: qcom: apq8026-samsung-matissewifi: Configure touch keys
cf76727f86a3 ARM: dts: stm32: lxa-tac: drive powerboard lines as open-drain
19fee3189355 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHYs
899bb26cef2c dt-bindings: iio: adc: rtq6056: add support for the whole RTQ6056 family
09065a127e3c dt-bindings: input: melfas,mms114: add MMS252 compatible
ef76ae751c3c dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support SDM660
97fd9e67ede2 dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: add TCSR registers
25bfbe442a13 dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support USB-C data
6ec985dff442 dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: split from sc8280xp PHY schema
8b41b5f06d8a arm64: dts: exynos: gs101: enable eeprom on gs101-oriole
eb43c96a2716 arm64: dts: exynos: gs101: define USI8 with I2C configuration
688d19a4c1d5 arm64: dts: exynos: gs101: update USI UART to use peric0 clocks
c8631c01c9d5 arm64: dts: exynos: gs101: enable cmu-peric0 clock controller
7f078f4efe48 arm64: dts: exynos: gs101: remove reg-io-width from serial
dfa299ac5670 arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node
dd8d6cdb498f dt-bindings: clock: tesla,fsd: Fix spelling mistake
2a50cd8b4cad Merge tag 'samsung-dt-bindings-clk-6.9-2' into next/clk
1308a1709db2 dt-bindings: clock: exynos850: Add PDMA clocks
5f252cf1954d dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit
b7045107b13d dt-bindings: phy: Add QMP UFS PHY compatible for SC7180
806828c18886 arm64: dts: qcom: sc8180x: Add RPMh sleep stats
8bfa57f18d67 arm64: dts: qcom: sc8180x: Shrink aoss_qmp register space size
39124f597a6a arm64: dts: qcom: sc8180x: Add missing CPU<->MDP_CFG path
076044c5542f arm64: dts: qcom: sc8180x: Require LOW_SVS vote for MMCX if DISPCC is on
76f855a9dca6 arm64: dts: qcom: sc8180x: Don't hold MDP core clock at FMAX
37f3285d146b arm64: dts: qcom: sc8180x: Fix eDP PHY power-domains
5e5b25b16167 arm64: dts: qcom: sc8180x: Add missing CPU off state
a971a001fe6a arm64: dts: qcom: sc8180x: Fix up big CPU idle state entry latency
d43c023044f1 arm64: dts: qcom: sc8180x: Hook up VDD_CX as GCC parent domain
0a90e0fc5c4b dt-bindings: clock: gcc-sc8180x: Add the missing CX power domain
7d930fbfa6d1 riscv: dts: starfive: jh7110: Add PWM node and pins configuration
98729d5d619d riscv: dts: starfive: jh7100: Add PWM node and pins configuration
2613a64bdc5e dt-bindings: spi: nxp-fspi: support i.MX93 and i.MX95
36d4b81404af dt-bindings: spi: fsl-lpspi: support i.MX95 LPSPI
3ff4d525b9f7 ASoC: dt-bindings: fsl-sai: Support Rx-only SAI
fc98068e41fe ASoC: dt-bindings: fsl-sai: Add power-domains
7e4487f7e723 ASoC: Support SAI and MICFIL on i.MX95 platform
170639843215 dt-bindings: iio: pressure: honeywell,mprls0025pa.yaml add spi bus
e06b0404e4ef dt-bindings: iio: pressure: honeywell,mprls0025pa.yaml add pressure-triplet
cb500c9133ee dt-bindings: iio: pressure: honeywell,mprls0025pa.yaml improvements
0c9fbdab661d dt-bindings: iio: light: as73211: add support for as7331
668faa4c00b6 ARM: dts: qcom: ipq4019: correct clock order in DWC3 node
01f571222843 ARM: dts: qcom: sdx65: correct clock order in DWC3 node
f0606dbf1b06 ARM: dts: qcom: ipq8064: drop unused reset-names from DWC3 node
638f430aa2c5 arm64: dts: qcom: qcm6490-fairphone-fp5: Enable venus node
2bf14ff2de89 arm64: dts: qcom: sc7280: Move video-firmware to chrome-common
e694053a2504 arm64: dts: qcom: x1e80100: drop qcom,drv-count
ae0bc4781d25 arm64: dts: qcom: sc7280: Add additional MSI interrupts
fbc40e8570be dt-bindings: pwm: Add bindings for OpenCores PWM Controller
f86a5abc5095 ASoC: codecs: add support for WCD939x Codec
0023860e3cd8 dt-bindings: Add DPS310 as trivial device
4d5cba356b2e docs: dt: submitting-patches: add commit subject prefix in reversed format
86c6d04414f3 docs: dt: submitting-patches: drop outdated points to TXT format
20fea215870b dt-bindings: Turn on undocumented compatible checks
c15bd0d0ea0d arm64: zynqmp: Align usb clock nodes with binding
506404184883 arm64: zynqmp: Comment all smmu entries
702fb0df1a8d arm64: zynqmp: Rename i2c?-gpio to i2c?-gpio-grp
8dae08d3ef0c arm64: zynqmp: Disable Tri-state for MIO38 Pin
08cee7c9acca arm64: zynqmp: Remove incorrect comment from kv260s
c28bc39bcbe4 arm64: zynqmp: Introduce u-boot options node with bootscr-address
346b5266ae26 arm64: zynqmp: Fix comment to be aligned with board name.
69a088e616d5 arm64: zynqmp: Update ECAM size to discover up to 256 buses
c78a834d7d85 arm64: zynqmp: Describe assigned-clocks for uarts
aab3209386cd arm64: zynqmp: Setup default si570 frequency to 156.25MHz
70d8c607c90e arm64: zynqmp: Add resets property for CAN nodes
1e662bbad32e arm64: zynqmp: Add an OP-TEE node to the device tree
b97de3d1f0f1 arm64: zynqmp: Add output-enable pins to SOMs
5149181eb2a0 arm64: zynqmp: Rename zynqmp-power node to power-management
4bbdddd5f137 dt-bindings: firmware: xilinx: Sort node names (clock-controller)
bbe26a5d3a74 dt-bindings: firmware: xilinx: Describe missing child nodes
3bb58ba1f178 dt-bindings: firmware: xilinx: Fix versal-fpga node name
552578beff16 dt-bindings: firmware: versal: add versal-net compatible string
a1e42c2d1feb dt-bindings: timer: exynos4210-mct: Add google,gs101-mct compatible
793923947260 dt-bindings: i2c: exynos5: add google,gs101-hsi2c compatible
e40d0f28e904 ARM: dts: samsung: exynos4412-p4note: add accelerometer and gyro to p4note
b0f7ebf9ebb5 ARM: dts: samsung: exynos5800-peach: Enable cros-ec-spi as wake source
7fb70f62fdc1 ARM: dts: samsung: exynos5420-peach: Enable cros-ec-spi as wake source
69ffe89c1f09 ARM: dts: samsung: exynos5422-odroidxu3: disable thermal polling
efc6740c2555 arm64: dts: renesas: r8a779g0: Restore sort order
4d29837048f1 ARM: dts: renesas: r8a73a4: Fix thermal parent clock
b3b5e2c31a6a ARM: dts: renesas: r8a73a4: Add cp clock
0355cc519d58 ARM: dts: renesas: r8a73a4: Fix external clocks and clock rate
c7faddebe0f9 arm64: dts: renesas: rzg3s-smarc: Add gpio keys
cf58f575cc98 dt-bindings: regulator: Convert ti,tps65132 to YAML
fc588d5d53ae ASoC: dt-bindings: Do not override firmware-name $ref
81002cf24ea5 ASoC: dt-bindings: document WCD939x Audio Codec
f47aa77e7a94 ASoC: dt-bindings: qcom,wcd938x: move out common properties
d7f07526a034 ASoC: dt-bindings: fsl,micfil: Add compatible string for i.MX95 platform
e4fa9d184d78 ASoC: dt-bindings: fsl,sai: Add compatible string for i.MX95 platform
6d65dad20b03 dt-bindings: input: touchscreen: goodix: clarify irq-gpios misleading text
1f08757666ca dt-bindings: input: silead,gsl1680: do not override firmware-name $ref
ffc68c88254b dt-bindings: display: panel: Add Novatek NT36672E LCD DSI
22dafcaa7945 dt-bindings: display: panel: Add BOE TH101MB31IG002-28A panel
29e394c3abcd dt-bindings: nt35510: add compatible for FRIDA FRD400B25025-A-CTK
c378224488e5 dt-bindings: display: Add SSD133x OLED controllers
d4d009fba537 dt-bindings: display: ssd132x: Add vendor prefix to width and height
b74c86bcffbc dt-bindings: display: ssd1307fb: Add vendor prefix to width and height
140b66753a95 dt-bindings: panel: lvds: Append edt,etml0700z9ndha in panel-lvds
git-subtree-dir: dts/upstream
git-subtree-split: 7e08733c96c84eb323f47e9b248c924e2ac6272a
---
This moves OF_UPSTREAM to be tracking the v6.9 release and is for the
-next branch. To test these changes yourself locally, either use my
"WIP/14May2024-next" branch or run:
./dts/update-dts-subtree.sh pull v6.9-dts
yourself locally. I intend to wait a few days to apply this to -next, to
give people time to test.
Cc: Adam Ford <aford173@gmail.com>
Cc: Apurva Nandan <a-nandan@ti.com>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Cc: Bryan Brattlof <bb@ti.com>
Cc: Caleb Connolly <caleb.connolly@linaro.org>
Cc: Christian Hewitt <christianshewitt@gmail.com>
Cc: "Cogent Embedded, Inc." <source@cogentembedded.com>
Cc: Dave Purdy <david.c.purdy@gmail.com>
Cc: Evgeni Dobrev <evgeni@studio-punkt.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jason Cooper <u-boot@lakedaemon.net>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Luka Perkov <luka@openwrt.org>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Marek Vasut <marek.vasut+renesas@mailbox.org>
Cc: Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Cc: Paul Barker <paul.barker.ct@bp.renesas.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Siddarth Gore <gores@marvell.com>
Cc: Simon Guinot <simon.guinot@sequanux.org>
Cc: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Cc: Stefan Roese <sr@denx.de>
Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Tony Dinh <mibodhi@gmail.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Vyacheslav Bocharov <adeep@lexina.in>
Cc: Wadim Egorov <w.egorov@phytec.de>
Cc: Walter Schweizer <swwa@users.sourceforge.net>
Cc: u-boot-amlogic@groups.io
Cc: u-boot-qcom@groups.io
Bindings/Makefile | 3 -
Bindings/arm/amlogic.yaml | 15 +-
Bindings/arm/arm,realview.yaml | 6 +-
Bindings/arm/atmel-at91.yaml | 6 +
Bindings/arm/fsl.yaml | 41 +-
Bindings/arm/marvell/armada-38x.txt | 27 -
Bindings/arm/marvell/armada-38x.yaml | 70 +
Bindings/arm/mediatek.yaml | 198 +-
Bindings/arm/mediatek/mediatek,hifsys.txt | 26 -
Bindings/arm/mediatek/mediatek,pciesys.txt | 25 -
Bindings/arm/mediatek/mediatek,ssusbsys.txt | 25 -
Bindings/arm/msm/qcom,saw2.txt | 58 -
Bindings/arm/qcom,coresight-tpdm.yaml | 40 +-
Bindings/arm/qcom.yaml | 58 +-
Bindings/arm/rockchip.yaml | 71 +-
Bindings/arm/sunxi.yaml | 12 +
Bindings/arm/syna.txt | 12 -
Bindings/arm/tegra.yaml | 8 +
Bindings/arm/tegra/nvidia,tegra186-pmc.yaml | 58 +-
Bindings/arm/ti/k3.yaml | 14 +
Bindings/ata/ahci-mtk.txt | 51 -
Bindings/ata/atmel-at91_cf.txt | 19 -
Bindings/ata/mediatek,mtk-ahci.yaml | 98 +
Bindings/auxdisplay/arm,versatile-lcd.yaml | 4 +-
Bindings/auxdisplay/gpio-7-segment.yaml | 55 +
Bindings/auxdisplay/hit,hd44780.yaml | 68 +-
Bindings/auxdisplay/holtek,ht16k33.yaml | 54 +-
Bindings/auxdisplay/img,ascii-lcd.yaml | 4 +-
Bindings/auxdisplay/maxim,max6959.yaml | 44 +
Bindings/bus/brcm,gisb-arb.yaml | 1 +
Bindings/bus/imx-weim.txt | 117 -
Bindings/clock/google,gs101-clock.yaml | 28 +-
Bindings/clock/keystone-gate.txt | 2 -
Bindings/clock/keystone-pll.txt | 2 -
Bindings/clock/mediatek,mt2701-hifsys.yaml | 50 +
Bindings/clock/mediatek,mt7622-pciesys.yaml | 45 +
Bindings/clock/mediatek,mt7622-ssusbsys.yaml | 45 +
Bindings/clock/mobileye,eyeq5-clk.yaml | 51 +
Bindings/clock/qcom,gcc-sc8180x.yaml | 7 +
Bindings/clock/qcom,gpucc.yaml | 9 +
Bindings/clock/qcom,q6sstopcc.yaml | 2 +-
Bindings/clock/qcom,sc7180-mss.yaml | 61 -
Bindings/clock/qcom,sm8450-camcc.yaml | 2 +
Bindings/clock/qcom,sm8450-gpucc.yaml | 2 +
Bindings/clock/qcom,sm8550-dispcc.yaml | 7 +-
Bindings/clock/qcom,sm8550-tcsr.yaml | 1 +
Bindings/clock/qcom,sm8650-dispcc.yaml | 106 -
Bindings/clock/renesas,cpg-mssr.yaml | 1 +
Bindings/clock/samsung,exynos850-clock.yaml | 42 +
Bindings/clock/tesla,fsd-clock.yaml | 2 +-
Bindings/clock/ti/adpll.txt | 2 -
Bindings/clock/ti/apll.txt | 2 -
Bindings/clock/ti/autoidle.txt | 2 -
Bindings/clock/ti/clockdomain.txt | 2 -
Bindings/clock/ti/composite.txt | 2 -
Bindings/clock/ti/divider.txt | 2 -
Bindings/clock/ti/dpll.txt | 2 -
Bindings/clock/ti/fapll.txt | 2 -
Bindings/clock/ti/fixed-factor-clock.txt | 2 -
Bindings/clock/ti/gate.txt | 2 -
Bindings/clock/ti/interface.txt | 2 -
Bindings/clock/ti/mux.txt | 2 -
Bindings/crypto/atmel,at91sam9g46-aes.yaml | 6 +-
Bindings/crypto/atmel,at91sam9g46-sha.yaml | 6 +-
Bindings/crypto/atmel,at91sam9g46-tdes.yaml | 6 +-
.../crypto/qcom,inline-crypto-engine.yaml | 1 +
Bindings/crypto/qcom-qce.yaml | 1 +
.../atmel/atmel,hlcdc-display-controller.yaml | 63 +
Bindings/display/atmel/hlcdc-dc.txt | 75 -
.../display/bridge/fsl,imx8mp-hdmi-tx.yaml | 102 +
Bindings/display/bridge/ti,sn65dsi86.yaml | 2 +-
Bindings/display/fsl,lcdif.yaml | 8 +-
Bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml | 84 +
Bindings/display/msm/dsi-controller-main.yaml | 2 +
Bindings/display/msm/gmu.yaml | 1 +
Bindings/display/msm/gpu.yaml | 6 +-
Bindings/display/msm/qcom,mdss.yaml | 1 +
Bindings/display/msm/qcom,sm8150-mdss.yaml | 9 +
Bindings/display/msm/qcom,sm8650-dpu.yaml | 4 +-
Bindings/display/msm/qcom,sm8650-mdss.yaml | 4 +
Bindings/display/msm/qcom,x1e80100-mdss.yaml | 251 ++
.../display/panel/boe,th101mb31ig002-28a.yaml | 58 +
Bindings/display/panel/himax,hx83112a.yaml | 74 +
.../display/panel/leadtek,ltk500hd1829.yaml | 4 +-
Bindings/display/panel/novatek,nt35510.yaml | 5 +-
Bindings/display/panel/novatek,nt36672e.yaml | 66 +
Bindings/display/panel/panel-lvds.yaml | 4 +
Bindings/display/panel/panel-simple.yaml | 4 +
.../display/panel/rocktech,jh057n00900.yaml | 3 +
Bindings/display/panel/visionox,r66451.yaml | 2 +-
Bindings/display/panel/visionox,rm69299.yaml | 3 +-
Bindings/display/renesas,rzg2l-du.yaml | 126 +
.../display/rockchip/rockchip,dw-hdmi.yaml | 33 +-
Bindings/display/solomon,ssd1307fb.yaml | 20 +-
Bindings/display/solomon,ssd132x.yaml | 12 +-
Bindings/display/solomon,ssd133x.yaml | 45 +
Bindings/display/ti/ti,am65x-dss.yaml | 7 +-
Bindings/dma/allwinner,sun50i-a64-dma.yaml | 12 +-
Bindings/dma/fsl,edma.yaml | 2 +
Bindings/dma/fsl,imx-sdma.yaml | 3 +-
Bindings/dma/marvell,mmp-dma.yaml | 72 +
Bindings/dma/mediatek,mt7622-hsdma.yaml | 63 +
Bindings/dma/mmp-dma.txt | 81 -
Bindings/dma/mtk-hsdma.txt | 33 -
Bindings/dma/renesas,rcar-dmac.yaml | 1 +
Bindings/dts-coding-style.rst | 2 +
Bindings/eeprom/at24.yaml | 5 +-
.../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 96 +-
Bindings/fpga/fpga-region.txt | 479 ----
Bindings/fpga/fpga-region.yaml | 358 +++
Bindings/fpga/xlnx,versal-fpga.yaml | 2 +-
Bindings/gpio/aspeed,ast2400-gpio.yaml | 148 +
Bindings/gpio/gateworks,pld-gpio.txt | 3 +-
Bindings/gpio/gpio-aspeed.txt | 39 -
Bindings/gpio/gpio-mvebu.yaml | 2 +-
Bindings/gpio/gpio-nmk.txt | 31 -
Bindings/gpio/gpio-pca9570.yaml | 3 +
Bindings/gpio/mrvl-gpio.yaml | 2 +-
Bindings/gpio/renesas,rcar-gpio.yaml | 1 +
Bindings/gpio/st,nomadik-gpio.yaml | 95 +
...mg,powervr.yaml => img,powervr-rogue.yaml} | 4 +-
Bindings/gpu/img,powervr-sgx.yaml | 138 +
Bindings/hwmon/adi,adm1177.yaml | 5 +-
Bindings/hwmon/adi,adm1275.yaml | 7 +-
Bindings/hwmon/adi,ltc2945.yaml | 5 +-
Bindings/hwmon/adi,ltc4282.yaml | 159 ++
Bindings/hwmon/amphenol,chipcap2.yaml | 77 +
Bindings/hwmon/aspeed,g6-pwm-tach.yaml | 71 +
Bindings/hwmon/fan-common.yaml | 79 +
Bindings/hwmon/hwmon-common.yaml | 19 +
Bindings/hwmon/lltc,ltc4151.yaml | 5 +-
Bindings/hwmon/lltc,ltc4286.yaml | 9 +-
Bindings/hwmon/lm75.yaml | 3 +-
Bindings/hwmon/nuvoton,nct6775.yaml | 1 +
Bindings/hwmon/pmbus/infineon,tda38640.yaml | 28 +
Bindings/hwmon/pmbus/ti,lm25066.yaml | 17 +-
Bindings/hwmon/ti,ina2xx.yaml | 11 +-
Bindings/hwmon/ti,tmp513.yaml | 5 +-
Bindings/hwmon/ti,tps23861.yaml | 5 +-
Bindings/i2c/atmel,at91sam-i2c.yaml | 4 +-
Bindings/i2c/i2c-demux-pinctrl.yaml | 3 +-
Bindings/i2c/i2c-exynos5.yaml | 1 +
Bindings/i2c/i2c-imx-lpi2c.yaml | 1 +
Bindings/i2c/i2c-mpc.yaml | 2 +-
Bindings/i2c/i2c-mux-pca954x.yaml | 30 +
Bindings/i2c/i2c-pxa.yaml | 2 +-
Bindings/i2c/i2c.txt | 151 -
Bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml | 3 +-
Bindings/i2c/qcom,i2c-cci.yaml | 2 +-
Bindings/i2c/renesas,rcar-i2c.yaml | 1 +
Bindings/i2c/st,nomadik-i2c.yaml | 49 +-
Bindings/i3c/aspeed,ast2600-i3c.yaml | 2 +-
Bindings/i3c/cdns,i3c-master.yaml | 2 +-
Bindings/i3c/i3c.yaml | 6 +-
Bindings/i3c/mipi-i3c-hci.yaml | 2 +-
Bindings/i3c/silvaco,i3c-master.yaml | 2 +-
Bindings/i3c/snps,dw-i3c-master.yaml | 2 +-
Bindings/iio/adc/adc.yaml | 1 -
Bindings/iio/adc/adi,ad9467.yaml | 4 +
Bindings/iio/adc/adi,axi-adc.yaml | 8 +-
Bindings/iio/adc/microchip,pac1934.yaml | 120 +
Bindings/iio/adc/nxp,imx93-adc.yaml | 4 +-
Bindings/iio/adc/qcom,spmi-vadc.yaml | 1 -
Bindings/iio/adc/richtek,rtq6056.yaml | 9 +-
Bindings/iio/adc/ti,ads1298.yaml | 80 +
Bindings/iio/afe/voltage-divider.yaml | 11 +
Bindings/iio/amplifiers/adi,hmc425a.yaml | 47 +-
Bindings/iio/frequency/adi,admfm2000.yaml | 127 +
Bindings/iio/gyroscope/bosch,bmg160.yaml | 8 +-
Bindings/iio/health/maxim,max30102.yaml | 2 +-
Bindings/iio/humidity/ti,hdc2010.yaml | 3 +
Bindings/iio/humidity/ti,hdc3020.yaml | 3 +
Bindings/iio/imu/st,lsm6dsx.yaml | 4 +-
Bindings/iio/light/ams,as73211.yaml | 7 +-
Bindings/iio/light/vishay,veml6075.yaml | 1 +
.../iio/magnetometer/voltafield,af8133j.yaml | 60 +
Bindings/iio/pressure/honeywell,hsc030pa.yaml | 3 +
.../iio/pressure/honeywell,mprls0025pa.yaml | 98 +-
Bindings/iio/temperature/ti,tmp117.yaml | 8 +
.../input/allwinner,sun4i-a10-lradc-keys.yaml | 1 -
Bindings/input/atmel,captouch.txt | 36 -
Bindings/input/atmel,captouch.yaml | 59 +
Bindings/input/da9062-onkey.txt | 47 -
Bindings/input/dlg,da9062-onkey.yaml | 38 +
Bindings/input/samsung,s3c6410-keypad.yaml | 121 +
Bindings/input/samsung-keypad.txt | 77 -
.../input/touchscreen/fsl,imx6ul-tsc.yaml | 97 +
Bindings/input/touchscreen/goodix,gt9916.yaml | 95 +
Bindings/input/touchscreen/goodix.yaml | 5 +-
.../input/touchscreen/imagis,ist3038c.yaml | 21 +-
Bindings/input/touchscreen/imx6ul_tsc.txt | 38 -
Bindings/input/touchscreen/melfas,mms114.yaml | 6 +-
.../input/touchscreen/silead,gsl1680.yaml | 2 +-
Bindings/interconnect/qcom,rpm.yaml | 3 +
Bindings/interconnect/qcom,rpmh.yaml | 2 +-
Bindings/interconnect/qcom,sm7150-rpmh.yaml | 84 +
.../amlogic,meson-gpio-intc.yaml | 1 +
Bindings/interrupt-controller/atmel,aic.txt | 43 -
Bindings/interrupt-controller/atmel,aic.yaml | 89 +
Bindings/interrupt-controller/fsl,intmux.yaml | 3 +
.../mediatek,mt6577-sysirq.yaml | 85 +
.../interrupt-controller/mediatek,sysirq.txt | 44 -
.../renesas,rzg2l-irqc.yaml | 44 +-
.../starfive,jh8100-intc.yaml | 61 +
Bindings/iommu/arm,smmu.yaml | 20 +-
Bindings/leds/backlight/kinetic,ktd2801.yaml | 46 +
Bindings/leds/backlight/qcom-wled.yaml | 4 +-
Bindings/leds/common.yaml | 12 +
Bindings/leds/leds-bcm63138.yaml | 4 -
Bindings/leds/leds-bcm6328.yaml | 4 -
Bindings/leds/leds-bcm6358.txt | 2 -
Bindings/leds/leds-pwm-multicolor.yaml | 4 +-
Bindings/leds/leds-pwm.yaml | 5 -
Bindings/leds/leds-qcom-lpg.yaml | 102 +-
Bindings/leds/onnn,ncp5623.yaml | 96 +
Bindings/mailbox/fsl,mu.yaml | 58 +-
Bindings/media/i2c/techwell,tw9900.yaml | 2 +-
Bindings/media/mediatek,vcodec-encoder.yaml | 31 +-
Bindings/media/mediatek-jpeg-encoder.yaml | 3 +-
Bindings/media/rockchip-isp1.yaml | 37 +-
Bindings/media/st,stm32mp25-video-codec.yaml | 49 +
.../fsl/fsl,imx-weim-peripherals.yaml | 31 +
.../memory-controllers/fsl/fsl,imx-weim.yaml | 204 ++
.../mc-peripheral-props.yaml | 1 +
.../nvidia,tegra20-emc.yaml | 2 +-
.../memory-controllers/renesas,rpc-if.yaml | 1 +
.../memory-controllers/st,stm32-fmc2-ebi.yaml | 7 +-
Bindings/mfd/atmel,hlcdc.yaml | 99 +
Bindings/mfd/atmel,sama5d2-flexcom.yaml | 99 +
Bindings/mfd/atmel-flexcom.txt | 64 -
Bindings/mfd/atmel-hlcdc.txt | 56 -
Bindings/mfd/da9062.txt | 124 -
Bindings/mfd/dlg,da9063.yaml | 251 +-
Bindings/mfd/google,cros-ec.yaml | 7 +
Bindings/mfd/iqs62x.yaml | 2 +-
Bindings/mfd/qcom,tcsr.yaml | 2 +
Bindings/mfd/syscon.yaml | 3 +
Bindings/mfd/ti,twl.yaml | 2 +
Bindings/mips/cpus.yaml | 13 +-
Bindings/mips/mobileye.yaml | 32 +
Bindings/misc/qcom,fastrpc.yaml | 2 +
Bindings/misc/xlnx,sd-fec.txt | 58 -
Bindings/misc/xlnx,sd-fec.yaml | 140 +
Bindings/mmc/fsl-imx-esdhc.yaml | 11 +-
Bindings/mmc/fsl-imx-mmc.yaml | 12 +
Bindings/mmc/hi3798cv200-dw-mshc.txt | 40 -
.../mmc/hisilicon,hi3798cv200-dw-mshc.yaml | 97 +
Bindings/mmc/renesas,sdhi.yaml | 1 +
Bindings/mmc/snps,dwcmshc-sdhci.yaml | 2 +
Bindings/mtd/atmel-nand.txt | 1 +
Bindings/mtd/brcm,brcmnand.yaml | 44 +-
Bindings/mtd/davinci-nand.txt | 2 +-
Bindings/mtd/flctl-nand.txt | 2 +-
Bindings/mtd/fsl-upm-nand.txt | 2 +-
Bindings/mtd/gpio-control-nand.txt | 2 +-
Bindings/mtd/gpmi-nand.yaml | 2 +-
Bindings/mtd/hisi504-nand.txt | 2 +-
Bindings/mtd/jedec,spi-nor.yaml | 3 +
Bindings/mtd/mtd.yaml | 2 +
Bindings/mtd/nvidia-tegra20-nand.txt | 2 +-
Bindings/mtd/orion-nand.txt | 2 +-
Bindings/mtd/partitions/linux,ubi.yaml | 75 +
Bindings/mtd/partitions/ubi-volume.yaml | 40 +
Bindings/mtd/samsung-s3c2410.txt | 2 +-
Bindings/mtd/st,stm32-fmc2-nand.yaml | 25 +-
Bindings/mux/mux-controller.yaml | 2 +-
.../net/bluetooth/qualcomm-bluetooth.yaml | 8 +-
Bindings/net/brcm,asp-v2.0.yaml | 4 +
Bindings/net/brcm,unimac-mdio.yaml | 1 +
Bindings/net/can/fsl,flexcan.yaml | 3 +
Bindings/net/can/microchip,mpfs-can.yaml | 6 +-
Bindings/net/can/tcan4x5x.txt | 3 +
Bindings/net/can/xilinx,can.yaml | 5 +
Bindings/net/cdns,macb.yaml | 5 +
Bindings/net/dsa/ar9331.txt | 147 -
Bindings/net/dsa/microchip,ksz.yaml | 1 +
Bindings/net/dsa/qca,ar9331.yaml | 161 ++
Bindings/net/dsa/realtek.yaml | 4 +-
Bindings/net/ethernet-controller.yaml | 1 -
Bindings/net/ethernet-phy-package.yaml | 52 +
Bindings/net/fsl,fec.yaml | 3 +
Bindings/net/mediatek,net.yaml | 22 +-
Bindings/net/nfc/ti,trf7970a.yaml | 2 +-
Bindings/net/qca,qca808x.yaml | 54 +
Bindings/net/qcom,ethqos.yaml | 9 +-
Bindings/net/qcom,ipa.yaml | 2 +-
Bindings/net/qcom,ipq4019-mdio.yaml | 15 +
Bindings/net/qcom,qca807x.yaml | 184 ++
Bindings/net/renesas,etheravb.yaml | 1 +
Bindings/net/snps,dwmac.yaml | 17 +-
Bindings/net/starfive,jh7110-dwmac.yaml | 72 +-
Bindings/net/ti,cpsw-switch.yaml | 5 +-
Bindings/net/ti,dp83822.yaml | 34 +
Bindings/net/ti,k3-am654-cpsw-nuss.yaml | 5 +-
Bindings/net/ti,k3-am654-cpts.yaml | 5 +-
Bindings/net/wireless/mediatek,mt76.yaml | 33 +-
Bindings/net/wireless/qcom,ath10k.yaml | 1 +
Bindings/net/wireless/qcom,ath11k-pci.yaml | 1 +
Bindings/net/wireless/qcom,ath11k.yaml | 1 +
Bindings/nvmem/layouts/fixed-cell.yaml | 22 +-
Bindings/nvmem/nvmem-provider.yaml | 18 +
Bindings/nvmem/xlnx,zynqmp-nvmem.txt | 46 -
Bindings/nvmem/xlnx,zynqmp-nvmem.yaml | 42 +
Bindings/opp/opp-v2-base.yaml | 2 -
Bindings/pci/fsl,imx6q-pcie-common.yaml | 17 +-
Bindings/pci/fsl,imx6q-pcie-ep.yaml | 46 +-
Bindings/pci/fsl,imx6q-pcie.yaml | 49 +-
Bindings/pci/qcom,pcie-common.yaml | 100 +
Bindings/pci/qcom,pcie-sa8775p.yaml | 166 ++
Bindings/pci/qcom,pcie-sc7280.yaml | 166 ++
Bindings/pci/qcom,pcie-sc8180x.yaml | 170 ++
Bindings/pci/qcom,pcie-sc8280xp.yaml | 180 ++
Bindings/pci/qcom,pcie-sm8150.yaml | 158 +
Bindings/pci/qcom,pcie-sm8250.yaml | 173 ++
Bindings/pci/qcom,pcie-sm8350.yaml | 184 ++
Bindings/pci/qcom,pcie-sm8450.yaml | 178 ++
Bindings/pci/qcom,pcie-sm8550.yaml | 171 ++
Bindings/pci/qcom,pcie-x1e80100.yaml | 165 ++
Bindings/pci/qcom,pcie.yaml | 378 +--
Bindings/perf/arm,coresight-pmu.yaml | 39 +
.../perf/starfive,jh8100-starlink-pmu.yaml | 46 +
Bindings/phy/mediatek,mt8365-csi-rx.yaml | 79 +
Bindings/phy/phy-cadence-torrent.yaml | 11 +-
Bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 184 ++
Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 6 +
Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 48 +-
.../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 22 -
Bindings/phy/rockchip,rk3588-hdptx-phy.yaml | 91 +
.../pinctrl/amlogic,meson-pinctrl-a1.yaml | 2 +-
.../amlogic,meson-pinctrl-g12a-aobus.yaml | 2 +-
.../amlogic,meson-pinctrl-g12a-periphs.yaml | 2 +-
.../pinctrl/amlogic,meson8-pinctrl-aobus.yaml | 2 +-
.../pinctrl/amlogic,meson8-pinctrl-cbus.yaml | 2 +-
Bindings/pinctrl/atmel,at91-pinctrl.txt | 2 +
Bindings/pinctrl/awinic,aw9523-pinctrl.yaml | 139 +
Bindings/pinctrl/cirrus,madera.yaml | 3 +-
Bindings/pinctrl/cypress,cy8c95x0.yaml | 24 +-
Bindings/pinctrl/fsl,imx6ul-pinctrl.txt | 37 -
Bindings/pinctrl/fsl,imx6ul-pinctrl.yaml | 116 +
Bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml | 242 ++
Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml | 2 -
Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml | 3 +-
.../pinctrl/nvidia,tegra234-pinmux-aon.yaml | 7 +-
.../nvidia,tegra234-pinmux-common.yaml | 84 +-
Bindings/pinctrl/nvidia,tegra234-pinmux.yaml | 7 +-
Bindings/pinctrl/pincfg-node.yaml | 2 +-
Bindings/pinctrl/qcom,sm4450-tlmm.yaml | 2 +-
Bindings/pinctrl/renesas,pfc.yaml | 1 +
Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 +
...nq-pinctrl.yaml => xlnx,pinctrl-zynq.yaml} | 6 +-
Bindings/power/qcom,rpmpd.yaml | 2 +
Bindings/power/renesas,rcar-sysc.yaml | 1 +
Bindings/power/wakeup-source.txt | 2 +-
Bindings/pwm/atmel,hlcdc-pwm.yaml | 35 +
Bindings/pwm/atmel-hlcdc-pwm.txt | 29 -
Bindings/pwm/marvell,pxa-pwm.yaml | 51 +
Bindings/pwm/mediatek,mt2712-pwm.yaml | 1 +
Bindings/pwm/mediatek,pwm-disp.yaml | 3 +
Bindings/pwm/opencores,pwm.yaml | 56 +
Bindings/pwm/pwm-amlogic.yaml | 115 +-
Bindings/pwm/pxa-pwm.txt | 30 -
Bindings/regulator/gpio-regulator.yaml | 4 +-
Bindings/regulator/infineon,ir38060.yaml | 45 +
Bindings/regulator/mcp16502-regulator.txt | 144 -
Bindings/regulator/microchip,mcp16502.yaml | 180 ++
.../regulator/qcom,usb-vbus-regulator.yaml | 11 +-
Bindings/regulator/ti,tps65132.yaml | 84 +
Bindings/regulator/tps65132-regulator.txt | 46 -
Bindings/remoteproc/mtk,scp.yaml | 4 +-
Bindings/remoteproc/qcom,glink-rpm-edge.yaml | 1 -
Bindings/remoteproc/qcom,qcs404-pas.yaml | 2 +-
Bindings/remoteproc/qcom,sc7180-pas.yaml | 2 +-
Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml | 2 +-
Bindings/remoteproc/qcom,sc8180x-pas.yaml | 2 +-
Bindings/remoteproc/qcom,sm6115-pas.yaml | 2 +-
Bindings/remoteproc/qcom,sm6350-pas.yaml | 2 +-
Bindings/remoteproc/qcom,sm6375-pas.yaml | 2 +-
Bindings/remoteproc/qcom,sm8150-pas.yaml | 2 +-
Bindings/remoteproc/qcom,sm8350-pas.yaml | 2 +-
Bindings/remoteproc/qcom,sm8550-pas.yaml | 51 +-
Bindings/remoteproc/qcom,wcnss-pil.yaml | 2 +-
Bindings/remoteproc/ti,davinci-rproc.txt | 3 -
Bindings/reset/mobileye,eyeq5-reset.yaml | 43 +
Bindings/reset/renesas,rst.yaml | 1 +
Bindings/reset/sophgo,sg2042-reset.yaml | 35 +
Bindings/riscv/cpus.yaml | 10 +-
Bindings/riscv/extensions.yaml | 7 +
Bindings/rng/atmel,at91-trng.yaml | 4 +
Bindings/rtc/abracon,abx80x.txt | 31 -
Bindings/rtc/abracon,abx80x.yaml | 98 +
Bindings/rtc/atmel,at91sam9260-rtt.yaml | 4 +-
Bindings/rtc/mediatek,mt2712-rtc.yaml | 39 +
Bindings/rtc/mediatek,mt7622-rtc.yaml | 52 +
Bindings/rtc/rtc-mt2712.txt | 14 -
Bindings/rtc/rtc-mt7622.txt | 21 -
Bindings/rtc/sa1100-rtc.yaml | 2 +-
Bindings/rtc/xlnx,zynqmp-rtc.yaml | 11 +-
Bindings/serial/atmel,at91-usart.yaml | 2 +-
Bindings/serial/cdns,uart.yaml | 1 +
Bindings/serial/fsl-lpuart.yaml | 1 +
Bindings/serial/renesas,hscif.yaml | 1 +
Bindings/serial/samsung_uart.yaml | 2 +
Bindings/serial/serial.yaml | 2 +-
Bindings/serial/st,asc.yaml | 55 +
Bindings/serial/st,stm32-uart.yaml | 3 +
Bindings/serial/st-asc.txt | 18 -
Bindings/soc/fsl/fsl,layerscape-dcfg.yaml | 2 +-
Bindings/soc/fsl/fsl,layerscape-scfg.yaml | 2 +-
Bindings/soc/imx/fsl,imx-anatop.yaml | 128 +
Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml | 18 +-
.../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml | 22 +-
Bindings/soc/qcom/qcom,pbs.yaml | 46 +
Bindings/soc/qcom/qcom,pmic-glink.yaml | 3 +
Bindings/soc/qcom/qcom,rpm-master-stats.yaml | 2 +
.../qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 46 +-
Bindings/soc/renesas/renesas-soc.yaml | 73 +
Bindings/soc/renesas/renesas.yaml | 25 +-
Bindings/soc/rockchip/grf.yaml | 23 +
.../soc/samsung/samsung,exynos-sysreg.yaml | 2 +
Bindings/soc/xilinx/xilinx.yaml | 70 +-
Bindings/sound/atmel,asoc-wm8904.yaml | 84 +
Bindings/sound/atmel,sam9x5-wm8731-audio.yaml | 76 +
Bindings/sound/atmel,sama5d2-classd.yaml | 7 +-
Bindings/sound/atmel-sam9x5-wm8731-audio.txt | 35 -
Bindings/sound/atmel-wm8904.txt | 55 -
Bindings/sound/audio-graph-port.yaml | 2 +-
Bindings/sound/cirrus,cs35l45.yaml | 3 +
Bindings/sound/cirrus,cs42l43.yaml | 11 +-
Bindings/sound/cs4341.txt | 2 +-
Bindings/sound/everest,es8326.yaml | 8 +-
Bindings/sound/fsl,asrc.txt | 80 -
Bindings/sound/fsl,easrc.yaml | 4 +-
Bindings/sound/fsl,imx-asrc.yaml | 162 ++
Bindings/sound/fsl,micfil.yaml | 14 +-
Bindings/sound/fsl,sai.yaml | 6 +
Bindings/sound/infineon,peb2466.yaml | 2 +-
Bindings/sound/microchip,sama7g5-i2smcc.yaml | 11 +-
Bindings/sound/qcom,q6usb.yaml | 55 +
Bindings/sound/qcom,sm8250.yaml | 2 +-
Bindings/sound/qcom,wcd938x.yaml | 81 +-
Bindings/sound/qcom,wcd939x-sdw.yaml | 69 +
Bindings/sound/qcom,wcd939x.yaml | 96 +
Bindings/sound/qcom,wcd93xx-common.yaml | 95 +
Bindings/sound/qcom,wsa8840.yaml | 11 +-
Bindings/sound/realtek,rt1015.yaml | 41 +
Bindings/sound/rt1015.txt | 23 -
Bindings/sound/rt5645.txt | 6 +
Bindings/sound/samsung,tm2.yaml | 7 +-
Bindings/spi/atmel,at91rm9200-spi.yaml | 1 -
Bindings/spi/samsung,spi.yaml | 4 +-
Bindings/spi/spi-controller.yaml | 27 +
Bindings/spi/spi-fsl-lpspi.yaml | 1 +
Bindings/spi/spi-nxp-fspi.yaml | 18 +-
.../allwinner,sun4i-a10-system-control.yaml | 2 +-
Bindings/submitting-patches.rst | 23 +-
.../thermal/allwinner,sun8i-a83t-ths.yaml | 34 +-
Bindings/thermal/da9062-thermal.txt | 36 -
Bindings/thermal/dlg,da9062-thermal.yaml | 35 +
Bindings/thermal/qoriq-thermal.yaml | 3 +-
Bindings/thermal/rcar-gen3-thermal.yaml | 2 +
Bindings/thermal/thermal-zones.yaml | 2 -
Bindings/timer/arm,arch_timer_mmio.yaml | 2 +-
Bindings/timer/cdns,ttc.yaml | 22 +-
Bindings/timer/mediatek,mtk-timer.txt | 48 -
Bindings/timer/mediatek,timer.yaml | 84 +
Bindings/timer/mrvl,mmp-timer.yaml | 2 +-
Bindings/timer/nxp,sysctr-timer.yaml | 4 +-
Bindings/timer/ralink,cevt-systick.yaml | 38 +
Bindings/timer/renesas,ostm.yaml | 2 +-
Bindings/timer/renesas,tmu.yaml | 18 +-
Bindings/timer/samsung,exynos4210-mct.yaml | 2 +
Bindings/tpm/tcg,tpm_tis-spi.yaml | 1 +
Bindings/trivial-devices.yaml | 87 +-
Bindings/ufs/qcom,ufs.yaml | 38 +-
Bindings/usb/analogix,anx7411.yaml | 13 -
Bindings/usb/ci-hdrc-usb2.yaml | 2 +-
Bindings/usb/cypress,hx3.yaml | 2 +-
Bindings/usb/fcs,fsa4480.yaml | 12 +-
Bindings/usb/generic-ehci.yaml | 1 +
Bindings/usb/gpio-sbu-mux.yaml | 12 +-
Bindings/usb/hisilicon,hi3798mv200-dwc3.yaml | 99 +
Bindings/usb/ite,it5205.yaml | 72 +
Bindings/usb/mediatek,mtu3.yaml | 5 +-
Bindings/usb/microchip,usb5744.yaml | 2 -
Bindings/usb/nxp,ptn36502.yaml | 12 +-
Bindings/usb/nxp,ptn5110.yaml | 6 +-
Bindings/usb/onnn,nb7vpq904m.yaml | 13 +-
Bindings/usb/qcom,dwc3.yaml | 2 +-
Bindings/usb/qcom,pmic-typec.yaml | 46 +-
Bindings/usb/qcom,wcd939x-usbss.yaml | 12 +-
Bindings/usb/realtek,rts5411.yaml | 55 +
Bindings/usb/ti,am62-usb.yaml | 8 +-
Bindings/usb/ti,usb8020b.yaml | 69 +
Bindings/usb/usb-nop-xceiv.yaml | 11 +-
Bindings/usb/usb-switch.yaml | 67 +
Bindings/usb/usb.yaml | 2 +
Bindings/vendor-prefixes.yaml | 45 +
Bindings/w1/w1-uart.yaml | 59 +
Bindings/watchdog/arm,sp805.yaml | 5 +
Bindings/watchdog/atmel,sama5d4-wdt.yaml | 12 +-
Bindings/watchdog/brcm,bcm2835-pm-wdog.txt | 18 -
Bindings/watchdog/qcom-wdt.yaml | 2 +-
Bindings/watchdog/renesas,wdt.yaml | 1 +
Bindings/watchdog/sprd,sp9860-wdt.yaml | 64 +
Bindings/watchdog/sprd-wdt.txt | 19 -
Bindings/watchdog/starfive,jh7100-wdt.yaml | 40 +-
Bindings/writing-schema.rst | 30 +-
include/dt-bindings/arm/qcom,ids.h | 5 +
include/dt-bindings/clock/ast2600-clock.h | 1 +
include/dt-bindings/clock/exynos850.h | 56 +
include/dt-bindings/clock/google,gs101.h | 129 +
.../dt-bindings/clock/microchip,mpfs-clock.h | 5 +
.../dt-bindings/clock/mobileye,eyeq5-clk.h | 22 +
include/dt-bindings/clock/qcom,gcc-msm8953.h | 4 +
include/dt-bindings/clock/qcom,gcc-sc8180x.h | 2 +
include/dt-bindings/clock/qcom,gcc-sm8150.h | 3 +
.../dt-bindings/clock/qcom,x1e80100-camcc.h | 135 +
.../dt-bindings/clock/qcom,x1e80100-dispcc.h | 98 +
.../dt-bindings/clock/qcom,x1e80100-gpucc.h | 41 +
.../dt-bindings/clock/qcom,x1e80100-tcsr.h | 23 +
include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 1 +
.../clock/renesas,r8a779h0-cpg-mssr.h | 96 +
.../dt-bindings/clock/rockchip,rk3588-cru.h | 3 +-
include/dt-bindings/input/linux-event-codes.h | 1 +
.../dt-bindings/interconnect/qcom,msm8909.h | 93 +
.../interconnect/qcom,sm7150-rpmh.h | 150 +
.../interconnect/qcom,x1e80100-rpmh.h | 24 -
include/dt-bindings/leds/common.h | 4 +
include/dt-bindings/mfd/stm32f7-rcc.h | 1 +
include/dt-bindings/power/amlogic,c3-pwrc.h | 2 +-
include/dt-bindings/power/qcom-rpmpd.h | 7 +
.../dt-bindings/power/renesas,r8a779h0-sysc.h | 49 +
.../reset/mediatek,mt7988-resets.h | 6 +
.../dt-bindings/reset/qcom,x1e80100-gpucc.h | 19 +
.../dt-bindings/reset/sophgo,sg2042-reset.h | 87 +
src/arc/axc003.dtsi | 4 +-
src/arc/hsdk.dts | 1 -
src/arc/vdk_axs10x_mb.dtsi | 2 +-
src/arm/allwinner/sun8i-r40-feta40i.dtsi | 7 +
src/arm/amlogic/meson.dtsi | 6 +-
src/arm/amlogic/meson8.dtsi | 1 -
src/arm/amlogic/meson8b.dtsi | 1 -
src/arm/arm/arm-realview-pb1176.dts | 2 +-
src/arm/arm/integratorap-im-pd1.dts | 3 +-
src/arm/arm/versatile-ab.dts | 3 +-
src/arm/arm/vexpress-v2p-ca9.dts | 4 +-
src/arm/broadcom/bcm47622.dtsi | 14 +
src/arm/broadcom/bcm63138.dtsi | 7 +-
src/arm/broadcom/bcm63148.dtsi | 14 +
src/arm/broadcom/bcm63178.dtsi | 14 +
src/arm/broadcom/bcm6756.dtsi | 14 +
src/arm/broadcom/bcm6846.dtsi | 14 +
src/arm/broadcom/bcm6855.dtsi | 14 +
src/arm/broadcom/bcm6878.dtsi | 14 +
src/arm/broadcom/bcm947622.dts | 10 +
src/arm/broadcom/bcm963138.dts | 10 +
src/arm/broadcom/bcm963138dvt.dts | 14 +-
src/arm/broadcom/bcm963148.dts | 10 +
src/arm/broadcom/bcm963178.dts | 10 +
src/arm/broadcom/bcm96756.dts | 10 +
src/arm/broadcom/bcm96846.dts | 10 +
src/arm/broadcom/bcm96855.dts | 10 +
src/arm/broadcom/bcm96878.dts | 10 +
src/arm/gemini/gemini-dlink-dir-685.dts | 30 +-
src/arm/gemini/gemini-dlink-dns-313.dts | 4 +-
src/arm/gemini/gemini-sl93512r.dts | 16 +-
src/arm/gemini/gemini-sq201.dts | 16 +-
src/arm/gemini/gemini-wbd111.dts | 6 +-
src/arm/gemini/gemini-wbd222.dts | 6 +-
.../marvell/armada-385-clearfog-gtr-l8.dts | 38 +-
.../marvell/armada-385-clearfog-gtr-s4.dts | 2 +
src/arm/marvell/armada-385-clearfog-gtr.dtsi | 84 +-
src/arm/marvell/armada-388-clearfog.dts | 5 +-
src/arm/marvell/dove-cubox.dts | 4 +-
src/arm/marvell/mmp2-brownstone.dts | 2 +-
src/arm/microchip/at91-sama7g54_curiosity.dts | 482 ++++
src/arm/microchip/at91-sama7g5ek.dts | 8 +-
.../at91sam9g25-gardena-smart-gateway.dts | 2 +
src/arm/microchip/at91sam9x5ek.dtsi | 2 +
src/arm/microchip/sam9x60.dtsi | 64 +-
src/arm/microchip/sama7g5.dtsi | 56 +-
src/arm/nvidia/tegra124-nyan.dtsi | 1 +
src/arm/nvidia/tegra124-venice2.dts | 1 +
.../tegra30-asus-nexus7-grouper-common.dtsi | 3 +
src/arm/nvidia/tegra30-lg-p880.dts | 489 ++++
src/arm/nvidia/tegra30-lg-p895.dts | 496 ++++
src/arm/nvidia/tegra30-lg-x3.dtsi | 1812 ++++++++++++
src/arm/nxp/imx/imx1-apf9328.dts | 2 +-
src/arm/nxp/imx/imx1.dtsi | 2 +-
src/arm/nxp/imx/imx27.dtsi | 2 +-
src/arm/nxp/imx/imx31.dtsi | 2 +-
src/arm/nxp/imx/imx35.dtsi | 2 +-
src/arm/nxp/imx/imx51.dtsi | 2 +-
src/arm/nxp/imx/imx53-qsb-hdmi.dtso | 87 +
src/arm/nxp/imx/imx6dl-sielaff.dts | 533 ++++
src/arm/nxp/imx/imx6dl-yapp4-common.dtsi | 25 +-
src/arm/nxp/imx/imx6q-apalis-eval-v1.2.dts | 200 ++
src/arm/nxp/imx/imx6q-apalis-eval.dts | 108 +-
src/arm/nxp/imx/imx6q-apalis-eval.dtsi | 120 +
src/arm/nxp/imx/imx6qdl-hummingboard.dtsi | 7 +-
src/arm/nxp/imx/imx6qdl-hummingboard2.dtsi | 5 +
src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi | 10 +-
src/arm/nxp/imx/imx6qdl.dtsi | 2 +-
src/arm/nxp/imx/imx6sl-tolino-shine2hd.dts | 6 +-
src/arm/nxp/imx/imx6sl.dtsi | 2 +-
src/arm/nxp/imx/imx6sx.dtsi | 2 +-
src/arm/nxp/imx/imx6ul-14x14-evk.dtsi | 2 +-
src/arm/nxp/imx/imx6ul-geam.dts | 2 +-
.../nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi | 2 +-
src/arm/nxp/imx/imx6ul.dtsi | 18 +-
.../nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi | 4 +-
src/arm/nxp/imx/imx6ull-dhcom-som.dtsi | 4 +-
src/arm/nxp/imx/imx6ull-dhcor-som.dtsi | 7 +-
src/arm/nxp/imx/imx6ull-tarragon-common.dtsi | 1 +
src/arm/nxp/imx/imx6ull.dtsi | 2 +-
src/arm/nxp/imx/imx7-mba7.dtsi | 325 ++-
src/arm/nxp/imx/imx7-tqma7.dtsi | 144 +-
src/arm/nxp/imx/imx7d-mba7.dts | 94 +-
src/arm/nxp/imx/imx7s-warp.dts | 1 +
src/arm/nxp/ls/ls1021a.dtsi | 2 +
src/arm/nxp/mxs/imx28-evk.dts | 2 +-
src/arm/qcom/qcom-apq8026-lg-lenok.dts | 38 +
.../qcom-apq8026-samsung-matisse-wifi.dts | 452 +--
src/arm/qcom/qcom-apq8064.dtsi | 70 +-
src/arm/qcom/qcom-apq8084.dtsi | 13 +-
src/arm/qcom/qcom-ipq4019-ap.dk01.1.dtsi | 138 +-
src/arm/qcom/qcom-ipq4019.dtsi | 35 +-
src/arm/qcom/qcom-ipq8064.dtsi | 12 +-
.../qcom-msm8226-samsung-matisse-common.dtsi | 457 +++
src/arm/qcom/qcom-msm8226.dtsi | 736 +++--
src/arm/qcom/qcom-msm8660.dtsi | 17 +-
src/arm/qcom/qcom-msm8926-htc-memul.dts | 15 +-
.../qcom/qcom-msm8926-samsung-matisselte.dts | 37 +
src/arm/qcom/qcom-msm8960-pins.dtsi | 21 +
.../qcom/qcom-msm8960-samsung-expressatt.dts | 71 +-
src/arm/qcom/qcom-msm8960.dtsi | 48 +-
src/arm/qcom/qcom-msm8974.dtsi | 33 +-
src/arm/qcom/qcom-sdx55.dtsi | 32 +-
src/arm/qcom/qcom-sdx65.dtsi | 48 +-
src/arm/renesas/r8a73a4-ape6evm.dts | 12 +
src/arm/renesas/r8a73a4.dtsi | 23 +-
src/arm/renesas/r8a7740.dtsi | 2 +
src/arm/renesas/r8a7778.dtsi | 11 +-
src/arm/renesas/r8a7779.dtsi | 9 +-
src/arm/rockchip/rk3128-xpi-3128.dts | 29 +
src/arm/rockchip/rk3128.dtsi | 60 +
src/arm/rockchip/rk322x.dtsi | 16 +-
src/arm/rockchip/rk3288.dtsi | 16 +-
src/arm/rockchip/rv1126-sonoff-ihost.dtsi | 10 +-
src/arm/samsung/exynos4412-i9300.dts | 2 +-
src/arm/samsung/exynos4412-i9305.dts | 2 +-
src/arm/samsung/exynos4412-n710x.dts | 2 +-
src/arm/samsung/exynos4412-p4note.dtsi | 53 +-
.../samsung/exynos5420-galaxy-tab-common.dtsi | 34 +-
src/arm/samsung/exynos5420-peach-pit.dts | 1 +
.../samsung/exynos5422-odroidxu3-common.dtsi | 16 +-
src/arm/samsung/exynos5800-peach-pi.dts | 1 +
src/arm/st/stih407-pinctrl.dtsi | 8 +-
src/arm/st/stm32f769-disco-mb1166-reva09.dts | 13 +
src/arm/st/stm32f769-disco.dts | 70 +-
src/arm/st/stm32f769.dtsi | 20 +
src/arm/st/stm32mp131.dtsi | 7 +
src/arm/st/stm32mp135f-dk.dts | 8 +
src/arm/st/stm32mp157.dtsi | 2 +-
src/arm/st/stm32mp157a-dk1-scmi.dts | 2 +-
src/arm/st/stm32mp157c-dk2-scmi.dts | 2 +-
src/arm/st/stm32mp157c-ed1-scmi.dts | 2 +-
src/arm/st/stm32mp157c-ev1-scmi.dts | 2 +-
src/arm/st/stm32mp157c-lxa-tac-gen2.dts | 2 +-
src/arm/st/stm32mp15xc-lxa-tac.dtsi | 6 +-
src/arm/ti/davinci/da850.dtsi | 4 +-
src/arm/ti/keystone/keystone-clocks.dtsi | 2 +-
src/arm/ti/keystone/keystone-k2e-clocks.dtsi | 2 +-
src/arm/ti/keystone/keystone-k2e-evm.dts | 2 +-
src/arm/ti/keystone/keystone-k2e-netcp.dtsi | 2 +-
src/arm/ti/keystone/keystone-k2e.dtsi | 2 +-
src/arm/ti/keystone/keystone-k2g-evm.dts | 2 +-
src/arm/ti/keystone/keystone-k2g-ice.dts | 2 +-
src/arm/ti/keystone/keystone-k2g-netcp.dtsi | 2 +-
src/arm/ti/keystone/keystone-k2g.dtsi | 2 +-
src/arm/ti/keystone/keystone-k2hk-clocks.dtsi | 2 +-
src/arm/ti/keystone/keystone-k2hk-evm.dts | 2 +-
src/arm/ti/keystone/keystone-k2hk-netcp.dtsi | 2 +-
src/arm/ti/keystone/keystone-k2hk.dtsi | 2 +-
src/arm/ti/keystone/keystone-k2l-clocks.dtsi | 2 +-
src/arm/ti/keystone/keystone-k2l-evm.dts | 2 +-
src/arm/ti/keystone/keystone-k2l-netcp.dtsi | 2 +-
src/arm/ti/keystone/keystone-k2l.dtsi | 2 +-
src/arm/ti/keystone/keystone.dtsi | 2 +-
src/arm/ti/omap/am335x-baltos-ir2110.dts | 2 +-
src/arm/ti/omap/am335x-baltos-ir3220.dts | 2 +-
src/arm/ti/omap/am335x-baltos-ir5221.dts | 2 +-
src/arm/ti/omap/am335x-baltos-leds.dtsi | 2 +-
src/arm/ti/omap/am335x-baltos.dtsi | 2 +-
src/arm/ti/omap/am335x-base0033.dts | 2 +-
src/arm/ti/omap/am335x-bone-common.dtsi | 4 +-
src/arm/ti/omap/am335x-cm-t335.dts | 2 +-
src/arm/ti/omap/am335x-evmsk.dts | 2 +-
src/arm/ti/omap/am335x-guardian.dts | 4 +-
src/arm/ti/omap/am335x-icev2.dts | 2 +-
src/arm/ti/omap/am335x-igep0033.dtsi | 2 +-
src/arm/ti/omap/am335x-myirtech-myc.dtsi | 2 +-
src/arm/ti/omap/am335x-myirtech-myd.dts | 2 +-
src/arm/ti/omap/am335x-nano.dts | 2 +-
src/arm/ti/omap/am335x-netcan-plus-1xx.dts | 2 +-
src/arm/ti/omap/am335x-netcom-plus-2xx.dts | 2 +-
src/arm/ti/omap/am335x-netcom-plus-8xx.dts | 2 +-
src/arm/ti/omap/am335x-pdu001.dts | 2 +-
.../am335x-sancloud-bbe-extended-wifi.dts | 2 +-
src/arm/ti/omap/am335x-sancloud-bbe-lite.dts | 2 +-
src/arm/ti/omap/am335x-sbc-t335.dts | 2 +-
src/arm/ti/omap/am335x-sl50.dts | 3 +-
src/arm/ti/omap/am33xx-clocks.dtsi | 39 +-
src/arm/ti/omap/am33xx.dtsi | 9 +-
src/arm/ti/omap/am3517.dtsi | 11 +-
src/arm/ti/omap/am35xx-clocks.dtsi | 18 +-
src/arm/ti/omap/am4372.dtsi | 6 +
src/arm/ti/omap/am437x-cm-t43.dts | 2 +-
src/arm/ti/omap/am437x-sbc-t43.dts | 2 +-
src/arm/ti/omap/am5729-beagleboneai.dts | 2 +-
src/arm/ti/omap/am57xx-cl-som-am57x.dts | 2 +-
src/arm/ti/omap/am57xx-sbc-am57x.dts | 2 +-
src/arm/ti/omap/compulab-sb-som.dtsi | 2 +-
src/arm/ti/omap/dra7-l4.dtsi | 2 +-
src/arm/ti/omap/dra7.dtsi | 17 +-
src/arm/ti/omap/dra74x-p.dtsi | 2 +-
src/arm/ti/omap/dra7xx-clocks.dtsi | 2 +-
src/arm/ti/omap/omap3430es1-clocks.dtsi | 52 +-
src/arm/ti/omap/omap34xx-omap36xx-clocks.dtsi | 86 +-
src/arm/ti/omap/omap34xx.dtsi | 11 +-
...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 28 +-
src/arm/ti/omap/omap36xx-clocks.dtsi | 7 +-
.../omap/omap36xx-omap3430es2plus-clocks.dtsi | 46 +-
src/arm/ti/omap/omap36xx.dtsi | 9 +-
src/arm/ti/omap/omap3xxx-clocks.dtsi | 510 ++--
src/arm/ti/omap/omap4-epson-embt2ws.dts | 1 +
src/arm/ti/omap/omap4-panda-common.dtsi | 1 +
src/arm/ti/omap/omap4-sdp.dts | 2 +-
src/arm/ti/omap/omap4.dtsi | 9 +-
src/arm/ti/omap/omap5-igep0050.dts | 2 +-
src/arm/ti/omap/omap5.dtsi | 9 +-
src/arm/ti/omap/twl4030.dtsi | 2 +-
src/arm/ti/omap/twl6030.dtsi | 4 +-
src/arm64/allwinner/sun50i-h6-beelink-gs1.dts | 2 +
src/arm64/allwinner/sun50i-h6-tanix.dtsi | 2 +
src/arm64/allwinner/sun50i-h6.dtsi | 7 +-
.../sun50i-h616-bigtreetech-cb1-manta.dts | 2 +-
.../sun50i-h616-bigtreetech-cb1.dtsi | 4 +-
.../allwinner/sun50i-h616-bigtreetech-pi.dts | 2 +-
src/arm64/allwinner/sun50i-h616.dtsi | 155 +
.../sun50i-h618-longan-module-3h.dtsi | 75 +
.../allwinner/sun50i-h618-longanpi-3h.dts | 144 +
.../sun50i-h618-transpeed-8k618-t.dts | 23 +
.../allwinner/sun50i-h64-remix-mini-pc.dts | 356 +++
src/arm64/amlogic/amlogic-c3.dtsi | 7 +
src/arm64/amlogic/amlogic-t7.dtsi | 12 +-
src/arm64/amlogic/meson-a1-ad402.dts | 2 +-
src/arm64/amlogic/meson-a1.dtsi | 2 +
.../meson-axg-jethome-jethub-j1xx.dtsi | 30 +-
src/arm64/amlogic/meson-axg-s400.dts | 16 +-
src/arm64/amlogic/meson-axg.dtsi | 8 +
src/arm64/amlogic/meson-g12-common.dtsi | 3 +
src/arm64/amlogic/meson-g12a-fbx8am-brcm.dtso | 31 +
.../amlogic/meson-g12a-fbx8am-realtek.dtso | 21 +
src/arm64/amlogic/meson-g12a-fbx8am.dts | 462 +++
src/arm64/amlogic/meson-g12a-radxa-zero.dts | 12 +-
src/arm64/amlogic/meson-g12a-sei510.dts | 14 +-
src/arm64/amlogic/meson-g12a-u200.dts | 16 +-
src/arm64/amlogic/meson-g12a-x96-max.dts | 14 +-
src/arm64/amlogic/meson-g12b-odroid-n2.dtsi | 2 +-
src/arm64/amlogic/meson-g12b-odroid.dtsi | 20 +-
src/arm64/amlogic/meson-g12b-w400.dtsi | 10 +-
src/arm64/amlogic/meson-gx-libretech-pc.dtsi | 12 +-
src/arm64/amlogic/meson-gx-p23x-q20x.dtsi | 8 +-
src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts | 6 +-
src/arm64/amlogic/meson-gxbb-odroidc2.dts | 8 +-
src/arm64/amlogic/meson-gxbb-p200.dts | 4 +-
src/arm64/amlogic/meson-gxbb-p20x.dtsi | 6 +-
src/arm64/amlogic/meson-gxbb-vega-s95.dtsi | 8 +-
src/arm64/amlogic/meson-gxbb-wetek.dtsi | 8 +-
.../amlogic/meson-gxl-s805x-libretech-ac.dts | 8 +-
src/arm64/amlogic/meson-gxl-s805x-p241.dts | 8 +-
.../meson-gxl-s905w-jethome-jethub-j80.dts | 8 +-
.../meson-gxl-s905x-hwacom-amazetv.dts | 6 +-
.../meson-gxl-s905x-libretech-cc-v2.dts | 12 +-
.../amlogic/meson-gxl-s905x-libretech-cc.dts | 6 +-
.../amlogic/meson-gxl-s905x-nexbox-a95x.dts | 6 +-
src/arm64/amlogic/meson-gxl-s905x-p212.dtsi | 8 +-
src/arm64/amlogic/meson-gxm-khadas-vim2.dts | 8 +-
.../amlogic/meson-gxm-s912-libretech-pc.dts | 2 +-
src/arm64/amlogic/meson-khadas-vim3.dtsi | 16 +-
.../amlogic/meson-libretech-cottonwood.dtsi | 6 +-
src/arm64/amlogic/meson-sm1-ac2xx.dtsi | 10 +-
src/arm64/amlogic/meson-sm1-bananapi.dtsi | 14 +-
src/arm64/amlogic/meson-sm1-odroid-hc4.dts | 4 +-
src/arm64/amlogic/meson-sm1-odroid.dtsi | 20 +-
src/arm64/amlogic/meson-sm1-sei610.dts | 12 +-
.../bcmbca/bcm4906-netgear-r8000p.dts | 5 +
.../bcmbca/bcm4906-tplink-archer-c2300-v1.dts | 5 +
.../bcmbca/bcm4908-asus-gt-ac5300.dts | 19 +-
src/arm64/broadcom/bcmbca/bcm4908.dtsi | 7 +-
src/arm64/broadcom/bcmbca/bcm4912.dtsi | 14 +
src/arm64/broadcom/bcmbca/bcm63146.dtsi | 14 +
src/arm64/broadcom/bcmbca/bcm63158.dtsi | 14 +
src/arm64/broadcom/bcmbca/bcm6813.dtsi | 14 +
src/arm64/broadcom/bcmbca/bcm6856.dtsi | 14 +
src/arm64/broadcom/bcmbca/bcm6858.dtsi | 14 +
src/arm64/broadcom/bcmbca/bcm94908.dts | 10 +
src/arm64/broadcom/bcmbca/bcm94912.dts | 10 +
src/arm64/broadcom/bcmbca/bcm963146.dts | 10 +
src/arm64/broadcom/bcmbca/bcm963158.dts | 10 +
src/arm64/broadcom/bcmbca/bcm96813.dts | 10 +
src/arm64/broadcom/bcmbca/bcm96856.dts | 10 +
src/arm64/broadcom/bcmbca/bcm96858.dts | 10 +
src/arm64/exynos/exynos850.dtsi | 64 +
src/arm64/exynos/google/gs101-oriole.dts | 24 +
src/arm64/exynos/google/gs101-pinctrl.dtsi | 2 +-
src/arm64/exynos/google/gs101.dtsi | 131 +-
src/arm64/freescale/fsl-ls1012a.dtsi | 10 +-
src/arm64/freescale/fsl-ls1046a.dtsi | 1 -
src/arm64/freescale/fsl-ls1088a.dtsi | 6 +
src/arm64/freescale/fsl-lx2160a.dtsi | 32 +-
.../freescale/imx8-apalis-eval-v1.1.dtsi | 26 +
.../freescale/imx8-apalis-eval-v1.2.dtsi | 124 +
src/arm64/freescale/imx8-apalis-eval.dtsi | 22 -
src/arm64/freescale/imx8-apalis-v1.1.dtsi | 1 -
src/arm64/freescale/imx8-ss-audio.dtsi | 330 +++
src/arm64/freescale/imx8-ss-conn.dtsi | 16 +-
src/arm64/freescale/imx8-ss-dma.dtsi | 103 +-
src/arm64/freescale/imx8-ss-gpu0.dtsi | 27 +
src/arm64/freescale/imx8-ss-lsio.dtsi | 16 +-
src/arm64/freescale/imx8dxl-evk.dts | 101 +
src/arm64/freescale/imx8dxl-ss-adma.dtsi | 77 +
src/arm64/freescale/imx8dxl.dtsi | 1 +
.../freescale/imx8dxp-tqma8xdp-mba8xx.dts | 16 +
src/arm64/freescale/imx8dxp-tqma8xdp.dtsi | 24 +
src/arm64/freescale/imx8dxp.dtsi | 24 +
src/arm64/freescale/imx8mm-evk.dtsi | 69 +
.../freescale/imx8mm-kontron-bl-osm-s.dts | 294 +-
src/arm64/freescale/imx8mm-kontron-bl.dts | 38 +-
src/arm64/freescale/imx8mm-kontron-osm-s.dtsi | 567 +++-
src/arm64/freescale/imx8mm-kontron-sl.dtsi | 4 +-
.../freescale/imx8mm-tqma8mqml-mba8mx.dts | 14 +-
src/arm64/freescale/imx8mm-venice-gw71xx.dtsi | 40 +-
src/arm64/freescale/imx8mm-venice-gw7901.dts | 14 +-
src/arm64/freescale/imx8mn-beacon-kit.dts | 2 -
src/arm64/freescale/imx8mn-evk.dtsi | 36 +
src/arm64/freescale/imx8mn-rve-gateway.dts | 2 +-
.../imx8mn-tqma8mqnl-mba8mx-usbotg.dtso | 64 +
.../freescale/imx8mn-tqma8mqnl-mba8mx.dts | 5 +-
src/arm64/freescale/imx8mn.dtsi | 2 +-
src/arm64/freescale/imx8mp-beacon-som.dtsi | 71 +
.../freescale/imx8mp-data-modul-edm-sbc.dts | 82 +-
src/arm64/freescale/imx8mp-evk.dts | 33 +-
.../freescale/imx8mp-phyboard-pollux-rdk.dts | 107 +-
src/arm64/freescale/imx8mp-phycore-som.dtsi | 1 -
src/arm64/freescale/imx8mp-venice-gw71xx.dtsi | 10 +-
src/arm64/freescale/imx8mp-venice-gw72xx.dtsi | 2 +-
src/arm64/freescale/imx8mp-venice-gw73xx.dtsi | 2 +-
src/arm64/freescale/imx8mp-verdin.dtsi | 3 +-
src/arm64/freescale/imx8mp.dtsi | 12 +-
src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts | 24 +-
.../freescale/imx8qm-apalis-eval-v1.2.dts | 16 +
src/arm64/freescale/imx8qm-apalis-eval.dts | 2 +-
.../imx8qm-apalis-v1.1-eval-v1.2.dts | 26 +
.../freescale/imx8qm-apalis-v1.1-eval.dts | 2 +-
src/arm64/freescale/imx8qm-mek.dts | 26 +
src/arm64/freescale/imx8qm-ss-conn.dtsi | 5 +
src/arm64/freescale/imx8qm-ss-dma.dtsi | 63 +-
src/arm64/freescale/imx8qm.dtsi | 41 +
.../freescale/imx8qxp-tqma8xqp-mba8xx.dts | 16 +
src/arm64/freescale/imx8qxp-tqma8xqp.dtsi | 14 +
src/arm64/freescale/imx8qxp.dtsi | 8 +
src/arm64/freescale/imx8ulp-evk.dts | 2 +-
src/arm64/freescale/imx93-phyboard-segin.dts | 117 +
src/arm64/freescale/imx93-phycore-som.dtsi | 126 +
src/arm64/freescale/imx93-tqma9352.dtsi | 4 +-
.../freescale/imx93-var-som-symphony.dts | 351 +++
src/arm64/freescale/imx93-var-som.dtsi | 110 +
src/arm64/freescale/imx93.dtsi | 4 +-
src/arm64/freescale/mba8mx.dtsi | 21 +-
src/arm64/freescale/mba8xx.dtsi | 554 ++++
src/arm64/freescale/tqma8xx.dtsi | 265 ++
src/arm64/intel/socfpga_agilex5.dtsi | 4 +-
src/arm64/marvell/ac5-98dx25xx.dtsi | 31 +-
src/arm64/marvell/ac5-98dx35xx-rd.dts | 4 +
src/arm64/marvell/armada-37xx.dtsi | 10 +-
src/arm64/marvell/armada-ap807.dtsi | 3 +
src/arm64/marvell/armada-cp11x.dtsi | 10 +-
src/arm64/mediatek/mt2712-evb.dts | 12 +-
src/arm64/mediatek/mt2712e.dtsi | 5 +-
src/arm64/mediatek/mt6797.dtsi | 8 +-
.../mediatek/mt7622-bananapi-bpi-r64.dts | 13 +
src/arm64/mediatek/mt7622-rfb1.dts | 25 +
src/arm64/mediatek/mt7622.dtsi | 34 +-
src/arm64/mediatek/mt7981b-xiaomi-ax3000t.dts | 15 +
src/arm64/mediatek/mt7981b.dtsi | 105 +
.../mediatek/mt7986a-acelink-ew-7886cax.dts | 173 ++
.../mt7986a-bananapi-bpi-r3-nand.dtso | 2 +-
.../mediatek/mt7986a-bananapi-bpi-r3.dts | 8 +-
src/arm64/mediatek/mt7986a-rfb.dts | 31 +-
src/arm64/mediatek/mt7986a.dtsi | 176 +-
src/arm64/mediatek/mt7986b-rfb.dts | 31 +-
.../mediatek/mt7988a-bananapi-bpi-r4.dts | 11 +
src/arm64/mediatek/mt7988a.dtsi | 136 +
src/arm64/mediatek/mt8173-elm-hana-rev7.dts | 2 +-
src/arm64/mediatek/mt8173-elm.dtsi | 3 +-
src/arm64/mediatek/mt8173-evb.dts | 2 +-
src/arm64/mediatek/mt8173.dtsi | 19 +-
.../mediatek/mt8183-kukui-jacuzzi-pico6.dts | 3 +-
src/arm64/mediatek/mt8183-kukui-kakadu.dtsi | 4 +
src/arm64/mediatek/mt8183-kukui-kodama.dtsi | 4 +
src/arm64/mediatek/mt8183-kukui-krane.dtsi | 4 +
src/arm64/mediatek/mt8183-kukui.dtsi | 6 +-
src/arm64/mediatek/mt8183-pumpkin.dts | 2 +-
src/arm64/mediatek/mt8183.dtsi | 12 +-
src/arm64/mediatek/mt8186-corsola-krabby.dtsi | 129 +
.../mt8186-corsola-magneton-sku393216.dts | 39 +
.../mt8186-corsola-magneton-sku393217.dts | 39 +
.../mt8186-corsola-magneton-sku393218.dts | 26 +
.../mt8186-corsola-rusty-sku196608.dts | 26 +
.../mt8186-corsola-steelix-sku131072.dts | 18 +
.../mt8186-corsola-steelix-sku131073.dts | 18 +
.../mediatek/mt8186-corsola-steelix.dtsi | 199 ++
.../mt8186-corsola-tentacool-sku327681.dts | 57 +
.../mt8186-corsola-tentacool-sku327683.dts | 24 +
.../mt8186-corsola-tentacruel-sku262144.dts | 44 +
.../mt8186-corsola-tentacruel-sku262148.dts | 26 +
src/arm64/mediatek/mt8186-corsola.dtsi | 1681 +++++++++++
src/arm64/mediatek/mt8186.dtsi | 93 +-
src/arm64/mediatek/mt8192-asurada.dtsi | 11 +-
src/arm64/mediatek/mt8192.dtsi | 11 +-
.../mediatek/mt8195-cherry-tomato-r1.dts | 4 +
.../mediatek/mt8195-cherry-tomato-r2.dts | 4 +
.../mediatek/mt8195-cherry-tomato-r3.dts | 4 +
src/arm64/mediatek/mt8195-cherry.dtsi | 63 +-
src/arm64/mediatek/mt8195-demo.dts | 18 +-
src/arm64/mediatek/mt8195-evb.dts | 12 +
src/arm64/mediatek/mt8195.dtsi | 133 +-
src/arm64/mediatek/mt8395-genio-1200-evk.dts | 17 +-
src/arm64/mediatek/mt8395-radxa-nio-12l.dts | 825 ++++++
src/arm64/nvidia/tegra132-norrin.dts | 1 +
src/arm64/nvidia/tegra194-p2888.dtsi | 50 +
src/arm64/nvidia/tegra194-p2972-0000.dts | 51 +-
src/arm64/nvidia/tegra194-p3668.dtsi | 27 +
src/arm64/nvidia/tegra234-p3701.dtsi | 1953 +------------
.../nvidia/tegra234-p3737-0000+p3701-0000.dts | 1 -
src/arm64/nvidia/tegra234-p3767-0000.dtsi | 14 -
src/arm64/nvidia/tegra234-p3767-0005.dtsi | 14 -
src/arm64/nvidia/tegra234-p3767.dtsi | 86 +
.../nvidia/tegra234-p3768-0000+p3767-0000.dts | 7 +-
.../nvidia/tegra234-p3768-0000+p3767-0005.dts | 12 +-
src/arm64/nvidia/tegra234-sim-vdk.dts | 1 -
src/arm64/nvidia/tegra234.dtsi | 2544 +++++++++++++++--
.../qcom/apq8016-sbc-d3-camera-mezzanine.dts | 8 +-
src/arm64/qcom/ipq5332.dtsi | 8 +-
src/arm64/qcom/ipq6018.dtsi | 159 ++
src/arm64/qcom/ipq8074.dtsi | 16 +
src/arm64/qcom/ipq9574.dtsi | 12 +-
src/arm64/qcom/msm8216-samsung-fortuna3g.dts | 11 +
.../qcom/msm8916-samsung-fortuna-common.dtsi | 203 ++
.../qcom/msm8916-samsung-gprimeltecan.dts | 27 +
.../qcom/msm8916-samsung-grandprimelte.dts | 16 +
.../qcom/msm8916-samsung-rossa-common.dtsi | 16 +
src/arm64/qcom/msm8916-samsung-rossa.dts | 16 +
src/arm64/qcom/msm8916.dtsi | 9 +
src/arm64/qcom/msm8939.dtsi | 11 +-
src/arm64/qcom/msm8953.dtsi | 155 +-
.../qcom/msm8994-msft-lumia-octagon.dtsi | 2 +-
.../qcom/msm8994-sony-xperia-kitakami.dtsi | 2 +-
src/arm64/qcom/msm8994.dtsi | 4 +-
src/arm64/qcom/msm8996.dtsi | 18 +-
src/arm64/qcom/msm8998.dtsi | 26 +-
src/arm64/qcom/{pm2250.dtsi => pm4125.dtsi} | 38 +-
src/arm64/qcom/pm6150.dtsi | 46 +
src/arm64/qcom/pmi632.dtsi | 39 +
src/arm64/qcom/qcm2290.dtsi | 7 +
src/arm64/qcom/qcm6490-fairphone-fp5.dts | 56 +-
src/arm64/qcom/qcm6490-idp.dts | 39 +-
src/arm64/qcom/qcs404.dtsi | 16 +
src/arm64/qcom/qcs6490-rb3gen2.dts | 23 +-
src/arm64/qcom/qrb2210-rb1.dts | 96 +-
src/arm64/qcom/qrb4210-rb2.dts | 50 +-
src/arm64/qcom/sa8155p-adp.dts | 30 +-
src/arm64/qcom/sa8295p-adp.dts | 68 +
src/arm64/qcom/sa8540p-ride.dts | 4 +-
src/arm64/qcom/sa8540p.dtsi | 3 +
src/arm64/qcom/sa8775p.dtsi | 119 +-
src/arm64/qcom/sc7180-trogdor.dtsi | 3 +
src/arm64/qcom/sc7180.dtsi | 86 +-
src/arm64/qcom/sc7280-chrome-common.dtsi | 28 +
src/arm64/qcom/sc7280-herobrine.dtsi | 1 +
src/arm64/qcom/sc7280-idp-ec-h1.dtsi | 1 +
src/arm64/qcom/sc7280.dtsi | 129 +-
src/arm64/qcom/sc8180x.dtsi | 143 +-
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 39 +-
src/arm64/qcom/sc8280xp-pmics.dtsi | 39 +-
src/arm64/qcom/sc8280xp.dtsi | 612 +++-
src/arm64/qcom/sda660-inforce-ifc6560.dts | 5 +
src/arm64/qcom/sdm450-motorola-ali.dts | 2 +-
src/arm64/qcom/sdm450.dtsi | 14 +
src/arm64/qcom/sdm630-sony-xperia-nile.dtsi | 16 +
src/arm64/qcom/sdm630.dtsi | 62 +-
src/arm64/qcom/sdm632.dtsi | 8 +
src/arm64/qcom/sdm660-xiaomi-lavender.dts | 6 +
src/arm64/qcom/sdm670.dtsi | 14 +-
src/arm64/qcom/sdm845-cheza.dtsi | 1 +
src/arm64/qcom/sdm845-db845c.dts | 2 +-
src/arm64/qcom/sdm845-oneplus-common.dtsi | 8 +-
src/arm64/qcom/sdm845-shift-axolotl.dts | 2 +-
src/arm64/qcom/sdm845.dtsi | 63 +-
src/arm64/qcom/sm4450.dtsi | 2 +-
src/arm64/qcom/sm6115.dtsi | 95 +-
src/arm64/qcom/sm6125.dtsi | 17 +-
src/arm64/qcom/sm6350.dtsi | 601 +++-
src/arm64/qcom/sm6375.dtsi | 14 +-
src/arm64/qcom/sm7125-xiaomi-common.dtsi | 26 +
src/arm64/qcom/sm7125-xiaomi-curtana.dts | 16 +
src/arm64/qcom/sm7225-fairphone-fp4.dts | 61 +-
src/arm64/qcom/sm8150.dtsi | 115 +-
.../qcom/sm8250-xiaomi-elish-common.dtsi | 3 +-
src/arm64/qcom/sm8250.dtsi | 113 +-
src/arm64/qcom/sm8350.dtsi | 87 +-
src/arm64/qcom/sm8450-hdk.dts | 6 +-
src/arm64/qcom/sm8450.dtsi | 97 +-
src/arm64/qcom/sm8550-hdk.dts | 1306 +++++++++
src/arm64/qcom/sm8550-mtp.dts | 11 +-
src/arm64/qcom/sm8550-qrd.dts | 53 +-
src/arm64/qcom/sm8550.dtsi | 187 +-
src/arm64/qcom/sm8650-mtp.dts | 155 +
src/arm64/qcom/sm8650-qrd.dts | 439 ++-
src/arm64/qcom/sm8650.dtsi | 81 +-
src/arm64/qcom/x1e80100-crd.dts | 450 +++
src/arm64/qcom/x1e80100-qcp.dts | 175 +-
src/arm64/qcom/x1e80100.dtsi | 1781 +++++++++++-
src/arm64/renesas/r8a774a1.dtsi | 11 +-
src/arm64/renesas/r8a774b1.dtsi | 11 +-
src/arm64/renesas/r8a774c0.dtsi | 11 +-
src/arm64/renesas/r8a774e1.dtsi | 11 +-
src/arm64/renesas/r8a77951.dtsi | 11 +-
src/arm64/renesas/r8a77960.dtsi | 11 +-
src/arm64/renesas/r8a77961.dtsi | 11 +-
src/arm64/renesas/r8a77965.dtsi | 11 +-
src/arm64/renesas/r8a77970.dtsi | 11 +-
src/arm64/renesas/r8a77980.dtsi | 17 +-
src/arm64/renesas/r8a77990.dtsi | 11 +-
src/arm64/renesas/r8a77995.dtsi | 11 +-
src/arm64/renesas/r8a779a0.dtsi | 21 +-
src/arm64/renesas/r8a779f0.dtsi | 17 +-
src/arm64/renesas/r8a779g0-white-hawk-cpu.dts | 13 +
.../renesas/r8a779g0-white-hawk-cpu.dtsi | 368 +--
src/arm64/renesas/r8a779g0-white-hawk.dts | 58 +-
src/arm64/renesas/r8a779g0.dtsi | 105 +-
.../renesas/r8a779g2-white-hawk-single.dts | 26 +
src/arm64/renesas/r8a779g2.dtsi | 12 +
.../renesas/r8a779h0-gray-hawk-single.dts | 230 ++
src/arm64/renesas/r8a779h0.dtsi | 664 +++++
src/arm64/renesas/r9a07g043u.dtsi | 81 +-
.../r9a07g043u11-smarc-cru-csi-ov5645.dtso | 21 +
src/arm64/renesas/r9a07g044.dtsi | 68 +-
src/arm64/renesas/r9a07g054.dtsi | 69 +-
src/arm64/renesas/r9a08g045.dtsi | 27 +-
src/arm64/renesas/rzg2l-smarc.dtsi | 14 +-
src/arm64/renesas/rzg2lc-smarc.dtsi | 14 +-
src/arm64/renesas/rzg3s-smarc-som.dtsi | 9 +
src/arm64/renesas/rzg3s-smarc.dtsi | 53 +
src/arm64/renesas/ulcb-kf.dtsi | 75 +-
src/arm64/renesas/white-hawk-common.dtsi | 65 +
src/arm64/renesas/white-hawk-cpu-common.dtsi | 375 +++
...k-csi-dsi.dtsi => white-hawk-csi-dsi.dtsi} | 2 +-
...ethernet.dtsi => white-hawk-ethernet.dtsi} | 2 +-
src/arm64/rockchip/px30-ringneck-haikou.dts | 1 +
src/arm64/rockchip/px30-ringneck.dtsi | 6 +
src/arm64/rockchip/rk3328-rock-pi-e.dts | 4 +-
src/arm64/rockchip/rk3328.dtsi | 11 +-
src/arm64/rockchip/rk3399-gru-scarlet.dtsi | 3 +-
src/arm64/rockchip/rk3399-kobol-helios64.dts | 5 +-
src/arm64/rockchip/rk3399-orangepi.dts | 2 +-
src/arm64/rockchip/rk3399-pinebook-pro.dts | 1 -
src/arm64/rockchip/rk3399-puma-haikou.dts | 5 +-
src/arm64/rockchip/rk3399-puma.dtsi | 53 +-
src/arm64/rockchip/rk3399-rock-pi-4a.dts | 2 +-
src/arm64/rockchip/rk3399-rock-pi-4b.dts | 2 +-
src/arm64/rockchip/rk3399-rock-pi-4c.dts | 2 +-
src/arm64/rockchip/rk3399.dtsi | 82 +-
.../rockchip/rk3566-anbernic-rg-arc-d.dts | 60 +
.../rockchip/rk3566-anbernic-rg-arc-s.dts | 19 +
.../rockchip/rk3566-anbernic-rg-arc.dtsi | 237 ++
.../rockchip/rk3566-anbernic-rg353x.dtsi | 74 +
src/arm64/rockchip/rk3566-anbernic-rg503.dts | 74 +
src/arm64/rockchip/rk3566-anbernic-rgxx3.dtsi | 74 -
src/arm64/rockchip/rk3566-lubancat-1.dts | 1 -
src/arm64/rockchip/rk3566-pinetab2-v0.1.dts | 28 +
src/arm64/rockchip/rk3566-pinetab2-v2.0.dts | 48 +
src/arm64/rockchip/rk3566-pinetab2.dtsi | 943 ++++++
.../rockchip/rk3566-powkiddy-rgb10max3.dts | 87 +
src/arm64/rockchip/rk3566-powkiddy-rgb30.dts | 18 +
src/arm64/rockchip/rk3566-powkiddy-rk2023.dts | 18 +
.../rockchip/rk3566-powkiddy-rk2023.dtsi | 18 +-
src/arm64/rockchip/rk3568-bpi-r2-pro.dts | 8 +-
src/arm64/rockchip/rk3568-lubancat-2.dts | 1 -
src/arm64/rockchip/rk3568-qnap-ts433.dts | 86 +
src/arm64/rockchip/rk356x.dtsi | 3 +-
src/arm64/rockchip/rk3588-coolpi-cm5.dtsi | 4 +-
.../rockchip/rk3588-edgeble-neu6a-common.dtsi | 466 +++
.../rockchip/rk3588-edgeble-neu6a-io.dts | 10 +-
.../rockchip/rk3588-edgeble-neu6a-io.dtsi | 232 ++
.../rockchip/rk3588-edgeble-neu6a-wifi.dtso | 56 +
src/arm64/rockchip/rk3588-edgeble-neu6a.dtsi | 25 +-
.../rockchip/rk3588-edgeble-neu6b-io.dts | 76 +-
src/arm64/rockchip/rk3588-edgeble-neu6b.dtsi | 383 +--
src/arm64/rockchip/rk3588-nanopc-t6.dts | 31 +-
src/arm64/rockchip/rk3588-orangepi-5-plus.dts | 4 +-
src/arm64/rockchip/rk3588-quartzpro64.dts | 2 +-
src/arm64/rockchip/rk3588-rock-5b.dts | 8 +-
src/arm64/rockchip/rk3588-tiger-haikou.dts | 266 ++
src/arm64/rockchip/rk3588-tiger.dtsi | 690 +++++
src/arm64/rockchip/rk3588-toybrick-x0.dts | 688 +++++
.../rockchip/rk3588s-indiedroid-nova.dts | 8 +
src/arm64/rockchip/rk3588s-nanopi-r6c.dts | 14 +
src/arm64/rockchip/rk3588s-nanopi-r6s.dts | 764 +++++
src/arm64/rockchip/rk3588s-rock-5a.dts | 1 -
src/arm64/rockchip/rk3588s.dtsi | 24 +-
src/arm64/st/stm32mp251.dtsi | 12 +
src/arm64/st/stm32mp255.dtsi | 17 +
src/arm64/tesla/fsd.dtsi | 2 +
src/arm64/ti/k3-am62-lp-sk.dts | 4 +-
src/arm64/ti/k3-am62-main.dtsi | 30 +-
src/arm64/ti/k3-am62-mcu.dtsi | 4 +-
src/arm64/ti/k3-am62-phycore-som.dtsi | 5 +-
src/arm64/ti/k3-am62-thermal.dtsi | 5 +-
src/arm64/ti/k3-am62-verdin-dahlia.dtsi | 1 -
src/arm64/ti/k3-am62-verdin-dev.dtsi | 1 -
src/arm64/ti/k3-am62-verdin-mallow.dtsi | 10 +
src/arm64/ti/k3-am62-verdin-wifi.dtsi | 1 -
src/arm64/ti/k3-am62-verdin.dtsi | 59 +-
src/arm64/ti/k3-am62-wakeup.dtsi | 38 +-
src/arm64/ti/k3-am62.dtsi | 4 +-
.../ti/k3-am625-beagleplay-csi2-ov5640.dtso | 4 +-
.../k3-am625-beagleplay-csi2-tevi-ov5640.dtso | 4 +-
src/arm64/ti/k3-am625-beagleplay.dts | 54 +-
src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts | 6 +-
src/arm64/ti/k3-am625-sk.dts | 4 +-
src/arm64/ti/k3-am625.dtsi | 4 +-
src/arm64/ti/k3-am62a-main.dtsi | 80 +-
src/arm64/ti/k3-am62a-mcu.dtsi | 4 +-
src/arm64/ti/k3-am62a-thermal.dtsi | 5 +-
src/arm64/ti/k3-am62a-wakeup.dtsi | 4 +-
src/arm64/ti/k3-am62a.dtsi | 4 +-
src/arm64/ti/k3-am62a7-sk.dts | 123 +-
src/arm64/ti/k3-am62a7.dtsi | 4 +-
src/arm64/ti/k3-am62p-main.dtsi | 154 +-
src/arm64/ti/k3-am62p-mcu.dtsi | 6 +-
src/arm64/ti/k3-am62p-thermal.dtsi | 5 +-
src/arm64/ti/k3-am62p-wakeup.dtsi | 5 +-
src/arm64/ti/k3-am62p.dtsi | 6 +-
src/arm64/ti/k3-am62p5-sk.dts | 11 +-
src/arm64/ti/k3-am62p5.dtsi | 4 +-
.../ti/k3-am62x-phyboard-lyra-gpio-fan.dtso | 50 +
src/arm64/ti/k3-am62x-sk-common.dtsi | 8 +-
src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso | 4 +-
src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso | 4 +-
.../ti/k3-am62x-sk-csi2-tevi-ov5640.dtso | 4 +-
src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso | 4 +-
src/arm64/ti/k3-am64-main.dtsi | 69 +-
src/arm64/ti/k3-am64-mcu.dtsi | 4 +-
src/arm64/ti/k3-am64-phycore-som.dtsi | 13 +-
src/arm64/ti/k3-am64-thermal.dtsi | 5 +-
src/arm64/ti/k3-am64.dtsi | 4 +-
.../ti/k3-am642-evm-icssg1-dualemac.dtso | 79 +
src/arm64/ti/k3-am642-evm.dts | 119 +-
.../ti/k3-am642-hummingboard-t-pcie.dtso | 45 +
.../ti/k3-am642-hummingboard-t-usb3.dtso | 44 +
src/arm64/ti/k3-am642-hummingboard-t.dts | 292 ++
.../ti/k3-am642-phyboard-electra-rdk.dts | 30 +-
src/arm64/ti/k3-am642-sk.dts | 14 +-
src/arm64/ti/k3-am642-sr-som.dtsi | 594 ++++
src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 1 -
src/arm64/ti/k3-am642.dtsi | 4 +-
.../ti/k3-am65-iot2050-arduino-connector.dtsi | 768 +++++
src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi | 7 +-
src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi | 27 +-
src/arm64/ti/k3-am65-iot2050-common.dtsi | 887 +-----
src/arm64/ti/k3-am65-iot2050-dp.dtsi | 98 +
src/arm64/ti/k3-am65-iot2050-usb3.dtsi | 27 +
src/arm64/ti/k3-am65-main.dtsi | 44 +-
src/arm64/ti/k3-am65-mcu.dtsi | 4 +-
src/arm64/ti/k3-am65-wakeup.dtsi | 4 +-
src/arm64/ti/k3-am65.dtsi | 4 +-
src/arm64/ti/k3-am652.dtsi | 4 +-
.../ti/k3-am6528-iot2050-basic-common.dtsi | 8 +-
src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts | 4 +-
src/arm64/ti/k3-am6528-iot2050-basic.dts | 7 +-
...am654-base-board-rocktech-rk101-panel.dtso | 4 +-
src/arm64/ti/k3-am654-base-board.dts | 8 +-
src/arm64/ti/k3-am654-icssg2.dtso | 4 +-
src/arm64/ti/k3-am654-idk.dtso | 4 +-
src/arm64/ti/k3-am654-industrial-thermal.dtsi | 5 +-
src/arm64/ti/k3-am654-pcie-usb2.dtso | 59 +
src/arm64/ti/k3-am654-pcie-usb3.dtso | 61 +
src/arm64/ti/k3-am654.dtsi | 4 +-
.../ti/k3-am6548-iot2050-advanced-common.dtsi | 2 +-
.../ti/k3-am6548-iot2050-advanced-m2.dts | 22 +-
.../ti/k3-am6548-iot2050-advanced-pg2.dts | 12 +-
.../ti/k3-am6548-iot2050-advanced-sm.dts | 189 ++
src/arm64/ti/k3-am6548-iot2050-advanced.dts | 3 +-
src/arm64/ti/k3-am68-sk-base-board.dts | 54 +-
src/arm64/ti/k3-am68-sk-som.dtsi | 20 +-
src/arm64/ti/k3-am69-sk.dts | 253 +-
src/arm64/ti/k3-j7200-common-proc-board.dts | 109 +-
.../ti/k3-j7200-evm-quad-port-eth-exp.dtso | 4 +-
src/arm64/ti/k3-j7200-main.dtsi | 315 +-
src/arm64/ti/k3-j7200-mcu-wakeup.dtsi | 57 +-
src/arm64/ti/k3-j7200-som-p0.dtsi | 47 +-
src/arm64/ti/k3-j7200-thermal.dtsi | 5 +-
src/arm64/ti/k3-j7200.dtsi | 4 +-
src/arm64/ti/k3-j721e-beagleboneai64.dts | 26 +-
src/arm64/ti/k3-j721e-common-proc-board.dts | 4 +-
src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso | 4 +-
src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso | 4 +-
.../ti/k3-j721e-evm-quad-port-eth-exp.dtso | 4 +-
src/arm64/ti/k3-j721e-main.dtsi | 149 +-
src/arm64/ti/k3-j721e-mcu-wakeup.dtsi | 8 +-
.../ti/k3-j721e-sk-csi2-dual-imx219.dtso | 165 ++
src/arm64/ti/k3-j721e-sk.dts | 45 +-
src/arm64/ti/k3-j721e-som-p0.dtsi | 22 +-
src/arm64/ti/k3-j721e-thermal.dtsi | 5 +-
src/arm64/ti/k3-j721e.dtsi | 4 +-
src/arm64/ti/k3-j721s2-common-proc-board.dts | 31 +-
.../ti/k3-j721s2-evm-gesi-exp-board.dtso | 4 +-
src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso | 4 +-
src/arm64/ti/k3-j721s2-main.dtsi | 143 +-
src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi | 6 +-
src/arm64/ti/k3-j721s2-som-p0.dtsi | 20 +-
src/arm64/ti/k3-j721s2-thermal.dtsi | 5 +-
src/arm64/ti/k3-j721s2.dtsi | 4 +-
src/arm64/ti/k3-j722s-evm.dts | 383 +++
src/arm64/ti/k3-j722s.dtsi | 89 +
src/arm64/ti/k3-j784s4-evm.dts | 32 +-
src/arm64/ti/k3-j784s4-main.dtsi | 215 +-
src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi | 6 +-
src/arm64/ti/k3-j784s4-thermal.dtsi | 5 +-
src/arm64/ti/k3-j784s4.dtsi | 6 +-
src/arm64/ti/k3-pinctrl.h | 7 +-
src/arm64/ti/k3-serdes.h | 4 +-
src/arm64/xilinx/zynqmp-clk-ccf.dtsi | 16 +-
src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso | 36 +-
src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso | 37 +-
src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +-
src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +-
src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
src/arm64/xilinx/zynqmp-zcu100-revC.dts | 2 +-
src/arm64/xilinx/zynqmp-zcu102-revA.dts | 6 +-
src/arm64/xilinx/zynqmp-zcu104-revA.dts | 2 +-
src/arm64/xilinx/zynqmp-zcu104-revC.dts | 2 +-
src/arm64/xilinx/zynqmp-zcu106-revA.dts | 6 +-
src/arm64/xilinx/zynqmp-zcu111-revA.dts | 4 +-
src/arm64/xilinx/zynqmp-zcu1275-revA.dts | 2 +-
src/arm64/xilinx/zynqmp.dtsi | 85 +-
src/loongarch/loongson-2k1000.dtsi | 7 +
src/loongarch/loongson-2k2000-ref.dts | 33 +
src/loongarch/loongson-2k2000.dtsi | 24 +-
src/mips/mobileye/eyeq5-epm5.dts | 23 +
src/mips/mobileye/eyeq5-fixed-clocks.dtsi | 292 ++
src/mips/mobileye/eyeq5.dtsi | 124 +
src/mips/ralink/mt7621.dtsi | 47 +
src/powerpc/akebono.dts | 6 +-
src/riscv/microchip/mpfs.dtsi | 6 +-
src/riscv/renesas/r9a07g043f.dtsi | 8 +-
src/riscv/sophgo/sg2042.dtsi | 9 +
.../starfive/jh7100-beaglev-starlight.dts | 11 +
src/riscv/starfive/jh7100-common.dtsi | 108 +
.../jh7100-starfive-visionfive-v1.dts | 22 +-
src/riscv/starfive/jh7100.dtsi | 49 +
.../jh7110-starfive-visionfive-2.dtsi | 71 +
src/riscv/starfive/jh7110.dtsi | 76 +
1276 files changed, 55515 insertions(+), 12702 deletions(-)
delete mode 100644 Bindings/arm/marvell/armada-38x.txt
create mode 100644 Bindings/arm/marvell/armada-38x.yaml
delete mode 100644 Bindings/arm/mediatek/mediatek,hifsys.txt
delete mode 100644 Bindings/arm/mediatek/mediatek,pciesys.txt
delete mode 100644 Bindings/arm/mediatek/mediatek,ssusbsys.txt
delete mode 100644 Bindings/arm/msm/qcom,saw2.txt
delete mode 100644 Bindings/ata/ahci-mtk.txt
delete mode 100644 Bindings/ata/atmel-at91_cf.txt
create mode 100644 Bindings/ata/mediatek,mtk-ahci.yaml
create mode 100644 Bindings/auxdisplay/gpio-7-segment.yaml
create mode 100644 Bindings/auxdisplay/maxim,max6959.yaml
delete mode 100644 Bindings/bus/imx-weim.txt
create mode 100644 Bindings/clock/mediatek,mt2701-hifsys.yaml
create mode 100644 Bindings/clock/mediatek,mt7622-pciesys.yaml
create mode 100644 Bindings/clock/mediatek,mt7622-ssusbsys.yaml
create mode 100644 Bindings/clock/mobileye,eyeq5-clk.yaml
delete mode 100644 Bindings/clock/qcom,sc7180-mss.yaml
delete mode 100644 Bindings/clock/qcom,sm8650-dispcc.yaml
create mode 100644 Bindings/display/atmel/atmel,hlcdc-display-controller.yaml
delete mode 100644 Bindings/display/atmel/hlcdc-dc.txt
create mode 100644 Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml
create mode 100644 Bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
create mode 100644 Bindings/display/msm/qcom,x1e80100-mdss.yaml
create mode 100644 Bindings/display/panel/boe,th101mb31ig002-28a.yaml
create mode 100644 Bindings/display/panel/himax,hx83112a.yaml
create mode 100644 Bindings/display/panel/novatek,nt36672e.yaml
create mode 100644 Bindings/display/renesas,rzg2l-du.yaml
create mode 100644 Bindings/display/solomon,ssd133x.yaml
create mode 100644 Bindings/dma/marvell,mmp-dma.yaml
create mode 100644 Bindings/dma/mediatek,mt7622-hsdma.yaml
delete mode 100644 Bindings/dma/mmp-dma.txt
delete mode 100644 Bindings/dma/mtk-hsdma.txt
delete mode 100644 Bindings/fpga/fpga-region.txt
create mode 100644 Bindings/fpga/fpga-region.yaml
create mode 100644 Bindings/gpio/aspeed,ast2400-gpio.yaml
delete mode 100644 Bindings/gpio/gpio-aspeed.txt
delete mode 100644 Bindings/gpio/gpio-nmk.txt
create mode 100644 Bindings/gpio/st,nomadik-gpio.yaml
rename Bindings/gpu/{img,powervr.yaml => img,powervr-rogue.yaml} (91%)
create mode 100644 Bindings/gpu/img,powervr-sgx.yaml
create mode 100644 Bindings/hwmon/adi,ltc4282.yaml
create mode 100644 Bindings/hwmon/amphenol,chipcap2.yaml
create mode 100644 Bindings/hwmon/aspeed,g6-pwm-tach.yaml
create mode 100644 Bindings/hwmon/fan-common.yaml
create mode 100644 Bindings/hwmon/hwmon-common.yaml
delete mode 100644 Bindings/i2c/i2c.txt
create mode 100644 Bindings/iio/adc/microchip,pac1934.yaml
create mode 100644 Bindings/iio/adc/ti,ads1298.yaml
create mode 100644 Bindings/iio/frequency/adi,admfm2000.yaml
create mode 100644 Bindings/iio/magnetometer/voltafield,af8133j.yaml
delete mode 100644 Bindings/input/atmel,captouch.txt
create mode 100644 Bindings/input/atmel,captouch.yaml
delete mode 100644 Bindings/input/da9062-onkey.txt
create mode 100644 Bindings/input/dlg,da9062-onkey.yaml
create mode 100644 Bindings/input/samsung,s3c6410-keypad.yaml
delete mode 100644 Bindings/input/samsung-keypad.txt
create mode 100644 Bindings/input/touchscreen/fsl,imx6ul-tsc.yaml
create mode 100644 Bindings/input/touchscreen/goodix,gt9916.yaml
delete mode 100644 Bindings/input/touchscreen/imx6ul_tsc.txt
create mode 100644 Bindings/interconnect/qcom,sm7150-rpmh.yaml
delete mode 100644 Bindings/interrupt-controller/atmel,aic.txt
create mode 100644 Bindings/interrupt-controller/atmel,aic.yaml
create mode 100644 Bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml
delete mode 100644 Bindings/interrupt-controller/mediatek,sysirq.txt
create mode 100644 Bindings/interrupt-controller/starfive,jh8100-intc.yaml
create mode 100644 Bindings/leds/backlight/kinetic,ktd2801.yaml
create mode 100644 Bindings/leds/onnn,ncp5623.yaml
create mode 100644 Bindings/media/st,stm32mp25-video-codec.yaml
create mode 100644 Bindings/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml
create mode 100644 Bindings/memory-controllers/fsl/fsl,imx-weim.yaml
create mode 100644 Bindings/mfd/atmel,hlcdc.yaml
create mode 100644 Bindings/mfd/atmel,sama5d2-flexcom.yaml
delete mode 100644 Bindings/mfd/atmel-flexcom.txt
delete mode 100644 Bindings/mfd/atmel-hlcdc.txt
delete mode 100644 Bindings/mfd/da9062.txt
create mode 100644 Bindings/mips/mobileye.yaml
delete mode 100644 Bindings/misc/xlnx,sd-fec.txt
create mode 100644 Bindings/misc/xlnx,sd-fec.yaml
delete mode 100644 Bindings/mmc/hi3798cv200-dw-mshc.txt
create mode 100644 Bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml
create mode 100644 Bindings/mtd/partitions/linux,ubi.yaml
create mode 100644 Bindings/mtd/partitions/ubi-volume.yaml
delete mode 100644 Bindings/net/dsa/ar9331.txt
create mode 100644 Bindings/net/dsa/qca,ar9331.yaml
create mode 100644 Bindings/net/ethernet-phy-package.yaml
create mode 100644 Bindings/net/qca,qca808x.yaml
create mode 100644 Bindings/net/qcom,qca807x.yaml
create mode 100644 Bindings/nvmem/nvmem-provider.yaml
delete mode 100644 Bindings/nvmem/xlnx,zynqmp-nvmem.txt
create mode 100644 Bindings/nvmem/xlnx,zynqmp-nvmem.yaml
create mode 100644 Bindings/pci/qcom,pcie-common.yaml
create mode 100644 Bindings/pci/qcom,pcie-sa8775p.yaml
create mode 100644 Bindings/pci/qcom,pcie-sc7280.yaml
create mode 100644 Bindings/pci/qcom,pcie-sc8180x.yaml
create mode 100644 Bindings/pci/qcom,pcie-sc8280xp.yaml
create mode 100644 Bindings/pci/qcom,pcie-sm8150.yaml
create mode 100644 Bindings/pci/qcom,pcie-sm8250.yaml
create mode 100644 Bindings/pci/qcom,pcie-sm8350.yaml
create mode 100644 Bindings/pci/qcom,pcie-sm8450.yaml
create mode 100644 Bindings/pci/qcom,pcie-sm8550.yaml
create mode 100644 Bindings/pci/qcom,pcie-x1e80100.yaml
create mode 100644 Bindings/perf/arm,coresight-pmu.yaml
create mode 100644 Bindings/perf/starfive,jh8100-starlink-pmu.yaml
create mode 100644 Bindings/phy/mediatek,mt8365-csi-rx.yaml
create mode 100644 Bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml
create mode 100644 Bindings/phy/rockchip,rk3588-hdptx-phy.yaml
create mode 100644 Bindings/pinctrl/awinic,aw9523-pinctrl.yaml
delete mode 100644 Bindings/pinctrl/fsl,imx6ul-pinctrl.txt
create mode 100644 Bindings/pinctrl/fsl,imx6ul-pinctrl.yaml
create mode 100644 Bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml
rename Bindings/pinctrl/{xlnx,zynq-pinctrl.yaml => xlnx,pinctrl-zynq.yaml} (98%)
create mode 100644 Bindings/pwm/atmel,hlcdc-pwm.yaml
delete mode 100644 Bindings/pwm/atmel-hlcdc-pwm.txt
create mode 100644 Bindings/pwm/marvell,pxa-pwm.yaml
create mode 100644 Bindings/pwm/opencores,pwm.yaml
delete mode 100644 Bindings/pwm/pxa-pwm.txt
create mode 100644 Bindings/regulator/infineon,ir38060.yaml
delete mode 100644 Bindings/regulator/mcp16502-regulator.txt
create mode 100644 Bindings/regulator/microchip,mcp16502.yaml
create mode 100644 Bindings/regulator/ti,tps65132.yaml
delete mode 100644 Bindings/regulator/tps65132-regulator.txt
create mode 100644 Bindings/reset/mobileye,eyeq5-reset.yaml
create mode 100644 Bindings/reset/sophgo,sg2042-reset.yaml
delete mode 100644 Bindings/rtc/abracon,abx80x.txt
create mode 100644 Bindings/rtc/abracon,abx80x.yaml
create mode 100644 Bindings/rtc/mediatek,mt2712-rtc.yaml
create mode 100644 Bindings/rtc/mediatek,mt7622-rtc.yaml
delete mode 100644 Bindings/rtc/rtc-mt2712.txt
delete mode 100644 Bindings/rtc/rtc-mt7622.txt
create mode 100644 Bindings/serial/st,asc.yaml
delete mode 100644 Bindings/serial/st-asc.txt
create mode 100644 Bindings/soc/imx/fsl,imx-anatop.yaml
create mode 100644 Bindings/soc/qcom/qcom,pbs.yaml
rename Bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (53%)
create mode 100644 Bindings/soc/renesas/renesas-soc.yaml
create mode 100644 Bindings/sound/atmel,asoc-wm8904.yaml
create mode 100644 Bindings/sound/atmel,sam9x5-wm8731-audio.yaml
delete mode 100644 Bindings/sound/atmel-sam9x5-wm8731-audio.txt
delete mode 100644 Bindings/sound/atmel-wm8904.txt
delete mode 100644 Bindings/sound/fsl,asrc.txt
create mode 100644 Bindings/sound/fsl,imx-asrc.yaml
create mode 100644 Bindings/sound/qcom,q6usb.yaml
create mode 100644 Bindings/sound/qcom,wcd939x-sdw.yaml
create mode 100644 Bindings/sound/qcom,wcd939x.yaml
create mode 100644 Bindings/sound/qcom,wcd93xx-common.yaml
create mode 100644 Bindings/sound/realtek,rt1015.yaml
delete mode 100644 Bindings/sound/rt1015.txt
delete mode 100644 Bindings/thermal/da9062-thermal.txt
create mode 100644 Bindings/thermal/dlg,da9062-thermal.yaml
delete mode 100644 Bindings/timer/mediatek,mtk-timer.txt
create mode 100644 Bindings/timer/mediatek,timer.yaml
create mode 100644 Bindings/timer/ralink,cevt-systick.yaml
create mode 100644 Bindings/usb/hisilicon,hi3798mv200-dwc3.yaml
create mode 100644 Bindings/usb/ite,it5205.yaml
create mode 100644 Bindings/usb/ti,usb8020b.yaml
create mode 100644 Bindings/usb/usb-switch.yaml
create mode 100644 Bindings/w1/w1-uart.yaml
delete mode 100644 Bindings/watchdog/brcm,bcm2835-pm-wdog.txt
create mode 100644 Bindings/watchdog/sprd,sp9860-wdt.yaml
delete mode 100644 Bindings/watchdog/sprd-wdt.txt
create mode 100644 include/dt-bindings/clock/mobileye,eyeq5-clk.h
create mode 100644 include/dt-bindings/clock/qcom,x1e80100-camcc.h
create mode 100644 include/dt-bindings/clock/qcom,x1e80100-dispcc.h
create mode 100644 include/dt-bindings/clock/qcom,x1e80100-gpucc.h
create mode 100644 include/dt-bindings/clock/qcom,x1e80100-tcsr.h
create mode 100644 include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h
create mode 100644 include/dt-bindings/interconnect/qcom,msm8909.h
create mode 100644 include/dt-bindings/interconnect/qcom,sm7150-rpmh.h
create mode 100644 include/dt-bindings/power/renesas,r8a779h0-sysc.h
create mode 100644 include/dt-bindings/reset/qcom,x1e80100-gpucc.h
create mode 100644 include/dt-bindings/reset/sophgo,sg2042-reset.h
create mode 100644 src/arm/microchip/at91-sama7g54_curiosity.dts
create mode 100644 src/arm/nvidia/tegra30-lg-p880.dts
create mode 100644 src/arm/nvidia/tegra30-lg-p895.dts
create mode 100644 src/arm/nvidia/tegra30-lg-x3.dtsi
create mode 100644 src/arm/nxp/imx/imx53-qsb-hdmi.dtso
create mode 100644 src/arm/nxp/imx/imx6dl-sielaff.dts
create mode 100644 src/arm/nxp/imx/imx6q-apalis-eval-v1.2.dts
create mode 100644 src/arm/nxp/imx/imx6q-apalis-eval.dtsi
create mode 100644 src/arm/qcom/qcom-msm8226-samsung-matisse-common.dtsi
create mode 100644 src/arm/qcom/qcom-msm8926-samsung-matisselte.dts
create mode 100644 src/arm/qcom/qcom-msm8960-pins.dtsi
create mode 100644 src/arm/st/stm32f769-disco-mb1166-reva09.dts
create mode 100644 src/arm/st/stm32f769.dtsi
create mode 100644 src/arm64/allwinner/sun50i-h618-longan-module-3h.dtsi
create mode 100644 src/arm64/allwinner/sun50i-h618-longanpi-3h.dts
create mode 100644 src/arm64/allwinner/sun50i-h64-remix-mini-pc.dts
create mode 100644 src/arm64/amlogic/meson-g12a-fbx8am-brcm.dtso
create mode 100644 src/arm64/amlogic/meson-g12a-fbx8am-realtek.dtso
create mode 100644 src/arm64/amlogic/meson-g12a-fbx8am.dts
create mode 100644 src/arm64/freescale/imx8-apalis-eval-v1.1.dtsi
create mode 100644 src/arm64/freescale/imx8-apalis-eval-v1.2.dtsi
create mode 100644 src/arm64/freescale/imx8-ss-gpu0.dtsi
create mode 100644 src/arm64/freescale/imx8dxp-tqma8xdp-mba8xx.dts
create mode 100644 src/arm64/freescale/imx8dxp-tqma8xdp.dtsi
create mode 100644 src/arm64/freescale/imx8dxp.dtsi
create mode 100644 src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso
create mode 100644 src/arm64/freescale/imx8qm-apalis-eval-v1.2.dts
create mode 100644 src/arm64/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts
create mode 100644 src/arm64/freescale/imx8qxp-tqma8xqp-mba8xx.dts
create mode 100644 src/arm64/freescale/imx8qxp-tqma8xqp.dtsi
create mode 100644 src/arm64/freescale/imx93-phyboard-segin.dts
create mode 100644 src/arm64/freescale/imx93-phycore-som.dtsi
create mode 100644 src/arm64/freescale/imx93-var-som-symphony.dts
create mode 100644 src/arm64/freescale/imx93-var-som.dtsi
create mode 100644 src/arm64/freescale/mba8xx.dtsi
create mode 100644 src/arm64/freescale/tqma8xx.dtsi
create mode 100644 src/arm64/mediatek/mt7981b-xiaomi-ax3000t.dts
create mode 100644 src/arm64/mediatek/mt7981b.dtsi
create mode 100644 src/arm64/mediatek/mt7986a-acelink-ew-7886cax.dts
create mode 100644 src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts
create mode 100644 src/arm64/mediatek/mt7988a.dtsi
create mode 100644 src/arm64/mediatek/mt8186-corsola-krabby.dtsi
create mode 100644 src/arm64/mediatek/mt8186-corsola-magneton-sku393216.dts
create mode 100644 src/arm64/mediatek/mt8186-corsola-magneton-sku393217.dts
create mode 100644 src/arm64/mediatek/mt8186-corsola-magneton-sku393218.dts
create mode 100644 src/arm64/mediatek/mt8186-corsola-rusty-sku196608.dts
create mode 100644 src/arm64/mediatek/mt8186-corsola-steelix-sku131072.dts
create mode 100644 src/arm64/mediatek/mt8186-corsola-steelix-sku131073.dts
create mode 100644 src/arm64/mediatek/mt8186-corsola-steelix.dtsi
create mode 100644 src/arm64/mediatek/mt8186-corsola-tentacool-sku327681.dts
create mode 100644 src/arm64/mediatek/mt8186-corsola-tentacool-sku327683.dts
create mode 100644 src/arm64/mediatek/mt8186-corsola-tentacruel-sku262144.dts
create mode 100644 src/arm64/mediatek/mt8186-corsola-tentacruel-sku262148.dts
create mode 100644 src/arm64/mediatek/mt8186-corsola.dtsi
create mode 100644 src/arm64/mediatek/mt8395-radxa-nio-12l.dts
delete mode 100644 src/arm64/nvidia/tegra234-p3767-0000.dtsi
delete mode 100644 src/arm64/nvidia/tegra234-p3767-0005.dtsi
create mode 100644 src/arm64/qcom/msm8216-samsung-fortuna3g.dts
create mode 100644 src/arm64/qcom/msm8916-samsung-fortuna-common.dtsi
create mode 100644 src/arm64/qcom/msm8916-samsung-gprimeltecan.dts
create mode 100644 src/arm64/qcom/msm8916-samsung-grandprimelte.dts
create mode 100644 src/arm64/qcom/msm8916-samsung-rossa-common.dtsi
create mode 100644 src/arm64/qcom/msm8916-samsung-rossa.dts
rename src/arm64/qcom/{pm2250.dtsi => pm4125.dtsi} (56%)
create mode 100644 src/arm64/qcom/sdm450.dtsi
create mode 100644 src/arm64/qcom/sm7125-xiaomi-curtana.dts
create mode 100644 src/arm64/qcom/sm8550-hdk.dts
create mode 100644 src/arm64/renesas/r8a779g0-white-hawk-cpu.dts
create mode 100644 src/arm64/renesas/r8a779g2-white-hawk-single.dts
create mode 100644 src/arm64/renesas/r8a779g2.dtsi
create mode 100644 src/arm64/renesas/r8a779h0-gray-hawk-single.dts
create mode 100644 src/arm64/renesas/r8a779h0.dtsi
create mode 100644 src/arm64/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso
create mode 100644 src/arm64/renesas/white-hawk-common.dtsi
create mode 100644 src/arm64/renesas/white-hawk-cpu-common.dtsi
rename src/arm64/renesas/{r8a779g0-white-hawk-csi-dsi.dtsi => white-hawk-csi-dsi.dtsi} (97%)
rename src/arm64/renesas/{r8a779g0-white-hawk-ethernet.dtsi => white-hawk-ethernet.dtsi} (76%)
create mode 100644 src/arm64/rockchip/rk3566-anbernic-rg-arc-d.dts
create mode 100644 src/arm64/rockchip/rk3566-anbernic-rg-arc-s.dts
create mode 100644 src/arm64/rockchip/rk3566-anbernic-rg-arc.dtsi
create mode 100644 src/arm64/rockchip/rk3566-pinetab2-v0.1.dts
create mode 100644 src/arm64/rockchip/rk3566-pinetab2-v2.0.dts
create mode 100644 src/arm64/rockchip/rk3566-pinetab2.dtsi
create mode 100644 src/arm64/rockchip/rk3566-powkiddy-rgb10max3.dts
create mode 100644 src/arm64/rockchip/rk3568-qnap-ts433.dts
create mode 100644 src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
create mode 100644 src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi
create mode 100644 src/arm64/rockchip/rk3588-edgeble-neu6a-wifi.dtso
create mode 100644 src/arm64/rockchip/rk3588-tiger-haikou.dts
create mode 100644 src/arm64/rockchip/rk3588-tiger.dtsi
create mode 100644 src/arm64/rockchip/rk3588-toybrick-x0.dts
create mode 100644 src/arm64/rockchip/rk3588s-nanopi-r6c.dts
create mode 100644 src/arm64/rockchip/rk3588s-nanopi-r6s.dts
create mode 100644 src/arm64/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso
create mode 100644 src/arm64/ti/k3-am642-evm-icssg1-dualemac.dtso
create mode 100644 src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso
create mode 100644 src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso
create mode 100644 src/arm64/ti/k3-am642-hummingboard-t.dts
create mode 100644 src/arm64/ti/k3-am642-sr-som.dtsi
create mode 100644 src/arm64/ti/k3-am65-iot2050-arduino-connector.dtsi
create mode 100644 src/arm64/ti/k3-am65-iot2050-dp.dtsi
create mode 100644 src/arm64/ti/k3-am65-iot2050-usb3.dtsi
create mode 100644 src/arm64/ti/k3-am654-pcie-usb2.dtso
create mode 100644 src/arm64/ti/k3-am654-pcie-usb3.dtso
create mode 100644 src/arm64/ti/k3-am6548-iot2050-advanced-sm.dts
create mode 100644 src/arm64/ti/k3-j721e-sk-csi2-dual-imx219.dtso
create mode 100644 src/arm64/ti/k3-j722s-evm.dts
create mode 100644 src/arm64/ti/k3-j722s.dtsi
create mode 100644 src/mips/mobileye/eyeq5-epm5.dts
create mode 100644 src/mips/mobileye/eyeq5-fixed-clocks.dtsi
create mode 100644 src/mips/mobileye/eyeq5.dtsi
^ permalink raw reply [relevance 4%]
* [PATCH 2/2] arm64: dts: qcom: Use 'ufshc' as the node name for UFS controller nodes
2024-05-14 13:08 4% [PATCH 0/2] arm64: dts: qcom: Use 'ufshc' as the node name for UFS controller nodes Manivannan Sadhasivam
@ 2024-05-14 13:08 14% ` Manivannan Sadhasivam
0 siblings, 0 replies; 200+ results
From: Manivannan Sadhasivam @ 2024-05-14 13:08 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, cros-qcom-dts-watchers
Cc: linux-arm-msm, linux-scsi, devicetree, linux-kernel,
Manivannan Sadhasivam
Devicetree binding has documented the node name for UFS controllers as
'ufshc'. So let's use it instead of 'ufs' which is for the UFS devices.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
8 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 231cea1f0fa8..3f65494259aa 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -1577,7 +1577,7 @@ rng: rng@10d2000 {
reg = <0 0x010d2000 0 0x1000>;
};
- ufs_mem_hc: ufs@1d84000 {
+ ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 7e7f0f0fb41b..da63e9435130 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2303,7 +2303,7 @@ pcie1_phy: phy@1c0e000 {
status = "disabled";
};
- ufs_mem_hc: ufs@1d84000 {
+ ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index a5b194813079..9c5437c2540a 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -2208,7 +2208,7 @@ pcie2a_phy: phy@1c24000 {
status = "disabled";
};
- ufs_mem_hc: ufs@1d84000 {
+ ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
@@ -2274,7 +2274,7 @@ ufs_mem_phy: phy@1d87000 {
status = "disabled";
};
- ufs_card_hc: ufs@1da4000 {
+ ufs_card_hc: ufshc@1da4000 {
compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01da4000 0 0x3000>;
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index aca0a87092e4..974e4b6e27a4 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -1175,7 +1175,7 @@ opp-202000000 {
};
};
- ufs_mem_hc: ufs@4804000 {
+ ufs_mem_hc: ufshc@4804000 {
compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
reg-names = "std", "ice";
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 98ab08356088..20527b254f6b 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -763,7 +763,7 @@ sdhc_2: mmc@4784000 {
status = "disabled";
};
- ufs_mem_hc: ufs@4804000 {
+ ufs_mem_hc: ufshc@4804000 {
compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
reg-names = "std", "ice";
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 24bcec3366ef..66e5ebbbbada 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1136,7 +1136,7 @@ mmss_noc: interconnect@1740000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
- ufs_mem_hc: ufs@1d84000 {
+ ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>,
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 3904348075f6..94eea47c24d3 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1957,7 +1957,7 @@ ufs_mem_phy: phy@1d80000 {
status = "disabled";
};
- ufs_mem_hc: ufs@1d84000 {
+ ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index ba72d8f38420..7c6d2150a1e0 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2509,7 +2509,7 @@ ufs_mem_phy: phy@1d80000 {
status = "disabled";
};
- ufs_mem_hc: ufs@1d84000 {
+ ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
--
2.25.1
^ permalink raw reply related [relevance 14%]
* [PATCH 0/2] arm64: dts: qcom: Use 'ufshc' as the node name for UFS controller nodes
@ 2024-05-14 13:08 4% Manivannan Sadhasivam
2024-05-14 13:08 14% ` [PATCH 2/2] " Manivannan Sadhasivam
0 siblings, 1 reply; 200+ results
From: Manivannan Sadhasivam @ 2024-05-14 13:08 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Alim Akhtar, Avri Altman,
Bart Van Assche, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, cros-qcom-dts-watchers
Cc: linux-arm-msm, linux-scsi, devicetree, linux-kernel,
Manivannan Sadhasivam
Devicetree binding has documented the node name for UFS controllers as
'ufshc'. So let's use it instead of 'ufs' which is for the UFS devices.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Manivannan Sadhasivam (2):
dt-bindings: ufs: qcom: Use 'ufshc' as the node name for UFS controller nodes
arm64: dts: qcom: Use 'ufshc' as the node name for UFS controller nodes
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 +-
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
9 files changed, 10 insertions(+), 10 deletions(-)
---
base-commit: 4cece764965020c22cff7665b18a012006359095
change-id: 20240514-ufs-nodename-fix-40672bc593a5
Best regards,
--
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^ permalink raw reply [relevance 4%]
* [PATCH 5.15 141/168] usb: typec: ucsi: Check for notifications after init
@ 2024-05-14 10:20 4% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2024-05-14 10:20 UTC (permalink / raw)
To: stable
Cc: Greg Kroah-Hartman, patches, Christian A. Ehrhardt,
Heikki Krogerus, Neil Armstrong
5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Christian A. Ehrhardt <lk@c--e.de>
commit 808a8b9e0b87bbc72bcc1f7ddfe5d04746e7ce56 upstream.
The completion notification for the final SET_NOTIFICATION_ENABLE
command during initialization can include a connector change
notification. However, at the time this completion notification is
processed, the ucsi struct is not ready to handle this notification.
As a result the notification is ignored and the controller
never sends an interrupt again.
Re-check CCI for a pending connector state change after
initialization is complete. Adjust the corresponding debug
message accordingly.
Fixes: 71a1fa0df2a3 ("usb: typec: ucsi: Store the notification mask")
Cc: stable@vger.kernel.org
Signed-off-by: Christian A. Ehrhardt <lk@c--e.de>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/20240320073927.1641788-3-lk@c--e.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/usb/typec/ucsi/ucsi.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/drivers/usb/typec/ucsi/ucsi.c
+++ b/drivers/usb/typec/ucsi/ucsi.c
@@ -854,7 +854,7 @@ void ucsi_connector_change(struct ucsi *
struct ucsi_connector *con = &ucsi->connector[num - 1];
if (!(ucsi->ntfy & UCSI_ENABLE_NTFY_CONNECTOR_CHANGE)) {
- dev_dbg(ucsi->dev, "Bogus connector change event\n");
+ dev_dbg(ucsi->dev, "Early connector change event\n");
return;
}
@@ -1241,6 +1241,7 @@ static int ucsi_init(struct ucsi *ucsi)
{
struct ucsi_connector *con;
u64 command, ntfy;
+ u32 cci;
int ret;
int i;
@@ -1292,6 +1293,13 @@ static int ucsi_init(struct ucsi *ucsi)
goto err_unregister;
ucsi->ntfy = ntfy;
+
+ ret = ucsi->ops->read(ucsi, UCSI_CCI, &cci, sizeof(cci));
+ if (ret)
+ return ret;
+ if (UCSI_CCI_CONNECTOR(READ_ONCE(cci)))
+ ucsi_connector_change(ucsi, cci);
+
return 0;
err_unregister:
^ permalink raw reply [relevance 4%]
* [PATCH 5.10 092/111] usb: typec: ucsi: Check for notifications after init
@ 2024-05-14 10:20 4% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2024-05-14 10:20 UTC (permalink / raw)
To: stable
Cc: Greg Kroah-Hartman, patches, Christian A. Ehrhardt,
Heikki Krogerus, Neil Armstrong
5.10-stable review patch. If anyone has any objections, please let me know.
------------------
From: Christian A. Ehrhardt <lk@c--e.de>
commit 808a8b9e0b87bbc72bcc1f7ddfe5d04746e7ce56 upstream.
The completion notification for the final SET_NOTIFICATION_ENABLE
command during initialization can include a connector change
notification. However, at the time this completion notification is
processed, the ucsi struct is not ready to handle this notification.
As a result the notification is ignored and the controller
never sends an interrupt again.
Re-check CCI for a pending connector state change after
initialization is complete. Adjust the corresponding debug
message accordingly.
Fixes: 71a1fa0df2a3 ("usb: typec: ucsi: Store the notification mask")
Cc: stable@vger.kernel.org
Signed-off-by: Christian A. Ehrhardt <lk@c--e.de>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/20240320073927.1641788-3-lk@c--e.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/usb/typec/ucsi/ucsi.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/drivers/usb/typec/ucsi/ucsi.c
+++ b/drivers/usb/typec/ucsi/ucsi.c
@@ -827,7 +827,7 @@ void ucsi_connector_change(struct ucsi *
struct ucsi_connector *con = &ucsi->connector[num - 1];
if (!(ucsi->ntfy & UCSI_ENABLE_NTFY_CONNECTOR_CHANGE)) {
- dev_dbg(ucsi->dev, "Bogus connector change event\n");
+ dev_dbg(ucsi->dev, "Early connector change event\n");
return;
}
@@ -1191,6 +1191,7 @@ static int ucsi_init(struct ucsi *ucsi)
{
struct ucsi_connector *con;
u64 command, ntfy;
+ u32 cci;
int ret;
int i;
@@ -1242,6 +1243,13 @@ static int ucsi_init(struct ucsi *ucsi)
goto err_unregister;
ucsi->ntfy = ntfy;
+
+ ret = ucsi->ops->read(ucsi, UCSI_CCI, &cci, sizeof(cci));
+ if (ret)
+ return ret;
+ if (UCSI_CCI_CONNECTOR(READ_ONCE(cci)))
+ ucsi_connector_change(ucsi, cci);
+
return 0;
err_unregister:
^ permalink raw reply [relevance 4%]
* [PATCH 6.1 192/236] usb: typec: ucsi: Check for notifications after init
@ 2024-05-14 10:19 4% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2024-05-14 10:19 UTC (permalink / raw)
To: stable
Cc: Greg Kroah-Hartman, patches, Christian A. Ehrhardt,
Heikki Krogerus, Neil Armstrong
6.1-stable review patch. If anyone has any objections, please let me know.
------------------
From: Christian A. Ehrhardt <lk@c--e.de>
commit 808a8b9e0b87bbc72bcc1f7ddfe5d04746e7ce56 upstream.
The completion notification for the final SET_NOTIFICATION_ENABLE
command during initialization can include a connector change
notification. However, at the time this completion notification is
processed, the ucsi struct is not ready to handle this notification.
As a result the notification is ignored and the controller
never sends an interrupt again.
Re-check CCI for a pending connector state change after
initialization is complete. Adjust the corresponding debug
message accordingly.
Fixes: 71a1fa0df2a3 ("usb: typec: ucsi: Store the notification mask")
Cc: stable@vger.kernel.org
Signed-off-by: Christian A. Ehrhardt <lk@c--e.de>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/20240320073927.1641788-3-lk@c--e.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/usb/typec/ucsi/ucsi.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/drivers/usb/typec/ucsi/ucsi.c
+++ b/drivers/usb/typec/ucsi/ucsi.c
@@ -855,7 +855,7 @@ void ucsi_connector_change(struct ucsi *
struct ucsi_connector *con = &ucsi->connector[num - 1];
if (!(ucsi->ntfy & UCSI_ENABLE_NTFY_CONNECTOR_CHANGE)) {
- dev_dbg(ucsi->dev, "Bogus connector change event\n");
+ dev_dbg(ucsi->dev, "Early connector change event\n");
return;
}
@@ -1248,6 +1248,7 @@ static int ucsi_init(struct ucsi *ucsi)
{
struct ucsi_connector *con, *connector;
u64 command, ntfy;
+ u32 cci;
int ret;
int i;
@@ -1300,6 +1301,13 @@ static int ucsi_init(struct ucsi *ucsi)
ucsi->connector = connector;
ucsi->ntfy = ntfy;
+
+ ret = ucsi->ops->read(ucsi, UCSI_CCI, &cci, sizeof(cci));
+ if (ret)
+ return ret;
+ if (UCSI_CCI_CONNECTOR(READ_ONCE(cci)))
+ ucsi_connector_change(ucsi, cci);
+
return 0;
err_unregister:
^ permalink raw reply [relevance 4%]
* [PATCH 6.6 225/301] usb: typec: ucsi: Check for notifications after init
@ 2024-05-14 10:18 4% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2024-05-14 10:18 UTC (permalink / raw)
To: stable
Cc: Greg Kroah-Hartman, patches, Christian A. Ehrhardt,
Heikki Krogerus, Neil Armstrong
6.6-stable review patch. If anyone has any objections, please let me know.
------------------
From: Christian A. Ehrhardt <lk@c--e.de>
commit 808a8b9e0b87bbc72bcc1f7ddfe5d04746e7ce56 upstream.
The completion notification for the final SET_NOTIFICATION_ENABLE
command during initialization can include a connector change
notification. However, at the time this completion notification is
processed, the ucsi struct is not ready to handle this notification.
As a result the notification is ignored and the controller
never sends an interrupt again.
Re-check CCI for a pending connector state change after
initialization is complete. Adjust the corresponding debug
message accordingly.
Fixes: 71a1fa0df2a3 ("usb: typec: ucsi: Store the notification mask")
Cc: stable@vger.kernel.org
Signed-off-by: Christian A. Ehrhardt <lk@c--e.de>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/20240320073927.1641788-3-lk@c--e.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/usb/typec/ucsi/ucsi.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/drivers/usb/typec/ucsi/ucsi.c
+++ b/drivers/usb/typec/ucsi/ucsi.c
@@ -972,7 +972,7 @@ void ucsi_connector_change(struct ucsi *
struct ucsi_connector *con = &ucsi->connector[num - 1];
if (!(ucsi->ntfy & UCSI_ENABLE_NTFY_CONNECTOR_CHANGE)) {
- dev_dbg(ucsi->dev, "Bogus connector change event\n");
+ dev_dbg(ucsi->dev, "Early connector change event\n");
return;
}
@@ -1403,6 +1403,7 @@ static int ucsi_init(struct ucsi *ucsi)
{
struct ucsi_connector *con, *connector;
u64 command, ntfy;
+ u32 cci;
int ret;
int i;
@@ -1455,6 +1456,13 @@ static int ucsi_init(struct ucsi *ucsi)
ucsi->connector = connector;
ucsi->ntfy = ntfy;
+
+ ret = ucsi->ops->read(ucsi, UCSI_CCI, &cci, sizeof(cci));
+ if (ret)
+ return ret;
+ if (UCSI_CCI_CONNECTOR(READ_ONCE(cci)))
+ ucsi_connector_change(ucsi, cci);
+
return 0;
err_unregister:
^ permalink raw reply [relevance 4%]
* [PATCH 6.8 245/336] usb: typec: ucsi: Check for notifications after init
@ 2024-05-14 10:17 4% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2024-05-14 10:17 UTC (permalink / raw)
To: stable
Cc: Greg Kroah-Hartman, patches, Christian A. Ehrhardt,
Heikki Krogerus, Neil Armstrong
6.8-stable review patch. If anyone has any objections, please let me know.
------------------
From: Christian A. Ehrhardt <lk@c--e.de>
commit 808a8b9e0b87bbc72bcc1f7ddfe5d04746e7ce56 upstream.
The completion notification for the final SET_NOTIFICATION_ENABLE
command during initialization can include a connector change
notification. However, at the time this completion notification is
processed, the ucsi struct is not ready to handle this notification.
As a result the notification is ignored and the controller
never sends an interrupt again.
Re-check CCI for a pending connector state change after
initialization is complete. Adjust the corresponding debug
message accordingly.
Fixes: 71a1fa0df2a3 ("usb: typec: ucsi: Store the notification mask")
Cc: stable@vger.kernel.org
Signed-off-by: Christian A. Ehrhardt <lk@c--e.de>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/20240320073927.1641788-3-lk@c--e.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/usb/typec/ucsi/ucsi.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/drivers/usb/typec/ucsi/ucsi.c
+++ b/drivers/usb/typec/ucsi/ucsi.c
@@ -975,7 +975,7 @@ void ucsi_connector_change(struct ucsi *
struct ucsi_connector *con = &ucsi->connector[num - 1];
if (!(ucsi->ntfy & UCSI_ENABLE_NTFY_CONNECTOR_CHANGE)) {
- dev_dbg(ucsi->dev, "Bogus connector change event\n");
+ dev_dbg(ucsi->dev, "Early connector change event\n");
return;
}
@@ -1406,6 +1406,7 @@ static int ucsi_init(struct ucsi *ucsi)
{
struct ucsi_connector *con, *connector;
u64 command, ntfy;
+ u32 cci;
int ret;
int i;
@@ -1458,6 +1459,13 @@ static int ucsi_init(struct ucsi *ucsi)
ucsi->connector = connector;
ucsi->ntfy = ntfy;
+
+ ret = ucsi->ops->read(ucsi, UCSI_CCI, &cci, sizeof(cci));
+ if (ret)
+ return ret;
+ if (UCSI_CCI_CONNECTOR(READ_ONCE(cci)))
+ ucsi_connector_change(ucsi, cci);
+
return 0;
err_unregister:
^ permalink raw reply [relevance 4%]
* Re: [PATCH v8 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi
2024-05-14 1:21 0% ` Aiqun Yu (Maria)
@ 2024-05-14 2:05 0% ` Tengfei Fan
0 siblings, 0 replies; 200+ results
From: Tengfei Fan @ 2024-05-14 2:05 UTC (permalink / raw)
To: Aiqun Yu (Maria),
Trilok Soni, andersson, konrad.dybcio, robh, krzk+dt, conor+dt,
dmitry.baryshkov
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel
On 5/14/2024 9:21 AM, Aiqun Yu (Maria) wrote:
>
>
> On 5/14/2024 12:37 AM, Trilok Soni wrote:
>> On 5/13/2024 2:07 AM, Tengfei Fan wrote:
>>> QCS8550 is derived from SM8550. The differnece between SM8550 and
>>
>> spellcheck s/difference/difference
Typos wil be modified.
>>
>>> QCS8550 is QCS8550 doesn't have modem RF system. QCS8550 is mainly used
>>> in IoT scenarios.
>>
>> IoT products and not scenarios.
I will modify this description.
>>
>>> QCS8550 firmware has different memory map with SM8550 firmware.
>>
>> "QCS8550 firmware has different memory map compared to SM8550"
>>
>>
>> The
>>> memory map will be runtime added through bootloader.
In the next version of the patch series, I will add "The" to make the
sentence's grammar more complete.
>>
>>
>>> There are 3 types of reserved memory regions here:
>>> 1. Firmware related regions which aren't shared with kernel.
>>> The device tree source in kernel doesn't need to have node to indicate
>>> the firmware related reserved information. OS bootloader conveys the
>>
>> Just "Bootloader conveys the information by updating devicetree at runtime" ?
I will modify this description.
>>
>>> information by update device tree in runtime.
>>> This will be described as: UEFI saves the physical address of the
>>> UEFI System Table to dts file's chosen node. Kernel read this table and
>>> add reserved memory regions to efi config table. Current reserved memory
>>> region may have reserved region which was not yet used, release note of
>>> the firmware have such kind of information.
>>
>> I understand what you are trying to explain below, but can we simplify further? I
>> had to read multiple times to understand what you are trying to convey above.
>>
>>> 2. Firmware related memory regions which are shared with Kernel
>>> Each region has a specific node with specific label name for later
>>> phandle reference from other driver dt node.
>
> How about like this:
> 2. Firmware related memory regions which are shared with Kernel
> The device tree source in the kernel needs to include nodes that
> indicate firmware-related shared information. A label name is suggested
> because this type of shared information needs to be referenced by
> specific drivers for handling purposes.
>
>>> 3. PIL regions.
>>
>> Do we use the PIL - peripheral image loader in the upstream kernel or just remoteproc?
>> I am fine w/ PIL if it is used at other places in Qualcomm remoteproc.
We are only used for remoteproc in the upstream kernel, and I will
remove the description related to PIL.
>>
>>> PIL regions will be reserved and then assigned to subsystem firmware
>>> later.
>>> Here is a reserved memory map for this platform:
>>> 0x100000000 +------------------+
>>> | |
>>> | Firmware Related |
>>> | |
>>> 0xd4d00000 +------------------+
>>> | |
>>> | Kernel Available |
>>
>> What is "kernel available" means?
>
> It means not reserved memory, normal available memory from kernel point
> of view.
>
>>
>>> | |
>>> 0xa7000000 +------------------+
>>> | |
>>> | PIL Region |
>>> | |
>>> 0x8a800000 +------------------+
>>> | |
>>> | Firmware Related |
>>> | |
>>> 0x80000000 +------------------+
>>
>>> Note that:
>>
>> Do we need to write "Note that:" ?
This "Note that:" will be removed.
>>
>>> 0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
>>> it is available for kernel usage. This region is not suggested to be
>>> used by kernel features like ramoops, suspend resume etc.
>>>
>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++++++++++++++++++++
>>> 1 file changed, 169 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8550.dtsi b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
>>> new file mode 100644
>>> index 000000000000..a3ebf3d4e16d
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
>>> @@ -0,0 +1,169 @@
>>> +// SPDX-License-Identifier: BSD-3-Clause
>>> +/*
>>> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
>>> + */
>>> +
>>> +#include "sm8550.dtsi"
>>> +
>>> +/delete-node/ &reserved_memory;
>>> +
>>> +/ {
>>> + reserved_memory: reserved-memory {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges;
>>> +
>>> +
>>> + /* These are 3 types of reserved memory regions here:
>>> + * 1. Firmware related regions which aren't shared with kernel.
>>> + * The device tree source in kernel doesn't need to have node to
>>> + * indicate the firmware related reserved information. OS bootloader
>>> + * conveys the information by update device tree in runtime.
>>> + * This will be described as: UEFI saves the physical address of
>>> + * the UEFI System Table to dts file's chosen node. Kernel read this
>>> + * table and add reserved memory regions to efi config table. Current
>>> + * reserved memory region may have reserved region which was not yet
>>> + * used, release note of the firmware have such kind of information.
>>> + * 2. Firmware related memory regions which are shared with Kernel.
>>> + * Each region has a specific node with specific label name for
>>> + * later phandle reference from other driver dt node.
>>> + * 3. PIL regions.
>>> + * PIL regions will be reserved and then assigned to subsystem
>>> + * firmware later.
>>> + * Here is a reserved memory map for this platform:
>>
>> Just check the comment above and it will apply here.
Sure, I will modify these according to the comments above.
>>
>>> + * 0x100000000 +------------------+
>>> + * | |
>>> + * | Firmware Related |
>>> + * | |
>>> + * 0xd4d00000 +------------------+
>>> + * | |
>>> + * | Kernel Available |
>>> + * | |
>>> + * 0xa7000000 +------------------+
>>> + * | |
>>> + * | PIL Region |
>>> + * | |
>>> + * 0x8a800000 +------------------+
>>> + * | |
>>> + * | Firmware Related |
>>> + * | |
>>> + * 0x80000000 +------------------+
>>> + * Note that:
>>> + * 0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
>>> + * it is available for kernel usage. This region is not suggested to
>>> + * be used by kernel features like ramoops, suspend resume etc.
>>> + */
>>> +
>>> + /*
>>> + * Firmware related regions, bootlader will possible reserve parts of
>>
>> spellcheck s/bootlader/bootloader
Typos wil be modified.
>>
>>> + * region from 0x80000000..0x8a800000.
>>> + */
>>> + aop_image_mem: aop-image-region@81c00000 {
>>> + reg = <0x0 0x81c00000 0x0 0x60000>;
>>> + no-map;
>>> + };
>>> +
>>> + aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
>>> + compatible = "qcom,cmd-db";
>>> + reg = <0x0 0x81c60000 0x0 0x20000>;
>>> + no-map;
>>> + };
>>> +
>>> + aop_config_mem: aop-config-region@81c80000 {
>>> + no-map;
>>> + reg = <0x0 0x81c80000 0x0 0x20000>;
>>> + };
>>> +
>>> + smem_mem: smem-region@81d00000 {
>>> + compatible = "qcom,smem";
>>> + reg = <0x0 0x81d00000 0x0 0x200000>;
>>> + hwlocks = <&tcsr_mutex 3>;
>>> + no-map;
>>> + };
>>> +
>>> + adsp_mhi_mem: adsp-mhi-region@81f00000 {
>>> + reg = <0x0 0x81f00000 0x0 0x20000>;
>>> + no-map;
>>> + };
>>> +
>>> + /* PIL region */
>>> + mpss_mem: mpss-region@8a800000 {
>>> + reg = <0x0 0x8a800000 0x0 0x10800000>;
>>> + no-map;
>>> + };
>>> +
>>> + q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
>>> + reg = <0x0 0x9b000000 0x0 0x80000>;
>>> + no-map;
>>> + };
>>> +
>>> + ipa_fw_mem: ipa-fw-region@9b080000 {
>>> + reg = <0x0 0x9b080000 0x0 0x10000>;
>>> + no-map;
>>> + };
>>> +
>>> + ipa_gsi_mem: ipa-gsi-region@9b090000 {
>>> + reg = <0x0 0x9b090000 0x0 0xa000>;
>>> + no-map;
>>> + };
>>> +
>>> + gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
>>> + reg = <0x0 0x9b09a000 0x0 0x2000>;
>>> + no-map;
>>> + };
>>> +
>>> + spss_region_mem: spss-region@9b100000 {
>>> + reg = <0x0 0x9b100000 0x0 0x180000>;
>>> + no-map;
>>> + };
>>> +
>>> + spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 {
>>> + reg = <0x0 0x9b280000 0x0 0x80000>;
>>> + no-map;
>>> + };
>>> +
>>> + camera_mem: camera-region@9b300000 {
>>> + reg = <0x0 0x9b300000 0x0 0x800000>;
>>> + no-map;
>>> + };
>>> +
>>> + video_mem: video-region@9bb00000 {
>>> + reg = <0x0 0x9bb00000 0x0 0x700000>;
>>> + no-map;
>>> + };
>>> +
>>> + cvp_mem: cvp-region@9c200000 {
>>> + reg = <0x0 0x9c200000 0x0 0x700000>;
>>> + no-map;
>>> + };
>>> +
>>> + cdsp_mem: cdsp-region@9c900000 {
>>> + reg = <0x0 0x9c900000 0x0 0x2000000>;
>>> + no-map;
>>> + };
>>> +
>>> + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
>>> + reg = <0x0 0x9e900000 0x0 0x80000>;
>>> + no-map;
>>> + };
>>> +
>>> + q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
>>> + reg = <0x0 0x9e980000 0x0 0x80000>;
>>> + no-map;
>>> + };
>>> +
>>> + adspslpi_mem: adspslpi-region@9ea00000 {
>>> + reg = <0x0 0x9ea00000 0x0 0x4080000>;
>>> + no-map;
>>> + };
>>> +
>>> + /*
>>> + * Firmware related regions, bootlader will possible reserve parts of
>>
>> Ditto.
Typos wil be modified.
>>
>>> + * region from 0xd8000000..0x100000000.
>>> + */
>>> + mpss_dsm_mem: mpss_dsm_region@d4d00000 {
>>> + reg = <0x0 0xd4d00000 0x0 0x3300000>;
>>> + no-map;
>>> + };
>>> + };
>>> +};
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [relevance 0%]
* Re: [PATCH v8 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi
2024-05-13 16:37 4% ` Trilok Soni
@ 2024-05-14 1:21 0% ` Aiqun Yu (Maria)
2024-05-14 2:05 0% ` Tengfei Fan
0 siblings, 1 reply; 200+ results
From: Aiqun Yu (Maria) @ 2024-05-14 1:21 UTC (permalink / raw)
To: Trilok Soni, Tengfei Fan, andersson, konrad.dybcio, robh,
krzk+dt, conor+dt, dmitry.baryshkov
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel
On 5/14/2024 12:37 AM, Trilok Soni wrote:
> On 5/13/2024 2:07 AM, Tengfei Fan wrote:
>> QCS8550 is derived from SM8550. The differnece between SM8550 and
>
> spellcheck s/difference/difference
>
>> QCS8550 is QCS8550 doesn't have modem RF system. QCS8550 is mainly used
>> in IoT scenarios.
>
> IoT products and not scenarios.
>
>> QCS8550 firmware has different memory map with SM8550 firmware.
>
> "QCS8550 firmware has different memory map compared to SM8550"
>
>
> The
>> memory map will be runtime added through bootloader.
>
>
>> There are 3 types of reserved memory regions here:
>> 1. Firmware related regions which aren't shared with kernel.
>> The device tree source in kernel doesn't need to have node to indicate
>> the firmware related reserved information. OS bootloader conveys the
>
> Just "Bootloader conveys the information by updating devicetree at runtime" ?
>
>> information by update device tree in runtime.
>> This will be described as: UEFI saves the physical address of the
>> UEFI System Table to dts file's chosen node. Kernel read this table and
>> add reserved memory regions to efi config table. Current reserved memory
>> region may have reserved region which was not yet used, release note of
>> the firmware have such kind of information.
>
> I understand what you are trying to explain below, but can we simplify further? I
> had to read multiple times to understand what you are trying to convey above.
>
>> 2. Firmware related memory regions which are shared with Kernel
>> Each region has a specific node with specific label name for later
>> phandle reference from other driver dt node.
How about like this:
2. Firmware related memory regions which are shared with Kernel
The device tree source in the kernel needs to include nodes that
indicate firmware-related shared information. A label name is suggested
because this type of shared information needs to be referenced by
specific drivers for handling purposes.
>> 3. PIL regions.
>
> Do we use the PIL - peripheral image loader in the upstream kernel or just remoteproc?
> I am fine w/ PIL if it is used at other places in Qualcomm remoteproc.
>
>> PIL regions will be reserved and then assigned to subsystem firmware
>> later.
>> Here is a reserved memory map for this platform:
>> 0x100000000 +------------------+
>> | |
>> | Firmware Related |
>> | |
>> 0xd4d00000 +------------------+
>> | |
>> | Kernel Available |
>
> What is "kernel available" means?
It means not reserved memory, normal available memory from kernel point
of view.
>
>> | |
>> 0xa7000000 +------------------+
>> | |
>> | PIL Region |
>> | |
>> 0x8a800000 +------------------+
>> | |
>> | Firmware Related |
>> | |
>> 0x80000000 +------------------+
>
>> Note that:
>
> Do we need to write "Note that:" ?
>
>> 0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
>> it is available for kernel usage. This region is not suggested to be
>> used by kernel features like ramoops, suspend resume etc.
>>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++++++++++++++++++++
>> 1 file changed, 169 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8550.dtsi b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
>> new file mode 100644
>> index 000000000000..a3ebf3d4e16d
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
>> @@ -0,0 +1,169 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include "sm8550.dtsi"
>> +
>> +/delete-node/ &reserved_memory;
>> +
>> +/ {
>> + reserved_memory: reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> +
>> + /* These are 3 types of reserved memory regions here:
>> + * 1. Firmware related regions which aren't shared with kernel.
>> + * The device tree source in kernel doesn't need to have node to
>> + * indicate the firmware related reserved information. OS bootloader
>> + * conveys the information by update device tree in runtime.
>> + * This will be described as: UEFI saves the physical address of
>> + * the UEFI System Table to dts file's chosen node. Kernel read this
>> + * table and add reserved memory regions to efi config table. Current
>> + * reserved memory region may have reserved region which was not yet
>> + * used, release note of the firmware have such kind of information.
>> + * 2. Firmware related memory regions which are shared with Kernel.
>> + * Each region has a specific node with specific label name for
>> + * later phandle reference from other driver dt node.
>> + * 3. PIL regions.
>> + * PIL regions will be reserved and then assigned to subsystem
>> + * firmware later.
>> + * Here is a reserved memory map for this platform:
>
> Just check the comment above and it will apply here.
>
>> + * 0x100000000 +------------------+
>> + * | |
>> + * | Firmware Related |
>> + * | |
>> + * 0xd4d00000 +------------------+
>> + * | |
>> + * | Kernel Available |
>> + * | |
>> + * 0xa7000000 +------------------+
>> + * | |
>> + * | PIL Region |
>> + * | |
>> + * 0x8a800000 +------------------+
>> + * | |
>> + * | Firmware Related |
>> + * | |
>> + * 0x80000000 +------------------+
>> + * Note that:
>> + * 0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
>> + * it is available for kernel usage. This region is not suggested to
>> + * be used by kernel features like ramoops, suspend resume etc.
>> + */
>> +
>> + /*
>> + * Firmware related regions, bootlader will possible reserve parts of
>
> spellcheck s/bootlader/bootloader
>
>> + * region from 0x80000000..0x8a800000.
>> + */
>> + aop_image_mem: aop-image-region@81c00000 {
>> + reg = <0x0 0x81c00000 0x0 0x60000>;
>> + no-map;
>> + };
>> +
>> + aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
>> + compatible = "qcom,cmd-db";
>> + reg = <0x0 0x81c60000 0x0 0x20000>;
>> + no-map;
>> + };
>> +
>> + aop_config_mem: aop-config-region@81c80000 {
>> + no-map;
>> + reg = <0x0 0x81c80000 0x0 0x20000>;
>> + };
>> +
>> + smem_mem: smem-region@81d00000 {
>> + compatible = "qcom,smem";
>> + reg = <0x0 0x81d00000 0x0 0x200000>;
>> + hwlocks = <&tcsr_mutex 3>;
>> + no-map;
>> + };
>> +
>> + adsp_mhi_mem: adsp-mhi-region@81f00000 {
>> + reg = <0x0 0x81f00000 0x0 0x20000>;
>> + no-map;
>> + };
>> +
>> + /* PIL region */
>> + mpss_mem: mpss-region@8a800000 {
>> + reg = <0x0 0x8a800000 0x0 0x10800000>;
>> + no-map;
>> + };
>> +
>> + q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
>> + reg = <0x0 0x9b000000 0x0 0x80000>;
>> + no-map;
>> + };
>> +
>> + ipa_fw_mem: ipa-fw-region@9b080000 {
>> + reg = <0x0 0x9b080000 0x0 0x10000>;
>> + no-map;
>> + };
>> +
>> + ipa_gsi_mem: ipa-gsi-region@9b090000 {
>> + reg = <0x0 0x9b090000 0x0 0xa000>;
>> + no-map;
>> + };
>> +
>> + gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
>> + reg = <0x0 0x9b09a000 0x0 0x2000>;
>> + no-map;
>> + };
>> +
>> + spss_region_mem: spss-region@9b100000 {
>> + reg = <0x0 0x9b100000 0x0 0x180000>;
>> + no-map;
>> + };
>> +
>> + spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 {
>> + reg = <0x0 0x9b280000 0x0 0x80000>;
>> + no-map;
>> + };
>> +
>> + camera_mem: camera-region@9b300000 {
>> + reg = <0x0 0x9b300000 0x0 0x800000>;
>> + no-map;
>> + };
>> +
>> + video_mem: video-region@9bb00000 {
>> + reg = <0x0 0x9bb00000 0x0 0x700000>;
>> + no-map;
>> + };
>> +
>> + cvp_mem: cvp-region@9c200000 {
>> + reg = <0x0 0x9c200000 0x0 0x700000>;
>> + no-map;
>> + };
>> +
>> + cdsp_mem: cdsp-region@9c900000 {
>> + reg = <0x0 0x9c900000 0x0 0x2000000>;
>> + no-map;
>> + };
>> +
>> + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
>> + reg = <0x0 0x9e900000 0x0 0x80000>;
>> + no-map;
>> + };
>> +
>> + q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
>> + reg = <0x0 0x9e980000 0x0 0x80000>;
>> + no-map;
>> + };
>> +
>> + adspslpi_mem: adspslpi-region@9ea00000 {
>> + reg = <0x0 0x9ea00000 0x0 0x4080000>;
>> + no-map;
>> + };
>> +
>> + /*
>> + * Firmware related regions, bootlader will possible reserve parts of
>
> Ditto.
>
>> + * region from 0xd8000000..0x100000000.
>> + */
>> + mpss_dsm_mem: mpss_dsm_region@d4d00000 {
>> + reg = <0x0 0xd4d00000 0x0 0x3300000>;
>> + no-map;
>> + };
>> + };
>> +};
--
Thx and BRs,
Aiqun(Maria) Yu
^ permalink raw reply [relevance 0%]
* Re: [PATCH] arm64: dts: qcom: sm8550: Move some common usb node settings to SoC dtsi
2024-05-13 8:56 4% ` Krzysztof Kozlowski
@ 2024-05-14 0:52 4% ` Tengfei Fan
0 siblings, 0 replies; 200+ results
From: Tengfei Fan @ 2024-05-14 0:52 UTC (permalink / raw)
To: Krzysztof Kozlowski, andersson, konrad.dybcio, robh, krzk+dt, conor+dt
Cc: linux-arm-msm, devicetree, linux-kernel, kernel
On 5/13/2024 4:56 PM, Krzysztof Kozlowski wrote:
> On 13/05/2024 10:47, Tengfei Fan wrote:
>> All the board dts which base on SM8550 SoC dtsi refer to usb_1_dwc3_ss,
>> usb_dp_qmpphy_usb_ss_in, orientation-switch and usb-role-switch, so move
>> them to SoC dtsi from board dts.
>
> That's not really a good argument. Argument is that it is a SoC property
> (vs being a property of a board). Provide rationale for that. You are
> moving things just because they look common, so to me it looks really
> unjustified.
In the next version of the patch series, I will modify the commit
message to more accurately indicate why they need to be moved SoC dtsi.
>
>> OTG is default for dr_mode, so it can be dropped from board dts.
>
> Separate patch, see submitting patches.
In the next version of the patch series, I will separate this.
>
> Best regards,
> Krzysztof
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [relevance 4%]
* Re: [PATCH v8 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi
2024-05-13 9:07 9% ` [PATCH v8 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi Tengfei Fan
@ 2024-05-13 16:37 4% ` Trilok Soni
2024-05-14 1:21 0% ` Aiqun Yu (Maria)
0 siblings, 1 reply; 200+ results
From: Trilok Soni @ 2024-05-13 16:37 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh, krzk+dt, conor+dt,
dmitry.baryshkov
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel
On 5/13/2024 2:07 AM, Tengfei Fan wrote:
> QCS8550 is derived from SM8550. The differnece between SM8550 and
spellcheck s/difference/difference
> QCS8550 is QCS8550 doesn't have modem RF system. QCS8550 is mainly used
> in IoT scenarios.
IoT products and not scenarios.
> QCS8550 firmware has different memory map with SM8550 firmware.
"QCS8550 firmware has different memory map compared to SM8550"
The
> memory map will be runtime added through bootloader.
> There are 3 types of reserved memory regions here:
> 1. Firmware related regions which aren't shared with kernel.
> The device tree source in kernel doesn't need to have node to indicate
> the firmware related reserved information. OS bootloader conveys the
Just "Bootloader conveys the information by updating devicetree at runtime" ?
> information by update device tree in runtime.
> This will be described as: UEFI saves the physical address of the
> UEFI System Table to dts file's chosen node. Kernel read this table and
> add reserved memory regions to efi config table. Current reserved memory
> region may have reserved region which was not yet used, release note of
> the firmware have such kind of information.
I understand what you are trying to explain below, but can we simplify further? I
had to read multiple times to understand what you are trying to convey above.
> 2. Firmware related memory regions which are shared with Kernel
> Each region has a specific node with specific label name for later
> phandle reference from other driver dt node.
> 3. PIL regions.
Do we use the PIL - peripheral image loader in the upstream kernel or just remoteproc?
I am fine w/ PIL if it is used at other places in Qualcomm remoteproc.
> PIL regions will be reserved and then assigned to subsystem firmware
> later.
> Here is a reserved memory map for this platform:
> 0x100000000 +------------------+
> | |
> | Firmware Related |
> | |
> 0xd4d00000 +------------------+
> | |
> | Kernel Available |
What is "kernel available" means?
> | |
> 0xa7000000 +------------------+
> | |
> | PIL Region |
> | |
> 0x8a800000 +------------------+
> | |
> | Firmware Related |
> | |
> 0x80000000 +------------------+
> Note that:
Do we need to write "Note that:" ?
> 0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
> it is available for kernel usage. This region is not suggested to be
> used by kernel features like ramoops, suspend resume etc.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++++++++++++++++++++
> 1 file changed, 169 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8550.dtsi b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
> new file mode 100644
> index 000000000000..a3ebf3d4e16d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
> @@ -0,0 +1,169 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include "sm8550.dtsi"
> +
> +/delete-node/ &reserved_memory;
> +
> +/ {
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> +
> + /* These are 3 types of reserved memory regions here:
> + * 1. Firmware related regions which aren't shared with kernel.
> + * The device tree source in kernel doesn't need to have node to
> + * indicate the firmware related reserved information. OS bootloader
> + * conveys the information by update device tree in runtime.
> + * This will be described as: UEFI saves the physical address of
> + * the UEFI System Table to dts file's chosen node. Kernel read this
> + * table and add reserved memory regions to efi config table. Current
> + * reserved memory region may have reserved region which was not yet
> + * used, release note of the firmware have such kind of information.
> + * 2. Firmware related memory regions which are shared with Kernel.
> + * Each region has a specific node with specific label name for
> + * later phandle reference from other driver dt node.
> + * 3. PIL regions.
> + * PIL regions will be reserved and then assigned to subsystem
> + * firmware later.
> + * Here is a reserved memory map for this platform:
Just check the comment above and it will apply here.
> + * 0x100000000 +------------------+
> + * | |
> + * | Firmware Related |
> + * | |
> + * 0xd4d00000 +------------------+
> + * | |
> + * | Kernel Available |
> + * | |
> + * 0xa7000000 +------------------+
> + * | |
> + * | PIL Region |
> + * | |
> + * 0x8a800000 +------------------+
> + * | |
> + * | Firmware Related |
> + * | |
> + * 0x80000000 +------------------+
> + * Note that:
> + * 0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
> + * it is available for kernel usage. This region is not suggested to
> + * be used by kernel features like ramoops, suspend resume etc.
> + */
> +
> + /*
> + * Firmware related regions, bootlader will possible reserve parts of
spellcheck s/bootlader/bootloader
> + * region from 0x80000000..0x8a800000.
> + */
> + aop_image_mem: aop-image-region@81c00000 {
> + reg = <0x0 0x81c00000 0x0 0x60000>;
> + no-map;
> + };
> +
> + aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
> + compatible = "qcom,cmd-db";
> + reg = <0x0 0x81c60000 0x0 0x20000>;
> + no-map;
> + };
> +
> + aop_config_mem: aop-config-region@81c80000 {
> + no-map;
> + reg = <0x0 0x81c80000 0x0 0x20000>;
> + };
> +
> + smem_mem: smem-region@81d00000 {
> + compatible = "qcom,smem";
> + reg = <0x0 0x81d00000 0x0 0x200000>;
> + hwlocks = <&tcsr_mutex 3>;
> + no-map;
> + };
> +
> + adsp_mhi_mem: adsp-mhi-region@81f00000 {
> + reg = <0x0 0x81f00000 0x0 0x20000>;
> + no-map;
> + };
> +
> + /* PIL region */
> + mpss_mem: mpss-region@8a800000 {
> + reg = <0x0 0x8a800000 0x0 0x10800000>;
> + no-map;
> + };
> +
> + q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
> + reg = <0x0 0x9b000000 0x0 0x80000>;
> + no-map;
> + };
> +
> + ipa_fw_mem: ipa-fw-region@9b080000 {
> + reg = <0x0 0x9b080000 0x0 0x10000>;
> + no-map;
> + };
> +
> + ipa_gsi_mem: ipa-gsi-region@9b090000 {
> + reg = <0x0 0x9b090000 0x0 0xa000>;
> + no-map;
> + };
> +
> + gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
> + reg = <0x0 0x9b09a000 0x0 0x2000>;
> + no-map;
> + };
> +
> + spss_region_mem: spss-region@9b100000 {
> + reg = <0x0 0x9b100000 0x0 0x180000>;
> + no-map;
> + };
> +
> + spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 {
> + reg = <0x0 0x9b280000 0x0 0x80000>;
> + no-map;
> + };
> +
> + camera_mem: camera-region@9b300000 {
> + reg = <0x0 0x9b300000 0x0 0x800000>;
> + no-map;
> + };
> +
> + video_mem: video-region@9bb00000 {
> + reg = <0x0 0x9bb00000 0x0 0x700000>;
> + no-map;
> + };
> +
> + cvp_mem: cvp-region@9c200000 {
> + reg = <0x0 0x9c200000 0x0 0x700000>;
> + no-map;
> + };
> +
> + cdsp_mem: cdsp-region@9c900000 {
> + reg = <0x0 0x9c900000 0x0 0x2000000>;
> + no-map;
> + };
> +
> + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
> + reg = <0x0 0x9e900000 0x0 0x80000>;
> + no-map;
> + };
> +
> + q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
> + reg = <0x0 0x9e980000 0x0 0x80000>;
> + no-map;
> + };
> +
> + adspslpi_mem: adspslpi-region@9ea00000 {
> + reg = <0x0 0x9ea00000 0x0 0x4080000>;
> + no-map;
> + };
> +
> + /*
> + * Firmware related regions, bootlader will possible reserve parts of
Ditto.
> + * region from 0xd8000000..0x100000000.
> + */
> + mpss_dsm_mem: mpss_dsm_region@d4d00000 {
> + reg = <0x0 0xd4d00000 0x0 0x3300000>;
> + no-map;
> + };
> + };
> +};
--
---Trilok Soni
^ permalink raw reply [relevance 4%]
* Re: [PATCH 6.1 251/272] usb: typec: ucsi: Check for notifications after init
2024-05-01 19:10 0% ` Christian A. Ehrhardt
@ 2024-05-13 13:02 0% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2024-05-13 13:02 UTC (permalink / raw)
To: Christian A. Ehrhardt; +Cc: stable, patches, Heikki Krogerus, Neil Armstrong
On Wed, May 01, 2024 at 09:10:42PM +0200, Christian A. Ehrhardt wrote:
>
> Hi Greg,
>
> On Tue, Apr 02, 2024 at 09:52:47AM +0200, Greg Kroah-Hartman wrote:
> > On Tue, Apr 02, 2024 at 08:06:52AM +0200, Christian A. Ehrhardt wrote:
> > >
> > > Hi Greg,
> > >
> > > On Tue, Apr 02, 2024 at 07:40:43AM +0200, Greg Kroah-Hartman wrote:
> > > > On Mon, Apr 01, 2024 at 10:16:45PM +0200, Christian A. Ehrhardt wrote:
> > > > >
> > > > > Hi Greg,
> > > > >
> > > > > On Mon, Apr 01, 2024 at 05:47:21PM +0200, Greg Kroah-Hartman wrote:
> > > > > > 6.1-stable review patch. If anyone has any objections, please let me know.
> > > > > >
> > > > > > ------------------
> > > > > >
> > > > > > From: Christian A. Ehrhardt <lk@c--e.de>
> > > > > >
> > > > > > commit 808a8b9e0b87bbc72bcc1f7ddfe5d04746e7ce56 upstream.
> > > > > >
> > > > > > The completion notification for the final SET_NOTIFICATION_ENABLE
> > > > > > command during initialization can include a connector change
> > > > > > notification. However, at the time this completion notification is
> > > > > > processed, the ucsi struct is not ready to handle this notification.
> > > > > > As a result the notification is ignored and the controller
> > > > > > never sends an interrupt again.
> > > > > >
> > > > > > Re-check CCI for a pending connector state change after
> > > > > > initialization is complete. Adjust the corresponding debug
> > > > > > message accordingly.
> > > > > >
> > > > > > Fixes: 71a1fa0df2a3 ("usb: typec: ucsi: Store the notification mask")
> > > > > > Cc: stable@vger.kernel.org
> > > > > > Signed-off-by: Christian A. Ehrhardt <lk@c--e.de>
> > > > > > Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> > > > > > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
> > > > > > Link: https://lore.kernel.org/r/20240320073927.1641788-3-lk@c--e.de
> > > > > > Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > > > > > ---
> > > > > > drivers/usb/typec/ucsi/ucsi.c | 10 +++++++++-
> > > > > > 1 file changed, 9 insertions(+), 1 deletion(-)
> > > > >
> > > > > This change has an out of bounds memory access. Please drop it from
> > > > > the stable trees until a fix is available.
> > > >
> > > > Shouldn't we get a fix for Linus's tree too? Have I missed that
> > > > somewhere? Or should this just be reverted now?
> > >
> > > I posted the fix a few hours after sending this mail. It is here:
> > > https://lore.kernel.org/all/20240401210515.1902048-1-lk@c--e.de/
> > >
> > > Either this should be fast tracked to Linus or the original change
> > > reverted, yes.
> >
> > I've dropped the offending commit from the stable queues now. Once this
> > fix gets into Linus's tree, let us know and I will add both in then.
>
> The fix for
> 808a8b9e0b87 ("usb: typec: ucsi: Check for notifications after init")
> has hit Linus's tree as
> ce4c8d21054a ("usb: typec: ucsi: Fix connector check on init")
>
> There is no urgency but this is to let you know that the original commit
> is eligible for -stable again, provided that the follow up commit is
> backported, too.
Thanks, all now queued up.
greg k-h
^ permalink raw reply [relevance 0%]
* [PATCH v8 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT
2024-05-13 9:07 6% [PATCH v8 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
2024-05-13 9:07 16% ` [PATCH v8 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board Tengfei Fan
2024-05-13 9:07 9% ` [PATCH v8 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi Tengfei Fan
@ 2024-05-13 9:07 5% ` Tengfei Fan
2 siblings, 0 replies; 200+ results
From: Tengfei Fan @ 2024-05-13 9:07 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzk+dt, conor+dt, dmitry.baryshkov
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan, Qiang Yu,
Ziyue Zhang
Add AIM300 AIoT Carrier board DTS support, including usb, UART, PCIe,
I2C functions support.
Here is a diagram of AIM300 AIoT Carrie Board and SoM
+--------------------------------------------------+
| AIM300 AIOT Carrier Board |
| |
| +-----------------+ |
|power----->| Fixed regulator |---------+ |
| +-----------------+ | |
| | |
| v VPH_PWR |
| +----------------------------------------------+ |
| | AIM300 SOM | | |
| | |VPH_PWR | |
| | v | |
| | +-------+ +--------+ +------+ | |
| | | UFS | | QCS8550| |PMIC | | |
| | +-------+ +--------+ +------+ | |
| | | |
| +----------------------------------------------+ |
| |
| +----+ +------+ |
| |USB | | UART | |
| +----+ +------+ |
+--------------------------------------------------+
Co-developed-by: Qiang Yu <quic_qianyu@quicinc.com>
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Co-developed-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/qcs8550-aim300-aiot.dts | 322 ++++++++++++++++++
2 files changed, 323 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index f63abb43e9fe..c46c10d85697 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -96,6 +96,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
new file mode 100644
index 000000000000..49759274fb4a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "qcs8550-aim300.dtsi"
+#include "pm8010.dtsi"
+#include "pmr735d_a.dtsi"
+#include "pmr735d_b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCS8550 AIM300 AIOT";
+ compatible = "qcom,qcs8550-aim300-aiot", "qcom,qcs8550-aim300", "qcom,qcs8550",
+ "qcom,sm8550";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ debounce-interval = <15>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&redriver_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&fsa4480_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ };
+
+ regulators-3 {
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ };
+
+ regulators-4 {
+ vdd-s4-supply = <&vph_pwr>;
+ };
+
+ regulators-5 {
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ };
+};
+
+&i2c_hub_2 {
+ status = "okay";
+
+ typec-mux@42 {
+ compatible = "fcs,fsa4480";
+ reg = <0x42>;
+
+ vcc-supply = <&vreg_bob1>;
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ fsa4480_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+
+ typec-retimer@1c {
+ compatible = "onnn,nb7vpq904m";
+ reg = <0x1c>;
+
+ vcc-supply = <&vreg_l15b_1p8>;
+
+ orientation-switch;
+ retimer-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ redriver_ss_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ redriver_ss_in: endpoint {
+ data-lanes = <3 2 1 0>;
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+ };
+ };
+};
+
+&mdss_dsi0 {
+ status = "okay";
+
+ panel@0 {
+ compatible = "visionox,vtdr6130";
+ reg = <0>;
+
+ pinctrl-0 = <&dsi_active>, <&te_active>;
+ pinctrl-1 = <&dsi_suspend>, <&te_suspend>;
+ pinctrl-names = "default", "sleep";
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vci-supply = <&vreg_l13b_3p0>;
+ vdd-supply = <&vreg_l11b_1p2>;
+ vddio-supply = <&vreg_l12b_1p8>;
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie0_phy {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&pcie1_phy {
+ status = "okay";
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/qcs8550/adsp.mbn",
+ "qcom/qcs8550/adsp_dtbs.elf";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcs8550/cdsp.mbn",
+ "qcom/qcs8550/cdsp_dtbs.elf";
+ status = "okay";
+};
+
+&swr1 {
+ status = "okay";
+};
+
+&swr2 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 8>;
+
+ dsi_active: dsi-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ dsi_suspend: dsi-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ te_active: te-active-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ te_suspend: te-suspend-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&redriver_ss_in>;
+};
--
2.25.1
^ permalink raw reply related [relevance 5%]
* [PATCH v8 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi
2024-05-13 9:07 6% [PATCH v8 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
2024-05-13 9:07 16% ` [PATCH v8 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board Tengfei Fan
@ 2024-05-13 9:07 9% ` Tengfei Fan
2024-05-13 16:37 4% ` Trilok Soni
2024-05-13 9:07 5% ` [PATCH v8 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT Tengfei Fan
2 siblings, 1 reply; 200+ results
From: Tengfei Fan @ 2024-05-13 9:07 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzk+dt, conor+dt, dmitry.baryshkov
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan
QCS8550 is derived from SM8550. The differnece between SM8550 and
QCS8550 is QCS8550 doesn't have modem RF system. QCS8550 is mainly used
in IoT scenarios.
QCS8550 firmware has different memory map with SM8550 firmware. The
memory map will be runtime added through bootloader.
There are 3 types of reserved memory regions here:
1. Firmware related regions which aren't shared with kernel.
The device tree source in kernel doesn't need to have node to indicate
the firmware related reserved information. OS bootloader conveys the
information by update device tree in runtime.
This will be described as: UEFI saves the physical address of the
UEFI System Table to dts file's chosen node. Kernel read this table and
add reserved memory regions to efi config table. Current reserved memory
region may have reserved region which was not yet used, release note of
the firmware have such kind of information.
2. Firmware related memory regions which are shared with Kernel
Each region has a specific node with specific label name for later
phandle reference from other driver dt node.
3. PIL regions.
PIL regions will be reserved and then assigned to subsystem firmware
later.
Here is a reserved memory map for this platform:
0x100000000 +------------------+
| |
| Firmware Related |
| |
0xd4d00000 +------------------+
| |
| Kernel Available |
| |
0xa7000000 +------------------+
| |
| PIL Region |
| |
0x8a800000 +------------------+
| |
| Firmware Related |
| |
0x80000000 +------------------+
Note that:
0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
it is available for kernel usage. This region is not suggested to be
used by kernel features like ramoops, suspend resume etc.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++++++++++++++++++++
1 file changed, 169 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi
diff --git a/arch/arm64/boot/dts/qcom/qcs8550.dtsi b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
new file mode 100644
index 000000000000..a3ebf3d4e16d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "sm8550.dtsi"
+
+/delete-node/ &reserved_memory;
+
+/ {
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+
+ /* These are 3 types of reserved memory regions here:
+ * 1. Firmware related regions which aren't shared with kernel.
+ * The device tree source in kernel doesn't need to have node to
+ * indicate the firmware related reserved information. OS bootloader
+ * conveys the information by update device tree in runtime.
+ * This will be described as: UEFI saves the physical address of
+ * the UEFI System Table to dts file's chosen node. Kernel read this
+ * table and add reserved memory regions to efi config table. Current
+ * reserved memory region may have reserved region which was not yet
+ * used, release note of the firmware have such kind of information.
+ * 2. Firmware related memory regions which are shared with Kernel.
+ * Each region has a specific node with specific label name for
+ * later phandle reference from other driver dt node.
+ * 3. PIL regions.
+ * PIL regions will be reserved and then assigned to subsystem
+ * firmware later.
+ * Here is a reserved memory map for this platform:
+ * 0x100000000 +------------------+
+ * | |
+ * | Firmware Related |
+ * | |
+ * 0xd4d00000 +------------------+
+ * | |
+ * | Kernel Available |
+ * | |
+ * 0xa7000000 +------------------+
+ * | |
+ * | PIL Region |
+ * | |
+ * 0x8a800000 +------------------+
+ * | |
+ * | Firmware Related |
+ * | |
+ * 0x80000000 +------------------+
+ * Note that:
+ * 0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
+ * it is available for kernel usage. This region is not suggested to
+ * be used by kernel features like ramoops, suspend resume etc.
+ */
+
+ /*
+ * Firmware related regions, bootlader will possible reserve parts of
+ * region from 0x80000000..0x8a800000.
+ */
+ aop_image_mem: aop-image-region@81c00000 {
+ reg = <0x0 0x81c00000 0x0 0x60000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ aop_config_mem: aop-config-region@81c80000 {
+ no-map;
+ reg = <0x0 0x81c80000 0x0 0x20000>;
+ };
+
+ smem_mem: smem-region@81d00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x81d00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ adsp_mhi_mem: adsp-mhi-region@81f00000 {
+ reg = <0x0 0x81f00000 0x0 0x20000>;
+ no-map;
+ };
+
+ /* PIL region */
+ mpss_mem: mpss-region@8a800000 {
+ reg = <0x0 0x8a800000 0x0 0x10800000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
+ reg = <0x0 0x9b000000 0x0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw-region@9b080000 {
+ reg = <0x0 0x9b080000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi-region@9b090000 {
+ reg = <0x0 0x9b090000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
+ reg = <0x0 0x9b09a000 0x0 0x2000>;
+ no-map;
+ };
+
+ spss_region_mem: spss-region@9b100000 {
+ reg = <0x0 0x9b100000 0x0 0x180000>;
+ no-map;
+ };
+
+ spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 {
+ reg = <0x0 0x9b280000 0x0 0x80000>;
+ no-map;
+ };
+
+ camera_mem: camera-region@9b300000 {
+ reg = <0x0 0x9b300000 0x0 0x800000>;
+ no-map;
+ };
+
+ video_mem: video-region@9bb00000 {
+ reg = <0x0 0x9bb00000 0x0 0x700000>;
+ no-map;
+ };
+
+ cvp_mem: cvp-region@9c200000 {
+ reg = <0x0 0x9c200000 0x0 0x700000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp-region@9c900000 {
+ reg = <0x0 0x9c900000 0x0 0x2000000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
+ reg = <0x0 0x9e900000 0x0 0x80000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
+ reg = <0x0 0x9e980000 0x0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi-region@9ea00000 {
+ reg = <0x0 0x9ea00000 0x0 0x4080000>;
+ no-map;
+ };
+
+ /*
+ * Firmware related regions, bootlader will possible reserve parts of
+ * region from 0xd8000000..0x100000000.
+ */
+ mpss_dsm_mem: mpss_dsm_region@d4d00000 {
+ reg = <0x0 0xd4d00000 0x0 0x3300000>;
+ no-map;
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [relevance 9%]
* [PATCH v8 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board
2024-05-13 9:07 6% [PATCH v8 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
@ 2024-05-13 9:07 16% ` Tengfei Fan
2024-05-13 9:07 9% ` [PATCH v8 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi Tengfei Fan
2024-05-13 9:07 5% ` [PATCH v8 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT Tengfei Fan
2 siblings, 0 replies; 200+ results
From: Tengfei Fan @ 2024-05-13 9:07 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzk+dt, conor+dt, dmitry.baryshkov
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan,
Krzysztof Kozlowski
Document QCS8550 SoC and the AIM300 AIoT board bindings.
QCS8550 is derived from SM8550. The difference between SM8550 and
QCS8550 is QCS8550 doesn't have modem RF system. QCS8550 is mainly used
in IoT scenarios.
AIM300 Series is a highly optimized family of modules designed to
support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC chip
etc.
AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index ae885414b181..a8cf7cd433c9 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -42,6 +42,7 @@ description: |
msm8996
msm8998
qcs404
+ qcs8550
qcm2290
qcm6490
qdu1000
@@ -1007,6 +1008,13 @@ properties:
- sony,pdx234
- const: qcom,sm8550
+ - items:
+ - enum:
+ - qcom,qcs8550-aim300-aiot
+ - const: qcom,qcs8550-aim300
+ - const: qcom,qcs8550
+ - const: qcom,sm8550
+
- items:
- enum:
- qcom,sm8650-mtp
--
2.25.1
^ permalink raw reply related [relevance 16%]
* [PATCH v8 0/4] arm64: qcom: add AIM300 AIoT board support
@ 2024-05-13 9:07 6% Tengfei Fan
2024-05-13 9:07 16% ` [PATCH v8 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board Tengfei Fan
` (2 more replies)
0 siblings, 3 replies; 200+ results
From: Tengfei Fan @ 2024-05-13 9:07 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzk+dt, conor+dt, dmitry.baryshkov
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan
Add AIM300 AIoT support along with usb, ufs, regulators, serial, PCIe,
and PMIC functions.
AIM300 Series is a highly optimized family of modules designed to
support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC
chip etc.
Here is a diagram of AIM300 AIoT Carrie Board and SoM
+--------------------------------------------------+
| AIM300 AIOT Carrier Board |
| |
| +-----------------+ |
|power----->| Fixed regulator |---------+ |
| +-----------------+ | |
| | |
| v VPH_PWR |
| +----------------------------------------------+ |
| | AIM300 SOM | | |
| | |VPH_PWR | |
| | v | |
| | +-------+ +--------+ +------+ | |
| | | UFS | | QCS8550| |PMIC | | |
| | +-------+ +--------+ +------+ | |
| | | |
| +----------------------------------------------+ |
| |
| +----+ +------+ |
| |USB | | UART | |
| +----+ +------+ |
+--------------------------------------------------+
The following functions have been verified:
- uart
- usb
- ufs
- PCIe
- PMIC
- display
- adsp
- cdsp
- tlmm
Documentation for qcs8550[1] and sm8550[2]
[1] https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
[2] https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/Snapdragon-8-Gen-2-Product-Brief.pdf
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
This patch series depends on patch series:
"[PATCH v5 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock"
https://lore.kernel.org/linux-arm-msm/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-0-10c650cfeade@linaro.org/
"[PATCH] arm64: dts: qcom: sm8550: Move some common usb node settings to SoC dtsi"
https://lore.kernel.org/linux-arm-msm/20240513084701.1658826-1-quic_tengfan@quicinc.com/
v7 -> v8:
- rebase patch series on top of:
https://lore.kernel.org/linux-arm-msm/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-0-10c650cfeade@linaro.org/
- add pinctrl configurations for pcie0 and pcie1 in AIM300 SOM dtsi
- move some common usb node settings to SoC dtsi
- verified with dtb check, and result is expected, because those
warnings are not introduced by current patch series.
arch/arm64/boot/dts/qcom/sm8550.dtsi:3037.27-3092.6: Warning
(avoid_unnecessary_addr_size): /soc@0/display-subsystem@ae00000/dsi@ae96000: unnecessary
#address-cells/#size-cells without "ranges" or child "reg" property
v6 -> v7:
- correct typos in the commit message
- move mdss_dsi0, mdss_dsi0_phy, pcie0_phy, pcie1_phy and usb_dp_qmpphy
vdda supply to qcs8550-aim300.dtsi
- move the perst and wake gpio settings of pcie0 and pcie1 to
qcs8550-aim300.dtsi
- move the clock frequency settings of pcie_1_phy_aux_clk, sleep_clk
and xo_board to qcs8550-aim300.dtsi
- verified with dtb check, and result is expected, because those
warnings are not introduced by current patch series.
arch/arm64/boot/dts/qcom/sm8550.dtsi:3037.27-3092.6: Warning
(avoid_unnecessary_addr_size): /soc@0/display-subsystem@ae00000/dsi@ae96000: unnecessary
#address-cells/#size-cells without "ranges" or child "reg" property
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
phy@1c0e000: clock-output-names: ['pcie1_pipe_clk'] is too short
from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: phy@1c0e000: #clock-cells:0:0: 1 was expected
from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
v5 -> v6:
- move qcs8550 board info bebind sm8550 boards info in qcom.yaml
v4 -> v5:
- "2023-2024" instead of "2023~2024" for License
- update patch commit message to previous comments and with an updated
board diagram
- use qcs8550.dtsi instead of qcm8550.dtsi
- remove the reserved memory regions which will be handled by
bootloader
- remove pm8550_flash, pm8550_pwm nodes, Type-C USB/DP function node,
remoteproc_mpss function node, audio sound DTS node, new patch will
be updated after respective team's end to end full verification
- address comments to vph_pwr, move vph_pwr node and related
references to qcs8550-aim300-aiot.dts
- use "regulator-vph-pwr" instead of "vph_pwr_regulator"
- add pcie0I AND pcie1 support together
- the following patches were applied, so remove these patches from new
patch series:
- https://lore.kernel.org/linux-arm-msm/20240119100621.11788-3-quic_tengfan@quicinc.com
- https://lore.kernel.org/linux-arm-msm/20240119100621.11788-4-quic_tengfan@quicinc.com
- verified with dtb check, and result is expected, because those
warnings are not introduced by current patch series.
DTC_CHK arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb
arch/arm64/boot/dts/qcom/sm8550.dtsi:3015.27-3070.6: Warning
(avoid_unnecessary_addr_size): /soc@0/display-subsystem@ae00000/dsi@ae96000: unnecessary
#address-cells/#size-cells without "ranges" or child "reg" property
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
opp-table: opp-75000000:opp-hz:0: [75000000, 0, 0, 75000000, 0, 0, 0, 0] is too long
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
opp-table: opp-150000000:opp-hz:0: [150000000, 0, 0, 150000000, 0, 0, 0, 0] is too long
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
opp-table: opp-300000000:opp-hz:0: [300000000, 0, 0, 300000000, 0, 0, 0, 0] is too long
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
opp-table: Unevaluated properties are not allowed ('opp-150000000', 'opp-300000000', 'opp-75000000' were unexpected)
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
v3 -> v4:
- use qcm8550.dtsi instead of qcs8550.dtsi, qcs8550 is a QCS version
of qcm8550, another board with qcm8550 will be added later
- add AIM300 AIoT board string in qcom.yaml file
- add sm8550 and qcm8550 fallback compatible
- add qcm8550 SoC id
- add reserved memory map codes in qcm8550.dtsi
- pm8010 and pmr73d are splited into carrier board DTS file. Because
the regulators which in pm8550, pm8550ve and pm8550vs are present
on the SoM. The regulators which in pm8010 and pmr73d are present
on the carrier board.
- stay VPH_PWR at qcs8550-aim300.dtsi file
VPH_PWR is obtained by vonverting 12v voltage into 3.7 voltage
with a 3.7v buck. VPH_PWR is power supply for regulators in AIM300
SOM. VPH_PWR regulator is defined in AIM300 SOM dtsi file.
v2 -> v3:
- introduce qcs8550.dtsi
- separate fix dtc W=1 warning patch to another patch series
v1 -> v2:
- merge the splited dts patches into one patch
- update dts file name from qcom8550-aim300.dts to qcs8550-aim300 dts
- drop PCIe1 dts node due to it is not enabled
- update display node name for drop sde characters
previous discussion here:
[1] v7: https://lore.kernel.org/linux-arm-msm/20240424024508.3857602-1-quic_tengfan@quicinc.com
[2] v6 RESEND: https://lore.kernel.org/linux-arm-msm/20240401093843.2591147-1-quic_tengfan@quicinc.com
[3] v6: https://lore.kernel.org/linux-arm-msm/20240308070432.28195-1-quic_tengfan@quicinc.com
[4] v5: https://lore.kernel.org/linux-arm-msm/20240301134113.14423-1-quic_tengfan@quicinc.com
[5] v4: https://lore.kernel.org/linux-arm-msm/20240119100621.11788-1-quic_tengfan@quicinc.com
[6] v3: https://lore.kernel.org/linux-arm-msm/20231219005007.11644-1-quic_tengfan@quicinc.com
[7] v2: https://lore.kernel.org/linux-arm-msm/20231207092801.7506-1-quic_tengfan@quicinc.com
[8] v1: https://lore.kernel.org/linux-arm-msm/20231117101817.4401-1-quic_tengfan@quicinc.com
Tengfei Fan (4):
dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board
arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi
arm64: dts: qcom: add base AIM300 dtsi
arm64: dts: qcom: aim300: add AIM300 AIoT
.../devicetree/bindings/arm/qcom.yaml | 8 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/qcs8550-aim300-aiot.dts | 322 ++++++++++++++
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 405 ++++++++++++++++++
arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++
5 files changed, 905 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi
base-commit: 6ba6c795dc73c22ce2c86006f17c4aa802db2a60
--
2.25.1
^ permalink raw reply [relevance 6%]
* Re: [PATCH] arm64: dts: qcom: sm8550: Move some common usb node settings to SoC dtsi
2024-05-13 8:47 19% [PATCH] arm64: dts: qcom: sm8550: Move some common usb node settings to SoC dtsi Tengfei Fan
@ 2024-05-13 8:56 4% ` Krzysztof Kozlowski
2024-05-14 0:52 4% ` Tengfei Fan
0 siblings, 1 reply; 200+ results
From: Krzysztof Kozlowski @ 2024-05-13 8:56 UTC (permalink / raw)
To: Tengfei Fan, andersson, konrad.dybcio, robh, krzk+dt, conor+dt
Cc: linux-arm-msm, devicetree, linux-kernel, kernel
On 13/05/2024 10:47, Tengfei Fan wrote:
> All the board dts which base on SM8550 SoC dtsi refer to usb_1_dwc3_ss,
> usb_dp_qmpphy_usb_ss_in, orientation-switch and usb-role-switch, so move
> them to SoC dtsi from board dts.
That's not really a good argument. Argument is that it is a SoC property
(vs being a property of a board). Provide rationale for that. You are
moving things just because they look common, so to me it looks really
unjustified.
> OTG is default for dr_mode, so it can be dropped from board dts.
Separate patch, see submitting patches.
Best regards,
Krzysztof
^ permalink raw reply [relevance 4%]
* [PATCH] arm64: dts: qcom: sm8550: Move some common usb node settings to SoC dtsi
@ 2024-05-13 8:47 19% Tengfei Fan
2024-05-13 8:56 4% ` Krzysztof Kozlowski
0 siblings, 1 reply; 200+ results
From: Tengfei Fan @ 2024-05-13 8:47 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzk+dt, conor+dt
Cc: linux-arm-msm, devicetree, linux-kernel, kernel, Tengfei Fan
All the board dts which base on SM8550 SoC dtsi refer to usb_1_dwc3_ss,
usb_dp_qmpphy_usb_ss_in, orientation-switch and usb-role-switch, so move
them to SoC dtsi from board dts.
OTG is default for dr_mode, so it can be dropped from board dts.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 15 ---------------
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 15 ---------------
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 15 ---------------
.../dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 14 --------------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++
5 files changed, 4 insertions(+), 59 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 12d60a0ee095..e6bfd3ce2bed 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -1258,19 +1258,10 @@ &usb_1 {
status = "okay";
};
-&usb_1_dwc3 {
- dr_mode = "otg";
- usb-role-switch;
-};
-
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&vreg_l1e_0p88>;
vdda12-supply = <&vreg_l3e_1p2>;
@@ -1284,8 +1275,6 @@ &usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3f_0p88>;
- orientation-switch;
-
status = "okay";
};
@@ -1297,10 +1286,6 @@ &usb_dp_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 3d4ad5aac70f..fbcdf66f16d6 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -951,19 +951,10 @@ &usb_1 {
status = "okay";
};
-&usb_1_dwc3 {
- dr_mode = "otg";
- usb-role-switch;
-};
-
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&vreg_l1e_0p88>;
vdda12-supply = <&vreg_l3e_1p2>;
@@ -977,8 +968,6 @@ &usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3f_0p91>;
- orientation-switch;
-
status = "okay";
};
@@ -990,10 +979,6 @@ &usb_dp_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 92f015017418..3ad616e46cb3 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -1135,19 +1135,10 @@ &usb_1 {
status = "okay";
};
-&usb_1_dwc3 {
- dr_mode = "otg";
- usb-role-switch;
-};
-
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&vreg_l1e_0p88>;
vdda12-supply = <&vreg_l3e_1p2>;
@@ -1161,8 +1152,6 @@ &usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3f_0p88>;
- orientation-switch;
-
status = "okay";
};
@@ -1174,10 +1163,6 @@ &usb_dp_qmpphy_out {
remote-endpoint = <&redriver_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
index 85e0d3d66e16..85d487ef80a0 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
@@ -737,19 +737,10 @@ &usb_1 {
status = "okay";
};
-&usb_1_dwc3 {
- dr_mode = "otg";
- usb-role-switch;
-};
-
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&pm8550vs_2_l1>;
vdda12-supply = <&pm8550vs_2_l3>;
@@ -761,7 +752,6 @@ &usb_1_hsphy {
&usb_dp_qmpphy {
vdda-phy-supply = <&pm8550vs_2_l3>;
vdda-pll-supply = <&pm8550ve_l3>;
- orientation-switch;
status = "okay";
};
@@ -770,10 +760,6 @@ &usb_dp_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index bc5aeb05ffc3..05f7d7341f72 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3168,6 +3168,7 @@ usb_dp_qmpphy: phy@88e8000 {
#clock-cells = <1>;
#phy-cells = <1>;
+ orientation-switch;
status = "disabled";
@@ -3186,6 +3187,7 @@ port@1 {
reg = <1>;
usb_dp_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
};
};
@@ -3264,6 +3266,7 @@ usb_1_dwc3: usb@a600000 {
snps,has-lpm-erratum;
tx-fifo-resize;
dma-coherent;
+ usb-role-switch;
ports {
#address-cells = <1>;
@@ -3280,6 +3283,7 @@ port@1 {
reg = <1>;
usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
};
};
base-commit: 6ba6c795dc73c22ce2c86006f17c4aa802db2a60
--
2.25.1
^ permalink raw reply related [relevance 19%]
* [PATCH v8 4/5] soc: qcom: add pd-mapper implementation
2024-05-11 21:56 4% ` [PATCH v8 1/5] soc: qcom: pdr: protect locator_addr with the main mutex Dmitry Baryshkov
@ 2024-05-11 21:56 2% ` Dmitry Baryshkov
1 sibling, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-05-11 21:56 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Sibi Sankar, Mathieu Poirier
Cc: linux-arm-msm, linux-kernel, linux-remoteproc, Johan Hovold,
Xilin Wu, Bryan O'Donoghue, Steev Klimaszewski,
Alexey Minnekhanov
Existing userspace protection domain mapper implementation has several
issue. It doesn't play well with CONFIG_EXTRA_FIRMWARE, it doesn't
reread JSON files if firmware location is changed (or if firmware was
not available at the time pd-mapper was started but the corresponding
directory is mounted later), etc.
Provide in-kernel service implementing protection domain mapping
required to work with several services, which are provided by the DSP
firmware.
This module is loaded automatically by the remoteproc drivers when
necessary via the symbol dependency. It uses a root node to match a
protection domains map for a particular board. It is not possible to
implement it as a 'driver' as there is no corresponding device.
Tested-by: Steev Klimaszewski <steev@kali.org>
Tested-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/soc/qcom/Kconfig | 11 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/pdr_internal.h | 14 +
drivers/soc/qcom/qcom_pd_mapper.c | 676 ++++++++++++++++++++++++++++++++++++++
drivers/soc/qcom/qcom_pdr_msg.c | 34 ++
5 files changed, 736 insertions(+)
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 95973c6b828f..0a2f2bfd7863 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -72,6 +72,17 @@ config QCOM_OCMEM
requirements. This is typically used by the GPU, camera/video, and
audio components on some Snapdragon SoCs.
+config QCOM_PD_MAPPER
+ tristate "Qualcomm Protection Domain Mapper"
+ select QCOM_QMI_HELPERS
+ depends on NET && QRTR
+ default QCOM_RPROC_COMMON
+ help
+ The Protection Domain Mapper maps registered services to the domains
+ and instances handled by the remote DSPs. This is a kernel-space
+ implementation of the service. It is a simpler alternative to the
+ userspace daemon.
+
config QCOM_PDR_HELPERS
tristate
select QCOM_QMI_HELPERS
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 3110ac3288bc..d3560f861085 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
obj-$(CONFIG_QCOM_OCMEM) += ocmem.o
+obj-$(CONFIG_QCOM_PD_MAPPER) += qcom_pd_mapper.o
obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o
obj-$(CONFIG_QCOM_PDR_MSG) += qcom_pdr_msg.o
obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink.o
diff --git a/drivers/soc/qcom/pdr_internal.h b/drivers/soc/qcom/pdr_internal.h
index 7e5bb5a95275..8d17f7fb79e7 100644
--- a/drivers/soc/qcom/pdr_internal.h
+++ b/drivers/soc/qcom/pdr_internal.h
@@ -13,6 +13,8 @@
#define SERVREG_SET_ACK_REQ 0x23
#define SERVREG_RESTART_PD_REQ 0x24
+#define SERVREG_LOC_PFR_REQ 0x24
+
#define SERVREG_DOMAIN_LIST_LENGTH 32
#define SERVREG_RESTART_PD_REQ_MAX_LEN 67
#define SERVREG_REGISTER_LISTENER_REQ_LEN 71
@@ -20,6 +22,7 @@
#define SERVREG_GET_DOMAIN_LIST_REQ_MAX_LEN 74
#define SERVREG_STATE_UPDATED_IND_MAX_LEN 79
#define SERVREG_GET_DOMAIN_LIST_RESP_MAX_LEN 2389
+#define SERVREG_LOC_PFR_RESP_MAX_LEN 10
struct servreg_location_entry {
char name[SERVREG_NAME_LENGTH + 1];
@@ -79,6 +82,15 @@ struct servreg_set_ack_resp {
struct qmi_response_type_v01 resp;
};
+struct servreg_loc_pfr_req {
+ char service[SERVREG_NAME_LENGTH + 1];
+ char reason[257];
+};
+
+struct servreg_loc_pfr_resp {
+ struct qmi_response_type_v01 rsp;
+};
+
extern const struct qmi_elem_info servreg_location_entry_ei[];
extern const struct qmi_elem_info servreg_get_domain_list_req_ei[];
extern const struct qmi_elem_info servreg_get_domain_list_resp_ei[];
@@ -89,5 +101,7 @@ extern const struct qmi_elem_info servreg_restart_pd_resp_ei[];
extern const struct qmi_elem_info servreg_state_updated_ind_ei[];
extern const struct qmi_elem_info servreg_set_ack_req_ei[];
extern const struct qmi_elem_info servreg_set_ack_resp_ei[];
+extern const struct qmi_elem_info servreg_loc_pfr_req_ei[];
+extern const struct qmi_elem_info servreg_loc_pfr_resp_ei[];
#endif
diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c
new file mode 100644
index 000000000000..ecb64f06527f
--- /dev/null
+++ b/drivers/soc/qcom/qcom_pd_mapper.c
@@ -0,0 +1,676 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Qualcomm Protection Domain mapper
+ *
+ * Copyright (c) 2023 Linaro Ltd.
+ */
+
+#include <linux/auxiliary_bus.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/refcount.h>
+#include <linux/soc/qcom/qmi.h>
+
+#include "pdr_internal.h"
+
+#define SERVREG_QMI_VERSION 0x101
+#define SERVREG_QMI_INSTANCE 0
+
+#define TMS_SERVREG_SERVICE "tms/servreg"
+
+struct qcom_pdm_domain_data {
+ const char *domain;
+ u32 instance_id;
+ /* NULL-terminated array */
+ const char * services[];
+};
+
+struct qcom_pdm_domain {
+ struct list_head list;
+ const char *name;
+ u32 instance_id;
+};
+
+struct qcom_pdm_service {
+ struct list_head list;
+ struct list_head domains;
+ const char *name;
+};
+
+struct qcom_pdm_data {
+ refcount_t refcnt;
+ struct qmi_handle handle;
+ struct list_head services;
+};
+
+static DEFINE_MUTEX(qcom_pdm_mutex); /* protects __qcom_pdm_data */
+static struct qcom_pdm_data *__qcom_pdm_data;
+
+static struct qcom_pdm_service *qcom_pdm_find(struct qcom_pdm_data *data,
+ const char *name)
+{
+ struct qcom_pdm_service *service;
+
+ list_for_each_entry(service, &data->services, list) {
+ if (!strcmp(service->name, name))
+ return service;
+ }
+
+ return NULL;
+}
+
+static int qcom_pdm_add_service_domain(struct qcom_pdm_data *data,
+ const char *service_name,
+ const char *domain_name,
+ u32 instance_id)
+{
+ struct qcom_pdm_service *service;
+ struct qcom_pdm_domain *domain;
+
+ service = qcom_pdm_find(data, service_name);
+ if (service) {
+ list_for_each_entry(domain, &service->domains, list) {
+ if (!strcmp(domain->name, domain_name))
+ return -EBUSY;
+ }
+ } else {
+ service = kzalloc(sizeof(*service), GFP_KERNEL);
+ if (!service)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&service->domains);
+ service->name = service_name;
+
+ list_add_tail(&service->list, &data->services);
+ }
+
+ domain = kzalloc(sizeof(*domain), GFP_KERNEL);
+ if (!domain) {
+ if (list_empty(&service->domains)) {
+ list_del(&service->list);
+ kfree(service);
+ }
+
+ return -ENOMEM;
+ }
+
+ domain->name = domain_name;
+ domain->instance_id = instance_id;
+ list_add_tail(&domain->list, &service->domains);
+
+ return 0;
+}
+
+static int qcom_pdm_add_domain(struct qcom_pdm_data *data,
+ const struct qcom_pdm_domain_data *domain)
+{
+ int ret;
+ int i;
+
+ ret = qcom_pdm_add_service_domain(data,
+ TMS_SERVREG_SERVICE,
+ domain->domain,
+ domain->instance_id);
+ if (ret)
+ return ret;
+
+ for (i = 0; domain->services[i]; i++) {
+ ret = qcom_pdm_add_service_domain(data,
+ domain->services[i],
+ domain->domain,
+ domain->instance_id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+
+}
+
+static void qcom_pdm_free_domains(struct qcom_pdm_data *data)
+{
+ struct qcom_pdm_service *service, *tservice;
+ struct qcom_pdm_domain *domain, *tdomain;
+
+ list_for_each_entry_safe(service, tservice, &data->services, list) {
+ list_for_each_entry_safe(domain, tdomain, &service->domains, list) {
+ list_del(&domain->list);
+ kfree(domain);
+ }
+
+ list_del(&service->list);
+ kfree(service);
+ }
+}
+
+static void qcom_pdm_get_domain_list(struct qmi_handle *qmi,
+ struct sockaddr_qrtr *sq,
+ struct qmi_txn *txn,
+ const void *decoded)
+{
+ struct qcom_pdm_data *data = container_of(qmi, struct qcom_pdm_data, handle);
+ const struct servreg_get_domain_list_req *req = decoded;
+ struct servreg_get_domain_list_resp *rsp;
+ struct qcom_pdm_service *service;
+ u32 offset;
+ int ret;
+
+ rsp = kzalloc(sizeof(*rsp), GFP_KERNEL);
+ if (!rsp)
+ return;
+
+ offset = req->domain_offset_valid ? req->domain_offset : 0;
+
+ rsp->resp.result = QMI_RESULT_SUCCESS_V01;
+ rsp->resp.error = QMI_ERR_NONE_V01;
+
+ rsp->db_rev_count_valid = true;
+ rsp->db_rev_count = 1;
+
+ rsp->total_domains_valid = true;
+ rsp->total_domains = 0;
+
+ mutex_lock(&qcom_pdm_mutex);
+
+ service = qcom_pdm_find(data, req->service_name);
+ if (service) {
+ struct qcom_pdm_domain *domain;
+
+ rsp->domain_list_valid = true;
+ rsp->domain_list_len = 0;
+
+ list_for_each_entry(domain, &service->domains, list) {
+ u32 i = rsp->total_domains++;
+
+ if (i >= offset && i < SERVREG_DOMAIN_LIST_LENGTH) {
+ u32 j = rsp->domain_list_len++;
+
+ strscpy(rsp->domain_list[j].name, domain->name,
+ sizeof(rsp->domain_list[i].name));
+ rsp->domain_list[j].instance = domain->instance_id;
+
+ pr_debug("PDM: found %s / %d\n", domain->name,
+ domain->instance_id);
+ }
+ }
+ }
+
+ pr_debug("PDM: service '%s' offset %d returning %d domains (of %d)\n", req->service_name,
+ req->domain_offset_valid ? req->domain_offset : -1, rsp->domain_list_len, rsp->total_domains);
+
+ ret = qmi_send_response(qmi, sq, txn, SERVREG_GET_DOMAIN_LIST_REQ,
+ SERVREG_GET_DOMAIN_LIST_RESP_MAX_LEN,
+ servreg_get_domain_list_resp_ei, rsp);
+ if (ret)
+ pr_err("Error sending servreg response: %d\n", ret);
+
+ mutex_unlock(&qcom_pdm_mutex);
+
+ kfree(rsp);
+}
+
+static void qcom_pdm_pfr(struct qmi_handle *qmi,
+ struct sockaddr_qrtr *sq,
+ struct qmi_txn *txn,
+ const void *decoded)
+{
+ const struct servreg_loc_pfr_req *req = decoded;
+ struct servreg_loc_pfr_resp rsp = {};
+ int ret;
+
+ pr_warn_ratelimited("PDM: service '%s' crash: '%s'\n", req->service, req->reason);
+
+ rsp.rsp.result = QMI_RESULT_SUCCESS_V01;
+ rsp.rsp.error = QMI_ERR_NONE_V01;
+
+ ret = qmi_send_response(qmi, sq, txn, SERVREG_LOC_PFR_REQ,
+ SERVREG_LOC_PFR_RESP_MAX_LEN,
+ servreg_loc_pfr_resp_ei, &rsp);
+ if (ret)
+ pr_err("Error sending servreg response: %d\n", ret);
+}
+
+static const struct qmi_msg_handler qcom_pdm_msg_handlers[] = {
+ {
+ .type = QMI_REQUEST,
+ .msg_id = SERVREG_GET_DOMAIN_LIST_REQ,
+ .ei = servreg_get_domain_list_req_ei,
+ .decoded_size = sizeof(struct servreg_get_domain_list_req),
+ .fn = qcom_pdm_get_domain_list,
+ },
+ {
+ .type = QMI_REQUEST,
+ .msg_id = SERVREG_LOC_PFR_REQ,
+ .ei = servreg_loc_pfr_req_ei,
+ .decoded_size = sizeof(struct servreg_loc_pfr_req),
+ .fn = qcom_pdm_pfr,
+ },
+ { },
+};
+
+static const struct qcom_pdm_domain_data adsp_audio_pd = {
+ .domain = "msm/adsp/audio_pd",
+ .instance_id = 74,
+ .services = {
+ "avs/audio",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data adsp_charger_pd = {
+ .domain = "msm/adsp/charger_pd",
+ .instance_id = 74,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data adsp_root_pd = {
+ .domain = "msm/adsp/root_pd",
+ .instance_id = 74,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data adsp_root_pd_pdr = {
+ .domain = "msm/adsp/root_pd",
+ .instance_id = 74,
+ .services = {
+ "tms/pdr_enabled",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data adsp_sensor_pd = {
+ .domain = "msm/adsp/sensor_pd",
+ .instance_id = 74,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data msm8996_adsp_audio_pd = {
+ .domain = "msm/adsp/audio_pd",
+ .instance_id = 4,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data msm8996_adsp_root_pd = {
+ .domain = "msm/adsp/root_pd",
+ .instance_id = 4,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data cdsp_root_pd = {
+ .domain = "msm/cdsp/root_pd",
+ .instance_id = 76,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data slpi_root_pd = {
+ .domain = "msm/slpi/root_pd",
+ .instance_id = 90,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data slpi_sensor_pd = {
+ .domain = "msm/slpi/sensor_pd",
+ .instance_id = 90,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data mpss_root_pd = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 180,
+ .services = {
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data mpss_root_pd_gps = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 180,
+ .services = {
+ "gps/gps_service",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data mpss_root_pd_gps_pdr = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 180,
+ .services = {
+ "gps/gps_service",
+ "tms/pdr_enabled",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data msm8996_mpss_root_pd = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 100,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data mpss_wlan_pd = {
+ .domain = "msm/modem/wlan_pd",
+ .instance_id = 180,
+ .services = {
+ "kernel/elf_loader",
+ "wlan/fw",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data *msm8996_domains[] = {
+ &msm8996_adsp_audio_pd,
+ &msm8996_adsp_root_pd,
+ &msm8996_mpss_root_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *msm8998_domains[] = {
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *qcm2290_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *qcs404_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc7180_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_sensor_pd,
+ &mpss_root_pd_gps_pdr,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc7280_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_charger_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps_pdr,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc8180x_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_charger_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc8280xp_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_charger_pd,
+ &cdsp_root_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sdm660_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sdm670_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sdm845_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ &slpi_root_pd,
+ &slpi_sensor_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm6115_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm6350_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8150_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8250_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &slpi_root_pd,
+ &slpi_sensor_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8350_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_charger_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &slpi_root_pd,
+ &slpi_sensor_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8550_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_charger_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ NULL,
+};
+
+static const struct of_device_id qcom_pdm_domains[] = {
+ { .compatible = "qcom,apq8064", .data = NULL, },
+ { .compatible = "qcom,apq8074", .data = NULL, },
+ { .compatible = "qcom,apq8084", .data = NULL, },
+ { .compatible = "qcom,apq8096", .data = msm8996_domains, },
+ { .compatible = "qcom,msm8226", .data = NULL, },
+ { .compatible = "qcom,msm8974", .data = NULL, },
+ { .compatible = "qcom,msm8996", .data = msm8996_domains, },
+ { .compatible = "qcom,msm8998", .data = msm8998_domains, },
+ { .compatible = "qcom,qcm2290", .data = qcm2290_domains, },
+ { .compatible = "qcom,qcs404", .data = qcs404_domains, },
+ { .compatible = "qcom,sc7180", .data = sc7180_domains, },
+ { .compatible = "qcom,sc7280", .data = sc7280_domains, },
+ { .compatible = "qcom,sc8180x", .data = sc8180x_domains, },
+ { .compatible = "qcom,sc8280xp", .data = sc8280xp_domains, },
+ { .compatible = "qcom,sda660", .data = sdm660_domains, },
+ { .compatible = "qcom,sdm660", .data = sdm660_domains, },
+ { .compatible = "qcom,sdm670", .data = sdm670_domains, },
+ { .compatible = "qcom,sdm845", .data = sdm845_domains, },
+ { .compatible = "qcom,sm4250", .data = sm6115_domains, },
+ { .compatible = "qcom,sm6115", .data = sm6115_domains, },
+ { .compatible = "qcom,sm6350", .data = sm6350_domains, },
+ { .compatible = "qcom,sm8150", .data = sm8150_domains, },
+ { .compatible = "qcom,sm8250", .data = sm8250_domains, },
+ { .compatible = "qcom,sm8350", .data = sm8350_domains, },
+ { .compatible = "qcom,sm8450", .data = sm8350_domains, },
+ { .compatible = "qcom,sm8550", .data = sm8550_domains, },
+ { .compatible = "qcom,sm8650", .data = sm8550_domains, },
+ {},
+};
+
+static void qcom_pdm_stop(struct qcom_pdm_data *data)
+{
+ qcom_pdm_free_domains(data);
+
+ /* The server is removed automatically */
+ qmi_handle_release(&data->handle);
+
+ kfree(data);
+}
+
+static struct qcom_pdm_data *qcom_pdm_start(void)
+{
+ const struct qcom_pdm_domain_data * const *domains;
+ const struct of_device_id *match;
+ struct qcom_pdm_data *data;
+ struct device_node *root;
+ int ret, i;
+
+ root = of_find_node_by_path("/");
+ if (!root)
+ return ERR_PTR(-ENODEV);
+
+ match = of_match_node(qcom_pdm_domains, root);
+ of_node_put(root);
+ if (!match) {
+ pr_notice("PDM: no support for the platform, userspace daemon might be required.\n");
+ return ERR_PTR(-ENODEV);
+ }
+
+ domains = match->data;
+ if (!domains) {
+ pr_debug("PDM: no domains\n");
+ return ERR_PTR(-ENODEV);
+ }
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return ERR_PTR(-ENOMEM);
+
+ INIT_LIST_HEAD(&data->services);
+
+ ret = qmi_handle_init(&data->handle, SERVREG_GET_DOMAIN_LIST_REQ_MAX_LEN,
+ NULL, qcom_pdm_msg_handlers);
+ if (ret) {
+ kfree(data);
+ return ERR_PTR(ret);
+ }
+
+ refcount_set(&data->refcnt, 1);
+
+ for (i = 0; domains[i]; i++) {
+ ret = qcom_pdm_add_domain(data, domains[i]);
+ if (ret)
+ goto err_stop;
+ }
+
+ ret = qmi_add_server(&data->handle, SERVREG_LOCATOR_SERVICE,
+ SERVREG_QMI_VERSION, SERVREG_QMI_INSTANCE);
+ if (ret) {
+ pr_err("PDM: error adding server %d\n", ret);
+ goto err_stop;
+ }
+
+ return data;
+
+err_stop:
+ qcom_pdm_stop(data);
+
+ return ERR_PTR(ret);
+}
+
+static int qcom_pdm_probe(struct auxiliary_device *auxdev,
+ const struct auxiliary_device_id *id)
+
+{
+ struct qcom_pdm_data *data;
+ int ret = 0;
+
+ mutex_lock(&qcom_pdm_mutex);
+
+ if (!__qcom_pdm_data) {
+ data = qcom_pdm_start();
+
+ if (IS_ERR(data))
+ ret = PTR_ERR(data);
+ else
+ __qcom_pdm_data = data;
+ }
+
+ auxiliary_set_drvdata(auxdev, __qcom_pdm_data);
+
+ mutex_unlock(&qcom_pdm_mutex);
+
+ return ret;
+}
+
+static void qcom_pdm_remove(struct auxiliary_device *auxdev)
+{
+ struct qcom_pdm_data *data;
+
+ data = auxiliary_get_drvdata(auxdev);
+ if (!data)
+ return;
+
+ if (refcount_dec_and_mutex_lock(&data->refcnt, &qcom_pdm_mutex)) {
+ __qcom_pdm_data = NULL;
+ qcom_pdm_stop(data);
+ mutex_unlock(&qcom_pdm_mutex);
+ }
+}
+
+static const struct auxiliary_device_id qcom_pdm_table[] = {
+ { .name = "qcom_common.pd-mapper" },
+ {},
+};
+MODULE_DEVICE_TABLE(auxiliary, qcom_pdm_table);
+
+static struct auxiliary_driver qcom_pdm_drv = {
+ .name = "qcom-pdm-mapper",
+ .id_table = qcom_pdm_table,
+ .probe = qcom_pdm_probe,
+ .remove = qcom_pdm_remove,
+};
+module_auxiliary_driver(qcom_pdm_drv);
+
+MODULE_DESCRIPTION("Qualcomm Protection Domain Mapper");
+MODULE_LICENSE("GPL");
diff --git a/drivers/soc/qcom/qcom_pdr_msg.c b/drivers/soc/qcom/qcom_pdr_msg.c
index 9b46f42aa146..bf3e4a47165e 100644
--- a/drivers/soc/qcom/qcom_pdr_msg.c
+++ b/drivers/soc/qcom/qcom_pdr_msg.c
@@ -315,5 +315,39 @@ const struct qmi_elem_info servreg_set_ack_resp_ei[] = {
};
EXPORT_SYMBOL_GPL(servreg_set_ack_resp_ei);
+const struct qmi_elem_info servreg_loc_pfr_req_ei[] = {
+ {
+ .data_type = QMI_STRING,
+ .elem_len = SERVREG_NAME_LENGTH + 1,
+ .elem_size = sizeof(char),
+ .array_type = VAR_LEN_ARRAY,
+ .tlv_type = 0x01,
+ .offset = offsetof(struct servreg_loc_pfr_req, service)
+ },
+ {
+ .data_type = QMI_STRING,
+ .elem_len = SERVREG_NAME_LENGTH + 1,
+ .elem_size = sizeof(char),
+ .array_type = VAR_LEN_ARRAY,
+ .tlv_type = 0x02,
+ .offset = offsetof(struct servreg_loc_pfr_req, reason)
+ },
+ {}
+};
+EXPORT_SYMBOL_GPL(servreg_loc_pfr_req_ei);
+
+const struct qmi_elem_info servreg_loc_pfr_resp_ei[] = {
+ {
+ .data_type = QMI_STRUCT,
+ .elem_len = 1,
+ .elem_size = sizeof_field(struct servreg_loc_pfr_resp, rsp),
+ .tlv_type = 0x02,
+ .offset = offsetof(struct servreg_loc_pfr_resp, rsp),
+ .ei_array = qmi_response_type_v01_ei,
+ },
+ {}
+};
+EXPORT_SYMBOL_GPL(servreg_loc_pfr_resp_ei);
+
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Qualcomm Protection Domain messages data");
--
2.39.2
^ permalink raw reply related [relevance 2%]
* [PATCH v8 1/5] soc: qcom: pdr: protect locator_addr with the main mutex
@ 2024-05-11 21:56 4% ` Dmitry Baryshkov
2024-05-11 21:56 2% ` [PATCH v8 4/5] soc: qcom: add pd-mapper implementation Dmitry Baryshkov
1 sibling, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-05-11 21:56 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Sibi Sankar, Mathieu Poirier
Cc: linux-arm-msm, linux-kernel, linux-remoteproc, Johan Hovold,
Xilin Wu, Bryan O'Donoghue, Steev Klimaszewski,
Alexey Minnekhanov, Neil Armstrong
If the service locator server is restarted fast enough, the PDR can
rewrite locator_addr fields concurrently. Protect them by placing
modification of those fields under the main pdr->lock.
Fixes: fbe639b44a82 ("soc: qcom: Introduce Protection Domain Restart helpers")
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Steev Klimaszewski <steev@kali.org>
Tested-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/soc/qcom/pdr_interface.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/qcom/pdr_interface.c b/drivers/soc/qcom/pdr_interface.c
index a1b6a4081dea..e014dd2d8ab3 100644
--- a/drivers/soc/qcom/pdr_interface.c
+++ b/drivers/soc/qcom/pdr_interface.c
@@ -76,12 +76,12 @@ static int pdr_locator_new_server(struct qmi_handle *qmi,
locator_hdl);
struct pdr_service *pds;
+ mutex_lock(&pdr->lock);
/* Create a local client port for QMI communication */
pdr->locator_addr.sq_family = AF_QIPCRTR;
pdr->locator_addr.sq_node = svc->node;
pdr->locator_addr.sq_port = svc->port;
- mutex_lock(&pdr->lock);
pdr->locator_init_complete = true;
mutex_unlock(&pdr->lock);
@@ -104,10 +104,10 @@ static void pdr_locator_del_server(struct qmi_handle *qmi,
mutex_lock(&pdr->lock);
pdr->locator_init_complete = false;
- mutex_unlock(&pdr->lock);
pdr->locator_addr.sq_node = 0;
pdr->locator_addr.sq_port = 0;
+ mutex_unlock(&pdr->lock);
}
static const struct qmi_ops pdr_locator_ops = {
@@ -365,6 +365,7 @@ static int pdr_get_domain_list(struct servreg_get_domain_list_req *req,
if (ret < 0)
return ret;
+ mutex_lock(&pdr->lock);
ret = qmi_send_request(&pdr->locator_hdl,
&pdr->locator_addr,
&txn, SERVREG_GET_DOMAIN_LIST_REQ,
@@ -373,15 +374,16 @@ static int pdr_get_domain_list(struct servreg_get_domain_list_req *req,
req);
if (ret < 0) {
qmi_txn_cancel(&txn);
- return ret;
+ goto err_unlock;
}
ret = qmi_txn_wait(&txn, 5 * HZ);
if (ret < 0) {
pr_err("PDR: %s get domain list txn wait failed: %d\n",
req->service_name, ret);
- return ret;
+ goto err_unlock;
}
+ mutex_unlock(&pdr->lock);
if (resp->resp.result != QMI_RESULT_SUCCESS_V01) {
pr_err("PDR: %s get domain list failed: 0x%x\n",
@@ -390,6 +392,11 @@ static int pdr_get_domain_list(struct servreg_get_domain_list_req *req,
}
return 0;
+
+err_unlock:
+ mutex_unlock(&pdr->lock);
+
+ return ret;
}
static int pdr_locate_service(struct pdr_handle *pdr, struct pdr_service *pds)
--
2.39.2
^ permalink raw reply related [relevance 4%]
* Re: [PATCH v7 1/6] soc: qcom: pdr: protect locator_addr with the main mutex
2024-04-25 19:30 0% ` Chris Lew
@ 2024-05-11 21:52 0% ` Dmitry Baryshkov
0 siblings, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-05-11 21:52 UTC (permalink / raw)
To: Chris Lew
Cc: Bjorn Andersson, Konrad Dybcio, Sibi Sankar, Mathieu Poirier,
linux-arm-msm, linux-kernel, linux-remoteproc, Johan Hovold,
Xilin Wu, Bryan O'Donoghue, Neil Armstrong
On Thu, 25 Apr 2024 at 22:30, Chris Lew <quic_clew@quicinc.com> wrote:
>
>
> On 4/24/2024 2:27 AM, Dmitry Baryshkov wrote:
> > If the service locator server is restarted fast enough, the PDR can
> > rewrite locator_addr fields concurrently. Protect them by placing
> > modification of those fields under the main pdr->lock.
> >
> > Fixes: fbe639b44a82 ("soc: qcom: Introduce Protection Domain Restart helpers")
> > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/soc/qcom/pdr_interface.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/soc/qcom/pdr_interface.c b/drivers/soc/qcom/pdr_interface.c
> > index a1b6a4081dea..19cfe4b41235 100644
> > --- a/drivers/soc/qcom/pdr_interface.c
> > +++ b/drivers/soc/qcom/pdr_interface.c
> > @@ -76,12 +76,12 @@ static int pdr_locator_new_server(struct qmi_handle *qmi,
> > locator_hdl);
> > struct pdr_service *pds;
> >
> > + mutex_lock(&pdr->lock);
> > /* Create a local client port for QMI communication */
> > pdr->locator_addr.sq_family = AF_QIPCRTR;
> > pdr->locator_addr.sq_node = svc->node;
> > pdr->locator_addr.sq_port = svc->port;
> >
> > - mutex_lock(&pdr->lock);
> > pdr->locator_init_complete = true;
> > mutex_unlock(&pdr->lock);
> >
> > @@ -104,10 +104,10 @@ static void pdr_locator_del_server(struct qmi_handle *qmi,
> >
> > mutex_lock(&pdr->lock);
> > pdr->locator_init_complete = false;
> > - mutex_unlock(&pdr->lock);
> >
> > pdr->locator_addr.sq_node = 0;
> > pdr->locator_addr.sq_port = 0;
> > + mutex_unlock(&pdr->lock);
> > }
> >
> > static const struct qmi_ops pdr_locator_ops = {
> >
>
> These two functions are provided as qmi_ops handlers in pdr_locator_ops.
> Aren't they serialized in the qmi handle's workqueue since it as an
> ordered_workqueue? Even in a fast pdr scenario I don't think we would
> see a race condition between these two functions.
>
> The other access these two functions do race against is in the
> pdr_notifier_work. I think you would need to protect locator_addr in
> pdr_get_domain_list since the qmi_send_request there uses
> 'pdr->locator_addr'.
Thanks, I missed it initially. I think I'd keep the rest of the
changes and expand the lock to cover pdr_get_domain_list().
>
> Thanks!
> Chris
--
With best wishes
Dmitry
^ permalink raw reply [relevance 0%]
* [GIT PULL 1/4] soc: devicetree updates for 6.10, part 1
@ 2024-05-10 21:11 3% ` Arnd Bergmann
0 siblings, 0 replies; 200+ results
From: Arnd Bergmann @ 2024-05-10 21:11 UTC (permalink / raw)
To: Linus Torvalds; +Cc: soc, linux-kernel, linux-arm-kernel
The following changes since commit fec50db7033ea478773b159e0e2efb135270e3b7:
Linux 6.9-rc3 (2024-04-07 13:22:46 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git tags/soc-dt-6.10
for you to fetch changes up to 0cb7e0c617c6aa3da46514ee5982bd7de11a2b2e:
Merge tag 'qcom-arm64-for-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt (2024-05-08 09:06:06 +0200)
----------------------------------------------------------------
soc: devicetree updates for 6.10, part 1
The updates this time are a bit smaller than most times, mainly because
it is not totally dominated by new Qualcomm hardware support. Instead,
we larger than average updates for Rockchips, NXP, Allwinner and TI.
The only two new SoCs this time are both from NXP and are minor variants
of already supported ones.
The updates for aspeed, amlogic and mediatek came a little late, so
I'm saving those for part 2 in a few days if everything turns out fine.
New machines this time contain:
- two Broadcom SoC based wireless routers from Asus
- Five allwinner based consumer devices for gaming, set-top-box and
eboot reader applications
- Three older phones based on Qualcomm chips, plus the more recent
Sony Xperia 1 V
- 14 industrial and embedded boards based on NXP i.MX6, i.MX8,
layerscape and s32g3 SoCs
- six rockchips boards including another handheld game console
and a few single-board computers
On top of these, we have the usual cleanups for dtc warnings and
updates to add more features to already merged machines.
----------------------------------------------------------------
Abel Vesa (7):
arm64: dts: qcom: x1e80100: Add SPMI support
arm64: dts: qcom: x1e80100: Add dedicated pmic dtsi
arm64: dts: qcom: x1e80100-crd: Add repeater nodes
arm64: dts: qcom: x1e80100-qcp: Add repeater nodes
arm64: dts: qcom: x1e80100: Drop the link-frequencies from mdss_dp3_in
arm64: dts: qcom: x1e80100-crd: Add data-lanes and link-frequencies to DP3
arm64: dts: qcom: x1e80100-qcp: Add data-lanes and link-frequencies to DP3
Akhil R (1):
arm64: tegra: Add Tegra Security Engine DT nodes
Alain Volmat (6):
arm64: dts: st: add all 8 i2c nodes on stm32mp251
arm64: dts: st: add i2c2/i2c8 pins for stm32mp25
arm64: dts: st: add i2c2 / i2c8 properties on stm32mp257f-ev1
arm64: dts: st: add all 8 spi nodes on stm32mp251
arm64: dts: st: add spi3/spi8 pins for stm32mp25
arm64: dts: st: add spi3 / spi8 properties on stm32mp257f-ev1
Alexander Stein (8):
arm64: dts: imx8mm: Add empty DSI output endpoint
arm64: dts: imx8mn: Add empty DSI output endpoint
arm64: dts: imx8mq: Add empty DSI output endpoint
arm64: dts: imx8mp: Add empty DSI output endpoint
arm64: dts: mba8mx: Simplify DSI connection
ARM: dts: imx6qdl: mba6: Add missing vdd-supply for on-board USB hub
ARM: dts: imx6qdl: Remove LCD.CONTRAST pinctrl from muxing
arm64: dts: imx8mp: Enable HDMI on TQMa8MPxL/MBa8MPxL
Alexandre Torgue (1):
ARM: dts: stm32: put ETZPC as an access controller for STM32MP13x boards
Alice Guo (1):
arm64: dts: imx8dxl: add lpuart device in cm40 subsystem
Anand Moon (2):
arm64: dts: rockchip: Support poweroff on Edgeble Neural Compute Module
arm64: dts: rockchip: Add USB3 on Edgeble NCM6A-IO board
Andre Przywara (3):
arm64: dts: allwinner: h616: Fix I2C0 pins
dt-bindings: arm: sunxi: document Tanix TX1 name
arm64: dts: allwinner: Add Tanix TX1 support
Andreas Kemnade (2):
ARM: dts: imx6sl: tolino-shine2hd: fix IRQ config of touchscreen
ARM: dts: imx6: fix IRQ config of RC5T619
Andrejs Cainikovs (1):
arm64: dts: ti: verdin-am62: dahlia: fix audio clock
Andrew Davis (14):
ARM: dts: ti: keystone: k2g: Remove ti,system-reboot-controller property
dt-bindings: arm: keystone: Remove ti,system-reboot-controller property
arm64: dts: ti: k3-am65: Remove UART baud rate selection
arm64: dts: ti: k3-am64: Remove UART baud rate selection
arm64: dts: ti: k3-j7200: Remove UART baud rate selection
arm64: dts: ti: k3-j721e: Remove UART baud rate selection
arm64: dts: ti: k3-j721s2: Remove UART baud rate selection
arm64: dts: ti: k3-j784s4: Remove UART baud rate selection
arm64: dts: ti: k3-am65: Add full compatible to SerDes control nodes
arm64: dts: ti: k3-am65: Move SerDes mux nodes under the control node
arm64: dts: ti: k3-am65: Use exact ranges for FSS node
arm64: dts: ti: k3-j7200: Use exact ranges for FSS node
arm64: dts: ti: k3-j721e: Use exact ranges for FSS node
arm64: dts: ti: k3-j784s4: Use exact ranges for FSS node
André Draszik (9):
arm64: dts: exynos: gs101: reorder pinctrl-* properties
dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit
arm64: dts: exynos: gs101: enable cmu-hsi0 clock controller
arm64: dts: exynos: gs101: add USB & USB-phy nodes
arm64: dts: exynos: gs101-oriole: enable USB on this board
arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) alive
arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01]
arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2
arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl
Andy Yan (2):
arm64: dts: rockchip: Enable gpu on Cool Pi CM5
arm64: dts: rockchip: Enable gpu on Cool Pi 4B
Anton Bambura (5):
arm64: dts: qcom: sc8180x-lenovo-flex-5g: fix GPU firmware path
arm64: dts: qcom: sc8180x-lenovo-flex-5g: set names for i2c hid nodes
arm64: dts: qcom: sc8180x-lenovo-flex-5g: move pinctrl to appropriate nodes
arm64: dts: qcom: sc8180x-lenovo-flex-5g: set touchpad i2c frequency to 1 MHz
arm64: dts: qcom: sc8180x-lenovo-flex-5g: Allow UFS regulators load/mode setting
Aren Moynihan (1):
arm64: dts: allwinner: pinephone: add multicolor LED node
Arnd Bergmann (31):
Merge tag 'renesas-dt-bindings-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Merge tag 'renesas-dts-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Merge tag 'omap-for-v6.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt
Merge tag 'samsung-dt-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Merge tag 'samsung-dt64-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Merge tag 'hisi-arm64-dt-for-6.10' of https://github.com/hisilicon/linux-hisi into soc/dt
Merge tag 'stm32-dt-for-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
Merge tag 'v6.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
Merge tag 'renesas-dts-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Merge tag 'sunxi-dt-for-6.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
Merge tag 'tegra-for-6.10-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
Merge tag 'tegra-for-6.10-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
Merge tag 'tegra-for-6.10-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
Merge tag 'sunxi-dt-for-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
Merge tag 'qcom-arm32-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Merge tag 'qcom-arm64-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Merge tag 'imx-bindings-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
Merge tag 'imx-dt-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
Merge tag 'imx-dt64-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
Merge tag 'dt64-cleanup-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
Merge tag 'dt-cleanup-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
Merge tag 'microchip-dt64-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
Merge tag 'arm-soc/for-6.10/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
Merge tag 'arm-soc/for-6.10/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
Merge tag 'riscv-sophgo-dt-for-v6.10' of https://github.com/sophgo/linux into soc/dt
Merge tag 'ti-keystone-dt-for-v6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
Merge tag 'ti-k3-dt-for-v6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
Merge tag 'mvebu-dt64-6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
Merge tag 'v6.10-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
Merge tag 'samsung-dt64-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Merge tag 'qcom-arm64-for-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Arthur Demchenkov (1):
ARM: dts: n900: set charge current limit to 950mA
Artur Weber (1):
ARM: dts: exynos4212-tab3: limit usable memory range
Arınç ÜNAL (9):
ARM: dts: BCM5301X: use color and function on ASUS RT-AC3100 and RT-AC88U
ARM: dts: BCM5301X: provide address for SoC MACs on ASUS RT-AC3100 & AC88U
ARM: dts: BCM5301X: remove duplicate compatible on ASUS RT-AC3100 & AC88U
ARM: dts: BCM5301X: remove earlycon on ASUS RT-AC3100 and ASUS RT-AC88U
dt-bindings: arm: bcm: add bindings for ASUS RT-AC3200
dt-bindings: arm: bcm: add bindings for ASUS RT-AC5300
ARM: dts: BCM5301X: Add DT for ASUS RT-AC3200
ARM: dts: BCM5301X: Add DT for ASUS RT-AC5300
ARM: dts: BCM5301X: Conform to DTS Coding Style on ASUS RT-AC3100 & AC88U
Bhavya Kapoor (2):
arm64: dts: ti: k3-j721s2-main: Enable support for SDR104 speed mode
arm64: dts: ti: k3-j722s-evm: Enable UHS support for MMCSD
Biju Das (1):
arm64: dts: renesas: rzg2ul-smarc: Enable PMIC and built-in RTC, GPIO and ONKEY
Bjorn Andersson (9):
arm64: dts: qcom: qcs6490-rb3gen2: Name the regulators
Merge branch 'arm64-for-6.10' onto 'v6.9-rc1'
Merge branch 'arm32-for-6.10' onto 'v6.9-rc1'
arm64: dts: qcom: sc7280: Enable MDP turbo mode
arm64: dts: qcom: qcs6490-rb3gen2: Add DP output
arm64: dts: qcom: qcs6490-rb3gen2: Enable adsp and cdsp
arm64: dts: qcom: qcs6490-rb3gen2: Introduce USB redriver
arm64: dts: qcom: qcs6490-rb3gen2: Enable USB Type-C display
arm64: dts: qcom: qcs6490-rb3gen2: Enable UFS
Boris Brezillon (3):
arm64: dts: rockchip: Add rk3588 GPU node
arm64: dts: rockchip: Enable GPU on rk3588-rock5b
arm64: dts: rockchip: Enable GPU on rk3588-evb1
Brandon Brnich (1):
arm64: dts: ti: k3-am62a-main: Add Wave5 Video Encoder/Decoder Node
Caleb Connolly (1):
arm64: dts: qcom: sdm845-db845c: make pcie0_3p3v_dual always-on
Carlos Song (1):
arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery
Chris Morgan (9):
arm64: dts: rockchip: Add additional properties for WiFi on Anbernic rgxx3
arm64: dts: rockchip: Add optional node for chasis-type on Anbernic rgxx3
arm64: dts: rockchip: Correct model name for Anbernic RGxx3 Devices
arm64: dts: rockchip: Add chasis-type for Powkiddy rk3566 devices
arm64: dts: rockchip: Correct model name for Powkiddy RK3566 Devices
dt-bindings: arm: rockchip: Add GameForce Chi
arm64: dts: rockchip: Add GameForce Chi
arm64: dts: rockchip: Add USB-C Support for rk3588s-indiedroid-nova
arm64: dts: allwinner: h616: Add NMI device node
Christian Marangi (1):
ARM: dts: qcom: ipq4019: add QCA8075 PHY Package nodes
Chukun Pan (5):
dt-bindings: arm: rockchip: correct the model name for Radxa ROCK 3A
arm64: dts: rockchip: correct the model name for Radxa ROCK 3A
dt-bindings: arm: rockchip: add Radxa ROCK 3C
arm64: dts: rockchip: Add Radxa ROCK 3C
arm64: dts: rockchip: enable onboard spi flash for rock-3a
Claudiu Beznea (1):
arm64: dts: renesas: rzg3s-smarc-som: Fix Ethernet aliases
Connor Abbott (1):
arm64: dts: qcom: sm8650: Fix GPU cx_mem size
Danila Tikhonov (3):
arm64: dts: qcom: pm6150: define USB-C related blocks
arm64: dts: qcom: sc7180: Fix UFS PHY clocks
arm64: dts: qcom: pm6150l: add Light Pulse Generator device node
Dario Binacchi (1):
ARM: dts: stm32: move can3 node from stm32f746 to stm32f769
Dasnavis Sabiya (1):
arm64: dts: ti: k3-j784s4-main: Enable support for UHS mode
David Heidelberg (2):
ARM: dts: qcom: include cpu in idle-state node names
ARM: dts: qcom: msm8916: idle-state compatible require the generic idle-state
David Jander (1):
arm64: dts: rockchip: add Protonic MECSBC device-tree
Denis Burkov (2):
dt-bindings: arm: sunxi: Add PocketBook 614 Plus
ARM: dts: sun5i: Add PocketBook 614 Plus support
Diederik de Haas (1):
arm64: dts: rockchip: Fix ordering of nodes on rk3588s
Dmitry Baryshkov (15):
arm64: dts: qcom: qrb2210-rb1: enable USB-C port handling
arm64: dts: qcom: sc8180x: drop legacy property #stream-id-cells
arm64: dts: qcom: sc8180x: Drop flags for mdss irqs
arm64: dts: qcom: sc8180x: add dp_p1 register blocks to DP nodes
arm64: dts: qcom: sm8350: Add interconnects to UFS
dt-bindings: arm: qcom: drop dtbTool-specific compatibles
arm64: dts: qcom: msm8916: drop dtbTool-specific compatibles
arm64: dts: qcom: sm8150-hdk: enable WiFI support
dt-bindings: soc: qcom: pmic-glink: allow orientation-gpios
arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO
arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO
arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs
arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs
arm64: dts: qcom: qrb2210-rb1: add firmware-name qualifier to WiFi node
arm64: dts: qcom: qrb4210-rb1: add firmware-name qualifier to WiFi node
Dmitry Yashin (3):
dt-bindings: arm: rockchip: add Forlinx FET3588-C
arm64: dts: rockchip: add Forlinx FET3588-C
arm64: dts: rockchip: add Forlinx OK3588-C
Dong Aisheng (1):
arm64: dts: imx8: add cm40 subsystem dtsi
Dragan Simic (7):
arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3328
arm64: dts: rockchip: Add cache information to the SoC dtsi for RK356x
arm64: dts: rockchip: Enable the GPU on quartzpro64
dt-bindings: arm: rockchip: Correct the descriptions for Radxa boards
arm64: dts: rockchip: Correct the model names for Radxa ROCK 5 boards
dt-bindings: arm: rockchip: Correct the descriptions for Pine64 boards
arm64: dts: rockchip: Correct the model names for Pine64 boards
Duy Nguyen (1):
arm64: dts: renesas: r8a779h0: Add thermal nodes
Elliot Berman (1):
arm64: dts: qcom: sm8650: Add missing reserved memory for chipinfo
Fabio Estevam (8):
ARM: dts: imx7s: Add snvs-poweroff support
ARM: dts: imx6qdl-udoo: Enable USB host
arm64: dts: imx8m/qxp: Pass the tcpci compatible
arm64: dts: imx8mn-evk: Fix ADV7535 dt-schema warnings
arm64: dts: imx8mn-evk: Describe the OV5640 supplies
arm64: dts: imx8mm-evk: Describe the OV5640 supplies
arm64: dts: imx8mp-debix-som-a-bmb-08: Remove 'phy-supply' from eqos
arm64: dts: imx8-ss-img: Remove JPEG clock-names
Florian Fainelli (1):
arm: dts: bcm2711: Describe Ethernet LEDs
Folker Schwesinger (2):
arm64: dts: rockchip: Add enable-strobe-pulldown to emmc phy on ROCK Pi 4
arm64: dts: rockchip: Add enable-strobe-pulldown to emmc phy on ROCK 4C+
Francesco Dolcini (3):
arm64: dts: ti: verdin-am62: use SD1 CD as GPIO
arm64: dts: ti: verdin-am62: mallow: fix GPIOs pinctrl
arm64: dts: ti: k3-am625-verdin: add PCIe reset gpio hog
Frank Li (10):
arm64: dts: imx8qm-mek: add adc0 support
arm64: dts: imx8qm-mek: add lpspi2 support
arm64: dts: imx8qm-mek: add flexspi0 support
arm64: dts: imx8: fix audio lpcg index
arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5]
arm64: dts: imx8dxl: update cm40 irq number information
arm64: dts: imx8dxl-evk: add lpuart1 and cm40 uart
ARM: dts: nxp: imx6sx: fix esai related warning when do dtb_check
ARM: dts: nxp: imx6qdl: fix esai clock warning when do dtb_check
arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960 and sai[0,1,4,5]
Frank Oltmanns (1):
arm64: dts: allwinner: a64: Run GPU at 432 MHz
Gabriel Fernandez (1):
arm64: dts: st: add rcc support for STM32MP25
Garrett Giordano (2):
arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Add Audio Codec
arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Add USB-C
Gatien Chevallier (4):
arm64: dts: st: add RIFSC as an access controller for STM32MP25x boards
ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
ARM: dts: stm32: put ETZPC as an access controller for STM32MP15x boards
ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
Geert Uytterhoeven (11):
ARM: dts: renesas: r8a73a4: Add TMU nodes
ARM: dts: renesas: rzg1: Add TMU nodes
ARM: dts: renesas: rcar-gen2: Add TMU nodes
arm64: dts: renesas: r8a779h0: Add remaining HSCIF nodes
arm64: dts: renesas: r8a779h0: Add SCIF nodes
arm64: dts: renesas: gray-hawk-single: Add second debug serial port
ARM: dts: renesas: r9a06g032: Remove duplicate interrupt-parent
arm64: dts: renesas: gray-hawk-single: Enable nfsroot
arm64: dts: renesas: s4sk: Fix ethernet0 alias
arm64: dts: renesas: r8a779h0: Add INTC-EX node
arm64: dts: renesas: r8a779h0: Link IOMMU consumers
Ghennadi Procopciuc (2):
arm64: dts: s32g: add SCMI firmware node
arm64: dts: s32g: add uSDHC node
Gilles Talis (3):
dt-bindings: vendor-prefixes: Add Emcraft Systems
dt-bindings: arm: Add Emcraft Systems i.MX8M Plus NavQ+ Kit
arm64: dts: freescale: Add device tree for Emcraft Systems NavQ+ Kit
Haibo Chen (1):
arm64: dts: imx93: assign usdhc[1..3] root clock to 400MHz
Heiko Stuebner (8):
arm64: dts: rockchip: enable gpu on rk3588-jaguar
arm64: dts: rockchip: enable gpu on rk3588-tiger
arm64: dts: rockchip: move uart2 pinmux to dtsi on rk3588-tiger
arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar
arm64: dts: rockchip: fix pcie-refclk frequency on rk3588 tiger
arm64: dts: rockchip: fix comment for upper usb3 port
arm64: dts: rockchip: add usb-id extcon on rk3588 tiger
arm64: dts: rockchip: add dual-role usb3 hosts to rk3588 Tiger-Haikou
Hiago De Franco (5):
arm64: dts: freescale: Add i.MX8DX dtsi
arm64: dts: freescale: Add Toradex Colibri iMX8DX
dt-bindings: arm: fsl: remove reduntant toradex,colibri-imx8x
dt-bindings: arm: fsl: Add Colibri iMX8DX
arm64: dts: freescale: imx8m[mp]-verdin: Update audio card name
Hugues Fruchet (1):
media: dt-bindings: add access-controllers to STM32MP25 video codecs
Hui Liu (1):
arm64: dts: qcom: qcm6490-idp: enable PMIC Volume and Power buttons
Ian Ray (2):
arm64: dts: imx8mp-msc-sm2s: correct i2c{1..6} pad drive strength
arm64: dts: imx8mp-msc-sm2s: Add i2c{1,6} sda-/scl-gpios
Inochi Amaoto (6):
riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC
riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC
riscv: dts: sophgo: cv18xx: Add spi devices
riscv: dts: sophgo: cv18xx: Add i2c devices
riscv: dts: sophgo: use real clock for sdhci
riscv: dts: sophgo: add reserved memory node for CV1800B
Jacopo Mondi (1):
arm64: dts: debix-a: Disable i2c2 in base .dts
Jai Luthra (1):
arm64: dts: ti: Fix csi2-dual-imx219 dtb names
Jan Kiszka (1):
arm64: dts: ti: iot2050: Add icssg-prueth nodes for PG1 devices
Jean-Michel Hautbois (1):
ARM: dts: bcm2835: Add Unicam CSI nodes
Jianfeng Liu (3):
dt-bindings: vendor-prefixes: add ArmSoM
dt-bindings: arm: rockchip: Add ArmSoM Sige7
arm64: dts: rockchip: Add ArmSom Sige7 board
Jianhua Lu (2):
arm64: dts: qcom: sm8250-xiaomi-elish: add usb pd negotiation support
arm64: dts: qcom: sm8250-xiaomi-elish: set pm8150b_vbus regulator-min-microamp and regulator-max-microamp
Jimmy Hon (2):
arm64: dts: rockchip: Enable GPU on Orange Pi 5
arm64: dts: rockchip: add USB-C support to rk3588s-orangepi-5
Jing Luo (1):
arm64: dts: rockchip: correct gpio_pwrctrl1 typos on rk3588(s) boards
Jisheng Zhang (1):
riscv: dts: sophgo: add sdcard support for milkv duo
Joe Mason (1):
arm64: dts: qcom: msm8916-samsung-fortuna: Add touchscreen
Johan Hovold (4):
arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
arm64: dts: qcom: sc8280xp: enable GICv3 ITS for PCIe
arm64: dts: qcom: sc8280xp-x13s: enable USB MP and fingerprint reader
arm64: dts: qcom: qcs404: fix bluetooth device address
Josua Mayer (2):
arm64: dts: fsl-lx2162a-som: add description for rtc
arm64: dts: fsl-lx2162a-clearfog: add alias for i2c bus iic6
Joy Zou (2):
arm64: dts: imx93-11x11-evk: add pca9451a support
arm64: dts: imx93-11x11-evk: add RTC PCF2131 support
Judith Mendez (2):
arm64: dts: ti: k3-am65-main: Fix sdhci node properties
arm64: dts: ti: k3-am65-main: Remove unused properties in sdhci nodes
Komal Bajaj (2):
arm64: dts: qcom: qcm6490-idp: Enable various remoteprocs
arm64: dts: qcom: qcs6490-rb3gen2: Enable various remoteprocs
Konrad Dybcio (12):
arm64: dts: qcom: sc8280xp: Add missing LMH interrupts
arm64: dts: qcom: sc8280xp: Add QFPROM node
arm64: dts: qcom: sc8280xp: Add PS_HOLD restart
arm64: dts: qcom: sc8280xp: Describe TCSR download mode register
arm64: dts: qcom: msm8998-yoshino: Enable RGB led
dt-bindings: arm: qcom: Add Xperia 1 V
arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherent
arm64: dts: qcom: sm8550: Mark APPS SMMU as dma-coherent
arm64: dts: qcom: sm8550: Add missing DWC3 quirks
arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent
arm64: dts: qcom: Add SM8550 Xperia 1 V
arm64: dts: qcom: sc8280xp: Fill in EAS properties
Krishna Kurapati (2):
arm64: dts: qcom: sc8280xp: Add missing hs_phy_irq in USB nodes
arm64: dts: qcom: sc8280xp: Add USB DWC3 Multiport controller
Krzysztof Kozlowski (76):
arm64: dts: qcom: x1e80100: correct SWR1 pack mode
arm64: dts: qcom: x1e80100-crd: switch WSA8845 speakers to shared reset-gpio
ARM: dts: samsung: smdkv310: fix keypad no-autorepeat
ARM: dts: samsung: exynos4412-origen: fix keypad no-autorepeat
ARM: dts: samsung: smdk4412: fix keypad no-autorepeat
ARM: dts: samsung: smdk4412: align keypad node names with dtschema
ARM: dts: samsung: exynos5800-peach-pi: switch to undeprecated DP HPD GPIOs
ARM: dts: samsung: s5pv210: align onenand node name with bindings
ARM: dts: samsung: s5pv210: correct onenand size-cells
arm64: dts: juno: fix thermal zone node names
arm64: dts: amd: use capital "OR" for multiple licenses in SPDX
arm64: dts: qcom: pm6150: correct Type-C compatible
arm64: dts: marvell: ap80x: fix IOMMU unit address
arm64: dts: marvell: cn9130-db: drop unneeded flash address/size-cells
arm64: dts: marvell: cn9131-db: drop unneeded flash address/size-cells
arm64: dts: marvell: cn9130-db: drop wrong unit-addresses
arm64: dts: marvell: cn9130-crb: drop wrong unit-addresses
arm64: dts: marvell: cn9130-crb: drop unneeded "status"
arm64: dts: sprd: minor whitespace cleanup
arm64: dts: qcom: apq8016-sbc: correct GPIO LEDs node names
arm64: dts: microchip: sparx5: fix mdio reg
arm64: dts: microchip: sparx5: correct serdes unit address
arm64: dts: microchip: sparx5_pcb134: add missing I2C mux unit addresses
arm64: dts: microchip: sparx5_pcb135: add missing I2C mux unit addresses
arm64: dts: microchip: sparx5_pcb134: align I2C mux node name with bindings
arm64: dts: microchip: sparx5_pcb135: align I2C mux node name with bindings
arm64: dts: microchip: sparx5_pcb134: drop LED unit addresses
arm64: dts: microchip: sparx5_pcb135: drop LED unit addresses
arm64: dts: microchip: sparx5_pcb134: drop duplicated NOR flash
arm64: dts: microchip: sparx5_pcb135: drop duplicated NOR flash
arm64: dts: ti: k3-am62p5-sk: minor whitespace cleanup
ARM: dts: ti: omap: minor whitespace cleanup
arm64: dts: hisilicon: hip05: move non-MMIO node out of soc
arm64: dts: hisilicon: hip05-d02: correct local-bus unit addresses
arm64: dts: hisilicon: hip06: move non-MMIO node out of soc
arm64: dts: hisilicon: hip06: correct unit addresses
arm64: dts: allwinner: Pine H64: correctly remove reg_gmac_3v3
arm64: dts: allwinner: drop underscore in node names
arm64: dts: allwinner: Orange Pi: delete node by phandle
arm: dts: allwinner: drop underscore in node names
arm64: dts: hisilicon: hip07: move non-MMIO node out of soc
arm64: dts: hisilicon: hip07: correct unit addresses
arm64: dts: hisilicon: hi6220-hikey: add missing port@0 reg
arm64: dts: hisilicon: hi6220-hikey: drop unit addresses from fixed regulators
arm64: dts: hisilicon: hi6220: correct tsensor unit addresses
arm64: dts: qcom: sdx75: add unit address to soc node
arm64: dts: imx8mm-var-som-symphony: drop redundant status from typec
arm64: dts: imx8mn-var-som-symphony: drop redundant status from typec
arm64: dts: sc9860: add missing aon-prediv unit address
arm64: dts: sc9860: move GPIO keys to board
arm64: dts: sc9860: move GIC to soc node
arm64: dts: whale2: add missing ap-apb unit address
arm64: dts: sharkl3: add missing unit addresses
arm64: dts: uniphier: ld11-global: use generic node name for audio-codec
arm64: dts: uniphier: ld11-global: drop audio codec port unit address
arm64: dts: uniphier: ld20-global: use generic node name for audio-codec
arm64: dts: uniphier: ld20-global: drop audio codec port unit address
arm64: dts: realtek: rtd129x: add missing unit address to soc node
arm64: dts: realtek: rtd139x: add missing unit address to soc node
arm64: dts: realtek: rtc16xx: add missing unit address to soc node
arm64: dts: cavium: move non-MMIO node out of soc
arm64: dts: cavium: correct unit addresses
arm64: dts: apm: storm: move non-MMIO node out of soc
arm64: dts: apm: shadowcat: move non-MMIO node out of soc
arm64: dts: amazon: alpine-v2: add missing io-fabric unit addresses
arm64: dts: amazon: alpine-v2: move non-MMIO node out of soc
arm64: dts: amazon: alpine-v3: add missing io-fabric unit addresses
arm64: dts: amazon: alpine-v3: drop cache nodes unit addresses
arm64: dts: amazon: alpine-v3: correct gic unit addresses
arm64: dts: cavium: thunder2-99xx: drop redundant reg-names
arm64: tegra: Correct Tegra132 I2C alias
Merge branch 'for-v6.10/clk-gs101-bindings' into next/dt64
arm64: dts: qcom: pm6150: correct USB VBUS regulator compatible
arm64: dts: marvell: eDPU: drop redundant address/size-cells
arm64: dts: marvell: turris-mox: drop unneeded flash address/size-cells
arm64: dts: marvell: espressobin-ultra: fix Ethernet Switch unit address
Lad Prabhakar (7):
ARM: dts: renesas: r7s72100: Add interrupt-names to SCIF nodes
dt-bindings: soc: renesas: Document Renesas RZ/V2H(P) SoC variants
dt-bindings: arm: renesas: Document Renesas RZ/V2H(P) System Controller
riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI
arm64: dts: renesas: r9a07g043: Move interrupt-parent property to common DTSI
riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt properties from ETH0/1 nodes
arm64: dts: renesas: rzg3s-smarc-som: Enable eMMC by default
Laurent Pinchart (5):
dt-bindings: arm: bcm: raspberrypi,bcm2835-firmware: Add gpio child node
firmware: raspberrypi: Use correct device for DMA mappings
ARM: dts: bcm283x: Drop unneeded properties in the bcm2835-firmware node
ARM: dts: bcm2835-rpi: Move duplicate firmware-clocks to bcm2835-rpi.dtsi
ARM: dts: bcm2711-rpi-4-b: Add CAM1 regulator
Ling Xu (1):
arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodes
Loic Poulain (1):
arm64: dts: qcom: qcm2290: Add LMH node
Luca Ceresoli (2):
arm64: dts: rockchip: add i2s_8ch_2 and i2s_8ch_3 to rk3308
arm64: dts: rockchip: add the internal audio codec on rk3308
Luca Weiss (16):
arm64: dts: qcom: sm6350: Add Crypto Engine
arm64: dts: qcom: sdm632-fairphone-fp3: enable USB-C port handling
ARM: dts: qcom: msm8974pro-castor: Clean up formatting
ARM: dts: qcom: msm8974pro-castor: Add mmc aliases
ARM: dts: qcom: msm8974pro-castor: Remove camera button definitions
ARM: dts: qcom: msm8974pro-castor: Add debounce-interval for keys
ARM: dts: qcom: msm8974pro-castor: Rename wifi node name
ARM: dts: qcom: msm8974-sony-castor: Split into shinano-common
ARM: dts: qcom: Add Sony Xperia Z3 smartphone
arm64: dts: qcom: sc7280: Add inline crypto engine
dt-bindings: arm: qcom: Add Sony Xperia Z3
ARM: dts: qcom: msm8974: Add @0 to memory node name
ARM: dts: qcom: msm8974: Add empty chosen node
ARM: dts: qcom: msm8974-sony-shinano: Enable vibrator
arm64: dts: qcom: qcm6490-fairphone-fp5: Add USB-C orientation GPIO
arm64: dts: qcom: sm6350: Add DisplayPort controller
Lucas Stach (3):
arm64: dts: imx8mp: add HDMI power-domains
arm64: dts: imx8mp: add HDMI irqsteer
arm64: dts: imx8mp: add HDMI display pipeline
Luke Wang (1):
arm64: dts: imx93-11x11-evk: add different usdhc pinctrl for different timing usage
Manivannan Sadhasivam (20):
ARM: dts: qcom: ipq8064: Add PCIe bridge node
ARM: dts: qcom: ipq4019: Add PCIe bridge node
ARM: dts: qcom: apq8064: Add PCIe bridge node
ARM: dts: qcom: sdx55: Add PCIe bridge node
arm64: dts: qcom: sm8250: Add PCIe bridge node
arm64: dts: qcom: sdm845: Add PCIe bridge node
arm64: dts: qcom: sm8150: Add PCIe bridge node
arm64: dts: qcom: sm8350: Add PCIe bridge node
arm64: dts: qcom: sm8450: Add PCIe bridge node
arm64: dts: qcom: sm8550: Add PCIe bridge node
arm64: dts: qcom: sm8650: Add PCIe bridge node
arm64: dts: qcom: sa8775p: Add PCIe bridge node
arm64: dts: qcom: sc8280xp: Add PCIe bridge node
arm64: dts: qcom: msm8998: Add PCIe bridge node
arm64: dts: qcom: sc7280: Add PCIe bridge node
arm64: dts: qcom: qcs404: Add PCIe bridge node
arm64: dts: qcom: sc8180x: Add PCIe bridge node
arm64: dts: qcom: msm8996: Add PCIe bridge node
arm64: dts: qcom: ipq8074: Add PCIe bridge node
arm64: dts: qcom: ipq6018: Add PCIe bridge node
Marek Vasut (3):
arm64: dts: imx8mp: Describe CSI2 GPIO expander on i.MX8MP DHCOM PDK3 board
arm64: dts: imx8mp: Align both CSI2 pixel clock
ARM: dts: stm32: add PWR regulators support on stm32mp131
Markus Schneider-Pargmann (1):
arm64: dts: ti: k3-am62-lp-sk: Remove tps65219 power-button
Max Krummenacher (1):
arm64: dts: ti: verdin-am62: Set memory size to 2gb
Michael Grzeschik (1):
ARM: dts: imx27-phytec: Add USB support
Michael Riesch (4):
dt-bindings: add wolfvision vendor prefix
dt-bindings: arm: rockchip: add wolfvision pf5 mainboard
arm64: dts: rockchip: add wolfvision pf5 mainboard
arm64: dts: rockchip: add wolfvision pf5 io expander board
Michael Walle (3):
arm64: dts: ti: k3-{am62p,j722s}: Disable ethernet by default
arm64: dts: ti: k3-j722s-evm: Enable eMMC support
arm64: dts: ls1028a: sl28: split variant 3/ads2 carrier
Miles Alan (1):
arm64: dts: allwinner: pinephone: Retain LEDs state in suspend
Mohammad Shehar Yaar Tausif (1):
ARM: tegra: tegra20-ac97: Replace deprecated "gpio" suffix
Muhammed Efe Cetin (10):
arm64: dts: rockchip: Add cpu regulators and vcc5v0_sys to Khadas Edge 2
arm64: dts: rockchip: Add PMIC to Khadas Edge 2
arm64: dts: rockchip: Add TF card to Khadas Edge 2
arm64: dts: rockchip: USB2, USB3 Host, PCIe2 to Khadas Edge 2
arm64: dts: rockchip: Add ir receiver and leds to Khadas Edge 2
arm64: dts: rockchip: Add saradc and adc buttons to Khadas Edge 2 and enable tsadc
arm64: dts: rockchip: Add SFC to Khadas Edge 2
arm64: dts: rockchip: Add UART9 (bluetooth) to Khadas Edge 2
arm64: dts: rockchip: Add RTC to Khadas Edge 2
arm64: dts: rockchip: enable GPU on khadas-edge2
Nathan Morrisson (4):
arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Increase CAN max bitrate
arm64: dts: ti: k3-am642-phyboard-electra-rdk: Increase CAN max bitrate
arm64: dts: ti: am64-phyboard-electra: Add overlay to enable a GPIO fan
arm64: dts: ti: Enable overlays for the am625-phyboard-lyra
Neil Armstrong (7):
arm64: dts: qcom: sm8450: add missing qcom,non-secure-domain property
arm64: dts: qcom: sm8550: add missing qcom,non-secure-domain property
arm64: dts: qcom: sm8650: add missing qcom,non-secure-domain property
arm64: dts: qcom: sm8650: fix usb interrupts properties
arm64: dts: qcom: sm8650: remove useless enablement of mdss_mdp
arm64: dts: qcom: sm8650: add GPU nodes
arm64: dts: qcom: sm8650-qrd: enable GPU
Nicolas Chauvet (1):
ARM: tegra: paz00: Add emc-tables for ram-code 1
Niklas Cassel (1):
arm64: dts: rockchip: add rk3588 pcie and php IOMMUs
Niklas Söderlund (1):
arm64: dts: renesas: eagle: Add capture overlay for Function expansion board
Pankaj Gupta (1):
arm64: dts: imx8ulp: add caam jr
Parthiban Nallathambi (2):
ARM: dts: imx6ull: add seeed studio NPi dev board
dt-bindings: arm: fsl: Add Seeed studio NPi based boards
Patrice Chotard (1):
ARM: dts: stm32: add heartbeat led for stm32mp157c-ed1
Patrick Delaunay (1):
arm64: dts: st: correct masks for GIC PPI interrupts on stm32mp25
Paweł Owoc (2):
arm64: dts: qcom: ipq8074: Add QUP UART6 node
arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins
Peng Fan (9):
arm64: dts: imx93: drop the 4th interrupt for ADC
arm64: dts: imx93: use FSL_EDMA_RX for rx channel
arm64: dts: imx93: add dma support for lpi2c[1..8]
arm64: dts: imx93: add dma support for lpspi[1..8]
arm64: dts: imx93: add nvmem property for fec1
arm64: dts: imx93: add nvmem property for eqos
arm64: dts: imx93-11x11-evk: update resource table address
arm64: dts: imx93-11x11-evk: add sleep pinctrl for eqos and fec
arm64: dts: imx93-11x11-evk: add sleep pinctrl for sdhc2
Peter Griffin (6):
dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller
dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible
arm64: dts: exynos: gs101: Add the hsi2 sysreg node
arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes
arm64: dts: exynos: gs101: enable ufs, phy on oriole & define ufs regulator
Rafał Miłecki (1):
arm64: dts: broadcom: bcmbca: bcm4908: set brcm,wp-not-connected
Raphael Gallais-Pou (4):
dt-bindings: display: simple: allow panel-common properties
ARM: dts: stm32: add LTDC support for STM32MP13x SoC family
ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family
ARM: dts: stm32: enable display support on stm32mp135f-dk board
Raymond Hackley (1):
arm64: dts: qcom: msm8916/39-samsung-a2015: Add connector for MUIC
Richard Acayan (1):
arm64: dts: qcom: sdm670-google-sargo: add panel
Ritesh Kumar (1):
arm64: dts: qcom: qcm6490-idp: add display and panel
Rob Herring (2):
arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usage
arm64: dts: Add/fix /memory node unit-addresses
Rob Herring (Arm) (2):
arm64: dts: freescale: ls1028a: Fix embedded PCI interrupt mapping
arm64: dts: freescale: ls1028a: Add standard PCI device compatible strings to ENETC
Roger Quadros (5):
arm64: dts: ti: k3-am62*: Add PHY2 region to USB wrapper node
arm64: dts: ti: k3-am62/a: use sub-node for USB_PHY_CTRL registers
arm64: dts: ti: k3-am62p: add the USB sub-system
arm64: dts: ti: k3-am62a: Disable USB LPM
arm64: dts: ti: k3-am625-beagleplay: Fix Ethernet PHY RESET GPIOs
Rong Zhang (4):
dt-bindings: arm: qcom: Add Samsung Galaxy S5 China (kltechn)
ARM: dts: qcom: msm8974: Split out common part of samsung-klte
ARM: dts: qcom: msm8974-klte-common: Pin WiFi board type
ARM: dts: qcom: msm8974: Add DTS for Samsung Galaxy S5 China (kltechn)
Ryan Walklin (4):
dt-bindings: arm: sunxi: document Anbernic RG35XX handheld gaming device variants
arm64: dts: allwinner: h700: Add RG35XX 2024 DTS
arm64: dts: allwinner: h700: Add RG35XX-Plus DTS
arm64: dts: allwinner: h700: Add RG35XX-H DTS
Sam Protsenko (1):
arm64: dts: exynos850: Add CPU clocks
Sascha Hauer (1):
dt-bindings: arm: rockchip: Add Protonic MECSBC board
Sebastian Raase (2):
arm64: dts: qcom: sdm630-nile: add pinctrl for camera key
arm64: dts: qcom: msm8998-yoshino: fix volume-up key
Sebastian Reichel (8):
ARM: dts: imx: Add UNI-T UTi260B thermal camera board
arm64: dts: rockchip: fix usb2phy nodename for rk3588
arm64: dts: rockchip: reorder usb2phy properties for rk3588
arm64: dts: rockchip: add USBDP phys on rk3588
arm64: dts: rockchip: add USB3 DRD controllers on rk3588
arm64: dts: rockchip: add USB3 to rk3588-evb1
arm64: dts: rockchip: add upper USB3 port to rock-5a
arm64: dts: rockchip: add lower USB3 port to rock-5b
Shengjiu Wang (5):
arm64: dts: imx8mp: Add AUD2HTX device node
arm64: dts: imx8mp-evk: Add HDMI audio sound card support
arm64: dts: imx8mp-evk: Add PDM micphone sound card support
ARM: dts: imx6sx-nitrogen6sx: drop incorrect cpu-dai property
ARM: dts: imx6: exchange fallback and specific compatible string
Siddharth Manthan (1):
arm64: dts: qcom: msm8916-samsung-fortuna: Add PWM backlight
Stanislav Jakubek (2):
dt-bindings: arm: qcom: Add Motorola Moto G (2013)
ARM: dts: qcom: Add support for Motorola Moto G (2013)
Stefan Eichenberger (6):
arm64: dts: freescale: imx8mp-verdin: replace sleep-moci hog with regulator
arm64: dts: freescale: imx8mp-verdin-dahlia: support sleep-moci
arm64: dts: freescale: imx8mm-verdin: replace sleep-moci hog with regulator
arm64: dts: freescale: imx8mm-verdin-dahlia: support sleep-moci
arm64: dts: ti: k3-am62-verdin: replace sleep-moci hog with regulator
arm64: dts: ti: k3-am62-verdin-dahlia: support sleep-moci
Stefan Wahren (1):
ARM: dts: imx6ull-tarragon: Reduce SPI clock for QCA7000
Stephen Boyd (2):
arm64: dts: qcom: sc7180: Disable pmic pinctrl node on Trogdor
arm64: dts: qcom: sc7180: Disable DCC node by default
Sukrut Bellary (1):
arm64: dts: ti: k3-am625-beagleplay: Use mmc-pwrseq for wl18xx enable
Thanh Le (1):
arm64: dts: renesas: r8a779h0: Add IPMMU nodes
Thanh Quan (3):
arm64: dts: renesas: r8a779h0: Add CMT nodes
arm64: dts: renesas: r8a779h0: Add TMU nodes
arm64: dts: renesas: r8a779h0: Add MSIOF nodes
Thierry Reding (1):
dt-bindings: display: tegra: Allow dma-coherent on Tegra194 and later
Tim Harvey (5):
arm64: dts: imx8mp-venice-gw74xx-imx219.dtso: fix dt warning
arm64: dts: imx8mp-venice-gw74xx: add ADC rail for VDD_1P0
arm64: dts: imx8mp-venice-gw72xx: add mac addr for eth1
arm64: dts: imx8mp-venice-gw73xx: add mac addr for eth1
arm64: dts: imx8m*-venice-gw7: Fix TPM schema violations
Tony Lindgren (12):
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB
ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0
Tudor Ambarus (11):
ARM: dts: samsung: exynos3250: specify the SPI FIFO depth
ARM: dts: samsung: exynos4: specify the SPI FIFO depth
ARM: dts: samsung: exynos5250: specify the SPI FIFO depth
ARM: dts: samsung: exynos5420: specify the SPI FIFO depth
arm64: dts: exynos5433: specify the SPI FIFO depth
arm64: dts: exynosautov9: specify the SPI FIFO depth
ARM: dts: samsung: s5pv210: specify the SPI FIFO depth
arm64: dts: exynos: gs101: move serial_0 pinctrl-0/names to dtsi
arm64: dts: exynos: gs101: move pinctrl-* properties after clocks
arm64: dts: exynos: gs101: join lines close to 80 chars
arm64: dts: exynos: gs101: define all PERIC USI nodes
Udipto Goswami (1):
arm64: dts: qcom: sm8450: Update SNPS Phy parameters for QRD platform
Udit Kumar (4):
arm64: dts: ti: k3-j784s4-evm: Fix UART pin type and macro type
arm64: dts: ti: k3-am69-sk: Fix UART pin type and macro type
arm64: dts: ti: k3-j721s2: Add main esm address range
arm64: dts: ti: k3-j784s4: Add main esm address range
Umang Chheda (1):
arm64: dts: qcom: qcm6490-idp: Name the regulators
Uwe Kleine-König (51):
ARM: dts: bcm2711-rpi: Add pinctrl-based multiplexing for I2C0
ARM: dts: bcm2711-rpi-cm4-io: Add RTC on I2C0
ARM: dts: imx51-ts4800: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx53-m53evk: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx53-ppd: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx53-kp: Drop redundant settings in pwm nodes
ARM: dts: imx53-tqma: Use #pwm-cells = <3> for imx27-pwm devices
ARM: dts: imx6dl-aristainetos_4: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6dl-aristainetos_7: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6dl-mamoj: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-ba16: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-bosch-acc: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-apf6dev: Use #pwm-cells = <3> for imx27-pwm devices
ARM: dts: imx6qdl-aristainetos2: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-cubox-i: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-emcon: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-gw52xx: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-gw53xx: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-gw54xx: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-gw560x: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-gw5903: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-gw5904: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-icore: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-nit6xlite: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-nitrogen6_max: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-nitrogen6_som2: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-nitrogen6x: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-phytec-mira: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-sabreauto: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-sabrelite: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-sabresd: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-savageboard: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-skov-cpu: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-kp: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-novena: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-pistachio: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-prti6q: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-var-dt6customboard: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sl-evk: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sll-evk: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sx-nitrogen6sx: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sx-sdb: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sx-softing-vining-2000: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-14x14-evk: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-ccimx6ulsbcpro: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-geam: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-imx6ull-opos6uldev: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-isiot: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-kontron-bl-43: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-kontron-bl-common: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-pico: Use #pwm-cells = <3> for imx27-pwm device
Vignesh Raghavendra (1):
arm64: dts: ti: k3-am62a: Enable UHS mode support for SD cards
Vitor Soares (1):
arm64: dts: freescale: verdin-imx8mp: enable Verdin I2C_3_HDMI interface
Volodymyr Babchuk (1):
arm64: dts: qcom: sa8155p-adp: lower min volt for L13C regulator
Wadim Mueller (2):
dt-bindings: arm: fsl: add NXP S32G3 board
arm64: dts: S32G3: Introduce device tree for S32G-VNP-RDB3
Wei Fang (1):
arm64: dts: imx93-11x11-evk: add reset gpios for ethernet PHYs
Xu Yang (7):
dt-bindings: usb: usbmisc-imx: add fsl,imx8ulp-usbmisc compatible
ARM: dts: imx6: remove fsl,anatop property from usb controller node
arm64: dts: imx8ulp: add usb nodes
arm64: dts: imx8ulp-evk: enable usb nodes and add ptn5150 nodes
arm64: dts: imx93: add usb nodes
arm64: dts: imx93-11x11-evk: enable usb and typec nodes
arm64: dts: imx8mm/n remove clock-names property from usb controller node
Yang Xiwen (3):
arm64: dts: hi3798cv200: fix the size of GICR
arm64: dts: hi3798cv200: add GICH, GICV register space and irq
arm64: dts: hi3798cv200: add cache info
Zev Weiss (1):
ARM: dts: aspeed: Add vendor prefixes to lm25066 compat strings
0.1% Documentation/devicetree/bindings/arm/bcm/
0.0% Documentation/devicetree/bindings/arm/keystone/
0.5% Documentation/devicetree/bindings/arm/
0.2% Documentation/devicetree/bindings/clock/
0.0% Documentation/devicetree/bindings/display/panel/
0.0% Documentation/devicetree/bindings/display/tegra/
0.1% Documentation/devicetree/bindings/gpio/
0.0% Documentation/devicetree/bindings/media/
0.0% Documentation/devicetree/bindings/soc/qcom/
0.2% Documentation/devicetree/bindings/soc/renesas/
0.0% Documentation/devicetree/bindings/soc/samsung/
0.0% Documentation/devicetree/bindings/usb/
0.0% Documentation/devicetree/bindings/
1.2% arch/arm/boot/dts/allwinner/
0.0% arch/arm/boot/dts/aspeed/
1.3% arch/arm/boot/dts/broadcom/
0.2% arch/arm/boot/dts/nvidia/
5.5% arch/arm/boot/dts/nxp/imx/
9.4% arch/arm/boot/dts/qcom/
3.0% arch/arm/boot/dts/renesas/
0.1% arch/arm/boot/dts/samsung/
14.8% arch/arm/boot/dts/st/
0.0% arch/arm/boot/dts/ti/keystone/
1.3% arch/arm/boot/dts/ti/omap/
0.0% arch/arm64/boot/dts/actions/
2.1% arch/arm64/boot/dts/allwinner/
0.0% arch/arm64/boot/dts/altera/
0.1% arch/arm64/boot/dts/amazon/
0.0% arch/arm64/boot/dts/amd/
0.1% arch/arm64/boot/dts/apm/
0.0% arch/arm64/boot/dts/arm/
0.0% arch/arm64/boot/dts/broadcom/bcmbca/
0.0% arch/arm64/boot/dts/broadcom/northstar2/
0.0% arch/arm64/boot/dts/broadcom/stingray/
0.1% arch/arm64/boot/dts/cavium/
4.5% arch/arm64/boot/dts/exynos/google/
0.1% arch/arm64/boot/dts/exynos/
11.9% arch/arm64/boot/dts/freescale/
0.8% arch/arm64/boot/dts/hisilicon/
0.0% arch/arm64/boot/dts/intel/
0.0% arch/arm64/boot/dts/lg/
0.5% arch/arm64/boot/dts/marvell/
0.0% arch/arm64/boot/dts/mediatek/
0.4% arch/arm64/boot/dts/microchip/
0.0% arch/arm64/boot/dts/nuvoton/
0.1% arch/arm64/boot/dts/nvidia/
9.8% arch/arm64/boot/dts/qcom/
0.0% arch/arm64/boot/dts/realtek/
3.3% arch/arm64/boot/dts/renesas/
18.9% arch/arm64/boot/dts/rockchip/
0.0% arch/arm64/boot/dts/socionext/
0.3% arch/arm64/boot/dts/sprd/
2.1% arch/arm64/boot/dts/st/
0.0% arch/arm64/boot/dts/synaptics/
0.0% arch/arm64/boot/dts/tesla/
3.1% arch/arm64/boot/dts/ti/
0.0% arch/arm64/boot/dts/xilinx/
0.4% arch/riscv/boot/dts/renesas/
0.6% arch/riscv/boot/dts/sophgo/
0.0% drivers/firmware/
0.8% include/dt-bindings/clock/
565 files changed, 23914 insertions(+), 5102 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt
create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
create mode 100644 arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-614-plus.dts
create mode 100644 arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts
create mode 100644 arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-emmc.dts
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-nand.dts
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts
create mode 100644 arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts
create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi
create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-kltechn.dts
create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi
create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-leo.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dx.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
create mode 100644 arch/arm64/boot/dts/freescale/s32g3.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
create mode 100644 arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso
create mode 100644 arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-mecsbc.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-gpio-fan.dtso
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^ permalink raw reply [relevance 3%]
* [GIT PULL 1/4] soc: devicetree updates for 6.10, part 1
@ 2024-05-10 21:11 3% ` Arnd Bergmann
0 siblings, 0 replies; 200+ results
From: Arnd Bergmann @ 2024-05-10 21:11 UTC (permalink / raw)
To: Linus Torvalds; +Cc: soc, linux-kernel, linux-arm-kernel
The following changes since commit fec50db7033ea478773b159e0e2efb135270e3b7:
Linux 6.9-rc3 (2024-04-07 13:22:46 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git tags/soc-dt-6.10
for you to fetch changes up to 0cb7e0c617c6aa3da46514ee5982bd7de11a2b2e:
Merge tag 'qcom-arm64-for-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt (2024-05-08 09:06:06 +0200)
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soc: devicetree updates for 6.10, part 1
The updates this time are a bit smaller than most times, mainly because
it is not totally dominated by new Qualcomm hardware support. Instead,
we larger than average updates for Rockchips, NXP, Allwinner and TI.
The only two new SoCs this time are both from NXP and are minor variants
of already supported ones.
The updates for aspeed, amlogic and mediatek came a little late, so
I'm saving those for part 2 in a few days if everything turns out fine.
New machines this time contain:
- two Broadcom SoC based wireless routers from Asus
- Five allwinner based consumer devices for gaming, set-top-box and
eboot reader applications
- Three older phones based on Qualcomm chips, plus the more recent
Sony Xperia 1 V
- 14 industrial and embedded boards based on NXP i.MX6, i.MX8,
layerscape and s32g3 SoCs
- six rockchips boards including another handheld game console
and a few single-board computers
On top of these, we have the usual cleanups for dtc warnings and
updates to add more features to already merged machines.
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Abel Vesa (7):
arm64: dts: qcom: x1e80100: Add SPMI support
arm64: dts: qcom: x1e80100: Add dedicated pmic dtsi
arm64: dts: qcom: x1e80100-crd: Add repeater nodes
arm64: dts: qcom: x1e80100-qcp: Add repeater nodes
arm64: dts: qcom: x1e80100: Drop the link-frequencies from mdss_dp3_in
arm64: dts: qcom: x1e80100-crd: Add data-lanes and link-frequencies to DP3
arm64: dts: qcom: x1e80100-qcp: Add data-lanes and link-frequencies to DP3
Akhil R (1):
arm64: tegra: Add Tegra Security Engine DT nodes
Alain Volmat (6):
arm64: dts: st: add all 8 i2c nodes on stm32mp251
arm64: dts: st: add i2c2/i2c8 pins for stm32mp25
arm64: dts: st: add i2c2 / i2c8 properties on stm32mp257f-ev1
arm64: dts: st: add all 8 spi nodes on stm32mp251
arm64: dts: st: add spi3/spi8 pins for stm32mp25
arm64: dts: st: add spi3 / spi8 properties on stm32mp257f-ev1
Alexander Stein (8):
arm64: dts: imx8mm: Add empty DSI output endpoint
arm64: dts: imx8mn: Add empty DSI output endpoint
arm64: dts: imx8mq: Add empty DSI output endpoint
arm64: dts: imx8mp: Add empty DSI output endpoint
arm64: dts: mba8mx: Simplify DSI connection
ARM: dts: imx6qdl: mba6: Add missing vdd-supply for on-board USB hub
ARM: dts: imx6qdl: Remove LCD.CONTRAST pinctrl from muxing
arm64: dts: imx8mp: Enable HDMI on TQMa8MPxL/MBa8MPxL
Alexandre Torgue (1):
ARM: dts: stm32: put ETZPC as an access controller for STM32MP13x boards
Alice Guo (1):
arm64: dts: imx8dxl: add lpuart device in cm40 subsystem
Anand Moon (2):
arm64: dts: rockchip: Support poweroff on Edgeble Neural Compute Module
arm64: dts: rockchip: Add USB3 on Edgeble NCM6A-IO board
Andre Przywara (3):
arm64: dts: allwinner: h616: Fix I2C0 pins
dt-bindings: arm: sunxi: document Tanix TX1 name
arm64: dts: allwinner: Add Tanix TX1 support
Andreas Kemnade (2):
ARM: dts: imx6sl: tolino-shine2hd: fix IRQ config of touchscreen
ARM: dts: imx6: fix IRQ config of RC5T619
Andrejs Cainikovs (1):
arm64: dts: ti: verdin-am62: dahlia: fix audio clock
Andrew Davis (14):
ARM: dts: ti: keystone: k2g: Remove ti,system-reboot-controller property
dt-bindings: arm: keystone: Remove ti,system-reboot-controller property
arm64: dts: ti: k3-am65: Remove UART baud rate selection
arm64: dts: ti: k3-am64: Remove UART baud rate selection
arm64: dts: ti: k3-j7200: Remove UART baud rate selection
arm64: dts: ti: k3-j721e: Remove UART baud rate selection
arm64: dts: ti: k3-j721s2: Remove UART baud rate selection
arm64: dts: ti: k3-j784s4: Remove UART baud rate selection
arm64: dts: ti: k3-am65: Add full compatible to SerDes control nodes
arm64: dts: ti: k3-am65: Move SerDes mux nodes under the control node
arm64: dts: ti: k3-am65: Use exact ranges for FSS node
arm64: dts: ti: k3-j7200: Use exact ranges for FSS node
arm64: dts: ti: k3-j721e: Use exact ranges for FSS node
arm64: dts: ti: k3-j784s4: Use exact ranges for FSS node
André Draszik (9):
arm64: dts: exynos: gs101: reorder pinctrl-* properties
dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit
arm64: dts: exynos: gs101: enable cmu-hsi0 clock controller
arm64: dts: exynos: gs101: add USB & USB-phy nodes
arm64: dts: exynos: gs101-oriole: enable USB on this board
arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) alive
arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01]
arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2
arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl
Andy Yan (2):
arm64: dts: rockchip: Enable gpu on Cool Pi CM5
arm64: dts: rockchip: Enable gpu on Cool Pi 4B
Anton Bambura (5):
arm64: dts: qcom: sc8180x-lenovo-flex-5g: fix GPU firmware path
arm64: dts: qcom: sc8180x-lenovo-flex-5g: set names for i2c hid nodes
arm64: dts: qcom: sc8180x-lenovo-flex-5g: move pinctrl to appropriate nodes
arm64: dts: qcom: sc8180x-lenovo-flex-5g: set touchpad i2c frequency to 1 MHz
arm64: dts: qcom: sc8180x-lenovo-flex-5g: Allow UFS regulators load/mode setting
Aren Moynihan (1):
arm64: dts: allwinner: pinephone: add multicolor LED node
Arnd Bergmann (31):
Merge tag 'renesas-dt-bindings-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Merge tag 'renesas-dts-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Merge tag 'omap-for-v6.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt
Merge tag 'samsung-dt-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Merge tag 'samsung-dt64-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Merge tag 'hisi-arm64-dt-for-6.10' of https://github.com/hisilicon/linux-hisi into soc/dt
Merge tag 'stm32-dt-for-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
Merge tag 'v6.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
Merge tag 'renesas-dts-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Merge tag 'sunxi-dt-for-6.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
Merge tag 'tegra-for-6.10-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
Merge tag 'tegra-for-6.10-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
Merge tag 'tegra-for-6.10-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
Merge tag 'sunxi-dt-for-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
Merge tag 'qcom-arm32-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Merge tag 'qcom-arm64-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Merge tag 'imx-bindings-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
Merge tag 'imx-dt-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
Merge tag 'imx-dt64-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
Merge tag 'dt64-cleanup-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
Merge tag 'dt-cleanup-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
Merge tag 'microchip-dt64-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
Merge tag 'arm-soc/for-6.10/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
Merge tag 'arm-soc/for-6.10/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
Merge tag 'riscv-sophgo-dt-for-v6.10' of https://github.com/sophgo/linux into soc/dt
Merge tag 'ti-keystone-dt-for-v6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
Merge tag 'ti-k3-dt-for-v6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
Merge tag 'mvebu-dt64-6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
Merge tag 'v6.10-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
Merge tag 'samsung-dt64-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Merge tag 'qcom-arm64-for-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Arthur Demchenkov (1):
ARM: dts: n900: set charge current limit to 950mA
Artur Weber (1):
ARM: dts: exynos4212-tab3: limit usable memory range
Arınç ÜNAL (9):
ARM: dts: BCM5301X: use color and function on ASUS RT-AC3100 and RT-AC88U
ARM: dts: BCM5301X: provide address for SoC MACs on ASUS RT-AC3100 & AC88U
ARM: dts: BCM5301X: remove duplicate compatible on ASUS RT-AC3100 & AC88U
ARM: dts: BCM5301X: remove earlycon on ASUS RT-AC3100 and ASUS RT-AC88U
dt-bindings: arm: bcm: add bindings for ASUS RT-AC3200
dt-bindings: arm: bcm: add bindings for ASUS RT-AC5300
ARM: dts: BCM5301X: Add DT for ASUS RT-AC3200
ARM: dts: BCM5301X: Add DT for ASUS RT-AC5300
ARM: dts: BCM5301X: Conform to DTS Coding Style on ASUS RT-AC3100 & AC88U
Bhavya Kapoor (2):
arm64: dts: ti: k3-j721s2-main: Enable support for SDR104 speed mode
arm64: dts: ti: k3-j722s-evm: Enable UHS support for MMCSD
Biju Das (1):
arm64: dts: renesas: rzg2ul-smarc: Enable PMIC and built-in RTC, GPIO and ONKEY
Bjorn Andersson (9):
arm64: dts: qcom: qcs6490-rb3gen2: Name the regulators
Merge branch 'arm64-for-6.10' onto 'v6.9-rc1'
Merge branch 'arm32-for-6.10' onto 'v6.9-rc1'
arm64: dts: qcom: sc7280: Enable MDP turbo mode
arm64: dts: qcom: qcs6490-rb3gen2: Add DP output
arm64: dts: qcom: qcs6490-rb3gen2: Enable adsp and cdsp
arm64: dts: qcom: qcs6490-rb3gen2: Introduce USB redriver
arm64: dts: qcom: qcs6490-rb3gen2: Enable USB Type-C display
arm64: dts: qcom: qcs6490-rb3gen2: Enable UFS
Boris Brezillon (3):
arm64: dts: rockchip: Add rk3588 GPU node
arm64: dts: rockchip: Enable GPU on rk3588-rock5b
arm64: dts: rockchip: Enable GPU on rk3588-evb1
Brandon Brnich (1):
arm64: dts: ti: k3-am62a-main: Add Wave5 Video Encoder/Decoder Node
Caleb Connolly (1):
arm64: dts: qcom: sdm845-db845c: make pcie0_3p3v_dual always-on
Carlos Song (1):
arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery
Chris Morgan (9):
arm64: dts: rockchip: Add additional properties for WiFi on Anbernic rgxx3
arm64: dts: rockchip: Add optional node for chasis-type on Anbernic rgxx3
arm64: dts: rockchip: Correct model name for Anbernic RGxx3 Devices
arm64: dts: rockchip: Add chasis-type for Powkiddy rk3566 devices
arm64: dts: rockchip: Correct model name for Powkiddy RK3566 Devices
dt-bindings: arm: rockchip: Add GameForce Chi
arm64: dts: rockchip: Add GameForce Chi
arm64: dts: rockchip: Add USB-C Support for rk3588s-indiedroid-nova
arm64: dts: allwinner: h616: Add NMI device node
Christian Marangi (1):
ARM: dts: qcom: ipq4019: add QCA8075 PHY Package nodes
Chukun Pan (5):
dt-bindings: arm: rockchip: correct the model name for Radxa ROCK 3A
arm64: dts: rockchip: correct the model name for Radxa ROCK 3A
dt-bindings: arm: rockchip: add Radxa ROCK 3C
arm64: dts: rockchip: Add Radxa ROCK 3C
arm64: dts: rockchip: enable onboard spi flash for rock-3a
Claudiu Beznea (1):
arm64: dts: renesas: rzg3s-smarc-som: Fix Ethernet aliases
Connor Abbott (1):
arm64: dts: qcom: sm8650: Fix GPU cx_mem size
Danila Tikhonov (3):
arm64: dts: qcom: pm6150: define USB-C related blocks
arm64: dts: qcom: sc7180: Fix UFS PHY clocks
arm64: dts: qcom: pm6150l: add Light Pulse Generator device node
Dario Binacchi (1):
ARM: dts: stm32: move can3 node from stm32f746 to stm32f769
Dasnavis Sabiya (1):
arm64: dts: ti: k3-j784s4-main: Enable support for UHS mode
David Heidelberg (2):
ARM: dts: qcom: include cpu in idle-state node names
ARM: dts: qcom: msm8916: idle-state compatible require the generic idle-state
David Jander (1):
arm64: dts: rockchip: add Protonic MECSBC device-tree
Denis Burkov (2):
dt-bindings: arm: sunxi: Add PocketBook 614 Plus
ARM: dts: sun5i: Add PocketBook 614 Plus support
Diederik de Haas (1):
arm64: dts: rockchip: Fix ordering of nodes on rk3588s
Dmitry Baryshkov (15):
arm64: dts: qcom: qrb2210-rb1: enable USB-C port handling
arm64: dts: qcom: sc8180x: drop legacy property #stream-id-cells
arm64: dts: qcom: sc8180x: Drop flags for mdss irqs
arm64: dts: qcom: sc8180x: add dp_p1 register blocks to DP nodes
arm64: dts: qcom: sm8350: Add interconnects to UFS
dt-bindings: arm: qcom: drop dtbTool-specific compatibles
arm64: dts: qcom: msm8916: drop dtbTool-specific compatibles
arm64: dts: qcom: sm8150-hdk: enable WiFI support
dt-bindings: soc: qcom: pmic-glink: allow orientation-gpios
arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO
arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO
arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs
arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs
arm64: dts: qcom: qrb2210-rb1: add firmware-name qualifier to WiFi node
arm64: dts: qcom: qrb4210-rb1: add firmware-name qualifier to WiFi node
Dmitry Yashin (3):
dt-bindings: arm: rockchip: add Forlinx FET3588-C
arm64: dts: rockchip: add Forlinx FET3588-C
arm64: dts: rockchip: add Forlinx OK3588-C
Dong Aisheng (1):
arm64: dts: imx8: add cm40 subsystem dtsi
Dragan Simic (7):
arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3328
arm64: dts: rockchip: Add cache information to the SoC dtsi for RK356x
arm64: dts: rockchip: Enable the GPU on quartzpro64
dt-bindings: arm: rockchip: Correct the descriptions for Radxa boards
arm64: dts: rockchip: Correct the model names for Radxa ROCK 5 boards
dt-bindings: arm: rockchip: Correct the descriptions for Pine64 boards
arm64: dts: rockchip: Correct the model names for Pine64 boards
Duy Nguyen (1):
arm64: dts: renesas: r8a779h0: Add thermal nodes
Elliot Berman (1):
arm64: dts: qcom: sm8650: Add missing reserved memory for chipinfo
Fabio Estevam (8):
ARM: dts: imx7s: Add snvs-poweroff support
ARM: dts: imx6qdl-udoo: Enable USB host
arm64: dts: imx8m/qxp: Pass the tcpci compatible
arm64: dts: imx8mn-evk: Fix ADV7535 dt-schema warnings
arm64: dts: imx8mn-evk: Describe the OV5640 supplies
arm64: dts: imx8mm-evk: Describe the OV5640 supplies
arm64: dts: imx8mp-debix-som-a-bmb-08: Remove 'phy-supply' from eqos
arm64: dts: imx8-ss-img: Remove JPEG clock-names
Florian Fainelli (1):
arm: dts: bcm2711: Describe Ethernet LEDs
Folker Schwesinger (2):
arm64: dts: rockchip: Add enable-strobe-pulldown to emmc phy on ROCK Pi 4
arm64: dts: rockchip: Add enable-strobe-pulldown to emmc phy on ROCK 4C+
Francesco Dolcini (3):
arm64: dts: ti: verdin-am62: use SD1 CD as GPIO
arm64: dts: ti: verdin-am62: mallow: fix GPIOs pinctrl
arm64: dts: ti: k3-am625-verdin: add PCIe reset gpio hog
Frank Li (10):
arm64: dts: imx8qm-mek: add adc0 support
arm64: dts: imx8qm-mek: add lpspi2 support
arm64: dts: imx8qm-mek: add flexspi0 support
arm64: dts: imx8: fix audio lpcg index
arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5]
arm64: dts: imx8dxl: update cm40 irq number information
arm64: dts: imx8dxl-evk: add lpuart1 and cm40 uart
ARM: dts: nxp: imx6sx: fix esai related warning when do dtb_check
ARM: dts: nxp: imx6qdl: fix esai clock warning when do dtb_check
arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960 and sai[0,1,4,5]
Frank Oltmanns (1):
arm64: dts: allwinner: a64: Run GPU at 432 MHz
Gabriel Fernandez (1):
arm64: dts: st: add rcc support for STM32MP25
Garrett Giordano (2):
arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Add Audio Codec
arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Add USB-C
Gatien Chevallier (4):
arm64: dts: st: add RIFSC as an access controller for STM32MP25x boards
ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
ARM: dts: stm32: put ETZPC as an access controller for STM32MP15x boards
ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
Geert Uytterhoeven (11):
ARM: dts: renesas: r8a73a4: Add TMU nodes
ARM: dts: renesas: rzg1: Add TMU nodes
ARM: dts: renesas: rcar-gen2: Add TMU nodes
arm64: dts: renesas: r8a779h0: Add remaining HSCIF nodes
arm64: dts: renesas: r8a779h0: Add SCIF nodes
arm64: dts: renesas: gray-hawk-single: Add second debug serial port
ARM: dts: renesas: r9a06g032: Remove duplicate interrupt-parent
arm64: dts: renesas: gray-hawk-single: Enable nfsroot
arm64: dts: renesas: s4sk: Fix ethernet0 alias
arm64: dts: renesas: r8a779h0: Add INTC-EX node
arm64: dts: renesas: r8a779h0: Link IOMMU consumers
Ghennadi Procopciuc (2):
arm64: dts: s32g: add SCMI firmware node
arm64: dts: s32g: add uSDHC node
Gilles Talis (3):
dt-bindings: vendor-prefixes: Add Emcraft Systems
dt-bindings: arm: Add Emcraft Systems i.MX8M Plus NavQ+ Kit
arm64: dts: freescale: Add device tree for Emcraft Systems NavQ+ Kit
Haibo Chen (1):
arm64: dts: imx93: assign usdhc[1..3] root clock to 400MHz
Heiko Stuebner (8):
arm64: dts: rockchip: enable gpu on rk3588-jaguar
arm64: dts: rockchip: enable gpu on rk3588-tiger
arm64: dts: rockchip: move uart2 pinmux to dtsi on rk3588-tiger
arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar
arm64: dts: rockchip: fix pcie-refclk frequency on rk3588 tiger
arm64: dts: rockchip: fix comment for upper usb3 port
arm64: dts: rockchip: add usb-id extcon on rk3588 tiger
arm64: dts: rockchip: add dual-role usb3 hosts to rk3588 Tiger-Haikou
Hiago De Franco (5):
arm64: dts: freescale: Add i.MX8DX dtsi
arm64: dts: freescale: Add Toradex Colibri iMX8DX
dt-bindings: arm: fsl: remove reduntant toradex,colibri-imx8x
dt-bindings: arm: fsl: Add Colibri iMX8DX
arm64: dts: freescale: imx8m[mp]-verdin: Update audio card name
Hugues Fruchet (1):
media: dt-bindings: add access-controllers to STM32MP25 video codecs
Hui Liu (1):
arm64: dts: qcom: qcm6490-idp: enable PMIC Volume and Power buttons
Ian Ray (2):
arm64: dts: imx8mp-msc-sm2s: correct i2c{1..6} pad drive strength
arm64: dts: imx8mp-msc-sm2s: Add i2c{1,6} sda-/scl-gpios
Inochi Amaoto (6):
riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC
riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC
riscv: dts: sophgo: cv18xx: Add spi devices
riscv: dts: sophgo: cv18xx: Add i2c devices
riscv: dts: sophgo: use real clock for sdhci
riscv: dts: sophgo: add reserved memory node for CV1800B
Jacopo Mondi (1):
arm64: dts: debix-a: Disable i2c2 in base .dts
Jai Luthra (1):
arm64: dts: ti: Fix csi2-dual-imx219 dtb names
Jan Kiszka (1):
arm64: dts: ti: iot2050: Add icssg-prueth nodes for PG1 devices
Jean-Michel Hautbois (1):
ARM: dts: bcm2835: Add Unicam CSI nodes
Jianfeng Liu (3):
dt-bindings: vendor-prefixes: add ArmSoM
dt-bindings: arm: rockchip: Add ArmSoM Sige7
arm64: dts: rockchip: Add ArmSom Sige7 board
Jianhua Lu (2):
arm64: dts: qcom: sm8250-xiaomi-elish: add usb pd negotiation support
arm64: dts: qcom: sm8250-xiaomi-elish: set pm8150b_vbus regulator-min-microamp and regulator-max-microamp
Jimmy Hon (2):
arm64: dts: rockchip: Enable GPU on Orange Pi 5
arm64: dts: rockchip: add USB-C support to rk3588s-orangepi-5
Jing Luo (1):
arm64: dts: rockchip: correct gpio_pwrctrl1 typos on rk3588(s) boards
Jisheng Zhang (1):
riscv: dts: sophgo: add sdcard support for milkv duo
Joe Mason (1):
arm64: dts: qcom: msm8916-samsung-fortuna: Add touchscreen
Johan Hovold (4):
arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
arm64: dts: qcom: sc8280xp: enable GICv3 ITS for PCIe
arm64: dts: qcom: sc8280xp-x13s: enable USB MP and fingerprint reader
arm64: dts: qcom: qcs404: fix bluetooth device address
Josua Mayer (2):
arm64: dts: fsl-lx2162a-som: add description for rtc
arm64: dts: fsl-lx2162a-clearfog: add alias for i2c bus iic6
Joy Zou (2):
arm64: dts: imx93-11x11-evk: add pca9451a support
arm64: dts: imx93-11x11-evk: add RTC PCF2131 support
Judith Mendez (2):
arm64: dts: ti: k3-am65-main: Fix sdhci node properties
arm64: dts: ti: k3-am65-main: Remove unused properties in sdhci nodes
Komal Bajaj (2):
arm64: dts: qcom: qcm6490-idp: Enable various remoteprocs
arm64: dts: qcom: qcs6490-rb3gen2: Enable various remoteprocs
Konrad Dybcio (12):
arm64: dts: qcom: sc8280xp: Add missing LMH interrupts
arm64: dts: qcom: sc8280xp: Add QFPROM node
arm64: dts: qcom: sc8280xp: Add PS_HOLD restart
arm64: dts: qcom: sc8280xp: Describe TCSR download mode register
arm64: dts: qcom: msm8998-yoshino: Enable RGB led
dt-bindings: arm: qcom: Add Xperia 1 V
arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherent
arm64: dts: qcom: sm8550: Mark APPS SMMU as dma-coherent
arm64: dts: qcom: sm8550: Add missing DWC3 quirks
arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent
arm64: dts: qcom: Add SM8550 Xperia 1 V
arm64: dts: qcom: sc8280xp: Fill in EAS properties
Krishna Kurapati (2):
arm64: dts: qcom: sc8280xp: Add missing hs_phy_irq in USB nodes
arm64: dts: qcom: sc8280xp: Add USB DWC3 Multiport controller
Krzysztof Kozlowski (76):
arm64: dts: qcom: x1e80100: correct SWR1 pack mode
arm64: dts: qcom: x1e80100-crd: switch WSA8845 speakers to shared reset-gpio
ARM: dts: samsung: smdkv310: fix keypad no-autorepeat
ARM: dts: samsung: exynos4412-origen: fix keypad no-autorepeat
ARM: dts: samsung: smdk4412: fix keypad no-autorepeat
ARM: dts: samsung: smdk4412: align keypad node names with dtschema
ARM: dts: samsung: exynos5800-peach-pi: switch to undeprecated DP HPD GPIOs
ARM: dts: samsung: s5pv210: align onenand node name with bindings
ARM: dts: samsung: s5pv210: correct onenand size-cells
arm64: dts: juno: fix thermal zone node names
arm64: dts: amd: use capital "OR" for multiple licenses in SPDX
arm64: dts: qcom: pm6150: correct Type-C compatible
arm64: dts: marvell: ap80x: fix IOMMU unit address
arm64: dts: marvell: cn9130-db: drop unneeded flash address/size-cells
arm64: dts: marvell: cn9131-db: drop unneeded flash address/size-cells
arm64: dts: marvell: cn9130-db: drop wrong unit-addresses
arm64: dts: marvell: cn9130-crb: drop wrong unit-addresses
arm64: dts: marvell: cn9130-crb: drop unneeded "status"
arm64: dts: sprd: minor whitespace cleanup
arm64: dts: qcom: apq8016-sbc: correct GPIO LEDs node names
arm64: dts: microchip: sparx5: fix mdio reg
arm64: dts: microchip: sparx5: correct serdes unit address
arm64: dts: microchip: sparx5_pcb134: add missing I2C mux unit addresses
arm64: dts: microchip: sparx5_pcb135: add missing I2C mux unit addresses
arm64: dts: microchip: sparx5_pcb134: align I2C mux node name with bindings
arm64: dts: microchip: sparx5_pcb135: align I2C mux node name with bindings
arm64: dts: microchip: sparx5_pcb134: drop LED unit addresses
arm64: dts: microchip: sparx5_pcb135: drop LED unit addresses
arm64: dts: microchip: sparx5_pcb134: drop duplicated NOR flash
arm64: dts: microchip: sparx5_pcb135: drop duplicated NOR flash
arm64: dts: ti: k3-am62p5-sk: minor whitespace cleanup
ARM: dts: ti: omap: minor whitespace cleanup
arm64: dts: hisilicon: hip05: move non-MMIO node out of soc
arm64: dts: hisilicon: hip05-d02: correct local-bus unit addresses
arm64: dts: hisilicon: hip06: move non-MMIO node out of soc
arm64: dts: hisilicon: hip06: correct unit addresses
arm64: dts: allwinner: Pine H64: correctly remove reg_gmac_3v3
arm64: dts: allwinner: drop underscore in node names
arm64: dts: allwinner: Orange Pi: delete node by phandle
arm: dts: allwinner: drop underscore in node names
arm64: dts: hisilicon: hip07: move non-MMIO node out of soc
arm64: dts: hisilicon: hip07: correct unit addresses
arm64: dts: hisilicon: hi6220-hikey: add missing port@0 reg
arm64: dts: hisilicon: hi6220-hikey: drop unit addresses from fixed regulators
arm64: dts: hisilicon: hi6220: correct tsensor unit addresses
arm64: dts: qcom: sdx75: add unit address to soc node
arm64: dts: imx8mm-var-som-symphony: drop redundant status from typec
arm64: dts: imx8mn-var-som-symphony: drop redundant status from typec
arm64: dts: sc9860: add missing aon-prediv unit address
arm64: dts: sc9860: move GPIO keys to board
arm64: dts: sc9860: move GIC to soc node
arm64: dts: whale2: add missing ap-apb unit address
arm64: dts: sharkl3: add missing unit addresses
arm64: dts: uniphier: ld11-global: use generic node name for audio-codec
arm64: dts: uniphier: ld11-global: drop audio codec port unit address
arm64: dts: uniphier: ld20-global: use generic node name for audio-codec
arm64: dts: uniphier: ld20-global: drop audio codec port unit address
arm64: dts: realtek: rtd129x: add missing unit address to soc node
arm64: dts: realtek: rtd139x: add missing unit address to soc node
arm64: dts: realtek: rtc16xx: add missing unit address to soc node
arm64: dts: cavium: move non-MMIO node out of soc
arm64: dts: cavium: correct unit addresses
arm64: dts: apm: storm: move non-MMIO node out of soc
arm64: dts: apm: shadowcat: move non-MMIO node out of soc
arm64: dts: amazon: alpine-v2: add missing io-fabric unit addresses
arm64: dts: amazon: alpine-v2: move non-MMIO node out of soc
arm64: dts: amazon: alpine-v3: add missing io-fabric unit addresses
arm64: dts: amazon: alpine-v3: drop cache nodes unit addresses
arm64: dts: amazon: alpine-v3: correct gic unit addresses
arm64: dts: cavium: thunder2-99xx: drop redundant reg-names
arm64: tegra: Correct Tegra132 I2C alias
Merge branch 'for-v6.10/clk-gs101-bindings' into next/dt64
arm64: dts: qcom: pm6150: correct USB VBUS regulator compatible
arm64: dts: marvell: eDPU: drop redundant address/size-cells
arm64: dts: marvell: turris-mox: drop unneeded flash address/size-cells
arm64: dts: marvell: espressobin-ultra: fix Ethernet Switch unit address
Lad Prabhakar (7):
ARM: dts: renesas: r7s72100: Add interrupt-names to SCIF nodes
dt-bindings: soc: renesas: Document Renesas RZ/V2H(P) SoC variants
dt-bindings: arm: renesas: Document Renesas RZ/V2H(P) System Controller
riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI
arm64: dts: renesas: r9a07g043: Move interrupt-parent property to common DTSI
riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt properties from ETH0/1 nodes
arm64: dts: renesas: rzg3s-smarc-som: Enable eMMC by default
Laurent Pinchart (5):
dt-bindings: arm: bcm: raspberrypi,bcm2835-firmware: Add gpio child node
firmware: raspberrypi: Use correct device for DMA mappings
ARM: dts: bcm283x: Drop unneeded properties in the bcm2835-firmware node
ARM: dts: bcm2835-rpi: Move duplicate firmware-clocks to bcm2835-rpi.dtsi
ARM: dts: bcm2711-rpi-4-b: Add CAM1 regulator
Ling Xu (1):
arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodes
Loic Poulain (1):
arm64: dts: qcom: qcm2290: Add LMH node
Luca Ceresoli (2):
arm64: dts: rockchip: add i2s_8ch_2 and i2s_8ch_3 to rk3308
arm64: dts: rockchip: add the internal audio codec on rk3308
Luca Weiss (16):
arm64: dts: qcom: sm6350: Add Crypto Engine
arm64: dts: qcom: sdm632-fairphone-fp3: enable USB-C port handling
ARM: dts: qcom: msm8974pro-castor: Clean up formatting
ARM: dts: qcom: msm8974pro-castor: Add mmc aliases
ARM: dts: qcom: msm8974pro-castor: Remove camera button definitions
ARM: dts: qcom: msm8974pro-castor: Add debounce-interval for keys
ARM: dts: qcom: msm8974pro-castor: Rename wifi node name
ARM: dts: qcom: msm8974-sony-castor: Split into shinano-common
ARM: dts: qcom: Add Sony Xperia Z3 smartphone
arm64: dts: qcom: sc7280: Add inline crypto engine
dt-bindings: arm: qcom: Add Sony Xperia Z3
ARM: dts: qcom: msm8974: Add @0 to memory node name
ARM: dts: qcom: msm8974: Add empty chosen node
ARM: dts: qcom: msm8974-sony-shinano: Enable vibrator
arm64: dts: qcom: qcm6490-fairphone-fp5: Add USB-C orientation GPIO
arm64: dts: qcom: sm6350: Add DisplayPort controller
Lucas Stach (3):
arm64: dts: imx8mp: add HDMI power-domains
arm64: dts: imx8mp: add HDMI irqsteer
arm64: dts: imx8mp: add HDMI display pipeline
Luke Wang (1):
arm64: dts: imx93-11x11-evk: add different usdhc pinctrl for different timing usage
Manivannan Sadhasivam (20):
ARM: dts: qcom: ipq8064: Add PCIe bridge node
ARM: dts: qcom: ipq4019: Add PCIe bridge node
ARM: dts: qcom: apq8064: Add PCIe bridge node
ARM: dts: qcom: sdx55: Add PCIe bridge node
arm64: dts: qcom: sm8250: Add PCIe bridge node
arm64: dts: qcom: sdm845: Add PCIe bridge node
arm64: dts: qcom: sm8150: Add PCIe bridge node
arm64: dts: qcom: sm8350: Add PCIe bridge node
arm64: dts: qcom: sm8450: Add PCIe bridge node
arm64: dts: qcom: sm8550: Add PCIe bridge node
arm64: dts: qcom: sm8650: Add PCIe bridge node
arm64: dts: qcom: sa8775p: Add PCIe bridge node
arm64: dts: qcom: sc8280xp: Add PCIe bridge node
arm64: dts: qcom: msm8998: Add PCIe bridge node
arm64: dts: qcom: sc7280: Add PCIe bridge node
arm64: dts: qcom: qcs404: Add PCIe bridge node
arm64: dts: qcom: sc8180x: Add PCIe bridge node
arm64: dts: qcom: msm8996: Add PCIe bridge node
arm64: dts: qcom: ipq8074: Add PCIe bridge node
arm64: dts: qcom: ipq6018: Add PCIe bridge node
Marek Vasut (3):
arm64: dts: imx8mp: Describe CSI2 GPIO expander on i.MX8MP DHCOM PDK3 board
arm64: dts: imx8mp: Align both CSI2 pixel clock
ARM: dts: stm32: add PWR regulators support on stm32mp131
Markus Schneider-Pargmann (1):
arm64: dts: ti: k3-am62-lp-sk: Remove tps65219 power-button
Max Krummenacher (1):
arm64: dts: ti: verdin-am62: Set memory size to 2gb
Michael Grzeschik (1):
ARM: dts: imx27-phytec: Add USB support
Michael Riesch (4):
dt-bindings: add wolfvision vendor prefix
dt-bindings: arm: rockchip: add wolfvision pf5 mainboard
arm64: dts: rockchip: add wolfvision pf5 mainboard
arm64: dts: rockchip: add wolfvision pf5 io expander board
Michael Walle (3):
arm64: dts: ti: k3-{am62p,j722s}: Disable ethernet by default
arm64: dts: ti: k3-j722s-evm: Enable eMMC support
arm64: dts: ls1028a: sl28: split variant 3/ads2 carrier
Miles Alan (1):
arm64: dts: allwinner: pinephone: Retain LEDs state in suspend
Mohammad Shehar Yaar Tausif (1):
ARM: tegra: tegra20-ac97: Replace deprecated "gpio" suffix
Muhammed Efe Cetin (10):
arm64: dts: rockchip: Add cpu regulators and vcc5v0_sys to Khadas Edge 2
arm64: dts: rockchip: Add PMIC to Khadas Edge 2
arm64: dts: rockchip: Add TF card to Khadas Edge 2
arm64: dts: rockchip: USB2, USB3 Host, PCIe2 to Khadas Edge 2
arm64: dts: rockchip: Add ir receiver and leds to Khadas Edge 2
arm64: dts: rockchip: Add saradc and adc buttons to Khadas Edge 2 and enable tsadc
arm64: dts: rockchip: Add SFC to Khadas Edge 2
arm64: dts: rockchip: Add UART9 (bluetooth) to Khadas Edge 2
arm64: dts: rockchip: Add RTC to Khadas Edge 2
arm64: dts: rockchip: enable GPU on khadas-edge2
Nathan Morrisson (4):
arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Increase CAN max bitrate
arm64: dts: ti: k3-am642-phyboard-electra-rdk: Increase CAN max bitrate
arm64: dts: ti: am64-phyboard-electra: Add overlay to enable a GPIO fan
arm64: dts: ti: Enable overlays for the am625-phyboard-lyra
Neil Armstrong (7):
arm64: dts: qcom: sm8450: add missing qcom,non-secure-domain property
arm64: dts: qcom: sm8550: add missing qcom,non-secure-domain property
arm64: dts: qcom: sm8650: add missing qcom,non-secure-domain property
arm64: dts: qcom: sm8650: fix usb interrupts properties
arm64: dts: qcom: sm8650: remove useless enablement of mdss_mdp
arm64: dts: qcom: sm8650: add GPU nodes
arm64: dts: qcom: sm8650-qrd: enable GPU
Nicolas Chauvet (1):
ARM: tegra: paz00: Add emc-tables for ram-code 1
Niklas Cassel (1):
arm64: dts: rockchip: add rk3588 pcie and php IOMMUs
Niklas Söderlund (1):
arm64: dts: renesas: eagle: Add capture overlay for Function expansion board
Pankaj Gupta (1):
arm64: dts: imx8ulp: add caam jr
Parthiban Nallathambi (2):
ARM: dts: imx6ull: add seeed studio NPi dev board
dt-bindings: arm: fsl: Add Seeed studio NPi based boards
Patrice Chotard (1):
ARM: dts: stm32: add heartbeat led for stm32mp157c-ed1
Patrick Delaunay (1):
arm64: dts: st: correct masks for GIC PPI interrupts on stm32mp25
Paweł Owoc (2):
arm64: dts: qcom: ipq8074: Add QUP UART6 node
arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins
Peng Fan (9):
arm64: dts: imx93: drop the 4th interrupt for ADC
arm64: dts: imx93: use FSL_EDMA_RX for rx channel
arm64: dts: imx93: add dma support for lpi2c[1..8]
arm64: dts: imx93: add dma support for lpspi[1..8]
arm64: dts: imx93: add nvmem property for fec1
arm64: dts: imx93: add nvmem property for eqos
arm64: dts: imx93-11x11-evk: update resource table address
arm64: dts: imx93-11x11-evk: add sleep pinctrl for eqos and fec
arm64: dts: imx93-11x11-evk: add sleep pinctrl for sdhc2
Peter Griffin (6):
dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller
dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible
arm64: dts: exynos: gs101: Add the hsi2 sysreg node
arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes
arm64: dts: exynos: gs101: enable ufs, phy on oriole & define ufs regulator
Rafał Miłecki (1):
arm64: dts: broadcom: bcmbca: bcm4908: set brcm,wp-not-connected
Raphael Gallais-Pou (4):
dt-bindings: display: simple: allow panel-common properties
ARM: dts: stm32: add LTDC support for STM32MP13x SoC family
ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family
ARM: dts: stm32: enable display support on stm32mp135f-dk board
Raymond Hackley (1):
arm64: dts: qcom: msm8916/39-samsung-a2015: Add connector for MUIC
Richard Acayan (1):
arm64: dts: qcom: sdm670-google-sargo: add panel
Ritesh Kumar (1):
arm64: dts: qcom: qcm6490-idp: add display and panel
Rob Herring (2):
arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usage
arm64: dts: Add/fix /memory node unit-addresses
Rob Herring (Arm) (2):
arm64: dts: freescale: ls1028a: Fix embedded PCI interrupt mapping
arm64: dts: freescale: ls1028a: Add standard PCI device compatible strings to ENETC
Roger Quadros (5):
arm64: dts: ti: k3-am62*: Add PHY2 region to USB wrapper node
arm64: dts: ti: k3-am62/a: use sub-node for USB_PHY_CTRL registers
arm64: dts: ti: k3-am62p: add the USB sub-system
arm64: dts: ti: k3-am62a: Disable USB LPM
arm64: dts: ti: k3-am625-beagleplay: Fix Ethernet PHY RESET GPIOs
Rong Zhang (4):
dt-bindings: arm: qcom: Add Samsung Galaxy S5 China (kltechn)
ARM: dts: qcom: msm8974: Split out common part of samsung-klte
ARM: dts: qcom: msm8974-klte-common: Pin WiFi board type
ARM: dts: qcom: msm8974: Add DTS for Samsung Galaxy S5 China (kltechn)
Ryan Walklin (4):
dt-bindings: arm: sunxi: document Anbernic RG35XX handheld gaming device variants
arm64: dts: allwinner: h700: Add RG35XX 2024 DTS
arm64: dts: allwinner: h700: Add RG35XX-Plus DTS
arm64: dts: allwinner: h700: Add RG35XX-H DTS
Sam Protsenko (1):
arm64: dts: exynos850: Add CPU clocks
Sascha Hauer (1):
dt-bindings: arm: rockchip: Add Protonic MECSBC board
Sebastian Raase (2):
arm64: dts: qcom: sdm630-nile: add pinctrl for camera key
arm64: dts: qcom: msm8998-yoshino: fix volume-up key
Sebastian Reichel (8):
ARM: dts: imx: Add UNI-T UTi260B thermal camera board
arm64: dts: rockchip: fix usb2phy nodename for rk3588
arm64: dts: rockchip: reorder usb2phy properties for rk3588
arm64: dts: rockchip: add USBDP phys on rk3588
arm64: dts: rockchip: add USB3 DRD controllers on rk3588
arm64: dts: rockchip: add USB3 to rk3588-evb1
arm64: dts: rockchip: add upper USB3 port to rock-5a
arm64: dts: rockchip: add lower USB3 port to rock-5b
Shengjiu Wang (5):
arm64: dts: imx8mp: Add AUD2HTX device node
arm64: dts: imx8mp-evk: Add HDMI audio sound card support
arm64: dts: imx8mp-evk: Add PDM micphone sound card support
ARM: dts: imx6sx-nitrogen6sx: drop incorrect cpu-dai property
ARM: dts: imx6: exchange fallback and specific compatible string
Siddharth Manthan (1):
arm64: dts: qcom: msm8916-samsung-fortuna: Add PWM backlight
Stanislav Jakubek (2):
dt-bindings: arm: qcom: Add Motorola Moto G (2013)
ARM: dts: qcom: Add support for Motorola Moto G (2013)
Stefan Eichenberger (6):
arm64: dts: freescale: imx8mp-verdin: replace sleep-moci hog with regulator
arm64: dts: freescale: imx8mp-verdin-dahlia: support sleep-moci
arm64: dts: freescale: imx8mm-verdin: replace sleep-moci hog with regulator
arm64: dts: freescale: imx8mm-verdin-dahlia: support sleep-moci
arm64: dts: ti: k3-am62-verdin: replace sleep-moci hog with regulator
arm64: dts: ti: k3-am62-verdin-dahlia: support sleep-moci
Stefan Wahren (1):
ARM: dts: imx6ull-tarragon: Reduce SPI clock for QCA7000
Stephen Boyd (2):
arm64: dts: qcom: sc7180: Disable pmic pinctrl node on Trogdor
arm64: dts: qcom: sc7180: Disable DCC node by default
Sukrut Bellary (1):
arm64: dts: ti: k3-am625-beagleplay: Use mmc-pwrseq for wl18xx enable
Thanh Le (1):
arm64: dts: renesas: r8a779h0: Add IPMMU nodes
Thanh Quan (3):
arm64: dts: renesas: r8a779h0: Add CMT nodes
arm64: dts: renesas: r8a779h0: Add TMU nodes
arm64: dts: renesas: r8a779h0: Add MSIOF nodes
Thierry Reding (1):
dt-bindings: display: tegra: Allow dma-coherent on Tegra194 and later
Tim Harvey (5):
arm64: dts: imx8mp-venice-gw74xx-imx219.dtso: fix dt warning
arm64: dts: imx8mp-venice-gw74xx: add ADC rail for VDD_1P0
arm64: dts: imx8mp-venice-gw72xx: add mac addr for eth1
arm64: dts: imx8mp-venice-gw73xx: add mac addr for eth1
arm64: dts: imx8m*-venice-gw7: Fix TPM schema violations
Tony Lindgren (12):
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB
ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0
Tudor Ambarus (11):
ARM: dts: samsung: exynos3250: specify the SPI FIFO depth
ARM: dts: samsung: exynos4: specify the SPI FIFO depth
ARM: dts: samsung: exynos5250: specify the SPI FIFO depth
ARM: dts: samsung: exynos5420: specify the SPI FIFO depth
arm64: dts: exynos5433: specify the SPI FIFO depth
arm64: dts: exynosautov9: specify the SPI FIFO depth
ARM: dts: samsung: s5pv210: specify the SPI FIFO depth
arm64: dts: exynos: gs101: move serial_0 pinctrl-0/names to dtsi
arm64: dts: exynos: gs101: move pinctrl-* properties after clocks
arm64: dts: exynos: gs101: join lines close to 80 chars
arm64: dts: exynos: gs101: define all PERIC USI nodes
Udipto Goswami (1):
arm64: dts: qcom: sm8450: Update SNPS Phy parameters for QRD platform
Udit Kumar (4):
arm64: dts: ti: k3-j784s4-evm: Fix UART pin type and macro type
arm64: dts: ti: k3-am69-sk: Fix UART pin type and macro type
arm64: dts: ti: k3-j721s2: Add main esm address range
arm64: dts: ti: k3-j784s4: Add main esm address range
Umang Chheda (1):
arm64: dts: qcom: qcm6490-idp: Name the regulators
Uwe Kleine-König (51):
ARM: dts: bcm2711-rpi: Add pinctrl-based multiplexing for I2C0
ARM: dts: bcm2711-rpi-cm4-io: Add RTC on I2C0
ARM: dts: imx51-ts4800: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx53-m53evk: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx53-ppd: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx53-kp: Drop redundant settings in pwm nodes
ARM: dts: imx53-tqma: Use #pwm-cells = <3> for imx27-pwm devices
ARM: dts: imx6dl-aristainetos_4: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6dl-aristainetos_7: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6dl-mamoj: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-ba16: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-bosch-acc: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-apf6dev: Use #pwm-cells = <3> for imx27-pwm devices
ARM: dts: imx6qdl-aristainetos2: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-cubox-i: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-emcon: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-gw52xx: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-gw53xx: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-gw54xx: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-gw560x: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-gw5903: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-gw5904: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-icore: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-nit6xlite: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-nitrogen6_max: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-nitrogen6_som2: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-nitrogen6x: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-phytec-mira: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-sabreauto: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-sabrelite: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-sabresd: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-savageboard: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6qdl-skov-cpu: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-kp: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-novena: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-pistachio: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-prti6q: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6q-var-dt6customboard: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sl-evk: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sll-evk: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sx-nitrogen6sx: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sx-sdb: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6sx-softing-vining-2000: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-14x14-evk: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-ccimx6ulsbcpro: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-geam: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-imx6ull-opos6uldev: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-isiot: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-kontron-bl-43: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-kontron-bl-common: Use #pwm-cells = <3> for imx27-pwm device
ARM: dts: imx6ul-pico: Use #pwm-cells = <3> for imx27-pwm device
Vignesh Raghavendra (1):
arm64: dts: ti: k3-am62a: Enable UHS mode support for SD cards
Vitor Soares (1):
arm64: dts: freescale: verdin-imx8mp: enable Verdin I2C_3_HDMI interface
Volodymyr Babchuk (1):
arm64: dts: qcom: sa8155p-adp: lower min volt for L13C regulator
Wadim Mueller (2):
dt-bindings: arm: fsl: add NXP S32G3 board
arm64: dts: S32G3: Introduce device tree for S32G-VNP-RDB3
Wei Fang (1):
arm64: dts: imx93-11x11-evk: add reset gpios for ethernet PHYs
Xu Yang (7):
dt-bindings: usb: usbmisc-imx: add fsl,imx8ulp-usbmisc compatible
ARM: dts: imx6: remove fsl,anatop property from usb controller node
arm64: dts: imx8ulp: add usb nodes
arm64: dts: imx8ulp-evk: enable usb nodes and add ptn5150 nodes
arm64: dts: imx93: add usb nodes
arm64: dts: imx93-11x11-evk: enable usb and typec nodes
arm64: dts: imx8mm/n remove clock-names property from usb controller node
Yang Xiwen (3):
arm64: dts: hi3798cv200: fix the size of GICR
arm64: dts: hi3798cv200: add GICH, GICV register space and irq
arm64: dts: hi3798cv200: add cache info
Zev Weiss (1):
ARM: dts: aspeed: Add vendor prefixes to lm25066 compat strings
0.1% Documentation/devicetree/bindings/arm/bcm/
0.0% Documentation/devicetree/bindings/arm/keystone/
0.5% Documentation/devicetree/bindings/arm/
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0.0% drivers/firmware/
0.8% include/dt-bindings/clock/
565 files changed, 23914 insertions(+), 5102 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt
create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
create mode 100644 arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-614-plus.dts
create mode 100644 arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts
create mode 100644 arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-emmc.dts
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-nand.dts
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts
create mode 100644 arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts
create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi
create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-kltechn.dts
create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi
create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-leo.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8dx.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
create mode 100644 arch/arm64/boot/dts/freescale/s32g3.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
create mode 100644 arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso
create mode 100644 arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-mecsbc.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi
create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-gpio-fan.dtso
^ permalink raw reply [relevance 3%]
* [PATCH 2/2] ASoC: codec: lpass-rx-macro: add suppor for 2.6 codec version
@ 2024-05-10 17:58 1% ` srinivas.kandagatla
0 siblings, 0 replies; 200+ results
From: srinivas.kandagatla @ 2024-05-10 17:58 UTC (permalink / raw)
To: broonie
Cc: perex, tiwai, alsa-devel, lgirdwood, linux-kernel,
krzysztof.kozlowski, neil.armstrong, Srinivas Kandagatla
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
LPASS Codec v2.6 has significant changes in the rx register offsets.
Due to this headset playback on SM8550, SM8650, x1e80100 and all SoCs
after SM8450 have only Left working.
This patch adjusts the registers to accomdate 2.6 changes. With this
fixed now L and R are functional on Headset playback.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
sound/soc/codecs/lpass-rx-macro.c | 565 ++++++++++++++++++++++--------
1 file changed, 410 insertions(+), 155 deletions(-)
diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-macro.c
index f35187d69cac..c1724f0830e9 100644
--- a/sound/soc/codecs/lpass-rx-macro.c
+++ b/sound/soc/codecs/lpass-rx-macro.c
@@ -158,7 +158,7 @@
#define CDC_RX_INTR_CTRL_LEVEL0 (0x03C0)
#define CDC_RX_INTR_CTRL_BYPASS0 (0x03C8)
#define CDC_RX_INTR_CTRL_SET0 (0x03D0)
-#define CDC_RX_RXn_RX_PATH_CTL(n) (0x0400 + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_CTL(rx, n) (0x0400 + rx->rxn_reg_offset * n)
#define CDC_RX_RX0_RX_PATH_CTL (0x0400)
#define CDC_RX_PATH_RESET_EN_MASK BIT(6)
#define CDC_RX_PATH_CLK_EN_MASK BIT(5)
@@ -166,45 +166,47 @@
#define CDC_RX_PATH_PGA_MUTE_MASK BIT(4)
#define CDC_RX_PATH_PGA_MUTE_ENABLE BIT(4)
#define CDC_RX_PATH_PCM_RATE_MASK GENMASK(3, 0)
-#define CDC_RX_RXn_RX_PATH_CFG0(n) (0x0404 + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_CFG0(rx, n) (0x0404 + rx->rxn_reg_offset * n)
#define CDC_RX_RXn_COMP_EN_MASK BIT(1)
#define CDC_RX_RX0_RX_PATH_CFG0 (0x0404)
#define CDC_RX_RXn_CLSH_EN_MASK BIT(6)
#define CDC_RX_DLY_ZN_EN_MASK BIT(3)
#define CDC_RX_DLY_ZN_ENABLE BIT(3)
#define CDC_RX_RXn_HD2_EN_MASK BIT(2)
-#define CDC_RX_RXn_RX_PATH_CFG1(n) (0x0408 + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_CFG1(rx, n) (0x0408 + rx->rxn_reg_offset * n)
#define CDC_RX_RXn_SIDETONE_EN_MASK BIT(4)
#define CDC_RX_RX0_RX_PATH_CFG1 (0x0408)
#define CDC_RX_RX0_HPH_L_EAR_SEL_MASK BIT(1)
-#define CDC_RX_RXn_RX_PATH_CFG2(n) (0x040C + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_CFG2(rx, n) (0x040C + rx->rxn_reg_offset * n)
#define CDC_RX_RXn_HPF_CUT_FREQ_MASK GENMASK(1, 0)
#define CDC_RX_RX0_RX_PATH_CFG2 (0x040C)
-#define CDC_RX_RXn_RX_PATH_CFG3(n) (0x0410 + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_CFG3(rx, n) (0x0410 + rx->rxn_reg_offset * n)
#define CDC_RX_RX0_RX_PATH_CFG3 (0x0410)
#define CDC_RX_DC_COEFF_SEL_MASK GENMASK(1, 0)
#define CDC_RX_DC_COEFF_SEL_TWO 0x2
-#define CDC_RX_RXn_RX_VOL_CTL(n) (0x0414 + 0x80 * n)
+#define CDC_RX_RXn_RX_VOL_CTL(rx, n) (0x0414 + rx->rxn_reg_offset * n)
#define CDC_RX_RX0_RX_VOL_CTL (0x0414)
-#define CDC_RX_RXn_RX_PATH_MIX_CTL(n) (0x0418 + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n) (0x0418 + rx->rxn_reg_offset * n)
#define CDC_RX_RXn_MIX_PCM_RATE_MASK GENMASK(3, 0)
#define CDC_RX_RXn_MIX_RESET_MASK BIT(6)
#define CDC_RX_RXn_MIX_RESET BIT(6)
#define CDC_RX_RXn_MIX_CLK_EN_MASK BIT(5)
#define CDC_RX_RX0_RX_PATH_MIX_CTL (0x0418)
#define CDC_RX_RX0_RX_PATH_MIX_CFG (0x041C)
-#define CDC_RX_RXn_RX_VOL_MIX_CTL(n) (0x0420 + 0x80 * n)
+#define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n) (0x0420 + rx->rxn_reg_offset * n)
#define CDC_RX_RX0_RX_VOL_MIX_CTL (0x0420)
#define CDC_RX_RX0_RX_PATH_SEC1 (0x0424)
#define CDC_RX_RX0_RX_PATH_SEC2 (0x0428)
#define CDC_RX_RX0_RX_PATH_SEC3 (0x042C)
+#define CDC_RX_RXn_RX_PATH_SEC3(rx, n) (0x042c + rx->rxn_reg_offset * n)
#define CDC_RX_RX0_RX_PATH_SEC4 (0x0430)
#define CDC_RX_RX0_RX_PATH_SEC7 (0x0434)
+#define CDC_RX_RXn_RX_PATH_SEC7(rx, n) (0x0434 + rx->rxn_reg_offset * n)
#define CDC_RX_DSM_OUT_DELAY_SEL_MASK GENMASK(2, 0)
#define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE 0x2
#define CDC_RX_RX0_RX_PATH_MIX_SEC0 (0x0438)
#define CDC_RX_RX0_RX_PATH_MIX_SEC1 (0x043C)
-#define CDC_RX_RXn_RX_PATH_DSM_CTL(n) (0x0440 + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_DSM_CTL(rx, n) (0x0440 + rx->rxn_reg_offset * n)
#define CDC_RX_RXn_DSM_CLK_EN_MASK BIT(0)
#define CDC_RX_RX0_RX_PATH_DSM_CTL (0x0440)
#define CDC_RX_RX0_RX_PATH_DSM_DATA1 (0x0444)
@@ -213,6 +215,7 @@
#define CDC_RX_RX0_RX_PATH_DSM_DATA4 (0x0450)
#define CDC_RX_RX0_RX_PATH_DSM_DATA5 (0x0454)
#define CDC_RX_RX0_RX_PATH_DSM_DATA6 (0x0458)
+/* RX offsets prior to 2.6 codec version */
#define CDC_RX_RX1_RX_PATH_CTL (0x0480)
#define CDC_RX_RX1_RX_PATH_CFG0 (0x0484)
#define CDC_RX_RX1_RX_PATH_CFG1 (0x0488)
@@ -259,10 +262,58 @@
#define CDC_RX_RX2_RX_PATH_MIX_SEC0 (0x0544)
#define CDC_RX_RX2_RX_PATH_MIX_SEC1 (0x0548)
#define CDC_RX_RX2_RX_PATH_DSM_CTL (0x054C)
+
+/* LPASS CODEC version 2.6 rx reg offsets */
+#define CDC_2_6_RX_RX1_RX_PATH_CTL (0x04c0)
+#define CDC_2_6_RX_RX1_RX_PATH_CFG0 (0x04c4)
+#define CDC_2_6_RX_RX1_RX_PATH_CFG1 (0x04c8)
+#define CDC_2_6_RX_RX1_RX_PATH_CFG2 (0x04cC)
+#define CDC_2_6_RX_RX1_RX_PATH_CFG3 (0x04d0)
+#define CDC_2_6_RX_RX1_RX_VOL_CTL (0x04d4)
+#define CDC_2_6_RX_RX1_RX_PATH_MIX_CTL (0x04d8)
+#define CDC_2_6_RX_RX1_RX_PATH_MIX_CFG (0x04dC)
+#define CDC_2_6_RX_RX1_RX_VOL_MIX_CTL (0x04e0)
+#define CDC_2_6_RX_RX1_RX_PATH_SEC1 (0x04e4)
+#define CDC_2_6_RX_RX1_RX_PATH_SEC2 (0x04e8)
+#define CDC_2_6_RX_RX1_RX_PATH_SEC3 (0x04eC)
+#define CDC_2_6_RX_RX1_RX_PATH_SEC4 (0x04f0)
+#define CDC_2_6_RX_RX1_RX_PATH_SEC7 (0x04f4)
+#define CDC_2_6_RX_RX1_RX_PATH_MIX_SEC0 (0x04f8)
+#define CDC_2_6_RX_RX1_RX_PATH_MIX_SEC1 (0x04fC)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_CTL (0x0500)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_DATA1 (0x0504)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_DATA2 (0x0508)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_DATA3 (0x050C)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_DATA4 (0x0510)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_DATA5 (0x0514)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_DATA6 (0x0518)
+
+#define CDC_2_6_RX_RX2_RX_PATH_CTL (0x0580)
+#define CDC_2_6_RX_RX2_RX_PATH_CFG0 (0x0584)
+#define CDC_2_6_RX_RX2_RX_PATH_CFG1 (0x0588)
+#define CDC_2_6_RX_RX2_RX_PATH_CFG2 (0x058C)
+#define CDC_2_6_RX_RX2_RX_PATH_CFG3 (0x0590)
+#define CDC_2_6_RX_RX2_RX_VOL_CTL (0x0594)
+#define CDC_2_6_RX_RX2_RX_PATH_MIX_CTL (0x0598)
+#define CDC_2_6_RX_RX2_RX_PATH_MIX_CFG (0x059C)
+#define CDC_2_6_RX_RX2_RX_VOL_MIX_CTL (0x05a0)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC0 (0x05a4)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC1 (0x05a8)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC2 (0x05aC)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC3 (0x05b0)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC4 (0x05b4)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC5 (0x05b8)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC6 (0x05bC)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC7 (0x05c0)
+#define CDC_2_6_RX_RX2_RX_PATH_MIX_SEC0 (0x05c4)
+#define CDC_2_6_RX_RX2_RX_PATH_MIX_SEC1 (0x05c8)
+#define CDC_2_6_RX_RX2_RX_PATH_DSM_CTL (0x05cC)
+
#define CDC_RX_IDLE_DETECT_PATH_CTL (0x0780)
#define CDC_RX_IDLE_DETECT_CFG0 (0x0784)
#define CDC_RX_IDLE_DETECT_CFG1 (0x0788)
#define CDC_RX_IDLE_DETECT_CFG2 (0x078C)
+
#define CDC_RX_IDLE_DETECT_CFG3 (0x0790)
#define CDC_RX_COMPANDERn_CTL0(n) (0x0800 + 0x40 * n)
#define CDC_RX_COMPANDERn_CLK_EN_MASK BIT(0)
@@ -598,6 +649,8 @@ struct rx_macro {
int rx_mclk_users;
int clsh_users;
int rx_mclk_cnt;
+ int codec_version;
+ int rxn_reg_offset;
bool is_ear_mode_on;
bool hph_pwr_mode;
bool hph_hd2_mode;
@@ -755,11 +808,15 @@ static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0,
rx_int1_2_interp_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0,
rx_int2_2_interp_mux_text);
+
static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0,
rx_int_dem_inp_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0,
rx_int_dem_inp_mux_text);
+static SOC_ENUM_SINGLE_DECL(rx_2_6_int1_dem_inp_enum, CDC_2_6_RX_RX1_RX_PATH_CFG1, 0,
+ rx_int_dem_inp_mux_text);
+
static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
@@ -976,49 +1033,6 @@ static const struct reg_default rx_defaults[] = {
{ CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55 },
{ CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55 },
{ CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55 },
- { CDC_RX_RX1_RX_PATH_CTL, 0x04 },
- { CDC_RX_RX1_RX_PATH_CFG0, 0x00 },
- { CDC_RX_RX1_RX_PATH_CFG1, 0x64 },
- { CDC_RX_RX1_RX_PATH_CFG2, 0x8F },
- { CDC_RX_RX1_RX_PATH_CFG3, 0x00 },
- { CDC_RX_RX1_RX_VOL_CTL, 0x00 },
- { CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
- { CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
- { CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
- { CDC_RX_RX1_RX_PATH_SEC1, 0x08 },
- { CDC_RX_RX1_RX_PATH_SEC2, 0x00 },
- { CDC_RX_RX1_RX_PATH_SEC3, 0x00 },
- { CDC_RX_RX1_RX_PATH_SEC4, 0x00 },
- { CDC_RX_RX1_RX_PATH_SEC7, 0x00 },
- { CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
- { CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
- { CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
- { CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
- { CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
- { CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
- { CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
- { CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
- { CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
- { CDC_RX_RX2_RX_PATH_CTL, 0x04 },
- { CDC_RX_RX2_RX_PATH_CFG0, 0x00 },
- { CDC_RX_RX2_RX_PATH_CFG1, 0x64 },
- { CDC_RX_RX2_RX_PATH_CFG2, 0x8F },
- { CDC_RX_RX2_RX_PATH_CFG3, 0x00 },
- { CDC_RX_RX2_RX_VOL_CTL, 0x00 },
- { CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
- { CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
- { CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
- { CDC_RX_RX2_RX_PATH_SEC0, 0x04 },
- { CDC_RX_RX2_RX_PATH_SEC1, 0x08 },
- { CDC_RX_RX2_RX_PATH_SEC2, 0x00 },
- { CDC_RX_RX2_RX_PATH_SEC3, 0x00 },
- { CDC_RX_RX2_RX_PATH_SEC4, 0x00 },
- { CDC_RX_RX2_RX_PATH_SEC5, 0x00 },
- { CDC_RX_RX2_RX_PATH_SEC6, 0x00 },
- { CDC_RX_RX2_RX_PATH_SEC7, 0x00 },
- { CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
- { CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
- { CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
{ CDC_RX_IDLE_DETECT_PATH_CTL, 0x00 },
{ CDC_RX_IDLE_DETECT_CFG0, 0x07 },
{ CDC_RX_IDLE_DETECT_CFG1, 0x3C },
@@ -1121,6 +1135,99 @@ static const struct reg_default rx_defaults[] = {
{ CDC_RX_DSD1_CFG2, 0x96 },
};
+static const struct reg_default rx_2_6_defaults[] = {
+ { CDC_2_6_RX_RX1_RX_PATH_CTL, 0x04 },
+ { CDC_2_6_RX_RX1_RX_PATH_CFG0, 0x00 },
+ { CDC_2_6_RX_RX1_RX_PATH_CFG1, 0x64 },
+ { CDC_2_6_RX_RX1_RX_PATH_CFG2, 0x8F },
+ { CDC_2_6_RX_RX1_RX_PATH_CFG3, 0x00 },
+ { CDC_2_6_RX_RX1_RX_VOL_CTL, 0x00 },
+ { CDC_2_6_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
+ { CDC_2_6_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
+ { CDC_2_6_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
+ { CDC_2_6_RX_RX1_RX_PATH_SEC1, 0x08 },
+ { CDC_2_6_RX_RX1_RX_PATH_SEC2, 0x00 },
+ { CDC_2_6_RX_RX1_RX_PATH_SEC3, 0x00 },
+ { CDC_2_6_RX_RX1_RX_PATH_SEC4, 0x00 },
+ { CDC_2_6_RX_RX1_RX_PATH_SEC7, 0x00 },
+ { CDC_2_6_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
+ { CDC_2_6_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
+ { CDC_2_6_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
+ { CDC_2_6_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
+ { CDC_2_6_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
+ { CDC_2_6_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
+ { CDC_2_6_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
+ { CDC_2_6_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
+ { CDC_2_6_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
+ { CDC_2_6_RX_RX2_RX_PATH_CTL, 0x04 },
+ { CDC_2_6_RX_RX2_RX_PATH_CFG0, 0x00 },
+ { CDC_2_6_RX_RX2_RX_PATH_CFG1, 0x64 },
+ { CDC_2_6_RX_RX2_RX_PATH_CFG2, 0x8F },
+ { CDC_2_6_RX_RX2_RX_PATH_CFG3, 0x00 },
+ { CDC_2_6_RX_RX2_RX_VOL_CTL, 0x00 },
+ { CDC_2_6_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
+ { CDC_2_6_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
+ { CDC_2_6_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
+ { CDC_2_6_RX_RX2_RX_PATH_SEC0, 0x04 },
+ { CDC_2_6_RX_RX2_RX_PATH_SEC1, 0x08 },
+ { CDC_2_6_RX_RX2_RX_PATH_SEC2, 0x00 },
+ { CDC_2_6_RX_RX2_RX_PATH_SEC3, 0x00 },
+ { CDC_2_6_RX_RX2_RX_PATH_SEC4, 0x00 },
+ { CDC_2_6_RX_RX2_RX_PATH_SEC5, 0x00 },
+ { CDC_2_6_RX_RX2_RX_PATH_SEC6, 0x00 },
+ { CDC_2_6_RX_RX2_RX_PATH_SEC7, 0x00 },
+ { CDC_2_6_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
+ { CDC_2_6_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
+ { CDC_2_6_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
+};
+
+static const struct reg_default rx_pre_2_6_defaults[] = {
+ { CDC_RX_RX1_RX_PATH_CTL, 0x04 },
+ { CDC_RX_RX1_RX_PATH_CFG0, 0x00 },
+ { CDC_RX_RX1_RX_PATH_CFG1, 0x64 },
+ { CDC_RX_RX1_RX_PATH_CFG2, 0x8F },
+ { CDC_RX_RX1_RX_PATH_CFG3, 0x00 },
+ { CDC_RX_RX1_RX_VOL_CTL, 0x00 },
+ { CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
+ { CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
+ { CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
+ { CDC_RX_RX1_RX_PATH_SEC1, 0x08 },
+ { CDC_RX_RX1_RX_PATH_SEC2, 0x00 },
+ { CDC_RX_RX1_RX_PATH_SEC3, 0x00 },
+ { CDC_RX_RX1_RX_PATH_SEC4, 0x00 },
+ { CDC_RX_RX1_RX_PATH_SEC7, 0x00 },
+ { CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
+ { CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
+ { CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
+ { CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
+ { CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
+ { CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
+ { CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
+ { CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
+ { CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
+ { CDC_RX_RX2_RX_PATH_CTL, 0x04 },
+ { CDC_RX_RX2_RX_PATH_CFG0, 0x00 },
+ { CDC_RX_RX2_RX_PATH_CFG1, 0x64 },
+ { CDC_RX_RX2_RX_PATH_CFG2, 0x8F },
+ { CDC_RX_RX2_RX_PATH_CFG3, 0x00 },
+ { CDC_RX_RX2_RX_VOL_CTL, 0x00 },
+ { CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
+ { CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
+ { CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
+ { CDC_RX_RX2_RX_PATH_SEC0, 0x04 },
+ { CDC_RX_RX2_RX_PATH_SEC1, 0x08 },
+ { CDC_RX_RX2_RX_PATH_SEC2, 0x00 },
+ { CDC_RX_RX2_RX_PATH_SEC3, 0x00 },
+ { CDC_RX_RX2_RX_PATH_SEC4, 0x00 },
+ { CDC_RX_RX2_RX_PATH_SEC5, 0x00 },
+ { CDC_RX_RX2_RX_PATH_SEC6, 0x00 },
+ { CDC_RX_RX2_RX_PATH_SEC7, 0x00 },
+ { CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
+ { CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
+ { CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
+
+};
+
static bool rx_is_wronly_register(struct device *dev,
unsigned int reg)
{
@@ -1175,8 +1282,114 @@ static bool rx_is_volatile_register(struct device *dev, unsigned int reg)
return false;
}
+static bool rx_2_2_is_rw_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CDC_RX_RX1_RX_PATH_CTL:
+ case CDC_RX_RX1_RX_PATH_CFG0:
+ case CDC_RX_RX1_RX_PATH_CFG1:
+ case CDC_RX_RX1_RX_PATH_CFG2:
+ case CDC_RX_RX1_RX_PATH_CFG3:
+ case CDC_RX_RX1_RX_VOL_CTL:
+ case CDC_RX_RX1_RX_PATH_MIX_CTL:
+ case CDC_RX_RX1_RX_PATH_MIX_CFG:
+ case CDC_RX_RX1_RX_VOL_MIX_CTL:
+ case CDC_RX_RX1_RX_PATH_SEC1:
+ case CDC_RX_RX1_RX_PATH_SEC2:
+ case CDC_RX_RX1_RX_PATH_SEC3:
+ case CDC_RX_RX1_RX_PATH_SEC4:
+ case CDC_RX_RX1_RX_PATH_SEC7:
+ case CDC_RX_RX1_RX_PATH_MIX_SEC0:
+ case CDC_RX_RX1_RX_PATH_MIX_SEC1:
+ case CDC_RX_RX1_RX_PATH_DSM_CTL:
+ case CDC_RX_RX1_RX_PATH_DSM_DATA1:
+ case CDC_RX_RX1_RX_PATH_DSM_DATA2:
+ case CDC_RX_RX1_RX_PATH_DSM_DATA3:
+ case CDC_RX_RX1_RX_PATH_DSM_DATA4:
+ case CDC_RX_RX1_RX_PATH_DSM_DATA5:
+ case CDC_RX_RX1_RX_PATH_DSM_DATA6:
+ case CDC_RX_RX2_RX_PATH_CTL:
+ case CDC_RX_RX2_RX_PATH_CFG0:
+ case CDC_RX_RX2_RX_PATH_CFG1:
+ case CDC_RX_RX2_RX_PATH_CFG2:
+ case CDC_RX_RX2_RX_PATH_CFG3:
+ case CDC_RX_RX2_RX_VOL_CTL:
+ case CDC_RX_RX2_RX_PATH_MIX_CTL:
+ case CDC_RX_RX2_RX_PATH_MIX_CFG:
+ case CDC_RX_RX2_RX_VOL_MIX_CTL:
+ case CDC_RX_RX2_RX_PATH_SEC0:
+ case CDC_RX_RX2_RX_PATH_SEC1:
+ case CDC_RX_RX2_RX_PATH_SEC2:
+ case CDC_RX_RX2_RX_PATH_SEC3:
+ case CDC_RX_RX2_RX_PATH_SEC4:
+ case CDC_RX_RX2_RX_PATH_SEC5:
+ case CDC_RX_RX2_RX_PATH_SEC6:
+ case CDC_RX_RX2_RX_PATH_SEC7:
+ case CDC_RX_RX2_RX_PATH_MIX_SEC0:
+ case CDC_RX_RX2_RX_PATH_MIX_SEC1:
+ case CDC_RX_RX2_RX_PATH_DSM_CTL:
+ return true;
+ }
+
+ return false;
+}
+
+static bool rx_2_6_is_rw_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case CDC_2_6_RX_RX1_RX_PATH_CTL:
+ case CDC_2_6_RX_RX1_RX_PATH_CFG0:
+ case CDC_2_6_RX_RX1_RX_PATH_CFG1:
+ case CDC_2_6_RX_RX1_RX_PATH_CFG2:
+ case CDC_2_6_RX_RX1_RX_PATH_CFG3:
+ case CDC_2_6_RX_RX1_RX_VOL_CTL:
+ case CDC_2_6_RX_RX1_RX_PATH_MIX_CTL:
+ case CDC_2_6_RX_RX1_RX_PATH_MIX_CFG:
+ case CDC_2_6_RX_RX1_RX_VOL_MIX_CTL:
+ case CDC_2_6_RX_RX1_RX_PATH_SEC1:
+ case CDC_2_6_RX_RX1_RX_PATH_SEC2:
+ case CDC_2_6_RX_RX1_RX_PATH_SEC3:
+ case CDC_2_6_RX_RX1_RX_PATH_SEC4:
+ case CDC_2_6_RX_RX1_RX_PATH_SEC7:
+ case CDC_2_6_RX_RX1_RX_PATH_MIX_SEC0:
+ case CDC_2_6_RX_RX1_RX_PATH_MIX_SEC1:
+ case CDC_2_6_RX_RX1_RX_PATH_DSM_CTL:
+ case CDC_2_6_RX_RX1_RX_PATH_DSM_DATA1:
+ case CDC_2_6_RX_RX1_RX_PATH_DSM_DATA2:
+ case CDC_2_6_RX_RX1_RX_PATH_DSM_DATA3:
+ case CDC_2_6_RX_RX1_RX_PATH_DSM_DATA4:
+ case CDC_2_6_RX_RX1_RX_PATH_DSM_DATA5:
+ case CDC_2_6_RX_RX1_RX_PATH_DSM_DATA6:
+ case CDC_2_6_RX_RX2_RX_PATH_CTL:
+ case CDC_2_6_RX_RX2_RX_PATH_CFG0:
+ case CDC_2_6_RX_RX2_RX_PATH_CFG1:
+ case CDC_2_6_RX_RX2_RX_PATH_CFG2:
+ case CDC_2_6_RX_RX2_RX_PATH_CFG3:
+ case CDC_2_6_RX_RX2_RX_VOL_CTL:
+ case CDC_2_6_RX_RX2_RX_PATH_MIX_CTL:
+ case CDC_2_6_RX_RX2_RX_PATH_MIX_CFG:
+ case CDC_2_6_RX_RX2_RX_VOL_MIX_CTL:
+ case CDC_2_6_RX_RX2_RX_PATH_SEC0:
+ case CDC_2_6_RX_RX2_RX_PATH_SEC1:
+ case CDC_2_6_RX_RX2_RX_PATH_SEC2:
+ case CDC_2_6_RX_RX2_RX_PATH_SEC3:
+ case CDC_2_6_RX_RX2_RX_PATH_SEC4:
+ case CDC_2_6_RX_RX2_RX_PATH_SEC5:
+ case CDC_2_6_RX_RX2_RX_PATH_SEC6:
+ case CDC_2_6_RX_RX2_RX_PATH_SEC7:
+ case CDC_2_6_RX_RX2_RX_PATH_MIX_SEC0:
+ case CDC_2_6_RX_RX2_RX_PATH_MIX_SEC1:
+ case CDC_2_6_RX_RX2_RX_PATH_DSM_CTL:
+ return true;
+ }
+
+ return false;
+}
+
static bool rx_is_rw_register(struct device *dev, unsigned int reg)
{
+ struct rx_macro *rx = dev_get_drvdata(dev);
+
switch (reg) {
case CDC_RX_TOP_TOP_CFG0:
case CDC_RX_TOP_SWR_CTRL:
@@ -1306,49 +1519,6 @@ static bool rx_is_rw_register(struct device *dev, unsigned int reg)
case CDC_RX_RX0_RX_PATH_DSM_DATA4:
case CDC_RX_RX0_RX_PATH_DSM_DATA5:
case CDC_RX_RX0_RX_PATH_DSM_DATA6:
- case CDC_RX_RX1_RX_PATH_CTL:
- case CDC_RX_RX1_RX_PATH_CFG0:
- case CDC_RX_RX1_RX_PATH_CFG1:
- case CDC_RX_RX1_RX_PATH_CFG2:
- case CDC_RX_RX1_RX_PATH_CFG3:
- case CDC_RX_RX1_RX_VOL_CTL:
- case CDC_RX_RX1_RX_PATH_MIX_CTL:
- case CDC_RX_RX1_RX_PATH_MIX_CFG:
- case CDC_RX_RX1_RX_VOL_MIX_CTL:
- case CDC_RX_RX1_RX_PATH_SEC1:
- case CDC_RX_RX1_RX_PATH_SEC2:
- case CDC_RX_RX1_RX_PATH_SEC3:
- case CDC_RX_RX1_RX_PATH_SEC4:
- case CDC_RX_RX1_RX_PATH_SEC7:
- case CDC_RX_RX1_RX_PATH_MIX_SEC0:
- case CDC_RX_RX1_RX_PATH_MIX_SEC1:
- case CDC_RX_RX1_RX_PATH_DSM_CTL:
- case CDC_RX_RX1_RX_PATH_DSM_DATA1:
- case CDC_RX_RX1_RX_PATH_DSM_DATA2:
- case CDC_RX_RX1_RX_PATH_DSM_DATA3:
- case CDC_RX_RX1_RX_PATH_DSM_DATA4:
- case CDC_RX_RX1_RX_PATH_DSM_DATA5:
- case CDC_RX_RX1_RX_PATH_DSM_DATA6:
- case CDC_RX_RX2_RX_PATH_CTL:
- case CDC_RX_RX2_RX_PATH_CFG0:
- case CDC_RX_RX2_RX_PATH_CFG1:
- case CDC_RX_RX2_RX_PATH_CFG2:
- case CDC_RX_RX2_RX_PATH_CFG3:
- case CDC_RX_RX2_RX_VOL_CTL:
- case CDC_RX_RX2_RX_PATH_MIX_CTL:
- case CDC_RX_RX2_RX_PATH_MIX_CFG:
- case CDC_RX_RX2_RX_VOL_MIX_CTL:
- case CDC_RX_RX2_RX_PATH_SEC0:
- case CDC_RX_RX2_RX_PATH_SEC1:
- case CDC_RX_RX2_RX_PATH_SEC2:
- case CDC_RX_RX2_RX_PATH_SEC3:
- case CDC_RX_RX2_RX_PATH_SEC4:
- case CDC_RX_RX2_RX_PATH_SEC5:
- case CDC_RX_RX2_RX_PATH_SEC6:
- case CDC_RX_RX2_RX_PATH_SEC7:
- case CDC_RX_RX2_RX_PATH_MIX_SEC0:
- case CDC_RX_RX2_RX_PATH_MIX_SEC1:
- case CDC_RX_RX2_RX_PATH_DSM_CTL:
case CDC_RX_IDLE_DETECT_PATH_CTL:
case CDC_RX_IDLE_DETECT_CFG0:
case CDC_RX_IDLE_DETECT_CFG1:
@@ -1435,7 +1605,10 @@ static bool rx_is_rw_register(struct device *dev, unsigned int reg)
return true;
}
- return false;
+ if (rx->codec_version == LPASS_CODEC_VERSION_2_6)
+ return rx_2_6_is_rw_register(dev, reg);
+
+ return rx_2_2_is_rw_register(dev, reg);
}
static bool rx_is_writeable_register(struct device *dev, unsigned int reg)
@@ -1485,14 +1658,12 @@ static bool rx_is_readable_register(struct device *dev, unsigned int reg)
return rx_is_rw_register(dev, reg);
}
-static const struct regmap_config rx_regmap_config = {
+static struct regmap_config rx_regmap_config = {
.name = "rx_macro",
.reg_bits = 16,
.val_bits = 32, /* 8 but with 32 bit read/write */
.reg_stride = 4,
.cache_type = REGCACHE_FLAT,
- .reg_defaults = rx_defaults,
- .num_reg_defaults = ARRAY_SIZE(rx_defaults),
.max_register = RX_MAX_OFFSET,
.writeable_reg = rx_is_writeable_register,
.volatile_reg = rx_is_volatile_register,
@@ -1504,16 +1675,17 @@ static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol,
{
struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
+ struct rx_macro *rx = snd_soc_component_get_drvdata(component);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned short look_ahead_dly_reg;
unsigned int val;
val = ucontrol->value.enumerated.item[0];
- if (e->reg == CDC_RX_RX0_RX_PATH_CFG1)
- look_ahead_dly_reg = CDC_RX_RX0_RX_PATH_CFG0;
- else if (e->reg == CDC_RX_RX1_RX_PATH_CFG1)
- look_ahead_dly_reg = CDC_RX_RX1_RX_PATH_CFG0;
+ if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 0))
+ look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0);
+ else if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 1))
+ look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1);
/* Set Look Ahead Delay */
if (val)
@@ -1534,6 +1706,10 @@ static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_int1_dem_inp_enum,
snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
+static const struct snd_kcontrol_new rx_2_6_int1_dem_inp_mux =
+ SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_2_6_int1_dem_inp_enum,
+ snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
+
static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
int rate_reg_val, u32 sample_rate)
{
@@ -1567,7 +1743,7 @@ static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
(inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
(inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
- int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(j);
+ int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(rx, j);
/* sample_rate is in Hz */
snd_soc_component_update_bits(component, int_fs_reg,
CDC_RX_PATH_PCM_RATE_MASK,
@@ -1600,7 +1776,7 @@ static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
CDC_RX_INTX_2_SEL_MASK);
if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
- int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
+ int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j);
snd_soc_component_update_bits(component, int_fs_reg,
CDC_RX_RXn_MIX_PCM_RATE_MASK,
rate_reg_val);
@@ -1719,6 +1895,7 @@ static int rx_macro_get_channel_map(struct snd_soc_dai *dai,
static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
{
struct snd_soc_component *component = dai->component;
+ struct rx_macro *rx = snd_soc_component_get_drvdata(component);
uint16_t j, reg, mix_reg, dsm_reg;
u16 int_mux_cfg0, int_mux_cfg1;
u8 int_mux_cfg0_val, int_mux_cfg1_val;
@@ -1729,9 +1906,9 @@ static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
case RX_MACRO_AIF3_PB:
case RX_MACRO_AIF4_PB:
for (j = 0; j < INTERP_MAX; j++) {
- reg = CDC_RX_RXn_RX_PATH_CTL(j);
- mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
- dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(j);
+ reg = CDC_RX_RXn_RX_PATH_CTL(rx, j);
+ mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j);
+ dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, j);
if (mute) {
snd_soc_component_update_bits(component, reg,
@@ -1748,7 +1925,7 @@ static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
}
if (j == INTERP_AUX)
- dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
+ dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, 2);
int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8;
int_mux_cfg1 = int_mux_cfg0 + 4;
@@ -1956,10 +2133,11 @@ static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w,
int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+ struct rx_macro *rx = snd_soc_component_get_drvdata(component);
u16 gain_reg, reg;
- reg = CDC_RX_RXn_RX_PATH_CTL(w->shift);
- gain_reg = CDC_RX_RXn_RX_VOL_CTL(w->shift);
+ reg = CDC_RX_RXn_RX_PATH_CTL(rx, w->shift);
+ gain_reg = CDC_RX_RXn_RX_VOL_CTL(rx, w->shift);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
@@ -1991,7 +2169,7 @@ static int rx_macro_config_compander(struct snd_soc_component *component,
if (comp == INTERP_AUX)
return 0;
- pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(comp)) & 0x0F;
+ pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(rx, comp)) & 0x0F;
if (pcm_rate < 0x06)
val = 0x03;
else if (pcm_rate < 0x08)
@@ -2002,11 +2180,11 @@ static int rx_macro_config_compander(struct snd_soc_component *component,
val = 0x00;
if (SND_SOC_DAPM_EVENT_ON(event))
- snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
+ snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp),
CDC_RX_DC_COEFF_SEL_MASK, val);
if (SND_SOC_DAPM_EVENT_OFF(event))
- snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
+ snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp),
CDC_RX_DC_COEFF_SEL_MASK, 0x3);
if (!rx->comp_enabled[comp])
return 0;
@@ -2019,14 +2197,14 @@ static int rx_macro_config_compander(struct snd_soc_component *component,
CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x1);
snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x0);
- snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
+ snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp),
CDC_RX_RXn_COMP_EN_MASK, 0x1);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
CDC_RX_COMPANDERn_HALT_MASK, 0x1);
- snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
+ snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp),
CDC_RX_RXn_COMP_EN_MASK, 0x0);
snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
CDC_RX_COMPANDERn_CLK_EN_MASK, 0x0);
@@ -2125,13 +2303,13 @@ static int rx_macro_config_aux_hpf(struct snd_soc_component *component,
/* Update Aux HPF control */
if (!rx->is_aux_hpf_on)
snd_soc_component_update_bits(component,
- CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x00);
+ CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x00);
}
if (SND_SOC_DAPM_EVENT_OFF(event)) {
/* Reset to default (HPF=ON) */
snd_soc_component_update_bits(component,
- CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x04);
+ CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x04);
}
return 0;
@@ -2157,7 +2335,6 @@ static int rx_macro_config_classh(struct snd_soc_component *component,
if (!SND_SOC_DAPM_EVENT_ON(event))
return 0;
-
rx_macro_enable_clsh_block(rx, true);
if (interp_n == INTERP_HPHL ||
interp_n == INTERP_HPHR) {
@@ -2183,7 +2360,7 @@ static int rx_macro_config_classh(struct snd_soc_component *component,
CDC_RX_CLSH_DECAY_CTRL,
CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
snd_soc_component_write_field(component,
- CDC_RX_RX0_RX_PATH_CFG0,
+ CDC_RX_RXn_RX_PATH_CFG0(rx, 0),
CDC_RX_RXn_CLSH_EN_MASK, 0x1);
break;
case INTERP_HPHR:
@@ -2199,15 +2376,15 @@ static int rx_macro_config_classh(struct snd_soc_component *component,
CDC_RX_CLSH_DECAY_CTRL,
CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
snd_soc_component_write_field(component,
- CDC_RX_RX1_RX_PATH_CFG0,
+ CDC_RX_RXn_RX_PATH_CFG0(rx, 1),
CDC_RX_RXn_CLSH_EN_MASK, 0x1);
break;
case INTERP_AUX:
snd_soc_component_update_bits(component,
- CDC_RX_RX2_RX_PATH_CFG0,
+ CDC_RX_RXn_RX_PATH_CFG0(rx, 2),
CDC_RX_RX2_DLY_Z_EN_MASK, 1);
snd_soc_component_write_field(component,
- CDC_RX_RX2_RX_PATH_CFG0,
+ CDC_RX_RXn_RX_PATH_CFG0(rx, 2),
CDC_RX_RX2_CLSH_EN_MASK, 1);
break;
}
@@ -2218,16 +2395,17 @@ static int rx_macro_config_classh(struct snd_soc_component *component,
static void rx_macro_hd2_control(struct snd_soc_component *component,
u16 interp_idx, int event)
{
+ struct rx_macro *rx = snd_soc_component_get_drvdata(component);
u16 hd2_scale_reg, hd2_enable_reg;
switch (interp_idx) {
case INTERP_HPHL:
- hd2_scale_reg = CDC_RX_RX0_RX_PATH_SEC3;
- hd2_enable_reg = CDC_RX_RX0_RX_PATH_CFG0;
+ hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 0);
+ hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0);
break;
case INTERP_HPHR:
- hd2_scale_reg = CDC_RX_RX1_RX_PATH_SEC3;
- hd2_enable_reg = CDC_RX_RX1_RX_PATH_CFG0;
+ hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 1);
+ hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1);
break;
}
@@ -2482,7 +2660,7 @@ static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component,
if (interp_idx == INTERP_HPHL) {
if (rx->is_ear_mode_on)
snd_soc_component_write_field(component,
- CDC_RX_RX0_RX_PATH_CFG1,
+ CDC_RX_RXn_RX_PATH_CFG1(rx, 0),
CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x1);
else
snd_soc_component_write_field(component,
@@ -2499,7 +2677,7 @@ static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component,
if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
snd_soc_component_write_field(component,
- CDC_RX_RX0_RX_PATH_CFG1,
+ CDC_RX_RXn_RX_PATH_CFG1(rx, 0),
CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x0);
snd_soc_component_update_bits(component, hph_lut_bypass_reg,
CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 0);
@@ -2516,11 +2694,13 @@ static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
u16 main_reg, dsm_reg, rx_cfg2_reg;
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
- main_reg = CDC_RX_RXn_RX_PATH_CTL(interp_idx);
- dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(interp_idx);
+ main_reg = CDC_RX_RXn_RX_PATH_CTL(rx, interp_idx);
+ dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, interp_idx);
+
if (interp_idx == INTERP_AUX)
- dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
- rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(interp_idx);
+ dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, 2);
+
+ rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(rx, interp_idx);
if (SND_SOC_DAPM_EVENT_ON(event)) {
if (rx->main_clk_users[interp_idx] == 0) {
@@ -2587,10 +2767,11 @@ static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+ struct rx_macro *rx = snd_soc_component_get_drvdata(component);
u16 gain_reg, mix_reg;
- gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(w->shift);
- mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(w->shift);
+ gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(rx, w->shift);
+ mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, w->shift);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
@@ -2621,17 +2802,18 @@ static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+ struct rx_macro *rx = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
rx_macro_enable_interp_clk(component, event, w->shift);
- snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
+ snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift),
CDC_RX_RXn_SIDETONE_EN_MASK, 1);
- snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(w->shift),
+ snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(rx, w->shift),
CDC_RX_PATH_CLK_EN_MASK, 1);
break;
case SND_SOC_DAPM_POST_PMD:
- snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
+ snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift),
CDC_RX_RXn_SIDETONE_EN_MASK, 0);
rx_macro_enable_interp_clk(component, event, w->shift);
break;
@@ -2801,20 +2983,34 @@ static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol,
return 0;
}
-static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
- SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL,
- -84, 40, digital_gain),
+static const struct snd_kcontrol_new rx_macro_def_snd_controls[] = {
SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_RX_RX1_RX_VOL_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_RX_RX2_RX_VOL_CTL,
-84, 40, digital_gain),
- SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL,
- -84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_RX_RX1_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_RX_RX2_RX_VOL_MIX_CTL,
-84, 40, digital_gain),
+};
+
+static const struct snd_kcontrol_new rx_macro_2_6_snd_controls[] = {
+
+ SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_2_6_RX_RX1_RX_VOL_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_2_6_RX_RX2_RX_VOL_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_2_6_RX_RX1_RX_VOL_MIX_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_2_6_RX_RX2_RX_VOL_MIX_CTL,
+ -84, 40, digital_gain),
+};
+static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
+ SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL,
+ -84, 40, digital_gain),
+ SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL,
+ -84, 40, digital_gain),
SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0,
rx_macro_get_compander, rx_macro_set_compander),
SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0,
@@ -2932,6 +3128,16 @@ static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
return 0;
}
+static const struct snd_soc_dapm_widget rx_macro_2_6_dapm_widgets[] = {
+ SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
+ &rx_2_6_int1_dem_inp_mux),
+};
+
+static const struct snd_soc_dapm_widget rx_macro_def_dapm_widgets[] = {
+ SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
+ &rx_int1_dem_inp_mux),
+};
+
static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
SND_SOC_NOPM, 0, 0),
@@ -2948,6 +3154,8 @@ static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
+ &rx_int0_dem_inp_mux),
SND_SOC_DAPM_MUX("RX_MACRO RX0 MUX", SND_SOC_NOPM, RX_MACRO_RX0, 0,
&rx_macro_rx0_mux),
SND_SOC_DAPM_MUX("RX_MACRO RX1 MUX", SND_SOC_NOPM, RX_MACRO_RX1, 0,
@@ -3001,10 +3209,6 @@ static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL,
4, 0, NULL, 0),
- SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
- &rx_int0_dem_inp_mux),
- SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
- &rx_int1_dem_inp_mux),
SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
&rx_int0_2_mux, rx_macro_enable_mix_path,
@@ -3399,32 +3603,53 @@ static const struct snd_soc_dapm_route rx_audio_map[] = {
static int rx_macro_component_probe(struct snd_soc_component *component)
{
+ struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct rx_macro *rx = snd_soc_component_get_drvdata(component);
+ const struct snd_soc_dapm_widget *widgets;
+ const struct snd_kcontrol_new *controls;
+ unsigned int num_controls;
+ int ret, num_widgets;
snd_soc_component_init_regmap(component, rx->regmap);
- snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_SEC7,
+ snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 0),
CDC_RX_DSM_OUT_DELAY_SEL_MASK,
CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
- snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_SEC7,
+ snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 1),
CDC_RX_DSM_OUT_DELAY_SEL_MASK,
CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
- snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_SEC7,
+ snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 2),
CDC_RX_DSM_OUT_DELAY_SEL_MASK,
CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
- snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_CFG3,
+ snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 0),
CDC_RX_DC_COEFF_SEL_MASK,
CDC_RX_DC_COEFF_SEL_TWO);
- snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_CFG3,
+ snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 1),
CDC_RX_DC_COEFF_SEL_MASK,
CDC_RX_DC_COEFF_SEL_TWO);
- snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_CFG3,
+ snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 2),
CDC_RX_DC_COEFF_SEL_MASK,
CDC_RX_DC_COEFF_SEL_TWO);
+ if (rx->codec_version == LPASS_CODEC_VERSION_2_6) {
+ controls = rx_macro_2_6_snd_controls;
+ num_controls = ARRAY_SIZE(rx_macro_2_6_snd_controls);
+ widgets = rx_macro_2_6_dapm_widgets;
+ num_widgets = ARRAY_SIZE(rx_macro_2_6_dapm_widgets);
+ } else {
+ controls = rx_macro_def_snd_controls;
+ num_controls = ARRAY_SIZE(rx_macro_def_snd_controls);
+ widgets = rx_macro_def_dapm_widgets;
+ num_widgets = ARRAY_SIZE(rx_macro_def_dapm_widgets);
+ }
+
rx->component = component;
- return 0;
+ ret = snd_soc_add_component_controls(component, controls, num_controls);
+ if (ret)
+ return ret;
+
+ return snd_soc_dapm_new_controls(dapm, widgets, num_widgets);
}
static int swclk_gate_enable(struct clk_hw *hw)
@@ -3523,11 +3748,12 @@ static const struct snd_soc_component_driver rx_macro_component_drv = {
static int rx_macro_probe(struct platform_device *pdev)
{
+ struct reg_default *reg_defaults;
struct device *dev = &pdev->dev;
kernel_ulong_t flags;
struct rx_macro *rx;
void __iomem *base;
- int ret;
+ int ret, def_count;
flags = (kernel_ulong_t)device_get_match_data(dev);
@@ -3567,6 +3793,33 @@ static int rx_macro_probe(struct platform_device *pdev)
goto err;
}
+ rx->codec_version = lpass_macro_get_codec_version();
+ switch (rx->codec_version) {
+ case LPASS_CODEC_VERSION_2_6:
+ rx->rxn_reg_offset = 0xc0;
+ def_count = ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_2_6_defaults);
+ reg_defaults = kmalloc_array(def_count, sizeof(struct reg_default), GFP_KERNEL);
+ if (!reg_defaults)
+ return -ENOMEM;
+ memcpy(®_defaults[0], rx_defaults, sizeof(rx_defaults));
+ memcpy(®_defaults[ARRAY_SIZE(rx_defaults)],
+ rx_2_6_defaults, sizeof(rx_2_6_defaults));
+ break;
+ default:
+ rx->rxn_reg_offset = 0x80;
+ def_count = ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_pre_2_6_defaults);
+ reg_defaults = kmalloc_array(def_count, sizeof(struct reg_default), GFP_KERNEL);
+ if (!reg_defaults)
+ return -ENOMEM;
+ memcpy(®_defaults[0], rx_defaults, sizeof(rx_defaults));
+ memcpy(®_defaults[ARRAY_SIZE(rx_defaults)],
+ rx_pre_2_6_defaults, sizeof(rx_pre_2_6_defaults));
+ break;
+ }
+
+ rx_regmap_config.reg_defaults = reg_defaults,
+ rx_regmap_config.num_reg_defaults = def_count;
+
rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config);
if (IS_ERR(rx->regmap)) {
ret = PTR_ERR(rx->regmap);
@@ -3629,6 +3882,7 @@ static int rx_macro_probe(struct platform_device *pdev)
if (ret)
goto err_clkout;
+ kfree(reg_defaults);
return 0;
err_clkout:
@@ -3642,6 +3896,7 @@ static int rx_macro_probe(struct platform_device *pdev)
err_dcodec:
clk_disable_unprepare(rx->macro);
err:
+ kfree(reg_defaults);
lpass_macro_pds_exit(rx->pds);
return ret;
--
2.25.1
^ permalink raw reply related [relevance 1%]
* [PATCH] clk: qcom: Constify struct pll_vco
@ 2024-05-10 16:50 7% Christophe JAILLET
0 siblings, 0 replies; 200+ results
From: Christophe JAILLET @ 2024-05-10 16:50 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd
Cc: linux-kernel, kernel-janitors, Christophe JAILLET, linux-arm-msm,
linux-clk
pll_vco structure are never modified. They are used as .vco_table in
"struct clk_alpha_pll".
And in this structure, we have:
const struct pll_vco *vco_table;
Constifying these structures moves some data to a read-only section, so
increase overall security.
On a x86_64, with allmodconfig:
Before:
text data bss dec hex filename
9905 47576 0 57481 e089 drivers/clk/qcom/mmcc-msm8994.o
After:
text data bss dec hex filename
10033 47440 0 57473 e081 drivers/clk/qcom/mmcc-msm8994.o
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
---
Compile tested only.
I hope that it can be applied with this single patch because all files are
in drivers/clk/qcom/.
---
drivers/clk/qcom/camcc-sc8280xp.c | 4 ++--
drivers/clk/qcom/camcc-sm6350.c | 2 +-
drivers/clk/qcom/camcc-sm8250.c | 4 ++--
drivers/clk/qcom/dispcc-sm6125.c | 2 +-
drivers/clk/qcom/dispcc-sm6350.c | 2 +-
drivers/clk/qcom/dispcc-sm6375.c | 2 +-
drivers/clk/qcom/dispcc-sm8450.c | 2 +-
drivers/clk/qcom/dispcc-sm8550.c | 2 +-
drivers/clk/qcom/dispcc-sm8650.c | 2 +-
drivers/clk/qcom/gcc-msm8998.c | 2 +-
drivers/clk/qcom/gcc-sc8180x.c | 2 +-
drivers/clk/qcom/gcc-sm6115.c | 6 +++---
drivers/clk/qcom/gcc-sm6375.c | 4 ++--
drivers/clk/qcom/gpucc-msm8998.c | 2 +-
drivers/clk/qcom/gpucc-sdm660.c | 2 +-
drivers/clk/qcom/gpucc-sm6115.c | 4 ++--
drivers/clk/qcom/gpucc-sm6125.c | 2 +-
drivers/clk/qcom/gpucc-sm6375.c | 2 +-
drivers/clk/qcom/gpucc-sm8250.c | 2 +-
drivers/clk/qcom/gpucc-sm8350.c | 2 +-
drivers/clk/qcom/gpucc-sm8450.c | 2 +-
drivers/clk/qcom/gpucc-sm8650.c | 2 +-
drivers/clk/qcom/lpasscorecc-sc7180.c | 2 +-
drivers/clk/qcom/mmcc-msm8994.c | 4 ++--
drivers/clk/qcom/mmcc-msm8996.c | 6 +++---
drivers/clk/qcom/mmcc-sdm660.c | 4 ++--
drivers/clk/qcom/videocc-sm8150.c | 2 +-
drivers/clk/qcom/videocc-sm8250.c | 2 +-
28 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/clk/qcom/camcc-sc8280xp.c b/drivers/clk/qcom/camcc-sc8280xp.c
index 8e26ec2def73..d8de924a878a 100644
--- a/drivers/clk/qcom/camcc-sc8280xp.c
+++ b/drivers/clk/qcom/camcc-sc8280xp.c
@@ -45,11 +45,11 @@ enum {
P_SLEEP_CLK,
};
-static struct pll_vco lucid_vco[] = {
+static const struct pll_vco lucid_vco[] = {
{ 249600000, 1800000000, 0 },
};
-static struct pll_vco zonda_vco[] = {
+static const struct pll_vco zonda_vco[] = {
{ 595200000, 3600000000, 0 },
};
diff --git a/drivers/clk/qcom/camcc-sm6350.c b/drivers/clk/qcom/camcc-sm6350.c
index e4e7b308ecf1..c6fe684aa780 100644
--- a/drivers/clk/qcom/camcc-sm6350.c
+++ b/drivers/clk/qcom/camcc-sm6350.c
@@ -32,7 +32,7 @@ enum {
P_CAMCC_PLL3_OUT_MAIN,
};
-static struct pll_vco fabia_vco[] = {
+static const struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
};
diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c
index 9b32c56a5bc5..96103eeda586 100644
--- a/drivers/clk/qcom/camcc-sm8250.c
+++ b/drivers/clk/qcom/camcc-sm8250.c
@@ -32,11 +32,11 @@ enum {
P_SLEEP_CLK,
};
-static struct pll_vco lucid_vco[] = {
+static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
-static struct pll_vco zonda_vco[] = {
+static const struct pll_vco zonda_vco[] = {
{ 595200000UL, 3600000000UL, 0 },
};
diff --git a/drivers/clk/qcom/dispcc-sm6125.c b/drivers/clk/qcom/dispcc-sm6125.c
index 1cc5f220a3c4..85e07731cce2 100644
--- a/drivers/clk/qcom/dispcc-sm6125.c
+++ b/drivers/clk/qcom/dispcc-sm6125.c
@@ -28,7 +28,7 @@ enum {
P_GPLL0_OUT_MAIN,
};
-static struct pll_vco disp_cc_pll_vco[] = {
+static const struct pll_vco disp_cc_pll_vco[] = {
{ 500000000, 1000000000, 2 },
};
diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c
index e4b7464c4d0e..f712cbef9456 100644
--- a/drivers/clk/qcom/dispcc-sm6350.c
+++ b/drivers/clk/qcom/dispcc-sm6350.c
@@ -31,7 +31,7 @@ enum {
P_GCC_DISP_GPLL0_CLK,
};
-static struct pll_vco fabia_vco[] = {
+static const struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
};
diff --git a/drivers/clk/qcom/dispcc-sm6375.c b/drivers/clk/qcom/dispcc-sm6375.c
index d81d4e3c0b0d..2d42f85f184b 100644
--- a/drivers/clk/qcom/dispcc-sm6375.c
+++ b/drivers/clk/qcom/dispcc-sm6375.c
@@ -35,7 +35,7 @@ enum {
P_GCC_DISP_GPLL0_CLK,
};
-static struct pll_vco lucid_vco[] = {
+static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
index 49bb4f58c391..5d028871624e 100644
--- a/drivers/clk/qcom/dispcc-sm8450.c
+++ b/drivers/clk/qcom/dispcc-sm8450.c
@@ -71,7 +71,7 @@ enum {
P_SLEEP_CLK,
};
-static struct pll_vco lucid_evo_vco[] = {
+static const struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2000000000, 0 },
};
diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c
index 38ecea805503..88f9347ab77c 100644
--- a/drivers/clk/qcom/dispcc-sm8550.c
+++ b/drivers/clk/qcom/dispcc-sm8550.c
@@ -71,7 +71,7 @@ enum {
P_SLEEP_CLK,
};
-static struct pll_vco lucid_ole_vco[] = {
+static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2000000000, 0 },
};
diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c
index 3eb64bcad487..c0e1ea63166b 100644
--- a/drivers/clk/qcom/dispcc-sm8650.c
+++ b/drivers/clk/qcom/dispcc-sm8650.c
@@ -69,7 +69,7 @@ enum {
P_SLEEP_CLK,
};
-static struct pll_vco lucid_ole_vco[] = {
+static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2100000000, 0 },
};
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index cad7f1c7789c..5f8c87c1793f 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -27,7 +27,7 @@
#define GCC_MMSS_MISC 0x0902C
#define GCC_GPU_MISC 0x71028
-static struct pll_vco fabia_vco[] = {
+static const struct pll_vco fabia_vco[] = {
{ 250000000, 2000000000, 0 },
{ 125000000, 1000000000, 1 },
};
diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c
index 5261bfc92b3d..ad905affd376 100644
--- a/drivers/clk/qcom/gcc-sc8180x.c
+++ b/drivers/clk/qcom/gcc-sc8180x.c
@@ -39,7 +39,7 @@ enum {
P_SLEEP_CLK,
};
-static struct pll_vco trion_vco[] = {
+static const struct pll_vco trion_vco[] = {
{ 249600000, 2000000000, 0 },
};
diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c
index 13e521cd4259..167e344ad399 100644
--- a/drivers/clk/qcom/gcc-sm6115.c
+++ b/drivers/clk/qcom/gcc-sm6115.c
@@ -42,15 +42,15 @@ enum {
P_SLEEP_CLK,
};
-static struct pll_vco default_vco[] = {
+static const struct pll_vco default_vco[] = {
{ 500000000, 1000000000, 2 },
};
-static struct pll_vco gpll9_vco[] = {
+static const struct pll_vco gpll9_vco[] = {
{ 500000000, 1250000000, 0 },
};
-static struct pll_vco gpll10_vco[] = {
+static const struct pll_vco gpll10_vco[] = {
{ 750000000, 1500000000, 1 },
};
diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c
index 84639d5b89bf..ac1ed2d728f9 100644
--- a/drivers/clk/qcom/gcc-sm6375.c
+++ b/drivers/clk/qcom/gcc-sm6375.c
@@ -50,11 +50,11 @@ enum {
P_SLEEP_CLK,
};
-static struct pll_vco lucid_vco[] = {
+static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
-static struct pll_vco zonda_vco[] = {
+static const struct pll_vco zonda_vco[] = {
{ 595200000, 3600000000UL, 0 },
};
diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c
index 9a4fdff719ec..7b1cb44e31b2 100644
--- a/drivers/clk/qcom/gpucc-msm8998.c
+++ b/drivers/clk/qcom/gpucc-msm8998.c
@@ -48,7 +48,7 @@ static struct clk_branch gpucc_cxo_clk = {
},
};
-static struct pll_vco fabia_vco[] = {
+static const struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
{ 125000000, 1000000000, 1 },
};
diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c
index 459f123a6720..a52d98b7cf4c 100644
--- a/drivers/clk/qcom/gpucc-sdm660.c
+++ b/drivers/clk/qcom/gpucc-sdm660.c
@@ -51,7 +51,7 @@ static struct clk_branch gpucc_cxo_clk = {
},
};
-static struct pll_vco gpu_vco[] = {
+static const struct pll_vco gpu_vco[] = {
{ 1000000000, 2000000000, 0 },
{ 500000000, 1000000000, 2 },
{ 250000000, 500000000, 3 },
diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c
index fb71c21c9a89..9793dd9a2596 100644
--- a/drivers/clk/qcom/gpucc-sm6115.c
+++ b/drivers/clk/qcom/gpucc-sm6115.c
@@ -38,11 +38,11 @@ enum {
P_GPU_CC_PLL1_OUT_MAIN,
};
-static struct pll_vco default_vco[] = {
+static const struct pll_vco default_vco[] = {
{ 1000000000, 2000000000, 0 },
};
-static struct pll_vco pll1_vco[] = {
+static const struct pll_vco pll1_vco[] = {
{ 500000000, 1000000000, 2 },
};
diff --git a/drivers/clk/qcom/gpucc-sm6125.c b/drivers/clk/qcom/gpucc-sm6125.c
index 61959ba02f9a..b719a48fe706 100644
--- a/drivers/clk/qcom/gpucc-sm6125.c
+++ b/drivers/clk/qcom/gpucc-sm6125.c
@@ -36,7 +36,7 @@ enum {
P_GPU_CC_PLL1_OUT_AUX2,
};
-static struct pll_vco gpu_cc_pll_vco[] = {
+static const struct pll_vco gpu_cc_pll_vco[] = {
{ 1000000000, 2000000000, 0 },
{ 500000000, 1000000000, 2 },
};
diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c
index da24276a018e..4e9a30a080d3 100644
--- a/drivers/clk/qcom/gpucc-sm6375.c
+++ b/drivers/clk/qcom/gpucc-sm6375.c
@@ -42,7 +42,7 @@ enum {
P_GPU_CC_PLL1_OUT_ODD,
};
-static struct pll_vco lucid_vco[] = {
+static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
diff --git a/drivers/clk/qcom/gpucc-sm8250.c b/drivers/clk/qcom/gpucc-sm8250.c
index 84f7f65c8d42..012bd1380f55 100644
--- a/drivers/clk/qcom/gpucc-sm8250.c
+++ b/drivers/clk/qcom/gpucc-sm8250.c
@@ -32,7 +32,7 @@ enum {
P_GPU_CC_PLL1_OUT_MAIN,
};
-static struct pll_vco lucid_vco[] = {
+static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c
index 38505d1388b6..9437d316d145 100644
--- a/drivers/clk/qcom/gpucc-sm8350.c
+++ b/drivers/clk/qcom/gpucc-sm8350.c
@@ -33,7 +33,7 @@ enum {
P_GPU_CC_PLL1_OUT_MAIN,
};
-static struct pll_vco lucid_5lpe_vco[] = {
+static const struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 1750000000, 0 },
};
diff --git a/drivers/clk/qcom/gpucc-sm8450.c b/drivers/clk/qcom/gpucc-sm8450.c
index 1c4769b646b0..7b329a803289 100644
--- a/drivers/clk/qcom/gpucc-sm8450.c
+++ b/drivers/clk/qcom/gpucc-sm8450.c
@@ -36,7 +36,7 @@ enum {
P_GPU_CC_PLL1_OUT_MAIN,
};
-static struct pll_vco lucid_evo_vco[] = {
+static const struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2000000000, 0 },
};
diff --git a/drivers/clk/qcom/gpucc-sm8650.c b/drivers/clk/qcom/gpucc-sm8650.c
index 03307e482aca..c53306d3093f 100644
--- a/drivers/clk/qcom/gpucc-sm8650.c
+++ b/drivers/clk/qcom/gpucc-sm8650.c
@@ -37,7 +37,7 @@ enum {
P_GPU_CC_PLL1_OUT_MAIN,
};
-static struct pll_vco lucid_ole_vco[] = {
+static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2100000000, 0 },
};
diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c b/drivers/clk/qcom/lpasscorecc-sc7180.c
index fd9cd2e3f956..8ac72d26087e 100644
--- a/drivers/clk/qcom/lpasscorecc-sc7180.c
+++ b/drivers/clk/qcom/lpasscorecc-sc7180.c
@@ -27,7 +27,7 @@ enum {
P_SLEEP_CLK,
};
-static struct pll_vco fabia_vco[] = {
+static const struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
};
diff --git a/drivers/clk/qcom/mmcc-msm8994.c b/drivers/clk/qcom/mmcc-msm8994.c
index 3229ff77372f..f19080cf715b 100644
--- a/drivers/clk/qcom/mmcc-msm8994.c
+++ b/drivers/clk/qcom/mmcc-msm8994.c
@@ -84,14 +84,14 @@ static const struct clk_parent_data mmcc_xo_dsibyte[] = {
{ .fw_name = "dsi1pllbyte" },
};
-static struct pll_vco mmpll_p_vco[] = {
+static const struct pll_vco mmpll_p_vco[] = {
{ 250000000, 500000000, 3 },
{ 500000000, 1000000000, 2 },
{ 1000000000, 1500000000, 1 },
{ 1500000000, 2000000000, 0 },
};
-static struct pll_vco mmpll_t_vco[] = {
+static const struct pll_vco mmpll_t_vco[] = {
{ 500000000, 1500000000, 0 },
};
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index d3f2dc798567..92287d40c3a5 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -57,20 +57,20 @@ static struct clk_fixed_factor gpll0_div = {
},
};
-static struct pll_vco mmpll_p_vco[] = {
+static const struct pll_vco mmpll_p_vco[] = {
{ 250000000, 500000000, 3 },
{ 500000000, 1000000000, 2 },
{ 1000000000, 1500000000, 1 },
{ 1500000000, 2000000000, 0 },
};
-static struct pll_vco mmpll_gfx_vco[] = {
+static const struct pll_vco mmpll_gfx_vco[] = {
{ 400000000, 1000000000, 2 },
{ 1000000000, 1500000000, 1 },
{ 1500000000, 2000000000, 0 },
};
-static struct pll_vco mmpll_t_vco[] = {
+static const struct pll_vco mmpll_t_vco[] = {
{ 500000000, 1500000000, 0 },
};
diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c
index 996bd01fb9ac..4b8380c2d648 100644
--- a/drivers/clk/qcom/mmcc-sdm660.c
+++ b/drivers/clk/qcom/mmcc-sdm660.c
@@ -96,14 +96,14 @@ static struct clk_alpha_pll mmpll6 = {
};
/* APSS controlled PLLs */
-static struct pll_vco vco[] = {
+static const struct pll_vco vco[] = {
{ 1000000000, 2000000000, 0 },
{ 750000000, 1500000000, 1 },
{ 500000000, 1000000000, 2 },
{ 250000000, 500000000, 3 },
};
-static struct pll_vco mmpll3_vco[] = {
+static const struct pll_vco mmpll3_vco[] = {
{ 750000000, 1500000000, 1 },
};
diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c
index a0329260157a..554631aa279b 100644
--- a/drivers/clk/qcom/videocc-sm8150.c
+++ b/drivers/clk/qcom/videocc-sm8150.c
@@ -24,7 +24,7 @@ enum {
P_VIDEO_PLL0_OUT_MAIN,
};
-static struct pll_vco trion_vco[] = {
+static const struct pll_vco trion_vco[] = {
{ 249600000, 2000000000, 0 },
};
diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c
index 016b596e03b3..914eddd0ae15 100644
--- a/drivers/clk/qcom/videocc-sm8250.c
+++ b/drivers/clk/qcom/videocc-sm8250.c
@@ -26,7 +26,7 @@ enum {
P_VIDEO_PLL1_OUT_MAIN,
};
-static struct pll_vco lucid_vco[] = {
+static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
--
2.45.0
^ permalink raw reply related [relevance 7%]
* [PATCH 11/12] arm64: dts: qcom: sm8550: Throttle the GPU when overheating
2024-05-10 12:58 5% [PATCH 00/12] Adreno cooling, take 2 Konrad Dybcio
@ 2024-05-10 12:58 14% ` Konrad Dybcio
0 siblings, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-05-10 12:58 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Johan Hovold
Cc: linux-arm-msm, devicetree, linux-kernel, Bjorn Andersson, Konrad Dybcio
Add an 85C passive trip point to ensure the thermal framework takes
sufficient action to prevent reaching junction temperature and a
110C critical point to help avoid hw damage.
Remove the copypasta-from-downstream userspace governor entries while
at it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 208 ++++++++++++++---------------------
1 file changed, 80 insertions(+), 128 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 51c547872438..23f769a5b1d4 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -5367,34 +5367,28 @@ gpuss-0-thermal {
cooling-maps {
map0 {
- trip = <&gpu0_junction_config>;
+ trip = <&gpu0_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu0_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
- };
-
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
+ type = "hot";
};
- gpu0_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
@@ -5406,34 +5400,28 @@ gpuss-1-thermal {
cooling-maps {
map0 {
- trip = <&gpu1_junction_config>;
+ trip = <&gpu1_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu1_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
- };
-
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
+ type = "hot";
};
- gpu1_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
@@ -5445,34 +5433,28 @@ gpuss-2-thermal {
cooling-maps {
map0 {
- trip = <&gpu2_junction_config>;
+ trip = <&gpu2_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu2_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
- };
-
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
+ type = "hot";
};
- gpu2_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
@@ -5484,34 +5466,28 @@ gpuss-3-thermal {
cooling-maps {
map0 {
- trip = <&gpu3_junction_config>;
+ trip = <&gpu3_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu3_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
- };
-
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
+ type = "hot";
};
- gpu3_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
@@ -5523,34 +5499,28 @@ gpuss-4-thermal {
cooling-maps {
map0 {
- trip = <&gpu4_junction_config>;
+ trip = <&gpu4_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu4_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
- };
-
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
+ type = "hot";
};
- gpu4_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
@@ -5562,34 +5532,28 @@ gpuss-5-thermal {
cooling-maps {
map0 {
- trip = <&gpu5_junction_config>;
+ trip = <&gpu5_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu5_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
- };
-
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
+ type = "hot";
};
- gpu5_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
@@ -5601,34 +5565,28 @@ gpuss-6-thermal {
cooling-maps {
map0 {
- trip = <&gpu6_junction_config>;
+ trip = <&gpu6_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu6_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
- };
-
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
+ type = "hot";
};
- gpu6_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
@@ -5640,34 +5598,28 @@ gpuss-7-thermal {
cooling-maps {
map0 {
- trip = <&gpu7_junction_config>;
+ trip = <&gpu7_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu7_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
- };
-
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
+ type = "hot";
};
- gpu7_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
--
2.40.1
^ permalink raw reply related [relevance 14%]
* [PATCH 00/12] Adreno cooling, take 2
@ 2024-05-10 12:58 5% Konrad Dybcio
2024-05-10 12:58 14% ` [PATCH 11/12] arm64: dts: qcom: sm8550: Throttle the GPU when overheating Konrad Dybcio
0 siblings, 1 reply; 200+ results
From: Konrad Dybcio @ 2024-05-10 12:58 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Johan Hovold
Cc: linux-arm-msm, devicetree, linux-kernel, Bjorn Andersson, Konrad Dybcio
For the thermal framework to cool devfreq-managed devices properly,
it seems like the following conditions must be met:
1. the devfreq device has a cooling device associated with it
2. there exists some thermal zone provider
3. the cooling device is referenced in a cooling map
4. the cooling map is associated with a thermal trip point
5. the thermal trip point is of the "passive" kind
6. the "passive" trip point is being updated (via polling or otherwise)
7. the trip point is being hit (i.e. the thing gets hot enough)
Various QC DTs have various issues, mostly around 4, 5, 6 and 7.
This series tries to amend the platforms that currently can't have
Adreno throttled, without making much unnecessary/debatable mess,
although sneaking in some configuration unification/standardization.
Further updates can be made in the future.
This was originally brought into attention by Daniel in [1], this
series resolves the issues on a treewide scale.
Developed atop (and thereby depends on) [2].
[1] https://lore.kernel.org/linux-arm-msm/20240116115921.804185-1-daniel.lezcano@linaro.org/
[2] https://lore.kernel.org/linux-arm-msm/b4dba1d5-448a-4a4b-94d5-f27c6ff0010d@linaro.org/T/#t
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (12):
arm64: dts: qcom: sc8180x: Throttle the GPU when overheating
arm64: dts: qcom: sc8280xp: Throttle the GPU when overheating
arm64: dts: qcom: sdm630: Throttle the GPU when overheating
arm64: dts: qcom: sdm845: Throttle the GPU when overheating
arm64: dts: qcom: sm6115: Update GPU thermal zone settings
arm64: dts: qcom: sm6350: Update GPU thermal zone settings
arm64: dts: qcom: sm8150: Throttle the GPU when overheating
arm64: dts: qcom: sm8250: Throttle the GPU when overheating
arm64: dts: qcom: sm8350: Throttle the GPU when overheating
arm64: dts: qcom: sm8450: Throttle the GPU when overheating
arm64: dts: qcom: sm8550: Throttle the GPU when overheating
arm64: dts: qcom: sm8650: Throttle the GPU when overheating
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 28 ++++-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 17 ++-
arch/arm64/boot/dts/qcom/sdm630.dtsi | 12 ++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 28 ++++-
arch/arm64/boot/dts/qcom/sm6115.dtsi | 8 +-
arch/arm64/boot/dts/qcom/sm6350.dtsi | 16 ++-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 ++++-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 ++++-
arch/arm64/boot/dts/qcom/sm8350.dtsi | 24 ++++
arch/arm64/boot/dts/qcom/sm8450.dtsi | 48 +++-----
arch/arm64/boot/dts/qcom/sm8550.dtsi | 208 +++++++++++++--------------------
arch/arm64/boot/dts/qcom/sm8650.dtsi | 169 ++++++++++++++++++++++-----
12 files changed, 406 insertions(+), 208 deletions(-)
---
base-commit: 2adffd063e54f8790132eedfaf3019bfb6f62268
change-id: 20240510-topic-gpus_are_cool_now-ed8d8c4f5f7f
Best regards,
--
Konrad Dybcio <konrad.dybcio@linaro.org>
^ permalink raw reply [relevance 5%]
* [PATCH v2 30/31] arm64: dts: qcom: sm8550-*: Remove thermal zone polling delays
2024-05-10 11:59 4% [PATCH v2 00/31] Clean up thermal zone polling-delay Konrad Dybcio
@ 2024-05-10 11:59 11% ` Konrad Dybcio
0 siblings, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-05-10 11:59 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
cros-qcom-dts-watchers, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Konrad Dybcio
All of the thermal zone suppliers are interrupt-driven, remove the
bogus and unnecessary polling that only wastes CPU time.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm64/boot/dts/qcom/pm8010.dtsi | 2 -
arch/arm64/boot/dts/qcom/pm8550.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm8550b.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm8550ve.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 4 --
arch/arm64/boot/dts/qcom/pmr735d_a.dtsi | 1 -
arch/arm64/boot/dts/qcom/pmr735d_b.dtsi | 1 -
arch/arm64/boot/dts/qcom/sm8550.dtsi | 82 ++++++---------------------------
8 files changed, 13 insertions(+), 80 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/pm8010.dtsi b/arch/arm64/boot/dts/qcom/pm8010.dtsi
index 0ea641e12209..ef330194946b 100644
--- a/arch/arm64/boot/dts/qcom/pm8010.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8010.dtsi
@@ -10,7 +10,6 @@ / {
thermal-zones {
pm8010-m-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8010_m_temp_alarm>;
@@ -31,7 +30,6 @@ trip1 {
pm8010-n-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8010_n_temp_alarm>;
diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi
index 797a18c249a4..896bcacb6490 100644
--- a/arch/arm64/boot/dts/qcom/pm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi
@@ -10,7 +10,6 @@ / {
thermal-zones {
pm8550-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550_temp_alarm>;
diff --git a/arch/arm64/boot/dts/qcom/pm8550b.dtsi b/arch/arm64/boot/dts/qcom/pm8550b.dtsi
index 72609f31c890..74d23b8970f4 100644
--- a/arch/arm64/boot/dts/qcom/pm8550b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550b.dtsi
@@ -10,7 +10,6 @@ / {
thermal-zones {
pm8550b-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550b_temp_alarm>;
diff --git a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi
index 4dc1f03ab2c7..9d4734eabf5a 100644
--- a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi
@@ -10,7 +10,6 @@ / {
thermal-zones {
pm8550ve-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550ve_temp_alarm>;
diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi
index 97b1c18aa7d8..6426b431616b 100644
--- a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi
@@ -10,7 +10,6 @@ / {
thermal-zones {
pm8550vs-c-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550vs_c_temp_alarm>;
@@ -31,7 +30,6 @@ trip1 {
pm8550vs-d-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550vs_d_temp_alarm>;
@@ -52,7 +50,6 @@ trip1 {
pm8550vs-e-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550vs_e_temp_alarm>;
@@ -73,7 +70,6 @@ trip1 {
pm8550vs-g-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550vs_g_temp_alarm>;
diff --git a/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi b/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi
index 37daaefe3431..f9f1793d310e 100644
--- a/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi
@@ -10,7 +10,6 @@ / {
thermal-zones {
pmr735d-k-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pmr735d_k_temp_alarm>;
diff --git a/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi b/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi
index 3b470f6ac46f..d91fbd3bff10 100644
--- a/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi
@@ -10,7 +10,6 @@ / {
thermal-zones {
pmr735d-l-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pmr735d_l_temp_alarm>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index bc5aeb05ffc3..51c547872438 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -4571,8 +4571,6 @@ compute-cb@8 {
thermal-zones {
aoss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
trips {
@@ -4591,8 +4589,6 @@ reset-mon-config {
};
cpuss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
trips {
@@ -4611,8 +4607,6 @@ reset-mon-config {
};
cpuss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
trips {
@@ -4631,8 +4625,6 @@ reset-mon-config {
};
cpuss2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
trips {
@@ -4651,8 +4643,6 @@ reset-mon-config {
};
cpuss3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
trips {
@@ -4671,8 +4661,6 @@ reset-mon-config {
};
cpu3-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
trips {
@@ -4697,8 +4685,6 @@ cpu3_top_crit: cpu-critical {
};
cpu3-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
trips {
@@ -4723,8 +4709,6 @@ cpu3_bottom_crit: cpu-critical {
};
cpu4-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
trips {
@@ -4749,8 +4733,6 @@ cpu4_top_crit: cpu-critical {
};
cpu4-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
trips {
@@ -4775,8 +4757,6 @@ cpu4_bottom_crit: cpu-critical {
};
cpu5-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
trips {
@@ -4801,8 +4781,6 @@ cpu5_top_crit: cpu-critical {
};
cpu5-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
trips {
@@ -4827,8 +4805,6 @@ cpu5_bottom_crit: cpu-critical {
};
cpu6-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
trips {
@@ -4853,8 +4829,6 @@ cpu6_top_crit: cpu-critical {
};
cpu6-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
trips {
@@ -4879,8 +4853,6 @@ cpu6_bottom_crit: cpu-critical {
};
cpu7-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
trips {
@@ -4905,8 +4877,6 @@ cpu7_top_crit: cpu-critical {
};
cpu7-middle-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
trips {
@@ -4931,8 +4901,6 @@ cpu7_middle_crit: cpu-critical {
};
cpu7-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 15>;
trips {
@@ -4957,8 +4925,6 @@ cpu7_bottom_crit: cpu-critical {
};
aoss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 0>;
trips {
@@ -4977,8 +4943,6 @@ reset-mon-config {
};
cpu0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
trips {
@@ -5003,8 +4967,6 @@ cpu0_crit: cpu-critical {
};
cpu1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
trips {
@@ -5029,8 +4991,6 @@ cpu1_crit: cpu-critical {
};
cpu2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 3>;
trips {
@@ -5056,7 +5016,7 @@ cpu2_crit: cpu-critical {
cdsp0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 4>;
trips {
@@ -5088,7 +5048,7 @@ cdsp0_junction_config: junction-config {
cdsp1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 5>;
trips {
@@ -5120,7 +5080,7 @@ cdsp1_junction_config: junction-config {
cdsp2-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 6>;
trips {
@@ -5152,7 +5112,7 @@ cdsp2_junction_config: junction-config {
cdsp3-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 7>;
trips {
@@ -5183,8 +5143,6 @@ cdsp3_junction_config: junction-config {
};
video-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 8>;
trips {
@@ -5204,7 +5162,7 @@ reset-mon-config {
mem-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens1 9>;
trips {
@@ -5229,8 +5187,6 @@ reset-mon-config {
};
modem0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 10>;
trips {
@@ -5261,8 +5217,6 @@ reset-mon-config {
};
modem1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 11>;
trips {
@@ -5293,8 +5247,6 @@ reset-mon-config {
};
modem2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 12>;
trips {
@@ -5325,8 +5277,6 @@ reset-mon-config {
};
modem3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 13>;
trips {
@@ -5357,8 +5307,6 @@ reset-mon-config {
};
camera0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 14>;
trips {
@@ -5377,8 +5325,6 @@ reset-mon-config {
};
camera1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 15>;
trips {
@@ -5397,8 +5343,6 @@ reset-mon-config {
};
aoss2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 0>;
trips {
@@ -5418,7 +5362,7 @@ reset-mon-config {
gpuss-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 1>;
cooling-maps {
@@ -5457,7 +5401,7 @@ gpu0_junction_config: junction-config {
gpuss-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 2>;
cooling-maps {
@@ -5496,7 +5440,7 @@ gpu1_junction_config: junction-config {
gpuss-2-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 3>;
cooling-maps {
@@ -5535,7 +5479,7 @@ gpu2_junction_config: junction-config {
gpuss-3-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 4>;
cooling-maps {
@@ -5574,7 +5518,7 @@ gpu3_junction_config: junction-config {
gpuss-4-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 5>;
cooling-maps {
@@ -5613,7 +5557,7 @@ gpu4_junction_config: junction-config {
gpuss-5-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 6>;
cooling-maps {
@@ -5652,7 +5596,7 @@ gpu5_junction_config: junction-config {
gpuss-6-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 7>;
cooling-maps {
@@ -5691,7 +5635,7 @@ gpu6_junction_config: junction-config {
gpuss-7-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 8>;
cooling-maps {
--
2.40.1
^ permalink raw reply related [relevance 11%]
* [PATCH v2 00/31] Clean up thermal zone polling-delay
@ 2024-05-10 11:59 4% Konrad Dybcio
2024-05-10 11:59 11% ` [PATCH v2 30/31] arm64: dts: qcom: sm8550-*: Remove thermal zone polling delays Konrad Dybcio
0 siblings, 1 reply; 200+ results
From: Konrad Dybcio @ 2024-05-10 11:59 UTC (permalink / raw)
To: Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
cros-qcom-dts-watchers, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Konrad Dybcio
A trivial follow-up on the changes introduced in Commit 488164006a28
("thermal/of: Assume polling-delay(-passive) 0 when absent").
Should probably wait until v6.9-rc1 so that the patch in question is
in the base tree, otherwise TZs will fail to register.
FWIW, Compile-tested only (except 8280).
To: Bjorn Andersson <andersson@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
To: Conor Dooley <conor+dt@kernel.org>
To: cros-qcom-dts-watchers@chromium.org
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Changes in v2:
- Un-drop passive delays. Whether they're useful where they're enabled
is a topic for another patchset, as it requires examination on a case-
-by-case basis.
- Better unify the style (newlines between properties)
- Link to v1: https://lore.kernel.org/r/20240319-topic-msm-polling-cleanup-v1-0-e0aee1dbcd78@linaro.org
---
Konrad Dybcio (31):
arm64: dts: qcom: ipq6018-*: Remove thermal zone polling delays
arm64: dts: qcom: ipq8074-*: Remove thermal zone polling delays
arm64: dts: qcom: ipq9574-*: Remove thermal zone polling delays
arm64: dts: qcom: msm8916-*: Remove thermal zone polling delays
arm64: dts: qcom: msm8939-*: Remove thermal zone polling delays
arm64: dts: qcom: msm8953-*: Remove thermal zone polling delays
arm64: dts: qcom: msm8976-*: Remove thermal zone polling delays
arm64: dts: qcom: msm8996-*: Remove thermal zone polling delays
arm64: dts: qcom: msm8998-*: Remove thermal zone polling delays
arm64: dts: qcom: pm7550ba: Remove thermal zone polling delays
arm64: dts: qcom: pms405: Remove thermal zone polling delays
arm64: dts: qcom: pmx75: Remove thermal zone polling delays
arm64: dts: qcom: qcm2290-*: Remove thermal zone polling delays
arm64: dts: qcom: qcs404-*: Remove thermal zone polling delays
arm64: dts: qcom: sa8775p-*: Remove thermal zone polling delays
arm64: dts: qcom: sc7180-*: Remove thermal zone polling delays
arm64: dts: qcom: sc7280-*: Remove thermal zone polling delays
arm64: dts: qcom: sc8180x-*: Remove thermal zone polling delays
arm64: dts: qcom: sc8280xp-*: Remove thermal zone polling delays
arm64: dts: qcom: sdm660-*: Remove thermal zone polling delays
arm64: dts: qcom: sdm845-*: Remove thermal zone polling delays
arm64: dts: qcom: sm6115-*: Remove thermal zone polling delays
arm64: dts: qcom: sm6125-*: Remove thermal zone polling delays
arm64: dts: qcom: sm6350-*: Remove thermal zone polling delays
arm64: dts: qcom: sm6375-*: Remove thermal zone polling delays
arm64: dts: qcom: sm8150-*: Remove thermal zone polling delays
arm64: dts: qcom: sm8250-*: Remove thermal zone polling delays
arm64: dts: qcom: sm8350-*: Remove thermal zone polling delays
arm64: dts: qcom: sm8450-*: Remove thermal zone polling delays
arm64: dts: qcom: sm8550-*: Remove thermal zone polling delays
arm64: dts: qcom: sm8650-*: Remove thermal zone polling delays
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 --
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 -------
arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 --
arch/arm64/boot/dts/qcom/msm8939.dtsi | 9 ---
arch/arm64/boot/dts/qcom/msm8953.dtsi | 17 ++---
arch/arm64/boot/dts/qcom/msm8976.dtsi | 18 ++---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 14 ----
arch/arm64/boot/dts/qcom/msm8998.dtsi | 19 -----
arch/arm64/boot/dts/qcom/pm6125.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm6150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6150l.dtsi | 3 -
arch/arm64/boot/dts/qcom/pm6350.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm660.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm660l.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm7250b.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm7325.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm7550ba.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm8010.dtsi | 2 -
arch/arm64/boot/dts/qcom/pm8150.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm8150b.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm8150l.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm8350.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8350b.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8350c.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8450.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm8550.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm8550b.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm8550ve.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 4 -
arch/arm64/boot/dts/qcom/pm8953.dtsi | 3 -
arch/arm64/boot/dts/qcom/pm8994.dtsi | 1 -
arch/arm64/boot/dts/qcom/pm8998.dtsi | 1 -
arch/arm64/boot/dts/qcom/pmi632.dtsi | 1 -
arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 1 -
arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi | 1 -
arch/arm64/boot/dts/qcom/pmr735a.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmr735b.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmr735d_a.dtsi | 1 -
arch/arm64/boot/dts/qcom/pmr735d_b.dtsi | 1 -
arch/arm64/boot/dts/qcom/pms405.dtsi | 1 -
arch/arm64/boot/dts/qcom/pmx75.dtsi | 1 -
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 30 --------
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 14 ++--
arch/arm64/boot/dts/qcom/qcs404.dtsi | 10 ---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 10 ---
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 8 +-
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 82 --------------------
.../arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 1 -
.../boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 1 -
.../arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 3 -
.../boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi | 1 -
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 3 -
arch/arm64/boot/dts/qcom/sc7180.dtsi | 25 ------
arch/arm64/boot/dts/qcom/sc7280.dtsi | 45 -----------
arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 2 -
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 26 -------
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 4 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 13 ----
arch/arm64/boot/dts/qcom/sdm630.dtsi | 9 ---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 12 ---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 21 ------
arch/arm64/boot/dts/qcom/sm6115.dtsi | 32 --------
.../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 8 --
.../boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts | 6 --
arch/arm64/boot/dts/qcom/sm6350.dtsi | 81 --------------------
arch/arm64/boot/dts/qcom/sm6375.dtsi | 78 -------------------
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 4 -
arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 -------
arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 14 ----
arch/arm64/boot/dts/qcom/sm8250.dtsi | 25 ------
arch/arm64/boot/dts/qcom/sm8350.dtsi | 29 -------
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 16 ++--
arch/arm64/boot/dts/qcom/sm8450.dtsi | 64 ++--------------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 82 ++++----------------
arch/arm64/boot/dts/qcom/sm8650.dtsi | 88 ++++------------------
77 files changed, 78 insertions(+), 973 deletions(-)
---
base-commit: 704ba27ac55579704ba1289392448b0c66b56258
change-id: 20240319-topic-msm-polling-cleanup-2616a8bece70
Best regards,
--
Konrad Dybcio <konrad.dybcio@linaro.org>
^ permalink raw reply [relevance 4%]
* Re: [PATCH RFT 0/7] arm64: qcom: allow up to 4 lanes for the Type-C DisplayPort Altmode
2024-04-23 14:08 0% ` neil.armstrong
@ 2024-05-10 6:51 0% ` Luca Weiss
-1 siblings, 0 replies; 200+ results
From: Luca Weiss @ 2024-05-10 6:51 UTC (permalink / raw)
To: neil.armstrong, Konrad Dybcio, Bjorn Andersson
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Abhinav Kumar, linux-arm-msm,
linux-phy, devicetree, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 8911 bytes --]
On Tue Apr 23, 2024 at 4:08 PM CEST, wrote:
> On 23/04/2024 15:03, Konrad Dybcio wrote:
> >
> >
> > On 4/5/24 12:19, Luca Weiss wrote:
> >> On Fri Apr 5, 2024 at 10:08 AM CEST, Neil Armstrong wrote:
> >>> Hi Luca,
> >>>
> >>> On 29/03/2024 10:02, Luca Weiss wrote:
> >>>> On Tue Mar 26, 2024 at 10:02 PM CET, Konrad Dybcio wrote:
> >>>>> On 16.03.2024 5:01 PM, Bjorn Andersson wrote:
> >>>>>> On Fri, Mar 15, 2024 at 06:35:15PM +0100, Neil Armstrong wrote:
> >>>>>>> On 15/03/2024 18:19, Luca Weiss wrote:
> >>>>>>>> On Thu Feb 29, 2024 at 2:07 PM CET, Neil Armstrong wrote:
> >>>>>>>>> Register a typec mux in order to change the PHY mode on the Type-C
> >>>>>>>>> mux events depending on the mode and the svid when in Altmode setup.
> >>>>>>>>>
> >>>>>>>>> The DisplayPort phy should be left enabled if is still powered on
> >>>>>>>>> by the DRM DisplayPort controller, so bail out until the DisplayPort
> >>>>>>>>> PHY is not powered off.
> >>>>>>>>>
> >>>>>>>>> The Type-C Mode/SVID only changes on plug/unplug, and USB SAFE states
> >>>>>>>>> will be set in between of USB-Only, Combo and DisplayPort Only so
> >>>>>>>>> this will leave enough time to the DRM DisplayPort controller to
> >>>>>>>>> turn of the DisplayPort PHY.
> >>>>>>>>>
> >>>>>>>>> The patchset also includes bindings changes and DT changes.
> >>>>>>>>>
> >>>>>>>>> This has been successfully tested on an SM8550 board, but the
> >>>>>>>>> Thinkpad X13s deserved testing between non-PD USB, non-PD DisplayPort,
> >>>>>>>>> PD USB Hubs and PD Altmode Dongles to make sure the switch works
> >>>>>>>>> as expected.
> >>>>>>>>>
> >>>>>>>>> The DisplayPort 4 lanes setup can be check with:
> >>>>>>>>> $ cat /sys/kernel/debug/dri/ae01000.display-controller/DP-1/dp_debug
> >>>>>>>>> name = msm_dp
> >>>>>>>>> drm_dp_link
> >>>>>>>>> rate = 540000
> >>>>>>>>> num_lanes = 4
> >>>>>>>>
> >>>>>>>> Hi Neil,
> >>>>>>>>
> >>>>>>>> I tried this on QCM6490/SC7280 which should also support 4-lane DP but I
> >>>>>>>> haven't had any success so far.
> >>>>>>>>
> >>>>>> [..]
> >>>>>>>> [ 1775.563969] [drm:dp_ctrl_link_train] *ERROR* max v_level reached
> >>>>>>>> [ 1775.564031] [drm:dp_ctrl_link_train] *ERROR* link training #1 failed. ret=-11
> >>>>>>>
> >>>>>>> Interesting #1 means the 4 lanes are not physically connected to the other side,
> >>>>>>> perhaps QCM6490/SC7280 requires a specific way to enable the 4 lanes in the PHY,
> >>>>>>> or some fixups in the init tables.
> >>>>>>>
> >>>>>>
> >>>>>> I tested the same on rb3gen2 (qcs6490) a couple of weeks ago, with the
> >>>>>> same outcome. Looking at the AUX reads, after switching to 4-lane the
> >>>>>> link training is failing on all 4 lanes, in contrast to succeeding only
> >>>>>> on the first 2 if you e.g. forget to mux the other two.
> >>>>>>
> >>>>>> As such, my expectation is that there's something wrong in the QMP PHY
> >>>>>> (or possibly redriver) for this platform.
> >>>>>
> >>>>> Do we have any downstream tag where 4lane dp works? I'm willing to believe
> >>>>> the PHY story..
> >>>>
> >>>> Just tested on Fairphone 5 downstream and 4 lane appears to work there.
> >>>> This is with an USB-C to HDMI adapter that only does HDMI.
> >>>>
> >>>> FP5:/ # cat /sys/kernel/debug/drm_dp/dp_debug
> >>>> state=0x20a5
> >>>> link_rate=270000
> >>>> num_lanes=4
> >>>> resolution=2560x1440@60Hz
> >>>> pclock=241500KHz
> >>>> bpp=24
> >>>> test_req=DP_LINK_STATUS_UPDATED
> >>>> lane_count=4
> >>>> bw_code=10
> >>>> v_level=0
> >>>> p_level=0
> >>>>
> >>>> Sources are here:
> >>>> https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-5.4/+/refs/heads/odm/rc/target/13/fp5
> >>>> And probably more importantly techpack/display:
> >>>> https://gerrit-public.fairphone.software/plugins/gitiles/platform/vendor/opensource/display-drivers/+/refs/heads/odm/rc/target/13/fp5
> >>>> Dts if useful:
> >>>> https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/refs/heads/kernel/13/fp5
> >>>
> >>> Could you retry with this applied ?
> >>>
> >>> https://lore.kernel.org/all/20240405000111.1450598-1-swboyd@chromium.org/
> >>
> >> Unfortunately I do not see any change with this on QCM6490 Fairphone 5
> >> and 4-lane DP.
> >
> > Hm, could you like dump all the PHY regions up and downstream with the display
> > connected (and nothing connected) and compare them?
>
> Yes would be great, PHY regions and DP regions as well.
Hi all,
This mail is mostly a dump, maybe someone sees something interesting in
there...
With this script here I dumped the usb_1_qmpphy region, unfortunately
for mdss_dp regions the board crashed so we probably aren't allowed to
read some of the registers there. I didn't try to narrow this down
further.
https://github.com/z3ntu/dotfiles/blob/master/scripts/usr/local/bin/devmem-dump.sh
./devmem-dump.sh 0x88e8000 0x3000
With that out of the way, here's a first 'dump diff' between Android
(5.4 kernel) and mainline - this was with the device being plugged in to
my computer in both cases, so without DP.
$ diff --ignore-case -U0 usb_1_qmpphy_20240503_142336_android.txt usb_1_qmpphy_20240503_113953_mainline.txt
--- usb_1_qmpphy_20240503_142336_android.txt 2024-05-03 14:28:38.363607165 +0200
+++ usb_1_qmpphy_20240503_113953_mainline.txt 2024-05-03 14:32:38.923709704 +0200
@@ -5 +5 @@
-0x88E8010 - 0x00
+0x88E8010 - 0x02
@@ -21 +21 @@
-0x88E8050 - 0x00
+0x88E8050 - 0x02
@@ -37 +37 @@
-0x88E8090 - 0x00
+0x88E8090 - 0x02
@@ -53 +53 @@
-0x88E80D0 - 0x00
+0x88E80D0 - 0x02
@@ -69 +69 @@
-0x88E8110 - 0x00
+0x88E8110 - 0x02
@@ -85 +85 @@
-0x88E8150 - 0x00
+0x88E8150 - 0x02
@@ -101 +101 @@
-0x88E8190 - 0x00
+0x88E8190 - 0x02
@@ -117 +117 @@
-0x88E81D0 - 0x00
+0x88E81D0 - 0x02
@@ -1107,2 +1107,2 @@
-0x88E9148 - 0x4c
-0x88E914C - 0x48
+0x88E9148 - 0x4D
+0x88E914C - 0x3C
@@ -1236,3 +1236,3 @@
-0x88E934C - 0x12
-0x88E9350 - 0x11
-0x88E9354 - 0x11
+0x88E934C - 0x11
+0x88E9350 - 0x12
+0x88E9354 - 0x12
@@ -1268,3 +1268,3 @@
-0x88E93CC - 0x12
-0x88E93D0 - 0x11
-0x88E93D4 - 0x11
+0x88E93CC - 0x11
+0x88E93D0 - 0x12
+0x88E93D4 - 0x12
@@ -1401 +1401 @@
-0x88E95E0 - 0xef
+0x88E95E0 - 0xFF
@@ -2131 +2131 @@
-0x88EA148 - 0x4c
+0x88EA148 - 0x4D
Not quite sure what those registers are supposed to be - I didn't see
them in the driver so maybe they're not written from Linux at all?
Here trying to get which registers which offset are, by dividing them
into the different regions (COM, USB3_SERDES, TXA, RXA, DP_SERDES).
# COM start
-0x88E8010 - 0x00 => 0x10 QPHY_V3_DP_COM_TYPEC_CTRL
+0x88E8010 - 0x02
@@ -21 +21 @@
-0x88E8050 - 0x00 => 0x50
+0x88E8050 - 0x02
@@ -37 +37 @@
-0x88E8090 - 0x00 => 0x90
+0x88E8090 - 0x02
@@ -53 +53 @@
-0x88E80D0 - 0x00 => 0xd0
+0x88E80D0 - 0x02
@@ -69 +69 @@
-0x88E8110 - 0x00 => 0x110
+0x88E8110 - 0x02
@@ -85 +85 @@
-0x88E8150 - 0x00 => 0x150
+0x88E8150 - 0x02
@@ -101 +101 @@
-0x88E8190 - 0x00 => 0x190
+0x88E8190 - 0x02
@@ -117 +117 @@
-0x88E81D0 - 0x00 => 0x1d0
+0x88E81D0 - 0x02
# COM end
# USB3_SERDES start
@@ -1107,2 +1107,2 @@
-0x88E9148 - 0x4c => 0x148 QSERDES_V4_COM_RESTRIM_CODE_STATUS
-0x88E914C - 0x48 => 0x14c QSERDES_V4_COM_PLLCAL_CODE1_STATUS
+0x88E9148 - 0x4D
+0x88E914C - 0x3C
# USB3_SERDES end
# TXA start
@@ -1236,3 +1236,3 @@
-0x88E934C - 0x12 => 0x14c QSERDES_V4_TX_IDAC_STATUS_IBAR
-0x88E9350 - 0x11 => 0x150 QSERDES_V4_TX_IDAC_STATUS_Q
-0x88E9354 - 0x11 => 0x154 QSERDES_V4_TX_IDAC_STATUS_QBAR
+0x88E934C - 0x11
+0x88E9350 - 0x12
+0x88E9354 - 0x12
@@ -1268,3 +1268,3 @@
-0x88E93CC - 0x12 => 0x1cc ?
-0x88E93D0 - 0x11 => 0x1d0 ?
-0x88E93D4 - 0x11 => 0x1d4 ?
+0x88E93CC - 0x11
+0x88E93D0 - 0x12
+0x88E93D4 - 0x12
# TXA end
# RXA start
@@ -1401 +1401 @@
-0x88E95E0 - 0xef => 0x1e0 QSERDES_V4_RX_IDATA1
+0x88E95E0 - 0xFF
# RXA end
# DP_SERDES start
@@ -2131 +2131 @@
-0x88EA148 - 0x4c => 0x148 QSERDES_V4_COM_RESTRIM_CODE_STATUS
+0x88EA148 - 0x4D
# DP_SERDES end
Next, with DP 4 lane (not working on mainline but still plugged into a
screen) the diff is quite a bit bigger.
See attachments for the full files:
* usb_1_qmpphy_20240503_151052_android_4lane.txt
* usb_1_qmpphy_20240503_122443_mainline_4lane.txt
Not attaching the diff because it's quite a lot
$ diff --ignore-case -U0 usb_1_qmpphy_20240503_151052_android_4lane.txt usb_1_qmpphy_20240503_122443_mainline_4lane.txt
Not sure this is helpful to anyone, but at least wanted to share what
I've done so far here.
Regards
Luca
>
> Neil
>
> >
> > Konrad
[-- Attachment #2: usb_1_qmpphy_20240503_151052_android_4lane.txt --]
[-- Type: text/plain, Size: 52224 bytes --]
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[-- Attachment #4: Type: text/plain, Size: 112 bytes --]
--
linux-phy mailing list
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^ permalink raw reply [relevance 0%]
* Re: [PATCH RFT 0/7] arm64: qcom: allow up to 4 lanes for the Type-C DisplayPort Altmode
@ 2024-05-10 6:51 0% ` Luca Weiss
0 siblings, 0 replies; 200+ results
From: Luca Weiss @ 2024-05-10 6:51 UTC (permalink / raw)
To: neil.armstrong, Konrad Dybcio, Bjorn Andersson
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Abhinav Kumar, linux-arm-msm,
linux-phy, devicetree, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 8911 bytes --]
On Tue Apr 23, 2024 at 4:08 PM CEST, wrote:
> On 23/04/2024 15:03, Konrad Dybcio wrote:
> >
> >
> > On 4/5/24 12:19, Luca Weiss wrote:
> >> On Fri Apr 5, 2024 at 10:08 AM CEST, Neil Armstrong wrote:
> >>> Hi Luca,
> >>>
> >>> On 29/03/2024 10:02, Luca Weiss wrote:
> >>>> On Tue Mar 26, 2024 at 10:02 PM CET, Konrad Dybcio wrote:
> >>>>> On 16.03.2024 5:01 PM, Bjorn Andersson wrote:
> >>>>>> On Fri, Mar 15, 2024 at 06:35:15PM +0100, Neil Armstrong wrote:
> >>>>>>> On 15/03/2024 18:19, Luca Weiss wrote:
> >>>>>>>> On Thu Feb 29, 2024 at 2:07 PM CET, Neil Armstrong wrote:
> >>>>>>>>> Register a typec mux in order to change the PHY mode on the Type-C
> >>>>>>>>> mux events depending on the mode and the svid when in Altmode setup.
> >>>>>>>>>
> >>>>>>>>> The DisplayPort phy should be left enabled if is still powered on
> >>>>>>>>> by the DRM DisplayPort controller, so bail out until the DisplayPort
> >>>>>>>>> PHY is not powered off.
> >>>>>>>>>
> >>>>>>>>> The Type-C Mode/SVID only changes on plug/unplug, and USB SAFE states
> >>>>>>>>> will be set in between of USB-Only, Combo and DisplayPort Only so
> >>>>>>>>> this will leave enough time to the DRM DisplayPort controller to
> >>>>>>>>> turn of the DisplayPort PHY.
> >>>>>>>>>
> >>>>>>>>> The patchset also includes bindings changes and DT changes.
> >>>>>>>>>
> >>>>>>>>> This has been successfully tested on an SM8550 board, but the
> >>>>>>>>> Thinkpad X13s deserved testing between non-PD USB, non-PD DisplayPort,
> >>>>>>>>> PD USB Hubs and PD Altmode Dongles to make sure the switch works
> >>>>>>>>> as expected.
> >>>>>>>>>
> >>>>>>>>> The DisplayPort 4 lanes setup can be check with:
> >>>>>>>>> $ cat /sys/kernel/debug/dri/ae01000.display-controller/DP-1/dp_debug
> >>>>>>>>> name = msm_dp
> >>>>>>>>> drm_dp_link
> >>>>>>>>> rate = 540000
> >>>>>>>>> num_lanes = 4
> >>>>>>>>
> >>>>>>>> Hi Neil,
> >>>>>>>>
> >>>>>>>> I tried this on QCM6490/SC7280 which should also support 4-lane DP but I
> >>>>>>>> haven't had any success so far.
> >>>>>>>>
> >>>>>> [..]
> >>>>>>>> [ 1775.563969] [drm:dp_ctrl_link_train] *ERROR* max v_level reached
> >>>>>>>> [ 1775.564031] [drm:dp_ctrl_link_train] *ERROR* link training #1 failed. ret=-11
> >>>>>>>
> >>>>>>> Interesting #1 means the 4 lanes are not physically connected to the other side,
> >>>>>>> perhaps QCM6490/SC7280 requires a specific way to enable the 4 lanes in the PHY,
> >>>>>>> or some fixups in the init tables.
> >>>>>>>
> >>>>>>
> >>>>>> I tested the same on rb3gen2 (qcs6490) a couple of weeks ago, with the
> >>>>>> same outcome. Looking at the AUX reads, after switching to 4-lane the
> >>>>>> link training is failing on all 4 lanes, in contrast to succeeding only
> >>>>>> on the first 2 if you e.g. forget to mux the other two.
> >>>>>>
> >>>>>> As such, my expectation is that there's something wrong in the QMP PHY
> >>>>>> (or possibly redriver) for this platform.
> >>>>>
> >>>>> Do we have any downstream tag where 4lane dp works? I'm willing to believe
> >>>>> the PHY story..
> >>>>
> >>>> Just tested on Fairphone 5 downstream and 4 lane appears to work there.
> >>>> This is with an USB-C to HDMI adapter that only does HDMI.
> >>>>
> >>>> FP5:/ # cat /sys/kernel/debug/drm_dp/dp_debug
> >>>> state=0x20a5
> >>>> link_rate=270000
> >>>> num_lanes=4
> >>>> resolution=2560x1440@60Hz
> >>>> pclock=241500KHz
> >>>> bpp=24
> >>>> test_req=DP_LINK_STATUS_UPDATED
> >>>> lane_count=4
> >>>> bw_code=10
> >>>> v_level=0
> >>>> p_level=0
> >>>>
> >>>> Sources are here:
> >>>> https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-5.4/+/refs/heads/odm/rc/target/13/fp5
> >>>> And probably more importantly techpack/display:
> >>>> https://gerrit-public.fairphone.software/plugins/gitiles/platform/vendor/opensource/display-drivers/+/refs/heads/odm/rc/target/13/fp5
> >>>> Dts if useful:
> >>>> https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/refs/heads/kernel/13/fp5
> >>>
> >>> Could you retry with this applied ?
> >>>
> >>> https://lore.kernel.org/all/20240405000111.1450598-1-swboyd@chromium.org/
> >>
> >> Unfortunately I do not see any change with this on QCM6490 Fairphone 5
> >> and 4-lane DP.
> >
> > Hm, could you like dump all the PHY regions up and downstream with the display
> > connected (and nothing connected) and compare them?
>
> Yes would be great, PHY regions and DP regions as well.
Hi all,
This mail is mostly a dump, maybe someone sees something interesting in
there...
With this script here I dumped the usb_1_qmpphy region, unfortunately
for mdss_dp regions the board crashed so we probably aren't allowed to
read some of the registers there. I didn't try to narrow this down
further.
https://github.com/z3ntu/dotfiles/blob/master/scripts/usr/local/bin/devmem-dump.sh
./devmem-dump.sh 0x88e8000 0x3000
With that out of the way, here's a first 'dump diff' between Android
(5.4 kernel) and mainline - this was with the device being plugged in to
my computer in both cases, so without DP.
$ diff --ignore-case -U0 usb_1_qmpphy_20240503_142336_android.txt usb_1_qmpphy_20240503_113953_mainline.txt
--- usb_1_qmpphy_20240503_142336_android.txt 2024-05-03 14:28:38.363607165 +0200
+++ usb_1_qmpphy_20240503_113953_mainline.txt 2024-05-03 14:32:38.923709704 +0200
@@ -5 +5 @@
-0x88E8010 - 0x00
+0x88E8010 - 0x02
@@ -21 +21 @@
-0x88E8050 - 0x00
+0x88E8050 - 0x02
@@ -37 +37 @@
-0x88E8090 - 0x00
+0x88E8090 - 0x02
@@ -53 +53 @@
-0x88E80D0 - 0x00
+0x88E80D0 - 0x02
@@ -69 +69 @@
-0x88E8110 - 0x00
+0x88E8110 - 0x02
@@ -85 +85 @@
-0x88E8150 - 0x00
+0x88E8150 - 0x02
@@ -101 +101 @@
-0x88E8190 - 0x00
+0x88E8190 - 0x02
@@ -117 +117 @@
-0x88E81D0 - 0x00
+0x88E81D0 - 0x02
@@ -1107,2 +1107,2 @@
-0x88E9148 - 0x4c
-0x88E914C - 0x48
+0x88E9148 - 0x4D
+0x88E914C - 0x3C
@@ -1236,3 +1236,3 @@
-0x88E934C - 0x12
-0x88E9350 - 0x11
-0x88E9354 - 0x11
+0x88E934C - 0x11
+0x88E9350 - 0x12
+0x88E9354 - 0x12
@@ -1268,3 +1268,3 @@
-0x88E93CC - 0x12
-0x88E93D0 - 0x11
-0x88E93D4 - 0x11
+0x88E93CC - 0x11
+0x88E93D0 - 0x12
+0x88E93D4 - 0x12
@@ -1401 +1401 @@
-0x88E95E0 - 0xef
+0x88E95E0 - 0xFF
@@ -2131 +2131 @@
-0x88EA148 - 0x4c
+0x88EA148 - 0x4D
Not quite sure what those registers are supposed to be - I didn't see
them in the driver so maybe they're not written from Linux at all?
Here trying to get which registers which offset are, by dividing them
into the different regions (COM, USB3_SERDES, TXA, RXA, DP_SERDES).
# COM start
-0x88E8010 - 0x00 => 0x10 QPHY_V3_DP_COM_TYPEC_CTRL
+0x88E8010 - 0x02
@@ -21 +21 @@
-0x88E8050 - 0x00 => 0x50
+0x88E8050 - 0x02
@@ -37 +37 @@
-0x88E8090 - 0x00 => 0x90
+0x88E8090 - 0x02
@@ -53 +53 @@
-0x88E80D0 - 0x00 => 0xd0
+0x88E80D0 - 0x02
@@ -69 +69 @@
-0x88E8110 - 0x00 => 0x110
+0x88E8110 - 0x02
@@ -85 +85 @@
-0x88E8150 - 0x00 => 0x150
+0x88E8150 - 0x02
@@ -101 +101 @@
-0x88E8190 - 0x00 => 0x190
+0x88E8190 - 0x02
@@ -117 +117 @@
-0x88E81D0 - 0x00 => 0x1d0
+0x88E81D0 - 0x02
# COM end
# USB3_SERDES start
@@ -1107,2 +1107,2 @@
-0x88E9148 - 0x4c => 0x148 QSERDES_V4_COM_RESTRIM_CODE_STATUS
-0x88E914C - 0x48 => 0x14c QSERDES_V4_COM_PLLCAL_CODE1_STATUS
+0x88E9148 - 0x4D
+0x88E914C - 0x3C
# USB3_SERDES end
# TXA start
@@ -1236,3 +1236,3 @@
-0x88E934C - 0x12 => 0x14c QSERDES_V4_TX_IDAC_STATUS_IBAR
-0x88E9350 - 0x11 => 0x150 QSERDES_V4_TX_IDAC_STATUS_Q
-0x88E9354 - 0x11 => 0x154 QSERDES_V4_TX_IDAC_STATUS_QBAR
+0x88E934C - 0x11
+0x88E9350 - 0x12
+0x88E9354 - 0x12
@@ -1268,3 +1268,3 @@
-0x88E93CC - 0x12 => 0x1cc ?
-0x88E93D0 - 0x11 => 0x1d0 ?
-0x88E93D4 - 0x11 => 0x1d4 ?
+0x88E93CC - 0x11
+0x88E93D0 - 0x12
+0x88E93D4 - 0x12
# TXA end
# RXA start
@@ -1401 +1401 @@
-0x88E95E0 - 0xef => 0x1e0 QSERDES_V4_RX_IDATA1
+0x88E95E0 - 0xFF
# RXA end
# DP_SERDES start
@@ -2131 +2131 @@
-0x88EA148 - 0x4c => 0x148 QSERDES_V4_COM_RESTRIM_CODE_STATUS
+0x88EA148 - 0x4D
# DP_SERDES end
Next, with DP 4 lane (not working on mainline but still plugged into a
screen) the diff is quite a bit bigger.
See attachments for the full files:
* usb_1_qmpphy_20240503_151052_android_4lane.txt
* usb_1_qmpphy_20240503_122443_mainline_4lane.txt
Not attaching the diff because it's quite a lot
$ diff --ignore-case -U0 usb_1_qmpphy_20240503_151052_android_4lane.txt usb_1_qmpphy_20240503_122443_mainline_4lane.txt
Not sure this is helpful to anyone, but at least wanted to share what
I've done so far here.
Regards
Luca
>
> Neil
>
> >
> > Konrad
[-- Attachment #2: usb_1_qmpphy_20240503_151052_android_4lane.txt --]
[-- Type: text/plain, Size: 52224 bytes --]
0x88E8000 - 0x02
0x88E8004 - 0x00
0x88E8008 - 0x01
0x88E800C - 0x00
0x88E8010 - 0x03
0x88E8014 - 0x00
0x88E8018 - 0x06
0x88E801C - 0x00
0x88E8020 - 0x00
0x88E8024 - 0x03
0x88E8028 - 0x00
0x88E802C - 0x0a
0x88E8030 - 0x00
0x88E8034 - 0x00
0x88E8038 - 0x40
0x88E803C - 0x00
0x88E8040 - 0x02
0x88E8044 - 0x00
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0x88EAFFC - 0x00
^ permalink raw reply [relevance 0%]
* [GIT PULL] Qualcomm clock updates for v6.10
@ 2024-05-08 2:36 5% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2024-05-08 2:36 UTC (permalink / raw)
To: Stephen Boyd, linux-clk
Cc: linux-arm-msm, linux-arm-kernel, Gabor Juhos, Dmitry Baryshkov,
Christian Marangi, Luca Weiss, Nathan Chancellor, Abel Vesa,
Christophe JAILLET, Krzysztof Kozlowski, Marc Gonzalez,
Satya Priya Kakitapalli
The following changes since commit 4cece764965020c22cff7665b18a012006359095:
Linux 6.9-rc1 (2024-03-24 14:10:05 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-clk-for-6.10
for you to fetch changes up to 3c5b3e17b8fd1f1add5a9477306c355fab126977:
clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs (2024-05-07 21:10:18 -0500)
----------------------------------------------------------------
Qualcomm clock updates for v6.10
Support in RCG and RCG2 are added for supporting setups where the same
frequency can be reached through multiple configurations. This is then
used to rework the IPQ8074 NSS port 5 and 6 clocks to resolve issues
with certain frequencies.
The APSS IPQ5018 PLL type is corrected, to resolve an issue with some
boards failing to boot. The configuration is further corrected, to
reduce the max CPU frequency to its expected value. This comes with a
few more cleanups and corrections for Stromer PLLs.
Kconfig dependencies are corrected for SM8650 GPU and SC8280XP camera
clock controllers.
The MSM8998 Venus clocks are corrected, to make Venus functional.
Downstream remnants related to DisplayPort are cleaned up across SM8450,
SM6350, SM8550, and SM8650.
The MSM8996 CBF PLL is cleaned up by reusing the Huayra APSS register
map.
The seemingly generic configuration of HFPLL is replaced by adding a
QCS404-specific compatible.
On SM8150 the CPUSS AHB clock source clock is removed, as this is not
controlled by Linux.
An unused field is removed in the RPM clock controller context. Missing
MODULE_DEVICE_TABLE is added to MSM8917 and MSM8953 global clock
controller drivers.
----------------------------------------------------------------
Abel Vesa (1):
clk: qcom: clk-alpha-pll: Skip reconfiguring the running Lucid Evo
Bjorn Andersson (1):
Merge branch '20240315-apss-ipq-pll-ipq5018-hang-v2-1-6fe30ada2009@gmail.com' into clk-for-6.10
Christian Marangi (3):
clk: qcom: clk-rcg: introduce support for multiple conf for same freq
clk: qcom: clk-rcg2: add support for rcg2 freq multi ops
clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf
Christophe JAILLET (1):
clk: qcom: rpm: Remove an unused field in struct rpm_cc
Dmitry Baryshkov (4):
clk: qcom: dispcc-sm8450: fix DisplayPort clocks
clk: qcom: dispcc-sm6350: fix DisplayPort clocks
clk: qcom: dispcc-sm8550: fix DisplayPort clocks
clk: qcom: dispcc-sm8650: fix DisplayPort clocks
Gabor Juhos (11):
clk: qcom: clk-alpha-pll: remove invalid Stromer register offset
clk: qcom: clk-alpha-pll: reorder Stromer register offsets
clk: qcom: clk-alpha-pll: fix kerneldoc of struct clk_alpha_pll
clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure
clk: qcom: apss-ipq-pll: reuse Stromer reg offsets from 'clk_alpha_pll_regs'
clk: qcom: apss-ipq-pll: move Huayra register map to 'clk_alpha_pll_regs'
clk: qcom: apss-ipq-pll: constify match data structures
clk: qcom: apss-ipq-pll: constify clk_init_data structures
clk: qcom: clk-cbf-8996: use HUAYRA_APSS register map for cbf_pll
clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs
Krzysztof Kozlowski (1):
clk: qcom: fix module autoloading
Luca Weiss (2):
dt-bindings: clock: qcom,hfpll: Convert to YAML
clk: qcom: hfpll: Add QCS404-specific compatible
Marc Gonzalez (1):
clk: qcom: mmcc-msm8998: fix venus clock issue
Nathan Chancellor (2):
clk: qcom: Fix SC_CAMCC_8280XP dependencies
clk: qcom: Fix SM_GPUCC_8650 dependencies
Satya Priya Kakitapalli (1):
clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src
.../devicetree/bindings/clock/qcom,hfpll.txt | 63 --------
.../devicetree/bindings/clock/qcom,hfpll.yaml | 69 +++++++++
drivers/clk/qcom/Kconfig | 2 +
drivers/clk/qcom/apss-ipq-pll.c | 75 +++++-----
drivers/clk/qcom/clk-alpha-pll.c | 24 ++-
drivers/clk/qcom/clk-alpha-pll.h | 5 +-
drivers/clk/qcom/clk-cbf-8996.c | 13 +-
drivers/clk/qcom/clk-rcg.h | 24 ++-
drivers/clk/qcom/clk-rcg2.c | 166 +++++++++++++++++++++
drivers/clk/qcom/clk-rpm.c | 1 -
drivers/clk/qcom/common.c | 18 +++
drivers/clk/qcom/common.h | 2 +
drivers/clk/qcom/dispcc-sm6350.c | 11 +-
drivers/clk/qcom/dispcc-sm8450.c | 20 +--
drivers/clk/qcom/dispcc-sm8550.c | 20 +--
drivers/clk/qcom/dispcc-sm8650.c | 20 +--
drivers/clk/qcom/gcc-ipq8074.c | 120 +++++++++------
drivers/clk/qcom/gcc-msm8917.c | 1 +
drivers/clk/qcom/gcc-msm8953.c | 1 +
drivers/clk/qcom/gcc-sm8150.c | 61 --------
drivers/clk/qcom/hfpll.c | 6 +-
drivers/clk/qcom/mmcc-msm8998.c | 8 +
22 files changed, 445 insertions(+), 285 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.yaml
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 5%]
* [GIT PULL] Qualcomm clock updates for v6.10
@ 2024-05-08 2:36 5% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2024-05-08 2:36 UTC (permalink / raw)
To: Stephen Boyd, linux-clk
Cc: linux-arm-msm, linux-arm-kernel, Gabor Juhos, Dmitry Baryshkov,
Christian Marangi, Luca Weiss, Nathan Chancellor, Abel Vesa,
Christophe JAILLET, Krzysztof Kozlowski, Marc Gonzalez,
Satya Priya Kakitapalli
The following changes since commit 4cece764965020c22cff7665b18a012006359095:
Linux 6.9-rc1 (2024-03-24 14:10:05 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-clk-for-6.10
for you to fetch changes up to 3c5b3e17b8fd1f1add5a9477306c355fab126977:
clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs (2024-05-07 21:10:18 -0500)
----------------------------------------------------------------
Qualcomm clock updates for v6.10
Support in RCG and RCG2 are added for supporting setups where the same
frequency can be reached through multiple configurations. This is then
used to rework the IPQ8074 NSS port 5 and 6 clocks to resolve issues
with certain frequencies.
The APSS IPQ5018 PLL type is corrected, to resolve an issue with some
boards failing to boot. The configuration is further corrected, to
reduce the max CPU frequency to its expected value. This comes with a
few more cleanups and corrections for Stromer PLLs.
Kconfig dependencies are corrected for SM8650 GPU and SC8280XP camera
clock controllers.
The MSM8998 Venus clocks are corrected, to make Venus functional.
Downstream remnants related to DisplayPort are cleaned up across SM8450,
SM6350, SM8550, and SM8650.
The MSM8996 CBF PLL is cleaned up by reusing the Huayra APSS register
map.
The seemingly generic configuration of HFPLL is replaced by adding a
QCS404-specific compatible.
On SM8150 the CPUSS AHB clock source clock is removed, as this is not
controlled by Linux.
An unused field is removed in the RPM clock controller context. Missing
MODULE_DEVICE_TABLE is added to MSM8917 and MSM8953 global clock
controller drivers.
----------------------------------------------------------------
Abel Vesa (1):
clk: qcom: clk-alpha-pll: Skip reconfiguring the running Lucid Evo
Bjorn Andersson (1):
Merge branch '20240315-apss-ipq-pll-ipq5018-hang-v2-1-6fe30ada2009@gmail.com' into clk-for-6.10
Christian Marangi (3):
clk: qcom: clk-rcg: introduce support for multiple conf for same freq
clk: qcom: clk-rcg2: add support for rcg2 freq multi ops
clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf
Christophe JAILLET (1):
clk: qcom: rpm: Remove an unused field in struct rpm_cc
Dmitry Baryshkov (4):
clk: qcom: dispcc-sm8450: fix DisplayPort clocks
clk: qcom: dispcc-sm6350: fix DisplayPort clocks
clk: qcom: dispcc-sm8550: fix DisplayPort clocks
clk: qcom: dispcc-sm8650: fix DisplayPort clocks
Gabor Juhos (11):
clk: qcom: clk-alpha-pll: remove invalid Stromer register offset
clk: qcom: clk-alpha-pll: reorder Stromer register offsets
clk: qcom: clk-alpha-pll: fix kerneldoc of struct clk_alpha_pll
clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure
clk: qcom: apss-ipq-pll: reuse Stromer reg offsets from 'clk_alpha_pll_regs'
clk: qcom: apss-ipq-pll: move Huayra register map to 'clk_alpha_pll_regs'
clk: qcom: apss-ipq-pll: constify match data structures
clk: qcom: apss-ipq-pll: constify clk_init_data structures
clk: qcom: clk-cbf-8996: use HUAYRA_APSS register map for cbf_pll
clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs
Krzysztof Kozlowski (1):
clk: qcom: fix module autoloading
Luca Weiss (2):
dt-bindings: clock: qcom,hfpll: Convert to YAML
clk: qcom: hfpll: Add QCS404-specific compatible
Marc Gonzalez (1):
clk: qcom: mmcc-msm8998: fix venus clock issue
Nathan Chancellor (2):
clk: qcom: Fix SC_CAMCC_8280XP dependencies
clk: qcom: Fix SM_GPUCC_8650 dependencies
Satya Priya Kakitapalli (1):
clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src
.../devicetree/bindings/clock/qcom,hfpll.txt | 63 --------
.../devicetree/bindings/clock/qcom,hfpll.yaml | 69 +++++++++
drivers/clk/qcom/Kconfig | 2 +
drivers/clk/qcom/apss-ipq-pll.c | 75 +++++-----
drivers/clk/qcom/clk-alpha-pll.c | 24 ++-
drivers/clk/qcom/clk-alpha-pll.h | 5 +-
drivers/clk/qcom/clk-cbf-8996.c | 13 +-
drivers/clk/qcom/clk-rcg.h | 24 ++-
drivers/clk/qcom/clk-rcg2.c | 166 +++++++++++++++++++++
drivers/clk/qcom/clk-rpm.c | 1 -
drivers/clk/qcom/common.c | 18 +++
drivers/clk/qcom/common.h | 2 +
drivers/clk/qcom/dispcc-sm6350.c | 11 +-
drivers/clk/qcom/dispcc-sm8450.c | 20 +--
drivers/clk/qcom/dispcc-sm8550.c | 20 +--
drivers/clk/qcom/dispcc-sm8650.c | 20 +--
drivers/clk/qcom/gcc-ipq8074.c | 120 +++++++++------
drivers/clk/qcom/gcc-msm8917.c | 1 +
drivers/clk/qcom/gcc-msm8953.c | 1 +
drivers/clk/qcom/gcc-sm8150.c | 61 --------
drivers/clk/qcom/hfpll.c | 6 +-
drivers/clk/qcom/mmcc-msm8998.c | 8 +
22 files changed, 445 insertions(+), 285 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.yaml
^ permalink raw reply [relevance 5%]
* [PATCH v14 3/4] clk: qcom: common: commonize qcom_cc_really_probe
2024-05-07 13:05 6% [PATCH v14 0/4] add clock controller of qca8386/qca8084 Luo Jie
@ 2024-05-07 13:05 10% ` Luo Jie
0 siblings, 0 replies; 200+ results
From: Luo Jie @ 2024-05-07 13:05 UTC (permalink / raw)
To: andersson, mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel,
quic_srichara, Bryan O'Donoghue
The previous wrapper qcom_cc_really_probe takes the platform
device as parameter, which is limited to platform driver.
As for qca8k clock controller driver, which is registered as
the MDIO device, which also follows the qcom clock framework.
To commonize qcom_cc_really_probe, updating it to take the
struct device as parameter, so that the qcom_cc_really_probe
can be utilized by the previous platform device and the new
added MDIO device.
Also update the current clock controller drivers to take
&pdev->dev as parameter when calling qcom_cc_really_probe.
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
drivers/clk/qcom/apss-ipq6018.c | 2 +-
drivers/clk/qcom/camcc-sc7180.c | 2 +-
drivers/clk/qcom/camcc-sc7280.c | 2 +-
drivers/clk/qcom/camcc-sc8280xp.c | 2 +-
drivers/clk/qcom/camcc-sdm845.c | 2 +-
drivers/clk/qcom/camcc-sm6350.c | 2 +-
drivers/clk/qcom/camcc-sm8250.c | 2 +-
drivers/clk/qcom/camcc-sm8450.c | 2 +-
drivers/clk/qcom/camcc-sm8550.c | 2 +-
drivers/clk/qcom/camcc-x1e80100.c | 2 +-
drivers/clk/qcom/common.c | 7 +++----
drivers/clk/qcom/common.h | 2 +-
drivers/clk/qcom/dispcc-qcm2290.c | 2 +-
drivers/clk/qcom/dispcc-sc7180.c | 2 +-
drivers/clk/qcom/dispcc-sc7280.c | 2 +-
drivers/clk/qcom/dispcc-sc8280xp.c | 2 +-
drivers/clk/qcom/dispcc-sdm845.c | 2 +-
drivers/clk/qcom/dispcc-sm6115.c | 2 +-
drivers/clk/qcom/dispcc-sm6125.c | 2 +-
drivers/clk/qcom/dispcc-sm6350.c | 2 +-
drivers/clk/qcom/dispcc-sm6375.c | 2 +-
drivers/clk/qcom/dispcc-sm8250.c | 2 +-
drivers/clk/qcom/dispcc-sm8450.c | 2 +-
drivers/clk/qcom/dispcc-sm8550.c | 2 +-
drivers/clk/qcom/dispcc-sm8650.c | 2 +-
drivers/clk/qcom/dispcc-x1e80100.c | 2 +-
drivers/clk/qcom/ecpricc-qdu1000.c | 2 +-
drivers/clk/qcom/gcc-ipq5018.c | 2 +-
drivers/clk/qcom/gcc-ipq6018.c | 2 +-
drivers/clk/qcom/gcc-ipq8074.c | 2 +-
drivers/clk/qcom/gcc-mdm9607.c | 2 +-
drivers/clk/qcom/gcc-mdm9615.c | 2 +-
drivers/clk/qcom/gcc-msm8917.c | 2 +-
drivers/clk/qcom/gcc-msm8939.c | 2 +-
drivers/clk/qcom/gcc-msm8953.c | 2 +-
drivers/clk/qcom/gcc-msm8976.c | 2 +-
drivers/clk/qcom/gcc-msm8996.c | 2 +-
drivers/clk/qcom/gcc-msm8998.c | 2 +-
drivers/clk/qcom/gcc-qcm2290.c | 2 +-
drivers/clk/qcom/gcc-qcs404.c | 2 +-
drivers/clk/qcom/gcc-qdu1000.c | 2 +-
drivers/clk/qcom/gcc-sa8775p.c | 2 +-
drivers/clk/qcom/gcc-sc7180.c | 2 +-
drivers/clk/qcom/gcc-sc7280.c | 2 +-
drivers/clk/qcom/gcc-sc8180x.c | 2 +-
drivers/clk/qcom/gcc-sc8280xp.c | 2 +-
drivers/clk/qcom/gcc-sdm660.c | 2 +-
drivers/clk/qcom/gcc-sdm845.c | 2 +-
drivers/clk/qcom/gcc-sdx55.c | 2 +-
drivers/clk/qcom/gcc-sdx65.c | 2 +-
drivers/clk/qcom/gcc-sdx75.c | 2 +-
drivers/clk/qcom/gcc-sm4450.c | 2 +-
drivers/clk/qcom/gcc-sm6115.c | 2 +-
drivers/clk/qcom/gcc-sm6125.c | 2 +-
drivers/clk/qcom/gcc-sm6350.c | 2 +-
drivers/clk/qcom/gcc-sm6375.c | 2 +-
drivers/clk/qcom/gcc-sm7150.c | 2 +-
drivers/clk/qcom/gcc-sm8150.c | 2 +-
drivers/clk/qcom/gcc-sm8250.c | 2 +-
drivers/clk/qcom/gcc-sm8350.c | 2 +-
drivers/clk/qcom/gcc-sm8450.c | 2 +-
drivers/clk/qcom/gcc-sm8550.c | 2 +-
drivers/clk/qcom/gcc-sm8650.c | 2 +-
drivers/clk/qcom/gcc-x1e80100.c | 2 +-
drivers/clk/qcom/gpucc-msm8998.c | 2 +-
drivers/clk/qcom/gpucc-sa8775p.c | 2 +-
drivers/clk/qcom/gpucc-sc7180.c | 2 +-
drivers/clk/qcom/gpucc-sc7280.c | 2 +-
drivers/clk/qcom/gpucc-sc8280xp.c | 2 +-
drivers/clk/qcom/gpucc-sdm660.c | 2 +-
drivers/clk/qcom/gpucc-sdm845.c | 2 +-
drivers/clk/qcom/gpucc-sm6115.c | 2 +-
drivers/clk/qcom/gpucc-sm6125.c | 2 +-
drivers/clk/qcom/gpucc-sm6350.c | 2 +-
drivers/clk/qcom/gpucc-sm6375.c | 2 +-
drivers/clk/qcom/gpucc-sm8150.c | 2 +-
drivers/clk/qcom/gpucc-sm8250.c | 2 +-
drivers/clk/qcom/gpucc-sm8350.c | 2 +-
drivers/clk/qcom/gpucc-sm8450.c | 2 +-
drivers/clk/qcom/gpucc-sm8550.c | 2 +-
drivers/clk/qcom/gpucc-sm8650.c | 2 +-
drivers/clk/qcom/gpucc-x1e80100.c | 2 +-
drivers/clk/qcom/lcc-ipq806x.c | 2 +-
drivers/clk/qcom/lcc-msm8960.c | 2 +-
drivers/clk/qcom/lpassaudiocc-sc7280.c | 4 ++--
drivers/clk/qcom/lpasscorecc-sc7180.c | 2 +-
drivers/clk/qcom/lpasscorecc-sc7280.c | 2 +-
drivers/clk/qcom/mmcc-msm8960.c | 2 +-
drivers/clk/qcom/mmcc-msm8974.c | 2 +-
drivers/clk/qcom/mmcc-msm8994.c | 2 +-
drivers/clk/qcom/mmcc-msm8996.c | 2 +-
drivers/clk/qcom/mmcc-msm8998.c | 2 +-
drivers/clk/qcom/mmcc-sdm660.c | 2 +-
drivers/clk/qcom/tcsrcc-sm8550.c | 2 +-
drivers/clk/qcom/videocc-sc7180.c | 2 +-
drivers/clk/qcom/videocc-sc7280.c | 2 +-
drivers/clk/qcom/videocc-sdm845.c | 2 +-
drivers/clk/qcom/videocc-sm8150.c | 2 +-
drivers/clk/qcom/videocc-sm8250.c | 2 +-
drivers/clk/qcom/videocc-sm8350.c | 2 +-
drivers/clk/qcom/videocc-sm8450.c | 2 +-
drivers/clk/qcom/videocc-sm8550.c | 2 +-
102 files changed, 105 insertions(+), 106 deletions(-)
diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
index e6295b832686..c89d126ebac3 100644
--- a/drivers/clk/qcom/apss-ipq6018.c
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -123,7 +123,7 @@ static int apss_ipq6018_probe(struct platform_device *pdev)
if (!regmap)
return -ENODEV;
- ret = qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &apss_ipq6018_desc, regmap);
if (ret)
return ret;
diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
index a78808b22b03..10e924cd533d 100644
--- a/drivers/clk/qcom/camcc-sc7180.c
+++ b/drivers/clk/qcom/camcc-sc7180.c
@@ -1680,7 +1680,7 @@ static int cam_cc_sc7180_probe(struct platform_device *pdev)
clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
- ret = qcom_cc_really_probe(pdev, &cam_cc_sc7180_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sc7180_desc, regmap);
pm_runtime_put(&pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register CAM CC clocks\n");
diff --git a/drivers/clk/qcom/camcc-sc7280.c b/drivers/clk/qcom/camcc-sc7280.c
index d89ddb2298e3..1d6401ad4e4a 100644
--- a/drivers/clk/qcom/camcc-sc7280.c
+++ b/drivers/clk/qcom/camcc-sc7280.c
@@ -2457,7 +2457,7 @@ static int cam_cc_sc7280_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
clk_lucid_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
- return qcom_cc_really_probe(pdev, &cam_cc_sc7280_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &cam_cc_sc7280_desc, regmap);
}
static struct platform_driver cam_cc_sc7280_driver = {
diff --git a/drivers/clk/qcom/camcc-sc8280xp.c b/drivers/clk/qcom/camcc-sc8280xp.c
index 8e26ec2def73..065a7568e6ab 100644
--- a/drivers/clk/qcom/camcc-sc8280xp.c
+++ b/drivers/clk/qcom/camcc-sc8280xp.c
@@ -3034,7 +3034,7 @@ static int camcc_sc8280xp_probe(struct platform_device *pdev)
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */
- ret = qcom_cc_really_probe(pdev, &camcc_sc8280xp_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &camcc_sc8280xp_desc, regmap);
if (ret)
goto err_disable;
diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
index 8466d03e0d05..40022a10f8c0 100644
--- a/drivers/clk/qcom/camcc-sdm845.c
+++ b/drivers/clk/qcom/camcc-sdm845.c
@@ -1735,7 +1735,7 @@ static int cam_cc_sdm845_probe(struct platform_device *pdev)
cam_cc_pll_config.l = 0x14;
clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll_config);
- return qcom_cc_really_probe(pdev, &cam_cc_sdm845_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &cam_cc_sdm845_desc, regmap);
}
static struct platform_driver cam_cc_sdm845_driver = {
diff --git a/drivers/clk/qcom/camcc-sm6350.c b/drivers/clk/qcom/camcc-sm6350.c
index e4e7b308ecf1..320a72c37f9a 100644
--- a/drivers/clk/qcom/camcc-sm6350.c
+++ b/drivers/clk/qcom/camcc-sm6350.c
@@ -1879,7 +1879,7 @@ static int camcc_sm6350_probe(struct platform_device *pdev)
clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config);
clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config);
- return qcom_cc_really_probe(pdev, &camcc_sm6350_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &camcc_sm6350_desc, regmap);
}
static struct platform_driver camcc_sm6350_driver = {
diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c
index 9b32c56a5bc5..6ac85b96a1ea 100644
--- a/drivers/clk/qcom/camcc-sm8250.c
+++ b/drivers/clk/qcom/camcc-sm8250.c
@@ -2433,7 +2433,7 @@ static int cam_cc_sm8250_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
- return qcom_cc_really_probe(pdev, &cam_cc_sm8250_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8250_desc, regmap);
}
static struct platform_driver cam_cc_sm8250_driver = {
diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c
index 51338a2884d2..26b78eed15ef 100644
--- a/drivers/clk/qcom/camcc-sm8450.c
+++ b/drivers/clk/qcom/camcc-sm8450.c
@@ -2839,7 +2839,7 @@ static int cam_cc_sm8450_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
- return qcom_cc_really_probe(pdev, &cam_cc_sm8450_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8450_desc, regmap);
}
static struct platform_driver cam_cc_sm8450_driver = {
diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
index 1ef59a96f664..eac850bb690a 100644
--- a/drivers/clk/qcom/camcc-sm8550.c
+++ b/drivers/clk/qcom/camcc-sm8550.c
@@ -3540,7 +3540,7 @@ static int cam_cc_sm8550_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x1419c); /* CAM_CC_GDSC_CLK */
qcom_branch_set_clk_en(regmap, 0x142cc); /* CAM_CC_SLEEP_CLK */
- ret = qcom_cc_really_probe(pdev, &cam_cc_sm8550_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8550_desc, regmap);
pm_runtime_put(&pdev->dev);
diff --git a/drivers/clk/qcom/camcc-x1e80100.c b/drivers/clk/qcom/camcc-x1e80100.c
index 46bb225906bf..85e76c7712ad 100644
--- a/drivers/clk/qcom/camcc-x1e80100.c
+++ b/drivers/clk/qcom/camcc-x1e80100.c
@@ -2466,7 +2466,7 @@ static int cam_cc_x1e80100_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x13a9c); /* CAM_CC_GDSC_CLK */
qcom_branch_set_clk_en(regmap, 0x13ab8); /* CAM_CC_SLEEP_CLK */
- ret = qcom_cc_really_probe(pdev, &cam_cc_x1e80100_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_x1e80100_desc, regmap);
pm_runtime_put(&pdev->dev);
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 48f81e3a5e80..9cf919c14324 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -252,11 +252,10 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
}
-int qcom_cc_really_probe(struct platform_device *pdev,
+int qcom_cc_really_probe(struct device *dev,
const struct qcom_cc_desc *desc, struct regmap *regmap)
{
int i, ret;
- struct device *dev = &pdev->dev;
struct qcom_reset_controller *reset;
struct qcom_cc *cc;
struct gdsc_desc *scd;
@@ -333,7 +332,7 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- return qcom_cc_really_probe(pdev, desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, desc, regmap);
}
EXPORT_SYMBOL_GPL(qcom_cc_probe);
@@ -351,7 +350,7 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- return qcom_cc_really_probe(pdev, desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, desc, regmap);
}
EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 2d4a8a837e6c..d048bdeeba10 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -60,7 +60,7 @@ extern int qcom_cc_register_sleep_clk(struct device *dev);
extern struct regmap *qcom_cc_map(struct platform_device *pdev,
const struct qcom_cc_desc *desc);
-extern int qcom_cc_really_probe(struct platform_device *pdev,
+extern int qcom_cc_really_probe(struct device *dev,
const struct qcom_cc_desc *desc,
struct regmap *regmap);
extern int qcom_cc_probe(struct platform_device *pdev,
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
index 654a10d53e5c..449ffea2295d 100644
--- a/drivers/clk/qcom/dispcc-qcm2290.c
+++ b/drivers/clk/qcom/dispcc-qcm2290.c
@@ -522,7 +522,7 @@ static int disp_cc_qcm2290_probe(struct platform_device *pdev)
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */
- ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_qcm2290_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
return ret;
diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c
index 38d7859981c7..4710247be530 100644
--- a/drivers/clk/qcom/dispcc-sc7180.c
+++ b/drivers/clk/qcom/dispcc-sc7180.c
@@ -713,7 +713,7 @@ static int disp_cc_sc7180_probe(struct platform_device *pdev)
clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config);
- return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &disp_cc_sc7180_desc, regmap);
}
static struct platform_driver disp_cc_sc7180_driver = {
diff --git a/drivers/clk/qcom/dispcc-sc7280.c b/drivers/clk/qcom/dispcc-sc7280.c
index fbeb8fccb99a..db0745954894 100644
--- a/drivers/clk/qcom/dispcc-sc7280.c
+++ b/drivers/clk/qcom/dispcc-sc7280.c
@@ -881,7 +881,7 @@ static int disp_cc_sc7280_probe(struct platform_device *pdev)
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */
- return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &disp_cc_sc7280_desc, regmap);
}
static struct platform_driver disp_cc_sc7280_driver = {
diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-sc8280xp.c
index 91172f5b2f15..f1ca9ae0b33f 100644
--- a/drivers/clk/qcom/dispcc-sc8280xp.c
+++ b/drivers/clk/qcom/dispcc-sc8280xp.c
@@ -3172,7 +3172,7 @@ static int disp_cc_sc8280xp_probe(struct platform_device *pdev)
clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL1]), regmap, &disp_cc_pll1_config);
clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL2]), regmap, &disp_cc_pll2_config);
- ret = qcom_cc_really_probe(pdev, desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register display clock controller\n");
goto out_pm_runtime_put;
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
index b84fdd17c3d8..e6139e8f74dc 100644
--- a/drivers/clk/qcom/dispcc-sdm845.c
+++ b/drivers/clk/qcom/dispcc-sdm845.c
@@ -863,7 +863,7 @@ static int disp_cc_sdm845_probe(struct platform_device *pdev)
/* Enable hardware clock gating for DSI and MDP clocks */
regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
- return qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &disp_cc_sdm845_desc, regmap);
}
static struct platform_driver disp_cc_sdm845_driver = {
diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c
index bd07f26af35a..939887f82ecc 100644
--- a/drivers/clk/qcom/dispcc-sm6115.c
+++ b/drivers/clk/qcom/dispcc-sm6115.c
@@ -586,7 +586,7 @@ static int disp_cc_sm6115_probe(struct platform_device *pdev)
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */
- ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6115_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
return ret;
diff --git a/drivers/clk/qcom/dispcc-sm6125.c b/drivers/clk/qcom/dispcc-sm6125.c
index 1cc5f220a3c4..9a35d1ec426f 100644
--- a/drivers/clk/qcom/dispcc-sm6125.c
+++ b/drivers/clk/qcom/dispcc-sm6125.c
@@ -682,7 +682,7 @@ static int disp_cc_sm6125_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
- return qcom_cc_really_probe(pdev, &disp_cc_sm6125_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6125_desc, regmap);
}
static struct platform_driver disp_cc_sm6125_driver = {
diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c
index e4b7464c4d0e..9baa2522398b 100644
--- a/drivers/clk/qcom/dispcc-sm6350.c
+++ b/drivers/clk/qcom/dispcc-sm6350.c
@@ -761,7 +761,7 @@ static int disp_cc_sm6350_probe(struct platform_device *pdev)
clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
- return qcom_cc_really_probe(pdev, &disp_cc_sm6350_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6350_desc, regmap);
}
static struct platform_driver disp_cc_sm6350_driver = {
diff --git a/drivers/clk/qcom/dispcc-sm6375.c b/drivers/clk/qcom/dispcc-sm6375.c
index d81d4e3c0b0d..61a4bba7d4bf 100644
--- a/drivers/clk/qcom/dispcc-sm6375.c
+++ b/drivers/clk/qcom/dispcc-sm6375.c
@@ -583,7 +583,7 @@ static int disp_cc_sm6375_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
- return qcom_cc_really_probe(pdev, &disp_cc_sm6375_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6375_desc, regmap);
}
static struct platform_driver disp_cc_sm6375_driver = {
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
index 43307c8a342c..5a09009b7289 100644
--- a/drivers/clk/qcom/dispcc-sm8250.c
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -1366,7 +1366,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */
- ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8250_desc, regmap);
pm_runtime_put(&pdev->dev);
diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
index 49bb4f58c391..0987bf8f5d0f 100644
--- a/drivers/clk/qcom/dispcc-sm8450.c
+++ b/drivers/clk/qcom/dispcc-sm8450.c
@@ -1778,7 +1778,7 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev)
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */
- ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8450_desc, regmap);
if (ret)
goto err_put_rpm;
diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c
index 38ecea805503..5b62dd2ced56 100644
--- a/drivers/clk/qcom/dispcc-sm8550.c
+++ b/drivers/clk/qcom/dispcc-sm8550.c
@@ -1771,7 +1771,7 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev)
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */
- ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8550_desc, regmap);
if (ret)
goto err_put_rpm;
diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c
index 3eb64bcad487..53a311d4f373 100644
--- a/drivers/clk/qcom/dispcc-sm8650.c
+++ b/drivers/clk/qcom/dispcc-sm8650.c
@@ -1768,7 +1768,7 @@ static int disp_cc_sm8650_probe(struct platform_device *pdev)
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */
- ret = qcom_cc_really_probe(pdev, &disp_cc_sm8650_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8650_desc, regmap);
if (ret)
goto err_put_rpm;
diff --git a/drivers/clk/qcom/dispcc-x1e80100.c b/drivers/clk/qcom/dispcc-x1e80100.c
index 0b2ee6456762..40069eba41f2 100644
--- a/drivers/clk/qcom/dispcc-x1e80100.c
+++ b/drivers/clk/qcom/dispcc-x1e80100.c
@@ -1680,7 +1680,7 @@ static int disp_cc_x1e80100_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0xe074); /* DISP_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */
- ret = qcom_cc_really_probe(pdev, &disp_cc_x1e80100_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_x1e80100_desc, regmap);
if (ret)
goto err_put_rpm;
diff --git a/drivers/clk/qcom/ecpricc-qdu1000.c b/drivers/clk/qcom/ecpricc-qdu1000.c
index c628054a7025..dbc11260479b 100644
--- a/drivers/clk/qcom/ecpricc-qdu1000.c
+++ b/drivers/clk/qcom/ecpricc-qdu1000.c
@@ -2439,7 +2439,7 @@ static int ecpri_cc_qdu1000_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&ecpri_cc_pll0, regmap, &ecpri_cc_pll0_config);
clk_lucid_evo_pll_configure(&ecpri_cc_pll1, regmap, &ecpri_cc_pll1_config);
- return qcom_cc_really_probe(pdev, &ecpri_cc_qdu1000_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &ecpri_cc_qdu1000_desc, regmap);
}
static struct platform_driver ecpri_cc_qdu1000_driver = {
diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
index c1732d70e3a2..70f5dcb96700 100644
--- a/drivers/clk/qcom/gcc-ipq5018.c
+++ b/drivers/clk/qcom/gcc-ipq5018.c
@@ -3698,7 +3698,7 @@ static int gcc_ipq5018_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
- return qcom_cc_really_probe(pdev, &ipq5018_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &ipq5018_desc, regmap);
}
static struct platform_driver gcc_ipq5018_driver = {
diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index 7e69de34c310..9e5885101366 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -4642,7 +4642,7 @@ static int gcc_ipq6018_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
&nss_crypto_pll_config);
- return qcom_cc_really_probe(pdev, &gcc_ipq6018_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_ipq6018_desc, regmap);
}
static struct platform_driver gcc_ipq6018_driver = {
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index d2be56c5892d..32fd01ef469a 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4760,7 +4760,7 @@ static int gcc_ipq8074_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
&nss_crypto_pll_config);
- return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_ipq8074_desc, regmap);
}
static struct platform_driver gcc_ipq8074_driver = {
diff --git a/drivers/clk/qcom/gcc-mdm9607.c b/drivers/clk/qcom/gcc-mdm9607.c
index fb290e73ce94..6e6068b168e6 100644
--- a/drivers/clk/qcom/gcc-mdm9607.c
+++ b/drivers/clk/qcom/gcc-mdm9607.c
@@ -1604,7 +1604,7 @@ static int gcc_mdm9607_probe(struct platform_device *pdev)
/* Vote for GPLL0 to turn on. Needed by acpuclock. */
regmap_update_bits(regmap, 0x45000, BIT(0), BIT(0));
- return qcom_cc_really_probe(pdev, &gcc_mdm9607_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_mdm9607_desc, regmap);
}
static struct platform_driver gcc_mdm9607_driver = {
diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
index aec7c4a1d3de..33987b957737 100644
--- a/drivers/clk/qcom/gcc-mdm9615.c
+++ b/drivers/clk/qcom/gcc-mdm9615.c
@@ -1736,7 +1736,7 @@ static int gcc_mdm9615_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- return qcom_cc_really_probe(pdev, &gcc_mdm9615_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_mdm9615_desc, regmap);
}
static struct platform_driver gcc_mdm9615_driver = {
diff --git a/drivers/clk/qcom/gcc-msm8917.c b/drivers/clk/qcom/gcc-msm8917.c
index f2b8729e4198..3e2a2ae2ee6e 100644
--- a/drivers/clk/qcom/gcc-msm8917.c
+++ b/drivers/clk/qcom/gcc-msm8917.c
@@ -3270,7 +3270,7 @@ static int gcc_msm8917_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config);
- return qcom_cc_really_probe(pdev, gcc_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, gcc_desc, regmap);
}
static const struct of_device_id gcc_msm8917_match_table[] = {
diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c
index 7b9a3e99b589..7431c9a65044 100644
--- a/drivers/clk/qcom/gcc-msm8939.c
+++ b/drivers/clk/qcom/gcc-msm8939.c
@@ -4108,7 +4108,7 @@ static int gcc_msm8939_probe(struct platform_device *pdev)
clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
- return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_msm8939_desc, regmap);
}
static struct platform_driver gcc_msm8939_driver = {
diff --git a/drivers/clk/qcom/gcc-msm8953.c b/drivers/clk/qcom/gcc-msm8953.c
index 7563bff58118..855a61966f3e 100644
--- a/drivers/clk/qcom/gcc-msm8953.c
+++ b/drivers/clk/qcom/gcc-msm8953.c
@@ -4220,7 +4220,7 @@ static int gcc_msm8953_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config);
- return qcom_cc_really_probe(pdev, &gcc_msm8953_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_msm8953_desc, regmap);
}
static const struct of_device_id gcc_msm8953_match_table[] = {
diff --git a/drivers/clk/qcom/gcc-msm8976.c b/drivers/clk/qcom/gcc-msm8976.c
index f60a8171972b..dfc343357ed0 100644
--- a/drivers/clk/qcom/gcc-msm8976.c
+++ b/drivers/clk/qcom/gcc-msm8976.c
@@ -4129,7 +4129,7 @@ static int gcc_msm8976_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_msm8976_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_msm8976_desc, regmap);
}
static struct platform_driver gcc_msm8976_driver = {
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index e7b03a17514a..4fc667b94cf2 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -3620,7 +3620,7 @@ static int gcc_msm8996_probe(struct platform_device *pdev)
*/
regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
- return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_msm8996_desc, regmap);
}
static struct platform_driver gcc_msm8996_driver = {
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index cad7f1c7789c..434ba6e21af1 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -3292,7 +3292,7 @@ static int gcc_msm8998_probe(struct platform_device *pdev)
regmap_write(regmap, GCC_MMSS_MISC, 0x10003);
regmap_write(regmap, GCC_GPU_MISC, 0x10003);
- return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_msm8998_desc, regmap);
}
static const struct of_device_id gcc_msm8998_match_table[] = {
diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c
index 48995e50c6bd..9a6703365e61 100644
--- a/drivers/clk/qcom/gcc-qcm2290.c
+++ b/drivers/clk/qcom/gcc-qcm2290.c
@@ -2994,7 +2994,7 @@ static int gcc_qcm2290_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config);
clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config);
- return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_qcm2290_desc, regmap);
}
static struct platform_driver gcc_qcm2290_driver = {
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index a39c4990b29d..c3cfd572e7c1 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -2824,7 +2824,7 @@ static int gcc_qcs404_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
- return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_qcs404_desc, regmap);
}
static struct platform_driver gcc_qcs404_driver = {
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 9f42d2601464..dbe9e9437939 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -2674,7 +2674,7 @@ static int gcc_qdu1000_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &gcc_qdu1000_desc, regmap);
if (ret)
return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n");
diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c
index 5bcbfbf52cb9..9f31ce4cea18 100644
--- a/drivers/clk/qcom/gcc-sa8775p.c
+++ b/drivers/clk/qcom/gcc-sa8775p.c
@@ -4753,7 +4753,7 @@ static int gcc_sa8775p_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */
- return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sa8775p_desc, regmap);
}
static struct platform_driver gcc_sa8775p_driver = {
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index 6a5f785c0ced..4a49ad7a9e5b 100644
--- a/drivers/clk/qcom/gcc-sc7180.c
+++ b/drivers/clk/qcom/gcc-sc7180.c
@@ -2458,7 +2458,7 @@ static int gcc_sc7180_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sc7180_desc, regmap);
}
static struct platform_driver gcc_sc7180_driver = {
diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
index f45a8318900c..a9d45d280062 100644
--- a/drivers/clk/qcom/gcc-sc7280.c
+++ b/drivers/clk/qcom/gcc-sc7280.c
@@ -3468,7 +3468,7 @@ static int gcc_sc7280_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sc7280_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sc7280_desc, regmap);
}
static struct platform_driver gcc_sc7280_driver = {
diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c
index 5261bfc92b3d..1946b93fdfd3 100644
--- a/drivers/clk/qcom/gcc-sc8180x.c
+++ b/drivers/clk/qcom/gcc-sc8180x.c
@@ -4623,7 +4623,7 @@ static int gcc_sc8180x_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
- return qcom_cc_really_probe(pdev, &gcc_sc8180x_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sc8180x_desc, regmap);
}
static struct platform_driver gcc_sc8180x_driver = {
diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c
index 082d7b5504eb..5f11760cf73f 100644
--- a/drivers/clk/qcom/gcc-sc8280xp.c
+++ b/drivers/clk/qcom/gcc-sc8280xp.c
@@ -7558,7 +7558,7 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev)
if (ret)
goto err_put_rpm;
- ret = qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &gcc_sc8280xp_desc, regmap);
if (ret)
goto err_put_rpm;
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index c4fe70871b6d..df79298a1a25 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -2474,7 +2474,7 @@ static int gcc_sdm660_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sdm660_desc, regmap);
}
static struct platform_driver gcc_sdm660_driver = {
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index ea4c3bf4fb9b..dc3aa7014c3e 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -4011,7 +4011,7 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
return ret;
gcc_desc = of_device_get_match_data(&pdev->dev);
- return qcom_cc_really_probe(pdev, gcc_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, gcc_desc, regmap);
}
static struct platform_driver gcc_sdm845_driver = {
diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c
index 26279b8d321a..84c507656e8f 100644
--- a/drivers/clk/qcom/gcc-sdx55.c
+++ b/drivers/clk/qcom/gcc-sdx55.c
@@ -1616,7 +1616,7 @@ static int gcc_sdx55_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */
- return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sdx55_desc, regmap);
}
static struct platform_driver gcc_sdx55_driver = {
diff --git a/drivers/clk/qcom/gcc-sdx65.c b/drivers/clk/qcom/gcc-sdx65.c
index 8fde6463574b..fe297c606f97 100644
--- a/drivers/clk/qcom/gcc-sdx65.c
+++ b/drivers/clk/qcom/gcc-sdx65.c
@@ -1580,7 +1580,7 @@ static int gcc_sdx65_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */
- return qcom_cc_really_probe(pdev, &gcc_sdx65_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sdx65_desc, regmap);
}
static struct platform_driver gcc_sdx65_driver = {
diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c
index c51338f08ef1..453a6bf8e878 100644
--- a/drivers/clk/qcom/gcc-sdx75.c
+++ b/drivers/clk/qcom/gcc-sdx75.c
@@ -2940,7 +2940,7 @@ static int gcc_sdx75_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x3e004); /* GCC_AHB_PCIE_LINK_CLK */
qcom_branch_set_clk_en(regmap, 0x3e008); /* GCC_XO_PCIE_LINK_CLK */
- return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sdx75_desc, regmap);
}
static struct platform_driver gcc_sdx75_driver = {
diff --git a/drivers/clk/qcom/gcc-sm4450.c b/drivers/clk/qcom/gcc-sm4450.c
index 062e55e98156..e2d9e4691c5b 100644
--- a/drivers/clk/qcom/gcc-sm4450.c
+++ b/drivers/clk/qcom/gcc-sm4450.c
@@ -2861,7 +2861,7 @@ static int gcc_sm4450_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21));
- return qcom_cc_really_probe(pdev, &gcc_sm4450_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm4450_desc, regmap);
}
static struct platform_driver gcc_sm4450_driver = {
diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c
index 13e521cd4259..f71752a50d03 100644
--- a/drivers/clk/qcom/gcc-sm6115.c
+++ b/drivers/clk/qcom/gcc-sm6115.c
@@ -3513,7 +3513,7 @@ static int gcc_sm6115_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config);
clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config);
- return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm6115_desc, regmap);
}
static struct platform_driver gcc_sm6115_driver = {
diff --git a/drivers/clk/qcom/gcc-sm6125.c b/drivers/clk/qcom/gcc-sm6125.c
index da554efee2ce..07bb1e5c4a30 100644
--- a/drivers/clk/qcom/gcc-sm6125.c
+++ b/drivers/clk/qcom/gcc-sm6125.c
@@ -4161,7 +4161,7 @@ static int gcc_sm6125_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sm6125_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm6125_desc, regmap);
}
static struct platform_driver gcc_sm6125_driver = {
diff --git a/drivers/clk/qcom/gcc-sm6350.c b/drivers/clk/qcom/gcc-sm6350.c
index cf4a7b6e0b23..0dcc8eeb77e6 100644
--- a/drivers/clk/qcom/gcc-sm6350.c
+++ b/drivers/clk/qcom/gcc-sm6350.c
@@ -2559,7 +2559,7 @@ static int gcc_sm6350_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sm6350_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm6350_desc, regmap);
}
static struct platform_driver gcc_sm6350_driver = {
diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c
index 84639d5b89bf..fe83d6e037e7 100644
--- a/drivers/clk/qcom/gcc-sm6375.c
+++ b/drivers/clk/qcom/gcc-sm6375.c
@@ -3892,7 +3892,7 @@ static int gcc_sm6375_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config);
clk_zonda_pll_configure(&gpll9, regmap, &gpll9_config);
- return qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm6375_desc, regmap);
}
static struct platform_driver gcc_sm6375_driver = {
diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c
index 44b49f7cd178..a6b42943eb1d 100644
--- a/drivers/clk/qcom/gcc-sm7150.c
+++ b/drivers/clk/qcom/gcc-sm7150.c
@@ -3017,7 +3017,7 @@ static int gcc_sm7150_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sm7150_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm7150_desc, regmap);
}
static struct platform_driver gcc_sm7150_driver = {
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 1f748141d12c..cefceb780889 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -3797,7 +3797,7 @@ static int gcc_sm8150_probe(struct platform_device *pdev)
if (ret)
dev_err_probe(&pdev->dev, ret, "Failed to register with DFS!\n");
- return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm8150_desc, regmap);
}
static struct platform_driver gcc_sm8150_driver = {
diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c
index e630bfa2d0c1..991cd8b8d597 100644
--- a/drivers/clk/qcom/gcc-sm8250.c
+++ b/drivers/clk/qcom/gcc-sm8250.c
@@ -3656,7 +3656,7 @@ static int gcc_sm8250_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sm8250_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm8250_desc, regmap);
}
static struct platform_driver gcc_sm8250_driver = {
diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
index fc0402e8a2a7..2d94f3046b71 100644
--- a/drivers/clk/qcom/gcc-sm8350.c
+++ b/drivers/clk/qcom/gcc-sm8350.c
@@ -3822,7 +3822,7 @@ static int gcc_sm8350_probe(struct platform_device *pdev)
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
- return qcom_cc_really_probe(pdev, &gcc_sm8350_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm8350_desc, regmap);
}
static struct platform_driver gcc_sm8350_driver = {
diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
index 9a1d48ff22bc..7b65ad0774f1 100644
--- a/drivers/clk/qcom/gcc-sm8450.c
+++ b/drivers/clk/qcom/gcc-sm8450.c
@@ -3289,7 +3289,7 @@ static int gcc_sm8450_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */
- return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm8450_desc, regmap);
}
static struct platform_driver gcc_sm8450_driver = {
diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
index 26d7349e7642..7944ddb4b47d 100644
--- a/drivers/clk/qcom/gcc-sm8550.c
+++ b/drivers/clk/qcom/gcc-sm8550.c
@@ -3364,7 +3364,7 @@ static int gcc_sm8550_probe(struct platform_device *pdev)
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
regmap_write(regmap, 0x52024, 0x0);
- return qcom_cc_really_probe(pdev, &gcc_sm8550_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm8550_desc, regmap);
}
static struct platform_driver gcc_sm8550_driver = {
diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c
index 9d1cbdf860fb..9bc19bea0c97 100644
--- a/drivers/clk/qcom/gcc-sm8650.c
+++ b/drivers/clk/qcom/gcc-sm8650.c
@@ -3822,7 +3822,7 @@ static int gcc_sm8650_probe(struct platform_device *pdev)
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
regmap_write(regmap, 0x52150, 0x0);
- return qcom_cc_really_probe(pdev, &gcc_sm8650_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm8650_desc, regmap);
}
static struct platform_driver gcc_sm8650_driver = {
diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
index 1404017be918..eb7e36ebd7ae 100644
--- a/drivers/clk/qcom/gcc-x1e80100.c
+++ b/drivers/clk/qcom/gcc-x1e80100.c
@@ -6781,7 +6781,7 @@ static int gcc_x1e80100_probe(struct platform_device *pdev)
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
regmap_write(regmap, 0x52224, 0x0);
- return qcom_cc_really_probe(pdev, &gcc_x1e80100_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_x1e80100_desc, regmap);
}
static struct platform_driver gcc_x1e80100_driver = {
diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c
index 9a4fdff719ec..617a2e97a320 100644
--- a/drivers/clk/qcom/gpucc-msm8998.c
+++ b/drivers/clk/qcom/gpucc-msm8998.c
@@ -334,7 +334,7 @@ static int gpucc_msm8998_probe(struct platform_device *pdev)
/* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */
regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0));
- return qcom_cc_really_probe(pdev, &gpucc_msm8998_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpucc_msm8998_desc, regmap);
}
static struct platform_driver gpucc_msm8998_driver = {
diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
index 1167c42da39d..ac7552b146c7 100644
--- a/drivers/clk/qcom/gpucc-sa8775p.c
+++ b/drivers/clk/qcom/gpucc-sa8775p.c
@@ -598,7 +598,7 @@ static int gpu_cc_sa8775p_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
- return qcom_cc_really_probe(pdev, &gpu_cc_sa8775p_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sa8775p_desc, regmap);
}
static struct platform_driver gpu_cc_sa8775p_driver = {
diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c
index 66f5b48cbf87..08f3983d016f 100644
--- a/drivers/clk/qcom/gpucc-sc7180.c
+++ b/drivers/clk/qcom/gpucc-sc7180.c
@@ -241,7 +241,7 @@ static int gpu_cc_sc7180_probe(struct platform_device *pdev)
value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value);
- return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sc7180_desc, regmap);
}
static struct platform_driver gpu_cc_sc7180_driver = {
diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c
index 35b394feb68d..3be6bc92639c 100644
--- a/drivers/clk/qcom/gpucc-sc7280.c
+++ b/drivers/clk/qcom/gpucc-sc7280.c
@@ -462,7 +462,7 @@ static int gpu_cc_sc7280_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x1098); /* GPUCC_CX_GMU_CLK */
regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13));
- return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sc7280_desc, regmap);
}
static struct platform_driver gpu_cc_sc7280_driver = {
diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8280xp.c
index 3611d2d1823d..c96be61e3f47 100644
--- a/drivers/clk/qcom/gpucc-sc8280xp.c
+++ b/drivers/clk/qcom/gpucc-sc8280xp.c
@@ -449,7 +449,7 @@ static int gpu_cc_sc8280xp_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */
qcom_branch_set_clk_en(regmap, 0x109c); /* GPU_CC_CXO_CLK */
- ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &gpu_cc_sc8280xp_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c
index 459f123a6720..611edf6d9ee2 100644
--- a/drivers/clk/qcom/gpucc-sdm660.c
+++ b/drivers/clk/qcom/gpucc-sdm660.c
@@ -330,7 +330,7 @@ static int gpucc_sdm660_probe(struct platform_device *pdev)
gpu_pll_config.alpha_hi = 0x8a;
clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, &gpu_pll_config);
- return qcom_cc_really_probe(pdev, &gpucc_sdm660_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpucc_sdm660_desc, regmap);
}
static struct platform_driver gpucc_sdm660_driver = {
diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c
index c87c3215dfe3..ef26690cf504 100644
--- a/drivers/clk/qcom/gpucc-sdm845.c
+++ b/drivers/clk/qcom/gpucc-sdm845.c
@@ -192,7 +192,7 @@ static int gpu_cc_sdm845_probe(struct platform_device *pdev)
value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value);
- return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sdm845_desc, regmap);
}
static struct platform_driver gpu_cc_sdm845_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c
index fb71c21c9a89..6ccbc93c5340 100644
--- a/drivers/clk/qcom/gpucc-sm6115.c
+++ b/drivers/clk/qcom/gpucc-sm6115.c
@@ -488,7 +488,7 @@ static int gpu_cc_sm6115_probe(struct platform_device *pdev)
qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true);
qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm6115_desc, regmap);
}
static struct platform_driver gpu_cc_sm6115_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm6125.c b/drivers/clk/qcom/gpucc-sm6125.c
index 61959ba02f9a..aba3f802071b 100644
--- a/drivers/clk/qcom/gpucc-sm6125.c
+++ b/drivers/clk/qcom/gpucc-sm6125.c
@@ -409,7 +409,7 @@ static int gpu_cc_sm6125_probe(struct platform_device *pdev)
qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true);
qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm6125_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm6125_desc, regmap);
}
static struct platform_driver gpu_cc_sm6125_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c
index 0bcbba2a2943..1e12ad8948db 100644
--- a/drivers/clk/qcom/gpucc-sm6350.c
+++ b/drivers/clk/qcom/gpucc-sm6350.c
@@ -502,7 +502,7 @@ static int gpu_cc_sm6350_probe(struct platform_device *pdev)
value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm6350_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm6350_desc, regmap);
}
static struct platform_driver gpu_cc_sm6350_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c
index da24276a018e..d8e0c1bbeedc 100644
--- a/drivers/clk/qcom/gpucc-sm6375.c
+++ b/drivers/clk/qcom/gpucc-sm6375.c
@@ -455,7 +455,7 @@ static int gpucc_sm6375_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config);
clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config);
- ret = qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &gpucc_sm6375_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
diff --git a/drivers/clk/qcom/gpucc-sm8150.c b/drivers/clk/qcom/gpucc-sm8150.c
index 135601629cba..d711464a71b6 100644
--- a/drivers/clk/qcom/gpucc-sm8150.c
+++ b/drivers/clk/qcom/gpucc-sm8150.c
@@ -304,7 +304,7 @@ static int gpu_cc_sm8150_probe(struct platform_device *pdev)
clk_trion_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm8150_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8150_desc, regmap);
}
static struct platform_driver gpu_cc_sm8150_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm8250.c b/drivers/clk/qcom/gpucc-sm8250.c
index 84f7f65c8d42..5b764ccdab02 100644
--- a/drivers/clk/qcom/gpucc-sm8250.c
+++ b/drivers/clk/qcom/gpucc-sm8250.c
@@ -320,7 +320,7 @@ static int gpu_cc_sm8250_probe(struct platform_device *pdev)
value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm8250_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8250_desc, regmap);
}
static struct platform_driver gpu_cc_sm8250_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c
index 38505d1388b6..89b134531c56 100644
--- a/drivers/clk/qcom/gpucc-sm8350.c
+++ b/drivers/clk/qcom/gpucc-sm8350.c
@@ -604,7 +604,7 @@ static int gpu_cc_sm8350_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8350_desc, regmap);
}
static const struct of_device_id gpu_cc_sm8350_match_table[] = {
diff --git a/drivers/clk/qcom/gpucc-sm8450.c b/drivers/clk/qcom/gpucc-sm8450.c
index 1c4769b646b0..9d8734569c93 100644
--- a/drivers/clk/qcom/gpucc-sm8450.c
+++ b/drivers/clk/qcom/gpucc-sm8450.c
@@ -751,7 +751,7 @@ static int gpu_cc_sm8450_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm8450_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8450_desc, regmap);
}
static struct platform_driver gpu_cc_sm8450_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c
index 4fc69c6026e5..7486edf56160 100644
--- a/drivers/clk/qcom/gpucc-sm8550.c
+++ b/drivers/clk/qcom/gpucc-sm8550.c
@@ -579,7 +579,7 @@ static int gpu_cc_sm8550_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */
qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */
- return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8550_desc, regmap);
}
static struct platform_driver gpu_cc_sm8550_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm8650.c b/drivers/clk/qcom/gpucc-sm8650.c
index 03307e482aca..57e6c057d214 100644
--- a/drivers/clk/qcom/gpucc-sm8650.c
+++ b/drivers/clk/qcom/gpucc-sm8650.c
@@ -647,7 +647,7 @@ static int gpu_cc_sm8650_probe(struct platform_device *pdev)
clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm8650_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8650_desc, regmap);
}
static struct platform_driver gpu_cc_sm8650_driver = {
diff --git a/drivers/clk/qcom/gpucc-x1e80100.c b/drivers/clk/qcom/gpucc-x1e80100.c
index b7e79d118d6e..2eec20dd0254 100644
--- a/drivers/clk/qcom/gpucc-x1e80100.c
+++ b/drivers/clk/qcom/gpucc-x1e80100.c
@@ -640,7 +640,7 @@ static int gpu_cc_x1e80100_probe(struct platform_device *pdev)
/* Keep clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */
- return qcom_cc_really_probe(pdev, &gpu_cc_x1e80100_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_x1e80100_desc, regmap);
}
static struct platform_driver gpu_cc_x1e80100_driver = {
diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c
index fa8cda63cf20..bf5320a43e8c 100644
--- a/drivers/clk/qcom/lcc-ipq806x.c
+++ b/drivers/clk/qcom/lcc-ipq806x.c
@@ -454,7 +454,7 @@ static int lcc_ipq806x_probe(struct platform_device *pdev)
/* Enable PLL4 source on the LPASS Primary PLL Mux */
regmap_write(regmap, 0xc4, 0x1);
- return qcom_cc_really_probe(pdev, &lcc_ipq806x_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &lcc_ipq806x_desc, regmap);
}
static struct platform_driver lcc_ipq806x_driver = {
diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
index e725e7b9c456..d53bf315e9c3 100644
--- a/drivers/clk/qcom/lcc-msm8960.c
+++ b/drivers/clk/qcom/lcc-msm8960.c
@@ -481,7 +481,7 @@ static int lcc_msm8960_probe(struct platform_device *pdev)
/* Enable PLL4 source on the LPASS Primary PLL Mux */
regmap_write(regmap, 0xc4, 0x1);
- return qcom_cc_really_probe(pdev, &lcc_msm8960_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &lcc_msm8960_desc, regmap);
}
static struct platform_driver lcc_msm8960_driver = {
diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
index c43d0b1af7f7..45e726477086 100644
--- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
+++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
@@ -772,7 +772,7 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
regmap_write(regmap, 0x4, 0x3b);
regmap_write(regmap, 0x8, 0xff05);
- ret = qcom_cc_really_probe(pdev, &lpass_audio_cc_sc7280_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &lpass_audio_cc_sc7280_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC clocks\n");
goto exit;
@@ -847,7 +847,7 @@ static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&lpass_aon_cc_pll, regmap, &lpass_aon_cc_pll_config);
- ret = qcom_cc_really_probe(pdev, &lpass_aon_cc_sc7280_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &lpass_aon_cc_sc7280_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register LPASS AON CC clocks\n");
goto exit;
diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c b/drivers/clk/qcom/lpasscorecc-sc7180.c
index fd9cd2e3f956..281d2d8f3e33 100644
--- a/drivers/clk/qcom/lpasscorecc-sc7180.c
+++ b/drivers/clk/qcom/lpasscorecc-sc7180.c
@@ -411,7 +411,7 @@ static int lpass_core_cc_sc7180_probe(struct platform_device *pdev)
clk_fabia_pll_configure(&lpass_lpaaudio_dig_pll, regmap,
&lpass_lpaaudio_dig_pll_config);
- ret = qcom_cc_really_probe(pdev, &lpass_core_cc_sc7180_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &lpass_core_cc_sc7180_desc, regmap);
pm_runtime_mark_last_busy(&pdev->dev);
exit:
diff --git a/drivers/clk/qcom/lpasscorecc-sc7280.c b/drivers/clk/qcom/lpasscorecc-sc7280.c
index a2f1e6ad6da4..b0888cd2460b 100644
--- a/drivers/clk/qcom/lpasscorecc-sc7280.c
+++ b/drivers/clk/qcom/lpasscorecc-sc7280.c
@@ -406,7 +406,7 @@ static int lpass_core_cc_sc7280_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&lpass_core_cc_dig_pll, regmap, &lpass_core_cc_dig_pll_config);
- return qcom_cc_really_probe(pdev, &lpass_core_cc_sc7280_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &lpass_core_cc_sc7280_desc, regmap);
}
static struct platform_driver lpass_core_cc_sc7280_driver = {
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index 50638ab341ec..1061322534c4 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -3122,7 +3122,7 @@ static int mmcc_msm8960_probe(struct platform_device *pdev)
clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
- return qcom_cc_really_probe(pdev, desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, desc, regmap);
}
static struct platform_driver mmcc_msm8960_driver = {
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index 36f460b78be2..d5bcb09ebd0c 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -2768,7 +2768,7 @@ static int mmcc_msm8974_probe(struct platform_device *pdev)
msm8226_clock_override();
}
- return qcom_cc_really_probe(pdev, desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, desc, regmap);
}
static struct platform_driver mmcc_msm8974_driver = {
diff --git a/drivers/clk/qcom/mmcc-msm8994.c b/drivers/clk/qcom/mmcc-msm8994.c
index 3229ff77372f..dd3f28c4bb00 100644
--- a/drivers/clk/qcom/mmcc-msm8994.c
+++ b/drivers/clk/qcom/mmcc-msm8994.c
@@ -2602,7 +2602,7 @@ static int mmcc_msm8994_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&mmpll3_early, regmap, &mmpll_p_config);
clk_alpha_pll_configure(&mmpll5_early, regmap, &mmpll_p_config);
- return qcom_cc_really_probe(pdev, &mmcc_msm8994_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8994_desc, regmap);
}
static struct platform_driver mmcc_msm8994_driver = {
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index d3f2dc798567..6849c16b3ce6 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -3626,7 +3626,7 @@ static int mmcc_msm8996_probe(struct platform_device *pdev)
/* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
regmap_update_bits(regmap, 0x5054, BIT(15), 0);
- return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8996_desc, regmap);
}
static struct platform_driver mmcc_msm8996_driver = {
diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c
index 275fb3b71ede..5738445a8656 100644
--- a/drivers/clk/qcom/mmcc-msm8998.c
+++ b/drivers/clk/qcom/mmcc-msm8998.c
@@ -2866,7 +2866,7 @@ static int mmcc_msm8998_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8998_desc, regmap);
}
static struct platform_driver mmcc_msm8998_driver = {
diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c
index 996bd01fb9ac..387e8efcd726 100644
--- a/drivers/clk/qcom/mmcc-sdm660.c
+++ b/drivers/clk/qcom/mmcc-sdm660.c
@@ -2847,7 +2847,7 @@ static int mmcc_660_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&mmpll8, regmap, &mmpll8_config);
clk_alpha_pll_configure(&mmpll10, regmap, &mmpll10_config);
- return qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &mmcc_660_desc, regmap);
}
static struct platform_driver mmcc_660_driver = {
diff --git a/drivers/clk/qcom/tcsrcc-sm8550.c b/drivers/clk/qcom/tcsrcc-sm8550.c
index 552a3eb1fd91..e5e8f2e82b94 100644
--- a/drivers/clk/qcom/tcsrcc-sm8550.c
+++ b/drivers/clk/qcom/tcsrcc-sm8550.c
@@ -166,7 +166,7 @@ static int tcsr_cc_sm8550_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- return qcom_cc_really_probe(pdev, &tcsr_cc_sm8550_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &tcsr_cc_sm8550_desc, regmap);
}
static struct platform_driver tcsr_cc_sm8550_driver = {
diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c
index ae0f812f83e8..d7f845480396 100644
--- a/drivers/clk/qcom/videocc-sc7180.c
+++ b/drivers/clk/qcom/videocc-sc7180.c
@@ -226,7 +226,7 @@ static int video_cc_sc7180_probe(struct platform_device *pdev)
/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
regmap_update_bits(regmap, 0x984, 0x1, 0x1);
- return qcom_cc_really_probe(pdev, &video_cc_sc7180_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &video_cc_sc7180_desc, regmap);
}
static struct platform_driver video_cc_sc7180_driver = {
diff --git a/drivers/clk/qcom/videocc-sc7280.c b/drivers/clk/qcom/videocc-sc7280.c
index cdd59c6f60df..4d146b6bd287 100644
--- a/drivers/clk/qcom/videocc-sc7280.c
+++ b/drivers/clk/qcom/videocc-sc7280.c
@@ -298,7 +298,7 @@ static int video_cc_sc7280_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
- return qcom_cc_really_probe(pdev, &video_cc_sc7280_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &video_cc_sc7280_desc, regmap);
}
static struct platform_driver video_cc_sc7280_driver = {
diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c
index b7f21ecad961..916aa4bc52c4 100644
--- a/drivers/clk/qcom/videocc-sdm845.c
+++ b/drivers/clk/qcom/videocc-sdm845.c
@@ -329,7 +329,7 @@ static int video_cc_sdm845_probe(struct platform_device *pdev)
clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
- return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &video_cc_sdm845_desc, regmap);
}
static struct platform_driver video_cc_sdm845_driver = {
diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c
index a0329260157a..5f26d9d5cc45 100644
--- a/drivers/clk/qcom/videocc-sm8150.c
+++ b/drivers/clk/qcom/videocc-sm8150.c
@@ -262,7 +262,7 @@ static int video_cc_sm8150_probe(struct platform_device *pdev)
/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
regmap_update_bits(regmap, 0x984, 0x1, 0x1);
- ret = qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8150_desc, regmap);
pm_runtime_put_sync(&pdev->dev);
diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c
index 016b596e03b3..19484225351a 100644
--- a/drivers/clk/qcom/videocc-sm8250.c
+++ b/drivers/clk/qcom/videocc-sm8250.c
@@ -387,7 +387,7 @@ static int video_cc_sm8250_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0xeec); /* VIDEO_CC_XO_CLK */
- ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8250_desc, regmap);
pm_runtime_put(&pdev->dev);
diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c
index f7aec28d4c87..5bd6fe3e1298 100644
--- a/drivers/clk/qcom/videocc-sm8350.c
+++ b/drivers/clk/qcom/videocc-sm8350.c
@@ -562,7 +562,7 @@ static int video_cc_sm8350_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */
qcom_branch_set_clk_en(regmap, video_cc_xo_clk_cbcr); /* VIDEO_CC_XO_CLK */
- ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8350_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c
index 67df40f16423..ed9163d64244 100644
--- a/drivers/clk/qcom/videocc-sm8450.c
+++ b/drivers/clk/qcom/videocc-sm8450.c
@@ -428,7 +428,7 @@ static int video_cc_sm8450_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */
- ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8450_desc, regmap);
pm_runtime_put(&pdev->dev);
diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c
index d73f747d2474..4d36362db1d0 100644
--- a/drivers/clk/qcom/videocc-sm8550.c
+++ b/drivers/clk/qcom/videocc-sm8550.c
@@ -433,7 +433,7 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */
- ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8550_desc, regmap);
pm_runtime_put(&pdev->dev);
--
2.34.1
^ permalink raw reply related [relevance 10%]
* [PATCH v14 0/4] add clock controller of qca8386/qca8084
@ 2024-05-07 13:05 6% Luo Jie
2024-05-07 13:05 10% ` [PATCH v14 3/4] clk: qcom: common: commonize qcom_cc_really_probe Luo Jie
0 siblings, 1 reply; 200+ results
From: Luo Jie @ 2024-05-07 13:05 UTC (permalink / raw)
To: andersson, mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, quic_srichara
qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode
named by qca8386, or working as PHY mode named by qca8084,
clock hardware reigster is accessed by MDIO bus.
This patch series add the clock controller of qca8363/qca8084,
and add the clock ops clk_branch2_prepare_ops to avoid spin lock
used during the clock operation of qca8k clock controller where
the sleep happens when accessing clock control register by MDIO
bus.
Changes in v2:
* remove clock flag CLK_ENABLE_MUTEX_LOCK.
* add clock ops clk_branch2_qca8k_ops.
* improve yaml file for fixing dtschema warnings.
* enable clock controller driver in defconfig.
Changes in v3:
* rename clk_branch2_qca8k_ops to clk_branch2_mdio_ops.
* fix review comments on yaml file.
* use dev_err_probe on driver probe error.
* only use the compatible "qcom,qca8084-nsscc".
* remove enable clock controller driver patch.
Changes in v4:
* add _qcom_cc_really_probe function.
* commonizing the probe function.
* remove flag CLK_IS_CRITICAL from clocks only needed
to be enabled in switch device.
* update device tree property reg to 0x10.
Changes in v5:
* commonize qcom_cc_really_probe.
* add halt_check for the branch clocks.
* fix the review comments on nsscc-qca8k.c.
Changes in v6:
* rename clk_branch2_mdio_ops to clk_branch2_prepare_ops.
Changes in v7:
* remove the clock flag CLK_IS_CRITICAL.
* optimize the file nsscc-qca8k.c.
* identify & fix the comments from Stephen.
Changes in v8:
* add dependency on ARM in Kconfig.
Changes in v9:
* take the clk_ops clk_rcg2_mux_closest_ops to remove the
redundant freq_tbls.
Changes in v10:
* fix the patch CHECK and improve the comments.
Changes in v11:
* update the clock names to reflect hardware connecton.
NSS_CC_MAC4_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC ->
NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC
NSS_CC_MAC4_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC ->
NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC
* resolve the qcom_cc_really_probe merge conflict based
on the latest code.
Changes in v12:
* fix the compile error caused by the parameter of
qcom_cc_really_probe updated from pdev to &pdev->dev in the
new merged clock driver gcc-sm4450.c and camcc-sm8550.c.
Changes in v13:
* fix the compile error caused by the parameter of
qcom_cc_really_probe from pdev to &pdev->dev in the new
merged gcc drivers.
* use the freq_multi_tbl for the same frequency config, which
is introduced by Christian's patch set below.
<clk: qcom: clk-rcg2: introduce support for multiple conf
for same freq>.
* add dependent patch set link.
Changes in v14:
* Rebase the patch series.
* Reset clock controller after enabling reference clock.
* remove the link of dependent patch series since it is merged.
Luo Jie (4):
clk: qcom: branch: Add clk_branch2_prepare_ops
dt-bindings: clock: add qca8386/qca8084 clock and reset definitions
clk: qcom: common: commonize qcom_cc_really_probe
clk: qcom: add clock controller driver for qca8386/qca8084
.../bindings/clock/qcom,qca8k-nsscc.yaml | 85 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq6018.c | 2 +-
drivers/clk/qcom/camcc-sc7180.c | 2 +-
drivers/clk/qcom/camcc-sc7280.c | 2 +-
drivers/clk/qcom/camcc-sc8280xp.c | 2 +-
drivers/clk/qcom/camcc-sdm845.c | 2 +-
drivers/clk/qcom/camcc-sm6350.c | 2 +-
drivers/clk/qcom/camcc-sm8250.c | 2 +-
drivers/clk/qcom/camcc-sm8450.c | 2 +-
drivers/clk/qcom/camcc-sm8550.c | 2 +-
drivers/clk/qcom/camcc-x1e80100.c | 2 +-
drivers/clk/qcom/clk-branch.c | 7 +
drivers/clk/qcom/clk-branch.h | 1 +
drivers/clk/qcom/common.c | 7 +-
drivers/clk/qcom/common.h | 2 +-
drivers/clk/qcom/dispcc-qcm2290.c | 2 +-
drivers/clk/qcom/dispcc-sc7180.c | 2 +-
drivers/clk/qcom/dispcc-sc7280.c | 2 +-
drivers/clk/qcom/dispcc-sc8280xp.c | 2 +-
drivers/clk/qcom/dispcc-sdm845.c | 2 +-
drivers/clk/qcom/dispcc-sm6115.c | 2 +-
drivers/clk/qcom/dispcc-sm6125.c | 2 +-
drivers/clk/qcom/dispcc-sm6350.c | 2 +-
drivers/clk/qcom/dispcc-sm6375.c | 2 +-
drivers/clk/qcom/dispcc-sm8250.c | 2 +-
drivers/clk/qcom/dispcc-sm8450.c | 2 +-
drivers/clk/qcom/dispcc-sm8550.c | 2 +-
drivers/clk/qcom/dispcc-sm8650.c | 2 +-
drivers/clk/qcom/dispcc-x1e80100.c | 2 +-
drivers/clk/qcom/ecpricc-qdu1000.c | 2 +-
drivers/clk/qcom/gcc-ipq5018.c | 2 +-
drivers/clk/qcom/gcc-ipq6018.c | 2 +-
drivers/clk/qcom/gcc-ipq8074.c | 2 +-
drivers/clk/qcom/gcc-mdm9607.c | 2 +-
drivers/clk/qcom/gcc-mdm9615.c | 2 +-
drivers/clk/qcom/gcc-msm8917.c | 2 +-
drivers/clk/qcom/gcc-msm8939.c | 2 +-
drivers/clk/qcom/gcc-msm8953.c | 2 +-
drivers/clk/qcom/gcc-msm8976.c | 2 +-
drivers/clk/qcom/gcc-msm8996.c | 2 +-
drivers/clk/qcom/gcc-msm8998.c | 2 +-
drivers/clk/qcom/gcc-qcm2290.c | 2 +-
drivers/clk/qcom/gcc-qcs404.c | 2 +-
drivers/clk/qcom/gcc-qdu1000.c | 2 +-
drivers/clk/qcom/gcc-sa8775p.c | 2 +-
drivers/clk/qcom/gcc-sc7180.c | 2 +-
drivers/clk/qcom/gcc-sc7280.c | 2 +-
drivers/clk/qcom/gcc-sc8180x.c | 2 +-
drivers/clk/qcom/gcc-sc8280xp.c | 2 +-
drivers/clk/qcom/gcc-sdm660.c | 2 +-
drivers/clk/qcom/gcc-sdm845.c | 2 +-
drivers/clk/qcom/gcc-sdx55.c | 2 +-
drivers/clk/qcom/gcc-sdx65.c | 2 +-
drivers/clk/qcom/gcc-sdx75.c | 2 +-
drivers/clk/qcom/gcc-sm4450.c | 2 +-
drivers/clk/qcom/gcc-sm6115.c | 2 +-
drivers/clk/qcom/gcc-sm6125.c | 2 +-
drivers/clk/qcom/gcc-sm6350.c | 2 +-
drivers/clk/qcom/gcc-sm6375.c | 2 +-
drivers/clk/qcom/gcc-sm7150.c | 2 +-
drivers/clk/qcom/gcc-sm8150.c | 2 +-
drivers/clk/qcom/gcc-sm8250.c | 2 +-
drivers/clk/qcom/gcc-sm8350.c | 2 +-
drivers/clk/qcom/gcc-sm8450.c | 2 +-
drivers/clk/qcom/gcc-sm8550.c | 2 +-
drivers/clk/qcom/gcc-sm8650.c | 2 +-
drivers/clk/qcom/gcc-x1e80100.c | 2 +-
drivers/clk/qcom/gpucc-msm8998.c | 2 +-
drivers/clk/qcom/gpucc-sa8775p.c | 2 +-
drivers/clk/qcom/gpucc-sc7180.c | 2 +-
drivers/clk/qcom/gpucc-sc7280.c | 2 +-
drivers/clk/qcom/gpucc-sc8280xp.c | 2 +-
drivers/clk/qcom/gpucc-sdm660.c | 2 +-
drivers/clk/qcom/gpucc-sdm845.c | 2 +-
drivers/clk/qcom/gpucc-sm6115.c | 2 +-
drivers/clk/qcom/gpucc-sm6125.c | 2 +-
drivers/clk/qcom/gpucc-sm6350.c | 2 +-
drivers/clk/qcom/gpucc-sm6375.c | 2 +-
drivers/clk/qcom/gpucc-sm8150.c | 2 +-
drivers/clk/qcom/gpucc-sm8250.c | 2 +-
drivers/clk/qcom/gpucc-sm8350.c | 2 +-
drivers/clk/qcom/gpucc-sm8450.c | 2 +-
drivers/clk/qcom/gpucc-sm8550.c | 2 +-
drivers/clk/qcom/gpucc-sm8650.c | 2 +-
drivers/clk/qcom/gpucc-x1e80100.c | 2 +-
drivers/clk/qcom/lcc-ipq806x.c | 2 +-
drivers/clk/qcom/lcc-msm8960.c | 2 +-
drivers/clk/qcom/lpassaudiocc-sc7280.c | 4 +-
drivers/clk/qcom/lpasscorecc-sc7180.c | 2 +-
drivers/clk/qcom/lpasscorecc-sc7280.c | 2 +-
drivers/clk/qcom/mmcc-msm8960.c | 2 +-
drivers/clk/qcom/mmcc-msm8974.c | 2 +-
drivers/clk/qcom/mmcc-msm8994.c | 2 +-
drivers/clk/qcom/mmcc-msm8996.c | 2 +-
drivers/clk/qcom/mmcc-msm8998.c | 2 +-
drivers/clk/qcom/mmcc-sdm660.c | 2 +-
drivers/clk/qcom/nsscc-qca8k.c | 2221 +++++++++++++++++
drivers/clk/qcom/tcsrcc-sm8550.c | 2 +-
drivers/clk/qcom/videocc-sc7180.c | 2 +-
drivers/clk/qcom/videocc-sc7280.c | 2 +-
drivers/clk/qcom/videocc-sdm845.c | 2 +-
drivers/clk/qcom/videocc-sm8150.c | 2 +-
drivers/clk/qcom/videocc-sm8250.c | 2 +-
drivers/clk/qcom/videocc-sm8350.c | 2 +-
drivers/clk/qcom/videocc-sm8450.c | 2 +-
drivers/clk/qcom/videocc-sm8550.c | 2 +-
include/dt-bindings/clock/qcom,qca8k-nsscc.h | 101 +
include/dt-bindings/reset/qcom,qca8k-nsscc.h | 76 +
110 files changed, 2606 insertions(+), 106 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml
create mode 100644 drivers/clk/qcom/nsscc-qca8k.c
create mode 100644 include/dt-bindings/clock/qcom,qca8k-nsscc.h
create mode 100644 include/dt-bindings/reset/qcom,qca8k-nsscc.h
base-commit: 93a39e4766083050ca0ecd6a3548093a3b9eb60c
--
2.34.1
^ permalink raw reply [relevance 6%]
* linux-next: Tree for May 6
@ 2024-05-06 6:49 1% Stephen Rothwell
0 siblings, 0 replies; 200+ results
From: Stephen Rothwell @ 2024-05-06 6:49 UTC (permalink / raw)
To: Linux Next Mailing List; +Cc: Linux Kernel Mailing List
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Hi all,
Changes since 20240503:
The mm tree lost its build failure.
The arm tree lost its build failure.
The vfs-brauner tree gained a conflict against Linus' tree.
The v4l-dvb-next tree lost its build failure but gained another for
which I applied a patch.
The dmi tree lost its build failure.
The net-next tree gained a conflict against the kbuild tree.
The drm-msm tree gained a conflict against the kbuild tree.
The drm-xe tree gained a conflict against the drm-intel tree.
The rust tree gained a conflict against the kbuild tree.
Non-merge commits (relative to Linus' tree): 10384
10232 files changed, 718413 insertions(+), 256326 deletions(-)
----------------------------------------------------------------------------
I have created today's linux-next tree at
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
(patches at http://www.kernel.org/pub/linux/kernel/next/ ). If you
are tracking the linux-next tree using git, you should not use "git pull"
to do so as that will try to merge the new linux-next release with the
old one. You should use "git fetch" and checkout or reset to the new
master.
You can see which trees have been included by looking in the Next/Trees
file in the source. There is also the merge.log file in the Next
directory. Between each merge, the tree was built with a ppc64_defconfig
for powerpc, an allmodconfig for x86_64, a multi_v7_defconfig for arm
and a native build of tools/perf. After the final fixups (if any), I do
an x86_64 modules_install followed by builds for x86_64 allnoconfig,
powerpc allnoconfig (32 and 64 bit), ppc44x_defconfig, allyesconfig
and pseries_le_defconfig and i386, arm64, s390, sparc and sparc64
defconfig and htmldocs. And finally, a simple boot test of the powerpc
pseries_le_defconfig kernel in qemu (with and without kvm enabled).
Below is a summary of the state of the merge.
I am currently merging 373 trees (counting Linus' and 103 trees of bug
fix patches pending for the current merge release).
Stats about the size of the tree over time can be seen at
http://neuling.org/linux-next-size.html .
Status of my local build tests will be at
http://kisskb.ellerman.id.au/linux-next . If maintainers want to give
advice about cross compilers/configs that work, we are always open to add
more builds.
Thanks to Randy Dunlap for doing many randconfig builds. And to Paul
Gortmaker for triage and bug fixes.
--
Cheers,
Stephen Rothwell
$ git checkout master
$ git reset --hard stable
Merging origin/master (dd5a440a31fa Linux 6.9-rc7)
Merging fixes/fixes (2dde18cd1d8f Linux 6.5)
Merging mm-hotfixes/mm-hotfixes-unstable (39f6e51dddbb XArray: Set the marks correctly when splitting an entry)
Merging kbuild-current/fixes (89e5462bb5ae kconfig: Fix typo HEIGTH to HEIGHT)
Merging arc-current/for-curr (e67572cd2204 Linux 6.9-rc6)
Merging arm-current/fixes (0c66c6f4e21c ARM: 9359/1: flush: check if the folio is reserved for no-mapping addresses)
Merging arm64-fixes/for-next/fixes (50449ca66cc5 arm64: hibernate: Fix level3 translation fault in swsusp_save())
Merging arm-soc-fixes/arm/fixes (e845bcc8cfda Merge tag 'riscv-soc-fixes-for-v6.9-rc6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes)
Merging davinci-current/davinci/for-current (6613476e225e Linux 6.8-rc1)
Merging drivers-memory-fixes/fixes (4cece7649650 Linux 6.9-rc1)
Merging sophgo-fixes/fixes (4cece7649650 Linux 6.9-rc1)
Merging m68k-current/for-linus (e8a7824856de m68k: defconfig: Update defconfigs for v6.8-rc1)
Merging powerpc-fixes/fixes (49a940dbdc31 powerpc/pseries/iommu: LPAR panics during boot up with a frozen PE)
Merging s390-fixes/fixes (7bbe449d0bdb s390/paes: Reestablish retry loop in paes)
Merging fscrypt-current/for-current (4cece7649650 Linux 6.9-rc1)
Merging fsverity-current/for-current (4cece7649650 Linux 6.9-rc1)
Merging net/main (fa870b45b08a MAINTAINERS: update cxgb4 and cxgb3 network drivers maintainer)
Merging bpf/master (3e9bc0472b91 Merge branch 'bpf: Add BPF_PROG_TYPE_CGROUP_SKB attach type enforcement in BPF_LINK_CREATE')
Merging ipsec/master (b6d2e438e16c xfrm: Correct spelling mistake in xfrm.h comment)
Merging netfilter/main (8a2e4d37afb8 s390/qeth: Fix kernel panic after setting hsuid)
Merging ipvs/main (8a2e4d37afb8 s390/qeth: Fix kernel panic after setting hsuid)
Merging wireless/for-next (838c7b8f1f27 wifi: nl80211: Avoid address calculations via out of bounds array indexing)
Merging wpan/master (b85ea95d0864 Linux 6.7-rc1)
Merging rdma-fixes/for-rc (ed30a4a51bb1 Linux 6.9-rc5)
Merging sound-current/for-linus (fdb3f29dfe0d ALSA: hda/realtek: Fix build error without CONFIG_PM)
Merging sound-asoc-fixes/for-linus (09068d624c49 ASoC: amd: acp: fix for acp platform device creation failure)
Merging regmap-fixes/for-linus (fec50db7033e Linux 6.9-rc3)
Merging regulator-fixes/for-linus (d1ef160b45a0 regulator: rtq2208: Fix the BUCK ramp_delay range to maximum of 16mVstep/us)
Merging spi-fixes/for-linus (52b62e7a5d4f spi: stm32: enable controller before asserting CS)
Merging pci-current/for-linus (2e0239d47d75 PCI/ASPM: Clarify that pcie_aspm=off means leave ASPM untouched)
Merging driver-core.current/driver-core-linus (ed30a4a51bb1 Linux 6.9-rc5)
Merging tty.current/tty-linus (8492bd91aa05 serial: sc16is7xx: fix bug in sc16is7xx_set_baud() when using prescaler)
Merging usb.current/usb-linus (ae11f04b452b usb: typec: tcpm: Check for port partner validity before consuming it)
Merging usb-serial-fixes/usb-linus (582ee2f9d268 USB: serial: option: add Telit FN920C04 rmnet compositions)
Merging phy/fixes (bf6e4ee5c436 phy: ti: tusb1210: Resolve charger-det crash if charger psy is unregistered)
Merging staging.current/staging-linus (39cd87c4eb2b Linux 6.9-rc2)
Merging iio-fixes/fixes-togreg (4f11dc1b7fd2 iio: pressure: bmp280: Fix BMP580 temperature reading)
Merging counter-current/counter-current (39cd87c4eb2b Linux 6.9-rc2)
Merging char-misc.current/char-misc-linus (98241a774db4 slimbus: qcom-ngd-ctrl: Add timeout for wait operation)
Merging soundwire-fixes/fixes (e67572cd2204 Linux 6.9-rc6)
Merging thunderbolt-fixes/fixes (e67572cd2204 Linux 6.9-rc6)
Merging input-current/for-linus (0537c8eef4f6 Input: amimouse - mark driver struct with __refdata to prevent section mismatch)
Merging crypto-current/master (5a7e89d3315d crypto: iaa - Fix nr_cpus < nr_iaa case)
Merging vfio-fixes/for-linus (4ea95c04fa6b vfio: Drop vfio_file_iommu_group() stub to fudge around a KVM wart)
Merging kselftest-fixes/fixes (72d7cb5c190b selftests/harness: Prevent infinite loop due to Assert in FIXTURE_TEARDOWN)
Merging dmaengine-fixes/fixes (e67572cd2204 Linux 6.9-rc6)
Merging backlight-fixes/for-backlight-fixes (6613476e225e Linux 6.8-rc1)
Merging mtd-fixes/mtd/fixes (d2d73a6dd173 mtd: limit OTP NVMEM cell parse to non-NAND devices)
Merging mfd-fixes/for-mfd-fixes (6613476e225e Linux 6.8-rc1)
Merging v4l-dvb-fixes/fixes (d353c3c34af0 media: mediatek: vcodec: support 36 bits physical address)
Merging reset-fixes/reset/fixes (4a6756f56bcf reset: Fix crash when freeing non-existent optional resets)
Merging mips-fixes/mips-fixes (0bbac3facb5d Linux 6.9-rc4)
Merging at91-fixes/at91-fixes (1fe5e0a31e62 ARM: dts: microchip: at91-sama7g54_curiosity: Replace regulator-suspend-voltage with the valid property)
Merging omap-fixes/fixes (9b6a51aab5f5 ARM: dts: Fix occasional boot hang for am3 usb)
Merging kvm-fixes/master (16c20208b9c2 Merge tag 'kvmarm-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD)
Merging kvms390-fixes/master (175f2f5bcdfc KVM: s390: Check kvm pointer when testing KVM_CAP_S390_HPAGE_1M)
Merging hwmon-fixes/hwmon (d02abd57e794 hwmon: (corsair-cpro) Protect ccp->wait_input_report with a spinlock)
Merging nvdimm-fixes/libnvdimm-fixes (33908660e814 ACPI: NFIT: Fix incorrect calculation of idt size)
Merging cxl-fixes/fixes (5d211c709059 cxl: Fix cxl_endpoint_get_perf_coordinate() support for RCH)
Merging btrfs-fixes/next-fixes (dd11e0f129c3 Merge branch 'misc-6.9' into next-fixes)
Merging vfs-fixes/fixes (aa23317d0268 qibfs: fix dentry leak)
Merging dma-mapping-fixes/for-linus (75961ffb5cb3 swiotlb: initialise restricted pool list_head when SWIOTLB_DYNAMIC=y)
Merging drivers-x86-fixes/fixes (515a3c3a5489 platform/x86: ISST: Add Grand Ridge to HPM CPU list)
Merging samsung-krzk-fixes/fixes (4cece7649650 Linux 6.9-rc1)
Merging pinctrl-samsung-fixes/fixes (4cece7649650 Linux 6.9-rc1)
Merging devicetree-fixes/dt/linus (dab6bc78e981 of: module: add buffer overflow check in of_modalias())
Merging dt-krzk-fixes/fixes (4cece7649650 Linux 6.9-rc1)
Merging scsi-fixes/fixes (961990efc608 scsi: sd: Only print updates to permanent stream count)
Merging drm-fixes/drm-fixes (09e10499ee6a Merge tag 'drm-misc-fixes-2024-05-02' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes)
Merging drm-intel-fixes/for-linux-next-fixes (e67572cd2204 Linux 6.9-rc6)
Merging mmc-fixes/fixes (e027e72ecc16 mmc: moxart: fix handling of sgm->consumed, otherwise WARN_ON triggers)
Merging rtc-fixes/rtc-fixes (4cece7649650 Linux 6.9-rc1)
Merging gnss-fixes/gnss-linus (0bbac3facb5d Linux 6.9-rc4)
Merging hyperv-fixes/hyperv-fixes (fb836d64a2ea hv/vmbus_drv: rename hv_acpi_init() to vmbus_init())
Merging soc-fsl-fixes/fix (06c2afb862f9 Linux 6.5-rc1)
Merging risc-v-fixes/fixes (6beb6bc5a81e Merge patch series "RISC-V: Test th.sxstatus.MAEE bit before enabling MAEE")
Merging riscv-dt-fixes/riscv-dt-fixes (e0503d47e93d riscv: dts: starfive: visionfive 2: Remove non-existing I2S hardware)
Merging riscv-soc-fixes/riscv-soc-fixes (3aa20d1f7bcb firmware: microchip: clarify that sizes and addresses are in hex)
Merging fpga-fixes/fixes (54435d1f21b3 fpga: dfl-pci: add PCI subdevice ID for Intel D5005 card)
Merging spdx/spdx-linus (4cece7649650 Linux 6.9-rc1)
Merging gpio-brgl-fixes/gpio/for-current (e67572cd2204 Linux 6.9-rc6)
Merging gpio-intel-fixes/fixes (7d045025a24b gpio: tangier: Use correct type for the IRQ chip data)
Merging pinctrl-intel-fixes/fixes (5d10a157ebe0 pinctrl: baytrail: Add pinconf group for uart3)
Merging auxdisplay-fixes/fixes (4cece7649650 Linux 6.9-rc1)
Merging erofs-fixes/fixes (7af2ae1b1531 erofs: reliably distinguish block based and fscache mode)
Merging kunit-fixes/kunit-fixes (cfedfb24c9dd kunit: configs: Enable CONFIG_DAMON_DBGFS_DEPRECATED for --alltests)
Merging memblock-fixes/fixes (592447f6cb3c memblock tests: fix undefined reference to `BIT')
Merging nfsd-fixes/nfsd-fixes (18180a4550d0 NFSD: Fix nfsd4_encode_fattr4() crasher)
Merging renesas-fixes/fixes (8c987693dc2d ARM: dts: renesas: rcar-gen2: Add missing #interrupt-cells to DA9063 nodes)
Merging perf-current/perf-tools (1cebd7f74976 tools/include: Sync arm64 asm/cputype.h with the kernel sources)
Merging efi-fixes/urgent (1c5a1627f481 efi/unaccepted: touch soft lockup during memory accept)
Merging zstd-fixes/zstd-linus (77618db34645 zstd: Fix array-index-out-of-bounds UBSAN warning)
Merging battery-fixes/fixes (1e0fb1136461 power: supply: mt6360_charger: Fix of_match for usb-otg-vbus regulator)
Merging uml-fixes/fixes (73a23d771033 um: harddog: fix modular build)
Merging iommufd-fixes/for-rc (2760c51b8040 iommufd: Add config needed for iommufd_fail_nth)
Merging rust-fixes/rust-fixes (e67572cd2204 Linux 6.9-rc6)
Merging v9fs-fixes/fixes/next (d05dcfdf5e16 fs/9p: mitigate inode collisions)
Merging w1-fixes/fixes (4cece7649650 Linux 6.9-rc1)
Merging pmdomain-fixes/fixes (670c900f6964 pmdomain: ti-sci: Fix duplicate PD referrals)
Merging overlayfs-fixes/ovl-fixes (77a28aa47687 ovl: relax WARN_ON in ovl_verify_area())
Merging i2c-host-fixes/i2c/i2c-host-fixes (18f109e5edc8 i2c: cadence: Avoid fifo clear after start)
Merging sparc-fixes/for-linus (6613476e225e Linux 6.8-rc1)
Merging clk-fixes/clk-fixes (aacb99de1099 clk: samsung: Revert "clk: Use device_get_match_data()")
Merging drm-misc-fixes/for-linux-next-fixes (08001033121d drm/meson: dw-hdmi: add bandgap setting for g12)
Merging mm-stable/mm-stable (72801513b2bf mm: set pageblock_order to HPAGE_PMD_ORDER in case with !CONFIG_HUGETLB_PAGE but THP enabled)
Merging mm-nonmm-stable/mm-nonmm-stable (e02577872ff5 crash: add prefix for crash dumping messages)
Merging mm/mm-everything (ebacef4eb695 foo)
Merging kbuild/for-next (1af0ac1bcdb0 kbuild: buildtar: install riscv compressed images as vmlinuz)
Merging clang-format/clang-format (5a205c6a9f79 clang-format: Update with v6.7-rc4's `for_each` macro list)
Merging perf/perf-tools-next (77a70f80751d perf vendor events amd: Add Zen 5 mapping)
Merging compiler-attributes/compiler-attributes (2993eb7a8d34 Compiler Attributes: counted_by: fixup clang URL)
Merging dma-mapping/for-next (c93f261dfc39 Documentation/core-api: add swiotlb documentation)
Merging asm-generic/master (8823fff36eb5 Merge branch 'alpha-cleanup-6.9' into asm-generic)
Merging arc/for-next (0bb80ecc33a8 Linux 6.6-rc1)
Merging arm/for-next (431dd6281857 Merge branches 'amba', 'cfi', 'clkdev', 'fixes' and 'misc' into for-next)
Merging arm64/for-next/core (02a5cc61de06 Merge branches 'for-next/acpi', 'for-next/kbuild', 'for-next/misc', 'for-next/mm', 'for-next/perf', 'for-next/selftests' and 'for-next/tlbi' into for-next/core)
Merging arm-perf/for-next/perf (410e471f8746 arm64: Add USER_STACKTRACE support)
Merging arm-soc/for-next (fa8870d46ddf soc: document merges)
Merging amlogic/for-next (e30237bd4f71 Merge branch 'v6.10/defconfig' into for-next)
Merging asahi-soc/asahi-soc/for-next (ffc253263a13 Linux 6.6)
Merging aspeed/for-next (c44211af1aa9 ARM: dts: aspeed: Add ASRock E3C256D4I BMC)
Merging at91/at91-next (fa8e55345b64 Merge branch 'microchip-dt64' into at91-next)
Merging broadcom/next (3d83aa97a6f7 Merge branch 'devicetree/next' into next)
Merging davinci/davinci/for-next (6613476e225e Linux 6.8-rc1)
Merging drivers-memory/for-next (bf11908757ee memory: mtk-smi: fix module autoloading)
Merging imx-mxs/for-next (8c4bf8c96748 Merge branch 'imx/defconfig' into for-next)
Merging mediatek/for-next (7f6f45a762c3 Merge branches 'v6.9-next/soc' and 'v6.9-next/dts64' into for-next)
7c9faab9d28f ("arm64: dts: mediatek: mt8183-pico6: Fix bluetooth node")
Merging mvebu/for-next (da8e8356f594 Merge branch 'mvebu/dt64' into mvebu/for-next)
Merging omap/for-next (5856330c3d56 Merge branch 'drivers-ti-sysc-for-v6.10' into for-next)
Merging qcom/for-next (b43b8fcbb87a Merge branches 'arm32-for-6.10', 'arm64-defconfig-for-6.10', 'arm64-fixes-for-6.9', 'arm64-for-6.10', 'clk-fixes-for-6.9', 'clk-for-6.10', 'drivers-fixes-for-6.9' and 'drivers-for-6.10' into for-next)
Merging renesas/next (1e2995ef0bb8 Merge branch 'renesas-dts-for-v6.10' into renesas-next)
Merging reset/reset/next (6d89df61650d reset: ti-sci: Convert to platform remove callback returning void)
Merging rockchip/for-next (160b088184ec Merge branch 'v6.10-clk/next' into for-next)
Merging samsung-krzk/for-next (f599b6538b60 Merge branch 'next/dt64' into for-next)
Merging scmi/for-linux-next (146928437fcb Merge tags 'scmi-updates-6.10' and 'ffa-updates-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into for-linux-next)
Merging sophgo/for-next (1eba0b61be72 riscv: dts: sophgo: add reserved memory node for CV1800B)
Merging stm32/stm32-next (dccdbccb7045 arm64: dts: st: correct masks for GIC PPI interrupts on stm32mp25)
Merging sunxi/sunxi/for-next (547c853141d1 Merge branch 'sunxi/dt-for-6.10' into sunxi/for-next)
Merging tee/next (60757f1264a2 Merge branch 'tee_ts_for_v6.10' into next)
Merging tegra/for-next (2fd759c1796c Merge branch for-6.10/arm64/defconfig into for-next)
Merging ti/ti-next (f532f2375771 Merge branch 'ti-k3-dts-next' into ti-next)
Merging xilinx/for-next (2dc107360e22 dts: zynqmp: add properties for TCM in remoteproc)
Merging clk/clk-next (804e3d8b695b Merge branch 'clk-binding' into clk-next)
Merging clk-imx/for-next (f5072cffb35c clk: imx: imx8mp: Convert to platform remove callback returning void)
Merging clk-renesas/renesas-clk (5add5ebc4e35 clk: renesas: r9a08g045: Add support for power domains)
Merging csky/linux-next (2c40c1c6adab Merge tag 'usb-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb)
Merging loongarch/loongarch-next (511b5b342cce LoongArch: KVM: Add mmio trace events support)
Merging m68k/for-next (bd622532f7b3 m68k: amiga: Use str_plural() to fix Coccinelle warning)
Merging m68knommu/for-next (2595108e5842 m68k: Avoid CONFIG_COLDFIRE switch in uapi header)
Merging microblaze/next (58d647506c92 microblaze: Remove early printk call from cpuinfo-static.c)
Merging mips/mips-next (07e6a6d7f1d9 MIPS: Take in account load hazards for HI/LO restoring)
Merging openrisc/for-next (4dc70e1aadfa openrisc: Move FPU state out of pt_regs)
Merging parisc-hd/for-next (487fa28fa8b6 parisc: Define sigset_t in parisc uapi header)
Merging powerpc/next (1fcd25473337 MAINTAINERS: MMU GATHER: Update Aneesh's address)
Merging powerpc-kdump-hotplug/topic/kdump-hotplug (849599b702ef powerpc/crash: add crash memory hotplug support)
Merging soc-fsl/next (fb9c384625dd bus: fsl-mc: fsl-mc-allocator: Drop a write-only variable)
Merging risc-v/for-next (0a16a1728790 riscv: select ARCH_HAS_FAST_MULTIPLIER)
CONFLICT (content): Merge conflict in Documentation/rust/arch-support.rst
Merging riscv-dt/riscv-dt-for-next (8fd63d81a760 riscv: dts: microchip: add pac1934 power-monitor to icicle)
CONFLICT (content): Merge conflict in arch/riscv/Makefile
Merging riscv-soc/riscv-soc-for-next (16d9122246cc Merge branch 'riscv-config' into riscv-soc-for-next)
Merging s390/for-next (63f922a4c63f Merge branch 'features-revert' into for-next)
Merging sh/for-next (21b8651502d5 sh: boot: Add proper forward declarations)
Merging sparc/for-next (48d85acdaa52 sparc: chmc: Convert to platform remove callback returning void)
Merging uml/next (919e3ece7f5a um: virtio_uml: Convert to platform remove callback returning void)
CONFLICT (content): Merge conflict in arch/um/include/shared/um_malloc.h
Merging xtensa/xtensa-for-next (b7cf2a1d9881 xtensa: remove redundant flush_dcache_page and ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE macros)
Merging bcachefs/for-next (bab182cf6a98 bcachefs: Move nocow unlock to bch2_write_endio())
Merging pidfd/for-next (a901a3568fd2 Merge tag 'iomap-6.5-merge-1' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux)
Merging fscrypt/for-next (8c62f31eddb7 fscrypt: shrink the size of struct fscrypt_inode_info slightly)
Merging afs/afs-next (abcbd3bfbbfe afs: trace: Log afs_make_call(), including server address)
Merging btrfs/for-next (d49e9f686546 Merge branch 'for-next-next-v6.9-20240503' into for-next-20240503)
Merging ceph/master (d3e046930679 MAINTAINERS: remove myself as a Reviewer for Ceph)
Merging cifs/for-next (ae4f73e84cb1 smb: smb2pdu.h: Avoid -Wflex-array-member-not-at-end warnings)
Merging configfs/for-next (4425c1d9b44d configfs: improve item creation performance)
Merging erofs/dev (b351756059e3 erofs: derive fsid from on-disk UUID for .statfs() if possible)
Merging exfat/dev (f19257997d9c exfat: zero the reserved fields of file and stream extension dentries)
Merging exportfs/exportfs-next (e8f897f4afef Linux 6.8)
Merging ext3/for_next (e6b4c0a8589b Merge ext2 Kconfig cleanup.)
Merging ext4/dev (0ecae5410ab5 ext4: initialize sbi->s_freeclusters_counter and sbi->s_dirtyclusters_counter before use in kunit test)
Merging f2fs/dev (3763f9effcdc f2fs: use helper to print zone condition)
Merging fsverity/for-next (ee5814dddefb fsverity: use register_sysctl_init() to avoid kmemleak warning)
Merging fuse/for-next (fa7e19337908 fuse: Add initial support for fs-verity)
Merging gfs2/for-next (50fabd42cb2f gfs2: Convert gfs2_aspace_writepage() to use a folio)
Merging jfs/jfs-next (e42e29cc4423 Revert "jfs: fix shift-out-of-bounds in dbJoin")
Merging ksmbd/ksmbd-for-next (691aae4f36f9 ksmbd: do not grant v2 lease if parent lease key and epoch are not set)
Merging nfs/linux-next (24457f1be29f nfs: Handle error of rpc_proc_register() in nfs_net_init().)
Merging nfs-anna/linux-next (57331a59ac0d NFSv4.1: Use the nfs_client's rpc timeouts for backchannel)
Merging nfsd/nfsd-next (7d3d6536ca8a nfsd: set security label during create operations)
Merging ntfs3/master (24f6f5020b0b fs/ntfs3: Mark volume as dirty if xattr is broken)
Merging orangefs/for-next (9bf93dcfc453 Julia Lawall reported this null pointer dereference, this should fix it.)
Merging overlayfs/overlayfs-next (096802748ea1 ovl: remove upper umask handling from ovl_create_upper())
Merging ubifs/next (b8a77b9a5f9c mtd: ubi: fix NVMEM over UBI volumes on 32-bit systems)
Merging v9fs/9p-next (2a0505cdd8c8 9p: remove SLAB_MEM_SPREAD flag usage)
Merging v9fs-ericvh/ericvh/for-next (4cece7649650 Linux 6.9-rc1)
Merging xfs/for-next (25576c5420e6 xfs: simplify iext overflow checking and upgrade)
Merging zonefs/for-next (567e629fd296 zonefs: convert zonefs to use the new mount api)
Merging iomap/iomap-for-next (3ac974796e5d iomap: fix short copy in iomap_write_iter())
Merging djw-vfs/vfs-for-next (ce85a1e04645 xfs: stabilize fs summary counters for online fsck)
Merging file-locks/locks-next (e0152e7481c6 Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux)
Merging iversion/iversion-next (e0152e7481c6 Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux)
Merging vfs-brauner/vfs.all (bf0a67a23c55 Merge branch 'vfs.netfs' into vfs.all)
CONFLICT (content): Merge conflict in fs/btrfs/disk-io.c
CONFLICT (content): Merge conflict in fs/tracefs/inode.c
Merging vfs/for-next (7c98f7cb8fda remove call_{read,write}_iter() functions)
Merging printk/for-next (a2b4cab9da77 Merge branch 'for-6.10' into for-next)
Merging pci/next (ccd0bdb57e31 Merge branch 'pci/misc')
Merging pstore/for-next/pstore (9dd12ed95c2d pstore/blk: replace deprecated strncpy with strscpy)
Merging hid/for-next (d82775b90601 Merge branch 'for-6.10/sony' into for-next)
Merging i2c/i2c/for-next (5deb5b56bccb i2c: smbus: fix NULL function pointer dereference)
Merging i2c-host/i2c/i2c-host (61e05bad821c i2c: designware: Replace MODULE_ALIAS() with MODULE_DEVICE_TABLE())
Merging i3c/i3c/next (8f06fb458539 i3c: Make i3c_bus_type const)
Merging dmi/dmi-for-next (0ef11f604503 firmware: dmi: Stop decoding on broken entry)
Merging hwmon-staging/hwmon-next (45bf8305fb2e hwmon: (max6639) Use regmap)
Merging jc_docs/docs-next (404b444fbb3d Merge branch 'docs-mw' into docs-next)
Merging v4l-dvb/master (4a7d735191de media: dw2102: fix coding style issues)
Merging v4l-dvb-next/master (8a09bb1be67a media: intel/ipu6: Don't re-allocate memory for firmware)
Applying: media: intel/ipu6: explicitly include vmalloc.h
Merging pm/linux-next (058b3af4882a Merge branches 'acpica', 'acpi-scan' and 'acpi-resource' into linux-next)
Merging cpufreq-arm/cpufreq/arm/linux-next (fde234239d16 dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles)
Merging cpupower/cpupower (55f9f60852ef tools/power/cpupower: Fix Pstate frequency reporting on AMD Family 1Ah CPUs)
Merging devfreq/devfreq-next (6f3c0cfe2aa5 PM / devfreq: rk3399_dmc: Convert to platform remove callback returning void)
Merging pmdomain/next (d88ea3034096 pmdomain: Merge branch fixes into next)
Merging opp/opp/linux-next (4cece7649650 Linux 6.9-rc1)
Merging thermal/thermal/linux-next (734b5def91b5 thermal/drivers/loongson2: Add Loongson-2K2000 support)
Merging dlm/next (7b72ab2c6a46 dlm: return -ENOMEM if ls_recover_buf fails)
Merging rdma/for-next (e4e40a87024c RDMA/ipoib: Remove NULL check before dev_{put, hold})
Merging net-next/main (cdc74c9d06e7 Merge branch 'gve-queue-api')
CONFLICT (content): Merge conflict in drivers/net/wireless/intel/iwlwifi/mvm/Makefile
CONFLICT (content): Merge conflict in drivers/of/property.c
CONFLICT (content): Merge conflict in include/linux/slab.h
Merging bpf-next/for-next (a9e7715ce8b3 libbpf: Avoid casts from pointers to enums in bpf_tracing.h)
Merging ipsec-next/master (dcf280ea0aad Merge remote branch 'xfrm: Introduce direction attribute for SA')
Merging mlx5-next/mlx5-next (d727d27db536 RDMA/mlx5: Expose register c0 for RDMA device)
Merging netfilter-next/main (ed1f164038b5 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net)
Merging ipvs-next/main (ed1f164038b5 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net)
Merging bluetooth/master (f7bbc1e0ec8f Bluetooth: hci_conn: Use __counted_by() and avoid -Wfamnae warning)
0438daa3384a ("Bluetooth: qca: fix info leak when fetching board id")
3da8bd8c636d ("Bluetooth: qca: fix wcn3991 device address check")
438fcfbffd50 ("Bluetooth: qca: fix NVM configuration parsing")
540587c30a7b ("Bluetooth: HCI: Fix potential null-ptr-deref")
639fb017762b ("Bluetooth: msft: fix slab-use-after-free in msft_do_close()")
a757a088c27b ("arm64: dts: mediatek: mt8183-pico6: Fix bluetooth node")
a7632943b8d8 ("Bluetooth: qca: fix firmware check error path")
acef4e6d383c ("Bluetooth: qca: generalise device address check")
bf6e892b6fd5 ("Bluetooth: l2cap: fix null-ptr-deref in l2cap_chan_timeout")
ce5e3554beb7 ("Bluetooth: Fix use-after-free bugs caused by sco_sock_timeout")
e3631691e44b ("Bluetooth: qca: fix info leak when fetching fw build id")
f905ae0be4b7 ("Bluetooth: qca: add missing firmware sanity checks")
CONFLICT (content): Merge conflict in drivers/bluetooth/btqca.c
CONFLICT (content): Merge conflict in drivers/bluetooth/btqca.h
CONFLICT (content): Merge conflict in net/bluetooth/l2cap_core.c
Merging wireless-next/for-next (f1c26960b6af Merge tag 'ath-next-20240502' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath)
Merging wpan-next/master (9187210eee7d Merge tag 'net-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next)
Merging wpan-staging/staging (9187210eee7d Merge tag 'net-next-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next)
Merging mtd/mtd/next (6277967d872e mtd: mchp23k256: drop unneeded MODULE_ALIAS)
Merging nand/nand/next (6819db94e1cd mtd: rawnand: hynix: fixed typo)
Merging spi-nor/spi-nor/next (c84b3925c7d6 mtd: spi-nor: replace unnecessary div64_u64() with div_u64())
Merging crypto/master (6117af863659 crypto: hisilicon/sec2 - fix for register offset)
Merging drm/drm-next (f03eee5fc922 Merge tag 'drm-xe-next-fixes-2024-05-02' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next)
28d21e3e66c5 ("drm/xe/vm: prevent UAF in rebind_work_func()")
8e1d1905951d ("drm/amdgpu: Fix VRAM memory accounting")
b528cac6deaa ("drm/amd/display: Handle Y carry-over in VCP X.Y calculation")
CONFLICT (content): Merge conflict in drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
Merging drm-exynos/for-linux-next (2236a61bd491 Merge tag 'mediatek-drm-next-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next)
Merging drm-misc/for-linux-next (be3f3042391d drm: zynqmp_dpsub: Always register bridge)
Merging amdgpu/drm-next (b0923d5d80fa drm/amdgpu: remove ip dump reg_count variable)
04790139c59a ("drm/amdgpu: fix doorbell regression")
2b6c4a4b7ae5 ("drm/amd/display: Ensure that dmcub support flag is set for DCN20")
35df442d813d ("drm/amd/display: Disable seamless boot on 128b/132b encoding")
6aa96aa8ffbe ("drm/amd/display: Fix DC mode screen flickering on DCN321")
771c75ad0bd2 ("drm/amd/display: Allocate zero bw after bw alloc enable")
81f3d3c9a037 ("drm/amd/display: Fix incorrect DSC instance for MST")
8acb83689258 ("drm/amd/display: Atom Integrated System Info v2_2 for DCN35")
a89a05e3ca3e ("drm/amdkfd: Flush the process wq before creating a kfd_process")
b9f5fcef7280 ("drm/amd/display: Add VCO speed parameter for DCN31 FPU")
c83ad4c3f943 ("drm/amd/display: Add dtbclk access to dcn315")
d17846a096b3 ("drm/amd/display: Disable panel replay by default for now")
ffda7081489b ("drm/amdgpu: once more fix the call oder in amdgpu_ttm_move() v2")
Merging drm-intel/for-linux-next (ca5d5ecbb90d drm/xe/bmg: Enable the display support)
Merging drm-tegra/for-next (2429b3c529da drm/tegra: Avoid potential 32-bit integer overflow)
Merging drm-msm/msm-next (104e548a7c97 drm/msm/mdp4: use drmm-managed allocation for mdp4_plane)
CONFLICT (content): Merge conflict in drivers/gpu/drm/msm/Makefile
Merging drm-msm-lumag/msm-next-lumag (104e548a7c97 drm/msm/mdp4: use drmm-managed allocation for mdp4_plane)
Merging drm-xe/drm-xe-next (e9c190b9b8e7 drm/xe: Demote CCS_MODE info to debug only)
CONFLICT (content): Merge conflict in drivers/gpu/drm/xe/xe_device.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/xe/xe_vm.c
Merging etnaviv/etnaviv/next (b735ee173f84 drm/etnaviv: Restore some id values)
Merging fbdev/for-next (ce4a7ae84a58 fbdev: offb: replace of_node_put with __free(device_node))
Merging regmap/for-next (991b5e2aad87 regmap: kunit: Fix an NULL vs IS_ERR() check)
Merging sound/for-next (e7aeb238026c ALSA: aoa: soundbus: i2sbus: pcm: use 'time_left' variable with wait_for_completion_timeout())
Merging ieee1394/for-next (6b0b708f12d1 firewire: core: add tracepoint event for handling bus reset)
Merging sound-asoc/for-next (3785e220fd42 Merge remote-tracking branch 'asoc/for-6.10' into asoc-next)
Merging modules/modules-next (493abdac43bf bpf: remove CONFIG_BPF_JIT dependency on CONFIG_MODULES of)
CONFLICT (content): Merge conflict in arch/powerpc/mm/mem.c
CONFLICT (content): Merge conflict in kernel/module/main.c
Merging input/next (7b4e0b39182c Input: cyapa - add missing input core locking to suspend/resume functions)
Merging block/for-next (7153772abb58 Merge branch 'for-6.10/block' into for-next)
CONFLICT (content): Merge conflict in io_uring/io_uring.c
CONFLICT (content): Merge conflict in io_uring/rw.c
Applying: fix up for "mm: switch mm->get_unmapped_area() to a flag"
Merging device-mapper/for-next (83637d9017b2 dm-crypt: don't set WQ_CPU_INTENSIVE for WQ_UNBOUND crypt_queue)
Merging libata/for-next (9e6938e14ea5 ata: libata-core: Remove ata_exec_internal_sg())
Merging pcmcia/pcmcia-next (ccae53aa8aa2 pcmcia: cs: make pcmcia_socket_class constant)
Merging mmc/next (35eea0defb6e mmc: renesas_sdhi: Add compatible string for RZ/G2L family, RZ/G3S, and RZ/V2M SoCs)
Merging mfd/for-mfd-next (7fcb2977c0b5 dt-bindings: mfd: Convert lp873x.txt to json-schema)
CONFLICT (content): Merge conflict in drivers/mfd/intel-lpss-pci.c
Merging backlight/for-backlight-next (4da294108e38 backlight: sky81452-backlight: Remove unnecessary call to of_node_get())
Merging battery/for-next (50f0ff7c8cc4 power: supply: bq27xxx: Move health reading out of update loop)
Merging regulator/for-next (d3ff4628b912 Merge remote-tracking branch 'regulator/for-6.10' into regulator-next)
Merging security/next (67889688e05b MAINTAINERS: update the LSM file list)
Merging apparmor/apparmor-next (8ead196be219 apparmor: Fix memory leak in unpack_profile())
Merging integrity/next-integrity (9fa8e7625008 ima: add crypto agility support for template-hash algorithm)
Merging selinux/next (4b60f3cd1134 Automated merge of 'dev' into 'next')
Merging smack/next (69b6d71052b5 Smack: use init_task_smack() in smack_cred_transfer())
Merging tomoyo/master (0bb80ecc33a8 Linux 6.6-rc1)
Merging tpmdd/next (152585665f0f docs: trusted-encrypted: add DCP as new trust source)
71dd2201bdef ("MAINTAINERS: Update URL's for KEYS/KEYRINGS_INTEGRITY and TPM DEVICE DRIVER")
Merging watchdog/master (413bf4e857fd watchdog: sa1100: Fix PTR_ERR_OR_ZERO() vs NULL check in sa1100dog_probe())
Merging iommu/next (ef6e717d93c7 Merge branches 'arm/renesas', 'x86/amd', 'core' and 'x86/vt-d' into next)
CONFLICT (content): Merge conflict in drivers/acpi/scan.c
CONFLICT (content): Merge conflict in drivers/iommu/amd/amd_iommu.h
Merging audit/next (4cece7649650 Linux 6.9-rc1)
Merging devicetree/for-next (649bad67d4b1 dt-bindings: PCI: microchip: increase number of items in ranges property)
CONFLICT (content): Merge conflict in drivers/of/dynamic.c
CONFLICT (content): Merge conflict in drivers/of/property.c
Merging dt-krzk/for-next (3d679a406f3a Merge branch 'next/dt64' into for-next)
Merging mailbox/for-next (0ac39d85a741 mailbox: zynqmp: Enable Bufferless IPI usage on Versal-based SOC's)
Merging spi/for-next (7f17199c1f36 Merge remote-tracking branch 'spi/for-6.10' into spi-next)
Merging tip/master (7de3d344c432 Merge branch into tip/master: 'x86/timers')
CONFLICT (content): Merge conflict in arch/arm64/boot/dts/st/stm32mp251.dtsi
Merging clockevents/timers/drivers/next (8248ca30ef89 clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization)
Merging edac/edac-for-next (03db22b93a01 Merge ras/edac-urgent into for-next)
Merging ftrace/for-next (7604256cecef tracing: Add __string_src() helper to help compilers not to get confused)
Merging rcu/rcu/next (e7d6f9dff52c rcu/nocb: Remove buggy bypass lock contention mitigation)
CONFLICT (content): Merge conflict in arch/Kconfig
Merging kvm/next (a96cb3bf390e Merge x86 bugfixes from Linux 6.9-rc3)
CONFLICT (content): Merge conflict in arch/x86/kvm/svm/svm.c
Applying: fixup for "KVM: VMX: Move posted interrupt descriptor out of VMX code"
Merging kvm-arm/next (b63b7db624b3 Merge branch kvm-arm64/misc-6.10 into kvmarm-master/next)
Merging kvms390/next (39cd87c4eb2b Linux 6.9-rc2)
Merging kvm-ppc/topic/ppc-kvm (41bccc98fb79 Linux 6.8-rc2)
Merging kvm-riscv/riscv_kvm_next (5ef2f3d4e747 KVM: riscv: selftests: Add commandline option for SBI PMU test)
Merging kvm-x86/next (d91a9cc16417 Merge branches 'fixes', 'generic', 'misc', 'mmu', 'selftests', 'selftests_utils' and 'vmx')
CONFLICT (content): Merge conflict in tools/testing/selftests/kvm/aarch64/psci_test.c
Merging xen-tip/linux-next (802600ebdf23 x86/xen: return a sane initial apic id when running as PV guest)
Merging percpu/for-next (2d9ad81ef935 Merge branch 'for-6.8-fixes' into for-next)
Merging workqueues/for-next (24283babc61f Merge branch 'for-6.9-fixes' into for-next)
Merging drivers-x86/for-next (76f09e22027f platform/x86: ISST: Support SST-BF and SST-TF per level)
CONFLICT (content): Merge conflict in MAINTAINERS
Merging chrome-platform/for-next (2fbe479c0024 platform/chrome: cros_ec: Handle events during suspend after resume completion)
Merging chrome-platform-firmware/for-firmware-next (7f20f21c22aa firmware: google: cbmem: drop driver owner initialization)
Merging hsi/for-next (c076486b6a28 HSI: omap_ssi_port: Convert to platform remove callback returning void)
Merging leds-lj/for-leds-next (f2994f5341e0 leds: mt6370: Remove unused field 'reg_cfgs' from 'struct mt6370_priv')
Merging ipmi/for-next (999dff3c1393 ipmi: kcs_bmc_npcm7xx: Convert to platform remove callback returning void)
Merging driver-core/driver-core-next (e5019b14230a Merge 6.9-rc5 into driver-core-next)
Merging usb/usb-next (b3e40fc85735 USB: usb_parse_endpoint: ignore reserved bits)
CONFLICT (content): Merge conflict in drivers/usb/dwc3/core.c
Merging thunderbolt/next (a3dc6d82de9b thunderbolt: Correct trace output of firmware connection manager packets)
Merging usb-serial/usb-next (39cd87c4eb2b Linux 6.9-rc2)
Merging tty/tty-next (6bd23e0c2bb6 tty: add the option to have a tty reject a new ldisc)
CONFLICT (content): Merge conflict in include/linux/kfifo.h
CONFLICT (content): Merge conflict in lib/kfifo.c
Merging char-misc/char-misc-next (1565fce99bd0 Merge tag 'iio-for-6.10b-take2' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next)
Merging accel/habanalabs-next (576d7cc5a9e2 accel: constify the struct device_type usage)
Merging coresight/next (9b47d9982d1d hwtracing: hisi_ptt: Assign parent for event_source device)
Merging fastrpc/for-next (4cece7649650 Linux 6.9-rc1)
Merging fpga/for-next (b7c0e1ecee40 fpga: region: add owner module and take its refcount)
Merging icc/icc-next (230d05b1179f interconnect: qcom: qcm2290: Fix mas_snoc_bimc QoS port assignment)
Merging iio/togreg (827dca312970 iio: temperature: mcp9600: Fix temperature reading for negative values)
Merging phy-next/next (960b3f023d3b dt-bindings: phy: qcom,usb-snps-femto-v2: use correct fallback for sc8180x)
Merging soundwire/next (a0df7e04eab0 soundwire: intel_ace2.x: add support for DOAISE property)
Merging extcon/extcon-next (abe83c4e5e4f extcon: realtek: Remove unused of_gpio.h)
Merging gnss/gnss-next (0bbac3facb5d Linux 6.9-rc4)
Merging vfio/next (bb208810b1ab vfio/qat: Add vfio_pci driver for Intel QAT SR-IOV VF devices)
Merging w1/for-next (cde37a5bdb0e w1: gpio: Don't use "proxy" headers)
Merging spmi/spmi-next (3bb8cd556eae spmi: pmic-arb: Add multi bus support)
Merging staging/staging-next (eb563dc752d3 staging: pi433: Remove unused driver)
Merging counter-next/counter-next (89d5d9e95008 counter: Don't use "proxy" headers)
Merging siox/siox/for-next (db418d5f1ca5 siox: bus-gpio: Simplify using devm_siox_* functions)
Merging mux/for-next (44c026a73be8 Linux 6.4-rc3)
Merging dmaengine/next (28059ddbee0e MAINTAINERS: Update role for IDXD driver)
Merging cgroup/for-next (8f6d24a5db2a selftests/cgroup: fix uninitialized variables in test_zswap.c)
Merging scsi/for-next (8c5220c43ba0 Merge branch 'fixes' into for-next)
CONFLICT (content): Merge conflict in block/blk-settings.c
CONFLICT (content): Merge conflict in include/linux/blkdev.h
Merging scsi-mkp/for-next (aca061774bc4 scsi: mpi3mr: Fix some kernel-doc warnings in scsi_bsg_mpi3mr.h)
Merging vhost/linux-next (88199634e516 vduse: enable Virtio-net device type)
CONFLICT (content): Merge conflict in drivers/virtio/virtio_mem.c
Merging rpmsg/for-next (0496190c4d42 Merge branches 'rproc-next' and 'rpmsg-next' into for-next)
Merging gpio/for-next (0bb80ecc33a8 Linux 6.6-rc1)
Merging gpio-brgl/gpio/for-next (5539287ca656 gpio: brcmstb: add support for gpio-ranges)
Merging gpio-intel/for-next (ecc4b1418e23 gpio: Add Intel Granite Rapids-D vGPIO driver)
Merging pinctrl/for-next (077895d14a6b Merge branch 'devel' into for-next)
Merging pinctrl-intel/for-next (5d10a157ebe0 pinctrl: baytrail: Add pinconf group for uart3)
Merging pinctrl-renesas/renesas-pinctrl (cd27553b0dee pinctrl: renesas: rzg2l: Limit 2.5V power supply to Ethernet interfaces)
Merging pinctrl-samsung/for-next (e5b3732a9654 pinctrl: samsung: drop redundant drvdata assignment)
Merging pwm/pwm/for-next (b664fc60d7f8 dt-bindings: pwm: snps,dw-apb-timers: Do not require pwm-cells twice)
Merging ktest/for-next (07283c1873a4 ktest: force $buildonly = 1 for 'make_warnings_file' test type)
Merging kselftest/next (70bfefe4252d selftests: default to host arch for LLVM builds)
CONFLICT (content): Merge conflict in tools/testing/selftests/mm/soft-dirty.c
Merging kunit/test (4cece7649650 Linux 6.9-rc1)
Merging kunit-next/kunit (2168e528f867 kunit: bail out early in __kunit_test_suites_init() if there are no suites to test)
Merging livepatching/for-next (602bf1830798 Merge branch 'for-6.7' into for-next)
Merging rtc/rtc-next (1c431b92e21b dt-bindings: rtc: convert trivial devices into dtschema)
Merging nvdimm/libnvdimm-for-next (41147b006be2 dax: remove redundant assignment to variable rc)
Merging at24/at24/for-next (4cece7649650 Linux 6.9-rc1)
Merging ntb/ntb-next (9341b37ec17a ntb_perf: Fix printk format)
Merging seccomp/for-next/seccomp (39cd87c4eb2b Linux 6.9-rc2)
Merging fsi/next (c5eeb63edac9 fsi: Fix panic on scom file read)
Merging slimbus/for-next (b12bd525ca6e slimbus: qcom-ngd-ctrl: Add timeout for wait operation)
5e8e32f81813 ("slimbus: qcom-ngd-ctrl: Reduce auto suspend delay")
772be93c1c24 ("slimbus: qcom-ctrl: fix module autoloading")
b12bd525ca6e ("slimbus: qcom-ngd-ctrl: Add timeout for wait operation")
f6c637ffe528 ("slimbus: Convert to platform remove callback returning void")
Merging nvmem/for-next (9e29a1dba59b nvmem: meson-mx-efuse: Remove nvmem_device from efuse struct)
04075398ec4f ("nvmem: lpc18xx_eeprom: Convert to platform remove callback returning void")
2ce7240c076f ("dt-bindings: nvmem: Add compatible for SC8280XP")
3575d48e5d2f ("nvmem: layouts: sl28vpd: drop driver owner initialization")
995b22c48ed0 ("nvmem: layouts: onie-tlv: drop driver owner initialization")
9e29a1dba59b ("nvmem: meson-mx-efuse: Remove nvmem_device from efuse struct")
af868167a709 ("dt-bindings: nvmem: qcom,spmi-sdam: update maintainer")
e428f11ae8fb ("nvmem: layouts: store owner from modules with nvmem_layout_driver_register()")
e5630036dab1 ("dt-bindings: nvmem: Add compatible for sm8450, sm8550 and sm8650")
ea8f9ec2bbb7 ("nvmem: core: switch to use device_add_groups()")
fbd0d725d4fa ("nvmem: sprd: fix module autoloading")
fc7d05b8e427 ("nvmem: sc27xx: fix module autoloading")
Merging xarray/main (2a15de80dd0f idr: fix param name in idr_alloc_cyclic() doc)
Merging hyperv/hyperv-next (f2580a907e5c x86/hyperv: Use Hyper-V entropy to seed guest random number generator)
Merging auxdisplay/for-next (93ee235f55d3 auxdisplay: charlcd: Don't rebuild when CONFIG_PANEL_BOOT_MESSAGE=y)
Merging kgdb/kgdb/for-next (b2aba15ad6f9 serial: kgdboc: Fix NMI-safety problems from keyboard reset code)
Merging hmm/hmm (6613476e225e Linux 6.8-rc1)
Merging cfi/cfi/next (06c2afb862f9 Linux 6.5-rc1)
Merging mhi/mhi-next (48f98496b1de bus: mhi: host: pci_generic: Add generic edl_trigger to allow devices to enter EDL mode)
Merging memblock/for-next (e5d1fdecfaf8 mm/memblock: remove empty dummy entry)
Merging cxl/next (d99f13843237 cxl/cper: Remove duplicated GUID defines)
Merging zstd/zstd-next (3f832dfb8a8e zstd: fix g_debuglevel export warning)
Merging efi/next (4b2543f7e1e6 efi: libstub: only free priv.runtime_map when allocated)
Merging unicode/for-next (0131c1f3cce7 unicode: make utf8 test count static)
Merging slab/slab/for-next (4a8dd3b3d550 Merge branch 'slab/for-6.10/cleanup' into slab/for-next)
Merging random/master (7b1bcd6b50a6 virt: vmgenid: add support for devicetree bindings)
CONFLICT (content): Merge conflict in drivers/virt/vmgenid.c
Merging landlock/next (d6a07bb3c18c MAINTAINERS: Add Günther Noack as Landlock reviewer)
Merging rust/rust-next (56f64b370612 rust: upgrade to Rust 1.78.0)
CONFLICT (content): Merge conflict in rust/Makefile
Merging sysctl/sysctl-next (a35dd3a786f5 sysctl: drop now unnecessary out-of-bounds check)
Merging execve/for-next/execve (10e29251be0e binfmt_elf_fdpic: fix /proc/<pid>/auxv)
Merging bitmap/bitmap-for-next (2eb411f428b8 MAINTAINERS: add BITOPS API record)
Merging hte/for-next (297f26dbf870 hte: tegra-194: Convert to platform remove callback returning void)
Merging kspp/for-next/kspp (0e148d3cca0d stackleak: Use a copy of the ctl_table argument)
Merging kspp-gustavo/for-next/kspp (6613476e225e Linux 6.8-rc1)
Merging nolibc/nolibc (0adab2b6b733 tools/nolibc: add support for uname(2))
Merging tsm/tsm-next (f4738f56d1dc virt: tdx-guest: Add Quote generation support using TSM_REPORTS)
Merging iommufd/for-next (4cece7649650 Linux 6.9-rc1)
Merging turbostat/next (6b9cd589464f tools/power turbostat: version 2024.04.27)
Merging refactor-heap/refactor-heap (940c306fd779 bcachefs: Remove heap-related macros and switch to generic min_heap)
Merging header_cleanup/header_cleanup (5f4c01f1e3c7 spinlock: Fix failing build for PREEMPT_RT)
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* linux-next: duplicate patches in the nvmem tree
@ 2024-05-06 5:42 5% Stephen Rothwell
0 siblings, 0 replies; 200+ results
From: Stephen Rothwell @ 2024-05-06 5:42 UTC (permalink / raw)
To: Srinivas Kandagatla, Greg KH, Arnd Bergmann
Cc: Linux Kernel Mailing List, Linux Next Mailing List
[-- Attachment #1: Type: text/plain, Size: 1870 bytes --]
Hi all,
The following commits are also in the char-misc tree as different
commits (but the same patches):
9e29a1dba59b ("nvmem: meson-mx-efuse: Remove nvmem_device from efuse struct")
2ce7240c076f ("dt-bindings: nvmem: Add compatible for SC8280XP")
af868167a709 ("dt-bindings: nvmem: qcom,spmi-sdam: update maintainer")
e5630036dab1 ("dt-bindings: nvmem: Add compatible for sm8450, sm8550 and sm8650")
04075398ec4f ("nvmem: lpc18xx_eeprom: Convert to platform remove callback returning void")
ea8f9ec2bbb7 ("nvmem: core: switch to use device_add_groups()")
fbd0d725d4fa ("nvmem: sprd: fix module autoloading")
fc7d05b8e427 ("nvmem: sc27xx: fix module autoloading")
3575d48e5d2f ("nvmem: layouts: sl28vpd: drop driver owner initialization")
995b22c48ed0 ("nvmem: layouts: onie-tlv: drop driver owner initialization")
e428f11ae8fb ("nvmem: layouts: store owner from modules with nvmem_layout_driver_register()")
These are commits
2a1ad6b75292 ("nvmem: meson-mx-efuse: Remove nvmem_device from efuse struct")
a5888ae5b3c3 ("dt-bindings: nvmem: Add compatible for SC8280XP")
dc5d4043510b ("dt-bindings: nvmem: qcom,spmi-sdam: update maintainer")
e2c7d6e02382 ("dt-bindings: nvmem: Add compatible for sm8450, sm8550 and sm8650")
693d2f629962 ("nvmem: lpc18xx_eeprom: Convert to platform remove callback returning void")
8d8fc146dd7a ("nvmem: core: switch to use device_add_groups()")
154c1ec943e3 ("nvmem: sprd: fix module autoloading")
dc3d88ade857 ("nvmem: sc27xx: fix module autoloading")
23fd602f2195 ("nvmem: layouts: sl28vpd: drop driver owner initialization")
21833338eccb ("nvmem: layouts: onie-tlv: drop driver owner initialization")
6d0ca4a2a7e2 ("nvmem: layouts: store owner from modules with nvmem_layout_driver_register()")
in the char-misc tree.
--
Cheers,
Stephen Rothwell
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* [PATCH v3 4/8] clk: qcom: Add Display Clock Controller driver for SM7150
@ 2024-05-05 20:10 2% ` Danila Tikhonov
2024-05-05 20:10 1% ` [PATCH v3 6/8] clk: qcom: Add Camera " Danila Tikhonov
2024-05-05 20:10 9% ` [PATCH v3 8/8] clk: qcom: Add Video " Danila Tikhonov
2 siblings, 0 replies; 200+ results
From: Danila Tikhonov @ 2024-05-05 20:10 UTC (permalink / raw)
To: andersson, konrad.dybcio, mturquette, sboyd, robh, krzk+dt,
conor+dt, david, adrian
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, Danila Tikhonov
Add support for the display clock controller found on SM7150.
Co-developed-by: David Wronek <david@mainlining.org>
Signed-off-by: David Wronek <david@mainlining.org>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/dispcc-sm7150.c | 1006 ++++++++++++++++++++++++++++++
3 files changed, 1017 insertions(+)
create mode 100644 drivers/clk/qcom/dispcc-sm7150.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 2b0e536d6d70..7b4c2ff580a3 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -847,6 +847,16 @@ config SM_DISPCC_6125
Say Y if you want to support display devices and functionality such as
splash screen
+config SM_DISPCC_7150
+ tristate "SM7150 Display Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ depends on SM_GCC_7150
+ help
+ Support for the display clock controller on Qualcomm Technologies, Inc
+ SM7150 devices.
+ Say Y if you want to support display devices and functionality such as
+ splash screen.
+
config SM_DISPCC_8250
tristate "SM8150/SM8250/SM8350 Display Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index dec5b6db6860..cdec5ce2bb94 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -113,6 +113,7 @@ obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
obj-$(CONFIG_SM_DISPCC_6375) += dispcc-sm6375.o
+obj-$(CONFIG_SM_DISPCC_7150) += dispcc-sm7150.o
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o
diff --git a/drivers/clk/qcom/dispcc-sm7150.c b/drivers/clk/qcom/dispcc-sm7150.c
new file mode 100644
index 000000000000..5c8ae95b6763
--- /dev/null
+++ b/drivers/clk/qcom/dispcc-sm7150.c
@@ -0,0 +1,1006 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
+ * Copyright (c) 2024, David Wronek <david@mainlining.org>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,sm7150-dispcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "gdsc.h"
+
+enum {
+ DT_BI_TCXO,
+ DT_BI_TCXO_AO,
+ DT_GCC_DISP_GPLL0_CLK,
+ DT_CHIP_SLEEP_CLK,
+ DT_DSI0_PHY_PLL_OUT_BYTECLK,
+ DT_DSI0_PHY_PLL_OUT_DSICLK,
+ DT_DSI1_PHY_PLL_OUT_BYTECLK,
+ DT_DSI1_PHY_PLL_OUT_DSICLK,
+ DT_DP_PHY_PLL_LINK_CLK,
+ DT_DP_PHY_PLL_VCO_DIV_CLK,
+};
+
+enum {
+ P_BI_TCXO,
+ P_CHIP_SLEEP_CLK,
+ P_DISPCC_PLL0_OUT_EVEN,
+ P_DISPCC_PLL0_OUT_MAIN,
+ P_DP_PHY_PLL_LINK_CLK,
+ P_DP_PHY_PLL_VCO_DIV_CLK,
+ P_DSI0_PHY_PLL_OUT_BYTECLK,
+ P_DSI0_PHY_PLL_OUT_DSICLK,
+ P_DSI1_PHY_PLL_OUT_BYTECLK,
+ P_DSI1_PHY_PLL_OUT_DSICLK,
+ P_GCC_DISP_GPLL0_CLK,
+};
+
+static const struct pll_vco fabia_vco[] = {
+ { 249600000, 2000000000, 0 },
+ { 125000000, 1000000000, 1 },
+};
+
+/* 860MHz configuration */
+static const struct alpha_pll_config dispcc_pll0_config = {
+ .l = 0x2c,
+ .alpha = 0xcaaa,
+ .test_ctl_val = 0x40000000,
+};
+
+static struct clk_alpha_pll dispcc_pll0 = {
+ .offset = 0x0,
+ .vco_table = fabia_vco,
+ .num_vco = ARRAY_SIZE(fabia_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_pll0",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fabia_ops,
+ },
+ },
+};
+
+static const struct parent_map dispcc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
+ { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
+};
+
+static const struct clk_parent_data dispcc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
+ { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
+};
+
+static const struct parent_map dispcc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_DP_PHY_PLL_LINK_CLK, 1 },
+ { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
+};
+
+static const struct clk_parent_data dispcc_parent_data_1[] = {
+ { .index = DT_BI_TCXO },
+ { .index = DT_DP_PHY_PLL_LINK_CLK },
+ { .index = DT_DP_PHY_PLL_VCO_DIV_CLK },
+};
+
+static const struct parent_map dispcc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+};
+
+static const struct clk_parent_data dispcc_parent_data_2[] = {
+ { .index = DT_BI_TCXO },
+};
+
+static const struct clk_parent_data dispcc_parent_data_2_ao[] = {
+ { .index = DT_BI_TCXO_AO },
+};
+
+static const struct parent_map dispcc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+ { P_DISPCC_PLL0_OUT_MAIN, 1 },
+ { P_GCC_DISP_GPLL0_CLK, 4 },
+ { P_DISPCC_PLL0_OUT_EVEN, 5 },
+};
+
+static const struct clk_parent_data dispcc_parent_data_3[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &dispcc_pll0.clkr.hw },
+ { .index = DT_GCC_DISP_GPLL0_CLK },
+ { .hw = &dispcc_pll0.clkr.hw },
+};
+
+static const struct parent_map dispcc_parent_map_4[] = {
+ { P_BI_TCXO, 0 },
+ { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
+ { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
+};
+
+static const struct clk_parent_data dispcc_parent_data_4[] = {
+ { .index = DT_BI_TCXO },
+ { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
+ { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
+};
+
+static const struct parent_map dispcc_parent_map_5[] = {
+ { P_BI_TCXO, 0 },
+ { P_GCC_DISP_GPLL0_CLK, 4 },
+};
+
+static const struct clk_parent_data dispcc_parent_data_5[] = {
+ { .index = DT_BI_TCXO },
+ { .index = DT_GCC_DISP_GPLL0_CLK },
+};
+
+static const struct parent_map dispcc_parent_map_6[] = {
+ { P_CHIP_SLEEP_CLK, 0 },
+};
+
+static const struct clk_parent_data dispcc_parent_data_6[] = {
+ { .index = DT_CHIP_SLEEP_CLK },
+};
+
+static const struct freq_tbl ftbl_dispcc_mdss_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
+ F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 dispcc_mdss_ahb_clk_src = {
+ .cmd_rcgr = 0x22bc,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_5,
+ .freq_tbl = ftbl_dispcc_mdss_ahb_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_ahb_clk_src",
+ .parent_data = dispcc_parent_data_5,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_5),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_dispcc_mdss_byte0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 dispcc_mdss_byte0_clk_src = {
+ .cmd_rcgr = 0x2110,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_0,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_byte0_clk_src",
+ .parent_data = dispcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_byte2_ops,
+ },
+};
+
+static struct clk_rcg2 dispcc_mdss_byte1_clk_src = {
+ .cmd_rcgr = 0x212c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_0,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_byte1_clk_src",
+ .parent_data = dispcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_byte2_ops,
+ },
+};
+
+static struct clk_rcg2 dispcc_mdss_dp_aux_clk_src = {
+ .cmd_rcgr = 0x21dc,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_2,
+ .freq_tbl = ftbl_dispcc_mdss_byte0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_dp_aux_clk_src",
+ .parent_data = dispcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_dispcc_mdss_dp_crypto_clk_src[] = {
+ F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
+ F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
+ F(360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
+ F(540000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 dispcc_mdss_dp_crypto_clk_src = {
+ .cmd_rcgr = 0x2194,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_1,
+ .freq_tbl = ftbl_dispcc_mdss_dp_crypto_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_dp_crypto_clk_src",
+ .parent_data = dispcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 dispcc_mdss_dp_link_clk_src = {
+ .cmd_rcgr = 0x2178,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_1,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_dp_link_clk_src",
+ .parent_data = dispcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_byte2_ops,
+ },
+};
+
+static struct clk_rcg2 dispcc_mdss_dp_pixel1_clk_src = {
+ .cmd_rcgr = 0x21c4,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_1,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_dp_pixel1_clk_src",
+ .parent_data = dispcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_dp_ops,
+ },
+};
+
+static struct clk_rcg2 dispcc_mdss_dp_pixel_clk_src = {
+ .cmd_rcgr = 0x21ac,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_1,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_dp_pixel_clk_src",
+ .parent_data = dispcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_dp_ops,
+ },
+};
+
+static struct clk_rcg2 dispcc_mdss_esc0_clk_src = {
+ .cmd_rcgr = 0x2148,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_0,
+ .freq_tbl = ftbl_dispcc_mdss_byte0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_esc0_clk_src",
+ .parent_data = dispcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 dispcc_mdss_esc1_clk_src = {
+ .cmd_rcgr = 0x2160,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_0,
+ .freq_tbl = ftbl_dispcc_mdss_byte0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_esc1_clk_src",
+ .parent_data = dispcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_dispcc_mdss_mdp_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(85714286, P_GCC_DISP_GPLL0_CLK, 7, 0, 0),
+ F(100000000, P_GCC_DISP_GPLL0_CLK, 6, 0, 0),
+ F(150000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0),
+ F(172000000, P_DISPCC_PLL0_OUT_MAIN, 5, 0, 0),
+ F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
+ F(286666667, P_DISPCC_PLL0_OUT_MAIN, 3, 0, 0),
+ F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
+ F(344000000, P_DISPCC_PLL0_OUT_MAIN, 2.5, 0, 0),
+ F(430000000, P_DISPCC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 dispcc_mdss_mdp_clk_src = {
+ .cmd_rcgr = 0x20c8,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_3,
+ .freq_tbl = ftbl_dispcc_mdss_mdp_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_mdp_clk_src",
+ .parent_data = dispcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 dispcc_mdss_pclk0_clk_src = {
+ .cmd_rcgr = 0x2098,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_pclk0_clk_src",
+ .parent_data = dispcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_4),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_pixel_ops,
+ },
+};
+
+static struct clk_rcg2 dispcc_mdss_pclk1_clk_src = {
+ .cmd_rcgr = 0x20b0,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_pclk1_clk_src",
+ .parent_data = dispcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_4),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_pixel_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_dispcc_mdss_rot_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(171428571, P_GCC_DISP_GPLL0_CLK, 3.5, 0, 0),
+ F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
+ F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
+ F(344000000, P_DISPCC_PLL0_OUT_MAIN, 2.5, 0, 0),
+ F(430000000, P_DISPCC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 dispcc_mdss_rot_clk_src = {
+ .cmd_rcgr = 0x20e0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_3,
+ .freq_tbl = ftbl_dispcc_mdss_rot_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_rot_clk_src",
+ .parent_data = dispcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_3),
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 dispcc_mdss_vsync_clk_src = {
+ .cmd_rcgr = 0x20f8,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_2,
+ .freq_tbl = ftbl_dispcc_mdss_byte0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_vsync_clk_src",
+ .parent_data = dispcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_dispcc_sleep_clk_src[] = {
+ F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 dispcc_sleep_clk_src = {
+ .cmd_rcgr = 0x6060,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_6,
+ .freq_tbl = ftbl_dispcc_sleep_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_sleep_clk_src",
+ .parent_data = dispcc_parent_data_6,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_6),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 dispcc_xo_clk_src = {
+ .cmd_rcgr = 0x6044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = dispcc_parent_map_2,
+ .freq_tbl = ftbl_dispcc_mdss_byte0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_xo_clk_src",
+ .parent_data = dispcc_parent_data_2_ao,
+ .num_parents = ARRAY_SIZE(dispcc_parent_data_2_ao),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch dispcc_mdss_ahb_clk = {
+ .halt_reg = 0x2080,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2080,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_byte0_clk = {
+ .halt_reg = 0x2028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_byte0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_byte0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap_div dispcc_mdss_byte0_div_clk_src = {
+ .reg = 0x2128,
+ .shift = 0,
+ .width = 2,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_byte0_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_byte0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_byte0_intf_clk = {
+ .halt_reg = 0x202c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x202c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_byte0_intf_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_byte0_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_byte1_clk = {
+ .halt_reg = 0x2030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_byte1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_byte1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap_div dispcc_mdss_byte1_div_clk_src = {
+ .reg = 0x2144,
+ .shift = 0,
+ .width = 2,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_byte1_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_byte1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_byte1_intf_clk = {
+ .halt_reg = 0x2034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2034,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_byte1_intf_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_byte1_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_dp_aux_clk = {
+ .halt_reg = 0x2054,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2054,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_dp_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_dp_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_dp_crypto_clk = {
+ .halt_reg = 0x2048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_dp_crypto_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_dp_crypto_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_dp_link_clk = {
+ .halt_reg = 0x2040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_dp_link_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_dp_link_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_dp_link_intf_clk = {
+ .halt_reg = 0x2044,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_dp_link_intf_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_dp_link_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_dp_pixel1_clk = {
+ .halt_reg = 0x2050,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2050,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_dp_pixel1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_dp_pixel1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_dp_pixel_clk = {
+ .halt_reg = 0x204c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x204c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_dp_pixel_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_dp_pixel_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_esc0_clk = {
+ .halt_reg = 0x2038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_esc0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_esc0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_esc1_clk = {
+ .halt_reg = 0x203c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x203c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_esc1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_esc1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_mdp_clk = {
+ .halt_reg = 0x200c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_mdp_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_mdp_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_mdp_lut_clk = {
+ .halt_reg = 0x201c,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x201c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_mdp_lut_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_mdp_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_non_gdsc_ahb_clk = {
+ .halt_reg = 0x4004,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x4004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_non_gdsc_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_pclk0_clk = {
+ .halt_reg = 0x2004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_pclk0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_pclk0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_pclk1_clk = {
+ .halt_reg = 0x2008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_pclk1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_pclk1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_rot_clk = {
+ .halt_reg = 0x2014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_rot_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_rot_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_rscc_ahb_clk = {
+ .halt_reg = 0x400c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x400c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_rscc_ahb_clk",
+ .parent_names = (const char *[]) {
+ "dispcc_mdss_ahb_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_rscc_vsync_clk = {
+ .halt_reg = 0x4008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_rscc_vsync_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_vsync_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_mdss_vsync_clk = {
+ .halt_reg = 0x2024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_mdss_vsync_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &dispcc_mdss_vsync_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch dispcc_sleep_clk = {
+ .halt_reg = 0x6078,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6078,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "dispcc_sleep_clk",
+ .parent_names = (const char *[]) {
+ "dispcc_sleep_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc mdss_gdsc = {
+ .gdscr = 0x3000,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "mdss_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = HW_CTRL,
+};
+
+static struct clk_regmap *dispcc_sm7150_clocks[] = {
+ [DISPCC_MDSS_AHB_CLK] = &dispcc_mdss_ahb_clk.clkr,
+ [DISPCC_MDSS_AHB_CLK_SRC] = &dispcc_mdss_ahb_clk_src.clkr,
+ [DISPCC_MDSS_BYTE0_CLK] = &dispcc_mdss_byte0_clk.clkr,
+ [DISPCC_MDSS_BYTE0_CLK_SRC] = &dispcc_mdss_byte0_clk_src.clkr,
+ [DISPCC_MDSS_BYTE0_DIV_CLK_SRC] = &dispcc_mdss_byte0_div_clk_src.clkr,
+ [DISPCC_MDSS_BYTE0_INTF_CLK] = &dispcc_mdss_byte0_intf_clk.clkr,
+ [DISPCC_MDSS_BYTE1_CLK] = &dispcc_mdss_byte1_clk.clkr,
+ [DISPCC_MDSS_BYTE1_CLK_SRC] = &dispcc_mdss_byte1_clk_src.clkr,
+ [DISPCC_MDSS_BYTE1_DIV_CLK_SRC] = &dispcc_mdss_byte1_div_clk_src.clkr,
+ [DISPCC_MDSS_BYTE1_INTF_CLK] = &dispcc_mdss_byte1_intf_clk.clkr,
+ [DISPCC_MDSS_DP_AUX_CLK] = &dispcc_mdss_dp_aux_clk.clkr,
+ [DISPCC_MDSS_DP_AUX_CLK_SRC] = &dispcc_mdss_dp_aux_clk_src.clkr,
+ [DISPCC_MDSS_DP_CRYPTO_CLK] = &dispcc_mdss_dp_crypto_clk.clkr,
+ [DISPCC_MDSS_DP_CRYPTO_CLK_SRC] = &dispcc_mdss_dp_crypto_clk_src.clkr,
+ [DISPCC_MDSS_DP_LINK_CLK] = &dispcc_mdss_dp_link_clk.clkr,
+ [DISPCC_MDSS_DP_LINK_CLK_SRC] = &dispcc_mdss_dp_link_clk_src.clkr,
+ [DISPCC_MDSS_DP_LINK_INTF_CLK] = &dispcc_mdss_dp_link_intf_clk.clkr,
+ [DISPCC_MDSS_DP_PIXEL1_CLK] = &dispcc_mdss_dp_pixel1_clk.clkr,
+ [DISPCC_MDSS_DP_PIXEL1_CLK_SRC] = &dispcc_mdss_dp_pixel1_clk_src.clkr,
+ [DISPCC_MDSS_DP_PIXEL_CLK] = &dispcc_mdss_dp_pixel_clk.clkr,
+ [DISPCC_MDSS_DP_PIXEL_CLK_SRC] = &dispcc_mdss_dp_pixel_clk_src.clkr,
+ [DISPCC_MDSS_ESC0_CLK] = &dispcc_mdss_esc0_clk.clkr,
+ [DISPCC_MDSS_ESC0_CLK_SRC] = &dispcc_mdss_esc0_clk_src.clkr,
+ [DISPCC_MDSS_ESC1_CLK] = &dispcc_mdss_esc1_clk.clkr,
+ [DISPCC_MDSS_ESC1_CLK_SRC] = &dispcc_mdss_esc1_clk_src.clkr,
+ [DISPCC_MDSS_MDP_CLK] = &dispcc_mdss_mdp_clk.clkr,
+ [DISPCC_MDSS_MDP_CLK_SRC] = &dispcc_mdss_mdp_clk_src.clkr,
+ [DISPCC_MDSS_MDP_LUT_CLK] = &dispcc_mdss_mdp_lut_clk.clkr,
+ [DISPCC_MDSS_NON_GDSC_AHB_CLK] = &dispcc_mdss_non_gdsc_ahb_clk.clkr,
+ [DISPCC_MDSS_PCLK0_CLK] = &dispcc_mdss_pclk0_clk.clkr,
+ [DISPCC_MDSS_PCLK0_CLK_SRC] = &dispcc_mdss_pclk0_clk_src.clkr,
+ [DISPCC_MDSS_PCLK1_CLK] = &dispcc_mdss_pclk1_clk.clkr,
+ [DISPCC_MDSS_PCLK1_CLK_SRC] = &dispcc_mdss_pclk1_clk_src.clkr,
+ [DISPCC_MDSS_ROT_CLK] = &dispcc_mdss_rot_clk.clkr,
+ [DISPCC_MDSS_ROT_CLK_SRC] = &dispcc_mdss_rot_clk_src.clkr,
+ [DISPCC_MDSS_RSCC_AHB_CLK] = &dispcc_mdss_rscc_ahb_clk.clkr,
+ [DISPCC_MDSS_RSCC_VSYNC_CLK] = &dispcc_mdss_rscc_vsync_clk.clkr,
+ [DISPCC_MDSS_VSYNC_CLK] = &dispcc_mdss_vsync_clk.clkr,
+ [DISPCC_MDSS_VSYNC_CLK_SRC] = &dispcc_mdss_vsync_clk_src.clkr,
+ [DISPCC_PLL0] = &dispcc_pll0.clkr,
+ [DISPCC_SLEEP_CLK] = &dispcc_sleep_clk.clkr,
+ [DISPCC_SLEEP_CLK_SRC] = &dispcc_sleep_clk_src.clkr,
+ [DISPCC_XO_CLK_SRC] = &dispcc_xo_clk_src.clkr,
+};
+
+static struct gdsc *dispcc_sm7150_gdscs[] = {
+ [MDSS_GDSC] = &mdss_gdsc,
+};
+
+static const struct regmap_config dispcc_sm7150_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x10000,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc dispcc_sm7150_desc = {
+ .config = &dispcc_sm7150_regmap_config,
+ .clks = dispcc_sm7150_clocks,
+ .num_clks = ARRAY_SIZE(dispcc_sm7150_clocks),
+ .gdscs = dispcc_sm7150_gdscs,
+ .num_gdscs = ARRAY_SIZE(dispcc_sm7150_gdscs),
+};
+
+static const struct of_device_id dispcc_sm7150_match_table[] = {
+ { .compatible = "qcom,sm7150-dispcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, dispcc_sm7150_match_table);
+
+static int dispcc_sm7150_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &dispcc_sm7150_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_fabia_pll_configure(&dispcc_pll0, regmap, &dispcc_pll0_config);
+ /* Enable clock gating for DSI and MDP clocks */
+ regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
+
+ /* Keep some clocks always-on */
+ qcom_branch_set_clk_en(regmap, 0x605c); /* DISPCC_XO_CLK */
+
+ return qcom_cc_really_probe(pdev, &dispcc_sm7150_desc, regmap);
+}
+
+static struct platform_driver dispcc_sm7150_driver = {
+ .probe = dispcc_sm7150_probe,
+ .driver = {
+ .name = "dispcc-sm7150",
+ .of_match_table = dispcc_sm7150_match_table,
+ },
+};
+
+module_platform_driver(dispcc_sm7150_driver);
+
+MODULE_DESCRIPTION("Qualcomm SM7150 Display Clock Controller");
+MODULE_LICENSE("GPL");
--
2.44.0
^ permalink raw reply related [relevance 2%]
* [PATCH v3 8/8] clk: qcom: Add Video Clock Controller driver for SM7150
2024-05-05 20:10 2% ` [PATCH v3 4/8] clk: qcom: Add Display Clock Controller driver " Danila Tikhonov
2024-05-05 20:10 1% ` [PATCH v3 6/8] clk: qcom: Add Camera " Danila Tikhonov
@ 2024-05-05 20:10 9% ` Danila Tikhonov
2 siblings, 0 replies; 200+ results
From: Danila Tikhonov @ 2024-05-05 20:10 UTC (permalink / raw)
To: andersson, konrad.dybcio, mturquette, sboyd, robh, krzk+dt,
conor+dt, david, adrian
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, Danila Tikhonov
Add support for the video clock controller found on SM7150.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-sm7150.c | 357 ++++++++++++++++++++++++++++++
3 files changed, 368 insertions(+)
create mode 100644 drivers/clk/qcom/videocc-sm7150.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 14e19f4c804c..20ba2eeb24ec 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -1137,6 +1137,16 @@ config SM_TCSRCC_8650
Support for the TCSR clock controller on SM8650 devices.
Say Y if you want to use peripheral devices such as SD/UFS.
+config SM_VIDEOCC_7150
+ tristate "SM7150 Video Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ select SM_GCC_7150
+ select QCOM_GDSC
+ help
+ Support for the video clock controller on SM7150 devices.
+ Say Y if you want to support video devices and functionality such as
+ video encode and decode.
+
config SM_VIDEOCC_8150
tristate "SM8150 Video Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 9c83abef9cac..b7de8600dc3d 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -143,6 +143,7 @@ obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o
obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o
+obj-$(CONFIG_SM_VIDEOCC_7150) += videocc-sm7150.o
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o
diff --git a/drivers/clk/qcom/videocc-sm7150.c b/drivers/clk/qcom/videocc-sm7150.c
new file mode 100644
index 000000000000..64f6b03996fc
--- /dev/null
+++ b/drivers/clk/qcom/videocc-sm7150.c
@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,sm7150-videocc.h>
+
+#include "common.h"
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "gdsc.h"
+
+enum {
+ DT_BI_TCXO,
+ DT_BI_TCXO_AO,
+};
+
+enum {
+ P_BI_TCXO,
+ P_VIDEOCC_PLL0_OUT_EVEN,
+ P_VIDEOCC_PLL0_OUT_MAIN,
+ P_VIDEOCC_PLL0_OUT_ODD,
+};
+
+static const struct pll_vco fabia_vco[] = {
+ { 249600000, 2000000000, 0 },
+ { 125000000, 1000000000, 1 },
+};
+
+static struct alpha_pll_config videocc_pll0_config = {
+ .l = 0x19,
+ .alpha = 0x0,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00002067,
+ .user_ctl_val = 0x00000001,
+ .user_ctl_hi_val = 0x00004805,
+ .test_ctl_hi_val = 0x40000000,
+};
+
+static struct clk_alpha_pll videocc_pll0 = {
+ .offset = 0x42c,
+ .vco_table = fabia_vco,
+ .num_vco = ARRAY_SIZE(fabia_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "videocc_pll0",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fabia_ops,
+ },
+ },
+};
+
+static const struct parent_map videocc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_VIDEOCC_PLL0_OUT_MAIN, 1 },
+ { P_VIDEOCC_PLL0_OUT_EVEN, 2 },
+ { P_VIDEOCC_PLL0_OUT_ODD, 3 },
+};
+
+static const struct clk_parent_data videocc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &videocc_pll0.clkr.hw },
+ { .hw = &videocc_pll0.clkr.hw },
+ { .hw = &videocc_pll0.clkr.hw },
+};
+
+static const struct parent_map videocc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+};
+
+static const struct clk_parent_data videocc_parent_data_1[] = {
+ { .index = DT_BI_TCXO_AO },
+};
+
+static const struct freq_tbl ftbl_videocc_iris_clk_src[] = {
+ F(240000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0),
+ F(338000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0),
+ F(365000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0),
+ F(444000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0),
+ F(533000000, P_VIDEOCC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 videocc_iris_clk_src = {
+ .cmd_rcgr = 0x7f0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = videocc_parent_map_0,
+ .freq_tbl = ftbl_videocc_iris_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "videocc_iris_clk_src",
+ .parent_data = videocc_parent_data_0,
+ .num_parents = ARRAY_SIZE(videocc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_videocc_xo_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 videocc_xo_clk_src = {
+ .cmd_rcgr = 0xa98,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = videocc_parent_map_1,
+ .freq_tbl = ftbl_videocc_xo_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "videocc_xo_clk_src",
+ .parent_data = videocc_parent_data_1,
+ .num_parents = ARRAY_SIZE(videocc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch videocc_iris_ahb_clk = {
+ .halt_reg = 0x8f4,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x8f4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "videocc_iris_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &videocc_iris_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch videocc_mvs0_axi_clk = {
+ .halt_reg = 0x9ec,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9ec,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "videocc_mvs0_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch videocc_mvs0_core_clk = {
+ .halt_reg = 0x890,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x890,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "videocc_mvs0_core_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &videocc_iris_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch videocc_mvs1_axi_clk = {
+ .halt_reg = 0xa0c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa0c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "videocc_mvs1_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch videocc_mvs1_core_clk = {
+ .halt_reg = 0x8d0,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x8d0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "videocc_mvs1_core_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &videocc_iris_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch videocc_mvsc_core_clk = {
+ .halt_reg = 0x850,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x850,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "videocc_mvsc_core_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &videocc_iris_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch videocc_mvsc_ctl_axi_clk = {
+ .halt_reg = 0x9cc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9cc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "videocc_mvsc_ctl_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch videocc_venus_ahb_clk = {
+ .halt_reg = 0xa6c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa6c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "videocc_venus_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc venus_gdsc = {
+ .gdscr = 0x814,
+ .pd = {
+ .name = "venus_gdsc",
+ },
+ .cxcs = (unsigned int []){ 0x850, 0x9cc },
+ .cxc_count = 2,
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc vcodec0_gdsc = {
+ .gdscr = 0x874,
+ .pd = {
+ .name = "vcodec0_gdsc",
+ },
+ .cxcs = (unsigned int []){ 0x890, 0x9ec },
+ .cxc_count = 2,
+ .flags = HW_CTRL | POLL_CFG_GDSCR,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc vcodec1_gdsc = {
+ .gdscr = 0x8b4,
+ .pd = {
+ .name = "vcodec1_gdsc",
+ },
+ .cxcs = (unsigned int []){ 0x8d0, 0xa0c },
+ .cxc_count = 2,
+ .flags = HW_CTRL | POLL_CFG_GDSCR,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct clk_regmap *videocc_sm7150_clocks[] = {
+ [VIDEOCC_PLL0] = &videocc_pll0.clkr,
+ [VIDEOCC_IRIS_AHB_CLK] = &videocc_iris_ahb_clk.clkr,
+ [VIDEOCC_IRIS_CLK_SRC] = &videocc_iris_clk_src.clkr,
+ [VIDEOCC_MVS0_AXI_CLK] = &videocc_mvs0_axi_clk.clkr,
+ [VIDEOCC_MVS0_CORE_CLK] = &videocc_mvs0_core_clk.clkr,
+ [VIDEOCC_MVS1_AXI_CLK] = &videocc_mvs1_axi_clk.clkr,
+ [VIDEOCC_MVS1_CORE_CLK] = &videocc_mvs1_core_clk.clkr,
+ [VIDEOCC_MVSC_CORE_CLK] = &videocc_mvsc_core_clk.clkr,
+ [VIDEOCC_MVSC_CTL_AXI_CLK] = &videocc_mvsc_ctl_axi_clk.clkr,
+ [VIDEOCC_VENUS_AHB_CLK] = &videocc_venus_ahb_clk.clkr,
+ [VIDEOCC_XO_CLK_SRC] = &videocc_xo_clk_src.clkr,
+};
+
+static struct gdsc *videocc_sm7150_gdscs[] = {
+ [VENUS_GDSC] = &venus_gdsc,
+ [VCODEC0_GDSC] = &vcodec0_gdsc,
+ [VCODEC1_GDSC] = &vcodec1_gdsc,
+};
+
+static const struct regmap_config videocc_sm7150_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xb94,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc videocc_sm7150_desc = {
+ .config = &videocc_sm7150_regmap_config,
+ .clks = videocc_sm7150_clocks,
+ .num_clks = ARRAY_SIZE(videocc_sm7150_clocks),
+ .gdscs = videocc_sm7150_gdscs,
+ .num_gdscs = ARRAY_SIZE(videocc_sm7150_gdscs),
+};
+
+static const struct of_device_id videocc_sm7150_match_table[] = {
+ { .compatible = "qcom,sm7150-videocc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, videocc_sm7150_match_table);
+
+static int videocc_sm7150_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &videocc_sm7150_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_fabia_pll_configure(&videocc_pll0, regmap, &videocc_pll0_config);
+
+ /* Keep some clocks always-on */
+ qcom_branch_set_clk_en(regmap, 0x984); /* VIDEOCC_XO_CLK */
+
+ return qcom_cc_really_probe(pdev, &videocc_sm7150_desc, regmap);
+}
+
+static struct platform_driver videocc_sm7150_driver = {
+ .probe = videocc_sm7150_probe,
+ .driver = {
+ .name = "videocc-sm7150",
+ .of_match_table = videocc_sm7150_match_table,
+ },
+};
+module_platform_driver(videocc_sm7150_driver);
+
+MODULE_DESCRIPTION("Qualcomm SM7150 Video Clock Controller");
+MODULE_LICENSE("GPL");
--
2.44.0
^ permalink raw reply related [relevance 9%]
* [PATCH v3 6/8] clk: qcom: Add Camera Clock Controller driver for SM7150
2024-05-05 20:10 2% ` [PATCH v3 4/8] clk: qcom: Add Display Clock Controller driver " Danila Tikhonov
@ 2024-05-05 20:10 1% ` Danila Tikhonov
2024-05-05 20:10 9% ` [PATCH v3 8/8] clk: qcom: Add Video " Danila Tikhonov
2 siblings, 0 replies; 200+ results
From: Danila Tikhonov @ 2024-05-05 20:10 UTC (permalink / raw)
To: andersson, konrad.dybcio, mturquette, sboyd, robh, krzk+dt,
conor+dt, david, adrian
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, Danila Tikhonov
Add support for the camera clock controller found on SM7150.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/camcc-sm7150.c | 2061 +++++++++++++++++++++++++++++++
3 files changed, 2070 insertions(+)
create mode 100644 drivers/clk/qcom/camcc-sm7150.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 7b4c2ff580a3..14e19f4c804c 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -803,6 +803,14 @@ config SM_CAMCC_6350
Support for the camera clock controller on SM6350 devices.
Say Y if you want to support camera devices and camera functionality.
+config SM_CAMCC_7150
+ tristate "SM7150 Camera Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ select SM_GCC_7150
+ help
+ Support for the camera clock controller on SM7150 devices.
+ Say Y if you want to support camera devices and camera functionality.
+
config SM_CAMCC_8250
tristate "SM8250 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index cdec5ce2bb94..9c83abef9cac 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -106,6 +106,7 @@ obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
+obj-$(CONFIG_SM_CAMCC_7150) += camcc-sm7150.o
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
diff --git a/drivers/clk/qcom/camcc-sm7150.c b/drivers/clk/qcom/camcc-sm7150.c
new file mode 100644
index 000000000000..a81ce6ab8cd5
--- /dev/null
+++ b/drivers/clk/qcom/camcc-sm7150.c
@@ -0,0 +1,2061 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,sm7150-camcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "common.h"
+#include "gdsc.h"
+
+enum {
+ DT_BI_TCXO,
+ DT_BI_TCXO_AO,
+ DT_CHIP_SLEEP_CLK,
+};
+
+enum {
+ P_BI_TCXO,
+ P_BI_TCXO_MX,
+ P_CAMCC_PLL0_OUT_EVEN,
+ P_CAMCC_PLL0_OUT_MAIN,
+ P_CAMCC_PLL0_OUT_ODD,
+ P_CAMCC_PLL1_OUT_EVEN,
+ P_CAMCC_PLL2_OUT_AUX,
+ P_CAMCC_PLL2_OUT_EARLY,
+ P_CAMCC_PLL2_OUT_MAIN,
+ P_CAMCC_PLL3_OUT_EVEN,
+ P_CAMCC_PLL4_OUT_EVEN,
+ P_CHIP_SLEEP_CLK,
+};
+
+static const struct pll_vco fabia_vco[] = {
+ { 249600000, 2000000000, 0 },
+};
+
+/* 1200MHz configuration */
+static const struct alpha_pll_config camcc_pll0_config = {
+ .l = 0x3e,
+ .alpha = 0x8000,
+ .post_div_mask = 0xff << 8,
+ .post_div_val = 0x31 << 8,
+ .test_ctl_val = 0x40000000,
+};
+
+static struct clk_alpha_pll camcc_pll0 = {
+ .offset = 0x0,
+ .vco_table = fabia_vco,
+ .num_vco = ARRAY_SIZE(fabia_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll0",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fabia_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor camcc_pll0_out_even = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll0_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_pll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_fixed_factor camcc_pll0_out_odd = {
+ .mult = 1,
+ .div = 3,
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll0_out_odd",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_pll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+/* 680MHz configuration */
+static const struct alpha_pll_config camcc_pll1_config = {
+ .l = 0x23,
+ .alpha = 0x6aaa,
+ .post_div_mask = 0xf << 8,
+ .post_div_val = 0x1 << 8,
+ .test_ctl_val = 0x40000000,
+};
+
+static struct clk_alpha_pll camcc_pll1 = {
+ .offset = 0x1000,
+ .vco_table = fabia_vco,
+ .num_vco = ARRAY_SIZE(fabia_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll1",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fabia_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor camcc_pll1_out_even = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll1_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_pll1.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+/* 1920MHz configuration */
+static const struct alpha_pll_config camcc_pll2_config = {
+ .l = 0x64,
+ .post_div_val = 0x3 << 8,
+ .post_div_mask = 0x3 << 8,
+ .early_output_mask = BIT(3),
+ .aux_output_mask = BIT(1),
+ .main_output_mask = BIT(0),
+ .config_ctl_hi_val = 0x400003d6,
+ .config_ctl_val = 0x20000954,
+};
+
+static struct clk_alpha_pll camcc_pll2 = {
+ .offset = 0x2000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll2",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_agera_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor camcc_pll2_out_early = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll2_out_early",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_pll2.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv camcc_pll2_out_aux = {
+ .offset = 0x2000,
+ .post_div_shift = 8,
+ .width = 2,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll2_out_aux",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_pll2.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv camcc_pll2_out_main = {
+ .offset = 0x2000,
+ .post_div_shift = 8,
+ .width = 2,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll2_out_main",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_pll2.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+/* 760MHz configuration */
+static const struct alpha_pll_config camcc_pll3_config = {
+ .l = 0x27,
+ .alpha = 0x9555,
+ .post_div_mask = 0xf << 8,
+ .post_div_val = 0x1 << 8,
+ .test_ctl_val = 0x40000000,
+};
+
+static struct clk_alpha_pll camcc_pll3 = {
+ .offset = 0x3000,
+ .vco_table = fabia_vco,
+ .num_vco = ARRAY_SIZE(fabia_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll3",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fabia_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor camcc_pll3_out_even = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll3_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_pll3.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll camcc_pll4 = {
+ .offset = 0x4000,
+ .vco_table = fabia_vco,
+ .num_vco = ARRAY_SIZE(fabia_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll4",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fabia_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor camcc_pll4_out_even = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_pll4_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_pll4.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static const struct parent_map camcc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAMCC_PLL0_OUT_MAIN, 1 },
+ { P_CAMCC_PLL0_OUT_EVEN, 2 },
+ { P_CAMCC_PLL0_OUT_ODD, 3 },
+ { P_CAMCC_PLL2_OUT_MAIN, 5 },
+};
+
+static const struct clk_parent_data camcc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &camcc_pll0.clkr.hw },
+ { .hw = &camcc_pll0_out_even.hw },
+ { .hw = &camcc_pll0_out_odd.hw },
+ { .hw = &camcc_pll2_out_main.clkr.hw },
+};
+
+static const struct parent_map camcc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAMCC_PLL0_OUT_MAIN, 1 },
+ { P_CAMCC_PLL0_OUT_EVEN, 2 },
+ { P_CAMCC_PLL0_OUT_ODD, 3 },
+ { P_CAMCC_PLL1_OUT_EVEN, 4 },
+ { P_CAMCC_PLL2_OUT_EARLY, 5 },
+};
+
+static const struct clk_parent_data camcc_parent_data_1[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &camcc_pll0.clkr.hw },
+ { .hw = &camcc_pll0_out_even.hw },
+ { .hw = &camcc_pll0_out_odd.hw },
+ { .hw = &camcc_pll1_out_even.hw },
+ { .hw = &camcc_pll2_out_early.hw },
+};
+
+static const struct parent_map camcc_parent_map_2[] = {
+ { P_BI_TCXO_MX, 0 },
+ { P_CAMCC_PLL2_OUT_AUX, 5 },
+};
+
+static const struct clk_parent_data camcc_parent_data_2[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &camcc_pll2_out_aux.clkr.hw },
+};
+
+static const struct parent_map camcc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAMCC_PLL0_OUT_MAIN, 1 },
+ { P_CAMCC_PLL0_OUT_EVEN, 2 },
+ { P_CAMCC_PLL0_OUT_ODD, 3 },
+ { P_CAMCC_PLL2_OUT_EARLY, 5 },
+ { P_CAMCC_PLL4_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data camcc_parent_data_3[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &camcc_pll0.clkr.hw },
+ { .hw = &camcc_pll0_out_even.hw },
+ { .hw = &camcc_pll0_out_odd.hw },
+ { .hw = &camcc_pll2_out_early.hw },
+ { .hw = &camcc_pll4_out_even.hw },
+};
+
+static const struct parent_map camcc_parent_map_4[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAMCC_PLL3_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data camcc_parent_data_4[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &camcc_pll3_out_even.hw },
+};
+
+static const struct parent_map camcc_parent_map_5[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAMCC_PLL4_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data camcc_parent_data_5[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &camcc_pll4_out_even.hw },
+};
+
+static const struct parent_map camcc_parent_map_6[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAMCC_PLL1_OUT_EVEN, 4 },
+};
+
+static const struct clk_parent_data camcc_parent_data_6[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &camcc_pll1_out_even.hw },
+};
+
+static const struct parent_map camcc_parent_map_7[] = {
+ { P_CHIP_SLEEP_CLK, 0 },
+};
+
+static const struct clk_parent_data camcc_parent_data_7[] = {
+ { .index = DT_CHIP_SLEEP_CLK },
+};
+
+static const struct parent_map camcc_parent_map_8[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAMCC_PLL0_OUT_ODD, 3 },
+};
+
+static const struct clk_parent_data camcc_parent_data_8[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &camcc_pll0_out_odd.hw },
+};
+
+static const struct parent_map camcc_parent_map_9[] = {
+ { P_BI_TCXO, 0 },
+};
+
+static const struct clk_parent_data camcc_parent_data_9[] = {
+ { .index = DT_BI_TCXO_AO },
+};
+
+static const struct freq_tbl ftbl_camcc_bps_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
+ F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),
+ F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
+ F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
+ F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_bps_clk_src = {
+ .cmd_rcgr = 0x7010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_bps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_bps_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_camnoc_axi_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0),
+ F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
+ F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
+ F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
+ F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_camnoc_axi_clk_src = {
+ .cmd_rcgr = 0xc12c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_camnoc_axi_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_camnoc_axi_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_cci_0_clk_src = {
+ .cmd_rcgr = 0xc0c4,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_cci_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_cci_0_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 camcc_cci_1_clk_src = {
+ .cmd_rcgr = 0xc0e0,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_cci_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_cci_1_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
+ F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
+ F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_cphy_rx_clk_src = {
+ .cmd_rcgr = 0xa064,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_1,
+ .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_cphy_rx_clk_src",
+ .parent_data = camcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_csi0phytimer_clk_src = {
+ .cmd_rcgr = 0x6004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_csi0phytimer_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 camcc_csi1phytimer_clk_src = {
+ .cmd_rcgr = 0x6028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_csi1phytimer_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 camcc_csi2phytimer_clk_src = {
+ .cmd_rcgr = 0x604c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_csi2phytimer_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 camcc_csi3phytimer_clk_src = {
+ .cmd_rcgr = 0x6070,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_csi3phytimer_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(50000000, P_CAMCC_PLL0_OUT_EVEN, 12, 0, 0),
+ F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
+ F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
+ F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
+ F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_fast_ahb_clk_src = {
+ .cmd_rcgr = 0x703c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_fast_ahb_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_fast_ahb_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_fd_core_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
+ F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
+ F(480000000, P_CAMCC_PLL2_OUT_EARLY, 2, 0, 0),
+ F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_fd_core_clk_src = {
+ .cmd_rcgr = 0xc09c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_3,
+ .freq_tbl = ftbl_camcc_fd_core_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_fd_core_clk_src",
+ .parent_data = camcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_icp_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
+ F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_icp_clk_src = {
+ .cmd_rcgr = 0xc074,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_icp_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_icp_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(380000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
+ F(510000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
+ F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
+ F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_ife_0_clk_src = {
+ .cmd_rcgr = 0xa010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_4,
+ .freq_tbl = ftbl_camcc_ife_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_0_clk_src",
+ .parent_data = camcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_4),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_ife_0_csid_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
+ F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
+ F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
+ F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_ife_0_csid_clk_src = {
+ .cmd_rcgr = 0xa03c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_1,
+ .freq_tbl = ftbl_camcc_ife_0_csid_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_0_csid_clk_src",
+ .parent_data = camcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_1),
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_ife_1_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(510000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_ife_1_clk_src = {
+ .cmd_rcgr = 0xb010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_5,
+ .freq_tbl = ftbl_camcc_ife_1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_1_clk_src",
+ .parent_data = camcc_parent_data_5,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_5),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 camcc_ife_1_csid_clk_src = {
+ .cmd_rcgr = 0xb034,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_1,
+ .freq_tbl = ftbl_camcc_ife_0_csid_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_1_csid_clk_src",
+ .parent_data = camcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_1),
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_ife_lite_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
+ F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
+ F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
+ F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_ife_lite_clk_src = {
+ .cmd_rcgr = 0xc004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_ife_lite_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_lite_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 camcc_ife_lite_csid_clk_src = {
+ .cmd_rcgr = 0xc020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_1,
+ .freq_tbl = ftbl_camcc_cphy_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_lite_csid_clk_src",
+ .parent_data = camcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_1),
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(340000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
+ F(430000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
+ F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
+ F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_ipe_0_clk_src = {
+ .cmd_rcgr = 0x8010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_6,
+ .freq_tbl = ftbl_camcc_ipe_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ipe_0_clk_src",
+ .parent_data = camcc_parent_data_6,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_6),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 camcc_jpeg_clk_src = {
+ .cmd_rcgr = 0xc048,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_bps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_jpeg_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
+ F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
+ F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
+ F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
+ F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_lrme_clk_src = {
+ .cmd_rcgr = 0xc100,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_0,
+ .freq_tbl = ftbl_camcc_lrme_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_lrme_clk_src",
+ .parent_data = camcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_0),
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = {
+ F(19200000, P_BI_TCXO_MX, 1, 0, 0),
+ F(24000000, P_CAMCC_PLL2_OUT_AUX, 1, 1, 20),
+ F(34285714, P_CAMCC_PLL2_OUT_AUX, 14, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_mclk0_clk_src = {
+ .cmd_rcgr = 0x5004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_2,
+ .freq_tbl = ftbl_camcc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_mclk0_clk_src",
+ .parent_data = camcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 camcc_mclk1_clk_src = {
+ .cmd_rcgr = 0x5024,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_2,
+ .freq_tbl = ftbl_camcc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_mclk1_clk_src",
+ .parent_data = camcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 camcc_mclk2_clk_src = {
+ .cmd_rcgr = 0x5044,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_2,
+ .freq_tbl = ftbl_camcc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_mclk2_clk_src",
+ .parent_data = camcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 camcc_mclk3_clk_src = {
+ .cmd_rcgr = 0x5064,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_2,
+ .freq_tbl = ftbl_camcc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_mclk3_clk_src",
+ .parent_data = camcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_sleep_clk_src[] = {
+ F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_sleep_clk_src = {
+ .cmd_rcgr = 0xc1a4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_7,
+ .freq_tbl = ftbl_camcc_sleep_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_sleep_clk_src",
+ .parent_data = camcc_parent_data_7,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_7),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(80000000, P_CAMCC_PLL0_OUT_ODD, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_slow_ahb_clk_src = {
+ .cmd_rcgr = 0x7058,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_8,
+ .freq_tbl = ftbl_camcc_slow_ahb_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_slow_ahb_clk_src",
+ .parent_data = camcc_parent_data_8,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_8),
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_camcc_xo_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 camcc_xo_clk_src = {
+ .cmd_rcgr = 0xc188,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = camcc_parent_map_9,
+ .freq_tbl = ftbl_camcc_xo_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "camcc_xo_clk_src",
+ .parent_data = camcc_parent_data_9,
+ .num_parents = ARRAY_SIZE(camcc_parent_data_9),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch camcc_bps_ahb_clk = {
+ .halt_reg = 0x7070,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7070,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_bps_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_bps_areg_clk = {
+ .halt_reg = 0x7054,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7054,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_bps_areg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_bps_axi_clk = {
+ .halt_reg = 0x7038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_bps_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_camnoc_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_bps_clk = {
+ .halt_reg = 0x7028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_bps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_bps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_camnoc_axi_clk = {
+ .halt_reg = 0xc148,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc148,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_camnoc_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_camnoc_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_camnoc_dcd_xo_clk = {
+ .halt_reg = 0xc150,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc150,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_camnoc_dcd_xo_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_cci_0_clk = {
+ .halt_reg = 0xc0dc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc0dc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_cci_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_cci_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_cci_1_clk = {
+ .halt_reg = 0xc0f8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc0f8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_cci_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_cci_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_core_ahb_clk = {
+ .halt_reg = 0xc184,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xc184,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_core_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_cpas_ahb_clk = {
+ .halt_reg = 0xc124,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc124,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_cpas_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_csi0phytimer_clk = {
+ .halt_reg = 0x601c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x601c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_csi0phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_csi0phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_csi1phytimer_clk = {
+ .halt_reg = 0x6040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_csi1phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_csi1phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_csi2phytimer_clk = {
+ .halt_reg = 0x6064,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6064,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_csi2phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_csi2phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_csi3phytimer_clk = {
+ .halt_reg = 0x6088,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6088,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_csi3phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_csi3phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_csiphy0_clk = {
+ .halt_reg = 0x6020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_csiphy0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_csiphy1_clk = {
+ .halt_reg = 0x6044,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_csiphy1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_csiphy2_clk = {
+ .halt_reg = 0x6068,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_csiphy2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_csiphy3_clk = {
+ .halt_reg = 0x608c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x608c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_csiphy3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_fd_core_clk = {
+ .halt_reg = 0xc0b4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc0b4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_fd_core_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_fd_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_fd_core_uar_clk = {
+ .halt_reg = 0xc0bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc0bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_fd_core_uar_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_fd_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_icp_ahb_clk = {
+ .halt_reg = 0xc094,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc094,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_icp_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_icp_clk = {
+ .halt_reg = 0xc08c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc08c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_icp_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_icp_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_0_axi_clk = {
+ .halt_reg = 0xa080,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa080,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_0_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_camnoc_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_0_clk = {
+ .halt_reg = 0xa028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_ife_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_0_cphy_rx_clk = {
+ .halt_reg = 0xa07c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa07c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_0_cphy_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_0_csid_clk = {
+ .halt_reg = 0xa054,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa054,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_0_csid_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_ife_0_csid_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_0_dsp_clk = {
+ .halt_reg = 0xa038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_0_dsp_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_ife_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_1_axi_clk = {
+ .halt_reg = 0xb058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb058,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_1_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_camnoc_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_1_clk = {
+ .halt_reg = 0xb028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_ife_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_1_cphy_rx_clk = {
+ .halt_reg = 0xb054,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb054,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_1_cphy_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_1_csid_clk = {
+ .halt_reg = 0xb04c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb04c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_1_csid_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_ife_1_csid_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_1_dsp_clk = {
+ .halt_reg = 0xb030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_1_dsp_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_ife_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_lite_clk = {
+ .halt_reg = 0xc01c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc01c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_lite_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_ife_lite_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_lite_cphy_rx_clk = {
+ .halt_reg = 0xc040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_lite_cphy_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ife_lite_csid_clk = {
+ .halt_reg = 0xc038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ife_lite_csid_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_ife_lite_csid_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ipe_0_ahb_clk = {
+ .halt_reg = 0x8040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ipe_0_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ipe_0_areg_clk = {
+ .halt_reg = 0x803c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x803c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ipe_0_areg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ipe_0_axi_clk = {
+ .halt_reg = 0x8038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ipe_0_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_camnoc_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ipe_0_clk = {
+ .halt_reg = 0x8028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ipe_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_ipe_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ipe_1_ahb_clk = {
+ .halt_reg = 0x9028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ipe_1_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ipe_1_areg_clk = {
+ .halt_reg = 0x9024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ipe_1_areg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ipe_1_axi_clk = {
+ .halt_reg = 0x9020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ipe_1_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_camnoc_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_ipe_1_clk = {
+ .halt_reg = 0x9010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_ipe_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_ipe_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_jpeg_clk = {
+ .halt_reg = 0xc060,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc060,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_jpeg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_jpeg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_lrme_clk = {
+ .halt_reg = 0xc118,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc118,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_lrme_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_lrme_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_mclk0_clk = {
+ .halt_reg = 0x501c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x501c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_mclk0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_mclk0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_mclk1_clk = {
+ .halt_reg = 0x503c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x503c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_mclk1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_mclk1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_mclk2_clk = {
+ .halt_reg = 0x505c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x505c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_mclk2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_mclk2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_mclk3_clk = {
+ .halt_reg = 0x507c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x507c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_mclk3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_mclk3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch camcc_sleep_clk = {
+ .halt_reg = 0xc1bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc1bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "camcc_sleep_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &camcc_sleep_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc camcc_titan_top_gdsc;
+
+static struct gdsc camcc_bps_gdsc = {
+ .gdscr = 0x7004,
+ .pd = {
+ .name = "camcc_bps_gdsc",
+ },
+ .flags = HW_CTRL | POLL_CFG_GDSCR,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camcc_ife_0_gdsc = {
+ .gdscr = 0xa004,
+ .pd = {
+ .name = "camcc_ife_0_gdsc",
+ },
+ .flags = POLL_CFG_GDSCR,
+ .parent = &camcc_titan_top_gdsc.pd,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camcc_ife_1_gdsc = {
+ .gdscr = 0xb004,
+ .pd = {
+ .name = "camcc_ife_1_gdsc",
+ },
+ .flags = POLL_CFG_GDSCR,
+ .parent = &camcc_titan_top_gdsc.pd,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camcc_ipe_0_gdsc = {
+ .gdscr = 0x8004,
+ .pd = {
+ .name = "camcc_ipe_0_gdsc",
+ },
+ .flags = HW_CTRL | POLL_CFG_GDSCR,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camcc_ipe_1_gdsc = {
+ .gdscr = 0x9004,
+ .pd = {
+ .name = "camcc_ipe_1_gdsc",
+ },
+ .flags = HW_CTRL | POLL_CFG_GDSCR,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc camcc_titan_top_gdsc = {
+ .gdscr = 0xc1c4,
+ .pd = {
+ .name = "camcc_titan_top_gdsc",
+ },
+ .flags = POLL_CFG_GDSCR,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+struct clk_hw *camcc_sm7150_hws[] = {
+ [CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.hw,
+ [CAMCC_PLL0_OUT_ODD] = &camcc_pll0_out_odd.hw,
+ [CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.hw,
+ [CAMCC_PLL2_OUT_EARLY] = &camcc_pll2_out_early.hw,
+ [CAMCC_PLL3_OUT_EVEN] = &camcc_pll3_out_even.hw,
+ [CAMCC_PLL4_OUT_EVEN] = &camcc_pll4_out_even.hw,
+};
+
+static struct clk_regmap *camcc_sm7150_clocks[] = {
+ [CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr,
+ [CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr,
+ [CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr,
+ [CAMCC_BPS_CLK] = &camcc_bps_clk.clkr,
+ [CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr,
+ [CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr,
+ [CAMCC_CAMNOC_AXI_CLK_SRC] = &camcc_camnoc_axi_clk_src.clkr,
+ [CAMCC_CAMNOC_DCD_XO_CLK] = &camcc_camnoc_dcd_xo_clk.clkr,
+ [CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr,
+ [CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr,
+ [CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr,
+ [CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr,
+ [CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr,
+ [CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr,
+ [CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr,
+ [CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr,
+ [CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr,
+ [CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr,
+ [CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr,
+ [CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr,
+ [CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr,
+ [CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr,
+ [CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr,
+ [CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr,
+ [CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr,
+ [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr,
+ [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr,
+ [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr,
+ [CAMCC_FD_CORE_CLK] = &camcc_fd_core_clk.clkr,
+ [CAMCC_FD_CORE_CLK_SRC] = &camcc_fd_core_clk_src.clkr,
+ [CAMCC_FD_CORE_UAR_CLK] = &camcc_fd_core_uar_clk.clkr,
+ [CAMCC_ICP_AHB_CLK] = &camcc_icp_ahb_clk.clkr,
+ [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr,
+ [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr,
+ [CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr,
+ [CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr,
+ [CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr,
+ [CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr,
+ [CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr,
+ [CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr,
+ [CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr,
+ [CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr,
+ [CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr,
+ [CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr,
+ [CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr,
+ [CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr,
+ [CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr,
+ [CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr,
+ [CAMCC_IFE_LITE_CLK] = &camcc_ife_lite_clk.clkr,
+ [CAMCC_IFE_LITE_CLK_SRC] = &camcc_ife_lite_clk_src.clkr,
+ [CAMCC_IFE_LITE_CPHY_RX_CLK] = &camcc_ife_lite_cphy_rx_clk.clkr,
+ [CAMCC_IFE_LITE_CSID_CLK] = &camcc_ife_lite_csid_clk.clkr,
+ [CAMCC_IFE_LITE_CSID_CLK_SRC] = &camcc_ife_lite_csid_clk_src.clkr,
+ [CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr,
+ [CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr,
+ [CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr,
+ [CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr,
+ [CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr,
+ [CAMCC_IPE_1_AHB_CLK] = &camcc_ipe_1_ahb_clk.clkr,
+ [CAMCC_IPE_1_AREG_CLK] = &camcc_ipe_1_areg_clk.clkr,
+ [CAMCC_IPE_1_AXI_CLK] = &camcc_ipe_1_axi_clk.clkr,
+ [CAMCC_IPE_1_CLK] = &camcc_ipe_1_clk.clkr,
+ [CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr,
+ [CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr,
+ [CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr,
+ [CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr,
+ [CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr,
+ [CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr,
+ [CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr,
+ [CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr,
+ [CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr,
+ [CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr,
+ [CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr,
+ [CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr,
+ [CAMCC_PLL0] = &camcc_pll0.clkr,
+ [CAMCC_PLL1] = &camcc_pll1.clkr,
+ [CAMCC_PLL2] = &camcc_pll2.clkr,
+ [CAMCC_PLL2_OUT_AUX] = &camcc_pll2_out_aux.clkr,
+ [CAMCC_PLL2_OUT_MAIN] = &camcc_pll2_out_main.clkr,
+ [CAMCC_PLL3] = &camcc_pll3.clkr,
+ [CAMCC_PLL4] = &camcc_pll4.clkr,
+ [CAMCC_SLEEP_CLK] = &camcc_sleep_clk.clkr,
+ [CAMCC_SLEEP_CLK_SRC] = &camcc_sleep_clk_src.clkr,
+ [CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr,
+ [CAMCC_XO_CLK_SRC] = &camcc_xo_clk_src.clkr,
+};
+
+static struct gdsc *camcc_sm7150_gdscs[] = {
+ [BPS_GDSC] = &camcc_bps_gdsc,
+ [IFE_0_GDSC] = &camcc_ife_0_gdsc,
+ [IFE_1_GDSC] = &camcc_ife_1_gdsc,
+ [IPE_0_GDSC] = &camcc_ipe_0_gdsc,
+ [IPE_1_GDSC] = &camcc_ipe_1_gdsc,
+ [TITAN_TOP_GDSC] = &camcc_titan_top_gdsc,
+};
+
+static const struct regmap_config camcc_sm7150_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xd024,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc camcc_sm7150_desc = {
+ .config = &camcc_sm7150_regmap_config,
+ .clk_hws = camcc_sm7150_hws,
+ .num_clk_hws = ARRAY_SIZE(camcc_sm7150_hws),
+ .clks = camcc_sm7150_clocks,
+ .num_clks = ARRAY_SIZE(camcc_sm7150_clocks),
+ .gdscs = camcc_sm7150_gdscs,
+ .num_gdscs = ARRAY_SIZE(camcc_sm7150_gdscs),
+};
+
+static const struct of_device_id camcc_sm7150_match_table[] = {
+ { .compatible = "qcom,sm7150-camcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, camcc_sm7150_match_table);
+
+static int camcc_sm7150_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &camcc_sm7150_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_fabia_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config);
+ clk_fabia_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config);
+ clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config);
+ clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config);
+ clk_fabia_pll_configure(&camcc_pll4, regmap, &camcc_pll3_config);
+
+ /* Keep some clocks always-on */
+ qcom_branch_set_clk_en(regmap, 0xc1a0); /* CAMCC_GDSC_CLK */
+
+ return qcom_cc_really_probe(pdev, &camcc_sm7150_desc, regmap);
+}
+
+static struct platform_driver camcc_sm7150_driver = {
+ .probe = camcc_sm7150_probe,
+ .driver = {
+ .name = "camcc-sm7150",
+ .of_match_table = camcc_sm7150_match_table,
+ },
+};
+
+module_platform_driver(camcc_sm7150_driver);
+
+MODULE_DESCRIPTION("Qualcomm SM7150 Camera Clock Controller");
+MODULE_LICENSE("GPL");
--
2.44.0
^ permalink raw reply related [relevance 1%]
* [PATCH 01/12] linux-yocto/6.6: update to v6.6.24
@ 2024-05-03 2:40 2% ` bruce.ashfield
0 siblings, 0 replies; 200+ results
From: bruce.ashfield @ 2024-05-03 2:40 UTC (permalink / raw)
To: richard.purdie; +Cc: openembedded-core
From: Bruce Ashfield <bruce.ashfield@gmail.com>
Updating linux-yocto/6.6 to the latest korg -stable release that comprises
the following commits:
9467d7a12f97 Linux 6.6.24
e87e08c94c95 drm/amdgpu: fix use-after-free bug
3a9569441b47 tools/resolve_btfids: fix build with musl libc
4338e40da808 x86/sev: Skip ROM range scans and validation for SEV-SNP guests
2048ff503f43 scsi: libsas: Fix disk not being scanned in after being removed
f23db7579283 scsi: libsas: Add a helper sas_get_sas_addr_and_dev_type()
76edb986c44b scsi: lpfc: Correct size for wqe for memset()
ac5b18f52858 scsi: lpfc: Correct size for cmdwqe/rspwqe for memset()
ff3cdff7c897 usb: dwc3: pci: Drop duplicate ID
70977e7d5e5f Revert "x86/bugs: Use fixed addressing for VERW operand"
367b4ce0d74d x86/bugs: Use fixed addressing for VERW operand
a492d6dad9af scsi: qla2xxx: Delay I/O Abort on PCI error
29520a334f3e scsi: qla2xxx: Change debug message during driver unload
f85af9f1aa5e scsi: qla2xxx: Fix double free of fcport
f14cee7a882c scsi: qla2xxx: Fix double free of the ha->vp_map pointer
8de1584ec4fe scsi: qla2xxx: Fix command flush on cable pull
adc9702642a0 scsi: qla2xxx: NVME|FCP prefer flag not being honored
b31a120b81ac scsi: qla2xxx: Update manufacturer detail
be895682c507 scsi: qla2xxx: Split FCE|EFT trace control
8ec0d55020f6 scsi: qla2xxx: Fix N2N stuck connection
ef23850940d9 scsi: qla2xxx: Prevent command send on chip reset
db4aaf281a5b usb: typec: ucsi: Clear UCSI_CCI_RESET_COMPLETE before reset
1f510af8dbc3 usb: typec: ucsi_acpi: Refactor and fix DELL quirk
5857494b5056 usb: typec: ucsi: Ack unsupported commands
68f57d013827 usb: typec: ucsi: Clear EVENT_PENDING under PPM lock
c708b704c26d usb: typec: Return size of buffer if pd_set operation succeeds
99731076722e usb: udc: remove warning when queue disabled ep
3e417f31b06a usb: dwc2: gadget: LPM flow fix
f047361fee44 usb: dwc2: gadget: Fix exiting from clock gating
8d310e5d702c usb: dwc2: host: Fix ISOC flow in DDMA mode
96dff759ef7d usb: dwc2: host: Fix hibernation flow
ba2951ec82e8 usb: dwc2: host: Fix remote wakeup from hibernation
f51849833705 USB: core: Fix deadlock in port "disable" sysfs attribute
8dbc001bba86 USB: core: Add hub_get() and hub_put() routines
122a06f1068b USB: core: Fix deadlock in usb_deauthorize_interface()
fd2304f4c0ae usb: dwc3: Properly set system wakeup
d12af9a1c59e staging: vc04_services: fix information leak in create_component()
98592a49956c staging: vc04_services: changen strncpy() to strscpy_pad()
d4c34782b6d7 scsi: core: Fix unremoved procfs host directory regression
a1f506af7ffe scsi: sd: Fix TCG OPAL unlock on system resume
61d4787692c1 ALSA: sh: aica: reorder cleanup operations to avoid UAF bugs
66aa5d95ea8c vfio/pds: Make sure migration file isn't accessed after reset
2ceddecdd0ef drm/amd/display: Clear OPTC mem select on disable
6a1cb68b9810 drm/amd/display: Disconnect phantom pipe OPP from OPTC being disabled
ae62f1dde66a drm/amd/display: Fix hang/underflow when transitioning to ODM4:1
ce748df0d570 USB: UAS: return ENODEV when submit urbs fail with device not attached
da3b75931bb7 usb: cdc-wdm: close race between read and workqueue
56c5145baef5 Revert "usb: phy: generic: Get the vbus supply"
9c74507e6c43 mtd: spinand: Add support for 5-byte IDs
9ae3954dd36b Bluetooth: hci_sync: Fix not checking error on hci_cmd_sync_cancel_sync
3b031e4fcb27 drm/i915/gt: Reset queue_priority_hint on parking
07c011e3351d drm/i915: Do not match JSL in ehl_combo_pll_div_frac_wa_needed()
69fa0e23a6a3 drm/i915/dsi: Go back to the previous INIT_OTP/DISPLAY_ON order, mostly
a891add409e3 drm/i915/bios: Tolerate devdata==NULL in intel_bios_encoder_supports_dp_dual_mode()
510c5f5e4837 drm/i915/hwmon: Fix locking inversion in sysfs getter
197f6d6987c5 drm/amdgpu: fix deadlock while reading mqd from debugfs
2684393685f7 drm/amdkfd: fix TLB flush after unmap for GFX9.4.2
042ef0afc40f drm/vmwgfx: Create debugfs ttm_resource_manager entry only if needed
476eed5f1c22 net: ll_temac: platform_get_resource replaced by wrong function
2a84744a037b nouveau/dmem: handle kcalloc() allocation failure
be4f3af178cb thermal: devfreq_cooling: Fix perf state when calculate dfc res_util
cc80b5d7fbef block: Do not force full zone append completion in req_bio_endio()
152799126327 sdhci-of-dwcmshc: disable PM runtime in dwcmshc_remove()
4466677dcabe mmc: core: Avoid negative index with array access
35ee8529eee7 mmc: core: Initialize mmc_blk_ioc_data
6810ebeb0975 mmc: sdhci-omap: re-tuning is needed after a pm transition to support emmc HS200 mode
07cf57eba52f selftests/mm: fix ARM related issue with fork after pthread_create
fe295de2d564 selftests/mm: sigbus-wp test requires UFFD_FEATURE_WP_HUGETLBFS_SHMEM
b79f9e1ff27c mm: cachestat: fix two shmem bugs
2e2f7a576b13 hexagon: vmlinux.lds.S: handle attributes section
c3639d87286a exec: Fix NOMMU linux_binprm::exec in transfer_args_to_stack()
78516979792d Revert "drm/amd/display: Fix sending VSC (+ colorimetry) packets for DP/eDP displays without PSR"
566e540b404f wifi: iwlwifi: fw: don't always use FW dump trig
3d7ac0250714 wifi: iwlwifi: mvm: disable MLO for the time being
6956ba7da71b wifi: cfg80211: add a flag to disable wireless extensions
6b948b54c8bd wifi: mac80211: check/clear fast rx for non-4addr sta VLAN changes
8ca8aac42bf7 btrfs: zoned: use zone aware sb location for scrub
7b5029e3f1b6 btrfs: zoned: don't skip block groups with 100% zone unusable
0427c8ef8bbb btrfs: fix race in read_extent_buffer_pages()
c7077f43f30d tmpfs: fix race on handling dquot rbtree
907efa8839cd ARM: prctl: reject PR_SET_MDWE on pre-ARMv6
a0071e3b0c24 prctl: generalize PR_SET_MDWE support check to be per-arch
5110da79d7d6 x86/efistub: Reinstate soft limit for initrd loading
90048007daea efi/libstub: Cast away type warning in use of max()
01666eece40e x86/efistub: Add missing boot_params for mixed mode compat entry
32e4750262e0 init: open /initrd.image with O_LARGEFILE
3f59182bcb4d ALSA: hda/tas2781: add locks to kcontrols
b999e77ecf3a ALSA: hda/tas2781: remove digital gain kcontrol
11b4dc6494b5 perf top: Use evsel's cpus to replace user_requested_cpus
78142322a1c3 selftests/mm: Fix build with _FORTIFY_SOURCE
ccf2d9d2ae95 selftests/mm: gup_test: conform test to TAP format output
674545b4852c pwm: img: fix pwm clock lookup
9114ba998750 efi: fix panic in kdump kernel
1acbca933313 x86/fpu: Keep xfd_state in sync with MSR_IA32_XFD
bebb5af001dc x86/mpparse: Register APIC address only once
31a6a791b046 efi/libstub: fix efi_random_alloc() to allocate memory at alloc_min or higher address
f13edd1871d4 kprobes/x86: Use copy_from_kernel_nofault() to read from unsafe address
455b94f95e49 irqchip/renesas-rzg2l: Prevent spurious interrupts when setting trigger type
e9b18e99938b irqchip/renesas-rzg2l: Rename rzg2l_irq_eoi()
ddec478fb711 irqchip/renesas-rzg2l: Rename rzg2l_tint_eoi()
ec5482d22c67 irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index
9913a07850e0 irqchip/renesas-rzg2l: Flush posted write in irq_eoi()
c15a37e3f162 irqchip/renesas-rzg2l: Implement restriction when writing ISCR register
ea4c338cfefa printk: Update @console_may_schedule in console_trylock_spinning()
e07a16e6f5b1 iommu/dma: Force swiotlb_max_mapping_size on an untrusted device
c803069d4845 swiotlb: Fix alignment checks when both allocation and DMA masks are present
ae2f8dbe921e swiotlb: Honour dma_alloc_coherent() alignment in swiotlb_alloc()
3e7acd6e25ba swiotlb: Fix double-allocation of slots due to broken alignment handling
4da463081026 entry: Respect changes to system call number by trace_sys_enter()
0c027c2bad7f ARM: 9359/1: flush: check if the folio is reserved for no-mapping addresses
66689127f1a7 ARM: 9352/1: iwmmxt: Remove support for PJ4/PJ4B cores
df13f43686f3 clocksource/drivers/arm_global_timer: Fix maximum prescaler value
0982fd6bf0b8 x86/sev: Fix position dependent variable references in startup code
ecd16da39d44 x86/Kconfig: Remove CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT
ee0bd4ad780d vfio/fsl-mc: Block calling interrupt handler without trigger
62d4e43a569b vfio/platform: Create persistent IRQ handlers
69276a555c74 vfio/pci: Create persistent INTx handler
2ee432d74043 vfio: Introduce interface to flush virqfd inject workqueue
ded566b4637f btrfs: fix deadlock with fiemap and extent locking
ea01221f95f3 xfs: remove conditional building of rt geometry validator functions
9efd84260f47 xfs: reset XFS_ATTR_INCOMPLETE filter on node removal
69252ab1d566 xfs: update dir3 leaf block metadata after swap
264e3509590c xfs: ensure logflagsp is initialized in xfs_bmap_del_extent_real
8a4566795552 xfs: fix perag leak when growfs fails
59b115a7e802 xfs: add lock protection when remove perag from radix tree
c4848932911b xfs: short circuit xfs_growfs_data_private() if delta is zero
47604cf2b803 xfs: initialise di_crc in xfs_log_dinode
b9358db0a811 xfs: add missing nrext64 inode flag check to scrub
1a48327c9e5a xfs: force all buffers to be written during btree bulk load
7bc086bbc977 xfs: fix an off-by-one error in xreap_agextent_binval
84cd4f79b4ce xfs: recompute growfsrtfree transaction reservation while growing rt volume
d6b65ed1cc5f xfs: remove unused fields from struct xbtree_ifakeroot
fb6e584e7471 xfs: make xchk_iget safer in the presence of corrupt inode btrees
3f6308034432 xfs: don't allow overly small or large realtime volumes
89e511a745be xfs: fix 32-bit truncation in xfs_compute_rextslog
0a31f1e8d8c6 xfs: make rextslog computation consistent with mkfs
680776e555f3 xfs: transfer recovered intent item ownership in ->iop_recover
87db24c8edd3 xfs: pass the xfs_defer_pending object to iop_recover
cd3c2cf35f7c xfs: use xfs_defer_pending objects to recover intent items
c0231292d059 xfs: don't leak recovered attri intent items
08bac45e02c6 xfs: consider minlen sized extents in xfs_rtallocate_extent_block
57a20b6150d3 xfs: convert rt bitmap extent lengths to xfs_rtbxlen_t
1a6d63f2418c xfs: move the xfs_rtbitmap.c declarations to xfs_rtbitmap.h
648b41f28181 wifi: rtw88: 8821cu: Fix connection failure
9fe75ad3c7e8 wifi: iwlwifi: pcie: fix RB status reading
3d0a7b23d688 ASoC: amd: yc: Revert "Fix non-functional mic on Lenovo 21J2"
930775060ca3 x86/efistub: Call mixed mode boot services on the firmware's stack
23b99c7bf6ec drm/amd/display: handle range offsets in VRR ranges
e21fee1035b9 drm/i915: Don't explode when the dig port we don't have an AUX CH
60b9d1887a35 iio: imu: inv_mpu6050: fix FIFO parsing when empty
3df5e345d6b4 iio: imu: inv_mpu6050: fix frequency setting when chip is off
d017ec50fac9 i2c: i801: Avoid potential double call to gpiod_remove_lookup_table
21e985684216 iio: accel: adxl367: fix I2C FIFO data register
73d42ed41182 iio: accel: adxl367: fix DEVID read after reset
d97be07a0027 arm64: dts: qcom: sc8280xp-x13s: limit pcie4 link speed
27cd25e3b3bc mm, vmscan: prevent infinite loop for costly GFP_NOIO | __GFP_RETRY_MAYFAIL allocations
b1c10caf752c ARM: imx_v6_v7_defconfig: Restore CONFIG_BACKLIGHT_CLASS_DEVICE
520f79c110ff tee: optee: Fix kernel panic caused by incorrect error handling
bccaba16db96 ALSA: hda/realtek: fix mute/micmute LEDs for HP EliteBook
6971e0592314 ALSA: hda/realtek - Add Headset Mic supported Acer NB platform
c01ed748847f fs/aio: Check IOCB_AIO_RW before the struct aio_kiocb conversion
ed56f3cfbe6f Revert "tty: serial: simplify qcom_geni_serial_send_chunk_fifo()"
7529cbd8b5f6 vt: fix unicode buffer corruption when deleting characters
68b988933885 mei: me: add arrow lake point H DID
e86a87a4bea8 mei: me: add arrow lake point S DID
434beb66368d serial: port: Don't suspend if the port is still busy
a62a30ccf721 misc: fastrpc: Pass proper arguments to scm call
997ca4153846 misc: lis3lv02d_i2c: Fix regulators getting en-/dis-abled twice on suspend/resume
16eac1126d6a tty: serial: fsl_lpuart: avoid idle preamble pending if CTS is enabled
cc31dba9afa6 xhci: Fix failure to detect ring expansion need.
a4eff9198449 usb: port: Don't try to peer unused USB ports based on location
a0f77b5d6067 usb: gadget: ncm: Fix handling of zero block length packets
4a22aeac24d0 usb: typec: altmodes/displayport: create sysfs nodes as driver's default device attribute group
871fd7b10b56 USB: usb-storage: Prevent divide-by-0 error in isd200_ata_command
a125ee2c06b0 ALSA: hda/realtek - Fix headset Mic no show at resume back for Lenovo ALC897 platform
a30c36bc0cfc drm/i915: Check before removing mm notifier
24b5eff43ec2 tty: serial: imx: Fix broken RS485
6f3c1dabe8d0 drm/amdgpu/pm: Fix the error of pwm1_enable setting
274f0b1a6b97 tracing: Use .flush() call to wake up readers
4577036353fa SEV: disable SEV-ES DebugSwap by default
12f8e32a5a38 KVM: SVM: Flush pages under kvm->lock to fix UAF in svm_register_enc_region()
9d1b22e573a3 KVM: x86: Mark target gfn of emulated atomic instruction as dirty
43c70cbc2502 firewire: ohci: prevent leak of left-over IRQ on unbind
a5b60c8b9a9e init/Kconfig: lower GCC version check for -Warray-bounds
4c9f70c73ddb Input: xpad - add additional HyperX Controller Identifiers
d9f400dc3e89 cgroup/cpuset: Fix retval in update_cpumask()
0f952b1bb048 usb: typec: tpcm: Fix PORT_RESET behavior for self powered devices
bae5b98dcf63 selftests: mptcp: diag: return KSFT_FAIL not test_cnt
b93494329656 mm, mmap: fix vma_merge() case 7 with vma_ops->close
b475226733f1 xfrm: Avoid clang fortify warning in copy_to_user_tmpl()
dc60b25540c8 crypto: sun8i-ce - Fix use after free in unprepare
48dd260fdb72 crypto: rk3288 - Fix use after free in unprepare
c288a61a48dd drm/nouveau: fix stale locked mutex in nouveau_gem_ioctl_pushbuf
6887314f5356 nouveau: lock the client object tree.
ba29cffccfea Drivers: hv: vmbus: Calculate ring buffer size for more efficient use of memory
7332d7389b5e netfilter: nf_tables: reject constant set with timeout
c0c2176d1814 netfilter: nf_tables: disallow anonymous set with timeout flag
b2d6f9a5b1cf netfilter: nf_tables: mark set as dead when unbinding anonymous set with timeout
56712f74b704 net: fix IPSTATS_MIB_OUTPKGS increment in OutForwDatagrams.
95232806972a drm/amd/display: Use freesync when `DRM_EDID_FEATURE_CONTINUOUS_FREQ` found
8b934390272d workqueue: Shorten events_freezable_power_efficient name
47ccb849a023 drm/bridge: lt8912b: do not return negative values from .get_modes()
d5a81e981769 drm/bridge: lt8912b: clear the EDID property on failures
a7d980a9f70e drm/bridge: lt8912b: use drm_bridge_edid_read()
2b6aaf7b193b drm/bridge: add ->edid_read hook and drm_bridge_edid_read()
de125efb3bae drm/ttm: Make sure the mapped tt pages are decrypted when needed
0436d691d216 wifi: brcmfmac: Demote vendor-specific attach/detach messages to info
8d59a64cbec8 wifi: brcmfmac: cfg80211: Use WSEC to set SAE password
47b563297a48 wifi: brcmfmac: add per-vendor feature detection callback
73520eeea49d x86/pm: Work around false positive kmemleak report in msr_build_context()
e50f83061ac2 dm snapshot: fix lockup in dm_exception_table_exit
066bbc430644 drm/amd/display: Fix noise issue on HDMI AV mute
c7c855fd3d5a drm/amd/display: Return the correct HDCP error code
6fcd12cb9088 drm/amdgpu: amdgpu_ttm_gart_bind set gtt bound flag
4992f44a3b05 ahci: asm1064: asm1166: don't limit reported ports
836af9a25b2d ahci: asm1064: correct count of reported ports
49391e9f1e14 wireguard: selftests: set RISCV_ISA_FALLBACK on riscv{32,64}
c991567e6c63 wireguard: netlink: access device through ctx instead of peer
13d107794304 wireguard: netlink: check for dangling peer via is_dead instead of empty list
7f1005dd39d2 LoongArch/crypto: Clean up useless assignment operations
d7d7c6cdea87 LoongArch: Define the __io_aw() hook as mmiowb()
f3f5d7a5049d LoongArch: Change __my_cpu_offset definition to avoid mis-optimization
3d26a2d80181 virtio: reenable config if freezing device failed
8a2e2336b8cf cxl/trace: Properly initialize cxl_poison region name
a66885b840d6 net: hns3: tracing: fix hclgevf trace event strings
9aa7a53c4733 drm/i915: Add missing ; to __assign_str() macros in tracepoint code
6244036a07ae NFSD: Fix nfsd_clid_class use of __string_len() macro
8291b4eac429 net: esp: fix bad handling of pages from page_pool
d0caabe6fe76 x86/CPU/AMD: Update the Zenbleed microcode revisions
f8a2a55a0b82 cpufreq: dt: always allocate zeroed cpumask
037414669414 mtd: rawnand: Constrain even more when continuous reads are enabled
26a4eee38f8c mtd: rawnand: Fix and simplify again the continuous read derivations
da2911798f25 cifs: open_cached_dir(): add FILE_READ_EA to desired access
997b0c26d3fa cifs: reduce warning log level for server not advertising interfaces
0845cb6bbf15 cifs: make cifs_chan_update_iface() a void function
4501f9cd36c1 cifs: delete unnecessary NULL checks in cifs_chan_update_iface()
db3a3e6fa33e cifs: do not let cifs_chan_update_iface deallocate channels
66c2940c9614 cifs: make sure server interfaces are requested only for SMB3+
407ced4e770e cifs: add xid to query server interface call
0c8aa4cfda4e nilfs2: prevent kernel bug at submit_bh_wbc()
f69e81396aea nilfs2: fix failure to detect DAT corruption in btree and direct mappings
6966586c2f77 f2fs: truncate page cache before clearing flags when aborting atomic write
99d1fd81d341 f2fs: mark inode dirty for FI_ATOMIC_COMMITTED flag
9a31f4b61448 Revert "block/mq-deadline: use correct way to throttling write requests"
f1d93b2a010c memtest: use {READ,WRITE}_ONCE in memory scanning
b483eff0bd19 drm/vc4: hdmi: do not return negative values from .get_modes()
fd79a093bb23 drm/imx/ipuv3: do not return negative values from .get_modes()
b71ae5fb2dd3 drm/exynos: do not return negative values from .get_modes()
a686732df6ce drm/panel: do not return negative error codes from drm_panel_get_modes()
12bbe2c25cdb drm/probe-helper: warn about negative .get_modes()
a64ab862e84e s390/zcrypt: fix reference counting on zcrypt card objects
54d26adf64c0 soc: fsl: qbman: Use raw spinlock for cgr_lock
0e6521b0f93f soc: fsl: qbman: Always disable interrupts when taking cgr_lock
700ed41bf63e dlm: fix user space lkb refcounting
b31301a1fa61 ring-buffer: Use wait_event_interruptible() in ring_buffer_wait()
7bcd58e8096a ring-buffer: Fix full_waiters_pending in poll
b87a7e108e6d ring-buffer: Fix resetting of shortest_full
73dae1a5d489 ring-buffer: Do not set shortest_full when full target is hit
b82dbe74ee31 ring-buffer: Fix waking up ring buffer readers
1241052e158d io_uring: clean rings on NO_MMAP alloc fail
e8fc78a1c70f platform/x86/intel/tpmi: Change vsec offset to u64
ed3fb2e2fe87 ksmbd: retrieve number of blocks using vfs_getattr in set_file_allocation_info
c8f7ad2df083 ksmbd: replace generic_fillattr with vfs_getattr
ef309589f01c server: convert to new timestamp accessors
1d7317d5b636 tpm,tpm_tis: Avoid warning splat at shutdown
74c564b7f008 vfio/platform: Disable virqfds on cleanup
04a4a017b9ff vfio/pci: Lock external INTx masking ops
2a4a666c4510 vfio/pci: Disable auto-enable of exclusive INTx IRQ
fe750e274442 thermal/drivers/mediatek: Fix control buffer enablement on MT7896
7e8cffa4f85e cifs: allow changing password during remount
9179aa27039a cifs: prevent updating file size from server if we have a read/write lease
b9e741ac2b7c smb: client: stop revalidating reparse points unnecessarily
db5f1f1fb8c1 PCI: hv: Fix ring buffer size calculation
cebb4baed803 PCI: dwc: endpoint: Fix advertised resizable BAR size
7aeca6f44cb6 PCI: qcom: Enable BDF to SID translation properly
52f86f3e091c kbuild: Move -Wenum-{compare-conditional,enum-conversion} into W=1
71739da67085 NFS: Read unlock folio on nfs_page_create_from_folio() error
e25447c35f87 nfs: fix UAF in direct writes
7293dd0bd34a sparc32: Fix parport build with sparc32
0f314c3be7d9 io_uring: fix mshot io-wq checks
f55ecbd9a78c io_uring/net: correctly handle multishot recvmsg retry setup
1a6efd4c286c PCI/AER: Block runtime suspend when handling errors
cc3519b818c1 speakup: Fix 8bit characters from direct synth
a973ef25f144 usb: gadget: tegra-xudc: Fix USB3 PHY retrieval logic
3dd6e0faa75d phy: tegra: xusb: Add API to retrieve the port number of phy
0ef9d78ba7e7 slimbus: core: Remove usage of the deprecated ida_simple_xx() API
63c7a5cf228e nvmem: meson-efuse: fix function pointer type mismatch
37b6a3ba793b ext4: fix corruption during on-line resize
27715371c162 hwmon: (amc6821) add of_match table
100d83b0da07 landlock: Warn once if a Landlock action is requested while disabled
bc8e5fda787b drm/etnaviv: Restore some id values
10f2af1af8ab leds: trigger: netdev: Fix kernel panic on interface rename trig notify
d4e2365b07f1 Bluetooth: btnxpuart: Fix btnxpuart_close
985edff78e80 mmc: core: Fix switch on gp3 partition
0f98f6d2fb5f mm: swap: fix race between free_swap_and_cache() and swapoff()
20d3e1c8a184 mac802154: fix llsec key resources release in mac802154_llsec_key_del
7d3765550374 block: Fix page refcounts for unaligned buffers in __bio_release_pages()
653d51504f41 powerpc: xor_vmx: Add '-mhard-float' to CFLAGS
dc9702acfb4f dm-raid: fix lockdep waring in "pers->hot_add_disk"
31ead1845c37 PCI/DPC: Quirk PIO log size for Intel Raptor Lake Root Ports
d86ad8c3e152 PCI/PM: Drain runtime-idle callbacks before driver removal
0bfe6b29d6ac wifi: rtw88: Add missing VID/PIDs for 8811CU and 8821CU
51dad05f1835 btrfs: fix off-by-one chunk length calculation at contains_pending_extent()
40a24160cf3c btrfs: qgroup: always free reserved space for extent records
4cc3e2ed6759 serial: Lock console when calling into driver before registration
6f12c54fa09d serial: core: only stop transmit when HW fifo is empty
1846bd4fc1bb usb: dwc3-am62: Disable wakeup at remove
7dfed9855397 usb: dwc3-am62: fix module unload/reload behavior
4a1f0678d15e usb: typec: ucsi: Clean up UCSI_CABLE_PROP macros
8b86779ade3a fuse: don't unhash root
777ba18929b5 fuse: fix root lookup with nonzero generation
3d304dd6b29d fuse: replace remaining make_bad_inode() with fuse_make_bad()
bd169abd394e mmc: tmio: avoid concurrent runs of mmc_request_done()
677aa47e3e43 PM: sleep: wakeirq: fix wake irq warning in system suspend
3c3df979e9b7 USB: serial: cp210x: add pid/vid for TDK NC0110013M and MM0110113M
28f719670f00 KVM: x86/xen: inject vCPU upcall vector when local APIC is enabled
5cf342a13d49 USB: serial: option: add MeiG Smart SLM320 product
07a8b301818f USB: serial: cp210x: add ID for MGP Instruments PDS100
515159ca62a8 USB: serial: add device ID for VeriFone adapter
58bb229d9714 USB: serial: ftdi_sio: add support for GMC Z216C Adapter IR-USB
816ae3cf3dcb powerpc/fsl: Fix mfpmr build errors with newer binutils
620b6cf2f1a2 usb: xhci: Add error handling in xhci_map_urb_for_dma
7e9926fef71e clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays
9b4c4546dd61 clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays
0204247cf366 clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays
b6b31b4c67ea clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays
421b135aceac clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays
b0cf3d200e8a clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays
245c318cdad0 vfio/pds: Always clear the save/restore FDs on reset
35c1cdd504a3 PM: suspend: Set mem_sleep_current during kernel command line setup
ed87a423756a cpufreq: Limit resolving a frequency to policy min/max
66e2c41b0c80 docs: Restore "smart quotes" for quotes
f77c8c1603bb iio: adc: rockchip_saradc: use mask for write_enable bitfield
7ed675cfaf51 iio: adc: rockchip_saradc: fix bitmask for channels on SARADCv2
8ec4a68a25a2 md/raid5: fix atomicity violation in raid5_cache_count
644604e6f014 parisc: Strip upper 32 bit of sum in csum_ipv6_magic for 64-bit builds
d4b71ff9c918 parisc: Fix csum_ipv6_magic on 64-bit systems
cabe3343acce parisc: Fix csum_ipv6_magic on 32-bit systems
d31c8d0ca8bf parisc: Fix ip_fast_csum
6bd42452713e parisc: Avoid clobbering the C/B bits in the PSW with tophys and tovirt macros
51408b47f8af parisc/unaligned: Rewrite 64-bit inline assembly of emulate_ldd()
f9f67e87e4b7 x86/nmi: Fix the inverse "in NMI handler" check
736ad6c577a3 md/md-bitmap: fix incorrect usage for sb_index
d8ea3e788b5a mtd: rawnand: meson: fix scrambling mode value in command macro
1a3487cdf8dc ubi: correct the calculation of fastmap size
d1b505c988b7 ubi: Check for too small LEB size in VTBL code
fc99f4e2d2f1 ubifs: Set page uptodate in the correct place
ab8f9df10694 fuse: fix VM_MAYSHARE and direct_io_allow_mmap
03a7e3f2ba3c fat: fix uninitialized field in nostale filehandles
b46c822f8b55 bounds: support non-power-of-two CONFIG_NR_CPUS
d6e646b86085 kasan/test: avoid gcc warning for intentional overflow
fe86d01ce7db block: Clear zone limits for a non-zoned stacked queue
ba191200a1ae ext4: correct best extent lstart adjustment logic
9a06d17abc16 selftests/mqueue: Set timeout to 180 seconds
8a5a7611ccc7 crypto: qat - resolve race condition during AER recovery
e8ac80031809 sparc: vDSO: fix return value of __setup handler
61798d3cb53a sparc64: NMI watchdog: fix return value of __setup handler
a0b9f4f8e22b powerpc/smp: Increase nr_cpu_ids to include the boot CPU
68a9c41f0167 powerpc/smp: Adjust nr_cpu_ids to cover all threads of a core
7f6282665dd7 powercap: intel_rapl_tpmi: Fix System Domain probing
b5cbb42fb658 powercap: intel_rapl_tpmi: Fix a register bug
d6c83ee705a1 powercap: intel_rapl: Fix locking in TPMI RAPL
c4c2f7e672e7 sched: Simplify tg_set_cfs_bandwidth()
0641908b906a powercap: intel_rapl: Fix a NULL pointer dereference
9df6a7a3c951 thermal/intel: Fix intel_tcc_get_temp() to support negative CPU temperature
868e3264f236 cpufreq: amd-pstate: Fix min_perf assignment in amd_pstate_adjust_perf()
e056484f189b arm64: dts: qcom: sm8550-mtp: correct WCD9385 TX port mapping
6eacb2ec2e79 arm64: dts: qcom: sm8550-qrd: correct WCD9385 TX port mapping
a75afe480d43 KVM: Always flush async #PF workqueue when vCPU is being destroyed
88efc3095b6d media: nxp: imx8-isi: Mark all crossbar sink pads as MUST_CONNECT
d0e3440dab0d media: mc: Expand MUST_CONNECT flag to always require an enabled link
3b6ccc91dcc4 media: mc: Rename pad variable to clarify intent
ebb6fb7f6265 media: mc: Add num_links flag to media_pad
c95318607fbe media: nxp: imx8-isi: Check whether crossbar pad is non-NULL before access
0a7690224714 media: mc: Fix flags handling when creating pad links
cc088ebf8b4a media: mc: Add local pad to pipeline regardless of the link state
dc5e4f240473 media: xc4000: Fix atomicity violation in xc4000_get_frequency
b5d40f02e722 pci_iounmap(): Fix MMIO mapping leak
86cb706a40b7 drm/vmwgfx: Fix the lifetime of the bo cursor memory
2160ad6861c4 serial: max310x: fix NULL pointer dereference in I2C instantiation
ff41e0d4f3fa drm/vmwgfx: Fix possible null pointer derefence with invalid contexts
01fad74090a0 arm: dts: marvell: Fix maxium->maxim typo in brownstone dts
3677d01c55bc smack: Handle SMACK64TRANSMUTE in smack_inode_setsecurity()
c6fc44595491 smack: Set SMACK64TRANSMUTE only for dirs in smack_inode_setxattr()
a1a8d40182e2 clk: qcom: gcc-sdm845: Add soft dependency on rpmhpd
2c26984759bb remoteproc: virtio: Fix wdg cannot recovery remote processor
779af170f1db arm64: dts: qcom: sc7280: Add additional MSI interrupts
1992f2af6444 media: staging: ipu3-imgu: Set fields before media_entity_pads_init()
e76f6b9618e8 wifi: brcmfmac: avoid invalid list operation when vendor attach fails
190794848e2b wifi: brcmfmac: Fix use-after-free bug in brcmf_cfg80211_detach
0a23f95af7f2 drm/vmwgfx: Unmap the surface before resetting it on a plane state
51138f1f3564 KVM: x86: Use a switch statement and macros in __feature_translate()
688313fb139e KVM: x86: Advertise CPUID.(EAX=7,ECX=2):EDX[5:0] to userspace
06644f0d7193 drm/tilcdc: Set preferred depth
ff7ae7b32324 crypto: jitter - add RCT/APT support for different OSRs
50cd24ddb6f0 arm64: defconfig: remove CONFIG_IPQ_APSS_5018
58e5c91d6701 x86/alternatives: Disable interrupts and sync when optimizing NOPs in place
c878fd2d4c79 x86/alternatives: Sync core before enabling interrupts
c2d64b9f52b6 qemux86: add configuration symbol to select values
630c33229e6d sched/isolation: really align nohz_full with rcu_nocbs
0e5e0f68e2e6 clear_warn_once: add a clear_warn_once= boot parameter
46934791b902 clear_warn_once: bind a timer to written reset value
cdee9e38ff32 clear_warn_once: expand debugfs to include read support
82b562b81841 tools: Remove some options from CLANG_CROSS_FLAGS
36dc380b776b libbpf: Fix build warning on ref_ctr_off
9e3e1fe20982 perf: perf can not parser the backtrace of app in the 32bit system and 64bit kernel.
e497a4a5da65 perf: x86-32: explicitly include <errno.h>
7b57ddd89565 perf: mips64: Convert __u64 to unsigned long long
1cfc19423dc7 perf: fix bench numa compilation
98bc2815fade perf: add SLANG_INC for slang.h
17209a70b9b3 perf: add sgidefs.h to for mips builds
9cd4258d910a perf: change --root to --prefix for python install
8110a4f26628 perf: add 'libperl not found' warning
bc89d5e08f77 perf: force include of <stdbool.h>
4f6c760cc876 fat: Replace prandom_u32() with get_random_u32()
bc53117b12b2 fat: don't use obsolete random32 call in namei_vfat
30b2236ab378 FAT: Added FAT_NO_83NAME
cef98d22b4ed FAT: Add CONFIG_VFAT_NO_CREATE_WITH_LONGNAMES option
0bbd7daba9e1 FAT: Add CONFIG_VFAT_FS_NO_DUALNAMES option
5883fc340084 aufs6: adapt to v6.6 i_op->ctime changes
c4342d979bf2 aufs6: fix magic.mk include path
35266bc2dc81 aufs6: adapt to v6.6
8edede4e98be aufs6: core
712248233ebe aufs6: standalone
3b71a8a848d8 aufs6: mmap
3e2924871f37 aufs6: base
7f4907a93101 aufs6: kbuild
d2f7b03e4aa7 yaffs2: update VFS ctime operations to 6.6+
bcd6cfcd1aa0 yaffs2: v6.5 fixups
cc615704b5f5 yaffs2: Fix miscalculation of devname buffer length
8ef2e22dcf91 yaffs2: convert user_namespace to mnt_idmap
c9c749f9f7d3 yaffs2: replace bdevname call with sprintf
395b01cdc39d yaffs2: convert read_page -> readfolio
d98b07e43ba6 yaffs: replace IS_ERR with IS_ERR_OR_NULL to check both ERR and NULL
613c6d50fdbe yaffs: fix -Wstringop-overread compile warning in yaffs_fix_null_name
622c4648936f yaffs2: v5.12+ build fixups (not runtime tested)
7562133d4090 yaffs: include blkdev.h
dbd44252cd59 yaffs: fix misplaced variable declaration
c223a10b1ac0 yaffs2: v5.6 build fixups
90f6007cfbf4 yaffs2: fix memory leak when /proc/yaffs is read
37ee169c5ea1 yaffs: add strict check when call yaffs_internal_read_super
b6e007b8abb6 yaffs: repair yaffs_get_mtd_device
fb98f65a466a yaffs: Fix build failure by handling inode i_version with proper atomic API
51e0aac75ea2 yaffs2: fix memory leak in mount/umount
2b74a0cae7b0 yaffs: Avoid setting any ACL releated xattr
ff4130a9c376 Yaffs:check oob size before auto selecting Yaffs1
ba95b409c67c fs: yaffs2: replace CURRENT_TIME by other appropriate apis
8fa35eba9056 yaffs2: adjust to proper location of MS_RDONLY
1eb5deaad8c4 yaffs2: import git revision b4ce1bb (jan, 2020)
4dce67c1e8c8 initramfs: allow an optional wrapper script around initramfs generation
2f603d83fcc4 pnmtologo: use relocatable file name
664a6a0a484b tools: use basename to identify file in gen-mach-types
9de64bc0c185 lib/build_OID_registry: fix reproducibility issues
ae9b80797295 vt/conmakehash: improve reproducibility
a972323151bd iwlwifi: select MAC80211_LEDS conditionally
15d2adcc0198 net/dccp: make it depend on CONFIG_BROKEN (CVE-2020-16119)
5556a6c04b19 arm64/perf: Fix wrong cast that may cause wrong truncation
5552dc768ffc defconfigs: drop obselete options
00fe4152df31 arm64/perf: fix backtrace for AAPCS with FP enabled
3888d0652edf linux-yocto: Handle /bin/awk issues
3d55d299f23a uvesafb: provide option to specify timeout for task completion
23c068c080be uvesafb: print error message when task timeout occurs
edbfc939266e compiler.h: Undef before redefining __attribute_const__
c99ae7e2a19a vmware: include jiffies.h
572d84d928c8 Resolve jiffies wrapping about arp
fdcd47cac843 nfs: Allow default io size to be configured.
927d48801098 check console device file on fs when booting
57cc27f821dd mount_root: clarify error messages for when no rootfs found
1b53d82a8152 mconf: fix output of cflags and libraries
1811da09f42c menuconfig,mconf-cfg: Allow specification of ncurses location
83c2e0c6eb1f modpost: mask trivial warnings
6de673039484 kbuild: exclude meta directory from distclean processing
6decd32815f5 powerpc: serialize image targets
f6b683b38318 arm: serialize build targets
e798b09ebf57 mtd_blkdevs: add mtd_table_mutex lock back to blktrans_{open, release} to avoid race condition
dc8a1e5a88f8 x86_64_defconfig: Fix warnings
68491e5f72b6 powerpc/ptrace: Disable array-bounds warning with gcc8
d71ebfce3004 powerpc: Disable attribute-alias warnings from gcc8
62f50884b8b1 powerpc: kexec fix for powerpc64
da6871c62c37 powerpc: Add unwind information for SPE registers of E500 core
f161c880c11d mips: make current_cpu_data preempt safe
5e94a8247ce7 mips: vdso: fix 'jalr $t9' crash in vdso code
19e36714b1c7 mips: Kconfig: add QEMUMIPS64 option
e2e537db3cbd 4kc cache tlb hazard: tlbp cache coherency
aee9870611e5 malta uhci quirks: make allowance for slow 4k(e)c
881948cd1517 drm/fb-helper: move zeroing code to drm_fb_helper_fill_var
98ec1963fcb7 arm64: defconfig: cleanup config options
f1727c537ba8 vexpress: Pass LOADADDR to Makefile
4474c32dc24a arm: ARM EABI socketcall
75e31a2b70fd ARM: LPAE: Invalidate the TLB for module addresses during translation fault
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
---
.../linux/linux-yocto-rt_6.6.bb | 6 ++--
.../linux/linux-yocto-tiny_6.6.bb | 6 ++--
meta/recipes-kernel/linux/linux-yocto_6.6.bb | 28 +++++++++----------
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/meta/recipes-kernel/linux/linux-yocto-rt_6.6.bb b/meta/recipes-kernel/linux/linux-yocto-rt_6.6.bb
index a44a08451a..2f788667f0 100644
--- a/meta/recipes-kernel/linux/linux-yocto-rt_6.6.bb
+++ b/meta/recipes-kernel/linux/linux-yocto-rt_6.6.bb
@@ -14,13 +14,13 @@ python () {
raise bb.parse.SkipRecipe("Set PREFERRED_PROVIDER_virtual/kernel to linux-yocto-rt to enable it")
}
-SRCREV_machine ?= "19813826de57a6425518c7b3daf8dd6a04d2321f"
-SRCREV_meta ?= "f7f00b22efcfcae6489e9ec7db7002685fbc078b"
+SRCREV_machine ?= "7290738691e931c361f5391a47189e40477cc2a2"
+SRCREV_meta ?= "03ec143a0ca70ff92968bc4ea919e936ab9e8572"
SRC_URI = "git://git.yoctoproject.org/linux-yocto.git;branch=${KBRANCH};name=machine;protocol=https \
git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.6;destsuffix=${KMETA};protocol=https"
-LINUX_VERSION ?= "6.6.23"
+LINUX_VERSION ?= "6.6.24"
LIC_FILES_CHKSUM = "file://COPYING;md5=6bc538ed5bd9a7fc9398086aedcd7e46"
diff --git a/meta/recipes-kernel/linux/linux-yocto-tiny_6.6.bb b/meta/recipes-kernel/linux/linux-yocto-tiny_6.6.bb
index db9e252572..4f9474efae 100644
--- a/meta/recipes-kernel/linux/linux-yocto-tiny_6.6.bb
+++ b/meta/recipes-kernel/linux/linux-yocto-tiny_6.6.bb
@@ -8,7 +8,7 @@ require recipes-kernel/linux/linux-yocto.inc
# CVE exclusions
include recipes-kernel/linux/cve-exclusion_6.6.inc
-LINUX_VERSION ?= "6.6.23"
+LINUX_VERSION ?= "6.6.24"
LIC_FILES_CHKSUM = "file://COPYING;md5=6bc538ed5bd9a7fc9398086aedcd7e46"
DEPENDS += "${@bb.utils.contains('ARCH', 'x86', 'elfutils-native', '', d)}"
@@ -17,8 +17,8 @@ DEPENDS += "openssl-native util-linux-native"
KMETA = "kernel-meta"
KCONF_BSP_AUDIT_LEVEL = "2"
-SRCREV_machine ?= "2d01bc1d4eeade12518371139dd24a21438f523c"
-SRCREV_meta ?= "f7f00b22efcfcae6489e9ec7db7002685fbc078b"
+SRCREV_machine ?= "2f64879b557ec6baccf27afdd4d02a46051b65bc"
+SRCREV_meta ?= "03ec143a0ca70ff92968bc4ea919e936ab9e8572"
PV = "${LINUX_VERSION}+git"
diff --git a/meta/recipes-kernel/linux/linux-yocto_6.6.bb b/meta/recipes-kernel/linux/linux-yocto_6.6.bb
index 43696db59b..65a3e9a97d 100644
--- a/meta/recipes-kernel/linux/linux-yocto_6.6.bb
+++ b/meta/recipes-kernel/linux/linux-yocto_6.6.bb
@@ -18,25 +18,25 @@ KBRANCH:qemux86-64 ?= "v6.6/standard/base"
KBRANCH:qemuloongarch64 ?= "v6.6/standard/base"
KBRANCH:qemumips64 ?= "v6.6/standard/mti-malta64"
-SRCREV_machine:qemuarm ?= "ceb94a85299b59d8840ed7ed392b1d3e4c727678"
-SRCREV_machine:qemuarm64 ?= "2d01bc1d4eeade12518371139dd24a21438f523c"
-SRCREV_machine:qemuloongarch64 ?= "2d01bc1d4eeade12518371139dd24a21438f523c"
-SRCREV_machine:qemumips ?= "c79ffc89f8909f60de52005ef258db9752634eda"
-SRCREV_machine:qemuppc ?= "2d01bc1d4eeade12518371139dd24a21438f523c"
-SRCREV_machine:qemuriscv64 ?= "2d01bc1d4eeade12518371139dd24a21438f523c"
-SRCREV_machine:qemuriscv32 ?= "2d01bc1d4eeade12518371139dd24a21438f523c"
-SRCREV_machine:qemux86 ?= "2d01bc1d4eeade12518371139dd24a21438f523c"
-SRCREV_machine:qemux86-64 ?= "2d01bc1d4eeade12518371139dd24a21438f523c"
-SRCREV_machine:qemumips64 ?= "b0a73fa83073c8d7d7bc917bcbeac88d296ebe38"
-SRCREV_machine ?= "2d01bc1d4eeade12518371139dd24a21438f523c"
-SRCREV_meta ?= "f7f00b22efcfcae6489e9ec7db7002685fbc078b"
+SRCREV_machine:qemuarm ?= "47c23d5ba2db28b76e62e152bf4601f30ffbb1a6"
+SRCREV_machine:qemuarm64 ?= "2f64879b557ec6baccf27afdd4d02a46051b65bc"
+SRCREV_machine:qemuloongarch64 ?= "2f64879b557ec6baccf27afdd4d02a46051b65bc"
+SRCREV_machine:qemumips ?= "d433ef0d8830772213f0d667478d675e778cfbc1"
+SRCREV_machine:qemuppc ?= "2f64879b557ec6baccf27afdd4d02a46051b65bc"
+SRCREV_machine:qemuriscv64 ?= "2f64879b557ec6baccf27afdd4d02a46051b65bc"
+SRCREV_machine:qemuriscv32 ?= "2f64879b557ec6baccf27afdd4d02a46051b65bc"
+SRCREV_machine:qemux86 ?= "2f64879b557ec6baccf27afdd4d02a46051b65bc"
+SRCREV_machine:qemux86-64 ?= "2f64879b557ec6baccf27afdd4d02a46051b65bc"
+SRCREV_machine:qemumips64 ?= "480ddad109153a5cadd6c625d93044d7d93ce8bd"
+SRCREV_machine ?= "2f64879b557ec6baccf27afdd4d02a46051b65bc"
+SRCREV_meta ?= "03ec143a0ca70ff92968bc4ea919e936ab9e8572"
# set your preferred provider of linux-yocto to 'linux-yocto-upstream', and you'll
# get the <version>/base branch, which is pure upstream -stable, and the same
# meta SRCREV as the linux-yocto-standard builds. Select your version using the
# normal PREFERRED_VERSION settings.
BBCLASSEXTEND = "devupstream:target"
-SRCREV_machine:class-devupstream ?= "5c7587f69194bc9fc714953ab4c7203e6e68885b"
+SRCREV_machine:class-devupstream ?= "9467d7a12f970e7f12adcba143b0c9b9d1a9e72d"
PN:class-devupstream = "linux-yocto-upstream"
KBRANCH:class-devupstream = "v6.6/base"
@@ -44,7 +44,7 @@ SRC_URI = "git://git.yoctoproject.org/linux-yocto.git;name=machine;branch=${KBRA
git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.6;destsuffix=${KMETA};protocol=https"
LIC_FILES_CHKSUM = "file://COPYING;md5=6bc538ed5bd9a7fc9398086aedcd7e46"
-LINUX_VERSION ?= "6.6.23"
+LINUX_VERSION ?= "6.6.24"
PV = "${LINUX_VERSION}+git"
--
2.39.2
^ permalink raw reply related [relevance 2%]
* Re: [PATCH V3 5/8] dt-bindings: clock: qcom: Fix the incorrect order of SC8280XP camcc header
2024-05-01 6:43 0% ` Johan Hovold
@ 2024-05-02 11:09 0% ` Jagadeesh Kona
0 siblings, 0 replies; 200+ results
From: Jagadeesh Kona @ 2024-05-02 11:09 UTC (permalink / raw)
To: Johan Hovold
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Vladimir Zapolskiy, Bryan O'Donoghue, linux-arm-msm,
linux-clk, devicetree, linux-kernel, Taniya Das,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik
On 5/1/2024 12:13 PM, Johan Hovold wrote:
> On Tue, Apr 30, 2024 at 07:57:54PM +0530, Jagadeesh Kona wrote:
>> Fix the incorrect order of SC8280XP camcc header file in SM8450 camcc
>> bindings.
>
> Try to avoid using the word "fix" in the commit summary (Subject) and
> commit message for things like this which are essentially cleanups to
> avoid making it sound like a bug fix (which automated tooling may then
> select for backporting).
>
Thanks Johan for your review!
Yes, will remove the word "fix" in commit subject and message.
>> Fixes: 206cd759fbd2 ("dt-bindings: clock: Add SC8280XP CAMCC")
>
> Also drop the Fixes tag as this is not a bug fix.
>
Sure, will drop Fixes tag in next series.
Thanks,
Jagadeesh
>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>> ---
>> Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
>> index fa0e5b6b02b8..bf23e25d71f5 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
>> @@ -14,9 +14,9 @@ description: |
>> domains on SM8450.
>>
>> See also::
>> + include/dt-bindings/clock/qcom,sc8280xp-camcc.h
>> include/dt-bindings/clock/qcom,sm8450-camcc.h
>> include/dt-bindings/clock/qcom,sm8550-camcc.h
>> - include/dt-bindings/clock/qcom,sc8280xp-camcc.h
>> include/dt-bindings/clock/qcom,x1e80100-camcc.h
>
> Johan
^ permalink raw reply [relevance 0%]
* [PATCH v5 2/3] arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
2024-05-02 8:00 7% [PATCH v5 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock Neil Armstrong
@ 2024-05-02 8:00 19% ` Neil Armstrong
0 siblings, 0 replies; 200+ results
From: Neil Armstrong @ 2024-05-02 8:00 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong,
Dmitry Baryshkov
The PCIe Gen4x2 PHY found in the SM8550 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.
Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes
2 clocks, properly add the pcie1_phy provided clocks to the Global Clock
Controller (GCC) node clocks inputs.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 19 -------------------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
4 files changed, 4 insertions(+), 36 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 12d60a0ee095..ccff744dcd14 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -979,10 +979,6 @@ &pcie1_phy {
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 3d4ad5aac70f..1fa7c4492057 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -739,10 +739,6 @@ &mdss_dp0_out {
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 92f015017418..39ba3e9969b7 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -720,17 +720,6 @@ &ipa {
status = "okay";
};
-&gcc {
- clocks = <&bi_tcxo_div2>, <&sleep_clk>,
- <&pcie0_phy>,
- <&pcie1_phy>,
- <0>,
- <&ufs_mem_phy 0>,
- <&ufs_mem_phy 1>,
- <&ufs_mem_phy 2>,
- <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
-};
-
&gpi_dma1 {
status = "okay";
};
@@ -810,10 +799,6 @@ &mdss_dp0_out {
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
-&pcie_1_phy_aux_clk {
- status = "disabled";
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
@@ -907,10 +892,6 @@ &pon_resin {
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&qupv3_id_0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index bc5aeb05ffc3..143994d1e6ca 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -58,11 +58,6 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-mult = <1>;
clock-div = <2>;
};
-
- pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
};
cpus {
@@ -776,8 +771,8 @@ gcc: clock-controller@100000 {
#power-domain-cells = <1>;
clocks = <&bi_tcxo_div2>, <&sleep_clk>,
<&pcie0_phy>,
- <&pcie1_phy>,
- <&pcie_1_phy_aux_clk>,
+ <&pcie1_phy QMP_PCIE_PIPE_CLK>,
+ <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
@@ -1928,8 +1923,8 @@ pcie1_phy: phy@1c0e000 {
power-domains = <&gcc PCIE_1_PHY_GDSC>;
- #clock-cells = <0>;
- clock-output-names = "pcie1_pipe_clk";
+ #clock-cells = <1>;
+ clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";
#phy-cells = <0>;
--
2.34.1
^ permalink raw reply related [relevance 19%]
* [PATCH v5 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock
@ 2024-05-02 8:00 7% Neil Armstrong
2024-05-02 8:00 19% ` [PATCH v5 2/3] arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk Neil Armstrong
0 siblings, 1 reply; 200+ results
From: Neil Armstrong @ 2024-05-02 8:00 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong,
Dmitry Baryshkov
The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.
Document the clock IDs to select the PIPE clock or the AUX clock,
also enforce a second clock-output-names and a #clock-cells value of 1
for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
The PHY driver needs a light refactoring to support a second clock,
and finally the DT is changed to connect the PHY second clock to the
corresponding GCC input then drop the dummy fixed rate clock.
To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Changes in v5:
- Reworked commit message to include more reasoning and details about the changes
- Link to v4: https://lore.kernel.org/r/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v4-0-868b15a17a45@linaro.org
Changes in v4:
- Fixed dtbs check error on sm8550-qrd.dtb after rebase on -next
- Link to v3: https://lore.kernel.org/r/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org
Changes in v3:
- Rebased on linux-next, applies now cleanly
- Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org
Changes in v2:
- Collected review tags
- Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility
- Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code
and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0
when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get()
- Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org
---
Neil Armstrong (3):
arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc
arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 19 -------------------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++---------
8 files changed, 12 insertions(+), 57 deletions(-)
---
base-commit: 1d0a6cdb7d77a14da03246bb6f10a489ad49af41
change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [relevance 7%]
* Re: [PATCH 6.1 251/272] usb: typec: ucsi: Check for notifications after init
@ 2024-05-01 19:10 0% ` Christian A. Ehrhardt
2024-05-13 13:02 0% ` Greg Kroah-Hartman
0 siblings, 1 reply; 200+ results
From: Christian A. Ehrhardt @ 2024-05-01 19:10 UTC (permalink / raw)
To: Greg Kroah-Hartman; +Cc: stable, patches, Heikki Krogerus, Neil Armstrong
Hi Greg,
On Tue, Apr 02, 2024 at 09:52:47AM +0200, Greg Kroah-Hartman wrote:
> On Tue, Apr 02, 2024 at 08:06:52AM +0200, Christian A. Ehrhardt wrote:
> >
> > Hi Greg,
> >
> > On Tue, Apr 02, 2024 at 07:40:43AM +0200, Greg Kroah-Hartman wrote:
> > > On Mon, Apr 01, 2024 at 10:16:45PM +0200, Christian A. Ehrhardt wrote:
> > > >
> > > > Hi Greg,
> > > >
> > > > On Mon, Apr 01, 2024 at 05:47:21PM +0200, Greg Kroah-Hartman wrote:
> > > > > 6.1-stable review patch. If anyone has any objections, please let me know.
> > > > >
> > > > > ------------------
> > > > >
> > > > > From: Christian A. Ehrhardt <lk@c--e.de>
> > > > >
> > > > > commit 808a8b9e0b87bbc72bcc1f7ddfe5d04746e7ce56 upstream.
> > > > >
> > > > > The completion notification for the final SET_NOTIFICATION_ENABLE
> > > > > command during initialization can include a connector change
> > > > > notification. However, at the time this completion notification is
> > > > > processed, the ucsi struct is not ready to handle this notification.
> > > > > As a result the notification is ignored and the controller
> > > > > never sends an interrupt again.
> > > > >
> > > > > Re-check CCI for a pending connector state change after
> > > > > initialization is complete. Adjust the corresponding debug
> > > > > message accordingly.
> > > > >
> > > > > Fixes: 71a1fa0df2a3 ("usb: typec: ucsi: Store the notification mask")
> > > > > Cc: stable@vger.kernel.org
> > > > > Signed-off-by: Christian A. Ehrhardt <lk@c--e.de>
> > > > > Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> > > > > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
> > > > > Link: https://lore.kernel.org/r/20240320073927.1641788-3-lk@c--e.de
> > > > > Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > > > > ---
> > > > > drivers/usb/typec/ucsi/ucsi.c | 10 +++++++++-
> > > > > 1 file changed, 9 insertions(+), 1 deletion(-)
> > > >
> > > > This change has an out of bounds memory access. Please drop it from
> > > > the stable trees until a fix is available.
> > >
> > > Shouldn't we get a fix for Linus's tree too? Have I missed that
> > > somewhere? Or should this just be reverted now?
> >
> > I posted the fix a few hours after sending this mail. It is here:
> > https://lore.kernel.org/all/20240401210515.1902048-1-lk@c--e.de/
> >
> > Either this should be fast tracked to Linus or the original change
> > reverted, yes.
>
> I've dropped the offending commit from the stable queues now. Once this
> fix gets into Linus's tree, let us know and I will add both in then.
The fix for
808a8b9e0b87 ("usb: typec: ucsi: Check for notifications after init")
has hit Linus's tree as
ce4c8d21054a ("usb: typec: ucsi: Fix connector check on init")
There is no urgency but this is to let you know that the original commit
is eligible for -stable again, provided that the follow up commit is
backported, too.
Best regards,
Christian
^ permalink raw reply [relevance 0%]
* [PATCH 01/13] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schema
@ 2024-05-01 16:19 5% ` Dmitry Baryshkov
0 siblings, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-05-01 16:19 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Abel Vesa, Wesley Cheng,
cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio,
David Wronek, Andy Gross, Evan Green, Douglas Anderson,
Iskren Chernev, Luca Weiss, Bryan O'Donoghue,
Yassine Oudjana
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-phy, devicetree,
linux-kernel, Krzysztof Kozlowski, Konrad Dybcio,
Dmitry Baryshkov
The qcom,x1e80100-qmp-gen3x2-pcie-phy device doesn't have second reset,
drop it from the clause enforcing second reset to be used.
Fixes: e94b29f2bd73 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHYs")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 14ac341b1577..16634f73bdcf 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -198,7 +198,6 @@ allOf:
enum:
- qcom,sm8550-qmp-gen4x2-pcie-phy
- qcom,sm8650-qmp-gen4x2-pcie-phy
- - qcom,x1e80100-qmp-gen3x2-pcie-phy
- qcom,x1e80100-qmp-gen4x2-pcie-phy
then:
properties:
--
2.39.2
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [relevance 5%]
* [PATCH 01/13] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schema
@ 2024-05-01 16:19 5% ` Dmitry Baryshkov
0 siblings, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-05-01 16:19 UTC (permalink / raw)
To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Abel Vesa, Wesley Cheng,
cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio,
David Wronek, Andy Gross, Evan Green, Douglas Anderson,
Iskren Chernev, Luca Weiss, Bryan O'Donoghue,
Yassine Oudjana
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-phy, devicetree,
linux-kernel, Krzysztof Kozlowski, Konrad Dybcio,
Dmitry Baryshkov
The qcom,x1e80100-qmp-gen3x2-pcie-phy device doesn't have second reset,
drop it from the clause enforcing second reset to be used.
Fixes: e94b29f2bd73 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHYs")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 14ac341b1577..16634f73bdcf 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -198,7 +198,6 @@ allOf:
enum:
- qcom,sm8550-qmp-gen4x2-pcie-phy
- qcom,sm8650-qmp-gen4x2-pcie-phy
- - qcom,x1e80100-qmp-gen3x2-pcie-phy
- qcom,x1e80100-qmp-gen4x2-pcie-phy
then:
properties:
--
2.39.2
^ permalink raw reply related [relevance 5%]
* Re: [PATCH V3 5/8] dt-bindings: clock: qcom: Fix the incorrect order of SC8280XP camcc header
2024-04-30 14:27 5% ` [PATCH V3 5/8] dt-bindings: clock: qcom: Fix the incorrect order of SC8280XP camcc header Jagadeesh Kona
2024-05-01 6:43 0% ` Johan Hovold
@ 2024-05-01 10:42 0% ` Bryan O'Donoghue
1 sibling, 0 replies; 200+ results
From: Bryan O'Donoghue @ 2024-05-01 10:42 UTC (permalink / raw)
To: Jagadeesh Kona, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Vladimir Zapolskiy
Cc: Bryan O'Donoghue, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Satya Priya Kakitapalli, Ajit Pandey,
Imran Shaik
On 30/04/2024 15:27, Jagadeesh Kona wrote:
> Fix the incorrect order of SC8280XP camcc header file in SM8450 camcc
> bindings.
>
> Fixes: 206cd759fbd2 ("dt-bindings: clock: Add SC8280XP CAMCC")
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> ---
> Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
> index fa0e5b6b02b8..bf23e25d71f5 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
> @@ -14,9 +14,9 @@ description: |
> domains on SM8450.
>
> See also::
> + include/dt-bindings/clock/qcom,sc8280xp-camcc.h
> include/dt-bindings/clock/qcom,sm8450-camcc.h
> include/dt-bindings/clock/qcom,sm8550-camcc.h
> - include/dt-bindings/clock/qcom,sc8280xp-camcc.h
> include/dt-bindings/clock/qcom,x1e80100-camcc.h
>
> allOf:
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH V3 2/8] dt-bindings: clock: qcom: Add SM8650 video clock controller
2024-04-30 14:27 5% ` [PATCH V3 2/8] dt-bindings: clock: qcom: Add SM8650 video clock controller Jagadeesh Kona
@ 2024-05-01 10:41 0% ` Bryan O'Donoghue
0 siblings, 0 replies; 200+ results
From: Bryan O'Donoghue @ 2024-05-01 10:41 UTC (permalink / raw)
To: Jagadeesh Kona, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Vladimir Zapolskiy
Cc: Bryan O'Donoghue, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Satya Priya Kakitapalli, Ajit Pandey,
Imran Shaik
On 30/04/2024 15:27, Jagadeesh Kona wrote:
> SM8650 video clock controller has most clocks same as SM8450,
> but it also has few additional clocks and resets. Add device tree
> bindings for the video clock controller on Qualcomm SM8650 platform
> by defining these additional clocks and resets on top of SM8450.
>
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> ---
> .../bindings/clock/qcom,sm8450-videocc.yaml | 6 ++++-
> .../dt-bindings/clock/qcom,sm8650-videocc.h | 23 +++++++++++++++++++
> 2 files changed, 28 insertions(+), 1 deletion(-)
> create mode 100644 include/dt-bindings/clock/qcom,sm8650-videocc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
> index 78a1bb5be878..922e95c61778 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
> @@ -8,18 +8,22 @@ title: Qualcomm Video Clock & Reset Controller on SM8450
>
> maintainers:
> - Taniya Das <quic_tdas@quicinc.com>
> + - Jagadeesh Kona <quic_jkona@quicinc.com>
>
> description: |
> Qualcomm video clock control module provides the clocks, resets and power
> domains on SM8450.
>
> - See also:: include/dt-bindings/clock/qcom,sm8450-videocc.h
> + See also::
> + include/dt-bindings/clock/qcom,sm8450-videocc.h
> + include/dt-bindings/clock/qcom,sm8650-videocc.h
>
> properties:
> compatible:
> enum:
> - qcom,sm8450-videocc
> - qcom,sm8550-videocc
> + - qcom,sm8650-videocc
>
> reg:
> maxItems: 1
> diff --git a/include/dt-bindings/clock/qcom,sm8650-videocc.h b/include/dt-bindings/clock/qcom,sm8650-videocc.h
> new file mode 100644
> index 000000000000..4e3c2d87280f
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,sm8650-videocc.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H
> +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H
> +
> +#include "qcom,sm8450-videocc.h"
> +
> +/* SM8650 introduces below new clocks and resets compared to SM8450 */
> +
> +/* VIDEO_CC clocks */
> +#define VIDEO_CC_MVS0_SHIFT_CLK 12
> +#define VIDEO_CC_MVS0C_SHIFT_CLK 13
> +#define VIDEO_CC_MVS1_SHIFT_CLK 14
> +#define VIDEO_CC_MVS1C_SHIFT_CLK 15
> +#define VIDEO_CC_XO_CLK_SRC 16
> +
> +/* VIDEO_CC resets */
> +#define VIDEO_CC_XO_CLK_ARES 7
> +
> +#endif
Extensibility +1
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH V3 5/8] dt-bindings: clock: qcom: Fix the incorrect order of SC8280XP camcc header
2024-04-30 14:27 5% ` [PATCH V3 5/8] dt-bindings: clock: qcom: Fix the incorrect order of SC8280XP camcc header Jagadeesh Kona
@ 2024-05-01 6:43 0% ` Johan Hovold
2024-05-02 11:09 0% ` Jagadeesh Kona
2024-05-01 10:42 0% ` Bryan O'Donoghue
1 sibling, 1 reply; 200+ results
From: Johan Hovold @ 2024-05-01 6:43 UTC (permalink / raw)
To: Jagadeesh Kona
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Vladimir Zapolskiy, Bryan O'Donoghue, linux-arm-msm,
linux-clk, devicetree, linux-kernel, Taniya Das,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik
On Tue, Apr 30, 2024 at 07:57:54PM +0530, Jagadeesh Kona wrote:
> Fix the incorrect order of SC8280XP camcc header file in SM8450 camcc
> bindings.
Try to avoid using the word "fix" in the commit summary (Subject) and
commit message for things like this which are essentially cleanups to
avoid making it sound like a bug fix (which automated tooling may then
select for backporting).
> Fixes: 206cd759fbd2 ("dt-bindings: clock: Add SC8280XP CAMCC")
Also drop the Fixes tag as this is not a bug fix.
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> ---
> Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
> index fa0e5b6b02b8..bf23e25d71f5 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
> @@ -14,9 +14,9 @@ description: |
> domains on SM8450.
>
> See also::
> + include/dt-bindings/clock/qcom,sc8280xp-camcc.h
> include/dt-bindings/clock/qcom,sm8450-camcc.h
> include/dt-bindings/clock/qcom,sm8550-camcc.h
> - include/dt-bindings/clock/qcom,sc8280xp-camcc.h
> include/dt-bindings/clock/qcom,x1e80100-camcc.h
Johan
^ permalink raw reply [relevance 0%]
* Re: [PATCH v9 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs
@ 2024-04-30 17:59 0% ` Dmitry Baryshkov
0 siblings, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-30 17:59 UTC (permalink / raw)
To: Bibek Kumar Patro, Rob Clark, robin.murphy, will
Cc: joro, konrad.dybcio, jsnitsel, quic_bjorande, mani, quic_eberman,
robdclark, u.kleine-koenig, robh, vladimir.oltean, quic_pkondeti,
quic_molvera, linux-arm-msm, linux-arm-kernel, iommu,
linux-kernel
On Tue, 23 Jan 2024 at 16:46, Bibek Kumar Patro
<quic_bibekkum@quicinc.com> wrote:
>
> This patch series consist of five parts and covers the following:
>
> 1. Re-enable context caching for Qualcomm SoCs to retain prefetcher
> settings during reset and runtime suspend.
>
> 2. Remove cfg inside qcom_smmu structure and replace it with single
> pointer to qcom_smmu_match_data avoiding replication of multiple
> members from same.
>
> 3. Introduce intital set of driver changes to implement ACTLR register
> for custom prefetcher settings in Qualcomm SoCs.
>
> 4. Add ACTLR data and implementation operations for SM8550.
>
> 5. Add ACTLR data and implementation operations for SC7280.
Colleagues, just wanted to check, what happened to this series?
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v9 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs
@ 2024-04-30 17:59 0% ` Dmitry Baryshkov
0 siblings, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-30 17:59 UTC (permalink / raw)
To: Bibek Kumar Patro, Rob Clark, robin.murphy, will
Cc: joro, konrad.dybcio, jsnitsel, quic_bjorande, mani, quic_eberman,
robdclark, u.kleine-koenig, robh, vladimir.oltean, quic_pkondeti,
quic_molvera, linux-arm-msm, linux-arm-kernel, iommu,
linux-kernel
On Tue, 23 Jan 2024 at 16:46, Bibek Kumar Patro
<quic_bibekkum@quicinc.com> wrote:
>
> This patch series consist of five parts and covers the following:
>
> 1. Re-enable context caching for Qualcomm SoCs to retain prefetcher
> settings during reset and runtime suspend.
>
> 2. Remove cfg inside qcom_smmu structure and replace it with single
> pointer to qcom_smmu_match_data avoiding replication of multiple
> members from same.
>
> 3. Introduce intital set of driver changes to implement ACTLR register
> for custom prefetcher settings in Qualcomm SoCs.
>
> 4. Add ACTLR data and implementation operations for SM8550.
>
> 5. Add ACTLR data and implementation operations for SC7280.
Colleagues, just wanted to check, what happened to this series?
--
With best wishes
Dmitry
^ permalink raw reply [relevance 0%]
* [PATCH V3 7/8] clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver
2024-04-30 14:27 6% [PATCH V3 0/8] Add support for videocc and camcc on SM8650 Jagadeesh Kona
` (4 preceding siblings ...)
2024-04-30 14:27 5% ` [PATCH V3 6/8] dt-bindings: clock: qcom: Add SM8650 camera clock controller Jagadeesh Kona
@ 2024-04-30 14:27 1% ` Jagadeesh Kona
5 siblings, 0 replies; 200+ results
From: Jagadeesh Kona @ 2024-04-30 14:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Vladimir Zapolskiy
Cc: Bryan O'Donoghue, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Jagadeesh Kona,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik,
Dmitry Baryshkov
Add support for the camera clock controller for camera clients to
be able to request for camcc clocks on SM8650 platform.
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Tested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/camcc-sm8650.c | 3591 +++++++++++++++++++++++++++++++
3 files changed, 3600 insertions(+)
create mode 100644 drivers/clk/qcom/camcc-sm8650.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 1bb51a058872..46369edfc07a 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -827,6 +827,14 @@ config SM_CAMCC_8550
Support for the camera clock controller on SM8550 devices.
Say Y if you want to support camera devices and camera functionality.
+config SM_CAMCC_8650
+ tristate "SM8650 Camera Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ select SM_GCC_8650
+ help
+ Support for the camera clock controller on SM8650 devices.
+ Say Y if you want to support camera devices and camera functionality.
+
config SM_DISPCC_6115
tristate "SM6115 Display Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index dec5b6db6860..28bffa1eb8dd 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -109,6 +109,7 @@ obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
+obj-$(CONFIG_SM_CAMCC_8650) += camcc-sm8650.o
obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
diff --git a/drivers/clk/qcom/camcc-sm8650.c b/drivers/clk/qcom/camcc-sm8650.c
new file mode 100644
index 000000000000..1b28e086e519
--- /dev/null
+++ b/drivers/clk/qcom/camcc-sm8650.c
@@ -0,0 +1,3591 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,sm8650-camcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ DT_IFACE,
+ DT_BI_TCXO,
+ DT_BI_TCXO_AO,
+ DT_SLEEP_CLK,
+};
+
+enum {
+ P_BI_TCXO,
+ P_BI_TCXO_AO,
+ P_CAM_CC_PLL0_OUT_EVEN,
+ P_CAM_CC_PLL0_OUT_MAIN,
+ P_CAM_CC_PLL0_OUT_ODD,
+ P_CAM_CC_PLL1_OUT_EVEN,
+ P_CAM_CC_PLL2_OUT_EVEN,
+ P_CAM_CC_PLL2_OUT_MAIN,
+ P_CAM_CC_PLL3_OUT_EVEN,
+ P_CAM_CC_PLL4_OUT_EVEN,
+ P_CAM_CC_PLL5_OUT_EVEN,
+ P_CAM_CC_PLL6_OUT_EVEN,
+ P_CAM_CC_PLL7_OUT_EVEN,
+ P_CAM_CC_PLL8_OUT_EVEN,
+ P_CAM_CC_PLL9_OUT_EVEN,
+ P_CAM_CC_PLL9_OUT_ODD,
+ P_CAM_CC_PLL10_OUT_EVEN,
+ P_SLEEP_CLK,
+};
+
+static const struct pll_vco lucid_ole_vco[] = {
+ { 249600000, 2300000000, 0 },
+};
+
+static const struct pll_vco rivian_ole_vco[] = {
+ { 777000000, 1285000000, 0 },
+};
+
+static const struct alpha_pll_config cam_cc_pll0_config = {
+ .l = 0x3e,
+ .alpha = 0x8000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00008400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll0 = {
+ .offset = 0x0,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll0",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
+ .offset = 0x0,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll0_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll0_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
+ { 0x2, 3 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
+ .offset = 0x0,
+ .post_div_shift = 14,
+ .post_div_table = post_div_table_cam_cc_pll0_out_odd,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll0_out_odd",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll1_config = {
+ .l = 0x31,
+ .alpha = 0x7aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll1 = {
+ .offset = 0x1000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll1",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
+ .offset = 0x1000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll1_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll1_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll1.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll2_config = {
+ .l = 0x32,
+ .alpha = 0x0,
+ .config_ctl_val = 0x10000030,
+ .config_ctl_hi_val = 0x80890263,
+ .config_ctl_hi1_val = 0x00000217,
+ .user_ctl_val = 0x00000001,
+ .user_ctl_hi_val = 0x00000000,
+};
+
+static struct clk_alpha_pll cam_cc_pll2 = {
+ .offset = 0x2000,
+ .vco_table = rivian_ole_vco,
+ .num_vco = ARRAY_SIZE(rivian_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll2",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_rivian_evo_ops,
+ },
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll3_config = {
+ .l = 0x30,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll3 = {
+ .offset = 0x3000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll3",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
+ .offset = 0x3000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll3_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll3_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll3.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll4_config = {
+ .l = 0x30,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll4 = {
+ .offset = 0x4000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll4",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
+ .offset = 0x4000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll4_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll4_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll4.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll5_config = {
+ .l = 0x30,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll5 = {
+ .offset = 0x5000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll5",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
+ .offset = 0x5000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll5_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll5_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll5.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll6_config = {
+ .l = 0x30,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll6 = {
+ .offset = 0x6000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll6",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
+ .offset = 0x6000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll6_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll6_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll6.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll7_config = {
+ .l = 0x30,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll7 = {
+ .offset = 0x7000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll7",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
+ .offset = 0x7000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll7_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll7_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll7.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll8_config = {
+ .l = 0x14,
+ .alpha = 0xd555,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll8 = {
+ .offset = 0x8000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll8",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
+ .offset = 0x8000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll8_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll8_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll8.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll9_config = {
+ .l = 0x32,
+ .alpha = 0x0,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00008400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll9 = {
+ .offset = 0x9000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll9",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll9_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll9_out_even = {
+ .offset = 0x9000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll9_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll9_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll9.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll9_out_odd[] = {
+ { 0x2, 3 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll9_out_odd = {
+ .offset = 0x9000,
+ .post_div_shift = 14,
+ .post_div_table = post_div_table_cam_cc_pll9_out_odd,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_odd),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll9_out_odd",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll9.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll10_config = {
+ .l = 0x30,
+ .alpha = 0x8aaa,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x82aa299c,
+ .test_ctl_val = 0x00000000,
+ .test_ctl_hi_val = 0x00000003,
+ .test_ctl_hi1_val = 0x00009000,
+ .test_ctl_hi2_val = 0x00000034,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000005,
+};
+
+static struct clk_alpha_pll cam_cc_pll10 = {
+ .offset = 0xa000,
+ .vco_table = lucid_ole_vco,
+ .num_vco = ARRAY_SIZE(lucid_ole_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll10",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll10_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll10_out_even = {
+ .offset = 0xa000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_cam_cc_pll10_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll10_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_pll10_out_even",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_pll10.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+ },
+};
+
+static const struct parent_map cam_cc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL0_OUT_MAIN, 1 },
+ { P_CAM_CC_PLL0_OUT_EVEN, 2 },
+ { P_CAM_CC_PLL0_OUT_ODD, 3 },
+ { P_CAM_CC_PLL9_OUT_ODD, 4 },
+ { P_CAM_CC_PLL9_OUT_EVEN, 5 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll0.clkr.hw },
+ { .hw = &cam_cc_pll0_out_even.clkr.hw },
+ { .hw = &cam_cc_pll0_out_odd.clkr.hw },
+ { .hw = &cam_cc_pll9_out_odd.clkr.hw },
+ { .hw = &cam_cc_pll9_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL2_OUT_EVEN, 3 },
+ { P_CAM_CC_PLL2_OUT_MAIN, 5 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_1[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll2.clkr.hw },
+ { .hw = &cam_cc_pll2.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL8_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_2[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll8_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL3_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_3[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll3_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_4[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL4_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_4[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll4_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_5[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL5_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_5[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll5_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_6[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL1_OUT_EVEN, 4 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_6[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll1_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_7[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL6_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_7[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll6_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_8[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL7_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_8[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll7_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_9[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL10_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_9[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &cam_cc_pll10_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_10[] = {
+ { P_SLEEP_CLK, 0 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_10[] = {
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map cam_cc_parent_map_11_ao[] = {
+ { P_BI_TCXO_AO, 0 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_11_ao[] = {
+ { .index = DT_BI_TCXO_AO },
+};
+
+static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
+ F(400000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
+ F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_bps_clk_src = {
+ .cmd_rcgr = 0x10050,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_2,
+ .freq_tbl = ftbl_cam_cc_bps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_bps_clk_src",
+ .parent_data = cam_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = {
+ F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = {
+ .cmd_rcgr = 0x1325c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_camnoc_axi_rt_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_cci_0_clk_src = {
+ .cmd_rcgr = 0x131cc,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cci_0_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_cci_1_clk_src = {
+ .cmd_rcgr = 0x131e8,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cci_1_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_cci_2_clk_src = {
+ .cmd_rcgr = 0x13204,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cci_2_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
+ F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
+ .cmd_rcgr = 0x1104c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cphy_rx_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = {
+ F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
+ F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_cre_clk_src = {
+ .cmd_rcgr = 0x13144,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cre_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cre_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
+ .cmd_rcgr = 0x150e0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi0phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
+ .cmd_rcgr = 0x15104,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi1phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
+ .cmd_rcgr = 0x15124,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi2phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
+ .cmd_rcgr = 0x15144,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi3phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
+ .cmd_rcgr = 0x15164,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi4phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
+ .cmd_rcgr = 0x15184,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi5phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi6phytimer_clk_src = {
+ .cmd_rcgr = 0x151a4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi6phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi7phytimer_clk_src = {
+ .cmd_rcgr = 0x151c4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi7phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
+ F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
+ F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_csid_clk_src = {
+ .cmd_rcgr = 0x13238,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csid_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csid_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
+ .cmd_rcgr = 0x10018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_fast_ahb_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
+ F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_icp_clk_src = {
+ .cmd_rcgr = 0x131a4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_icp_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_icp_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(466000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_0_clk_src = {
+ .cmd_rcgr = 0x11018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_3,
+ .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_0_clk_src",
+ .parent_data = cam_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(466000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_1_clk_src = {
+ .cmd_rcgr = 0x12018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_4,
+ .freq_tbl = ftbl_cam_cc_ife_1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_1_clk_src",
+ .parent_data = cam_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(466000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_2_clk_src = {
+ .cmd_rcgr = 0x12068,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_5,
+ .freq_tbl = ftbl_cam_cc_ife_2_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_2_clk_src",
+ .parent_data = cam_cc_parent_data_5,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
+ .cmd_rcgr = 0x13000,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csid_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_lite_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
+ .cmd_rcgr = 0x13028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csid_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_lite_csid_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
+ F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
+ F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
+ F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
+ .cmd_rcgr = 0x10094,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_6,
+ .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_nps_clk_src",
+ .parent_data = cam_cc_parent_data_6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
+ F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_jpeg_clk_src = {
+ .cmd_rcgr = 0x13168,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_jpeg_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_jpeg_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 4),
+ F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_mclk0_clk_src = {
+ .cmd_rcgr = 0x15000,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk0_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk1_clk_src = {
+ .cmd_rcgr = 0x1501c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk1_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk2_clk_src = {
+ .cmd_rcgr = 0x15038,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk2_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk3_clk_src = {
+ .cmd_rcgr = 0x15054,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk3_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk4_clk_src = {
+ .cmd_rcgr = 0x15070,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk4_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk5_clk_src = {
+ .cmd_rcgr = 0x1508c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk5_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk6_clk_src = {
+ .cmd_rcgr = 0x150a8,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk6_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk7_clk_src = {
+ .cmd_rcgr = 0x150c4,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk7_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
+ F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
+ F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
+ .cmd_rcgr = 0x1329c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_qdss_debug_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
+ F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
+ .cmd_rcgr = 0x1306c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_7,
+ .freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_0_clk_src",
+ .parent_data = cam_cc_parent_data_7,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
+ F(466000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
+ .cmd_rcgr = 0x130bc,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_8,
+ .freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_1_clk_src",
+ .parent_data = cam_cc_parent_data_8,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_sfe_2_clk_src[] = {
+ F(466000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
+ F(594000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
+ F(675000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
+ F(785000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_sfe_2_clk_src = {
+ .cmd_rcgr = 0x1310c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_9,
+ .freq_tbl = ftbl_cam_cc_sfe_2_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_2_clk_src",
+ .parent_data = cam_cc_parent_data_9,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_9),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
+ F(32000, P_SLEEP_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_sleep_clk_src = {
+ .cmd_rcgr = 0x132f0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_10,
+ .freq_tbl = ftbl_cam_cc_sleep_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sleep_clk_src",
+ .parent_data = cam_cc_parent_data_10,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_10),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
+ .cmd_rcgr = 0x10034,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_slow_ahb_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
+ F(19200000, P_BI_TCXO_AO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_xo_clk_src = {
+ .cmd_rcgr = 0x132d4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_11_ao,
+ .freq_tbl = ftbl_cam_cc_xo_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_xo_clk_src",
+ .parent_data = cam_cc_parent_data_11_ao,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_11_ao),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_branch cam_cc_bps_ahb_clk = {
+ .halt_reg = 0x1004c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1004c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_bps_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_bps_clk = {
+ .halt_reg = 0x10068,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_bps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_bps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_bps_fast_ahb_clk = {
+ .halt_reg = 0x10030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_bps_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_bps_shift_clk = {
+ .halt_reg = 0x10078,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x10078,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_bps_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_camnoc_axi_nrt_clk = {
+ .halt_reg = 0x13284,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13284,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_camnoc_axi_nrt_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_camnoc_axi_rt_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_camnoc_axi_rt_clk = {
+ .halt_reg = 0x13274,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13274,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_camnoc_axi_rt_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_camnoc_axi_rt_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
+ .halt_reg = 0x13290,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13290,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_camnoc_dcd_xo_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_camnoc_xo_clk = {
+ .halt_reg = 0x13294,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13294,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_camnoc_xo_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cci_0_clk = {
+ .halt_reg = 0x131e4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x131e4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cci_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cci_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cci_1_clk = {
+ .halt_reg = 0x13200,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13200,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cci_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cci_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cci_2_clk = {
+ .halt_reg = 0x1321c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1321c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cci_2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cci_2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_core_ahb_clk = {
+ .halt_reg = 0x132d0,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x132d0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_core_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ahb_clk = {
+ .halt_reg = 0x13220,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13220,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_bps_clk = {
+ .halt_reg = 0x10074,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10074,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_bps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_bps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_cre_clk = {
+ .halt_reg = 0x13160,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13160,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_cre_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cre_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
+ .halt_reg = 0x1322c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1322c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ife_0_clk = {
+ .halt_reg = 0x1103c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1103c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_ife_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ife_1_clk = {
+ .halt_reg = 0x1203c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1203c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_ife_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ife_2_clk = {
+ .halt_reg = 0x1208c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1208c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_ife_2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ife_lite_clk = {
+ .halt_reg = 0x13024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_ife_lite_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_lite_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
+ .halt_reg = 0x100b8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x100b8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_ipe_nps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ipe_nps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_sbi_clk = {
+ .halt_reg = 0x10104,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10104,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_sbi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_sfe_0_clk = {
+ .halt_reg = 0x13090,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13090,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_sfe_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_sfe_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_sfe_1_clk = {
+ .halt_reg = 0x130e0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x130e0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_sfe_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_sfe_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_sfe_2_clk = {
+ .halt_reg = 0x13130,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13130,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cpas_sfe_2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_sfe_2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cre_ahb_clk = {
+ .halt_reg = 0x13164,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13164,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cre_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cre_clk = {
+ .halt_reg = 0x1315c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1315c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_cre_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cre_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi0phytimer_clk = {
+ .halt_reg = 0x150f8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x150f8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi0phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi0phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi1phytimer_clk = {
+ .halt_reg = 0x1511c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1511c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi1phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi1phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi2phytimer_clk = {
+ .halt_reg = 0x1513c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1513c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi2phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi2phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi3phytimer_clk = {
+ .halt_reg = 0x1515c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1515c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi3phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi3phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi4phytimer_clk = {
+ .halt_reg = 0x1517c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1517c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi4phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi4phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi5phytimer_clk = {
+ .halt_reg = 0x1519c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1519c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi5phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi5phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi6phytimer_clk = {
+ .halt_reg = 0x151bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x151bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi6phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi6phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi7phytimer_clk = {
+ .halt_reg = 0x151dc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x151dc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csi7phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csi7phytimer_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csid_clk = {
+ .halt_reg = 0x13250,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13250,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csid_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_csid_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
+ .halt_reg = 0x15100,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15100,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csid_csiphy_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy0_clk = {
+ .halt_reg = 0x150fc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x150fc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy1_clk = {
+ .halt_reg = 0x15120,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15120,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy2_clk = {
+ .halt_reg = 0x15140,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15140,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy3_clk = {
+ .halt_reg = 0x15160,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15160,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy4_clk = {
+ .halt_reg = 0x15180,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15180,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy4_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy5_clk = {
+ .halt_reg = 0x151a0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x151a0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy5_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy6_clk = {
+ .halt_reg = 0x151c0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x151c0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy6_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy7_clk = {
+ .halt_reg = 0x151e0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x151e0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_csiphy7_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_icp_ahb_clk = {
+ .halt_reg = 0x131c8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x131c8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_icp_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_icp_clk = {
+ .halt_reg = 0x131bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x131bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_icp_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_icp_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_clk = {
+ .halt_reg = 0x11030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x11030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
+ .halt_reg = 0x11048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x11048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_0_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_shift_clk = {
+ .halt_reg = 0x11064,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x11064,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_0_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_clk = {
+ .halt_reg = 0x12030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
+ .halt_reg = 0x12048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_1_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_shift_clk = {
+ .halt_reg = 0x1204c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1204c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_1_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_2_clk = {
+ .halt_reg = 0x12080,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12080,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
+ .halt_reg = 0x12098,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12098,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_2_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_2_shift_clk = {
+ .halt_reg = 0x1209c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1209c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_2_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_ahb_clk = {
+ .halt_reg = 0x13050,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13050,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_lite_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_clk = {
+ .halt_reg = 0x13018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_lite_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_lite_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
+ .halt_reg = 0x1304c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1304c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_lite_cphy_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_cphy_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_csid_clk = {
+ .halt_reg = 0x13040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ife_lite_csid_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_lite_csid_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
+ .halt_reg = 0x100d0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x100d0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_nps_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_slow_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_nps_clk = {
+ .halt_reg = 0x100ac,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x100ac,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_nps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ipe_nps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
+ .halt_reg = 0x100d4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x100d4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_nps_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_pps_clk = {
+ .halt_reg = 0x100bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x100bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_pps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ipe_nps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
+ .halt_reg = 0x100d8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x100d8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_pps_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_shift_clk = {
+ .halt_reg = 0x100dc,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x100dc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_ipe_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_jpeg_1_clk = {
+ .halt_reg = 0x1318c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1318c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_jpeg_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_jpeg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_jpeg_clk = {
+ .halt_reg = 0x13180,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13180,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_jpeg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_jpeg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk0_clk = {
+ .halt_reg = 0x15018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk1_clk = {
+ .halt_reg = 0x15034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15034,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk2_clk = {
+ .halt_reg = 0x15050,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15050,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk3_clk = {
+ .halt_reg = 0x1506c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1506c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk4_clk = {
+ .halt_reg = 0x15088,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x15088,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk4_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk4_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk5_clk = {
+ .halt_reg = 0x150a4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x150a4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk5_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk5_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk6_clk = {
+ .halt_reg = 0x150c0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x150c0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk6_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk6_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk7_clk = {
+ .halt_reg = 0x150dc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x150dc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_mclk7_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_mclk7_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_qdss_debug_clk = {
+ .halt_reg = 0x132b4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x132b4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_qdss_debug_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_qdss_debug_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_qdss_debug_xo_clk = {
+ .halt_reg = 0x132b8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x132b8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_qdss_debug_xo_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sbi_clk = {
+ .halt_reg = 0x100f8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x100f8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sbi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_ife_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sbi_fast_ahb_clk = {
+ .halt_reg = 0x10108,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10108,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sbi_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sbi_shift_clk = {
+ .halt_reg = 0x1010c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1010c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sbi_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_0_clk = {
+ .halt_reg = 0x13084,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13084,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_sfe_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
+ .halt_reg = 0x1309c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1309c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_0_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_0_shift_clk = {
+ .halt_reg = 0x130a0,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x130a0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_0_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_1_clk = {
+ .halt_reg = 0x130d4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x130d4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_sfe_1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
+ .halt_reg = 0x130ec,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x130ec,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_1_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_1_shift_clk = {
+ .halt_reg = 0x130f0,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x130f0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_1_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_2_clk = {
+ .halt_reg = 0x13124,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13124,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_sfe_2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_2_fast_ahb_clk = {
+ .halt_reg = 0x1313c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1313c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_2_fast_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_fast_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sfe_2_shift_clk = {
+ .halt_reg = 0x13140,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x13140,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_sfe_2_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_titan_top_shift_clk = {
+ .halt_reg = 0x1330c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1330c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "cam_cc_titan_top_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cam_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc cam_cc_titan_top_gdsc = {
+ .gdscr = 0x132bc,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_titan_top_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_bps_gdsc = {
+ .gdscr = 0x10004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_bps_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .parent = &cam_cc_titan_top_gdsc.pd,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_ife_0_gdsc = {
+ .gdscr = 0x11004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_ife_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .parent = &cam_cc_titan_top_gdsc.pd,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_ife_1_gdsc = {
+ .gdscr = 0x12004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_ife_1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .parent = &cam_cc_titan_top_gdsc.pd,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_ife_2_gdsc = {
+ .gdscr = 0x12054,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_ife_2_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .parent = &cam_cc_titan_top_gdsc.pd,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_ipe_0_gdsc = {
+ .gdscr = 0x10080,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_ipe_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .parent = &cam_cc_titan_top_gdsc.pd,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_sbi_gdsc = {
+ .gdscr = 0x100e4,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_sbi_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .parent = &cam_cc_titan_top_gdsc.pd,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_sfe_0_gdsc = {
+ .gdscr = 0x13058,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_sfe_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .parent = &cam_cc_titan_top_gdsc.pd,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_sfe_1_gdsc = {
+ .gdscr = 0x130a8,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_sfe_1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .parent = &cam_cc_titan_top_gdsc.pd,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc cam_cc_sfe_2_gdsc = {
+ .gdscr = 0x130f8,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "cam_cc_sfe_2_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .parent = &cam_cc_titan_top_gdsc.pd,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct clk_regmap *cam_cc_sm8650_clocks[] = {
+ [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
+ [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
+ [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
+ [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
+ [CAM_CC_BPS_SHIFT_CLK] = &cam_cc_bps_shift_clk.clkr,
+ [CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr,
+ [CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr,
+ [CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr,
+ [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
+ [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr,
+ [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
+ [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
+ [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
+ [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
+ [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr,
+ [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr,
+ [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
+ [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
+ [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
+ [CAM_CC_CPAS_CRE_CLK] = &cam_cc_cpas_cre_clk.clkr,
+ [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
+ [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
+ [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
+ [CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
+ [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
+ [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
+ [CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
+ [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
+ [CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
+ [CAM_CC_CPAS_SFE_2_CLK] = &cam_cc_cpas_sfe_2_clk.clkr,
+ [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
+ [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr,
+ [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr,
+ [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr,
+ [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
+ [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
+ [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
+ [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
+ [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
+ [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
+ [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
+ [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
+ [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
+ [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
+ [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
+ [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
+ [CAM_CC_CSI6PHYTIMER_CLK] = &cam_cc_csi6phytimer_clk.clkr,
+ [CAM_CC_CSI6PHYTIMER_CLK_SRC] = &cam_cc_csi6phytimer_clk_src.clkr,
+ [CAM_CC_CSI7PHYTIMER_CLK] = &cam_cc_csi7phytimer_clk.clkr,
+ [CAM_CC_CSI7PHYTIMER_CLK_SRC] = &cam_cc_csi7phytimer_clk_src.clkr,
+ [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
+ [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
+ [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
+ [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
+ [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
+ [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
+ [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
+ [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
+ [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
+ [CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr,
+ [CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr,
+ [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
+ [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
+ [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
+ [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
+ [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
+ [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
+ [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
+ [CAM_CC_IFE_0_SHIFT_CLK] = &cam_cc_ife_0_shift_clk.clkr,
+ [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
+ [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
+ [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
+ [CAM_CC_IFE_1_SHIFT_CLK] = &cam_cc_ife_1_shift_clk.clkr,
+ [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
+ [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
+ [CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
+ [CAM_CC_IFE_2_SHIFT_CLK] = &cam_cc_ife_2_shift_clk.clkr,
+ [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
+ [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
+ [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
+ [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
+ [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
+ [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
+ [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
+ [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
+ [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
+ [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
+ [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
+ [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
+ [CAM_CC_IPE_SHIFT_CLK] = &cam_cc_ipe_shift_clk.clkr,
+ [CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr,
+ [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
+ [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
+ [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
+ [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
+ [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
+ [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
+ [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
+ [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
+ [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
+ [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
+ [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
+ [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
+ [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
+ [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
+ [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
+ [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
+ [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
+ [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
+ [CAM_CC_PLL0] = &cam_cc_pll0.clkr,
+ [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
+ [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
+ [CAM_CC_PLL1] = &cam_cc_pll1.clkr,
+ [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
+ [CAM_CC_PLL2] = &cam_cc_pll2.clkr,
+ [CAM_CC_PLL3] = &cam_cc_pll3.clkr,
+ [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
+ [CAM_CC_PLL4] = &cam_cc_pll4.clkr,
+ [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
+ [CAM_CC_PLL5] = &cam_cc_pll5.clkr,
+ [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
+ [CAM_CC_PLL6] = &cam_cc_pll6.clkr,
+ [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
+ [CAM_CC_PLL7] = &cam_cc_pll7.clkr,
+ [CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
+ [CAM_CC_PLL8] = &cam_cc_pll8.clkr,
+ [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
+ [CAM_CC_PLL9] = &cam_cc_pll9.clkr,
+ [CAM_CC_PLL9_OUT_EVEN] = &cam_cc_pll9_out_even.clkr,
+ [CAM_CC_PLL9_OUT_ODD] = &cam_cc_pll9_out_odd.clkr,
+ [CAM_CC_PLL10] = &cam_cc_pll10.clkr,
+ [CAM_CC_PLL10_OUT_EVEN] = &cam_cc_pll10_out_even.clkr,
+ [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
+ [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
+ [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
+ [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
+ [CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr,
+ [CAM_CC_SBI_SHIFT_CLK] = &cam_cc_sbi_shift_clk.clkr,
+ [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
+ [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
+ [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
+ [CAM_CC_SFE_0_SHIFT_CLK] = &cam_cc_sfe_0_shift_clk.clkr,
+ [CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
+ [CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
+ [CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
+ [CAM_CC_SFE_1_SHIFT_CLK] = &cam_cc_sfe_1_shift_clk.clkr,
+ [CAM_CC_SFE_2_CLK] = &cam_cc_sfe_2_clk.clkr,
+ [CAM_CC_SFE_2_CLK_SRC] = &cam_cc_sfe_2_clk_src.clkr,
+ [CAM_CC_SFE_2_FAST_AHB_CLK] = &cam_cc_sfe_2_fast_ahb_clk.clkr,
+ [CAM_CC_SFE_2_SHIFT_CLK] = &cam_cc_sfe_2_shift_clk.clkr,
+ [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
+ [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
+ [CAM_CC_TITAN_TOP_SHIFT_CLK] = &cam_cc_titan_top_shift_clk.clkr,
+ [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
+};
+
+static struct gdsc *cam_cc_sm8650_gdscs[] = {
+ [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc,
+ [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc,
+ [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc,
+ [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc,
+ [CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc,
+ [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc,
+ [CAM_CC_SBI_GDSC] = &cam_cc_sbi_gdsc,
+ [CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc,
+ [CAM_CC_SFE_1_GDSC] = &cam_cc_sfe_1_gdsc,
+ [CAM_CC_SFE_2_GDSC] = &cam_cc_sfe_2_gdsc,
+};
+
+static const struct qcom_reset_map cam_cc_sm8650_resets[] = {
+ [CAM_CC_BPS_BCR] = { 0x10000 },
+ [CAM_CC_DRV_BCR] = { 0x13310 },
+ [CAM_CC_ICP_BCR] = { 0x131a0 },
+ [CAM_CC_IFE_0_BCR] = { 0x11000 },
+ [CAM_CC_IFE_1_BCR] = { 0x12000 },
+ [CAM_CC_IFE_2_BCR] = { 0x12050 },
+ [CAM_CC_IPE_0_BCR] = { 0x1007c },
+ [CAM_CC_QDSS_DEBUG_BCR] = { 0x13298 },
+ [CAM_CC_SBI_BCR] = { 0x100e0 },
+ [CAM_CC_SFE_0_BCR] = { 0x13054 },
+ [CAM_CC_SFE_1_BCR] = { 0x130a4 },
+ [CAM_CC_SFE_2_BCR] = { 0x130f4 },
+};
+
+static const struct regmap_config cam_cc_sm8650_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1603c,
+ .fast_io = true,
+};
+
+static struct qcom_cc_desc cam_cc_sm8650_desc = {
+ .config = &cam_cc_sm8650_regmap_config,
+ .clks = cam_cc_sm8650_clocks,
+ .num_clks = ARRAY_SIZE(cam_cc_sm8650_clocks),
+ .resets = cam_cc_sm8650_resets,
+ .num_resets = ARRAY_SIZE(cam_cc_sm8650_resets),
+ .gdscs = cam_cc_sm8650_gdscs,
+ .num_gdscs = ARRAY_SIZE(cam_cc_sm8650_gdscs),
+};
+
+static const struct of_device_id cam_cc_sm8650_match_table[] = {
+ { .compatible = "qcom,sm8650-camcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, cam_cc_sm8650_match_table);
+
+static int cam_cc_sm8650_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ int ret;
+
+ ret = devm_pm_runtime_enable(&pdev->dev);
+ if (ret)
+ return ret;
+
+ ret = pm_runtime_resume_and_get(&pdev->dev);
+ if (ret)
+ return ret;
+
+ regmap = qcom_cc_map(pdev, &cam_cc_sm8650_desc);
+ if (IS_ERR(regmap)) {
+ pm_runtime_put(&pdev->dev);
+ return PTR_ERR(regmap);
+ }
+
+ clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
+ clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
+ clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
+ clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
+ clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
+ clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
+ clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
+ clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
+ clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
+ clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config);
+ clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config);
+
+ /* Keep clocks always enabled */
+ qcom_branch_set_clk_en(regmap, 0x13318); /* CAM_CC_DRV_AHB_CLK */
+ qcom_branch_set_clk_en(regmap, 0x13314); /* CAM_CC_DRV_XO_CLK */
+ qcom_branch_set_clk_en(regmap, 0x132ec); /* CAM_CC_GDSC_CLK */
+ qcom_branch_set_clk_en(regmap, 0x13308); /* CAM_CC_SLEEP_CLK */
+
+ ret = qcom_cc_really_probe(pdev, &cam_cc_sm8650_desc, regmap);
+
+ pm_runtime_put(&pdev->dev);
+
+ return ret;
+}
+
+static struct platform_driver cam_cc_sm8650_driver = {
+ .probe = cam_cc_sm8650_probe,
+ .driver = {
+ .name = "camcc-sm8650",
+ .of_match_table = cam_cc_sm8650_match_table,
+ },
+};
+
+module_platform_driver(cam_cc_sm8650_driver);
+
+MODULE_DESCRIPTION("QTI CAMCC SM8650 Driver");
+MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related [relevance 1%]
* [PATCH V3 6/8] dt-bindings: clock: qcom: Add SM8650 camera clock controller
2024-04-30 14:27 6% [PATCH V3 0/8] Add support for videocc and camcc on SM8650 Jagadeesh Kona
` (3 preceding siblings ...)
2024-04-30 14:27 5% ` [PATCH V3 5/8] dt-bindings: clock: qcom: Fix the incorrect order of SC8280XP camcc header Jagadeesh Kona
@ 2024-04-30 14:27 5% ` Jagadeesh Kona
2024-04-30 14:27 1% ` [PATCH V3 7/8] clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver Jagadeesh Kona
5 siblings, 0 replies; 200+ results
From: Jagadeesh Kona @ 2024-04-30 14:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Vladimir Zapolskiy
Cc: Bryan O'Donoghue, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Jagadeesh Kona,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik,
Krzysztof Kozlowski
Add device tree bindings for the camera clock controller on
Qualcomm SM8650 platform.
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
.../bindings/clock/qcom,sm8450-camcc.yaml | 3 +
include/dt-bindings/clock/qcom,sm8650-camcc.h | 195 ++++++++++++++++++
2 files changed, 198 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,sm8650-camcc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
index bf23e25d71f5..abd414328495 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
@@ -8,6 +8,7 @@ title: Qualcomm Camera Clock & Reset Controller on SM8450
maintainers:
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
+ - Jagadeesh Kona <quic_jkona@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
@@ -17,6 +18,7 @@ description: |
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
+ include/dt-bindings/clock/qcom,sm8650-camcc.h
include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
@@ -28,6 +30,7 @@ properties:
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
+ - qcom,sm8650-camcc
- qcom,x1e80100-camcc
clocks:
diff --git a/include/dt-bindings/clock/qcom,sm8650-camcc.h b/include/dt-bindings/clock/qcom,sm8650-camcc.h
new file mode 100644
index 000000000000..df73bf35f4bf
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8650-camcc.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8650_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8650_H
+
+/* CAM_CC clocks */
+#define CAM_CC_BPS_AHB_CLK 0
+#define CAM_CC_BPS_CLK 1
+#define CAM_CC_BPS_CLK_SRC 2
+#define CAM_CC_BPS_FAST_AHB_CLK 3
+#define CAM_CC_BPS_SHIFT_CLK 4
+#define CAM_CC_CAMNOC_AXI_NRT_CLK 5
+#define CAM_CC_CAMNOC_AXI_RT_CLK 6
+#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 7
+#define CAM_CC_CAMNOC_DCD_XO_CLK 8
+#define CAM_CC_CAMNOC_XO_CLK 9
+#define CAM_CC_CCI_0_CLK 10
+#define CAM_CC_CCI_0_CLK_SRC 11
+#define CAM_CC_CCI_1_CLK 12
+#define CAM_CC_CCI_1_CLK_SRC 13
+#define CAM_CC_CCI_2_CLK 14
+#define CAM_CC_CCI_2_CLK_SRC 15
+#define CAM_CC_CORE_AHB_CLK 16
+#define CAM_CC_CPAS_AHB_CLK 17
+#define CAM_CC_CPAS_BPS_CLK 18
+#define CAM_CC_CPAS_CRE_CLK 19
+#define CAM_CC_CPAS_FAST_AHB_CLK 20
+#define CAM_CC_CPAS_IFE_0_CLK 21
+#define CAM_CC_CPAS_IFE_1_CLK 22
+#define CAM_CC_CPAS_IFE_2_CLK 23
+#define CAM_CC_CPAS_IFE_LITE_CLK 24
+#define CAM_CC_CPAS_IPE_NPS_CLK 25
+#define CAM_CC_CPAS_SBI_CLK 26
+#define CAM_CC_CPAS_SFE_0_CLK 27
+#define CAM_CC_CPAS_SFE_1_CLK 28
+#define CAM_CC_CPAS_SFE_2_CLK 29
+#define CAM_CC_CPHY_RX_CLK_SRC 30
+#define CAM_CC_CRE_AHB_CLK 31
+#define CAM_CC_CRE_CLK 32
+#define CAM_CC_CRE_CLK_SRC 33
+#define CAM_CC_CSI0PHYTIMER_CLK 34
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC 35
+#define CAM_CC_CSI1PHYTIMER_CLK 36
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC 37
+#define CAM_CC_CSI2PHYTIMER_CLK 38
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC 39
+#define CAM_CC_CSI3PHYTIMER_CLK 40
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC 41
+#define CAM_CC_CSI4PHYTIMER_CLK 42
+#define CAM_CC_CSI4PHYTIMER_CLK_SRC 43
+#define CAM_CC_CSI5PHYTIMER_CLK 44
+#define CAM_CC_CSI5PHYTIMER_CLK_SRC 45
+#define CAM_CC_CSI6PHYTIMER_CLK 46
+#define CAM_CC_CSI6PHYTIMER_CLK_SRC 47
+#define CAM_CC_CSI7PHYTIMER_CLK 48
+#define CAM_CC_CSI7PHYTIMER_CLK_SRC 49
+#define CAM_CC_CSID_CLK 50
+#define CAM_CC_CSID_CLK_SRC 51
+#define CAM_CC_CSID_CSIPHY_RX_CLK 52
+#define CAM_CC_CSIPHY0_CLK 53
+#define CAM_CC_CSIPHY1_CLK 54
+#define CAM_CC_CSIPHY2_CLK 55
+#define CAM_CC_CSIPHY3_CLK 56
+#define CAM_CC_CSIPHY4_CLK 57
+#define CAM_CC_CSIPHY5_CLK 58
+#define CAM_CC_CSIPHY6_CLK 59
+#define CAM_CC_CSIPHY7_CLK 60
+#define CAM_CC_DRV_AHB_CLK 61
+#define CAM_CC_DRV_XO_CLK 62
+#define CAM_CC_FAST_AHB_CLK_SRC 63
+#define CAM_CC_GDSC_CLK 64
+#define CAM_CC_ICP_AHB_CLK 65
+#define CAM_CC_ICP_CLK 66
+#define CAM_CC_ICP_CLK_SRC 67
+#define CAM_CC_IFE_0_CLK 68
+#define CAM_CC_IFE_0_CLK_SRC 69
+#define CAM_CC_IFE_0_FAST_AHB_CLK 70
+#define CAM_CC_IFE_0_SHIFT_CLK 71
+#define CAM_CC_IFE_1_CLK 72
+#define CAM_CC_IFE_1_CLK_SRC 73
+#define CAM_CC_IFE_1_FAST_AHB_CLK 74
+#define CAM_CC_IFE_1_SHIFT_CLK 75
+#define CAM_CC_IFE_2_CLK 76
+#define CAM_CC_IFE_2_CLK_SRC 77
+#define CAM_CC_IFE_2_FAST_AHB_CLK 78
+#define CAM_CC_IFE_2_SHIFT_CLK 79
+#define CAM_CC_IFE_LITE_AHB_CLK 80
+#define CAM_CC_IFE_LITE_CLK 81
+#define CAM_CC_IFE_LITE_CLK_SRC 82
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83
+#define CAM_CC_IFE_LITE_CSID_CLK 84
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85
+#define CAM_CC_IPE_NPS_AHB_CLK 86
+#define CAM_CC_IPE_NPS_CLK 87
+#define CAM_CC_IPE_NPS_CLK_SRC 88
+#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89
+#define CAM_CC_IPE_PPS_CLK 90
+#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91
+#define CAM_CC_IPE_SHIFT_CLK 92
+#define CAM_CC_JPEG_1_CLK 93
+#define CAM_CC_JPEG_CLK 94
+#define CAM_CC_JPEG_CLK_SRC 95
+#define CAM_CC_MCLK0_CLK 96
+#define CAM_CC_MCLK0_CLK_SRC 97
+#define CAM_CC_MCLK1_CLK 98
+#define CAM_CC_MCLK1_CLK_SRC 99
+#define CAM_CC_MCLK2_CLK 100
+#define CAM_CC_MCLK2_CLK_SRC 101
+#define CAM_CC_MCLK3_CLK 102
+#define CAM_CC_MCLK3_CLK_SRC 103
+#define CAM_CC_MCLK4_CLK 104
+#define CAM_CC_MCLK4_CLK_SRC 105
+#define CAM_CC_MCLK5_CLK 106
+#define CAM_CC_MCLK5_CLK_SRC 107
+#define CAM_CC_MCLK6_CLK 108
+#define CAM_CC_MCLK6_CLK_SRC 109
+#define CAM_CC_MCLK7_CLK 110
+#define CAM_CC_MCLK7_CLK_SRC 111
+#define CAM_CC_PLL0 112
+#define CAM_CC_PLL0_OUT_EVEN 113
+#define CAM_CC_PLL0_OUT_ODD 114
+#define CAM_CC_PLL1 115
+#define CAM_CC_PLL1_OUT_EVEN 116
+#define CAM_CC_PLL2 117
+#define CAM_CC_PLL3 118
+#define CAM_CC_PLL3_OUT_EVEN 119
+#define CAM_CC_PLL4 120
+#define CAM_CC_PLL4_OUT_EVEN 121
+#define CAM_CC_PLL5 122
+#define CAM_CC_PLL5_OUT_EVEN 123
+#define CAM_CC_PLL6 124
+#define CAM_CC_PLL6_OUT_EVEN 125
+#define CAM_CC_PLL7 126
+#define CAM_CC_PLL7_OUT_EVEN 127
+#define CAM_CC_PLL8 128
+#define CAM_CC_PLL8_OUT_EVEN 129
+#define CAM_CC_PLL9 130
+#define CAM_CC_PLL9_OUT_EVEN 131
+#define CAM_CC_PLL9_OUT_ODD 132
+#define CAM_CC_PLL10 133
+#define CAM_CC_PLL10_OUT_EVEN 134
+#define CAM_CC_QDSS_DEBUG_CLK 135
+#define CAM_CC_QDSS_DEBUG_CLK_SRC 136
+#define CAM_CC_QDSS_DEBUG_XO_CLK 137
+#define CAM_CC_SBI_CLK 138
+#define CAM_CC_SBI_FAST_AHB_CLK 139
+#define CAM_CC_SBI_SHIFT_CLK 140
+#define CAM_CC_SFE_0_CLK 141
+#define CAM_CC_SFE_0_CLK_SRC 142
+#define CAM_CC_SFE_0_FAST_AHB_CLK 143
+#define CAM_CC_SFE_0_SHIFT_CLK 144
+#define CAM_CC_SFE_1_CLK 145
+#define CAM_CC_SFE_1_CLK_SRC 146
+#define CAM_CC_SFE_1_FAST_AHB_CLK 147
+#define CAM_CC_SFE_1_SHIFT_CLK 148
+#define CAM_CC_SFE_2_CLK 149
+#define CAM_CC_SFE_2_CLK_SRC 150
+#define CAM_CC_SFE_2_FAST_AHB_CLK 151
+#define CAM_CC_SFE_2_SHIFT_CLK 152
+#define CAM_CC_SLEEP_CLK 153
+#define CAM_CC_SLEEP_CLK_SRC 154
+#define CAM_CC_SLOW_AHB_CLK_SRC 155
+#define CAM_CC_TITAN_TOP_SHIFT_CLK 156
+#define CAM_CC_XO_CLK_SRC 157
+
+/* CAM_CC power domains */
+#define CAM_CC_TITAN_TOP_GDSC 0
+#define CAM_CC_BPS_GDSC 1
+#define CAM_CC_IFE_0_GDSC 2
+#define CAM_CC_IFE_1_GDSC 3
+#define CAM_CC_IFE_2_GDSC 4
+#define CAM_CC_IPE_0_GDSC 5
+#define CAM_CC_SBI_GDSC 6
+#define CAM_CC_SFE_0_GDSC 7
+#define CAM_CC_SFE_1_GDSC 8
+#define CAM_CC_SFE_2_GDSC 9
+
+/* CAM_CC resets */
+#define CAM_CC_BPS_BCR 0
+#define CAM_CC_DRV_BCR 1
+#define CAM_CC_ICP_BCR 2
+#define CAM_CC_IFE_0_BCR 3
+#define CAM_CC_IFE_1_BCR 4
+#define CAM_CC_IFE_2_BCR 5
+#define CAM_CC_IPE_0_BCR 6
+#define CAM_CC_QDSS_DEBUG_BCR 7
+#define CAM_CC_SBI_BCR 8
+#define CAM_CC_SFE_0_BCR 9
+#define CAM_CC_SFE_1_BCR 10
+#define CAM_CC_SFE_2_BCR 11
+
+#endif
--
2.43.0
^ permalink raw reply related [relevance 5%]
* [PATCH V3 5/8] dt-bindings: clock: qcom: Fix the incorrect order of SC8280XP camcc header
2024-04-30 14:27 6% [PATCH V3 0/8] Add support for videocc and camcc on SM8650 Jagadeesh Kona
` (2 preceding siblings ...)
2024-04-30 14:27 18% ` [PATCH V3 4/8] clk: qcom: videocc-sm8550: Add SM8650 video clock controller Jagadeesh Kona
@ 2024-04-30 14:27 5% ` Jagadeesh Kona
2024-05-01 6:43 0% ` Johan Hovold
2024-05-01 10:42 0% ` Bryan O'Donoghue
2024-04-30 14:27 5% ` [PATCH V3 6/8] dt-bindings: clock: qcom: Add SM8650 camera clock controller Jagadeesh Kona
2024-04-30 14:27 1% ` [PATCH V3 7/8] clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver Jagadeesh Kona
5 siblings, 2 replies; 200+ results
From: Jagadeesh Kona @ 2024-04-30 14:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Vladimir Zapolskiy
Cc: Bryan O'Donoghue, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Jagadeesh Kona,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik
Fix the incorrect order of SC8280XP camcc header file in SM8450 camcc
bindings.
Fixes: 206cd759fbd2 ("dt-bindings: clock: Add SC8280XP CAMCC")
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
index fa0e5b6b02b8..bf23e25d71f5 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
@@ -14,9 +14,9 @@ description: |
domains on SM8450.
See also::
+ include/dt-bindings/clock/qcom,sc8280xp-camcc.h
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
- include/dt-bindings/clock/qcom,sc8280xp-camcc.h
include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
--
2.43.0
^ permalink raw reply related [relevance 5%]
* [PATCH V3 4/8] clk: qcom: videocc-sm8550: Add SM8650 video clock controller
2024-04-30 14:27 6% [PATCH V3 0/8] Add support for videocc and camcc on SM8650 Jagadeesh Kona
2024-04-30 14:27 5% ` [PATCH V3 2/8] dt-bindings: clock: qcom: Add SM8650 video clock controller Jagadeesh Kona
2024-04-30 14:27 17% ` [PATCH V3 3/8] clk: qcom: videocc-sm8550: Add support for videocc XO clk ares Jagadeesh Kona
@ 2024-04-30 14:27 18% ` Jagadeesh Kona
2024-04-30 14:27 5% ` [PATCH V3 5/8] dt-bindings: clock: qcom: Fix the incorrect order of SC8280XP camcc header Jagadeesh Kona
` (2 subsequent siblings)
5 siblings, 0 replies; 200+ results
From: Jagadeesh Kona @ 2024-04-30 14:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Vladimir Zapolskiy
Cc: Bryan O'Donoghue, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Jagadeesh Kona,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik,
Dmitry Baryshkov
Add support to the SM8650 video clock controller by extending
the SM8550 video clock controller, which is mostly identical
but SM8650 has few additional clocks and minor differences.
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/videocc-sm8550.c | 153 +++++++++++++++++++++++++++++-
1 file changed, 149 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c
index 25133cf5a2b8..c601c35e6724 100644
--- a/drivers/clk/qcom/videocc-sm8550.c
+++ b/drivers/clk/qcom/videocc-sm8550.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
@@ -35,7 +35,7 @@ static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};
-static const struct alpha_pll_config video_cc_pll0_config = {
+static struct alpha_pll_config video_cc_pll0_config = {
.l = 0x25,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
@@ -66,7 +66,7 @@ static struct clk_alpha_pll video_cc_pll0 = {
},
};
-static const struct alpha_pll_config video_cc_pll1_config = {
+static struct alpha_pll_config video_cc_pll1_config = {
.l = 0x36,
.alpha = 0xb000,
.config_ctl_val = 0x20485699,
@@ -117,6 +117,14 @@ static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .hw = &video_cc_pll1.clkr.hw },
};
+static const struct parent_map video_cc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_2[] = {
+ { .index = DT_BI_TCXO },
+};
+
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
@@ -126,6 +134,16 @@ static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
{ }
};
+static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_sm8650[] = {
+ F(588000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ F(900000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1140000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
static struct clk_rcg2 video_cc_mvs0_clk_src = {
.cmd_rcgr = 0x8000,
.mnd_width = 0,
@@ -149,6 +167,15 @@ static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
{ }
};
+static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_sm8650[] = {
+ F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
+ F(1110000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
+ F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
+ F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
+ F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
static struct clk_rcg2 video_cc_mvs1_clk_src = {
.cmd_rcgr = 0x8018,
.mnd_width = 0,
@@ -164,6 +191,26 @@ static struct clk_rcg2 video_cc_mvs1_clk_src = {
},
};
+static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 video_cc_xo_clk_src = {
+ .cmd_rcgr = 0x810c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = video_cc_parent_map_2,
+ .freq_tbl = ftbl_video_cc_xo_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_xo_clk_src",
+ .parent_data = video_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(video_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
.reg = 0x80c4,
.shift = 0,
@@ -244,6 +291,26 @@ static struct clk_branch video_cc_mvs0_clk = {
},
};
+static struct clk_branch video_cc_mvs0_shift_clk = {
+ .halt_reg = 0x8128,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x8128,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x8128,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch video_cc_mvs0c_clk = {
.halt_reg = 0x8064,
.halt_check = BRANCH_HALT,
@@ -262,6 +329,26 @@ static struct clk_branch video_cc_mvs0c_clk = {
},
};
+static struct clk_branch video_cc_mvs0c_shift_clk = {
+ .halt_reg = 0x812c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x812c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x812c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0c_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch video_cc_mvs1_clk = {
.halt_reg = 0x80e0,
.halt_check = BRANCH_HALT_SKIP,
@@ -282,6 +369,26 @@ static struct clk_branch video_cc_mvs1_clk = {
},
};
+static struct clk_branch video_cc_mvs1_shift_clk = {
+ .halt_reg = 0x8130,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x8130,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x8130,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs1_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch video_cc_mvs1c_clk = {
.halt_reg = 0x8090,
.halt_check = BRANCH_HALT,
@@ -300,6 +407,26 @@ static struct clk_branch video_cc_mvs1c_clk = {
},
};
+static struct clk_branch video_cc_mvs1c_shift_clk = {
+ .halt_reg = 0x8134,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x8134,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x8134,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs1c_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct gdsc video_cc_mvs0c_gdsc = {
.gdscr = 0x804c,
.en_rest_wait_val = 0x2,
@@ -363,6 +490,7 @@ static struct clk_regmap *video_cc_sm8550_clocks[] = {
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
+ [VIDEO_CC_XO_CLK_SRC] = NULL,
};
static struct gdsc *video_cc_sm8550_gdscs[] = {
@@ -403,6 +531,7 @@ static struct qcom_cc_desc video_cc_sm8550_desc = {
static const struct of_device_id video_cc_sm8550_match_table[] = {
{ .compatible = "qcom,sm8550-videocc" },
+ { .compatible = "qcom,sm8650-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
@@ -411,6 +540,7 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
+ u32 sleep_clk_offset = 0x8140;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
@@ -426,12 +556,27 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
return PTR_ERR(regmap);
}
+ if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) {
+ sleep_clk_offset = 0x8150;
+ video_cc_pll0_config.l = 0x1e;
+ video_cc_pll0_config.alpha = 0xa000;
+ video_cc_pll1_config.l = 0x2b;
+ video_cc_pll1_config.alpha = 0xc000;
+ video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_sm8650;
+ video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_sm8650;
+ video_cc_sm8550_clocks[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr;
+ video_cc_sm8550_clocks[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr;
+ video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr;
+ video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr;
+ video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr;
+ }
+
clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */
- qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */
+ qcom_branch_set_clk_en(regmap, sleep_clk_offset); /* VIDEO_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */
ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
--
2.43.0
^ permalink raw reply related [relevance 18%]
* [PATCH V3 3/8] clk: qcom: videocc-sm8550: Add support for videocc XO clk ares
2024-04-30 14:27 6% [PATCH V3 0/8] Add support for videocc and camcc on SM8650 Jagadeesh Kona
2024-04-30 14:27 5% ` [PATCH V3 2/8] dt-bindings: clock: qcom: Add SM8650 video clock controller Jagadeesh Kona
@ 2024-04-30 14:27 17% ` Jagadeesh Kona
2024-04-30 14:27 18% ` [PATCH V3 4/8] clk: qcom: videocc-sm8550: Add SM8650 video clock controller Jagadeesh Kona
` (3 subsequent siblings)
5 siblings, 0 replies; 200+ results
From: Jagadeesh Kona @ 2024-04-30 14:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Vladimir Zapolskiy
Cc: Bryan O'Donoghue, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Jagadeesh Kona,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik,
Dmitry Baryshkov
Add support for videocc XO clk ares for consumer drivers to be
able to request this reset.
Fixes: f53153a37969 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550")
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/clk/qcom/videocc-sm8550.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c
index d73f747d2474..25133cf5a2b8 100644
--- a/drivers/clk/qcom/videocc-sm8550.c
+++ b/drivers/clk/qcom/videocc-sm8550.c
@@ -10,7 +10,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
-#include <dt-bindings/clock/qcom,sm8450-videocc.h>
+#include <dt-bindings/clock/qcom,sm8650-videocc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
@@ -380,6 +380,7 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = {
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
[VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 },
[VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 },
+ [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 },
};
static const struct regmap_config video_cc_sm8550_regmap_config = {
--
2.43.0
^ permalink raw reply related [relevance 17%]
* [PATCH V3 2/8] dt-bindings: clock: qcom: Add SM8650 video clock controller
2024-04-30 14:27 6% [PATCH V3 0/8] Add support for videocc and camcc on SM8650 Jagadeesh Kona
@ 2024-04-30 14:27 5% ` Jagadeesh Kona
2024-05-01 10:41 0% ` Bryan O'Donoghue
2024-04-30 14:27 17% ` [PATCH V3 3/8] clk: qcom: videocc-sm8550: Add support for videocc XO clk ares Jagadeesh Kona
` (4 subsequent siblings)
5 siblings, 1 reply; 200+ results
From: Jagadeesh Kona @ 2024-04-30 14:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Vladimir Zapolskiy
Cc: Bryan O'Donoghue, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Jagadeesh Kona,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik
SM8650 video clock controller has most clocks same as SM8450,
but it also has few additional clocks and resets. Add device tree
bindings for the video clock controller on Qualcomm SM8650 platform
by defining these additional clocks and resets on top of SM8450.
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
.../bindings/clock/qcom,sm8450-videocc.yaml | 6 ++++-
.../dt-bindings/clock/qcom,sm8650-videocc.h | 23 +++++++++++++++++++
2 files changed, 28 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/clock/qcom,sm8650-videocc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
index 78a1bb5be878..922e95c61778 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
@@ -8,18 +8,22 @@ title: Qualcomm Video Clock & Reset Controller on SM8450
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
+ - Jagadeesh Kona <quic_jkona@quicinc.com>
description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on SM8450.
- See also:: include/dt-bindings/clock/qcom,sm8450-videocc.h
+ See also::
+ include/dt-bindings/clock/qcom,sm8450-videocc.h
+ include/dt-bindings/clock/qcom,sm8650-videocc.h
properties:
compatible:
enum:
- qcom,sm8450-videocc
- qcom,sm8550-videocc
+ - qcom,sm8650-videocc
reg:
maxItems: 1
diff --git a/include/dt-bindings/clock/qcom,sm8650-videocc.h b/include/dt-bindings/clock/qcom,sm8650-videocc.h
new file mode 100644
index 000000000000..4e3c2d87280f
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8650-videocc.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H
+
+#include "qcom,sm8450-videocc.h"
+
+/* SM8650 introduces below new clocks and resets compared to SM8450 */
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_MVS0_SHIFT_CLK 12
+#define VIDEO_CC_MVS0C_SHIFT_CLK 13
+#define VIDEO_CC_MVS1_SHIFT_CLK 14
+#define VIDEO_CC_MVS1C_SHIFT_CLK 15
+#define VIDEO_CC_XO_CLK_SRC 16
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_XO_CLK_ARES 7
+
+#endif
--
2.43.0
^ permalink raw reply related [relevance 5%]
* [PATCH V3 0/8] Add support for videocc and camcc on SM8650
@ 2024-04-30 14:27 6% Jagadeesh Kona
2024-04-30 14:27 5% ` [PATCH V3 2/8] dt-bindings: clock: qcom: Add SM8650 video clock controller Jagadeesh Kona
` (5 more replies)
0 siblings, 6 replies; 200+ results
From: Jagadeesh Kona @ 2024-04-30 14:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Vladimir Zapolskiy
Cc: Bryan O'Donoghue, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Jagadeesh Kona,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik
Add support for video and camera clock controllers on Qualcomm SM8650
platform.
Changes in V3:
[PATCH 1/8]: Split incorrect header file name in SM8450 videocc bindings
into a separate patch and added fixes tag
[PATCH 2/8]: Added new header file for SM8650 videocc to define the extra clocks
and resets on top of SM8450 videocc bindings, Dropped Krzysztof
R-By tag due to these changes
[PATCH 3/8]: Updated SM8550 videocc driver to use new SM8650 videocc header file,
added Dmitry and Konrad R-By tags
[PATCH 4/8]: Updated offset variable name to sleep_clk_offset in probe and added
Dmitry R-By tag
[PATCH 5/8]: This patch is newly added to fix the incorrect order for SC8280XP
camcc header file in bindings
[PATCH 6/8]: Fixed the incorrect alphabetical order for SM8650 camcc compatible
and header files, added Krzysztof R-By tag and Vladimir Acked-By tags
[PATCH 7/8]: No changes, added R-By tags received till V2 series
[PATCH 8/8]: Dropped required-opps property in videocc and camcc nodes and
updated DT file to use new SM8650 videocc header file, added Vladimir R-By tag
Previous series:
V2 RESEND: https://lore.kernel.org/all/20240321092529.13362-1-quic_jkona@quicinc.com/
V2: https://lore.kernel.org/all/20240220135121.22578-1-quic_jkona@quicinc.com/
V1: https://lore.kernel.org/linux-kernel/20240206113145.31096-1-quic_jkona@quicinc.com/T/
Jagadeesh Kona (8):
dt-bindings: clock: qcom: Fix SM8450 videocc incorrect header file
name
dt-bindings: clock: qcom: Add SM8650 video clock controller
clk: qcom: videocc-sm8550: Add support for videocc XO clk ares
clk: qcom: videocc-sm8550: Add SM8650 video clock controller
dt-bindings: clock: qcom: Fix the incorrect order of SC8280XP camcc
header
dt-bindings: clock: qcom: Add SM8650 camera clock controller
clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver
arm64: dts: qcom: sm8650: Add video and camera clock controllers
.../bindings/clock/qcom,sm8450-camcc.yaml | 5 +-
.../bindings/clock/qcom,sm8450-videocc.yaml | 6 +-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 26 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/camcc-sm8650.c | 3591 +++++++++++++++++
drivers/clk/qcom/videocc-sm8550.c | 156 +-
include/dt-bindings/clock/qcom,sm8650-camcc.h | 195 +
.../dt-bindings/clock/qcom,sm8650-videocc.h | 23 +
9 files changed, 4004 insertions(+), 7 deletions(-)
create mode 100644 drivers/clk/qcom/camcc-sm8650.c
create mode 100644 include/dt-bindings/clock/qcom,sm8650-camcc.h
create mode 100644 include/dt-bindings/clock/qcom,sm8650-videocc.h
--
2.43.0
^ permalink raw reply [relevance 6%]
* Re: [PATCH] arm64: Properly clean up iommu-dma remnants
@ 2024-04-30 12:51 4% ` Konrad Dybcio
0 siblings, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-04-30 12:51 UTC (permalink / raw)
To: Robin Murphy, joro
Cc: will, catalin.marinas, linux-arm-kernel, iommu, Dmitry Baryshkov
On 30.04.2024 12:22 PM, Robin Murphy wrote:
> Thanks to the somewhat asymmetrical nature, while removing
> iommu_setup_dma_ops() from the arch_setup_dma_ops() flow, I managed to
> forget that arm64's teardown path was also specific to iommu-dma. Clean
> that up to match, otherwise probe deferral will lead to the arch code
> erroneously removing DMA ops set elsewhere.
>
> Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Link: https://lore.kernel.org/linux-iommu/Zi_LV28TR-P-PzXi@eriador.lumag.spb.ru/
> Fixes: b67483b3c44e ("iommu/dma: Centralise iommu_setup_dma_ops()")
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # QC SM8550 QRD
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [relevance 4%]
* Re: [PATCH] arm64: Properly clean up iommu-dma remnants
@ 2024-04-30 12:51 4% ` Konrad Dybcio
0 siblings, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-04-30 12:51 UTC (permalink / raw)
To: Robin Murphy, joro
Cc: will, catalin.marinas, linux-arm-kernel, iommu, Dmitry Baryshkov
On 30.04.2024 12:22 PM, Robin Murphy wrote:
> Thanks to the somewhat asymmetrical nature, while removing
> iommu_setup_dma_ops() from the arch_setup_dma_ops() flow, I managed to
> forget that arm64's teardown path was also specific to iommu-dma. Clean
> that up to match, otherwise probe deferral will lead to the arch code
> erroneously removing DMA ops set elsewhere.
>
> Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Link: https://lore.kernel.org/linux-iommu/Zi_LV28TR-P-PzXi@eriador.lumag.spb.ru/
> Fixes: b67483b3c44e ("iommu/dma: Centralise iommu_setup_dma_ops()")
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # QC SM8550 QRD
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
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^ permalink raw reply [relevance 4%]
* Re: [PATCH v4 6/7] iommu/dma: Centralise iommu_setup_dma_ops()
2024-04-30 12:23 4% ` Konrad Dybcio
@ 2024-04-30 12:33 0% ` Robin Murphy
-1 siblings, 0 replies; 200+ results
From: Robin Murphy @ 2024-04-30 12:33 UTC (permalink / raw)
To: Konrad Dybcio, Dmitry Baryshkov,
open list:DRM DRIVER FOR MSM ADRENO GPU, Bjorn Andersson
Cc: Joerg Roedel, Christoph Hellwig, Vineet Gupta, Russell King,
Catalin Marinas, Will Deacon, Huacai Chen, WANG Xuerui,
Thomas Bogendoerfer, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, K. Y. Srinivasan,
Haiyang Zhang, Wei Liu, Dexuan Cui, Suravee Suthikulpanit,
David Woodhouse, Lu Baolu, Niklas Schnelle, Matthew Rosato,
Gerald Schaefer, Jean-Philippe Brucker, Rob Herring,
Frank Rowand, Marek Szyprowski, Jason Gunthorpe, linux-kernel,
linux-arm-kernel, linux-acpi, iommu, devicetree, Jason Gunthorpe
On 30/04/2024 1:23 pm, Konrad Dybcio wrote:
> On 29.04.2024 11:26 PM, Dmitry Baryshkov wrote:
>> On Mon, 29 Apr 2024 at 19:31, Dmitry Baryshkov
>> <dmitry.baryshkov@linaro.org> wrote:
>>>
>>> On Fri, Apr 19, 2024 at 05:54:45PM +0100, Robin Murphy wrote:
>>>> It's somewhat hard to see, but arm64's arch_setup_dma_ops() should only
>>>> ever call iommu_setup_dma_ops() after a successful iommu_probe_device(),
>>>> which means there should be no harm in achieving the same order of
>>>> operations by running it off the back of iommu_probe_device() itself.
>>>> This then puts it in line with the x86 and s390 .probe_finalize bodges,
>>>> letting us pull it all into the main flow properly. As a bonus this lets
>>>> us fold in and de-scope the PCI workaround setup as well.
>>>>
>>>> At this point we can also then pull the call up inside the group mutex,
>>>> and avoid having to think about whether iommu_group_store_type() could
>>>> theoretically race and free the domain if iommu_setup_dma_ops() ran just
>>>> *before* iommu_device_use_default_domain() claims it... Furthermore we
>>>> replace one .probe_finalize call completely, since the only remaining
>>>> implementations are now one which only needs to run once for the initial
>>>> boot-time probe, and two which themselves render that path unreachable.
>>>>
>>>> This leaves us a big step closer to realistically being able to unpick
>>>> the variety of different things that iommu_setup_dma_ops() has been
>>>> muddling together, and further streamline iommu-dma into core API flows
>>>> in future.
>>>>
>>>> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> # For Intel IOMMU
>>>> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
>>>> Tested-by: Hanjun Guo <guohanjun@huawei.com>
>>>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>>>> ---
>>>> v2: Shuffle around to make sure the iommu_group_do_probe_finalize() case
>>>> is covered as well, with bonus side-effects as above.
>>>> v3: *Really* do that, remembering the other two probe_finalize sites too.
>>>> ---
>>>> arch/arm64/mm/dma-mapping.c | 2 --
>>>> drivers/iommu/amd/iommu.c | 8 --------
>>>> drivers/iommu/dma-iommu.c | 18 ++++++------------
>>>> drivers/iommu/dma-iommu.h | 14 ++++++--------
>>>> drivers/iommu/intel/iommu.c | 7 -------
>>>> drivers/iommu/iommu.c | 20 +++++++-------------
>>>> drivers/iommu/s390-iommu.c | 6 ------
>>>> drivers/iommu/virtio-iommu.c | 10 ----------
>>>> include/linux/iommu.h | 7 -------
>>>> 9 files changed, 19 insertions(+), 73 deletions(-)
>>>
>>> This patch breaks UFS on Qualcomm SC8180X Primus platform:
>>>
>>>
>>> [ 3.846856] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x1032db3e0, fsynr=0x130000, cbfrsynra=0x300, cb=4
>>> [ 3.846880] ufshcd-qcom 1d84000.ufshc: ufshcd_check_errors: saved_err 0x20000 saved_uic_err 0x0
>>> [ 3.846929] host_regs: 00000000: 1587031f 00000000 00000300 00000000
>>> [ 3.846935] host_regs: 00000010: 01000000 00010217 00000000 00000000
>>> [ 3.846941] host_regs: 00000020: 00000000 00070ef5 00000000 00000000
>>> [ 3.846946] host_regs: 00000030: 0000000f 00000001 00000000 00000000
>>> [ 3.846951] host_regs: 00000040: 00000000 00000000 00000000 00000000
>>> [ 3.846956] host_regs: 00000050: 032db000 00000001 00000000 00000000
>>> [ 3.846962] host_regs: 00000060: 00000000 80000000 00000000 00000000
>>> [ 3.846967] host_regs: 00000070: 032dd000 00000001 00000000 00000000
>>> [ 3.846972] host_regs: 00000080: 00000000 00000000 00000000 00000000
>>> [ 3.846977] host_regs: 00000090: 00000016 00000000 00000000 0000000c
>>> [ 3.847074] ufshcd-qcom 1d84000.ufshc: ufshcd_err_handler started; HBA state eh_fatal; powered 1; shutting down 0; saved_err = 131072; saved_uic_err = 0; force_reset = 0
>>> [ 4.406550] ufshcd-qcom 1d84000.ufshc: ufshcd_verify_dev_init: NOP OUT failed -11
>>> [ 4.417953] ufshcd-qcom 1d84000.ufshc: ufshcd_async_scan failed: -11
>>
>> Just to confirm: reverting f091e93306e0 ("dma-mapping: Simplify
>> arch_setup_dma_ops()") and b67483b3c44e ("iommu/dma: Centralise
>> iommu_setup_dma_ops()" fixes the issue for me. Please ping me if you'd
>> like me to test a fix.
>
> This also triggers a different issue (that also comes down to "ufs bad") on
> another QC platform (SM8550):
>
> [ 4.282098] scsi host0: ufshcd
> [ 4.315970] ufshcd-qcom 1d84000.ufs: ufshcd_check_errors: saved_err 0x20000 saved_uic_err 0x0
> [ 4.330155] host_regs: 00000000: 3587031f 00000000 00000400 00000000
> [ 4.343955] host_regs: 00000010: 01000000 00010217 00000000 00000000
> [ 4.356027] host_regs: 00000020: 00000000 00070ef5 00000000 00000000
> [ 4.370136] host_regs: 00000030: 0000000f 00000003 00000000 00000000
> [ 4.376662] host_regs: 00000040: 00000000 00000000 00000000 00000000
> [ 4.383192] host_regs: 00000050: 85109000 00000008 00000000 00000000
> [ 4.389719] host_regs: 00000060: 00000000 80000000 00000000 00000000
> [ 4.396245] host_regs: 00000070: 8510a000 00000008 00000000 00000000
> [ 4.402773] host_regs: 00000080: 00000000 00000000 00000000 00000000
> [ 4.409298] host_regs: 00000090: 00000016 00000000 00000000 0000000c
> [ 4.415900] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x8851093e0, fsynr=0x3b0001, cbfrsynra=0x60, cb=2
> [ 4.416135] ufshcd-qcom 1d84000.ufs: ufshcd_err_handler started; HBA state eh_fatal; powered 1; shutting down 0; saved_err = 131072; saved_uic_err = 0; force_reset = 0
> [ 4.951750] ufshcd-qcom 1d84000.ufs: ufshcd_verify_dev_init: NOP OUT failed -11
> [ 4.960644] ufshcd-qcom 1d84000.ufs: ufshcd_async_scan failed: -11
>
> Reverting the commits Dmitry mentioned also fixes this.
Yeah, It'll be the same thing - doesn't really matter exactly *how* the
UFS goes wrong due to the SMMU blocking it, the issue is that the SMMU
is erroneously blocking it in the first place due to a DMA ops mixup.
Fix is now here:
https://lore.kernel.org/linux-iommu/d4cc20cbb0c45175e98dd76bf187e2ad6421296d.1714472573.git.robin.murphy@arm.com/
Thanks,
Robin.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 6/7] iommu/dma: Centralise iommu_setup_dma_ops()
@ 2024-04-30 12:33 0% ` Robin Murphy
0 siblings, 0 replies; 200+ results
From: Robin Murphy @ 2024-04-30 12:33 UTC (permalink / raw)
To: Konrad Dybcio, Dmitry Baryshkov,
open list:DRM DRIVER FOR MSM ADRENO GPU, Bjorn Andersson
Cc: Joerg Roedel, Christoph Hellwig, Vineet Gupta, Russell King,
Catalin Marinas, Will Deacon, Huacai Chen, WANG Xuerui,
Thomas Bogendoerfer, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, K. Y. Srinivasan,
Haiyang Zhang, Wei Liu, Dexuan Cui, Suravee Suthikulpanit,
David Woodhouse, Lu Baolu, Niklas Schnelle, Matthew Rosato,
Gerald Schaefer, Jean-Philippe Brucker, Rob Herring,
Frank Rowand, Marek Szyprowski, Jason Gunthorpe, linux-kernel,
linux-arm-kernel, linux-acpi, iommu, devicetree, Jason Gunthorpe
On 30/04/2024 1:23 pm, Konrad Dybcio wrote:
> On 29.04.2024 11:26 PM, Dmitry Baryshkov wrote:
>> On Mon, 29 Apr 2024 at 19:31, Dmitry Baryshkov
>> <dmitry.baryshkov@linaro.org> wrote:
>>>
>>> On Fri, Apr 19, 2024 at 05:54:45PM +0100, Robin Murphy wrote:
>>>> It's somewhat hard to see, but arm64's arch_setup_dma_ops() should only
>>>> ever call iommu_setup_dma_ops() after a successful iommu_probe_device(),
>>>> which means there should be no harm in achieving the same order of
>>>> operations by running it off the back of iommu_probe_device() itself.
>>>> This then puts it in line with the x86 and s390 .probe_finalize bodges,
>>>> letting us pull it all into the main flow properly. As a bonus this lets
>>>> us fold in and de-scope the PCI workaround setup as well.
>>>>
>>>> At this point we can also then pull the call up inside the group mutex,
>>>> and avoid having to think about whether iommu_group_store_type() could
>>>> theoretically race and free the domain if iommu_setup_dma_ops() ran just
>>>> *before* iommu_device_use_default_domain() claims it... Furthermore we
>>>> replace one .probe_finalize call completely, since the only remaining
>>>> implementations are now one which only needs to run once for the initial
>>>> boot-time probe, and two which themselves render that path unreachable.
>>>>
>>>> This leaves us a big step closer to realistically being able to unpick
>>>> the variety of different things that iommu_setup_dma_ops() has been
>>>> muddling together, and further streamline iommu-dma into core API flows
>>>> in future.
>>>>
>>>> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> # For Intel IOMMU
>>>> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
>>>> Tested-by: Hanjun Guo <guohanjun@huawei.com>
>>>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>>>> ---
>>>> v2: Shuffle around to make sure the iommu_group_do_probe_finalize() case
>>>> is covered as well, with bonus side-effects as above.
>>>> v3: *Really* do that, remembering the other two probe_finalize sites too.
>>>> ---
>>>> arch/arm64/mm/dma-mapping.c | 2 --
>>>> drivers/iommu/amd/iommu.c | 8 --------
>>>> drivers/iommu/dma-iommu.c | 18 ++++++------------
>>>> drivers/iommu/dma-iommu.h | 14 ++++++--------
>>>> drivers/iommu/intel/iommu.c | 7 -------
>>>> drivers/iommu/iommu.c | 20 +++++++-------------
>>>> drivers/iommu/s390-iommu.c | 6 ------
>>>> drivers/iommu/virtio-iommu.c | 10 ----------
>>>> include/linux/iommu.h | 7 -------
>>>> 9 files changed, 19 insertions(+), 73 deletions(-)
>>>
>>> This patch breaks UFS on Qualcomm SC8180X Primus platform:
>>>
>>>
>>> [ 3.846856] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x1032db3e0, fsynr=0x130000, cbfrsynra=0x300, cb=4
>>> [ 3.846880] ufshcd-qcom 1d84000.ufshc: ufshcd_check_errors: saved_err 0x20000 saved_uic_err 0x0
>>> [ 3.846929] host_regs: 00000000: 1587031f 00000000 00000300 00000000
>>> [ 3.846935] host_regs: 00000010: 01000000 00010217 00000000 00000000
>>> [ 3.846941] host_regs: 00000020: 00000000 00070ef5 00000000 00000000
>>> [ 3.846946] host_regs: 00000030: 0000000f 00000001 00000000 00000000
>>> [ 3.846951] host_regs: 00000040: 00000000 00000000 00000000 00000000
>>> [ 3.846956] host_regs: 00000050: 032db000 00000001 00000000 00000000
>>> [ 3.846962] host_regs: 00000060: 00000000 80000000 00000000 00000000
>>> [ 3.846967] host_regs: 00000070: 032dd000 00000001 00000000 00000000
>>> [ 3.846972] host_regs: 00000080: 00000000 00000000 00000000 00000000
>>> [ 3.846977] host_regs: 00000090: 00000016 00000000 00000000 0000000c
>>> [ 3.847074] ufshcd-qcom 1d84000.ufshc: ufshcd_err_handler started; HBA state eh_fatal; powered 1; shutting down 0; saved_err = 131072; saved_uic_err = 0; force_reset = 0
>>> [ 4.406550] ufshcd-qcom 1d84000.ufshc: ufshcd_verify_dev_init: NOP OUT failed -11
>>> [ 4.417953] ufshcd-qcom 1d84000.ufshc: ufshcd_async_scan failed: -11
>>
>> Just to confirm: reverting f091e93306e0 ("dma-mapping: Simplify
>> arch_setup_dma_ops()") and b67483b3c44e ("iommu/dma: Centralise
>> iommu_setup_dma_ops()" fixes the issue for me. Please ping me if you'd
>> like me to test a fix.
>
> This also triggers a different issue (that also comes down to "ufs bad") on
> another QC platform (SM8550):
>
> [ 4.282098] scsi host0: ufshcd
> [ 4.315970] ufshcd-qcom 1d84000.ufs: ufshcd_check_errors: saved_err 0x20000 saved_uic_err 0x0
> [ 4.330155] host_regs: 00000000: 3587031f 00000000 00000400 00000000
> [ 4.343955] host_regs: 00000010: 01000000 00010217 00000000 00000000
> [ 4.356027] host_regs: 00000020: 00000000 00070ef5 00000000 00000000
> [ 4.370136] host_regs: 00000030: 0000000f 00000003 00000000 00000000
> [ 4.376662] host_regs: 00000040: 00000000 00000000 00000000 00000000
> [ 4.383192] host_regs: 00000050: 85109000 00000008 00000000 00000000
> [ 4.389719] host_regs: 00000060: 00000000 80000000 00000000 00000000
> [ 4.396245] host_regs: 00000070: 8510a000 00000008 00000000 00000000
> [ 4.402773] host_regs: 00000080: 00000000 00000000 00000000 00000000
> [ 4.409298] host_regs: 00000090: 00000016 00000000 00000000 0000000c
> [ 4.415900] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x8851093e0, fsynr=0x3b0001, cbfrsynra=0x60, cb=2
> [ 4.416135] ufshcd-qcom 1d84000.ufs: ufshcd_err_handler started; HBA state eh_fatal; powered 1; shutting down 0; saved_err = 131072; saved_uic_err = 0; force_reset = 0
> [ 4.951750] ufshcd-qcom 1d84000.ufs: ufshcd_verify_dev_init: NOP OUT failed -11
> [ 4.960644] ufshcd-qcom 1d84000.ufs: ufshcd_async_scan failed: -11
>
> Reverting the commits Dmitry mentioned also fixes this.
Yeah, It'll be the same thing - doesn't really matter exactly *how* the
UFS goes wrong due to the SMMU blocking it, the issue is that the SMMU
is erroneously blocking it in the first place due to a DMA ops mixup.
Fix is now here:
https://lore.kernel.org/linux-iommu/d4cc20cbb0c45175e98dd76bf187e2ad6421296d.1714472573.git.robin.murphy@arm.com/
Thanks,
Robin.
^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 6/7] iommu/dma: Centralise iommu_setup_dma_ops()
@ 2024-04-30 12:23 4% ` Konrad Dybcio
0 siblings, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-04-30 12:23 UTC (permalink / raw)
To: Dmitry Baryshkov, Robin Murphy,
open list:DRM DRIVER FOR MSM ADRENO GPU, Bjorn Andersson
Cc: Joerg Roedel, Christoph Hellwig, Vineet Gupta, Russell King,
Catalin Marinas, Will Deacon, Huacai Chen, WANG Xuerui,
Thomas Bogendoerfer, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, K. Y. Srinivasan,
Haiyang Zhang, Wei Liu, Dexuan Cui, Suravee Suthikulpanit,
David Woodhouse, Lu Baolu, Niklas Schnelle, Matthew Rosato,
Gerald Schaefer, Jean-Philippe Brucker, Rob Herring,
Frank Rowand, Marek Szyprowski, Jason Gunthorpe, linux-kernel,
linux-arm-kernel, linux-acpi, iommu, devicetree, Jason Gunthorpe
On 29.04.2024 11:26 PM, Dmitry Baryshkov wrote:
> On Mon, 29 Apr 2024 at 19:31, Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
>>
>> On Fri, Apr 19, 2024 at 05:54:45PM +0100, Robin Murphy wrote:
>>> It's somewhat hard to see, but arm64's arch_setup_dma_ops() should only
>>> ever call iommu_setup_dma_ops() after a successful iommu_probe_device(),
>>> which means there should be no harm in achieving the same order of
>>> operations by running it off the back of iommu_probe_device() itself.
>>> This then puts it in line with the x86 and s390 .probe_finalize bodges,
>>> letting us pull it all into the main flow properly. As a bonus this lets
>>> us fold in and de-scope the PCI workaround setup as well.
>>>
>>> At this point we can also then pull the call up inside the group mutex,
>>> and avoid having to think about whether iommu_group_store_type() could
>>> theoretically race and free the domain if iommu_setup_dma_ops() ran just
>>> *before* iommu_device_use_default_domain() claims it... Furthermore we
>>> replace one .probe_finalize call completely, since the only remaining
>>> implementations are now one which only needs to run once for the initial
>>> boot-time probe, and two which themselves render that path unreachable.
>>>
>>> This leaves us a big step closer to realistically being able to unpick
>>> the variety of different things that iommu_setup_dma_ops() has been
>>> muddling together, and further streamline iommu-dma into core API flows
>>> in future.
>>>
>>> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> # For Intel IOMMU
>>> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
>>> Tested-by: Hanjun Guo <guohanjun@huawei.com>
>>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>>> ---
>>> v2: Shuffle around to make sure the iommu_group_do_probe_finalize() case
>>> is covered as well, with bonus side-effects as above.
>>> v3: *Really* do that, remembering the other two probe_finalize sites too.
>>> ---
>>> arch/arm64/mm/dma-mapping.c | 2 --
>>> drivers/iommu/amd/iommu.c | 8 --------
>>> drivers/iommu/dma-iommu.c | 18 ++++++------------
>>> drivers/iommu/dma-iommu.h | 14 ++++++--------
>>> drivers/iommu/intel/iommu.c | 7 -------
>>> drivers/iommu/iommu.c | 20 +++++++-------------
>>> drivers/iommu/s390-iommu.c | 6 ------
>>> drivers/iommu/virtio-iommu.c | 10 ----------
>>> include/linux/iommu.h | 7 -------
>>> 9 files changed, 19 insertions(+), 73 deletions(-)
>>
>> This patch breaks UFS on Qualcomm SC8180X Primus platform:
>>
>>
>> [ 3.846856] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x1032db3e0, fsynr=0x130000, cbfrsynra=0x300, cb=4
>> [ 3.846880] ufshcd-qcom 1d84000.ufshc: ufshcd_check_errors: saved_err 0x20000 saved_uic_err 0x0
>> [ 3.846929] host_regs: 00000000: 1587031f 00000000 00000300 00000000
>> [ 3.846935] host_regs: 00000010: 01000000 00010217 00000000 00000000
>> [ 3.846941] host_regs: 00000020: 00000000 00070ef5 00000000 00000000
>> [ 3.846946] host_regs: 00000030: 0000000f 00000001 00000000 00000000
>> [ 3.846951] host_regs: 00000040: 00000000 00000000 00000000 00000000
>> [ 3.846956] host_regs: 00000050: 032db000 00000001 00000000 00000000
>> [ 3.846962] host_regs: 00000060: 00000000 80000000 00000000 00000000
>> [ 3.846967] host_regs: 00000070: 032dd000 00000001 00000000 00000000
>> [ 3.846972] host_regs: 00000080: 00000000 00000000 00000000 00000000
>> [ 3.846977] host_regs: 00000090: 00000016 00000000 00000000 0000000c
>> [ 3.847074] ufshcd-qcom 1d84000.ufshc: ufshcd_err_handler started; HBA state eh_fatal; powered 1; shutting down 0; saved_err = 131072; saved_uic_err = 0; force_reset = 0
>> [ 4.406550] ufshcd-qcom 1d84000.ufshc: ufshcd_verify_dev_init: NOP OUT failed -11
>> [ 4.417953] ufshcd-qcom 1d84000.ufshc: ufshcd_async_scan failed: -11
>
> Just to confirm: reverting f091e93306e0 ("dma-mapping: Simplify
> arch_setup_dma_ops()") and b67483b3c44e ("iommu/dma: Centralise
> iommu_setup_dma_ops()" fixes the issue for me. Please ping me if you'd
> like me to test a fix.
This also triggers a different issue (that also comes down to "ufs bad") on
another QC platform (SM8550):
[ 4.282098] scsi host0: ufshcd
[ 4.315970] ufshcd-qcom 1d84000.ufs: ufshcd_check_errors: saved_err 0x20000 saved_uic_err 0x0
[ 4.330155] host_regs: 00000000: 3587031f 00000000 00000400 00000000
[ 4.343955] host_regs: 00000010: 01000000 00010217 00000000 00000000
[ 4.356027] host_regs: 00000020: 00000000 00070ef5 00000000 00000000
[ 4.370136] host_regs: 00000030: 0000000f 00000003 00000000 00000000
[ 4.376662] host_regs: 00000040: 00000000 00000000 00000000 00000000
[ 4.383192] host_regs: 00000050: 85109000 00000008 00000000 00000000
[ 4.389719] host_regs: 00000060: 00000000 80000000 00000000 00000000
[ 4.396245] host_regs: 00000070: 8510a000 00000008 00000000 00000000
[ 4.402773] host_regs: 00000080: 00000000 00000000 00000000 00000000
[ 4.409298] host_regs: 00000090: 00000016 00000000 00000000 0000000c
[ 4.415900] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x8851093e0, fsynr=0x3b0001, cbfrsynra=0x60, cb=2
[ 4.416135] ufshcd-qcom 1d84000.ufs: ufshcd_err_handler started; HBA state eh_fatal; powered 1; shutting down 0; saved_err = 131072; saved_uic_err = 0; force_reset = 0
[ 4.951750] ufshcd-qcom 1d84000.ufs: ufshcd_verify_dev_init: NOP OUT failed -11
[ 4.960644] ufshcd-qcom 1d84000.ufs: ufshcd_async_scan failed: -11
Reverting the commits Dmitry mentioned also fixes this.
Konrad
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 4%]
* Re: [PATCH v4 6/7] iommu/dma: Centralise iommu_setup_dma_ops()
@ 2024-04-30 12:23 4% ` Konrad Dybcio
0 siblings, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-04-30 12:23 UTC (permalink / raw)
To: Dmitry Baryshkov, Robin Murphy,
open list:DRM DRIVER FOR MSM ADRENO GPU, Bjorn Andersson
Cc: Joerg Roedel, Christoph Hellwig, Vineet Gupta, Russell King,
Catalin Marinas, Will Deacon, Huacai Chen, WANG Xuerui,
Thomas Bogendoerfer, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, K. Y. Srinivasan,
Haiyang Zhang, Wei Liu, Dexuan Cui, Suravee Suthikulpanit,
David Woodhouse, Lu Baolu, Niklas Schnelle, Matthew Rosato,
Gerald Schaefer, Jean-Philippe Brucker, Rob Herring,
Frank Rowand, Marek Szyprowski, Jason Gunthorpe, linux-kernel,
linux-arm-kernel, linux-acpi, iommu, devicetree, Jason Gunthorpe
On 29.04.2024 11:26 PM, Dmitry Baryshkov wrote:
> On Mon, 29 Apr 2024 at 19:31, Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
>>
>> On Fri, Apr 19, 2024 at 05:54:45PM +0100, Robin Murphy wrote:
>>> It's somewhat hard to see, but arm64's arch_setup_dma_ops() should only
>>> ever call iommu_setup_dma_ops() after a successful iommu_probe_device(),
>>> which means there should be no harm in achieving the same order of
>>> operations by running it off the back of iommu_probe_device() itself.
>>> This then puts it in line with the x86 and s390 .probe_finalize bodges,
>>> letting us pull it all into the main flow properly. As a bonus this lets
>>> us fold in and de-scope the PCI workaround setup as well.
>>>
>>> At this point we can also then pull the call up inside the group mutex,
>>> and avoid having to think about whether iommu_group_store_type() could
>>> theoretically race and free the domain if iommu_setup_dma_ops() ran just
>>> *before* iommu_device_use_default_domain() claims it... Furthermore we
>>> replace one .probe_finalize call completely, since the only remaining
>>> implementations are now one which only needs to run once for the initial
>>> boot-time probe, and two which themselves render that path unreachable.
>>>
>>> This leaves us a big step closer to realistically being able to unpick
>>> the variety of different things that iommu_setup_dma_ops() has been
>>> muddling together, and further streamline iommu-dma into core API flows
>>> in future.
>>>
>>> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> # For Intel IOMMU
>>> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
>>> Tested-by: Hanjun Guo <guohanjun@huawei.com>
>>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>>> ---
>>> v2: Shuffle around to make sure the iommu_group_do_probe_finalize() case
>>> is covered as well, with bonus side-effects as above.
>>> v3: *Really* do that, remembering the other two probe_finalize sites too.
>>> ---
>>> arch/arm64/mm/dma-mapping.c | 2 --
>>> drivers/iommu/amd/iommu.c | 8 --------
>>> drivers/iommu/dma-iommu.c | 18 ++++++------------
>>> drivers/iommu/dma-iommu.h | 14 ++++++--------
>>> drivers/iommu/intel/iommu.c | 7 -------
>>> drivers/iommu/iommu.c | 20 +++++++-------------
>>> drivers/iommu/s390-iommu.c | 6 ------
>>> drivers/iommu/virtio-iommu.c | 10 ----------
>>> include/linux/iommu.h | 7 -------
>>> 9 files changed, 19 insertions(+), 73 deletions(-)
>>
>> This patch breaks UFS on Qualcomm SC8180X Primus platform:
>>
>>
>> [ 3.846856] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x1032db3e0, fsynr=0x130000, cbfrsynra=0x300, cb=4
>> [ 3.846880] ufshcd-qcom 1d84000.ufshc: ufshcd_check_errors: saved_err 0x20000 saved_uic_err 0x0
>> [ 3.846929] host_regs: 00000000: 1587031f 00000000 00000300 00000000
>> [ 3.846935] host_regs: 00000010: 01000000 00010217 00000000 00000000
>> [ 3.846941] host_regs: 00000020: 00000000 00070ef5 00000000 00000000
>> [ 3.846946] host_regs: 00000030: 0000000f 00000001 00000000 00000000
>> [ 3.846951] host_regs: 00000040: 00000000 00000000 00000000 00000000
>> [ 3.846956] host_regs: 00000050: 032db000 00000001 00000000 00000000
>> [ 3.846962] host_regs: 00000060: 00000000 80000000 00000000 00000000
>> [ 3.846967] host_regs: 00000070: 032dd000 00000001 00000000 00000000
>> [ 3.846972] host_regs: 00000080: 00000000 00000000 00000000 00000000
>> [ 3.846977] host_regs: 00000090: 00000016 00000000 00000000 0000000c
>> [ 3.847074] ufshcd-qcom 1d84000.ufshc: ufshcd_err_handler started; HBA state eh_fatal; powered 1; shutting down 0; saved_err = 131072; saved_uic_err = 0; force_reset = 0
>> [ 4.406550] ufshcd-qcom 1d84000.ufshc: ufshcd_verify_dev_init: NOP OUT failed -11
>> [ 4.417953] ufshcd-qcom 1d84000.ufshc: ufshcd_async_scan failed: -11
>
> Just to confirm: reverting f091e93306e0 ("dma-mapping: Simplify
> arch_setup_dma_ops()") and b67483b3c44e ("iommu/dma: Centralise
> iommu_setup_dma_ops()" fixes the issue for me. Please ping me if you'd
> like me to test a fix.
This also triggers a different issue (that also comes down to "ufs bad") on
another QC platform (SM8550):
[ 4.282098] scsi host0: ufshcd
[ 4.315970] ufshcd-qcom 1d84000.ufs: ufshcd_check_errors: saved_err 0x20000 saved_uic_err 0x0
[ 4.330155] host_regs: 00000000: 3587031f 00000000 00000400 00000000
[ 4.343955] host_regs: 00000010: 01000000 00010217 00000000 00000000
[ 4.356027] host_regs: 00000020: 00000000 00070ef5 00000000 00000000
[ 4.370136] host_regs: 00000030: 0000000f 00000003 00000000 00000000
[ 4.376662] host_regs: 00000040: 00000000 00000000 00000000 00000000
[ 4.383192] host_regs: 00000050: 85109000 00000008 00000000 00000000
[ 4.389719] host_regs: 00000060: 00000000 80000000 00000000 00000000
[ 4.396245] host_regs: 00000070: 8510a000 00000008 00000000 00000000
[ 4.402773] host_regs: 00000080: 00000000 00000000 00000000 00000000
[ 4.409298] host_regs: 00000090: 00000016 00000000 00000000 0000000c
[ 4.415900] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x8851093e0, fsynr=0x3b0001, cbfrsynra=0x60, cb=2
[ 4.416135] ufshcd-qcom 1d84000.ufs: ufshcd_err_handler started; HBA state eh_fatal; powered 1; shutting down 0; saved_err = 131072; saved_uic_err = 0; force_reset = 0
[ 4.951750] ufshcd-qcom 1d84000.ufs: ufshcd_verify_dev_init: NOP OUT failed -11
[ 4.960644] ufshcd-qcom 1d84000.ufs: ufshcd_async_scan failed: -11
Reverting the commits Dmitry mentioned also fixes this.
Konrad
^ permalink raw reply [relevance 4%]
* Re: [PATCH] arch/topology: Fix variable naming
@ 2024-04-30 12:19 4% ` Konrad Dybcio
2024-05-15 8:27 4% ` [tip: sched/urgent] arch/topology: Fix variable naming to avoid shadowing tip-bot2 for Vincent Guittot
1 sibling, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-04-30 12:19 UTC (permalink / raw)
To: Vincent Guittot, lkp, sudeep.holla, rafael, mingo, peterz,
lukasz.luba, gregkh, linux-kernel, qyousef
On 25.04.2024 9:37 AM, Vincent Guittot wrote:
> Using hw_pressure for local variable is confusing in regard to the
> per_cpu hw_pressure variable. Rename it to avoid confusion.
To avoid confusing the compiler :P
>
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202404250740.VhQQoD7N-lkp@intel.com/
> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
> ---
Fixes: d4dbc991714e ("sched/cpufreq: Rename arch_update_thermal_pressure() => arch_update_hw_pressure()")
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # QC SM8550 QRD
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [relevance 4%]
* Re: [PATCH v6 4/5] sched: Rename arch_update_thermal_pressure into arch_update_hw_pressure
@ 2024-04-30 12:15 4% ` Konrad Dybcio
0 siblings, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-04-30 12:15 UTC (permalink / raw)
To: Vincent Guittot
Cc: linux, catalin.marinas, will, sudeep.holla, rafael, viresh.kumar,
agross, andersson, mingo, peterz, juri.lelli, dietmar.eggemann,
rostedt, bsegall, mgorman, bristot, vschneid, lukasz.luba,
rui.zhang, mhiramat, daniel.lezcano, amit.kachhap, corbet,
gregkh, linux-arm-kernel, linux-kernel, linux-pm, linux-arm-msm,
linux-trace-kernel, linux-doc, Qais Yousef, Dmitry Baryshkov
On 30.04.2024 2:00 PM, Vincent Guittot wrote:
> H Konrad,
>
> On Tue, 30 Apr 2024 at 13:23, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>> On 26.03.2024 10:16 AM, Vincent Guittot wrote:
>>> Now that cpufreq provides a pressure value to the scheduler, rename
>>> arch_update_thermal_pressure into HW pressure to reflect that it returns
>>> a pressure applied by HW (i.e. with a high frequency change) and not
>>> always related to thermal mitigation but also generated by max current
>>> limitation as an example. Such high frequency signal needs filtering to be
>>> smoothed and provide an value that reflects the average available capacity
>>> into the scheduler time scale.
>>>
>>> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
>>> Reviewed-by: Qais Yousef <qyousef@layalina.io>
>>> Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
>>> Tested-by: Lukasz Luba <lukasz.luba@arm.com>
>>> ---
>>
>> Hi, I'm not quite sure how, but this commit specifically breaks booting
>> on Qualcomm platforms with EAS..
>
> This is the fix:
> https://lore.kernel.org/lkml/20240425073709.379016-1-vincent.guittot@linaro.org/
Yep, works now!
>
>>
>> https://pastebin.com/raw/1Uh7u81x
>
> Which platform is it ?
> I tested it on dragonboard rb3 and it booted and run tests even w/o the fix
As the log suggests, SM8550 QRD
Thanks for your prompt response!
Konrad
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 4%]
* Re: [PATCH v6 4/5] sched: Rename arch_update_thermal_pressure into arch_update_hw_pressure
@ 2024-04-30 12:15 4% ` Konrad Dybcio
0 siblings, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-04-30 12:15 UTC (permalink / raw)
To: Vincent Guittot
Cc: linux, catalin.marinas, will, sudeep.holla, rafael, viresh.kumar,
agross, andersson, mingo, peterz, juri.lelli, dietmar.eggemann,
rostedt, bsegall, mgorman, bristot, vschneid, lukasz.luba,
rui.zhang, mhiramat, daniel.lezcano, amit.kachhap, corbet,
gregkh, linux-arm-kernel, linux-kernel, linux-pm, linux-arm-msm,
linux-trace-kernel, linux-doc, Qais Yousef, Dmitry Baryshkov
On 30.04.2024 2:00 PM, Vincent Guittot wrote:
> H Konrad,
>
> On Tue, 30 Apr 2024 at 13:23, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>> On 26.03.2024 10:16 AM, Vincent Guittot wrote:
>>> Now that cpufreq provides a pressure value to the scheduler, rename
>>> arch_update_thermal_pressure into HW pressure to reflect that it returns
>>> a pressure applied by HW (i.e. with a high frequency change) and not
>>> always related to thermal mitigation but also generated by max current
>>> limitation as an example. Such high frequency signal needs filtering to be
>>> smoothed and provide an value that reflects the average available capacity
>>> into the scheduler time scale.
>>>
>>> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
>>> Reviewed-by: Qais Yousef <qyousef@layalina.io>
>>> Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
>>> Tested-by: Lukasz Luba <lukasz.luba@arm.com>
>>> ---
>>
>> Hi, I'm not quite sure how, but this commit specifically breaks booting
>> on Qualcomm platforms with EAS..
>
> This is the fix:
> https://lore.kernel.org/lkml/20240425073709.379016-1-vincent.guittot@linaro.org/
Yep, works now!
>
>>
>> https://pastebin.com/raw/1Uh7u81x
>
> Which platform is it ?
> I tested it on dragonboard rb3 and it booted and run tests even w/o the fix
As the log suggests, SM8550 QRD
Thanks for your prompt response!
Konrad
^ permalink raw reply [relevance 4%]
* Re: [PATCH 10/10] arm64: dts: qcom: Add AYN Odin 2
2024-04-24 15:29 8% ` Xilin Wu
(?)
(?)
@ 2024-04-30 10:26 0% ` Konrad Dybcio
-1 siblings, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-04-30 10:26 UTC (permalink / raw)
To: wuxilin123, Uwe Kleine-König, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Junhao Xie, Neil Armstrong,
Jessica Zhang, Sam Ravnborg, David Airlie, Daniel Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Bjorn Andersson, Tengfei Fan, Molly Sophia
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm
On 24.04.2024 5:29 PM, Xilin Wu via B4 Relay wrote:
> From: Xilin Wu <wuxilin123@gmail.com>
>
> AYN Odin 2 is a gaming handheld based on QCS8550, which is derived
> from SM8550 but without modem RF system.
>
> This commit brings support for:
> * Remoteprocs
> * UFS storage
> * SD Card
> * Type-C with USB3 10Gbps and DisplayPort (4-lane requires a pending
> patch)
> * PCIe0 (Wi-Fi requires the pending pwrseq series)
> * Bluetooth
> * Regulators
> * Integrated fan with automatic speed control based on CPU temperature
> * Power and volume keys
> * M1, M2 buttons
> * HDMI output up to 1080p 60hz
> * four groups of RGB lights
> * GPU
> * Internal DSI display with touchscreen
>
> Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
> ---
[...]
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pmk8550_pwm 0 860000>;
> + brightness-levels = <1023 0>;
Huh? Is min/max swapped?
> + num-interpolated-steps = <1023>;
> + default-brightness-level = <600>;
> + power-supply = <&vph_pwr>;
> + enable-gpios = <&pmk8550_gpios 5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm_backlight_default>;
property-n
property-names
[...]
> + cooling-maps {
> + map0 {
> + trip = <&cpuss0_active0>;
> + cooling-device = <&fan 0 1>;
> + };
Please adda a newline between each subnode
[...]
> + /* Setting regulator-allow-set-load here will crash the device */
??
> + vreg_l17b_2p5: ldo17 {
> + regulator-name = "vreg_l17b_2p5";
> + regulator-min-microvolt = <2504000>;
> + regulator-max-microvolt = <2504000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
[...]
> +
> + backlight = <&backlight>;
> + /* touchscreen and display panel share the same reset gpio! */
> + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
Perhaps you would be interested in drm_panel_follower
[...]
> +
> +&sdhc_2 {
> + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
> + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
> + vmmc-supply = <&vreg_l9b_2p9>;
> + vqmmc-supply = <&vreg_l8b_1p8>;
> + bus-width = <4>;
> + no-sdio;
> + no-mmc;
> +
> + /* SDR104 does seem to be working on this device*/
> + /delete-property/ sdhci-caps-mask;
Eeeh.. I'm not sure about this. Maybe it still has some issues that
don't manifest immediately.
[...]
> +&uart15 {
> + status = "okay";
> +
> + /* Gamepad controlled by onboard MCU */
As in, that MCU is connected to 8550 through this UART port?
Konrad
^ permalink raw reply [relevance 0%]
* Re: [PATCH 08/12] arm64: dts: qcom: sm8550: move PHY's orientation-switch to SoC dtsi
2024-04-29 12:43 20% ` [PATCH 08/12] arm64: dts: qcom: sm8550: move PHY's orientation-switch to " Dmitry Baryshkov
2024-04-29 12:51 4% ` neil.armstrong
@ 2024-04-30 9:35 4% ` Konrad Dybcio
1 sibling, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-04-30 9:35 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 29.04.2024 2:43 PM, Dmitry Baryshkov wrote:
> The orientation-switch of the USB+DP QMP PHY is not a property of the
> board, it is a design property of the QMP PHY itself. Move the property
> from board DTS to SoC DTSI.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [relevance 4%]
* Re: [PATCH 04/12] arm64: dts: qcom: sm8550: move USB graph to the SoC dtsi
2024-04-29 12:43 20% ` [PATCH 04/12] arm64: dts: qcom: sm8550: move USB graph to the " Dmitry Baryshkov
2024-04-29 12:52 4% ` neil.armstrong
@ 2024-04-30 9:35 4% ` Konrad Dybcio
1 sibling, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-04-30 9:35 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 29.04.2024 2:43 PM, Dmitry Baryshkov wrote:
> Move the graph connection between USB host, USB SS PHY and DP port to
> the SoC dtsi file. They are linked in hardware in this way.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [relevance 4%]
* [PATCH 08/11] dt-bindings: nvmem: Add compatible for sm8450, sm8550 and sm8650
2024-04-30 8:49 4% [PATCH 00/11] nvmem: patches(set 1) for 6.10 srinivas.kandagatla
@ 2024-04-30 8:49 15% ` srinivas.kandagatla
0 siblings, 0 replies; 200+ results
From: srinivas.kandagatla @ 2024-04-30 8:49 UTC (permalink / raw)
To: gregkh
Cc: linux-kernel, Mukesh Ojha, Krzysztof Kozlowski, Srinivas Kandagatla
From: Mukesh Ojha <quic_mojha@quicinc.com>
Document QFPROM compatible for sm8450, sm8550 and sm8650 SoCs.
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
index 8c8f05d9eaf1..aed90aff3593 100644
--- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
+++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
@@ -42,6 +42,9 @@ properties:
- qcom,sm6375-qfprom
- qcom,sm8150-qfprom
- qcom,sm8250-qfprom
+ - qcom,sm8450-qfprom
+ - qcom,sm8550-qfprom
+ - qcom,sm8650-qfprom
- const: qcom,qfprom
reg:
--
2.25.1
^ permalink raw reply related [relevance 15%]
* [PATCH 00/11] nvmem: patches(set 1) for 6.10
@ 2024-04-30 8:49 4% srinivas.kandagatla
2024-04-30 8:49 15% ` [PATCH 08/11] dt-bindings: nvmem: Add compatible for sm8450, sm8550 and sm8650 srinivas.kandagatla
0 siblings, 1 reply; 200+ results
From: srinivas.kandagatla @ 2024-04-30 8:49 UTC (permalink / raw)
To: gregkh; +Cc: linux-kernel, Srinivas Kandagatla
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Hi Greg,
Here are few patches in nvmem for 6.10 that includes
- few driver owner related cleanups by Krzysztof
- switch to device_add_groups
- add support for SC8280XP
- few very minor updates.
Can you please queue them up for 6.10.
Thanks,
Srini
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
David Collins (1):
dt-bindings: nvmem: qcom,spmi-sdam: update maintainer
Greg Kroah-Hartman (1):
nvmem: core: switch to use device_add_groups()
Konrad Dybcio (1):
dt-bindings: nvmem: Add compatible for SC8280XP
Krzysztof Kozlowski (5):
nvmem: layouts: store owner from modules with
nvmem_layout_driver_register()
nvmem: layouts: onie-tlv: drop driver owner initialization
nvmem: layouts: sl28vpd: drop driver owner initialization
nvmem: sc27xx: fix module autoloading
nvmem: sprd: fix module autoloading
Mukesh Ojha (2):
dt-bindings: nvmem: Add compatible for sm8450, sm8550 and sm8650
nvmem: meson-mx-efuse: Remove nvmem_device from efuse struct
Uwe Kleine-König (1):
nvmem: lpc18xx_eeprom: Convert to platform remove callback returning
void
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 4 ++++
Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml | 2 +-
drivers/nvmem/core.c | 2 +-
drivers/nvmem/layouts.c | 6 ++++--
drivers/nvmem/layouts/onie-tlv.c | 1 -
drivers/nvmem/layouts/sl28vpd.c | 1 -
drivers/nvmem/lpc18xx_eeprom.c | 6 ++----
drivers/nvmem/meson-mx-efuse.c | 6 +++---
drivers/nvmem/sc27xx-efuse.c | 1 +
drivers/nvmem/sprd-efuse.c | 1 +
include/linux/nvmem-provider.h | 5 ++++-
11 files changed, 21 insertions(+), 14 deletions(-)
--
2.25.1
^ permalink raw reply [relevance 4%]
* Re: [PATCH 04/12] arm64: dts: qcom: sm8550: move USB graph to the SoC dtsi
2024-04-29 12:43 20% ` [PATCH 04/12] arm64: dts: qcom: sm8550: move USB graph to the " Dmitry Baryshkov
@ 2024-04-29 12:52 4% ` neil.armstrong
2024-04-30 9:35 4% ` Konrad Dybcio
1 sibling, 0 replies; 200+ results
From: neil.armstrong @ 2024-04-29 12:52 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 29/04/2024 14:43, Dmitry Baryshkov wrote:
> Move the graph connection between USB host, USB SS PHY and DP port to
> the SoC dtsi file. They are linked in hardware in this way.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 13 -------------
> arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 13 -------------
> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 13 -------------
> arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 8 --------
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++
> 5 files changed, 4 insertions(+), 47 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> index 12d60a0ee095..f786d9114936 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> @@ -940,7 +940,6 @@ &mdss_dp0 {
> };
>
> &mdss_dp0_out {
> - remote-endpoint = <&usb_dp_qmpphy_dp_in>;
> data-lanes = <0 1>;
> };
>
> @@ -1267,10 +1266,6 @@ &usb_1_dwc3_hs {
> remote-endpoint = <&pmic_glink_hs_in>;
> };
>
> -&usb_1_dwc3_ss {
> - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
> -};
> -
> &usb_1_hsphy {
> vdd-supply = <&vreg_l1e_0p88>;
> vdda12-supply = <&vreg_l3e_1p2>;
> @@ -1289,18 +1284,10 @@ &usb_dp_qmpphy {
> status = "okay";
> };
>
> -&usb_dp_qmpphy_dp_in {
> - remote-endpoint = <&mdss_dp0_out>;
> -};
> -
> &usb_dp_qmpphy_out {
> remote-endpoint = <&pmic_glink_ss_in>;
> };
>
> -&usb_dp_qmpphy_usb_ss_in {
> - remote-endpoint = <&usb_1_dwc3_ss>;
> -};
> -
> &xo_board {
> clock-frequency = <76800000>;
> };
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
> index 3d4ad5aac70f..56800ab903a1 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
> @@ -736,7 +736,6 @@ &mdss_dp0 {
>
> &mdss_dp0_out {
> data-lanes = <0 1>;
> - remote-endpoint = <&usb_dp_qmpphy_dp_in>;
> };
>
> &pcie_1_phy_aux_clk {
> @@ -960,10 +959,6 @@ &usb_1_dwc3_hs {
> remote-endpoint = <&pmic_glink_hs_in>;
> };
>
> -&usb_1_dwc3_ss {
> - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
> -};
> -
> &usb_1_hsphy {
> vdd-supply = <&vreg_l1e_0p88>;
> vdda12-supply = <&vreg_l3e_1p2>;
> @@ -982,18 +977,10 @@ &usb_dp_qmpphy {
> status = "okay";
> };
>
> -&usb_dp_qmpphy_dp_in {
> - remote-endpoint = <&mdss_dp0_out>;
> -};
> -
> &usb_dp_qmpphy_out {
> remote-endpoint = <&pmic_glink_ss_in>;
> };
>
> -&usb_dp_qmpphy_usb_ss_in {
> - remote-endpoint = <&usb_1_dwc3_ss>;
> -};
> -
> &xo_board {
> clock-frequency = <76800000>;
> };
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> index 92f015017418..d0b373da39d4 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> @@ -807,7 +807,6 @@ &mdss_dp0 {
>
> &mdss_dp0_out {
> data-lanes = <0 1>;
> - remote-endpoint = <&usb_dp_qmpphy_dp_in>;
> };
>
> &pcie_1_phy_aux_clk {
> @@ -1144,10 +1143,6 @@ &usb_1_dwc3_hs {
> remote-endpoint = <&pmic_glink_hs_in>;
> };
>
> -&usb_1_dwc3_ss {
> - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
> -};
> -
> &usb_1_hsphy {
> vdd-supply = <&vreg_l1e_0p88>;
> vdda12-supply = <&vreg_l3e_1p2>;
> @@ -1166,18 +1161,10 @@ &usb_dp_qmpphy {
> status = "okay";
> };
>
> -&usb_dp_qmpphy_dp_in {
> - remote-endpoint = <&mdss_dp0_out>;
> -};
> -
> &usb_dp_qmpphy_out {
> remote-endpoint = <&redriver_ss_in>;
> };
>
> -&usb_dp_qmpphy_usb_ss_in {
> - remote-endpoint = <&usb_1_dwc3_ss>;
> -};
> -
> &xo_board {
> clock-frequency = <76800000>;
> };
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
> index 85e0d3d66e16..7a8d5c34e9e6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
> @@ -746,10 +746,6 @@ &usb_1_dwc3_hs {
> remote-endpoint = <&pmic_glink_hs_in>;
> };
>
> -&usb_1_dwc3_ss {
> - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
> -};
> -
> &usb_1_hsphy {
> vdd-supply = <&pm8550vs_2_l1>;
> vdda12-supply = <&pm8550vs_2_l3>;
> @@ -770,10 +766,6 @@ &usb_dp_qmpphy_out {
> remote-endpoint = <&pmic_glink_ss_in>;
> };
>
> -&usb_dp_qmpphy_usb_ss_in {
> - remote-endpoint = <&usb_1_dwc3_ss>;
> -};
> -
> &xo_board {
> clock-frequency = <76800000>;
> };
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index bc5aeb05ffc3..3ada5a30ecb7 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -2910,6 +2910,7 @@ mdss_dp0_in: endpoint {
> port@1 {
> reg = <1>;
> mdss_dp0_out: endpoint {
> + remote-endpoint = <&usb_dp_qmpphy_dp_in>;
> };
> };
> };
> @@ -3186,6 +3187,7 @@ port@1 {
> reg = <1>;
>
> usb_dp_qmpphy_usb_ss_in: endpoint {
> + remote-endpoint = <&usb_1_dwc3_ss>;
> };
> };
>
> @@ -3193,6 +3195,7 @@ port@2 {
> reg = <2>;
>
> usb_dp_qmpphy_dp_in: endpoint {
> + remote-endpoint = <&mdss_dp0_out>;
> };
> };
> };
> @@ -3280,6 +3283,7 @@ port@1 {
> reg = <1>;
>
> usb_1_dwc3_ss: endpoint {
> + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
> };
> };
> };
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [relevance 4%]
* Re: [PATCH 08/12] arm64: dts: qcom: sm8550: move PHY's orientation-switch to SoC dtsi
2024-04-29 12:43 20% ` [PATCH 08/12] arm64: dts: qcom: sm8550: move PHY's orientation-switch to " Dmitry Baryshkov
@ 2024-04-29 12:51 4% ` neil.armstrong
2024-04-30 9:35 4% ` Konrad Dybcio
1 sibling, 0 replies; 200+ results
From: neil.armstrong @ 2024-04-29 12:51 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 29/04/2024 14:43, Dmitry Baryshkov wrote:
> The orientation-switch of the USB+DP QMP PHY is not a property of the
> board, it is a design property of the QMP PHY itself. Move the property
> from board DTS to SoC DTSI.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 --
> arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 2 --
> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 --
> arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 1 -
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++
> 5 files changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> index f786d9114936..98934e4a81b2 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> @@ -1279,8 +1279,6 @@ &usb_dp_qmpphy {
> vdda-phy-supply = <&vreg_l3e_1p2>;
> vdda-pll-supply = <&vreg_l3f_0p88>;
>
> - orientation-switch;
> -
> status = "okay";
> };
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
> index 56800ab903a1..d3fd00176233 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
> @@ -972,8 +972,6 @@ &usb_dp_qmpphy {
> vdda-phy-supply = <&vreg_l3e_1p2>;
> vdda-pll-supply = <&vreg_l3f_0p91>;
>
> - orientation-switch;
> -
> status = "okay";
> };
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> index d0b373da39d4..1d487c42a39b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> @@ -1156,8 +1156,6 @@ &usb_dp_qmpphy {
> vdda-phy-supply = <&vreg_l3e_1p2>;
> vdda-pll-supply = <&vreg_l3f_0p88>;
>
> - orientation-switch;
> -
> status = "okay";
> };
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
> index 7a8d5c34e9e6..92a88fb05609 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
> @@ -757,7 +757,6 @@ &usb_1_hsphy {
> &usb_dp_qmpphy {
> vdda-phy-supply = <&pm8550vs_2_l3>;
> vdda-pll-supply = <&pm8550ve_l3>;
> - orientation-switch;
>
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 3ada5a30ecb7..9980504f66db 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -3170,6 +3170,8 @@ usb_dp_qmpphy: phy@88e8000 {
> #clock-cells = <1>;
> #phy-cells = <1>;
>
> + orientation-switch;
> +
> status = "disabled";
>
> ports {
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [relevance 4%]
* [PATCH 08/12] arm64: dts: qcom: sm8550: move PHY's orientation-switch to SoC dtsi
2024-04-29 12:43 7% [PATCH 00/12] arm64: dts: qcom: move common USB-related properties to SoC dtsi Dmitry Baryshkov
2024-04-29 12:43 20% ` [PATCH 04/12] arm64: dts: qcom: sm8550: move USB graph to the " Dmitry Baryshkov
@ 2024-04-29 12:43 20% ` Dmitry Baryshkov
2024-04-29 12:51 4% ` neil.armstrong
2024-04-30 9:35 4% ` Konrad Dybcio
1 sibling, 2 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-29 12:43 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Dmitry Baryshkov
The orientation-switch of the USB+DP QMP PHY is not a property of the
board, it is a design property of the QMP PHY itself. Move the property
from board DTS to SoC DTSI.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 --
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 2 --
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 --
arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 1 -
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++
5 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index f786d9114936..98934e4a81b2 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -1279,8 +1279,6 @@ &usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3f_0p88>;
- orientation-switch;
-
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 56800ab903a1..d3fd00176233 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -972,8 +972,6 @@ &usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3f_0p91>;
- orientation-switch;
-
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index d0b373da39d4..1d487c42a39b 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -1156,8 +1156,6 @@ &usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3f_0p88>;
- orientation-switch;
-
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
index 7a8d5c34e9e6..92a88fb05609 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
@@ -757,7 +757,6 @@ &usb_1_hsphy {
&usb_dp_qmpphy {
vdda-phy-supply = <&pm8550vs_2_l3>;
vdda-pll-supply = <&pm8550ve_l3>;
- orientation-switch;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 3ada5a30ecb7..9980504f66db 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3170,6 +3170,8 @@ usb_dp_qmpphy: phy@88e8000 {
#clock-cells = <1>;
#phy-cells = <1>;
+ orientation-switch;
+
status = "disabled";
ports {
--
2.39.2
^ permalink raw reply related [relevance 20%]
* [PATCH 04/12] arm64: dts: qcom: sm8550: move USB graph to the SoC dtsi
2024-04-29 12:43 7% [PATCH 00/12] arm64: dts: qcom: move common USB-related properties to SoC dtsi Dmitry Baryshkov
@ 2024-04-29 12:43 20% ` Dmitry Baryshkov
2024-04-29 12:52 4% ` neil.armstrong
2024-04-30 9:35 4% ` Konrad Dybcio
2024-04-29 12:43 20% ` [PATCH 08/12] arm64: dts: qcom: sm8550: move PHY's orientation-switch to " Dmitry Baryshkov
1 sibling, 2 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-29 12:43 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Dmitry Baryshkov
Move the graph connection between USB host, USB SS PHY and DP port to
the SoC dtsi file. They are linked in hardware in this way.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 13 -------------
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 13 -------------
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 13 -------------
arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 8 --------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++
5 files changed, 4 insertions(+), 47 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 12d60a0ee095..f786d9114936 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -940,7 +940,6 @@ &mdss_dp0 {
};
&mdss_dp0_out {
- remote-endpoint = <&usb_dp_qmpphy_dp_in>;
data-lanes = <0 1>;
};
@@ -1267,10 +1266,6 @@ &usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&vreg_l1e_0p88>;
vdda12-supply = <&vreg_l3e_1p2>;
@@ -1289,18 +1284,10 @@ &usb_dp_qmpphy {
status = "okay";
};
-&usb_dp_qmpphy_dp_in {
- remote-endpoint = <&mdss_dp0_out>;
-};
-
&usb_dp_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 3d4ad5aac70f..56800ab903a1 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -736,7 +736,6 @@ &mdss_dp0 {
&mdss_dp0_out {
data-lanes = <0 1>;
- remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
&pcie_1_phy_aux_clk {
@@ -960,10 +959,6 @@ &usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&vreg_l1e_0p88>;
vdda12-supply = <&vreg_l3e_1p2>;
@@ -982,18 +977,10 @@ &usb_dp_qmpphy {
status = "okay";
};
-&usb_dp_qmpphy_dp_in {
- remote-endpoint = <&mdss_dp0_out>;
-};
-
&usb_dp_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 92f015017418..d0b373da39d4 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -807,7 +807,6 @@ &mdss_dp0 {
&mdss_dp0_out {
data-lanes = <0 1>;
- remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
&pcie_1_phy_aux_clk {
@@ -1144,10 +1143,6 @@ &usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&vreg_l1e_0p88>;
vdda12-supply = <&vreg_l3e_1p2>;
@@ -1166,18 +1161,10 @@ &usb_dp_qmpphy {
status = "okay";
};
-&usb_dp_qmpphy_dp_in {
- remote-endpoint = <&mdss_dp0_out>;
-};
-
&usb_dp_qmpphy_out {
remote-endpoint = <&redriver_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
index 85e0d3d66e16..7a8d5c34e9e6 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
@@ -746,10 +746,6 @@ &usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&pm8550vs_2_l1>;
vdda12-supply = <&pm8550vs_2_l3>;
@@ -770,10 +766,6 @@ &usb_dp_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index bc5aeb05ffc3..3ada5a30ecb7 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2910,6 +2910,7 @@ mdss_dp0_in: endpoint {
port@1 {
reg = <1>;
mdss_dp0_out: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
};
};
@@ -3186,6 +3187,7 @@ port@1 {
reg = <1>;
usb_dp_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
};
};
@@ -3193,6 +3195,7 @@ port@2 {
reg = <2>;
usb_dp_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
};
};
};
@@ -3280,6 +3283,7 @@ port@1 {
reg = <1>;
usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
};
};
--
2.39.2
^ permalink raw reply related [relevance 20%]
* [PATCH 00/12] arm64: dts: qcom: move common USB-related properties to SoC dtsi
@ 2024-04-29 12:43 7% Dmitry Baryshkov
2024-04-29 12:43 20% ` [PATCH 04/12] arm64: dts: qcom: sm8550: move USB graph to the " Dmitry Baryshkov
2024-04-29 12:43 20% ` [PATCH 08/12] arm64: dts: qcom: sm8550: move PHY's orientation-switch to " Dmitry Baryshkov
0 siblings, 2 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-29 12:43 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Dmitry Baryshkov
Move common USB-related properties and nodes (e.g. PHY's
orientation-switch, generic endpoint connections) to the SoC file. If
the board has different needs, it has to override these generic
usecases.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Dmitry Baryshkov (12):
arm64: dts: qcom: sm8150: move USB graph to the SoC dtsi
arm64: dts: qcom: sm8350: move USB graph to the SoC dtsi
arm64: dts: qcom: sm8450: move USB graph to the SoC dtsi
arm64: dts: qcom: sm8550: move USB graph to the SoC dtsi
arm64: dts: qcom: sm8650: move USB graph to the SoC dtsi
arm64: dts: qcom: sm8350: move PHY's orientation-switch to SoC dtsi
arm64: dts: qcom: sm8450: move PHY's orientation-switch to SoC dtsi
arm64: dts: qcom: sm8550: move PHY's orientation-switch to SoC dtsi
arm64: dts: qcom: sm8650: move PHY's orientation-switch to SoC dtsi
arm64: dts: qcom: sm8650-mtp: connect USB-C SS port to QMP PHY
arm64: dts: qcom: delete wrong usb-role-switch properties
arm64: dts: qcom: x1e80100: drop wrong usb-role-switch properties
.../boot/dts/qcom/msm8953-motorola-potter.dts | 1 +
arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts | 1 +
arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts | 1 +
arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts | 1 +
arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts | 1 +
arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 1 +
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 1 -
arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts | 1 +
arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts | 1 +
.../arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts | 1 +
arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 1 +
arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 1 +
arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 13 -----------
arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++++
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 ++
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 27 +++-------------------
arch/arm64/boot/dts/qcom/sm8350.dtsi | 13 +++++++++++
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 27 +++-------------------
arch/arm64/boot/dts/qcom/sm8450.dtsi | 13 +++++++++++
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 15 ------------
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 15 ------------
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 15 ------------
.../dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 9 --------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++++
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 10 ++++----
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 15 ------------
arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +++++
arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 3 ---
arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 3 ---
29 files changed, 66 insertions(+), 142 deletions(-)
---
base-commit: dee9d87bf6c3cb70771fbc057d507bc6bd24a604
change-id: 20240425-usb-link-dtsi-33f511287192
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
^ permalink raw reply [relevance 7%]
* Linux 6.9-rc6
@ 2024-04-28 20:58 1% Linus Torvalds
0 siblings, 0 replies; 200+ results
From: Linus Torvalds @ 2024-04-28 20:58 UTC (permalink / raw)
To: Linux Kernel Mailing List
Things continue to look pretty normal, and nothing here really stands
out. The biggest single change that stands out in the diffstat is
literally a documentation update, everything else looks pretty small
and spread out.
We have the usual driver updates (mainly networking and gpu but some
updates elsewhere), some filesystem updates (mainly smb, bcachefs,
nfsd reverts, and some ntfs compat updates), and misc other fixes all
over - wifi fixes, arm dts fixlets, yadda yadda.
Nothing looks particularly big or bad. Shortlog appended for details,
please do keep testing,
Linus
---
Abdelrahman Morsy (1):
HID: mcp-2221: cancel delayed_work only when CONFIG_IIO is enabled
Akhil R (1):
dmaengine: tegra186: Fix residual calculation
Alex Deucher (1):
drm/amdgpu/sdma5.2: use legacy HDP flush for SDMA2/3
Alex Elder (1):
mailmap: add entries for Alex Elder
Alexey Brodkin (1):
ARC: [plat-hsdk]: Remove misplaced interrupt-cells property
Alice Ryhl (1):
rust: don't select CONSTRUCTORS
Andrei Simion (2):
ARM: dts: microchip: at91-sama7g5ek: Replace
regulator-suspend-voltage with the valid property
ARM: dts: microchip: at91-sama7g54_curiosity: Replace
regulator-suspend-voltage with the valid property
Andrew Jones (1):
RISC-V: selftests: cbo: Ensure asm operands match constraints, take 2
Andrey Ryabinin (1):
stackdepot: respect __GFP_NOLOCKDEP allocation flag
Andy Shevchenko (2):
idma64: Don't try to serve interrupts when device is powered off
gpio: tangier: Use correct type for the IRQ chip data
Andy Yan (1):
arm64: dts: rockchip: Fix the i2c address of es8316 on Cool Pi CM5
AngeloGioacchino Del Regno (1):
soc: mediatek: mtk-svs: Append "-thermal" to thermal zone names
Arkadiusz Kubalewski (1):
dpll: fix dpll_pin_on_pin_register() for multiple parent pins
Arnd Bergmann (2):
dmaengine: owl: fix register access functions
mtd: diskonchip: work around ubsan link failure
Arınç ÜNAL (1):
arm64: dts: rockchip: set PHY address of MT7531 switch to 0x1f
Aswin Unnikrishnan (1):
rust: remove `params` from `module` macro example
Avraham Stern (1):
wifi: iwlwifi: mvm: remove old PASN station when adding a new one
Baoquan He (1):
LoongArch: Fix Kconfig item and left code related to CRASH_CORE
Bartosz Golaszewski (1):
Bluetooth: qca: set power_ctrl_enabled on NULL returned by
gpiod_get_optional()
Ben Zong-You Xie (1):
perf riscv: Fix the warning due to the incompatible type
Benjamin Tissoires (1):
MAINTAINERS: update Benjamin's email address
Benno Lossin (1):
rust: macros: fix soundness issue in `module!` macro
Bibo Mao (1):
LoongArch: Lately init pmu after smp is online
Bjorn Helgaas (1):
ARC: Fix typos
Bo-Wei Chen (1):
docs: rust: fix improper rendering in Arch Support page
Christian Brauner (3):
ntfs3: serve as alias for the legacy ntfs driver
ntfs3: enforce read-only when used as legacy ntfs driver
ntfs3: add legacy ntfs file operations
Christian Gmeiner (1):
Revert "drm/etnaviv: Expose a few more chipspecs to userspace"
Christian Marangi (2):
mtd: rawnand: qcom: Fix broken OP_RESET_DEVICE command in
qcom_misc_cmd_type_exec()
mtd: limit OTP NVMEM cell parse to non-NAND devices
Christoph Müllner (2):
riscv: thead: Rename T-Head PBMT to MAE
riscv: T-Head: Test availability bit before enabling MAE errata
Chuck Lever (3):
Revert "svcrdma: Add Write chunk WRs to the RPC's Send WR chain"
Revert "NFSD: Reschedule CB operations when backchannel rpc_clnt
is shut down"
Revert "NFSD: Convert the callback workqueue to use delayed_work"
Chun-Yi Lee (1):
Bluetooth: hci_sync: Using hci_cmd_sync_submit when removing Adv Monitor
Clément Léger (2):
riscv: hwprobe: fix invalid sign extension for RISCV_HWPROBE_EXT_ZVFHMIN
selftests: sud_test: return correct emulated syscall value on RISC-V
Conor Dooley (1):
rust: make mutually exclusive with CFI_CLANG
Cristian Ciocaltea (1):
phy: phy-rockchip-samsung-hdptx: Select CONFIG_RATIONAL
Dan Carpenter (1):
net: ti: icssg-prueth: Fix signedness bug in prueth_init_rx_chns()
Dan Williams (1):
cxl/core: Fix potential payload size confusion in cxl_mem_get_poison()
Daniel Golle (2):
soc: mediatek: mtk-socinfo: depends on CONFIG_SOC_BUS
net: phy: mediatek-ge-soc: follow netdev LED trigger semantics
Daniel Okazaki (1):
eeprom: at24: fix memory corruption race condition
Daniele Palmas (1):
net: usb: qmi_wwan: add Telit FN920C04 compositions
David Bauer (1):
vxlan: drop packets from invalid src-address
David Christensen (1):
MAINTAINERS: eth: mark IBM eHEA as an Orphan
David Hildenbrand (1):
LoongArch: Fix a build error due to __tlb_remove_tlb_entry()
David Howells (4):
cifs: Fix reacquisition of volume cookie on still-live connection
cifs: Add tracing for the cifs_tcon struct refcounting
netfs: Fix writethrough-mode error handling
netfs: Fix the pre-flush when appending to a file in writethrough mode
David Kaplan (1):
x86/cpu: Fix check for RDPKRU in __show_regs()
David Sterba (1):
btrfs: remove colon from messages with state
Derek Foreman (1):
drm/etnaviv: fix tx clock gating on some GC7000 variants
Dragan Simic (2):
arm64: dts: rockchip: Remove unsupported node from the Pinebook Pro dts
arm64: dts: rockchip: Designate the system power controller on QuartzPro64
Duanqiang Wen (3):
net: libwx: fix alloc msix vectors failed
Revert "net: txgbe: fix i2c dev name cannot match clkdev"
Revert "net: txgbe: fix clk_name exceed MAX_DEV_ID limits"
Duoming Zhou (1):
ax25: Fix netdev refcount issue
Edward Liaw (1):
selftests/harness: remove use of LINE_MAX
Eric Dumazet (4):
icmp: prevent possible NULL dereferences from icmp_build_probe()
net: fix sk_memory_allocated_{add|sub} vs softirqs
ipv4: check for NULL idev in ip_route_use_hint()
net: usb: ax88179_178a: stop lying about skb->truesize
Eric Van Hensbergen (1):
fs/9p: mitigate inode collisions
Erwan Velu (1):
i40e: Report MFS in decimal base instead of hex
Felix Fietkau (1):
wifi: mac80211: split mesh fast tx cache into local/proxied/forwarded
Felix Kuehling (3):
drm/amdkfd: Fix eviction fence handling
drm/amdgpu: Update BO eviction priorities
drm/amdkfd: Fix rescheduling of restore worker
Fenghua Yu (1):
dmaengine: idxd: Fix oops during rmmod on single-CPU platforms
Gabor Juhos (1):
phy: qcom: m31: match requested regulator name with dt schema
Geert Uytterhoeven (1):
net: ravb: Fix registered interrupt names
Guanrui Huang (1):
irqchip/gic-v3-its: Prevent double free on error
Guenter Roeck (1):
MAINTAINERS: Drop entry for PCA9541 bus master selector
Gustavo A. R. Silva (1):
smb: client: Fix struct_group() usage in __packed structs
Günther Noack (1):
fs: Return ENOTTY directly if FS_IOC_GETUUID or FS_IOC_GETFSSYSFSPATH fail
Hangbin Liu (1):
bridge/br_netlink.c: no need to return void function
Hans de Goede (1):
phy: ti: tusb1210: Resolve charger-det crash if charger psy is
unregistered
Himal Prasad Ghimiray (2):
drm/xe: Remove sysfs only once on action add failure
drm/xe: call free_gsc_pkt only once on action add failure
Huacai Chen (1):
LoongArch: Fix callchain parse error with kernel tracepoint events
Hyunwoo Kim (3):
tcp: Fix Use-After-Free in tcp_ao_connect_init
net: gtp: Fix Use-After-Free in gtp_dellink
net: openvswitch: Fix Use-After-Free in ovs_ct_exit
Ido Schimmel (12):
mlxsw: core: Unregister EMAD trap using FORWARD action
mlxsw: core_env: Fix driver initialization with old firmware
mlxsw: pci: Fix driver initialization with old firmware
mlxsw: spectrum_acl_tcam: Fix race in region ID allocation
mlxsw: spectrum_acl_tcam: Fix race during rehash delayed work
mlxsw: spectrum_acl_tcam: Fix possible use-after-free during
activity update
mlxsw: spectrum_acl_tcam: Fix possible use-after-free during rehash
mlxsw: spectrum_acl_tcam: Rate limit error message
mlxsw: spectrum_acl_tcam: Fix memory leak during rehash
mlxsw: spectrum_acl_tcam: Fix warning during rehash
mlxsw: spectrum_acl_tcam: Fix incorrect list API usage
mlxsw: spectrum_acl_tcam: Fix memory leak when canceling rehash work
Igor Artemiev (1):
wifi: cfg80211: fix the order of arguments for trace events of
the tx_rx_evt class
Ikjoon Jang (1):
arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg
Iskander Amara (2):
arm64: dts: rockchip: enable internal pull-up for Q7_THRM# on RK3399 Puma
arm64: dts: rockchip: fix alphabetical ordering RK3399 puma
Ismael Luceno (1):
ipvs: Fix checksumming on GSO of SCTP packets
Jack Xiao (1):
drm/amdgpu/mes: fix use-after-free issue
Jacob Keller (1):
ice: fix LAG and VF lock dependency in ice_reset_vf()
Jakub Kicinski (2):
tools: ynl: don't ignore errors in NLMSG_DONE messages
eth: bnxt: fix counting packets discarded due to OOM and netpoll
Jarred White (1):
ACPI: CPPC: Fix bit_offset shift in MASK_VAL() macro
Jason Reeder (1):
net: ethernet: ti: am65-cpts: Fix PTPv1 message type on TX packets
Jiantao Shan (1):
LoongArch: Fix access error when read fault on a write-only VMA
Johan Hovold (5):
phy: qcom: qmp-combo: fix VCO div offset on v5_5nm and v6
arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
Bluetooth: qca: fix invalid device address check
Bluetooth: qca: fix NULL-deref on non-serdev suspend
Bluetooth: qca: fix NULL-deref on non-serdev setup
Johannes Berg (12):
wifi: mac80211: check EHT/TTLM action frame length
wifi: mac80211: don't use rate mask for scanning
Revert "wifi: iwlwifi: bump FW API to 90 for BZ/SC devices"
wifi: mac80211: fix idle calculation with multi-link
wifi: mac80211: mlme: re-parse with correct mode
wifi: mac80211: mlme: fix memory leak
wifi: mac80211: mlme: re-parse if AP mode is less than client
wifi: nl80211: don't free NULL coalescing rule
wifi: mac80211_hwsim: init peer measurement result
wifi: mac80211: remove link before AP
wifi: mac80211: fix unaligned le16 access
wifi: iwlwifi: mvm: fix link ID management
Johannes Thumshirn (1):
btrfs: fix information leak in btrfs_ioctl_logical_to_ino()
Johannes Weiner (1):
mm: zswap: fix shrinker NULL crash with cgroup_disable=memory
Jose Ignacio Tornos Martinez (1):
arm64: dts: rockchip: regulator for sd needs to be always on for BPI-R2Pro
Joshua Ashton (1):
drm/amd/display: Set color_mgmt_changed to true on unsuspend
Justin Chen (1):
net: bcmasp: fix memory leak when bringing down interface
Kalle Valo (1):
wifi: ath11k: use RCU when accessing struct inet6_dev::ac_list
Kenny Levinsen (1):
HID: i2c-hid: Revert to await reset ACK before reading report descriptor
Kent Overstreet (14):
bcachefs: Fix null ptr deref in twf from BCH_IOCTL_FSCK_OFFLINE
bcachefs: node scan: ignore multiple nodes with same seq if interior
bcachefs: make sure to release last journal pin in replay
bcachefs: Fix bch2_dev_btree_bitmap_marked_sectors() shift
bcachefs: KEY_TYPE_error is allowed for reflink
bcachefs: fix leak in bch2_gc_write_reflink_key
bcachefs: Fix bio alloc in check_extent_checksum()
bcachefs: Check for journal entries overruning end of sb clean section
bcachefs: Fix missing call to bch2_fs_allocator_background_exit()
bcachefs: bkey_cached.btree_trans_barrier_seq needs to be a ulong
bcachefs: Tweak btree key cache shrinker so it actually frees
bcachefs: Fix deadlock in journal write path
bcachefs: Fix inode early destruction path
bcachefs: If we run merges at a lower watermark, they must be nonblocking
Kirill A. Shutemov (1):
x86/tdx: Preserve shared bit on mprotect()
Krzysztof Kozlowski (4):
arm64: dts: rockchip: drop panel port unit address in GRU Scarlet
arm64: dts: rockchip: drop redundant pcie-reset-suspend in Scarlet Dumo
arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 1
arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 2
Kuniyuki Iwashima (1):
af_unix: Suppress false-positive lockdep splat for spin_lock()
in __unix_gc().
Laine Taffin Altman (1):
rust: init: remove impl Zeroable for Infallible
Lang Yu (2):
drm/amdkfd: make sure VM is ready for updating operations
drm/amdgpu/umsch: don't execute umsch test when GPU is in reset/suspend
Lijo Lazar (2):
drm/amdgpu: Assign correct bits for SDMA HDP flush
drm/amd/pm: Restore config space after reset
Linus Torvalds (1):
Linux 6.9-rc6
Louis Chauvet (1):
dmaengine: xilinx: xdma: Fix synchronization issue
Luca Weiss (1):
arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocs
Lucas Stach (1):
drm/atomic-helper: fix parameter order in
drm_format_conv_state_copy() call
Luiz Augusto von Dentz (3):
Bluetooth: hci_sync: Use advertised PHYs on hci_le_ext_create_conn_sync
Bluetooth: hci_event: Fix sending HCI_OP_READ_ENC_KEY_SIZE
Bluetooth: MGMT: Fix failing to MGMT_OP_ADD_UUID/MGMT_OP_REMOVE_UUID
Lukas Wunner (1):
igc: Fix LED-related deadlock on driver unbind
MD Danish Anwar (1):
net: phy: dp83869: Fix MII mode failure
Ma Jun (1):
drm/amdgpu/pm: Remove gpu_od if it's an empty directory
Maksim Kiselev (1):
mmc: sdhci-of-dwcmshc: th1520: Increase tuning loop count to 128
Manivannan Sadhasivam (3):
arm64: dts: qcom: sm8450: Fix the msi-map entries
arm64: dts: qcom: sm8550: Fix the msi-map entries
arm64: dts: qcom: sm8650: Fix the msi-map entries
Mantas Pucka (1):
mmc: sdhci-msm: pervent access to suspended controller
Marcel Ziswiler (1):
phy: freescale: imx8m-pcie: fix pcie link-up instability
Marek Vasut (1):
arm64: dts: imx8mp: Fix assigned-clocks for second CSI2
Marios Makassikis (1):
ksmbd: clear RENAME_NOREPLACE before calling vfs_rename
Matthew Sakai (1):
dm vdo murmurhash: remove unneeded semicolon
Matthew Wilcox (Oracle) (3):
mm: create FOLIO_FLAG_FALSE and FOLIO_TYPE_OPS macros
mm: support page_mapcount() on page_has_type() pages
mm: turn folio_test_hugetlb into a PageType
Matthias Schiffer (1):
net: dsa: mv88e6xx: fix supported_interfaces setup in
mv88e6250_phylink_get_caps()
Maximilian Luz (2):
firmware: qcom: uefisecapp: Fix memory related IO errors and crashes
arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller
Miaohe Lin (1):
mm/hugetlb: fix DEBUG_LOCKS_WARN_ON(1) when dissolve_free_hugetlb_folio()
Michael Chan (1):
bnxt_en: Fix error recovery for 5760X (P7) chips
Michael Heimpold (1):
ARM: dts: imx6ull-tarragon: fix USB over-current polarity
Michal Tomek (1):
phy: rockchip-snps-pcie3: fix bifurcation on rk3588
Michal Wajdeczko (1):
drm/xe/guc: Fix arguments passed to relay G2H handlers
Miguel Ojeda (2):
kbuild: rust: remove unneeded `@rustc_cfg` to avoid ICE
kbuild: rust: force `alloc` extern to allow "empty" Rust files
Mikhail Kobuk (2):
phy: marvell: a3700-comphy: Fix out of bounds read
phy: marvell: a3700-comphy: Fix hardcoded array size
Ming Lei (1):
dm: restore synchronous close of device mapper block device
Miquel Raynal (2):
dmaengine: xilinx: xdma: Fix wrong offsets in the buffers
addresses in dma descriptor
dmaengine: xilinx: xdma: Clarify kdoc in XDMA driver
Miri Korenblit (1):
wifi: iwlwifi: mvm: return uid from iwl_mvm_build_scan_cmd
Muhammad Usama Anjum (2):
selftests: mm: fix unused and uninitialized variable warning
selftests: mm: protection_keys: save/restore nr_hugepages value
from launch script
Muhammed Efe Cetin (1):
arm64: dts: rockchip: mark system power controller and fix typo
on orangepi-5-plus
Mukul Joshi (2):
drm/amdgpu: Fix leak when GPU memory allocation fails
drm/amdkfd: Add VRAM accounting for SVM migration
Nam Cao (2):
HID: i2c-hid: remove I2C_HID_READ_PENDING flag to prevent lock-up
fbdev: fix incorrect address computation in deferred IO
Namjae Jeon (4):
ksmbd: fix slab-out-of-bounds in smb2_allocate_rsp_buf
ksmbd: validate request buffer size in smb2_allocate_rsp_buf()
ksmbd: common: use struct_group_attr instead of struct_group for
network_open_info
ksmbd: add continuous availability share parameter
Naohiro Aota (1):
btrfs: scrub: run relocation repair when/only needed
Nathan Chancellor (2):
bcachefs: Fix format specifier in validate_bset_keys()
Bluetooth: Fix type of len in {l2cap,sco}_sock_getsockopt_old()
Nuno Pereira (1):
HID: nintendo: Fix N64 controller being identified as mouse
Nícolas F. R. A. Prado (5):
arm64: dts: mediatek: mt8192: Add missing gce-client-reg to mutex
arm64: dts: mediatek: mt8195: Add missing gce-client-reg to vpp/vdosys
arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex
arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex1
arm64: dts: mediatek: cherry: Describe CPU supplies
Oleg Nesterov (2):
sched/isolation: Prevent boot crash when the boot CPU is nohz_full
sched/isolation: Fix boot crash when maxcpus < first housekeeping CPU
Pablo Neira Ayuso (1):
netfilter: nf_tables: honor table dormant flag from netdev
release event path
Patrik Jakobsson (1):
drm/gma500: Remove lid code
Paul Geurts (1):
NFC: trf7970a: disable all regulators on removal
Paulo Alcantara (1):
smb: client: fix rename(2) regression against samba
Peter Münster (1):
net: b44: set pause params only when interface is up
Peter Xu (1):
mm/hugetlb: fix missing hugetlb_lock for resv uncharge
Peyton Lee (1):
drm/amdgpu/vpe: fix vpe dpm setup failed
Pin-yen Lin (4):
arm64: dts: mediatek: mt8192-asurada: Update min voltage
constraint for MT6315
arm64: dts: mediatek: mt8195-cherry: Update min voltage
constraint for MT6315
arm64: dts: mediatek: mt8183-kukui: Use default min voltage for MT6358
arm64: dts: mediatek: mt8186-corsola: Update min voltage
constraint for Vgpu
Prathamesh Shete (1):
gpio: tegra186: Fix tegra186_gpio_is_accessible() check
Prike Liang (1):
drm/amdgpu: Fix the ring buffer size for queue VM flush
Qu Wenruo (1):
btrfs: fix wrong block_start calculation for btrfs_drop_extent_map_range()
Quentin Schulz (3):
arm64: dts: rockchip: enable internal pull-up on Q7_USB_ID for RK3399 Puma
arm64: dts: rockchip: enable internal pull-up on PCIE_WAKE# for
RK3399 Puma
arm64: dts: rockchip: add regulators for PCIe on RK3399 Puma Haikou
Rafael J. Wysocki (1):
ACPI: PM: s2idle: Evaluate all Low-Power S0 Idle _DSM functions
Rafał Miłecki (9):
arm64: dts: mediatek: mt7622: fix clock controllers
arm64: dts: mediatek: mt7622: fix IR nodename
arm64: dts: mediatek: mt7622: fix ethernet controller "compatible"
arm64: dts: mediatek: mt7622: drop "reset-names" from thermal block
arm64: dts: mediatek: mt7986: drop invalid properties from ethsys
arm64: dts: mediatek: mt7986: drop "#reset-cells" from Ethernet controller
arm64: dts: mediatek: mt7986: drop invalid thermal block clock
arm64: dts: mediatek: mt7986: prefix BPI-R3 cooling maps with "map-"
arm64: dts: mediatek: mt2712: fix validation errors
Rahul Rameshbabu (4):
macsec: Enable devices to advertise whether they update sk_buff
md_dst during offloads
ethernet: Add helper for assigning packet type when dest address
does not match device address
macsec: Detect if Rx skb is macsec-related for offloading
devices that update md_dst
net/mlx5e: Advertise mlx5 ethernet driver updates sk_buff md_dst
for MACsec
Rajendra Nayak (1):
arm64: dts: qcom: x1e80100: Fix the compatible for cluster idle states
Rex Zhang (1):
dmaengine: idxd: Convert spinlock to mutex to lock evl workqueue
Richard Kinder (1):
wifi: mac80211: ensure beacon is non-S1G prior to extracting the
beacon timestamp field
Rob Herring (3):
dt-bindings: rockchip: grf: Add missing type to 'pcie-phy' node
dt-bindings: eeprom: at24: Fix ST M24C64-D compatible schema
arm64: dts: rockchip: Fix USB interface compatible string on
kobol-helios64
Sabrina Dubroca (1):
tls: fix lockless read of strp->msg_ready in ->poll
Samuel Holland (2):
riscv: Fix TASK_SIZE on 64-bit NOMMU
riscv: Fix loading 64-bit NOMMU kernels past the start of RAM
Sean Anderson (1):
dma: xilinx_dpdma: Fix locking
Sean Christopherson (2):
cpu: Re-enable CPU mitigations by default for !X86 architectures
cpu: Ignore "mitigations" kernel parameter if CPU_MITIGATIONS=n
Sean Wang (1):
Bluetooth: btusb: mediatek: Fix double free of skb in coredump
Sebastian Reichel (2):
phy: rockchip-snps-pcie3: fix clearing PHP_GRF_PCIESEL_CON bits
phy: rockchip: naneng-combphy: Fix mux on rk3588
Sergei Antonov (1):
mmc: moxart: fix handling of sgm->consumed, otherwise WARN_ON triggers
Sindhu Devale (1):
i40e: Do not use WQ_MEM_RECLAIM flag for workqueue
Stephen Boyd (2):
phy: qcom: qmp-combo: Fix VCO div offset on v3
phy: qcom: qmp-combo: Fix register base for QSERDES_DP_PHY_MODE
Steve French (2):
smb3: missing lock when picking channel
smb3: fix lock ordering potential deadlock in cifs_sync_mid_result
Su Hui (1):
octeontx2-af: fix the double free in rvu_npc_freemem()
Sudheer Mogilappagari (1):
iavf: Fix TC config comparison with existing adapter TC config
Sweet Tea Dorminy (1):
btrfs: fallback if compressed IO fails for ENOSPC
Takayuki Nagata (1):
cifs: reinstate original behavior again for forceuid/forcegid
Tetsuo Handa (1):
profiling: Remove create_prof_cpu_mask().
Thorsten Leemhuis (6):
docs: verify/bisect: use git switch, tag kernel, and various fixes
docs: verify/bisect: add and fetch stable branches ahead of time
docs: verify/bisect: proper headlines and more spacing
docs: verify/bisect: explain testing reverts, patches and newer code
docs: verify/bisect: describe how to use a build host
docs: verify/bisect: stable regressions: first stable, then mainline
Tianchen Ding (2):
sched/eevdf: Always update V if se->on_rq when reweighting
sched/eevdf: Fix miscalculation in reweight_entity() when se is not curr
Tom Lendacky (1):
x86/sev: Check for MWAITX and MONITORX opcodes in the #VC handler
Uwe Kleine-König (1):
MAINTAINERS: Update Uwe's email address, drop SIOX maintenance
Vanshidhar Konda (1):
ACPI: CPPC: Fix access width used for PCC registers
Vijendar Mukunda (1):
soundwire: amd: fix for wake interrupt handling for clockstop mode
Vikas Gupta (2):
bnxt_en: refactor reset close code
bnxt_en: Fix the PCI-AER routines
Vineet Gupta (2):
ARC: Fix -Wmissing-prototypes warnings
ARC: mm: fix new code about cache aliasing
Vinod Koul (1):
dmaengine: Revert "dmaengine: pl330: issue_pending waits until WFP state"
Vishal Moola (Oracle) (1):
hugetlb: check for anon_vma prior to folio allocation
WangYuli (1):
Bluetooth: btusb: Add Realtek RTL8852BE support ID 0x0bda:0x4853
Wedson Almeida Filho (2):
rust: phy: implement `Send` for `Registration`
rust: kernel: require `Send` for `Module` implementations
Wenkuan Wang (1):
x86/CPU/AMD: Add models 0x10-0x1f to the Zen5 range
William Zhang (1):
mtd: rawnand: brcmnand: Fix data access violation for STB chip
Wolfram Sang (1):
i2c: smbus: fix NULL function pointer dereference
Xuewen Yan (1):
sched/eevdf: Prevent vlag from going out of bounds in reweight_eevdf()
Yaraslau Furman (1):
HID: logitech-dj: allow mice to use all types of reports
Yick Xie (1):
udp: preserve the connected status if only UDP cmsg
Yu Kuai (1):
block: fix module reference leakage from bdev_open_by_dev error path
Zhang Lixu (1):
HID: intel-ish-hid: ipc: Fix dev_err usage with uninitialized dev->devc
Zhu Lingshan (1):
vDPA: code clean for vhost_vdpa uapi
Zijun Hu (1):
Bluetooth: btusb: Fix triggering coredump implementation for QCA
^ permalink raw reply [relevance 1%]
* Re: [PATCH 10/10] arm64: dts: qcom: Add AYN Odin 2
2024-04-25 6:28 0% ` Krzysztof Kozlowski
@ 2024-04-28 3:54 0% ` Xilin Wu
0 siblings, 0 replies; 200+ results
From: Xilin Wu @ 2024-04-28 3:54 UTC (permalink / raw)
To: Krzysztof Kozlowski, Uwe Kleine-König, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Junhao Xie, Neil Armstrong,
Jessica Zhang, Sam Ravnborg, David Airlie, Daniel Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Bjorn Andersson, Konrad Dybcio, Tengfei Fan, Molly Sophia
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm
On 2024/4/25 14:28, Krzysztof Kozlowski wrote:
> On 24/04/2024 17:29, Xilin Wu via B4 Relay wrote:
>> From: Xilin Wu <wuxilin123@gmail.com>
>>
>> AYN Odin 2 is a gaming handheld based on QCS8550, which is derived
>> from SM8550 but without modem RF system.
>>
>
>
>
>> +
>> +/ {
>> + model = "AYN Odin 2";
>> + compatible = "ayn,odin2", "qcom,qcs8550", "qcom,sm8550";
>> + chassis-type = "handset";
>> +
>> + qcom,msm-id = <QCOM_ID_QCS8550 0x20000>;
>> + qcom,board-id = <0x1001f 0>;
>
> No, these are not allowed. You did not test your dts.
>
> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check W=1` (see
> Documentation/devicetree/bindings/writing-schema.rst or
> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
> for instructions).
>
>> +
>> + aliases {
>> + serial0 = &uart7;
>> + serial1 = &uart14;
>> + serial2 = &uart15;
>> + };
>> +
>> + backlight: backlight {
>> + compatible = "pwm-backlight";
>> + pwms = <&pmk8550_pwm 0 860000>;
>> + brightness-levels = <1023 0>;
>> + num-interpolated-steps = <1023>;
>> + default-brightness-level = <600>;
>> + power-supply = <&vph_pwr>;
>> + enable-gpios = <&pmk8550_gpios 5 GPIO_ACTIVE_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pwm_backlight_default>;
>> + status = "okay";
>
> Drop, why do you need it? Do you see it anywhere else in the backlight
> nodes in DTS?
>
>
>> + };
>> +
>> + fan_pwr: fan-pwr-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "fan_pwr";
>> +
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> +
>> + gpio = <&tlmm 109 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&fan_pwr_en>;
>> +
>> + regulator-state-mem {
>> + regulator-off-in-suspend;
>> + };
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> +
>> + pinctrl-0 = <&volume_up_n>, <&m1_m2_keys_default>;
>> + pinctrl-names = "default";
>> +
>> + key-volume-up {
>> + label = "Volume Up";
>> + linux,code = <KEY_VOLUMEUP>;
>> + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
>> + debounce-interval = <15>;
>> + linux,can-disable;
>> + wakeup-source;
>> + };
>> +
>> + m1-button {
>> + label = "M1";
>> + linux,code = <BTN_TRIGGER_HAPPY1>;
>> + gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
>> + };
>> +
>> + m2-button {
>> + label = "M2";
>> + linux,code = <BTN_TRIGGER_HAPPY2>;
>> + gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
>> + };
>> + };
>> +
>> + hdmi-out {
>> + compatible = "hdmi-connector";
>> + type = "d";
>> + hpd-gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>;
>> +
>> + port {
>> + hdmi_con: endpoint {
>> + remote-endpoint = <<8912_out>;
>> + };
>> + };
>> + };
>> +
>> + hdmi_pwr: hdmi-pwr-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "hdmi_pwr";
>> +
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> +
>> + gpio = <&tlmm 10 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + };
>> +
>> + vdd_lcm_2p8: vdd-lcm-2p8-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vdd_lcm_2p8";
>> +
>> + regulator-min-microvolt = <2800000>;
>> + regulator-max-microvolt = <2800000>;
>> +
>> + gpio = <&tlmm 142 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + };
>> +
>> + led_left_side: led-controller-1 {
>> + compatible = "pwm-leds-multicolor";
>> +
>> + multi-led {
>> + label = "left-side";
>> + color = <LED_COLOR_ID_RGB>;
>> + max-brightness = <255>;
>> +
>> + led-red {
>> + color = <LED_COLOR_ID_RED>;
>> + pwms = <&pwm_rgb_left 0>;
>> + };
>> +
>> + led-green {
>> + color = <LED_COLOR_ID_GREEN>;
>> + pwms = <&pwm_rgb_left 1>;
>> + };
>> +
>> + led-blue {
>> + color = <LED_COLOR_ID_BLUE>;
>> + pwms = <&pwm_rgb_left 2>;
>> + };
>> + };
>> + };
>> +
>> + led_left_joystick: led-controller-2 {
>> + compatible = "pwm-leds-multicolor";
>> +
>> + multi-led {
>> + label = "left-joystick";
>> + color = <LED_COLOR_ID_RGB>;
>> + max-brightness = <255>;
>> +
>> + led-red {
>> + color = <LED_COLOR_ID_RED>;
>> + pwms = <&pwm_rgb_left 6>;
>> + };
>> +
>> + led-green {
>> + color = <LED_COLOR_ID_GREEN>;
>> + pwms = <&pwm_rgb_left 7>;
>> + };
>> +
>> + led-blue {
>> + color = <LED_COLOR_ID_BLUE>;
>> + pwms = <&pwm_rgb_left 8>;
>> + };
>> + };
>> + };
>> +
>> + led_right_side: led-controller-3 {
>> + compatible = "pwm-leds-multicolor";
>> +
>> + multi-led {
>> + label = "right-side";
>> + color = <LED_COLOR_ID_RGB>;
>> + max-brightness = <255>;
>> +
>> + led-red {
>> + color = <LED_COLOR_ID_RED>;
>> + pwms = <&pwm_rgb_right 0>;
>> + };
>> +
>> + led-green {
>> + color = <LED_COLOR_ID_GREEN>;
>> + pwms = <&pwm_rgb_right 1>;
>> + };
>> +
>> + led-blue {
>> + color = <LED_COLOR_ID_BLUE>;
>> + pwms = <&pwm_rgb_right 2>;
>> + };
>> + };
>> + };
>> +
>> + led_right_joystick: led-controller-4 {
>> + compatible = "pwm-leds-multicolor";
>> +
>> + multi-led {
>> + label = "right-joystick";
>> + color = <LED_COLOR_ID_RGB>;
>> + max-brightness = <255>;
>> +
>> + led-red {
>> + color = <LED_COLOR_ID_RED>;
>> + pwms = <&pwm_rgb_right 6>;
>> + };
>> +
>> + led-green {
>> + color = <LED_COLOR_ID_GREEN>;
>> + pwms = <&pwm_rgb_right 7>;
>> + };
>> +
>> + led-blue {
>> + color = <LED_COLOR_ID_BLUE>;
>> + pwms = <&pwm_rgb_right 8>;
>> + };
>> + };
>> + };
>> +
>> + mcu_3v3: mcu-3v3-regulator {
>
> Name all regulators regulator-n, where n is decimal number. Then order
> the nodes by name.
>
>
> ...
>
>> +
>> +&i2c4 {
>> + clock-frequency = <400000>;
>> + status = "okay";
>> +
>> + touchscreen@20 {
>> + compatible = "syna,rmi4-i2c";
>> + reg = <0x20>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + interrupts-extended = <&tlmm 25 0x2008>;
>> +
>> + pinctrl-names = "default", "sleep";
>> + pinctrl-0 = <&ts_int_default>;
>> + pinctrl-1 = <&ts_int_sleep>;
>> +
>> + vio-supply = <&vreg_l12b_1p8>;
>> +
>> + syna,startup-delay-ms = <200>;
>> + syna,reset-delay-ms = <200>;
>> +
>> + rmi4-f01@1 {
>> + syna,nosleep-mode = <0x1>;
>> + reg = <0x1>;
>> + };
>> +
>> + rmi4-f12@12 {
>> + reg = <0x12>;
>> + syna,rezero-wait-ms = <20>;
>> + syna,clip-x-low = <0>;
>> + syna,clip-y-low = <0>;
>> + syna,clip-x-high = <1080>;
>> + syna,clip-y-high = <1920>;
>> + syna,sensor-type = <1>;
>> + touchscreen-inverted-x;
>> + };
>> + };
>
> Please confirm the status of dtbs_check for your board. I am pretty sure
> it fails.
>
> Best regards,
> Krzysztof
>
I will correct all the mistakes in v2. Thanks for catching them!
--
Thanks,
Xilin Wu
^ permalink raw reply [relevance 0%]
* Re: [PATCH 07/10] arm64: dts: qcom: sm8550: Update EAS properties
2024-04-24 22:45 4% ` Bryan O'Donoghue
@ 2024-04-28 3:43 4% ` Xilin Wu
0 siblings, 0 replies; 200+ results
From: Xilin Wu @ 2024-04-28 3:43 UTC (permalink / raw)
To: Bryan O'Donoghue, Uwe Kleine-König, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Junhao Xie, Neil Armstrong,
Jessica Zhang, Sam Ravnborg, David Airlie, Daniel Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Bjorn Andersson, Konrad Dybcio, Tengfei Fan, Molly Sophia
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm
On 2024/4/25 6:45, Bryan O'Donoghue wrote:
> On 24/04/2024 16:29, Xilin Wu via B4 Relay wrote:
>> From: Xilin Wu <wuxilin123@gmail.com>
>>
>> The original values provided by Qualcomm appear to be quite
>> inaccurate. Specifically, some heavy gaming tasks could be
>> improperly assigned to the A510 cores by the scheduler, resulting
>> in a CPU bottleneck. This update to the EAS properties aims to
>> enhance the user experience across various scenarios.
>>
>> The power numbers were obtained using a Type-C power meter, which
>> was directly connected to the battery connector on the AYN Odin 2
>> motherboard, acting as a fake battery.
>>
>> It should be noted that the A715 cores seem less efficient than the
>> A710 cores. Therefore, an average value has been assigned to them,
>> considering that the A715 and A710 cores share a single cpufreq
>> domain.
>>
>> Cortex-A510 cores:
>> 441 kHz, 564 mV, 43 mW, 350 Cx
>> 556 kHz, 580 mV, 59 mW, 346 Cx
>> 672 kHz, 592 mV, 71 mW, 312 Cx
>> 787 kHz, 604 mV, 83 mW, 290 Cx
>> 902 kHz, 608 mV, 96 mW, 288 Cx
>> 1017 kHz, 624 mV, 107 mW, 264 Cx
>> 1113 kHz, 636 mV, 117 mW, 252 Cx
>> 1228 kHz, 652 mV, 130 mW, 240 Cx
>> 1344 kHz, 668 mV, 146 mW, 235 Cx
>> 1459 kHz, 688 mV, 155 mW, 214 Cx
>> 1555 kHz, 704 mV, 166 mW, 205 Cx
>> 1670 kHz, 724 mV, 178 mW, 192 Cx
>> 1785 kHz, 744 mV, 197 mW, 189 Cx
>> 1900 kHz, 764 mV, 221 mW, 190 Cx
>> 2016 kHz, 784 mV, 243 mW, 188 Cx
>> Your dynamic-power-coefficient for cpu 1: 251
>
> This looks pretty convincing and like good work.
>
> A few questions and suggestions for your commit log.
>
> I'd really love to know more about how you ran this test. What values
> exactly does your power meter give you?
>
> How did you lock the core to a specific CPU frequency ?
>
> Maybe also give the equation to calculate Pdyn in the commit log.
>
> https://patchwork.kernel.org/project/linux-arm-kernel/patch/1500974575-2244-1-git-send-email-wxt@rock-chips.com/#20763985
>
> ---
> bod
The power meter accepts a fixed 4 volts input, and outputs to the
battery connector on the board. It is also connected to a computer for
data recording, including voltage and current.
The CPU frequency pinning and Pdyn calculation is done by a script on
the list: [1]. I just removed the power measuring part since it was done
on the computer with the meter.
I will improve the commit log in v2.
[1]
https://lore.kernel.org/all/CAD=FV=U1FP0e3_AVHpauUUZtD-5X3XCwh5aT9fH_8S_FFML2Uw@mail.gmail.com/
--
Thanks,
Xilin Wu
^ permalink raw reply [relevance 4%]
* Re: [PATCH v2 0/4] clk: qcom: dispcc: fix DisplayPort link clocks
2024-04-24 1:39 6% [PATCH v2 0/4] clk: qcom: dispcc: fix DisplayPort link clocks Dmitry Baryshkov
2024-04-24 1:39 16% ` [PATCH v2 3/4] clk: qcom: dispcc-sm8550: fix DisplayPort clocks Dmitry Baryshkov
@ 2024-04-27 19:34 4% ` Bjorn Andersson
1 sibling, 0 replies; 200+ results
From: Bjorn Andersson @ 2024-04-27 19:34 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Konrad Dybcio, Konrad Dybcio,
Neil Armstrong, Dmitry Baryshkov
Cc: linux-arm-msm, linux-clk, linux-kernel, Luca Weiss
On Wed, 24 Apr 2024 04:39:28 +0300, Dmitry Baryshkov wrote:
> On several Qualcomm platforms DisplayPort link clocks used incorrect
> frequency tables. Drop frequency tables and use clk_byte2_ops instead of
> clk_rcg2_ops.
>
> Note, this was tested on SM8450 only and then extended to other
> platforms.
>
> [...]
Applied, thanks!
[1/4] clk: qcom: dispcc-sm8450: fix DisplayPort clocks
commit: e801038a02ce1e8c652a0b668dd233a4ee48aeb7
[2/4] clk: qcom: dispcc-sm6350: fix DisplayPort clocks
commit: 1113501cfb46d5c0eb960f0a8a9f6c0f91dc6fb6
[3/4] clk: qcom: dispcc-sm8550: fix DisplayPort clocks
commit: e90b5139da8465a15c3820b4b67ca9468dce93b4
[4/4] clk: qcom: dispcc-sm8650: fix DisplayPort clocks
commit: 615a292ee4d51303246278f3fa33cc38700fe00e
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [relevance 4%]
* [GIT PULL] Qualcomm Arm64 DeviceTree updates for v6.10
@ 2024-04-27 17:59 6% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2024-04-27 17:59 UTC (permalink / raw)
To: arm, soc
Cc: linux-arm-msm, linux-arm-kernel, Arnd Bergmann, Olof Johansson,
Kevin Hilman, Manivannan Sadhasivam, Dmitry Baryshkov,
Konrad Dybcio, Abel Vesa, Bjorn Andersson, Neil Armstrong,
Anton Bambura, Krzysztof Kozlowski, Luca Weiss, Danila Tikhonov,
Jianhua Lu, Johan Hovold, Komal Bajaj, Paweł Owoc,
Sebastian Raase, Stephen Boyd, Caleb Connolly, Elliot Berman,
Hui Liu, Joe Mason, Konrad Dybcio, Krishna Kurapati, Ling Xu,
Loic Poulain, Luca Weiss, Raymond Hackley, Richard Acayan,
Ritesh Kumar, Rong Zhang, Siddharth Manthan, Udipto Goswami,
Umang Chheda, Volodymyr Babchuk
The following changes since commit 4cece764965020c22cff7665b18a012006359095:
Linux 6.9-rc1 (2024-03-24 14:10:05 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-arm64-for-6.10
for you to fetch changes up to 873d845a357a4d89700cb1bb5b3da68890756f50:
dt-bindings: arm: qcom: Add Samsung Galaxy S5 China (kltechn) (2024-04-23 08:00:06 -0500)
----------------------------------------------------------------
Qualcomm Arm64 DeviceTree updates for v6.10
Support for Sony Xperia 1V, on the SM8550 platform, is added.
On IPQ8074, UART6 is described and unused gpios from QPIC are removed.
Backlight and touchscreen are described on Samsung Grand Prime devices.
RGB LED is added to Sony Xperia "Yoshino" devices, on which the
volume-up key definition is corrected as well.
Light Pulse Generator node is added to PM6150L PMIC, and blocks related
to USB Type-C on PM6150 are added.
On QCS6490 Rb3Gen2 UFS storage, USB Type-C management, a couple of
remoteprocs and both USB Type-C and native DisplayPort are enabled.
For the related IDP display is enabled, and the PMIC volume and power
buttons are described.
The inline crypto engine is added for SC7280, and an additional turbo
frequency is added to the MDP.
USB Type-C port management is introduce for the QRB2210 RB1. WiFi
firmware-name qualifier is added to both RB1 and RB2 boards.
The LMH node is added for the QCM2290, to configure the thresholds as
well as provide thermal pressure input.
The regulator range is adjusted for SD-card IO on SA8155P ADP, to allow
UHS modes.
The unused DCC is disabled on SC7180, and unused PMIC gpio block is
disabled on Trogdor.
For Lenovo Flex 5G, on SC8180X, the GPU firmware path is aligned with
agreed upon firmware structure. The frequency of the I2C bus for
touchpad is brought up to mitigate missing events. A number of
additional cleanups are introduced.
For SC8280XP GICv3 ITS is wired up for PCIe. EAS properties ad
introduced. A PS_HOLD-based restart node is introduced and acts as a
fallback if other mechanisms are unavailable to restart the board.
QFPROM is described, missing LMH interrupts for thermal pressure are
added. The TCSR download mode register is added, to allow configuring
if download mode should be entered on a crash.
USB Type-C handling is introduce for Fairphone FP3 as well.
On SM6350 crypto engine and DisplayPort controllers are introduced.
WiFi is enabled on the SM8150 Hardware Development Kit (HDK)
USB PD properties are added on Xiaomi Mi Pad 5 Pro devices.
Interconnect paths are added for UFS on SM8350, to ensure the bus is
voted for when the controller is operating.
On SM8550 the DMA coherency properties are corrected for SMMU and a few
consumers. Missing DWC3 quirks are added and the SNPS PHY parameters are
adjusted. Fastrpc banks are marked non-secure as needed.
The GPU description is introduced on SM8650, and enabled on the QRD. A
missing reserved-memory node is added, as is a few missing fastrpc
compute banks, and the non-secure-domain flag for other banks.
On X1 Elite SPMI support is added, together with PMIC definitons. The
link properties for DP3 are corrected, and audio-related resets are
introduced. SoundWire properties are corrected.
Nodes describing the PCIe bridge under the host controller is added
for a bunch of platforms.
The GPIO carrying orientation information for USB Type-C is added across
Fairphone 5, Lenovo Flex 5G, Lenovo Thinkpad X13s, SM8350 and SM845
HDKs.
A few dtbTool-specific compatibles for msm8916 is dropped from the
bindings.
A number of DeviceTree binding validation issues are corrected.
----------------------------------------------------------------
Abel Vesa (7):
arm64: dts: qcom: x1e80100: Add SPMI support
arm64: dts: qcom: x1e80100: Add dedicated pmic dtsi
arm64: dts: qcom: x1e80100-crd: Add repeater nodes
arm64: dts: qcom: x1e80100-qcp: Add repeater nodes
arm64: dts: qcom: x1e80100: Drop the link-frequencies from mdss_dp3_in
arm64: dts: qcom: x1e80100-crd: Add data-lanes and link-frequencies to DP3
arm64: dts: qcom: x1e80100-qcp: Add data-lanes and link-frequencies to DP3
Anton Bambura (5):
arm64: dts: qcom: sc8180x-lenovo-flex-5g: fix GPU firmware path
arm64: dts: qcom: sc8180x-lenovo-flex-5g: set names for i2c hid nodes
arm64: dts: qcom: sc8180x-lenovo-flex-5g: move pinctrl to appropriate nodes
arm64: dts: qcom: sc8180x-lenovo-flex-5g: set touchpad i2c frequency to 1 MHz
arm64: dts: qcom: sc8180x-lenovo-flex-5g: Allow UFS regulators load/mode setting
Bjorn Andersson (8):
arm64: dts: qcom: qcs6490-rb3gen2: Name the regulators
Merge branch 'arm64-for-6.10' onto 'v6.9-rc1'
arm64: dts: qcom: sc7280: Enable MDP turbo mode
arm64: dts: qcom: qcs6490-rb3gen2: Add DP output
arm64: dts: qcom: qcs6490-rb3gen2: Enable adsp and cdsp
arm64: dts: qcom: qcs6490-rb3gen2: Introduce USB redriver
arm64: dts: qcom: qcs6490-rb3gen2: Enable USB Type-C display
arm64: dts: qcom: qcs6490-rb3gen2: Enable UFS
Caleb Connolly (1):
arm64: dts: qcom: sdm845-db845c: make pcie0_3p3v_dual always-on
Danila Tikhonov (3):
arm64: dts: qcom: pm6150: define USB-C related blocks
arm64: dts: qcom: sc7180: Fix UFS PHY clocks
arm64: dts: qcom: pm6150l: add Light Pulse Generator device node
Dmitry Baryshkov (15):
arm64: dts: qcom: qrb2210-rb1: enable USB-C port handling
arm64: dts: qcom: sc8180x: drop legacy property #stream-id-cells
arm64: dts: qcom: sc8180x: Drop flags for mdss irqs
arm64: dts: qcom: sc8180x: add dp_p1 register blocks to DP nodes
arm64: dts: qcom: sm8350: Add interconnects to UFS
dt-bindings: arm: qcom: drop dtbTool-specific compatibles
arm64: dts: qcom: msm8916: drop dtbTool-specific compatibles
arm64: dts: qcom: sm8150-hdk: enable WiFI support
dt-bindings: soc: qcom: pmic-glink: allow orientation-gpios
arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO
arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO
arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs
arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs
arm64: dts: qcom: qrb2210-rb1: add firmware-name qualifier to WiFi node
arm64: dts: qcom: qrb4210-rb1: add firmware-name qualifier to WiFi node
Elliot Berman (1):
arm64: dts: qcom: sm8650: Add missing reserved memory for chipinfo
Hui Liu (1):
arm64: dts: qcom: qcm6490-idp: enable PMIC Volume and Power buttons
Jianhua Lu (2):
arm64: dts: qcom: sm8250-xiaomi-elish: add usb pd negotiation support
arm64: dts: qcom: sm8250-xiaomi-elish: set pm8150b_vbus regulator-min-microamp and regulator-max-microamp
Joe Mason (1):
arm64: dts: qcom: msm8916-samsung-fortuna: Add touchscreen
Johan Hovold (2):
arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
arm64: dts: qcom: sc8280xp: enable GICv3 ITS for PCIe
Komal Bajaj (2):
arm64: dts: qcom: qcm6490-idp: Enable various remoteprocs
arm64: dts: qcom: qcs6490-rb3gen2: Enable various remoteprocs
Konrad Dybcio (12):
arm64: dts: qcom: sc8280xp: Add missing LMH interrupts
arm64: dts: qcom: sc8280xp: Add QFPROM node
arm64: dts: qcom: sc8280xp: Add PS_HOLD restart
arm64: dts: qcom: sc8280xp: Describe TCSR download mode register
arm64: dts: qcom: msm8998-yoshino: Enable RGB led
dt-bindings: arm: qcom: Add Xperia 1 V
arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherent
arm64: dts: qcom: sm8550: Mark APPS SMMU as dma-coherent
arm64: dts: qcom: sm8550: Add missing DWC3 quirks
arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent
arm64: dts: qcom: Add SM8550 Xperia 1 V
arm64: dts: qcom: sc8280xp: Fill in EAS properties
Krishna Kurapati (1):
arm64: dts: qcom: sc8280xp: Add missing hs_phy_irq in USB nodes
Krzysztof Kozlowski (5):
arm64: dts: qcom: x1e80100: correct SWR1 pack mode
arm64: dts: qcom: x1e80100-crd: switch WSA8845 speakers to shared reset-gpio
arm64: dts: qcom: pm6150: correct Type-C compatible
arm64: dts: qcom: apq8016-sbc: correct GPIO LEDs node names
arm64: dts: qcom: sdx75: add unit address to soc node
Ling Xu (1):
arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodes
Loic Poulain (1):
arm64: dts: qcom: qcm2290: Add LMH node
Luca Weiss (6):
arm64: dts: qcom: sm6350: Add Crypto Engine
arm64: dts: qcom: sdm632-fairphone-fp3: enable USB-C port handling
arm64: dts: qcom: sc7280: Add inline crypto engine
dt-bindings: arm: qcom: Add Sony Xperia Z3
arm64: dts: qcom: qcm6490-fairphone-fp5: Add USB-C orientation GPIO
arm64: dts: qcom: sm6350: Add DisplayPort controller
Manivannan Sadhasivam (16):
arm64: dts: qcom: sm8250: Add PCIe bridge node
arm64: dts: qcom: sdm845: Add PCIe bridge node
arm64: dts: qcom: sm8150: Add PCIe bridge node
arm64: dts: qcom: sm8350: Add PCIe bridge node
arm64: dts: qcom: sm8450: Add PCIe bridge node
arm64: dts: qcom: sm8550: Add PCIe bridge node
arm64: dts: qcom: sm8650: Add PCIe bridge node
arm64: dts: qcom: sa8775p: Add PCIe bridge node
arm64: dts: qcom: sc8280xp: Add PCIe bridge node
arm64: dts: qcom: msm8998: Add PCIe bridge node
arm64: dts: qcom: sc7280: Add PCIe bridge node
arm64: dts: qcom: qcs404: Add PCIe bridge node
arm64: dts: qcom: sc8180x: Add PCIe bridge node
arm64: dts: qcom: msm8996: Add PCIe bridge node
arm64: dts: qcom: ipq8074: Add PCIe bridge node
arm64: dts: qcom: ipq6018: Add PCIe bridge node
Neil Armstrong (7):
arm64: dts: qcom: sm8450: add missing qcom,non-secure-domain property
arm64: dts: qcom: sm8550: add missing qcom,non-secure-domain property
arm64: dts: qcom: sm8650: add missing qcom,non-secure-domain property
arm64: dts: qcom: sm8650: fix usb interrupts properties
arm64: dts: qcom: sm8650: remove useless enablement of mdss_mdp
arm64: dts: qcom: sm8650: add GPU nodes
arm64: dts: qcom: sm8650-qrd: enable GPU
Paweł Owoc (2):
arm64: dts: qcom: ipq8074: Add QUP UART6 node
arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins
Raymond Hackley (1):
arm64: dts: qcom: msm8916/39-samsung-a2015: Add connector for MUIC
Richard Acayan (1):
arm64: dts: qcom: sdm670-google-sargo: add panel
Ritesh Kumar (1):
arm64: dts: qcom: qcm6490-idp: add display and panel
Rong Zhang (1):
dt-bindings: arm: qcom: Add Samsung Galaxy S5 China (kltechn)
Sebastian Raase (2):
arm64: dts: qcom: sdm630-nile: add pinctrl for camera key
arm64: dts: qcom: msm8998-yoshino: fix volume-up key
Siddharth Manthan (1):
arm64: dts: qcom: msm8916-samsung-fortuna: Add PWM backlight
Stephen Boyd (2):
arm64: dts: qcom: sc7180: Disable pmic pinctrl node on Trogdor
arm64: dts: qcom: sc7180: Disable DCC node by default
Udipto Goswami (1):
arm64: dts: qcom: sm8450: Update SNPS Phy parameters for QRD platform
Umang Chheda (1):
arm64: dts: qcom: qcm6490-idp: Name the regulators
Volodymyr Babchuk (1):
arm64: dts: qcom: sa8155p-adp: lower min volt for L13C regulator
Documentation/devicetree/bindings/arm/qcom.yaml | 17 +-
.../bindings/soc/qcom/qcom,pmic-glink.yaml | 14 -
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 12 +-
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 +
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 41 +-
.../boot/dts/qcom/msm8916-longcheer-l8150.dts | 2 +-
arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 2 +-
.../dts/qcom/msm8916-samsung-a2015-common.dtsi | 6 +
.../dts/qcom/msm8916-samsung-e2015-common.dtsi | 6 +
.../dts/qcom/msm8916-samsung-fortuna-common.dtsi | 83 +++
.../dts/qcom/msm8916-samsung-rossa-common.dtsi | 12 +
arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts | 6 +
arch/arm64/boot/dts/qcom/msm8953.dtsi | 14 +
arch/arm64/boot/dts/qcom/msm8996.dtsi | 30 +
.../boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 67 +-
arch/arm64/boot/dts/qcom/msm8998.dtsi | 10 +
arch/arm64/boot/dts/qcom/pm6150.dtsi | 4 +-
arch/arm64/boot/dts/qcom/pm6150l.dtsi | 10 +
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 56 +-
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 2 +
arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 189 +++++
arch/arm64/boot/dts/qcom/qcs404.dtsi | 10 +
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 251 ++++++-
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 61 +-
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 1 +
arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 2 +-
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 20 +
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 +
arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 24 +
.../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 59 +-
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 53 +-
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 22 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 110 ++-
.../boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 9 +
arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts | 31 +-
arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts | 64 ++
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 6 +
arch/arm64/boot/dts/qcom/sdm845.dtsi | 20 +
arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm6350.dtsi | 119 ++++
arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 16 +
arch/arm64/boot/dts/qcom/sm8150.dtsi | 20 +
.../boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 11 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 +
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 +
arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 +
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 +
arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 8 +
arch/arm64/boot/dts/qcom/sm8450.dtsi | 23 +
.../dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 779 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 42 +-
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 -
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 12 +-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 255 ++++++-
arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 47 +-
arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 51 ++
arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 27 +-
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 46 +-
60 files changed, 2720 insertions(+), 148 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi
_______________________________________________
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^ permalink raw reply [relevance 6%]
* [GIT PULL] Qualcomm Arm64 DeviceTree updates for v6.10
@ 2024-04-27 17:59 6% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2024-04-27 17:59 UTC (permalink / raw)
To: arm, soc
Cc: linux-arm-msm, linux-arm-kernel, Arnd Bergmann, Olof Johansson,
Kevin Hilman, Manivannan Sadhasivam, Dmitry Baryshkov,
Konrad Dybcio, Abel Vesa, Bjorn Andersson, Neil Armstrong,
Anton Bambura, Krzysztof Kozlowski, Luca Weiss, Danila Tikhonov,
Jianhua Lu, Johan Hovold, Komal Bajaj, Paweł Owoc,
Sebastian Raase, Stephen Boyd, Caleb Connolly, Elliot Berman,
Hui Liu, Joe Mason, Konrad Dybcio, Krishna Kurapati, Ling Xu,
Loic Poulain, Luca Weiss, Raymond Hackley, Richard Acayan,
Ritesh Kumar, Rong Zhang, Siddharth Manthan, Udipto Goswami,
Umang Chheda, Volodymyr Babchuk
The following changes since commit 4cece764965020c22cff7665b18a012006359095:
Linux 6.9-rc1 (2024-03-24 14:10:05 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-arm64-for-6.10
for you to fetch changes up to 873d845a357a4d89700cb1bb5b3da68890756f50:
dt-bindings: arm: qcom: Add Samsung Galaxy S5 China (kltechn) (2024-04-23 08:00:06 -0500)
----------------------------------------------------------------
Qualcomm Arm64 DeviceTree updates for v6.10
Support for Sony Xperia 1V, on the SM8550 platform, is added.
On IPQ8074, UART6 is described and unused gpios from QPIC are removed.
Backlight and touchscreen are described on Samsung Grand Prime devices.
RGB LED is added to Sony Xperia "Yoshino" devices, on which the
volume-up key definition is corrected as well.
Light Pulse Generator node is added to PM6150L PMIC, and blocks related
to USB Type-C on PM6150 are added.
On QCS6490 Rb3Gen2 UFS storage, USB Type-C management, a couple of
remoteprocs and both USB Type-C and native DisplayPort are enabled.
For the related IDP display is enabled, and the PMIC volume and power
buttons are described.
The inline crypto engine is added for SC7280, and an additional turbo
frequency is added to the MDP.
USB Type-C port management is introduce for the QRB2210 RB1. WiFi
firmware-name qualifier is added to both RB1 and RB2 boards.
The LMH node is added for the QCM2290, to configure the thresholds as
well as provide thermal pressure input.
The regulator range is adjusted for SD-card IO on SA8155P ADP, to allow
UHS modes.
The unused DCC is disabled on SC7180, and unused PMIC gpio block is
disabled on Trogdor.
For Lenovo Flex 5G, on SC8180X, the GPU firmware path is aligned with
agreed upon firmware structure. The frequency of the I2C bus for
touchpad is brought up to mitigate missing events. A number of
additional cleanups are introduced.
For SC8280XP GICv3 ITS is wired up for PCIe. EAS properties ad
introduced. A PS_HOLD-based restart node is introduced and acts as a
fallback if other mechanisms are unavailable to restart the board.
QFPROM is described, missing LMH interrupts for thermal pressure are
added. The TCSR download mode register is added, to allow configuring
if download mode should be entered on a crash.
USB Type-C handling is introduce for Fairphone FP3 as well.
On SM6350 crypto engine and DisplayPort controllers are introduced.
WiFi is enabled on the SM8150 Hardware Development Kit (HDK)
USB PD properties are added on Xiaomi Mi Pad 5 Pro devices.
Interconnect paths are added for UFS on SM8350, to ensure the bus is
voted for when the controller is operating.
On SM8550 the DMA coherency properties are corrected for SMMU and a few
consumers. Missing DWC3 quirks are added and the SNPS PHY parameters are
adjusted. Fastrpc banks are marked non-secure as needed.
The GPU description is introduced on SM8650, and enabled on the QRD. A
missing reserved-memory node is added, as is a few missing fastrpc
compute banks, and the non-secure-domain flag for other banks.
On X1 Elite SPMI support is added, together with PMIC definitons. The
link properties for DP3 are corrected, and audio-related resets are
introduced. SoundWire properties are corrected.
Nodes describing the PCIe bridge under the host controller is added
for a bunch of platforms.
The GPIO carrying orientation information for USB Type-C is added across
Fairphone 5, Lenovo Flex 5G, Lenovo Thinkpad X13s, SM8350 and SM845
HDKs.
A few dtbTool-specific compatibles for msm8916 is dropped from the
bindings.
A number of DeviceTree binding validation issues are corrected.
----------------------------------------------------------------
Abel Vesa (7):
arm64: dts: qcom: x1e80100: Add SPMI support
arm64: dts: qcom: x1e80100: Add dedicated pmic dtsi
arm64: dts: qcom: x1e80100-crd: Add repeater nodes
arm64: dts: qcom: x1e80100-qcp: Add repeater nodes
arm64: dts: qcom: x1e80100: Drop the link-frequencies from mdss_dp3_in
arm64: dts: qcom: x1e80100-crd: Add data-lanes and link-frequencies to DP3
arm64: dts: qcom: x1e80100-qcp: Add data-lanes and link-frequencies to DP3
Anton Bambura (5):
arm64: dts: qcom: sc8180x-lenovo-flex-5g: fix GPU firmware path
arm64: dts: qcom: sc8180x-lenovo-flex-5g: set names for i2c hid nodes
arm64: dts: qcom: sc8180x-lenovo-flex-5g: move pinctrl to appropriate nodes
arm64: dts: qcom: sc8180x-lenovo-flex-5g: set touchpad i2c frequency to 1 MHz
arm64: dts: qcom: sc8180x-lenovo-flex-5g: Allow UFS regulators load/mode setting
Bjorn Andersson (8):
arm64: dts: qcom: qcs6490-rb3gen2: Name the regulators
Merge branch 'arm64-for-6.10' onto 'v6.9-rc1'
arm64: dts: qcom: sc7280: Enable MDP turbo mode
arm64: dts: qcom: qcs6490-rb3gen2: Add DP output
arm64: dts: qcom: qcs6490-rb3gen2: Enable adsp and cdsp
arm64: dts: qcom: qcs6490-rb3gen2: Introduce USB redriver
arm64: dts: qcom: qcs6490-rb3gen2: Enable USB Type-C display
arm64: dts: qcom: qcs6490-rb3gen2: Enable UFS
Caleb Connolly (1):
arm64: dts: qcom: sdm845-db845c: make pcie0_3p3v_dual always-on
Danila Tikhonov (3):
arm64: dts: qcom: pm6150: define USB-C related blocks
arm64: dts: qcom: sc7180: Fix UFS PHY clocks
arm64: dts: qcom: pm6150l: add Light Pulse Generator device node
Dmitry Baryshkov (15):
arm64: dts: qcom: qrb2210-rb1: enable USB-C port handling
arm64: dts: qcom: sc8180x: drop legacy property #stream-id-cells
arm64: dts: qcom: sc8180x: Drop flags for mdss irqs
arm64: dts: qcom: sc8180x: add dp_p1 register blocks to DP nodes
arm64: dts: qcom: sm8350: Add interconnects to UFS
dt-bindings: arm: qcom: drop dtbTool-specific compatibles
arm64: dts: qcom: msm8916: drop dtbTool-specific compatibles
arm64: dts: qcom: sm8150-hdk: enable WiFI support
dt-bindings: soc: qcom: pmic-glink: allow orientation-gpios
arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO
arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO
arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs
arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs
arm64: dts: qcom: qrb2210-rb1: add firmware-name qualifier to WiFi node
arm64: dts: qcom: qrb4210-rb1: add firmware-name qualifier to WiFi node
Elliot Berman (1):
arm64: dts: qcom: sm8650: Add missing reserved memory for chipinfo
Hui Liu (1):
arm64: dts: qcom: qcm6490-idp: enable PMIC Volume and Power buttons
Jianhua Lu (2):
arm64: dts: qcom: sm8250-xiaomi-elish: add usb pd negotiation support
arm64: dts: qcom: sm8250-xiaomi-elish: set pm8150b_vbus regulator-min-microamp and regulator-max-microamp
Joe Mason (1):
arm64: dts: qcom: msm8916-samsung-fortuna: Add touchscreen
Johan Hovold (2):
arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
arm64: dts: qcom: sc8280xp: enable GICv3 ITS for PCIe
Komal Bajaj (2):
arm64: dts: qcom: qcm6490-idp: Enable various remoteprocs
arm64: dts: qcom: qcs6490-rb3gen2: Enable various remoteprocs
Konrad Dybcio (12):
arm64: dts: qcom: sc8280xp: Add missing LMH interrupts
arm64: dts: qcom: sc8280xp: Add QFPROM node
arm64: dts: qcom: sc8280xp: Add PS_HOLD restart
arm64: dts: qcom: sc8280xp: Describe TCSR download mode register
arm64: dts: qcom: msm8998-yoshino: Enable RGB led
dt-bindings: arm: qcom: Add Xperia 1 V
arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherent
arm64: dts: qcom: sm8550: Mark APPS SMMU as dma-coherent
arm64: dts: qcom: sm8550: Add missing DWC3 quirks
arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent
arm64: dts: qcom: Add SM8550 Xperia 1 V
arm64: dts: qcom: sc8280xp: Fill in EAS properties
Krishna Kurapati (1):
arm64: dts: qcom: sc8280xp: Add missing hs_phy_irq in USB nodes
Krzysztof Kozlowski (5):
arm64: dts: qcom: x1e80100: correct SWR1 pack mode
arm64: dts: qcom: x1e80100-crd: switch WSA8845 speakers to shared reset-gpio
arm64: dts: qcom: pm6150: correct Type-C compatible
arm64: dts: qcom: apq8016-sbc: correct GPIO LEDs node names
arm64: dts: qcom: sdx75: add unit address to soc node
Ling Xu (1):
arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodes
Loic Poulain (1):
arm64: dts: qcom: qcm2290: Add LMH node
Luca Weiss (6):
arm64: dts: qcom: sm6350: Add Crypto Engine
arm64: dts: qcom: sdm632-fairphone-fp3: enable USB-C port handling
arm64: dts: qcom: sc7280: Add inline crypto engine
dt-bindings: arm: qcom: Add Sony Xperia Z3
arm64: dts: qcom: qcm6490-fairphone-fp5: Add USB-C orientation GPIO
arm64: dts: qcom: sm6350: Add DisplayPort controller
Manivannan Sadhasivam (16):
arm64: dts: qcom: sm8250: Add PCIe bridge node
arm64: dts: qcom: sdm845: Add PCIe bridge node
arm64: dts: qcom: sm8150: Add PCIe bridge node
arm64: dts: qcom: sm8350: Add PCIe bridge node
arm64: dts: qcom: sm8450: Add PCIe bridge node
arm64: dts: qcom: sm8550: Add PCIe bridge node
arm64: dts: qcom: sm8650: Add PCIe bridge node
arm64: dts: qcom: sa8775p: Add PCIe bridge node
arm64: dts: qcom: sc8280xp: Add PCIe bridge node
arm64: dts: qcom: msm8998: Add PCIe bridge node
arm64: dts: qcom: sc7280: Add PCIe bridge node
arm64: dts: qcom: qcs404: Add PCIe bridge node
arm64: dts: qcom: sc8180x: Add PCIe bridge node
arm64: dts: qcom: msm8996: Add PCIe bridge node
arm64: dts: qcom: ipq8074: Add PCIe bridge node
arm64: dts: qcom: ipq6018: Add PCIe bridge node
Neil Armstrong (7):
arm64: dts: qcom: sm8450: add missing qcom,non-secure-domain property
arm64: dts: qcom: sm8550: add missing qcom,non-secure-domain property
arm64: dts: qcom: sm8650: add missing qcom,non-secure-domain property
arm64: dts: qcom: sm8650: fix usb interrupts properties
arm64: dts: qcom: sm8650: remove useless enablement of mdss_mdp
arm64: dts: qcom: sm8650: add GPU nodes
arm64: dts: qcom: sm8650-qrd: enable GPU
Paweł Owoc (2):
arm64: dts: qcom: ipq8074: Add QUP UART6 node
arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins
Raymond Hackley (1):
arm64: dts: qcom: msm8916/39-samsung-a2015: Add connector for MUIC
Richard Acayan (1):
arm64: dts: qcom: sdm670-google-sargo: add panel
Ritesh Kumar (1):
arm64: dts: qcom: qcm6490-idp: add display and panel
Rong Zhang (1):
dt-bindings: arm: qcom: Add Samsung Galaxy S5 China (kltechn)
Sebastian Raase (2):
arm64: dts: qcom: sdm630-nile: add pinctrl for camera key
arm64: dts: qcom: msm8998-yoshino: fix volume-up key
Siddharth Manthan (1):
arm64: dts: qcom: msm8916-samsung-fortuna: Add PWM backlight
Stephen Boyd (2):
arm64: dts: qcom: sc7180: Disable pmic pinctrl node on Trogdor
arm64: dts: qcom: sc7180: Disable DCC node by default
Udipto Goswami (1):
arm64: dts: qcom: sm8450: Update SNPS Phy parameters for QRD platform
Umang Chheda (1):
arm64: dts: qcom: qcm6490-idp: Name the regulators
Volodymyr Babchuk (1):
arm64: dts: qcom: sa8155p-adp: lower min volt for L13C regulator
Documentation/devicetree/bindings/arm/qcom.yaml | 17 +-
.../bindings/soc/qcom/qcom,pmic-glink.yaml | 14 -
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 12 +-
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 +
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 41 +-
.../boot/dts/qcom/msm8916-longcheer-l8150.dts | 2 +-
arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 2 +-
.../dts/qcom/msm8916-samsung-a2015-common.dtsi | 6 +
.../dts/qcom/msm8916-samsung-e2015-common.dtsi | 6 +
.../dts/qcom/msm8916-samsung-fortuna-common.dtsi | 83 +++
.../dts/qcom/msm8916-samsung-rossa-common.dtsi | 12 +
arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts | 6 +
arch/arm64/boot/dts/qcom/msm8953.dtsi | 14 +
arch/arm64/boot/dts/qcom/msm8996.dtsi | 30 +
.../boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 67 +-
arch/arm64/boot/dts/qcom/msm8998.dtsi | 10 +
arch/arm64/boot/dts/qcom/pm6150.dtsi | 4 +-
arch/arm64/boot/dts/qcom/pm6150l.dtsi | 10 +
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 56 +-
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 2 +
arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 189 +++++
arch/arm64/boot/dts/qcom/qcs404.dtsi | 10 +
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 251 ++++++-
arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 61 +-
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 1 +
arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 2 +-
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 20 +
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 +
arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 24 +
.../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 59 +-
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 53 +-
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 22 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 110 ++-
.../boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 9 +
arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts | 31 +-
arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts | 64 ++
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 6 +
arch/arm64/boot/dts/qcom/sdm845.dtsi | 20 +
arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm6350.dtsi | 119 ++++
arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 16 +
arch/arm64/boot/dts/qcom/sm8150.dtsi | 20 +
.../boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 11 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 +
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 +
arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 +
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 +
arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 8 +
arch/arm64/boot/dts/qcom/sm8450.dtsi | 23 +
.../dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 779 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 42 +-
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 -
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 12 +-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 255 ++++++-
arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 47 +-
arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 51 ++
arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 27 +-
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 46 +-
60 files changed, 2720 insertions(+), 148 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi
^ permalink raw reply [relevance 6%]
* [linux-linus test] 185828: tolerable FAIL - PUSHED
@ 2024-04-27 12:16 2% osstest service owner
0 siblings, 0 replies; 200+ results
From: osstest service owner @ 2024-04-27 12:16 UTC (permalink / raw)
To: xen-devel
flight 185828 linux-linus real [real]
flight 185831 linux-linus real-retest [real]
http://logs.test-lab.xenproject.org/osstest/logs/185828/
http://logs.test-lab.xenproject.org/osstest/logs/185831/
Failures :-/ but no regressions.
Tests which are failing intermittently (not blocking):
test-armhf-armhf-xl 8 xen-boot fail pass in 185831-retest
test-armhf-armhf-xl-credit1 8 xen-boot fail pass in 185831-retest
test-armhf-armhf-xl-credit2 8 xen-boot fail pass in 185831-retest
Regressions which are regarded as allowable (not blocking):
test-armhf-armhf-xl-rtds 8 xen-boot fail REGR. vs. 185802
Tests which did not succeed, but are not blocking:
test-armhf-armhf-xl 15 migrate-support-check fail in 185831 never pass
test-armhf-armhf-xl 16 saverestore-support-check fail in 185831 never pass
test-armhf-armhf-xl-credit1 15 migrate-support-check fail in 185831 never pass
test-armhf-armhf-xl-credit1 16 saverestore-support-check fail in 185831 never pass
test-armhf-armhf-xl-credit2 15 migrate-support-check fail in 185831 never pass
test-armhf-armhf-xl-credit2 16 saverestore-support-check fail in 185831 never pass
test-armhf-armhf-libvirt 16 saverestore-support-check fail like 185802
test-amd64-amd64-xl-qemut-win7-amd64 19 guest-stop fail like 185802
test-amd64-amd64-xl-qemuu-win7-amd64 19 guest-stop fail like 185802
test-amd64-amd64-xl-qemuu-ws16-amd64 19 guest-stop fail like 185802
test-amd64-amd64-qemuu-nested-amd 20 debian-hvm-install/l1/l2 fail like 185802
test-amd64-amd64-xl-qemut-ws16-amd64 19 guest-stop fail like 185802
test-amd64-amd64-libvirt-xsm 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 13 migrate-support-check fail never pass
test-arm64-arm64-libvirt-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-libvirt-xsm 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit1 15 migrate-support-check fail never pass
test-arm64-arm64-xl-xsm 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit1 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-xsm 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-thunderx 15 migrate-support-check fail never pass
test-arm64-arm64-xl-thunderx 16 saverestore-support-check fail never pass
test-arm64-arm64-xl-credit2 15 migrate-support-check fail never pass
test-arm64-arm64-xl-credit2 16 saverestore-support-check fail never pass
test-arm64-arm64-xl 15 migrate-support-check fail never pass
test-arm64-arm64-xl 16 saverestore-support-check fail never pass
test-armhf-armhf-libvirt 15 migrate-support-check fail never pass
test-amd64-amd64-libvirt-qcow2 14 migrate-support-check fail never pass
test-armhf-armhf-xl-multivcpu 15 migrate-support-check fail never pass
test-armhf-armhf-xl-multivcpu 16 saverestore-support-check fail never pass
test-armhf-armhf-xl-arndale 15 migrate-support-check fail never pass
test-armhf-armhf-xl-arndale 16 saverestore-support-check fail never pass
test-amd64-amd64-libvirt-raw 14 migrate-support-check fail never pass
test-amd64-amd64-libvirt-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-libvirt-raw 14 migrate-support-check fail never pass
test-arm64-arm64-libvirt-raw 15 saverestore-support-check fail never pass
test-arm64-arm64-xl-vhd 14 migrate-support-check fail never pass
test-arm64-arm64-xl-vhd 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-qcow2 14 migrate-support-check fail never pass
test-armhf-armhf-xl-qcow2 15 saverestore-support-check fail never pass
test-armhf-armhf-xl-raw 14 migrate-support-check fail never pass
test-armhf-armhf-xl-raw 15 saverestore-support-check fail never pass
test-armhf-armhf-libvirt-vhd 14 migrate-support-check fail never pass
test-armhf-armhf-libvirt-vhd 15 saverestore-support-check fail never pass
version targeted for testing:
linux 5eb4573ea63d0c83bf58fb7c243fc2c2b6966c02
baseline version:
linux c942a0cd3603e34dd2d7237e064d9318cb7f9654
Last test of basis 185802 2024-04-26 01:58:59 Z 1 days
Failing since 185824 2024-04-26 18:40:13 Z 0 days 2 attempts
Testing same since 185828 2024-04-27 03:43:12 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
Adrian Hunter <adrian.hunter@intel.com>
Alex Deucher <alexander.deucher@amd.com>
Alexey Brodkin <abrodkin@synopsys.com>
Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Andrei Simion <andrei.simion@microchip.com>
Andrew Morton <akpm@linux-foundation.org>
Andrey Ryabinin <ryabinin.a.a@gmail.com>
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Andy Yan <andyshrk@163.com>
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Arnd Bergmann <arnd@arndb.de>
Arınç ÜNAL <arinc.unal@arinc9.com>
Baoquan He <bhe@redhat.com>
Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Bibo Mao <maobibo@loongson.cn>
Bjorn Andersson <andersson@kernel.org>
Bjorn Helgaas <bhelgaas@google.com>
Chen-Yu Tsai <wenst@chromium.org>
Christian Brauner <brauner@kernel.org>
Christian Gmeiner <cgmeiner@igalia.com>
Christian Heusel <christian@heusel.eu>
Christian König <christian.koenig@amd.com>
Christian Marangi <ansuelsmth@gmail.com>
Claudiu Beznea <claudiu.beznea@tuxon.dev>
Conor Dooley <conor.dooley@microchip.com>
Dan Williams <dan.j.williams@intel.com>
Daniel Golle <daniel@makrotopia.org>
Dave Airlie <airlied@redhat.com>
Dave Jiang <dave.jiang@intel.com>
David Hildenbrand <david@redhat.com>
David Howells <dhowells@redhat.com>
Derek Foreman <derek.foreman@collabora.com>
Dragan Simic <dsimic@manjaro.org>
Drew Fustini <drew@pdp7.com>
Edward Liaw <edliaw@google.com>
Enrico Bartky <enrico.bartky@gmail.com>
Felix Kuehling <felix.kuehling@amd.com>
Florian Fainelli <florian.fainelli@broadcom.com>
Gang BA <Gang.Ba@amd.com>
Günther Noack <gnoack@google.com>
Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com>
Heiko Stuebner <heiko@sntech.de>
Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Huacai Chen <chenhuacai@loongson.cn>
Ikjoon Jang <ikjn@chromium.org>
Iskander Amara <iskander.amara@theobroma-systems.com>
Jack Xiao <Jack.Xiao@amd.com>
Jiantao Shan <shanjiantao@loongson.cn>
Johan Hovold <johan+linaro@kernel.org>
Johannes Weiner <hannes@cmpxchg.org>
Jose Ignacio Tornos Martinez <jtornosm@redhat.com>
Joshua Ashton <joshua@froggi.es>
Kent Overstreet <kent.overstreet@linux.dev>
Konrad Dybcio <konrad.dybcio@linaro.org> # X13s
Krzysztof Kozlowski <krzk@kernel.org>
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Lang Yu <Lang.Yu@amd.com>
Leonard Göhrs <l.goehrs@pengutronix.de>
Lijo Lazar <lijo.lazar@amd.com>
Linus Torvalds <torvalds@linux-foundation.org>
Luca Weiss <luca.weiss@fairphone.com>
Lucas De Marchi <lucas.demarchi@intel.com>
Lucas Stach <l.stach@pengutronix.de>
Ma Jun <Jun.Ma2@amd.com>
Maksim Kiselev <bigunclemax@gmail.com>
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Mantas Pucka <mantas@8devices.com>
Marek Vasut <marex@denx.de>
Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Matthew Sakai <msakai@redhat.com>
Matthew Wilcox (Oracle) <willy@infradead.org>
Maximilian Luz <luzmaximilian@gmail.com>
Miaohe Lin <linmiaohe@huawei.com>
Michael Heimpold <michael.heimpold@chargebyte.com>
Michal Wajdeczko <michal.wajdeczko@intel.com>
Miguel Ojeda <ojeda@kernel.org>
Mike Snitzer <snitzer@kernel.org>
Mikulas Patocka <mpatocka@redhat.com>
Ming Lei <ming.lei@redhat.com>
Miquel Raynal <miquel.raynal@bootlin.com>
Muhammad Usama Anjum <usama.anjum@collabora.com>
Muhammed Efe Cetin <efectn@protonmail.com>
Mukul Joshi <mukul.joshi@amd.com>
Nam Cao <namcao@linutronix.de>
Neil Armstrong <neil.armstrong@linaro.org>
Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Nicolas Ferre <nicolas.ferre@microchip.com>
Nícolas F. R. A. Prado <nfraprado@collabora.com>
Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Peter Xu <peterx@redhat.com>
Peyton Lee <peytolee@amd.com>
Pin-yen Lin <treapking@chromium.org>
Prathamesh Shete <pshete@nvidia.com>
Prike Liang <Prike.Liang@amd.com>
Quentin Schulz <quentin.schulz@theobroma-systems.com>
Rafał Miłecki <rafal@milecki.pl>
Rajendra Nayak <quic_rjendra@quicinc.com>
Rob Herring <robh@kernel.org>
Sergei Antonov <saproj@gmail.com>
Shawn Guo <shawnguo@kernel.org>
Stefan Wahren <wahrenst@gmx.net>
Thierry Reding <treding@nvidia.com>
Thomas Zimmermann <tzimmermann@suse.de>
Thorsten Scherer <t.scherer@eckelmann.de>
Ulf Hansson <ulf.hansson@linaro.org>
Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Uwe Kleine-König <ukleinek@kernel.org>
Vineet Gupta <vgupta@kernel.org>
Vishal Moola (Oracle) <vishal.moola@gmail.com>
Vlastimil Babka <vbabka@suse.cz>
Weiyi Lu <weiyi.lu@mediatek.com>
William Zhang <william.zhang@broadcom.com>
Xi Ruoyao <xry111@xry111.site>
Xiubo Li <xiubli@redhat.com>
Yosry Ahmed <yosryahmed@google.com>
Yu Kuai <yukuai3@huawei.com>
Yunxiang Li <Yunxiang.Li@amd.com>
jobs:
build-amd64-xsm pass
build-arm64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-arm64 pass
build-armhf pass
build-i386 pass
build-amd64-libvirt pass
build-arm64-libvirt pass
build-armhf-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-arm64-pvops pass
build-armhf-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl pass
test-amd64-coresched-amd64-xl pass
test-arm64-arm64-xl pass
test-armhf-armhf-xl fail
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-stubdom-debianhvm-amd64-xsm pass
test-amd64-amd64-xl-qemut-debianhvm-i386-xsm pass
test-amd64-amd64-xl-qemuu-debianhvm-i386-xsm pass
test-amd64-amd64-libvirt-xsm pass
test-arm64-arm64-libvirt-xsm pass
test-amd64-amd64-xl-xsm pass
test-arm64-arm64-xl-xsm pass
test-amd64-amd64-qemuu-nested-amd fail
test-amd64-amd64-xl-pvhv2-amd pass
test-amd64-amd64-dom0pvh-xl-amd pass
test-amd64-amd64-xl-qemut-debianhvm-amd64 pass
test-amd64-amd64-xl-qemuu-debianhvm-amd64 pass
test-amd64-amd64-qemuu-freebsd11-amd64 pass
test-amd64-amd64-qemuu-freebsd12-amd64 pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-amd64-xl-qemut-win7-amd64 fail
test-amd64-amd64-xl-qemuu-win7-amd64 fail
test-amd64-amd64-xl-qemut-ws16-amd64 fail
test-amd64-amd64-xl-qemuu-ws16-amd64 fail
test-armhf-armhf-xl-arndale pass
test-amd64-amd64-examine-bios pass
test-amd64-amd64-xl-credit1 pass
test-arm64-arm64-xl-credit1 pass
test-armhf-armhf-xl-credit1 fail
test-amd64-amd64-xl-credit2 pass
test-arm64-arm64-xl-credit2 pass
test-armhf-armhf-xl-credit2 fail
test-amd64-amd64-xl-qemuu-dmrestrict-amd64-dmrestrict pass
test-amd64-amd64-examine pass
test-arm64-arm64-examine pass
test-armhf-armhf-examine pass
test-amd64-amd64-qemuu-nested-intel pass
test-amd64-amd64-xl-pvhv2-intel pass
test-amd64-amd64-dom0pvh-xl-intel pass
test-amd64-amd64-libvirt pass
test-armhf-armhf-libvirt pass
test-amd64-amd64-xl-multivcpu pass
test-armhf-armhf-xl-multivcpu pass
test-amd64-amd64-pair pass
test-amd64-amd64-libvirt-pair pass
test-amd64-amd64-xl-pvshim pass
test-amd64-amd64-pygrub pass
test-amd64-amd64-libvirt-qcow2 pass
test-amd64-amd64-xl-qcow2 pass
test-armhf-armhf-xl-qcow2 pass
test-amd64-amd64-libvirt-raw pass
test-arm64-arm64-libvirt-raw pass
test-amd64-amd64-xl-raw pass
test-armhf-armhf-xl-raw pass
test-amd64-amd64-xl-rtds pass
test-armhf-armhf-xl-rtds fail
test-amd64-amd64-xl-qemuu-debianhvm-amd64-shadow pass
test-amd64-amd64-xl-shadow pass
test-arm64-arm64-xl-thunderx pass
test-amd64-amd64-examine-uefi pass
test-amd64-amd64-libvirt-vhd pass
test-armhf-armhf-libvirt-vhd pass
test-amd64-amd64-xl-vhd pass
test-arm64-arm64-xl-vhd pass
------------------------------------------------------------
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
Pushing revision :
hint: The 'hooks/update' hook was ignored because it's not set as executable.
hint: You can disable this warning with `git config advice.ignoredHook false`.
hint: The 'hooks/post-receive' hook was ignored because it's not set as executable.
hint: You can disable this warning with `git config advice.ignoredHook false`.
hint: The 'hooks/post-update' hook was ignored because it's not set as executable.
hint: You can disable this warning with `git config advice.ignoredHook false`.
To xenbits.xen.org:/home/xen/git/linux-pvops.git
c942a0cd3603..5eb4573ea63d 5eb4573ea63d0c83bf58fb7c243fc2c2b6966c02 -> tested/linux-linus
^ permalink raw reply [relevance 2%]
* [GIT PULL] ARM SoC fixes for 6.9, part 2
@ 2024-04-26 21:00 4% ` Arnd Bergmann
0 siblings, 0 replies; 200+ results
From: Arnd Bergmann @ 2024-04-26 21:00 UTC (permalink / raw)
To: Linus Torvalds; +Cc: soc, linux-arm-kernel, linux-kernel
The following changes since commit 0bbac3facb5d6cc0171c45c9873a2dc96bea9680:
Linux 6.9-rc4 (2024-04-14 13:38:39 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git tags/soc-fixes-6.9-2
for you to fetch changes up to 9f26bc71b1fd895e22151e63934588e5ddb11b05:
Merge tag 'mtk-soc-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into for-next (2024-04-26 19:45:10 +0200)
----------------------------------------------------------------
ARM SoC fixes for 6.9, part 2
There are a lot of minor DT fixes for Mediatek, Rockchip, Qualcomm and
Microchip and NXP, addressing both build-time warnings and bugs found during
runtime testing. Most of these changes are machine specific fixups, but
there are a few notable regressions that affect an entire SoC:
- The Qualcomm MSI support that was improved for 6.9 ended up being
wrong on some chips and now gets fixed.
- The i.MX8MP camera interface broke due to a typo and gets
updated again.
The main driver fix is also for Qualcomm platofrms, rewriting an interface
in the QSEECOM firmware support that could lead to crashing the kernel
from a trusted application. The only other code changes are minor fixes
for Mediatek SoC drivers.
----------------------------------------------------------------
Andrei Simion (2):
ARM: dts: microchip: at91-sama7g5ek: Replace regulator-suspend-voltage with the valid property
ARM: dts: microchip: at91-sama7g54_curiosity: Replace regulator-suspend-voltage with the valid property
Andy Yan (1):
arm64: dts: rockchip: Fix the i2c address of es8316 on Cool Pi CM5
AngeloGioacchino Del Regno (1):
soc: mediatek: mtk-svs: Append "-thermal" to thermal zone names
Arnd Bergmann (7):
Merge branch 'v6.9-armsoc/dtsfixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into for-next
Merge tag 'qcom-arm64-fixes-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into for-next
Merge tag 'at91-fixes-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into for-next
Merge tag 'mtk-dts64-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into for-next
Merge tag 'imx-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into for-next
Merge tag 'qcom-drivers-fixes-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into for-next
Merge tag 'mtk-soc-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into for-next
Arınç ÜNAL (1):
arm64: dts: rockchip: set PHY address of MT7531 switch to 0x1f
Daniel Golle (1):
soc: mediatek: mtk-socinfo: depends on CONFIG_SOC_BUS
Dragan Simic (2):
arm64: dts: rockchip: Remove unsupported node from the Pinebook Pro dts
arm64: dts: rockchip: Designate the system power controller on QuartzPro64
Ikjoon Jang (1):
arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg
Iskander Amara (2):
arm64: dts: rockchip: enable internal pull-up for Q7_THRM# on RK3399 Puma
arm64: dts: rockchip: fix alphabetical ordering RK3399 puma
Johan Hovold (1):
arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
Jose Ignacio Tornos Martinez (1):
arm64: dts: rockchip: regulator for sd needs to be always on for BPI-R2Pro
Krzysztof Kozlowski (4):
arm64: dts: rockchip: drop panel port unit address in GRU Scarlet
arm64: dts: rockchip: drop redundant pcie-reset-suspend in Scarlet Dumo
arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 1
arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 2
Luca Weiss (1):
arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocs
Manivannan Sadhasivam (3):
arm64: dts: qcom: sm8450: Fix the msi-map entries
arm64: dts: qcom: sm8550: Fix the msi-map entries
arm64: dts: qcom: sm8650: Fix the msi-map entries
Marek Vasut (1):
arm64: dts: imx8mp: Fix assigned-clocks for second CSI2
Maximilian Luz (2):
firmware: qcom: uefisecapp: Fix memory related IO errors and crashes
arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller
Michael Heimpold (1):
ARM: dts: imx6ull-tarragon: fix USB over-current polarity
Muhammed Efe Cetin (1):
arm64: dts: rockchip: mark system power controller and fix typo on orangepi-5-plus
Nícolas F. R. A. Prado (5):
arm64: dts: mediatek: mt8192: Add missing gce-client-reg to mutex
arm64: dts: mediatek: mt8195: Add missing gce-client-reg to vpp/vdosys
arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex
arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex1
arm64: dts: mediatek: cherry: Describe CPU supplies
Pin-yen Lin (4):
arm64: dts: mediatek: mt8192-asurada: Update min voltage constraint for MT6315
arm64: dts: mediatek: mt8195-cherry: Update min voltage constraint for MT6315
arm64: dts: mediatek: mt8183-kukui: Use default min voltage for MT6358
arm64: dts: mediatek: mt8186-corsola: Update min voltage constraint for Vgpu
Quentin Schulz (3):
arm64: dts: rockchip: enable internal pull-up on Q7_USB_ID for RK3399 Puma
arm64: dts: rockchip: enable internal pull-up on PCIE_WAKE# for RK3399 Puma
arm64: dts: rockchip: add regulators for PCIe on RK3399 Puma Haikou
Rafał Miłecki (9):
arm64: dts: mediatek: mt7622: fix clock controllers
arm64: dts: mediatek: mt7622: fix IR nodename
arm64: dts: mediatek: mt7622: fix ethernet controller "compatible"
arm64: dts: mediatek: mt7622: drop "reset-names" from thermal block
arm64: dts: mediatek: mt7986: drop invalid properties from ethsys
arm64: dts: mediatek: mt7986: drop "#reset-cells" from Ethernet controller
arm64: dts: mediatek: mt7986: drop invalid thermal block clock
arm64: dts: mediatek: mt7986: prefix BPI-R3 cooling maps with "map-"
arm64: dts: mediatek: mt2712: fix validation errors
Rajendra Nayak (1):
arm64: dts: qcom: x1e80100: Fix the compatible for cluster idle states
Rob Herring (2):
dt-bindings: rockchip: grf: Add missing type to 'pcie-phy' node
arm64: dts: rockchip: Fix USB interface compatible string on kobol-helios64
.../devicetree/bindings/soc/rockchip/grf.yaml | 1 +
.../boot/dts/microchip/at91-sama7g54_curiosity.dts | 8 +-
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 8 +-
.../boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +-
arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 8 +-
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 34 +++--
.../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 6 +-
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 8 +-
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 -
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi | 2 +-
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 6 +-
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 +
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 36 +++++-
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 5 +
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 +-
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 11 +-
arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 +-
arch/arm64/boot/dts/qcom/sm6375.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +-
arch/arm64/boot/dts/qcom/sm8450.dtsi | 16 +--
arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 +-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 +-
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 4 +-
.../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 3 +-
.../boot/dts/rockchip/rk3399-kobol-helios64.dts | 2 +-
.../boot/dts/rockchip/rk3399-pinebook-pro.dts | 1 -
.../arm64/boot/dts/rockchip/rk3399-puma-haikou.dts | 2 +
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 53 +++++++-
arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts | 1 -
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 6 +-
arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts | 1 -
.../arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi | 4 +-
.../boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 3 +-
.../arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 1 +
drivers/firmware/qcom/qcom_qseecom_uefisecapp.c | 137 ++++++++++++++-------
drivers/firmware/qcom/qcom_scm.c | 37 +-----
drivers/soc/mediatek/Kconfig | 1 +
drivers/soc/mediatek/mtk-svs.c | 7 +-
include/linux/firmware/qcom/qcom_qseecom.h | 55 ++++++++-
include/linux/firmware/qcom/qcom_scm.h | 10 +-
44 files changed, 331 insertions(+), 193 deletions(-)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 4%]
* [GIT PULL] ARM SoC fixes for 6.9, part 2
@ 2024-04-26 21:00 4% ` Arnd Bergmann
0 siblings, 0 replies; 200+ results
From: Arnd Bergmann @ 2024-04-26 21:00 UTC (permalink / raw)
To: Linus Torvalds; +Cc: soc, linux-arm-kernel, linux-kernel
The following changes since commit 0bbac3facb5d6cc0171c45c9873a2dc96bea9680:
Linux 6.9-rc4 (2024-04-14 13:38:39 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git tags/soc-fixes-6.9-2
for you to fetch changes up to 9f26bc71b1fd895e22151e63934588e5ddb11b05:
Merge tag 'mtk-soc-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into for-next (2024-04-26 19:45:10 +0200)
----------------------------------------------------------------
ARM SoC fixes for 6.9, part 2
There are a lot of minor DT fixes for Mediatek, Rockchip, Qualcomm and
Microchip and NXP, addressing both build-time warnings and bugs found during
runtime testing. Most of these changes are machine specific fixups, but
there are a few notable regressions that affect an entire SoC:
- The Qualcomm MSI support that was improved for 6.9 ended up being
wrong on some chips and now gets fixed.
- The i.MX8MP camera interface broke due to a typo and gets
updated again.
The main driver fix is also for Qualcomm platofrms, rewriting an interface
in the QSEECOM firmware support that could lead to crashing the kernel
from a trusted application. The only other code changes are minor fixes
for Mediatek SoC drivers.
----------------------------------------------------------------
Andrei Simion (2):
ARM: dts: microchip: at91-sama7g5ek: Replace regulator-suspend-voltage with the valid property
ARM: dts: microchip: at91-sama7g54_curiosity: Replace regulator-suspend-voltage with the valid property
Andy Yan (1):
arm64: dts: rockchip: Fix the i2c address of es8316 on Cool Pi CM5
AngeloGioacchino Del Regno (1):
soc: mediatek: mtk-svs: Append "-thermal" to thermal zone names
Arnd Bergmann (7):
Merge branch 'v6.9-armsoc/dtsfixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into for-next
Merge tag 'qcom-arm64-fixes-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into for-next
Merge tag 'at91-fixes-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into for-next
Merge tag 'mtk-dts64-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into for-next
Merge tag 'imx-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into for-next
Merge tag 'qcom-drivers-fixes-for-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into for-next
Merge tag 'mtk-soc-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into for-next
Arınç ÜNAL (1):
arm64: dts: rockchip: set PHY address of MT7531 switch to 0x1f
Daniel Golle (1):
soc: mediatek: mtk-socinfo: depends on CONFIG_SOC_BUS
Dragan Simic (2):
arm64: dts: rockchip: Remove unsupported node from the Pinebook Pro dts
arm64: dts: rockchip: Designate the system power controller on QuartzPro64
Ikjoon Jang (1):
arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg
Iskander Amara (2):
arm64: dts: rockchip: enable internal pull-up for Q7_THRM# on RK3399 Puma
arm64: dts: rockchip: fix alphabetical ordering RK3399 puma
Johan Hovold (1):
arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
Jose Ignacio Tornos Martinez (1):
arm64: dts: rockchip: regulator for sd needs to be always on for BPI-R2Pro
Krzysztof Kozlowski (4):
arm64: dts: rockchip: drop panel port unit address in GRU Scarlet
arm64: dts: rockchip: drop redundant pcie-reset-suspend in Scarlet Dumo
arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 1
arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 2
Luca Weiss (1):
arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocs
Manivannan Sadhasivam (3):
arm64: dts: qcom: sm8450: Fix the msi-map entries
arm64: dts: qcom: sm8550: Fix the msi-map entries
arm64: dts: qcom: sm8650: Fix the msi-map entries
Marek Vasut (1):
arm64: dts: imx8mp: Fix assigned-clocks for second CSI2
Maximilian Luz (2):
firmware: qcom: uefisecapp: Fix memory related IO errors and crashes
arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller
Michael Heimpold (1):
ARM: dts: imx6ull-tarragon: fix USB over-current polarity
Muhammed Efe Cetin (1):
arm64: dts: rockchip: mark system power controller and fix typo on orangepi-5-plus
Nícolas F. R. A. Prado (5):
arm64: dts: mediatek: mt8192: Add missing gce-client-reg to mutex
arm64: dts: mediatek: mt8195: Add missing gce-client-reg to vpp/vdosys
arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex
arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex1
arm64: dts: mediatek: cherry: Describe CPU supplies
Pin-yen Lin (4):
arm64: dts: mediatek: mt8192-asurada: Update min voltage constraint for MT6315
arm64: dts: mediatek: mt8195-cherry: Update min voltage constraint for MT6315
arm64: dts: mediatek: mt8183-kukui: Use default min voltage for MT6358
arm64: dts: mediatek: mt8186-corsola: Update min voltage constraint for Vgpu
Quentin Schulz (3):
arm64: dts: rockchip: enable internal pull-up on Q7_USB_ID for RK3399 Puma
arm64: dts: rockchip: enable internal pull-up on PCIE_WAKE# for RK3399 Puma
arm64: dts: rockchip: add regulators for PCIe on RK3399 Puma Haikou
Rafał Miłecki (9):
arm64: dts: mediatek: mt7622: fix clock controllers
arm64: dts: mediatek: mt7622: fix IR nodename
arm64: dts: mediatek: mt7622: fix ethernet controller "compatible"
arm64: dts: mediatek: mt7622: drop "reset-names" from thermal block
arm64: dts: mediatek: mt7986: drop invalid properties from ethsys
arm64: dts: mediatek: mt7986: drop "#reset-cells" from Ethernet controller
arm64: dts: mediatek: mt7986: drop invalid thermal block clock
arm64: dts: mediatek: mt7986: prefix BPI-R3 cooling maps with "map-"
arm64: dts: mediatek: mt2712: fix validation errors
Rajendra Nayak (1):
arm64: dts: qcom: x1e80100: Fix the compatible for cluster idle states
Rob Herring (2):
dt-bindings: rockchip: grf: Add missing type to 'pcie-phy' node
arm64: dts: rockchip: Fix USB interface compatible string on kobol-helios64
.../devicetree/bindings/soc/rockchip/grf.yaml | 1 +
.../boot/dts/microchip/at91-sama7g54_curiosity.dts | 8 +-
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 8 +-
.../boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +-
arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 8 +-
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 34 +++--
.../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 6 +-
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 8 +-
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 -
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi | 2 +-
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 6 +-
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 +
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 36 +++++-
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 5 +
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 +-
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 11 +-
arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 +-
arch/arm64/boot/dts/qcom/sm6375.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +-
arch/arm64/boot/dts/qcom/sm8450.dtsi | 16 +--
arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 +-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 +-
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 4 +-
.../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 3 +-
.../boot/dts/rockchip/rk3399-kobol-helios64.dts | 2 +-
.../boot/dts/rockchip/rk3399-pinebook-pro.dts | 1 -
.../arm64/boot/dts/rockchip/rk3399-puma-haikou.dts | 2 +
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 53 +++++++-
arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts | 1 -
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 6 +-
arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts | 1 -
.../arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi | 4 +-
.../boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 3 +-
.../arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 1 +
drivers/firmware/qcom/qcom_qseecom_uefisecapp.c | 137 ++++++++++++++-------
drivers/firmware/qcom/qcom_scm.c | 37 +-----
drivers/soc/mediatek/Kconfig | 1 +
drivers/soc/mediatek/mtk-svs.c | 7 +-
include/linux/firmware/qcom/qcom_qseecom.h | 55 ++++++++-
include/linux/firmware/qcom/qcom_scm.h | 10 +-
44 files changed, 331 insertions(+), 193 deletions(-)
^ permalink raw reply [relevance 4%]
* Re: [PATCH V2 RESEND 1/6] dt-bindings: clock: qcom: Add SM8650 video clock controller
2024-04-25 13:32 0% ` Vladimir Zapolskiy
@ 2024-04-26 14:26 0% ` Jagadeesh Kona
0 siblings, 0 replies; 200+ results
From: Jagadeesh Kona @ 2024-04-26 14:26 UTC (permalink / raw)
To: Vladimir Zapolskiy, Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
linux-clk, devicetree, linux-kernel, Taniya Das,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik,
Krzysztof Kozlowski
On 4/25/2024 7:02 PM, Vladimir Zapolskiy wrote:
> Hi Jagadeesh,
>
> On 4/22/24 14:00, Jagadeesh Kona wrote:
>>
>> On 4/19/2024 2:31 AM, Vladimir Zapolskiy wrote:
>>> Hello Jagadeesh,
>>>
>>> On 3/25/24 08:07, Jagadeesh Kona wrote:
>>>>
>>>>
>>>> On 3/21/2024 6:42 PM, Dmitry Baryshkov wrote:
>>>>> On Thu, 21 Mar 2024 at 11:26, Jagadeesh Kona <quic_jkona@quicinc.com>
>>>>> wrote:
>>>>>>
>>>>>> Extend device tree bindings of SM8450 videocc to add support
>>>>>> for SM8650 videocc. While it at, fix the incorrect header
>>>>>> include in sm8450 videocc yaml documentation.
>>>>>>
>>>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>>>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>>>> ---
>>>>>> .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 4
>>>>>> +++-
>>>>>> include/dt-bindings/clock/qcom,sm8450-videocc.h | 8
>>>>>> +++++++-
>>>>>> 2 files changed, 10 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git
>>>>>> a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>>>>>> b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>>>>>> index bad8f019a8d3..79f55620eb70 100644
>>>>>> ---
>>>>>> a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>>>>>> +++
>>>>>> b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>>>>>> @@ -8,18 +8,20 @@ title: Qualcomm Video Clock & Reset Controller on
>>>>>> SM8450
>>>>>>
>>>>>> maintainers:
>>>>>> - Taniya Das <quic_tdas@quicinc.com>
>>>>>> + - Jagadeesh Kona <quic_jkona@quicinc.com>
>>>>>>
>>>>>> description: |
>>>>>> Qualcomm video clock control module provides the clocks, resets
>>>>>> and power
>>>>>> domains on SM8450.
>>>>>>
>>>>>> - See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
>>>>>> + See also:: include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>>>
>>>>> This almost pleads to go to a separate patch. Fixes generally should
>>>>> be separated from the rest of the changes.
>>>>>
>>>>
>>>> Thanks Dmitry for your review.
>>>>
>>>> Sure, will separate this into a separate patch in next series.
>>>>
>>>>>>
>>>>>> properties:
>>>>>> compatible:
>>>>>> enum:
>>>>>> - qcom,sm8450-videocc
>>>>>> - qcom,sm8550-videocc
>>>>>> + - qcom,sm8650-videocc
>>>>>>
>>>>>> reg:
>>>>>> maxItems: 1
>>>>>> diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>>>> b/include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>>>> index 9d795adfe4eb..ecfebe52e4bb 100644
>>>>>> --- a/include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>>>> +++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>>>> @@ -1,6 +1,6 @@
>>>>>> /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>>>>>> /*
>>>>>> - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights
>>>>>> reserved.
>>>>>> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All
>>>>>> rights reserved.
>>>>>> */
>>>>>>
>>>>>> #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
>>>>>> @@ -19,6 +19,11 @@
>>>>>> #define
>>>>>> VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9
>>>>>> #define VIDEO_CC_PLL0 10
>>>>>> #define VIDEO_CC_PLL1 11
>>>>>> +#define
>>>>>> VIDEO_CC_MVS0_SHIFT_CLK 12
>>>>>> +#define VIDEO_CC_MVS0C_SHIFT_CLK 13
>>>>>> +#define
>>>>>> VIDEO_CC_MVS1_SHIFT_CLK 14
>>>>>> +#define VIDEO_CC_MVS1C_SHIFT_CLK 15
>>>>>> +#define VIDEO_CC_XO_CLK_SRC 16
>>>>>
>>>>> Are these values applicable to sm8450?
>>>>>
>>>>
>>>> No, the shift clocks above are part of SM8650 only. To reuse the
>>>> existing SM8550 videocc driver for SM8650 and to register these shift
>>>> clocks for SM8650, I added them here.
>>>>
>>>
>>> In such case I'd strongly suggest to add a new qcom,sm8650-videocc.h
>>> file,
>>> and do #include qcom,sm8450-videocc.h in it, thus the new header will be
>>> really a short one.
>>>
>>> This will add pristine clarity.
>>>
>>
>> Thanks Vladimir for your suggestion. I believe adding a comment for
>> these set of clocks should be sufficient to indicate these clocks are
>> applicable only for SM8650, I can add the required comment and post the
>> next series. Please let me know if this works?
>
> Well, I didn't get any new information to abandon my suggestion, what is
> wrong with it or why is it less preferable?
>
> Even if you add a comment in the header file, it means that for SM8450
> platforms you'll begin to define inapplicable/unrelated macro for the
> platform, which opens a small risk of the misusage, and which can be
> easily avoided. I believe that the clarity is better for maintenance.
>
Yes, I agree. Will check and move these new clocks to a separate header
file in next series. Thanks!
Thanks,
Jagadeesh
^ permalink raw reply [relevance 0%]
* Re: [PATCH v7 4/6] soc: qcom: qmi: add a way to remove running service
2024-04-24 9:28 4% ` [PATCH v7 4/6] soc: qcom: qmi: add a way to remove running service Dmitry Baryshkov
@ 2024-04-25 20:57 0% ` Chris Lew
0 siblings, 0 replies; 200+ results
From: Chris Lew @ 2024-04-25 20:57 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Konrad Dybcio, Sibi Sankar,
Mathieu Poirier
Cc: linux-arm-msm, linux-kernel, linux-remoteproc, Johan Hovold,
Xilin Wu, Bryan O'Donoghue, Neil Armstrong
On 4/24/2024 2:28 AM, Dmitry Baryshkov wrote:
> Add qmi_del_server(), a pair to qmi_add_server(), a way to remove
> running server from the QMI socket. This is e.g. necessary for
> pd-mapper, which needs to readd a server each time the DSP is started or
s/readd/read/
> stopped.
>
> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
<snip>
> +/**
> + * qmi_del_server() - register a service with the name service
Update comment to describe removal of service instead of 'register'.
^ permalink raw reply [relevance 0%]
* Re: [PATCH v7 1/6] soc: qcom: pdr: protect locator_addr with the main mutex
2024-04-24 9:27 4% ` [PATCH v7 1/6] soc: qcom: pdr: protect locator_addr with the main mutex Dmitry Baryshkov
@ 2024-04-25 19:30 0% ` Chris Lew
2024-05-11 21:52 0% ` Dmitry Baryshkov
0 siblings, 1 reply; 200+ results
From: Chris Lew @ 2024-04-25 19:30 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Konrad Dybcio, Sibi Sankar,
Mathieu Poirier
Cc: linux-arm-msm, linux-kernel, linux-remoteproc, Johan Hovold,
Xilin Wu, Bryan O'Donoghue, Neil Armstrong
On 4/24/2024 2:27 AM, Dmitry Baryshkov wrote:
> If the service locator server is restarted fast enough, the PDR can
> rewrite locator_addr fields concurrently. Protect them by placing
> modification of those fields under the main pdr->lock.
>
> Fixes: fbe639b44a82 ("soc: qcom: Introduce Protection Domain Restart helpers")
> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/soc/qcom/pdr_interface.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/qcom/pdr_interface.c b/drivers/soc/qcom/pdr_interface.c
> index a1b6a4081dea..19cfe4b41235 100644
> --- a/drivers/soc/qcom/pdr_interface.c
> +++ b/drivers/soc/qcom/pdr_interface.c
> @@ -76,12 +76,12 @@ static int pdr_locator_new_server(struct qmi_handle *qmi,
> locator_hdl);
> struct pdr_service *pds;
>
> + mutex_lock(&pdr->lock);
> /* Create a local client port for QMI communication */
> pdr->locator_addr.sq_family = AF_QIPCRTR;
> pdr->locator_addr.sq_node = svc->node;
> pdr->locator_addr.sq_port = svc->port;
>
> - mutex_lock(&pdr->lock);
> pdr->locator_init_complete = true;
> mutex_unlock(&pdr->lock);
>
> @@ -104,10 +104,10 @@ static void pdr_locator_del_server(struct qmi_handle *qmi,
>
> mutex_lock(&pdr->lock);
> pdr->locator_init_complete = false;
> - mutex_unlock(&pdr->lock);
>
> pdr->locator_addr.sq_node = 0;
> pdr->locator_addr.sq_port = 0;
> + mutex_unlock(&pdr->lock);
> }
>
> static const struct qmi_ops pdr_locator_ops = {
>
These two functions are provided as qmi_ops handlers in pdr_locator_ops.
Aren't they serialized in the qmi handle's workqueue since it as an
ordered_workqueue? Even in a fast pdr scenario I don't think we would
see a race condition between these two functions.
The other access these two functions do race against is in the
pdr_notifier_work. I think you would need to protect locator_addr in
pdr_get_domain_list since the qmi_send_request there uses
'pdr->locator_addr'.
Thanks!
Chris
^ permalink raw reply [relevance 0%]
* Re: [PATCH V2 RESEND 1/6] dt-bindings: clock: qcom: Add SM8650 video clock controller
2024-04-22 11:00 0% ` Jagadeesh Kona
@ 2024-04-25 13:32 0% ` Vladimir Zapolskiy
2024-04-26 14:26 0% ` Jagadeesh Kona
0 siblings, 1 reply; 200+ results
From: Vladimir Zapolskiy @ 2024-04-25 13:32 UTC (permalink / raw)
To: Jagadeesh Kona, Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
linux-clk, devicetree, linux-kernel, Taniya Das,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik,
Krzysztof Kozlowski
Hi Jagadeesh,
On 4/22/24 14:00, Jagadeesh Kona wrote:
>
> On 4/19/2024 2:31 AM, Vladimir Zapolskiy wrote:
>> Hello Jagadeesh,
>>
>> On 3/25/24 08:07, Jagadeesh Kona wrote:
>>>
>>>
>>> On 3/21/2024 6:42 PM, Dmitry Baryshkov wrote:
>>>> On Thu, 21 Mar 2024 at 11:26, Jagadeesh Kona <quic_jkona@quicinc.com>
>>>> wrote:
>>>>>
>>>>> Extend device tree bindings of SM8450 videocc to add support
>>>>> for SM8650 videocc. While it at, fix the incorrect header
>>>>> include in sm8450 videocc yaml documentation.
>>>>>
>>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>>> ---
>>>>> .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 4 +++-
>>>>> include/dt-bindings/clock/qcom,sm8450-videocc.h | 8
>>>>> +++++++-
>>>>> 2 files changed, 10 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git
>>>>> a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>>>>> b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>>>>> index bad8f019a8d3..79f55620eb70 100644
>>>>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>>>>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>>>>> @@ -8,18 +8,20 @@ title: Qualcomm Video Clock & Reset Controller on
>>>>> SM8450
>>>>>
>>>>> maintainers:
>>>>> - Taniya Das <quic_tdas@quicinc.com>
>>>>> + - Jagadeesh Kona <quic_jkona@quicinc.com>
>>>>>
>>>>> description: |
>>>>> Qualcomm video clock control module provides the clocks, resets
>>>>> and power
>>>>> domains on SM8450.
>>>>>
>>>>> - See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
>>>>> + See also:: include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>>
>>>> This almost pleads to go to a separate patch. Fixes generally should
>>>> be separated from the rest of the changes.
>>>>
>>>
>>> Thanks Dmitry for your review.
>>>
>>> Sure, will separate this into a separate patch in next series.
>>>
>>>>>
>>>>> properties:
>>>>> compatible:
>>>>> enum:
>>>>> - qcom,sm8450-videocc
>>>>> - qcom,sm8550-videocc
>>>>> + - qcom,sm8650-videocc
>>>>>
>>>>> reg:
>>>>> maxItems: 1
>>>>> diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>>> b/include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>>> index 9d795adfe4eb..ecfebe52e4bb 100644
>>>>> --- a/include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>>> +++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>>> @@ -1,6 +1,6 @@
>>>>> /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>>>>> /*
>>>>> - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights
>>>>> reserved.
>>>>> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All
>>>>> rights reserved.
>>>>> */
>>>>>
>>>>> #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
>>>>> @@ -19,6 +19,11 @@
>>>>> #define
>>>>> VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9
>>>>> #define VIDEO_CC_PLL0 10
>>>>> #define VIDEO_CC_PLL1 11
>>>>> +#define
>>>>> VIDEO_CC_MVS0_SHIFT_CLK 12
>>>>> +#define VIDEO_CC_MVS0C_SHIFT_CLK 13
>>>>> +#define
>>>>> VIDEO_CC_MVS1_SHIFT_CLK 14
>>>>> +#define VIDEO_CC_MVS1C_SHIFT_CLK 15
>>>>> +#define VIDEO_CC_XO_CLK_SRC 16
>>>>
>>>> Are these values applicable to sm8450?
>>>>
>>>
>>> No, the shift clocks above are part of SM8650 only. To reuse the
>>> existing SM8550 videocc driver for SM8650 and to register these shift
>>> clocks for SM8650, I added them here.
>>>
>>
>> In such case I'd strongly suggest to add a new qcom,sm8650-videocc.h file,
>> and do #include qcom,sm8450-videocc.h in it, thus the new header will be
>> really a short one.
>>
>> This will add pristine clarity.
>>
>
> Thanks Vladimir for your suggestion. I believe adding a comment for
> these set of clocks should be sufficient to indicate these clocks are
> applicable only for SM8650, I can add the required comment and post the
> next series. Please let me know if this works?
Well, I didn't get any new information to abandon my suggestion, what is
wrong with it or why is it less preferable?
Even if you add a comment in the header file, it means that for SM8450
platforms you'll begin to define inapplicable/unrelated macro for the
platform, which opens a small risk of the misusage, and which can be
easily avoided. I believe that the clarity is better for maintenance.
--
Best wishes,
Vladimir
^ permalink raw reply [relevance 0%]
* Re: [PATCH 10/10] arm64: dts: qcom: Add AYN Odin 2
2024-04-24 15:29 8% ` Xilin Wu
(?)
@ 2024-04-25 6:28 0% ` Krzysztof Kozlowski
2024-04-28 3:54 0% ` Xilin Wu
-1 siblings, 1 reply; 200+ results
From: Krzysztof Kozlowski @ 2024-04-25 6:28 UTC (permalink / raw)
To: wuxilin123, Uwe Kleine-König, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Junhao Xie, Neil Armstrong,
Jessica Zhang, Sam Ravnborg, David Airlie, Daniel Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Bjorn Andersson, Konrad Dybcio, Tengfei Fan, Molly Sophia
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm
On 24/04/2024 17:29, Xilin Wu via B4 Relay wrote:
> From: Xilin Wu <wuxilin123@gmail.com>
>
> AYN Odin 2 is a gaming handheld based on QCS8550, which is derived
> from SM8550 but without modem RF system.
>
> +
> +/ {
> + model = "AYN Odin 2";
> + compatible = "ayn,odin2", "qcom,qcs8550", "qcom,sm8550";
> + chassis-type = "handset";
> +
> + qcom,msm-id = <QCOM_ID_QCS8550 0x20000>;
> + qcom,board-id = <0x1001f 0>;
No, these are not allowed. You did not test your dts.
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
> +
> + aliases {
> + serial0 = &uart7;
> + serial1 = &uart14;
> + serial2 = &uart15;
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pmk8550_pwm 0 860000>;
> + brightness-levels = <1023 0>;
> + num-interpolated-steps = <1023>;
> + default-brightness-level = <600>;
> + power-supply = <&vph_pwr>;
> + enable-gpios = <&pmk8550_gpios 5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm_backlight_default>;
> + status = "okay";
Drop, why do you need it? Do you see it anywhere else in the backlight
nodes in DTS?
> + };
> +
> + fan_pwr: fan-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "fan_pwr";
> +
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> +
> + gpio = <&tlmm 109 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&fan_pwr_en>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + pinctrl-0 = <&volume_up_n>, <&m1_m2_keys_default>;
> + pinctrl-names = "default";
> +
> + key-volume-up {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
> + debounce-interval = <15>;
> + linux,can-disable;
> + wakeup-source;
> + };
> +
> + m1-button {
> + label = "M1";
> + linux,code = <BTN_TRIGGER_HAPPY1>;
> + gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
> + };
> +
> + m2-button {
> + label = "M2";
> + linux,code = <BTN_TRIGGER_HAPPY2>;
> + gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + hdmi-out {
> + compatible = "hdmi-connector";
> + type = "d";
> + hpd-gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>;
> +
> + port {
> + hdmi_con: endpoint {
> + remote-endpoint = <<8912_out>;
> + };
> + };
> + };
> +
> + hdmi_pwr: hdmi-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "hdmi_pwr";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + gpio = <&tlmm 10 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + vdd_lcm_2p8: vdd-lcm-2p8-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd_lcm_2p8";
> +
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> +
> + gpio = <&tlmm 142 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + led_left_side: led-controller-1 {
> + compatible = "pwm-leds-multicolor";
> +
> + multi-led {
> + label = "left-side";
> + color = <LED_COLOR_ID_RGB>;
> + max-brightness = <255>;
> +
> + led-red {
> + color = <LED_COLOR_ID_RED>;
> + pwms = <&pwm_rgb_left 0>;
> + };
> +
> + led-green {
> + color = <LED_COLOR_ID_GREEN>;
> + pwms = <&pwm_rgb_left 1>;
> + };
> +
> + led-blue {
> + color = <LED_COLOR_ID_BLUE>;
> + pwms = <&pwm_rgb_left 2>;
> + };
> + };
> + };
> +
> + led_left_joystick: led-controller-2 {
> + compatible = "pwm-leds-multicolor";
> +
> + multi-led {
> + label = "left-joystick";
> + color = <LED_COLOR_ID_RGB>;
> + max-brightness = <255>;
> +
> + led-red {
> + color = <LED_COLOR_ID_RED>;
> + pwms = <&pwm_rgb_left 6>;
> + };
> +
> + led-green {
> + color = <LED_COLOR_ID_GREEN>;
> + pwms = <&pwm_rgb_left 7>;
> + };
> +
> + led-blue {
> + color = <LED_COLOR_ID_BLUE>;
> + pwms = <&pwm_rgb_left 8>;
> + };
> + };
> + };
> +
> + led_right_side: led-controller-3 {
> + compatible = "pwm-leds-multicolor";
> +
> + multi-led {
> + label = "right-side";
> + color = <LED_COLOR_ID_RGB>;
> + max-brightness = <255>;
> +
> + led-red {
> + color = <LED_COLOR_ID_RED>;
> + pwms = <&pwm_rgb_right 0>;
> + };
> +
> + led-green {
> + color = <LED_COLOR_ID_GREEN>;
> + pwms = <&pwm_rgb_right 1>;
> + };
> +
> + led-blue {
> + color = <LED_COLOR_ID_BLUE>;
> + pwms = <&pwm_rgb_right 2>;
> + };
> + };
> + };
> +
> + led_right_joystick: led-controller-4 {
> + compatible = "pwm-leds-multicolor";
> +
> + multi-led {
> + label = "right-joystick";
> + color = <LED_COLOR_ID_RGB>;
> + max-brightness = <255>;
> +
> + led-red {
> + color = <LED_COLOR_ID_RED>;
> + pwms = <&pwm_rgb_right 6>;
> + };
> +
> + led-green {
> + color = <LED_COLOR_ID_GREEN>;
> + pwms = <&pwm_rgb_right 7>;
> + };
> +
> + led-blue {
> + color = <LED_COLOR_ID_BLUE>;
> + pwms = <&pwm_rgb_right 8>;
> + };
> + };
> + };
> +
> + mcu_3v3: mcu-3v3-regulator {
Name all regulators regulator-n, where n is decimal number. Then order
the nodes by name.
...
> +
> +&i2c4 {
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + touchscreen@20 {
> + compatible = "syna,rmi4-i2c";
> + reg = <0x20>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts-extended = <&tlmm 25 0x2008>;
> +
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&ts_int_default>;
> + pinctrl-1 = <&ts_int_sleep>;
> +
> + vio-supply = <&vreg_l12b_1p8>;
> +
> + syna,startup-delay-ms = <200>;
> + syna,reset-delay-ms = <200>;
> +
> + rmi4-f01@1 {
> + syna,nosleep-mode = <0x1>;
> + reg = <0x1>;
> + };
> +
> + rmi4-f12@12 {
> + reg = <0x12>;
> + syna,rezero-wait-ms = <20>;
> + syna,clip-x-low = <0>;
> + syna,clip-y-low = <0>;
> + syna,clip-x-high = <1080>;
> + syna,clip-y-high = <1920>;
> + syna,sensor-type = <1>;
> + touchscreen-inverted-x;
> + };
> + };
Please confirm the status of dtbs_check for your board. I am pretty sure
it fails.
Best regards,
Krzysztof
^ permalink raw reply [relevance 0%]
* Re: [PATCH v7 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT
2024-04-24 23:50 0% ` Dmitry Baryshkov
@ 2024-04-25 3:23 0% ` Tengfei Fan
0 siblings, 0 replies; 200+ results
From: Tengfei Fan @ 2024-04-25 3:23 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: andersson, konrad.dybcio, robh, krzk+dt, conor+dt, keescook,
tony.luck, gpiccoli, linux-arm-msm, devicetree, linux-kernel,
linux-hardening, kernel, Qiang Yu, Ziyue Zhang
On 4/25/2024 7:50 AM, Dmitry Baryshkov wrote:
> On Wed, 24 Apr 2024 at 05:46, Tengfei Fan <quic_tengfan@quicinc.com> wrote:
>>
>> Add AIM300 AIoT Carrier board DTS support, including usb, UART, PCIe,
>> I2C functions support.
>> Here is a diagram of AIM300 AIoT Carrie Board and SoM
>> +--------------------------------------------------+
>> | AIM300 AIOT Carrier Board |
>> | |
>> | +-----------------+ |
>> |power----->| Fixed regulator |---------+ |
>> | +-----------------+ | |
>> | | |
>> | v VPH_PWR |
>> | +----------------------------------------------+ |
>> | | AIM300 SOM | | |
>> | | |VPH_PWR | |
>> | | v | |
>> | | +-------+ +--------+ +------+ | |
>> | | | UFS | | QCS8550| |PMIC | | |
>> | | +-------+ +--------+ +------+ | |
>> | | | |
>> | +----------------------------------------------+ |
>> | |
>> | +----+ +------+ |
>> | |USB | | UART | |
>> | +----+ +------+ |
>> +--------------------------------------------------+
>>
>> Co-developed-by: Qiang Yu <quic_qianyu@quicinc.com>
>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
>> Co-developed-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
>> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> .../boot/dts/qcom/qcs8550-aim300-aiot.dts | 343 ++++++++++++++++++
>> 2 files changed, 344 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index f63abb43e9fe..c46c10d85697 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -96,6 +96,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
>> new file mode 100644
>> index 000000000000..146bf6ea9e6a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
>> @@ -0,0 +1,343 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/leds/common.h>
>> +#include "qcs8550-aim300.dtsi"
>> +#include "pm8010.dtsi"
>> +#include "pmr735d_a.dtsi"
>> +#include "pmr735d_b.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. QCS8550 AIM300 AIOT";
>> + compatible = "qcom,qcs8550-aim300-aiot", "qcom,qcs8550-aim300", "qcom,qcs8550",
>> + "qcom,sm8550";
>> +
>> + aliases {
>> + serial0 = &uart7;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> +
>> + pinctrl-0 = <&volume_up_n>;
>> + pinctrl-names = "default";
>> +
>> + key-volume-up {
>> + label = "Volume Up";
>> + debounce-interval = <15>;
>> + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
>> + linux,code = <KEY_VOLUMEUP>;
>> + linux,can-disable;
>> + wakeup-source;
>> + };
>> + };
>> +
>> + pmic-glink {
>> + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
>> +
>> + connector@0 {
>> + compatible = "usb-c-connector";
>> + reg = <0>;
>> + power-role = "dual";
>> + data-role = "dual";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> +
>> + pmic_glink_hs_in: endpoint {
>> + remote-endpoint = <&usb_1_dwc3_hs>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> +
>> + pmic_glink_ss_in: endpoint {
>> + remote-endpoint = <&redriver_ss_out>;
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <2>;
>> +
>> + pmic_glink_sbu: endpoint {
>> + remote-endpoint = <&fsa4480_sbu_mux>;
>> + };
>> + };
>> + };
>> + };
>> + };
>> +
>> + vph_pwr: regulator-vph-pwr {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vph_pwr";
>> + regulator-min-microvolt = <3700000>;
>> + regulator-max-microvolt = <3700000>;
>> +
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +};
>> +
>> +&apps_rsc {
>> + regulators-0 {
>> + vdd-bob1-supply = <&vph_pwr>;
>> + vdd-bob2-supply = <&vph_pwr>;
>> + };
>> +
>> + regulators-3 {
>> + vdd-s4-supply = <&vph_pwr>;
>> + vdd-s5-supply = <&vph_pwr>;
>> + };
>> +
>> + regulators-4 {
>> + vdd-s4-supply = <&vph_pwr>;
>> + };
>> +
>> + regulators-5 {
>> + vdd-s1-supply = <&vph_pwr>;
>> + vdd-s2-supply = <&vph_pwr>;
>> + vdd-s3-supply = <&vph_pwr>;
>> + vdd-s4-supply = <&vph_pwr>;
>> + vdd-s5-supply = <&vph_pwr>;
>> + vdd-s6-supply = <&vph_pwr>;
>> + };
>> +};
>> +
>> +&i2c_hub_2 {
>> + status = "okay";
>> +
>> + typec-mux@42 {
>> + compatible = "fcs,fsa4480";
>> + reg = <0x42>;
>> +
>> + vcc-supply = <&vreg_bob1>;
>> +
>> + mode-switch;
>> + orientation-switch;
>> +
>> + port {
>> + fsa4480_sbu_mux: endpoint {
>> + remote-endpoint = <&pmic_glink_sbu>;
>> + };
>> + };
>> + };
>> +
>> + typec-retimer@1c {
>> + compatible = "onnn,nb7vpq904m";
>> + reg = <0x1c>;
>> +
>> + vcc-supply = <&vreg_l15b_1p8>;
>> +
>> + orientation-switch;
>> + retimer-switch;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> +
>> + redriver_ss_out: endpoint {
>> + remote-endpoint = <&pmic_glink_ss_in>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> +
>> + redriver_ss_in: endpoint {
>> + data-lanes = <3 2 1 0>;
>> + remote-endpoint = <&usb_dp_qmpphy_out>;
>> + };
>> + };
>> + };
>> + };
>> +};
>> +
>> +&mdss_dsi0 {
>> + status = "okay";
>> +
>> + panel@0 {
>> + compatible = "visionox,vtdr6130";
>> + reg = <0>;
>> +
>> + pinctrl-0 = <&dsi_active>, <&te_active>;
>> + pinctrl-1 = <&dsi_suspend>, <&te_suspend>;
>> + pinctrl-names = "default", "sleep";
>> +
>> + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
>> +
>> + vci-supply = <&vreg_l13b_3p0>;
>> + vdd-supply = <&vreg_l11b_1p2>;
>> + vddio-supply = <&vreg_l12b_1p8>;
>> +
>> + port {
>> + panel0_in: endpoint {
>> + remote-endpoint = <&mdss_dsi0_out>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&mdss_dsi0_out {
>> + remote-endpoint = <&panel0_in>;
>> + data-lanes = <0 1 2 3>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> + status = "okay";
>> +};
>> +
>> +&pcie0 {
>> + pinctrl-0 = <&pcie0_default_state>;
>> + pinctrl-names = "default";
>> +
>> + status = "okay";
>> +};
>> +
>> +&pcie0_phy {
>> + status = "okay";
>> +};
>> +
>> +&pcie1 {
>> + pinctrl-0 = <&pcie1_default_state>;
>> + pinctrl-names = "default";
>> +
>> + status = "okay";
>> +};
>> +
>> +&pcie1_phy {
>> + status = "okay";
>> +};
>> +
>> +&pm8550_gpios {
>> + volume_up_n: volume-up-n-state {
>> + pins = "gpio6";
>> + function = "normal";
>> + power-source = <1>;
>> + bias-pull-up;
>> + input-enable;
>> + };
>> +};
>> +
>> +&pon_pwrkey {
>> + status = "okay";
>> +};
>> +
>> +&pon_resin {
>> + linux,code = <KEY_VOLUMEDOWN>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&qupv3_id_0 {
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_adsp {
>> + firmware-name = "qcom/qcs8550/adsp.mbn",
>> + "qcom/qcs8550/adsp_dtbs.elf";
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_cdsp {
>> + firmware-name = "qcom/qcs8550/cdsp.mbn",
>> + "qcom/qcs8550/cdsp_dtbs.elf";
>> + status = "okay";
>> +};
>> +
>> +&swr1 {
>> + status = "okay";
>> +};
>> +
>> +&swr2 {
>> + status = "okay";
>> +};
>> +
>> +&tlmm {
>> + gpio-reserved-ranges = <32 8>;
>> +
>> + dsi_active: dsi-active-state {
>> + pins = "gpio133";
>> + function = "gpio";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> +
>> + dsi_suspend: dsi-suspend-state {
>> + pins = "gpio133";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + te_active: te-active-state {
>> + pins = "gpio86";
>> + function = "mdp_vsync";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + te_suspend: te-suspend-state {
>> + pins = "gpio86";
>> + function = "mdp_vsync";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +};
>> +
>> +&uart7 {
>> + status = "okay";
>> +};
>> +
>> +&usb_1 {
>> + status = "okay";
>> +};
>> +
>> +&usb_1_dwc3 {
>> + dr_mode = "otg";
>
> OTG is default and can be dropped.
OTG will be dropped.
>
>> + usb-role-switch;
>
> Please move to SoC dtsi and drop from board files.
This will be moved to SoC dtsi.
>
>> +};
>> +
>> +&usb_1_dwc3_hs {
>> + remote-endpoint = <&pmic_glink_hs_in>;
>> +};
>> +
>> +&usb_1_dwc3_ss {
>> + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
>
> This too.
This will be moved to SoC dtsi.
>
>> +};
>> +
>> +&usb_1_hsphy {
>> + status = "okay";
>> +};
>> +
>> +&usb_dp_qmpphy {
>> + orientation-switch;
>
> This too
This will be moved to SoC dtsi.
>
>> +
>> + status = "okay";
>> +};
>> +
>> +&usb_dp_qmpphy_out {
>> + remote-endpoint = <&redriver_ss_in>;
>> +};
>> +
>> +&usb_dp_qmpphy_usb_ss_in {
>> + remote-endpoint = <&usb_1_dwc3_ss>;
>
> And this.
This will be moved to SoC dtsi.
>
>> +};
>> --
>> 2.25.1
>>
>
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [relevance 0%]
* Re: [PATCH v7 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT
2024-04-24 2:45 5% ` [PATCH v7 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT Tengfei Fan
@ 2024-04-24 23:50 0% ` Dmitry Baryshkov
2024-04-25 3:23 0% ` Tengfei Fan
0 siblings, 1 reply; 200+ results
From: Dmitry Baryshkov @ 2024-04-24 23:50 UTC (permalink / raw)
To: Tengfei Fan
Cc: andersson, konrad.dybcio, robh, krzk+dt, conor+dt, keescook,
tony.luck, gpiccoli, linux-arm-msm, devicetree, linux-kernel,
linux-hardening, kernel, Qiang Yu, Ziyue Zhang
On Wed, 24 Apr 2024 at 05:46, Tengfei Fan <quic_tengfan@quicinc.com> wrote:
>
> Add AIM300 AIoT Carrier board DTS support, including usb, UART, PCIe,
> I2C functions support.
> Here is a diagram of AIM300 AIoT Carrie Board and SoM
> +--------------------------------------------------+
> | AIM300 AIOT Carrier Board |
> | |
> | +-----------------+ |
> |power----->| Fixed regulator |---------+ |
> | +-----------------+ | |
> | | |
> | v VPH_PWR |
> | +----------------------------------------------+ |
> | | AIM300 SOM | | |
> | | |VPH_PWR | |
> | | v | |
> | | +-------+ +--------+ +------+ | |
> | | | UFS | | QCS8550| |PMIC | | |
> | | +-------+ +--------+ +------+ | |
> | | | |
> | +----------------------------------------------+ |
> | |
> | +----+ +------+ |
> | |USB | | UART | |
> | +----+ +------+ |
> +--------------------------------------------------+
>
> Co-developed-by: Qiang Yu <quic_qianyu@quicinc.com>
> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
> Co-developed-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> .../boot/dts/qcom/qcs8550-aim300-aiot.dts | 343 ++++++++++++++++++
> 2 files changed, 344 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index f63abb43e9fe..c46c10d85697 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -96,6 +96,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
> diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
> new file mode 100644
> index 000000000000..146bf6ea9e6a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
> @@ -0,0 +1,343 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/leds/common.h>
> +#include "qcs8550-aim300.dtsi"
> +#include "pm8010.dtsi"
> +#include "pmr735d_a.dtsi"
> +#include "pmr735d_b.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. QCS8550 AIM300 AIOT";
> + compatible = "qcom,qcs8550-aim300-aiot", "qcom,qcs8550-aim300", "qcom,qcs8550",
> + "qcom,sm8550";
> +
> + aliases {
> + serial0 = &uart7;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + pinctrl-0 = <&volume_up_n>;
> + pinctrl-names = "default";
> +
> + key-volume-up {
> + label = "Volume Up";
> + debounce-interval = <15>;
> + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_VOLUMEUP>;
> + linux,can-disable;
> + wakeup-source;
> + };
> + };
> +
> + pmic-glink {
> + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
> +
> + connector@0 {
> + compatible = "usb-c-connector";
> + reg = <0>;
> + power-role = "dual";
> + data-role = "dual";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + pmic_glink_hs_in: endpoint {
> + remote-endpoint = <&usb_1_dwc3_hs>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + pmic_glink_ss_in: endpoint {
> + remote-endpoint = <&redriver_ss_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + pmic_glink_sbu: endpoint {
> + remote-endpoint = <&fsa4480_sbu_mux>;
> + };
> + };
> + };
> + };
> + };
> +
> + vph_pwr: regulator-vph-pwr {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +};
> +
> +&apps_rsc {
> + regulators-0 {
> + vdd-bob1-supply = <&vph_pwr>;
> + vdd-bob2-supply = <&vph_pwr>;
> + };
> +
> + regulators-3 {
> + vdd-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + };
> +
> + regulators-4 {
> + vdd-s4-supply = <&vph_pwr>;
> + };
> +
> + regulators-5 {
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-supply = <&vph_pwr>;
> + vdd-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + vdd-s6-supply = <&vph_pwr>;
> + };
> +};
> +
> +&i2c_hub_2 {
> + status = "okay";
> +
> + typec-mux@42 {
> + compatible = "fcs,fsa4480";
> + reg = <0x42>;
> +
> + vcc-supply = <&vreg_bob1>;
> +
> + mode-switch;
> + orientation-switch;
> +
> + port {
> + fsa4480_sbu_mux: endpoint {
> + remote-endpoint = <&pmic_glink_sbu>;
> + };
> + };
> + };
> +
> + typec-retimer@1c {
> + compatible = "onnn,nb7vpq904m";
> + reg = <0x1c>;
> +
> + vcc-supply = <&vreg_l15b_1p8>;
> +
> + orientation-switch;
> + retimer-switch;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + redriver_ss_out: endpoint {
> + remote-endpoint = <&pmic_glink_ss_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + redriver_ss_in: endpoint {
> + data-lanes = <3 2 1 0>;
> + remote-endpoint = <&usb_dp_qmpphy_out>;
> + };
> + };
> + };
> + };
> +};
> +
> +&mdss_dsi0 {
> + status = "okay";
> +
> + panel@0 {
> + compatible = "visionox,vtdr6130";
> + reg = <0>;
> +
> + pinctrl-0 = <&dsi_active>, <&te_active>;
> + pinctrl-1 = <&dsi_suspend>, <&te_suspend>;
> + pinctrl-names = "default", "sleep";
> +
> + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
> +
> + vci-supply = <&vreg_l13b_3p0>;
> + vdd-supply = <&vreg_l11b_1p2>;
> + vddio-supply = <&vreg_l12b_1p8>;
> +
> + port {
> + panel0_in: endpoint {
> + remote-endpoint = <&mdss_dsi0_out>;
> + };
> + };
> + };
> +};
> +
> +&mdss_dsi0_out {
> + remote-endpoint = <&panel0_in>;
> + data-lanes = <0 1 2 3>;
> +};
> +
> +&mdss_dsi0_phy {
> + status = "okay";
> +};
> +
> +&pcie0 {
> + pinctrl-0 = <&pcie0_default_state>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> +&pcie0_phy {
> + status = "okay";
> +};
> +
> +&pcie1 {
> + pinctrl-0 = <&pcie1_default_state>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> +&pcie1_phy {
> + status = "okay";
> +};
> +
> +&pm8550_gpios {
> + volume_up_n: volume-up-n-state {
> + pins = "gpio6";
> + function = "normal";
> + power-source = <1>;
> + bias-pull-up;
> + input-enable;
> + };
> +};
> +
> +&pon_pwrkey {
> + status = "okay";
> +};
> +
> +&pon_resin {
> + linux,code = <KEY_VOLUMEDOWN>;
> +
> + status = "okay";
> +};
> +
> +&qupv3_id_0 {
> + status = "okay";
> +};
> +
> +&remoteproc_adsp {
> + firmware-name = "qcom/qcs8550/adsp.mbn",
> + "qcom/qcs8550/adsp_dtbs.elf";
> + status = "okay";
> +};
> +
> +&remoteproc_cdsp {
> + firmware-name = "qcom/qcs8550/cdsp.mbn",
> + "qcom/qcs8550/cdsp_dtbs.elf";
> + status = "okay";
> +};
> +
> +&swr1 {
> + status = "okay";
> +};
> +
> +&swr2 {
> + status = "okay";
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <32 8>;
> +
> + dsi_active: dsi-active-state {
> + pins = "gpio133";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-disable;
> + };
> +
> + dsi_suspend: dsi-suspend-state {
> + pins = "gpio133";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + te_active: te-active-state {
> + pins = "gpio86";
> + function = "mdp_vsync";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + te_suspend: te-suspend-state {
> + pins = "gpio86";
> + function = "mdp_vsync";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +};
> +
> +&uart7 {
> + status = "okay";
> +};
> +
> +&usb_1 {
> + status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> + dr_mode = "otg";
OTG is default and can be dropped.
> + usb-role-switch;
Please move to SoC dtsi and drop from board files.
> +};
> +
> +&usb_1_dwc3_hs {
> + remote-endpoint = <&pmic_glink_hs_in>;
> +};
> +
> +&usb_1_dwc3_ss {
> + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
This too.
> +};
> +
> +&usb_1_hsphy {
> + status = "okay";
> +};
> +
> +&usb_dp_qmpphy {
> + orientation-switch;
This too
> +
> + status = "okay";
> +};
> +
> +&usb_dp_qmpphy_out {
> + remote-endpoint = <&redriver_ss_in>;
> +};
> +
> +&usb_dp_qmpphy_usb_ss_in {
> + remote-endpoint = <&usb_1_dwc3_ss>;
And this.
> +};
> --
> 2.25.1
>
--
With best wishes
Dmitry
^ permalink raw reply [relevance 0%]
* Re: [PATCH 06/10] arm64: dts: qcom: sm8550: Add UART15
2024-04-24 15:29 16% ` Xilin Wu
(?)
@ 2024-04-24 23:39 4% ` Dmitry Baryshkov
-1 siblings, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-24 23:39 UTC (permalink / raw)
To: wuxilin123
Cc: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, linux-pwm, devicetree, linux-kernel,
dri-devel, linux-arm-msm
On Wed, 24 Apr 2024 at 18:30, Xilin Wu via B4 Relay
<devnull+wuxilin123.gmail.com@kernel.org> wrote:
>
> From: Xilin Wu <wuxilin123@gmail.com>
>
> Add uart15 node for UART bus present on sm8550 SoC.
>
> Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
> Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [relevance 4%]
* Re: [PATCH 07/10] arm64: dts: qcom: sm8550: Update EAS properties
2024-04-24 15:29 12% ` Xilin Wu
(?)
@ 2024-04-24 22:45 4% ` Bryan O'Donoghue
2024-04-28 3:43 4% ` Xilin Wu
-1 siblings, 1 reply; 200+ results
From: Bryan O'Donoghue @ 2024-04-24 22:45 UTC (permalink / raw)
To: wuxilin123, Uwe Kleine-König, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Junhao Xie, Neil Armstrong,
Jessica Zhang, Sam Ravnborg, David Airlie, Daniel Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Bjorn Andersson, Konrad Dybcio, Tengfei Fan, Molly Sophia
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm
On 24/04/2024 16:29, Xilin Wu via B4 Relay wrote:
> From: Xilin Wu <wuxilin123@gmail.com>
>
> The original values provided by Qualcomm appear to be quite
> inaccurate. Specifically, some heavy gaming tasks could be
> improperly assigned to the A510 cores by the scheduler, resulting
> in a CPU bottleneck. This update to the EAS properties aims to
> enhance the user experience across various scenarios.
>
> The power numbers were obtained using a Type-C power meter, which
> was directly connected to the battery connector on the AYN Odin 2
> motherboard, acting as a fake battery.
>
> It should be noted that the A715 cores seem less efficient than the
> A710 cores. Therefore, an average value has been assigned to them,
> considering that the A715 and A710 cores share a single cpufreq
> domain.
>
> Cortex-A510 cores:
> 441 kHz, 564 mV, 43 mW, 350 Cx
> 556 kHz, 580 mV, 59 mW, 346 Cx
> 672 kHz, 592 mV, 71 mW, 312 Cx
> 787 kHz, 604 mV, 83 mW, 290 Cx
> 902 kHz, 608 mV, 96 mW, 288 Cx
> 1017 kHz, 624 mV, 107 mW, 264 Cx
> 1113 kHz, 636 mV, 117 mW, 252 Cx
> 1228 kHz, 652 mV, 130 mW, 240 Cx
> 1344 kHz, 668 mV, 146 mW, 235 Cx
> 1459 kHz, 688 mV, 155 mW, 214 Cx
> 1555 kHz, 704 mV, 166 mW, 205 Cx
> 1670 kHz, 724 mV, 178 mW, 192 Cx
> 1785 kHz, 744 mV, 197 mW, 189 Cx
> 1900 kHz, 764 mV, 221 mW, 190 Cx
> 2016 kHz, 784 mV, 243 mW, 188 Cx
> Your dynamic-power-coefficient for cpu 1: 251
This looks pretty convincing and like good work.
A few questions and suggestions for your commit log.
I'd really love to know more about how you ran this test. What values
exactly does your power meter give you?
How did you lock the core to a specific CPU frequency ?
Maybe also give the equation to calculate Pdyn in the commit log.
https://patchwork.kernel.org/project/linux-arm-kernel/patch/1500974575-2244-1-git-send-email-wxt@rock-chips.com/#20763985
---
bod
^ permalink raw reply [relevance 4%]
* [PATCH 06/10] arm64: dts: qcom: sm8550: Add UART15
2024-04-24 15:29 6% ` Xilin Wu
@ 2024-04-24 15:29 16% ` Xilin Wu
-1 siblings, 0 replies; 200+ results
From: Xilin Wu via B4 Relay @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm, Xilin Wu
From: Xilin Wu <wuxilin123@gmail.com>
Add uart15 node for UART bus present on sm8550 SoC.
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index bc5aeb05ffc3..b8bbe88e770f 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1122,6 +1122,20 @@ spi15: spi@89c000 {
#size-cells = <0>;
status = "disabled";
};
+
+ uart15: serial@89c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x89c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart15_default>;
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
};
i2c_master_hub_0: geniqup@9c0000 {
@@ -3856,6 +3870,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state {
bias-pull-down;
};
+ qup_uart15_default: qup-uart15-default-state {
+ /* TX, RX */
+ pins = "gpio74", "gpio75";
+ function = "qup2_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
sdc2_sleep: sdc2-sleep-state {
clk-pins {
pins = "sdc2_clk";
--
2.44.0
^ permalink raw reply related [relevance 16%]
* [PATCH 07/10] arm64: dts: qcom: sm8550: Update EAS properties
2024-04-24 15:29 6% ` Xilin Wu
@ 2024-04-24 15:29 12% ` Xilin Wu
-1 siblings, 0 replies; 200+ results
From: Xilin Wu via B4 Relay @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm, Xilin Wu
From: Xilin Wu <wuxilin123@gmail.com>
The original values provided by Qualcomm appear to be quite
inaccurate. Specifically, some heavy gaming tasks could be
improperly assigned to the A510 cores by the scheduler, resulting
in a CPU bottleneck. This update to the EAS properties aims to
enhance the user experience across various scenarios.
The power numbers were obtained using a Type-C power meter, which
was directly connected to the battery connector on the AYN Odin 2
motherboard, acting as a fake battery.
It should be noted that the A715 cores seem less efficient than the
A710 cores. Therefore, an average value has been assigned to them,
considering that the A715 and A710 cores share a single cpufreq
domain.
Cortex-A510 cores:
441 kHz, 564 mV, 43 mW, 350 Cx
556 kHz, 580 mV, 59 mW, 346 Cx
672 kHz, 592 mV, 71 mW, 312 Cx
787 kHz, 604 mV, 83 mW, 290 Cx
902 kHz, 608 mV, 96 mW, 288 Cx
1017 kHz, 624 mV, 107 mW, 264 Cx
1113 kHz, 636 mV, 117 mW, 252 Cx
1228 kHz, 652 mV, 130 mW, 240 Cx
1344 kHz, 668 mV, 146 mW, 235 Cx
1459 kHz, 688 mV, 155 mW, 214 Cx
1555 kHz, 704 mV, 166 mW, 205 Cx
1670 kHz, 724 mV, 178 mW, 192 Cx
1785 kHz, 744 mV, 197 mW, 189 Cx
1900 kHz, 764 mV, 221 mW, 190 Cx
2016 kHz, 784 mV, 243 mW, 188 Cx
Your dynamic-power-coefficient for cpu 1: 251
Cortex-A715 cores:
614 kHz, 572 mV, 97 mW, 470 Cx
729 kHz, 592 mV, 123 mW, 473 Cx
844 kHz, 608 mV, 152 mW, 486 Cx
940 kHz, 624 mV, 178 mW, 485 Cx
1056 kHz, 644 mV, 207 mW, 465 Cx
1171 kHz, 656 mV, 243 mW, 480 Cx
1286 kHz, 672 mV, 271 mW, 459 Cx
1401 kHz, 692 mV, 310 mW, 454 Cx
1536 kHz, 716 mV, 368 mW, 462 Cx
1651 kHz, 740 mV, 416 mW, 454 Cx
1785 kHz, 760 mV, 492 mW, 475 Cx
1920 kHz, 784 mV, 544 mW, 457 Cx
2054 kHz, 804 mV, 613 mW, 458 Cx
2188 kHz, 828 mV, 702 mW, 465 Cx
2323 kHz, 852 mV, 782 mW, 461 Cx
2457 kHz, 876 mV, 895 mW, 473 Cx
2592 kHz, 896 mV, 1020 mW, 490 Cx
2707 kHz, 920 mV, 1140 mW, 498 Cx
2803 kHz, 940 mV, 1215 mW, 490 Cx
Your dynamic-power-coefficient for cpu 3: 472
Cortex-A710 cores:
614 kHz, 572 mV, 91 mW, 388 Cx
729 kHz, 592 mV, 116 mW, 424 Cx
844 kHz, 608 mV, 143 mW, 443 Cx
940 kHz, 624 mV, 165 mW, 434 Cx
1056 kHz, 644 mV, 195 mW, 430 Cx
1171 kHz, 656 mV, 218 mW, 414 Cx
1286 kHz, 672 mV, 250 mW, 415 Cx
1401 kHz, 692 mV, 286 mW, 412 Cx
1536 kHz, 716 mV, 331 mW, 407 Cx
1651 kHz, 740 mV, 374 mW, 401 Cx
1785 kHz, 760 mV, 439 mW, 417 Cx
1920 kHz, 784 mV, 495 mW, 411 Cx
2054 kHz, 804 mV, 557 mW, 412 Cx
2188 kHz, 828 mV, 632 mW, 415 Cx
2323 kHz, 852 mV, 721 mW, 422 Cx
2457 kHz, 876 mV, 813 mW, 427 Cx
2592 kHz, 896 mV, 912 mW, 435 Cx
2707 kHz, 920 mV, 1019 mW, 442 Cx
2803 kHz, 940 mV, 1087 mW, 436 Cx
Your dynamic-power-coefficient for cpu 5: 421
Cortex-X3 core:
729 kHz, 568 mV, 252 mW, 1110 Cx
864 kHz, 580 mV, 312 mW, 1097 Cx
998 kHz, 592 mV, 379 mW, 1109 Cx
1132 kHz, 608 mV, 453 mW, 1099 Cx
1248 kHz, 624 mV, 517 mW, 1067 Cx
1363 kHz, 636 mV, 587 mW, 1067 Cx
1478 kHz, 648 mV, 657 mW, 1058 Cx
1593 kHz, 664 mV, 739 mW, 1049 Cx
1708 kHz, 680 mV, 813 mW, 1020 Cx
1843 kHz, 704 mV, 940 mW, 1021 Cx
1977 kHz, 724 mV, 1054 mW, 1007 Cx
2092 kHz, 740 mV, 1201 mW, 1045 Cx
2227 kHz, 768 mV, 1358 mW, 1029 Cx
2342 kHz, 788 mV, 1486 mW, 1016 Cx
2476 kHz, 812 mV, 1711 mW, 1046 Cx
2592 kHz, 836 mV, 1846 mW, 1014 Cx
2726 kHz, 856 mV, 2046 mW, 1020 Cx
2841 kHz, 880 mV, 2266 mW, 1027 Cx
2956 kHz, 908 mV, 2616 mW, 1074 Cx
3187 kHz, 956 mV, 3326 mW, 1147 Cx
Your dynamic-power-coefficient for cpu 7: 1057
7-zip benchmark single-core MIPS:
2128 4416 4632 6686
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index b8bbe88e770f..a84dd7f6ebc1 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -79,8 +79,8 @@ CPU0: cpu@0 {
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <326>;
+ dynamic-power-coefficient = <251>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
@@ -105,8 +105,8 @@ CPU1: cpu@100 {
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <326>;
+ dynamic-power-coefficient = <251>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
@@ -126,8 +126,8 @@ CPU2: cpu@200 {
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <326>;
+ dynamic-power-coefficient = <251>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
@@ -147,8 +147,8 @@ CPU3: cpu@300 {
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
@@ -168,8 +168,8 @@ CPU4: cpu@400 {
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
@@ -189,8 +189,8 @@ CPU5: cpu@500 {
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
@@ -210,8 +210,8 @@ CPU6: cpu@600 {
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
@@ -231,8 +231,8 @@ CPU7: cpu@700 {
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
- capacity-dmips-mhz = <1894>;
- dynamic-power-coefficient = <588>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <1057>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
--
2.44.0
^ permalink raw reply related [relevance 12%]
* [PATCH 10/10] arm64: dts: qcom: Add AYN Odin 2
2024-04-24 15:29 6% ` Xilin Wu
@ 2024-04-24 15:29 8% ` Xilin Wu
-1 siblings, 0 replies; 200+ results
From: Xilin Wu via B4 Relay @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm, Xilin Wu
From: Xilin Wu <wuxilin123@gmail.com>
AYN Odin 2 is a gaming handheld based on QCS8550, which is derived
from SM8550 but without modem RF system.
This commit brings support for:
* Remoteprocs
* UFS storage
* SD Card
* Type-C with USB3 10Gbps and DisplayPort (4-lane requires a pending
patch)
* PCIe0 (Wi-Fi requires the pending pwrseq series)
* Bluetooth
* Regulators
* Integrated fan with automatic speed control based on CPU temperature
* Power and volume keys
* M1, M2 buttons
* HDMI output up to 1080p 60hz
* four groups of RGB lights
* GPU
* Internal DSI display with touchscreen
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts | 1410 ++++++++++++++++++++++++
2 files changed, 1411 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index c46c10d85697..070c0d996059 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -97,6 +97,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayn-odin2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts
new file mode 100644
index 000000000000..bfe353d3c53e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts
@@ -0,0 +1,1410 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Xilin Wu <wuxilin123@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qcs8550.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/*
+ * The SoC being used on this product doesn't feature modem
+ * and camera subsystem.
+ * Variant: 202-AB
+ * FEATURE_ID: 0x8
+ */
+
+/delete-node/ &mpss_mem;
+/delete-node/ &q6_mpss_dtb_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &ipa_gsi_mem;
+/delete-node/ &camera_mem;
+/delete-node/ &mpss_dsm_mem;
+/delete-node/ &camcc;
+/delete-node/ &remoteproc_mpss;
+
+/ {
+ model = "AYN Odin 2";
+ compatible = "ayn,odin2", "qcom,qcs8550", "qcom,sm8550";
+ chassis-type = "handset";
+
+ qcom,msm-id = <QCOM_ID_QCS8550 0x20000>;
+ qcom,board-id = <0x1001f 0>;
+
+ aliases {
+ serial0 = &uart7;
+ serial1 = &uart14;
+ serial2 = &uart15;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pmk8550_pwm 0 860000>;
+ brightness-levels = <1023 0>;
+ num-interpolated-steps = <1023>;
+ default-brightness-level = <600>;
+ power-supply = <&vph_pwr>;
+ enable-gpios = <&pmk8550_gpios 5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_backlight_default>;
+ status = "okay";
+ };
+
+ fan_pwr: fan-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "fan_pwr";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&tlmm 109 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&fan_pwr_en>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>, <&m1_m2_keys_default>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+
+ m1-button {
+ label = "M1";
+ linux,code = <BTN_TRIGGER_HAPPY1>;
+ gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+ };
+
+ m2-button {
+ label = "M2";
+ linux,code = <BTN_TRIGGER_HAPPY2>;
+ gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "d";
+ hpd-gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>;
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<8912_out>;
+ };
+ };
+ };
+
+ hdmi_pwr: hdmi-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi_pwr";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_lcm_2p8: vdd-lcm-2p8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_lcm_2p8";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&tlmm 142 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ led_left_side: led-controller-1 {
+ compatible = "pwm-leds-multicolor";
+
+ multi-led {
+ label = "left-side";
+ color = <LED_COLOR_ID_RGB>;
+ max-brightness = <255>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm_rgb_left 0>;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm_rgb_left 1>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm_rgb_left 2>;
+ };
+ };
+ };
+
+ led_left_joystick: led-controller-2 {
+ compatible = "pwm-leds-multicolor";
+
+ multi-led {
+ label = "left-joystick";
+ color = <LED_COLOR_ID_RGB>;
+ max-brightness = <255>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm_rgb_left 6>;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm_rgb_left 7>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm_rgb_left 8>;
+ };
+ };
+ };
+
+ led_right_side: led-controller-3 {
+ compatible = "pwm-leds-multicolor";
+
+ multi-led {
+ label = "right-side";
+ color = <LED_COLOR_ID_RGB>;
+ max-brightness = <255>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm_rgb_right 0>;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm_rgb_right 1>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm_rgb_right 2>;
+ };
+ };
+ };
+
+ led_right_joystick: led-controller-4 {
+ compatible = "pwm-leds-multicolor";
+
+ multi-led {
+ label = "right-joystick";
+ color = <LED_COLOR_ID_RGB>;
+ max-brightness = <255>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm_rgb_right 6>;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm_rgb_right 7>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm_rgb_right 8>;
+ };
+ };
+ };
+
+ mcu_3v3: mcu-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "mcu_3v3";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&usb0_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 40 65 75 90 100 120 150>;
+ #cooling-cells = <2>;
+ fan-supply = <&fan_pwr>;
+ pwms = <&pm8550_pwm 3 100000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_out_default &fan_int>;
+
+ pulses-per-revolution = <4>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ thermal-zones {
+ cpuss0-thermal {
+ trips {
+ cpuss0_active0: trip-point2 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active1: trip-point3 {
+ temperature = <55000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active2: trip-point4 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active3: trip-point5 {
+ temperature = <65000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active4: trip-point6 {
+ temperature = <70000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active5: trip-point7 {
+ temperature = <75000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active6: trip-point8 {
+ temperature = <80000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpuss0_active0>;
+ cooling-device = <&fan 0 1>;
+ };
+ map1 {
+ trip = <&cpuss0_active1>;
+ cooling-device = <&fan 1 2>;
+ };
+ map2 {
+ trip = <&cpuss0_active2>;
+ cooling-device = <&fan 2 3>;
+ };
+ map3 {
+ trip = <&cpuss0_active3>;
+ cooling-device = <&fan 3 4>;
+ };
+ map4 {
+ trip = <&cpuss0_active4>;
+ cooling-device = <&fan 4 5>;
+ };
+ map5 {
+ trip = <&cpuss0_active5>;
+ cooling-device = <&fan 5 6>;
+ };
+ map6 {
+ trip = <&cpuss0_active6>;
+ cooling-device = <&fan 6 7>;
+ };
+ };
+ };
+ };
+
+ usb0-sbu-mux {
+ compatible = "pericom,pi3usb102", "gpio-sbu-mux";
+
+ enable-gpios = <&tlmm 140 GPIO_ACTIVE_LOW>;
+ select-gpios = <&tlmm 141 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_sbu_default>;
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ usb0_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s4g_1p25>;
+ vdd-l12-supply = <&vreg_s6g_1p86>;
+ vdd-l15-supply = <&vreg_s6g_1p86>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* Setting regulator-allow-set-load here will crash the device */
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l1c_1p2: ldo1 {
+ regulator-name = "vreg_l1c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* ldo2 supplies SM8550 VDD_LPI_MX */
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_s4e_0p95: smps4 {
+ regulator-name = "vreg_s4e_0p95";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p08: smps5 {
+ regulator-name = "vreg_s5e_1p08";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p88: ldo3 {
+ regulator-name = "vreg_l3f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_s1g_1p25: smps1 {
+ regulator-name = "vreg_s1g_1p25";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p85: smps2 {
+ regulator-name = "vreg_s2g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1036000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p8: smps3 {
+ regulator-name = "vreg_s3g_0p8";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p25: smps4 {
+ regulator-name = "vreg_s4g_1p25";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+
+ vreg_s5g_0p85: smps5 {
+ regulator-name = "vreg_s5g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p86: smps6 {
+ regulator-name = "vreg_s6g_1p86";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1144000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2g_1p1: ldo2 {
+ regulator-name = "vreg_l2g_1p1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/sm8550/ayn/odin2/a740_zap.mbn";
+ };
+};
+
+&hub_i2c0_data_clk {
+ /delete-property/ bias-pull-up;
+ bias-disable;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pwm_rgb_left: pwm@54 {
+ compatible = "si-en,sn3112-pwm";
+ reg = <0x54>;
+ sdb-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&mcu_3v3>;
+ #pwm-cells = <1>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&tlmm 25 0x2008>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&ts_int_default>;
+ pinctrl-1 = <&ts_int_sleep>;
+
+ vio-supply = <&vreg_l12b_1p8>;
+
+ syna,startup-delay-ms = <200>;
+ syna,reset-delay-ms = <200>;
+
+ rmi4-f01@1 {
+ syna,nosleep-mode = <0x1>;
+ reg = <0x1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,rezero-wait-ms = <20>;
+ syna,clip-x-low = <0>;
+ syna,clip-y-low = <0>;
+ syna,clip-x-high = <1080>;
+ syna,clip-y-high = <1920>;
+ syna,sensor-type = <1>;
+ touchscreen-inverted-x;
+ };
+ };
+};
+
+&i2c12 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pwm_rgb_right: pwm@54 {
+ compatible = "si-en,sn3112-pwm";
+ reg = <0x54>;
+ sdb-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&mcu_3v3>;
+ #pwm-cells = <1>;
+ };
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&i2c_hub_0 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ hdmi-bridge@48 {
+ compatible = "lontium,lt8912b";
+ reg = <0x48> ;
+ reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>;
+
+ vdd-supply = <&hdmi_pwr>;
+ vccmipirx-supply = <&hdmi_pwr>;
+ vccsysclk-supply = <&hdmi_pwr>;
+ vcclvdstx-supply = <&hdmi_pwr>;
+ vcchdmitx-supply = <&hdmi_pwr>;
+ vcclvdspll-supply = <&hdmi_pwr>;
+ vcchdmipll-supply = <&hdmi_pwr>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_out_in: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lt8912_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&i2c_hub_2 {
+ status = "okay";
+
+ /* Awinic AW88166 audio amplifier @ 34, 35 */
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&hdmi_out_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
+&mdss_dsi1 {
+ vdda-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+
+ panel: panel@0 {
+ compatible = "syna,td4328";
+ reg = <0>;
+
+ pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>;
+ pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>;
+ pinctrl-names = "default", "sleep";
+
+ vdd-supply = <&vdd_lcm_2p8>;
+ vddio-supply = <&vreg_l12b_1p8>;
+
+ backlight = <&backlight>;
+ /* touchscreen and display panel share the same reset gpio! */
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi1_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi1_out {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi1_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ max-link-speed = <2>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pm8550_gpios {
+ pwm_out_default: pwm-out-default-state {
+ pins = "gpio8";
+ function = "func1";
+ input-disable;
+ output-enable;
+ output-low;
+ bias-disable;
+ power-source = <1>;
+ };
+
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio12";
+ function = "normal";
+ input-enable;
+ output-disable;
+ bias-pull-up;
+ power-source = <1>; /* 1.8 V */
+ };
+
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm8550_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_CHARGING;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ qcom,tune-usb2-disc-thres = /bits/ 8 <0x6>;
+ qcom,tune-usb2-amplitude = /bits/ 8 <0xb>;
+ qcom,tune-usb2-preem = /bits/ 8 <0x3>;
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_gpios {
+ pwm_backlight_default: pwm-backlight-default-state {
+ pins = "gpio5";
+ function = "func3";
+ input-disable;
+ output-enable;
+ output-low;
+ bias-disable;
+ power-source = <0>;
+ qcom,drive-strength = <2>;
+ };
+};
+
+&pmk8550_pwm {
+ status = "okay";
+};
+
+&pmk8550_rtc {
+ nvmem-cells = <&rtc_offset>;
+ nvmem-cell-names = "offset";
+
+ status = "okay";
+};
+
+&pmk8550_sdam_2 {
+ status = "okay";
+
+ rtc_offset: rtc-offset@bc {
+ reg = <0xbc 0x4>;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/ayn/odin2/adsp.mbn",
+ "qcom/sm8550/ayn/odin2/adsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8550/ayn/odin2/cdsp.mbn",
+ "qcom/sm8550/ayn/odin2/cdsp_dtb.mbn";
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+
+ /* SDR104 does seem to be working on this device*/
+ /delete-property/ sdhci-caps-mask;
+ qcom,dll-config = <0x0007442c>;
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 8>;
+
+ fan_int: fan-int-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ fan_pwr_en: fan-pwr-en-state {
+ pins = "gpio109";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
+ m1_m2_keys_default: m1-m2-keys-default-state {
+ pins = "gpio57", "gpio58";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ ts_int_default: ts-int-default-state {
+ pins = "gpio25";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ ts_int_sleep: ts-int-sleep-state {
+ pins = "gpio25";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ bt_default: bt-default-state {
+ bt-en-pins {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sw-ctrl-pins {
+ pins = "gpio82";
+ function = "gpio";
+ bias-pull-down;
+ };
+ };
+
+ usb0_sbu_default: usb0-sbu-state {
+ oe-n-pins {
+ pins = "gpio140";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <16>;
+ output-high;
+ };
+
+ sel-pins {
+ pins = "gpio141";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ };
+
+ sde_dsi_active: sde-dsi-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ sde_dsi_suspend: sde-dsi-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ sde_te_active: sde-te-active-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ sde_te_suspend: sde-te-suspend-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_s4e_0p95>;
+ vdddig-supply = <&vreg_s4e_0p95>;
+ vddrfa0p8-supply = <&vreg_s4e_0p95>;
+ vddrfa1p2-supply = <&vreg_s4g_1p25>;
+ vddrfa1p9-supply = <&vreg_s6g_1p86>;
+
+ max-speed = <3200000>;
+
+ enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&bt_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&uart15 {
+ status = "okay";
+
+ /* Gamepad controlled by onboard MCU */
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+ maximum-speed = "super-speed-plus-gen2x1";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ phys = <&pm8550b_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p88>;
+
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_dp_in {
+ remote-endpoint = <&mdss_dp0_out>;
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&usb_dp_qmpphy_usb_ss_in {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
--
2.44.0
^ permalink raw reply related [relevance 8%]
* [PATCH 00/10] AYN Odin 2 support
@ 2024-04-24 15:29 6% ` Xilin Wu
0 siblings, 0 replies; 200+ results
From: Xilin Wu via B4 Relay @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm, Xilin Wu
AYN Odin 2 is a gaming handheld based on QCS8550, which is derived
from SM8550 but without modem RF system.
This series bring support for:
* Remoteprocs
* UFS storage
* SD Card
* Type-C with USB3 10Gbps and DisplayPort (4-lane requires a pending
patch)
* PCIe0 (Wi-Fi requires the pending pwrseq series)
* Bluetooth
* Regulators
* Integrated fan with automatic speed control based on CPU temperature
* Power and volume keys
* M1, M2 buttons
* HDMI output up to 1080p 60hz
* four groups of RGB lights
* GPU
* Internal DSI display with touchscreen
Depends: [1]
[1] https://lore.kernel.org/all/20240424024508.3857602-1-quic_tengfan@quicinc.com/
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
Junhao Xie (2):
dt-bindings: pwm: Add SI-EN SN3112 PWM support
pwm: Add SI-EN SN3112 PWM support
Xilin Wu (8):
dt-bindings: display: panel: Add Synaptics TD4328
drm/panel: Add driver for Synaptics TD4328 LCD panel
arm64: dts: qcom: pmk8550: Add PWM controller
arm64: dts: qcom: sm8550: Add UART15
arm64: dts: qcom: sm8550: Update EAS properties
dt-bindings: vendor-prefixes: Add AYN Technologies
dt-bindings: arm: qcom: Add AYN Odin 2
arm64: dts: qcom: Add AYN Odin 2
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
.../bindings/display/panel/synaptics,td4328.yaml | 69 +
.../devicetree/bindings/pwm/si-en,sn3112-pwm.yaml | 55 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/pmk8550.dtsi | 10 +
arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts | 1410 ++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 54 +-
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-synaptics-td4328.c | 246 ++++
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sn3112.c | 336 +++++
14 files changed, 2190 insertions(+), 16 deletions(-)
---
base-commit: 90388b2f9fa5f332289335f99996e252697c0242
change-id: 20240424-ayn-odin2-initial-95b7c060cd03
Best regards,
--
Xilin Wu <wuxilin123@gmail.com>
^ permalink raw reply [relevance 6%]
* [PATCH 10/10] arm64: dts: qcom: Add AYN Odin 2
@ 2024-04-24 15:29 8% ` Xilin Wu
0 siblings, 0 replies; 200+ results
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm, Xilin Wu
AYN Odin 2 is a gaming handheld based on QCS8550, which is derived
from SM8550 but without modem RF system.
This commit brings support for:
* Remoteprocs
* UFS storage
* SD Card
* Type-C with USB3 10Gbps and DisplayPort (4-lane requires a pending
patch)
* PCIe0 (Wi-Fi requires the pending pwrseq series)
* Bluetooth
* Regulators
* Integrated fan with automatic speed control based on CPU temperature
* Power and volume keys
* M1, M2 buttons
* HDMI output up to 1080p 60hz
* four groups of RGB lights
* GPU
* Internal DSI display with touchscreen
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts | 1410 ++++++++++++++++++++++++
2 files changed, 1411 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index c46c10d85697..070c0d996059 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -97,6 +97,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayn-odin2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts
new file mode 100644
index 000000000000..bfe353d3c53e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts
@@ -0,0 +1,1410 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Xilin Wu <wuxilin123@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qcs8550.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/*
+ * The SoC being used on this product doesn't feature modem
+ * and camera subsystem.
+ * Variant: 202-AB
+ * FEATURE_ID: 0x8
+ */
+
+/delete-node/ &mpss_mem;
+/delete-node/ &q6_mpss_dtb_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &ipa_gsi_mem;
+/delete-node/ &camera_mem;
+/delete-node/ &mpss_dsm_mem;
+/delete-node/ &camcc;
+/delete-node/ &remoteproc_mpss;
+
+/ {
+ model = "AYN Odin 2";
+ compatible = "ayn,odin2", "qcom,qcs8550", "qcom,sm8550";
+ chassis-type = "handset";
+
+ qcom,msm-id = <QCOM_ID_QCS8550 0x20000>;
+ qcom,board-id = <0x1001f 0>;
+
+ aliases {
+ serial0 = &uart7;
+ serial1 = &uart14;
+ serial2 = &uart15;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pmk8550_pwm 0 860000>;
+ brightness-levels = <1023 0>;
+ num-interpolated-steps = <1023>;
+ default-brightness-level = <600>;
+ power-supply = <&vph_pwr>;
+ enable-gpios = <&pmk8550_gpios 5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_backlight_default>;
+ status = "okay";
+ };
+
+ fan_pwr: fan-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "fan_pwr";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&tlmm 109 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&fan_pwr_en>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>, <&m1_m2_keys_default>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+
+ m1-button {
+ label = "M1";
+ linux,code = <BTN_TRIGGER_HAPPY1>;
+ gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+ };
+
+ m2-button {
+ label = "M2";
+ linux,code = <BTN_TRIGGER_HAPPY2>;
+ gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "d";
+ hpd-gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>;
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<8912_out>;
+ };
+ };
+ };
+
+ hdmi_pwr: hdmi-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi_pwr";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_lcm_2p8: vdd-lcm-2p8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_lcm_2p8";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&tlmm 142 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ led_left_side: led-controller-1 {
+ compatible = "pwm-leds-multicolor";
+
+ multi-led {
+ label = "left-side";
+ color = <LED_COLOR_ID_RGB>;
+ max-brightness = <255>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm_rgb_left 0>;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm_rgb_left 1>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm_rgb_left 2>;
+ };
+ };
+ };
+
+ led_left_joystick: led-controller-2 {
+ compatible = "pwm-leds-multicolor";
+
+ multi-led {
+ label = "left-joystick";
+ color = <LED_COLOR_ID_RGB>;
+ max-brightness = <255>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm_rgb_left 6>;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm_rgb_left 7>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm_rgb_left 8>;
+ };
+ };
+ };
+
+ led_right_side: led-controller-3 {
+ compatible = "pwm-leds-multicolor";
+
+ multi-led {
+ label = "right-side";
+ color = <LED_COLOR_ID_RGB>;
+ max-brightness = <255>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm_rgb_right 0>;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm_rgb_right 1>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm_rgb_right 2>;
+ };
+ };
+ };
+
+ led_right_joystick: led-controller-4 {
+ compatible = "pwm-leds-multicolor";
+
+ multi-led {
+ label = "right-joystick";
+ color = <LED_COLOR_ID_RGB>;
+ max-brightness = <255>;
+
+ led-red {
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm_rgb_right 6>;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm_rgb_right 7>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm_rgb_right 8>;
+ };
+ };
+ };
+
+ mcu_3v3: mcu-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "mcu_3v3";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&usb0_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 40 65 75 90 100 120 150>;
+ #cooling-cells = <2>;
+ fan-supply = <&fan_pwr>;
+ pwms = <&pm8550_pwm 3 100000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_out_default &fan_int>;
+
+ pulses-per-revolution = <4>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ thermal-zones {
+ cpuss0-thermal {
+ trips {
+ cpuss0_active0: trip-point2 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active1: trip-point3 {
+ temperature = <55000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active2: trip-point4 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active3: trip-point5 {
+ temperature = <65000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active4: trip-point6 {
+ temperature = <70000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active5: trip-point7 {
+ temperature = <75000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active6: trip-point8 {
+ temperature = <80000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpuss0_active0>;
+ cooling-device = <&fan 0 1>;
+ };
+ map1 {
+ trip = <&cpuss0_active1>;
+ cooling-device = <&fan 1 2>;
+ };
+ map2 {
+ trip = <&cpuss0_active2>;
+ cooling-device = <&fan 2 3>;
+ };
+ map3 {
+ trip = <&cpuss0_active3>;
+ cooling-device = <&fan 3 4>;
+ };
+ map4 {
+ trip = <&cpuss0_active4>;
+ cooling-device = <&fan 4 5>;
+ };
+ map5 {
+ trip = <&cpuss0_active5>;
+ cooling-device = <&fan 5 6>;
+ };
+ map6 {
+ trip = <&cpuss0_active6>;
+ cooling-device = <&fan 6 7>;
+ };
+ };
+ };
+ };
+
+ usb0-sbu-mux {
+ compatible = "pericom,pi3usb102", "gpio-sbu-mux";
+
+ enable-gpios = <&tlmm 140 GPIO_ACTIVE_LOW>;
+ select-gpios = <&tlmm 141 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_sbu_default>;
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ usb0_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s4g_1p25>;
+ vdd-l12-supply = <&vreg_s6g_1p86>;
+ vdd-l15-supply = <&vreg_s6g_1p86>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* Setting regulator-allow-set-load here will crash the device */
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l1c_1p2: ldo1 {
+ regulator-name = "vreg_l1c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* ldo2 supplies SM8550 VDD_LPI_MX */
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_s4e_0p95: smps4 {
+ regulator-name = "vreg_s4e_0p95";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p08: smps5 {
+ regulator-name = "vreg_s5e_1p08";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p88: ldo3 {
+ regulator-name = "vreg_l3f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_s1g_1p25: smps1 {
+ regulator-name = "vreg_s1g_1p25";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p85: smps2 {
+ regulator-name = "vreg_s2g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1036000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p8: smps3 {
+ regulator-name = "vreg_s3g_0p8";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p25: smps4 {
+ regulator-name = "vreg_s4g_1p25";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+
+ vreg_s5g_0p85: smps5 {
+ regulator-name = "vreg_s5g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p86: smps6 {
+ regulator-name = "vreg_s6g_1p86";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1144000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2g_1p1: ldo2 {
+ regulator-name = "vreg_l2g_1p1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/sm8550/ayn/odin2/a740_zap.mbn";
+ };
+};
+
+&hub_i2c0_data_clk {
+ /delete-property/ bias-pull-up;
+ bias-disable;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pwm_rgb_left: pwm@54 {
+ compatible = "si-en,sn3112-pwm";
+ reg = <0x54>;
+ sdb-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&mcu_3v3>;
+ #pwm-cells = <1>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&tlmm 25 0x2008>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&ts_int_default>;
+ pinctrl-1 = <&ts_int_sleep>;
+
+ vio-supply = <&vreg_l12b_1p8>;
+
+ syna,startup-delay-ms = <200>;
+ syna,reset-delay-ms = <200>;
+
+ rmi4-f01@1 {
+ syna,nosleep-mode = <0x1>;
+ reg = <0x1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,rezero-wait-ms = <20>;
+ syna,clip-x-low = <0>;
+ syna,clip-y-low = <0>;
+ syna,clip-x-high = <1080>;
+ syna,clip-y-high = <1920>;
+ syna,sensor-type = <1>;
+ touchscreen-inverted-x;
+ };
+ };
+};
+
+&i2c12 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pwm_rgb_right: pwm@54 {
+ compatible = "si-en,sn3112-pwm";
+ reg = <0x54>;
+ sdb-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&mcu_3v3>;
+ #pwm-cells = <1>;
+ };
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&i2c_hub_0 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ hdmi-bridge@48 {
+ compatible = "lontium,lt8912b";
+ reg = <0x48> ;
+ reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>;
+
+ vdd-supply = <&hdmi_pwr>;
+ vccmipirx-supply = <&hdmi_pwr>;
+ vccsysclk-supply = <&hdmi_pwr>;
+ vcclvdstx-supply = <&hdmi_pwr>;
+ vcchdmitx-supply = <&hdmi_pwr>;
+ vcclvdspll-supply = <&hdmi_pwr>;
+ vcchdmipll-supply = <&hdmi_pwr>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_out_in: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lt8912_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&i2c_hub_2 {
+ status = "okay";
+
+ /* Awinic AW88166 audio amplifier @ 34, 35 */
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&hdmi_out_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
+&mdss_dsi1 {
+ vdda-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+
+ panel: panel@0 {
+ compatible = "syna,td4328";
+ reg = <0>;
+
+ pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>;
+ pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>;
+ pinctrl-names = "default", "sleep";
+
+ vdd-supply = <&vdd_lcm_2p8>;
+ vddio-supply = <&vreg_l12b_1p8>;
+
+ backlight = <&backlight>;
+ /* touchscreen and display panel share the same reset gpio! */
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi1_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi1_out {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi1_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ max-link-speed = <2>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pm8550_gpios {
+ pwm_out_default: pwm-out-default-state {
+ pins = "gpio8";
+ function = "func1";
+ input-disable;
+ output-enable;
+ output-low;
+ bias-disable;
+ power-source = <1>;
+ };
+
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio12";
+ function = "normal";
+ input-enable;
+ output-disable;
+ bias-pull-up;
+ power-source = <1>; /* 1.8 V */
+ };
+
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm8550_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_CHARGING;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ qcom,tune-usb2-disc-thres = /bits/ 8 <0x6>;
+ qcom,tune-usb2-amplitude = /bits/ 8 <0xb>;
+ qcom,tune-usb2-preem = /bits/ 8 <0x3>;
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_gpios {
+ pwm_backlight_default: pwm-backlight-default-state {
+ pins = "gpio5";
+ function = "func3";
+ input-disable;
+ output-enable;
+ output-low;
+ bias-disable;
+ power-source = <0>;
+ qcom,drive-strength = <2>;
+ };
+};
+
+&pmk8550_pwm {
+ status = "okay";
+};
+
+&pmk8550_rtc {
+ nvmem-cells = <&rtc_offset>;
+ nvmem-cell-names = "offset";
+
+ status = "okay";
+};
+
+&pmk8550_sdam_2 {
+ status = "okay";
+
+ rtc_offset: rtc-offset@bc {
+ reg = <0xbc 0x4>;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/ayn/odin2/adsp.mbn",
+ "qcom/sm8550/ayn/odin2/adsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8550/ayn/odin2/cdsp.mbn",
+ "qcom/sm8550/ayn/odin2/cdsp_dtb.mbn";
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+
+ /* SDR104 does seem to be working on this device*/
+ /delete-property/ sdhci-caps-mask;
+ qcom,dll-config = <0x0007442c>;
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 8>;
+
+ fan_int: fan-int-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ fan_pwr_en: fan-pwr-en-state {
+ pins = "gpio109";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
+ m1_m2_keys_default: m1-m2-keys-default-state {
+ pins = "gpio57", "gpio58";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ ts_int_default: ts-int-default-state {
+ pins = "gpio25";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ ts_int_sleep: ts-int-sleep-state {
+ pins = "gpio25";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ bt_default: bt-default-state {
+ bt-en-pins {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sw-ctrl-pins {
+ pins = "gpio82";
+ function = "gpio";
+ bias-pull-down;
+ };
+ };
+
+ usb0_sbu_default: usb0-sbu-state {
+ oe-n-pins {
+ pins = "gpio140";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <16>;
+ output-high;
+ };
+
+ sel-pins {
+ pins = "gpio141";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ };
+
+ sde_dsi_active: sde-dsi-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ sde_dsi_suspend: sde-dsi-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ sde_te_active: sde-te-active-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ sde_te_suspend: sde-te-suspend-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_s4e_0p95>;
+ vdddig-supply = <&vreg_s4e_0p95>;
+ vddrfa0p8-supply = <&vreg_s4e_0p95>;
+ vddrfa1p2-supply = <&vreg_s4g_1p25>;
+ vddrfa1p9-supply = <&vreg_s6g_1p86>;
+
+ max-speed = <3200000>;
+
+ enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&bt_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&uart15 {
+ status = "okay";
+
+ /* Gamepad controlled by onboard MCU */
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+ maximum-speed = "super-speed-plus-gen2x1";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ phys = <&pm8550b_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p88>;
+
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_dp_in {
+ remote-endpoint = <&mdss_dp0_out>;
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&usb_dp_qmpphy_usb_ss_in {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
--
2.44.0
^ permalink raw reply related [relevance 8%]
* [PATCH 07/10] arm64: dts: qcom: sm8550: Update EAS properties
@ 2024-04-24 15:29 12% ` Xilin Wu
0 siblings, 0 replies; 200+ results
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm, Xilin Wu
The original values provided by Qualcomm appear to be quite
inaccurate. Specifically, some heavy gaming tasks could be
improperly assigned to the A510 cores by the scheduler, resulting
in a CPU bottleneck. This update to the EAS properties aims to
enhance the user experience across various scenarios.
The power numbers were obtained using a Type-C power meter, which
was directly connected to the battery connector on the AYN Odin 2
motherboard, acting as a fake battery.
It should be noted that the A715 cores seem less efficient than the
A710 cores. Therefore, an average value has been assigned to them,
considering that the A715 and A710 cores share a single cpufreq
domain.
Cortex-A510 cores:
441 kHz, 564 mV, 43 mW, 350 Cx
556 kHz, 580 mV, 59 mW, 346 Cx
672 kHz, 592 mV, 71 mW, 312 Cx
787 kHz, 604 mV, 83 mW, 290 Cx
902 kHz, 608 mV, 96 mW, 288 Cx
1017 kHz, 624 mV, 107 mW, 264 Cx
1113 kHz, 636 mV, 117 mW, 252 Cx
1228 kHz, 652 mV, 130 mW, 240 Cx
1344 kHz, 668 mV, 146 mW, 235 Cx
1459 kHz, 688 mV, 155 mW, 214 Cx
1555 kHz, 704 mV, 166 mW, 205 Cx
1670 kHz, 724 mV, 178 mW, 192 Cx
1785 kHz, 744 mV, 197 mW, 189 Cx
1900 kHz, 764 mV, 221 mW, 190 Cx
2016 kHz, 784 mV, 243 mW, 188 Cx
Your dynamic-power-coefficient for cpu 1: 251
Cortex-A715 cores:
614 kHz, 572 mV, 97 mW, 470 Cx
729 kHz, 592 mV, 123 mW, 473 Cx
844 kHz, 608 mV, 152 mW, 486 Cx
940 kHz, 624 mV, 178 mW, 485 Cx
1056 kHz, 644 mV, 207 mW, 465 Cx
1171 kHz, 656 mV, 243 mW, 480 Cx
1286 kHz, 672 mV, 271 mW, 459 Cx
1401 kHz, 692 mV, 310 mW, 454 Cx
1536 kHz, 716 mV, 368 mW, 462 Cx
1651 kHz, 740 mV, 416 mW, 454 Cx
1785 kHz, 760 mV, 492 mW, 475 Cx
1920 kHz, 784 mV, 544 mW, 457 Cx
2054 kHz, 804 mV, 613 mW, 458 Cx
2188 kHz, 828 mV, 702 mW, 465 Cx
2323 kHz, 852 mV, 782 mW, 461 Cx
2457 kHz, 876 mV, 895 mW, 473 Cx
2592 kHz, 896 mV, 1020 mW, 490 Cx
2707 kHz, 920 mV, 1140 mW, 498 Cx
2803 kHz, 940 mV, 1215 mW, 490 Cx
Your dynamic-power-coefficient for cpu 3: 472
Cortex-A710 cores:
614 kHz, 572 mV, 91 mW, 388 Cx
729 kHz, 592 mV, 116 mW, 424 Cx
844 kHz, 608 mV, 143 mW, 443 Cx
940 kHz, 624 mV, 165 mW, 434 Cx
1056 kHz, 644 mV, 195 mW, 430 Cx
1171 kHz, 656 mV, 218 mW, 414 Cx
1286 kHz, 672 mV, 250 mW, 415 Cx
1401 kHz, 692 mV, 286 mW, 412 Cx
1536 kHz, 716 mV, 331 mW, 407 Cx
1651 kHz, 740 mV, 374 mW, 401 Cx
1785 kHz, 760 mV, 439 mW, 417 Cx
1920 kHz, 784 mV, 495 mW, 411 Cx
2054 kHz, 804 mV, 557 mW, 412 Cx
2188 kHz, 828 mV, 632 mW, 415 Cx
2323 kHz, 852 mV, 721 mW, 422 Cx
2457 kHz, 876 mV, 813 mW, 427 Cx
2592 kHz, 896 mV, 912 mW, 435 Cx
2707 kHz, 920 mV, 1019 mW, 442 Cx
2803 kHz, 940 mV, 1087 mW, 436 Cx
Your dynamic-power-coefficient for cpu 5: 421
Cortex-X3 core:
729 kHz, 568 mV, 252 mW, 1110 Cx
864 kHz, 580 mV, 312 mW, 1097 Cx
998 kHz, 592 mV, 379 mW, 1109 Cx
1132 kHz, 608 mV, 453 mW, 1099 Cx
1248 kHz, 624 mV, 517 mW, 1067 Cx
1363 kHz, 636 mV, 587 mW, 1067 Cx
1478 kHz, 648 mV, 657 mW, 1058 Cx
1593 kHz, 664 mV, 739 mW, 1049 Cx
1708 kHz, 680 mV, 813 mW, 1020 Cx
1843 kHz, 704 mV, 940 mW, 1021 Cx
1977 kHz, 724 mV, 1054 mW, 1007 Cx
2092 kHz, 740 mV, 1201 mW, 1045 Cx
2227 kHz, 768 mV, 1358 mW, 1029 Cx
2342 kHz, 788 mV, 1486 mW, 1016 Cx
2476 kHz, 812 mV, 1711 mW, 1046 Cx
2592 kHz, 836 mV, 1846 mW, 1014 Cx
2726 kHz, 856 mV, 2046 mW, 1020 Cx
2841 kHz, 880 mV, 2266 mW, 1027 Cx
2956 kHz, 908 mV, 2616 mW, 1074 Cx
3187 kHz, 956 mV, 3326 mW, 1147 Cx
Your dynamic-power-coefficient for cpu 7: 1057
7-zip benchmark single-core MIPS:
2128 4416 4632 6686
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index b8bbe88e770f..a84dd7f6ebc1 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -79,8 +79,8 @@ CPU0: cpu@0 {
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <326>;
+ dynamic-power-coefficient = <251>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
@@ -105,8 +105,8 @@ CPU1: cpu@100 {
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <326>;
+ dynamic-power-coefficient = <251>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
@@ -126,8 +126,8 @@ CPU2: cpu@200 {
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <326>;
+ dynamic-power-coefficient = <251>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
@@ -147,8 +147,8 @@ CPU3: cpu@300 {
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
@@ -168,8 +168,8 @@ CPU4: cpu@400 {
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
@@ -189,8 +189,8 @@ CPU5: cpu@500 {
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
@@ -210,8 +210,8 @@ CPU6: cpu@600 {
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
@@ -231,8 +231,8 @@ CPU7: cpu@700 {
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
- capacity-dmips-mhz = <1894>;
- dynamic-power-coefficient = <588>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <1057>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
--
2.44.0
^ permalink raw reply related [relevance 12%]
* [PATCH 06/10] arm64: dts: qcom: sm8550: Add UART15
@ 2024-04-24 15:29 16% ` Xilin Wu
0 siblings, 0 replies; 200+ results
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm, Xilin Wu
Add uart15 node for UART bus present on sm8550 SoC.
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index bc5aeb05ffc3..b8bbe88e770f 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1122,6 +1122,20 @@ spi15: spi@89c000 {
#size-cells = <0>;
status = "disabled";
};
+
+ uart15: serial@89c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x89c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart15_default>;
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
};
i2c_master_hub_0: geniqup@9c0000 {
@@ -3856,6 +3870,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state {
bias-pull-down;
};
+ qup_uart15_default: qup-uart15-default-state {
+ /* TX, RX */
+ pins = "gpio74", "gpio75";
+ function = "qup2_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
sdc2_sleep: sdc2-sleep-state {
clk-pins {
pins = "sdc2_clk";
--
2.44.0
^ permalink raw reply related [relevance 16%]
* [PATCH 00/10] AYN Odin 2 support
@ 2024-04-24 15:29 6% ` Xilin Wu
0 siblings, 0 replies; 200+ results
From: Xilin Wu @ 2024-04-24 15:29 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Junhao Xie, Neil Armstrong, Jessica Zhang,
Sam Ravnborg, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Bjorn Andersson, Konrad Dybcio,
Tengfei Fan, Molly Sophia, Junhao Xie
Cc: linux-pwm, devicetree, linux-kernel, dri-devel, linux-arm-msm, Xilin Wu
AYN Odin 2 is a gaming handheld based on QCS8550, which is derived
from SM8550 but without modem RF system.
This series bring support for:
* Remoteprocs
* UFS storage
* SD Card
* Type-C with USB3 10Gbps and DisplayPort (4-lane requires a pending
patch)
* PCIe0 (Wi-Fi requires the pending pwrseq series)
* Bluetooth
* Regulators
* Integrated fan with automatic speed control based on CPU temperature
* Power and volume keys
* M1, M2 buttons
* HDMI output up to 1080p 60hz
* four groups of RGB lights
* GPU
* Internal DSI display with touchscreen
Depends: [1]
[1] https://lore.kernel.org/all/20240424024508.3857602-1-quic_tengfan@quicinc.com/
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
---
Junhao Xie (2):
dt-bindings: pwm: Add SI-EN SN3112 PWM support
pwm: Add SI-EN SN3112 PWM support
Xilin Wu (8):
dt-bindings: display: panel: Add Synaptics TD4328
drm/panel: Add driver for Synaptics TD4328 LCD panel
arm64: dts: qcom: pmk8550: Add PWM controller
arm64: dts: qcom: sm8550: Add UART15
arm64: dts: qcom: sm8550: Update EAS properties
dt-bindings: vendor-prefixes: Add AYN Technologies
dt-bindings: arm: qcom: Add AYN Odin 2
arm64: dts: qcom: Add AYN Odin 2
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
.../bindings/display/panel/synaptics,td4328.yaml | 69 +
.../devicetree/bindings/pwm/si-en,sn3112-pwm.yaml | 55 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/pmk8550.dtsi | 10 +
arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts | 1410 ++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 54 +-
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-synaptics-td4328.c | 246 ++++
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sn3112.c | 336 +++++
14 files changed, 2190 insertions(+), 16 deletions(-)
---
base-commit: 90388b2f9fa5f332289335f99996e252697c0242
change-id: 20240424-ayn-odin2-initial-95b7c060cd03
Best regards,
--
Xilin Wu <wuxilin123@gmail.com>
^ permalink raw reply [relevance 6%]
* Re: [PATCH v7 0/4] arm64: qcom: add AIM300 AIoT board support
2024-04-24 2:45 6% [PATCH v7 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
` (2 preceding siblings ...)
2024-04-24 2:45 5% ` [PATCH v7 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT Tengfei Fan
@ 2024-04-24 13:14 0% ` Rob Herring
3 siblings, 0 replies; 200+ results
From: Rob Herring @ 2024-04-24 13:14 UTC (permalink / raw)
To: Tengfei Fan
Cc: konrad.dybcio, linux-kernel, gpiccoli, linux-hardening,
linux-arm-msm, conor+dt, kernel, krzk+dt, devicetree, tony.luck,
andersson, dmitry.baryshkov, keescook
On Wed, 24 Apr 2024 10:45:04 +0800, Tengfei Fan wrote:
> Add AIM300 AIoT support along with usb, ufs, regulators, serial, PCIe,
> and PMIC functions.
> AIM300 Series is a highly optimized family of modules designed to
> support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC
> chip etc.
> Here is a diagram of AIM300 AIoT Carrie Board and SoM
> +--------------------------------------------------+
> | AIM300 AIOT Carrier Board |
> | |
> | +-----------------+ |
> |power----->| Fixed regulator |---------+ |
> | +-----------------+ | |
> | | |
> | v VPH_PWR |
> | +----------------------------------------------+ |
> | | AIM300 SOM | | |
> | | |VPH_PWR | |
> | | v | |
> | | +-------+ +--------+ +------+ | |
> | | | UFS | | QCS8550| |PMIC | | |
> | | +-------+ +--------+ +------+ | |
> | | | |
> | +----------------------------------------------+ |
> | |
> | +----+ +------+ |
> | |USB | | UART | |
> | +----+ +------+ |
> +--------------------------------------------------+
> The following functions have been verified:
> - uart
> - usb
> - ufs
> - PCIe
> - PMIC
> - display
> - adsp
> - cdsp
> - tlmm
>
> Documentation for qcs8550[1] and sm8550[2]
> [1] https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
> [2] https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/Snapdragon-8-Gen-2-Product-Brief.pdf
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>
> v6 -> v7:
> - correct typos in the commit message
> - move mdss_dsi0, mdss_dsi0_phy, pcie0_phy, pcie1_phy and usb_dp_qmpphy
> vdda supply to qcs8550-aim300.dtsi
> - move the perst and wake gpio settings of pcie0 and pcie1 to
> qcs8550-aim300.dtsi
> - move the clock frequency settings of pcie_1_phy_aux_clk, sleep_clk
> and xo_board to qcs8550-aim300.dtsi
> - verified with dtb check, and result is expected, because those
> warnings are not introduced by current patch series.
> arch/arm64/boot/dts/qcom/sm8550.dtsi:3037.27-3092.6: Warning
> (avoid_unnecessary_addr_size): /soc@0/display-subsystem@ae00000/dsi@ae96000: unnecessary
> #address-cells/#size-cells without "ranges" or child "reg" property
> arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
> phy@1c0e000: clock-output-names: ['pcie1_pipe_clk'] is too short
> from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
> arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: phy@1c0e000: #clock-cells:0:0: 1 was expected
> from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
>
> v5 -> v6:
> - move qcs8550 board info bebind sm8550 boards info in qcom.yaml
>
> v4 -> v5:
> - "2023-2024" instead of "2023~2024" for License
> - update patch commit message to previous comments and with an updated
> board diagram
> - use qcs8550.dtsi instead of qcm8550.dtsi
> - remove the reserved memory regions which will be handled by
> bootloader
> - remove pm8550_flash, pm8550_pwm nodes, Type-C USB/DP function node,
> remoteproc_mpss function node, audio sound DTS node, new patch will
> be updated after respective team's end to end full verification
> - address comments to vph_pwr, move vph_pwr node and related
> references to qcs8550-aim300-aiot.dts
> - use "regulator-vph-pwr" instead of "vph_pwr_regulator"
> - add pcie0I AND pcie1 support together
> - the following patches were applied, so remove these patches from new
> patch series:
> - https://lore.kernel.org/linux-arm-msm/20240119100621.11788-3-quic_tengfan@quicinc.com
> - https://lore.kernel.org/linux-arm-msm/20240119100621.11788-4-quic_tengfan@quicinc.com
> - verified with dtb check, and result is expected, because those
> warnings are not introduced by current patch series.
> DTC_CHK arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb
> arch/arm64/boot/dts/qcom/sm8550.dtsi:3015.27-3070.6: Warning
> (avoid_unnecessary_addr_size): /soc@0/display-subsystem@ae00000/dsi@ae96000: unnecessary
> #address-cells/#size-cells without "ranges" or child "reg" property
> arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
> opp-table: opp-75000000:opp-hz:0: [75000000, 0, 0, 75000000, 0, 0, 0, 0] is too long
> from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
> arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
> opp-table: opp-150000000:opp-hz:0: [150000000, 0, 0, 150000000, 0, 0, 0, 0] is too long
> from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
> arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
> opp-table: opp-300000000:opp-hz:0: [300000000, 0, 0, 300000000, 0, 0, 0, 0] is too long
> from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
> arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
> opp-table: Unevaluated properties are not allowed ('opp-150000000', 'opp-300000000', 'opp-75000000' were unexpected)
> from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
>
> v3 -> v4:
> - use qcm8550.dtsi instead of qcs8550.dtsi, qcs8550 is a QCS version
> of qcm8550, another board with qcm8550 will be added later
> - add AIM300 AIoT board string in qcom.yaml file
> - add sm8550 and qcm8550 fallback compatible
> - add qcm8550 SoC id
> - add reserved memory map codes in qcm8550.dtsi
> - pm8010 and pmr73d are splited into carrier board DTS file. Because
> the regulators which in pm8550, pm8550ve and pm8550vs are present
> on the SoM. The regulators which in pm8010 and pmr73d are present
> on the carrier board.
> - stay VPH_PWR at qcs8550-aim300.dtsi file
> VPH_PWR is obtained by vonverting 12v voltage into 3.7 voltage
> with a 3.7v buck. VPH_PWR is power supply for regulators in AIM300
> SOM. VPH_PWR regulator is defined in AIM300 SOM dtsi file.
>
> v2 -> v3:
> - introduce qcs8550.dtsi
> - separate fix dtc W=1 warning patch to another patch series
>
> v1 -> v2:
> - merge the splited dts patches into one patch
> - update dts file name from qcom8550-aim300.dts to qcs8550-aim300 dts
> - drop PCIe1 dts node due to it is not enabled
> - update display node name for drop sde characters
>
> previous discussion here:
> [1] v6 RESEND: https://lore.kernel.org/linux-arm-msm/20240401093843.2591147-1-quic_tengfan@quicinc.com
> [2] v6: https://lore.kernel.org/linux-arm-msm/20240308070432.28195-1-quic_tengfan@quicinc.com
> [3] v5: https://lore.kernel.org/linux-arm-msm/20240301134113.14423-1-quic_tengfan@quicinc.com
> [4] v4: https://lore.kernel.org/linux-arm-msm/20240119100621.11788-1-quic_tengfan@quicinc.com
> [5] v3: https://lore.kernel.org/linux-arm-msm/20231219005007.11644-1-quic_tengfan@quicinc.com
> [6] v2: https://lore.kernel.org/linux-arm-msm/20231207092801.7506-1-quic_tengfan@quicinc.com
> [7] v1: https://lore.kernel.org/linux-arm-msm/20231117101817.4401-1-quic_tengfan@quicinc.com
>
> Tengfei Fan (4):
> dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board
> arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi
> arm64: dts: qcom: add base AIM300 dtsi
> arm64: dts: qcom: aim300: add AIM300 AIoT
>
> .../devicetree/bindings/arm/qcom.yaml | 8 +
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> .../boot/dts/qcom/qcs8550-aim300-aiot.dts | 343 +++++++++++++++
> arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 403 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++
> 5 files changed, 924 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
> create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi
>
>
> base-commit: a59668a9397e7245b26e9be85d23f242ff757ae8
> --
> 2.25.1
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y qcom/qcs8550-aim300-aiot.dtb' for 20240424024508.3857602-1-quic_tengfan@quicinc.com:
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: phy@1c0e000: clock-output-names: ['pcie1_pipe_clk'] is too short
from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: phy@1c0e000: #clock-cells:0:0: 1 was expected
from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
^ permalink raw reply [relevance 0%]
* [PATCH v7 5/6] soc: qcom: add pd-mapper implementation
2024-04-24 9:27 4% ` [PATCH v7 1/6] soc: qcom: pdr: protect locator_addr with the main mutex Dmitry Baryshkov
2024-04-24 9:28 4% ` [PATCH v7 4/6] soc: qcom: qmi: add a way to remove running service Dmitry Baryshkov
@ 2024-04-24 9:28 2% ` Dmitry Baryshkov
2 siblings, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-24 9:28 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Sibi Sankar, Mathieu Poirier
Cc: linux-arm-msm, linux-kernel, linux-remoteproc, Johan Hovold,
Xilin Wu, Bryan O'Donoghue
Existing userspace protection domain mapper implementation has several
issue. It doesn't play well with CONFIG_EXTRA_FIRMWARE, it doesn't
reread JSON files if firmware location is changed (or if firmware was
not available at the time pd-mapper was started but the corresponding
directory is mounted later), etc.
Provide in-kernel service implementing protection domain mapping
required to work with several services, which are provided by the DSP
firmware.
This module is loaded automatically by the remoteproc drivers when
necessary via the symbol dependency. It uses a root node to match a
protection domains map for a particular board. It is not possible to
implement it as a 'driver' as there is no corresponding device.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/soc/qcom/Kconfig | 10 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/pdr_internal.h | 14 +
drivers/soc/qcom/qcom_pd_mapper.c | 656 +++++++++++++++++++++++++++++++++++++
drivers/soc/qcom/qcom_pdr_msg.c | 34 ++
include/linux/soc/qcom/pd_mapper.h | 28 ++
6 files changed, 743 insertions(+)
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 95973c6b828f..f666366841b8 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -72,6 +72,16 @@ config QCOM_OCMEM
requirements. This is typically used by the GPU, camera/video, and
audio components on some Snapdragon SoCs.
+config QCOM_PD_MAPPER
+ tristate "Qualcomm Protection Domain Mapper"
+ select QCOM_QMI_HELPERS
+ depends on NET && QRTR
+ help
+ The Protection Domain Mapper maps registered services to the domains
+ and instances handled by the remote DSPs. This is a kernel-space
+ implementation of the service. It is a simpler alternative to the
+ userspace daemon.
+
config QCOM_PDR_HELPERS
tristate
select QCOM_QMI_HELPERS
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 3110ac3288bc..d3560f861085 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
obj-$(CONFIG_QCOM_OCMEM) += ocmem.o
+obj-$(CONFIG_QCOM_PD_MAPPER) += qcom_pd_mapper.o
obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o
obj-$(CONFIG_QCOM_PDR_MSG) += qcom_pdr_msg.o
obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink.o
diff --git a/drivers/soc/qcom/pdr_internal.h b/drivers/soc/qcom/pdr_internal.h
index 7e5bb5a95275..8d17f7fb79e7 100644
--- a/drivers/soc/qcom/pdr_internal.h
+++ b/drivers/soc/qcom/pdr_internal.h
@@ -13,6 +13,8 @@
#define SERVREG_SET_ACK_REQ 0x23
#define SERVREG_RESTART_PD_REQ 0x24
+#define SERVREG_LOC_PFR_REQ 0x24
+
#define SERVREG_DOMAIN_LIST_LENGTH 32
#define SERVREG_RESTART_PD_REQ_MAX_LEN 67
#define SERVREG_REGISTER_LISTENER_REQ_LEN 71
@@ -20,6 +22,7 @@
#define SERVREG_GET_DOMAIN_LIST_REQ_MAX_LEN 74
#define SERVREG_STATE_UPDATED_IND_MAX_LEN 79
#define SERVREG_GET_DOMAIN_LIST_RESP_MAX_LEN 2389
+#define SERVREG_LOC_PFR_RESP_MAX_LEN 10
struct servreg_location_entry {
char name[SERVREG_NAME_LENGTH + 1];
@@ -79,6 +82,15 @@ struct servreg_set_ack_resp {
struct qmi_response_type_v01 resp;
};
+struct servreg_loc_pfr_req {
+ char service[SERVREG_NAME_LENGTH + 1];
+ char reason[257];
+};
+
+struct servreg_loc_pfr_resp {
+ struct qmi_response_type_v01 rsp;
+};
+
extern const struct qmi_elem_info servreg_location_entry_ei[];
extern const struct qmi_elem_info servreg_get_domain_list_req_ei[];
extern const struct qmi_elem_info servreg_get_domain_list_resp_ei[];
@@ -89,5 +101,7 @@ extern const struct qmi_elem_info servreg_restart_pd_resp_ei[];
extern const struct qmi_elem_info servreg_state_updated_ind_ei[];
extern const struct qmi_elem_info servreg_set_ack_req_ei[];
extern const struct qmi_elem_info servreg_set_ack_resp_ei[];
+extern const struct qmi_elem_info servreg_loc_pfr_req_ei[];
+extern const struct qmi_elem_info servreg_loc_pfr_resp_ei[];
#endif
diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c
new file mode 100644
index 000000000000..ba5440506c95
--- /dev/null
+++ b/drivers/soc/qcom/qcom_pd_mapper.c
@@ -0,0 +1,656 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Qualcomm Protection Domain mapper
+ *
+ * Copyright (c) 2023 Linaro Ltd.
+ */
+
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/soc/qcom/pd_mapper.h>
+#include <linux/soc/qcom/qmi.h>
+
+#include "pdr_internal.h"
+
+#define SERVREG_QMI_VERSION 0x101
+#define SERVREG_QMI_INSTANCE 0
+
+#define TMS_SERVREG_SERVICE "tms/servreg"
+
+struct qcom_pdm_domain_data {
+ const char *domain;
+ u32 instance_id;
+ /* NULL-terminated array */
+ const char * services[];
+};
+
+struct qcom_pdm_domain {
+ struct list_head list;
+ const char *name;
+ u32 instance_id;
+};
+
+struct qcom_pdm_service {
+ struct list_head list;
+ struct list_head domains;
+ const char *name;
+};
+
+static DEFINE_MUTEX(qcom_pdm_count_mutex); /* guards count */
+/*
+ * It is not possible to use refcount_t here. The service needs to go to 0 and
+ * back without warnings.
+ */
+static unsigned int qcom_pdm_count;
+
+static DEFINE_MUTEX(qcom_pdm_mutex);
+static struct qmi_handle qcom_pdm_handle;
+static LIST_HEAD(qcom_pdm_services);
+
+static struct qcom_pdm_service *qcom_pdm_find(const char *name)
+{
+ struct qcom_pdm_service *service;
+
+ list_for_each_entry(service, &qcom_pdm_services, list) {
+ if (!strcmp(service->name, name))
+ return service;
+ }
+
+ return NULL;
+}
+
+static int qcom_pdm_add_service_domain(const char *service_name,
+ const char *domain_name,
+ u32 instance_id)
+{
+ struct qcom_pdm_service *service;
+ struct qcom_pdm_domain *domain;
+
+ service = qcom_pdm_find(service_name);
+ if (service) {
+ list_for_each_entry(domain, &service->domains, list) {
+ if (!strcmp(domain->name, domain_name))
+ return -EBUSY;
+ }
+ } else {
+ service = kzalloc(sizeof(*service), GFP_KERNEL);
+ if (!service)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&service->domains);
+ service->name = service_name;
+
+ list_add_tail(&service->list, &qcom_pdm_services);
+ }
+
+ domain = kzalloc(sizeof(*domain), GFP_KERNEL);
+ if (!domain) {
+ if (list_empty(&service->domains)) {
+ list_del(&service->list);
+ kfree(service);
+ }
+
+ return -ENOMEM;
+ }
+
+ domain->name = domain_name;
+ domain->instance_id = instance_id;
+ list_add_tail(&domain->list, &service->domains);
+
+ return 0;
+}
+
+static int qcom_pdm_add_domain(const struct qcom_pdm_domain_data *data)
+{
+ int ret;
+ int i;
+
+ ret = qcom_pdm_add_service_domain(TMS_SERVREG_SERVICE,
+ data->domain,
+ data->instance_id);
+ if (ret)
+ return ret;
+
+ for (i = 0; data->services[i]; i++) {
+ ret = qcom_pdm_add_service_domain(data->services[i],
+ data->domain,
+ data->instance_id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+
+}
+
+static void qcom_pdm_free_domains(void)
+{
+ struct qcom_pdm_service *service, *tservice;
+ struct qcom_pdm_domain *domain, *tdomain;
+
+ list_for_each_entry_safe(service, tservice, &qcom_pdm_services, list) {
+ list_for_each_entry_safe(domain, tdomain, &service->domains, list) {
+ list_del(&domain->list);
+ kfree(domain);
+ }
+
+ list_del(&service->list);
+ kfree(service);
+ }
+}
+
+static void qcom_pdm_get_domain_list(struct qmi_handle *qmi,
+ struct sockaddr_qrtr *sq,
+ struct qmi_txn *txn,
+ const void *decoded)
+{
+ const struct servreg_get_domain_list_req *req = decoded;
+ struct servreg_get_domain_list_resp *rsp = kzalloc(sizeof(*rsp), GFP_KERNEL);
+ struct qcom_pdm_service *service;
+ u32 offset;
+ int ret;
+
+ offset = req->domain_offset_valid ? req->domain_offset : 0;
+
+ rsp->resp.result = QMI_RESULT_SUCCESS_V01;
+ rsp->resp.error = QMI_ERR_NONE_V01;
+
+ rsp->db_rev_count_valid = true;
+ rsp->db_rev_count = 1;
+
+ rsp->total_domains_valid = true;
+ rsp->total_domains = 0;
+
+ mutex_lock(&qcom_pdm_mutex);
+
+ service = qcom_pdm_find(req->service_name);
+ if (service) {
+ struct qcom_pdm_domain *domain;
+
+ rsp->domain_list_valid = true;
+ rsp->domain_list_len = 0;
+
+ list_for_each_entry(domain, &service->domains, list) {
+ u32 i = rsp->total_domains++;
+
+ if (i >= offset && i < SERVREG_DOMAIN_LIST_LENGTH) {
+ u32 j = rsp->domain_list_len++;
+
+ strscpy(rsp->domain_list[j].name, domain->name,
+ sizeof(rsp->domain_list[i].name));
+ rsp->domain_list[j].instance = domain->instance_id;
+
+ pr_debug("PDM: found %s / %d\n", domain->name,
+ domain->instance_id);
+ }
+ }
+ }
+
+ pr_debug("PDM: service '%s' offset %d returning %d domains (of %d)\n", req->service_name,
+ req->domain_offset_valid ? req->domain_offset : -1, rsp->domain_list_len, rsp->total_domains);
+
+ ret = qmi_send_response(qmi, sq, txn, SERVREG_GET_DOMAIN_LIST_REQ,
+ SERVREG_GET_DOMAIN_LIST_RESP_MAX_LEN,
+ servreg_get_domain_list_resp_ei, rsp);
+ if (ret)
+ pr_err("Error sending servreg response: %d\n", ret);
+
+ mutex_unlock(&qcom_pdm_mutex);
+
+ kfree(rsp);
+}
+
+static void qcom_pdm_pfr(struct qmi_handle *qmi,
+ struct sockaddr_qrtr *sq,
+ struct qmi_txn *txn,
+ const void *decoded)
+{
+ const struct servreg_loc_pfr_req *req = decoded;
+ struct servreg_loc_pfr_resp rsp = {};
+ int ret;
+
+ pr_warn_ratelimited("PDM: service '%s' crash: '%s'\n", req->service, req->reason);
+
+ rsp.rsp.result = QMI_RESULT_SUCCESS_V01;
+ rsp.rsp.error = QMI_ERR_NONE_V01;
+
+ ret = qmi_send_response(qmi, sq, txn, SERVREG_LOC_PFR_REQ,
+ SERVREG_LOC_PFR_RESP_MAX_LEN,
+ servreg_loc_pfr_resp_ei, &rsp);
+ if (ret)
+ pr_err("Error sending servreg response: %d\n", ret);
+}
+
+static const struct qmi_msg_handler qcom_pdm_msg_handlers[] = {
+ {
+ .type = QMI_REQUEST,
+ .msg_id = SERVREG_GET_DOMAIN_LIST_REQ,
+ .ei = servreg_get_domain_list_req_ei,
+ .decoded_size = sizeof(struct servreg_get_domain_list_req),
+ .fn = qcom_pdm_get_domain_list,
+ },
+ {
+ .type = QMI_REQUEST,
+ .msg_id = SERVREG_LOC_PFR_REQ,
+ .ei = servreg_loc_pfr_req_ei,
+ .decoded_size = sizeof(struct servreg_loc_pfr_req),
+ .fn = qcom_pdm_pfr,
+ },
+ { },
+};
+
+static const struct qcom_pdm_domain_data adsp_audio_pd = {
+ .domain = "msm/adsp/audio_pd",
+ .instance_id = 74,
+ .services = {
+ "avs/audio",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data adsp_charger_pd = {
+ .domain = "msm/adsp/charger_pd",
+ .instance_id = 74,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data adsp_root_pd = {
+ .domain = "msm/adsp/root_pd",
+ .instance_id = 74,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data adsp_root_pd_pdr = {
+ .domain = "msm/adsp/root_pd",
+ .instance_id = 74,
+ .services = {
+ "tms/pdr_enabled",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data adsp_sensor_pd = {
+ .domain = "msm/adsp/sensor_pd",
+ .instance_id = 74,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data msm8996_adsp_audio_pd = {
+ .domain = "msm/adsp/audio_pd",
+ .instance_id = 4,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data msm8996_adsp_root_pd = {
+ .domain = "msm/adsp/root_pd",
+ .instance_id = 4,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data cdsp_root_pd = {
+ .domain = "msm/cdsp/root_pd",
+ .instance_id = 76,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data slpi_root_pd = {
+ .domain = "msm/slpi/root_pd",
+ .instance_id = 90,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data slpi_sensor_pd = {
+ .domain = "msm/slpi/sensor_pd",
+ .instance_id = 90,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data mpss_root_pd = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 180,
+ .services = {
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data mpss_root_pd_gps = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 180,
+ .services = {
+ "gps/gps_service",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data mpss_root_pd_gps_pdr = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 180,
+ .services = {
+ "gps/gps_service",
+ "tms/pdr_enabled",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data msm8996_mpss_root_pd = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 100,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data mpss_wlan_pd = {
+ .domain = "msm/modem/wlan_pd",
+ .instance_id = 180,
+ .services = {
+ "kernel/elf_loader",
+ "wlan/fw",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data *msm8996_domains[] = {
+ &msm8996_adsp_audio_pd,
+ &msm8996_adsp_root_pd,
+ &msm8996_mpss_root_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *msm8998_domains[] = {
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *qcm2290_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *qcs404_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc7180_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_sensor_pd,
+ &mpss_root_pd_gps_pdr,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc7280_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_charger_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps_pdr,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc8180x_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_charger_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc8280xp_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_charger_pd,
+ &cdsp_root_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sdm660_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sdm670_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sdm845_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ &slpi_root_pd,
+ &slpi_sensor_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm6115_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm6350_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8150_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8250_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &slpi_root_pd,
+ &slpi_sensor_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8350_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_charger_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &slpi_root_pd,
+ &slpi_sensor_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8550_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_charger_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ NULL,
+};
+
+static const struct of_device_id qcom_pdm_domains[] = {
+ { .compatible = "qcom,apq8064", .data = NULL, },
+ { .compatible = "qcom,apq8074", .data = NULL, },
+ { .compatible = "qcom,apq8084", .data = NULL, },
+ { .compatible = "qcom,apq8096", .data = msm8996_domains, },
+ { .compatible = "qcom,msm8226", .data = NULL, },
+ { .compatible = "qcom,msm8974", .data = NULL, },
+ { .compatible = "qcom,msm8996", .data = msm8996_domains, },
+ { .compatible = "qcom,msm8998", .data = msm8998_domains, },
+ { .compatible = "qcom,qcm2290", .data = qcm2290_domains, },
+ { .compatible = "qcom,qcs404", .data = qcs404_domains, },
+ { .compatible = "qcom,sc7180", .data = sc7180_domains, },
+ { .compatible = "qcom,sc7280", .data = sc7280_domains, },
+ { .compatible = "qcom,sc8180x", .data = sc8180x_domains, },
+ { .compatible = "qcom,sc8280xp", .data = sc8280xp_domains, },
+ { .compatible = "qcom,sda660", .data = sdm660_domains, },
+ { .compatible = "qcom,sdm660", .data = sdm660_domains, },
+ { .compatible = "qcom,sdm670", .data = sdm670_domains, },
+ { .compatible = "qcom,sdm845", .data = sdm845_domains, },
+ { .compatible = "qcom,sm6115", .data = sm6115_domains, },
+ { .compatible = "qcom,sm6350", .data = sm6350_domains, },
+ { .compatible = "qcom,sm8150", .data = sm8150_domains, },
+ { .compatible = "qcom,sm8250", .data = sm8250_domains, },
+ { .compatible = "qcom,sm8350", .data = sm8350_domains, },
+ { .compatible = "qcom,sm8450", .data = sm8350_domains, },
+ { .compatible = "qcom,sm8550", .data = sm8550_domains, },
+ { .compatible = "qcom,sm8650", .data = sm8550_domains, },
+ {},
+};
+
+static int qcom_pdm_start(void)
+{
+ const struct of_device_id *match;
+ const struct qcom_pdm_domain_data * const *domains;
+ struct device_node *root;
+ int ret, i;
+
+ root = of_find_node_by_path("/");
+ if (!root)
+ return -ENODEV;
+
+ match = of_match_node(qcom_pdm_domains, root);
+ of_node_put(root);
+ if (!match) {
+ pr_notice("PDM: no support for the platform, userspace daemon might be required.\n");
+ return -ENODEV;
+ }
+
+ domains = match->data;
+ if (!domains) {
+ pr_debug("PDM: no domains\n");
+ return -ENODEV;
+ }
+
+ mutex_lock(&qcom_pdm_mutex);
+ for (i = 0; domains[i]; i++) {
+ ret = qcom_pdm_add_domain(domains[i]);
+ if (ret)
+ goto free_domains;
+ }
+
+ ret = qmi_handle_init(&qcom_pdm_handle, 1024,
+ NULL, qcom_pdm_msg_handlers);
+ if (ret)
+ goto free_domains;
+
+ ret = qmi_add_server(&qcom_pdm_handle, SERVREG_LOCATOR_SERVICE,
+ SERVREG_QMI_VERSION, SERVREG_QMI_INSTANCE);
+ if (ret) {
+ pr_err("PDM: error adding server %d\n", ret);
+ goto release_handle;
+ }
+ mutex_unlock(&qcom_pdm_mutex);
+
+ return 0;
+
+release_handle:
+ qmi_handle_release(&qcom_pdm_handle);
+
+free_domains:
+ qcom_pdm_free_domains();
+ mutex_unlock(&qcom_pdm_mutex);
+
+ return ret;
+}
+
+static void qcom_pdm_stop(void)
+{
+ qmi_del_server(&qcom_pdm_handle, SERVREG_LOCATOR_SERVICE,
+ SERVREG_QMI_VERSION, SERVREG_QMI_INSTANCE);
+
+ qmi_handle_release(&qcom_pdm_handle);
+
+ qcom_pdm_free_domains();
+}
+
+/**
+ * qcom_pdm_get() - ensure that PD mapper is up and running
+ *
+ * Start the in-kernel Qualcomm DSP protection domain mapper service if it was
+ * not running.
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+int qcom_pdm_get(void)
+{
+ int ret = 0;
+
+ mutex_lock(&qcom_pdm_count_mutex);
+
+ if (!qcom_pdm_count)
+ ret = qcom_pdm_start();
+ if (!ret)
+ ++qcom_pdm_count;
+
+ mutex_unlock(&qcom_pdm_count_mutex);
+
+ /*
+ * If it is -ENODEV, the plaform is not supported by the in-kernel
+ * mapper. Still return 0 to rproc driver, userspace daemon will be
+ * used instead of the kernel server.
+ */
+ if (ret == -ENODEV)
+ return 0;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(qcom_pdm_get);
+
+/**
+ * qcom_pdm_release() - possibly stop PD mapper service
+ *
+ * Decreases refcount, stopping the server when the last user was removed.
+ */
+void qcom_pdm_release(void)
+{
+ mutex_lock(&qcom_pdm_count_mutex);
+
+ if (qcom_pdm_count == 1)
+ qcom_pdm_stop();
+
+ if (qcom_pdm_count >= 1)
+ --qcom_pdm_count;
+
+ mutex_unlock(&qcom_pdm_count_mutex);
+}
+EXPORT_SYMBOL_GPL(qcom_pdm_release);
+
+MODULE_DESCRIPTION("Qualcomm Protection Domain Mapper");
+MODULE_LICENSE("GPL");
diff --git a/drivers/soc/qcom/qcom_pdr_msg.c b/drivers/soc/qcom/qcom_pdr_msg.c
index 9b46f42aa146..bf3e4a47165e 100644
--- a/drivers/soc/qcom/qcom_pdr_msg.c
+++ b/drivers/soc/qcom/qcom_pdr_msg.c
@@ -315,5 +315,39 @@ const struct qmi_elem_info servreg_set_ack_resp_ei[] = {
};
EXPORT_SYMBOL_GPL(servreg_set_ack_resp_ei);
+const struct qmi_elem_info servreg_loc_pfr_req_ei[] = {
+ {
+ .data_type = QMI_STRING,
+ .elem_len = SERVREG_NAME_LENGTH + 1,
+ .elem_size = sizeof(char),
+ .array_type = VAR_LEN_ARRAY,
+ .tlv_type = 0x01,
+ .offset = offsetof(struct servreg_loc_pfr_req, service)
+ },
+ {
+ .data_type = QMI_STRING,
+ .elem_len = SERVREG_NAME_LENGTH + 1,
+ .elem_size = sizeof(char),
+ .array_type = VAR_LEN_ARRAY,
+ .tlv_type = 0x02,
+ .offset = offsetof(struct servreg_loc_pfr_req, reason)
+ },
+ {}
+};
+EXPORT_SYMBOL_GPL(servreg_loc_pfr_req_ei);
+
+const struct qmi_elem_info servreg_loc_pfr_resp_ei[] = {
+ {
+ .data_type = QMI_STRUCT,
+ .elem_len = 1,
+ .elem_size = sizeof_field(struct servreg_loc_pfr_resp, rsp),
+ .tlv_type = 0x02,
+ .offset = offsetof(struct servreg_loc_pfr_resp, rsp),
+ .ei_array = qmi_response_type_v01_ei,
+ },
+ {}
+};
+EXPORT_SYMBOL_GPL(servreg_loc_pfr_resp_ei);
+
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Qualcomm Protection Domain messages data");
diff --git a/include/linux/soc/qcom/pd_mapper.h b/include/linux/soc/qcom/pd_mapper.h
new file mode 100644
index 000000000000..d0dd3dfc8fea
--- /dev/null
+++ b/include/linux/soc/qcom/pd_mapper.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Qualcomm Protection Domain mapper
+ *
+ * Copyright (c) 2023 Linaro Ltd.
+ */
+#ifndef __QCOM_PD_MAPPER__
+#define __QCOM_PD_MAPPER__
+
+#if IS_ENABLED(CONFIG_QCOM_PD_MAPPER)
+
+int qcom_pdm_get(void);
+void qcom_pdm_release(void);
+
+#else
+
+static inline int qcom_pdm_get(void)
+{
+ return 0;
+}
+
+static inline void qcom_pdm_release(void)
+{
+}
+
+#endif
+
+#endif
--
2.39.2
^ permalink raw reply related [relevance 2%]
* [PATCH v7 4/6] soc: qcom: qmi: add a way to remove running service
2024-04-24 9:27 4% ` [PATCH v7 1/6] soc: qcom: pdr: protect locator_addr with the main mutex Dmitry Baryshkov
@ 2024-04-24 9:28 4% ` Dmitry Baryshkov
2024-04-25 20:57 0% ` Chris Lew
2024-04-24 9:28 2% ` [PATCH v7 5/6] soc: qcom: add pd-mapper implementation Dmitry Baryshkov
2 siblings, 1 reply; 200+ results
From: Dmitry Baryshkov @ 2024-04-24 9:28 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Sibi Sankar, Mathieu Poirier
Cc: linux-arm-msm, linux-kernel, linux-remoteproc, Johan Hovold,
Xilin Wu, Bryan O'Donoghue, Neil Armstrong
Add qmi_del_server(), a pair to qmi_add_server(), a way to remove
running server from the QMI socket. This is e.g. necessary for
pd-mapper, which needs to readd a server each time the DSP is started or
stopped.
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/soc/qcom/qmi_interface.c | 67 ++++++++++++++++++++++++++++++++++++++++
include/linux/soc/qcom/qmi.h | 2 ++
2 files changed, 69 insertions(+)
diff --git a/drivers/soc/qcom/qmi_interface.c b/drivers/soc/qcom/qmi_interface.c
index bb98b06e87f8..18ff2015c682 100644
--- a/drivers/soc/qcom/qmi_interface.c
+++ b/drivers/soc/qcom/qmi_interface.c
@@ -289,6 +289,73 @@ int qmi_add_server(struct qmi_handle *qmi, unsigned int service,
}
EXPORT_SYMBOL_GPL(qmi_add_server);
+static void qmi_send_del_server(struct qmi_handle *qmi, struct qmi_service *svc)
+{
+ struct qrtr_ctrl_pkt pkt;
+ struct sockaddr_qrtr sq;
+ struct msghdr msg = { };
+ struct kvec iv = { &pkt, sizeof(pkt) };
+ int ret;
+
+ memset(&pkt, 0, sizeof(pkt));
+ pkt.cmd = cpu_to_le32(QRTR_TYPE_DEL_SERVER);
+ pkt.server.service = cpu_to_le32(svc->service);
+ pkt.server.instance = cpu_to_le32(svc->version | svc->instance << 8);
+ pkt.server.node = cpu_to_le32(qmi->sq.sq_node);
+ pkt.server.port = cpu_to_le32(qmi->sq.sq_port);
+
+ sq.sq_family = qmi->sq.sq_family;
+ sq.sq_node = qmi->sq.sq_node;
+ sq.sq_port = QRTR_PORT_CTRL;
+
+ msg.msg_name = &sq;
+ msg.msg_namelen = sizeof(sq);
+
+ mutex_lock(&qmi->sock_lock);
+ if (qmi->sock) {
+ ret = kernel_sendmsg(qmi->sock, &msg, &iv, 1, sizeof(pkt));
+ if (ret < 0)
+ pr_err("send service deregistration failed: %d\n", ret);
+ }
+ mutex_unlock(&qmi->sock_lock);
+}
+
+/**
+ * qmi_del_server() - register a service with the name service
+ * @qmi: qmi handle
+ * @service: type of the service
+ * @instance: instance of the service
+ * @version: version of the service
+ *
+ * Remove registration of the service with the name service. This notifies
+ * clients that they should no longer send messages to the client associated
+ * with @qmi.
+ *
+ * Return: 0 on success, negative errno on failure.
+ */
+int qmi_del_server(struct qmi_handle *qmi, unsigned int service,
+ unsigned int version, unsigned int instance)
+{
+ struct qmi_service *svc;
+ struct qmi_service *tmp;
+
+ list_for_each_entry_safe(svc, tmp, &qmi->services, list_node) {
+ if (svc->service != service ||
+ svc->version != version ||
+ svc->instance != instance)
+ continue;
+
+ qmi_send_del_server(qmi, svc);
+ list_del(&svc->list_node);
+ kfree(svc);
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(qmi_del_server);
+
/**
* qmi_txn_init() - allocate transaction id within the given QMI handle
* @qmi: QMI handle
diff --git a/include/linux/soc/qcom/qmi.h b/include/linux/soc/qcom/qmi.h
index 469e02d2aa0d..5039c30e4bdc 100644
--- a/include/linux/soc/qcom/qmi.h
+++ b/include/linux/soc/qcom/qmi.h
@@ -241,6 +241,8 @@ int qmi_add_lookup(struct qmi_handle *qmi, unsigned int service,
unsigned int version, unsigned int instance);
int qmi_add_server(struct qmi_handle *qmi, unsigned int service,
unsigned int version, unsigned int instance);
+int qmi_del_server(struct qmi_handle *qmi, unsigned int service,
+ unsigned int version, unsigned int instance);
int qmi_handle_init(struct qmi_handle *qmi, size_t max_msg_len,
const struct qmi_ops *ops,
--
2.39.2
^ permalink raw reply related [relevance 4%]
* [PATCH v7 1/6] soc: qcom: pdr: protect locator_addr with the main mutex
@ 2024-04-24 9:27 4% ` Dmitry Baryshkov
2024-04-25 19:30 0% ` Chris Lew
2024-04-24 9:28 4% ` [PATCH v7 4/6] soc: qcom: qmi: add a way to remove running service Dmitry Baryshkov
2024-04-24 9:28 2% ` [PATCH v7 5/6] soc: qcom: add pd-mapper implementation Dmitry Baryshkov
2 siblings, 1 reply; 200+ results
From: Dmitry Baryshkov @ 2024-04-24 9:27 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Sibi Sankar, Mathieu Poirier
Cc: linux-arm-msm, linux-kernel, linux-remoteproc, Johan Hovold,
Xilin Wu, Bryan O'Donoghue, Neil Armstrong
If the service locator server is restarted fast enough, the PDR can
rewrite locator_addr fields concurrently. Protect them by placing
modification of those fields under the main pdr->lock.
Fixes: fbe639b44a82 ("soc: qcom: Introduce Protection Domain Restart helpers")
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/soc/qcom/pdr_interface.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/qcom/pdr_interface.c b/drivers/soc/qcom/pdr_interface.c
index a1b6a4081dea..19cfe4b41235 100644
--- a/drivers/soc/qcom/pdr_interface.c
+++ b/drivers/soc/qcom/pdr_interface.c
@@ -76,12 +76,12 @@ static int pdr_locator_new_server(struct qmi_handle *qmi,
locator_hdl);
struct pdr_service *pds;
+ mutex_lock(&pdr->lock);
/* Create a local client port for QMI communication */
pdr->locator_addr.sq_family = AF_QIPCRTR;
pdr->locator_addr.sq_node = svc->node;
pdr->locator_addr.sq_port = svc->port;
- mutex_lock(&pdr->lock);
pdr->locator_init_complete = true;
mutex_unlock(&pdr->lock);
@@ -104,10 +104,10 @@ static void pdr_locator_del_server(struct qmi_handle *qmi,
mutex_lock(&pdr->lock);
pdr->locator_init_complete = false;
- mutex_unlock(&pdr->lock);
pdr->locator_addr.sq_node = 0;
pdr->locator_addr.sq_port = 0;
+ mutex_unlock(&pdr->lock);
}
static const struct qmi_ops pdr_locator_ops = {
--
2.39.2
^ permalink raw reply related [relevance 4%]
* [PATCH v7 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT
2024-04-24 2:45 6% [PATCH v7 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
2024-04-24 2:45 16% ` [PATCH v7 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board Tengfei Fan
2024-04-24 2:45 9% ` [PATCH v7 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi Tengfei Fan
@ 2024-04-24 2:45 5% ` Tengfei Fan
2024-04-24 23:50 0% ` Dmitry Baryshkov
2024-04-24 13:14 0% ` [PATCH v7 0/4] arm64: qcom: add AIM300 AIoT board support Rob Herring
3 siblings, 1 reply; 200+ results
From: Tengfei Fan @ 2024-04-24 2:45 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzk+dt, conor+dt, dmitry.baryshkov
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan, Qiang Yu,
Ziyue Zhang
Add AIM300 AIoT Carrier board DTS support, including usb, UART, PCIe,
I2C functions support.
Here is a diagram of AIM300 AIoT Carrie Board and SoM
+--------------------------------------------------+
| AIM300 AIOT Carrier Board |
| |
| +-----------------+ |
|power----->| Fixed regulator |---------+ |
| +-----------------+ | |
| | |
| v VPH_PWR |
| +----------------------------------------------+ |
| | AIM300 SOM | | |
| | |VPH_PWR | |
| | v | |
| | +-------+ +--------+ +------+ | |
| | | UFS | | QCS8550| |PMIC | | |
| | +-------+ +--------+ +------+ | |
| | | |
| +----------------------------------------------+ |
| |
| +----+ +------+ |
| |USB | | UART | |
| +----+ +------+ |
+--------------------------------------------------+
Co-developed-by: Qiang Yu <quic_qianyu@quicinc.com>
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Co-developed-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/qcs8550-aim300-aiot.dts | 343 ++++++++++++++++++
2 files changed, 344 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index f63abb43e9fe..c46c10d85697 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -96,6 +96,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
new file mode 100644
index 000000000000..146bf6ea9e6a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "qcs8550-aim300.dtsi"
+#include "pm8010.dtsi"
+#include "pmr735d_a.dtsi"
+#include "pmr735d_b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCS8550 AIM300 AIOT";
+ compatible = "qcom,qcs8550-aim300-aiot", "qcom,qcs8550-aim300", "qcom,qcs8550",
+ "qcom,sm8550";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ debounce-interval = <15>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&redriver_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&fsa4480_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ };
+
+ regulators-3 {
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ };
+
+ regulators-4 {
+ vdd-s4-supply = <&vph_pwr>;
+ };
+
+ regulators-5 {
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ };
+};
+
+&i2c_hub_2 {
+ status = "okay";
+
+ typec-mux@42 {
+ compatible = "fcs,fsa4480";
+ reg = <0x42>;
+
+ vcc-supply = <&vreg_bob1>;
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ fsa4480_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+
+ typec-retimer@1c {
+ compatible = "onnn,nb7vpq904m";
+ reg = <0x1c>;
+
+ vcc-supply = <&vreg_l15b_1p8>;
+
+ orientation-switch;
+ retimer-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ redriver_ss_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ redriver_ss_in: endpoint {
+ data-lanes = <3 2 1 0>;
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+ };
+ };
+};
+
+&mdss_dsi0 {
+ status = "okay";
+
+ panel@0 {
+ compatible = "visionox,vtdr6130";
+ reg = <0>;
+
+ pinctrl-0 = <&dsi_active>, <&te_active>;
+ pinctrl-1 = <&dsi_suspend>, <&te_suspend>;
+ pinctrl-names = "default", "sleep";
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vci-supply = <&vreg_l13b_3p0>;
+ vdd-supply = <&vreg_l11b_1p2>;
+ vddio-supply = <&vreg_l12b_1p8>;
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ status = "okay";
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/qcs8550/adsp.mbn",
+ "qcom/qcs8550/adsp_dtbs.elf";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcs8550/cdsp.mbn",
+ "qcom/qcs8550/cdsp_dtbs.elf";
+ status = "okay";
+};
+
+&swr1 {
+ status = "okay";
+};
+
+&swr2 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 8>;
+
+ dsi_active: dsi-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ dsi_suspend: dsi-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ te_active: te-active-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ te_suspend: te-suspend-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+};
+
+&usb_1_hsphy {
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&redriver_ss_in>;
+};
+
+&usb_dp_qmpphy_usb_ss_in {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+};
--
2.25.1
^ permalink raw reply related [relevance 5%]
* [PATCH v7 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi
2024-04-24 2:45 6% [PATCH v7 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
2024-04-24 2:45 16% ` [PATCH v7 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board Tengfei Fan
@ 2024-04-24 2:45 9% ` Tengfei Fan
2024-04-24 2:45 5% ` [PATCH v7 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT Tengfei Fan
2024-04-24 13:14 0% ` [PATCH v7 0/4] arm64: qcom: add AIM300 AIoT board support Rob Herring
3 siblings, 0 replies; 200+ results
From: Tengfei Fan @ 2024-04-24 2:45 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzk+dt, conor+dt, dmitry.baryshkov
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan
QCS8550 is derived from SM8550. The differnece between SM8550 and
QCS8550 is QCS8550 doesn't have modem RF system. QCS8550 is mainly used
in IoT scenarios.
QCS8550 firmware has different memory map with SM8550 firmware. The
memory map will be runtime added through bootloader.
There are 3 types of reserved memory regions here:
1. Firmware related regions which aren't shared with kernel.
The device tree source in kernel doesn't need to have node to indicate
the firmware related reserved information. OS bootloader conveys the
information by update device tree in runtime.
This will be described as: UEFI saves the physical address of the
UEFI System Table to dts file's chosen node. Kernel read this table and
add reserved memory regions to efi config table. Current reserved memory
region may have reserved region which was not yet used, release note of
the firmware have such kind of information.
2. Firmware related memory regions which are shared with Kernel
Each region has a specific node with specific label name for later
phandle reference from other driver dt node.
3. PIL regions.
PIL regions will be reserved and then assigned to subsystem firmware
later.
Here is a reserved memory map for this platform:
0x100000000 +------------------+
| |
| Firmware Related |
| |
0xd4d00000 +------------------+
| |
| Kernel Available |
| |
0xa7000000 +------------------+
| |
| PIL Region |
| |
0x8a800000 +------------------+
| |
| Firmware Related |
| |
0x80000000 +------------------+
Note that:
0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
it is available for kernel usage. This region is not suggested to be
used by kernel features like ramoops, suspend resume etc.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++++++++++++++++++++
1 file changed, 169 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi
diff --git a/arch/arm64/boot/dts/qcom/qcs8550.dtsi b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
new file mode 100644
index 000000000000..a3ebf3d4e16d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550.dtsi
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "sm8550.dtsi"
+
+/delete-node/ &reserved_memory;
+
+/ {
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+
+ /* These are 3 types of reserved memory regions here:
+ * 1. Firmware related regions which aren't shared with kernel.
+ * The device tree source in kernel doesn't need to have node to
+ * indicate the firmware related reserved information. OS bootloader
+ * conveys the information by update device tree in runtime.
+ * This will be described as: UEFI saves the physical address of
+ * the UEFI System Table to dts file's chosen node. Kernel read this
+ * table and add reserved memory regions to efi config table. Current
+ * reserved memory region may have reserved region which was not yet
+ * used, release note of the firmware have such kind of information.
+ * 2. Firmware related memory regions which are shared with Kernel.
+ * Each region has a specific node with specific label name for
+ * later phandle reference from other driver dt node.
+ * 3. PIL regions.
+ * PIL regions will be reserved and then assigned to subsystem
+ * firmware later.
+ * Here is a reserved memory map for this platform:
+ * 0x100000000 +------------------+
+ * | |
+ * | Firmware Related |
+ * | |
+ * 0xd4d00000 +------------------+
+ * | |
+ * | Kernel Available |
+ * | |
+ * 0xa7000000 +------------------+
+ * | |
+ * | PIL Region |
+ * | |
+ * 0x8a800000 +------------------+
+ * | |
+ * | Firmware Related |
+ * | |
+ * 0x80000000 +------------------+
+ * Note that:
+ * 0xa7000000..0xA8000000 is used by bootloader, when kernel boot up,
+ * it is available for kernel usage. This region is not suggested to
+ * be used by kernel features like ramoops, suspend resume etc.
+ */
+
+ /*
+ * Firmware related regions, bootlader will possible reserve parts of
+ * region from 0x80000000..0x8a800000.
+ */
+ aop_image_mem: aop-image-region@81c00000 {
+ reg = <0x0 0x81c00000 0x0 0x60000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ aop_config_mem: aop-config-region@81c80000 {
+ no-map;
+ reg = <0x0 0x81c80000 0x0 0x20000>;
+ };
+
+ smem_mem: smem-region@81d00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x81d00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ adsp_mhi_mem: adsp-mhi-region@81f00000 {
+ reg = <0x0 0x81f00000 0x0 0x20000>;
+ no-map;
+ };
+
+ /* PIL region */
+ mpss_mem: mpss-region@8a800000 {
+ reg = <0x0 0x8a800000 0x0 0x10800000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
+ reg = <0x0 0x9b000000 0x0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw-region@9b080000 {
+ reg = <0x0 0x9b080000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi-region@9b090000 {
+ reg = <0x0 0x9b090000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
+ reg = <0x0 0x9b09a000 0x0 0x2000>;
+ no-map;
+ };
+
+ spss_region_mem: spss-region@9b100000 {
+ reg = <0x0 0x9b100000 0x0 0x180000>;
+ no-map;
+ };
+
+ spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 {
+ reg = <0x0 0x9b280000 0x0 0x80000>;
+ no-map;
+ };
+
+ camera_mem: camera-region@9b300000 {
+ reg = <0x0 0x9b300000 0x0 0x800000>;
+ no-map;
+ };
+
+ video_mem: video-region@9bb00000 {
+ reg = <0x0 0x9bb00000 0x0 0x700000>;
+ no-map;
+ };
+
+ cvp_mem: cvp-region@9c200000 {
+ reg = <0x0 0x9c200000 0x0 0x700000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp-region@9c900000 {
+ reg = <0x0 0x9c900000 0x0 0x2000000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
+ reg = <0x0 0x9e900000 0x0 0x80000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
+ reg = <0x0 0x9e980000 0x0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi-region@9ea00000 {
+ reg = <0x0 0x9ea00000 0x0 0x4080000>;
+ no-map;
+ };
+
+ /*
+ * Firmware related regions, bootlader will possible reserve parts of
+ * region from 0xd8000000..0x100000000.
+ */
+ mpss_dsm_mem: mpss_dsm_region@d4d00000 {
+ reg = <0x0 0xd4d00000 0x0 0x3300000>;
+ no-map;
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [relevance 9%]
* [PATCH v7 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board
2024-04-24 2:45 6% [PATCH v7 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
@ 2024-04-24 2:45 16% ` Tengfei Fan
2024-04-24 2:45 9% ` [PATCH v7 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi Tengfei Fan
` (2 subsequent siblings)
3 siblings, 0 replies; 200+ results
From: Tengfei Fan @ 2024-04-24 2:45 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzk+dt, conor+dt, dmitry.baryshkov
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan,
Krzysztof Kozlowski
Document QCS8550 SoC and the AIM300 AIoT board bindings.
QCS8550 is derived from SM8550. The difference between SM8550 and
QCS8550 is QCS8550 doesn't have modem RF system. QCS8550 is mainly used
in IoT scenarios.
AIM300 Series is a highly optimized family of modules designed to
support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC chip
etc.
AIM stands for Artificial Intelligence Module. AIoT stands for AI IoT.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 98b4187f2aad..090fc5fda9b0 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -42,6 +42,7 @@ description: |
msm8996
msm8998
qcs404
+ qcs8550
qcm2290
qcm6490
qdu1000
@@ -1000,6 +1001,13 @@ properties:
- sony,pdx234
- const: qcom,sm8550
+ - items:
+ - enum:
+ - qcom,qcs8550-aim300-aiot
+ - const: qcom,qcs8550-aim300
+ - const: qcom,qcs8550
+ - const: qcom,sm8550
+
- items:
- enum:
- qcom,sm8650-mtp
--
2.25.1
^ permalink raw reply related [relevance 16%]
* [PATCH v7 0/4] arm64: qcom: add AIM300 AIoT board support
@ 2024-04-24 2:45 6% Tengfei Fan
2024-04-24 2:45 16% ` [PATCH v7 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board Tengfei Fan
` (3 more replies)
0 siblings, 4 replies; 200+ results
From: Tengfei Fan @ 2024-04-24 2:45 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzk+dt, conor+dt, dmitry.baryshkov
Cc: keescook, tony.luck, gpiccoli, linux-arm-msm, devicetree,
linux-kernel, linux-hardening, kernel, Tengfei Fan
Add AIM300 AIoT support along with usb, ufs, regulators, serial, PCIe,
and PMIC functions.
AIM300 Series is a highly optimized family of modules designed to
support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC
chip etc.
Here is a diagram of AIM300 AIoT Carrie Board and SoM
+--------------------------------------------------+
| AIM300 AIOT Carrier Board |
| |
| +-----------------+ |
|power----->| Fixed regulator |---------+ |
| +-----------------+ | |
| | |
| v VPH_PWR |
| +----------------------------------------------+ |
| | AIM300 SOM | | |
| | |VPH_PWR | |
| | v | |
| | +-------+ +--------+ +------+ | |
| | | UFS | | QCS8550| |PMIC | | |
| | +-------+ +--------+ +------+ | |
| | | |
| +----------------------------------------------+ |
| |
| +----+ +------+ |
| |USB | | UART | |
| +----+ +------+ |
+--------------------------------------------------+
The following functions have been verified:
- uart
- usb
- ufs
- PCIe
- PMIC
- display
- adsp
- cdsp
- tlmm
Documentation for qcs8550[1] and sm8550[2]
[1] https://docs.qualcomm.com/bundle/publicresource/87-61717-1_REV_A_Qualcomm_QCS8550_QCM8550_Processors_Product_Brief.pdf
[2] https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/Snapdragon-8-Gen-2-Product-Brief.pdf
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
v6 -> v7:
- correct typos in the commit message
- move mdss_dsi0, mdss_dsi0_phy, pcie0_phy, pcie1_phy and usb_dp_qmpphy
vdda supply to qcs8550-aim300.dtsi
- move the perst and wake gpio settings of pcie0 and pcie1 to
qcs8550-aim300.dtsi
- move the clock frequency settings of pcie_1_phy_aux_clk, sleep_clk
and xo_board to qcs8550-aim300.dtsi
- verified with dtb check, and result is expected, because those
warnings are not introduced by current patch series.
arch/arm64/boot/dts/qcom/sm8550.dtsi:3037.27-3092.6: Warning
(avoid_unnecessary_addr_size): /soc@0/display-subsystem@ae00000/dsi@ae96000: unnecessary
#address-cells/#size-cells without "ranges" or child "reg" property
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
phy@1c0e000: clock-output-names: ['pcie1_pipe_clk'] is too short
from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb: phy@1c0e000: #clock-cells:0:0: 1 was expected
from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
v5 -> v6:
- move qcs8550 board info bebind sm8550 boards info in qcom.yaml
v4 -> v5:
- "2023-2024" instead of "2023~2024" for License
- update patch commit message to previous comments and with an updated
board diagram
- use qcs8550.dtsi instead of qcm8550.dtsi
- remove the reserved memory regions which will be handled by
bootloader
- remove pm8550_flash, pm8550_pwm nodes, Type-C USB/DP function node,
remoteproc_mpss function node, audio sound DTS node, new patch will
be updated after respective team's end to end full verification
- address comments to vph_pwr, move vph_pwr node and related
references to qcs8550-aim300-aiot.dts
- use "regulator-vph-pwr" instead of "vph_pwr_regulator"
- add pcie0I AND pcie1 support together
- the following patches were applied, so remove these patches from new
patch series:
- https://lore.kernel.org/linux-arm-msm/20240119100621.11788-3-quic_tengfan@quicinc.com
- https://lore.kernel.org/linux-arm-msm/20240119100621.11788-4-quic_tengfan@quicinc.com
- verified with dtb check, and result is expected, because those
warnings are not introduced by current patch series.
DTC_CHK arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb
arch/arm64/boot/dts/qcom/sm8550.dtsi:3015.27-3070.6: Warning
(avoid_unnecessary_addr_size): /soc@0/display-subsystem@ae00000/dsi@ae96000: unnecessary
#address-cells/#size-cells without "ranges" or child "reg" property
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
opp-table: opp-75000000:opp-hz:0: [75000000, 0, 0, 75000000, 0, 0, 0, 0] is too long
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
opp-table: opp-150000000:opp-hz:0: [150000000, 0, 0, 150000000, 0, 0, 0, 0] is too long
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
opp-table: opp-300000000:opp-hz:0: [300000000, 0, 0, 300000000, 0, 0, 0, 0] is too long
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dtb:
opp-table: Unevaluated properties are not allowed ('opp-150000000', 'opp-300000000', 'opp-75000000' were unexpected)
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
v3 -> v4:
- use qcm8550.dtsi instead of qcs8550.dtsi, qcs8550 is a QCS version
of qcm8550, another board with qcm8550 will be added later
- add AIM300 AIoT board string in qcom.yaml file
- add sm8550 and qcm8550 fallback compatible
- add qcm8550 SoC id
- add reserved memory map codes in qcm8550.dtsi
- pm8010 and pmr73d are splited into carrier board DTS file. Because
the regulators which in pm8550, pm8550ve and pm8550vs are present
on the SoM. The regulators which in pm8010 and pmr73d are present
on the carrier board.
- stay VPH_PWR at qcs8550-aim300.dtsi file
VPH_PWR is obtained by vonverting 12v voltage into 3.7 voltage
with a 3.7v buck. VPH_PWR is power supply for regulators in AIM300
SOM. VPH_PWR regulator is defined in AIM300 SOM dtsi file.
v2 -> v3:
- introduce qcs8550.dtsi
- separate fix dtc W=1 warning patch to another patch series
v1 -> v2:
- merge the splited dts patches into one patch
- update dts file name from qcom8550-aim300.dts to qcs8550-aim300 dts
- drop PCIe1 dts node due to it is not enabled
- update display node name for drop sde characters
previous discussion here:
[1] v6 RESEND: https://lore.kernel.org/linux-arm-msm/20240401093843.2591147-1-quic_tengfan@quicinc.com
[2] v6: https://lore.kernel.org/linux-arm-msm/20240308070432.28195-1-quic_tengfan@quicinc.com
[3] v5: https://lore.kernel.org/linux-arm-msm/20240301134113.14423-1-quic_tengfan@quicinc.com
[4] v4: https://lore.kernel.org/linux-arm-msm/20240119100621.11788-1-quic_tengfan@quicinc.com
[5] v3: https://lore.kernel.org/linux-arm-msm/20231219005007.11644-1-quic_tengfan@quicinc.com
[6] v2: https://lore.kernel.org/linux-arm-msm/20231207092801.7506-1-quic_tengfan@quicinc.com
[7] v1: https://lore.kernel.org/linux-arm-msm/20231117101817.4401-1-quic_tengfan@quicinc.com
Tengfei Fan (4):
dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board
arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi
arm64: dts: qcom: add base AIM300 dtsi
arm64: dts: qcom: aim300: add AIM300 AIoT
.../devicetree/bindings/arm/qcom.yaml | 8 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/qcs8550-aim300-aiot.dts | 343 +++++++++++++++
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 403 ++++++++++++++++++
arch/arm64/boot/dts/qcom/qcs8550.dtsi | 169 ++++++++
5 files changed, 924 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550.dtsi
base-commit: a59668a9397e7245b26e9be85d23f242ff757ae8
--
2.25.1
^ permalink raw reply [relevance 6%]
* [PATCH v2 3/4] clk: qcom: dispcc-sm8550: fix DisplayPort clocks
2024-04-24 1:39 6% [PATCH v2 0/4] clk: qcom: dispcc: fix DisplayPort link clocks Dmitry Baryshkov
@ 2024-04-24 1:39 16% ` Dmitry Baryshkov
2024-04-27 19:34 4% ` [PATCH v2 0/4] clk: qcom: dispcc: fix DisplayPort link clocks Bjorn Andersson
1 sibling, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-24 1:39 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Konrad Dybcio,
Konrad Dybcio, Neil Armstrong
Cc: linux-arm-msm, linux-clk, linux-kernel
On SM8550 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.
This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/dispcc-sm8550.c | 20 ++++----------------
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c
index 3672c73ac11c..38ecea805503 100644
--- a/drivers/clk/qcom/dispcc-sm8550.c
+++ b/drivers/clk/qcom/dispcc-sm8550.c
@@ -345,26 +345,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
},
};
-static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {
- F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
- F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
- F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
- F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
- { }
-};
-
static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
.cmd_rcgr = 0x8170,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_7,
- .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_clk_src",
.parent_data = disp_cc_parent_data_7,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_byte2_ops,
},
};
@@ -418,13 +409,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
- .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_byte2_ops,
},
};
@@ -478,13 +468,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
- .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_byte2_ops,
},
};
@@ -538,13 +527,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
- .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_byte2_ops,
},
};
--
2.39.2
^ permalink raw reply related [relevance 16%]
* [PATCH v2 0/4] clk: qcom: dispcc: fix DisplayPort link clocks
@ 2024-04-24 1:39 6% Dmitry Baryshkov
2024-04-24 1:39 16% ` [PATCH v2 3/4] clk: qcom: dispcc-sm8550: fix DisplayPort clocks Dmitry Baryshkov
2024-04-27 19:34 4% ` [PATCH v2 0/4] clk: qcom: dispcc: fix DisplayPort link clocks Bjorn Andersson
0 siblings, 2 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-24 1:39 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Konrad Dybcio,
Konrad Dybcio, Neil Armstrong
Cc: linux-arm-msm, linux-clk, linux-kernel, Luca Weiss
On several Qualcomm platforms DisplayPort link clocks used incorrect
frequency tables. Drop frequency tables and use clk_byte2_ops instead of
clk_rcg2_ops.
Note, this was tested on SM8450 only and then extended to other
platforms.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes in v2:
- Expanded commit messages to mention exact issue being fixed and the
triggering message (Stephen Boyd, Bjorn)
- Link to v1: https://lore.kernel.org/r/20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@linaro.org
---
Dmitry Baryshkov (4):
clk: qcom: dispcc-sm8450: fix DisplayPort clocks
clk: qcom: dispcc-sm6350: fix DisplayPort clocks
clk: qcom: dispcc-sm8550: fix DisplayPort clocks
clk: qcom: dispcc-sm8650: fix DisplayPort clocks
drivers/clk/qcom/dispcc-sm6350.c | 11 +----------
drivers/clk/qcom/dispcc-sm8450.c | 20 ++++----------------
drivers/clk/qcom/dispcc-sm8550.c | 20 ++++----------------
drivers/clk/qcom/dispcc-sm8650.c | 20 ++++----------------
4 files changed, 13 insertions(+), 58 deletions(-)
---
base-commit: a59668a9397e7245b26e9be85d23f242ff757ae8
change-id: 20240408-dispcc-dp-clocks-5ee5d5926346
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
^ permalink raw reply [relevance 6%]
* [PATCH 6.6 021/158] drm/msm/dpu: populate SSPP scaler block version
@ 2024-04-23 21:37 2% ` Greg Kroah-Hartman
0 siblings, 0 replies; 200+ results
From: Greg Kroah-Hartman @ 2024-04-23 21:37 UTC (permalink / raw)
To: stable
Cc: Greg Kroah-Hartman, patches, Marijn Suijten, Dmitry Baryshkov,
Sasha Levin
6.6-stable review patch. If anyone has any objections, please let me know.
------------------
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
[ Upstream commit 46b1f1b839cad600de3ad7ed999bd0155c528746 ]
The function _dpu_hw_sspp_setup_scaler3() passes and
dpu_hw_setup_scaler3() uses scaler_blk.version to determine in which way
the scaler (QSEED3) block should be programmed. However up to now we
were not setting this field. Set it now, splitting the vig_sblk data
which has different version fields.
Reported-by: Marijn Suijten <marijn.suijten@somainline.org>
Fixes: 9b6f4fedaac2 ("drm/msm/dpu: Add SM6125 support")
Fixes: 27f0df03f3ff ("drm/msm/dpu: Add SM6375 support")
Fixes: 3186acba5cdc ("drm/msm/dpu: Add SM6350 support")
Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550")
Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP")
Fixes: 0e91bcbb0016 ("drm/msm/dpu: Add SM8350 to hw catalog")
Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450")
Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM6115")
Fixes: dabfdd89eaa9 ("drm/msm/disp/dpu1: add inline rotation support for sc7280")
Fixes: f3af2d6ee9ab ("drm/msm/dpu: Add SC8180x to hw catalog")
Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog")
Fixes: af776a3e1c30 ("drm/msm/dpu: add SM8250 to hw catalog")
Fixes: 386fced3f76f ("drm/msm/dpu: add SM8150 to hw catalog")
Fixes: b75ab05a3479 ("msm:disp:dpu1: add scaler support on SC7180 display")
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/570098/
Link: https://lore.kernel.org/r/20231201234234.2065610-2-dmitry.baryshkov@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 +-
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 8 +-
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 95 ++++++++++++++-----
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +-
5 files changed, 87 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 99acaf917e430..f0c3804f42587 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -77,7 +77,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f0,
.features = VIG_SDM845_MASK,
- .sblk = &sdm845_vig_sblk_0,
+ .sblk = &sm8150_vig_sblk_0,
.xin_id = 0,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0,
@@ -85,7 +85,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x1f0,
.features = VIG_SDM845_MASK,
- .sblk = &sdm845_vig_sblk_1,
+ .sblk = &sm8150_vig_sblk_1,
.xin_id = 4,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1,
@@ -93,7 +93,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x1f0,
.features = VIG_SDM845_MASK,
- .sblk = &sdm845_vig_sblk_2,
+ .sblk = &sm8150_vig_sblk_2,
.xin_id = 8,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2,
@@ -101,7 +101,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x1f0,
.features = VIG_SDM845_MASK,
- .sblk = &sdm845_vig_sblk_3,
+ .sblk = &sm8150_vig_sblk_3,
.xin_id = 12,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index c92fbf24fbac1..47de71e71e310 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -76,7 +76,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f0,
.features = VIG_SDM845_MASK,
- .sblk = &sdm845_vig_sblk_0,
+ .sblk = &sm8150_vig_sblk_0,
.xin_id = 0,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0,
@@ -84,7 +84,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x1f0,
.features = VIG_SDM845_MASK,
- .sblk = &sdm845_vig_sblk_1,
+ .sblk = &sm8150_vig_sblk_1,
.xin_id = 4,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1,
@@ -92,7 +92,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x1f0,
.features = VIG_SDM845_MASK,
- .sblk = &sdm845_vig_sblk_2,
+ .sblk = &sm8150_vig_sblk_2,
.xin_id = 8,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2,
@@ -100,7 +100,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x1f0,
.features = VIG_SDM845_MASK,
- .sblk = &sdm845_vig_sblk_3,
+ .sblk = &sm8150_vig_sblk_3,
.xin_id = 12,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 8a19cfa274dea..72a1726371cae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -77,7 +77,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x32c,
.features = VIG_SC7180_MASK,
- .sblk = &sm8250_vig_sblk_0,
+ .sblk = &sm8450_vig_sblk_0,
.xin_id = 0,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0,
@@ -85,7 +85,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x32c,
.features = VIG_SC7180_MASK,
- .sblk = &sm8250_vig_sblk_1,
+ .sblk = &sm8450_vig_sblk_1,
.xin_id = 4,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1,
@@ -93,7 +93,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x32c,
.features = VIG_SC7180_MASK,
- .sblk = &sm8250_vig_sblk_2,
+ .sblk = &sm8450_vig_sblk_2,
.xin_id = 8,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2,
@@ -101,7 +101,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x32c,
.features = VIG_SC7180_MASK,
- .sblk = &sm8250_vig_sblk_3,
+ .sblk = &sm8450_vig_sblk_3,
.xin_id = 12,
.type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 713dfc0797181..77d09f961d866 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -250,14 +250,17 @@ static const uint32_t wb2_formats[] = {
* SSPP sub blocks config
*************************************************************/
+#define SSPP_SCALER_VER(maj, min) (((maj) << 16) | (min))
+
/* SSPP common configuration */
-#define _VIG_SBLK(sdma_pri, qseed_ver) \
+#define _VIG_SBLK(sdma_pri, qseed_ver, scaler_ver) \
{ \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \
.smart_dma_priority = sdma_pri, \
.scaler_blk = {.name = "scaler", \
.id = qseed_ver, \
+ .version = scaler_ver, \
.base = 0xa00, .len = 0xa0,}, \
.csc_blk = {.name = "csc", \
.id = DPU_SSPP_CSC_10BIT, \
@@ -269,13 +272,14 @@ static const uint32_t wb2_formats[] = {
.rotation_cfg = NULL, \
}
-#define _VIG_SBLK_ROT(sdma_pri, qseed_ver, rot_cfg) \
+#define _VIG_SBLK_ROT(sdma_pri, qseed_ver, scaler_ver, rot_cfg) \
{ \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \
.smart_dma_priority = sdma_pri, \
.scaler_blk = {.name = "scaler", \
.id = qseed_ver, \
+ .version = scaler_ver, \
.base = 0xa00, .len = 0xa0,}, \
.csc_blk = {.name = "csc", \
.id = DPU_SSPP_CSC_10BIT, \
@@ -299,13 +303,17 @@ static const uint32_t wb2_formats[] = {
}
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 =
- _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3,
+ SSPP_SCALER_VER(1, 2));
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 =
- _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3,
+ SSPP_SCALER_VER(1, 2));
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 =
- _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3,
+ SSPP_SCALER_VER(1, 2));
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 =
- _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3,
+ SSPP_SCALER_VER(1, 2));
static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
.rot_maxheight = 1088,
@@ -314,13 +322,30 @@ static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
};
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
- _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3,
+ SSPP_SCALER_VER(1, 3));
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
- _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3,
+ SSPP_SCALER_VER(1, 3));
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
- _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3,
+ SSPP_SCALER_VER(1, 3));
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
- _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3);
+ _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3,
+ SSPP_SCALER_VER(1, 3));
+
+static const struct dpu_sspp_sub_blks sm8150_vig_sblk_0 =
+ _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3,
+ SSPP_SCALER_VER(1, 4));
+static const struct dpu_sspp_sub_blks sm8150_vig_sblk_1 =
+ _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3,
+ SSPP_SCALER_VER(1, 4));
+static const struct dpu_sspp_sub_blks sm8150_vig_sblk_2 =
+ _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3,
+ SSPP_SCALER_VER(1, 4));
+static const struct dpu_sspp_sub_blks sm8150_vig_sblk_3 =
+ _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3,
+ SSPP_SCALER_VER(1, 4));
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2);
@@ -328,34 +353,60 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK(3);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4);
static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
- _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
- _VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2);
+ _VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 0),
+ &dpu_rot_sc7280_cfg_v2);
static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
- _VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =
- _VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE);
+ _VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE,
+ SSPP_SCALER_VER(2, 4));
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
- _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
- _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
- _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
- _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 0));
+
+static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 =
+ _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 1));
+static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 =
+ _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 1));
+static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 =
+ _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 1));
+static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 =
+ _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 1));
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =
- _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 2));
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 =
- _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 2));
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 =
- _VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 2));
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 =
- _VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4);
+ _VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4,
+ SSPP_SCALER_VER(3, 2));
static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5);
static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 6c9634209e9fc..3f82d84bd1c90 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -269,7 +269,8 @@ enum {
/**
* struct dpu_scaler_blk: Scaler information
* @info: HW register and features supported by this sub-blk
- * @version: qseed block revision
+ * @version: qseed block revision, on QSEED3+ platforms this is the value of
+ * scaler_blk.base + QSEED3_HW_VERSION registers.
*/
struct dpu_scaler_blk {
DPU_HW_SUBBLK_INFO;
--
2.43.0
^ permalink raw reply related [relevance 2%]
* Re: [PULL] Please pull qcom/qcom-main
2024-04-23 13:46 6% [PULL] Please pull qcom/qcom-main Caleb Connolly
@ 2024-04-23 21:22 0% ` Tom Rini
0 siblings, 0 replies; 200+ results
From: Tom Rini @ 2024-04-23 21:22 UTC (permalink / raw)
To: Caleb Connolly
Cc: Neil Armstrong, Robert Marko, Sumit Garg, u-boot-qcom, u-boot
[-- Attachment #1: Type: text/plain, Size: 1691 bytes --]
On Tue, Apr 23, 2024 at 03:46:19PM +0200, Caleb Connolly wrote:
> Overshot the -rc1 deadline, but I hope these can still make in for 2024.07.
>
> Support is added for 5 new Qualcomm SoCs:
>
> * QCM2290 and SM6115 are low and mid range SoCs used on the RB1 and RB2
> respectively. SM6115 is also used in some mid-range smartphones/tablets.
> Initial support includes buttons and USB (host and gadget).
> * SM8250 is a flagship SoC from 2020 used on the RB5, as well as many flagship
> smartphones. The board can boot to a U-Boot prompt, but is missing regulators
> necessary for USB support.
> * SM8550, and SM8650 are flagship mobile SoCs from 2023 and 2024
> respectively. Found on many high end smartphones.
>
> In addition:
>
> * Support is added for the Schneider HMIBSC board.
> * mach-snapdragon switches to OF_UPSTREAM
> * IPQ40xx gets several regressions fixed and some overall cleanup.
> * The MSM serial driver gains the ability to generate the bit-clock
> automatically, no longer relying on a custom DT property.
> * The Qualcomm SMMU driver gets a generic compatible (so per-SoC compatibles
> don't need to be added).
> * Support for the GENI I2C controller is added.
> * The qcom SPMI driver has SPMI v5 support fixed, and v7 support added.
> * The qcom sdhci driver gets some fixes for SDCC v5 support.
> * SDM845 gains sdcard support
> * Support is added for the Synopsys eUSB2 PHY driver (used on SM8550 and SM8650)
> * SYS_INIT_SP_BSS_OFFSET is set to 1.5M to give us more space for FDTs.
> * RB2 gets a work-around to fix the USB dr_mode property before booting Linux.
>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [relevance 0%]
* [PATCH v2] usb: dwc3: support USB 3.1 controllers
@ 2024-04-23 14:15 4% Caleb Connolly
0 siblings, 0 replies; 200+ results
From: Caleb Connolly @ 2024-04-23 14:15 UTC (permalink / raw)
To: Caleb Connolly, Igor Prusov, Marek Vasut, Mattijs Korpershoek,
Nishanth Menon, Patrice Chotard, Stefan Bosch, Tom Rini
Cc: Neil Armstrong, Eugen Hristev, Marek Vasut, u-boot
The revision is different for these, add the additional check as in
xhci-dwc3 core_init code.
Equivalent upstream Linux patch:
690fb3718a70 ("usb: dwc3: Support Synopsys USB 3.1 IP")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
Changes since v1:
* Reference Linux patch
* V1: https://lore.kernel.org/u-boot/20240411160527.835767-1-caleb.connolly@linaro.org
---
drivers/usb/dwc3/core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 96e850b7170f..db045f5822d4 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -594,9 +594,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
int ret;
reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
/* This should read as U3 followed by revision number */
- if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
+ if ((reg & DWC3_GSNPSID_MASK) != 0x55330000 &&
+ (reg & DWC3_GSNPSID_MASK) != 0x33310000) {
dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
ret = -ENODEV;
goto err0;
}
--
2.44.0
^ permalink raw reply related [relevance 4%]
* Re: [PATCH RFT 0/7] arm64: qcom: allow up to 4 lanes for the Type-C DisplayPort Altmode
2024-04-23 13:03 0% ` Konrad Dybcio
@ 2024-04-23 14:08 0% ` neil.armstrong
-1 siblings, 0 replies; 200+ results
From: neil.armstrong @ 2024-04-23 14:08 UTC (permalink / raw)
To: Konrad Dybcio, Luca Weiss, Bjorn Andersson
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Abhinav Kumar, linux-arm-msm,
linux-phy, devicetree, linux-kernel
On 23/04/2024 15:03, Konrad Dybcio wrote:
>
>
> On 4/5/24 12:19, Luca Weiss wrote:
>> On Fri Apr 5, 2024 at 10:08 AM CEST, Neil Armstrong wrote:
>>> Hi Luca,
>>>
>>> On 29/03/2024 10:02, Luca Weiss wrote:
>>>> On Tue Mar 26, 2024 at 10:02 PM CET, Konrad Dybcio wrote:
>>>>> On 16.03.2024 5:01 PM, Bjorn Andersson wrote:
>>>>>> On Fri, Mar 15, 2024 at 06:35:15PM +0100, Neil Armstrong wrote:
>>>>>>> On 15/03/2024 18:19, Luca Weiss wrote:
>>>>>>>> On Thu Feb 29, 2024 at 2:07 PM CET, Neil Armstrong wrote:
>>>>>>>>> Register a typec mux in order to change the PHY mode on the Type-C
>>>>>>>>> mux events depending on the mode and the svid when in Altmode setup.
>>>>>>>>>
>>>>>>>>> The DisplayPort phy should be left enabled if is still powered on
>>>>>>>>> by the DRM DisplayPort controller, so bail out until the DisplayPort
>>>>>>>>> PHY is not powered off.
>>>>>>>>>
>>>>>>>>> The Type-C Mode/SVID only changes on plug/unplug, and USB SAFE states
>>>>>>>>> will be set in between of USB-Only, Combo and DisplayPort Only so
>>>>>>>>> this will leave enough time to the DRM DisplayPort controller to
>>>>>>>>> turn of the DisplayPort PHY.
>>>>>>>>>
>>>>>>>>> The patchset also includes bindings changes and DT changes.
>>>>>>>>>
>>>>>>>>> This has been successfully tested on an SM8550 board, but the
>>>>>>>>> Thinkpad X13s deserved testing between non-PD USB, non-PD DisplayPort,
>>>>>>>>> PD USB Hubs and PD Altmode Dongles to make sure the switch works
>>>>>>>>> as expected.
>>>>>>>>>
>>>>>>>>> The DisplayPort 4 lanes setup can be check with:
>>>>>>>>> $ cat /sys/kernel/debug/dri/ae01000.display-controller/DP-1/dp_debug
>>>>>>>>> name = msm_dp
>>>>>>>>> drm_dp_link
>>>>>>>>> rate = 540000
>>>>>>>>> num_lanes = 4
>>>>>>>>
>>>>>>>> Hi Neil,
>>>>>>>>
>>>>>>>> I tried this on QCM6490/SC7280 which should also support 4-lane DP but I
>>>>>>>> haven't had any success so far.
>>>>>>>>
>>>>>> [..]
>>>>>>>> [ 1775.563969] [drm:dp_ctrl_link_train] *ERROR* max v_level reached
>>>>>>>> [ 1775.564031] [drm:dp_ctrl_link_train] *ERROR* link training #1 failed. ret=-11
>>>>>>>
>>>>>>> Interesting #1 means the 4 lanes are not physically connected to the other side,
>>>>>>> perhaps QCM6490/SC7280 requires a specific way to enable the 4 lanes in the PHY,
>>>>>>> or some fixups in the init tables.
>>>>>>>
>>>>>>
>>>>>> I tested the same on rb3gen2 (qcs6490) a couple of weeks ago, with the
>>>>>> same outcome. Looking at the AUX reads, after switching to 4-lane the
>>>>>> link training is failing on all 4 lanes, in contrast to succeeding only
>>>>>> on the first 2 if you e.g. forget to mux the other two.
>>>>>>
>>>>>> As such, my expectation is that there's something wrong in the QMP PHY
>>>>>> (or possibly redriver) for this platform.
>>>>>
>>>>> Do we have any downstream tag where 4lane dp works? I'm willing to believe
>>>>> the PHY story..
>>>>
>>>> Just tested on Fairphone 5 downstream and 4 lane appears to work there.
>>>> This is with an USB-C to HDMI adapter that only does HDMI.
>>>>
>>>> FP5:/ # cat /sys/kernel/debug/drm_dp/dp_debug
>>>> state=0x20a5
>>>> link_rate=270000
>>>> num_lanes=4
>>>> resolution=2560x1440@60Hz
>>>> pclock=241500KHz
>>>> bpp=24
>>>> test_req=DP_LINK_STATUS_UPDATED
>>>> lane_count=4
>>>> bw_code=10
>>>> v_level=0
>>>> p_level=0
>>>>
>>>> Sources are here:
>>>> https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-5.4/+/refs/heads/odm/rc/target/13/fp5
>>>> And probably more importantly techpack/display:
>>>> https://gerrit-public.fairphone.software/plugins/gitiles/platform/vendor/opensource/display-drivers/+/refs/heads/odm/rc/target/13/fp5
>>>> Dts if useful:
>>>> https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/refs/heads/kernel/13/fp5
>>>
>>> Could you retry with this applied ?
>>>
>>> https://lore.kernel.org/all/20240405000111.1450598-1-swboyd@chromium.org/
>>
>> Unfortunately I do not see any change with this on QCM6490 Fairphone 5
>> and 4-lane DP.
>
> Hm, could you like dump all the PHY regions up and downstream with the display
> connected (and nothing connected) and compare them?
Yes would be great, PHY regions and DP regions as well.
Neil
>
> Konrad
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [relevance 0%]
* Re: [PATCH RFT 0/7] arm64: qcom: allow up to 4 lanes for the Type-C DisplayPort Altmode
@ 2024-04-23 14:08 0% ` neil.armstrong
0 siblings, 0 replies; 200+ results
From: neil.armstrong @ 2024-04-23 14:08 UTC (permalink / raw)
To: Konrad Dybcio, Luca Weiss, Bjorn Andersson
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Abhinav Kumar, linux-arm-msm,
linux-phy, devicetree, linux-kernel
On 23/04/2024 15:03, Konrad Dybcio wrote:
>
>
> On 4/5/24 12:19, Luca Weiss wrote:
>> On Fri Apr 5, 2024 at 10:08 AM CEST, Neil Armstrong wrote:
>>> Hi Luca,
>>>
>>> On 29/03/2024 10:02, Luca Weiss wrote:
>>>> On Tue Mar 26, 2024 at 10:02 PM CET, Konrad Dybcio wrote:
>>>>> On 16.03.2024 5:01 PM, Bjorn Andersson wrote:
>>>>>> On Fri, Mar 15, 2024 at 06:35:15PM +0100, Neil Armstrong wrote:
>>>>>>> On 15/03/2024 18:19, Luca Weiss wrote:
>>>>>>>> On Thu Feb 29, 2024 at 2:07 PM CET, Neil Armstrong wrote:
>>>>>>>>> Register a typec mux in order to change the PHY mode on the Type-C
>>>>>>>>> mux events depending on the mode and the svid when in Altmode setup.
>>>>>>>>>
>>>>>>>>> The DisplayPort phy should be left enabled if is still powered on
>>>>>>>>> by the DRM DisplayPort controller, so bail out until the DisplayPort
>>>>>>>>> PHY is not powered off.
>>>>>>>>>
>>>>>>>>> The Type-C Mode/SVID only changes on plug/unplug, and USB SAFE states
>>>>>>>>> will be set in between of USB-Only, Combo and DisplayPort Only so
>>>>>>>>> this will leave enough time to the DRM DisplayPort controller to
>>>>>>>>> turn of the DisplayPort PHY.
>>>>>>>>>
>>>>>>>>> The patchset also includes bindings changes and DT changes.
>>>>>>>>>
>>>>>>>>> This has been successfully tested on an SM8550 board, but the
>>>>>>>>> Thinkpad X13s deserved testing between non-PD USB, non-PD DisplayPort,
>>>>>>>>> PD USB Hubs and PD Altmode Dongles to make sure the switch works
>>>>>>>>> as expected.
>>>>>>>>>
>>>>>>>>> The DisplayPort 4 lanes setup can be check with:
>>>>>>>>> $ cat /sys/kernel/debug/dri/ae01000.display-controller/DP-1/dp_debug
>>>>>>>>> name = msm_dp
>>>>>>>>> drm_dp_link
>>>>>>>>> rate = 540000
>>>>>>>>> num_lanes = 4
>>>>>>>>
>>>>>>>> Hi Neil,
>>>>>>>>
>>>>>>>> I tried this on QCM6490/SC7280 which should also support 4-lane DP but I
>>>>>>>> haven't had any success so far.
>>>>>>>>
>>>>>> [..]
>>>>>>>> [ 1775.563969] [drm:dp_ctrl_link_train] *ERROR* max v_level reached
>>>>>>>> [ 1775.564031] [drm:dp_ctrl_link_train] *ERROR* link training #1 failed. ret=-11
>>>>>>>
>>>>>>> Interesting #1 means the 4 lanes are not physically connected to the other side,
>>>>>>> perhaps QCM6490/SC7280 requires a specific way to enable the 4 lanes in the PHY,
>>>>>>> or some fixups in the init tables.
>>>>>>>
>>>>>>
>>>>>> I tested the same on rb3gen2 (qcs6490) a couple of weeks ago, with the
>>>>>> same outcome. Looking at the AUX reads, after switching to 4-lane the
>>>>>> link training is failing on all 4 lanes, in contrast to succeeding only
>>>>>> on the first 2 if you e.g. forget to mux the other two.
>>>>>>
>>>>>> As such, my expectation is that there's something wrong in the QMP PHY
>>>>>> (or possibly redriver) for this platform.
>>>>>
>>>>> Do we have any downstream tag where 4lane dp works? I'm willing to believe
>>>>> the PHY story..
>>>>
>>>> Just tested on Fairphone 5 downstream and 4 lane appears to work there.
>>>> This is with an USB-C to HDMI adapter that only does HDMI.
>>>>
>>>> FP5:/ # cat /sys/kernel/debug/drm_dp/dp_debug
>>>> state=0x20a5
>>>> link_rate=270000
>>>> num_lanes=4
>>>> resolution=2560x1440@60Hz
>>>> pclock=241500KHz
>>>> bpp=24
>>>> test_req=DP_LINK_STATUS_UPDATED
>>>> lane_count=4
>>>> bw_code=10
>>>> v_level=0
>>>> p_level=0
>>>>
>>>> Sources are here:
>>>> https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-5.4/+/refs/heads/odm/rc/target/13/fp5
>>>> And probably more importantly techpack/display:
>>>> https://gerrit-public.fairphone.software/plugins/gitiles/platform/vendor/opensource/display-drivers/+/refs/heads/odm/rc/target/13/fp5
>>>> Dts if useful:
>>>> https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/refs/heads/kernel/13/fp5
>>>
>>> Could you retry with this applied ?
>>>
>>> https://lore.kernel.org/all/20240405000111.1450598-1-swboyd@chromium.org/
>>
>> Unfortunately I do not see any change with this on QCM6490 Fairphone 5
>> and 4-lane DP.
>
> Hm, could you like dump all the PHY regions up and downstream with the display
> connected (and nothing connected) and compare them?
Yes would be great, PHY regions and DP regions as well.
Neil
>
> Konrad
^ permalink raw reply [relevance 0%]
* [PULL] Please pull qcom/qcom-main
@ 2024-04-23 13:46 6% Caleb Connolly
2024-04-23 21:22 0% ` Tom Rini
0 siblings, 1 reply; 200+ results
From: Caleb Connolly @ 2024-04-23 13:46 UTC (permalink / raw)
To: Tom Rini
Cc: Neil Armstrong, Robert Marko, Sumit Garg, u-boot-qcom, u-boot,
Caleb Connolly
Overshot the -rc1 deadline, but I hope these can still make in for 2024.07.
Support is added for 5 new Qualcomm SoCs:
* QCM2290 and SM6115 are low and mid range SoCs used on the RB1 and RB2
respectively. SM6115 is also used in some mid-range smartphones/tablets.
Initial support includes buttons and USB (host and gadget).
* SM8250 is a flagship SoC from 2020 used on the RB5, as well as many flagship
smartphones. The board can boot to a U-Boot prompt, but is missing regulators
necessary for USB support.
* SM8550, and SM8650 are flagship mobile SoCs from 2023 and 2024
respectively. Found on many high end smartphones.
In addition:
* Support is added for the Schneider HMIBSC board.
* mach-snapdragon switches to OF_UPSTREAM
* IPQ40xx gets several regressions fixed and some overall cleanup.
* The MSM serial driver gains the ability to generate the bit-clock
automatically, no longer relying on a custom DT property.
* The Qualcomm SMMU driver gets a generic compatible (so per-SoC compatibles
don't need to be added).
* Support for the GENI I2C controller is added.
* The qcom SPMI driver has SPMI v5 support fixed, and v7 support added.
* The qcom sdhci driver gets some fixes for SDCC v5 support.
* SDM845 gains sdcard support
* Support is added for the Synopsys eUSB2 PHY driver (used on SM8550 and SM8650)
* SYS_INIT_SP_BSS_OFFSET is set to 1.5M to give us more space for FDTs.
* RB2 gets a work-around to fix the USB dr_mode property before booting Linux.
---
The following changes since commit 38ea74d6d5c05224acdb03f799897c1bdd56f8cc:
Prepare v2024.07-rc1 (2024-04-22 15:10:21 -0600)
are available in the Git repository at:
git@source.denx.de:u-boot/custodians/u-boot-snapdragon.git qcom-main
for you to fetch changes up to ad12acd7a8f5aeea5816d5c2fc37c205c403eee0:
configs: qcom_defconfig: enable GENI I2C Driver (2024-04-23 13:29:32 +0200)
----------------------------------------------------------------
Caleb Connolly (32):
pinctrl: qcom: add qcm2290 pinctrl driver
pinctrl: qcom: add sm6115 pinctrl driver
pinctrl: qcom: add sm8250 pinctrl driver
qcom_defconfig: enable pinctrl for new qcm2290/sm6115/sm8250
clk/qcom: add driver for qcm2290 GCC
clk/qcom: add driver for sm6115 GCC
clk/qcom: add driver for sm8250 GCC
qcom_defconfig: enable clocks for qcm2290/sm6115/sm8250
mmc: msm_sdhci: correct vendor_spec_cap0 register for v5
mmc: msm_sdhci: use modern DT handling
mmc: msm_sdhci: print core version
mmc: msm_sdhci: use a more sensible default clock rate
clk/qcom: sdm845: enable SDCC2 core clock
pinctrl: qcom: sdm845: add special pin names
dts: sdm845-db845c-u-boot: adjust MMC clocks
MAINTAINERS: add Qualcomm mailing list
mmc: msm_sdhci: fix vendor_spec_cap0 registers
clk/qcom: apq8016: return valid rate when setting UART clock
clk/qcom: ipq4019: return valid rate when setting UART clock
serial: msm: calculate bit clock divider
mach-snapdragon: use OF_UPSTREAM
arm: dts: drop qcom dts files
qcom_defconfig: set SYS_INIT_SP_BSS_OFFSET
gpio: qcom_pmic: add pm6125
gpio: qcom_pmic: add pm8150l
iommu: qcom-smmu: add qcom generic compatible
phy: qcom: snps-femto-v2: drop clocks
arm: dts: qrb4210-rb2-u-boot: add u-boot fixups
mach-snapdragon: implement ft_board_setup() for USB role selection
qcom_defconfig: enable OF_BOARD_SETUP
qcom_defconfig: define safe default SYS_LOAD_ADDR
qcom_defconfig: generate SMBIOS tables
Neil Armstrong (17):
phy: qcom: add Synopsys eUSB2 PHY driver
qcom_defconfig: enable the Qualcomm Synopsys eUSB2 PHY driver
pinctrl: qcom: Add SM8550 pinctrl driver
pinctrl: qcom: Add SM8650 pinctrl driver
qcom_defconfig: enable SM8550 & SM8650 pinctrl driver
gpio: qcom_pmic_gpio: add support for pm8550-gpio
button: qcom-pmic: move node name checks to btn_data struct
button: qcom-pmic: add support for pmk8350 button configs
clk: qcom: Add SM8550 clock driver
clk: qcom: Add SM8650 clock driver
qcom_defconfig: enable SM8550 & SM8650 clock driver
spmi: msm: fix version 5 support
spmi: msm: properly format command
spmi: msm: handle peripheral ownership
spmi: msm: support controller version 7
i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller
configs: qcom_defconfig: enable GENI I2C Driver
Robert Marko (8):
serial: allow selecting MSM debug UART with ARCH_IPQ40XX
serial: msm_serial: remove .clk_rate from debug UART
arm: mach-ipq40xx: dont select SMEM by default
pinctrl: qcom: allow selecting with ARCH_IPQ40XX
mach-ipq40xx: import GPIO header from mach-snapgradon
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC
pinctrl: qcom: ipq4019: support all pin functions
Sumit Garg (8):
mach-snapdragon: Allow other board vendors apart from Qcom
qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default
apq8016: Add support for UART1 clocks and pinmux
serial_msm: Enable RS232 flow control
pinctrl: qcom: Add support for driving GPIO pins output
pinctrl: qcom: apq8016: Add GPIO pinctrl function
arm: dts: qcom: Add Schneider HMIBSC board dts
board: add support for Schneider HMIBSC board
MAINTAINERS | 6 +-
arch/arm/Kconfig | 5 +-
arch/arm/dts/Makefile | 6 -
...pq8016-sbc.dts => apq8016-schneider-hmibsc.dts} | 706 +--
arch/arm/dts/apq8096-db820c.dts | 1137 ----
arch/arm/dts/msm8916-pm8916.dtsi | 157 -
arch/arm/dts/msm8916.dtsi | 2702 ---------
arch/arm/dts/msm8996.dtsi | 3884 -------------
arch/arm/dts/pm8916.dtsi | 178 -
arch/arm/dts/pm8994.dtsi | 152 -
arch/arm/dts/pm8998.dtsi | 130 -
arch/arm/dts/pmi8994.dtsi | 65 -
arch/arm/dts/pmi8998.dtsi | 98 -
arch/arm/dts/pms405.dtsi | 149 -
arch/arm/dts/qcs404-evb-4000.dts | 96 -
arch/arm/dts/qcs404-evb.dtsi | 389 --
arch/arm/dts/qcs404.dtsi | 1829 -------
arch/arm/dts/qrb4210-rb2-u-boot.dtsi | 6 +
arch/arm/dts/sdm845-db845c-u-boot.dtsi | 7 +
arch/arm/dts/sdm845-db845c.dts | 1190 ----
arch/arm/dts/sdm845-samsung-starqltechn.dts | 460 --
arch/arm/dts/sdm845-wcd9340.dtsi | 86 -
arch/arm/dts/sdm845.dtsi | 5752 --------------------
arch/arm/mach-ipq40xx/include/mach/gpio.h | 37 +-
arch/arm/mach-snapdragon/Kconfig | 14 +-
arch/arm/mach-snapdragon/of_fixup.c | 20 +
board/schneider/hmibsc/MAINTAINERS | 6 +
board/schneider/hmibsc/hmibsc.env | 40 +
configs/dragonboard410c_defconfig | 2 +-
configs/dragonboard820c_defconfig | 2 +-
configs/hmibsc_defconfig | 87 +
configs/qcom_defconfig | 20 +-
doc/board/index.rst | 1 +
doc/board/schneider/hmibsc.rst | 45 +
doc/board/schneider/index.rst | 9 +
doc/device-tree-bindings/serial/msm-serial.txt | 10 -
drivers/button/button-qcom-pmic.c | 99 +-
drivers/clk/qcom/Kconfig | 39 +
drivers/clk/qcom/Makefile | 5 +
drivers/clk/qcom/clock-apq8016.c | 39 +-
drivers/clk/qcom/clock-ipq4019.c | 2 +-
drivers/clk/qcom/clock-qcm2290.c | 192 +
drivers/clk/qcom/clock-qcom.h | 5 +
drivers/clk/qcom/clock-sdm845.c | 17 +
drivers/clk/qcom/clock-sm6115.c | 199 +
drivers/clk/qcom/clock-sm8250.c | 282 +
drivers/clk/qcom/clock-sm8550.c | 335 ++
drivers/clk/qcom/clock-sm8650.c | 332 ++
drivers/gpio/qcom_pmic_gpio.c | 20 +-
drivers/i2c/Kconfig | 10 +
drivers/i2c/Makefile | 1 +
drivers/i2c/geni_i2c.c | 575 ++
drivers/iommu/qcom-hyp-smmu.c | 1 +
drivers/mmc/msm_sdhci.c | 43 +-
drivers/phy/qcom/Kconfig | 8 +
drivers/phy/qcom/Makefile | 1 +
drivers/phy/qcom/phy-qcom-snps-eusb2.c | 366 ++
drivers/phy/qcom/phy-qcom-snps-femto-v2.c | 14 -
drivers/pinctrl/qcom/Kconfig | 36 +-
drivers/pinctrl/qcom/Makefile | 5 +
drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 +
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 311 +-
drivers/pinctrl/qcom/pinctrl-qcm2290.c | 70 +
drivers/pinctrl/qcom/pinctrl-qcom.c | 25 +-
drivers/pinctrl/qcom/pinctrl-sdm845.c | 13 +-
drivers/pinctrl/qcom/pinctrl-sm6115.c | 200 +
drivers/pinctrl/qcom/pinctrl-sm8250.c | 99 +
drivers/pinctrl/qcom/pinctrl-sm8550.c | 75 +
drivers/pinctrl/qcom/pinctrl-sm8650.c | 75 +
drivers/serial/Kconfig | 2 +-
drivers/serial/serial_msm.c | 109 +-
drivers/spmi/spmi-msm.c | 152 +-
include/configs/hmibsc.h | 16 +
include/soc/qcom/geni-se.h | 265 +
74 files changed, 4405 insertions(+), 19118 deletions(-)
rename arch/arm/dts/{apq8016-sbc.dts => apq8016-schneider-hmibsc.dts} (50%)
delete mode 100644 arch/arm/dts/apq8096-db820c.dts
delete mode 100644 arch/arm/dts/msm8916-pm8916.dtsi
delete mode 100644 arch/arm/dts/msm8916.dtsi
delete mode 100644 arch/arm/dts/msm8996.dtsi
delete mode 100644 arch/arm/dts/pm8916.dtsi
delete mode 100644 arch/arm/dts/pm8994.dtsi
delete mode 100644 arch/arm/dts/pm8998.dtsi
delete mode 100644 arch/arm/dts/pmi8994.dtsi
delete mode 100644 arch/arm/dts/pmi8998.dtsi
delete mode 100644 arch/arm/dts/pms405.dtsi
delete mode 100644 arch/arm/dts/qcs404-evb-4000.dts
delete mode 100644 arch/arm/dts/qcs404-evb.dtsi
delete mode 100644 arch/arm/dts/qcs404.dtsi
create mode 100644 arch/arm/dts/qrb4210-rb2-u-boot.dtsi
delete mode 100644 arch/arm/dts/sdm845-db845c.dts
delete mode 100644 arch/arm/dts/sdm845-samsung-starqltechn.dts
delete mode 100644 arch/arm/dts/sdm845-wcd9340.dtsi
delete mode 100644 arch/arm/dts/sdm845.dtsi
create mode 100644 board/schneider/hmibsc/MAINTAINERS
create mode 100644 board/schneider/hmibsc/hmibsc.env
create mode 100644 configs/hmibsc_defconfig
create mode 100644 doc/board/schneider/hmibsc.rst
create mode 100644 doc/board/schneider/index.rst
delete mode 100644 doc/device-tree-bindings/serial/msm-serial.txt
create mode 100644 drivers/clk/qcom/clock-qcm2290.c
create mode 100644 drivers/clk/qcom/clock-sm6115.c
create mode 100644 drivers/clk/qcom/clock-sm8250.c
create mode 100644 drivers/clk/qcom/clock-sm8550.c
create mode 100644 drivers/clk/qcom/clock-sm8650.c
create mode 100644 drivers/i2c/geni_i2c.c
create mode 100644 drivers/phy/qcom/phy-qcom-snps-eusb2.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-qcm2290.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-sm6115.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8550.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8650.c
create mode 100644 include/configs/hmibsc.h
create mode 100644 include/soc/qcom/geni-se.h
^ permalink raw reply [relevance 6%]
* Re: [PATCH RFT 0/7] arm64: qcom: allow up to 4 lanes for the Type-C DisplayPort Altmode
@ 2024-04-23 13:03 0% ` Konrad Dybcio
0 siblings, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-04-23 13:03 UTC (permalink / raw)
To: Luca Weiss, neil.armstrong, Bjorn Andersson
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Abhinav Kumar, linux-arm-msm,
linux-phy, devicetree, linux-kernel
On 4/5/24 12:19, Luca Weiss wrote:
> On Fri Apr 5, 2024 at 10:08 AM CEST, Neil Armstrong wrote:
>> Hi Luca,
>>
>> On 29/03/2024 10:02, Luca Weiss wrote:
>>> On Tue Mar 26, 2024 at 10:02 PM CET, Konrad Dybcio wrote:
>>>> On 16.03.2024 5:01 PM, Bjorn Andersson wrote:
>>>>> On Fri, Mar 15, 2024 at 06:35:15PM +0100, Neil Armstrong wrote:
>>>>>> On 15/03/2024 18:19, Luca Weiss wrote:
>>>>>>> On Thu Feb 29, 2024 at 2:07 PM CET, Neil Armstrong wrote:
>>>>>>>> Register a typec mux in order to change the PHY mode on the Type-C
>>>>>>>> mux events depending on the mode and the svid when in Altmode setup.
>>>>>>>>
>>>>>>>> The DisplayPort phy should be left enabled if is still powered on
>>>>>>>> by the DRM DisplayPort controller, so bail out until the DisplayPort
>>>>>>>> PHY is not powered off.
>>>>>>>>
>>>>>>>> The Type-C Mode/SVID only changes on plug/unplug, and USB SAFE states
>>>>>>>> will be set in between of USB-Only, Combo and DisplayPort Only so
>>>>>>>> this will leave enough time to the DRM DisplayPort controller to
>>>>>>>> turn of the DisplayPort PHY.
>>>>>>>>
>>>>>>>> The patchset also includes bindings changes and DT changes.
>>>>>>>>
>>>>>>>> This has been successfully tested on an SM8550 board, but the
>>>>>>>> Thinkpad X13s deserved testing between non-PD USB, non-PD DisplayPort,
>>>>>>>> PD USB Hubs and PD Altmode Dongles to make sure the switch works
>>>>>>>> as expected.
>>>>>>>>
>>>>>>>> The DisplayPort 4 lanes setup can be check with:
>>>>>>>> $ cat /sys/kernel/debug/dri/ae01000.display-controller/DP-1/dp_debug
>>>>>>>> name = msm_dp
>>>>>>>> drm_dp_link
>>>>>>>> rate = 540000
>>>>>>>> num_lanes = 4
>>>>>>>
>>>>>>> Hi Neil,
>>>>>>>
>>>>>>> I tried this on QCM6490/SC7280 which should also support 4-lane DP but I
>>>>>>> haven't had any success so far.
>>>>>>>
>>>>> [..]
>>>>>>> [ 1775.563969] [drm:dp_ctrl_link_train] *ERROR* max v_level reached
>>>>>>> [ 1775.564031] [drm:dp_ctrl_link_train] *ERROR* link training #1 failed. ret=-11
>>>>>>
>>>>>> Interesting #1 means the 4 lanes are not physically connected to the other side,
>>>>>> perhaps QCM6490/SC7280 requires a specific way to enable the 4 lanes in the PHY,
>>>>>> or some fixups in the init tables.
>>>>>>
>>>>>
>>>>> I tested the same on rb3gen2 (qcs6490) a couple of weeks ago, with the
>>>>> same outcome. Looking at the AUX reads, after switching to 4-lane the
>>>>> link training is failing on all 4 lanes, in contrast to succeeding only
>>>>> on the first 2 if you e.g. forget to mux the other two.
>>>>>
>>>>> As such, my expectation is that there's something wrong in the QMP PHY
>>>>> (or possibly redriver) for this platform.
>>>>
>>>> Do we have any downstream tag where 4lane dp works? I'm willing to believe
>>>> the PHY story..
>>>
>>> Just tested on Fairphone 5 downstream and 4 lane appears to work there.
>>> This is with an USB-C to HDMI adapter that only does HDMI.
>>>
>>> FP5:/ # cat /sys/kernel/debug/drm_dp/dp_debug
>>> state=0x20a5
>>> link_rate=270000
>>> num_lanes=4
>>> resolution=2560x1440@60Hz
>>> pclock=241500KHz
>>> bpp=24
>>> test_req=DP_LINK_STATUS_UPDATED
>>> lane_count=4
>>> bw_code=10
>>> v_level=0
>>> p_level=0
>>>
>>> Sources are here:
>>> https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-5.4/+/refs/heads/odm/rc/target/13/fp5
>>> And probably more importantly techpack/display:
>>> https://gerrit-public.fairphone.software/plugins/gitiles/platform/vendor/opensource/display-drivers/+/refs/heads/odm/rc/target/13/fp5
>>> Dts if useful:
>>> https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/refs/heads/kernel/13/fp5
>>
>> Could you retry with this applied ?
>>
>> https://lore.kernel.org/all/20240405000111.1450598-1-swboyd@chromium.org/
>
> Unfortunately I do not see any change with this on QCM6490 Fairphone 5
> and 4-lane DP.
Hm, could you like dump all the PHY regions up and downstream with the display
connected (and nothing connected) and compare them?
Konrad
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [relevance 0%]
* Re: [PATCH RFT 0/7] arm64: qcom: allow up to 4 lanes for the Type-C DisplayPort Altmode
@ 2024-04-23 13:03 0% ` Konrad Dybcio
0 siblings, 0 replies; 200+ results
From: Konrad Dybcio @ 2024-04-23 13:03 UTC (permalink / raw)
To: Luca Weiss, neil.armstrong, Bjorn Andersson
Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Abhinav Kumar, linux-arm-msm,
linux-phy, devicetree, linux-kernel
On 4/5/24 12:19, Luca Weiss wrote:
> On Fri Apr 5, 2024 at 10:08 AM CEST, Neil Armstrong wrote:
>> Hi Luca,
>>
>> On 29/03/2024 10:02, Luca Weiss wrote:
>>> On Tue Mar 26, 2024 at 10:02 PM CET, Konrad Dybcio wrote:
>>>> On 16.03.2024 5:01 PM, Bjorn Andersson wrote:
>>>>> On Fri, Mar 15, 2024 at 06:35:15PM +0100, Neil Armstrong wrote:
>>>>>> On 15/03/2024 18:19, Luca Weiss wrote:
>>>>>>> On Thu Feb 29, 2024 at 2:07 PM CET, Neil Armstrong wrote:
>>>>>>>> Register a typec mux in order to change the PHY mode on the Type-C
>>>>>>>> mux events depending on the mode and the svid when in Altmode setup.
>>>>>>>>
>>>>>>>> The DisplayPort phy should be left enabled if is still powered on
>>>>>>>> by the DRM DisplayPort controller, so bail out until the DisplayPort
>>>>>>>> PHY is not powered off.
>>>>>>>>
>>>>>>>> The Type-C Mode/SVID only changes on plug/unplug, and USB SAFE states
>>>>>>>> will be set in between of USB-Only, Combo and DisplayPort Only so
>>>>>>>> this will leave enough time to the DRM DisplayPort controller to
>>>>>>>> turn of the DisplayPort PHY.
>>>>>>>>
>>>>>>>> The patchset also includes bindings changes and DT changes.
>>>>>>>>
>>>>>>>> This has been successfully tested on an SM8550 board, but the
>>>>>>>> Thinkpad X13s deserved testing between non-PD USB, non-PD DisplayPort,
>>>>>>>> PD USB Hubs and PD Altmode Dongles to make sure the switch works
>>>>>>>> as expected.
>>>>>>>>
>>>>>>>> The DisplayPort 4 lanes setup can be check with:
>>>>>>>> $ cat /sys/kernel/debug/dri/ae01000.display-controller/DP-1/dp_debug
>>>>>>>> name = msm_dp
>>>>>>>> drm_dp_link
>>>>>>>> rate = 540000
>>>>>>>> num_lanes = 4
>>>>>>>
>>>>>>> Hi Neil,
>>>>>>>
>>>>>>> I tried this on QCM6490/SC7280 which should also support 4-lane DP but I
>>>>>>> haven't had any success so far.
>>>>>>>
>>>>> [..]
>>>>>>> [ 1775.563969] [drm:dp_ctrl_link_train] *ERROR* max v_level reached
>>>>>>> [ 1775.564031] [drm:dp_ctrl_link_train] *ERROR* link training #1 failed. ret=-11
>>>>>>
>>>>>> Interesting #1 means the 4 lanes are not physically connected to the other side,
>>>>>> perhaps QCM6490/SC7280 requires a specific way to enable the 4 lanes in the PHY,
>>>>>> or some fixups in the init tables.
>>>>>>
>>>>>
>>>>> I tested the same on rb3gen2 (qcs6490) a couple of weeks ago, with the
>>>>> same outcome. Looking at the AUX reads, after switching to 4-lane the
>>>>> link training is failing on all 4 lanes, in contrast to succeeding only
>>>>> on the first 2 if you e.g. forget to mux the other two.
>>>>>
>>>>> As such, my expectation is that there's something wrong in the QMP PHY
>>>>> (or possibly redriver) for this platform.
>>>>
>>>> Do we have any downstream tag where 4lane dp works? I'm willing to believe
>>>> the PHY story..
>>>
>>> Just tested on Fairphone 5 downstream and 4 lane appears to work there.
>>> This is with an USB-C to HDMI adapter that only does HDMI.
>>>
>>> FP5:/ # cat /sys/kernel/debug/drm_dp/dp_debug
>>> state=0x20a5
>>> link_rate=270000
>>> num_lanes=4
>>> resolution=2560x1440@60Hz
>>> pclock=241500KHz
>>> bpp=24
>>> test_req=DP_LINK_STATUS_UPDATED
>>> lane_count=4
>>> bw_code=10
>>> v_level=0
>>> p_level=0
>>>
>>> Sources are here:
>>> https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-5.4/+/refs/heads/odm/rc/target/13/fp5
>>> And probably more importantly techpack/display:
>>> https://gerrit-public.fairphone.software/plugins/gitiles/platform/vendor/opensource/display-drivers/+/refs/heads/odm/rc/target/13/fp5
>>> Dts if useful:
>>> https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/refs/heads/kernel/13/fp5
>>
>> Could you retry with this applied ?
>>
>> https://lore.kernel.org/all/20240405000111.1450598-1-swboyd@chromium.org/
>
> Unfortunately I do not see any change with this on QCM6490 Fairphone 5
> and 4-lane DP.
Hm, could you like dump all the PHY regions up and downstream with the display
connected (and nothing connected) and compare them?
Konrad
^ permalink raw reply [relevance 0%]
* [PATCH v4 2/3] arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
2024-04-22 16:16 7% ` Neil Armstrong
@ 2024-04-22 16:16 19% ` Neil Armstrong
-1 siblings, 0 replies; 200+ results
From: Neil Armstrong @ 2024-04-22 16:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Neil Armstrong, Dmitry Baryshkov
Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy
provided QMP_PCIE_PHY_AUX_CLK.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 19 -------------------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
4 files changed, 4 insertions(+), 36 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 12d60a0ee095..ccff744dcd14 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -979,10 +979,6 @@ &pcie1_phy {
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 3d4ad5aac70f..1fa7c4492057 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -739,10 +739,6 @@ &mdss_dp0_out {
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 92f015017418..39ba3e9969b7 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -720,17 +720,6 @@ &ipa {
status = "okay";
};
-&gcc {
- clocks = <&bi_tcxo_div2>, <&sleep_clk>,
- <&pcie0_phy>,
- <&pcie1_phy>,
- <0>,
- <&ufs_mem_phy 0>,
- <&ufs_mem_phy 1>,
- <&ufs_mem_phy 2>,
- <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
-};
-
&gpi_dma1 {
status = "okay";
};
@@ -810,10 +799,6 @@ &mdss_dp0_out {
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
-&pcie_1_phy_aux_clk {
- status = "disabled";
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
@@ -907,10 +892,6 @@ &pon_resin {
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&qupv3_id_0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index bc5aeb05ffc3..143994d1e6ca 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -58,11 +58,6 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-mult = <1>;
clock-div = <2>;
};
-
- pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
};
cpus {
@@ -776,8 +771,8 @@ gcc: clock-controller@100000 {
#power-domain-cells = <1>;
clocks = <&bi_tcxo_div2>, <&sleep_clk>,
<&pcie0_phy>,
- <&pcie1_phy>,
- <&pcie_1_phy_aux_clk>,
+ <&pcie1_phy QMP_PCIE_PIPE_CLK>,
+ <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
@@ -1928,8 +1923,8 @@ pcie1_phy: phy@1c0e000 {
power-domains = <&gcc PCIE_1_PHY_GDSC>;
- #clock-cells = <0>;
- clock-output-names = "pcie1_pipe_clk";
+ #clock-cells = <1>;
+ clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";
#phy-cells = <0>;
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [relevance 19%]
* [PATCH v4 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock
@ 2024-04-22 16:16 7% ` Neil Armstrong
0 siblings, 0 replies; 200+ results
From: Neil Armstrong @ 2024-04-22 16:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Neil Armstrong, Dmitry Baryshkov
The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.
Document the clock IDs to select the PIPE clock or the AUX clock,
also enforce a second clock-output-names and a #clock-cells value of 1
for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
The PHY driver needs a light refactoring to support a second clock,
and finally the DT is changed to connect the PHY second clock to the
corresponding GCC input then drop the dummy fixed rate clock.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v4:
- Fixed dtbs check error on sm8550-qrd.dtb after rebase on -next
- Link to v3: https://lore.kernel.org/r/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org
Changes in v3:
- Rebased on linux-next, applies now cleanly
- Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org
Changes in v2:
- Collected review tags
- Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility
- Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code
and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0
when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get()
- Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org
---
Neil Armstrong (3):
arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 19 -------------------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++---------
8 files changed, 12 insertions(+), 57 deletions(-)
---
base-commit: f529a6d274b3b8c75899e949649d231298f30a32
change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [relevance 7%]
* [PATCH v4 2/3] arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
@ 2024-04-22 16:16 19% ` Neil Armstrong
0 siblings, 0 replies; 200+ results
From: Neil Armstrong @ 2024-04-22 16:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Neil Armstrong, Dmitry Baryshkov
Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy
provided QMP_PCIE_PHY_AUX_CLK.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 19 -------------------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
4 files changed, 4 insertions(+), 36 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 12d60a0ee095..ccff744dcd14 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -979,10 +979,6 @@ &pcie1_phy {
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 3d4ad5aac70f..1fa7c4492057 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -739,10 +739,6 @@ &mdss_dp0_out {
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 92f015017418..39ba3e9969b7 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -720,17 +720,6 @@ &ipa {
status = "okay";
};
-&gcc {
- clocks = <&bi_tcxo_div2>, <&sleep_clk>,
- <&pcie0_phy>,
- <&pcie1_phy>,
- <0>,
- <&ufs_mem_phy 0>,
- <&ufs_mem_phy 1>,
- <&ufs_mem_phy 2>,
- <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
-};
-
&gpi_dma1 {
status = "okay";
};
@@ -810,10 +799,6 @@ &mdss_dp0_out {
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
-&pcie_1_phy_aux_clk {
- status = "disabled";
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
@@ -907,10 +892,6 @@ &pon_resin {
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&qupv3_id_0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index bc5aeb05ffc3..143994d1e6ca 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -58,11 +58,6 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-mult = <1>;
clock-div = <2>;
};
-
- pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
};
cpus {
@@ -776,8 +771,8 @@ gcc: clock-controller@100000 {
#power-domain-cells = <1>;
clocks = <&bi_tcxo_div2>, <&sleep_clk>,
<&pcie0_phy>,
- <&pcie1_phy>,
- <&pcie_1_phy_aux_clk>,
+ <&pcie1_phy QMP_PCIE_PIPE_CLK>,
+ <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
@@ -1928,8 +1923,8 @@ pcie1_phy: phy@1c0e000 {
power-domains = <&gcc PCIE_1_PHY_GDSC>;
- #clock-cells = <0>;
- clock-output-names = "pcie1_pipe_clk";
+ #clock-cells = <1>;
+ clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";
#phy-cells = <0>;
--
2.34.1
^ permalink raw reply related [relevance 19%]
* [PATCH v4 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock
@ 2024-04-22 16:16 7% ` Neil Armstrong
0 siblings, 0 replies; 200+ results
From: Neil Armstrong @ 2024-04-22 16:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Neil Armstrong, Dmitry Baryshkov
The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.
Document the clock IDs to select the PIPE clock or the AUX clock,
also enforce a second clock-output-names and a #clock-cells value of 1
for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
The PHY driver needs a light refactoring to support a second clock,
and finally the DT is changed to connect the PHY second clock to the
corresponding GCC input then drop the dummy fixed rate clock.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v4:
- Fixed dtbs check error on sm8550-qrd.dtb after rebase on -next
- Link to v3: https://lore.kernel.org/r/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org
Changes in v3:
- Rebased on linux-next, applies now cleanly
- Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org
Changes in v2:
- Collected review tags
- Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility
- Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code
and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0
when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get()
- Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org
---
Neil Armstrong (3):
arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 19 -------------------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++---------
8 files changed, 12 insertions(+), 57 deletions(-)
---
base-commit: f529a6d274b3b8c75899e949649d231298f30a32
change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [relevance 7%]
* Re: [PATCH v3 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock
2024-04-22 11:50 7% ` Rob Herring
@ 2024-04-22 16:07 0% ` Neil Armstrong
-1 siblings, 0 replies; 200+ results
From: Neil Armstrong @ 2024-04-22 16:07 UTC (permalink / raw)
To: Rob Herring
Cc: Conor Dooley, Vinod Koul, devicetree, Krzysztof Kozlowski,
linux-kernel, linux-phy, linux-arm-msm, Bjorn Andersson,
Krzysztof Kozlowski, Dmitry Baryshkov, Konrad Dybcio,
Kishon Vijay Abraham I
On 22/04/2024 13:50, Rob Herring wrote:
>
> On Mon, 22 Apr 2024 10:33:10 +0200, Neil Armstrong wrote:
>> The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
>> "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
>> is muxed & gated then returned to the PHY as an input.
>>
>> Document the clock IDs to select the PIPE clock or the AUX clock,
>> also enforce a second clock-output-names and a #clock-cells value of 1
>> for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
>>
>> The PHY driver needs a light refactoring to support a second clock,
>> and finally the DT is changed to connect the PHY second clock to the
>> corresponding GCC input then drop the dummy fixed rate clock.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> Changes in v3:
>> - Rebased on linux-next, applies now cleanly
>> - Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org
>>
>> Changes in v2:
>> - Collected review tags
>> - Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility
>> - Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code
>> and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0
>> when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get()
>> - Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org
>>
>> ---
>> Neil Armstrong (3):
>> arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
>> arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
>> arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
>>
>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
>> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
>> arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
>> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 --------
>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
>> arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ----
>> arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ----
>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++---------
>> 8 files changed, 12 insertions(+), 46 deletions(-)
>> ---
>> base-commit: f529a6d274b3b8c75899e949649d231298f30a32
>> change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
>>
>> Best regards,
>> --
>> Neil Armstrong <neil.armstrong@linaro.org>
>>
>>
>>
>
>
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
>
> Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> are fixed by another series. Ultimately, it is up to the platform
> maintainer whether these warnings are acceptable or not. No need to reply
> unless the platform maintainer has comments.
>
> If you already ran DT checks and didn't see these error(s), then
> make sure dt-schema is up to date:
>
> pip3 install dtschema --upgrade
>
>
> New warnings running 'make CHECK_DTBS=y qcom/sm8550-hdk.dtb qcom/sm8550-mtp.dtb qcom/sm8550-qrd.dtb qcom/sm8650-mtp.dtb qcom/sm8650-qrd.dtb' for 20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org:
>
> arch/arm64/boot/dts/qcom/sm8550-qrd.dtb: clock-controller@100000: clocks: [[41], [42], [43], [44, 0], [45, 0], [45, 1], [45, 2], [46, 0]] is too short
> from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
> arch/arm64/boot/dts/qcom/sm8550-qrd.dtb: clock-controller@100000: Unevaluated properties are not allowed ('clocks' was unexpected)
> from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
>
Ok thx, I found out why, sending a v4 fixing that
Neil
>
>
>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock
@ 2024-04-22 16:07 0% ` Neil Armstrong
0 siblings, 0 replies; 200+ results
From: Neil Armstrong @ 2024-04-22 16:07 UTC (permalink / raw)
To: Rob Herring
Cc: Conor Dooley, Vinod Koul, devicetree, Krzysztof Kozlowski,
linux-kernel, linux-phy, linux-arm-msm, Bjorn Andersson,
Krzysztof Kozlowski, Dmitry Baryshkov, Konrad Dybcio,
Kishon Vijay Abraham I
On 22/04/2024 13:50, Rob Herring wrote:
>
> On Mon, 22 Apr 2024 10:33:10 +0200, Neil Armstrong wrote:
>> The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
>> "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
>> is muxed & gated then returned to the PHY as an input.
>>
>> Document the clock IDs to select the PIPE clock or the AUX clock,
>> also enforce a second clock-output-names and a #clock-cells value of 1
>> for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
>>
>> The PHY driver needs a light refactoring to support a second clock,
>> and finally the DT is changed to connect the PHY second clock to the
>> corresponding GCC input then drop the dummy fixed rate clock.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> Changes in v3:
>> - Rebased on linux-next, applies now cleanly
>> - Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org
>>
>> Changes in v2:
>> - Collected review tags
>> - Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility
>> - Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code
>> and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0
>> when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get()
>> - Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org
>>
>> ---
>> Neil Armstrong (3):
>> arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
>> arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
>> arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
>>
>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
>> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
>> arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
>> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 --------
>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
>> arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ----
>> arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ----
>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++---------
>> 8 files changed, 12 insertions(+), 46 deletions(-)
>> ---
>> base-commit: f529a6d274b3b8c75899e949649d231298f30a32
>> change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
>>
>> Best regards,
>> --
>> Neil Armstrong <neil.armstrong@linaro.org>
>>
>>
>>
>
>
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
>
> Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> are fixed by another series. Ultimately, it is up to the platform
> maintainer whether these warnings are acceptable or not. No need to reply
> unless the platform maintainer has comments.
>
> If you already ran DT checks and didn't see these error(s), then
> make sure dt-schema is up to date:
>
> pip3 install dtschema --upgrade
>
>
> New warnings running 'make CHECK_DTBS=y qcom/sm8550-hdk.dtb qcom/sm8550-mtp.dtb qcom/sm8550-qrd.dtb qcom/sm8650-mtp.dtb qcom/sm8650-qrd.dtb' for 20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org:
>
> arch/arm64/boot/dts/qcom/sm8550-qrd.dtb: clock-controller@100000: clocks: [[41], [42], [43], [44, 0], [45, 0], [45, 1], [45, 2], [46, 0]] is too short
> from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
> arch/arm64/boot/dts/qcom/sm8550-qrd.dtb: clock-controller@100000: Unevaluated properties are not allowed ('clocks' was unexpected)
> from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
>
Ok thx, I found out why, sending a v4 fixing that
Neil
>
>
>
^ permalink raw reply [relevance 0%]
* Re: [PATCH] docs: driver-api: interconnect: fix typo
2024-04-22 4:29 5% [PATCH] docs: driver-api: interconnect: fix typo Sekhar Nori
@ 2024-04-22 14:53 0% ` Mike Tipton
0 siblings, 0 replies; 200+ results
From: Mike Tipton @ 2024-04-22 14:53 UTC (permalink / raw)
To: Sekhar Nori; +Cc: Georgi Djakov, Jonathan Corbet, linux-pm, linux-doc
On Mon, Apr 22, 2024 at 04:29:10AM +0000, Sekhar Nori wrote:
> Fix typo in debugfs path name that prevents copy-paste of
> commands given.
>
> Signed-off-by: Sekhar Nori <nsekhar@google.com>
> ---
> Documentation/driver-api/interconnect.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/driver-api/interconnect.rst b/Documentation/driver-api/interconnect.rst
> index a92d0f277a1f..6d0a205b42b7 100644
> --- a/Documentation/driver-api/interconnect.rst
> +++ b/Documentation/driver-api/interconnect.rst
> @@ -119,7 +119,7 @@ any arbitrary path. Note that for safety reasons, this feature is disabled by
> default without a Kconfig to enable it. Enabling it requires code changes to
> ``#define INTERCONNECT_ALLOW_WRITE_DEBUGFS``. Example usage::
>
> - cd /sys/kernel/debug/interconnect/test-client/
> + cd /sys/kernel/debug/interconnect/test_client/
>
> # Configure node endpoints for the path from CPU to DDR on
> # qcom/sm8550.
> --
> 2.44.0.769.g3c40516874-goog
>
Thanks Sekhar. Could you also fix the similar typo a few lines above at
the same time?
The ``test-client`` directory...
^
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock
2024-04-22 8:33 6% ` Neil Armstrong
@ 2024-04-22 11:50 7% ` Rob Herring
-1 siblings, 0 replies; 200+ results
From: Rob Herring @ 2024-04-22 11:50 UTC (permalink / raw)
To: Neil Armstrong
Cc: Conor Dooley, Vinod Koul, devicetree, Krzysztof Kozlowski,
linux-kernel, linux-phy, linux-arm-msm, Bjorn Andersson,
Krzysztof Kozlowski, Dmitry Baryshkov, Konrad Dybcio,
Kishon Vijay Abraham I
On Mon, 22 Apr 2024 10:33:10 +0200, Neil Armstrong wrote:
> The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
> "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
> is muxed & gated then returned to the PHY as an input.
>
> Document the clock IDs to select the PIPE clock or the AUX clock,
> also enforce a second clock-output-names and a #clock-cells value of 1
> for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
>
> The PHY driver needs a light refactoring to support a second clock,
> and finally the DT is changed to connect the PHY second clock to the
> corresponding GCC input then drop the dummy fixed rate clock.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> Changes in v3:
> - Rebased on linux-next, applies now cleanly
> - Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org
>
> Changes in v2:
> - Collected review tags
> - Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility
> - Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code
> and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0
> when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get()
> - Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org
>
> ---
> Neil Armstrong (3):
> arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
> arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
> arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
>
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
> arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 --------
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
> arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ----
> arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ----
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++---------
> 8 files changed, 12 insertions(+), 46 deletions(-)
> ---
> base-commit: f529a6d274b3b8c75899e949649d231298f30a32
> change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
>
> Best regards,
> --
> Neil Armstrong <neil.armstrong@linaro.org>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y qcom/sm8550-hdk.dtb qcom/sm8550-mtp.dtb qcom/sm8550-qrd.dtb qcom/sm8650-mtp.dtb qcom/sm8650-qrd.dtb' for 20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org:
arch/arm64/boot/dts/qcom/sm8550-qrd.dtb: clock-controller@100000: clocks: [[41], [42], [43], [44, 0], [45, 0], [45, 1], [45, 2], [46, 0]] is too short
from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
arch/arm64/boot/dts/qcom/sm8550-qrd.dtb: clock-controller@100000: Unevaluated properties are not allowed ('clocks' was unexpected)
from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [relevance 7%]
* Re: [PATCH v3 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock
@ 2024-04-22 11:50 7% ` Rob Herring
0 siblings, 0 replies; 200+ results
From: Rob Herring @ 2024-04-22 11:50 UTC (permalink / raw)
To: Neil Armstrong
Cc: Conor Dooley, Vinod Koul, devicetree, Krzysztof Kozlowski,
linux-kernel, linux-phy, linux-arm-msm, Bjorn Andersson,
Krzysztof Kozlowski, Dmitry Baryshkov, Konrad Dybcio,
Kishon Vijay Abraham I
On Mon, 22 Apr 2024 10:33:10 +0200, Neil Armstrong wrote:
> The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
> "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
> is muxed & gated then returned to the PHY as an input.
>
> Document the clock IDs to select the PIPE clock or the AUX clock,
> also enforce a second clock-output-names and a #clock-cells value of 1
> for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
>
> The PHY driver needs a light refactoring to support a second clock,
> and finally the DT is changed to connect the PHY second clock to the
> corresponding GCC input then drop the dummy fixed rate clock.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> Changes in v3:
> - Rebased on linux-next, applies now cleanly
> - Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org
>
> Changes in v2:
> - Collected review tags
> - Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility
> - Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code
> and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0
> when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get()
> - Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org
>
> ---
> Neil Armstrong (3):
> arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
> arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
> arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
>
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
> arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 --------
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
> arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ----
> arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ----
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++---------
> 8 files changed, 12 insertions(+), 46 deletions(-)
> ---
> base-commit: f529a6d274b3b8c75899e949649d231298f30a32
> change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
>
> Best regards,
> --
> Neil Armstrong <neil.armstrong@linaro.org>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y qcom/sm8550-hdk.dtb qcom/sm8550-mtp.dtb qcom/sm8550-qrd.dtb qcom/sm8650-mtp.dtb qcom/sm8650-qrd.dtb' for 20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org:
arch/arm64/boot/dts/qcom/sm8550-qrd.dtb: clock-controller@100000: clocks: [[41], [42], [43], [44, 0], [45, 0], [45, 1], [45, 2], [46, 0]] is too short
from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
arch/arm64/boot/dts/qcom/sm8550-qrd.dtb: clock-controller@100000: Unevaluated properties are not allowed ('clocks' was unexpected)
from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
^ permalink raw reply [relevance 7%]
* Re: [PATCH V2 RESEND 1/6] dt-bindings: clock: qcom: Add SM8650 video clock controller
@ 2024-04-22 11:00 0% ` Jagadeesh Kona
2024-04-25 13:32 0% ` Vladimir Zapolskiy
0 siblings, 1 reply; 200+ results
From: Jagadeesh Kona @ 2024-04-22 11:00 UTC (permalink / raw)
To: Vladimir Zapolskiy, Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
linux-clk, devicetree, linux-kernel, Taniya Das,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik,
Krzysztof Kozlowski
On 4/19/2024 2:31 AM, Vladimir Zapolskiy wrote:
> Hello Jagadeesh,
>
> On 3/25/24 08:07, Jagadeesh Kona wrote:
>>
>>
>> On 3/21/2024 6:42 PM, Dmitry Baryshkov wrote:
>>> On Thu, 21 Mar 2024 at 11:26, Jagadeesh Kona <quic_jkona@quicinc.com>
>>> wrote:
>>>>
>>>> Extend device tree bindings of SM8450 videocc to add support
>>>> for SM8650 videocc. While it at, fix the incorrect header
>>>> include in sm8450 videocc yaml documentation.
>>>>
>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>> ---
>>>> .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 4 +++-
>>>> include/dt-bindings/clock/qcom,sm8450-videocc.h | 8
>>>> +++++++-
>>>> 2 files changed, 10 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>>>> b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>>>> index bad8f019a8d3..79f55620eb70 100644
>>>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>>>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>>>> @@ -8,18 +8,20 @@ title: Qualcomm Video Clock & Reset Controller on
>>>> SM8450
>>>>
>>>> maintainers:
>>>> - Taniya Das <quic_tdas@quicinc.com>
>>>> + - Jagadeesh Kona <quic_jkona@quicinc.com>
>>>>
>>>> description: |
>>>> Qualcomm video clock control module provides the clocks, resets
>>>> and power
>>>> domains on SM8450.
>>>>
>>>> - See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
>>>> + See also:: include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>
>>> This almost pleads to go to a separate patch. Fixes generally should
>>> be separated from the rest of the changes.
>>>
>>
>> Thanks Dmitry for your review.
>>
>> Sure, will separate this into a separate patch in next series.
>>
>>>>
>>>> properties:
>>>> compatible:
>>>> enum:
>>>> - qcom,sm8450-videocc
>>>> - qcom,sm8550-videocc
>>>> + - qcom,sm8650-videocc
>>>>
>>>> reg:
>>>> maxItems: 1
>>>> diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>> b/include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>> index 9d795adfe4eb..ecfebe52e4bb 100644
>>>> --- a/include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>> +++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h
>>>> @@ -1,6 +1,6 @@
>>>> /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>>>> /*
>>>> - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights
>>>> reserved.
>>>> + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All
>>>> rights reserved.
>>>> */
>>>>
>>>> #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
>>>> @@ -19,6 +19,11 @@
>>>> #define
>>>> VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9
>>>> #define VIDEO_CC_PLL0 10
>>>> #define VIDEO_CC_PLL1 11
>>>> +#define
>>>> VIDEO_CC_MVS0_SHIFT_CLK 12
>>>> +#define VIDEO_CC_MVS0C_SHIFT_CLK 13
>>>> +#define
>>>> VIDEO_CC_MVS1_SHIFT_CLK 14
>>>> +#define VIDEO_CC_MVS1C_SHIFT_CLK 15
>>>> +#define VIDEO_CC_XO_CLK_SRC 16
>>>
>>> Are these values applicable to sm8450?
>>>
>>
>> No, the shift clocks above are part of SM8650 only. To reuse the
>> existing SM8550 videocc driver for SM8650 and to register these shift
>> clocks for SM8650, I added them here.
>>
>
> In such case I'd strongly suggest to add a new qcom,sm8650-videocc.h file,
> and do #include qcom,sm8450-videocc.h in it, thus the new header will be
> really a short one.
>
> This will add pristine clarity.
>
Thanks Vladimir for your suggestion. I believe adding a comment for
these set of clocks should be sufficient to indicate these clocks are
applicable only for SM8650, I can add the required comment and post the
next series. Please let me know if this works?
Thanks,
Jagadeesh
^ permalink raw reply [relevance 0%]
* Re: [PATCH V2 RESEND 5/6] clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver
@ 2024-04-22 10:57 0% ` Jagadeesh Kona
0 siblings, 0 replies; 200+ results
From: Jagadeesh Kona @ 2024-04-22 10:57 UTC (permalink / raw)
To: Vladimir Zapolskiy, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, Taniya Das,
Satya Priya Kakitapalli, Ajit Pandey, Imran Shaik,
Bryan O'Donoghue
On 4/19/2024 3:00 AM, Vladimir Zapolskiy wrote:
> Hello Jagadeesh,
>
> thank you for submitting the clock driver.
>
> On 3/21/24 11:25, Jagadeesh Kona wrote:
>> Add support for the camera clock controller for camera clients to
>> be able to request for camcc clocks on SM8650 platform.
>>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>> ---
>> drivers/clk/qcom/Kconfig | 8 +
>> drivers/clk/qcom/Makefile | 1 +
>> drivers/clk/qcom/camcc-sm8650.c | 3591 +++++++++++++++++++++++++++++++
>> 3 files changed, 3600 insertions(+)
>> create mode 100644 drivers/clk/qcom/camcc-sm8650.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 8ab08e7b5b6c..6257f4a02ec4 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -826,6 +826,14 @@ config SM_CAMCC_8550
>> Support for the camera clock controller on SM8550 devices.
>> Say Y if you want to support camera devices and camera
>> functionality.
>> +config SM_CAMCC_8650
>> + tristate "SM8650 Camera Clock Controller"
>> + depends on ARM64 || COMPILE_TEST
>> + select SM_GCC_8650
>> + help
>> + Support for the camera clock controller on SM8650 devices.
>> + Say Y if you want to support camera devices and camera
>> functionality.
>> +
>> config SM_DISPCC_6115
>> tristate "SM6115 Display Clock Controller"
>> depends on ARM64 || COMPILE_TEST
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index dec5b6db6860..28bffa1eb8dd 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -109,6 +109,7 @@ obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
>> obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
>> obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
>> obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
>> +obj-$(CONFIG_SM_CAMCC_8650) += camcc-sm8650.o
>> obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
>> obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
>> obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
>> diff --git a/drivers/clk/qcom/camcc-sm8650.c
>> b/drivers/clk/qcom/camcc-sm8650.c
>> new file mode 100644
>> index 000000000000..1b28e086e519
>> --- /dev/null
>> +++ b/drivers/clk/qcom/camcc-sm8650.c
>> @@ -0,0 +1,3591 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/mod_devicetable.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/regmap.h>
>> +
>> +#include <dt-bindings/clock/qcom,sm8650-camcc.h>
>> +
>> +#include "clk-alpha-pll.h"
>> +#include "clk-branch.h"
>> +#include "clk-rcg.h"
>> +#include "clk-regmap.h"
>> +#include "common.h"
>> +#include "gdsc.h"
>> +#include "reset.h"
>> +
>> +enum {
>> + DT_IFACE,
>> + DT_BI_TCXO,
>> + DT_BI_TCXO_AO,
>> + DT_SLEEP_CLK,
>> +};
>> +
>> +enum {
>> + P_BI_TCXO,
>> + P_BI_TCXO_AO,
>> + P_CAM_CC_PLL0_OUT_EVEN,
>> + P_CAM_CC_PLL0_OUT_MAIN,
>> + P_CAM_CC_PLL0_OUT_ODD,
>> + P_CAM_CC_PLL1_OUT_EVEN,
>> + P_CAM_CC_PLL2_OUT_EVEN,
>> + P_CAM_CC_PLL2_OUT_MAIN,
>> + P_CAM_CC_PLL3_OUT_EVEN,
>> + P_CAM_CC_PLL4_OUT_EVEN,
>> + P_CAM_CC_PLL5_OUT_EVEN,
>> + P_CAM_CC_PLL6_OUT_EVEN,
>> + P_CAM_CC_PLL7_OUT_EVEN,
>> + P_CAM_CC_PLL8_OUT_EVEN,
>> + P_CAM_CC_PLL9_OUT_EVEN,
>> + P_CAM_CC_PLL9_OUT_ODD,
>> + P_CAM_CC_PLL10_OUT_EVEN,
>> + P_SLEEP_CLK,
>> +};
>> +
>> +static const struct pll_vco lucid_ole_vco[] = {
>> + { 249600000, 2300000000, 0 },
>> +};
>
> I've noticed that a downstream Android kernel v6.1.25 defines this clock as
>
> static const struct pll_vco lucid_ole_vco[] = {
> { 249600000, 2100000000, 0 },
> };
>
> Do you know any particular reason why here the clock frequencies are
> different?
>
Thanks Vladimir for your review!
The min and max supported frequencies of PLL mentioned above are taken
from the HW specification, and as per the latest HW spec, the maximum
supported frequency for lucid OLE PLL is 2300MHz, hence used 2300MHz above.
>> +
>> +static const struct pll_vco rivian_ole_vco[] = {
>> + { 777000000, 1285000000, 0 },
>> +};
>> +
>
> <snip>
>
>> +static struct clk_rcg2 cam_cc_bps_clk_src = {
>> + .cmd_rcgr = 0x10050,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = cam_cc_parent_map_2,
>> + .freq_tbl = ftbl_cam_cc_bps_clk_src,
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "cam_cc_bps_clk_src",
>> + .parent_data = cam_cc_parent_data_2,
>> + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_rcg2_shared_ops,
>> + },
>> +};
>
> Please let me ask after Dmitry about your rationale to select
> &clk_rcg2_shared_ops here and below for all *_src clocks introduced in
> the driver, I do remember you've did it in v1, could you please
> elaborate it a bit more?
>
> I have a concern that it's not possible to get an .is_enabled status
> of the shared clocks, however at least in this particular case of
> camcc clocks it seems to be technically possible.
>
> It might indicate that there is an incompleteness in clk-rcg2.c driver
> also, if it's really possible to get is_enabled runtime status at least
> for some of the shared clocks.
>
The recommendation from HW team is to park the RCG's at XO clock source
when RCG is in disabled state and clk_rcg2_shared_ops is the closest
implementation for achieving the same, hence used clk_rcg2_shared_ops
for all the RCG's.
I will check if .is_enabled callback can be added to shared_ops and post
a separate series for it based on the requirement.
>> +
>> +static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = {
>> + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
>> + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
>> + { }
>> +};
>> +
>
> <snip>
>
> Other than two my open questions above I don't see any issues with the
> driver, if you be kind to provide the answers, please feel free to add
> my
>
> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> Tested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
>
Thanks, sure will add these tags in next series.
Thanks,
Jagadeesh
> --
> Best wishes,
> Vladimir
>
^ permalink raw reply [relevance 0%]
* [PATCH v6 5/6] soc: qcom: add pd-mapper implementation
2024-04-22 10:11 4% ` [PATCH v6 1/6] soc: qcom: pdr: protect locator_addr with the main mutex Dmitry Baryshkov
2024-04-22 10:11 4% ` [PATCH v6 4/6] soc: qcom: qmi: add a way to remove running service Dmitry Baryshkov
@ 2024-04-22 10:11 2% ` Dmitry Baryshkov
2 siblings, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-22 10:11 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Mathieu Poirier, Sibi Sankar
Cc: linux-arm-msm, linux-remoteproc, Johan Hovold, Xilin Wu
Existing userspace protection domain mapper implementation has several
issue. It doesn't play well with CONFIG_EXTRA_FIRMWARE, it doesn't
reread JSON files if firmware location is changed (or if firmware was
not available at the time pd-mapper was started but the corresponding
directory is mounted later), etc.
Provide in-kernel service implementing protection domain mapping
required to work with several services, which are provided by the DSP
firmware.
This module is loaded automatically by the remoteproc drivers when
necessary via the symbol dependency. It uses a root node to match a
protection domains map for a particular board. It is not possible to
implement it as a 'driver' as there is no corresponding device.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/soc/qcom/Kconfig | 10 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/pdr_internal.h | 14 +
drivers/soc/qcom/qcom_pd_mapper.c | 656 +++++++++++++++++++++++++++++++++++++
drivers/soc/qcom/qcom_pdr_msg.c | 34 ++
include/linux/soc/qcom/pd_mapper.h | 28 ++
6 files changed, 743 insertions(+)
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 95973c6b828f..f666366841b8 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -72,6 +72,16 @@ config QCOM_OCMEM
requirements. This is typically used by the GPU, camera/video, and
audio components on some Snapdragon SoCs.
+config QCOM_PD_MAPPER
+ tristate "Qualcomm Protection Domain Mapper"
+ select QCOM_QMI_HELPERS
+ depends on NET && QRTR
+ help
+ The Protection Domain Mapper maps registered services to the domains
+ and instances handled by the remote DSPs. This is a kernel-space
+ implementation of the service. It is a simpler alternative to the
+ userspace daemon.
+
config QCOM_PDR_HELPERS
tristate
select QCOM_QMI_HELPERS
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 3110ac3288bc..d3560f861085 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
obj-$(CONFIG_QCOM_OCMEM) += ocmem.o
+obj-$(CONFIG_QCOM_PD_MAPPER) += qcom_pd_mapper.o
obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o
obj-$(CONFIG_QCOM_PDR_MSG) += qcom_pdr_msg.o
obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink.o
diff --git a/drivers/soc/qcom/pdr_internal.h b/drivers/soc/qcom/pdr_internal.h
index 7e5bb5a95275..8d17f7fb79e7 100644
--- a/drivers/soc/qcom/pdr_internal.h
+++ b/drivers/soc/qcom/pdr_internal.h
@@ -13,6 +13,8 @@
#define SERVREG_SET_ACK_REQ 0x23
#define SERVREG_RESTART_PD_REQ 0x24
+#define SERVREG_LOC_PFR_REQ 0x24
+
#define SERVREG_DOMAIN_LIST_LENGTH 32
#define SERVREG_RESTART_PD_REQ_MAX_LEN 67
#define SERVREG_REGISTER_LISTENER_REQ_LEN 71
@@ -20,6 +22,7 @@
#define SERVREG_GET_DOMAIN_LIST_REQ_MAX_LEN 74
#define SERVREG_STATE_UPDATED_IND_MAX_LEN 79
#define SERVREG_GET_DOMAIN_LIST_RESP_MAX_LEN 2389
+#define SERVREG_LOC_PFR_RESP_MAX_LEN 10
struct servreg_location_entry {
char name[SERVREG_NAME_LENGTH + 1];
@@ -79,6 +82,15 @@ struct servreg_set_ack_resp {
struct qmi_response_type_v01 resp;
};
+struct servreg_loc_pfr_req {
+ char service[SERVREG_NAME_LENGTH + 1];
+ char reason[257];
+};
+
+struct servreg_loc_pfr_resp {
+ struct qmi_response_type_v01 rsp;
+};
+
extern const struct qmi_elem_info servreg_location_entry_ei[];
extern const struct qmi_elem_info servreg_get_domain_list_req_ei[];
extern const struct qmi_elem_info servreg_get_domain_list_resp_ei[];
@@ -89,5 +101,7 @@ extern const struct qmi_elem_info servreg_restart_pd_resp_ei[];
extern const struct qmi_elem_info servreg_state_updated_ind_ei[];
extern const struct qmi_elem_info servreg_set_ack_req_ei[];
extern const struct qmi_elem_info servreg_set_ack_resp_ei[];
+extern const struct qmi_elem_info servreg_loc_pfr_req_ei[];
+extern const struct qmi_elem_info servreg_loc_pfr_resp_ei[];
#endif
diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c
new file mode 100644
index 000000000000..ba5440506c95
--- /dev/null
+++ b/drivers/soc/qcom/qcom_pd_mapper.c
@@ -0,0 +1,656 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Qualcomm Protection Domain mapper
+ *
+ * Copyright (c) 2023 Linaro Ltd.
+ */
+
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/soc/qcom/pd_mapper.h>
+#include <linux/soc/qcom/qmi.h>
+
+#include "pdr_internal.h"
+
+#define SERVREG_QMI_VERSION 0x101
+#define SERVREG_QMI_INSTANCE 0
+
+#define TMS_SERVREG_SERVICE "tms/servreg"
+
+struct qcom_pdm_domain_data {
+ const char *domain;
+ u32 instance_id;
+ /* NULL-terminated array */
+ const char * services[];
+};
+
+struct qcom_pdm_domain {
+ struct list_head list;
+ const char *name;
+ u32 instance_id;
+};
+
+struct qcom_pdm_service {
+ struct list_head list;
+ struct list_head domains;
+ const char *name;
+};
+
+static DEFINE_MUTEX(qcom_pdm_count_mutex); /* guards count */
+/*
+ * It is not possible to use refcount_t here. The service needs to go to 0 and
+ * back without warnings.
+ */
+static unsigned int qcom_pdm_count;
+
+static DEFINE_MUTEX(qcom_pdm_mutex);
+static struct qmi_handle qcom_pdm_handle;
+static LIST_HEAD(qcom_pdm_services);
+
+static struct qcom_pdm_service *qcom_pdm_find(const char *name)
+{
+ struct qcom_pdm_service *service;
+
+ list_for_each_entry(service, &qcom_pdm_services, list) {
+ if (!strcmp(service->name, name))
+ return service;
+ }
+
+ return NULL;
+}
+
+static int qcom_pdm_add_service_domain(const char *service_name,
+ const char *domain_name,
+ u32 instance_id)
+{
+ struct qcom_pdm_service *service;
+ struct qcom_pdm_domain *domain;
+
+ service = qcom_pdm_find(service_name);
+ if (service) {
+ list_for_each_entry(domain, &service->domains, list) {
+ if (!strcmp(domain->name, domain_name))
+ return -EBUSY;
+ }
+ } else {
+ service = kzalloc(sizeof(*service), GFP_KERNEL);
+ if (!service)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&service->domains);
+ service->name = service_name;
+
+ list_add_tail(&service->list, &qcom_pdm_services);
+ }
+
+ domain = kzalloc(sizeof(*domain), GFP_KERNEL);
+ if (!domain) {
+ if (list_empty(&service->domains)) {
+ list_del(&service->list);
+ kfree(service);
+ }
+
+ return -ENOMEM;
+ }
+
+ domain->name = domain_name;
+ domain->instance_id = instance_id;
+ list_add_tail(&domain->list, &service->domains);
+
+ return 0;
+}
+
+static int qcom_pdm_add_domain(const struct qcom_pdm_domain_data *data)
+{
+ int ret;
+ int i;
+
+ ret = qcom_pdm_add_service_domain(TMS_SERVREG_SERVICE,
+ data->domain,
+ data->instance_id);
+ if (ret)
+ return ret;
+
+ for (i = 0; data->services[i]; i++) {
+ ret = qcom_pdm_add_service_domain(data->services[i],
+ data->domain,
+ data->instance_id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+
+}
+
+static void qcom_pdm_free_domains(void)
+{
+ struct qcom_pdm_service *service, *tservice;
+ struct qcom_pdm_domain *domain, *tdomain;
+
+ list_for_each_entry_safe(service, tservice, &qcom_pdm_services, list) {
+ list_for_each_entry_safe(domain, tdomain, &service->domains, list) {
+ list_del(&domain->list);
+ kfree(domain);
+ }
+
+ list_del(&service->list);
+ kfree(service);
+ }
+}
+
+static void qcom_pdm_get_domain_list(struct qmi_handle *qmi,
+ struct sockaddr_qrtr *sq,
+ struct qmi_txn *txn,
+ const void *decoded)
+{
+ const struct servreg_get_domain_list_req *req = decoded;
+ struct servreg_get_domain_list_resp *rsp = kzalloc(sizeof(*rsp), GFP_KERNEL);
+ struct qcom_pdm_service *service;
+ u32 offset;
+ int ret;
+
+ offset = req->domain_offset_valid ? req->domain_offset : 0;
+
+ rsp->resp.result = QMI_RESULT_SUCCESS_V01;
+ rsp->resp.error = QMI_ERR_NONE_V01;
+
+ rsp->db_rev_count_valid = true;
+ rsp->db_rev_count = 1;
+
+ rsp->total_domains_valid = true;
+ rsp->total_domains = 0;
+
+ mutex_lock(&qcom_pdm_mutex);
+
+ service = qcom_pdm_find(req->service_name);
+ if (service) {
+ struct qcom_pdm_domain *domain;
+
+ rsp->domain_list_valid = true;
+ rsp->domain_list_len = 0;
+
+ list_for_each_entry(domain, &service->domains, list) {
+ u32 i = rsp->total_domains++;
+
+ if (i >= offset && i < SERVREG_DOMAIN_LIST_LENGTH) {
+ u32 j = rsp->domain_list_len++;
+
+ strscpy(rsp->domain_list[j].name, domain->name,
+ sizeof(rsp->domain_list[i].name));
+ rsp->domain_list[j].instance = domain->instance_id;
+
+ pr_debug("PDM: found %s / %d\n", domain->name,
+ domain->instance_id);
+ }
+ }
+ }
+
+ pr_debug("PDM: service '%s' offset %d returning %d domains (of %d)\n", req->service_name,
+ req->domain_offset_valid ? req->domain_offset : -1, rsp->domain_list_len, rsp->total_domains);
+
+ ret = qmi_send_response(qmi, sq, txn, SERVREG_GET_DOMAIN_LIST_REQ,
+ SERVREG_GET_DOMAIN_LIST_RESP_MAX_LEN,
+ servreg_get_domain_list_resp_ei, rsp);
+ if (ret)
+ pr_err("Error sending servreg response: %d\n", ret);
+
+ mutex_unlock(&qcom_pdm_mutex);
+
+ kfree(rsp);
+}
+
+static void qcom_pdm_pfr(struct qmi_handle *qmi,
+ struct sockaddr_qrtr *sq,
+ struct qmi_txn *txn,
+ const void *decoded)
+{
+ const struct servreg_loc_pfr_req *req = decoded;
+ struct servreg_loc_pfr_resp rsp = {};
+ int ret;
+
+ pr_warn_ratelimited("PDM: service '%s' crash: '%s'\n", req->service, req->reason);
+
+ rsp.rsp.result = QMI_RESULT_SUCCESS_V01;
+ rsp.rsp.error = QMI_ERR_NONE_V01;
+
+ ret = qmi_send_response(qmi, sq, txn, SERVREG_LOC_PFR_REQ,
+ SERVREG_LOC_PFR_RESP_MAX_LEN,
+ servreg_loc_pfr_resp_ei, &rsp);
+ if (ret)
+ pr_err("Error sending servreg response: %d\n", ret);
+}
+
+static const struct qmi_msg_handler qcom_pdm_msg_handlers[] = {
+ {
+ .type = QMI_REQUEST,
+ .msg_id = SERVREG_GET_DOMAIN_LIST_REQ,
+ .ei = servreg_get_domain_list_req_ei,
+ .decoded_size = sizeof(struct servreg_get_domain_list_req),
+ .fn = qcom_pdm_get_domain_list,
+ },
+ {
+ .type = QMI_REQUEST,
+ .msg_id = SERVREG_LOC_PFR_REQ,
+ .ei = servreg_loc_pfr_req_ei,
+ .decoded_size = sizeof(struct servreg_loc_pfr_req),
+ .fn = qcom_pdm_pfr,
+ },
+ { },
+};
+
+static const struct qcom_pdm_domain_data adsp_audio_pd = {
+ .domain = "msm/adsp/audio_pd",
+ .instance_id = 74,
+ .services = {
+ "avs/audio",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data adsp_charger_pd = {
+ .domain = "msm/adsp/charger_pd",
+ .instance_id = 74,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data adsp_root_pd = {
+ .domain = "msm/adsp/root_pd",
+ .instance_id = 74,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data adsp_root_pd_pdr = {
+ .domain = "msm/adsp/root_pd",
+ .instance_id = 74,
+ .services = {
+ "tms/pdr_enabled",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data adsp_sensor_pd = {
+ .domain = "msm/adsp/sensor_pd",
+ .instance_id = 74,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data msm8996_adsp_audio_pd = {
+ .domain = "msm/adsp/audio_pd",
+ .instance_id = 4,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data msm8996_adsp_root_pd = {
+ .domain = "msm/adsp/root_pd",
+ .instance_id = 4,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data cdsp_root_pd = {
+ .domain = "msm/cdsp/root_pd",
+ .instance_id = 76,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data slpi_root_pd = {
+ .domain = "msm/slpi/root_pd",
+ .instance_id = 90,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data slpi_sensor_pd = {
+ .domain = "msm/slpi/sensor_pd",
+ .instance_id = 90,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data mpss_root_pd = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 180,
+ .services = {
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data mpss_root_pd_gps = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 180,
+ .services = {
+ "gps/gps_service",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data mpss_root_pd_gps_pdr = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 180,
+ .services = {
+ "gps/gps_service",
+ "tms/pdr_enabled",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data msm8996_mpss_root_pd = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 100,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data mpss_wlan_pd = {
+ .domain = "msm/modem/wlan_pd",
+ .instance_id = 180,
+ .services = {
+ "kernel/elf_loader",
+ "wlan/fw",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data *msm8996_domains[] = {
+ &msm8996_adsp_audio_pd,
+ &msm8996_adsp_root_pd,
+ &msm8996_mpss_root_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *msm8998_domains[] = {
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *qcm2290_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *qcs404_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc7180_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_sensor_pd,
+ &mpss_root_pd_gps_pdr,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc7280_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_charger_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps_pdr,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc8180x_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_charger_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc8280xp_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_charger_pd,
+ &cdsp_root_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sdm660_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sdm670_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sdm845_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ &slpi_root_pd,
+ &slpi_sensor_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm6115_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm6350_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8150_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8250_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &slpi_root_pd,
+ &slpi_sensor_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8350_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_charger_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &slpi_root_pd,
+ &slpi_sensor_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8550_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_charger_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ NULL,
+};
+
+static const struct of_device_id qcom_pdm_domains[] = {
+ { .compatible = "qcom,apq8064", .data = NULL, },
+ { .compatible = "qcom,apq8074", .data = NULL, },
+ { .compatible = "qcom,apq8084", .data = NULL, },
+ { .compatible = "qcom,apq8096", .data = msm8996_domains, },
+ { .compatible = "qcom,msm8226", .data = NULL, },
+ { .compatible = "qcom,msm8974", .data = NULL, },
+ { .compatible = "qcom,msm8996", .data = msm8996_domains, },
+ { .compatible = "qcom,msm8998", .data = msm8998_domains, },
+ { .compatible = "qcom,qcm2290", .data = qcm2290_domains, },
+ { .compatible = "qcom,qcs404", .data = qcs404_domains, },
+ { .compatible = "qcom,sc7180", .data = sc7180_domains, },
+ { .compatible = "qcom,sc7280", .data = sc7280_domains, },
+ { .compatible = "qcom,sc8180x", .data = sc8180x_domains, },
+ { .compatible = "qcom,sc8280xp", .data = sc8280xp_domains, },
+ { .compatible = "qcom,sda660", .data = sdm660_domains, },
+ { .compatible = "qcom,sdm660", .data = sdm660_domains, },
+ { .compatible = "qcom,sdm670", .data = sdm670_domains, },
+ { .compatible = "qcom,sdm845", .data = sdm845_domains, },
+ { .compatible = "qcom,sm6115", .data = sm6115_domains, },
+ { .compatible = "qcom,sm6350", .data = sm6350_domains, },
+ { .compatible = "qcom,sm8150", .data = sm8150_domains, },
+ { .compatible = "qcom,sm8250", .data = sm8250_domains, },
+ { .compatible = "qcom,sm8350", .data = sm8350_domains, },
+ { .compatible = "qcom,sm8450", .data = sm8350_domains, },
+ { .compatible = "qcom,sm8550", .data = sm8550_domains, },
+ { .compatible = "qcom,sm8650", .data = sm8550_domains, },
+ {},
+};
+
+static int qcom_pdm_start(void)
+{
+ const struct of_device_id *match;
+ const struct qcom_pdm_domain_data * const *domains;
+ struct device_node *root;
+ int ret, i;
+
+ root = of_find_node_by_path("/");
+ if (!root)
+ return -ENODEV;
+
+ match = of_match_node(qcom_pdm_domains, root);
+ of_node_put(root);
+ if (!match) {
+ pr_notice("PDM: no support for the platform, userspace daemon might be required.\n");
+ return -ENODEV;
+ }
+
+ domains = match->data;
+ if (!domains) {
+ pr_debug("PDM: no domains\n");
+ return -ENODEV;
+ }
+
+ mutex_lock(&qcom_pdm_mutex);
+ for (i = 0; domains[i]; i++) {
+ ret = qcom_pdm_add_domain(domains[i]);
+ if (ret)
+ goto free_domains;
+ }
+
+ ret = qmi_handle_init(&qcom_pdm_handle, 1024,
+ NULL, qcom_pdm_msg_handlers);
+ if (ret)
+ goto free_domains;
+
+ ret = qmi_add_server(&qcom_pdm_handle, SERVREG_LOCATOR_SERVICE,
+ SERVREG_QMI_VERSION, SERVREG_QMI_INSTANCE);
+ if (ret) {
+ pr_err("PDM: error adding server %d\n", ret);
+ goto release_handle;
+ }
+ mutex_unlock(&qcom_pdm_mutex);
+
+ return 0;
+
+release_handle:
+ qmi_handle_release(&qcom_pdm_handle);
+
+free_domains:
+ qcom_pdm_free_domains();
+ mutex_unlock(&qcom_pdm_mutex);
+
+ return ret;
+}
+
+static void qcom_pdm_stop(void)
+{
+ qmi_del_server(&qcom_pdm_handle, SERVREG_LOCATOR_SERVICE,
+ SERVREG_QMI_VERSION, SERVREG_QMI_INSTANCE);
+
+ qmi_handle_release(&qcom_pdm_handle);
+
+ qcom_pdm_free_domains();
+}
+
+/**
+ * qcom_pdm_get() - ensure that PD mapper is up and running
+ *
+ * Start the in-kernel Qualcomm DSP protection domain mapper service if it was
+ * not running.
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+int qcom_pdm_get(void)
+{
+ int ret = 0;
+
+ mutex_lock(&qcom_pdm_count_mutex);
+
+ if (!qcom_pdm_count)
+ ret = qcom_pdm_start();
+ if (!ret)
+ ++qcom_pdm_count;
+
+ mutex_unlock(&qcom_pdm_count_mutex);
+
+ /*
+ * If it is -ENODEV, the plaform is not supported by the in-kernel
+ * mapper. Still return 0 to rproc driver, userspace daemon will be
+ * used instead of the kernel server.
+ */
+ if (ret == -ENODEV)
+ return 0;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(qcom_pdm_get);
+
+/**
+ * qcom_pdm_release() - possibly stop PD mapper service
+ *
+ * Decreases refcount, stopping the server when the last user was removed.
+ */
+void qcom_pdm_release(void)
+{
+ mutex_lock(&qcom_pdm_count_mutex);
+
+ if (qcom_pdm_count == 1)
+ qcom_pdm_stop();
+
+ if (qcom_pdm_count >= 1)
+ --qcom_pdm_count;
+
+ mutex_unlock(&qcom_pdm_count_mutex);
+}
+EXPORT_SYMBOL_GPL(qcom_pdm_release);
+
+MODULE_DESCRIPTION("Qualcomm Protection Domain Mapper");
+MODULE_LICENSE("GPL");
diff --git a/drivers/soc/qcom/qcom_pdr_msg.c b/drivers/soc/qcom/qcom_pdr_msg.c
index a8867e8b1319..bdebbe929468 100644
--- a/drivers/soc/qcom/qcom_pdr_msg.c
+++ b/drivers/soc/qcom/qcom_pdr_msg.c
@@ -313,3 +313,37 @@ const struct qmi_elem_info servreg_set_ack_resp_ei[] = {
{}
};
EXPORT_SYMBOL_GPL(servreg_set_ack_resp_ei);
+
+const struct qmi_elem_info servreg_loc_pfr_req_ei[] = {
+ {
+ .data_type = QMI_STRING,
+ .elem_len = SERVREG_NAME_LENGTH + 1,
+ .elem_size = sizeof(char),
+ .array_type = VAR_LEN_ARRAY,
+ .tlv_type = 0x01,
+ .offset = offsetof(struct servreg_loc_pfr_req, service)
+ },
+ {
+ .data_type = QMI_STRING,
+ .elem_len = SERVREG_NAME_LENGTH + 1,
+ .elem_size = sizeof(char),
+ .array_type = VAR_LEN_ARRAY,
+ .tlv_type = 0x02,
+ .offset = offsetof(struct servreg_loc_pfr_req, reason)
+ },
+ {}
+};
+EXPORT_SYMBOL_GPL(servreg_loc_pfr_req_ei);
+
+const struct qmi_elem_info servreg_loc_pfr_resp_ei[] = {
+ {
+ .data_type = QMI_STRUCT,
+ .elem_len = 1,
+ .elem_size = sizeof_field(struct servreg_loc_pfr_resp, rsp),
+ .tlv_type = 0x02,
+ .offset = offsetof(struct servreg_loc_pfr_resp, rsp),
+ .ei_array = qmi_response_type_v01_ei,
+ },
+ {}
+};
+EXPORT_SYMBOL_GPL(servreg_loc_pfr_resp_ei);
diff --git a/include/linux/soc/qcom/pd_mapper.h b/include/linux/soc/qcom/pd_mapper.h
new file mode 100644
index 000000000000..d0dd3dfc8fea
--- /dev/null
+++ b/include/linux/soc/qcom/pd_mapper.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Qualcomm Protection Domain mapper
+ *
+ * Copyright (c) 2023 Linaro Ltd.
+ */
+#ifndef __QCOM_PD_MAPPER__
+#define __QCOM_PD_MAPPER__
+
+#if IS_ENABLED(CONFIG_QCOM_PD_MAPPER)
+
+int qcom_pdm_get(void);
+void qcom_pdm_release(void);
+
+#else
+
+static inline int qcom_pdm_get(void)
+{
+ return 0;
+}
+
+static inline void qcom_pdm_release(void)
+{
+}
+
+#endif
+
+#endif
--
2.39.2
^ permalink raw reply related [relevance 2%]
* [PATCH v6 4/6] soc: qcom: qmi: add a way to remove running service
2024-04-22 10:11 4% ` [PATCH v6 1/6] soc: qcom: pdr: protect locator_addr with the main mutex Dmitry Baryshkov
@ 2024-04-22 10:11 4% ` Dmitry Baryshkov
2024-04-22 10:11 2% ` [PATCH v6 5/6] soc: qcom: add pd-mapper implementation Dmitry Baryshkov
2 siblings, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-22 10:11 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Mathieu Poirier, Sibi Sankar
Cc: linux-arm-msm, linux-remoteproc, Johan Hovold, Xilin Wu, Neil Armstrong
Add qmi_del_server(), a pair to qmi_add_server(), a way to remove
running server from the QMI socket. This is e.g. necessary for
pd-mapper, which needs to readd a server each time the DSP is started or
stopped.
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/soc/qcom/qmi_interface.c | 67 ++++++++++++++++++++++++++++++++++++++++
include/linux/soc/qcom/qmi.h | 2 ++
2 files changed, 69 insertions(+)
diff --git a/drivers/soc/qcom/qmi_interface.c b/drivers/soc/qcom/qmi_interface.c
index bb98b06e87f8..18ff2015c682 100644
--- a/drivers/soc/qcom/qmi_interface.c
+++ b/drivers/soc/qcom/qmi_interface.c
@@ -289,6 +289,73 @@ int qmi_add_server(struct qmi_handle *qmi, unsigned int service,
}
EXPORT_SYMBOL_GPL(qmi_add_server);
+static void qmi_send_del_server(struct qmi_handle *qmi, struct qmi_service *svc)
+{
+ struct qrtr_ctrl_pkt pkt;
+ struct sockaddr_qrtr sq;
+ struct msghdr msg = { };
+ struct kvec iv = { &pkt, sizeof(pkt) };
+ int ret;
+
+ memset(&pkt, 0, sizeof(pkt));
+ pkt.cmd = cpu_to_le32(QRTR_TYPE_DEL_SERVER);
+ pkt.server.service = cpu_to_le32(svc->service);
+ pkt.server.instance = cpu_to_le32(svc->version | svc->instance << 8);
+ pkt.server.node = cpu_to_le32(qmi->sq.sq_node);
+ pkt.server.port = cpu_to_le32(qmi->sq.sq_port);
+
+ sq.sq_family = qmi->sq.sq_family;
+ sq.sq_node = qmi->sq.sq_node;
+ sq.sq_port = QRTR_PORT_CTRL;
+
+ msg.msg_name = &sq;
+ msg.msg_namelen = sizeof(sq);
+
+ mutex_lock(&qmi->sock_lock);
+ if (qmi->sock) {
+ ret = kernel_sendmsg(qmi->sock, &msg, &iv, 1, sizeof(pkt));
+ if (ret < 0)
+ pr_err("send service deregistration failed: %d\n", ret);
+ }
+ mutex_unlock(&qmi->sock_lock);
+}
+
+/**
+ * qmi_del_server() - register a service with the name service
+ * @qmi: qmi handle
+ * @service: type of the service
+ * @instance: instance of the service
+ * @version: version of the service
+ *
+ * Remove registration of the service with the name service. This notifies
+ * clients that they should no longer send messages to the client associated
+ * with @qmi.
+ *
+ * Return: 0 on success, negative errno on failure.
+ */
+int qmi_del_server(struct qmi_handle *qmi, unsigned int service,
+ unsigned int version, unsigned int instance)
+{
+ struct qmi_service *svc;
+ struct qmi_service *tmp;
+
+ list_for_each_entry_safe(svc, tmp, &qmi->services, list_node) {
+ if (svc->service != service ||
+ svc->version != version ||
+ svc->instance != instance)
+ continue;
+
+ qmi_send_del_server(qmi, svc);
+ list_del(&svc->list_node);
+ kfree(svc);
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(qmi_del_server);
+
/**
* qmi_txn_init() - allocate transaction id within the given QMI handle
* @qmi: QMI handle
diff --git a/include/linux/soc/qcom/qmi.h b/include/linux/soc/qcom/qmi.h
index 469e02d2aa0d..5039c30e4bdc 100644
--- a/include/linux/soc/qcom/qmi.h
+++ b/include/linux/soc/qcom/qmi.h
@@ -241,6 +241,8 @@ int qmi_add_lookup(struct qmi_handle *qmi, unsigned int service,
unsigned int version, unsigned int instance);
int qmi_add_server(struct qmi_handle *qmi, unsigned int service,
unsigned int version, unsigned int instance);
+int qmi_del_server(struct qmi_handle *qmi, unsigned int service,
+ unsigned int version, unsigned int instance);
int qmi_handle_init(struct qmi_handle *qmi, size_t max_msg_len,
const struct qmi_ops *ops,
--
2.39.2
^ permalink raw reply related [relevance 4%]
* [PATCH v6 1/6] soc: qcom: pdr: protect locator_addr with the main mutex
@ 2024-04-22 10:11 4% ` Dmitry Baryshkov
2024-04-22 10:11 4% ` [PATCH v6 4/6] soc: qcom: qmi: add a way to remove running service Dmitry Baryshkov
2024-04-22 10:11 2% ` [PATCH v6 5/6] soc: qcom: add pd-mapper implementation Dmitry Baryshkov
2 siblings, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-22 10:11 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Mathieu Poirier, Sibi Sankar
Cc: linux-arm-msm, linux-remoteproc, Johan Hovold, Xilin Wu, Neil Armstrong
If the service locator server is restarted fast enough, the PDR can
rewrite locator_addr fields concurrently. Protect them by placing
modification of those fields under the main pdr->lock.
Fixes: fbe639b44a82 ("soc: qcom: Introduce Protection Domain Restart helpers")
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/soc/qcom/pdr_interface.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/qcom/pdr_interface.c b/drivers/soc/qcom/pdr_interface.c
index a1b6a4081dea..19cfe4b41235 100644
--- a/drivers/soc/qcom/pdr_interface.c
+++ b/drivers/soc/qcom/pdr_interface.c
@@ -76,12 +76,12 @@ static int pdr_locator_new_server(struct qmi_handle *qmi,
locator_hdl);
struct pdr_service *pds;
+ mutex_lock(&pdr->lock);
/* Create a local client port for QMI communication */
pdr->locator_addr.sq_family = AF_QIPCRTR;
pdr->locator_addr.sq_node = svc->node;
pdr->locator_addr.sq_port = svc->port;
- mutex_lock(&pdr->lock);
pdr->locator_init_complete = true;
mutex_unlock(&pdr->lock);
@@ -104,10 +104,10 @@ static void pdr_locator_del_server(struct qmi_handle *qmi,
mutex_lock(&pdr->lock);
pdr->locator_init_complete = false;
- mutex_unlock(&pdr->lock);
pdr->locator_addr.sq_node = 0;
pdr->locator_addr.sq_port = 0;
+ mutex_unlock(&pdr->lock);
}
static const struct qmi_ops pdr_locator_ops = {
--
2.39.2
^ permalink raw reply related [relevance 4%]
* [PATCH v4 3/3] arch: arm64: dts: sm8650-hdk: add support for the Display Card overlay
2024-04-22 8:48 9% ` [PATCH v4 2/3] arm64: dts: " Neil Armstrong
@ 2024-04-22 8:48 13% ` Neil Armstrong
1 sibling, 0 replies; 200+ results
From: Neil Armstrong @ 2024-04-22 8:48 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong,
Vladimir Zapolskiy
With the SM8650-HDK, a Display Card kit can be connected to provide
a VTDR6130 display with Goodix Berlin Touch controller.
In order to route the DSI lanes to the connector for the Display
Card kit, a switch must be changed on the board.
The HDMI nodes are disabled since the DSI lanes are shared with
the DSI to HDMI transceiver.
Add support for this card as an overlay and apply it it at
build-time to the sm8650-hdk dtb.
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Tested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/Makefile | 4 +
.../boot/dts/qcom/sm8650-hdk-display-card.dtso | 144 +++++++++++++++++++++
2 files changed, 148 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 74e6796eb5eb..640c8fb499fe 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -242,6 +242,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb
+
+sm8650-hdk-display-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso b/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso
new file mode 100644
index 000000000000..83f2338e5bf4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+/*
+ * Display Card kit overlay
+ * This requires S5702 Switch 7 to be turned to OFF to route DSI0 to the display panel
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+/plugin/;
+
+&i2c6 {
+ status = "disabled";
+};
+
+<9611_1v2 {
+ status = "disabled";
+};
+
+<9611_3v3 {
+ status = "disabled";
+};
+
+&vreg_bob_3v3 {
+ status = "disabled";
+};
+
+<9611_codec {
+ status = "disabled";
+};
+
+&mdss_dsi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "visionox,vtdr6130";
+ reg = <0>;
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vddio-supply = <&vreg_l12b_1p8>;
+ vci-supply = <&vreg_l13b_3p0>;
+ vdd-supply = <&vreg_l11b_1p2>;
+
+ pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>;
+ pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>;
+ pinctrl-names = "default", "sleep";
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+
+ /*
+ * DTC requires to have both endpoints when compiling the overlay
+ * and also requires the #address/size-cells + reg properties
+ */
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi0_out: endpoint {
+ remote-endpoint = <&panel0_in>;
+ };
+ };
+ };
+};
+
+&spi4 {
+ /* DTC requires the #address/size-cells to compile DTBO */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ touchscreen@0 {
+ compatible = "goodix,gt9916";
+ reg = <0>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <162 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&tlmm 161 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&vreg_l14b_3p2>;
+
+ spi-max-frequency = <1000000>;
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <2400>;
+
+ pinctrl-0 = <&ts_irq>, <&ts_reset>;
+ pinctrl-names = "default";
+ };
+};
+
+&tlmm {
+ disp0_reset_n_active: disp0-reset-n-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ disp0_reset_n_suspend: disp0-reset-n-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdp_vsync: mdp-vsync-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ ts_irq: ts-irq-state {
+ pins = "gpio161";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-disable;
+ };
+
+ ts_reset: ts-reset-state {
+ pins = "gpio162";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+};
--
2.34.1
^ permalink raw reply related [relevance 13%]
* [PATCH v4 2/3] arm64: dts: qcom: sm8650: add support for the SM8650-HDK board
@ 2024-04-22 8:48 9% ` Neil Armstrong
2024-04-22 8:48 13% ` [PATCH v4 3/3] arch: arm64: dts: sm8650-hdk: add support for the Display Card overlay Neil Armstrong
1 sibling, 0 replies; 200+ results
From: Neil Armstrong @ 2024-04-22 8:48 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong,
Vladimir Zapolskiy
The SM8650-HDK is an embedded development platforms for the
Snapdragon 8 Gen 3 SoC aka SM8650, with the following features:
- Qualcomm SM8650 SoC
- 16GiB On-board LPDDR5
- On-board WiFi 7 + Bluetooth 5.3/BLE
- On-board UFS4.0
- M.2 Key B+M Gen3x2 PCIe Slot
- HDMI Output
- USB-C Connector with DP Almode & Audio Accessory mode
- Micro-SDCard Slot
- Audio Jack with Playback and Microphone
- 2 On-board Analog microphones
- 2 On-board Speakers
- 96Boards Compatible Low-Speed and High-Speed connectors [1]
- For Camera, Sensors and external Display cards
- Compatible with the Linaro Debug board [2]
- SIM Slot for Modem
- Debug connectors
- 6x On-Board LEDs
Product Page: [3]
[1] https://www.96boards.org/specifications/
[2] https://git.codelinaro.org/linaro/qcomlt/debugboard
[3] https://www.lantronix.com/products/snapdragon-8-gen-3-mobile-hardware-development-kit/
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Tested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 1251 +++++++++++++++++++++++++++++++
2 files changed, 1252 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index f63abb43e9fe..74e6796eb5eb 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -242,6 +242,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
new file mode 100644
index 000000000000..3791c36579be
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -0,0 +1,1251 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8650.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 8
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SM8650 HDK";
+ compatible = "qcom,sm8650-hdk", "qcom,sm8650";
+ chassis-type = "embedded";
+
+ aliases {
+ serial0 = &uart15;
+ serial1 = &uart14;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_out: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_BLUETOOTH;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ default-state = "off";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pm8550b_gpios 9 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ panic-indicator;
+ };
+
+ led-2 {
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_ORANGE>;
+ gpios = <&pm8550b_gpios 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8650-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&wcd_usbss_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ lt9611_1v2: regulator-lt9611-1v2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "LT9611_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ vin-supply = <&vph_pwr>;
+ gpio = <&tlmm 79 GPIO_ACTIVE_HIGH>;
+
+ enable-active-high;
+ };
+
+ lt9611_3v3: regulator-lt9611-3v3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "LT9611_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&vreg_bob_3v3>;
+ gpio = <&tlmm 78 GPIO_ACTIVE_HIGH>;
+
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard";
+ model = "SM8650-HDK";
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC1", "MIC BIAS1",
+ "AMIC2", "MIC BIAS2",
+ "AMIC5", "MIC BIAS4",
+ "TX SWR_INPUT0", "ADC1_OUTPUT",
+ "TX SWR_INPUT1", "ADC2_OUTPUT",
+ "TX SWR_INPUT3", "ADC4_OUTPUT";
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ codec {
+ sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_bob_3v3: regulator-vreg-bob-3v3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_BOB_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ wcd939x: audio-codec {
+ compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec";
+
+ pinctrl-0 = <&wcd_default>;
+ pinctrl-names = "default";
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ reset-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+
+ vdd-buck-supply = <&vreg_l15b_1p8>;
+ vdd-rxtx-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob1>;
+
+ #sound-dai-cells = <1>;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s1c_1p2>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s1c_1p2>;
+ vdd-l12-supply = <&vreg_s6c_1p8>;
+ vdd-l15-supply = <&vreg_s6c_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ qcom,pmic-id = "b";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1c_1p2>;
+ vdd-l2-supply = <&vreg_s1c_1p2>;
+ vdd-l3-supply = <&vreg_s1c_1p2>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "c";
+
+ vreg_s1c_1p2: smps1 {
+ regulator-name = "vreg_s1c_1p2";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1348000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2c_0p8: smps2 {
+ regulator-name = "vreg_s2c_0p8";
+ regulator-min-microvolt = <852000>;
+ regulator-max-microvolt = <1036000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3c_0p9: smps3 {
+ regulator-name = "vreg_s3c_0p9";
+ regulator-min-microvolt = <976000>;
+ regulator-max-microvolt = <1064000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4c_1p2: smps4 {
+ regulator-name = "vreg_s4c_1p2";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1280000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5c_0p7: smps5 {
+ regulator-name = "vreg_s5c_0p7";
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6c_1p8: smps6 {
+ regulator-name = "vreg_s6c_1p8";
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p2: ldo1 {
+ regulator-name = "vreg_l1c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_1p2: ldo3 {
+ regulator-name = "vreg_l3c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3c_0p9>;
+
+ qcom,pmic-id = "d";
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l3-supply = <&vreg_s3c_0p9>;
+
+ qcom,pmic-id = "e";
+
+ vreg_l3e_0p9: ldo3 {
+ regulator-name = "vreg_l3e_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3c_0p9>;
+ vdd-l3-supply = <&vreg_s3c_0p9>;
+
+ qcom,pmic-id = "g";
+
+ vreg_l1g_0p91: ldo1 {
+ regulator-name = "vreg_l1g_0p91";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_0p91: ldo3 {
+ regulator-name = "vreg_l3g_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3c_0p9>;
+ vdd-l2-supply = <&vreg_s3c_0p9>;
+ vdd-l3-supply = <&vreg_s1c_1p2>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "i";
+
+ vreg_s4i_0p85: smps4 {
+ regulator-name = "vreg_s4i_0p85";
+ regulator-min-microvolt = <852000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1i_0p88: ldo1 {
+ regulator-name = "vreg_l1i_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_0p88: ldo2 {
+ regulator-name = "vreg_l2i_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3i_1p2: ldo3 {
+ regulator-name = "vreg_l3i_0p91";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "m";
+
+ vdd-l1-l2-supply = <&vreg_s1c_1p2>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6c_1p8>;
+ vdd-l6-supply = <&vreg_bob1>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1m_1p1: ldo1 {
+ regulator-name = "vreg_l1m_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_2p8: ldo6 {
+ regulator-name = "vreg_l6m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p96: ldo7 {
+ regulator-name = "vreg_l7m_2p96";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "n";
+
+ vdd-l1-l2-supply = <&vreg_s1c_1p2>;
+ vdd-l3-l4-supply = <&vreg_s6c_1p8>;
+ vdd-l5-supply = <&vreg_bob2>;
+ vdd-l6-supply = <&vreg_bob2>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p056: ldo2 {
+ regulator-name = "vreg_l2n_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_1p8: ldo3 {
+ regulator-name = "vreg_l3n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_1p8: ldo4 {
+ regulator-name = "vreg_l4n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_2p8: ldo5 {
+ regulator-name = "vreg_l5n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_2p8: ldo6 {
+ regulator-name = "vreg_l6n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_3p3: ldo7 {
+ regulator-name = "vreg_l7n_3p3";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&dispcc {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ wcd_usbss: typec-mux@e {
+ compatible = "qcom,wcd9395-usbss", "qcom,wcd9390-usbss";
+ reg = <0xe>;
+
+ vdd-supply = <&vreg_l15b_1p8>;
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_HIGH>;
+
+ mode-switch;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ wcd_usbss_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+ };
+};
+
+&i2c6 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-0 = <<9611_irq_pin>, <<9611_rst_pin>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_connector_out>;
+ };
+ };
+ };
+ };
+};
+
+&ipa {
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
+ firmware-name = "qcom/sm8650/ipa_fws.mbn";
+ status = "okay";
+};
+
+&lpass_tlmm {
+ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3i_1p2>;
+
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1i_0p88>;
+
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ data-lanes = <0 1>;
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1i_0p88>;
+ vdda-pll-supply = <&vreg_l3i_1p2>;
+
+ status = "okay";
+};
+
+&pcie1 {
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3e_0p9>;
+ vdda-pll-supply = <&vreg_l3i_1p2>;
+ vdda-qref-supply = <&vreg_l1i_0p88>;
+
+ status = "okay";
+};
+
+&pm8550_gpios {
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio12";
+ function = "normal";
+ bias-pull-up;
+ input-enable;
+ output-disable;
+ power-source = <1>; /* 1.8 V */
+ };
+
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ bias-pull-up;
+ input-enable;
+ power-source = <1>;
+ };
+};
+
+/* The RGB signals are routed to 3 separate LEDs on the HDK8650 */
+&pm8550_pwm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ };
+
+ led@2 {
+ reg = <2>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ };
+
+ led@3 {
+ reg = <3>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_rtc {
+ status = "okay";
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qup_i2c3_data_clk {
+ /* Use internal I2C pull-up */
+ bias-pull-up = <2200>;
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8650/adsp.mbn",
+ "qcom/sm8650/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8650/cdsp.mbn",
+ "qcom/sm8650/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm8650/modem.mbn",
+ "qcom/sm8650/modem_dtb.mbn";
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>;
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&swr0 {
+ status = "okay";
+
+ /* WSA8845, Speaker North */
+ north_spkr: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&lpass_tlmm 21 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l3c_1p2>;
+ };
+
+ /* WSA8845, Speaker South */
+ south_spkr: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ pinctrl-0 = <&spkr_2_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l3c_1p2>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ /* WCD9395 RX */
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010e00";
+ reg = <0 4>;
+
+ /*
+ * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R)
+ * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH)
+ * WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R)
+ * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO)
+ * WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R)
+ * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R)
+ */
+ qcom,rx-port-mapping = <1 2 3 4 5 9>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ /* WCD9395 TX */
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010e00";
+ reg = <0 3>;
+
+ /*
+ * WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
+ * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
+ * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7)
+ * WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11)
+ */
+ qcom,tx-port-mapping = <2 2 3 4>;
+ };
+};
+
+&tlmm {
+ /* Reserved I/Os for NFC */
+ gpio-reserved-ranges = <32 8>, <74 1>;
+
+ bt_default: bt-default-state {
+ bt-en-pins {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sw-ctrl-pins {
+ pins = "gpio18";
+ function = "gpio";
+ bias-pull-down;
+ };
+ };
+
+ lt9611_irq_pin: lt9611-irq-state {
+ pins = "gpio85";
+ function = "gpio";
+ bias-disable;
+ };
+
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio28";
+ function = "gpio";
+ output-high;
+ };
+
+ spkr_2_sd_n_active: spkr-2-sd-n-active-state {
+ pins = "gpio77";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio107";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ vddio-supply = <&vreg_l3c_1p2>;
+ vddaon-supply = <&vreg_l15b_1p8>;
+ vdddig-supply = <&vreg_s3c_0p9>;
+ vddrfa0p8-supply = <&vreg_s3c_0p9>;
+ vddrfa1p2-supply = <&vreg_s1c_1p2>;
+ vddrfa1p9-supply = <&vreg_s6c_1p8>;
+
+ max-speed = <3200000>;
+
+ enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&bt_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&uart15 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1c_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3i_1p2>;
+
+ status = "okay";
+};
+
+/*
+ * DPAUX -> WCD9395 -> USB_SBU -> USB-C
+ * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> WCD9395 -> USB-C
+ * USB SS -> USB-C
+ */
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1i_0p88>;
+ vdda12-supply = <&vreg_l3i_1p2>;
+
+ phys = <&pm8550b_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3i_1p2>;
+ vdda-pll-supply = <&vreg_l3g_0p91>;
+
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_dp_in {
+ remote-endpoint = <&mdss_dp0_out>;
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&usb_dp_qmpphy_usb_ss_in {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
--
2.34.1
^ permalink raw reply related [relevance 9%]
* [PATCH v3 2/3] arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
2024-04-22 8:33 6% ` Neil Armstrong
@ 2024-04-22 8:33 19% ` Neil Armstrong
-1 siblings, 0 replies; 200+ results
From: Neil Armstrong @ 2024-04-22 8:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Neil Armstrong, Dmitry Baryshkov
Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy
provided QMP_PCIE_PHY_AUX_CLK.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 --------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
4 files changed, 4 insertions(+), 25 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 12d60a0ee095..ccff744dcd14 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -979,10 +979,6 @@ &pcie1_phy {
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 3d4ad5aac70f..1fa7c4492057 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -739,10 +739,6 @@ &mdss_dp0_out {
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 92f015017418..da3cfa697969 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -810,10 +810,6 @@ &mdss_dp0_out {
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
-&pcie_1_phy_aux_clk {
- status = "disabled";
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
@@ -907,10 +903,6 @@ &pon_resin {
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&qupv3_id_0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index bc5aeb05ffc3..143994d1e6ca 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -58,11 +58,6 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-mult = <1>;
clock-div = <2>;
};
-
- pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
};
cpus {
@@ -776,8 +771,8 @@ gcc: clock-controller@100000 {
#power-domain-cells = <1>;
clocks = <&bi_tcxo_div2>, <&sleep_clk>,
<&pcie0_phy>,
- <&pcie1_phy>,
- <&pcie_1_phy_aux_clk>,
+ <&pcie1_phy QMP_PCIE_PIPE_CLK>,
+ <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
@@ -1928,8 +1923,8 @@ pcie1_phy: phy@1c0e000 {
power-domains = <&gcc PCIE_1_PHY_GDSC>;
- #clock-cells = <0>;
- clock-output-names = "pcie1_pipe_clk";
+ #clock-cells = <1>;
+ clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";
#phy-cells = <0>;
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [relevance 19%]
* [PATCH v3 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock
@ 2024-04-22 8:33 6% ` Neil Armstrong
0 siblings, 0 replies; 200+ results
From: Neil Armstrong @ 2024-04-22 8:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Neil Armstrong, Dmitry Baryshkov
The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.
Document the clock IDs to select the PIPE clock or the AUX clock,
also enforce a second clock-output-names and a #clock-cells value of 1
for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
The PHY driver needs a light refactoring to support a second clock,
and finally the DT is changed to connect the PHY second clock to the
corresponding GCC input then drop the dummy fixed rate clock.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v3:
- Rebased on linux-next, applies now cleanly
- Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org
Changes in v2:
- Collected review tags
- Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility
- Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code
and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0
when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get()
- Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org
---
Neil Armstrong (3):
arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 --------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++---------
8 files changed, 12 insertions(+), 46 deletions(-)
---
base-commit: f529a6d274b3b8c75899e949649d231298f30a32
change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [relevance 6%]
* [PATCH v3 2/3] arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
@ 2024-04-22 8:33 19% ` Neil Armstrong
0 siblings, 0 replies; 200+ results
From: Neil Armstrong @ 2024-04-22 8:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Neil Armstrong, Dmitry Baryshkov
Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy
provided QMP_PCIE_PHY_AUX_CLK.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 --------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
4 files changed, 4 insertions(+), 25 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 12d60a0ee095..ccff744dcd14 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -979,10 +979,6 @@ &pcie1_phy {
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 3d4ad5aac70f..1fa7c4492057 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -739,10 +739,6 @@ &mdss_dp0_out {
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 92f015017418..da3cfa697969 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -810,10 +810,6 @@ &mdss_dp0_out {
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
-&pcie_1_phy_aux_clk {
- status = "disabled";
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
@@ -907,10 +903,6 @@ &pon_resin {
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&qupv3_id_0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index bc5aeb05ffc3..143994d1e6ca 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -58,11 +58,6 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-mult = <1>;
clock-div = <2>;
};
-
- pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
};
cpus {
@@ -776,8 +771,8 @@ gcc: clock-controller@100000 {
#power-domain-cells = <1>;
clocks = <&bi_tcxo_div2>, <&sleep_clk>,
<&pcie0_phy>,
- <&pcie1_phy>,
- <&pcie_1_phy_aux_clk>,
+ <&pcie1_phy QMP_PCIE_PIPE_CLK>,
+ <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
@@ -1928,8 +1923,8 @@ pcie1_phy: phy@1c0e000 {
power-domains = <&gcc PCIE_1_PHY_GDSC>;
- #clock-cells = <0>;
- clock-output-names = "pcie1_pipe_clk";
+ #clock-cells = <1>;
+ clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk";
#phy-cells = <0>;
--
2.34.1
^ permalink raw reply related [relevance 19%]
* [PATCH v3 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock
@ 2024-04-22 8:33 6% ` Neil Armstrong
0 siblings, 0 replies; 200+ results
From: Neil Armstrong @ 2024-04-22 8:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel,
Neil Armstrong, Dmitry Baryshkov
The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.
Document the clock IDs to select the PIPE clock or the AUX clock,
also enforce a second clock-output-names and a #clock-cells value of 1
for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
The PHY driver needs a light refactoring to support a second clock,
and finally the DT is changed to connect the PHY second clock to the
corresponding GCC input then drop the dummy fixed rate clock.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v3:
- Rebased on linux-next, applies now cleanly
- Link to v2: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org
Changes in v2:
- Collected review tags
- Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility
- Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code
and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0
when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get()
- Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org
---
Neil Armstrong (3):
arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 --------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 ++++---------
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ----
arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++---------
8 files changed, 12 insertions(+), 46 deletions(-)
---
base-commit: f529a6d274b3b8c75899e949649d231298f30a32
change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [relevance 6%]
* [PATCH] docs: driver-api: interconnect: fix typo
@ 2024-04-22 4:29 5% Sekhar Nori
2024-04-22 14:53 0% ` Mike Tipton
0 siblings, 1 reply; 200+ results
From: Sekhar Nori @ 2024-04-22 4:29 UTC (permalink / raw)
To: Mike Tipton, Georgi Djakov
Cc: Jonathan Corbet, linux-pm, linux-doc, Sekhar Nori
Fix typo in debugfs path name that prevents copy-paste of
commands given.
Signed-off-by: Sekhar Nori <nsekhar@google.com>
---
Documentation/driver-api/interconnect.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/driver-api/interconnect.rst b/Documentation/driver-api/interconnect.rst
index a92d0f277a1f..6d0a205b42b7 100644
--- a/Documentation/driver-api/interconnect.rst
+++ b/Documentation/driver-api/interconnect.rst
@@ -119,7 +119,7 @@ any arbitrary path. Note that for safety reasons, this feature is disabled by
default without a Kconfig to enable it. Enabling it requires code changes to
``#define INTERCONNECT_ALLOW_WRITE_DEBUGFS``. Example usage::
- cd /sys/kernel/debug/interconnect/test-client/
+ cd /sys/kernel/debug/interconnect/test_client/
# Configure node endpoints for the path from CPU to DDR on
# qcom/sm8550.
--
2.44.0.769.g3c40516874-goog
^ permalink raw reply related [relevance 5%]
* Re: [PATCH v4 0/2] drm/msm: Add support for the A750 GPU found on the SM8650 platform
@ 2024-04-21 22:29 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2024-04-21 22:29 UTC (permalink / raw)
To: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong
Cc: linux-arm-msm, devicetree, linux-kernel
On Mon, 18 Mar 2024 11:09:44 +0100, Neil Armstrong wrote:
> Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU
> doesn't have an HWCFG block but a separate register set.
>
> The missing registers are added in the a6xx.xml.h file that would
> require a subsequent sync and the non-existent hwcfg is handled
> in a6xx_set_hwcg().
>
> [...]
Applied, thanks!
[1/2] arm64: dts: qcom: sm8650: add GPU nodes
commit: db33633b05c0b57aef197f072826127f65f59ee9
[2/2] arm64: dts: qcom: sm8650-qrd: enable GPU
commit: b8cf87ca7827388ed8d817fadec7ea65aef2a172
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [relevance 0%]
* Re: [PATCH 0/4] clk: qcom: dispcc: fix DisplayPort link clocks
@ 2024-04-20 18:05 0% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2024-04-20 18:05 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Michael Turquette, Stephen Boyd, Konrad Dybcio, Konrad Dybcio,
Neil Armstrong, linux-arm-msm, linux-clk, linux-kernel
On Mon, Apr 08, 2024 at 02:47:03PM +0300, Dmitry Baryshkov wrote:
> On several Qualcomm platforms DisplayPort link clocks used incorrect
> frequency tables. Drop frequency tables and use clk_byte2_ops instead of
> clk_rcg2_ops.
>
> Note, this was tested on SM8450 only and then extended to other
> platforms.
>
As Stephen points out, it seems from the commit messages that this just
cleans up the code because it's wrong. But both Luca and Neil points out
that it resolves a visible issue/error.
Can we please have this (the actual problem being resolved) captured in
the commit messages?
Regards,
Bjorn
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> Dmitry Baryshkov (4):
> clk: qcom: dispcc-sm8450: fix DisplayPort clocks
> clk: qcom: dispcc-sm6350: fix DisplayPort clocks
> clk: qcom: dispcc-sm8550: fix DisplayPort clocks
> clk: qcom: dispcc-sm8650: fix DisplayPort clocks
>
> drivers/clk/qcom/dispcc-sm6350.c | 11 +----------
> drivers/clk/qcom/dispcc-sm8450.c | 20 ++++----------------
> drivers/clk/qcom/dispcc-sm8550.c | 20 ++++----------------
> drivers/clk/qcom/dispcc-sm8650.c | 20 ++++----------------
> 4 files changed, 13 insertions(+), 58 deletions(-)
> ---
> base-commit: 8568bb2ccc278f344e6ac44af6ed010a90aa88dc
> change-id: 20240408-dispcc-dp-clocks-5ee5d5926346
>
> Best regards,
> --
> Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
^ permalink raw reply [relevance 0%]
* [GIT PULL] Qualcomm Arm64 DeviceTree fixes for v6.9
@ 2024-04-20 16:10 6% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2024-04-20 16:10 UTC (permalink / raw)
To: arm, soc
Cc: linux-arm-msm, linux-arm-kernel, Andy Gross, Arnd Bergmann,
Olof Johansson, Kevin Hilman, Manivannan Sadhasivam,
Johan Hovold, Luca Weiss, Maximilian Luz, Rajendra Nayak
The following changes since commit 4cece764965020c22cff7665b18a012006359095:
Linux 6.9-rc1 (2024-03-24 14:10:05 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-arm64-fixes-for-6.9
for you to fetch changes up to ecda8309098402f878c96184f29a1b7ec682d772:
arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller (2024-04-12 12:21:47 -0500)
----------------------------------------------------------------
Qualcomm Arm64 DeviceTree fixes for v6.9
This corrects the watchdog IRQ flags for a number of remoteproc
instances, which otherwise prevents the driver from probe in the face of
a probe deferral.
Improvements in other areas, such as USB, have made it possible for CX
rail voltage on SC8280XP to be lowered, no longer meeting requirements
of active PCIe controllers. Necessary votes are added to these
controllers.
The MSI definitions for PCIe controllers in SM8450, SM8550, and SM8650
was incorrect, due to a bug in the driver. As this has now been fixed
the definition needs to be corrected.
Lastly, the SuperSpeed PHY irq of the second USB controller in SC8180x,
and the compatible string for X1 Elite domain idle states are corrected.
----------------------------------------------------------------
Johan Hovold (1):
arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
Luca Weiss (1):
arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocs
Manivannan Sadhasivam (3):
arm64: dts: qcom: sm8450: Fix the msi-map entries
arm64: dts: qcom: sm8550: Fix the msi-map entries
arm64: dts: qcom: sm8650: Fix the msi-map entries
Maximilian Luz (1):
arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller
Rajendra Nayak (1):
arm64: dts: qcom: x1e80100: Fix the compatible for cluster idle states
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 11 ++++++++---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm6375.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 16 ++++------------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++++------
arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++++------
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 4 ++--
10 files changed, 31 insertions(+), 38 deletions(-)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 6%]
* [GIT PULL] Qualcomm Arm64 DeviceTree fixes for v6.9
@ 2024-04-20 16:10 6% ` Bjorn Andersson
0 siblings, 0 replies; 200+ results
From: Bjorn Andersson @ 2024-04-20 16:10 UTC (permalink / raw)
To: arm, soc
Cc: linux-arm-msm, linux-arm-kernel, Andy Gross, Arnd Bergmann,
Olof Johansson, Kevin Hilman, Manivannan Sadhasivam,
Johan Hovold, Luca Weiss, Maximilian Luz, Rajendra Nayak
The following changes since commit 4cece764965020c22cff7665b18a012006359095:
Linux 6.9-rc1 (2024-03-24 14:10:05 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-arm64-fixes-for-6.9
for you to fetch changes up to ecda8309098402f878c96184f29a1b7ec682d772:
arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller (2024-04-12 12:21:47 -0500)
----------------------------------------------------------------
Qualcomm Arm64 DeviceTree fixes for v6.9
This corrects the watchdog IRQ flags for a number of remoteproc
instances, which otherwise prevents the driver from probe in the face of
a probe deferral.
Improvements in other areas, such as USB, have made it possible for CX
rail voltage on SC8280XP to be lowered, no longer meeting requirements
of active PCIe controllers. Necessary votes are added to these
controllers.
The MSI definitions for PCIe controllers in SM8450, SM8550, and SM8650
was incorrect, due to a bug in the driver. As this has now been fixed
the definition needs to be corrected.
Lastly, the SuperSpeed PHY irq of the second USB controller in SC8180x,
and the compatible string for X1 Elite domain idle states are corrected.
----------------------------------------------------------------
Johan Hovold (1):
arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
Luca Weiss (1):
arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocs
Manivannan Sadhasivam (3):
arm64: dts: qcom: sm8450: Fix the msi-map entries
arm64: dts: qcom: sm8550: Fix the msi-map entries
arm64: dts: qcom: sm8650: Fix the msi-map entries
Maximilian Luz (1):
arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller
Rajendra Nayak (1):
arm64: dts: qcom: x1e80100: Fix the compatible for cluster idle states
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 11 ++++++++---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm6375.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 16 ++++------------
arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++++------
arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++++------
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 4 ++--
10 files changed, 31 insertions(+), 38 deletions(-)
^ permalink raw reply [relevance 6%]
* Re: [PATCH v5 5/6] soc: qcom: add pd-mapper implementation
2024-04-19 18:15 0% ` Krzysztof Kozlowski
@ 2024-04-19 18:24 0% ` Dmitry Baryshkov
0 siblings, 0 replies; 200+ results
From: Dmitry Baryshkov @ 2024-04-19 18:24 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Konrad Dybcio, Mathieu Poirier, Sibi Sankar,
Bartosz Golaszewski, linux-arm-msm, linux-remoteproc,
Johan Hovold, Xilin Wu
On Fri, 19 Apr 2024 at 21:15, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 19/04/2024 20:10, Dmitry Baryshkov wrote:
> > On Fri, 19 Apr 2024 at 20:07, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>
> >> On 19/04/2024 16:00, Dmitry Baryshkov wrote:
> >>> Existing userspace protection domain mapper implementation has several
> >>> issue. It doesn't play well with CONFIG_EXTRA_FIRMWARE, it doesn't
> >>> reread JSON files if firmware location is changed (or if firmware was
> >>> not available at the time pd-mapper was started but the corresponding
> >>> directory is mounted later), etc.
> >>>
> >>> Provide in-kernel service implementing protection domain mapping
> >>> required to work with several services, which are provided by the DSP
> >>> firmware.
> >>>
> >>
> >> ...
> >>
> >>> +
> >>> +static const struct of_device_id qcom_pdm_domains[] = {
> >>> + { .compatible = "qcom,apq8096", .data = msm8996_domains, },
> >>> + { .compatible = "qcom,msm8996", .data = msm8996_domains, },
> >>> + { .compatible = "qcom,msm8998", .data = msm8998_domains, },
> >>> + { .compatible = "qcom,qcm2290", .data = qcm2290_domains, },
> >>> + { .compatible = "qcom,qcs404", .data = qcs404_domains, },
> >>> + { .compatible = "qcom,sc7180", .data = sc7180_domains, },
> >>> + { .compatible = "qcom,sc7280", .data = sc7280_domains, },
> >>> + { .compatible = "qcom,sc8180x", .data = sc8180x_domains, },
> >>> + { .compatible = "qcom,sc8280xp", .data = sc8280xp_domains, },
> >>> + { .compatible = "qcom,sda660", .data = sdm660_domains, },
> >>> + { .compatible = "qcom,sdm660", .data = sdm660_domains, },
> >>> + { .compatible = "qcom,sdm670", .data = sdm670_domains, },
> >>> + { .compatible = "qcom,sdm845", .data = sdm845_domains, },
> >>> + { .compatible = "qcom,sm6115", .data = sm6115_domains, },
> >>> + { .compatible = "qcom,sm6350", .data = sm6350_domains, },
> >>> + { .compatible = "qcom,sm8150", .data = sm8150_domains, },
> >>> + { .compatible = "qcom,sm8250", .data = sm8250_domains, },
> >>> + { .compatible = "qcom,sm8350", .data = sm8350_domains, },
> >>> + { .compatible = "qcom,sm8450", .data = sm8350_domains, },
> >>> + { .compatible = "qcom,sm8550", .data = sm8550_domains, },
> >>> + { .compatible = "qcom,sm8650", .data = sm8550_domains, },
> >>> + {},
> >>> +};
> >>
> >> If this is supposed to be a module, then why no MODULE_DEVICE_TABLE?
> >
> > Ok, I should add this to the commit message.
> >
> > For now:
> >
> > This module is loaded automatically by the remoteproc drivers when
>
> Hm? How remoteproc loads this module?
remoteproc drivers call qcom_pdm_start(). This brings in this module
via symbol deps.
>
> > necessary. It uses a root node to match a protection domains map for a
> > particular device.
> >
> >>
> >>> +
> >>> +static int qcom_pdm_start(void)
> >>> +{
> >>> + const struct of_device_id *match;
> >>> + const struct qcom_pdm_domain_data * const *domains;
> >>> + struct device_node *root;
> >>> + int ret, i;
> >>> +
> >>> + pr_debug("PDM: starting service\n");
> >>
> >> Drop simple entry/exit debug messages.
> >
> > ack
> >
> >>
> >>> +
> >>> + root = of_find_node_by_path("/");
> >>> + if (!root)
> >>> + return -ENODEV;
> >>> +
> >>> + match = of_match_node(qcom_pdm_domains, root);
> >>> + of_node_put(root);
> >>> + if (!match) {
> >>> + pr_notice("PDM: no support for the platform, userspace daemon might be required.\n");
> >>> + return 0;
> >>> + }
> >>> +
> >>> + domains = match->data;
> >>
> >> All this is odd a bit. Why is this not a driver? You are open coding
> >> here of_device_get_match_data().
> >
> > Except that it matches the root node instead of matching a device.
>
> Yep, but if this was proper device then things get simpler, don't they?
I don't think we are supposed to have devices for software things?
This is purely a software construct. It replaces userspace daemon for
the reason outlined in the cover letter, but other than that there is
no hardware entity. Not even a firmware entity to drive this thing.
> >>> +
> >>> + if (!ret)
> >>> + ++qcom_pdm_count;
> >>> +
> >>> + mutex_unlock(&qcom_pdm_mutex);
> >>
> >> Looks like you implement refcnt manually...
> >
> > Yes... There is refcount_dec_and_mutex_lock(), but I found no
> > corresponding refcount_add_and_mutex_lock(). Maybe I'm
> > misunderstanding that framework.
> > I need to have a mutex after incrementing the lock from 0, so that the
> > driver can init QMI handlers.
> >
> >> Also, what happens if this module gets unloaded? How do you handle
> >> module dependencies? I don't see any device links. Bartosz won't be
> >> happy... We really need to stop adding more of
> >> old-style-buggy-never-unload-logic. At least for new code.
> >
> > Module dependencies are handled by the symbol dependencies.
>
> You mean build dependencies, not runtime load.
No, I mean runtime load dependencies.
>
> > Remoteproc module depends on this symbol. Once q6v5 remoteproc modules
> > are unloaded this module can be unloaded too.
>
> I am pretty sure you can unload this and get crashes.
If for some reason somebody has called qcom_pdm_get() without
qcom_pdm_release(), then yes. To make it 100% safe, I can cleanup
actions to module_exit(), but for me it looks like an overkill.
--
With best wishes
Dmitry
^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 5/6] soc: qcom: add pd-mapper implementation
2024-04-19 18:10 0% ` Dmitry Baryshkov
@ 2024-04-19 18:15 0% ` Krzysztof Kozlowski
2024-04-19 18:24 0% ` Dmitry Baryshkov
0 siblings, 1 reply; 200+ results
From: Krzysztof Kozlowski @ 2024-04-19 18:15 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Mathieu Poirier, Sibi Sankar,
Bartosz Golaszewski, linux-arm-msm, linux-remoteproc,
Johan Hovold, Xilin Wu
On 19/04/2024 20:10, Dmitry Baryshkov wrote:
> On Fri, 19 Apr 2024 at 20:07, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On 19/04/2024 16:00, Dmitry Baryshkov wrote:
>>> Existing userspace protection domain mapper implementation has several
>>> issue. It doesn't play well with CONFIG_EXTRA_FIRMWARE, it doesn't
>>> reread JSON files if firmware location is changed (or if firmware was
>>> not available at the time pd-mapper was started but the corresponding
>>> directory is mounted later), etc.
>>>
>>> Provide in-kernel service implementing protection domain mapping
>>> required to work with several services, which are provided by the DSP
>>> firmware.
>>>
>>
>> ...
>>
>>> +
>>> +static const struct of_device_id qcom_pdm_domains[] = {
>>> + { .compatible = "qcom,apq8096", .data = msm8996_domains, },
>>> + { .compatible = "qcom,msm8996", .data = msm8996_domains, },
>>> + { .compatible = "qcom,msm8998", .data = msm8998_domains, },
>>> + { .compatible = "qcom,qcm2290", .data = qcm2290_domains, },
>>> + { .compatible = "qcom,qcs404", .data = qcs404_domains, },
>>> + { .compatible = "qcom,sc7180", .data = sc7180_domains, },
>>> + { .compatible = "qcom,sc7280", .data = sc7280_domains, },
>>> + { .compatible = "qcom,sc8180x", .data = sc8180x_domains, },
>>> + { .compatible = "qcom,sc8280xp", .data = sc8280xp_domains, },
>>> + { .compatible = "qcom,sda660", .data = sdm660_domains, },
>>> + { .compatible = "qcom,sdm660", .data = sdm660_domains, },
>>> + { .compatible = "qcom,sdm670", .data = sdm670_domains, },
>>> + { .compatible = "qcom,sdm845", .data = sdm845_domains, },
>>> + { .compatible = "qcom,sm6115", .data = sm6115_domains, },
>>> + { .compatible = "qcom,sm6350", .data = sm6350_domains, },
>>> + { .compatible = "qcom,sm8150", .data = sm8150_domains, },
>>> + { .compatible = "qcom,sm8250", .data = sm8250_domains, },
>>> + { .compatible = "qcom,sm8350", .data = sm8350_domains, },
>>> + { .compatible = "qcom,sm8450", .data = sm8350_domains, },
>>> + { .compatible = "qcom,sm8550", .data = sm8550_domains, },
>>> + { .compatible = "qcom,sm8650", .data = sm8550_domains, },
>>> + {},
>>> +};
>>
>> If this is supposed to be a module, then why no MODULE_DEVICE_TABLE?
>
> Ok, I should add this to the commit message.
>
> For now:
>
> This module is loaded automatically by the remoteproc drivers when
Hm? How remoteproc loads this module?
> necessary. It uses a root node to match a protection domains map for a
> particular device.
>
>>
>>> +
>>> +static int qcom_pdm_start(void)
>>> +{
>>> + const struct of_device_id *match;
>>> + const struct qcom_pdm_domain_data * const *domains;
>>> + struct device_node *root;
>>> + int ret, i;
>>> +
>>> + pr_debug("PDM: starting service\n");
>>
>> Drop simple entry/exit debug messages.
>
> ack
>
>>
>>> +
>>> + root = of_find_node_by_path("/");
>>> + if (!root)
>>> + return -ENODEV;
>>> +
>>> + match = of_match_node(qcom_pdm_domains, root);
>>> + of_node_put(root);
>>> + if (!match) {
>>> + pr_notice("PDM: no support for the platform, userspace daemon might be required.\n");
>>> + return 0;
>>> + }
>>> +
>>> + domains = match->data;
>>
>> All this is odd a bit. Why is this not a driver? You are open coding
>> here of_device_get_match_data().
>
> Except that it matches the root node instead of matching a device.
Yep, but if this was proper device then things get simpler, don't they?
...
>>> +
>>> + if (!ret)
>>> + ++qcom_pdm_count;
>>> +
>>> + mutex_unlock(&qcom_pdm_mutex);
>>
>> Looks like you implement refcnt manually...
>
> Yes... There is refcount_dec_and_mutex_lock(), but I found no
> corresponding refcount_add_and_mutex_lock(). Maybe I'm
> misunderstanding that framework.
> I need to have a mutex after incrementing the lock from 0, so that the
> driver can init QMI handlers.
>
>> Also, what happens if this module gets unloaded? How do you handle
>> module dependencies? I don't see any device links. Bartosz won't be
>> happy... We really need to stop adding more of
>> old-style-buggy-never-unload-logic. At least for new code.
>
> Module dependencies are handled by the symbol dependencies.
You mean build dependencies, not runtime load.
> Remoteproc module depends on this symbol. Once q6v5 remoteproc modules
> are unloaded this module can be unloaded too.
I am pretty sure you can unload this and get crashes.
Best regards,
Krzysztof
^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 5/6] soc: qcom: add pd-mapper implementation
2024-04-19 17:07 0% ` Krzysztof Kozlowski
@ 2024-04-19 18:10 0% ` Dmitry Baryshkov
2024-04-19 18:15 0% ` Krzysztof Kozlowski
0 siblings, 1 reply; 200+ results
From: Dmitry Baryshkov @ 2024-04-19 18:10 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Konrad Dybcio, Mathieu Poirier, Sibi Sankar,
Bartosz Golaszewski, linux-arm-msm, linux-remoteproc,
Johan Hovold, Xilin Wu
On Fri, 19 Apr 2024 at 20:07, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 19/04/2024 16:00, Dmitry Baryshkov wrote:
> > Existing userspace protection domain mapper implementation has several
> > issue. It doesn't play well with CONFIG_EXTRA_FIRMWARE, it doesn't
> > reread JSON files if firmware location is changed (or if firmware was
> > not available at the time pd-mapper was started but the corresponding
> > directory is mounted later), etc.
> >
> > Provide in-kernel service implementing protection domain mapping
> > required to work with several services, which are provided by the DSP
> > firmware.
> >
>
> ...
>
> > +
> > +static const struct of_device_id qcom_pdm_domains[] = {
> > + { .compatible = "qcom,apq8096", .data = msm8996_domains, },
> > + { .compatible = "qcom,msm8996", .data = msm8996_domains, },
> > + { .compatible = "qcom,msm8998", .data = msm8998_domains, },
> > + { .compatible = "qcom,qcm2290", .data = qcm2290_domains, },
> > + { .compatible = "qcom,qcs404", .data = qcs404_domains, },
> > + { .compatible = "qcom,sc7180", .data = sc7180_domains, },
> > + { .compatible = "qcom,sc7280", .data = sc7280_domains, },
> > + { .compatible = "qcom,sc8180x", .data = sc8180x_domains, },
> > + { .compatible = "qcom,sc8280xp", .data = sc8280xp_domains, },
> > + { .compatible = "qcom,sda660", .data = sdm660_domains, },
> > + { .compatible = "qcom,sdm660", .data = sdm660_domains, },
> > + { .compatible = "qcom,sdm670", .data = sdm670_domains, },
> > + { .compatible = "qcom,sdm845", .data = sdm845_domains, },
> > + { .compatible = "qcom,sm6115", .data = sm6115_domains, },
> > + { .compatible = "qcom,sm6350", .data = sm6350_domains, },
> > + { .compatible = "qcom,sm8150", .data = sm8150_domains, },
> > + { .compatible = "qcom,sm8250", .data = sm8250_domains, },
> > + { .compatible = "qcom,sm8350", .data = sm8350_domains, },
> > + { .compatible = "qcom,sm8450", .data = sm8350_domains, },
> > + { .compatible = "qcom,sm8550", .data = sm8550_domains, },
> > + { .compatible = "qcom,sm8650", .data = sm8550_domains, },
> > + {},
> > +};
>
> If this is supposed to be a module, then why no MODULE_DEVICE_TABLE?
Ok, I should add this to the commit message.
For now:
This module is loaded automatically by the remoteproc drivers when
necessary. It uses a root node to match a protection domains map for a
particular device.
>
> > +
> > +static int qcom_pdm_start(void)
> > +{
> > + const struct of_device_id *match;
> > + const struct qcom_pdm_domain_data * const *domains;
> > + struct device_node *root;
> > + int ret, i;
> > +
> > + pr_debug("PDM: starting service\n");
>
> Drop simple entry/exit debug messages.
ack
>
> > +
> > + root = of_find_node_by_path("/");
> > + if (!root)
> > + return -ENODEV;
> > +
> > + match = of_match_node(qcom_pdm_domains, root);
> > + of_node_put(root);
> > + if (!match) {
> > + pr_notice("PDM: no support for the platform, userspace daemon might be required.\n");
> > + return 0;
> > + }
> > +
> > + domains = match->data;
>
> All this is odd a bit. Why is this not a driver? You are open coding
> here of_device_get_match_data().
Except that it matches the root node instead of matching a device.
>
>
> > + if (!domains) {
> > + pr_debug("PDM: no domains\n");
> > + return 0;
> > + }
> > +
> > + for (i = 0; domains[i]; i++) {
> > + ret = qcom_pdm_add_domain(domains[i]);
> > + if (ret)
> > + goto free_domains;
> > + }
> > +
> > + ret = qmi_handle_init(&qcom_pdm_handle, 1024,
> > + NULL, qcom_pdm_msg_handlers);
> > + if (ret)
> > + goto free_domains;
> > +
> > + ret = qmi_add_server(&qcom_pdm_handle, SERVREG_LOCATOR_SERVICE,
> > + SERVREG_QMI_VERSION, SERVREG_QMI_INSTANCE);
> > + if (ret) {
> > + pr_err("PDM: error adding server %d\n", ret);
> > + goto release_handle;
> > + }
> > +
> > + return 0;
> > +
> > +release_handle:
> > + qmi_handle_release(&qcom_pdm_handle);
> > +
> > +free_domains:
> > + qcom_pdm_free_domains();
> > +
> > + return ret;
> > +}
> > +
> > +static void qcom_pdm_stop(void)
> > +{
> > + qmi_del_server(&qcom_pdm_handle, SERVREG_LOCATOR_SERVICE,
> > + SERVREG_QMI_VERSION, SERVREG_QMI_INSTANCE);
> > +
> > + qmi_handle_release(&qcom_pdm_handle);
> > +
> > + qcom_pdm_free_domains();
> > +
> > + WARN_ON(!list_empty(&qcom_pdm_services));
>
> This should be handled, not warned.
I'll just drop it, qcom_pdm_free_domains() should free them.
>
> > +
> > + pr_debug("PDM: stopped service\n");
>
> Drop debug. Tracing gives you such information.
>
> > +}
> > +
> > +/**
> > + * qcom_pdm_get() - ensure that PD mapper is up and running
> > + */
>
> Please provide full kerneldoc, so also return and short description.
>
> > +int qcom_pdm_get(void)
> > +{
> > + int ret = 0;
> > +
> > + mutex_lock(&qcom_pdm_mutex);
> > +
> > + if (!qcom_pdm_count)
> > + ret = qcom_pdm_start();
> > +
> > + if (!ret)
> > + ++qcom_pdm_count;
> > +
> > + mutex_unlock(&qcom_pdm_mutex);
>
> Looks like you implement refcnt manually...
Yes... There is refcount_dec_and_mutex_lock(), but I found no
corresponding refcount_add_and_mutex_lock(). Maybe I'm
misunderstanding that framework.
I need to have a mutex after incrementing the lock from 0, so that the
driver can init QMI handlers.
> Also, what happens if this module gets unloaded? How do you handle
> module dependencies? I don't see any device links. Bartosz won't be
> happy... We really need to stop adding more of
> old-style-buggy-never-unload-logic. At least for new code.
Module dependencies are handled by the symbol dependencies.
Remoteproc module depends on this symbol. Once q6v5 remoteproc modules
are unloaded this module can be unloaded too.
But I know what got missing. I should add 'depends on PD_MAPPER ||
!PD_MAPPER' to remoteproc Kconfig entries.
>
> > +
> > + return ret;
> > +}
>
> No export? Isn't this a module?
Ack, missed them.
>
> > +
> > +/**
> > + * qcom_pdm_release() - possibly stop PD mapper service
> > + */
> > +void qcom_pdm_release(void)
> > +{
>
> Best regards,
> Krzysztof
>
--
With best wishes
Dmitry
^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 5/6] soc: qcom: add pd-mapper implementation
2024-04-19 14:00 2% ` [PATCH v5 5/6] soc: qcom: add " Dmitry Baryshkov
@ 2024-04-19 17:07 0% ` Krzysztof Kozlowski
2024-04-19 18:10 0% ` Dmitry Baryshkov
0 siblings, 1 reply; 200+ results
From: Krzysztof Kozlowski @ 2024-04-19 17:07 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Konrad Dybcio,
Mathieu Poirier, Sibi Sankar, Bartosz Golaszewski
Cc: linux-arm-msm, linux-remoteproc, Johan Hovold, Xilin Wu
On 19/04/2024 16:00, Dmitry Baryshkov wrote:
> Existing userspace protection domain mapper implementation has several
> issue. It doesn't play well with CONFIG_EXTRA_FIRMWARE, it doesn't
> reread JSON files if firmware location is changed (or if firmware was
> not available at the time pd-mapper was started but the corresponding
> directory is mounted later), etc.
>
> Provide in-kernel service implementing protection domain mapping
> required to work with several services, which are provided by the DSP
> firmware.
>
...
> +
> +static const struct of_device_id qcom_pdm_domains[] = {
> + { .compatible = "qcom,apq8096", .data = msm8996_domains, },
> + { .compatible = "qcom,msm8996", .data = msm8996_domains, },
> + { .compatible = "qcom,msm8998", .data = msm8998_domains, },
> + { .compatible = "qcom,qcm2290", .data = qcm2290_domains, },
> + { .compatible = "qcom,qcs404", .data = qcs404_domains, },
> + { .compatible = "qcom,sc7180", .data = sc7180_domains, },
> + { .compatible = "qcom,sc7280", .data = sc7280_domains, },
> + { .compatible = "qcom,sc8180x", .data = sc8180x_domains, },
> + { .compatible = "qcom,sc8280xp", .data = sc8280xp_domains, },
> + { .compatible = "qcom,sda660", .data = sdm660_domains, },
> + { .compatible = "qcom,sdm660", .data = sdm660_domains, },
> + { .compatible = "qcom,sdm670", .data = sdm670_domains, },
> + { .compatible = "qcom,sdm845", .data = sdm845_domains, },
> + { .compatible = "qcom,sm6115", .data = sm6115_domains, },
> + { .compatible = "qcom,sm6350", .data = sm6350_domains, },
> + { .compatible = "qcom,sm8150", .data = sm8150_domains, },
> + { .compatible = "qcom,sm8250", .data = sm8250_domains, },
> + { .compatible = "qcom,sm8350", .data = sm8350_domains, },
> + { .compatible = "qcom,sm8450", .data = sm8350_domains, },
> + { .compatible = "qcom,sm8550", .data = sm8550_domains, },
> + { .compatible = "qcom,sm8650", .data = sm8550_domains, },
> + {},
> +};
If this is supposed to be a module, then why no MODULE_DEVICE_TABLE?
> +
> +static int qcom_pdm_start(void)
> +{
> + const struct of_device_id *match;
> + const struct qcom_pdm_domain_data * const *domains;
> + struct device_node *root;
> + int ret, i;
> +
> + pr_debug("PDM: starting service\n");
Drop simple entry/exit debug messages.
> +
> + root = of_find_node_by_path("/");
> + if (!root)
> + return -ENODEV;
> +
> + match = of_match_node(qcom_pdm_domains, root);
> + of_node_put(root);
> + if (!match) {
> + pr_notice("PDM: no support for the platform, userspace daemon might be required.\n");
> + return 0;
> + }
> +
> + domains = match->data;
All this is odd a bit. Why is this not a driver? You are open coding
here of_device_get_match_data().
> + if (!domains) {
> + pr_debug("PDM: no domains\n");
> + return 0;
> + }
> +
> + for (i = 0; domains[i]; i++) {
> + ret = qcom_pdm_add_domain(domains[i]);
> + if (ret)
> + goto free_domains;
> + }
> +
> + ret = qmi_handle_init(&qcom_pdm_handle, 1024,
> + NULL, qcom_pdm_msg_handlers);
> + if (ret)
> + goto free_domains;
> +
> + ret = qmi_add_server(&qcom_pdm_handle, SERVREG_LOCATOR_SERVICE,
> + SERVREG_QMI_VERSION, SERVREG_QMI_INSTANCE);
> + if (ret) {
> + pr_err("PDM: error adding server %d\n", ret);
> + goto release_handle;
> + }
> +
> + return 0;
> +
> +release_handle:
> + qmi_handle_release(&qcom_pdm_handle);
> +
> +free_domains:
> + qcom_pdm_free_domains();
> +
> + return ret;
> +}
> +
> +static void qcom_pdm_stop(void)
> +{
> + qmi_del_server(&qcom_pdm_handle, SERVREG_LOCATOR_SERVICE,
> + SERVREG_QMI_VERSION, SERVREG_QMI_INSTANCE);
> +
> + qmi_handle_release(&qcom_pdm_handle);
> +
> + qcom_pdm_free_domains();
> +
> + WARN_ON(!list_empty(&qcom_pdm_services));
This should be handled, not warned.
> +
> + pr_debug("PDM: stopped service\n");
Drop debug. Tracing gives you such information.
> +}
> +
> +/**
> + * qcom_pdm_get() - ensure that PD mapper is up and running
> + */
Please provide full kerneldoc, so also return and short description.
> +int qcom_pdm_get(void)
> +{
> + int ret = 0;
> +
> + mutex_lock(&qcom_pdm_mutex);
> +
> + if (!qcom_pdm_count)
> + ret = qcom_pdm_start();
> +
> + if (!ret)
> + ++qcom_pdm_count;
> +
> + mutex_unlock(&qcom_pdm_mutex);
Looks like you implement refcnt manually...
Also, what happens if this module gets unloaded? How do you handle
module dependencies? I don't see any device links. Bartosz won't be
happy... We really need to stop adding more of
old-style-buggy-never-unload-logic. At least for new code.
> +
> + return ret;
> +}
No export? Isn't this a module?
> +
> +/**
> + * qcom_pdm_release() - possibly stop PD mapper service
> + */
> +void qcom_pdm_release(void)
> +{
Best regards,
Krzysztof
^ permalink raw reply [relevance 0%]
* [PATCH v5 5/6] soc: qcom: add pd-mapper implementation
@ 2024-04-19 14:00 2% ` Dmitry Baryshkov
2024-04-19 17:07 0% ` Krzysztof Kozlowski
0 siblings, 1 reply; 200+ results
From: Dmitry Baryshkov @ 2024-04-19 14:00 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Mathieu Poirier, Sibi Sankar
Cc: linux-arm-msm, linux-remoteproc, Johan Hovold, Xilin Wu
Existing userspace protection domain mapper implementation has several
issue. It doesn't play well with CONFIG_EXTRA_FIRMWARE, it doesn't
reread JSON files if firmware location is changed (or if firmware was
not available at the time pd-mapper was started but the corresponding
directory is mounted later), etc.
Provide in-kernel service implementing protection domain mapping
required to work with several services, which are provided by the DSP
firmware.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/soc/qcom/Kconfig | 11 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/pdr_internal.h | 14 +
drivers/soc/qcom/qcom_pd_mapper.c | 632 +++++++++++++++++++++++++++++++++++++
drivers/soc/qcom/qcom_pdr_msg.c | 34 ++
include/linux/soc/qcom/pd_mapper.h | 28 ++
6 files changed, 720 insertions(+)
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 95973c6b828f..0a2f2bfd7863 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -72,6 +72,17 @@ config QCOM_OCMEM
requirements. This is typically used by the GPU, camera/video, and
audio components on some Snapdragon SoCs.
+config QCOM_PD_MAPPER
+ tristate "Qualcomm Protection Domain Mapper"
+ select QCOM_QMI_HELPERS
+ depends on NET && QRTR
+ default QCOM_RPROC_COMMON
+ help
+ The Protection Domain Mapper maps registered services to the domains
+ and instances handled by the remote DSPs. This is a kernel-space
+ implementation of the service. It is a simpler alternative to the
+ userspace daemon.
+
config QCOM_PDR_HELPERS
tristate
select QCOM_QMI_HELPERS
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 3110ac3288bc..d3560f861085 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
obj-$(CONFIG_QCOM_OCMEM) += ocmem.o
+obj-$(CONFIG_QCOM_PD_MAPPER) += qcom_pd_mapper.o
obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o
obj-$(CONFIG_QCOM_PDR_MSG) += qcom_pdr_msg.o
obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink.o
diff --git a/drivers/soc/qcom/pdr_internal.h b/drivers/soc/qcom/pdr_internal.h
index 7e5bb5a95275..8d17f7fb79e7 100644
--- a/drivers/soc/qcom/pdr_internal.h
+++ b/drivers/soc/qcom/pdr_internal.h
@@ -13,6 +13,8 @@
#define SERVREG_SET_ACK_REQ 0x23
#define SERVREG_RESTART_PD_REQ 0x24
+#define SERVREG_LOC_PFR_REQ 0x24
+
#define SERVREG_DOMAIN_LIST_LENGTH 32
#define SERVREG_RESTART_PD_REQ_MAX_LEN 67
#define SERVREG_REGISTER_LISTENER_REQ_LEN 71
@@ -20,6 +22,7 @@
#define SERVREG_GET_DOMAIN_LIST_REQ_MAX_LEN 74
#define SERVREG_STATE_UPDATED_IND_MAX_LEN 79
#define SERVREG_GET_DOMAIN_LIST_RESP_MAX_LEN 2389
+#define SERVREG_LOC_PFR_RESP_MAX_LEN 10
struct servreg_location_entry {
char name[SERVREG_NAME_LENGTH + 1];
@@ -79,6 +82,15 @@ struct servreg_set_ack_resp {
struct qmi_response_type_v01 resp;
};
+struct servreg_loc_pfr_req {
+ char service[SERVREG_NAME_LENGTH + 1];
+ char reason[257];
+};
+
+struct servreg_loc_pfr_resp {
+ struct qmi_response_type_v01 rsp;
+};
+
extern const struct qmi_elem_info servreg_location_entry_ei[];
extern const struct qmi_elem_info servreg_get_domain_list_req_ei[];
extern const struct qmi_elem_info servreg_get_domain_list_resp_ei[];
@@ -89,5 +101,7 @@ extern const struct qmi_elem_info servreg_restart_pd_resp_ei[];
extern const struct qmi_elem_info servreg_state_updated_ind_ei[];
extern const struct qmi_elem_info servreg_set_ack_req_ei[];
extern const struct qmi_elem_info servreg_set_ack_resp_ei[];
+extern const struct qmi_elem_info servreg_loc_pfr_req_ei[];
+extern const struct qmi_elem_info servreg_loc_pfr_resp_ei[];
#endif
diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c
new file mode 100644
index 000000000000..b2a8b1f41964
--- /dev/null
+++ b/drivers/soc/qcom/qcom_pd_mapper.c
@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Qualcomm Protection Domain mapper
+ *
+ * Copyright (c) 2023 Linaro Ltd.
+ */
+
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/soc/qcom/pd_mapper.h>
+#include <linux/soc/qcom/qmi.h>
+
+#include "pdr_internal.h"
+
+#define SERVREG_QMI_VERSION 0x101
+#define SERVREG_QMI_INSTANCE 0
+
+#define TMS_SERVREG_SERVICE "tms/servreg"
+
+struct qcom_pdm_domain_data {
+ const char *domain;
+ u32 instance_id;
+ /* NULL-terminated array */
+ const char * services[];
+};
+
+struct qcom_pdm_domain {
+ struct list_head list;
+ const char *name;
+ u32 instance_id;
+};
+
+struct qcom_pdm_service {
+ struct list_head list;
+ struct list_head domains;
+ const char *name;
+};
+
+static DEFINE_MUTEX(qcom_pdm_mutex);
+static LIST_HEAD(qcom_pdm_services);
+static int qcom_pdm_count;
+static struct qmi_handle qcom_pdm_handle;
+
+static struct qcom_pdm_service *qcom_pdm_find(const char *name)
+{
+ struct qcom_pdm_service *service;
+
+ list_for_each_entry(service, &qcom_pdm_services, list) {
+ if (!strcmp(service->name, name))
+ return service;
+ }
+
+ return NULL;
+}
+
+static int qcom_pdm_add_service_domain(const char *service_name,
+ const char *domain_name,
+ u32 instance_id)
+{
+ struct qcom_pdm_service *service;
+ struct qcom_pdm_domain *domain;
+
+ service = qcom_pdm_find(service_name);
+ if (service) {
+ list_for_each_entry(domain, &service->domains, list) {
+ if (!strcmp(domain->name, domain_name))
+ return -EBUSY;
+ }
+ } else {
+ service = kzalloc(sizeof(*service), GFP_KERNEL);
+ if (!service)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&service->domains);
+ service->name = service_name;
+
+ list_add_tail(&service->list, &qcom_pdm_services);
+ }
+
+ domain = kzalloc(sizeof(*domain), GFP_KERNEL);
+ if (!domain) {
+ if (list_empty(&service->domains)) {
+ list_del(&service->list);
+ kfree(service);
+ }
+
+ return -ENOMEM;
+ }
+
+ domain->name = domain_name;
+ domain->instance_id = instance_id;
+ list_add_tail(&domain->list, &service->domains);
+
+ return 0;
+}
+
+static int qcom_pdm_add_domain(const struct qcom_pdm_domain_data *data)
+{
+ int ret;
+ int i;
+
+ ret = qcom_pdm_add_service_domain(TMS_SERVREG_SERVICE,
+ data->domain,
+ data->instance_id);
+ if (ret)
+ return ret;
+
+ for (i = 0; data->services[i]; i++) {
+ ret = qcom_pdm_add_service_domain(data->services[i],
+ data->domain,
+ data->instance_id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+
+}
+
+static void qcom_pdm_free_domains(void)
+{
+ struct qcom_pdm_service *service, *tservice;
+ struct qcom_pdm_domain *domain, *tdomain;
+
+ list_for_each_entry_safe(service, tservice, &qcom_pdm_services, list) {
+ list_for_each_entry_safe(domain, tdomain, &service->domains, list) {
+ list_del(&domain->list);
+ kfree(domain);
+ }
+
+ list_del(&service->list);
+ kfree(service);
+ }
+}
+
+static void qcom_pdm_get_domain_list(struct qmi_handle *qmi,
+ struct sockaddr_qrtr *sq,
+ struct qmi_txn *txn,
+ const void *decoded)
+{
+ const struct servreg_get_domain_list_req *req = decoded;
+ struct servreg_get_domain_list_resp *rsp = kzalloc(sizeof(*rsp), GFP_KERNEL);
+ struct qcom_pdm_service *service;
+ u32 offset;
+ int ret;
+
+ offset = req->domain_offset_valid ? req->domain_offset : 0;
+
+ rsp->resp.result = QMI_RESULT_SUCCESS_V01;
+ rsp->resp.error = QMI_ERR_NONE_V01;
+
+ rsp->db_rev_count_valid = true;
+ rsp->db_rev_count = 1;
+
+ rsp->total_domains_valid = true;
+ rsp->total_domains = 0;
+
+ mutex_lock(&qcom_pdm_mutex);
+
+ service = qcom_pdm_find(req->service_name);
+ if (service) {
+ struct qcom_pdm_domain *domain;
+
+ rsp->domain_list_valid = true;
+ rsp->domain_list_len = 0;
+
+ list_for_each_entry(domain, &service->domains, list) {
+ u32 i = rsp->total_domains++;
+
+ if (i >= offset && i < SERVREG_DOMAIN_LIST_LENGTH) {
+ u32 j = rsp->domain_list_len++;
+
+ strscpy(rsp->domain_list[j].name, domain->name,
+ sizeof(rsp->domain_list[i].name));
+ rsp->domain_list[j].instance = domain->instance_id;
+
+ pr_debug("PDM: found %s / %d\n", domain->name,
+ domain->instance_id);
+ }
+ }
+ }
+
+ pr_debug("PDM: service '%s' offset %d returning %d domains (of %d)\n", req->service_name,
+ req->domain_offset_valid ? req->domain_offset : -1, rsp->domain_list_len, rsp->total_domains);
+
+ ret = qmi_send_response(qmi, sq, txn, SERVREG_GET_DOMAIN_LIST_REQ,
+ SERVREG_GET_DOMAIN_LIST_RESP_MAX_LEN,
+ servreg_get_domain_list_resp_ei, rsp);
+ if (ret)
+ pr_err("Error sending servreg response: %d\n", ret);
+
+ mutex_unlock(&qcom_pdm_mutex);
+
+ kfree(rsp);
+}
+
+static void qcom_pdm_pfr(struct qmi_handle *qmi,
+ struct sockaddr_qrtr *sq,
+ struct qmi_txn *txn,
+ const void *decoded)
+{
+ const struct servreg_loc_pfr_req *req = decoded;
+ struct servreg_loc_pfr_resp rsp = {};
+ int ret;
+
+ pr_warn_ratelimited("PDM: service '%s' crash: '%s'\n", req->service, req->reason);
+
+ rsp.rsp.result = QMI_RESULT_SUCCESS_V01;
+ rsp.rsp.error = QMI_ERR_NONE_V01;
+
+ ret = qmi_send_response(qmi, sq, txn, SERVREG_LOC_PFR_REQ,
+ SERVREG_LOC_PFR_RESP_MAX_LEN,
+ servreg_loc_pfr_resp_ei, &rsp);
+ if (ret)
+ pr_err("Error sending servreg response: %d\n", ret);
+}
+
+static const struct qmi_msg_handler qcom_pdm_msg_handlers[] = {
+ {
+ .type = QMI_REQUEST,
+ .msg_id = SERVREG_GET_DOMAIN_LIST_REQ,
+ .ei = servreg_get_domain_list_req_ei,
+ .decoded_size = sizeof(struct servreg_get_domain_list_req),
+ .fn = qcom_pdm_get_domain_list,
+ },
+ {
+ .type = QMI_REQUEST,
+ .msg_id = SERVREG_LOC_PFR_REQ,
+ .ei = servreg_loc_pfr_req_ei,
+ .decoded_size = sizeof(struct servreg_loc_pfr_req),
+ .fn = qcom_pdm_pfr,
+ },
+ { },
+};
+
+static const struct qcom_pdm_domain_data adsp_audio_pd = {
+ .domain = "msm/adsp/audio_pd",
+ .instance_id = 74,
+ .services = {
+ "avs/audio",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data adsp_charger_pd = {
+ .domain = "msm/adsp/charger_pd",
+ .instance_id = 74,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data adsp_root_pd = {
+ .domain = "msm/adsp/root_pd",
+ .instance_id = 74,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data adsp_root_pd_pdr = {
+ .domain = "msm/adsp/root_pd",
+ .instance_id = 74,
+ .services = {
+ "tms/pdr_enabled",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data adsp_sensor_pd = {
+ .domain = "msm/adsp/sensor_pd",
+ .instance_id = 74,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data msm8996_adsp_audio_pd = {
+ .domain = "msm/adsp/audio_pd",
+ .instance_id = 4,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data msm8996_adsp_root_pd = {
+ .domain = "msm/adsp/root_pd",
+ .instance_id = 4,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data cdsp_root_pd = {
+ .domain = "msm/cdsp/root_pd",
+ .instance_id = 76,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data slpi_root_pd = {
+ .domain = "msm/slpi/root_pd",
+ .instance_id = 90,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data slpi_sensor_pd = {
+ .domain = "msm/slpi/sensor_pd",
+ .instance_id = 90,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data mpss_root_pd = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 180,
+ .services = {
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data mpss_root_pd_gps = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 180,
+ .services = {
+ "gps/gps_service",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data mpss_root_pd_gps_pdr = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 180,
+ .services = {
+ "gps/gps_service",
+ "tms/pdr_enabled",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data msm8996_mpss_root_pd = {
+ .domain = "msm/modem/root_pd",
+ .instance_id = 100,
+ .services = { NULL },
+};
+
+static const struct qcom_pdm_domain_data mpss_wlan_pd = {
+ .domain = "msm/modem/wlan_pd",
+ .instance_id = 180,
+ .services = {
+ "kernel/elf_loader",
+ "wlan/fw",
+ NULL,
+ },
+};
+
+static const struct qcom_pdm_domain_data *msm8996_domains[] = {
+ &msm8996_adsp_audio_pd,
+ &msm8996_adsp_root_pd,
+ &msm8996_mpss_root_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *msm8998_domains[] = {
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *qcm2290_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *qcs404_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc7180_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_sensor_pd,
+ &mpss_root_pd_gps_pdr,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc7280_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_charger_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps_pdr,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc8180x_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_charger_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sc8280xp_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_charger_pd,
+ &cdsp_root_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sdm660_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sdm670_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sdm845_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd,
+ &mpss_wlan_pd,
+ &slpi_root_pd,
+ &slpi_sensor_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm6115_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm6350_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8150_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &mpss_wlan_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8250_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &cdsp_root_pd,
+ &slpi_root_pd,
+ &slpi_sensor_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8350_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd_pdr,
+ &adsp_charger_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ &slpi_root_pd,
+ &slpi_sensor_pd,
+ NULL,
+};
+
+static const struct qcom_pdm_domain_data *sm8550_domains[] = {
+ &adsp_audio_pd,
+ &adsp_root_pd,
+ &adsp_charger_pd,
+ &adsp_sensor_pd,
+ &cdsp_root_pd,
+ &mpss_root_pd_gps,
+ NULL,
+};
+
+static const struct of_device_id qcom_pdm_domains[] = {
+ { .compatible = "qcom,apq8096", .data = msm8996_domains, },
+ { .compatible = "qcom,msm8996", .data = msm8996_domains, },
+ { .compatible = "qcom,msm8998", .data = msm8998_domains, },
+ { .compatible = "qcom,qcm2290", .data = qcm2290_domains, },
+ { .compatible = "qcom,qcs404", .data = qcs404_domains, },
+ { .compatible = "qcom,sc7180", .data = sc7180_domains, },
+ { .compatible = "qcom,sc7280", .data = sc7280_domains, },
+ { .compatible = "qcom,sc8180x", .data = sc8180x_domains, },
+ { .compatible = "qcom,sc8280xp", .data = sc8280xp_domains, },
+ { .compatible = "qcom,sda660", .data = sdm660_domains, },
+ { .compatible = "qcom,sdm660", .data = sdm660_domains, },
+ { .compatible = "qcom,sdm670", .data = sdm670_domains, },
+ { .compatible = "qcom,sdm845", .data = sdm845_domains, },
+ { .compatible = "qcom,sm6115", .data = sm6115_domains, },
+ { .compatible = "qcom,sm6350", .data = sm6350_domains, },
+ { .compatible = "qcom,sm8150", .data = sm8150_domains, },
+ { .compatible = "qcom,sm8250", .data = sm8250_domains, },
+ { .compatible = "qcom,sm8350", .data = sm8350_domains, },
+ { .compatible = "qcom,sm8450", .data = sm8350_domains, },
+ { .compatible = "qcom,sm8550", .data = sm8550_domains, },
+ { .compatible = "qcom,sm8650", .data = sm8550_domains, },
+ {},
+};
+
+static int qcom_pdm_start(void)
+{
+ const struct of_device_id *match;
+ const struct qcom_pdm_domain_data * const *domains;
+ struct device_node *root;
+ int ret, i;
+
+ pr_debug("PDM: starting service\n");
+
+ root = of_find_node_by_path("/");
+ if (!root)
+ return -ENODEV;
+
+ match = of_match_node(qcom_pdm_domains, root);
+ of_node_put(root);
+ if (!match) {
+ pr_notice("PDM: no support for the platform, userspace daemon might be required.\n");
+ return 0;
+ }
+
+ domains = match->data;
+ if (!domains) {
+ pr_debug("PDM: no domains\n");
+ return 0;
+ }
+
+ for (i = 0; domains[i]; i++) {
+ ret = qcom_pdm_add_domain(domains[i]);
+ if (ret)
+ goto free_domains;
+ }
+
+ ret = qmi_handle_init(&qcom_pdm_handle, 1024,
+ NULL, qcom_pdm_msg_handlers);
+ if (ret)
+ goto free_domains;
+
+ ret = qmi_add_server(&qcom_pdm_handle, SERVREG_LOCATOR_SERVICE,
+ SERVREG_QMI_VERSION, SERVREG_QMI_INSTANCE);
+ if (ret) {
+ pr_err("PDM: error adding server %d\n", ret);
+ goto release_handle;
+ }
+
+ return 0;
+
+release_handle:
+ qmi_handle_release(&qcom_pdm_handle);
+
+free_domains:
+ qcom_pdm_free_domains();
+
+ return ret;
+}
+
+static void qcom_pdm_stop(void)
+{
+ qmi_del_server(&qcom_pdm_handle, SERVREG_LOCATOR_SERVICE,
+ SERVREG_QMI_VERSION, SERVREG_QMI_INSTANCE);
+
+ qmi_handle_release(&qcom_pdm_handle);
+
+ qcom_pdm_free_domains();
+
+ WARN_ON(!list_empty(&qcom_pdm_services));
+
+ pr_debug("PDM: stopped service\n");
+}
+
+/**
+ * qcom_pdm_get() - ensure that PD mapper is up and running
+ */
+int qcom_pdm_get(void)
+{
+ int ret = 0;
+
+ mutex_lock(&qcom_pdm_mutex);
+
+ if (!qcom_pdm_count)
+ ret = qcom_pdm_start();
+
+ if (!ret)
+ ++qcom_pdm_count;
+
+ mutex_unlock(&qcom_pdm_mutex);
+
+ return ret;
+}
+
+/**
+ * qcom_pdm_release() - possibly stop PD mapper service
+ */
+void qcom_pdm_release(void)
+{
+ mutex_lock(&qcom_pdm_mutex);
+
+ if (qcom_pdm_count == 1)
+ qcom_pdm_stop();
+
+ if (qcom_pdm_count >= 1)
+ --qcom_pdm_count;
+
+ mutex_unlock(&qcom_pdm_mutex);
+}
+
+MODULE_DESCRIPTION("Qualcomm Protection Domain Mapper");
+MODULE_LICENSE("GPL");
diff --git a/drivers/soc/qcom/qcom_pdr_msg.c b/drivers/soc/qcom/qcom_pdr_msg.c
index a8867e8b1319..bdebbe929468 100644
--- a/drivers/soc/qcom/qcom_pdr_msg.c
+++ b/drivers/soc/qcom/qcom_pdr_msg.c
@@ -313,3 +313,37 @@ const struct qmi_elem_info servreg_set_ack_resp_ei[] = {
{}
};
EXPORT_SYMBOL_GPL(servreg_set_ack_resp_ei);
+
+const struct qmi_elem_info servreg_loc_pfr_req_ei[] = {
+ {
+ .data_type = QMI_STRING,
+ .elem_len = SERVREG_NAME_LENGTH + 1,
+ .elem_size = sizeof(char),
+ .array_type = VAR_LEN_ARRAY,
+ .tlv_type = 0x01,
+ .offset = offsetof(struct servreg_loc_pfr_req, service)
+ },
+ {
+ .data_type = QMI_STRING,
+ .elem_len = SERVREG_NAME_LENGTH + 1,
+ .elem_size = sizeof(char),
+ .array_type = VAR_LEN_ARRAY,
+ .tlv_type = 0x02,
+ .offset = offsetof(struct servreg_loc_pfr_req, reason)
+ },
+ {}
+};
+EXPORT_SYMBOL_GPL(servreg_loc_pfr_req_ei);
+
+const struct qmi_elem_info servreg_loc_pfr_resp_ei[] = {
+ {
+ .data_type = QMI_STRUCT,
+ .elem_len = 1,
+ .elem_size = sizeof_field(struct servreg_loc_pfr_resp, rsp),
+ .tlv_type = 0x02,
+ .offset = offsetof(struct servreg_loc_pfr_resp, rsp),
+ .ei_array = qmi_response_type_v01_ei,
+ },
+ {}
+};
+EXPORT_SYMBOL_GPL(servreg_loc_pfr_resp_ei);
diff --git a/include/linux/soc/qcom/pd_mapper.h b/include/linux/soc/qcom/pd_mapper.h
new file mode 100644
index 000000000000..d0dd3dfc8fea
--- /dev/null
+++ b/include/linux/soc/qcom/pd_mapper.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Qualcomm Protection Domain mapper
+ *
+ * Copyright (c) 2023 Linaro Ltd.
+ */
+#ifndef __QCOM_PD_MAPPER__
+#define __QCOM_PD_MAPPER__
+
+#if IS_ENABLED(CONFIG_QCOM_PD_MAPPER)
+
+int qcom_pdm_get(void);
+void qcom_pdm_release(void);
+
+#else
+
+static inline int qcom_pdm_get(void)
+{
+ return 0;
+}
+
+static inline void qcom_pdm_release(void)
+{
+}
+
+#endif
+
+#endif
--
2.39.2
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2024-01-23 14:45 [PATCH v9 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs Bibek Kumar Patro
2024-04-30 17:59 0% ` Dmitry Baryshkov
2024-04-30 17:59 0% ` Dmitry Baryshkov
2024-02-29 13:07 [PATCH RFT 0/7] arm64: qcom: allow up to 4 lanes for the Type-C DisplayPort Altmode Neil Armstrong
2024-03-15 17:19 ` Luca Weiss
2024-03-15 17:35 ` Neil Armstrong
2024-03-16 16:01 ` Bjorn Andersson
2024-03-26 21:02 ` Konrad Dybcio
2024-03-29 9:02 ` Luca Weiss
2024-04-05 8:08 ` Neil Armstrong
2024-04-05 10:19 ` Luca Weiss
2024-04-23 13:03 0% ` Konrad Dybcio
2024-04-23 13:03 0% ` Konrad Dybcio
2024-04-23 14:08 0% ` neil.armstrong
2024-04-23 14:08 0% ` neil.armstrong
2024-05-10 6:51 0% ` Luca Weiss
2024-05-10 6:51 0% ` Luca Weiss
2024-03-18 10:09 [PATCH v4 0/2] drm/msm: Add support for the A750 GPU found on the SM8650 platform Neil Armstrong
2024-04-21 22:29 0% ` Bjorn Andersson
2024-03-21 9:25 [PATCH V2 RESEND 0/6] Add support for videocc and camcc on SM8650 Jagadeesh Kona
2024-03-21 9:25 ` [PATCH V2 RESEND 1/6] dt-bindings: clock: qcom: Add SM8650 video clock controller Jagadeesh Kona
2024-03-21 13:12 ` Dmitry Baryshkov
2024-03-25 6:07 ` Jagadeesh Kona
2024-04-18 21:01 ` Vladimir Zapolskiy
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2024-04-25 13:32 0% ` Vladimir Zapolskiy
2024-04-26 14:26 0% ` Jagadeesh Kona
2024-03-21 9:25 ` [PATCH V2 RESEND 5/6] clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver Jagadeesh Kona
2024-04-18 21:30 ` Vladimir Zapolskiy
2024-04-22 10:57 0% ` Jagadeesh Kona
2024-03-26 9:16 [PATCH v6 0/5] Rework system pressure interface to the scheduler Vincent Guittot
2024-03-26 9:16 ` [PATCH v6 4/5] sched: Rename arch_update_thermal_pressure into arch_update_hw_pressure Vincent Guittot
2024-04-30 11:23 ` Konrad Dybcio
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2024-04-30 12:15 4% ` Konrad Dybcio
2024-04-30 12:15 4% ` Konrad Dybcio
2024-04-01 15:43 [PATCH 6.1 000/272] 6.1.84-rc1 review Greg Kroah-Hartman
2024-04-01 15:47 ` [PATCH 6.1 251/272] usb: typec: ucsi: Check for notifications after init Greg Kroah-Hartman
2024-04-01 20:16 ` Christian A. Ehrhardt
2024-04-02 5:40 ` Greg Kroah-Hartman
2024-04-02 6:06 ` Christian A. Ehrhardt
2024-04-02 7:52 ` Greg Kroah-Hartman
2024-05-01 19:10 0% ` Christian A. Ehrhardt
2024-05-13 13:02 0% ` Greg Kroah-Hartman
2024-04-08 11:47 [PATCH 0/4] clk: qcom: dispcc: fix DisplayPort link clocks Dmitry Baryshkov
2024-04-20 18:05 0% ` Bjorn Andersson
2024-04-19 14:00 [PATCH v5 0/6] soc: qcom: add in-kernel pd-mapper implementation Dmitry Baryshkov
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2024-04-19 18:24 0% ` Dmitry Baryshkov
2024-04-19 16:54 [PATCH v4 0/7] iommu, dma-mapping: Simplify arch_setup_dma_ops() Robin Murphy
2024-04-19 16:54 ` [PATCH v4 6/7] iommu/dma: Centralise iommu_setup_dma_ops() Robin Murphy
2024-04-29 16:31 ` Dmitry Baryshkov
2024-04-29 21:26 ` Dmitry Baryshkov
2024-04-30 12:23 4% ` Konrad Dybcio
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2024-04-30 12:33 0% ` Robin Murphy
2024-04-20 16:10 6% [GIT PULL] Qualcomm Arm64 DeviceTree fixes for v6.9 Bjorn Andersson
2024-04-20 16:10 6% ` Bjorn Andersson
2024-04-22 4:29 5% [PATCH] docs: driver-api: interconnect: fix typo Sekhar Nori
2024-04-22 14:53 0% ` Mike Tipton
2024-04-22 8:33 6% [PATCH v3 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock Neil Armstrong
2024-04-22 8:33 6% ` Neil Armstrong
2024-04-22 8:33 19% ` [PATCH v3 2/3] arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk Neil Armstrong
2024-04-22 8:33 19% ` Neil Armstrong
2024-04-22 11:50 7% ` [PATCH v3 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock Rob Herring
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2024-04-22 16:07 0% ` Neil Armstrong
2024-04-22 16:07 0% ` Neil Armstrong
2024-04-22 8:48 [PATCH v4 0/3] arm64: qcom: sm8650: add support for the SM8650-HDK board Neil Armstrong
2024-04-22 8:48 9% ` [PATCH v4 2/3] arm64: dts: " Neil Armstrong
2024-04-22 8:48 13% ` [PATCH v4 3/3] arch: arm64: dts: sm8650-hdk: add support for the Display Card overlay Neil Armstrong
2024-04-22 10:11 [PATCH v6 0/6] soc: qcom: add in-kernel pd-mapper implementation Dmitry Baryshkov
2024-04-22 10:11 4% ` [PATCH v6 1/6] soc: qcom: pdr: protect locator_addr with the main mutex Dmitry Baryshkov
2024-04-22 10:11 4% ` [PATCH v6 4/6] soc: qcom: qmi: add a way to remove running service Dmitry Baryshkov
2024-04-22 10:11 2% ` [PATCH v6 5/6] soc: qcom: add pd-mapper implementation Dmitry Baryshkov
2024-04-22 13:43 [PATCH v2 0/4] ASoC: qcom: display port changes srinivas.kandagatla
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2024-04-22 16:16 19% ` [PATCH v4 2/3] arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk Neil Armstrong
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2024-04-24 15:29 16% ` [PATCH 06/10] arm64: dts: qcom: sm8550: Add UART15 Xilin Wu via B4 Relay
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2024-05-01 10:42 0% ` Bryan O'Donoghue
2024-04-30 14:27 5% ` [PATCH V3 6/8] dt-bindings: clock: qcom: Add SM8650 camera clock controller Jagadeesh Kona
2024-04-30 14:27 1% ` [PATCH V3 7/8] clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver Jagadeesh Kona
2024-05-01 16:19 [PATCH 00/13] arm64: dts: qcom: fix PHY-related warnings Dmitry Baryshkov
2024-05-01 16:19 5% ` [PATCH 01/13] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schema Dmitry Baryshkov
2024-05-01 16:19 5% ` Dmitry Baryshkov
2024-05-02 8:00 7% [PATCH v5 0/3] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock Neil Armstrong
2024-05-02 8:00 19% ` [PATCH v5 2/3] arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk Neil Armstrong
2024-05-03 2:40 [PATCH 00/12] linux-yocto: v6.6 updates bruce.ashfield
2024-05-03 2:40 2% ` [PATCH 01/12] linux-yocto/6.6: update to v6.6.24 bruce.ashfield
2024-05-05 20:10 [PATCH v3 0/8] Add dispcc, videocc and camcc for SM7150 Danila Tikhonov
2024-05-05 20:10 2% ` [PATCH v3 4/8] clk: qcom: Add Display Clock Controller driver " Danila Tikhonov
2024-05-05 20:10 1% ` [PATCH v3 6/8] clk: qcom: Add Camera " Danila Tikhonov
2024-05-05 20:10 9% ` [PATCH v3 8/8] clk: qcom: Add Video " Danila Tikhonov
2024-05-06 5:42 5% linux-next: duplicate patches in the nvmem tree Stephen Rothwell
2024-05-06 6:49 1% linux-next: Tree for May 6 Stephen Rothwell
2024-05-07 13:05 6% [PATCH v14 0/4] add clock controller of qca8386/qca8084 Luo Jie
2024-05-07 13:05 10% ` [PATCH v14 3/4] clk: qcom: common: commonize qcom_cc_really_probe Luo Jie
2024-05-07 20:10 [PATCH v1 1/1] spi: Remove unneded check for orig_nents Andy Shevchenko
2024-05-15 21:09 ` Nícolas F. R. A. Prado
2024-05-22 10:03 4% ` Neil Armstrong
2024-05-22 11:33 0% ` Andy Shevchenko
2024-05-22 11:53 0% ` Neil Armstrong
2024-05-22 13:18 0% ` Neil Armstrong
2024-05-22 14:24 0% ` Andy Shevchenko
2024-05-22 15:12 0% ` Nícolas F. R. A. Prado
2024-05-22 15:24 0% ` Andy Shevchenko
2024-05-08 2:36 5% [GIT PULL] Qualcomm clock updates for v6.10 Bjorn Andersson
2024-05-08 2:36 5% ` Bjorn Andersson
2024-05-10 11:59 4% [PATCH v2 00/31] Clean up thermal zone polling-delay Konrad Dybcio
2024-05-10 11:59 11% ` [PATCH v2 30/31] arm64: dts: qcom: sm8550-*: Remove thermal zone polling delays Konrad Dybcio
2024-05-10 12:58 5% [PATCH 00/12] Adreno cooling, take 2 Konrad Dybcio
2024-05-10 12:58 14% ` [PATCH 11/12] arm64: dts: qcom: sm8550: Throttle the GPU when overheating Konrad Dybcio
2024-05-10 16:50 7% [PATCH] clk: qcom: Constify struct pll_vco Christophe JAILLET
2024-05-10 17:58 [PATCH 0/2] ASoC: codecs: lpass: add support for v2.6 rx macro srinivas.kandagatla
2024-05-10 17:58 1% ` [PATCH 2/2] ASoC: codec: lpass-rx-macro: add suppor for 2.6 codec version srinivas.kandagatla
2024-05-10 21:09 [GIT PULL 0/4] arm soc changes for 6.10 Arnd Bergmann
2024-05-10 21:11 3% ` [GIT PULL 1/4] soc: devicetree updates for 6.10, part 1 Arnd Bergmann
2024-05-10 21:11 3% ` Arnd Bergmann
2024-05-11 21:56 [PATCH v8 0/5] soc: qcom: add in-kernel pd-mapper implementation Dmitry Baryshkov
2024-05-11 21:56 4% ` [PATCH v8 1/5] soc: qcom: pdr: protect locator_addr with the main mutex Dmitry Baryshkov
2024-05-11 21:56 2% ` [PATCH v8 4/5] soc: qcom: add pd-mapper implementation Dmitry Baryshkov
2024-05-13 8:47 19% [PATCH] arm64: dts: qcom: sm8550: Move some common usb node settings to SoC dtsi Tengfei Fan
2024-05-13 8:56 4% ` Krzysztof Kozlowski
2024-05-14 0:52 4% ` Tengfei Fan
2024-05-13 9:07 6% [PATCH v8 0/4] arm64: qcom: add AIM300 AIoT board support Tengfei Fan
2024-05-13 9:07 16% ` [PATCH v8 1/4] dt-bindings: arm: qcom: Document QCS8550 SoC and the AIM300 AIoT board Tengfei Fan
2024-05-13 9:07 9% ` [PATCH v8 2/4] arm64: dts: qcom: qcs8550: introduce qcs8550 dtsi Tengfei Fan
2024-05-13 16:37 4% ` Trilok Soni
2024-05-14 1:21 0% ` Aiqun Yu (Maria)
2024-05-14 2:05 0% ` Tengfei Fan
2024-05-13 9:07 5% ` [PATCH v8 4/4] arm64: dts: qcom: aim300: add AIM300 AIoT Tengfei Fan
2024-05-14 10:13 [PATCH 6.8 000/336] 6.8.10-rc1 review Greg Kroah-Hartman
2024-05-14 10:17 4% ` [PATCH 6.8 245/336] usb: typec: ucsi: Check for notifications after init Greg Kroah-Hartman
2024-05-14 10:14 [PATCH 6.6 000/301] 6.6.31-rc1 review Greg Kroah-Hartman
2024-05-14 10:18 4% ` [PATCH 6.6 225/301] usb: typec: ucsi: Check for notifications after init Greg Kroah-Hartman
2024-05-14 10:16 [PATCH 6.1 000/236] 6.1.91-rc1 review Greg Kroah-Hartman
2024-05-14 10:19 4% ` [PATCH 6.1 192/236] usb: typec: ucsi: Check for notifications after init Greg Kroah-Hartman
2024-05-14 10:18 [PATCH 5.15 000/168] 5.15.159-rc1 review Greg Kroah-Hartman
2024-05-14 10:20 4% ` [PATCH 5.15 141/168] usb: typec: ucsi: Check for notifications after init Greg Kroah-Hartman
2024-05-14 10:18 [PATCH 5.10 000/111] 5.10.217-rc1 review Greg Kroah-Hartman
2024-05-14 10:20 4% ` [PATCH 5.10 092/111] usb: typec: ucsi: Check for notifications after init Greg Kroah-Hartman
2024-05-14 13:08 4% [PATCH 0/2] arm64: dts: qcom: Use 'ufshc' as the node name for UFS controller nodes Manivannan Sadhasivam
2024-05-14 13:08 14% ` [PATCH 2/2] " Manivannan Sadhasivam
2024-05-14 16:41 [REGRESSION] boot regression on linux-next on sc7180 platforms - null pointer dereference on iommu_dma_sync_sg_for_device Nícolas F. R. A. Prado
2024-05-22 10:00 4% ` Neil Armstrong
2024-05-14 16:42 4% [PATCH 1/1] Squashed 'dts/upstream/' changes from b35b9bd1d4ee..7e08733c96c8 Tom Rini
2024-05-17 1:31 3% [GIT PULL] clk changes for the merge window Stephen Boyd
2024-05-17 22:27 1% [linux-6.1 test] 186028: tolerable FAIL - PUSHED osstest service owner
2024-05-19 3:48 2% [linux-linus test] 186036: " osstest service owner
2024-05-20 5:11 2% [linux-linus test] 186041: regressions - FAIL osstest service owner
2024-05-20 14:59 2% [linux-linus test] 186044: " osstest service owner
2024-05-20 21:00 6% [PATCH v5 0/5] LLCC: Support for Broadcast_AND region Unnathi Chalicheemala
2024-05-20 21:00 9% ` [PATCH v5 1/5] dt-bindings: arm: msm: Add llcc Broadcast_AND register Unnathi Chalicheemala
2024-05-20 21:00 17% ` [PATCH v5 4/5] arm64: dts: qcom: sm8550: Add Broadcast_AND register in LLCC block Unnathi Chalicheemala
2024-05-21 1:19 2% [linux-linus test] 186047: tolerable FAIL - PUSHED osstest service owner
2024-05-21 9:45 [PATCH 00/12] arm64: qcom: autodetect firmware paths Dmitry Baryshkov
2024-05-21 9:45 6% ` [PATCH 01/12] soc: qcom: add firmware name helper Dmitry Baryshkov
2024-05-21 9:52 0% ` neil.armstrong
2024-05-21 10:01 0% ` Dmitry Baryshkov
2024-05-21 18:37 6% [PATCH RFC v3 0/9] dt-bindings: hwinfo: Introduce board-id Elliot Berman
2024-05-21 18:37 6% ` Elliot Berman
2024-05-21 18:38 5% ` [PATCH RFC v3 6/9] arm64: boot: dts: sm8650: Add board-id Elliot Berman
2024-05-21 18:38 5% ` Elliot Berman
2024-05-21 18:38 9% ` [PATCH RFC v3 7/9] arm64: boot: dts: qcom: Use phandles for thermal_zones Elliot Berman
2024-05-21 18:38 9% ` Elliot Berman
2024-05-21 18:38 42% ` [PATCH RFC v3 8/9] arm64: boot: dts: qcom: sm8550: Split into overlays Elliot Berman
2024-05-21 18:38 42% ` Elliot Berman
2024-05-21 18:38 6% ` [PATCH RFC v3 9/9] tools: board-id: Add test suite Elliot Berman
2024-05-21 18:38 6% ` Elliot Berman
2024-05-22 12:08 5% [PATCH 0/5] arm64: qcom: sa8775p: enable remoteprocs - ADSP, CDSP and GPDSP Bartosz Golaszewski
2024-05-22 12:08 23% ` [PATCH 1/5] dt-bindings: remoteproc: qcom,sm8550-pas: Document the SA8775p " Bartosz Golaszewski
2024-05-22 12:42 4% ` neil.armstrong
2024-05-22 13:04 4% ` Bartosz Golaszewski
2024-05-22 13:06 4% ` neil.armstrong
2024-05-22 13:08 4% ` Bartosz Golaszewski
2024-05-22 14:49 1% [GIT PULL] USB/Thunderbolt driver changes for 6.10-rc1 Greg KH
2024-05-22 14:51 1% [GIT PULL] Char/Misc " Greg KH
2024-05-24 3:53 [PATCH v2 0/2] Add support for QCM6490 and QCS6490 Mohammad Rafi Shaik
2024-05-24 3:53 7% ` [PATCH v2 2/2] ASoC: qcom: sc8280xp: " Mohammad Rafi Shaik
2024-05-24 13:17 5% [PATCH v10 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs Bibek Kumar Patro
2024-05-24 13:17 5% ` Bibek Kumar Patro
2024-05-24 13:17 14% ` [PATCH v10 4/5] iommu/arm-smmu: add ACTLR data and support for SM8550 Bibek Kumar Patro
2024-05-24 13:17 14% ` Bibek Kumar Patro
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