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* [PATCH 1/3] x86/mce/AMD: Use msr_stat when clearing MCA_STATUS
@ 2017-05-24 20:41 ` Yazen Ghannam
  0 siblings, 0 replies; 16+ messages in thread
From: Yazen Ghannam @ 2017-05-24 20:41 UTC (permalink / raw)
  To: linux-edac; +Cc: Borislav Petkov, Tony Luck, x86, linux-kernel, Yazen Ghannam

From: Yazen Ghannam <yazen.ghannam@amd.com>

The value of MCA_STATUS is used as the MSR when clearing MCA_STATUS.

This may cause the following warning:
 unchecked MSR access error: WRMSR to 0x11b (tried to write 0x0000000000000000)
 Call Trace:
  <IRQ>
  ? amd_threshold_interrupt+0x209/0x220
  smp_threshold_interrupt+0x1b/0x40
  threshold_interrupt+0x89/0x90

Use msr_stat instead which has the MSR address.

Fixes: 37d43acfd79f ("x86/mce/AMD: Redo error logging from APIC LVT interrupt handlers")
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index d00f299..d11f94e 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -815,7 +815,7 @@ _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
 
 	__log_error(bank, status, addr, misc);
 
-	wrmsrl(status, 0);
+	wrmsrl(msr_stat, 0);
 
 	return status & MCI_STATUS_DEFERRED;
 }
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 16+ messages in thread

end of thread, other threads:[~2017-05-30 14:11 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-05-24 20:41 [PATCH 1/3] x86/mce/AMD: Use msr_stat when clearing MCA_STATUS Yazen Ghannam
2017-05-24 20:41 ` [1/3] " Yazen Ghannam
2017-05-24 20:41 ` [PATCH 2/3] x86/mce/AMD: Define a list_head for threshold blocks outside the list Yazen Ghannam
2017-05-24 20:41   ` [2/3] " Yazen Ghannam
2017-05-28 17:22   ` [PATCH 2/3] " Borislav Petkov
2017-05-28 17:22     ` [2/3] " Borislav Petkov
2017-05-30 12:39     ` [PATCH 2/3] " Ghannam, Yazen
2017-05-30 12:39       ` [2/3] " Yazen Ghannam
2017-05-30 13:56       ` [PATCH 2/3] " Borislav Petkov
2017-05-30 13:56         ` [2/3] " Borislav Petkov
2017-05-30 14:06         ` [PATCH 2/3] " Ghannam, Yazen
2017-05-30 14:06           ` [2/3] " Yazen Ghannam
2017-05-30 14:10           ` [PATCH 2/3] " Borislav Petkov
2017-05-30 14:10             ` [2/3] " Borislav Petkov
2017-05-24 20:41 ` [PATCH 3/3] x86/mce/AMD: Use saved threshold block info in interrupt handler Yazen Ghannam
2017-05-24 20:41   ` [3/3] " Yazen Ghannam

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