Re: [Qemu-devel] [PATCH target-arm v4 15/16] arm: xilinx-ep108: Add bootloading

[Peter Crosthwaite <peter.crosthwaite@xilinx.com>]

On Thu, Apr 23, 2015 at 5:43 PM, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> On Thu, Apr 23, 2015 at 11:15 AM, Peter Maydell
> <peter.maydell@linaro.org> wrote:
>> On 23 March 2015 at 11:05, Peter Crosthwaite
>> <peter.crosthwaite@xilinx.com> wrote:
>>> Using standard ARM bootloader.
>>
>> Commit msg, etc.
>>
>>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>> ---
>>>  hw/arm/xlnx-ep108.c | 8 ++++++++
>>>  1 file changed, 8 insertions(+)
>>>
>>> diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
>>> index 6e89456..a86f595 100644
>>> --- a/hw/arm/xlnx-ep108.c
>>> +++ b/hw/arm/xlnx-ep108.c
>>> @@ -28,6 +28,8 @@ typedef struct XlnxEP108 {
>>>  /* Max 2GB RAM */
>>>  #define EP108_MAX_RAM_SIZE 0x80000000ull
>>>
>>> +static struct arm_boot_info xlnx_ep108_binfo;
>>> +
>>>  static void xlnx_ep108_init(MachineState *machine)
>>>  {
>>>      XlnxEP108 *s = g_new0(XlnxEP108, 1);
>>> @@ -58,6 +60,12 @@ static void xlnx_ep108_init(MachineState *machine)
>>>                             &error_abort);
>>>      vmstate_register_ram_global(&s->ddr_ram);
>>>      memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
>>> +
>>> +    xlnx_ep108_binfo.ram_size = machine->ram_size;
>>> +    xlnx_ep108_binfo.kernel_filename = machine->kernel_filename;
>>> +    xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline;
>>> +    xlnx_ep108_binfo.initrd_filename = machine->initrd_filename;
>>
>> nb_cpus, loader_start ?
>>
>
> I don't see any valid use for non-0 nb_cpus for aarch64 bootloading. I
> think PSCI just handles it all? default_write_secondary will write in
> smpboot contents which is AA32.
>

I just did another sanity check on this. SMP works fine via PSCI with
nb_cpus unset:

CPU1: Booted secondary processor
Detected VIPT I-cache on CPU1
CPU2: Booted secondary processor
Detected VIPT I-cache on CPU2
CPU3: Booted secondary processor
Detected VIPT I-cache on CPU3
Brought up 4 CPUs
SMP: Total of 4 processors activated.
devtmpfs: initialized

 The real hardware on POR holds all the SMP CPUs in reset and PSCI
would layer onto of that. For Linux boots, the correct solution is
going to be PSCI. For other boots you will need your own firmware
which will then have to unreset via the reset controller (device mode
TBA). So I don't see the SMP secondary loop having a place in this
machine model and nb_cpus should default to 0 ( == 1).

Regards,
Peter

> Loader start is 0. I'll make it explicit.
>
> Regards,
> Peter
>
>>> +    arm_load_kernel(&s->soc.cpu[0], &xlnx_ep108_binfo);
>>>  }
>>>
>>>  static QEMUMachine xlnx_ep108_machine = {
>>> --
>>> 2.3.1.2.g90df61e.dirty
>>
>> thanks
>> -- PMM
>>