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From: Peter Maydell <peter.maydell@linaro.org>
To: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Cc: Edgar Iglesias <edgar.iglesias@xilinx.com>,
	zach.pfeffer@xilinx.com, Ryota Ozaki <ozaki.ryota@gmail.com>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Alistair Francis <alistair.francis@xilinx.com>,
	michals@xilinx.com
Subject: Re: [Qemu-devel] [PATCH target-arm v4 10/16] char: cadence_uart: Clean up variable names
Date: Thu, 23 Apr 2015 18:59:22 +0100	[thread overview]
Message-ID: <CAFEAcA_AODA-mrx8zLxb9D6LWCR2fZES-JDDhbPgSevzsrcT0A@mail.gmail.com> (raw)
In-Reply-To: <f865c90b0ca53fce8d7e2a8a1970dd2e30986966.1427108387.git.peter.crosthwaite@xilinx.com>

On 23 March 2015 at 11:05, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> In preparation for migrating the state struct and type cast macro to a public
> header. The acronym "UART" on it's own is not specific enough to be used in a
> more global namespace so preface with "cadence". Fix the capitalisation of
> "uart" in the state type while touching the typename. Preface macros
> used by the state struct itself with CADENCE_UART so they don't conflict
> in namespace either.

This is another non-standalone commit message. Other than that:
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

> -    s->r[R_SR] |= s->rx_count == RX_FIFO_SIZE ? UART_SR_INTR_RFUL : 0;
> +    s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
> +                                                           : 0;

These look kind of ugly as the line length got long enough to wrap.
    if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
        s->r[R_SR] |= UART_SR_INTR_RFUL;
    }
looks nicer to me (and makes it clearer that the bit only updates
if the condition is true, rather than leaving you to figure it out
from the combination of the OR and the ternary operator with a zero
operand), but that kind of change doesn't belong in this
no-content-change patch. You could do it in a later patch, or
not do it at all if you don't think it's important enough (I
don't care strongly either way).

-- PMM

  reply	other threads:[~2015-04-23 17:59 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-23 11:05 [Qemu-devel] [PATCH target-arm v4 00/16] Next Generation Xilinx Zynq SoC Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 01/16] cpus: Don't kick un-realized cpus Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 02/16] target-arm: cpu64: Factor out ARM cortex init Peter Crosthwaite
2015-04-23 17:35   ` Peter Maydell
2015-04-24 16:39     ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 03/16] target-arm: cpu64: Add support for cortex-a53 Peter Crosthwaite
2015-03-23 13:17   ` Ryota Ozaki
2015-04-24 16:42     ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 05/16] arm: xlnx-zynqmp: Add GIC Peter Crosthwaite
2015-04-23 17:45   ` Peter Maydell
2015-04-23 23:55     ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 04/16] arm: Introduce Xilinx ZynqMP SoC Peter Crosthwaite
2015-03-30  1:17   ` Alistair Francis
2015-04-23 17:42   ` Peter Maydell
2015-04-23 19:21     ` Peter Crosthwaite
2015-04-23 21:38       ` Peter Maydell
2015-04-24 15:26         ` Peter Maydell
2015-04-24 16:31           ` Peter Crosthwaite
2015-04-23 17:47   ` Peter Maydell
2015-04-23 19:30     ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 06/16] arm: xlnx-zynqmp: Connect CPU Timers to GIC Peter Crosthwaite
2015-03-30  1:29   ` Alistair Francis
2015-04-24  0:02     ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 07/16] net: cadence_gem: Clean up variable names Peter Crosthwaite
2015-04-23 17:50   ` Peter Maydell
2015-04-24 16:51     ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 08/16] net: cadence_gem: Split state struct and type into header Peter Crosthwaite
2015-04-23 17:51   ` Peter Maydell
2015-04-24  0:10     ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 10/16] char: cadence_uart: Clean up variable names Peter Crosthwaite
2015-04-23 17:59   ` Peter Maydell [this message]
2015-04-24  0:25     ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 11/16] char: cadence_uart: Split state struct and type into header Peter Crosthwaite
2015-04-23 18:00   ` Peter Maydell
2015-04-24  0:20     ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 13/16] arm: Add xlnx-ep108 machine Peter Crosthwaite
2015-03-30  1:11   ` Alistair Francis
2015-04-23 18:09   ` Peter Maydell
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 14/16] arm: xilinx-ep108: Add external RAM Peter Crosthwaite
2015-03-30  1:31   ` Alistair Francis
2015-04-23 18:12   ` Peter Maydell
2015-04-24  0:36     ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 15/16] arm: xilinx-ep108: Add bootloading Peter Crosthwaite
2015-03-30  1:42   ` Alistair Francis
2015-04-23 18:15   ` Peter Maydell
2015-04-24  0:43     ` Peter Crosthwaite
2015-04-24 19:10       ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 16/16] arm: xlnx-zynqmp: Add PSCI setup Peter Crosthwaite
2015-04-23 18:16   ` Peter Maydell
2015-04-24  0:46     ` Peter Crosthwaite
2015-03-30  1:21 ` [Qemu-devel] [PATCH target-arm v4 00/16] Next Generation Xilinx Zynq SoC Alistair Francis
     [not found] ` <267e60dda9e3d2ecfbd43d7fa86bf884a955ba44.1427108387.git.peter.crosthwaite@xilinx.com>
2015-04-23 17:52   ` [Qemu-devel] [PATCH target-arm v4 09/16] arm: xilinx-zynqmp: Add GEM support Peter Maydell
2015-04-24  0:12     ` Peter Crosthwaite
     [not found] ` <9c0afa7c2c54b22be3ad95f74efa4ccc3f0ca4ba.1427108387.git.peter.crosthwaite@xilinx.com>
2015-04-23 18:09   ` [Qemu-devel] [PATCH target-arm v4 12/16] arm: xilinx-zynqmp: Add UART support Peter Maydell

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