From: Alistair Francis <alistair23@gmail.com>
To: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Cc: Edgar Iglesias <edgar.iglesias@xilinx.com>,
Peter Maydell <peter.maydell@linaro.org>,
zach.pfeffer@xilinx.com, Ryota Ozaki <ozaki.ryota@gmail.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"michals@xilinx.com" <michals@xilinx.com>
Subject: Re: [Qemu-devel] [PATCH target-arm v4 06/16] arm: xlnx-zynqmp: Connect CPU Timers to GIC
Date: Mon, 30 Mar 2015 11:29:31 +1000 [thread overview]
Message-ID: <CAKmqyKPY7GDJ0ka6knMPMaNEUv_WtjEH51a7gSrDz0mkE5DJzg@mail.gmail.com> (raw)
In-Reply-To: <a873a22bb722ca08119605c378672e87141d9780.1427108387.git.peter.crosthwaite@xilinx.com>
On Mon, Mar 23, 2015 at 9:05 PM, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> Connect the GPIO outputs from the individual CPUs for the timers to the
> GIC.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> ---
> hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 9465185..29954f5 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -19,9 +19,17 @@
>
> #define GIC_NUM_SPI_INTR 128
>
> +#define ARM_PHYS_TIMER_PPI 30
> +#define ARM_VIRT_TIMER_PPI 27
> +
> #define GIC_DIST_ADDR 0xf9010000
> #define GIC_CPU_ADDR 0xf9020000
Hey Peter,
I'm wondering if the #define's should be in the header file?
>
> +static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
> +{
> + return GIC_NUM_SPI_INTR + cpu_nr * 32 + ppi_index;
Should the 32 also be a #define? Everything else is.
Thanks,
Alistair
> +}
> +
> static void xlnx_zynqmp_init(Object *obj)
> {
> XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
> @@ -60,11 +68,19 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, GIC_CPU_ADDR);
>
> for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
> + qemu_irq irq;
> +
> object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
> ERR_PROP_CHECK_RETURN(err, errp);
>
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
> qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
> + irq = qdev_get_gpio_in(DEVICE(&s->gic),
> + arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
> + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq);
> + irq = qdev_get_gpio_in(DEVICE(&s->gic),
> + arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
> + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
> }
> }
>
> --
> 2.3.1.2.g90df61e.dirty
>
>
next prev parent reply other threads:[~2015-03-30 1:30 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-23 11:05 [Qemu-devel] [PATCH target-arm v4 00/16] Next Generation Xilinx Zynq SoC Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 01/16] cpus: Don't kick un-realized cpus Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 02/16] target-arm: cpu64: Factor out ARM cortex init Peter Crosthwaite
2015-04-23 17:35 ` Peter Maydell
2015-04-24 16:39 ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 03/16] target-arm: cpu64: Add support for cortex-a53 Peter Crosthwaite
2015-03-23 13:17 ` Ryota Ozaki
2015-04-24 16:42 ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 05/16] arm: xlnx-zynqmp: Add GIC Peter Crosthwaite
2015-04-23 17:45 ` Peter Maydell
2015-04-23 23:55 ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 04/16] arm: Introduce Xilinx ZynqMP SoC Peter Crosthwaite
2015-03-30 1:17 ` Alistair Francis
2015-04-23 17:42 ` Peter Maydell
2015-04-23 19:21 ` Peter Crosthwaite
2015-04-23 21:38 ` Peter Maydell
2015-04-24 15:26 ` Peter Maydell
2015-04-24 16:31 ` Peter Crosthwaite
2015-04-23 17:47 ` Peter Maydell
2015-04-23 19:30 ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 06/16] arm: xlnx-zynqmp: Connect CPU Timers to GIC Peter Crosthwaite
2015-03-30 1:29 ` Alistair Francis [this message]
2015-04-24 0:02 ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 07/16] net: cadence_gem: Clean up variable names Peter Crosthwaite
2015-04-23 17:50 ` Peter Maydell
2015-04-24 16:51 ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 08/16] net: cadence_gem: Split state struct and type into header Peter Crosthwaite
2015-04-23 17:51 ` Peter Maydell
2015-04-24 0:10 ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 10/16] char: cadence_uart: Clean up variable names Peter Crosthwaite
2015-04-23 17:59 ` Peter Maydell
2015-04-24 0:25 ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 11/16] char: cadence_uart: Split state struct and type into header Peter Crosthwaite
2015-04-23 18:00 ` Peter Maydell
2015-04-24 0:20 ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 13/16] arm: Add xlnx-ep108 machine Peter Crosthwaite
2015-03-30 1:11 ` Alistair Francis
2015-04-23 18:09 ` Peter Maydell
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 14/16] arm: xilinx-ep108: Add external RAM Peter Crosthwaite
2015-03-30 1:31 ` Alistair Francis
2015-04-23 18:12 ` Peter Maydell
2015-04-24 0:36 ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 15/16] arm: xilinx-ep108: Add bootloading Peter Crosthwaite
2015-03-30 1:42 ` Alistair Francis
2015-04-23 18:15 ` Peter Maydell
2015-04-24 0:43 ` Peter Crosthwaite
2015-04-24 19:10 ` Peter Crosthwaite
2015-03-23 11:05 ` [Qemu-devel] [PATCH target-arm v4 16/16] arm: xlnx-zynqmp: Add PSCI setup Peter Crosthwaite
2015-04-23 18:16 ` Peter Maydell
2015-04-24 0:46 ` Peter Crosthwaite
2015-03-30 1:21 ` [Qemu-devel] [PATCH target-arm v4 00/16] Next Generation Xilinx Zynq SoC Alistair Francis
[not found] ` <267e60dda9e3d2ecfbd43d7fa86bf884a955ba44.1427108387.git.peter.crosthwaite@xilinx.com>
2015-04-23 17:52 ` [Qemu-devel] [PATCH target-arm v4 09/16] arm: xilinx-zynqmp: Add GEM support Peter Maydell
2015-04-24 0:12 ` Peter Crosthwaite
[not found] ` <9c0afa7c2c54b22be3ad95f74efa4ccc3f0ca4ba.1427108387.git.peter.crosthwaite@xilinx.com>
2015-04-23 18:09 ` [Qemu-devel] [PATCH target-arm v4 12/16] arm: xilinx-zynqmp: Add UART support Peter Maydell
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