* [Qemu-devel] [PATCH 0/5 v2] RISC-V: Add gdb xml files and gdbstub support.
@ 2018-12-28 22:05 ` Jim Wilson
0 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-28 22:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
This is the second version of the patch set. I haven't gotten any bug
reports for the patches in the several weeks that they have been
available, and no review yet, so the only significant difference from
the first version is that I ran them through checkpatch to fix style
issues, and I sent them to the right mailing list this time.
With these patches, I can run system qemu with -s -S, connect to it
with gdb, and then print any integer, FP, or CSR register. This
support is currently broken.
The first two patches in the series are just dropping in xml files
from gdb unchanged, with configure support to point at them. The next
two patches are the inconvenient stuff. The gdb CSR files are in
documentation order not numerical order, so I need an array to map the
gdb numbers to the actual hardware numbers. The gdb files should
probably be improved, but I don't know when that will happen. That is
the third patch. The fourth patch is to disable all of the illegal
instruction checks when accessing CSRs from the debugger, as it needs
to be able to access them without traps. The last patch adds the
gdbstub support to use the new xml files which is pretty simple,
though there is an unanswered question in there about what to do with
the FP registers. Should we try to configure them based on the
target? Right now I just always enable them which is the simple
solution. I'm not sure if enabling them based on the target will even
work with gdb or not.
Jim
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Qemu-riscv] [PATCH 0/5 v2] RISC-V: Add gdb xml files and gdbstub support.
@ 2018-12-28 22:05 ` Jim Wilson
0 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-28 22:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
This is the second version of the patch set. I haven't gotten any bug
reports for the patches in the several weeks that they have been
available, and no review yet, so the only significant difference from
the first version is that I ran them through checkpatch to fix style
issues, and I sent them to the right mailing list this time.
With these patches, I can run system qemu with -s -S, connect to it
with gdb, and then print any integer, FP, or CSR register. This
support is currently broken.
The first two patches in the series are just dropping in xml files
from gdb unchanged, with configure support to point at them. The next
two patches are the inconvenient stuff. The gdb CSR files are in
documentation order not numerical order, so I need an array to map the
gdb numbers to the actual hardware numbers. The gdb files should
probably be improved, but I don't know when that will happen. That is
the third patch. The fourth patch is to disable all of the illegal
instruction checks when accessing CSRs from the debugger, as it needs
to be able to access them without traps. The last patch adds the
gdbstub support to use the new xml files which is pretty simple,
though there is an unanswered question in there about what to do with
the FP registers. Should we try to configure them based on the
target? Right now I just always enable them which is the simple
solution. I'm not sure if enabling them based on the target will even
work with gdb or not.
Jim
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files.
2018-12-28 22:05 ` [Qemu-riscv] " Jim Wilson
@ 2018-12-28 22:07 ` Jim Wilson
-1 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-28 22:07 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
Signed-off-by: Jim Wilson <jimw@sifive.com>
---
configure | 1 +
gdb-xml/riscv-32bit-cpu.xml | 43 ++++++++
gdb-xml/riscv-32bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++
gdb-xml/riscv-32bit-fpu.xml | 46 ++++++++
4 files changed, 340 insertions(+)
create mode 100644 gdb-xml/riscv-32bit-cpu.xml
create mode 100644 gdb-xml/riscv-32bit-csr.xml
create mode 100644 gdb-xml/riscv-32bit-fpu.xml
diff --git a/configure b/configure
index 224d307..4e05eed 100755
--- a/configure
+++ b/configure
@@ -7208,6 +7208,7 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
+ gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml"
target_compiler=$cross_cc_riscv32
;;
riscv64)
diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
new file mode 100644
index 0000000..c02f86c
--- /dev/null
+++ b/gdb-xml/riscv-32bit-cpu.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="32" type="int"/>
+ <reg name="ra" bitsize="32" type="code_ptr"/>
+ <reg name="sp" bitsize="32" type="data_ptr"/>
+ <reg name="gp" bitsize="32" type="data_ptr"/>
+ <reg name="tp" bitsize="32" type="data_ptr"/>
+ <reg name="t0" bitsize="32" type="int"/>
+ <reg name="t1" bitsize="32" type="int"/>
+ <reg name="t2" bitsize="32" type="int"/>
+ <reg name="fp" bitsize="32" type="data_ptr"/>
+ <reg name="s1" bitsize="32" type="int"/>
+ <reg name="a0" bitsize="32" type="int"/>
+ <reg name="a1" bitsize="32" type="int"/>
+ <reg name="a2" bitsize="32" type="int"/>
+ <reg name="a3" bitsize="32" type="int"/>
+ <reg name="a4" bitsize="32" type="int"/>
+ <reg name="a5" bitsize="32" type="int"/>
+ <reg name="a6" bitsize="32" type="int"/>
+ <reg name="a7" bitsize="32" type="int"/>
+ <reg name="s2" bitsize="32" type="int"/>
+ <reg name="s3" bitsize="32" type="int"/>
+ <reg name="s4" bitsize="32" type="int"/>
+ <reg name="s5" bitsize="32" type="int"/>
+ <reg name="s6" bitsize="32" type="int"/>
+ <reg name="s7" bitsize="32" type="int"/>
+ <reg name="s8" bitsize="32" type="int"/>
+ <reg name="s9" bitsize="32" type="int"/>
+ <reg name="s10" bitsize="32" type="int"/>
+ <reg name="s11" bitsize="32" type="int"/>
+ <reg name="t3" bitsize="32" type="int"/>
+ <reg name="t4" bitsize="32" type="int"/>
+ <reg name="t5" bitsize="32" type="int"/>
+ <reg name="t6" bitsize="32" type="int"/>
+ <reg name="pc" bitsize="32" type="code_ptr"/>
+</feature>
diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
new file mode 100644
index 0000000..4aea9e6
--- /dev/null
+++ b/gdb-xml/riscv-32bit-csr.xml
@@ -0,0 +1,250 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.csr">
+ <reg name="ustatus" bitsize="32"/>
+ <reg name="uie" bitsize="32"/>
+ <reg name="utvec" bitsize="32"/>
+ <reg name="uscratch" bitsize="32"/>
+ <reg name="uepc" bitsize="32"/>
+ <reg name="ucause" bitsize="32"/>
+ <reg name="utval" bitsize="32"/>
+ <reg name="uip" bitsize="32"/>
+ <reg name="fflags" bitsize="32"/>
+ <reg name="frm" bitsize="32"/>
+ <reg name="fcsr" bitsize="32"/>
+ <reg name="cycle" bitsize="32"/>
+ <reg name="time" bitsize="32"/>
+ <reg name="instret" bitsize="32"/>
+ <reg name="hpmcounter3" bitsize="32"/>
+ <reg name="hpmcounter4" bitsize="32"/>
+ <reg name="hpmcounter5" bitsize="32"/>
+ <reg name="hpmcounter6" bitsize="32"/>
+ <reg name="hpmcounter7" bitsize="32"/>
+ <reg name="hpmcounter8" bitsize="32"/>
+ <reg name="hpmcounter9" bitsize="32"/>
+ <reg name="hpmcounter10" bitsize="32"/>
+ <reg name="hpmcounter11" bitsize="32"/>
+ <reg name="hpmcounter12" bitsize="32"/>
+ <reg name="hpmcounter13" bitsize="32"/>
+ <reg name="hpmcounter14" bitsize="32"/>
+ <reg name="hpmcounter15" bitsize="32"/>
+ <reg name="hpmcounter16" bitsize="32"/>
+ <reg name="hpmcounter17" bitsize="32"/>
+ <reg name="hpmcounter18" bitsize="32"/>
+ <reg name="hpmcounter19" bitsize="32"/>
+ <reg name="hpmcounter20" bitsize="32"/>
+ <reg name="hpmcounter21" bitsize="32"/>
+ <reg name="hpmcounter22" bitsize="32"/>
+ <reg name="hpmcounter23" bitsize="32"/>
+ <reg name="hpmcounter24" bitsize="32"/>
+ <reg name="hpmcounter25" bitsize="32"/>
+ <reg name="hpmcounter26" bitsize="32"/>
+ <reg name="hpmcounter27" bitsize="32"/>
+ <reg name="hpmcounter28" bitsize="32"/>
+ <reg name="hpmcounter29" bitsize="32"/>
+ <reg name="hpmcounter30" bitsize="32"/>
+ <reg name="hpmcounter31" bitsize="32"/>
+ <reg name="cycleh" bitsize="32"/>
+ <reg name="timeh" bitsize="32"/>
+ <reg name="instreth" bitsize="32"/>
+ <reg name="hpmcounter3h" bitsize="32"/>
+ <reg name="hpmcounter4h" bitsize="32"/>
+ <reg name="hpmcounter5h" bitsize="32"/>
+ <reg name="hpmcounter6h" bitsize="32"/>
+ <reg name="hpmcounter7h" bitsize="32"/>
+ <reg name="hpmcounter8h" bitsize="32"/>
+ <reg name="hpmcounter9h" bitsize="32"/>
+ <reg name="hpmcounter10h" bitsize="32"/>
+ <reg name="hpmcounter11h" bitsize="32"/>
+ <reg name="hpmcounter12h" bitsize="32"/>
+ <reg name="hpmcounter13h" bitsize="32"/>
+ <reg name="hpmcounter14h" bitsize="32"/>
+ <reg name="hpmcounter15h" bitsize="32"/>
+ <reg name="hpmcounter16h" bitsize="32"/>
+ <reg name="hpmcounter17h" bitsize="32"/>
+ <reg name="hpmcounter18h" bitsize="32"/>
+ <reg name="hpmcounter19h" bitsize="32"/>
+ <reg name="hpmcounter20h" bitsize="32"/>
+ <reg name="hpmcounter21h" bitsize="32"/>
+ <reg name="hpmcounter22h" bitsize="32"/>
+ <reg name="hpmcounter23h" bitsize="32"/>
+ <reg name="hpmcounter24h" bitsize="32"/>
+ <reg name="hpmcounter25h" bitsize="32"/>
+ <reg name="hpmcounter26h" bitsize="32"/>
+ <reg name="hpmcounter27h" bitsize="32"/>
+ <reg name="hpmcounter28h" bitsize="32"/>
+ <reg name="hpmcounter29h" bitsize="32"/>
+ <reg name="hpmcounter30h" bitsize="32"/>
+ <reg name="hpmcounter31h" bitsize="32"/>
+ <reg name="sstatus" bitsize="32"/>
+ <reg name="sedeleg" bitsize="32"/>
+ <reg name="sideleg" bitsize="32"/>
+ <reg name="sie" bitsize="32"/>
+ <reg name="stvec" bitsize="32"/>
+ <reg name="scounteren" bitsize="32"/>
+ <reg name="sscratch" bitsize="32"/>
+ <reg name="sepc" bitsize="32"/>
+ <reg name="scause" bitsize="32"/>
+ <reg name="stval" bitsize="32"/>
+ <reg name="sip" bitsize="32"/>
+ <reg name="satp" bitsize="32"/>
+ <reg name="mvendorid" bitsize="32"/>
+ <reg name="marchid" bitsize="32"/>
+ <reg name="mimpid" bitsize="32"/>
+ <reg name="mhartid" bitsize="32"/>
+ <reg name="mstatus" bitsize="32"/>
+ <reg name="misa" bitsize="32"/>
+ <reg name="medeleg" bitsize="32"/>
+ <reg name="mideleg" bitsize="32"/>
+ <reg name="mie" bitsize="32"/>
+ <reg name="mtvec" bitsize="32"/>
+ <reg name="mcounteren" bitsize="32"/>
+ <reg name="mscratch" bitsize="32"/>
+ <reg name="mepc" bitsize="32"/>
+ <reg name="mcause" bitsize="32"/>
+ <reg name="mtval" bitsize="32"/>
+ <reg name="mip" bitsize="32"/>
+ <reg name="pmpcfg0" bitsize="32"/>
+ <reg name="pmpcfg1" bitsize="32"/>
+ <reg name="pmpcfg2" bitsize="32"/>
+ <reg name="pmpcfg3" bitsize="32"/>
+ <reg name="pmpaddr0" bitsize="32"/>
+ <reg name="pmpaddr1" bitsize="32"/>
+ <reg name="pmpaddr2" bitsize="32"/>
+ <reg name="pmpaddr3" bitsize="32"/>
+ <reg name="pmpaddr4" bitsize="32"/>
+ <reg name="pmpaddr5" bitsize="32"/>
+ <reg name="pmpaddr6" bitsize="32"/>
+ <reg name="pmpaddr7" bitsize="32"/>
+ <reg name="pmpaddr8" bitsize="32"/>
+ <reg name="pmpaddr9" bitsize="32"/>
+ <reg name="pmpaddr10" bitsize="32"/>
+ <reg name="pmpaddr11" bitsize="32"/>
+ <reg name="pmpaddr12" bitsize="32"/>
+ <reg name="pmpaddr13" bitsize="32"/>
+ <reg name="pmpaddr14" bitsize="32"/>
+ <reg name="pmpaddr15" bitsize="32"/>
+ <reg name="mcycle" bitsize="32"/>
+ <reg name="minstret" bitsize="32"/>
+ <reg name="mhpmcounter3" bitsize="32"/>
+ <reg name="mhpmcounter4" bitsize="32"/>
+ <reg name="mhpmcounter5" bitsize="32"/>
+ <reg name="mhpmcounter6" bitsize="32"/>
+ <reg name="mhpmcounter7" bitsize="32"/>
+ <reg name="mhpmcounter8" bitsize="32"/>
+ <reg name="mhpmcounter9" bitsize="32"/>
+ <reg name="mhpmcounter10" bitsize="32"/>
+ <reg name="mhpmcounter11" bitsize="32"/>
+ <reg name="mhpmcounter12" bitsize="32"/>
+ <reg name="mhpmcounter13" bitsize="32"/>
+ <reg name="mhpmcounter14" bitsize="32"/>
+ <reg name="mhpmcounter15" bitsize="32"/>
+ <reg name="mhpmcounter16" bitsize="32"/>
+ <reg name="mhpmcounter17" bitsize="32"/>
+ <reg name="mhpmcounter18" bitsize="32"/>
+ <reg name="mhpmcounter19" bitsize="32"/>
+ <reg name="mhpmcounter20" bitsize="32"/>
+ <reg name="mhpmcounter21" bitsize="32"/>
+ <reg name="mhpmcounter22" bitsize="32"/>
+ <reg name="mhpmcounter23" bitsize="32"/>
+ <reg name="mhpmcounter24" bitsize="32"/>
+ <reg name="mhpmcounter25" bitsize="32"/>
+ <reg name="mhpmcounter26" bitsize="32"/>
+ <reg name="mhpmcounter27" bitsize="32"/>
+ <reg name="mhpmcounter28" bitsize="32"/>
+ <reg name="mhpmcounter29" bitsize="32"/>
+ <reg name="mhpmcounter30" bitsize="32"/>
+ <reg name="mhpmcounter31" bitsize="32"/>
+ <reg name="mcycleh" bitsize="32"/>
+ <reg name="minstreth" bitsize="32"/>
+ <reg name="mhpmcounter3h" bitsize="32"/>
+ <reg name="mhpmcounter4h" bitsize="32"/>
+ <reg name="mhpmcounter5h" bitsize="32"/>
+ <reg name="mhpmcounter6h" bitsize="32"/>
+ <reg name="mhpmcounter7h" bitsize="32"/>
+ <reg name="mhpmcounter8h" bitsize="32"/>
+ <reg name="mhpmcounter9h" bitsize="32"/>
+ <reg name="mhpmcounter10h" bitsize="32"/>
+ <reg name="mhpmcounter11h" bitsize="32"/>
+ <reg name="mhpmcounter12h" bitsize="32"/>
+ <reg name="mhpmcounter13h" bitsize="32"/>
+ <reg name="mhpmcounter14h" bitsize="32"/>
+ <reg name="mhpmcounter15h" bitsize="32"/>
+ <reg name="mhpmcounter16h" bitsize="32"/>
+ <reg name="mhpmcounter17h" bitsize="32"/>
+ <reg name="mhpmcounter18h" bitsize="32"/>
+ <reg name="mhpmcounter19h" bitsize="32"/>
+ <reg name="mhpmcounter20h" bitsize="32"/>
+ <reg name="mhpmcounter21h" bitsize="32"/>
+ <reg name="mhpmcounter22h" bitsize="32"/>
+ <reg name="mhpmcounter23h" bitsize="32"/>
+ <reg name="mhpmcounter24h" bitsize="32"/>
+ <reg name="mhpmcounter25h" bitsize="32"/>
+ <reg name="mhpmcounter26h" bitsize="32"/>
+ <reg name="mhpmcounter27h" bitsize="32"/>
+ <reg name="mhpmcounter28h" bitsize="32"/>
+ <reg name="mhpmcounter29h" bitsize="32"/>
+ <reg name="mhpmcounter30h" bitsize="32"/>
+ <reg name="mhpmcounter31h" bitsize="32"/>
+ <reg name="mhpmevent3" bitsize="32"/>
+ <reg name="mhpmevent4" bitsize="32"/>
+ <reg name="mhpmevent5" bitsize="32"/>
+ <reg name="mhpmevent6" bitsize="32"/>
+ <reg name="mhpmevent7" bitsize="32"/>
+ <reg name="mhpmevent8" bitsize="32"/>
+ <reg name="mhpmevent9" bitsize="32"/>
+ <reg name="mhpmevent10" bitsize="32"/>
+ <reg name="mhpmevent11" bitsize="32"/>
+ <reg name="mhpmevent12" bitsize="32"/>
+ <reg name="mhpmevent13" bitsize="32"/>
+ <reg name="mhpmevent14" bitsize="32"/>
+ <reg name="mhpmevent15" bitsize="32"/>
+ <reg name="mhpmevent16" bitsize="32"/>
+ <reg name="mhpmevent17" bitsize="32"/>
+ <reg name="mhpmevent18" bitsize="32"/>
+ <reg name="mhpmevent19" bitsize="32"/>
+ <reg name="mhpmevent20" bitsize="32"/>
+ <reg name="mhpmevent21" bitsize="32"/>
+ <reg name="mhpmevent22" bitsize="32"/>
+ <reg name="mhpmevent23" bitsize="32"/>
+ <reg name="mhpmevent24" bitsize="32"/>
+ <reg name="mhpmevent25" bitsize="32"/>
+ <reg name="mhpmevent26" bitsize="32"/>
+ <reg name="mhpmevent27" bitsize="32"/>
+ <reg name="mhpmevent28" bitsize="32"/>
+ <reg name="mhpmevent29" bitsize="32"/>
+ <reg name="mhpmevent30" bitsize="32"/>
+ <reg name="mhpmevent31" bitsize="32"/>
+ <reg name="tselect" bitsize="32"/>
+ <reg name="tdata1" bitsize="32"/>
+ <reg name="tdata2" bitsize="32"/>
+ <reg name="tdata3" bitsize="32"/>
+ <reg name="dcsr" bitsize="32"/>
+ <reg name="dpc" bitsize="32"/>
+ <reg name="dscratch" bitsize="32"/>
+ <reg name="hstatus" bitsize="32"/>
+ <reg name="hedeleg" bitsize="32"/>
+ <reg name="hideleg" bitsize="32"/>
+ <reg name="hie" bitsize="32"/>
+ <reg name="htvec" bitsize="32"/>
+ <reg name="hscratch" bitsize="32"/>
+ <reg name="hepc" bitsize="32"/>
+ <reg name="hcause" bitsize="32"/>
+ <reg name="hbadaddr" bitsize="32"/>
+ <reg name="hip" bitsize="32"/>
+ <reg name="mbase" bitsize="32"/>
+ <reg name="mbound" bitsize="32"/>
+ <reg name="mibase" bitsize="32"/>
+ <reg name="mibound" bitsize="32"/>
+ <reg name="mdbase" bitsize="32"/>
+ <reg name="mdbound" bitsize="32"/>
+ <reg name="mucounteren" bitsize="32"/>
+ <reg name="mscounteren" bitsize="32"/>
+ <reg name="mhcounteren" bitsize="32"/>
+</feature>
diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml
new file mode 100644
index 0000000..783287d
--- /dev/null
+++ b/gdb-xml/riscv-32bit-fpu.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.fpu">
+ <reg name="ft0" bitsize="32" type="ieee_single"/>
+ <reg name="ft1" bitsize="32" type="ieee_single"/>
+ <reg name="ft2" bitsize="32" type="ieee_single"/>
+ <reg name="ft3" bitsize="32" type="ieee_single"/>
+ <reg name="ft4" bitsize="32" type="ieee_single"/>
+ <reg name="ft5" bitsize="32" type="ieee_single"/>
+ <reg name="ft6" bitsize="32" type="ieee_single"/>
+ <reg name="ft7" bitsize="32" type="ieee_single"/>
+ <reg name="fs0" bitsize="32" type="ieee_single"/>
+ <reg name="fs1" bitsize="32" type="ieee_single"/>
+ <reg name="fa0" bitsize="32" type="ieee_single"/>
+ <reg name="fa1" bitsize="32" type="ieee_single"/>
+ <reg name="fa2" bitsize="32" type="ieee_single"/>
+ <reg name="fa3" bitsize="32" type="ieee_single"/>
+ <reg name="fa4" bitsize="32" type="ieee_single"/>
+ <reg name="fa5" bitsize="32" type="ieee_single"/>
+ <reg name="fa6" bitsize="32" type="ieee_single"/>
+ <reg name="fa7" bitsize="32" type="ieee_single"/>
+ <reg name="fs2" bitsize="32" type="ieee_single"/>
+ <reg name="fs3" bitsize="32" type="ieee_single"/>
+ <reg name="fs4" bitsize="32" type="ieee_single"/>
+ <reg name="fs5" bitsize="32" type="ieee_single"/>
+ <reg name="fs6" bitsize="32" type="ieee_single"/>
+ <reg name="fs7" bitsize="32" type="ieee_single"/>
+ <reg name="fs8" bitsize="32" type="ieee_single"/>
+ <reg name="fs9" bitsize="32" type="ieee_single"/>
+ <reg name="fs10" bitsize="32" type="ieee_single"/>
+ <reg name="fs11" bitsize="32" type="ieee_single"/>
+ <reg name="ft8" bitsize="32" type="ieee_single"/>
+ <reg name="ft9" bitsize="32" type="ieee_single"/>
+ <reg name="ft10" bitsize="32" type="ieee_single"/>
+ <reg name="ft11" bitsize="32" type="ieee_single"/>
+
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+</feature>
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-riscv] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files.
@ 2018-12-28 22:07 ` Jim Wilson
0 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-28 22:07 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
Signed-off-by: Jim Wilson <jimw@sifive.com>
---
configure | 1 +
gdb-xml/riscv-32bit-cpu.xml | 43 ++++++++
gdb-xml/riscv-32bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++
gdb-xml/riscv-32bit-fpu.xml | 46 ++++++++
4 files changed, 340 insertions(+)
create mode 100644 gdb-xml/riscv-32bit-cpu.xml
create mode 100644 gdb-xml/riscv-32bit-csr.xml
create mode 100644 gdb-xml/riscv-32bit-fpu.xml
diff --git a/configure b/configure
index 224d307..4e05eed 100755
--- a/configure
+++ b/configure
@@ -7208,6 +7208,7 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
+ gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml"
target_compiler=$cross_cc_riscv32
;;
riscv64)
diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
new file mode 100644
index 0000000..c02f86c
--- /dev/null
+++ b/gdb-xml/riscv-32bit-cpu.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="32" type="int"/>
+ <reg name="ra" bitsize="32" type="code_ptr"/>
+ <reg name="sp" bitsize="32" type="data_ptr"/>
+ <reg name="gp" bitsize="32" type="data_ptr"/>
+ <reg name="tp" bitsize="32" type="data_ptr"/>
+ <reg name="t0" bitsize="32" type="int"/>
+ <reg name="t1" bitsize="32" type="int"/>
+ <reg name="t2" bitsize="32" type="int"/>
+ <reg name="fp" bitsize="32" type="data_ptr"/>
+ <reg name="s1" bitsize="32" type="int"/>
+ <reg name="a0" bitsize="32" type="int"/>
+ <reg name="a1" bitsize="32" type="int"/>
+ <reg name="a2" bitsize="32" type="int"/>
+ <reg name="a3" bitsize="32" type="int"/>
+ <reg name="a4" bitsize="32" type="int"/>
+ <reg name="a5" bitsize="32" type="int"/>
+ <reg name="a6" bitsize="32" type="int"/>
+ <reg name="a7" bitsize="32" type="int"/>
+ <reg name="s2" bitsize="32" type="int"/>
+ <reg name="s3" bitsize="32" type="int"/>
+ <reg name="s4" bitsize="32" type="int"/>
+ <reg name="s5" bitsize="32" type="int"/>
+ <reg name="s6" bitsize="32" type="int"/>
+ <reg name="s7" bitsize="32" type="int"/>
+ <reg name="s8" bitsize="32" type="int"/>
+ <reg name="s9" bitsize="32" type="int"/>
+ <reg name="s10" bitsize="32" type="int"/>
+ <reg name="s11" bitsize="32" type="int"/>
+ <reg name="t3" bitsize="32" type="int"/>
+ <reg name="t4" bitsize="32" type="int"/>
+ <reg name="t5" bitsize="32" type="int"/>
+ <reg name="t6" bitsize="32" type="int"/>
+ <reg name="pc" bitsize="32" type="code_ptr"/>
+</feature>
diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
new file mode 100644
index 0000000..4aea9e6
--- /dev/null
+++ b/gdb-xml/riscv-32bit-csr.xml
@@ -0,0 +1,250 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.csr">
+ <reg name="ustatus" bitsize="32"/>
+ <reg name="uie" bitsize="32"/>
+ <reg name="utvec" bitsize="32"/>
+ <reg name="uscratch" bitsize="32"/>
+ <reg name="uepc" bitsize="32"/>
+ <reg name="ucause" bitsize="32"/>
+ <reg name="utval" bitsize="32"/>
+ <reg name="uip" bitsize="32"/>
+ <reg name="fflags" bitsize="32"/>
+ <reg name="frm" bitsize="32"/>
+ <reg name="fcsr" bitsize="32"/>
+ <reg name="cycle" bitsize="32"/>
+ <reg name="time" bitsize="32"/>
+ <reg name="instret" bitsize="32"/>
+ <reg name="hpmcounter3" bitsize="32"/>
+ <reg name="hpmcounter4" bitsize="32"/>
+ <reg name="hpmcounter5" bitsize="32"/>
+ <reg name="hpmcounter6" bitsize="32"/>
+ <reg name="hpmcounter7" bitsize="32"/>
+ <reg name="hpmcounter8" bitsize="32"/>
+ <reg name="hpmcounter9" bitsize="32"/>
+ <reg name="hpmcounter10" bitsize="32"/>
+ <reg name="hpmcounter11" bitsize="32"/>
+ <reg name="hpmcounter12" bitsize="32"/>
+ <reg name="hpmcounter13" bitsize="32"/>
+ <reg name="hpmcounter14" bitsize="32"/>
+ <reg name="hpmcounter15" bitsize="32"/>
+ <reg name="hpmcounter16" bitsize="32"/>
+ <reg name="hpmcounter17" bitsize="32"/>
+ <reg name="hpmcounter18" bitsize="32"/>
+ <reg name="hpmcounter19" bitsize="32"/>
+ <reg name="hpmcounter20" bitsize="32"/>
+ <reg name="hpmcounter21" bitsize="32"/>
+ <reg name="hpmcounter22" bitsize="32"/>
+ <reg name="hpmcounter23" bitsize="32"/>
+ <reg name="hpmcounter24" bitsize="32"/>
+ <reg name="hpmcounter25" bitsize="32"/>
+ <reg name="hpmcounter26" bitsize="32"/>
+ <reg name="hpmcounter27" bitsize="32"/>
+ <reg name="hpmcounter28" bitsize="32"/>
+ <reg name="hpmcounter29" bitsize="32"/>
+ <reg name="hpmcounter30" bitsize="32"/>
+ <reg name="hpmcounter31" bitsize="32"/>
+ <reg name="cycleh" bitsize="32"/>
+ <reg name="timeh" bitsize="32"/>
+ <reg name="instreth" bitsize="32"/>
+ <reg name="hpmcounter3h" bitsize="32"/>
+ <reg name="hpmcounter4h" bitsize="32"/>
+ <reg name="hpmcounter5h" bitsize="32"/>
+ <reg name="hpmcounter6h" bitsize="32"/>
+ <reg name="hpmcounter7h" bitsize="32"/>
+ <reg name="hpmcounter8h" bitsize="32"/>
+ <reg name="hpmcounter9h" bitsize="32"/>
+ <reg name="hpmcounter10h" bitsize="32"/>
+ <reg name="hpmcounter11h" bitsize="32"/>
+ <reg name="hpmcounter12h" bitsize="32"/>
+ <reg name="hpmcounter13h" bitsize="32"/>
+ <reg name="hpmcounter14h" bitsize="32"/>
+ <reg name="hpmcounter15h" bitsize="32"/>
+ <reg name="hpmcounter16h" bitsize="32"/>
+ <reg name="hpmcounter17h" bitsize="32"/>
+ <reg name="hpmcounter18h" bitsize="32"/>
+ <reg name="hpmcounter19h" bitsize="32"/>
+ <reg name="hpmcounter20h" bitsize="32"/>
+ <reg name="hpmcounter21h" bitsize="32"/>
+ <reg name="hpmcounter22h" bitsize="32"/>
+ <reg name="hpmcounter23h" bitsize="32"/>
+ <reg name="hpmcounter24h" bitsize="32"/>
+ <reg name="hpmcounter25h" bitsize="32"/>
+ <reg name="hpmcounter26h" bitsize="32"/>
+ <reg name="hpmcounter27h" bitsize="32"/>
+ <reg name="hpmcounter28h" bitsize="32"/>
+ <reg name="hpmcounter29h" bitsize="32"/>
+ <reg name="hpmcounter30h" bitsize="32"/>
+ <reg name="hpmcounter31h" bitsize="32"/>
+ <reg name="sstatus" bitsize="32"/>
+ <reg name="sedeleg" bitsize="32"/>
+ <reg name="sideleg" bitsize="32"/>
+ <reg name="sie" bitsize="32"/>
+ <reg name="stvec" bitsize="32"/>
+ <reg name="scounteren" bitsize="32"/>
+ <reg name="sscratch" bitsize="32"/>
+ <reg name="sepc" bitsize="32"/>
+ <reg name="scause" bitsize="32"/>
+ <reg name="stval" bitsize="32"/>
+ <reg name="sip" bitsize="32"/>
+ <reg name="satp" bitsize="32"/>
+ <reg name="mvendorid" bitsize="32"/>
+ <reg name="marchid" bitsize="32"/>
+ <reg name="mimpid" bitsize="32"/>
+ <reg name="mhartid" bitsize="32"/>
+ <reg name="mstatus" bitsize="32"/>
+ <reg name="misa" bitsize="32"/>
+ <reg name="medeleg" bitsize="32"/>
+ <reg name="mideleg" bitsize="32"/>
+ <reg name="mie" bitsize="32"/>
+ <reg name="mtvec" bitsize="32"/>
+ <reg name="mcounteren" bitsize="32"/>
+ <reg name="mscratch" bitsize="32"/>
+ <reg name="mepc" bitsize="32"/>
+ <reg name="mcause" bitsize="32"/>
+ <reg name="mtval" bitsize="32"/>
+ <reg name="mip" bitsize="32"/>
+ <reg name="pmpcfg0" bitsize="32"/>
+ <reg name="pmpcfg1" bitsize="32"/>
+ <reg name="pmpcfg2" bitsize="32"/>
+ <reg name="pmpcfg3" bitsize="32"/>
+ <reg name="pmpaddr0" bitsize="32"/>
+ <reg name="pmpaddr1" bitsize="32"/>
+ <reg name="pmpaddr2" bitsize="32"/>
+ <reg name="pmpaddr3" bitsize="32"/>
+ <reg name="pmpaddr4" bitsize="32"/>
+ <reg name="pmpaddr5" bitsize="32"/>
+ <reg name="pmpaddr6" bitsize="32"/>
+ <reg name="pmpaddr7" bitsize="32"/>
+ <reg name="pmpaddr8" bitsize="32"/>
+ <reg name="pmpaddr9" bitsize="32"/>
+ <reg name="pmpaddr10" bitsize="32"/>
+ <reg name="pmpaddr11" bitsize="32"/>
+ <reg name="pmpaddr12" bitsize="32"/>
+ <reg name="pmpaddr13" bitsize="32"/>
+ <reg name="pmpaddr14" bitsize="32"/>
+ <reg name="pmpaddr15" bitsize="32"/>
+ <reg name="mcycle" bitsize="32"/>
+ <reg name="minstret" bitsize="32"/>
+ <reg name="mhpmcounter3" bitsize="32"/>
+ <reg name="mhpmcounter4" bitsize="32"/>
+ <reg name="mhpmcounter5" bitsize="32"/>
+ <reg name="mhpmcounter6" bitsize="32"/>
+ <reg name="mhpmcounter7" bitsize="32"/>
+ <reg name="mhpmcounter8" bitsize="32"/>
+ <reg name="mhpmcounter9" bitsize="32"/>
+ <reg name="mhpmcounter10" bitsize="32"/>
+ <reg name="mhpmcounter11" bitsize="32"/>
+ <reg name="mhpmcounter12" bitsize="32"/>
+ <reg name="mhpmcounter13" bitsize="32"/>
+ <reg name="mhpmcounter14" bitsize="32"/>
+ <reg name="mhpmcounter15" bitsize="32"/>
+ <reg name="mhpmcounter16" bitsize="32"/>
+ <reg name="mhpmcounter17" bitsize="32"/>
+ <reg name="mhpmcounter18" bitsize="32"/>
+ <reg name="mhpmcounter19" bitsize="32"/>
+ <reg name="mhpmcounter20" bitsize="32"/>
+ <reg name="mhpmcounter21" bitsize="32"/>
+ <reg name="mhpmcounter22" bitsize="32"/>
+ <reg name="mhpmcounter23" bitsize="32"/>
+ <reg name="mhpmcounter24" bitsize="32"/>
+ <reg name="mhpmcounter25" bitsize="32"/>
+ <reg name="mhpmcounter26" bitsize="32"/>
+ <reg name="mhpmcounter27" bitsize="32"/>
+ <reg name="mhpmcounter28" bitsize="32"/>
+ <reg name="mhpmcounter29" bitsize="32"/>
+ <reg name="mhpmcounter30" bitsize="32"/>
+ <reg name="mhpmcounter31" bitsize="32"/>
+ <reg name="mcycleh" bitsize="32"/>
+ <reg name="minstreth" bitsize="32"/>
+ <reg name="mhpmcounter3h" bitsize="32"/>
+ <reg name="mhpmcounter4h" bitsize="32"/>
+ <reg name="mhpmcounter5h" bitsize="32"/>
+ <reg name="mhpmcounter6h" bitsize="32"/>
+ <reg name="mhpmcounter7h" bitsize="32"/>
+ <reg name="mhpmcounter8h" bitsize="32"/>
+ <reg name="mhpmcounter9h" bitsize="32"/>
+ <reg name="mhpmcounter10h" bitsize="32"/>
+ <reg name="mhpmcounter11h" bitsize="32"/>
+ <reg name="mhpmcounter12h" bitsize="32"/>
+ <reg name="mhpmcounter13h" bitsize="32"/>
+ <reg name="mhpmcounter14h" bitsize="32"/>
+ <reg name="mhpmcounter15h" bitsize="32"/>
+ <reg name="mhpmcounter16h" bitsize="32"/>
+ <reg name="mhpmcounter17h" bitsize="32"/>
+ <reg name="mhpmcounter18h" bitsize="32"/>
+ <reg name="mhpmcounter19h" bitsize="32"/>
+ <reg name="mhpmcounter20h" bitsize="32"/>
+ <reg name="mhpmcounter21h" bitsize="32"/>
+ <reg name="mhpmcounter22h" bitsize="32"/>
+ <reg name="mhpmcounter23h" bitsize="32"/>
+ <reg name="mhpmcounter24h" bitsize="32"/>
+ <reg name="mhpmcounter25h" bitsize="32"/>
+ <reg name="mhpmcounter26h" bitsize="32"/>
+ <reg name="mhpmcounter27h" bitsize="32"/>
+ <reg name="mhpmcounter28h" bitsize="32"/>
+ <reg name="mhpmcounter29h" bitsize="32"/>
+ <reg name="mhpmcounter30h" bitsize="32"/>
+ <reg name="mhpmcounter31h" bitsize="32"/>
+ <reg name="mhpmevent3" bitsize="32"/>
+ <reg name="mhpmevent4" bitsize="32"/>
+ <reg name="mhpmevent5" bitsize="32"/>
+ <reg name="mhpmevent6" bitsize="32"/>
+ <reg name="mhpmevent7" bitsize="32"/>
+ <reg name="mhpmevent8" bitsize="32"/>
+ <reg name="mhpmevent9" bitsize="32"/>
+ <reg name="mhpmevent10" bitsize="32"/>
+ <reg name="mhpmevent11" bitsize="32"/>
+ <reg name="mhpmevent12" bitsize="32"/>
+ <reg name="mhpmevent13" bitsize="32"/>
+ <reg name="mhpmevent14" bitsize="32"/>
+ <reg name="mhpmevent15" bitsize="32"/>
+ <reg name="mhpmevent16" bitsize="32"/>
+ <reg name="mhpmevent17" bitsize="32"/>
+ <reg name="mhpmevent18" bitsize="32"/>
+ <reg name="mhpmevent19" bitsize="32"/>
+ <reg name="mhpmevent20" bitsize="32"/>
+ <reg name="mhpmevent21" bitsize="32"/>
+ <reg name="mhpmevent22" bitsize="32"/>
+ <reg name="mhpmevent23" bitsize="32"/>
+ <reg name="mhpmevent24" bitsize="32"/>
+ <reg name="mhpmevent25" bitsize="32"/>
+ <reg name="mhpmevent26" bitsize="32"/>
+ <reg name="mhpmevent27" bitsize="32"/>
+ <reg name="mhpmevent28" bitsize="32"/>
+ <reg name="mhpmevent29" bitsize="32"/>
+ <reg name="mhpmevent30" bitsize="32"/>
+ <reg name="mhpmevent31" bitsize="32"/>
+ <reg name="tselect" bitsize="32"/>
+ <reg name="tdata1" bitsize="32"/>
+ <reg name="tdata2" bitsize="32"/>
+ <reg name="tdata3" bitsize="32"/>
+ <reg name="dcsr" bitsize="32"/>
+ <reg name="dpc" bitsize="32"/>
+ <reg name="dscratch" bitsize="32"/>
+ <reg name="hstatus" bitsize="32"/>
+ <reg name="hedeleg" bitsize="32"/>
+ <reg name="hideleg" bitsize="32"/>
+ <reg name="hie" bitsize="32"/>
+ <reg name="htvec" bitsize="32"/>
+ <reg name="hscratch" bitsize="32"/>
+ <reg name="hepc" bitsize="32"/>
+ <reg name="hcause" bitsize="32"/>
+ <reg name="hbadaddr" bitsize="32"/>
+ <reg name="hip" bitsize="32"/>
+ <reg name="mbase" bitsize="32"/>
+ <reg name="mbound" bitsize="32"/>
+ <reg name="mibase" bitsize="32"/>
+ <reg name="mibound" bitsize="32"/>
+ <reg name="mdbase" bitsize="32"/>
+ <reg name="mdbound" bitsize="32"/>
+ <reg name="mucounteren" bitsize="32"/>
+ <reg name="mscounteren" bitsize="32"/>
+ <reg name="mhcounteren" bitsize="32"/>
+</feature>
diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml
new file mode 100644
index 0000000..783287d
--- /dev/null
+++ b/gdb-xml/riscv-32bit-fpu.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.fpu">
+ <reg name="ft0" bitsize="32" type="ieee_single"/>
+ <reg name="ft1" bitsize="32" type="ieee_single"/>
+ <reg name="ft2" bitsize="32" type="ieee_single"/>
+ <reg name="ft3" bitsize="32" type="ieee_single"/>
+ <reg name="ft4" bitsize="32" type="ieee_single"/>
+ <reg name="ft5" bitsize="32" type="ieee_single"/>
+ <reg name="ft6" bitsize="32" type="ieee_single"/>
+ <reg name="ft7" bitsize="32" type="ieee_single"/>
+ <reg name="fs0" bitsize="32" type="ieee_single"/>
+ <reg name="fs1" bitsize="32" type="ieee_single"/>
+ <reg name="fa0" bitsize="32" type="ieee_single"/>
+ <reg name="fa1" bitsize="32" type="ieee_single"/>
+ <reg name="fa2" bitsize="32" type="ieee_single"/>
+ <reg name="fa3" bitsize="32" type="ieee_single"/>
+ <reg name="fa4" bitsize="32" type="ieee_single"/>
+ <reg name="fa5" bitsize="32" type="ieee_single"/>
+ <reg name="fa6" bitsize="32" type="ieee_single"/>
+ <reg name="fa7" bitsize="32" type="ieee_single"/>
+ <reg name="fs2" bitsize="32" type="ieee_single"/>
+ <reg name="fs3" bitsize="32" type="ieee_single"/>
+ <reg name="fs4" bitsize="32" type="ieee_single"/>
+ <reg name="fs5" bitsize="32" type="ieee_single"/>
+ <reg name="fs6" bitsize="32" type="ieee_single"/>
+ <reg name="fs7" bitsize="32" type="ieee_single"/>
+ <reg name="fs8" bitsize="32" type="ieee_single"/>
+ <reg name="fs9" bitsize="32" type="ieee_single"/>
+ <reg name="fs10" bitsize="32" type="ieee_single"/>
+ <reg name="fs11" bitsize="32" type="ieee_single"/>
+ <reg name="ft8" bitsize="32" type="ieee_single"/>
+ <reg name="ft9" bitsize="32" type="ieee_single"/>
+ <reg name="ft10" bitsize="32" type="ieee_single"/>
+ <reg name="ft11" bitsize="32" type="ieee_single"/>
+
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+</feature>
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 2/5 v2] RISC-V: Add 64-bit gdb xml files.
2018-12-28 22:05 ` [Qemu-riscv] " Jim Wilson
@ 2018-12-28 22:08 ` Jim Wilson
-1 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-28 22:08 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
Signed-off-by: Jim Wilson <jimw@sifive.com>
---
configure | 1 +
gdb-xml/riscv-64bit-cpu.xml | 43 ++++++++
gdb-xml/riscv-64bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++
gdb-xml/riscv-64bit-fpu.xml | 52 +++++++++
4 files changed, 346 insertions(+)
create mode 100644 gdb-xml/riscv-64bit-cpu.xml
create mode 100644 gdb-xml/riscv-64bit-csr.xml
create mode 100644 gdb-xml/riscv-64bit-fpu.xml
diff --git a/configure b/configure
index 4e05eed..00b7495 100755
--- a/configure
+++ b/configure
@@ -7215,6 +7215,7 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
+ gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
target_compiler=$cross_cc_riscv64
;;
sh4|sh4eb)
diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml
new file mode 100644
index 0000000..f37d7f3
--- /dev/null
+++ b/gdb-xml/riscv-64bit-cpu.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="64" type="int"/>
+ <reg name="ra" bitsize="64" type="code_ptr"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+ <reg name="gp" bitsize="64" type="data_ptr"/>
+ <reg name="tp" bitsize="64" type="data_ptr"/>
+ <reg name="t0" bitsize="64" type="int"/>
+ <reg name="t1" bitsize="64" type="int"/>
+ <reg name="t2" bitsize="64" type="int"/>
+ <reg name="fp" bitsize="64" type="data_ptr"/>
+ <reg name="s1" bitsize="64" type="int"/>
+ <reg name="a0" bitsize="64" type="int"/>
+ <reg name="a1" bitsize="64" type="int"/>
+ <reg name="a2" bitsize="64" type="int"/>
+ <reg name="a3" bitsize="64" type="int"/>
+ <reg name="a4" bitsize="64" type="int"/>
+ <reg name="a5" bitsize="64" type="int"/>
+ <reg name="a6" bitsize="64" type="int"/>
+ <reg name="a7" bitsize="64" type="int"/>
+ <reg name="s2" bitsize="64" type="int"/>
+ <reg name="s3" bitsize="64" type="int"/>
+ <reg name="s4" bitsize="64" type="int"/>
+ <reg name="s5" bitsize="64" type="int"/>
+ <reg name="s6" bitsize="64" type="int"/>
+ <reg name="s7" bitsize="64" type="int"/>
+ <reg name="s8" bitsize="64" type="int"/>
+ <reg name="s9" bitsize="64" type="int"/>
+ <reg name="s10" bitsize="64" type="int"/>
+ <reg name="s11" bitsize="64" type="int"/>
+ <reg name="t3" bitsize="64" type="int"/>
+ <reg name="t4" bitsize="64" type="int"/>
+ <reg name="t5" bitsize="64" type="int"/>
+ <reg name="t6" bitsize="64" type="int"/>
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+</feature>
diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml
new file mode 100644
index 0000000..a3de834
--- /dev/null
+++ b/gdb-xml/riscv-64bit-csr.xml
@@ -0,0 +1,250 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.csr">
+ <reg name="ustatus" bitsize="64"/>
+ <reg name="uie" bitsize="64"/>
+ <reg name="utvec" bitsize="64"/>
+ <reg name="uscratch" bitsize="64"/>
+ <reg name="uepc" bitsize="64"/>
+ <reg name="ucause" bitsize="64"/>
+ <reg name="utval" bitsize="64"/>
+ <reg name="uip" bitsize="64"/>
+ <reg name="fflags" bitsize="64"/>
+ <reg name="frm" bitsize="64"/>
+ <reg name="fcsr" bitsize="64"/>
+ <reg name="cycle" bitsize="64"/>
+ <reg name="time" bitsize="64"/>
+ <reg name="instret" bitsize="64"/>
+ <reg name="hpmcounter3" bitsize="64"/>
+ <reg name="hpmcounter4" bitsize="64"/>
+ <reg name="hpmcounter5" bitsize="64"/>
+ <reg name="hpmcounter6" bitsize="64"/>
+ <reg name="hpmcounter7" bitsize="64"/>
+ <reg name="hpmcounter8" bitsize="64"/>
+ <reg name="hpmcounter9" bitsize="64"/>
+ <reg name="hpmcounter10" bitsize="64"/>
+ <reg name="hpmcounter11" bitsize="64"/>
+ <reg name="hpmcounter12" bitsize="64"/>
+ <reg name="hpmcounter13" bitsize="64"/>
+ <reg name="hpmcounter14" bitsize="64"/>
+ <reg name="hpmcounter15" bitsize="64"/>
+ <reg name="hpmcounter16" bitsize="64"/>
+ <reg name="hpmcounter17" bitsize="64"/>
+ <reg name="hpmcounter18" bitsize="64"/>
+ <reg name="hpmcounter19" bitsize="64"/>
+ <reg name="hpmcounter20" bitsize="64"/>
+ <reg name="hpmcounter21" bitsize="64"/>
+ <reg name="hpmcounter22" bitsize="64"/>
+ <reg name="hpmcounter23" bitsize="64"/>
+ <reg name="hpmcounter24" bitsize="64"/>
+ <reg name="hpmcounter25" bitsize="64"/>
+ <reg name="hpmcounter26" bitsize="64"/>
+ <reg name="hpmcounter27" bitsize="64"/>
+ <reg name="hpmcounter28" bitsize="64"/>
+ <reg name="hpmcounter29" bitsize="64"/>
+ <reg name="hpmcounter30" bitsize="64"/>
+ <reg name="hpmcounter31" bitsize="64"/>
+ <reg name="cycleh" bitsize="64"/>
+ <reg name="timeh" bitsize="64"/>
+ <reg name="instreth" bitsize="64"/>
+ <reg name="hpmcounter3h" bitsize="64"/>
+ <reg name="hpmcounter4h" bitsize="64"/>
+ <reg name="hpmcounter5h" bitsize="64"/>
+ <reg name="hpmcounter6h" bitsize="64"/>
+ <reg name="hpmcounter7h" bitsize="64"/>
+ <reg name="hpmcounter8h" bitsize="64"/>
+ <reg name="hpmcounter9h" bitsize="64"/>
+ <reg name="hpmcounter10h" bitsize="64"/>
+ <reg name="hpmcounter11h" bitsize="64"/>
+ <reg name="hpmcounter12h" bitsize="64"/>
+ <reg name="hpmcounter13h" bitsize="64"/>
+ <reg name="hpmcounter14h" bitsize="64"/>
+ <reg name="hpmcounter15h" bitsize="64"/>
+ <reg name="hpmcounter16h" bitsize="64"/>
+ <reg name="hpmcounter17h" bitsize="64"/>
+ <reg name="hpmcounter18h" bitsize="64"/>
+ <reg name="hpmcounter19h" bitsize="64"/>
+ <reg name="hpmcounter20h" bitsize="64"/>
+ <reg name="hpmcounter21h" bitsize="64"/>
+ <reg name="hpmcounter22h" bitsize="64"/>
+ <reg name="hpmcounter23h" bitsize="64"/>
+ <reg name="hpmcounter24h" bitsize="64"/>
+ <reg name="hpmcounter25h" bitsize="64"/>
+ <reg name="hpmcounter26h" bitsize="64"/>
+ <reg name="hpmcounter27h" bitsize="64"/>
+ <reg name="hpmcounter28h" bitsize="64"/>
+ <reg name="hpmcounter29h" bitsize="64"/>
+ <reg name="hpmcounter30h" bitsize="64"/>
+ <reg name="hpmcounter31h" bitsize="64"/>
+ <reg name="sstatus" bitsize="64"/>
+ <reg name="sedeleg" bitsize="64"/>
+ <reg name="sideleg" bitsize="64"/>
+ <reg name="sie" bitsize="64"/>
+ <reg name="stvec" bitsize="64"/>
+ <reg name="scounteren" bitsize="64"/>
+ <reg name="sscratch" bitsize="64"/>
+ <reg name="sepc" bitsize="64"/>
+ <reg name="scause" bitsize="64"/>
+ <reg name="stval" bitsize="64"/>
+ <reg name="sip" bitsize="64"/>
+ <reg name="satp" bitsize="64"/>
+ <reg name="mvendorid" bitsize="64"/>
+ <reg name="marchid" bitsize="64"/>
+ <reg name="mimpid" bitsize="64"/>
+ <reg name="mhartid" bitsize="64"/>
+ <reg name="mstatus" bitsize="64"/>
+ <reg name="misa" bitsize="64"/>
+ <reg name="medeleg" bitsize="64"/>
+ <reg name="mideleg" bitsize="64"/>
+ <reg name="mie" bitsize="64"/>
+ <reg name="mtvec" bitsize="64"/>
+ <reg name="mcounteren" bitsize="64"/>
+ <reg name="mscratch" bitsize="64"/>
+ <reg name="mepc" bitsize="64"/>
+ <reg name="mcause" bitsize="64"/>
+ <reg name="mtval" bitsize="64"/>
+ <reg name="mip" bitsize="64"/>
+ <reg name="pmpcfg0" bitsize="64"/>
+ <reg name="pmpcfg1" bitsize="64"/>
+ <reg name="pmpcfg2" bitsize="64"/>
+ <reg name="pmpcfg3" bitsize="64"/>
+ <reg name="pmpaddr0" bitsize="64"/>
+ <reg name="pmpaddr1" bitsize="64"/>
+ <reg name="pmpaddr2" bitsize="64"/>
+ <reg name="pmpaddr3" bitsize="64"/>
+ <reg name="pmpaddr4" bitsize="64"/>
+ <reg name="pmpaddr5" bitsize="64"/>
+ <reg name="pmpaddr6" bitsize="64"/>
+ <reg name="pmpaddr7" bitsize="64"/>
+ <reg name="pmpaddr8" bitsize="64"/>
+ <reg name="pmpaddr9" bitsize="64"/>
+ <reg name="pmpaddr10" bitsize="64"/>
+ <reg name="pmpaddr11" bitsize="64"/>
+ <reg name="pmpaddr12" bitsize="64"/>
+ <reg name="pmpaddr13" bitsize="64"/>
+ <reg name="pmpaddr14" bitsize="64"/>
+ <reg name="pmpaddr15" bitsize="64"/>
+ <reg name="mcycle" bitsize="64"/>
+ <reg name="minstret" bitsize="64"/>
+ <reg name="mhpmcounter3" bitsize="64"/>
+ <reg name="mhpmcounter4" bitsize="64"/>
+ <reg name="mhpmcounter5" bitsize="64"/>
+ <reg name="mhpmcounter6" bitsize="64"/>
+ <reg name="mhpmcounter7" bitsize="64"/>
+ <reg name="mhpmcounter8" bitsize="64"/>
+ <reg name="mhpmcounter9" bitsize="64"/>
+ <reg name="mhpmcounter10" bitsize="64"/>
+ <reg name="mhpmcounter11" bitsize="64"/>
+ <reg name="mhpmcounter12" bitsize="64"/>
+ <reg name="mhpmcounter13" bitsize="64"/>
+ <reg name="mhpmcounter14" bitsize="64"/>
+ <reg name="mhpmcounter15" bitsize="64"/>
+ <reg name="mhpmcounter16" bitsize="64"/>
+ <reg name="mhpmcounter17" bitsize="64"/>
+ <reg name="mhpmcounter18" bitsize="64"/>
+ <reg name="mhpmcounter19" bitsize="64"/>
+ <reg name="mhpmcounter20" bitsize="64"/>
+ <reg name="mhpmcounter21" bitsize="64"/>
+ <reg name="mhpmcounter22" bitsize="64"/>
+ <reg name="mhpmcounter23" bitsize="64"/>
+ <reg name="mhpmcounter24" bitsize="64"/>
+ <reg name="mhpmcounter25" bitsize="64"/>
+ <reg name="mhpmcounter26" bitsize="64"/>
+ <reg name="mhpmcounter27" bitsize="64"/>
+ <reg name="mhpmcounter28" bitsize="64"/>
+ <reg name="mhpmcounter29" bitsize="64"/>
+ <reg name="mhpmcounter30" bitsize="64"/>
+ <reg name="mhpmcounter31" bitsize="64"/>
+ <reg name="mcycleh" bitsize="64"/>
+ <reg name="minstreth" bitsize="64"/>
+ <reg name="mhpmcounter3h" bitsize="64"/>
+ <reg name="mhpmcounter4h" bitsize="64"/>
+ <reg name="mhpmcounter5h" bitsize="64"/>
+ <reg name="mhpmcounter6h" bitsize="64"/>
+ <reg name="mhpmcounter7h" bitsize="64"/>
+ <reg name="mhpmcounter8h" bitsize="64"/>
+ <reg name="mhpmcounter9h" bitsize="64"/>
+ <reg name="mhpmcounter10h" bitsize="64"/>
+ <reg name="mhpmcounter11h" bitsize="64"/>
+ <reg name="mhpmcounter12h" bitsize="64"/>
+ <reg name="mhpmcounter13h" bitsize="64"/>
+ <reg name="mhpmcounter14h" bitsize="64"/>
+ <reg name="mhpmcounter15h" bitsize="64"/>
+ <reg name="mhpmcounter16h" bitsize="64"/>
+ <reg name="mhpmcounter17h" bitsize="64"/>
+ <reg name="mhpmcounter18h" bitsize="64"/>
+ <reg name="mhpmcounter19h" bitsize="64"/>
+ <reg name="mhpmcounter20h" bitsize="64"/>
+ <reg name="mhpmcounter21h" bitsize="64"/>
+ <reg name="mhpmcounter22h" bitsize="64"/>
+ <reg name="mhpmcounter23h" bitsize="64"/>
+ <reg name="mhpmcounter24h" bitsize="64"/>
+ <reg name="mhpmcounter25h" bitsize="64"/>
+ <reg name="mhpmcounter26h" bitsize="64"/>
+ <reg name="mhpmcounter27h" bitsize="64"/>
+ <reg name="mhpmcounter28h" bitsize="64"/>
+ <reg name="mhpmcounter29h" bitsize="64"/>
+ <reg name="mhpmcounter30h" bitsize="64"/>
+ <reg name="mhpmcounter31h" bitsize="64"/>
+ <reg name="mhpmevent3" bitsize="64"/>
+ <reg name="mhpmevent4" bitsize="64"/>
+ <reg name="mhpmevent5" bitsize="64"/>
+ <reg name="mhpmevent6" bitsize="64"/>
+ <reg name="mhpmevent7" bitsize="64"/>
+ <reg name="mhpmevent8" bitsize="64"/>
+ <reg name="mhpmevent9" bitsize="64"/>
+ <reg name="mhpmevent10" bitsize="64"/>
+ <reg name="mhpmevent11" bitsize="64"/>
+ <reg name="mhpmevent12" bitsize="64"/>
+ <reg name="mhpmevent13" bitsize="64"/>
+ <reg name="mhpmevent14" bitsize="64"/>
+ <reg name="mhpmevent15" bitsize="64"/>
+ <reg name="mhpmevent16" bitsize="64"/>
+ <reg name="mhpmevent17" bitsize="64"/>
+ <reg name="mhpmevent18" bitsize="64"/>
+ <reg name="mhpmevent19" bitsize="64"/>
+ <reg name="mhpmevent20" bitsize="64"/>
+ <reg name="mhpmevent21" bitsize="64"/>
+ <reg name="mhpmevent22" bitsize="64"/>
+ <reg name="mhpmevent23" bitsize="64"/>
+ <reg name="mhpmevent24" bitsize="64"/>
+ <reg name="mhpmevent25" bitsize="64"/>
+ <reg name="mhpmevent26" bitsize="64"/>
+ <reg name="mhpmevent27" bitsize="64"/>
+ <reg name="mhpmevent28" bitsize="64"/>
+ <reg name="mhpmevent29" bitsize="64"/>
+ <reg name="mhpmevent30" bitsize="64"/>
+ <reg name="mhpmevent31" bitsize="64"/>
+ <reg name="tselect" bitsize="64"/>
+ <reg name="tdata1" bitsize="64"/>
+ <reg name="tdata2" bitsize="64"/>
+ <reg name="tdata3" bitsize="64"/>
+ <reg name="dcsr" bitsize="64"/>
+ <reg name="dpc" bitsize="64"/>
+ <reg name="dscratch" bitsize="64"/>
+ <reg name="hstatus" bitsize="64"/>
+ <reg name="hedeleg" bitsize="64"/>
+ <reg name="hideleg" bitsize="64"/>
+ <reg name="hie" bitsize="64"/>
+ <reg name="htvec" bitsize="64"/>
+ <reg name="hscratch" bitsize="64"/>
+ <reg name="hepc" bitsize="64"/>
+ <reg name="hcause" bitsize="64"/>
+ <reg name="hbadaddr" bitsize="64"/>
+ <reg name="hip" bitsize="64"/>
+ <reg name="mbase" bitsize="64"/>
+ <reg name="mbound" bitsize="64"/>
+ <reg name="mibase" bitsize="64"/>
+ <reg name="mibound" bitsize="64"/>
+ <reg name="mdbase" bitsize="64"/>
+ <reg name="mdbound" bitsize="64"/>
+ <reg name="mucounteren" bitsize="64"/>
+ <reg name="mscounteren" bitsize="64"/>
+ <reg name="mhcounteren" bitsize="64"/>
+</feature>
diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml
new file mode 100644
index 0000000..fb24b72
--- /dev/null
+++ b/gdb-xml/riscv-64bit-fpu.xml
@@ -0,0 +1,52 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.fpu">
+
+ <union id="riscv_double">
+ <field name="float" type="ieee_single"/>
+ <field name="double" type="ieee_double"/>
+ </union>
+
+ <reg name="ft0" bitsize="64" type="riscv_double"/>
+ <reg name="ft1" bitsize="64" type="riscv_double"/>
+ <reg name="ft2" bitsize="64" type="riscv_double"/>
+ <reg name="ft3" bitsize="64" type="riscv_double"/>
+ <reg name="ft4" bitsize="64" type="riscv_double"/>
+ <reg name="ft5" bitsize="64" type="riscv_double"/>
+ <reg name="ft6" bitsize="64" type="riscv_double"/>
+ <reg name="ft7" bitsize="64" type="riscv_double"/>
+ <reg name="fs0" bitsize="64" type="riscv_double"/>
+ <reg name="fs1" bitsize="64" type="riscv_double"/>
+ <reg name="fa0" bitsize="64" type="riscv_double"/>
+ <reg name="fa1" bitsize="64" type="riscv_double"/>
+ <reg name="fa2" bitsize="64" type="riscv_double"/>
+ <reg name="fa3" bitsize="64" type="riscv_double"/>
+ <reg name="fa4" bitsize="64" type="riscv_double"/>
+ <reg name="fa5" bitsize="64" type="riscv_double"/>
+ <reg name="fa6" bitsize="64" type="riscv_double"/>
+ <reg name="fa7" bitsize="64" type="riscv_double"/>
+ <reg name="fs2" bitsize="64" type="riscv_double"/>
+ <reg name="fs3" bitsize="64" type="riscv_double"/>
+ <reg name="fs4" bitsize="64" type="riscv_double"/>
+ <reg name="fs5" bitsize="64" type="riscv_double"/>
+ <reg name="fs6" bitsize="64" type="riscv_double"/>
+ <reg name="fs7" bitsize="64" type="riscv_double"/>
+ <reg name="fs8" bitsize="64" type="riscv_double"/>
+ <reg name="fs9" bitsize="64" type="riscv_double"/>
+ <reg name="fs10" bitsize="64" type="riscv_double"/>
+ <reg name="fs11" bitsize="64" type="riscv_double"/>
+ <reg name="ft8" bitsize="64" type="riscv_double"/>
+ <reg name="ft9" bitsize="64" type="riscv_double"/>
+ <reg name="ft10" bitsize="64" type="riscv_double"/>
+ <reg name="ft11" bitsize="64" type="riscv_double"/>
+
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+</feature>
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-riscv] [PATCH 2/5 v2] RISC-V: Add 64-bit gdb xml files.
@ 2018-12-28 22:08 ` Jim Wilson
0 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-28 22:08 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
Signed-off-by: Jim Wilson <jimw@sifive.com>
---
configure | 1 +
gdb-xml/riscv-64bit-cpu.xml | 43 ++++++++
gdb-xml/riscv-64bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++
gdb-xml/riscv-64bit-fpu.xml | 52 +++++++++
4 files changed, 346 insertions(+)
create mode 100644 gdb-xml/riscv-64bit-cpu.xml
create mode 100644 gdb-xml/riscv-64bit-csr.xml
create mode 100644 gdb-xml/riscv-64bit-fpu.xml
diff --git a/configure b/configure
index 4e05eed..00b7495 100755
--- a/configure
+++ b/configure
@@ -7215,6 +7215,7 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
+ gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
target_compiler=$cross_cc_riscv64
;;
sh4|sh4eb)
diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml
new file mode 100644
index 0000000..f37d7f3
--- /dev/null
+++ b/gdb-xml/riscv-64bit-cpu.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="64" type="int"/>
+ <reg name="ra" bitsize="64" type="code_ptr"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+ <reg name="gp" bitsize="64" type="data_ptr"/>
+ <reg name="tp" bitsize="64" type="data_ptr"/>
+ <reg name="t0" bitsize="64" type="int"/>
+ <reg name="t1" bitsize="64" type="int"/>
+ <reg name="t2" bitsize="64" type="int"/>
+ <reg name="fp" bitsize="64" type="data_ptr"/>
+ <reg name="s1" bitsize="64" type="int"/>
+ <reg name="a0" bitsize="64" type="int"/>
+ <reg name="a1" bitsize="64" type="int"/>
+ <reg name="a2" bitsize="64" type="int"/>
+ <reg name="a3" bitsize="64" type="int"/>
+ <reg name="a4" bitsize="64" type="int"/>
+ <reg name="a5" bitsize="64" type="int"/>
+ <reg name="a6" bitsize="64" type="int"/>
+ <reg name="a7" bitsize="64" type="int"/>
+ <reg name="s2" bitsize="64" type="int"/>
+ <reg name="s3" bitsize="64" type="int"/>
+ <reg name="s4" bitsize="64" type="int"/>
+ <reg name="s5" bitsize="64" type="int"/>
+ <reg name="s6" bitsize="64" type="int"/>
+ <reg name="s7" bitsize="64" type="int"/>
+ <reg name="s8" bitsize="64" type="int"/>
+ <reg name="s9" bitsize="64" type="int"/>
+ <reg name="s10" bitsize="64" type="int"/>
+ <reg name="s11" bitsize="64" type="int"/>
+ <reg name="t3" bitsize="64" type="int"/>
+ <reg name="t4" bitsize="64" type="int"/>
+ <reg name="t5" bitsize="64" type="int"/>
+ <reg name="t6" bitsize="64" type="int"/>
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+</feature>
diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml
new file mode 100644
index 0000000..a3de834
--- /dev/null
+++ b/gdb-xml/riscv-64bit-csr.xml
@@ -0,0 +1,250 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.csr">
+ <reg name="ustatus" bitsize="64"/>
+ <reg name="uie" bitsize="64"/>
+ <reg name="utvec" bitsize="64"/>
+ <reg name="uscratch" bitsize="64"/>
+ <reg name="uepc" bitsize="64"/>
+ <reg name="ucause" bitsize="64"/>
+ <reg name="utval" bitsize="64"/>
+ <reg name="uip" bitsize="64"/>
+ <reg name="fflags" bitsize="64"/>
+ <reg name="frm" bitsize="64"/>
+ <reg name="fcsr" bitsize="64"/>
+ <reg name="cycle" bitsize="64"/>
+ <reg name="time" bitsize="64"/>
+ <reg name="instret" bitsize="64"/>
+ <reg name="hpmcounter3" bitsize="64"/>
+ <reg name="hpmcounter4" bitsize="64"/>
+ <reg name="hpmcounter5" bitsize="64"/>
+ <reg name="hpmcounter6" bitsize="64"/>
+ <reg name="hpmcounter7" bitsize="64"/>
+ <reg name="hpmcounter8" bitsize="64"/>
+ <reg name="hpmcounter9" bitsize="64"/>
+ <reg name="hpmcounter10" bitsize="64"/>
+ <reg name="hpmcounter11" bitsize="64"/>
+ <reg name="hpmcounter12" bitsize="64"/>
+ <reg name="hpmcounter13" bitsize="64"/>
+ <reg name="hpmcounter14" bitsize="64"/>
+ <reg name="hpmcounter15" bitsize="64"/>
+ <reg name="hpmcounter16" bitsize="64"/>
+ <reg name="hpmcounter17" bitsize="64"/>
+ <reg name="hpmcounter18" bitsize="64"/>
+ <reg name="hpmcounter19" bitsize="64"/>
+ <reg name="hpmcounter20" bitsize="64"/>
+ <reg name="hpmcounter21" bitsize="64"/>
+ <reg name="hpmcounter22" bitsize="64"/>
+ <reg name="hpmcounter23" bitsize="64"/>
+ <reg name="hpmcounter24" bitsize="64"/>
+ <reg name="hpmcounter25" bitsize="64"/>
+ <reg name="hpmcounter26" bitsize="64"/>
+ <reg name="hpmcounter27" bitsize="64"/>
+ <reg name="hpmcounter28" bitsize="64"/>
+ <reg name="hpmcounter29" bitsize="64"/>
+ <reg name="hpmcounter30" bitsize="64"/>
+ <reg name="hpmcounter31" bitsize="64"/>
+ <reg name="cycleh" bitsize="64"/>
+ <reg name="timeh" bitsize="64"/>
+ <reg name="instreth" bitsize="64"/>
+ <reg name="hpmcounter3h" bitsize="64"/>
+ <reg name="hpmcounter4h" bitsize="64"/>
+ <reg name="hpmcounter5h" bitsize="64"/>
+ <reg name="hpmcounter6h" bitsize="64"/>
+ <reg name="hpmcounter7h" bitsize="64"/>
+ <reg name="hpmcounter8h" bitsize="64"/>
+ <reg name="hpmcounter9h" bitsize="64"/>
+ <reg name="hpmcounter10h" bitsize="64"/>
+ <reg name="hpmcounter11h" bitsize="64"/>
+ <reg name="hpmcounter12h" bitsize="64"/>
+ <reg name="hpmcounter13h" bitsize="64"/>
+ <reg name="hpmcounter14h" bitsize="64"/>
+ <reg name="hpmcounter15h" bitsize="64"/>
+ <reg name="hpmcounter16h" bitsize="64"/>
+ <reg name="hpmcounter17h" bitsize="64"/>
+ <reg name="hpmcounter18h" bitsize="64"/>
+ <reg name="hpmcounter19h" bitsize="64"/>
+ <reg name="hpmcounter20h" bitsize="64"/>
+ <reg name="hpmcounter21h" bitsize="64"/>
+ <reg name="hpmcounter22h" bitsize="64"/>
+ <reg name="hpmcounter23h" bitsize="64"/>
+ <reg name="hpmcounter24h" bitsize="64"/>
+ <reg name="hpmcounter25h" bitsize="64"/>
+ <reg name="hpmcounter26h" bitsize="64"/>
+ <reg name="hpmcounter27h" bitsize="64"/>
+ <reg name="hpmcounter28h" bitsize="64"/>
+ <reg name="hpmcounter29h" bitsize="64"/>
+ <reg name="hpmcounter30h" bitsize="64"/>
+ <reg name="hpmcounter31h" bitsize="64"/>
+ <reg name="sstatus" bitsize="64"/>
+ <reg name="sedeleg" bitsize="64"/>
+ <reg name="sideleg" bitsize="64"/>
+ <reg name="sie" bitsize="64"/>
+ <reg name="stvec" bitsize="64"/>
+ <reg name="scounteren" bitsize="64"/>
+ <reg name="sscratch" bitsize="64"/>
+ <reg name="sepc" bitsize="64"/>
+ <reg name="scause" bitsize="64"/>
+ <reg name="stval" bitsize="64"/>
+ <reg name="sip" bitsize="64"/>
+ <reg name="satp" bitsize="64"/>
+ <reg name="mvendorid" bitsize="64"/>
+ <reg name="marchid" bitsize="64"/>
+ <reg name="mimpid" bitsize="64"/>
+ <reg name="mhartid" bitsize="64"/>
+ <reg name="mstatus" bitsize="64"/>
+ <reg name="misa" bitsize="64"/>
+ <reg name="medeleg" bitsize="64"/>
+ <reg name="mideleg" bitsize="64"/>
+ <reg name="mie" bitsize="64"/>
+ <reg name="mtvec" bitsize="64"/>
+ <reg name="mcounteren" bitsize="64"/>
+ <reg name="mscratch" bitsize="64"/>
+ <reg name="mepc" bitsize="64"/>
+ <reg name="mcause" bitsize="64"/>
+ <reg name="mtval" bitsize="64"/>
+ <reg name="mip" bitsize="64"/>
+ <reg name="pmpcfg0" bitsize="64"/>
+ <reg name="pmpcfg1" bitsize="64"/>
+ <reg name="pmpcfg2" bitsize="64"/>
+ <reg name="pmpcfg3" bitsize="64"/>
+ <reg name="pmpaddr0" bitsize="64"/>
+ <reg name="pmpaddr1" bitsize="64"/>
+ <reg name="pmpaddr2" bitsize="64"/>
+ <reg name="pmpaddr3" bitsize="64"/>
+ <reg name="pmpaddr4" bitsize="64"/>
+ <reg name="pmpaddr5" bitsize="64"/>
+ <reg name="pmpaddr6" bitsize="64"/>
+ <reg name="pmpaddr7" bitsize="64"/>
+ <reg name="pmpaddr8" bitsize="64"/>
+ <reg name="pmpaddr9" bitsize="64"/>
+ <reg name="pmpaddr10" bitsize="64"/>
+ <reg name="pmpaddr11" bitsize="64"/>
+ <reg name="pmpaddr12" bitsize="64"/>
+ <reg name="pmpaddr13" bitsize="64"/>
+ <reg name="pmpaddr14" bitsize="64"/>
+ <reg name="pmpaddr15" bitsize="64"/>
+ <reg name="mcycle" bitsize="64"/>
+ <reg name="minstret" bitsize="64"/>
+ <reg name="mhpmcounter3" bitsize="64"/>
+ <reg name="mhpmcounter4" bitsize="64"/>
+ <reg name="mhpmcounter5" bitsize="64"/>
+ <reg name="mhpmcounter6" bitsize="64"/>
+ <reg name="mhpmcounter7" bitsize="64"/>
+ <reg name="mhpmcounter8" bitsize="64"/>
+ <reg name="mhpmcounter9" bitsize="64"/>
+ <reg name="mhpmcounter10" bitsize="64"/>
+ <reg name="mhpmcounter11" bitsize="64"/>
+ <reg name="mhpmcounter12" bitsize="64"/>
+ <reg name="mhpmcounter13" bitsize="64"/>
+ <reg name="mhpmcounter14" bitsize="64"/>
+ <reg name="mhpmcounter15" bitsize="64"/>
+ <reg name="mhpmcounter16" bitsize="64"/>
+ <reg name="mhpmcounter17" bitsize="64"/>
+ <reg name="mhpmcounter18" bitsize="64"/>
+ <reg name="mhpmcounter19" bitsize="64"/>
+ <reg name="mhpmcounter20" bitsize="64"/>
+ <reg name="mhpmcounter21" bitsize="64"/>
+ <reg name="mhpmcounter22" bitsize="64"/>
+ <reg name="mhpmcounter23" bitsize="64"/>
+ <reg name="mhpmcounter24" bitsize="64"/>
+ <reg name="mhpmcounter25" bitsize="64"/>
+ <reg name="mhpmcounter26" bitsize="64"/>
+ <reg name="mhpmcounter27" bitsize="64"/>
+ <reg name="mhpmcounter28" bitsize="64"/>
+ <reg name="mhpmcounter29" bitsize="64"/>
+ <reg name="mhpmcounter30" bitsize="64"/>
+ <reg name="mhpmcounter31" bitsize="64"/>
+ <reg name="mcycleh" bitsize="64"/>
+ <reg name="minstreth" bitsize="64"/>
+ <reg name="mhpmcounter3h" bitsize="64"/>
+ <reg name="mhpmcounter4h" bitsize="64"/>
+ <reg name="mhpmcounter5h" bitsize="64"/>
+ <reg name="mhpmcounter6h" bitsize="64"/>
+ <reg name="mhpmcounter7h" bitsize="64"/>
+ <reg name="mhpmcounter8h" bitsize="64"/>
+ <reg name="mhpmcounter9h" bitsize="64"/>
+ <reg name="mhpmcounter10h" bitsize="64"/>
+ <reg name="mhpmcounter11h" bitsize="64"/>
+ <reg name="mhpmcounter12h" bitsize="64"/>
+ <reg name="mhpmcounter13h" bitsize="64"/>
+ <reg name="mhpmcounter14h" bitsize="64"/>
+ <reg name="mhpmcounter15h" bitsize="64"/>
+ <reg name="mhpmcounter16h" bitsize="64"/>
+ <reg name="mhpmcounter17h" bitsize="64"/>
+ <reg name="mhpmcounter18h" bitsize="64"/>
+ <reg name="mhpmcounter19h" bitsize="64"/>
+ <reg name="mhpmcounter20h" bitsize="64"/>
+ <reg name="mhpmcounter21h" bitsize="64"/>
+ <reg name="mhpmcounter22h" bitsize="64"/>
+ <reg name="mhpmcounter23h" bitsize="64"/>
+ <reg name="mhpmcounter24h" bitsize="64"/>
+ <reg name="mhpmcounter25h" bitsize="64"/>
+ <reg name="mhpmcounter26h" bitsize="64"/>
+ <reg name="mhpmcounter27h" bitsize="64"/>
+ <reg name="mhpmcounter28h" bitsize="64"/>
+ <reg name="mhpmcounter29h" bitsize="64"/>
+ <reg name="mhpmcounter30h" bitsize="64"/>
+ <reg name="mhpmcounter31h" bitsize="64"/>
+ <reg name="mhpmevent3" bitsize="64"/>
+ <reg name="mhpmevent4" bitsize="64"/>
+ <reg name="mhpmevent5" bitsize="64"/>
+ <reg name="mhpmevent6" bitsize="64"/>
+ <reg name="mhpmevent7" bitsize="64"/>
+ <reg name="mhpmevent8" bitsize="64"/>
+ <reg name="mhpmevent9" bitsize="64"/>
+ <reg name="mhpmevent10" bitsize="64"/>
+ <reg name="mhpmevent11" bitsize="64"/>
+ <reg name="mhpmevent12" bitsize="64"/>
+ <reg name="mhpmevent13" bitsize="64"/>
+ <reg name="mhpmevent14" bitsize="64"/>
+ <reg name="mhpmevent15" bitsize="64"/>
+ <reg name="mhpmevent16" bitsize="64"/>
+ <reg name="mhpmevent17" bitsize="64"/>
+ <reg name="mhpmevent18" bitsize="64"/>
+ <reg name="mhpmevent19" bitsize="64"/>
+ <reg name="mhpmevent20" bitsize="64"/>
+ <reg name="mhpmevent21" bitsize="64"/>
+ <reg name="mhpmevent22" bitsize="64"/>
+ <reg name="mhpmevent23" bitsize="64"/>
+ <reg name="mhpmevent24" bitsize="64"/>
+ <reg name="mhpmevent25" bitsize="64"/>
+ <reg name="mhpmevent26" bitsize="64"/>
+ <reg name="mhpmevent27" bitsize="64"/>
+ <reg name="mhpmevent28" bitsize="64"/>
+ <reg name="mhpmevent29" bitsize="64"/>
+ <reg name="mhpmevent30" bitsize="64"/>
+ <reg name="mhpmevent31" bitsize="64"/>
+ <reg name="tselect" bitsize="64"/>
+ <reg name="tdata1" bitsize="64"/>
+ <reg name="tdata2" bitsize="64"/>
+ <reg name="tdata3" bitsize="64"/>
+ <reg name="dcsr" bitsize="64"/>
+ <reg name="dpc" bitsize="64"/>
+ <reg name="dscratch" bitsize="64"/>
+ <reg name="hstatus" bitsize="64"/>
+ <reg name="hedeleg" bitsize="64"/>
+ <reg name="hideleg" bitsize="64"/>
+ <reg name="hie" bitsize="64"/>
+ <reg name="htvec" bitsize="64"/>
+ <reg name="hscratch" bitsize="64"/>
+ <reg name="hepc" bitsize="64"/>
+ <reg name="hcause" bitsize="64"/>
+ <reg name="hbadaddr" bitsize="64"/>
+ <reg name="hip" bitsize="64"/>
+ <reg name="mbase" bitsize="64"/>
+ <reg name="mbound" bitsize="64"/>
+ <reg name="mibase" bitsize="64"/>
+ <reg name="mibound" bitsize="64"/>
+ <reg name="mdbase" bitsize="64"/>
+ <reg name="mdbound" bitsize="64"/>
+ <reg name="mucounteren" bitsize="64"/>
+ <reg name="mscounteren" bitsize="64"/>
+ <reg name="mhcounteren" bitsize="64"/>
+</feature>
diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml
new file mode 100644
index 0000000..fb24b72
--- /dev/null
+++ b/gdb-xml/riscv-64bit-fpu.xml
@@ -0,0 +1,52 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.fpu">
+
+ <union id="riscv_double">
+ <field name="float" type="ieee_single"/>
+ <field name="double" type="ieee_double"/>
+ </union>
+
+ <reg name="ft0" bitsize="64" type="riscv_double"/>
+ <reg name="ft1" bitsize="64" type="riscv_double"/>
+ <reg name="ft2" bitsize="64" type="riscv_double"/>
+ <reg name="ft3" bitsize="64" type="riscv_double"/>
+ <reg name="ft4" bitsize="64" type="riscv_double"/>
+ <reg name="ft5" bitsize="64" type="riscv_double"/>
+ <reg name="ft6" bitsize="64" type="riscv_double"/>
+ <reg name="ft7" bitsize="64" type="riscv_double"/>
+ <reg name="fs0" bitsize="64" type="riscv_double"/>
+ <reg name="fs1" bitsize="64" type="riscv_double"/>
+ <reg name="fa0" bitsize="64" type="riscv_double"/>
+ <reg name="fa1" bitsize="64" type="riscv_double"/>
+ <reg name="fa2" bitsize="64" type="riscv_double"/>
+ <reg name="fa3" bitsize="64" type="riscv_double"/>
+ <reg name="fa4" bitsize="64" type="riscv_double"/>
+ <reg name="fa5" bitsize="64" type="riscv_double"/>
+ <reg name="fa6" bitsize="64" type="riscv_double"/>
+ <reg name="fa7" bitsize="64" type="riscv_double"/>
+ <reg name="fs2" bitsize="64" type="riscv_double"/>
+ <reg name="fs3" bitsize="64" type="riscv_double"/>
+ <reg name="fs4" bitsize="64" type="riscv_double"/>
+ <reg name="fs5" bitsize="64" type="riscv_double"/>
+ <reg name="fs6" bitsize="64" type="riscv_double"/>
+ <reg name="fs7" bitsize="64" type="riscv_double"/>
+ <reg name="fs8" bitsize="64" type="riscv_double"/>
+ <reg name="fs9" bitsize="64" type="riscv_double"/>
+ <reg name="fs10" bitsize="64" type="riscv_double"/>
+ <reg name="fs11" bitsize="64" type="riscv_double"/>
+ <reg name="ft8" bitsize="64" type="riscv_double"/>
+ <reg name="ft9" bitsize="64" type="riscv_double"/>
+ <reg name="ft10" bitsize="64" type="riscv_double"/>
+ <reg name="ft11" bitsize="64" type="riscv_double"/>
+
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+</feature>
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.
2018-12-28 22:05 ` [Qemu-riscv] " Jim Wilson
@ 2018-12-28 22:09 ` Jim Wilson
-1 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-28 22:09 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers. This also adds
some missing CSR_* register macros.
Signed-off-by: Jim Wilson <jimw@sifive.com>
---
target/riscv/cpu_bits.h | 35 ++++++-
target/riscv/csr-map.h | 248 ++++++++++++++++++++++++++++++++++++++++++++++++
target/riscv/gdbstub.c | 1 +
3 files changed, 282 insertions(+), 2 deletions(-)
create mode 100644 target/riscv/csr-map.h
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5439f47..316d500 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -135,16 +135,22 @@
/* Legacy Counter Setup (priv v1.9.1) */
#define CSR_MUCOUNTEREN 0x320
#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHCOUNTEREN 0x322
/* Machine Trap Handling */
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
-#define CSR_MBADADDR 0x343
+#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
+/* Legacy Machine Trap Handling (priv v1.9.1) */
+#define CSR_MBADADDR 0x343
+
/* Supervisor Trap Setup */
#define CSR_SSTATUS 0x100
+#define CSR_SEDELEG 0x102
+#define CSR_SIDELEG 0x103
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106
@@ -153,9 +159,12 @@
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142
-#define CSR_SBADADDR 0x143
+#define CSR_STVAL 0x143
#define CSR_SIP 0x144
+/* Legacy Supervisor Trap Handling (priv v1.9.1) */
+#define CSR_SBADADDR 0x143
+
/* Supervisor Protection and Translation */
#define CSR_SPTBR 0x180
#define CSR_SATP 0x180
@@ -282,6 +291,28 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
+/* Legacy Hypervisor Trap Setup (priv v1.9.1) */
+#define CSR_HSTATUS 0x200
+#define CSR_HEDELEG 0x202
+#define CSR_HIDELEG 0x203
+#define CSR_HIE 0x204
+#define CSR_HTVEC 0x205
+
+/* Legacy Hypervisor Trap Handling (priv v1.9.1) */
+#define CSR_HSCRATCH 0x240
+#define CSR_HEPC 0x241
+#define CSR_HCAUSE 0x242
+#define CSR_HBADADDR 0x243
+#define CSR_HIP 0x244
+
+/* Legacy Machine Protection and Translation (priv v1.9.1) */
+#define CSR_MBASE 0x380
+#define CSR_MBOUND 0x381
+#define CSR_MIBASE 0x382
+#define CSR_MIBOUND 0x383
+#define CSR_MDBASE 0x384
+#define CSR_MDBOUND 0x385
+
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
diff --git a/target/riscv/csr-map.h b/target/riscv/csr-map.h
new file mode 100644
index 0000000..cce32fd
--- /dev/null
+++ b/target/riscv/csr-map.h
@@ -0,0 +1,248 @@
+/*
+ * The GDB CSR xml files list them in documentation order, not numerical order,
+ * and are missing entries for unnamed CSRs. So we need to map the gdb numbers
+ * to the hardware numbers.
+ */
+
+int csr_register_map[] = {
+ CSR_USTATUS,
+ CSR_UIE,
+ CSR_UTVEC,
+ CSR_USCRATCH,
+ CSR_UEPC,
+ CSR_UCAUSE,
+ CSR_UTVAL,
+ CSR_UIP,
+ CSR_FFLAGS,
+ CSR_FRM,
+ CSR_FCSR,
+ CSR_CYCLE,
+ CSR_TIME,
+ CSR_INSTRET,
+ CSR_HPMCOUNTER3,
+ CSR_HPMCOUNTER4,
+ CSR_HPMCOUNTER5,
+ CSR_HPMCOUNTER6,
+ CSR_HPMCOUNTER7,
+ CSR_HPMCOUNTER8,
+ CSR_HPMCOUNTER9,
+ CSR_HPMCOUNTER10,
+ CSR_HPMCOUNTER11,
+ CSR_HPMCOUNTER12,
+ CSR_HPMCOUNTER13,
+ CSR_HPMCOUNTER14,
+ CSR_HPMCOUNTER15,
+ CSR_HPMCOUNTER16,
+ CSR_HPMCOUNTER17,
+ CSR_HPMCOUNTER18,
+ CSR_HPMCOUNTER19,
+ CSR_HPMCOUNTER20,
+ CSR_HPMCOUNTER21,
+ CSR_HPMCOUNTER22,
+ CSR_HPMCOUNTER23,
+ CSR_HPMCOUNTER24,
+ CSR_HPMCOUNTER25,
+ CSR_HPMCOUNTER26,
+ CSR_HPMCOUNTER27,
+ CSR_HPMCOUNTER28,
+ CSR_HPMCOUNTER29,
+ CSR_HPMCOUNTER30,
+ CSR_HPMCOUNTER31,
+ CSR_CYCLEH,
+ CSR_TIMEH,
+ CSR_INSTRETH,
+ CSR_HPMCOUNTER3H,
+ CSR_HPMCOUNTER4H,
+ CSR_HPMCOUNTER5H,
+ CSR_HPMCOUNTER6H,
+ CSR_HPMCOUNTER7H,
+ CSR_HPMCOUNTER8H,
+ CSR_HPMCOUNTER9H,
+ CSR_HPMCOUNTER10H,
+ CSR_HPMCOUNTER11H,
+ CSR_HPMCOUNTER12H,
+ CSR_HPMCOUNTER13H,
+ CSR_HPMCOUNTER14H,
+ CSR_HPMCOUNTER15H,
+ CSR_HPMCOUNTER16H,
+ CSR_HPMCOUNTER17H,
+ CSR_HPMCOUNTER18H,
+ CSR_HPMCOUNTER19H,
+ CSR_HPMCOUNTER20H,
+ CSR_HPMCOUNTER21H,
+ CSR_HPMCOUNTER22H,
+ CSR_HPMCOUNTER23H,
+ CSR_HPMCOUNTER24H,
+ CSR_HPMCOUNTER25H,
+ CSR_HPMCOUNTER26H,
+ CSR_HPMCOUNTER27H,
+ CSR_HPMCOUNTER28H,
+ CSR_HPMCOUNTER29H,
+ CSR_HPMCOUNTER30H,
+ CSR_HPMCOUNTER31H,
+ CSR_SSTATUS,
+ CSR_SEDELEG,
+ CSR_SIDELEG,
+ CSR_SIE,
+ CSR_STVEC,
+ CSR_SCOUNTEREN,
+ CSR_SSCRATCH,
+ CSR_SEPC,
+ CSR_SCAUSE,
+ CSR_STVAL,
+ CSR_SIP,
+ CSR_SATP,
+ CSR_MVENDORID,
+ CSR_MARCHID,
+ CSR_MIMPID,
+ CSR_MHARTID,
+ CSR_MSTATUS,
+ CSR_MISA,
+ CSR_MEDELEG,
+ CSR_MIDELEG,
+ CSR_MIE,
+ CSR_MTVEC,
+ CSR_MCOUNTEREN,
+ CSR_MSCRATCH,
+ CSR_MEPC,
+ CSR_MCAUSE,
+ CSR_MTVAL,
+ CSR_MIP,
+ CSR_PMPCFG0,
+ CSR_PMPCFG1,
+ CSR_PMPCFG2,
+ CSR_PMPCFG3,
+ CSR_PMPADDR0,
+ CSR_PMPADDR1,
+ CSR_PMPADDR2,
+ CSR_PMPADDR3,
+ CSR_PMPADDR4,
+ CSR_PMPADDR5,
+ CSR_PMPADDR6,
+ CSR_PMPADDR7,
+ CSR_PMPADDR8,
+ CSR_PMPADDR9,
+ CSR_PMPADDR10,
+ CSR_PMPADDR11,
+ CSR_PMPADDR12,
+ CSR_PMPADDR13,
+ CSR_PMPADDR14,
+ CSR_PMPADDR15,
+ CSR_MCYCLE,
+ CSR_MINSTRET,
+ CSR_MHPMCOUNTER3,
+ CSR_MHPMCOUNTER4,
+ CSR_MHPMCOUNTER5,
+ CSR_MHPMCOUNTER6,
+ CSR_MHPMCOUNTER7,
+ CSR_MHPMCOUNTER8,
+ CSR_MHPMCOUNTER9,
+ CSR_MHPMCOUNTER10,
+ CSR_MHPMCOUNTER11,
+ CSR_MHPMCOUNTER12,
+ CSR_MHPMCOUNTER13,
+ CSR_MHPMCOUNTER14,
+ CSR_MHPMCOUNTER15,
+ CSR_MHPMCOUNTER16,
+ CSR_MHPMCOUNTER17,
+ CSR_MHPMCOUNTER18,
+ CSR_MHPMCOUNTER19,
+ CSR_MHPMCOUNTER20,
+ CSR_MHPMCOUNTER21,
+ CSR_MHPMCOUNTER22,
+ CSR_MHPMCOUNTER23,
+ CSR_MHPMCOUNTER24,
+ CSR_MHPMCOUNTER25,
+ CSR_MHPMCOUNTER26,
+ CSR_MHPMCOUNTER27,
+ CSR_MHPMCOUNTER28,
+ CSR_MHPMCOUNTER29,
+ CSR_MHPMCOUNTER30,
+ CSR_MHPMCOUNTER31,
+ CSR_MCYCLEH,
+ CSR_MINSTRETH,
+ CSR_MHPMCOUNTER3H,
+ CSR_MHPMCOUNTER4H,
+ CSR_MHPMCOUNTER5H,
+ CSR_MHPMCOUNTER6H,
+ CSR_MHPMCOUNTER7H,
+ CSR_MHPMCOUNTER8H,
+ CSR_MHPMCOUNTER9H,
+ CSR_MHPMCOUNTER10H,
+ CSR_MHPMCOUNTER11H,
+ CSR_MHPMCOUNTER12H,
+ CSR_MHPMCOUNTER13H,
+ CSR_MHPMCOUNTER14H,
+ CSR_MHPMCOUNTER15H,
+ CSR_MHPMCOUNTER16H,
+ CSR_MHPMCOUNTER17H,
+ CSR_MHPMCOUNTER18H,
+ CSR_MHPMCOUNTER19H,
+ CSR_MHPMCOUNTER20H,
+ CSR_MHPMCOUNTER21H,
+ CSR_MHPMCOUNTER22H,
+ CSR_MHPMCOUNTER23H,
+ CSR_MHPMCOUNTER24H,
+ CSR_MHPMCOUNTER25H,
+ CSR_MHPMCOUNTER26H,
+ CSR_MHPMCOUNTER27H,
+ CSR_MHPMCOUNTER28H,
+ CSR_MHPMCOUNTER29H,
+ CSR_MHPMCOUNTER30H,
+ CSR_MHPMCOUNTER31H,
+ CSR_MHPMEVENT3,
+ CSR_MHPMEVENT4,
+ CSR_MHPMEVENT5,
+ CSR_MHPMEVENT6,
+ CSR_MHPMEVENT7,
+ CSR_MHPMEVENT8,
+ CSR_MHPMEVENT9,
+ CSR_MHPMEVENT10,
+ CSR_MHPMEVENT11,
+ CSR_MHPMEVENT12,
+ CSR_MHPMEVENT13,
+ CSR_MHPMEVENT14,
+ CSR_MHPMEVENT15,
+ CSR_MHPMEVENT16,
+ CSR_MHPMEVENT17,
+ CSR_MHPMEVENT18,
+ CSR_MHPMEVENT19,
+ CSR_MHPMEVENT20,
+ CSR_MHPMEVENT21,
+ CSR_MHPMEVENT22,
+ CSR_MHPMEVENT23,
+ CSR_MHPMEVENT24,
+ CSR_MHPMEVENT25,
+ CSR_MHPMEVENT26,
+ CSR_MHPMEVENT27,
+ CSR_MHPMEVENT28,
+ CSR_MHPMEVENT29,
+ CSR_MHPMEVENT30,
+ CSR_MHPMEVENT31,
+ CSR_TSELECT,
+ CSR_TDATA1,
+ CSR_TDATA2,
+ CSR_TDATA3,
+ CSR_DCSR,
+ CSR_DPC,
+ CSR_DSCRATCH,
+ CSR_HSTATUS,
+ CSR_HEDELEG,
+ CSR_HIDELEG,
+ CSR_HIE,
+ CSR_HTVEC,
+ CSR_HSCRATCH,
+ CSR_HEPC,
+ CSR_HCAUSE,
+ CSR_HBADADDR,
+ CSR_HIP,
+ CSR_MBASE,
+ CSR_MBOUND,
+ CSR_MIBASE,
+ CSR_MIBOUND,
+ CSR_MDBASE,
+ CSR_MDBOUND,
+ CSR_MUCOUNTEREN,
+ CSR_MSCOUNTEREN,
+ CSR_MHCOUNTEREN,
+};
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 4f919b6..71c3eb1 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -20,6 +20,7 @@
#include "qemu-common.h"
#include "exec/gdbstub.h"
#include "cpu.h"
+#include "csr-map.h"
int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-riscv] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.
@ 2018-12-28 22:09 ` Jim Wilson
0 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-28 22:09 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers. This also adds
some missing CSR_* register macros.
Signed-off-by: Jim Wilson <jimw@sifive.com>
---
target/riscv/cpu_bits.h | 35 ++++++-
target/riscv/csr-map.h | 248 ++++++++++++++++++++++++++++++++++++++++++++++++
target/riscv/gdbstub.c | 1 +
3 files changed, 282 insertions(+), 2 deletions(-)
create mode 100644 target/riscv/csr-map.h
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5439f47..316d500 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -135,16 +135,22 @@
/* Legacy Counter Setup (priv v1.9.1) */
#define CSR_MUCOUNTEREN 0x320
#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHCOUNTEREN 0x322
/* Machine Trap Handling */
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
-#define CSR_MBADADDR 0x343
+#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
+/* Legacy Machine Trap Handling (priv v1.9.1) */
+#define CSR_MBADADDR 0x343
+
/* Supervisor Trap Setup */
#define CSR_SSTATUS 0x100
+#define CSR_SEDELEG 0x102
+#define CSR_SIDELEG 0x103
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106
@@ -153,9 +159,12 @@
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142
-#define CSR_SBADADDR 0x143
+#define CSR_STVAL 0x143
#define CSR_SIP 0x144
+/* Legacy Supervisor Trap Handling (priv v1.9.1) */
+#define CSR_SBADADDR 0x143
+
/* Supervisor Protection and Translation */
#define CSR_SPTBR 0x180
#define CSR_SATP 0x180
@@ -282,6 +291,28 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
+/* Legacy Hypervisor Trap Setup (priv v1.9.1) */
+#define CSR_HSTATUS 0x200
+#define CSR_HEDELEG 0x202
+#define CSR_HIDELEG 0x203
+#define CSR_HIE 0x204
+#define CSR_HTVEC 0x205
+
+/* Legacy Hypervisor Trap Handling (priv v1.9.1) */
+#define CSR_HSCRATCH 0x240
+#define CSR_HEPC 0x241
+#define CSR_HCAUSE 0x242
+#define CSR_HBADADDR 0x243
+#define CSR_HIP 0x244
+
+/* Legacy Machine Protection and Translation (priv v1.9.1) */
+#define CSR_MBASE 0x380
+#define CSR_MBOUND 0x381
+#define CSR_MIBASE 0x382
+#define CSR_MIBOUND 0x383
+#define CSR_MDBASE 0x384
+#define CSR_MDBOUND 0x385
+
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
diff --git a/target/riscv/csr-map.h b/target/riscv/csr-map.h
new file mode 100644
index 0000000..cce32fd
--- /dev/null
+++ b/target/riscv/csr-map.h
@@ -0,0 +1,248 @@
+/*
+ * The GDB CSR xml files list them in documentation order, not numerical order,
+ * and are missing entries for unnamed CSRs. So we need to map the gdb numbers
+ * to the hardware numbers.
+ */
+
+int csr_register_map[] = {
+ CSR_USTATUS,
+ CSR_UIE,
+ CSR_UTVEC,
+ CSR_USCRATCH,
+ CSR_UEPC,
+ CSR_UCAUSE,
+ CSR_UTVAL,
+ CSR_UIP,
+ CSR_FFLAGS,
+ CSR_FRM,
+ CSR_FCSR,
+ CSR_CYCLE,
+ CSR_TIME,
+ CSR_INSTRET,
+ CSR_HPMCOUNTER3,
+ CSR_HPMCOUNTER4,
+ CSR_HPMCOUNTER5,
+ CSR_HPMCOUNTER6,
+ CSR_HPMCOUNTER7,
+ CSR_HPMCOUNTER8,
+ CSR_HPMCOUNTER9,
+ CSR_HPMCOUNTER10,
+ CSR_HPMCOUNTER11,
+ CSR_HPMCOUNTER12,
+ CSR_HPMCOUNTER13,
+ CSR_HPMCOUNTER14,
+ CSR_HPMCOUNTER15,
+ CSR_HPMCOUNTER16,
+ CSR_HPMCOUNTER17,
+ CSR_HPMCOUNTER18,
+ CSR_HPMCOUNTER19,
+ CSR_HPMCOUNTER20,
+ CSR_HPMCOUNTER21,
+ CSR_HPMCOUNTER22,
+ CSR_HPMCOUNTER23,
+ CSR_HPMCOUNTER24,
+ CSR_HPMCOUNTER25,
+ CSR_HPMCOUNTER26,
+ CSR_HPMCOUNTER27,
+ CSR_HPMCOUNTER28,
+ CSR_HPMCOUNTER29,
+ CSR_HPMCOUNTER30,
+ CSR_HPMCOUNTER31,
+ CSR_CYCLEH,
+ CSR_TIMEH,
+ CSR_INSTRETH,
+ CSR_HPMCOUNTER3H,
+ CSR_HPMCOUNTER4H,
+ CSR_HPMCOUNTER5H,
+ CSR_HPMCOUNTER6H,
+ CSR_HPMCOUNTER7H,
+ CSR_HPMCOUNTER8H,
+ CSR_HPMCOUNTER9H,
+ CSR_HPMCOUNTER10H,
+ CSR_HPMCOUNTER11H,
+ CSR_HPMCOUNTER12H,
+ CSR_HPMCOUNTER13H,
+ CSR_HPMCOUNTER14H,
+ CSR_HPMCOUNTER15H,
+ CSR_HPMCOUNTER16H,
+ CSR_HPMCOUNTER17H,
+ CSR_HPMCOUNTER18H,
+ CSR_HPMCOUNTER19H,
+ CSR_HPMCOUNTER20H,
+ CSR_HPMCOUNTER21H,
+ CSR_HPMCOUNTER22H,
+ CSR_HPMCOUNTER23H,
+ CSR_HPMCOUNTER24H,
+ CSR_HPMCOUNTER25H,
+ CSR_HPMCOUNTER26H,
+ CSR_HPMCOUNTER27H,
+ CSR_HPMCOUNTER28H,
+ CSR_HPMCOUNTER29H,
+ CSR_HPMCOUNTER30H,
+ CSR_HPMCOUNTER31H,
+ CSR_SSTATUS,
+ CSR_SEDELEG,
+ CSR_SIDELEG,
+ CSR_SIE,
+ CSR_STVEC,
+ CSR_SCOUNTEREN,
+ CSR_SSCRATCH,
+ CSR_SEPC,
+ CSR_SCAUSE,
+ CSR_STVAL,
+ CSR_SIP,
+ CSR_SATP,
+ CSR_MVENDORID,
+ CSR_MARCHID,
+ CSR_MIMPID,
+ CSR_MHARTID,
+ CSR_MSTATUS,
+ CSR_MISA,
+ CSR_MEDELEG,
+ CSR_MIDELEG,
+ CSR_MIE,
+ CSR_MTVEC,
+ CSR_MCOUNTEREN,
+ CSR_MSCRATCH,
+ CSR_MEPC,
+ CSR_MCAUSE,
+ CSR_MTVAL,
+ CSR_MIP,
+ CSR_PMPCFG0,
+ CSR_PMPCFG1,
+ CSR_PMPCFG2,
+ CSR_PMPCFG3,
+ CSR_PMPADDR0,
+ CSR_PMPADDR1,
+ CSR_PMPADDR2,
+ CSR_PMPADDR3,
+ CSR_PMPADDR4,
+ CSR_PMPADDR5,
+ CSR_PMPADDR6,
+ CSR_PMPADDR7,
+ CSR_PMPADDR8,
+ CSR_PMPADDR9,
+ CSR_PMPADDR10,
+ CSR_PMPADDR11,
+ CSR_PMPADDR12,
+ CSR_PMPADDR13,
+ CSR_PMPADDR14,
+ CSR_PMPADDR15,
+ CSR_MCYCLE,
+ CSR_MINSTRET,
+ CSR_MHPMCOUNTER3,
+ CSR_MHPMCOUNTER4,
+ CSR_MHPMCOUNTER5,
+ CSR_MHPMCOUNTER6,
+ CSR_MHPMCOUNTER7,
+ CSR_MHPMCOUNTER8,
+ CSR_MHPMCOUNTER9,
+ CSR_MHPMCOUNTER10,
+ CSR_MHPMCOUNTER11,
+ CSR_MHPMCOUNTER12,
+ CSR_MHPMCOUNTER13,
+ CSR_MHPMCOUNTER14,
+ CSR_MHPMCOUNTER15,
+ CSR_MHPMCOUNTER16,
+ CSR_MHPMCOUNTER17,
+ CSR_MHPMCOUNTER18,
+ CSR_MHPMCOUNTER19,
+ CSR_MHPMCOUNTER20,
+ CSR_MHPMCOUNTER21,
+ CSR_MHPMCOUNTER22,
+ CSR_MHPMCOUNTER23,
+ CSR_MHPMCOUNTER24,
+ CSR_MHPMCOUNTER25,
+ CSR_MHPMCOUNTER26,
+ CSR_MHPMCOUNTER27,
+ CSR_MHPMCOUNTER28,
+ CSR_MHPMCOUNTER29,
+ CSR_MHPMCOUNTER30,
+ CSR_MHPMCOUNTER31,
+ CSR_MCYCLEH,
+ CSR_MINSTRETH,
+ CSR_MHPMCOUNTER3H,
+ CSR_MHPMCOUNTER4H,
+ CSR_MHPMCOUNTER5H,
+ CSR_MHPMCOUNTER6H,
+ CSR_MHPMCOUNTER7H,
+ CSR_MHPMCOUNTER8H,
+ CSR_MHPMCOUNTER9H,
+ CSR_MHPMCOUNTER10H,
+ CSR_MHPMCOUNTER11H,
+ CSR_MHPMCOUNTER12H,
+ CSR_MHPMCOUNTER13H,
+ CSR_MHPMCOUNTER14H,
+ CSR_MHPMCOUNTER15H,
+ CSR_MHPMCOUNTER16H,
+ CSR_MHPMCOUNTER17H,
+ CSR_MHPMCOUNTER18H,
+ CSR_MHPMCOUNTER19H,
+ CSR_MHPMCOUNTER20H,
+ CSR_MHPMCOUNTER21H,
+ CSR_MHPMCOUNTER22H,
+ CSR_MHPMCOUNTER23H,
+ CSR_MHPMCOUNTER24H,
+ CSR_MHPMCOUNTER25H,
+ CSR_MHPMCOUNTER26H,
+ CSR_MHPMCOUNTER27H,
+ CSR_MHPMCOUNTER28H,
+ CSR_MHPMCOUNTER29H,
+ CSR_MHPMCOUNTER30H,
+ CSR_MHPMCOUNTER31H,
+ CSR_MHPMEVENT3,
+ CSR_MHPMEVENT4,
+ CSR_MHPMEVENT5,
+ CSR_MHPMEVENT6,
+ CSR_MHPMEVENT7,
+ CSR_MHPMEVENT8,
+ CSR_MHPMEVENT9,
+ CSR_MHPMEVENT10,
+ CSR_MHPMEVENT11,
+ CSR_MHPMEVENT12,
+ CSR_MHPMEVENT13,
+ CSR_MHPMEVENT14,
+ CSR_MHPMEVENT15,
+ CSR_MHPMEVENT16,
+ CSR_MHPMEVENT17,
+ CSR_MHPMEVENT18,
+ CSR_MHPMEVENT19,
+ CSR_MHPMEVENT20,
+ CSR_MHPMEVENT21,
+ CSR_MHPMEVENT22,
+ CSR_MHPMEVENT23,
+ CSR_MHPMEVENT24,
+ CSR_MHPMEVENT25,
+ CSR_MHPMEVENT26,
+ CSR_MHPMEVENT27,
+ CSR_MHPMEVENT28,
+ CSR_MHPMEVENT29,
+ CSR_MHPMEVENT30,
+ CSR_MHPMEVENT31,
+ CSR_TSELECT,
+ CSR_TDATA1,
+ CSR_TDATA2,
+ CSR_TDATA3,
+ CSR_DCSR,
+ CSR_DPC,
+ CSR_DSCRATCH,
+ CSR_HSTATUS,
+ CSR_HEDELEG,
+ CSR_HIDELEG,
+ CSR_HIE,
+ CSR_HTVEC,
+ CSR_HSCRATCH,
+ CSR_HEPC,
+ CSR_HCAUSE,
+ CSR_HBADADDR,
+ CSR_HIP,
+ CSR_MBASE,
+ CSR_MBOUND,
+ CSR_MIBASE,
+ CSR_MIBOUND,
+ CSR_MDBASE,
+ CSR_MDBOUND,
+ CSR_MUCOUNTEREN,
+ CSR_MSCOUNTEREN,
+ CSR_MHCOUNTEREN,
+};
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 4f919b6..71c3eb1 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -20,6 +20,7 @@
#include "qemu-common.h"
#include "exec/gdbstub.h"
#include "cpu.h"
+#include "csr-map.h"
int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 4/5 v2] RISC-V: Add debug support for accessing CSRs.
2018-12-28 22:05 ` [Qemu-riscv] " Jim Wilson
@ 2018-12-28 22:10 ` Jim Wilson
-1 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-28 22:10 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
Adds a debugger parameter to csr_read_helper and csr_write_helper. When
this is true, we disable illegal instruction checks.
Signed-off-by: Jim Wilson <jimw@sifive.com>
---
linux-user/riscv/signal.c | 5 ++-
target/riscv/cpu.h | 7 +++-
target/riscv/cpu_helper.c | 4 +-
target/riscv/gdbstub.c | 4 +-
target/riscv/op_helper.c | 93 ++++++++++++++++++++++++++++++++---------------
5 files changed, 76 insertions(+), 37 deletions(-)
diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
index f598d41..ed76f23 100644
--- a/linux-user/riscv/signal.c
+++ b/linux-user/riscv/signal.c
@@ -83,7 +83,8 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
__put_user(env->fpr[i], &sc->fpr[i]);
}
- uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
+ /*riscv_get_fcsr(env);*/
+ uint32_t fcsr = csr_read_helper(env, CSR_FCSR, false);
__put_user(fcsr, &sc->fcsr);
}
@@ -159,7 +160,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
uint32_t fcsr;
__get_user(fcsr, &sc->fcsr);
- csr_write_helper(env, fcsr, CSR_FCSR);
+ csr_write_helper(env, fcsr, CSR_FCSR, false);
}
static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4ee09b9..29361ca 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -290,8 +290,11 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
}
void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
- target_ulong csrno);
-target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno);
+ target_ulong csrno, bool debugger);
+target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno,
+ bool debugger);
+
+void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
#include "exec/cpu-all.h"
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 86f9f47..1abad94 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -526,7 +526,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
- csr_write_helper(env, s, CSR_MSTATUS);
+ csr_write_helper(env, s, CSR_MSTATUS, false);
riscv_set_mode(env, PRV_S);
} else {
/* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
@@ -551,7 +551,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
- csr_write_helper(env, s, CSR_MSTATUS);
+ csr_write_helper(env, s, CSR_MSTATUS, false);
riscv_set_mode(env, PRV_M);
}
/* TODO yield load reservation */
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 71c3eb1..b06f0fa 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -34,7 +34,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
} else if (n < 65) {
return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
} else if (n < 4096 + 65) {
- return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65));
+ return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65, true));
}
return 0;
}
@@ -57,7 +57,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
return sizeof(uint64_t);
} else if (n < 4096 + 65) {
- csr_write_helper(env, ldtul_p(mem_buf), n - 65);
+ csr_write_helper(env, ldtul_p(mem_buf), n - 65, true);
}
return 0;
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 3726299..3c5641e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -87,7 +87,7 @@ static void validate_mstatus_fs(CPURISCVState *env, uintptr_t ra)
* Adapted from Spike's processor_t::set_csr
*/
void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
- target_ulong csrno)
+ target_ulong csrno, bool debugger)
{
#ifndef CONFIG_USER_ONLY
uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP;
@@ -96,15 +96,21 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
switch (csrno) {
case CSR_FFLAGS:
- validate_mstatus_fs(env, GETPC());
+ if (!debugger) {
+ validate_mstatus_fs(env, GETPC());
+ }
cpu_riscv_set_fflags(env, val_to_write & (FSR_AEXC >> FSR_AEXC_SHIFT));
break;
case CSR_FRM:
- validate_mstatus_fs(env, GETPC());
+ if (!debugger) {
+ validate_mstatus_fs(env, GETPC());
+ }
env->frm = val_to_write & (FSR_RD >> FSR_RD_SHIFT);
break;
case CSR_FCSR:
- validate_mstatus_fs(env, GETPC());
+ if (!debugger) {
+ validate_mstatus_fs(env, GETPC());
+ }
env->frm = (val_to_write & FSR_RD) >> FSR_RD_SHIFT;
cpu_riscv_set_fflags(env, (val_to_write & FSR_AEXC) >> FSR_AEXC_SHIFT);
break;
@@ -169,7 +175,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
* CLINT, no additional locking is needed for read-modifiy-write
* CSR operations
*/
- qemu_mutex_lock_iothread();
+ if (!debugger) {
+ qemu_mutex_lock_iothread();
+ }
RISCVCPU *cpu = riscv_env_get_cpu(env);
riscv_cpu_update_mip(cpu, MIP_SSIP | MIP_STIP,
(val_to_write & (MIP_SSIP | MIP_STIP)));
@@ -177,7 +185,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
* csrs, csrc on mip.SEIP is not decomposable into separate read and
* write steps, so a different implementation is needed
*/
- qemu_mutex_unlock_iothread();
+ if (!debugger) {
+ qemu_mutex_unlock_iothread();
+ }
break;
}
case CSR_MIE: {
@@ -247,21 +257,25 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
mask |= SSTATUS_MXR;
}
ms = (ms & ~mask) | (val_to_write & mask);
- csr_write_helper(env, ms, CSR_MSTATUS);
+ csr_write_helper(env, ms, CSR_MSTATUS, debugger);
break;
}
case CSR_SIP: {
- qemu_mutex_lock_iothread();
+ if (!debugger) {
+ qemu_mutex_lock_iothread();
+ }
target_ulong next_mip = (env->mip & ~env->mideleg)
| (val_to_write & env->mideleg);
- qemu_mutex_unlock_iothread();
- csr_write_helper(env, next_mip, CSR_MIP);
+ if (!debugger) {
+ qemu_mutex_unlock_iothread();
+ }
+ csr_write_helper(env, next_mip, CSR_MIP, debugger);
break;
}
case CSR_SIE: {
target_ulong next_mie = (env->mie & ~env->mideleg)
| (val_to_write & env->mideleg);
- csr_write_helper(env, next_mie, CSR_MIE);
+ csr_write_helper(env, next_mie, CSR_MIE, debugger);
break;
}
case CSR_SATP: /* CSR_SPTBR */ {
@@ -371,7 +385,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
do_illegal:
#endif
default:
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (!debugger) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
}
}
@@ -380,7 +396,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
*
* Adapted from Spike's processor_t::get_csr
*/
-target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
+target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno,
+ bool debugger)
{
#ifndef CONFIG_USER_ONLY
target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
@@ -416,13 +433,19 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
switch (csrno) {
case CSR_FFLAGS:
- validate_mstatus_fs(env, GETPC());
+ if (!debugger) {
+ validate_mstatus_fs(env, GETPC());
+ }
return cpu_riscv_get_fflags(env);
case CSR_FRM:
- validate_mstatus_fs(env, GETPC());
+ if (!debugger) {
+ validate_mstatus_fs(env, GETPC());
+ }
return env->frm;
case CSR_FCSR:
- validate_mstatus_fs(env, GETPC());
+ if (!debugger) {
+ validate_mstatus_fs(env, GETPC());
+ }
return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
/* rdtime/rdtimeh is trapped and emulated by bbl in system mode */
@@ -504,9 +527,13 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
return env->mstatus & mask;
}
case CSR_SIP: {
- qemu_mutex_lock_iothread();
+ if (!debugger) {
+ qemu_mutex_lock_iothread();
+ }
target_ulong tmp = env->mip & env->mideleg;
- qemu_mutex_unlock_iothread();
+ if (!debugger) {
+ qemu_mutex_unlock_iothread();
+ }
return tmp;
}
case CSR_SIE:
@@ -539,9 +566,13 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
case CSR_MSTATUS:
return env->mstatus;
case CSR_MIP: {
- qemu_mutex_lock_iothread();
+ if (!debugger) {
+ qemu_mutex_lock_iothread();
+ }
target_ulong tmp = env->mip;
- qemu_mutex_unlock_iothread();
+ if (!debugger) {
+ qemu_mutex_unlock_iothread();
+ }
return tmp;
}
case CSR_MIE:
@@ -601,7 +632,11 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
#endif
}
/* used by e.g. MTIME read */
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (!debugger) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ } else {
+ return 0;
+ }
}
/*
@@ -625,8 +660,8 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
target_ulong csr)
{
validate_csr(env, csr, 1, GETPC());
- uint64_t csr_backup = csr_read_helper(env, csr);
- csr_write_helper(env, src, csr);
+ uint64_t csr_backup = csr_read_helper(env, csr, false);
+ csr_write_helper(env, src, csr, false);
return csr_backup;
}
@@ -634,9 +669,9 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
target_ulong csr, target_ulong rs1_pass)
{
validate_csr(env, csr, rs1_pass != 0, GETPC());
- uint64_t csr_backup = csr_read_helper(env, csr);
+ uint64_t csr_backup = csr_read_helper(env, csr, false);
if (rs1_pass != 0) {
- csr_write_helper(env, src | csr_backup, csr);
+ csr_write_helper(env, src | csr_backup, csr, false);
}
return csr_backup;
}
@@ -645,9 +680,9 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
target_ulong csr, target_ulong rs1_pass)
{
validate_csr(env, csr, rs1_pass != 0, GETPC());
- uint64_t csr_backup = csr_read_helper(env, csr);
+ uint64_t csr_backup = csr_read_helper(env, csr, false);
if (rs1_pass != 0) {
- csr_write_helper(env, (~src) & csr_backup, csr);
+ csr_write_helper(env, (~src) & csr_backup, csr, false);
}
return csr_backup;
}
@@ -674,7 +709,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
riscv_set_mode(env, prev_priv);
- csr_write_helper(env, mstatus, CSR_MSTATUS);
+ csr_write_helper(env, mstatus, CSR_MSTATUS, false);
return retpc;
}
@@ -699,7 +734,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
riscv_set_mode(env, prev_priv);
- csr_write_helper(env, mstatus, CSR_MSTATUS);
+ csr_write_helper(env, mstatus, CSR_MSTATUS, false);
return retpc;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-riscv] [PATCH 4/5 v2] RISC-V: Add debug support for accessing CSRs.
@ 2018-12-28 22:10 ` Jim Wilson
0 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-28 22:10 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
Adds a debugger parameter to csr_read_helper and csr_write_helper. When
this is true, we disable illegal instruction checks.
Signed-off-by: Jim Wilson <jimw@sifive.com>
---
linux-user/riscv/signal.c | 5 ++-
target/riscv/cpu.h | 7 +++-
target/riscv/cpu_helper.c | 4 +-
target/riscv/gdbstub.c | 4 +-
target/riscv/op_helper.c | 93 ++++++++++++++++++++++++++++++++---------------
5 files changed, 76 insertions(+), 37 deletions(-)
diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
index f598d41..ed76f23 100644
--- a/linux-user/riscv/signal.c
+++ b/linux-user/riscv/signal.c
@@ -83,7 +83,8 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
__put_user(env->fpr[i], &sc->fpr[i]);
}
- uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
+ /*riscv_get_fcsr(env);*/
+ uint32_t fcsr = csr_read_helper(env, CSR_FCSR, false);
__put_user(fcsr, &sc->fcsr);
}
@@ -159,7 +160,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
uint32_t fcsr;
__get_user(fcsr, &sc->fcsr);
- csr_write_helper(env, fcsr, CSR_FCSR);
+ csr_write_helper(env, fcsr, CSR_FCSR, false);
}
static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4ee09b9..29361ca 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -290,8 +290,11 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
}
void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
- target_ulong csrno);
-target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno);
+ target_ulong csrno, bool debugger);
+target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno,
+ bool debugger);
+
+void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
#include "exec/cpu-all.h"
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 86f9f47..1abad94 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -526,7 +526,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
- csr_write_helper(env, s, CSR_MSTATUS);
+ csr_write_helper(env, s, CSR_MSTATUS, false);
riscv_set_mode(env, PRV_S);
} else {
/* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
@@ -551,7 +551,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
- csr_write_helper(env, s, CSR_MSTATUS);
+ csr_write_helper(env, s, CSR_MSTATUS, false);
riscv_set_mode(env, PRV_M);
}
/* TODO yield load reservation */
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 71c3eb1..b06f0fa 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -34,7 +34,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
} else if (n < 65) {
return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
} else if (n < 4096 + 65) {
- return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65));
+ return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65, true));
}
return 0;
}
@@ -57,7 +57,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
return sizeof(uint64_t);
} else if (n < 4096 + 65) {
- csr_write_helper(env, ldtul_p(mem_buf), n - 65);
+ csr_write_helper(env, ldtul_p(mem_buf), n - 65, true);
}
return 0;
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 3726299..3c5641e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -87,7 +87,7 @@ static void validate_mstatus_fs(CPURISCVState *env, uintptr_t ra)
* Adapted from Spike's processor_t::set_csr
*/
void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
- target_ulong csrno)
+ target_ulong csrno, bool debugger)
{
#ifndef CONFIG_USER_ONLY
uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP;
@@ -96,15 +96,21 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
switch (csrno) {
case CSR_FFLAGS:
- validate_mstatus_fs(env, GETPC());
+ if (!debugger) {
+ validate_mstatus_fs(env, GETPC());
+ }
cpu_riscv_set_fflags(env, val_to_write & (FSR_AEXC >> FSR_AEXC_SHIFT));
break;
case CSR_FRM:
- validate_mstatus_fs(env, GETPC());
+ if (!debugger) {
+ validate_mstatus_fs(env, GETPC());
+ }
env->frm = val_to_write & (FSR_RD >> FSR_RD_SHIFT);
break;
case CSR_FCSR:
- validate_mstatus_fs(env, GETPC());
+ if (!debugger) {
+ validate_mstatus_fs(env, GETPC());
+ }
env->frm = (val_to_write & FSR_RD) >> FSR_RD_SHIFT;
cpu_riscv_set_fflags(env, (val_to_write & FSR_AEXC) >> FSR_AEXC_SHIFT);
break;
@@ -169,7 +175,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
* CLINT, no additional locking is needed for read-modifiy-write
* CSR operations
*/
- qemu_mutex_lock_iothread();
+ if (!debugger) {
+ qemu_mutex_lock_iothread();
+ }
RISCVCPU *cpu = riscv_env_get_cpu(env);
riscv_cpu_update_mip(cpu, MIP_SSIP | MIP_STIP,
(val_to_write & (MIP_SSIP | MIP_STIP)));
@@ -177,7 +185,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
* csrs, csrc on mip.SEIP is not decomposable into separate read and
* write steps, so a different implementation is needed
*/
- qemu_mutex_unlock_iothread();
+ if (!debugger) {
+ qemu_mutex_unlock_iothread();
+ }
break;
}
case CSR_MIE: {
@@ -247,21 +257,25 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
mask |= SSTATUS_MXR;
}
ms = (ms & ~mask) | (val_to_write & mask);
- csr_write_helper(env, ms, CSR_MSTATUS);
+ csr_write_helper(env, ms, CSR_MSTATUS, debugger);
break;
}
case CSR_SIP: {
- qemu_mutex_lock_iothread();
+ if (!debugger) {
+ qemu_mutex_lock_iothread();
+ }
target_ulong next_mip = (env->mip & ~env->mideleg)
| (val_to_write & env->mideleg);
- qemu_mutex_unlock_iothread();
- csr_write_helper(env, next_mip, CSR_MIP);
+ if (!debugger) {
+ qemu_mutex_unlock_iothread();
+ }
+ csr_write_helper(env, next_mip, CSR_MIP, debugger);
break;
}
case CSR_SIE: {
target_ulong next_mie = (env->mie & ~env->mideleg)
| (val_to_write & env->mideleg);
- csr_write_helper(env, next_mie, CSR_MIE);
+ csr_write_helper(env, next_mie, CSR_MIE, debugger);
break;
}
case CSR_SATP: /* CSR_SPTBR */ {
@@ -371,7 +385,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
do_illegal:
#endif
default:
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (!debugger) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
}
}
@@ -380,7 +396,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
*
* Adapted from Spike's processor_t::get_csr
*/
-target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
+target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno,
+ bool debugger)
{
#ifndef CONFIG_USER_ONLY
target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
@@ -416,13 +433,19 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
switch (csrno) {
case CSR_FFLAGS:
- validate_mstatus_fs(env, GETPC());
+ if (!debugger) {
+ validate_mstatus_fs(env, GETPC());
+ }
return cpu_riscv_get_fflags(env);
case CSR_FRM:
- validate_mstatus_fs(env, GETPC());
+ if (!debugger) {
+ validate_mstatus_fs(env, GETPC());
+ }
return env->frm;
case CSR_FCSR:
- validate_mstatus_fs(env, GETPC());
+ if (!debugger) {
+ validate_mstatus_fs(env, GETPC());
+ }
return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
/* rdtime/rdtimeh is trapped and emulated by bbl in system mode */
@@ -504,9 +527,13 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
return env->mstatus & mask;
}
case CSR_SIP: {
- qemu_mutex_lock_iothread();
+ if (!debugger) {
+ qemu_mutex_lock_iothread();
+ }
target_ulong tmp = env->mip & env->mideleg;
- qemu_mutex_unlock_iothread();
+ if (!debugger) {
+ qemu_mutex_unlock_iothread();
+ }
return tmp;
}
case CSR_SIE:
@@ -539,9 +566,13 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
case CSR_MSTATUS:
return env->mstatus;
case CSR_MIP: {
- qemu_mutex_lock_iothread();
+ if (!debugger) {
+ qemu_mutex_lock_iothread();
+ }
target_ulong tmp = env->mip;
- qemu_mutex_unlock_iothread();
+ if (!debugger) {
+ qemu_mutex_unlock_iothread();
+ }
return tmp;
}
case CSR_MIE:
@@ -601,7 +632,11 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
#endif
}
/* used by e.g. MTIME read */
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (!debugger) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ } else {
+ return 0;
+ }
}
/*
@@ -625,8 +660,8 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
target_ulong csr)
{
validate_csr(env, csr, 1, GETPC());
- uint64_t csr_backup = csr_read_helper(env, csr);
- csr_write_helper(env, src, csr);
+ uint64_t csr_backup = csr_read_helper(env, csr, false);
+ csr_write_helper(env, src, csr, false);
return csr_backup;
}
@@ -634,9 +669,9 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
target_ulong csr, target_ulong rs1_pass)
{
validate_csr(env, csr, rs1_pass != 0, GETPC());
- uint64_t csr_backup = csr_read_helper(env, csr);
+ uint64_t csr_backup = csr_read_helper(env, csr, false);
if (rs1_pass != 0) {
- csr_write_helper(env, src | csr_backup, csr);
+ csr_write_helper(env, src | csr_backup, csr, false);
}
return csr_backup;
}
@@ -645,9 +680,9 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
target_ulong csr, target_ulong rs1_pass)
{
validate_csr(env, csr, rs1_pass != 0, GETPC());
- uint64_t csr_backup = csr_read_helper(env, csr);
+ uint64_t csr_backup = csr_read_helper(env, csr, false);
if (rs1_pass != 0) {
- csr_write_helper(env, (~src) & csr_backup, csr);
+ csr_write_helper(env, (~src) & csr_backup, csr, false);
}
return csr_backup;
}
@@ -674,7 +709,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
riscv_set_mode(env, prev_priv);
- csr_write_helper(env, mstatus, CSR_MSTATUS);
+ csr_write_helper(env, mstatus, CSR_MSTATUS, false);
return retpc;
}
@@ -699,7 +734,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
riscv_set_mode(env, prev_priv);
- csr_write_helper(env, mstatus, CSR_MSTATUS);
+ csr_write_helper(env, mstatus, CSR_MSTATUS, false);
return retpc;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
2018-12-28 22:05 ` [Qemu-riscv] " Jim Wilson
@ 2018-12-28 22:11 ` Jim Wilson
-1 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-28 22:11 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
Signed-off-by: Jim Wilson <jimw@sifive.com>
---
target/riscv/cpu.c | 9 ++++++-
target/riscv/gdbstub.c | 73 ++++++++++++++++++++++++++++++++++++++++++++------
2 files changed, 73 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a025a0a..b248e3e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -305,6 +305,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
+ riscv_cpu_register_gdb_regs_for_features(cs);
+
qemu_init_vcpu(cs);
cpu_reset(cs);
@@ -345,7 +347,12 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
- cc->gdb_num_core_regs = 65;
+ cc->gdb_num_core_regs = 33;
+#if defined(TARGET_RISCV32)
+ cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+#elif defined(TARGET_RISCV64)
+ cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+#endif
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifdef CONFIG_USER_ONLY
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index b06f0fa..9558d80 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -31,10 +31,6 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
return gdb_get_regl(mem_buf, env->gpr[n]);
} else if (n == 32) {
return gdb_get_regl(mem_buf, env->pc);
- } else if (n < 65) {
- return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
- } else if (n < 4096 + 65) {
- return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65, true));
}
return 0;
}
@@ -53,11 +49,72 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
} else if (n == 32) {
env->pc = ldtul_p(mem_buf);
return sizeof(target_ulong);
- } else if (n < 65) {
- env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
+ }
+ return 0;
+}
+
+static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ return gdb_get_reg64(mem_buf, env->fpr[n]);
+ } else if (n < 35) {
+ /*
+ * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we
+ * subtract 31 to map the gdb FP register number to the CSR number.
+ * This also works for CSR_FRM and CSR_FCSR.
+ */
+ return gdb_get_regl(mem_buf, csr_read_helper(env, n - 31, true));
+ }
+ return 0;
+}
+
+static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
return sizeof(uint64_t);
- } else if (n < 4096 + 65) {
- csr_write_helper(env, ldtul_p(mem_buf), n - 65, true);
+ } else if (n < 35) {
+ /*
+ * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we
+ * subtract 31 to map the gdb FP register number to the CSR number.
+ * This also works for CSR_FRM and CSR_FCSR.
+ */
+ csr_write_helper(env, ldtul_p(mem_buf), n - 31, true);
}
return 0;
}
+
+static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < ARRAY_SIZE(csr_register_map)) {
+ return gdb_get_regl(mem_buf, csr_read_helper(env, csr_register_map[n],
+ true));
+ }
+ return 0;
+}
+
+static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < ARRAY_SIZE(csr_register_map)) {
+ csr_write_helper(env, ldtul_p(mem_buf), csr_register_map[n], true);
+ }
+ return 0;
+}
+
+void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
+{
+ /* ??? Assume all targets have FPU regs for now. */
+#if defined(TARGET_RISCV32)
+ gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ 35, "riscv-32bit-fpu.xml", 0);
+
+ gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
+ 4096, "riscv-32bit-csr.xml", 0);
+#elif defined(TARGET_RISCV64)
+ gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ 35, "riscv-64bit-fpu.xml", 0);
+
+ gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
+ 4096, "riscv-64bit-csr.xml", 0);
+#endif
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-riscv] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
@ 2018-12-28 22:11 ` Jim Wilson
0 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-28 22:11 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
Signed-off-by: Jim Wilson <jimw@sifive.com>
---
target/riscv/cpu.c | 9 ++++++-
target/riscv/gdbstub.c | 73 ++++++++++++++++++++++++++++++++++++++++++++------
2 files changed, 73 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a025a0a..b248e3e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -305,6 +305,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
+ riscv_cpu_register_gdb_regs_for_features(cs);
+
qemu_init_vcpu(cs);
cpu_reset(cs);
@@ -345,7 +347,12 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
- cc->gdb_num_core_regs = 65;
+ cc->gdb_num_core_regs = 33;
+#if defined(TARGET_RISCV32)
+ cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+#elif defined(TARGET_RISCV64)
+ cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+#endif
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifdef CONFIG_USER_ONLY
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index b06f0fa..9558d80 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -31,10 +31,6 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
return gdb_get_regl(mem_buf, env->gpr[n]);
} else if (n == 32) {
return gdb_get_regl(mem_buf, env->pc);
- } else if (n < 65) {
- return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
- } else if (n < 4096 + 65) {
- return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65, true));
}
return 0;
}
@@ -53,11 +49,72 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
} else if (n == 32) {
env->pc = ldtul_p(mem_buf);
return sizeof(target_ulong);
- } else if (n < 65) {
- env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
+ }
+ return 0;
+}
+
+static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ return gdb_get_reg64(mem_buf, env->fpr[n]);
+ } else if (n < 35) {
+ /*
+ * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we
+ * subtract 31 to map the gdb FP register number to the CSR number.
+ * This also works for CSR_FRM and CSR_FCSR.
+ */
+ return gdb_get_regl(mem_buf, csr_read_helper(env, n - 31, true));
+ }
+ return 0;
+}
+
+static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
return sizeof(uint64_t);
- } else if (n < 4096 + 65) {
- csr_write_helper(env, ldtul_p(mem_buf), n - 65, true);
+ } else if (n < 35) {
+ /*
+ * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we
+ * subtract 31 to map the gdb FP register number to the CSR number.
+ * This also works for CSR_FRM and CSR_FCSR.
+ */
+ csr_write_helper(env, ldtul_p(mem_buf), n - 31, true);
}
return 0;
}
+
+static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < ARRAY_SIZE(csr_register_map)) {
+ return gdb_get_regl(mem_buf, csr_read_helper(env, csr_register_map[n],
+ true));
+ }
+ return 0;
+}
+
+static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < ARRAY_SIZE(csr_register_map)) {
+ csr_write_helper(env, ldtul_p(mem_buf), csr_register_map[n], true);
+ }
+ return 0;
+}
+
+void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
+{
+ /* ??? Assume all targets have FPU regs for now. */
+#if defined(TARGET_RISCV32)
+ gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ 35, "riscv-32bit-fpu.xml", 0);
+
+ gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
+ 4096, "riscv-32bit-csr.xml", 0);
+#elif defined(TARGET_RISCV64)
+ gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ 35, "riscv-64bit-fpu.xml", 0);
+
+ gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
+ 4096, "riscv-64bit-csr.xml", 0);
+#endif
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files.
2018-12-28 22:07 ` [Qemu-riscv] " Jim Wilson
@ 2018-12-29 22:20 ` Richard Henderson
-1 siblings, 0 replies; 38+ messages in thread
From: Richard Henderson @ 2018-12-29 22:20 UTC (permalink / raw)
To: Jim Wilson, qemu-devel; +Cc: qemu-riscv
On 12/29/18 9:07 AM, Jim Wilson wrote:
> Signed-off-by: Jim Wilson <jimw@sifive.com>
> ---
> configure | 1 +
> gdb-xml/riscv-32bit-cpu.xml | 43 ++++++++
> gdb-xml/riscv-32bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++
> gdb-xml/riscv-32bit-fpu.xml | 46 ++++++++
> 4 files changed, 340 insertions(+)
> create mode 100644 gdb-xml/riscv-32bit-cpu.xml
> create mode 100644 gdb-xml/riscv-32bit-csr.xml
> create mode 100644 gdb-xml/riscv-32bit-fpu.xml
Don't the csr's vary between priv-1.9.1 and priv-1.10?
I wonder if it would be better to auto-generate these, via the
gdb_get_dynamic_xml hook. That way you don't need near identical copies for
32-bit vs 64-bit.
r~
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files.
@ 2018-12-29 22:20 ` Richard Henderson
0 siblings, 0 replies; 38+ messages in thread
From: Richard Henderson @ 2018-12-29 22:20 UTC (permalink / raw)
To: Jim Wilson, qemu-devel; +Cc: qemu-riscv
On 12/29/18 9:07 AM, Jim Wilson wrote:
> Signed-off-by: Jim Wilson <jimw@sifive.com>
> ---
> configure | 1 +
> gdb-xml/riscv-32bit-cpu.xml | 43 ++++++++
> gdb-xml/riscv-32bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++
> gdb-xml/riscv-32bit-fpu.xml | 46 ++++++++
> 4 files changed, 340 insertions(+)
> create mode 100644 gdb-xml/riscv-32bit-cpu.xml
> create mode 100644 gdb-xml/riscv-32bit-csr.xml
> create mode 100644 gdb-xml/riscv-32bit-fpu.xml
Don't the csr's vary between priv-1.9.1 and priv-1.10?
I wonder if it would be better to auto-generate these, via the
gdb_get_dynamic_xml hook. That way you don't need near identical copies for
32-bit vs 64-bit.
r~
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.
2018-12-28 22:09 ` [Qemu-riscv] " Jim Wilson
@ 2018-12-29 22:23 ` Richard Henderson
-1 siblings, 0 replies; 38+ messages in thread
From: Richard Henderson @ 2018-12-29 22:23 UTC (permalink / raw)
To: Jim Wilson, qemu-devel; +Cc: qemu-riscv
On 12/29/18 9:09 AM, Jim Wilson wrote:
> +++ b/target/riscv/csr-map.h
> @@ -0,0 +1,248 @@
> +/*
> + * The GDB CSR xml files list them in documentation order, not numerical order,
> + * and are missing entries for unnamed CSRs. So we need to map the gdb numbers
> + * to the hardware numbers.
> + */
> +
> +int csr_register_map[] = {
static const?
Putting an initialized variable in a header file doesn't seem right. Is this
supposed to be a declaration that is shared between c files?
r~
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.
@ 2018-12-29 22:23 ` Richard Henderson
0 siblings, 0 replies; 38+ messages in thread
From: Richard Henderson @ 2018-12-29 22:23 UTC (permalink / raw)
To: Jim Wilson, qemu-devel; +Cc: qemu-riscv
On 12/29/18 9:09 AM, Jim Wilson wrote:
> +++ b/target/riscv/csr-map.h
> @@ -0,0 +1,248 @@
> +/*
> + * The GDB CSR xml files list them in documentation order, not numerical order,
> + * and are missing entries for unnamed CSRs. So we need to map the gdb numbers
> + * to the hardware numbers.
> + */
> +
> +int csr_register_map[] = {
static const?
Putting an initialized variable in a header file doesn't seem right. Is this
supposed to be a declaration that is shared between c files?
r~
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 4/5 v2] RISC-V: Add debug support for accessing CSRs.
2018-12-28 22:10 ` [Qemu-riscv] " Jim Wilson
@ 2018-12-29 22:25 ` Richard Henderson
-1 siblings, 0 replies; 38+ messages in thread
From: Richard Henderson @ 2018-12-29 22:25 UTC (permalink / raw)
To: Jim Wilson, qemu-devel; +Cc: qemu-riscv
On 12/29/18 9:10 AM, Jim Wilson wrote:
> Adds a debugger parameter to csr_read_helper and csr_write_helper. When
> this is true, we disable illegal instruction checks.
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>
> ---
> linux-user/riscv/signal.c | 5 ++-
> target/riscv/cpu.h | 7 +++-
> target/riscv/cpu_helper.c | 4 +-
> target/riscv/gdbstub.c | 4 +-
> target/riscv/op_helper.c | 93 ++++++++++++++++++++++++++++++++---------------
> 5 files changed, 76 insertions(+), 37 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 4/5 v2] RISC-V: Add debug support for accessing CSRs.
@ 2018-12-29 22:25 ` Richard Henderson
0 siblings, 0 replies; 38+ messages in thread
From: Richard Henderson @ 2018-12-29 22:25 UTC (permalink / raw)
To: Jim Wilson, qemu-devel; +Cc: qemu-riscv
On 12/29/18 9:10 AM, Jim Wilson wrote:
> Adds a debugger parameter to csr_read_helper and csr_write_helper. When
> this is true, we disable illegal instruction checks.
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>
> ---
> linux-user/riscv/signal.c | 5 ++-
> target/riscv/cpu.h | 7 +++-
> target/riscv/cpu_helper.c | 4 +-
> target/riscv/gdbstub.c | 4 +-
> target/riscv/op_helper.c | 93 ++++++++++++++++++++++++++++++++---------------
> 5 files changed, 76 insertions(+), 37 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.
2018-12-29 22:23 ` [Qemu-riscv] " Richard Henderson
@ 2018-12-30 19:22 ` Jim Wilson
-1 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-30 19:22 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-riscv
On Sat, Dec 29, 2018 at 2:23 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 12/29/18 9:09 AM, Jim Wilson wrote:
> > +int csr_register_map[] = {
>
> static const?
If I add static const here, then I get a build error if this patch is
applied to the tree but the following patch #5 that uses the variable
is not applied. Though I suppose I could fix that if I put the static
const in patch 5. That would look a little funny but would work.
> Putting an initialized variable in a header file doesn't seem right. Is this
> supposed to be a declaration that is shared between c files?
I did it this way for two reasons. It makes it easier to keep the
register mapping consistent with the gdb csr file, if the gdb csr file
happens to change in the future. We can just do a line by line
comparison of the gdb csr file against the csr-map.h file to verify
that the csr names match. And it makes for a cleaner patch if the gdb
csr file register numbering gets fixed in the future, in that case we
can just delete this file and change a few lines to stop using this
variable.
This variable is only meant to be used in one file, the
target/riscv/gdbstubs.c file.
Jim
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.
@ 2018-12-30 19:22 ` Jim Wilson
0 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-30 19:22 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-riscv
On Sat, Dec 29, 2018 at 2:23 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 12/29/18 9:09 AM, Jim Wilson wrote:
> > +int csr_register_map[] = {
>
> static const?
If I add static const here, then I get a build error if this patch is
applied to the tree but the following patch #5 that uses the variable
is not applied. Though I suppose I could fix that if I put the static
const in patch 5. That would look a little funny but would work.
> Putting an initialized variable in a header file doesn't seem right. Is this
> supposed to be a declaration that is shared between c files?
I did it this way for two reasons. It makes it easier to keep the
register mapping consistent with the gdb csr file, if the gdb csr file
happens to change in the future. We can just do a line by line
comparison of the gdb csr file against the csr-map.h file to verify
that the csr names match. And it makes for a cleaner patch if the gdb
csr file register numbering gets fixed in the future, in that case we
can just delete this file and change a few lines to stop using this
variable.
This variable is only meant to be used in one file, the
target/riscv/gdbstubs.c file.
Jim
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files.
2018-12-29 22:20 ` [Qemu-riscv] " Richard Henderson
@ 2018-12-30 19:56 ` Jim Wilson
-1 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-30 19:56 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-riscv
On Sat, Dec 29, 2018 at 2:20 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 12/29/18 9:07 AM, Jim Wilson wrote:
> Don't the csr's vary between priv-1.9.1 and priv-1.10?
There are a few csr's that disappear in 1.10, but there is no known
hardware that implements them. There are a few csr's new in 1.10, but
I don't know of any 1.9.1 systems that can run the software that
requires the new registers. There are a few that change name; the
toolchain supports both the old and new names. On the toolchain side,
currently, none of the tools care about the privilege spec version.
And the linux kernel doesn't care about the priv spec version either.
This will eventually have to change, maybe with 1.11, but so far it
hasn't been an issue with any software I've seen.
qemu has an option to specify the priv spec version. But looking at
the csr's, this affects two of the registers that disappeared, which
were never implemented in hardware, and aren't supported by gdb. This
also affects a few registers that have new fields in 1.10, but gdb
doesn't know about those internal register fields, so this doesn't
affect gdb either.
> I wonder if it would be better to auto-generate these, via the
> gdb_get_dynamic_xml hook. That way you don't need near identical copies for
> 32-bit vs 64-bit.
I haven't tried looking at this, but I don't see a convenient list of
implemented csr's. This list would be every csr that the
csr_read_helper function in target/riscv/op_helper.c supports That
function requires some machine state that includes the register
values, so it doesn't look convenient to use, unless we add more
hackery to it.
Long term, it would be useful to have target specific csr register
lists. Most csr's are optional, and most hardware only implements a
subset of them. This is somewhat orthogonal to what I'm trying to do
here, but this would require a list of supported csr's in the target
hardware file, then this would have to be fed back into
csr_read_helper somehow, and then we could also use this to generate
an appropriate xml csr register file for that target for use with gdb.
Openocd already does something like this for a few supported targets.
Jim
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files.
@ 2018-12-30 19:56 ` Jim Wilson
0 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2018-12-30 19:56 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-riscv
On Sat, Dec 29, 2018 at 2:20 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 12/29/18 9:07 AM, Jim Wilson wrote:
> Don't the csr's vary between priv-1.9.1 and priv-1.10?
There are a few csr's that disappear in 1.10, but there is no known
hardware that implements them. There are a few csr's new in 1.10, but
I don't know of any 1.9.1 systems that can run the software that
requires the new registers. There are a few that change name; the
toolchain supports both the old and new names. On the toolchain side,
currently, none of the tools care about the privilege spec version.
And the linux kernel doesn't care about the priv spec version either.
This will eventually have to change, maybe with 1.11, but so far it
hasn't been an issue with any software I've seen.
qemu has an option to specify the priv spec version. But looking at
the csr's, this affects two of the registers that disappeared, which
were never implemented in hardware, and aren't supported by gdb. This
also affects a few registers that have new fields in 1.10, but gdb
doesn't know about those internal register fields, so this doesn't
affect gdb either.
> I wonder if it would be better to auto-generate these, via the
> gdb_get_dynamic_xml hook. That way you don't need near identical copies for
> 32-bit vs 64-bit.
I haven't tried looking at this, but I don't see a convenient list of
implemented csr's. This list would be every csr that the
csr_read_helper function in target/riscv/op_helper.c supports That
function requires some machine state that includes the register
values, so it doesn't look convenient to use, unless we add more
hackery to it.
Long term, it would be useful to have target specific csr register
lists. Most csr's are optional, and most hardware only implements a
subset of them. This is somewhat orthogonal to what I'm trying to do
here, but this would require a list of supported csr's in the target
hardware file, then this would have to be fed back into
csr_read_helper somehow, and then we could also use this to generate
an appropriate xml csr register file for that target for use with gdb.
Openocd already does something like this for a few supported targets.
Jim
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.
2018-12-30 19:22 ` [Qemu-riscv] " Jim Wilson
@ 2019-01-22 21:45 ` Alistair Francis
-1 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2019-01-22 21:45 UTC (permalink / raw)
To: Jim Wilson
Cc: Richard Henderson, qemu-riscv, qemu-devel@nongnu.org Developers
On Sun, Dec 30, 2018 at 11:22 AM Jim Wilson <jimw@sifive.com> wrote:
>
> On Sat, Dec 29, 2018 at 2:23 PM Richard Henderson
> <richard.henderson@linaro.org> wrote:
> > On 12/29/18 9:09 AM, Jim Wilson wrote:
> > > +int csr_register_map[] = {
> >
> > static const?
>
> If I add static const here, then I get a build error if this patch is
> applied to the tree but the following patch #5 that uses the variable
> is not applied. Though I suppose I could fix that if I put the static
> const in patch 5. That would look a little funny but would work.
>
> > Putting an initialized variable in a header file doesn't seem right. Is this
> > supposed to be a declaration that is shared between c files?
>
> I did it this way for two reasons. It makes it easier to keep the
> register mapping consistent with the gdb csr file, if the gdb csr file
> happens to change in the future. We can just do a line by line
> comparison of the gdb csr file against the csr-map.h file to verify
> that the csr names match. And it makes for a cleaner patch if the gdb
> csr file register numbering gets fixed in the future, in that case we
> can just delete this file and change a few lines to stop using this
> variable.
>
> This variable is only meant to be used in one file, the
> target/riscv/gdbstubs.c file.
I think it makes more sense to just define the variable in the
gdbstubs.c file then. Can you move it to patch 5?
Alistair
>
> Jim
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.
@ 2019-01-22 21:45 ` Alistair Francis
0 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2019-01-22 21:45 UTC (permalink / raw)
To: Jim Wilson
Cc: Richard Henderson, qemu-riscv, qemu-devel@nongnu.org Developers
On Sun, Dec 30, 2018 at 11:22 AM Jim Wilson <jimw@sifive.com> wrote:
>
> On Sat, Dec 29, 2018 at 2:23 PM Richard Henderson
> <richard.henderson@linaro.org> wrote:
> > On 12/29/18 9:09 AM, Jim Wilson wrote:
> > > +int csr_register_map[] = {
> >
> > static const?
>
> If I add static const here, then I get a build error if this patch is
> applied to the tree but the following patch #5 that uses the variable
> is not applied. Though I suppose I could fix that if I put the static
> const in patch 5. That would look a little funny but would work.
>
> > Putting an initialized variable in a header file doesn't seem right. Is this
> > supposed to be a declaration that is shared between c files?
>
> I did it this way for two reasons. It makes it easier to keep the
> register mapping consistent with the gdb csr file, if the gdb csr file
> happens to change in the future. We can just do a line by line
> comparison of the gdb csr file against the csr-map.h file to verify
> that the csr names match. And it makes for a cleaner patch if the gdb
> csr file register numbering gets fixed in the future, in that case we
> can just delete this file and change a few lines to stop using this
> variable.
>
> This variable is only meant to be used in one file, the
> target/riscv/gdbstubs.c file.
I think it makes more sense to just define the variable in the
gdbstubs.c file then. Can you move it to patch 5?
Alistair
>
> Jim
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 4/5 v2] RISC-V: Add debug support for accessing CSRs.
2018-12-28 22:10 ` [Qemu-riscv] " Jim Wilson
@ 2019-01-22 21:46 ` Alistair Francis
-1 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2019-01-22 21:46 UTC (permalink / raw)
To: Jim Wilson; +Cc: qemu-devel@nongnu.org Developers, qemu-riscv
On Fri, Dec 28, 2018 at 2:23 PM Jim Wilson <jimw@sifive.com> wrote:
>
> Adds a debugger parameter to csr_read_helper and csr_write_helper. When
> this is true, we disable illegal instruction checks.
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> linux-user/riscv/signal.c | 5 ++-
> target/riscv/cpu.h | 7 +++-
> target/riscv/cpu_helper.c | 4 +-
> target/riscv/gdbstub.c | 4 +-
> target/riscv/op_helper.c | 93 ++++++++++++++++++++++++++++++++---------------
> 5 files changed, 76 insertions(+), 37 deletions(-)
>
> diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
> index f598d41..ed76f23 100644
> --- a/linux-user/riscv/signal.c
> +++ b/linux-user/riscv/signal.c
> @@ -83,7 +83,8 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
> __put_user(env->fpr[i], &sc->fpr[i]);
> }
>
> - uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
> + /*riscv_get_fcsr(env);*/
> + uint32_t fcsr = csr_read_helper(env, CSR_FCSR, false);
> __put_user(fcsr, &sc->fcsr);
> }
>
> @@ -159,7 +160,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
>
> uint32_t fcsr;
> __get_user(fcsr, &sc->fcsr);
> - csr_write_helper(env, fcsr, CSR_FCSR);
> + csr_write_helper(env, fcsr, CSR_FCSR, false);
> }
>
> static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4ee09b9..29361ca 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -290,8 +290,11 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> }
>
> void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> - target_ulong csrno);
> -target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno);
> + target_ulong csrno, bool debugger);
> +target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno,
> + bool debugger);
> +
> +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
>
> #include "exec/cpu-all.h"
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 86f9f47..1abad94 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -526,7 +526,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
> s = set_field(s, MSTATUS_SPP, env->priv);
> s = set_field(s, MSTATUS_SIE, 0);
> - csr_write_helper(env, s, CSR_MSTATUS);
> + csr_write_helper(env, s, CSR_MSTATUS, false);
> riscv_set_mode(env, PRV_S);
> } else {
> /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
> @@ -551,7 +551,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
> s = set_field(s, MSTATUS_MPP, env->priv);
> s = set_field(s, MSTATUS_MIE, 0);
> - csr_write_helper(env, s, CSR_MSTATUS);
> + csr_write_helper(env, s, CSR_MSTATUS, false);
> riscv_set_mode(env, PRV_M);
> }
> /* TODO yield load reservation */
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 71c3eb1..b06f0fa 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -34,7 +34,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
> } else if (n < 65) {
> return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
> } else if (n < 4096 + 65) {
> - return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65));
> + return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65, true));
> }
> return 0;
> }
> @@ -57,7 +57,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
> return sizeof(uint64_t);
> } else if (n < 4096 + 65) {
> - csr_write_helper(env, ldtul_p(mem_buf), n - 65);
> + csr_write_helper(env, ldtul_p(mem_buf), n - 65, true);
> }
> return 0;
> }
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 3726299..3c5641e 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -87,7 +87,7 @@ static void validate_mstatus_fs(CPURISCVState *env, uintptr_t ra)
> * Adapted from Spike's processor_t::set_csr
> */
> void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> - target_ulong csrno)
> + target_ulong csrno, bool debugger)
> {
> #ifndef CONFIG_USER_ONLY
> uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP;
> @@ -96,15 +96,21 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
>
> switch (csrno) {
> case CSR_FFLAGS:
> - validate_mstatus_fs(env, GETPC());
> + if (!debugger) {
> + validate_mstatus_fs(env, GETPC());
> + }
> cpu_riscv_set_fflags(env, val_to_write & (FSR_AEXC >> FSR_AEXC_SHIFT));
> break;
> case CSR_FRM:
> - validate_mstatus_fs(env, GETPC());
> + if (!debugger) {
> + validate_mstatus_fs(env, GETPC());
> + }
> env->frm = val_to_write & (FSR_RD >> FSR_RD_SHIFT);
> break;
> case CSR_FCSR:
> - validate_mstatus_fs(env, GETPC());
> + if (!debugger) {
> + validate_mstatus_fs(env, GETPC());
> + }
> env->frm = (val_to_write & FSR_RD) >> FSR_RD_SHIFT;
> cpu_riscv_set_fflags(env, (val_to_write & FSR_AEXC) >> FSR_AEXC_SHIFT);
> break;
> @@ -169,7 +175,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> * CLINT, no additional locking is needed for read-modifiy-write
> * CSR operations
> */
> - qemu_mutex_lock_iothread();
> + if (!debugger) {
> + qemu_mutex_lock_iothread();
> + }
> RISCVCPU *cpu = riscv_env_get_cpu(env);
> riscv_cpu_update_mip(cpu, MIP_SSIP | MIP_STIP,
> (val_to_write & (MIP_SSIP | MIP_STIP)));
> @@ -177,7 +185,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> * csrs, csrc on mip.SEIP is not decomposable into separate read and
> * write steps, so a different implementation is needed
> */
> - qemu_mutex_unlock_iothread();
> + if (!debugger) {
> + qemu_mutex_unlock_iothread();
> + }
> break;
> }
> case CSR_MIE: {
> @@ -247,21 +257,25 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> mask |= SSTATUS_MXR;
> }
> ms = (ms & ~mask) | (val_to_write & mask);
> - csr_write_helper(env, ms, CSR_MSTATUS);
> + csr_write_helper(env, ms, CSR_MSTATUS, debugger);
> break;
> }
> case CSR_SIP: {
> - qemu_mutex_lock_iothread();
> + if (!debugger) {
> + qemu_mutex_lock_iothread();
> + }
> target_ulong next_mip = (env->mip & ~env->mideleg)
> | (val_to_write & env->mideleg);
> - qemu_mutex_unlock_iothread();
> - csr_write_helper(env, next_mip, CSR_MIP);
> + if (!debugger) {
> + qemu_mutex_unlock_iothread();
> + }
> + csr_write_helper(env, next_mip, CSR_MIP, debugger);
> break;
> }
> case CSR_SIE: {
> target_ulong next_mie = (env->mie & ~env->mideleg)
> | (val_to_write & env->mideleg);
> - csr_write_helper(env, next_mie, CSR_MIE);
> + csr_write_helper(env, next_mie, CSR_MIE, debugger);
> break;
> }
> case CSR_SATP: /* CSR_SPTBR */ {
> @@ -371,7 +385,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> do_illegal:
> #endif
> default:
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + if (!debugger) {
> + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + }
> }
> }
>
> @@ -380,7 +396,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> *
> * Adapted from Spike's processor_t::get_csr
> */
> -target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
> +target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno,
> + bool debugger)
> {
> #ifndef CONFIG_USER_ONLY
> target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
> @@ -416,13 +433,19 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
>
> switch (csrno) {
> case CSR_FFLAGS:
> - validate_mstatus_fs(env, GETPC());
> + if (!debugger) {
> + validate_mstatus_fs(env, GETPC());
> + }
> return cpu_riscv_get_fflags(env);
> case CSR_FRM:
> - validate_mstatus_fs(env, GETPC());
> + if (!debugger) {
> + validate_mstatus_fs(env, GETPC());
> + }
> return env->frm;
> case CSR_FCSR:
> - validate_mstatus_fs(env, GETPC());
> + if (!debugger) {
> + validate_mstatus_fs(env, GETPC());
> + }
> return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
> | (env->frm << FSR_RD_SHIFT);
> /* rdtime/rdtimeh is trapped and emulated by bbl in system mode */
> @@ -504,9 +527,13 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
> return env->mstatus & mask;
> }
> case CSR_SIP: {
> - qemu_mutex_lock_iothread();
> + if (!debugger) {
> + qemu_mutex_lock_iothread();
> + }
> target_ulong tmp = env->mip & env->mideleg;
> - qemu_mutex_unlock_iothread();
> + if (!debugger) {
> + qemu_mutex_unlock_iothread();
> + }
> return tmp;
> }
> case CSR_SIE:
> @@ -539,9 +566,13 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
> case CSR_MSTATUS:
> return env->mstatus;
> case CSR_MIP: {
> - qemu_mutex_lock_iothread();
> + if (!debugger) {
> + qemu_mutex_lock_iothread();
> + }
> target_ulong tmp = env->mip;
> - qemu_mutex_unlock_iothread();
> + if (!debugger) {
> + qemu_mutex_unlock_iothread();
> + }
> return tmp;
> }
> case CSR_MIE:
> @@ -601,7 +632,11 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
> #endif
> }
> /* used by e.g. MTIME read */
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + if (!debugger) {
> + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + } else {
> + return 0;
> + }
> }
>
> /*
> @@ -625,8 +660,8 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
> target_ulong csr)
> {
> validate_csr(env, csr, 1, GETPC());
> - uint64_t csr_backup = csr_read_helper(env, csr);
> - csr_write_helper(env, src, csr);
> + uint64_t csr_backup = csr_read_helper(env, csr, false);
> + csr_write_helper(env, src, csr, false);
> return csr_backup;
> }
>
> @@ -634,9 +669,9 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
> target_ulong csr, target_ulong rs1_pass)
> {
> validate_csr(env, csr, rs1_pass != 0, GETPC());
> - uint64_t csr_backup = csr_read_helper(env, csr);
> + uint64_t csr_backup = csr_read_helper(env, csr, false);
> if (rs1_pass != 0) {
> - csr_write_helper(env, src | csr_backup, csr);
> + csr_write_helper(env, src | csr_backup, csr, false);
> }
> return csr_backup;
> }
> @@ -645,9 +680,9 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> target_ulong csr, target_ulong rs1_pass)
> {
> validate_csr(env, csr, rs1_pass != 0, GETPC());
> - uint64_t csr_backup = csr_read_helper(env, csr);
> + uint64_t csr_backup = csr_read_helper(env, csr, false);
> if (rs1_pass != 0) {
> - csr_write_helper(env, (~src) & csr_backup, csr);
> + csr_write_helper(env, (~src) & csr_backup, csr, false);
> }
> return csr_backup;
> }
> @@ -674,7 +709,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
> riscv_set_mode(env, prev_priv);
> - csr_write_helper(env, mstatus, CSR_MSTATUS);
> + csr_write_helper(env, mstatus, CSR_MSTATUS, false);
>
> return retpc;
> }
> @@ -699,7 +734,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> riscv_set_mode(env, prev_priv);
> - csr_write_helper(env, mstatus, CSR_MSTATUS);
> + csr_write_helper(env, mstatus, CSR_MSTATUS, false);
>
> return retpc;
> }
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 4/5 v2] RISC-V: Add debug support for accessing CSRs.
@ 2019-01-22 21:46 ` Alistair Francis
0 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2019-01-22 21:46 UTC (permalink / raw)
To: Jim Wilson; +Cc: qemu-devel@nongnu.org Developers, qemu-riscv
On Fri, Dec 28, 2018 at 2:23 PM Jim Wilson <jimw@sifive.com> wrote:
>
> Adds a debugger parameter to csr_read_helper and csr_write_helper. When
> this is true, we disable illegal instruction checks.
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> linux-user/riscv/signal.c | 5 ++-
> target/riscv/cpu.h | 7 +++-
> target/riscv/cpu_helper.c | 4 +-
> target/riscv/gdbstub.c | 4 +-
> target/riscv/op_helper.c | 93 ++++++++++++++++++++++++++++++++---------------
> 5 files changed, 76 insertions(+), 37 deletions(-)
>
> diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
> index f598d41..ed76f23 100644
> --- a/linux-user/riscv/signal.c
> +++ b/linux-user/riscv/signal.c
> @@ -83,7 +83,8 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
> __put_user(env->fpr[i], &sc->fpr[i]);
> }
>
> - uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
> + /*riscv_get_fcsr(env);*/
> + uint32_t fcsr = csr_read_helper(env, CSR_FCSR, false);
> __put_user(fcsr, &sc->fcsr);
> }
>
> @@ -159,7 +160,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
>
> uint32_t fcsr;
> __get_user(fcsr, &sc->fcsr);
> - csr_write_helper(env, fcsr, CSR_FCSR);
> + csr_write_helper(env, fcsr, CSR_FCSR, false);
> }
>
> static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4ee09b9..29361ca 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -290,8 +290,11 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> }
>
> void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> - target_ulong csrno);
> -target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno);
> + target_ulong csrno, bool debugger);
> +target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno,
> + bool debugger);
> +
> +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
>
> #include "exec/cpu-all.h"
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 86f9f47..1abad94 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -526,7 +526,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
> s = set_field(s, MSTATUS_SPP, env->priv);
> s = set_field(s, MSTATUS_SIE, 0);
> - csr_write_helper(env, s, CSR_MSTATUS);
> + csr_write_helper(env, s, CSR_MSTATUS, false);
> riscv_set_mode(env, PRV_S);
> } else {
> /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
> @@ -551,7 +551,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
> s = set_field(s, MSTATUS_MPP, env->priv);
> s = set_field(s, MSTATUS_MIE, 0);
> - csr_write_helper(env, s, CSR_MSTATUS);
> + csr_write_helper(env, s, CSR_MSTATUS, false);
> riscv_set_mode(env, PRV_M);
> }
> /* TODO yield load reservation */
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 71c3eb1..b06f0fa 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -34,7 +34,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
> } else if (n < 65) {
> return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
> } else if (n < 4096 + 65) {
> - return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65));
> + return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65, true));
> }
> return 0;
> }
> @@ -57,7 +57,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
> return sizeof(uint64_t);
> } else if (n < 4096 + 65) {
> - csr_write_helper(env, ldtul_p(mem_buf), n - 65);
> + csr_write_helper(env, ldtul_p(mem_buf), n - 65, true);
> }
> return 0;
> }
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 3726299..3c5641e 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -87,7 +87,7 @@ static void validate_mstatus_fs(CPURISCVState *env, uintptr_t ra)
> * Adapted from Spike's processor_t::set_csr
> */
> void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> - target_ulong csrno)
> + target_ulong csrno, bool debugger)
> {
> #ifndef CONFIG_USER_ONLY
> uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP;
> @@ -96,15 +96,21 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
>
> switch (csrno) {
> case CSR_FFLAGS:
> - validate_mstatus_fs(env, GETPC());
> + if (!debugger) {
> + validate_mstatus_fs(env, GETPC());
> + }
> cpu_riscv_set_fflags(env, val_to_write & (FSR_AEXC >> FSR_AEXC_SHIFT));
> break;
> case CSR_FRM:
> - validate_mstatus_fs(env, GETPC());
> + if (!debugger) {
> + validate_mstatus_fs(env, GETPC());
> + }
> env->frm = val_to_write & (FSR_RD >> FSR_RD_SHIFT);
> break;
> case CSR_FCSR:
> - validate_mstatus_fs(env, GETPC());
> + if (!debugger) {
> + validate_mstatus_fs(env, GETPC());
> + }
> env->frm = (val_to_write & FSR_RD) >> FSR_RD_SHIFT;
> cpu_riscv_set_fflags(env, (val_to_write & FSR_AEXC) >> FSR_AEXC_SHIFT);
> break;
> @@ -169,7 +175,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> * CLINT, no additional locking is needed for read-modifiy-write
> * CSR operations
> */
> - qemu_mutex_lock_iothread();
> + if (!debugger) {
> + qemu_mutex_lock_iothread();
> + }
> RISCVCPU *cpu = riscv_env_get_cpu(env);
> riscv_cpu_update_mip(cpu, MIP_SSIP | MIP_STIP,
> (val_to_write & (MIP_SSIP | MIP_STIP)));
> @@ -177,7 +185,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> * csrs, csrc on mip.SEIP is not decomposable into separate read and
> * write steps, so a different implementation is needed
> */
> - qemu_mutex_unlock_iothread();
> + if (!debugger) {
> + qemu_mutex_unlock_iothread();
> + }
> break;
> }
> case CSR_MIE: {
> @@ -247,21 +257,25 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> mask |= SSTATUS_MXR;
> }
> ms = (ms & ~mask) | (val_to_write & mask);
> - csr_write_helper(env, ms, CSR_MSTATUS);
> + csr_write_helper(env, ms, CSR_MSTATUS, debugger);
> break;
> }
> case CSR_SIP: {
> - qemu_mutex_lock_iothread();
> + if (!debugger) {
> + qemu_mutex_lock_iothread();
> + }
> target_ulong next_mip = (env->mip & ~env->mideleg)
> | (val_to_write & env->mideleg);
> - qemu_mutex_unlock_iothread();
> - csr_write_helper(env, next_mip, CSR_MIP);
> + if (!debugger) {
> + qemu_mutex_unlock_iothread();
> + }
> + csr_write_helper(env, next_mip, CSR_MIP, debugger);
> break;
> }
> case CSR_SIE: {
> target_ulong next_mie = (env->mie & ~env->mideleg)
> | (val_to_write & env->mideleg);
> - csr_write_helper(env, next_mie, CSR_MIE);
> + csr_write_helper(env, next_mie, CSR_MIE, debugger);
> break;
> }
> case CSR_SATP: /* CSR_SPTBR */ {
> @@ -371,7 +385,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> do_illegal:
> #endif
> default:
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + if (!debugger) {
> + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + }
> }
> }
>
> @@ -380,7 +396,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
> *
> * Adapted from Spike's processor_t::get_csr
> */
> -target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
> +target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno,
> + bool debugger)
> {
> #ifndef CONFIG_USER_ONLY
> target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
> @@ -416,13 +433,19 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
>
> switch (csrno) {
> case CSR_FFLAGS:
> - validate_mstatus_fs(env, GETPC());
> + if (!debugger) {
> + validate_mstatus_fs(env, GETPC());
> + }
> return cpu_riscv_get_fflags(env);
> case CSR_FRM:
> - validate_mstatus_fs(env, GETPC());
> + if (!debugger) {
> + validate_mstatus_fs(env, GETPC());
> + }
> return env->frm;
> case CSR_FCSR:
> - validate_mstatus_fs(env, GETPC());
> + if (!debugger) {
> + validate_mstatus_fs(env, GETPC());
> + }
> return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
> | (env->frm << FSR_RD_SHIFT);
> /* rdtime/rdtimeh is trapped and emulated by bbl in system mode */
> @@ -504,9 +527,13 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
> return env->mstatus & mask;
> }
> case CSR_SIP: {
> - qemu_mutex_lock_iothread();
> + if (!debugger) {
> + qemu_mutex_lock_iothread();
> + }
> target_ulong tmp = env->mip & env->mideleg;
> - qemu_mutex_unlock_iothread();
> + if (!debugger) {
> + qemu_mutex_unlock_iothread();
> + }
> return tmp;
> }
> case CSR_SIE:
> @@ -539,9 +566,13 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
> case CSR_MSTATUS:
> return env->mstatus;
> case CSR_MIP: {
> - qemu_mutex_lock_iothread();
> + if (!debugger) {
> + qemu_mutex_lock_iothread();
> + }
> target_ulong tmp = env->mip;
> - qemu_mutex_unlock_iothread();
> + if (!debugger) {
> + qemu_mutex_unlock_iothread();
> + }
> return tmp;
> }
> case CSR_MIE:
> @@ -601,7 +632,11 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
> #endif
> }
> /* used by e.g. MTIME read */
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + if (!debugger) {
> + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + } else {
> + return 0;
> + }
> }
>
> /*
> @@ -625,8 +660,8 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
> target_ulong csr)
> {
> validate_csr(env, csr, 1, GETPC());
> - uint64_t csr_backup = csr_read_helper(env, csr);
> - csr_write_helper(env, src, csr);
> + uint64_t csr_backup = csr_read_helper(env, csr, false);
> + csr_write_helper(env, src, csr, false);
> return csr_backup;
> }
>
> @@ -634,9 +669,9 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
> target_ulong csr, target_ulong rs1_pass)
> {
> validate_csr(env, csr, rs1_pass != 0, GETPC());
> - uint64_t csr_backup = csr_read_helper(env, csr);
> + uint64_t csr_backup = csr_read_helper(env, csr, false);
> if (rs1_pass != 0) {
> - csr_write_helper(env, src | csr_backup, csr);
> + csr_write_helper(env, src | csr_backup, csr, false);
> }
> return csr_backup;
> }
> @@ -645,9 +680,9 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> target_ulong csr, target_ulong rs1_pass)
> {
> validate_csr(env, csr, rs1_pass != 0, GETPC());
> - uint64_t csr_backup = csr_read_helper(env, csr);
> + uint64_t csr_backup = csr_read_helper(env, csr, false);
> if (rs1_pass != 0) {
> - csr_write_helper(env, (~src) & csr_backup, csr);
> + csr_write_helper(env, (~src) & csr_backup, csr, false);
> }
> return csr_backup;
> }
> @@ -674,7 +709,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
> riscv_set_mode(env, prev_priv);
> - csr_write_helper(env, mstatus, CSR_MSTATUS);
> + csr_write_helper(env, mstatus, CSR_MSTATUS, false);
>
> return retpc;
> }
> @@ -699,7 +734,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> riscv_set_mode(env, prev_priv);
> - csr_write_helper(env, mstatus, CSR_MSTATUS);
> + csr_write_helper(env, mstatus, CSR_MSTATUS, false);
>
> return retpc;
> }
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
2018-12-28 22:11 ` [Qemu-riscv] " Jim Wilson
@ 2019-01-22 21:52 ` Alistair Francis
-1 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2019-01-22 21:52 UTC (permalink / raw)
To: Jim Wilson; +Cc: qemu-devel@nongnu.org Developers, qemu-riscv
On Fri, Dec 28, 2018 at 2:20 PM Jim Wilson <jimw@sifive.com> wrote:
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>
> ---
> target/riscv/cpu.c | 9 ++++++-
> target/riscv/gdbstub.c | 73 ++++++++++++++++++++++++++++++++++++++++++++------
> 2 files changed, 73 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a025a0a..b248e3e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -305,6 +305,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> + riscv_cpu_register_gdb_regs_for_features(cs);
> +
> qemu_init_vcpu(cs);
> cpu_reset(cs);
>
> @@ -345,7 +347,12 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
> cc->gdb_read_register = riscv_cpu_gdb_read_register;
> cc->gdb_write_register = riscv_cpu_gdb_write_register;
> - cc->gdb_num_core_regs = 65;
> + cc->gdb_num_core_regs = 33;
> +#if defined(TARGET_RISCV32)
> + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> +#elif defined(TARGET_RISCV64)
> + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> +#endif
> cc->gdb_stop_before_watchpoint = true;
> cc->disas_set_info = riscv_cpu_disas_set_info;
> #ifdef CONFIG_USER_ONLY
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index b06f0fa..9558d80 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -31,10 +31,6 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
> return gdb_get_regl(mem_buf, env->gpr[n]);
> } else if (n == 32) {
> return gdb_get_regl(mem_buf, env->pc);
> - } else if (n < 65) {
> - return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
> - } else if (n < 4096 + 65) {
> - return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65, true));
> }
> return 0;
> }
> @@ -53,11 +49,72 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> } else if (n == 32) {
> env->pc = ldtul_p(mem_buf);
> return sizeof(target_ulong);
> - } else if (n < 65) {
> - env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
> + }
> + return 0;
> +}
> +
> +static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> +{
> + if (n < 32) {
> + return gdb_get_reg64(mem_buf, env->fpr[n]);
> + } else if (n < 35) {
> + /*
> + * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we
> + * subtract 31 to map the gdb FP register number to the CSR number.
> + * This also works for CSR_FRM and CSR_FCSR.
> + */
> + return gdb_get_regl(mem_buf, csr_read_helper(env, n - 31, true));
> + }
> + return 0;
> +}
> +
> +static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> +{
> + if (n < 32) {
> + env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
> return sizeof(uint64_t);
> - } else if (n < 4096 + 65) {
> - csr_write_helper(env, ldtul_p(mem_buf), n - 65, true);
> + } else if (n < 35) {
> + /*
> + * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we
> + * subtract 31 to map the gdb FP register number to the CSR number.
> + * This also works for CSR_FRM and CSR_FCSR.
> + */
> + csr_write_helper(env, ldtul_p(mem_buf), n - 31, true);
> }
> return 0;
> }
> +
> +static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
> +{
> + if (n < ARRAY_SIZE(csr_register_map)) {
> + return gdb_get_regl(mem_buf, csr_read_helper(env, csr_register_map[n],
> + true));
> + }
> + return 0;
> +}
> +
> +static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
> +{
> + if (n < ARRAY_SIZE(csr_register_map)) {
> + csr_write_helper(env, ldtul_p(mem_buf), csr_register_map[n], true);
> + }
> + return 0;
> +}
> +
> +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> +{
> + /* ??? Assume all targets have FPU regs for now. */
You can get env and then check for floating point support:
CPURISCVState *env = &cs->env;
if (env->misa_mask & RVF) {
...
Alistair
> +#if defined(TARGET_RISCV32)
> + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> + 35, "riscv-32bit-fpu.xml", 0);
> +
> + gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> + 4096, "riscv-32bit-csr.xml", 0);
> +#elif defined(TARGET_RISCV64)
> + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> + 35, "riscv-64bit-fpu.xml", 0);
> +
> + gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> + 4096, "riscv-64bit-csr.xml", 0);
> +#endif
> +}
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
@ 2019-01-22 21:52 ` Alistair Francis
0 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2019-01-22 21:52 UTC (permalink / raw)
To: Jim Wilson; +Cc: qemu-devel@nongnu.org Developers, qemu-riscv
On Fri, Dec 28, 2018 at 2:20 PM Jim Wilson <jimw@sifive.com> wrote:
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>
> ---
> target/riscv/cpu.c | 9 ++++++-
> target/riscv/gdbstub.c | 73 ++++++++++++++++++++++++++++++++++++++++++++------
> 2 files changed, 73 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a025a0a..b248e3e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -305,6 +305,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> + riscv_cpu_register_gdb_regs_for_features(cs);
> +
> qemu_init_vcpu(cs);
> cpu_reset(cs);
>
> @@ -345,7 +347,12 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
> cc->gdb_read_register = riscv_cpu_gdb_read_register;
> cc->gdb_write_register = riscv_cpu_gdb_write_register;
> - cc->gdb_num_core_regs = 65;
> + cc->gdb_num_core_regs = 33;
> +#if defined(TARGET_RISCV32)
> + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> +#elif defined(TARGET_RISCV64)
> + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> +#endif
> cc->gdb_stop_before_watchpoint = true;
> cc->disas_set_info = riscv_cpu_disas_set_info;
> #ifdef CONFIG_USER_ONLY
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index b06f0fa..9558d80 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -31,10 +31,6 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
> return gdb_get_regl(mem_buf, env->gpr[n]);
> } else if (n == 32) {
> return gdb_get_regl(mem_buf, env->pc);
> - } else if (n < 65) {
> - return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
> - } else if (n < 4096 + 65) {
> - return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65, true));
> }
> return 0;
> }
> @@ -53,11 +49,72 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> } else if (n == 32) {
> env->pc = ldtul_p(mem_buf);
> return sizeof(target_ulong);
> - } else if (n < 65) {
> - env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
> + }
> + return 0;
> +}
> +
> +static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> +{
> + if (n < 32) {
> + return gdb_get_reg64(mem_buf, env->fpr[n]);
> + } else if (n < 35) {
> + /*
> + * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we
> + * subtract 31 to map the gdb FP register number to the CSR number.
> + * This also works for CSR_FRM and CSR_FCSR.
> + */
> + return gdb_get_regl(mem_buf, csr_read_helper(env, n - 31, true));
> + }
> + return 0;
> +}
> +
> +static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> +{
> + if (n < 32) {
> + env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
> return sizeof(uint64_t);
> - } else if (n < 4096 + 65) {
> - csr_write_helper(env, ldtul_p(mem_buf), n - 65, true);
> + } else if (n < 35) {
> + /*
> + * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we
> + * subtract 31 to map the gdb FP register number to the CSR number.
> + * This also works for CSR_FRM and CSR_FCSR.
> + */
> + csr_write_helper(env, ldtul_p(mem_buf), n - 31, true);
> }
> return 0;
> }
> +
> +static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
> +{
> + if (n < ARRAY_SIZE(csr_register_map)) {
> + return gdb_get_regl(mem_buf, csr_read_helper(env, csr_register_map[n],
> + true));
> + }
> + return 0;
> +}
> +
> +static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
> +{
> + if (n < ARRAY_SIZE(csr_register_map)) {
> + csr_write_helper(env, ldtul_p(mem_buf), csr_register_map[n], true);
> + }
> + return 0;
> +}
> +
> +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> +{
> + /* ??? Assume all targets have FPU regs for now. */
You can get env and then check for floating point support:
CPURISCVState *env = &cs->env;
if (env->misa_mask & RVF) {
...
Alistair
> +#if defined(TARGET_RISCV32)
> + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> + 35, "riscv-32bit-fpu.xml", 0);
> +
> + gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> + 4096, "riscv-32bit-csr.xml", 0);
> +#elif defined(TARGET_RISCV64)
> + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> + 35, "riscv-64bit-fpu.xml", 0);
> +
> + gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> + 4096, "riscv-64bit-csr.xml", 0);
> +#endif
> +}
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files.
2018-12-28 22:07 ` [Qemu-riscv] " Jim Wilson
@ 2019-01-22 21:53 ` Alistair Francis
-1 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2019-01-22 21:53 UTC (permalink / raw)
To: Jim Wilson; +Cc: qemu-devel@nongnu.org Developers, qemu-riscv
On Fri, Dec 28, 2018 at 2:24 PM Jim Wilson <jimw@sifive.com> wrote:
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> configure | 1 +
> gdb-xml/riscv-32bit-cpu.xml | 43 ++++++++
> gdb-xml/riscv-32bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++
> gdb-xml/riscv-32bit-fpu.xml | 46 ++++++++
> 4 files changed, 340 insertions(+)
> create mode 100644 gdb-xml/riscv-32bit-cpu.xml
> create mode 100644 gdb-xml/riscv-32bit-csr.xml
> create mode 100644 gdb-xml/riscv-32bit-fpu.xml
>
> diff --git a/configure b/configure
> index 224d307..4e05eed 100755
> --- a/configure
> +++ b/configure
> @@ -7208,6 +7208,7 @@ case "$target_name" in
> TARGET_BASE_ARCH=riscv
> TARGET_ABI_DIR=riscv
> mttcg=yes
> + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml"
> target_compiler=$cross_cc_riscv32
> ;;
> riscv64)
> diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
> new file mode 100644
> index 0000000..c02f86c
> --- /dev/null
> +++ b/gdb-xml/riscv-32bit-cpu.xml
> @@ -0,0 +1,43 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2018 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.riscv.cpu">
> + <reg name="zero" bitsize="32" type="int"/>
> + <reg name="ra" bitsize="32" type="code_ptr"/>
> + <reg name="sp" bitsize="32" type="data_ptr"/>
> + <reg name="gp" bitsize="32" type="data_ptr"/>
> + <reg name="tp" bitsize="32" type="data_ptr"/>
> + <reg name="t0" bitsize="32" type="int"/>
> + <reg name="t1" bitsize="32" type="int"/>
> + <reg name="t2" bitsize="32" type="int"/>
> + <reg name="fp" bitsize="32" type="data_ptr"/>
> + <reg name="s1" bitsize="32" type="int"/>
> + <reg name="a0" bitsize="32" type="int"/>
> + <reg name="a1" bitsize="32" type="int"/>
> + <reg name="a2" bitsize="32" type="int"/>
> + <reg name="a3" bitsize="32" type="int"/>
> + <reg name="a4" bitsize="32" type="int"/>
> + <reg name="a5" bitsize="32" type="int"/>
> + <reg name="a6" bitsize="32" type="int"/>
> + <reg name="a7" bitsize="32" type="int"/>
> + <reg name="s2" bitsize="32" type="int"/>
> + <reg name="s3" bitsize="32" type="int"/>
> + <reg name="s4" bitsize="32" type="int"/>
> + <reg name="s5" bitsize="32" type="int"/>
> + <reg name="s6" bitsize="32" type="int"/>
> + <reg name="s7" bitsize="32" type="int"/>
> + <reg name="s8" bitsize="32" type="int"/>
> + <reg name="s9" bitsize="32" type="int"/>
> + <reg name="s10" bitsize="32" type="int"/>
> + <reg name="s11" bitsize="32" type="int"/>
> + <reg name="t3" bitsize="32" type="int"/>
> + <reg name="t4" bitsize="32" type="int"/>
> + <reg name="t5" bitsize="32" type="int"/>
> + <reg name="t6" bitsize="32" type="int"/>
> + <reg name="pc" bitsize="32" type="code_ptr"/>
> +</feature>
> diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
> new file mode 100644
> index 0000000..4aea9e6
> --- /dev/null
> +++ b/gdb-xml/riscv-32bit-csr.xml
> @@ -0,0 +1,250 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2018 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.riscv.csr">
> + <reg name="ustatus" bitsize="32"/>
> + <reg name="uie" bitsize="32"/>
> + <reg name="utvec" bitsize="32"/>
> + <reg name="uscratch" bitsize="32"/>
> + <reg name="uepc" bitsize="32"/>
> + <reg name="ucause" bitsize="32"/>
> + <reg name="utval" bitsize="32"/>
> + <reg name="uip" bitsize="32"/>
> + <reg name="fflags" bitsize="32"/>
> + <reg name="frm" bitsize="32"/>
> + <reg name="fcsr" bitsize="32"/>
> + <reg name="cycle" bitsize="32"/>
> + <reg name="time" bitsize="32"/>
> + <reg name="instret" bitsize="32"/>
> + <reg name="hpmcounter3" bitsize="32"/>
> + <reg name="hpmcounter4" bitsize="32"/>
> + <reg name="hpmcounter5" bitsize="32"/>
> + <reg name="hpmcounter6" bitsize="32"/>
> + <reg name="hpmcounter7" bitsize="32"/>
> + <reg name="hpmcounter8" bitsize="32"/>
> + <reg name="hpmcounter9" bitsize="32"/>
> + <reg name="hpmcounter10" bitsize="32"/>
> + <reg name="hpmcounter11" bitsize="32"/>
> + <reg name="hpmcounter12" bitsize="32"/>
> + <reg name="hpmcounter13" bitsize="32"/>
> + <reg name="hpmcounter14" bitsize="32"/>
> + <reg name="hpmcounter15" bitsize="32"/>
> + <reg name="hpmcounter16" bitsize="32"/>
> + <reg name="hpmcounter17" bitsize="32"/>
> + <reg name="hpmcounter18" bitsize="32"/>
> + <reg name="hpmcounter19" bitsize="32"/>
> + <reg name="hpmcounter20" bitsize="32"/>
> + <reg name="hpmcounter21" bitsize="32"/>
> + <reg name="hpmcounter22" bitsize="32"/>
> + <reg name="hpmcounter23" bitsize="32"/>
> + <reg name="hpmcounter24" bitsize="32"/>
> + <reg name="hpmcounter25" bitsize="32"/>
> + <reg name="hpmcounter26" bitsize="32"/>
> + <reg name="hpmcounter27" bitsize="32"/>
> + <reg name="hpmcounter28" bitsize="32"/>
> + <reg name="hpmcounter29" bitsize="32"/>
> + <reg name="hpmcounter30" bitsize="32"/>
> + <reg name="hpmcounter31" bitsize="32"/>
> + <reg name="cycleh" bitsize="32"/>
> + <reg name="timeh" bitsize="32"/>
> + <reg name="instreth" bitsize="32"/>
> + <reg name="hpmcounter3h" bitsize="32"/>
> + <reg name="hpmcounter4h" bitsize="32"/>
> + <reg name="hpmcounter5h" bitsize="32"/>
> + <reg name="hpmcounter6h" bitsize="32"/>
> + <reg name="hpmcounter7h" bitsize="32"/>
> + <reg name="hpmcounter8h" bitsize="32"/>
> + <reg name="hpmcounter9h" bitsize="32"/>
> + <reg name="hpmcounter10h" bitsize="32"/>
> + <reg name="hpmcounter11h" bitsize="32"/>
> + <reg name="hpmcounter12h" bitsize="32"/>
> + <reg name="hpmcounter13h" bitsize="32"/>
> + <reg name="hpmcounter14h" bitsize="32"/>
> + <reg name="hpmcounter15h" bitsize="32"/>
> + <reg name="hpmcounter16h" bitsize="32"/>
> + <reg name="hpmcounter17h" bitsize="32"/>
> + <reg name="hpmcounter18h" bitsize="32"/>
> + <reg name="hpmcounter19h" bitsize="32"/>
> + <reg name="hpmcounter20h" bitsize="32"/>
> + <reg name="hpmcounter21h" bitsize="32"/>
> + <reg name="hpmcounter22h" bitsize="32"/>
> + <reg name="hpmcounter23h" bitsize="32"/>
> + <reg name="hpmcounter24h" bitsize="32"/>
> + <reg name="hpmcounter25h" bitsize="32"/>
> + <reg name="hpmcounter26h" bitsize="32"/>
> + <reg name="hpmcounter27h" bitsize="32"/>
> + <reg name="hpmcounter28h" bitsize="32"/>
> + <reg name="hpmcounter29h" bitsize="32"/>
> + <reg name="hpmcounter30h" bitsize="32"/>
> + <reg name="hpmcounter31h" bitsize="32"/>
> + <reg name="sstatus" bitsize="32"/>
> + <reg name="sedeleg" bitsize="32"/>
> + <reg name="sideleg" bitsize="32"/>
> + <reg name="sie" bitsize="32"/>
> + <reg name="stvec" bitsize="32"/>
> + <reg name="scounteren" bitsize="32"/>
> + <reg name="sscratch" bitsize="32"/>
> + <reg name="sepc" bitsize="32"/>
> + <reg name="scause" bitsize="32"/>
> + <reg name="stval" bitsize="32"/>
> + <reg name="sip" bitsize="32"/>
> + <reg name="satp" bitsize="32"/>
> + <reg name="mvendorid" bitsize="32"/>
> + <reg name="marchid" bitsize="32"/>
> + <reg name="mimpid" bitsize="32"/>
> + <reg name="mhartid" bitsize="32"/>
> + <reg name="mstatus" bitsize="32"/>
> + <reg name="misa" bitsize="32"/>
> + <reg name="medeleg" bitsize="32"/>
> + <reg name="mideleg" bitsize="32"/>
> + <reg name="mie" bitsize="32"/>
> + <reg name="mtvec" bitsize="32"/>
> + <reg name="mcounteren" bitsize="32"/>
> + <reg name="mscratch" bitsize="32"/>
> + <reg name="mepc" bitsize="32"/>
> + <reg name="mcause" bitsize="32"/>
> + <reg name="mtval" bitsize="32"/>
> + <reg name="mip" bitsize="32"/>
> + <reg name="pmpcfg0" bitsize="32"/>
> + <reg name="pmpcfg1" bitsize="32"/>
> + <reg name="pmpcfg2" bitsize="32"/>
> + <reg name="pmpcfg3" bitsize="32"/>
> + <reg name="pmpaddr0" bitsize="32"/>
> + <reg name="pmpaddr1" bitsize="32"/>
> + <reg name="pmpaddr2" bitsize="32"/>
> + <reg name="pmpaddr3" bitsize="32"/>
> + <reg name="pmpaddr4" bitsize="32"/>
> + <reg name="pmpaddr5" bitsize="32"/>
> + <reg name="pmpaddr6" bitsize="32"/>
> + <reg name="pmpaddr7" bitsize="32"/>
> + <reg name="pmpaddr8" bitsize="32"/>
> + <reg name="pmpaddr9" bitsize="32"/>
> + <reg name="pmpaddr10" bitsize="32"/>
> + <reg name="pmpaddr11" bitsize="32"/>
> + <reg name="pmpaddr12" bitsize="32"/>
> + <reg name="pmpaddr13" bitsize="32"/>
> + <reg name="pmpaddr14" bitsize="32"/>
> + <reg name="pmpaddr15" bitsize="32"/>
> + <reg name="mcycle" bitsize="32"/>
> + <reg name="minstret" bitsize="32"/>
> + <reg name="mhpmcounter3" bitsize="32"/>
> + <reg name="mhpmcounter4" bitsize="32"/>
> + <reg name="mhpmcounter5" bitsize="32"/>
> + <reg name="mhpmcounter6" bitsize="32"/>
> + <reg name="mhpmcounter7" bitsize="32"/>
> + <reg name="mhpmcounter8" bitsize="32"/>
> + <reg name="mhpmcounter9" bitsize="32"/>
> + <reg name="mhpmcounter10" bitsize="32"/>
> + <reg name="mhpmcounter11" bitsize="32"/>
> + <reg name="mhpmcounter12" bitsize="32"/>
> + <reg name="mhpmcounter13" bitsize="32"/>
> + <reg name="mhpmcounter14" bitsize="32"/>
> + <reg name="mhpmcounter15" bitsize="32"/>
> + <reg name="mhpmcounter16" bitsize="32"/>
> + <reg name="mhpmcounter17" bitsize="32"/>
> + <reg name="mhpmcounter18" bitsize="32"/>
> + <reg name="mhpmcounter19" bitsize="32"/>
> + <reg name="mhpmcounter20" bitsize="32"/>
> + <reg name="mhpmcounter21" bitsize="32"/>
> + <reg name="mhpmcounter22" bitsize="32"/>
> + <reg name="mhpmcounter23" bitsize="32"/>
> + <reg name="mhpmcounter24" bitsize="32"/>
> + <reg name="mhpmcounter25" bitsize="32"/>
> + <reg name="mhpmcounter26" bitsize="32"/>
> + <reg name="mhpmcounter27" bitsize="32"/>
> + <reg name="mhpmcounter28" bitsize="32"/>
> + <reg name="mhpmcounter29" bitsize="32"/>
> + <reg name="mhpmcounter30" bitsize="32"/>
> + <reg name="mhpmcounter31" bitsize="32"/>
> + <reg name="mcycleh" bitsize="32"/>
> + <reg name="minstreth" bitsize="32"/>
> + <reg name="mhpmcounter3h" bitsize="32"/>
> + <reg name="mhpmcounter4h" bitsize="32"/>
> + <reg name="mhpmcounter5h" bitsize="32"/>
> + <reg name="mhpmcounter6h" bitsize="32"/>
> + <reg name="mhpmcounter7h" bitsize="32"/>
> + <reg name="mhpmcounter8h" bitsize="32"/>
> + <reg name="mhpmcounter9h" bitsize="32"/>
> + <reg name="mhpmcounter10h" bitsize="32"/>
> + <reg name="mhpmcounter11h" bitsize="32"/>
> + <reg name="mhpmcounter12h" bitsize="32"/>
> + <reg name="mhpmcounter13h" bitsize="32"/>
> + <reg name="mhpmcounter14h" bitsize="32"/>
> + <reg name="mhpmcounter15h" bitsize="32"/>
> + <reg name="mhpmcounter16h" bitsize="32"/>
> + <reg name="mhpmcounter17h" bitsize="32"/>
> + <reg name="mhpmcounter18h" bitsize="32"/>
> + <reg name="mhpmcounter19h" bitsize="32"/>
> + <reg name="mhpmcounter20h" bitsize="32"/>
> + <reg name="mhpmcounter21h" bitsize="32"/>
> + <reg name="mhpmcounter22h" bitsize="32"/>
> + <reg name="mhpmcounter23h" bitsize="32"/>
> + <reg name="mhpmcounter24h" bitsize="32"/>
> + <reg name="mhpmcounter25h" bitsize="32"/>
> + <reg name="mhpmcounter26h" bitsize="32"/>
> + <reg name="mhpmcounter27h" bitsize="32"/>
> + <reg name="mhpmcounter28h" bitsize="32"/>
> + <reg name="mhpmcounter29h" bitsize="32"/>
> + <reg name="mhpmcounter30h" bitsize="32"/>
> + <reg name="mhpmcounter31h" bitsize="32"/>
> + <reg name="mhpmevent3" bitsize="32"/>
> + <reg name="mhpmevent4" bitsize="32"/>
> + <reg name="mhpmevent5" bitsize="32"/>
> + <reg name="mhpmevent6" bitsize="32"/>
> + <reg name="mhpmevent7" bitsize="32"/>
> + <reg name="mhpmevent8" bitsize="32"/>
> + <reg name="mhpmevent9" bitsize="32"/>
> + <reg name="mhpmevent10" bitsize="32"/>
> + <reg name="mhpmevent11" bitsize="32"/>
> + <reg name="mhpmevent12" bitsize="32"/>
> + <reg name="mhpmevent13" bitsize="32"/>
> + <reg name="mhpmevent14" bitsize="32"/>
> + <reg name="mhpmevent15" bitsize="32"/>
> + <reg name="mhpmevent16" bitsize="32"/>
> + <reg name="mhpmevent17" bitsize="32"/>
> + <reg name="mhpmevent18" bitsize="32"/>
> + <reg name="mhpmevent19" bitsize="32"/>
> + <reg name="mhpmevent20" bitsize="32"/>
> + <reg name="mhpmevent21" bitsize="32"/>
> + <reg name="mhpmevent22" bitsize="32"/>
> + <reg name="mhpmevent23" bitsize="32"/>
> + <reg name="mhpmevent24" bitsize="32"/>
> + <reg name="mhpmevent25" bitsize="32"/>
> + <reg name="mhpmevent26" bitsize="32"/>
> + <reg name="mhpmevent27" bitsize="32"/>
> + <reg name="mhpmevent28" bitsize="32"/>
> + <reg name="mhpmevent29" bitsize="32"/>
> + <reg name="mhpmevent30" bitsize="32"/>
> + <reg name="mhpmevent31" bitsize="32"/>
> + <reg name="tselect" bitsize="32"/>
> + <reg name="tdata1" bitsize="32"/>
> + <reg name="tdata2" bitsize="32"/>
> + <reg name="tdata3" bitsize="32"/>
> + <reg name="dcsr" bitsize="32"/>
> + <reg name="dpc" bitsize="32"/>
> + <reg name="dscratch" bitsize="32"/>
> + <reg name="hstatus" bitsize="32"/>
> + <reg name="hedeleg" bitsize="32"/>
> + <reg name="hideleg" bitsize="32"/>
> + <reg name="hie" bitsize="32"/>
> + <reg name="htvec" bitsize="32"/>
> + <reg name="hscratch" bitsize="32"/>
> + <reg name="hepc" bitsize="32"/>
> + <reg name="hcause" bitsize="32"/>
> + <reg name="hbadaddr" bitsize="32"/>
> + <reg name="hip" bitsize="32"/>
> + <reg name="mbase" bitsize="32"/>
> + <reg name="mbound" bitsize="32"/>
> + <reg name="mibase" bitsize="32"/>
> + <reg name="mibound" bitsize="32"/>
> + <reg name="mdbase" bitsize="32"/>
> + <reg name="mdbound" bitsize="32"/>
> + <reg name="mucounteren" bitsize="32"/>
> + <reg name="mscounteren" bitsize="32"/>
> + <reg name="mhcounteren" bitsize="32"/>
> +</feature>
> diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml
> new file mode 100644
> index 0000000..783287d
> --- /dev/null
> +++ b/gdb-xml/riscv-32bit-fpu.xml
> @@ -0,0 +1,46 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2018 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.riscv.fpu">
> + <reg name="ft0" bitsize="32" type="ieee_single"/>
> + <reg name="ft1" bitsize="32" type="ieee_single"/>
> + <reg name="ft2" bitsize="32" type="ieee_single"/>
> + <reg name="ft3" bitsize="32" type="ieee_single"/>
> + <reg name="ft4" bitsize="32" type="ieee_single"/>
> + <reg name="ft5" bitsize="32" type="ieee_single"/>
> + <reg name="ft6" bitsize="32" type="ieee_single"/>
> + <reg name="ft7" bitsize="32" type="ieee_single"/>
> + <reg name="fs0" bitsize="32" type="ieee_single"/>
> + <reg name="fs1" bitsize="32" type="ieee_single"/>
> + <reg name="fa0" bitsize="32" type="ieee_single"/>
> + <reg name="fa1" bitsize="32" type="ieee_single"/>
> + <reg name="fa2" bitsize="32" type="ieee_single"/>
> + <reg name="fa3" bitsize="32" type="ieee_single"/>
> + <reg name="fa4" bitsize="32" type="ieee_single"/>
> + <reg name="fa5" bitsize="32" type="ieee_single"/>
> + <reg name="fa6" bitsize="32" type="ieee_single"/>
> + <reg name="fa7" bitsize="32" type="ieee_single"/>
> + <reg name="fs2" bitsize="32" type="ieee_single"/>
> + <reg name="fs3" bitsize="32" type="ieee_single"/>
> + <reg name="fs4" bitsize="32" type="ieee_single"/>
> + <reg name="fs5" bitsize="32" type="ieee_single"/>
> + <reg name="fs6" bitsize="32" type="ieee_single"/>
> + <reg name="fs7" bitsize="32" type="ieee_single"/>
> + <reg name="fs8" bitsize="32" type="ieee_single"/>
> + <reg name="fs9" bitsize="32" type="ieee_single"/>
> + <reg name="fs10" bitsize="32" type="ieee_single"/>
> + <reg name="fs11" bitsize="32" type="ieee_single"/>
> + <reg name="ft8" bitsize="32" type="ieee_single"/>
> + <reg name="ft9" bitsize="32" type="ieee_single"/>
> + <reg name="ft10" bitsize="32" type="ieee_single"/>
> + <reg name="ft11" bitsize="32" type="ieee_single"/>
> +
> + <reg name="fflags" bitsize="32" type="int"/>
> + <reg name="frm" bitsize="32" type="int"/>
> + <reg name="fcsr" bitsize="32" type="int"/>
> +</feature>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files.
@ 2019-01-22 21:53 ` Alistair Francis
0 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2019-01-22 21:53 UTC (permalink / raw)
To: Jim Wilson; +Cc: qemu-devel@nongnu.org Developers, qemu-riscv
On Fri, Dec 28, 2018 at 2:24 PM Jim Wilson <jimw@sifive.com> wrote:
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> configure | 1 +
> gdb-xml/riscv-32bit-cpu.xml | 43 ++++++++
> gdb-xml/riscv-32bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++
> gdb-xml/riscv-32bit-fpu.xml | 46 ++++++++
> 4 files changed, 340 insertions(+)
> create mode 100644 gdb-xml/riscv-32bit-cpu.xml
> create mode 100644 gdb-xml/riscv-32bit-csr.xml
> create mode 100644 gdb-xml/riscv-32bit-fpu.xml
>
> diff --git a/configure b/configure
> index 224d307..4e05eed 100755
> --- a/configure
> +++ b/configure
> @@ -7208,6 +7208,7 @@ case "$target_name" in
> TARGET_BASE_ARCH=riscv
> TARGET_ABI_DIR=riscv
> mttcg=yes
> + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml"
> target_compiler=$cross_cc_riscv32
> ;;
> riscv64)
> diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
> new file mode 100644
> index 0000000..c02f86c
> --- /dev/null
> +++ b/gdb-xml/riscv-32bit-cpu.xml
> @@ -0,0 +1,43 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2018 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.riscv.cpu">
> + <reg name="zero" bitsize="32" type="int"/>
> + <reg name="ra" bitsize="32" type="code_ptr"/>
> + <reg name="sp" bitsize="32" type="data_ptr"/>
> + <reg name="gp" bitsize="32" type="data_ptr"/>
> + <reg name="tp" bitsize="32" type="data_ptr"/>
> + <reg name="t0" bitsize="32" type="int"/>
> + <reg name="t1" bitsize="32" type="int"/>
> + <reg name="t2" bitsize="32" type="int"/>
> + <reg name="fp" bitsize="32" type="data_ptr"/>
> + <reg name="s1" bitsize="32" type="int"/>
> + <reg name="a0" bitsize="32" type="int"/>
> + <reg name="a1" bitsize="32" type="int"/>
> + <reg name="a2" bitsize="32" type="int"/>
> + <reg name="a3" bitsize="32" type="int"/>
> + <reg name="a4" bitsize="32" type="int"/>
> + <reg name="a5" bitsize="32" type="int"/>
> + <reg name="a6" bitsize="32" type="int"/>
> + <reg name="a7" bitsize="32" type="int"/>
> + <reg name="s2" bitsize="32" type="int"/>
> + <reg name="s3" bitsize="32" type="int"/>
> + <reg name="s4" bitsize="32" type="int"/>
> + <reg name="s5" bitsize="32" type="int"/>
> + <reg name="s6" bitsize="32" type="int"/>
> + <reg name="s7" bitsize="32" type="int"/>
> + <reg name="s8" bitsize="32" type="int"/>
> + <reg name="s9" bitsize="32" type="int"/>
> + <reg name="s10" bitsize="32" type="int"/>
> + <reg name="s11" bitsize="32" type="int"/>
> + <reg name="t3" bitsize="32" type="int"/>
> + <reg name="t4" bitsize="32" type="int"/>
> + <reg name="t5" bitsize="32" type="int"/>
> + <reg name="t6" bitsize="32" type="int"/>
> + <reg name="pc" bitsize="32" type="code_ptr"/>
> +</feature>
> diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
> new file mode 100644
> index 0000000..4aea9e6
> --- /dev/null
> +++ b/gdb-xml/riscv-32bit-csr.xml
> @@ -0,0 +1,250 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2018 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.riscv.csr">
> + <reg name="ustatus" bitsize="32"/>
> + <reg name="uie" bitsize="32"/>
> + <reg name="utvec" bitsize="32"/>
> + <reg name="uscratch" bitsize="32"/>
> + <reg name="uepc" bitsize="32"/>
> + <reg name="ucause" bitsize="32"/>
> + <reg name="utval" bitsize="32"/>
> + <reg name="uip" bitsize="32"/>
> + <reg name="fflags" bitsize="32"/>
> + <reg name="frm" bitsize="32"/>
> + <reg name="fcsr" bitsize="32"/>
> + <reg name="cycle" bitsize="32"/>
> + <reg name="time" bitsize="32"/>
> + <reg name="instret" bitsize="32"/>
> + <reg name="hpmcounter3" bitsize="32"/>
> + <reg name="hpmcounter4" bitsize="32"/>
> + <reg name="hpmcounter5" bitsize="32"/>
> + <reg name="hpmcounter6" bitsize="32"/>
> + <reg name="hpmcounter7" bitsize="32"/>
> + <reg name="hpmcounter8" bitsize="32"/>
> + <reg name="hpmcounter9" bitsize="32"/>
> + <reg name="hpmcounter10" bitsize="32"/>
> + <reg name="hpmcounter11" bitsize="32"/>
> + <reg name="hpmcounter12" bitsize="32"/>
> + <reg name="hpmcounter13" bitsize="32"/>
> + <reg name="hpmcounter14" bitsize="32"/>
> + <reg name="hpmcounter15" bitsize="32"/>
> + <reg name="hpmcounter16" bitsize="32"/>
> + <reg name="hpmcounter17" bitsize="32"/>
> + <reg name="hpmcounter18" bitsize="32"/>
> + <reg name="hpmcounter19" bitsize="32"/>
> + <reg name="hpmcounter20" bitsize="32"/>
> + <reg name="hpmcounter21" bitsize="32"/>
> + <reg name="hpmcounter22" bitsize="32"/>
> + <reg name="hpmcounter23" bitsize="32"/>
> + <reg name="hpmcounter24" bitsize="32"/>
> + <reg name="hpmcounter25" bitsize="32"/>
> + <reg name="hpmcounter26" bitsize="32"/>
> + <reg name="hpmcounter27" bitsize="32"/>
> + <reg name="hpmcounter28" bitsize="32"/>
> + <reg name="hpmcounter29" bitsize="32"/>
> + <reg name="hpmcounter30" bitsize="32"/>
> + <reg name="hpmcounter31" bitsize="32"/>
> + <reg name="cycleh" bitsize="32"/>
> + <reg name="timeh" bitsize="32"/>
> + <reg name="instreth" bitsize="32"/>
> + <reg name="hpmcounter3h" bitsize="32"/>
> + <reg name="hpmcounter4h" bitsize="32"/>
> + <reg name="hpmcounter5h" bitsize="32"/>
> + <reg name="hpmcounter6h" bitsize="32"/>
> + <reg name="hpmcounter7h" bitsize="32"/>
> + <reg name="hpmcounter8h" bitsize="32"/>
> + <reg name="hpmcounter9h" bitsize="32"/>
> + <reg name="hpmcounter10h" bitsize="32"/>
> + <reg name="hpmcounter11h" bitsize="32"/>
> + <reg name="hpmcounter12h" bitsize="32"/>
> + <reg name="hpmcounter13h" bitsize="32"/>
> + <reg name="hpmcounter14h" bitsize="32"/>
> + <reg name="hpmcounter15h" bitsize="32"/>
> + <reg name="hpmcounter16h" bitsize="32"/>
> + <reg name="hpmcounter17h" bitsize="32"/>
> + <reg name="hpmcounter18h" bitsize="32"/>
> + <reg name="hpmcounter19h" bitsize="32"/>
> + <reg name="hpmcounter20h" bitsize="32"/>
> + <reg name="hpmcounter21h" bitsize="32"/>
> + <reg name="hpmcounter22h" bitsize="32"/>
> + <reg name="hpmcounter23h" bitsize="32"/>
> + <reg name="hpmcounter24h" bitsize="32"/>
> + <reg name="hpmcounter25h" bitsize="32"/>
> + <reg name="hpmcounter26h" bitsize="32"/>
> + <reg name="hpmcounter27h" bitsize="32"/>
> + <reg name="hpmcounter28h" bitsize="32"/>
> + <reg name="hpmcounter29h" bitsize="32"/>
> + <reg name="hpmcounter30h" bitsize="32"/>
> + <reg name="hpmcounter31h" bitsize="32"/>
> + <reg name="sstatus" bitsize="32"/>
> + <reg name="sedeleg" bitsize="32"/>
> + <reg name="sideleg" bitsize="32"/>
> + <reg name="sie" bitsize="32"/>
> + <reg name="stvec" bitsize="32"/>
> + <reg name="scounteren" bitsize="32"/>
> + <reg name="sscratch" bitsize="32"/>
> + <reg name="sepc" bitsize="32"/>
> + <reg name="scause" bitsize="32"/>
> + <reg name="stval" bitsize="32"/>
> + <reg name="sip" bitsize="32"/>
> + <reg name="satp" bitsize="32"/>
> + <reg name="mvendorid" bitsize="32"/>
> + <reg name="marchid" bitsize="32"/>
> + <reg name="mimpid" bitsize="32"/>
> + <reg name="mhartid" bitsize="32"/>
> + <reg name="mstatus" bitsize="32"/>
> + <reg name="misa" bitsize="32"/>
> + <reg name="medeleg" bitsize="32"/>
> + <reg name="mideleg" bitsize="32"/>
> + <reg name="mie" bitsize="32"/>
> + <reg name="mtvec" bitsize="32"/>
> + <reg name="mcounteren" bitsize="32"/>
> + <reg name="mscratch" bitsize="32"/>
> + <reg name="mepc" bitsize="32"/>
> + <reg name="mcause" bitsize="32"/>
> + <reg name="mtval" bitsize="32"/>
> + <reg name="mip" bitsize="32"/>
> + <reg name="pmpcfg0" bitsize="32"/>
> + <reg name="pmpcfg1" bitsize="32"/>
> + <reg name="pmpcfg2" bitsize="32"/>
> + <reg name="pmpcfg3" bitsize="32"/>
> + <reg name="pmpaddr0" bitsize="32"/>
> + <reg name="pmpaddr1" bitsize="32"/>
> + <reg name="pmpaddr2" bitsize="32"/>
> + <reg name="pmpaddr3" bitsize="32"/>
> + <reg name="pmpaddr4" bitsize="32"/>
> + <reg name="pmpaddr5" bitsize="32"/>
> + <reg name="pmpaddr6" bitsize="32"/>
> + <reg name="pmpaddr7" bitsize="32"/>
> + <reg name="pmpaddr8" bitsize="32"/>
> + <reg name="pmpaddr9" bitsize="32"/>
> + <reg name="pmpaddr10" bitsize="32"/>
> + <reg name="pmpaddr11" bitsize="32"/>
> + <reg name="pmpaddr12" bitsize="32"/>
> + <reg name="pmpaddr13" bitsize="32"/>
> + <reg name="pmpaddr14" bitsize="32"/>
> + <reg name="pmpaddr15" bitsize="32"/>
> + <reg name="mcycle" bitsize="32"/>
> + <reg name="minstret" bitsize="32"/>
> + <reg name="mhpmcounter3" bitsize="32"/>
> + <reg name="mhpmcounter4" bitsize="32"/>
> + <reg name="mhpmcounter5" bitsize="32"/>
> + <reg name="mhpmcounter6" bitsize="32"/>
> + <reg name="mhpmcounter7" bitsize="32"/>
> + <reg name="mhpmcounter8" bitsize="32"/>
> + <reg name="mhpmcounter9" bitsize="32"/>
> + <reg name="mhpmcounter10" bitsize="32"/>
> + <reg name="mhpmcounter11" bitsize="32"/>
> + <reg name="mhpmcounter12" bitsize="32"/>
> + <reg name="mhpmcounter13" bitsize="32"/>
> + <reg name="mhpmcounter14" bitsize="32"/>
> + <reg name="mhpmcounter15" bitsize="32"/>
> + <reg name="mhpmcounter16" bitsize="32"/>
> + <reg name="mhpmcounter17" bitsize="32"/>
> + <reg name="mhpmcounter18" bitsize="32"/>
> + <reg name="mhpmcounter19" bitsize="32"/>
> + <reg name="mhpmcounter20" bitsize="32"/>
> + <reg name="mhpmcounter21" bitsize="32"/>
> + <reg name="mhpmcounter22" bitsize="32"/>
> + <reg name="mhpmcounter23" bitsize="32"/>
> + <reg name="mhpmcounter24" bitsize="32"/>
> + <reg name="mhpmcounter25" bitsize="32"/>
> + <reg name="mhpmcounter26" bitsize="32"/>
> + <reg name="mhpmcounter27" bitsize="32"/>
> + <reg name="mhpmcounter28" bitsize="32"/>
> + <reg name="mhpmcounter29" bitsize="32"/>
> + <reg name="mhpmcounter30" bitsize="32"/>
> + <reg name="mhpmcounter31" bitsize="32"/>
> + <reg name="mcycleh" bitsize="32"/>
> + <reg name="minstreth" bitsize="32"/>
> + <reg name="mhpmcounter3h" bitsize="32"/>
> + <reg name="mhpmcounter4h" bitsize="32"/>
> + <reg name="mhpmcounter5h" bitsize="32"/>
> + <reg name="mhpmcounter6h" bitsize="32"/>
> + <reg name="mhpmcounter7h" bitsize="32"/>
> + <reg name="mhpmcounter8h" bitsize="32"/>
> + <reg name="mhpmcounter9h" bitsize="32"/>
> + <reg name="mhpmcounter10h" bitsize="32"/>
> + <reg name="mhpmcounter11h" bitsize="32"/>
> + <reg name="mhpmcounter12h" bitsize="32"/>
> + <reg name="mhpmcounter13h" bitsize="32"/>
> + <reg name="mhpmcounter14h" bitsize="32"/>
> + <reg name="mhpmcounter15h" bitsize="32"/>
> + <reg name="mhpmcounter16h" bitsize="32"/>
> + <reg name="mhpmcounter17h" bitsize="32"/>
> + <reg name="mhpmcounter18h" bitsize="32"/>
> + <reg name="mhpmcounter19h" bitsize="32"/>
> + <reg name="mhpmcounter20h" bitsize="32"/>
> + <reg name="mhpmcounter21h" bitsize="32"/>
> + <reg name="mhpmcounter22h" bitsize="32"/>
> + <reg name="mhpmcounter23h" bitsize="32"/>
> + <reg name="mhpmcounter24h" bitsize="32"/>
> + <reg name="mhpmcounter25h" bitsize="32"/>
> + <reg name="mhpmcounter26h" bitsize="32"/>
> + <reg name="mhpmcounter27h" bitsize="32"/>
> + <reg name="mhpmcounter28h" bitsize="32"/>
> + <reg name="mhpmcounter29h" bitsize="32"/>
> + <reg name="mhpmcounter30h" bitsize="32"/>
> + <reg name="mhpmcounter31h" bitsize="32"/>
> + <reg name="mhpmevent3" bitsize="32"/>
> + <reg name="mhpmevent4" bitsize="32"/>
> + <reg name="mhpmevent5" bitsize="32"/>
> + <reg name="mhpmevent6" bitsize="32"/>
> + <reg name="mhpmevent7" bitsize="32"/>
> + <reg name="mhpmevent8" bitsize="32"/>
> + <reg name="mhpmevent9" bitsize="32"/>
> + <reg name="mhpmevent10" bitsize="32"/>
> + <reg name="mhpmevent11" bitsize="32"/>
> + <reg name="mhpmevent12" bitsize="32"/>
> + <reg name="mhpmevent13" bitsize="32"/>
> + <reg name="mhpmevent14" bitsize="32"/>
> + <reg name="mhpmevent15" bitsize="32"/>
> + <reg name="mhpmevent16" bitsize="32"/>
> + <reg name="mhpmevent17" bitsize="32"/>
> + <reg name="mhpmevent18" bitsize="32"/>
> + <reg name="mhpmevent19" bitsize="32"/>
> + <reg name="mhpmevent20" bitsize="32"/>
> + <reg name="mhpmevent21" bitsize="32"/>
> + <reg name="mhpmevent22" bitsize="32"/>
> + <reg name="mhpmevent23" bitsize="32"/>
> + <reg name="mhpmevent24" bitsize="32"/>
> + <reg name="mhpmevent25" bitsize="32"/>
> + <reg name="mhpmevent26" bitsize="32"/>
> + <reg name="mhpmevent27" bitsize="32"/>
> + <reg name="mhpmevent28" bitsize="32"/>
> + <reg name="mhpmevent29" bitsize="32"/>
> + <reg name="mhpmevent30" bitsize="32"/>
> + <reg name="mhpmevent31" bitsize="32"/>
> + <reg name="tselect" bitsize="32"/>
> + <reg name="tdata1" bitsize="32"/>
> + <reg name="tdata2" bitsize="32"/>
> + <reg name="tdata3" bitsize="32"/>
> + <reg name="dcsr" bitsize="32"/>
> + <reg name="dpc" bitsize="32"/>
> + <reg name="dscratch" bitsize="32"/>
> + <reg name="hstatus" bitsize="32"/>
> + <reg name="hedeleg" bitsize="32"/>
> + <reg name="hideleg" bitsize="32"/>
> + <reg name="hie" bitsize="32"/>
> + <reg name="htvec" bitsize="32"/>
> + <reg name="hscratch" bitsize="32"/>
> + <reg name="hepc" bitsize="32"/>
> + <reg name="hcause" bitsize="32"/>
> + <reg name="hbadaddr" bitsize="32"/>
> + <reg name="hip" bitsize="32"/>
> + <reg name="mbase" bitsize="32"/>
> + <reg name="mbound" bitsize="32"/>
> + <reg name="mibase" bitsize="32"/>
> + <reg name="mibound" bitsize="32"/>
> + <reg name="mdbase" bitsize="32"/>
> + <reg name="mdbound" bitsize="32"/>
> + <reg name="mucounteren" bitsize="32"/>
> + <reg name="mscounteren" bitsize="32"/>
> + <reg name="mhcounteren" bitsize="32"/>
> +</feature>
> diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml
> new file mode 100644
> index 0000000..783287d
> --- /dev/null
> +++ b/gdb-xml/riscv-32bit-fpu.xml
> @@ -0,0 +1,46 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2018 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.riscv.fpu">
> + <reg name="ft0" bitsize="32" type="ieee_single"/>
> + <reg name="ft1" bitsize="32" type="ieee_single"/>
> + <reg name="ft2" bitsize="32" type="ieee_single"/>
> + <reg name="ft3" bitsize="32" type="ieee_single"/>
> + <reg name="ft4" bitsize="32" type="ieee_single"/>
> + <reg name="ft5" bitsize="32" type="ieee_single"/>
> + <reg name="ft6" bitsize="32" type="ieee_single"/>
> + <reg name="ft7" bitsize="32" type="ieee_single"/>
> + <reg name="fs0" bitsize="32" type="ieee_single"/>
> + <reg name="fs1" bitsize="32" type="ieee_single"/>
> + <reg name="fa0" bitsize="32" type="ieee_single"/>
> + <reg name="fa1" bitsize="32" type="ieee_single"/>
> + <reg name="fa2" bitsize="32" type="ieee_single"/>
> + <reg name="fa3" bitsize="32" type="ieee_single"/>
> + <reg name="fa4" bitsize="32" type="ieee_single"/>
> + <reg name="fa5" bitsize="32" type="ieee_single"/>
> + <reg name="fa6" bitsize="32" type="ieee_single"/>
> + <reg name="fa7" bitsize="32" type="ieee_single"/>
> + <reg name="fs2" bitsize="32" type="ieee_single"/>
> + <reg name="fs3" bitsize="32" type="ieee_single"/>
> + <reg name="fs4" bitsize="32" type="ieee_single"/>
> + <reg name="fs5" bitsize="32" type="ieee_single"/>
> + <reg name="fs6" bitsize="32" type="ieee_single"/>
> + <reg name="fs7" bitsize="32" type="ieee_single"/>
> + <reg name="fs8" bitsize="32" type="ieee_single"/>
> + <reg name="fs9" bitsize="32" type="ieee_single"/>
> + <reg name="fs10" bitsize="32" type="ieee_single"/>
> + <reg name="fs11" bitsize="32" type="ieee_single"/>
> + <reg name="ft8" bitsize="32" type="ieee_single"/>
> + <reg name="ft9" bitsize="32" type="ieee_single"/>
> + <reg name="ft10" bitsize="32" type="ieee_single"/>
> + <reg name="ft11" bitsize="32" type="ieee_single"/>
> +
> + <reg name="fflags" bitsize="32" type="int"/>
> + <reg name="frm" bitsize="32" type="int"/>
> + <reg name="fcsr" bitsize="32" type="int"/>
> +</feature>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 2/5 v2] RISC-V: Add 64-bit gdb xml files.
2018-12-28 22:08 ` [Qemu-riscv] " Jim Wilson
@ 2019-01-22 21:53 ` Alistair Francis
-1 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2019-01-22 21:53 UTC (permalink / raw)
To: Jim Wilson; +Cc: qemu-devel@nongnu.org Developers, qemu-riscv
On Fri, Dec 28, 2018 at 2:20 PM Jim Wilson <jimw@sifive.com> wrote:
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> configure | 1 +
> gdb-xml/riscv-64bit-cpu.xml | 43 ++++++++
> gdb-xml/riscv-64bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++
> gdb-xml/riscv-64bit-fpu.xml | 52 +++++++++
> 4 files changed, 346 insertions(+)
> create mode 100644 gdb-xml/riscv-64bit-cpu.xml
> create mode 100644 gdb-xml/riscv-64bit-csr.xml
> create mode 100644 gdb-xml/riscv-64bit-fpu.xml
>
> diff --git a/configure b/configure
> index 4e05eed..00b7495 100755
> --- a/configure
> +++ b/configure
> @@ -7215,6 +7215,7 @@ case "$target_name" in
> TARGET_BASE_ARCH=riscv
> TARGET_ABI_DIR=riscv
> mttcg=yes
> + gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
> target_compiler=$cross_cc_riscv64
> ;;
> sh4|sh4eb)
> diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml
> new file mode 100644
> index 0000000..f37d7f3
> --- /dev/null
> +++ b/gdb-xml/riscv-64bit-cpu.xml
> @@ -0,0 +1,43 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2018 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.riscv.cpu">
> + <reg name="zero" bitsize="64" type="int"/>
> + <reg name="ra" bitsize="64" type="code_ptr"/>
> + <reg name="sp" bitsize="64" type="data_ptr"/>
> + <reg name="gp" bitsize="64" type="data_ptr"/>
> + <reg name="tp" bitsize="64" type="data_ptr"/>
> + <reg name="t0" bitsize="64" type="int"/>
> + <reg name="t1" bitsize="64" type="int"/>
> + <reg name="t2" bitsize="64" type="int"/>
> + <reg name="fp" bitsize="64" type="data_ptr"/>
> + <reg name="s1" bitsize="64" type="int"/>
> + <reg name="a0" bitsize="64" type="int"/>
> + <reg name="a1" bitsize="64" type="int"/>
> + <reg name="a2" bitsize="64" type="int"/>
> + <reg name="a3" bitsize="64" type="int"/>
> + <reg name="a4" bitsize="64" type="int"/>
> + <reg name="a5" bitsize="64" type="int"/>
> + <reg name="a6" bitsize="64" type="int"/>
> + <reg name="a7" bitsize="64" type="int"/>
> + <reg name="s2" bitsize="64" type="int"/>
> + <reg name="s3" bitsize="64" type="int"/>
> + <reg name="s4" bitsize="64" type="int"/>
> + <reg name="s5" bitsize="64" type="int"/>
> + <reg name="s6" bitsize="64" type="int"/>
> + <reg name="s7" bitsize="64" type="int"/>
> + <reg name="s8" bitsize="64" type="int"/>
> + <reg name="s9" bitsize="64" type="int"/>
> + <reg name="s10" bitsize="64" type="int"/>
> + <reg name="s11" bitsize="64" type="int"/>
> + <reg name="t3" bitsize="64" type="int"/>
> + <reg name="t4" bitsize="64" type="int"/>
> + <reg name="t5" bitsize="64" type="int"/>
> + <reg name="t6" bitsize="64" type="int"/>
> + <reg name="pc" bitsize="64" type="code_ptr"/>
> +</feature>
> diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml
> new file mode 100644
> index 0000000..a3de834
> --- /dev/null
> +++ b/gdb-xml/riscv-64bit-csr.xml
> @@ -0,0 +1,250 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2018 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.riscv.csr">
> + <reg name="ustatus" bitsize="64"/>
> + <reg name="uie" bitsize="64"/>
> + <reg name="utvec" bitsize="64"/>
> + <reg name="uscratch" bitsize="64"/>
> + <reg name="uepc" bitsize="64"/>
> + <reg name="ucause" bitsize="64"/>
> + <reg name="utval" bitsize="64"/>
> + <reg name="uip" bitsize="64"/>
> + <reg name="fflags" bitsize="64"/>
> + <reg name="frm" bitsize="64"/>
> + <reg name="fcsr" bitsize="64"/>
> + <reg name="cycle" bitsize="64"/>
> + <reg name="time" bitsize="64"/>
> + <reg name="instret" bitsize="64"/>
> + <reg name="hpmcounter3" bitsize="64"/>
> + <reg name="hpmcounter4" bitsize="64"/>
> + <reg name="hpmcounter5" bitsize="64"/>
> + <reg name="hpmcounter6" bitsize="64"/>
> + <reg name="hpmcounter7" bitsize="64"/>
> + <reg name="hpmcounter8" bitsize="64"/>
> + <reg name="hpmcounter9" bitsize="64"/>
> + <reg name="hpmcounter10" bitsize="64"/>
> + <reg name="hpmcounter11" bitsize="64"/>
> + <reg name="hpmcounter12" bitsize="64"/>
> + <reg name="hpmcounter13" bitsize="64"/>
> + <reg name="hpmcounter14" bitsize="64"/>
> + <reg name="hpmcounter15" bitsize="64"/>
> + <reg name="hpmcounter16" bitsize="64"/>
> + <reg name="hpmcounter17" bitsize="64"/>
> + <reg name="hpmcounter18" bitsize="64"/>
> + <reg name="hpmcounter19" bitsize="64"/>
> + <reg name="hpmcounter20" bitsize="64"/>
> + <reg name="hpmcounter21" bitsize="64"/>
> + <reg name="hpmcounter22" bitsize="64"/>
> + <reg name="hpmcounter23" bitsize="64"/>
> + <reg name="hpmcounter24" bitsize="64"/>
> + <reg name="hpmcounter25" bitsize="64"/>
> + <reg name="hpmcounter26" bitsize="64"/>
> + <reg name="hpmcounter27" bitsize="64"/>
> + <reg name="hpmcounter28" bitsize="64"/>
> + <reg name="hpmcounter29" bitsize="64"/>
> + <reg name="hpmcounter30" bitsize="64"/>
> + <reg name="hpmcounter31" bitsize="64"/>
> + <reg name="cycleh" bitsize="64"/>
> + <reg name="timeh" bitsize="64"/>
> + <reg name="instreth" bitsize="64"/>
> + <reg name="hpmcounter3h" bitsize="64"/>
> + <reg name="hpmcounter4h" bitsize="64"/>
> + <reg name="hpmcounter5h" bitsize="64"/>
> + <reg name="hpmcounter6h" bitsize="64"/>
> + <reg name="hpmcounter7h" bitsize="64"/>
> + <reg name="hpmcounter8h" bitsize="64"/>
> + <reg name="hpmcounter9h" bitsize="64"/>
> + <reg name="hpmcounter10h" bitsize="64"/>
> + <reg name="hpmcounter11h" bitsize="64"/>
> + <reg name="hpmcounter12h" bitsize="64"/>
> + <reg name="hpmcounter13h" bitsize="64"/>
> + <reg name="hpmcounter14h" bitsize="64"/>
> + <reg name="hpmcounter15h" bitsize="64"/>
> + <reg name="hpmcounter16h" bitsize="64"/>
> + <reg name="hpmcounter17h" bitsize="64"/>
> + <reg name="hpmcounter18h" bitsize="64"/>
> + <reg name="hpmcounter19h" bitsize="64"/>
> + <reg name="hpmcounter20h" bitsize="64"/>
> + <reg name="hpmcounter21h" bitsize="64"/>
> + <reg name="hpmcounter22h" bitsize="64"/>
> + <reg name="hpmcounter23h" bitsize="64"/>
> + <reg name="hpmcounter24h" bitsize="64"/>
> + <reg name="hpmcounter25h" bitsize="64"/>
> + <reg name="hpmcounter26h" bitsize="64"/>
> + <reg name="hpmcounter27h" bitsize="64"/>
> + <reg name="hpmcounter28h" bitsize="64"/>
> + <reg name="hpmcounter29h" bitsize="64"/>
> + <reg name="hpmcounter30h" bitsize="64"/>
> + <reg name="hpmcounter31h" bitsize="64"/>
> + <reg name="sstatus" bitsize="64"/>
> + <reg name="sedeleg" bitsize="64"/>
> + <reg name="sideleg" bitsize="64"/>
> + <reg name="sie" bitsize="64"/>
> + <reg name="stvec" bitsize="64"/>
> + <reg name="scounteren" bitsize="64"/>
> + <reg name="sscratch" bitsize="64"/>
> + <reg name="sepc" bitsize="64"/>
> + <reg name="scause" bitsize="64"/>
> + <reg name="stval" bitsize="64"/>
> + <reg name="sip" bitsize="64"/>
> + <reg name="satp" bitsize="64"/>
> + <reg name="mvendorid" bitsize="64"/>
> + <reg name="marchid" bitsize="64"/>
> + <reg name="mimpid" bitsize="64"/>
> + <reg name="mhartid" bitsize="64"/>
> + <reg name="mstatus" bitsize="64"/>
> + <reg name="misa" bitsize="64"/>
> + <reg name="medeleg" bitsize="64"/>
> + <reg name="mideleg" bitsize="64"/>
> + <reg name="mie" bitsize="64"/>
> + <reg name="mtvec" bitsize="64"/>
> + <reg name="mcounteren" bitsize="64"/>
> + <reg name="mscratch" bitsize="64"/>
> + <reg name="mepc" bitsize="64"/>
> + <reg name="mcause" bitsize="64"/>
> + <reg name="mtval" bitsize="64"/>
> + <reg name="mip" bitsize="64"/>
> + <reg name="pmpcfg0" bitsize="64"/>
> + <reg name="pmpcfg1" bitsize="64"/>
> + <reg name="pmpcfg2" bitsize="64"/>
> + <reg name="pmpcfg3" bitsize="64"/>
> + <reg name="pmpaddr0" bitsize="64"/>
> + <reg name="pmpaddr1" bitsize="64"/>
> + <reg name="pmpaddr2" bitsize="64"/>
> + <reg name="pmpaddr3" bitsize="64"/>
> + <reg name="pmpaddr4" bitsize="64"/>
> + <reg name="pmpaddr5" bitsize="64"/>
> + <reg name="pmpaddr6" bitsize="64"/>
> + <reg name="pmpaddr7" bitsize="64"/>
> + <reg name="pmpaddr8" bitsize="64"/>
> + <reg name="pmpaddr9" bitsize="64"/>
> + <reg name="pmpaddr10" bitsize="64"/>
> + <reg name="pmpaddr11" bitsize="64"/>
> + <reg name="pmpaddr12" bitsize="64"/>
> + <reg name="pmpaddr13" bitsize="64"/>
> + <reg name="pmpaddr14" bitsize="64"/>
> + <reg name="pmpaddr15" bitsize="64"/>
> + <reg name="mcycle" bitsize="64"/>
> + <reg name="minstret" bitsize="64"/>
> + <reg name="mhpmcounter3" bitsize="64"/>
> + <reg name="mhpmcounter4" bitsize="64"/>
> + <reg name="mhpmcounter5" bitsize="64"/>
> + <reg name="mhpmcounter6" bitsize="64"/>
> + <reg name="mhpmcounter7" bitsize="64"/>
> + <reg name="mhpmcounter8" bitsize="64"/>
> + <reg name="mhpmcounter9" bitsize="64"/>
> + <reg name="mhpmcounter10" bitsize="64"/>
> + <reg name="mhpmcounter11" bitsize="64"/>
> + <reg name="mhpmcounter12" bitsize="64"/>
> + <reg name="mhpmcounter13" bitsize="64"/>
> + <reg name="mhpmcounter14" bitsize="64"/>
> + <reg name="mhpmcounter15" bitsize="64"/>
> + <reg name="mhpmcounter16" bitsize="64"/>
> + <reg name="mhpmcounter17" bitsize="64"/>
> + <reg name="mhpmcounter18" bitsize="64"/>
> + <reg name="mhpmcounter19" bitsize="64"/>
> + <reg name="mhpmcounter20" bitsize="64"/>
> + <reg name="mhpmcounter21" bitsize="64"/>
> + <reg name="mhpmcounter22" bitsize="64"/>
> + <reg name="mhpmcounter23" bitsize="64"/>
> + <reg name="mhpmcounter24" bitsize="64"/>
> + <reg name="mhpmcounter25" bitsize="64"/>
> + <reg name="mhpmcounter26" bitsize="64"/>
> + <reg name="mhpmcounter27" bitsize="64"/>
> + <reg name="mhpmcounter28" bitsize="64"/>
> + <reg name="mhpmcounter29" bitsize="64"/>
> + <reg name="mhpmcounter30" bitsize="64"/>
> + <reg name="mhpmcounter31" bitsize="64"/>
> + <reg name="mcycleh" bitsize="64"/>
> + <reg name="minstreth" bitsize="64"/>
> + <reg name="mhpmcounter3h" bitsize="64"/>
> + <reg name="mhpmcounter4h" bitsize="64"/>
> + <reg name="mhpmcounter5h" bitsize="64"/>
> + <reg name="mhpmcounter6h" bitsize="64"/>
> + <reg name="mhpmcounter7h" bitsize="64"/>
> + <reg name="mhpmcounter8h" bitsize="64"/>
> + <reg name="mhpmcounter9h" bitsize="64"/>
> + <reg name="mhpmcounter10h" bitsize="64"/>
> + <reg name="mhpmcounter11h" bitsize="64"/>
> + <reg name="mhpmcounter12h" bitsize="64"/>
> + <reg name="mhpmcounter13h" bitsize="64"/>
> + <reg name="mhpmcounter14h" bitsize="64"/>
> + <reg name="mhpmcounter15h" bitsize="64"/>
> + <reg name="mhpmcounter16h" bitsize="64"/>
> + <reg name="mhpmcounter17h" bitsize="64"/>
> + <reg name="mhpmcounter18h" bitsize="64"/>
> + <reg name="mhpmcounter19h" bitsize="64"/>
> + <reg name="mhpmcounter20h" bitsize="64"/>
> + <reg name="mhpmcounter21h" bitsize="64"/>
> + <reg name="mhpmcounter22h" bitsize="64"/>
> + <reg name="mhpmcounter23h" bitsize="64"/>
> + <reg name="mhpmcounter24h" bitsize="64"/>
> + <reg name="mhpmcounter25h" bitsize="64"/>
> + <reg name="mhpmcounter26h" bitsize="64"/>
> + <reg name="mhpmcounter27h" bitsize="64"/>
> + <reg name="mhpmcounter28h" bitsize="64"/>
> + <reg name="mhpmcounter29h" bitsize="64"/>
> + <reg name="mhpmcounter30h" bitsize="64"/>
> + <reg name="mhpmcounter31h" bitsize="64"/>
> + <reg name="mhpmevent3" bitsize="64"/>
> + <reg name="mhpmevent4" bitsize="64"/>
> + <reg name="mhpmevent5" bitsize="64"/>
> + <reg name="mhpmevent6" bitsize="64"/>
> + <reg name="mhpmevent7" bitsize="64"/>
> + <reg name="mhpmevent8" bitsize="64"/>
> + <reg name="mhpmevent9" bitsize="64"/>
> + <reg name="mhpmevent10" bitsize="64"/>
> + <reg name="mhpmevent11" bitsize="64"/>
> + <reg name="mhpmevent12" bitsize="64"/>
> + <reg name="mhpmevent13" bitsize="64"/>
> + <reg name="mhpmevent14" bitsize="64"/>
> + <reg name="mhpmevent15" bitsize="64"/>
> + <reg name="mhpmevent16" bitsize="64"/>
> + <reg name="mhpmevent17" bitsize="64"/>
> + <reg name="mhpmevent18" bitsize="64"/>
> + <reg name="mhpmevent19" bitsize="64"/>
> + <reg name="mhpmevent20" bitsize="64"/>
> + <reg name="mhpmevent21" bitsize="64"/>
> + <reg name="mhpmevent22" bitsize="64"/>
> + <reg name="mhpmevent23" bitsize="64"/>
> + <reg name="mhpmevent24" bitsize="64"/>
> + <reg name="mhpmevent25" bitsize="64"/>
> + <reg name="mhpmevent26" bitsize="64"/>
> + <reg name="mhpmevent27" bitsize="64"/>
> + <reg name="mhpmevent28" bitsize="64"/>
> + <reg name="mhpmevent29" bitsize="64"/>
> + <reg name="mhpmevent30" bitsize="64"/>
> + <reg name="mhpmevent31" bitsize="64"/>
> + <reg name="tselect" bitsize="64"/>
> + <reg name="tdata1" bitsize="64"/>
> + <reg name="tdata2" bitsize="64"/>
> + <reg name="tdata3" bitsize="64"/>
> + <reg name="dcsr" bitsize="64"/>
> + <reg name="dpc" bitsize="64"/>
> + <reg name="dscratch" bitsize="64"/>
> + <reg name="hstatus" bitsize="64"/>
> + <reg name="hedeleg" bitsize="64"/>
> + <reg name="hideleg" bitsize="64"/>
> + <reg name="hie" bitsize="64"/>
> + <reg name="htvec" bitsize="64"/>
> + <reg name="hscratch" bitsize="64"/>
> + <reg name="hepc" bitsize="64"/>
> + <reg name="hcause" bitsize="64"/>
> + <reg name="hbadaddr" bitsize="64"/>
> + <reg name="hip" bitsize="64"/>
> + <reg name="mbase" bitsize="64"/>
> + <reg name="mbound" bitsize="64"/>
> + <reg name="mibase" bitsize="64"/>
> + <reg name="mibound" bitsize="64"/>
> + <reg name="mdbase" bitsize="64"/>
> + <reg name="mdbound" bitsize="64"/>
> + <reg name="mucounteren" bitsize="64"/>
> + <reg name="mscounteren" bitsize="64"/>
> + <reg name="mhcounteren" bitsize="64"/>
> +</feature>
> diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml
> new file mode 100644
> index 0000000..fb24b72
> --- /dev/null
> +++ b/gdb-xml/riscv-64bit-fpu.xml
> @@ -0,0 +1,52 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2018 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.riscv.fpu">
> +
> + <union id="riscv_double">
> + <field name="float" type="ieee_single"/>
> + <field name="double" type="ieee_double"/>
> + </union>
> +
> + <reg name="ft0" bitsize="64" type="riscv_double"/>
> + <reg name="ft1" bitsize="64" type="riscv_double"/>
> + <reg name="ft2" bitsize="64" type="riscv_double"/>
> + <reg name="ft3" bitsize="64" type="riscv_double"/>
> + <reg name="ft4" bitsize="64" type="riscv_double"/>
> + <reg name="ft5" bitsize="64" type="riscv_double"/>
> + <reg name="ft6" bitsize="64" type="riscv_double"/>
> + <reg name="ft7" bitsize="64" type="riscv_double"/>
> + <reg name="fs0" bitsize="64" type="riscv_double"/>
> + <reg name="fs1" bitsize="64" type="riscv_double"/>
> + <reg name="fa0" bitsize="64" type="riscv_double"/>
> + <reg name="fa1" bitsize="64" type="riscv_double"/>
> + <reg name="fa2" bitsize="64" type="riscv_double"/>
> + <reg name="fa3" bitsize="64" type="riscv_double"/>
> + <reg name="fa4" bitsize="64" type="riscv_double"/>
> + <reg name="fa5" bitsize="64" type="riscv_double"/>
> + <reg name="fa6" bitsize="64" type="riscv_double"/>
> + <reg name="fa7" bitsize="64" type="riscv_double"/>
> + <reg name="fs2" bitsize="64" type="riscv_double"/>
> + <reg name="fs3" bitsize="64" type="riscv_double"/>
> + <reg name="fs4" bitsize="64" type="riscv_double"/>
> + <reg name="fs5" bitsize="64" type="riscv_double"/>
> + <reg name="fs6" bitsize="64" type="riscv_double"/>
> + <reg name="fs7" bitsize="64" type="riscv_double"/>
> + <reg name="fs8" bitsize="64" type="riscv_double"/>
> + <reg name="fs9" bitsize="64" type="riscv_double"/>
> + <reg name="fs10" bitsize="64" type="riscv_double"/>
> + <reg name="fs11" bitsize="64" type="riscv_double"/>
> + <reg name="ft8" bitsize="64" type="riscv_double"/>
> + <reg name="ft9" bitsize="64" type="riscv_double"/>
> + <reg name="ft10" bitsize="64" type="riscv_double"/>
> + <reg name="ft11" bitsize="64" type="riscv_double"/>
> +
> + <reg name="fflags" bitsize="32" type="int"/>
> + <reg name="frm" bitsize="32" type="int"/>
> + <reg name="fcsr" bitsize="32" type="int"/>
> +</feature>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/5 v2] RISC-V: Add 64-bit gdb xml files.
@ 2019-01-22 21:53 ` Alistair Francis
0 siblings, 0 replies; 38+ messages in thread
From: Alistair Francis @ 2019-01-22 21:53 UTC (permalink / raw)
To: Jim Wilson; +Cc: qemu-devel@nongnu.org Developers, qemu-riscv
On Fri, Dec 28, 2018 at 2:20 PM Jim Wilson <jimw@sifive.com> wrote:
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> configure | 1 +
> gdb-xml/riscv-64bit-cpu.xml | 43 ++++++++
> gdb-xml/riscv-64bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++
> gdb-xml/riscv-64bit-fpu.xml | 52 +++++++++
> 4 files changed, 346 insertions(+)
> create mode 100644 gdb-xml/riscv-64bit-cpu.xml
> create mode 100644 gdb-xml/riscv-64bit-csr.xml
> create mode 100644 gdb-xml/riscv-64bit-fpu.xml
>
> diff --git a/configure b/configure
> index 4e05eed..00b7495 100755
> --- a/configure
> +++ b/configure
> @@ -7215,6 +7215,7 @@ case "$target_name" in
> TARGET_BASE_ARCH=riscv
> TARGET_ABI_DIR=riscv
> mttcg=yes
> + gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
> target_compiler=$cross_cc_riscv64
> ;;
> sh4|sh4eb)
> diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml
> new file mode 100644
> index 0000000..f37d7f3
> --- /dev/null
> +++ b/gdb-xml/riscv-64bit-cpu.xml
> @@ -0,0 +1,43 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2018 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.riscv.cpu">
> + <reg name="zero" bitsize="64" type="int"/>
> + <reg name="ra" bitsize="64" type="code_ptr"/>
> + <reg name="sp" bitsize="64" type="data_ptr"/>
> + <reg name="gp" bitsize="64" type="data_ptr"/>
> + <reg name="tp" bitsize="64" type="data_ptr"/>
> + <reg name="t0" bitsize="64" type="int"/>
> + <reg name="t1" bitsize="64" type="int"/>
> + <reg name="t2" bitsize="64" type="int"/>
> + <reg name="fp" bitsize="64" type="data_ptr"/>
> + <reg name="s1" bitsize="64" type="int"/>
> + <reg name="a0" bitsize="64" type="int"/>
> + <reg name="a1" bitsize="64" type="int"/>
> + <reg name="a2" bitsize="64" type="int"/>
> + <reg name="a3" bitsize="64" type="int"/>
> + <reg name="a4" bitsize="64" type="int"/>
> + <reg name="a5" bitsize="64" type="int"/>
> + <reg name="a6" bitsize="64" type="int"/>
> + <reg name="a7" bitsize="64" type="int"/>
> + <reg name="s2" bitsize="64" type="int"/>
> + <reg name="s3" bitsize="64" type="int"/>
> + <reg name="s4" bitsize="64" type="int"/>
> + <reg name="s5" bitsize="64" type="int"/>
> + <reg name="s6" bitsize="64" type="int"/>
> + <reg name="s7" bitsize="64" type="int"/>
> + <reg name="s8" bitsize="64" type="int"/>
> + <reg name="s9" bitsize="64" type="int"/>
> + <reg name="s10" bitsize="64" type="int"/>
> + <reg name="s11" bitsize="64" type="int"/>
> + <reg name="t3" bitsize="64" type="int"/>
> + <reg name="t4" bitsize="64" type="int"/>
> + <reg name="t5" bitsize="64" type="int"/>
> + <reg name="t6" bitsize="64" type="int"/>
> + <reg name="pc" bitsize="64" type="code_ptr"/>
> +</feature>
> diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml
> new file mode 100644
> index 0000000..a3de834
> --- /dev/null
> +++ b/gdb-xml/riscv-64bit-csr.xml
> @@ -0,0 +1,250 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2018 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.riscv.csr">
> + <reg name="ustatus" bitsize="64"/>
> + <reg name="uie" bitsize="64"/>
> + <reg name="utvec" bitsize="64"/>
> + <reg name="uscratch" bitsize="64"/>
> + <reg name="uepc" bitsize="64"/>
> + <reg name="ucause" bitsize="64"/>
> + <reg name="utval" bitsize="64"/>
> + <reg name="uip" bitsize="64"/>
> + <reg name="fflags" bitsize="64"/>
> + <reg name="frm" bitsize="64"/>
> + <reg name="fcsr" bitsize="64"/>
> + <reg name="cycle" bitsize="64"/>
> + <reg name="time" bitsize="64"/>
> + <reg name="instret" bitsize="64"/>
> + <reg name="hpmcounter3" bitsize="64"/>
> + <reg name="hpmcounter4" bitsize="64"/>
> + <reg name="hpmcounter5" bitsize="64"/>
> + <reg name="hpmcounter6" bitsize="64"/>
> + <reg name="hpmcounter7" bitsize="64"/>
> + <reg name="hpmcounter8" bitsize="64"/>
> + <reg name="hpmcounter9" bitsize="64"/>
> + <reg name="hpmcounter10" bitsize="64"/>
> + <reg name="hpmcounter11" bitsize="64"/>
> + <reg name="hpmcounter12" bitsize="64"/>
> + <reg name="hpmcounter13" bitsize="64"/>
> + <reg name="hpmcounter14" bitsize="64"/>
> + <reg name="hpmcounter15" bitsize="64"/>
> + <reg name="hpmcounter16" bitsize="64"/>
> + <reg name="hpmcounter17" bitsize="64"/>
> + <reg name="hpmcounter18" bitsize="64"/>
> + <reg name="hpmcounter19" bitsize="64"/>
> + <reg name="hpmcounter20" bitsize="64"/>
> + <reg name="hpmcounter21" bitsize="64"/>
> + <reg name="hpmcounter22" bitsize="64"/>
> + <reg name="hpmcounter23" bitsize="64"/>
> + <reg name="hpmcounter24" bitsize="64"/>
> + <reg name="hpmcounter25" bitsize="64"/>
> + <reg name="hpmcounter26" bitsize="64"/>
> + <reg name="hpmcounter27" bitsize="64"/>
> + <reg name="hpmcounter28" bitsize="64"/>
> + <reg name="hpmcounter29" bitsize="64"/>
> + <reg name="hpmcounter30" bitsize="64"/>
> + <reg name="hpmcounter31" bitsize="64"/>
> + <reg name="cycleh" bitsize="64"/>
> + <reg name="timeh" bitsize="64"/>
> + <reg name="instreth" bitsize="64"/>
> + <reg name="hpmcounter3h" bitsize="64"/>
> + <reg name="hpmcounter4h" bitsize="64"/>
> + <reg name="hpmcounter5h" bitsize="64"/>
> + <reg name="hpmcounter6h" bitsize="64"/>
> + <reg name="hpmcounter7h" bitsize="64"/>
> + <reg name="hpmcounter8h" bitsize="64"/>
> + <reg name="hpmcounter9h" bitsize="64"/>
> + <reg name="hpmcounter10h" bitsize="64"/>
> + <reg name="hpmcounter11h" bitsize="64"/>
> + <reg name="hpmcounter12h" bitsize="64"/>
> + <reg name="hpmcounter13h" bitsize="64"/>
> + <reg name="hpmcounter14h" bitsize="64"/>
> + <reg name="hpmcounter15h" bitsize="64"/>
> + <reg name="hpmcounter16h" bitsize="64"/>
> + <reg name="hpmcounter17h" bitsize="64"/>
> + <reg name="hpmcounter18h" bitsize="64"/>
> + <reg name="hpmcounter19h" bitsize="64"/>
> + <reg name="hpmcounter20h" bitsize="64"/>
> + <reg name="hpmcounter21h" bitsize="64"/>
> + <reg name="hpmcounter22h" bitsize="64"/>
> + <reg name="hpmcounter23h" bitsize="64"/>
> + <reg name="hpmcounter24h" bitsize="64"/>
> + <reg name="hpmcounter25h" bitsize="64"/>
> + <reg name="hpmcounter26h" bitsize="64"/>
> + <reg name="hpmcounter27h" bitsize="64"/>
> + <reg name="hpmcounter28h" bitsize="64"/>
> + <reg name="hpmcounter29h" bitsize="64"/>
> + <reg name="hpmcounter30h" bitsize="64"/>
> + <reg name="hpmcounter31h" bitsize="64"/>
> + <reg name="sstatus" bitsize="64"/>
> + <reg name="sedeleg" bitsize="64"/>
> + <reg name="sideleg" bitsize="64"/>
> + <reg name="sie" bitsize="64"/>
> + <reg name="stvec" bitsize="64"/>
> + <reg name="scounteren" bitsize="64"/>
> + <reg name="sscratch" bitsize="64"/>
> + <reg name="sepc" bitsize="64"/>
> + <reg name="scause" bitsize="64"/>
> + <reg name="stval" bitsize="64"/>
> + <reg name="sip" bitsize="64"/>
> + <reg name="satp" bitsize="64"/>
> + <reg name="mvendorid" bitsize="64"/>
> + <reg name="marchid" bitsize="64"/>
> + <reg name="mimpid" bitsize="64"/>
> + <reg name="mhartid" bitsize="64"/>
> + <reg name="mstatus" bitsize="64"/>
> + <reg name="misa" bitsize="64"/>
> + <reg name="medeleg" bitsize="64"/>
> + <reg name="mideleg" bitsize="64"/>
> + <reg name="mie" bitsize="64"/>
> + <reg name="mtvec" bitsize="64"/>
> + <reg name="mcounteren" bitsize="64"/>
> + <reg name="mscratch" bitsize="64"/>
> + <reg name="mepc" bitsize="64"/>
> + <reg name="mcause" bitsize="64"/>
> + <reg name="mtval" bitsize="64"/>
> + <reg name="mip" bitsize="64"/>
> + <reg name="pmpcfg0" bitsize="64"/>
> + <reg name="pmpcfg1" bitsize="64"/>
> + <reg name="pmpcfg2" bitsize="64"/>
> + <reg name="pmpcfg3" bitsize="64"/>
> + <reg name="pmpaddr0" bitsize="64"/>
> + <reg name="pmpaddr1" bitsize="64"/>
> + <reg name="pmpaddr2" bitsize="64"/>
> + <reg name="pmpaddr3" bitsize="64"/>
> + <reg name="pmpaddr4" bitsize="64"/>
> + <reg name="pmpaddr5" bitsize="64"/>
> + <reg name="pmpaddr6" bitsize="64"/>
> + <reg name="pmpaddr7" bitsize="64"/>
> + <reg name="pmpaddr8" bitsize="64"/>
> + <reg name="pmpaddr9" bitsize="64"/>
> + <reg name="pmpaddr10" bitsize="64"/>
> + <reg name="pmpaddr11" bitsize="64"/>
> + <reg name="pmpaddr12" bitsize="64"/>
> + <reg name="pmpaddr13" bitsize="64"/>
> + <reg name="pmpaddr14" bitsize="64"/>
> + <reg name="pmpaddr15" bitsize="64"/>
> + <reg name="mcycle" bitsize="64"/>
> + <reg name="minstret" bitsize="64"/>
> + <reg name="mhpmcounter3" bitsize="64"/>
> + <reg name="mhpmcounter4" bitsize="64"/>
> + <reg name="mhpmcounter5" bitsize="64"/>
> + <reg name="mhpmcounter6" bitsize="64"/>
> + <reg name="mhpmcounter7" bitsize="64"/>
> + <reg name="mhpmcounter8" bitsize="64"/>
> + <reg name="mhpmcounter9" bitsize="64"/>
> + <reg name="mhpmcounter10" bitsize="64"/>
> + <reg name="mhpmcounter11" bitsize="64"/>
> + <reg name="mhpmcounter12" bitsize="64"/>
> + <reg name="mhpmcounter13" bitsize="64"/>
> + <reg name="mhpmcounter14" bitsize="64"/>
> + <reg name="mhpmcounter15" bitsize="64"/>
> + <reg name="mhpmcounter16" bitsize="64"/>
> + <reg name="mhpmcounter17" bitsize="64"/>
> + <reg name="mhpmcounter18" bitsize="64"/>
> + <reg name="mhpmcounter19" bitsize="64"/>
> + <reg name="mhpmcounter20" bitsize="64"/>
> + <reg name="mhpmcounter21" bitsize="64"/>
> + <reg name="mhpmcounter22" bitsize="64"/>
> + <reg name="mhpmcounter23" bitsize="64"/>
> + <reg name="mhpmcounter24" bitsize="64"/>
> + <reg name="mhpmcounter25" bitsize="64"/>
> + <reg name="mhpmcounter26" bitsize="64"/>
> + <reg name="mhpmcounter27" bitsize="64"/>
> + <reg name="mhpmcounter28" bitsize="64"/>
> + <reg name="mhpmcounter29" bitsize="64"/>
> + <reg name="mhpmcounter30" bitsize="64"/>
> + <reg name="mhpmcounter31" bitsize="64"/>
> + <reg name="mcycleh" bitsize="64"/>
> + <reg name="minstreth" bitsize="64"/>
> + <reg name="mhpmcounter3h" bitsize="64"/>
> + <reg name="mhpmcounter4h" bitsize="64"/>
> + <reg name="mhpmcounter5h" bitsize="64"/>
> + <reg name="mhpmcounter6h" bitsize="64"/>
> + <reg name="mhpmcounter7h" bitsize="64"/>
> + <reg name="mhpmcounter8h" bitsize="64"/>
> + <reg name="mhpmcounter9h" bitsize="64"/>
> + <reg name="mhpmcounter10h" bitsize="64"/>
> + <reg name="mhpmcounter11h" bitsize="64"/>
> + <reg name="mhpmcounter12h" bitsize="64"/>
> + <reg name="mhpmcounter13h" bitsize="64"/>
> + <reg name="mhpmcounter14h" bitsize="64"/>
> + <reg name="mhpmcounter15h" bitsize="64"/>
> + <reg name="mhpmcounter16h" bitsize="64"/>
> + <reg name="mhpmcounter17h" bitsize="64"/>
> + <reg name="mhpmcounter18h" bitsize="64"/>
> + <reg name="mhpmcounter19h" bitsize="64"/>
> + <reg name="mhpmcounter20h" bitsize="64"/>
> + <reg name="mhpmcounter21h" bitsize="64"/>
> + <reg name="mhpmcounter22h" bitsize="64"/>
> + <reg name="mhpmcounter23h" bitsize="64"/>
> + <reg name="mhpmcounter24h" bitsize="64"/>
> + <reg name="mhpmcounter25h" bitsize="64"/>
> + <reg name="mhpmcounter26h" bitsize="64"/>
> + <reg name="mhpmcounter27h" bitsize="64"/>
> + <reg name="mhpmcounter28h" bitsize="64"/>
> + <reg name="mhpmcounter29h" bitsize="64"/>
> + <reg name="mhpmcounter30h" bitsize="64"/>
> + <reg name="mhpmcounter31h" bitsize="64"/>
> + <reg name="mhpmevent3" bitsize="64"/>
> + <reg name="mhpmevent4" bitsize="64"/>
> + <reg name="mhpmevent5" bitsize="64"/>
> + <reg name="mhpmevent6" bitsize="64"/>
> + <reg name="mhpmevent7" bitsize="64"/>
> + <reg name="mhpmevent8" bitsize="64"/>
> + <reg name="mhpmevent9" bitsize="64"/>
> + <reg name="mhpmevent10" bitsize="64"/>
> + <reg name="mhpmevent11" bitsize="64"/>
> + <reg name="mhpmevent12" bitsize="64"/>
> + <reg name="mhpmevent13" bitsize="64"/>
> + <reg name="mhpmevent14" bitsize="64"/>
> + <reg name="mhpmevent15" bitsize="64"/>
> + <reg name="mhpmevent16" bitsize="64"/>
> + <reg name="mhpmevent17" bitsize="64"/>
> + <reg name="mhpmevent18" bitsize="64"/>
> + <reg name="mhpmevent19" bitsize="64"/>
> + <reg name="mhpmevent20" bitsize="64"/>
> + <reg name="mhpmevent21" bitsize="64"/>
> + <reg name="mhpmevent22" bitsize="64"/>
> + <reg name="mhpmevent23" bitsize="64"/>
> + <reg name="mhpmevent24" bitsize="64"/>
> + <reg name="mhpmevent25" bitsize="64"/>
> + <reg name="mhpmevent26" bitsize="64"/>
> + <reg name="mhpmevent27" bitsize="64"/>
> + <reg name="mhpmevent28" bitsize="64"/>
> + <reg name="mhpmevent29" bitsize="64"/>
> + <reg name="mhpmevent30" bitsize="64"/>
> + <reg name="mhpmevent31" bitsize="64"/>
> + <reg name="tselect" bitsize="64"/>
> + <reg name="tdata1" bitsize="64"/>
> + <reg name="tdata2" bitsize="64"/>
> + <reg name="tdata3" bitsize="64"/>
> + <reg name="dcsr" bitsize="64"/>
> + <reg name="dpc" bitsize="64"/>
> + <reg name="dscratch" bitsize="64"/>
> + <reg name="hstatus" bitsize="64"/>
> + <reg name="hedeleg" bitsize="64"/>
> + <reg name="hideleg" bitsize="64"/>
> + <reg name="hie" bitsize="64"/>
> + <reg name="htvec" bitsize="64"/>
> + <reg name="hscratch" bitsize="64"/>
> + <reg name="hepc" bitsize="64"/>
> + <reg name="hcause" bitsize="64"/>
> + <reg name="hbadaddr" bitsize="64"/>
> + <reg name="hip" bitsize="64"/>
> + <reg name="mbase" bitsize="64"/>
> + <reg name="mbound" bitsize="64"/>
> + <reg name="mibase" bitsize="64"/>
> + <reg name="mibound" bitsize="64"/>
> + <reg name="mdbase" bitsize="64"/>
> + <reg name="mdbound" bitsize="64"/>
> + <reg name="mucounteren" bitsize="64"/>
> + <reg name="mscounteren" bitsize="64"/>
> + <reg name="mhcounteren" bitsize="64"/>
> +</feature>
> diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml
> new file mode 100644
> index 0000000..fb24b72
> --- /dev/null
> +++ b/gdb-xml/riscv-64bit-fpu.xml
> @@ -0,0 +1,52 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2018 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.riscv.fpu">
> +
> + <union id="riscv_double">
> + <field name="float" type="ieee_single"/>
> + <field name="double" type="ieee_double"/>
> + </union>
> +
> + <reg name="ft0" bitsize="64" type="riscv_double"/>
> + <reg name="ft1" bitsize="64" type="riscv_double"/>
> + <reg name="ft2" bitsize="64" type="riscv_double"/>
> + <reg name="ft3" bitsize="64" type="riscv_double"/>
> + <reg name="ft4" bitsize="64" type="riscv_double"/>
> + <reg name="ft5" bitsize="64" type="riscv_double"/>
> + <reg name="ft6" bitsize="64" type="riscv_double"/>
> + <reg name="ft7" bitsize="64" type="riscv_double"/>
> + <reg name="fs0" bitsize="64" type="riscv_double"/>
> + <reg name="fs1" bitsize="64" type="riscv_double"/>
> + <reg name="fa0" bitsize="64" type="riscv_double"/>
> + <reg name="fa1" bitsize="64" type="riscv_double"/>
> + <reg name="fa2" bitsize="64" type="riscv_double"/>
> + <reg name="fa3" bitsize="64" type="riscv_double"/>
> + <reg name="fa4" bitsize="64" type="riscv_double"/>
> + <reg name="fa5" bitsize="64" type="riscv_double"/>
> + <reg name="fa6" bitsize="64" type="riscv_double"/>
> + <reg name="fa7" bitsize="64" type="riscv_double"/>
> + <reg name="fs2" bitsize="64" type="riscv_double"/>
> + <reg name="fs3" bitsize="64" type="riscv_double"/>
> + <reg name="fs4" bitsize="64" type="riscv_double"/>
> + <reg name="fs5" bitsize="64" type="riscv_double"/>
> + <reg name="fs6" bitsize="64" type="riscv_double"/>
> + <reg name="fs7" bitsize="64" type="riscv_double"/>
> + <reg name="fs8" bitsize="64" type="riscv_double"/>
> + <reg name="fs9" bitsize="64" type="riscv_double"/>
> + <reg name="fs10" bitsize="64" type="riscv_double"/>
> + <reg name="fs11" bitsize="64" type="riscv_double"/>
> + <reg name="ft8" bitsize="64" type="riscv_double"/>
> + <reg name="ft9" bitsize="64" type="riscv_double"/>
> + <reg name="ft10" bitsize="64" type="riscv_double"/>
> + <reg name="ft11" bitsize="64" type="riscv_double"/>
> +
> + <reg name="fflags" bitsize="32" type="int"/>
> + <reg name="frm" bitsize="32" type="int"/>
> + <reg name="fcsr" bitsize="32" type="int"/>
> +</feature>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.
2019-01-22 21:45 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-29 3:00 ` Jim Wilson
-1 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2019-01-29 3:00 UTC (permalink / raw)
To: Alistair Francis
Cc: Richard Henderson, qemu-riscv, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 1:45 PM Alistair Francis <alistair23@gmail.com> wrote:
> I think it makes more sense to just define the variable in the
> gdbstubs.c file then. Can you move it to patch 5?
Yes, that is no problem. That makes patch 3 a lot smaller and patch 5
a lot bigger, but it is the same code as before, just arranged
differently, so this shouldn't complicate the review too much.
Jim
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers.
@ 2019-01-29 3:00 ` Jim Wilson
0 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2019-01-29 3:00 UTC (permalink / raw)
To: Alistair Francis
Cc: Richard Henderson, qemu-riscv, qemu-devel@nongnu.org Developers
On Tue, Jan 22, 2019 at 1:45 PM Alistair Francis <alistair23@gmail.com> wrote:
> I think it makes more sense to just define the variable in the
> gdbstubs.c file then. Can you move it to patch 5?
Yes, that is no problem. That makes patch 3 a lot smaller and patch 5
a lot bigger, but it is the same code as before, just arranged
differently, so this shouldn't complicate the review too much.
Jim
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
2019-01-22 21:52 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-29 3:11 ` Jim Wilson
-1 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2019-01-29 3:11 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel@nongnu.org Developers, qemu-riscv
On Tue, Jan 22, 2019 at 1:52 PM Alistair Francis <alistair23@gmail.com> wrote:
> You can get env and then check for floating point support:
>
> CPURISCVState *env = &cs->env;
> if (env->misa_mask & RVF) {
> ...
I needed this which wasn't hard to figure out.
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
if (env->misa & RVF) {
The tricky bit was figuring out how to test it, because I wasn't sure
if making registers conditional would actually work. I figured out
that using -machine sifive_e gives me a target with no fpu, and
playing with that a bit I get the expected result, which is that the
FP regs don't print anymore. The FP related CSRs still do, but that
would require gdb fixes I think, because gdb knows that they are both
FP regs and CSR, and tries to print them both ways. That leads to a
more general problem of figuring out exactly which CSRs a particular
target implements, which is a bigger problem than I have time to fix
at the moment, and should be handled as a separate problem.
Since my patch set is now a month old, I'll rebase onto current master
and post a version 3 patch set.
Jim
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
@ 2019-01-29 3:11 ` Jim Wilson
0 siblings, 0 replies; 38+ messages in thread
From: Jim Wilson @ 2019-01-29 3:11 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel@nongnu.org Developers, qemu-riscv
On Tue, Jan 22, 2019 at 1:52 PM Alistair Francis <alistair23@gmail.com> wrote:
> You can get env and then check for floating point support:
>
> CPURISCVState *env = &cs->env;
> if (env->misa_mask & RVF) {
> ...
I needed this which wasn't hard to figure out.
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
if (env->misa & RVF) {
The tricky bit was figuring out how to test it, because I wasn't sure
if making registers conditional would actually work. I figured out
that using -machine sifive_e gives me a target with no fpu, and
playing with that a bit I get the expected result, which is that the
FP regs don't print anymore. The FP related CSRs still do, but that
would require gdb fixes I think, because gdb knows that they are both
FP regs and CSR, and tries to print them both ways. That leads to a
more general problem of figuring out exactly which CSRs a particular
target implements, which is a bigger problem than I have time to fix
at the moment, and should be handled as a separate problem.
Since my patch set is now a month old, I'll rebase onto current master
and post a version 3 patch set.
Jim
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
2019-01-29 3:11 ` [Qemu-riscv] " Jim Wilson
@ 2019-01-29 23:21 ` Palmer Dabbelt
-1 siblings, 0 replies; 38+ messages in thread
From: Palmer Dabbelt @ 2019-01-29 23:21 UTC (permalink / raw)
To: Jim Wilson; +Cc: alistair23, qemu-riscv, qemu-devel
On Mon, 28 Jan 2019 19:11:58 PST (-0800), Jim Wilson wrote:
> On Tue, Jan 22, 2019 at 1:52 PM Alistair Francis <alistair23@gmail.com> wrote:
>> You can get env and then check for floating point support:
>>
>> CPURISCVState *env = &cs->env;
>> if (env->misa_mask & RVF) {
>> ...
>
> I needed this which wasn't hard to figure out.
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> if (env->misa & RVF) {
>
> The tricky bit was figuring out how to test it, because I wasn't sure
> if making registers conditional would actually work. I figured out
> that using -machine sifive_e gives me a target with no fpu, and
> playing with that a bit I get the expected result, which is that the
> FP regs don't print anymore. The FP related CSRs still do, but that
> would require gdb fixes I think, because gdb knows that they are both
> FP regs and CSR, and tries to print them both ways. That leads to a
> more general problem of figuring out exactly which CSRs a particular
> target implements, which is a bigger problem than I have time to fix
> at the moment, and should be handled as a separate problem.
>
> Since my patch set is now a month old, I'll rebase onto current master
> and post a version 3 patch set.
Thanks!
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files.
@ 2019-01-29 23:21 ` Palmer Dabbelt
0 siblings, 0 replies; 38+ messages in thread
From: Palmer Dabbelt @ 2019-01-29 23:21 UTC (permalink / raw)
To: Jim Wilson; +Cc: alistair23, qemu-riscv, qemu-devel
On Mon, 28 Jan 2019 19:11:58 PST (-0800), Jim Wilson wrote:
> On Tue, Jan 22, 2019 at 1:52 PM Alistair Francis <alistair23@gmail.com> wrote:
>> You can get env and then check for floating point support:
>>
>> CPURISCVState *env = &cs->env;
>> if (env->misa_mask & RVF) {
>> ...
>
> I needed this which wasn't hard to figure out.
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> if (env->misa & RVF) {
>
> The tricky bit was figuring out how to test it, because I wasn't sure
> if making registers conditional would actually work. I figured out
> that using -machine sifive_e gives me a target with no fpu, and
> playing with that a bit I get the expected result, which is that the
> FP regs don't print anymore. The FP related CSRs still do, but that
> would require gdb fixes I think, because gdb knows that they are both
> FP regs and CSR, and tries to print them both ways. That leads to a
> more general problem of figuring out exactly which CSRs a particular
> target implements, which is a bigger problem than I have time to fix
> at the moment, and should be handled as a separate problem.
>
> Since my patch set is now a month old, I'll rebase onto current master
> and post a version 3 patch set.
Thanks!
^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2019-01-29 23:21 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-12-28 22:05 [Qemu-devel] [PATCH 0/5 v2] RISC-V: Add gdb xml files and gdbstub support Jim Wilson
2018-12-28 22:05 ` [Qemu-riscv] " Jim Wilson
2018-12-28 22:07 ` [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files Jim Wilson
2018-12-28 22:07 ` [Qemu-riscv] " Jim Wilson
2018-12-29 22:20 ` [Qemu-devel] " Richard Henderson
2018-12-29 22:20 ` [Qemu-riscv] " Richard Henderson
2018-12-30 19:56 ` Jim Wilson
2018-12-30 19:56 ` [Qemu-riscv] " Jim Wilson
2019-01-22 21:53 ` Alistair Francis
2019-01-22 21:53 ` [Qemu-riscv] " Alistair Francis
2018-12-28 22:08 ` [Qemu-devel] [PATCH 2/5 v2] RISC-V: Add 64-bit " Jim Wilson
2018-12-28 22:08 ` [Qemu-riscv] " Jim Wilson
2019-01-22 21:53 ` [Qemu-devel] " Alistair Francis
2019-01-22 21:53 ` [Qemu-riscv] " Alistair Francis
2018-12-28 22:09 ` [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers Jim Wilson
2018-12-28 22:09 ` [Qemu-riscv] " Jim Wilson
2018-12-29 22:23 ` [Qemu-devel] " Richard Henderson
2018-12-29 22:23 ` [Qemu-riscv] " Richard Henderson
2018-12-30 19:22 ` Jim Wilson
2018-12-30 19:22 ` [Qemu-riscv] " Jim Wilson
2019-01-22 21:45 ` Alistair Francis
2019-01-22 21:45 ` [Qemu-riscv] " Alistair Francis
2019-01-29 3:00 ` Jim Wilson
2019-01-29 3:00 ` [Qemu-riscv] " Jim Wilson
2018-12-28 22:10 ` [Qemu-devel] [PATCH 4/5 v2] RISC-V: Add debug support for accessing CSRs Jim Wilson
2018-12-28 22:10 ` [Qemu-riscv] " Jim Wilson
2018-12-29 22:25 ` [Qemu-devel] " Richard Henderson
2018-12-29 22:25 ` [Qemu-riscv] " Richard Henderson
2019-01-22 21:46 ` Alistair Francis
2019-01-22 21:46 ` [Qemu-riscv] " Alistair Francis
2018-12-28 22:11 ` [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files Jim Wilson
2018-12-28 22:11 ` [Qemu-riscv] " Jim Wilson
2019-01-22 21:52 ` [Qemu-devel] " Alistair Francis
2019-01-22 21:52 ` [Qemu-riscv] " Alistair Francis
2019-01-29 3:11 ` Jim Wilson
2019-01-29 3:11 ` [Qemu-riscv] " Jim Wilson
2019-01-29 23:21 ` Palmer Dabbelt
2019-01-29 23:21 ` [Qemu-riscv] " Palmer Dabbelt
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