From: Lucas De Marchi <lucas.de.marchi@gmail.com> To: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michel Thierry <michel.thierry@intel.com>, intel-gfx <intel-gfx@lists.freedesktop.org> Subject: Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Date: Tue, 26 Nov 2019 01:38:20 -0800 [thread overview] Message-ID: <CAKi4VAKNfh5uriVmi6H7wev3XhwMrGrArsaqrGWHJ=qa=vZuzw@mail.gmail.com> (raw) In-Reply-To: <157441498323.2524.12613965179682887118@skylake-alporthouse-com> On Fri, Nov 22, 2019 at 1:30 AM Chris Wilson <chris@chris-wilson.co.uk> wrote: > > Quoting Tvrtko Ursulin (2019-11-22 09:21:45) > > > > On 22/11/2019 04:02, Ramalingam C wrote: > > > @@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, > > > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > > > struct i915_wa_list *wal) > > > { > > > + u32 val; > > > + > > > /* Wa_1409142259:tgl */ > > > WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, > > > GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); > > > + > > > + /* Wa_1604555607:tgl */ > > > + val = intel_uncore_read(engine->uncore, FF_MODE2); > > > + val &= ~FF_MODE2_TDS_TIMER_MASK; > > > + val |= FF_MODE2_TDS_TIMER_128; > > > + /* > > > + * FIXME: FF_MODE2 register is not readable till TGL B0. We can > > > + * enable verification of WA from the later steppings, which enables > > > + * the read of FF_MODE2. > > > + */ > > > + __wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0); > > > > If I was a betting man I'd bet no one will ever remember to add the > > verification back. So I have to say I disagree with Lucas on this point. > > Someone do a casting vote please. :) > > I would go with IS_TGL_REVID(A0, A0) as we expect it to be picked up by then it is broken from start? In A2 it's not fixed yet.... not sure if CI has A2. But we should add at least A2 and A3 and make it pass on these. Lucas De Marchi > the selftests if we have a new stepping that is unfixed -- and a blip in > CI is a much clearer reminder to come back and revisit this code. We > should be able to go "oops, live_workarounds is red, failing on ctx:0xf00" > and from there find this fixme. And so update for a new stepping in the > course of a day (because that's how long it takes for CI to approve a > patch). > -Chris > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Lucas De Marchi _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Lucas De Marchi <lucas.de.marchi@gmail.com> To: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michel Thierry <michel.thierry@intel.com>, intel-gfx <intel-gfx@lists.freedesktop.org> Subject: Re: [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Date: Tue, 26 Nov 2019 01:38:20 -0800 [thread overview] Message-ID: <CAKi4VAKNfh5uriVmi6H7wev3XhwMrGrArsaqrGWHJ=qa=vZuzw@mail.gmail.com> (raw) Message-ID: <20191126093820.FpcKzI3lLVWk7mJw-0_52CdZiWJDBGARESTi0LHJt50@z> (raw) In-Reply-To: <157441498323.2524.12613965179682887118@skylake-alporthouse-com> On Fri, Nov 22, 2019 at 1:30 AM Chris Wilson <chris@chris-wilson.co.uk> wrote: > > Quoting Tvrtko Ursulin (2019-11-22 09:21:45) > > > > On 22/11/2019 04:02, Ramalingam C wrote: > > > @@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, > > > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > > > struct i915_wa_list *wal) > > > { > > > + u32 val; > > > + > > > /* Wa_1409142259:tgl */ > > > WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, > > > GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); > > > + > > > + /* Wa_1604555607:tgl */ > > > + val = intel_uncore_read(engine->uncore, FF_MODE2); > > > + val &= ~FF_MODE2_TDS_TIMER_MASK; > > > + val |= FF_MODE2_TDS_TIMER_128; > > > + /* > > > + * FIXME: FF_MODE2 register is not readable till TGL B0. We can > > > + * enable verification of WA from the later steppings, which enables > > > + * the read of FF_MODE2. > > > + */ > > > + __wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0); > > > > If I was a betting man I'd bet no one will ever remember to add the > > verification back. So I have to say I disagree with Lucas on this point. > > Someone do a casting vote please. :) > > I would go with IS_TGL_REVID(A0, A0) as we expect it to be picked up by then it is broken from start? In A2 it's not fixed yet.... not sure if CI has A2. But we should add at least A2 and A3 and make it pass on these. Lucas De Marchi > the selftests if we have a new stepping that is unfixed -- and a blip in > CI is a much clearer reminder to come back and revisit this code. We > should be able to go "oops, live_workarounds is red, failing on ctx:0xf00" > and from there find this fixme. And so update for a new stepping in the > course of a day (because that's how long it takes for CI to approve a > patch). > -Chris > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Lucas De Marchi _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-26 9:38 UTC|newest] Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-22 4:02 [PATCH 0/1] Wa_1604555607 implementation and verification skip Ramalingam C 2019-11-22 4:02 ` [Intel-gfx] " Ramalingam C 2019-11-22 4:02 ` [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C 2019-11-22 4:02 ` [Intel-gfx] " Ramalingam C 2019-11-22 9:21 ` Tvrtko Ursulin 2019-11-22 9:21 ` [Intel-gfx] " Tvrtko Ursulin 2019-11-22 9:29 ` Chris Wilson 2019-11-22 9:29 ` [Intel-gfx] " Chris Wilson 2019-11-26 8:00 ` Ramalingam C 2019-11-26 8:00 ` [Intel-gfx] " Ramalingam C 2019-11-26 9:38 ` Lucas De Marchi [this message] 2019-11-26 9:38 ` Lucas De Marchi 2019-11-26 10:10 ` Ramalingam C 2019-11-26 10:10 ` [Intel-gfx] " Ramalingam C 2019-11-22 4:46 ` ✓ Fi.CI.BAT: success for Wa_1604555607 implementation and verification skip (rev6) Patchwork 2019-11-22 4:46 ` [Intel-gfx] " Patchwork 2019-11-23 11:45 ` ✓ Fi.CI.IGT: " Patchwork 2019-11-23 11:45 ` [Intel-gfx] " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2019-11-21 10:12 [PATCH 0/1] Wa_1604555607 implementation and verification skip Ramalingam C 2019-11-21 10:12 ` [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C 2019-11-21 10:19 ` Chris Wilson 2019-11-21 10:51 ` Ramalingam C 2019-11-21 10:19 ` Tvrtko Ursulin 2019-11-21 11:12 ` Ramalingam C 2019-11-21 18:29 ` Lucas De Marchi 2019-11-22 3:27 ` Ramalingam C
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to='CAKi4VAKNfh5uriVmi6H7wev3XhwMrGrArsaqrGWHJ=qa=vZuzw@mail.gmail.com' \ --to=lucas.de.marchi@gmail.com \ --cc=chris@chris-wilson.co.uk \ --cc=intel-gfx@lists.freedesktop.org \ --cc=michel.thierry@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.