* [PATCH v2 0/5] Dedicated CLINT timer driver
@ 2020-06-27 16:19 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-06-27 16:19 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner
Cc: Damien Le Moal, Atish Patra, Alistair Francis, Anup Patel,
linux-riscv, linux-kernel, devicetree, Anup Patel
The current RISC-V timer driver is convoluted and implements two
distinct timers:
1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The
clocksource is implemented using TIME CSR and clockevent device
is implemented using SBI Timer calls.
2. M-mode timer: This is for Linux RISC-V M-mode without MMU. The
clocksource is implemented using CLINT MMIO time register and
clockevent device is implemented using CLINT MMIO timecmp registers.
This patchset removes clint related code from RISC-V timer driver and
arch/riscv directory. Instead, the series adds a dedicated MMIO based
CLINT driver under drivers/clocksource directory which can be used by
Linux RISC-V M-mode (i.e NoMMU Linux RISC-V).
The patchset is based up Linux-5.8-rc2 and can be found at riscv_clint_v2
branch of: https://github.com/avpatel/linux.git
This series is tested on:
1. QEMU RV64 virt machine using Linux RISC-V S-mode
2. QEMU RV32 virt machine using Linux RISC-V S-mode
3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU)
Changes since v1:
- Rebased series on Linux-5.8-rc2
- Added pr_warn() for case where ipi_ops not available in PATCH1
- Updated ipi_inject() prototype to use "struct cpumask *" in PATCH1
- Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4
- Added riscv,clint0 compatible string in DT bindings document
Anup Patel (5):
RISC-V: Add mechanism to provide custom IPI operations
RISC-V: Remove CLINT related code
clocksource/drivers/timer-riscv: Remove MMIO related stuff
clocksource/drivers: Add CLINT timer driver
dt-bindings: timer: Add CLINT bindings
.../bindings/timer/sifive,clint.txt | 34 +++
arch/riscv/Kconfig | 2 +-
arch/riscv/include/asm/clint.h | 39 ---
arch/riscv/include/asm/smp.h | 11 +
arch/riscv/include/asm/timex.h | 28 +--
arch/riscv/kernel/Makefile | 2 +-
arch/riscv/kernel/clint.c | 44 ----
arch/riscv/kernel/sbi.c | 14 ++
arch/riscv/kernel/setup.c | 2 -
arch/riscv/kernel/smp.c | 44 ++--
arch/riscv/kernel/smpboot.c | 4 +-
drivers/clocksource/Kconfig | 12 +-
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++
drivers/clocksource/timer-riscv.c | 17 +-
include/linux/cpuhotplug.h | 1 +
16 files changed, 337 insertions(+), 147 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
delete mode 100644 arch/riscv/include/asm/clint.h
delete mode 100644 arch/riscv/kernel/clint.c
create mode 100644 drivers/clocksource/timer-clint.c
--
2.25.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 0/5] Dedicated CLINT timer driver
@ 2020-06-27 16:19 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-06-27 16:19 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner
Cc: devicetree, Damien Le Moal, Anup Patel, Anup Patel, linux-kernel,
Atish Patra, Alistair Francis, linux-riscv
The current RISC-V timer driver is convoluted and implements two
distinct timers:
1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The
clocksource is implemented using TIME CSR and clockevent device
is implemented using SBI Timer calls.
2. M-mode timer: This is for Linux RISC-V M-mode without MMU. The
clocksource is implemented using CLINT MMIO time register and
clockevent device is implemented using CLINT MMIO timecmp registers.
This patchset removes clint related code from RISC-V timer driver and
arch/riscv directory. Instead, the series adds a dedicated MMIO based
CLINT driver under drivers/clocksource directory which can be used by
Linux RISC-V M-mode (i.e NoMMU Linux RISC-V).
The patchset is based up Linux-5.8-rc2 and can be found at riscv_clint_v2
branch of: https://github.com/avpatel/linux.git
This series is tested on:
1. QEMU RV64 virt machine using Linux RISC-V S-mode
2. QEMU RV32 virt machine using Linux RISC-V S-mode
3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU)
Changes since v1:
- Rebased series on Linux-5.8-rc2
- Added pr_warn() for case where ipi_ops not available in PATCH1
- Updated ipi_inject() prototype to use "struct cpumask *" in PATCH1
- Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4
- Added riscv,clint0 compatible string in DT bindings document
Anup Patel (5):
RISC-V: Add mechanism to provide custom IPI operations
RISC-V: Remove CLINT related code
clocksource/drivers/timer-riscv: Remove MMIO related stuff
clocksource/drivers: Add CLINT timer driver
dt-bindings: timer: Add CLINT bindings
.../bindings/timer/sifive,clint.txt | 34 +++
arch/riscv/Kconfig | 2 +-
arch/riscv/include/asm/clint.h | 39 ---
arch/riscv/include/asm/smp.h | 11 +
arch/riscv/include/asm/timex.h | 28 +--
arch/riscv/kernel/Makefile | 2 +-
arch/riscv/kernel/clint.c | 44 ----
arch/riscv/kernel/sbi.c | 14 ++
arch/riscv/kernel/setup.c | 2 -
arch/riscv/kernel/smp.c | 44 ++--
arch/riscv/kernel/smpboot.c | 4 +-
drivers/clocksource/Kconfig | 12 +-
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++
drivers/clocksource/timer-riscv.c | 17 +-
include/linux/cpuhotplug.h | 1 +
16 files changed, 337 insertions(+), 147 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
delete mode 100644 arch/riscv/include/asm/clint.h
delete mode 100644 arch/riscv/kernel/clint.c
create mode 100644 drivers/clocksource/timer-clint.c
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 1/5] RISC-V: Add mechanism to provide custom IPI operations
2020-06-27 16:19 ` Anup Patel
@ 2020-06-27 16:19 ` Anup Patel
-1 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-06-27 16:19 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner
Cc: Damien Le Moal, Atish Patra, Alistair Francis, Anup Patel,
linux-riscv, linux-kernel, devicetree, Anup Patel
We add mechanism to set custom IPI operations so that CLINT driver
from drivers directory can provide custom IPI operations.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/include/asm/smp.h | 11 +++++++++
arch/riscv/kernel/sbi.c | 14 ++++++++++++
arch/riscv/kernel/smp.c | 43 ++++++++++++++++++++----------------
arch/riscv/kernel/smpboot.c | 3 +--
4 files changed, 50 insertions(+), 21 deletions(-)
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 40bb1c15a731..c6acd44767c1 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -40,6 +40,17 @@ void arch_send_call_function_single_ipi(int cpu);
int riscv_hartid_to_cpuid(int hartid);
void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out);
+struct riscv_ipi_ops {
+ void (*ipi_inject)(const struct cpumask *target);
+ void (*ipi_clear)(void);
+};
+
+/* Set custom IPI operations */
+void riscv_set_ipi_ops(struct riscv_ipi_ops *ops);
+
+/* Clear IPI for current CPU */
+void riscv_clear_ipi(void);
+
/*
* Obtains the hart ID of the currently executing task. This relies on
* THREAD_INFO_IN_TASK, but we define that unconditionally.
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index f383ef5672b2..226ccce0f9e0 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -547,6 +547,18 @@ static inline long sbi_get_firmware_version(void)
return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION);
}
+static void sbi_send_cpumask_ipi(const struct cpumask *target)
+{
+ struct cpumask hartid_mask;
+
+ riscv_cpuid_to_hartid_mask(target, &hartid_mask);
+
+ sbi_send_ipi(cpumask_bits(&hartid_mask));
+}
+
+static struct riscv_ipi_ops sbi_ipi_ops = {
+ .ipi_inject = sbi_send_cpumask_ipi
+};
int __init sbi_init(void)
{
@@ -587,5 +599,7 @@ int __init sbi_init(void)
__sbi_rfence = __sbi_rfence_v01;
}
+ riscv_set_ipi_ops(&sbi_ipi_ops);
+
return 0;
}
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index b1d4f452f843..8b85683ce203 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -84,9 +84,25 @@ static void ipi_stop(void)
wait_for_interrupt();
}
+static struct riscv_ipi_ops *ipi_ops;
+
+void riscv_set_ipi_ops(struct riscv_ipi_ops *ops)
+{
+ ipi_ops = ops;
+}
+EXPORT_SYMBOL_GPL(riscv_set_ipi_ops);
+
+void riscv_clear_ipi(void)
+{
+ if (ipi_ops && ipi_ops->ipi_clear)
+ ipi_ops->ipi_clear();
+
+ csr_clear(CSR_IP, IE_SIE);
+}
+EXPORT_SYMBOL_GPL(riscv_clear_ipi);
+
static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
{
- struct cpumask hartid_mask;
int cpu;
smp_mb__before_atomic();
@@ -94,33 +110,22 @@ static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
set_bit(op, &ipi_data[cpu].bits);
smp_mb__after_atomic();
- riscv_cpuid_to_hartid_mask(mask, &hartid_mask);
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- sbi_send_ipi(cpumask_bits(&hartid_mask));
+ if (ipi_ops && ipi_ops->ipi_inject)
+ ipi_ops->ipi_inject(mask);
else
- clint_send_ipi_mask(mask);
+ pr_warn("SMP: IPI inject method not available\n");
}
static void send_ipi_single(int cpu, enum ipi_message_type op)
{
- int hartid = cpuid_to_hartid_map(cpu);
-
smp_mb__before_atomic();
set_bit(op, &ipi_data[cpu].bits);
smp_mb__after_atomic();
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- sbi_send_ipi(cpumask_bits(cpumask_of(hartid)));
- else
- clint_send_ipi_single(hartid);
-}
-
-static inline void clear_ipi(void)
-{
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- csr_clear(CSR_IP, IE_SIE);
+ if (ipi_ops && ipi_ops->ipi_inject)
+ ipi_ops->ipi_inject(cpumask_of(cpu));
else
- clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id()));
+ pr_warn("SMP: IPI inject method not available\n");
}
void handle_IPI(struct pt_regs *regs)
@@ -131,7 +136,7 @@ void handle_IPI(struct pt_regs *regs)
irq_enter();
- clear_ipi();
+ riscv_clear_ipi();
while (true) {
unsigned long ops;
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 4e9922790f6e..5fe849791bf0 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -147,8 +147,7 @@ asmlinkage __visible void smp_callin(void)
{
struct mm_struct *mm = &init_mm;
- if (!IS_ENABLED(CONFIG_RISCV_SBI))
- clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id()));
+ riscv_clear_ipi();
/* All kernel threads share the same mm context. */
mmgrab(mm);
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 1/5] RISC-V: Add mechanism to provide custom IPI operations
@ 2020-06-27 16:19 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-06-27 16:19 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner
Cc: devicetree, Damien Le Moal, Anup Patel, Anup Patel, linux-kernel,
Atish Patra, Alistair Francis, linux-riscv
We add mechanism to set custom IPI operations so that CLINT driver
from drivers directory can provide custom IPI operations.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/include/asm/smp.h | 11 +++++++++
arch/riscv/kernel/sbi.c | 14 ++++++++++++
arch/riscv/kernel/smp.c | 43 ++++++++++++++++++++----------------
arch/riscv/kernel/smpboot.c | 3 +--
4 files changed, 50 insertions(+), 21 deletions(-)
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 40bb1c15a731..c6acd44767c1 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -40,6 +40,17 @@ void arch_send_call_function_single_ipi(int cpu);
int riscv_hartid_to_cpuid(int hartid);
void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out);
+struct riscv_ipi_ops {
+ void (*ipi_inject)(const struct cpumask *target);
+ void (*ipi_clear)(void);
+};
+
+/* Set custom IPI operations */
+void riscv_set_ipi_ops(struct riscv_ipi_ops *ops);
+
+/* Clear IPI for current CPU */
+void riscv_clear_ipi(void);
+
/*
* Obtains the hart ID of the currently executing task. This relies on
* THREAD_INFO_IN_TASK, but we define that unconditionally.
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index f383ef5672b2..226ccce0f9e0 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -547,6 +547,18 @@ static inline long sbi_get_firmware_version(void)
return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION);
}
+static void sbi_send_cpumask_ipi(const struct cpumask *target)
+{
+ struct cpumask hartid_mask;
+
+ riscv_cpuid_to_hartid_mask(target, &hartid_mask);
+
+ sbi_send_ipi(cpumask_bits(&hartid_mask));
+}
+
+static struct riscv_ipi_ops sbi_ipi_ops = {
+ .ipi_inject = sbi_send_cpumask_ipi
+};
int __init sbi_init(void)
{
@@ -587,5 +599,7 @@ int __init sbi_init(void)
__sbi_rfence = __sbi_rfence_v01;
}
+ riscv_set_ipi_ops(&sbi_ipi_ops);
+
return 0;
}
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index b1d4f452f843..8b85683ce203 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -84,9 +84,25 @@ static void ipi_stop(void)
wait_for_interrupt();
}
+static struct riscv_ipi_ops *ipi_ops;
+
+void riscv_set_ipi_ops(struct riscv_ipi_ops *ops)
+{
+ ipi_ops = ops;
+}
+EXPORT_SYMBOL_GPL(riscv_set_ipi_ops);
+
+void riscv_clear_ipi(void)
+{
+ if (ipi_ops && ipi_ops->ipi_clear)
+ ipi_ops->ipi_clear();
+
+ csr_clear(CSR_IP, IE_SIE);
+}
+EXPORT_SYMBOL_GPL(riscv_clear_ipi);
+
static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
{
- struct cpumask hartid_mask;
int cpu;
smp_mb__before_atomic();
@@ -94,33 +110,22 @@ static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
set_bit(op, &ipi_data[cpu].bits);
smp_mb__after_atomic();
- riscv_cpuid_to_hartid_mask(mask, &hartid_mask);
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- sbi_send_ipi(cpumask_bits(&hartid_mask));
+ if (ipi_ops && ipi_ops->ipi_inject)
+ ipi_ops->ipi_inject(mask);
else
- clint_send_ipi_mask(mask);
+ pr_warn("SMP: IPI inject method not available\n");
}
static void send_ipi_single(int cpu, enum ipi_message_type op)
{
- int hartid = cpuid_to_hartid_map(cpu);
-
smp_mb__before_atomic();
set_bit(op, &ipi_data[cpu].bits);
smp_mb__after_atomic();
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- sbi_send_ipi(cpumask_bits(cpumask_of(hartid)));
- else
- clint_send_ipi_single(hartid);
-}
-
-static inline void clear_ipi(void)
-{
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- csr_clear(CSR_IP, IE_SIE);
+ if (ipi_ops && ipi_ops->ipi_inject)
+ ipi_ops->ipi_inject(cpumask_of(cpu));
else
- clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id()));
+ pr_warn("SMP: IPI inject method not available\n");
}
void handle_IPI(struct pt_regs *regs)
@@ -131,7 +136,7 @@ void handle_IPI(struct pt_regs *regs)
irq_enter();
- clear_ipi();
+ riscv_clear_ipi();
while (true) {
unsigned long ops;
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 4e9922790f6e..5fe849791bf0 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -147,8 +147,7 @@ asmlinkage __visible void smp_callin(void)
{
struct mm_struct *mm = &init_mm;
- if (!IS_ENABLED(CONFIG_RISCV_SBI))
- clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id()));
+ riscv_clear_ipi();
/* All kernel threads share the same mm context. */
mmgrab(mm);
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 2/5] RISC-V: Remove CLINT related code
2020-06-27 16:19 ` Anup Patel
@ 2020-06-27 16:19 ` Anup Patel
-1 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-06-27 16:19 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner
Cc: Damien Le Moal, Atish Patra, Alistair Francis, Anup Patel,
linux-riscv, linux-kernel, devicetree, Anup Patel
We will be having separate CLINT timer driver which will also
provide CLINT based IPI operations so let's remove CLINT related
code from arch/riscv directory.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/include/asm/clint.h | 39 ------------------------------
arch/riscv/kernel/Makefile | 2 +-
arch/riscv/kernel/clint.c | 44 ----------------------------------
arch/riscv/kernel/setup.c | 2 --
arch/riscv/kernel/smp.c | 1 -
arch/riscv/kernel/smpboot.c | 1 -
6 files changed, 1 insertion(+), 88 deletions(-)
delete mode 100644 arch/riscv/include/asm/clint.h
delete mode 100644 arch/riscv/kernel/clint.c
diff --git a/arch/riscv/include/asm/clint.h b/arch/riscv/include/asm/clint.h
deleted file mode 100644
index a279b17a6aad..000000000000
--- a/arch/riscv/include/asm/clint.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_RISCV_CLINT_H
-#define _ASM_RISCV_CLINT_H 1
-
-#include <linux/io.h>
-#include <linux/smp.h>
-
-#ifdef CONFIG_RISCV_M_MODE
-extern u32 __iomem *clint_ipi_base;
-
-void clint_init_boot_cpu(void);
-
-static inline void clint_send_ipi_single(unsigned long hartid)
-{
- writel(1, clint_ipi_base + hartid);
-}
-
-static inline void clint_send_ipi_mask(const struct cpumask *mask)
-{
- int cpu;
-
- for_each_cpu(cpu, mask)
- clint_send_ipi_single(cpuid_to_hartid_map(cpu));
-}
-
-static inline void clint_clear_ipi(unsigned long hartid)
-{
- writel(0, clint_ipi_base + hartid);
-}
-#else /* CONFIG_RISCV_M_MODE */
-#define clint_init_boot_cpu() do { } while (0)
-
-/* stubs to for code is only reachable under IS_ENABLED(CONFIG_RISCV_M_MODE): */
-void clint_send_ipi_single(unsigned long hartid);
-void clint_send_ipi_mask(const struct cpumask *hartid_mask);
-void clint_clear_ipi(unsigned long hartid);
-#endif /* CONFIG_RISCV_M_MODE */
-
-#endif /* _ASM_RISCV_CLINT_H */
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index b355cf485671..7edf15643146 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -31,7 +31,7 @@ obj-y += cacheinfo.o
obj-y += patch.o
obj-$(CONFIG_MMU) += vdso.o vdso/
-obj-$(CONFIG_RISCV_M_MODE) += clint.o traps_misaligned.o
+obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o
obj-$(CONFIG_FPU) += fpu.o
obj-$(CONFIG_SMP) += smpboot.o
obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/riscv/kernel/clint.c b/arch/riscv/kernel/clint.c
deleted file mode 100644
index 3647980d14c3..000000000000
--- a/arch/riscv/kernel/clint.c
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2019 Christoph Hellwig.
- */
-
-#include <linux/io.h>
-#include <linux/of_address.h>
-#include <linux/types.h>
-#include <asm/clint.h>
-#include <asm/csr.h>
-#include <asm/timex.h>
-#include <asm/smp.h>
-
-/*
- * This is the layout used by the SiFive clint, which is also shared by the qemu
- * virt platform, and the Kendryte KD210 at least.
- */
-#define CLINT_IPI_OFF 0
-#define CLINT_TIME_CMP_OFF 0x4000
-#define CLINT_TIME_VAL_OFF 0xbff8
-
-u32 __iomem *clint_ipi_base;
-
-void clint_init_boot_cpu(void)
-{
- struct device_node *np;
- void __iomem *base;
-
- np = of_find_compatible_node(NULL, NULL, "riscv,clint0");
- if (!np) {
- panic("clint not found");
- return;
- }
-
- base = of_iomap(np, 0);
- if (!base)
- panic("could not map CLINT");
-
- clint_ipi_base = base + CLINT_IPI_OFF;
- riscv_time_cmp = base + CLINT_TIME_CMP_OFF;
- riscv_time_val = base + CLINT_TIME_VAL_OFF;
-
- clint_clear_ipi(boot_cpu_hartid);
-}
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index f04373be54a6..2c6dd329312b 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -18,7 +18,6 @@
#include <linux/swiotlb.h>
#include <linux/smp.h>
-#include <asm/clint.h>
#include <asm/cpu_ops.h>
#include <asm/setup.h>
#include <asm/sections.h>
@@ -79,7 +78,6 @@ void __init setup_arch(char **cmdline_p)
#else
unflatten_device_tree();
#endif
- clint_init_boot_cpu();
#ifdef CONFIG_SWIOTLB
swiotlb_init(1);
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 8b85683ce203..07626be78c23 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -17,7 +17,6 @@
#include <linux/seq_file.h>
#include <linux/delay.h>
-#include <asm/clint.h>
#include <asm/sbi.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 5fe849791bf0..a6cfa9842d4b 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -24,7 +24,6 @@
#include <linux/of.h>
#include <linux/sched/task_stack.h>
#include <linux/sched/mm.h>
-#include <asm/clint.h>
#include <asm/cpu_ops.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 2/5] RISC-V: Remove CLINT related code
@ 2020-06-27 16:19 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-06-27 16:19 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner
Cc: devicetree, Damien Le Moal, Anup Patel, Anup Patel, linux-kernel,
Atish Patra, Alistair Francis, linux-riscv
We will be having separate CLINT timer driver which will also
provide CLINT based IPI operations so let's remove CLINT related
code from arch/riscv directory.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/include/asm/clint.h | 39 ------------------------------
arch/riscv/kernel/Makefile | 2 +-
arch/riscv/kernel/clint.c | 44 ----------------------------------
arch/riscv/kernel/setup.c | 2 --
arch/riscv/kernel/smp.c | 1 -
arch/riscv/kernel/smpboot.c | 1 -
6 files changed, 1 insertion(+), 88 deletions(-)
delete mode 100644 arch/riscv/include/asm/clint.h
delete mode 100644 arch/riscv/kernel/clint.c
diff --git a/arch/riscv/include/asm/clint.h b/arch/riscv/include/asm/clint.h
deleted file mode 100644
index a279b17a6aad..000000000000
--- a/arch/riscv/include/asm/clint.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_RISCV_CLINT_H
-#define _ASM_RISCV_CLINT_H 1
-
-#include <linux/io.h>
-#include <linux/smp.h>
-
-#ifdef CONFIG_RISCV_M_MODE
-extern u32 __iomem *clint_ipi_base;
-
-void clint_init_boot_cpu(void);
-
-static inline void clint_send_ipi_single(unsigned long hartid)
-{
- writel(1, clint_ipi_base + hartid);
-}
-
-static inline void clint_send_ipi_mask(const struct cpumask *mask)
-{
- int cpu;
-
- for_each_cpu(cpu, mask)
- clint_send_ipi_single(cpuid_to_hartid_map(cpu));
-}
-
-static inline void clint_clear_ipi(unsigned long hartid)
-{
- writel(0, clint_ipi_base + hartid);
-}
-#else /* CONFIG_RISCV_M_MODE */
-#define clint_init_boot_cpu() do { } while (0)
-
-/* stubs to for code is only reachable under IS_ENABLED(CONFIG_RISCV_M_MODE): */
-void clint_send_ipi_single(unsigned long hartid);
-void clint_send_ipi_mask(const struct cpumask *hartid_mask);
-void clint_clear_ipi(unsigned long hartid);
-#endif /* CONFIG_RISCV_M_MODE */
-
-#endif /* _ASM_RISCV_CLINT_H */
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index b355cf485671..7edf15643146 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -31,7 +31,7 @@ obj-y += cacheinfo.o
obj-y += patch.o
obj-$(CONFIG_MMU) += vdso.o vdso/
-obj-$(CONFIG_RISCV_M_MODE) += clint.o traps_misaligned.o
+obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o
obj-$(CONFIG_FPU) += fpu.o
obj-$(CONFIG_SMP) += smpboot.o
obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/riscv/kernel/clint.c b/arch/riscv/kernel/clint.c
deleted file mode 100644
index 3647980d14c3..000000000000
--- a/arch/riscv/kernel/clint.c
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2019 Christoph Hellwig.
- */
-
-#include <linux/io.h>
-#include <linux/of_address.h>
-#include <linux/types.h>
-#include <asm/clint.h>
-#include <asm/csr.h>
-#include <asm/timex.h>
-#include <asm/smp.h>
-
-/*
- * This is the layout used by the SiFive clint, which is also shared by the qemu
- * virt platform, and the Kendryte KD210 at least.
- */
-#define CLINT_IPI_OFF 0
-#define CLINT_TIME_CMP_OFF 0x4000
-#define CLINT_TIME_VAL_OFF 0xbff8
-
-u32 __iomem *clint_ipi_base;
-
-void clint_init_boot_cpu(void)
-{
- struct device_node *np;
- void __iomem *base;
-
- np = of_find_compatible_node(NULL, NULL, "riscv,clint0");
- if (!np) {
- panic("clint not found");
- return;
- }
-
- base = of_iomap(np, 0);
- if (!base)
- panic("could not map CLINT");
-
- clint_ipi_base = base + CLINT_IPI_OFF;
- riscv_time_cmp = base + CLINT_TIME_CMP_OFF;
- riscv_time_val = base + CLINT_TIME_VAL_OFF;
-
- clint_clear_ipi(boot_cpu_hartid);
-}
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index f04373be54a6..2c6dd329312b 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -18,7 +18,6 @@
#include <linux/swiotlb.h>
#include <linux/smp.h>
-#include <asm/clint.h>
#include <asm/cpu_ops.h>
#include <asm/setup.h>
#include <asm/sections.h>
@@ -79,7 +78,6 @@ void __init setup_arch(char **cmdline_p)
#else
unflatten_device_tree();
#endif
- clint_init_boot_cpu();
#ifdef CONFIG_SWIOTLB
swiotlb_init(1);
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 8b85683ce203..07626be78c23 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -17,7 +17,6 @@
#include <linux/seq_file.h>
#include <linux/delay.h>
-#include <asm/clint.h>
#include <asm/sbi.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 5fe849791bf0..a6cfa9842d4b 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -24,7 +24,6 @@
#include <linux/of.h>
#include <linux/sched/task_stack.h>
#include <linux/sched/mm.h>
-#include <asm/clint.h>
#include <asm/cpu_ops.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 3/5] clocksource/drivers/timer-riscv: Remove MMIO related stuff
2020-06-27 16:19 ` Anup Patel
@ 2020-06-27 16:19 ` Anup Patel
-1 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-06-27 16:19 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner
Cc: Damien Le Moal, Atish Patra, Alistair Francis, Anup Patel,
linux-riscv, linux-kernel, devicetree, Anup Patel
Right now the RISC-V timer is convoluted to support:
1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR
for clocksource and SBI timer calls for clockevent device.
2. Linux RISC-V M-mode (without MMU) where it will use CLINT
MMIO counter register for clocksource and CLINT MMIO compare
register for clockevent device.
This patch removes MMIO related stuff from RISC-V timer driver
so that we can have a separate CLINT timer driver.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/Kconfig | 2 +-
arch/riscv/include/asm/timex.h | 28 +++++++---------------------
drivers/clocksource/Kconfig | 2 +-
drivers/clocksource/timer-riscv.c | 17 ++---------------
4 files changed, 11 insertions(+), 38 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 448a9952aa2f..868bbc4d0803 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -72,7 +72,7 @@ config RISCV
select PCI_DOMAINS_GENERIC if PCI
select PCI_MSI if PCI
select RISCV_INTC
- select RISCV_TIMER
+ select RISCV_TIMER if RISCV_SBI
select SPARSEMEM_STATIC if 32BIT
select SPARSE_IRQ
select SYSCTL_EXCEPTION_TRACE
diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
index bad2a7c2cda5..a3fb85d505d4 100644
--- a/arch/riscv/include/asm/timex.h
+++ b/arch/riscv/include/asm/timex.h
@@ -7,41 +7,27 @@
#define _ASM_RISCV_TIMEX_H
#include <asm/csr.h>
-#include <asm/mmio.h>
typedef unsigned long cycles_t;
-extern u64 __iomem *riscv_time_val;
-extern u64 __iomem *riscv_time_cmp;
-
-#ifdef CONFIG_64BIT
-#define mmio_get_cycles() readq_relaxed(riscv_time_val)
-#else
-#define mmio_get_cycles() readl_relaxed(riscv_time_val)
-#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1)
-#endif
-
static inline cycles_t get_cycles(void)
{
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- return csr_read(CSR_TIME);
- return mmio_get_cycles();
+ return csr_read(CSR_TIME);
}
#define get_cycles get_cycles
+static inline u32 get_cycles_hi(void)
+{
+ return csr_read(CSR_TIMEH);
+}
+#define get_cycles_hi get_cycles_hi
+
#ifdef CONFIG_64BIT
static inline u64 get_cycles64(void)
{
return get_cycles();
}
#else /* CONFIG_64BIT */
-static inline u32 get_cycles_hi(void)
-{
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- return csr_read(CSR_TIMEH);
- return mmio_get_cycles_hi();
-}
-
static inline u64 get_cycles64(void)
{
u32 hi, lo;
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 91418381fcd4..8c6a0f1274af 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -649,7 +649,7 @@ config ATCPIT100_TIMER
config RISCV_TIMER
bool "Timer for the RISC-V platform"
- depends on GENERIC_SCHED_CLOCK && RISCV
+ depends on GENERIC_SCHED_CLOCK && RISCV_SBI
default y
select TIMER_PROBE
select TIMER_OF
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 9de1dabfb126..c51c5ed15aa7 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -19,26 +19,13 @@
#include <linux/of_irq.h>
#include <asm/smp.h>
#include <asm/sbi.h>
-
-u64 __iomem *riscv_time_cmp;
-u64 __iomem *riscv_time_val;
-
-static inline void mmio_set_timer(u64 val)
-{
- void __iomem *r;
-
- r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id());
- writeq_relaxed(val, r);
-}
+#include <asm/timex.h>
static int riscv_clock_next_event(unsigned long delta,
struct clock_event_device *ce)
{
csr_set(CSR_IE, IE_TIE);
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- sbi_set_timer(get_cycles64() + delta);
- else
- mmio_set_timer(get_cycles64() + delta);
+ sbi_set_timer(get_cycles64() + delta);
return 0;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 3/5] clocksource/drivers/timer-riscv: Remove MMIO related stuff
@ 2020-06-27 16:19 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-06-27 16:19 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner
Cc: devicetree, Damien Le Moal, Anup Patel, Anup Patel, linux-kernel,
Atish Patra, Alistair Francis, linux-riscv
Right now the RISC-V timer is convoluted to support:
1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR
for clocksource and SBI timer calls for clockevent device.
2. Linux RISC-V M-mode (without MMU) where it will use CLINT
MMIO counter register for clocksource and CLINT MMIO compare
register for clockevent device.
This patch removes MMIO related stuff from RISC-V timer driver
so that we can have a separate CLINT timer driver.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/Kconfig | 2 +-
arch/riscv/include/asm/timex.h | 28 +++++++---------------------
drivers/clocksource/Kconfig | 2 +-
drivers/clocksource/timer-riscv.c | 17 ++---------------
4 files changed, 11 insertions(+), 38 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 448a9952aa2f..868bbc4d0803 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -72,7 +72,7 @@ config RISCV
select PCI_DOMAINS_GENERIC if PCI
select PCI_MSI if PCI
select RISCV_INTC
- select RISCV_TIMER
+ select RISCV_TIMER if RISCV_SBI
select SPARSEMEM_STATIC if 32BIT
select SPARSE_IRQ
select SYSCTL_EXCEPTION_TRACE
diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
index bad2a7c2cda5..a3fb85d505d4 100644
--- a/arch/riscv/include/asm/timex.h
+++ b/arch/riscv/include/asm/timex.h
@@ -7,41 +7,27 @@
#define _ASM_RISCV_TIMEX_H
#include <asm/csr.h>
-#include <asm/mmio.h>
typedef unsigned long cycles_t;
-extern u64 __iomem *riscv_time_val;
-extern u64 __iomem *riscv_time_cmp;
-
-#ifdef CONFIG_64BIT
-#define mmio_get_cycles() readq_relaxed(riscv_time_val)
-#else
-#define mmio_get_cycles() readl_relaxed(riscv_time_val)
-#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1)
-#endif
-
static inline cycles_t get_cycles(void)
{
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- return csr_read(CSR_TIME);
- return mmio_get_cycles();
+ return csr_read(CSR_TIME);
}
#define get_cycles get_cycles
+static inline u32 get_cycles_hi(void)
+{
+ return csr_read(CSR_TIMEH);
+}
+#define get_cycles_hi get_cycles_hi
+
#ifdef CONFIG_64BIT
static inline u64 get_cycles64(void)
{
return get_cycles();
}
#else /* CONFIG_64BIT */
-static inline u32 get_cycles_hi(void)
-{
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- return csr_read(CSR_TIMEH);
- return mmio_get_cycles_hi();
-}
-
static inline u64 get_cycles64(void)
{
u32 hi, lo;
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 91418381fcd4..8c6a0f1274af 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -649,7 +649,7 @@ config ATCPIT100_TIMER
config RISCV_TIMER
bool "Timer for the RISC-V platform"
- depends on GENERIC_SCHED_CLOCK && RISCV
+ depends on GENERIC_SCHED_CLOCK && RISCV_SBI
default y
select TIMER_PROBE
select TIMER_OF
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 9de1dabfb126..c51c5ed15aa7 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -19,26 +19,13 @@
#include <linux/of_irq.h>
#include <asm/smp.h>
#include <asm/sbi.h>
-
-u64 __iomem *riscv_time_cmp;
-u64 __iomem *riscv_time_val;
-
-static inline void mmio_set_timer(u64 val)
-{
- void __iomem *r;
-
- r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id());
- writeq_relaxed(val, r);
-}
+#include <asm/timex.h>
static int riscv_clock_next_event(unsigned long delta,
struct clock_event_device *ce)
{
csr_set(CSR_IE, IE_TIE);
- if (IS_ENABLED(CONFIG_RISCV_SBI))
- sbi_set_timer(get_cycles64() + delta);
- else
- mmio_set_timer(get_cycles64() + delta);
+ sbi_set_timer(get_cycles64() + delta);
return 0;
}
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 4/5] clocksource/drivers: Add CLINT timer driver
2020-06-27 16:19 ` Anup Patel
@ 2020-06-27 16:19 ` Anup Patel
-1 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-06-27 16:19 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner
Cc: Damien Le Moal, Atish Patra, Alistair Francis, Anup Patel,
linux-riscv, linux-kernel, devicetree, Anup Patel
The TIME CSR and SBI calls are not available in RISC-V M-mode so we
add CLINT driver for Linux RISC-V M-mode (i.e. RISC-V NoMMU kernel).
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
4 files changed, 241 insertions(+)
create mode 100644 drivers/clocksource/timer-clint.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8c6a0f1274af..d3bf66123c4e 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -658,6 +658,16 @@ config RISCV_TIMER
is accessed via both the SBI and the rdcycle instruction. This is
required for all RISC-V systems.
+config CLINT_TIMER
+ bool "Timer for the RISC-V platform"
+ depends on GENERIC_SCHED_CLOCK && RISCV_M_MODE
+ default y
+ select TIMER_PROBE
+ select TIMER_OF
+ help
+ This option enables the CLINT timer for RISC-V systems. The CLINT
+ driver is usually used for NoMMU RISC-V systems.
+
config CSKY_MP_TIMER
bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
depends on CSKY
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index bdda1a2e4097..18e700e703a0 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
obj-$(CONFIG_X86_NUMACHIP) += numachip.o
obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o
obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
+obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o
diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
new file mode 100644
index 000000000000..e5c36d49bfdd
--- /dev/null
+++ b/drivers/clocksource/timer-clint.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
+ * CLINT MMIO timer device.
+ */
+
+#define pr_fmt(fmt) "clint: " fmt
+#include <linux/bitops.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/cpu.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/sched_clock.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/interrupt.h>
+#include <linux/of_irq.h>
+#include <linux/smp.h>
+
+#define CLINT_IPI_OFF 0
+#define CLINT_TIMER_CMP_OFF 0x4000
+#define CLINT_TIMER_VAL_OFF 0xbff8
+
+/* CLINT manages IPI and Timer for RISC-V M-mode */
+static u32 __iomem *clint_ipi_base;
+static u64 __iomem *clint_timer_cmp;
+static u64 __iomem *clint_timer_val;
+static unsigned long clint_timer_freq;
+static unsigned int clint_timer_irq;
+
+static void clint_send_ipi(const struct cpumask *target)
+{
+ unsigned int cpu;
+
+ for_each_cpu(cpu, target)
+ writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
+}
+
+static void clint_clear_ipi(void)
+{
+ writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
+}
+
+static struct riscv_ipi_ops clint_ipi_ops = {
+ .ipi_inject = clint_send_ipi,
+ .ipi_clear = clint_clear_ipi,
+};
+
+#ifdef CONFIG_64BIT
+#define clint_get_cycles() readq_relaxed(clint_timer_val)
+#else
+#define clint_get_cycles() readl_relaxed(clint_timer_val)
+#define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_timer_val) + 1)
+#endif
+
+#ifdef CONFIG_64BIT
+static u64 clint_get_cycles64(void)
+{
+ return clint_get_cycles();
+}
+#else /* CONFIG_64BIT */
+static u64 clint_get_cycles64(void)
+{
+ u32 hi, lo;
+
+ do {
+ hi = clint_get_cycles_hi();
+ lo = clint_get_cycles();
+ } while (hi != clint_get_cycles_hi());
+
+ return ((u64)hi << 32) | lo;
+}
+#endif /* CONFIG_64BIT */
+
+static int clint_clock_next_event(unsigned long delta,
+ struct clock_event_device *ce)
+{
+ void __iomem *r = clint_timer_cmp +
+ cpuid_to_hartid_map(smp_processor_id());
+
+ csr_set(CSR_IE, IE_TIE);
+ writeq_relaxed(clint_get_cycles64() + delta, r);
+ return 0;
+}
+
+static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = {
+ .name = "clint_clockevent",
+ .features = CLOCK_EVT_FEAT_ONESHOT,
+ .rating = 100,
+ .set_next_event = clint_clock_next_event,
+};
+
+static u64 clint_rdtime(struct clocksource *cs)
+{
+ return readq_relaxed(clint_timer_val);
+}
+
+static u64 notrace clint_sched_clock(void)
+{
+ return readq_relaxed(clint_timer_val);
+}
+
+static struct clocksource clint_clocksource = {
+ .name = "clint_clocksource",
+ .rating = 300,
+ .mask = CLOCKSOURCE_MASK(64),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+ .read = clint_rdtime,
+};
+
+static int clint_timer_starting_cpu(unsigned int cpu)
+{
+ struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
+
+ ce->cpumask = cpumask_of(cpu);
+ clockevents_config_and_register(ce, clint_timer_freq, 200, ULONG_MAX);
+
+ enable_percpu_irq(clint_timer_irq,
+ irq_get_trigger_type(clint_timer_irq));
+ return 0;
+}
+
+static int clint_timer_dying_cpu(unsigned int cpu)
+{
+ disable_percpu_irq(clint_timer_irq);
+ return 0;
+}
+
+static irqreturn_t clint_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evdev = this_cpu_ptr(&clint_clock_event);
+
+ csr_clear(CSR_IE, IE_TIE);
+ evdev->event_handler(evdev);
+
+ return IRQ_HANDLED;
+}
+
+static int __init clint_timer_init_dt(struct device_node *np)
+{
+ int rc;
+ u32 i, nr_irqs;
+ void __iomem *base;
+ struct of_phandle_args oirq;
+
+ /*
+ * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or
+ * RV_IRQ_SOFT. If it's anything else then we ignore the device.
+ */
+ nr_irqs = of_irq_count(np);
+ for (i = 0; i < nr_irqs; i++) {
+ if (of_irq_parse_one(np, i, &oirq)) {
+ pr_err("%pOFP: failed to parse irq %d.\n", np, i);
+ continue;
+ }
+
+ if ((oirq.args_count != 1) ||
+ (oirq.args[0] != RV_IRQ_TIMER &&
+ oirq.args[0] != RV_IRQ_SOFT)) {
+ pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
+ np, i, oirq.args[0]);
+ return -ENODEV;
+ }
+
+ /* Find parent irq domain and map timer irq */
+ if (!clint_timer_irq &&
+ oirq.args[0] == RV_IRQ_TIMER &&
+ irq_find_host(oirq.np))
+ clint_timer_irq = irq_of_parse_and_map(np, i);
+ }
+
+ /* If CLINT timer irq not found then fail */
+ if (!clint_timer_irq) {
+ pr_err("%pOFP: timer irq not found\n", np);
+ return -ENODEV;
+ }
+
+ base = of_iomap(np, 0);
+ if (!base) {
+ pr_err("%pOFP: could not map registers\n", np);
+ return -ENODEV;
+ }
+
+ clint_ipi_base = base + CLINT_IPI_OFF;
+ clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
+ clint_timer_val = base + CLINT_TIMER_VAL_OFF;
+ clint_timer_freq = riscv_timebase;
+
+ pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq);
+
+ rc = clocksource_register_hz(&clint_clocksource, clint_timer_freq);
+ if (rc) {
+ iounmap(base);
+ pr_err("%pOFP: clocksource register failed [%d]\n", np, rc);
+ return rc;
+ }
+
+ sched_clock_register(clint_sched_clock, 64, clint_timer_freq);
+
+ rc = request_percpu_irq(clint_timer_irq, clint_timer_interrupt,
+ "clint-timer", &clint_clock_event);
+ if (rc) {
+ iounmap(base);
+ pr_err("registering percpu irq failed [%d]\n", rc);
+ return rc;
+ }
+
+ rc = cpuhp_setup_state(CPUHP_AP_CLINT_TIMER_STARTING,
+ "clockevents/clint/timer:starting",
+ clint_timer_starting_cpu,
+ clint_timer_dying_cpu);
+ if (rc) {
+ free_irq(clint_timer_irq, &clint_clock_event);
+ iounmap(base);
+ pr_err("%pOFP: cpuhp setup state failed [%d]\n", np, rc);
+ return rc;
+ }
+
+ riscv_set_ipi_ops(&clint_ipi_ops);
+ clint_clear_ipi();
+
+ return 0;
+}
+
+TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
+TIMER_OF_DECLARE(clint_timer1, "sifive,clint-1.0.0", clint_timer_init_dt);
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 191772d4a4d7..1451f4625833 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -132,6 +132,7 @@ enum cpuhp_state {
CPUHP_AP_MIPS_GIC_TIMER_STARTING,
CPUHP_AP_ARC_TIMER_STARTING,
CPUHP_AP_RISCV_TIMER_STARTING,
+ CPUHP_AP_CLINT_TIMER_STARTING,
CPUHP_AP_CSKY_TIMER_STARTING,
CPUHP_AP_HYPERV_TIMER_STARTING,
CPUHP_AP_KVM_STARTING,
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 4/5] clocksource/drivers: Add CLINT timer driver
@ 2020-06-27 16:19 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-06-27 16:19 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner
Cc: devicetree, Damien Le Moal, Anup Patel, Anup Patel, linux-kernel,
Atish Patra, Alistair Francis, linux-riscv
The TIME CSR and SBI calls are not available in RISC-V M-mode so we
add CLINT driver for Linux RISC-V M-mode (i.e. RISC-V NoMMU kernel).
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
drivers/clocksource/Kconfig | 10 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
4 files changed, 241 insertions(+)
create mode 100644 drivers/clocksource/timer-clint.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8c6a0f1274af..d3bf66123c4e 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -658,6 +658,16 @@ config RISCV_TIMER
is accessed via both the SBI and the rdcycle instruction. This is
required for all RISC-V systems.
+config CLINT_TIMER
+ bool "Timer for the RISC-V platform"
+ depends on GENERIC_SCHED_CLOCK && RISCV_M_MODE
+ default y
+ select TIMER_PROBE
+ select TIMER_OF
+ help
+ This option enables the CLINT timer for RISC-V systems. The CLINT
+ driver is usually used for NoMMU RISC-V systems.
+
config CSKY_MP_TIMER
bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
depends on CSKY
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index bdda1a2e4097..18e700e703a0 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
obj-$(CONFIG_X86_NUMACHIP) += numachip.o
obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o
obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
+obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o
diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
new file mode 100644
index 000000000000..e5c36d49bfdd
--- /dev/null
+++ b/drivers/clocksource/timer-clint.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
+ * CLINT MMIO timer device.
+ */
+
+#define pr_fmt(fmt) "clint: " fmt
+#include <linux/bitops.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/cpu.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/sched_clock.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/interrupt.h>
+#include <linux/of_irq.h>
+#include <linux/smp.h>
+
+#define CLINT_IPI_OFF 0
+#define CLINT_TIMER_CMP_OFF 0x4000
+#define CLINT_TIMER_VAL_OFF 0xbff8
+
+/* CLINT manages IPI and Timer for RISC-V M-mode */
+static u32 __iomem *clint_ipi_base;
+static u64 __iomem *clint_timer_cmp;
+static u64 __iomem *clint_timer_val;
+static unsigned long clint_timer_freq;
+static unsigned int clint_timer_irq;
+
+static void clint_send_ipi(const struct cpumask *target)
+{
+ unsigned int cpu;
+
+ for_each_cpu(cpu, target)
+ writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
+}
+
+static void clint_clear_ipi(void)
+{
+ writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
+}
+
+static struct riscv_ipi_ops clint_ipi_ops = {
+ .ipi_inject = clint_send_ipi,
+ .ipi_clear = clint_clear_ipi,
+};
+
+#ifdef CONFIG_64BIT
+#define clint_get_cycles() readq_relaxed(clint_timer_val)
+#else
+#define clint_get_cycles() readl_relaxed(clint_timer_val)
+#define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_timer_val) + 1)
+#endif
+
+#ifdef CONFIG_64BIT
+static u64 clint_get_cycles64(void)
+{
+ return clint_get_cycles();
+}
+#else /* CONFIG_64BIT */
+static u64 clint_get_cycles64(void)
+{
+ u32 hi, lo;
+
+ do {
+ hi = clint_get_cycles_hi();
+ lo = clint_get_cycles();
+ } while (hi != clint_get_cycles_hi());
+
+ return ((u64)hi << 32) | lo;
+}
+#endif /* CONFIG_64BIT */
+
+static int clint_clock_next_event(unsigned long delta,
+ struct clock_event_device *ce)
+{
+ void __iomem *r = clint_timer_cmp +
+ cpuid_to_hartid_map(smp_processor_id());
+
+ csr_set(CSR_IE, IE_TIE);
+ writeq_relaxed(clint_get_cycles64() + delta, r);
+ return 0;
+}
+
+static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = {
+ .name = "clint_clockevent",
+ .features = CLOCK_EVT_FEAT_ONESHOT,
+ .rating = 100,
+ .set_next_event = clint_clock_next_event,
+};
+
+static u64 clint_rdtime(struct clocksource *cs)
+{
+ return readq_relaxed(clint_timer_val);
+}
+
+static u64 notrace clint_sched_clock(void)
+{
+ return readq_relaxed(clint_timer_val);
+}
+
+static struct clocksource clint_clocksource = {
+ .name = "clint_clocksource",
+ .rating = 300,
+ .mask = CLOCKSOURCE_MASK(64),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+ .read = clint_rdtime,
+};
+
+static int clint_timer_starting_cpu(unsigned int cpu)
+{
+ struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
+
+ ce->cpumask = cpumask_of(cpu);
+ clockevents_config_and_register(ce, clint_timer_freq, 200, ULONG_MAX);
+
+ enable_percpu_irq(clint_timer_irq,
+ irq_get_trigger_type(clint_timer_irq));
+ return 0;
+}
+
+static int clint_timer_dying_cpu(unsigned int cpu)
+{
+ disable_percpu_irq(clint_timer_irq);
+ return 0;
+}
+
+static irqreturn_t clint_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evdev = this_cpu_ptr(&clint_clock_event);
+
+ csr_clear(CSR_IE, IE_TIE);
+ evdev->event_handler(evdev);
+
+ return IRQ_HANDLED;
+}
+
+static int __init clint_timer_init_dt(struct device_node *np)
+{
+ int rc;
+ u32 i, nr_irqs;
+ void __iomem *base;
+ struct of_phandle_args oirq;
+
+ /*
+ * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or
+ * RV_IRQ_SOFT. If it's anything else then we ignore the device.
+ */
+ nr_irqs = of_irq_count(np);
+ for (i = 0; i < nr_irqs; i++) {
+ if (of_irq_parse_one(np, i, &oirq)) {
+ pr_err("%pOFP: failed to parse irq %d.\n", np, i);
+ continue;
+ }
+
+ if ((oirq.args_count != 1) ||
+ (oirq.args[0] != RV_IRQ_TIMER &&
+ oirq.args[0] != RV_IRQ_SOFT)) {
+ pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
+ np, i, oirq.args[0]);
+ return -ENODEV;
+ }
+
+ /* Find parent irq domain and map timer irq */
+ if (!clint_timer_irq &&
+ oirq.args[0] == RV_IRQ_TIMER &&
+ irq_find_host(oirq.np))
+ clint_timer_irq = irq_of_parse_and_map(np, i);
+ }
+
+ /* If CLINT timer irq not found then fail */
+ if (!clint_timer_irq) {
+ pr_err("%pOFP: timer irq not found\n", np);
+ return -ENODEV;
+ }
+
+ base = of_iomap(np, 0);
+ if (!base) {
+ pr_err("%pOFP: could not map registers\n", np);
+ return -ENODEV;
+ }
+
+ clint_ipi_base = base + CLINT_IPI_OFF;
+ clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
+ clint_timer_val = base + CLINT_TIMER_VAL_OFF;
+ clint_timer_freq = riscv_timebase;
+
+ pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq);
+
+ rc = clocksource_register_hz(&clint_clocksource, clint_timer_freq);
+ if (rc) {
+ iounmap(base);
+ pr_err("%pOFP: clocksource register failed [%d]\n", np, rc);
+ return rc;
+ }
+
+ sched_clock_register(clint_sched_clock, 64, clint_timer_freq);
+
+ rc = request_percpu_irq(clint_timer_irq, clint_timer_interrupt,
+ "clint-timer", &clint_clock_event);
+ if (rc) {
+ iounmap(base);
+ pr_err("registering percpu irq failed [%d]\n", rc);
+ return rc;
+ }
+
+ rc = cpuhp_setup_state(CPUHP_AP_CLINT_TIMER_STARTING,
+ "clockevents/clint/timer:starting",
+ clint_timer_starting_cpu,
+ clint_timer_dying_cpu);
+ if (rc) {
+ free_irq(clint_timer_irq, &clint_clock_event);
+ iounmap(base);
+ pr_err("%pOFP: cpuhp setup state failed [%d]\n", np, rc);
+ return rc;
+ }
+
+ riscv_set_ipi_ops(&clint_ipi_ops);
+ clint_clear_ipi();
+
+ return 0;
+}
+
+TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
+TIMER_OF_DECLARE(clint_timer1, "sifive,clint-1.0.0", clint_timer_init_dt);
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 191772d4a4d7..1451f4625833 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -132,6 +132,7 @@ enum cpuhp_state {
CPUHP_AP_MIPS_GIC_TIMER_STARTING,
CPUHP_AP_ARC_TIMER_STARTING,
CPUHP_AP_RISCV_TIMER_STARTING,
+ CPUHP_AP_CLINT_TIMER_STARTING,
CPUHP_AP_CSKY_TIMER_STARTING,
CPUHP_AP_HYPERV_TIMER_STARTING,
CPUHP_AP_KVM_STARTING,
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings
2020-06-27 16:19 ` Anup Patel
@ 2020-06-27 16:19 ` Anup Patel
-1 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-06-27 16:19 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner
Cc: Damien Le Moal, Atish Patra, Alistair Francis, Anup Patel,
linux-riscv, linux-kernel, devicetree, Anup Patel,
Palmer Dabbelt
We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
.../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt
new file mode 100644
index 000000000000..45b75347a7d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt
@@ -0,0 +1,34 @@
+SiFive Core Local Interruptor (CLINT)
+-------------------------------------
+
+SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core
+Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts.
+
+It directly connects to the timer and inter-processor interrupt lines of
+various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt
+controller is the parent interrupt controller for CLINT device.
+
+The clock frequency of CLINT is specified via "timebase-frequency" DT
+property of "/cpus" DT node. The "timebase-frequency" DT property is
+described in: Documentation/devicetree/bindings/riscv/cpus.yaml
+
+Required properties:
+- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific
+ string identifying the actual implementation can be added if implementation
+ specific worked arounds are needed.
+- reg : Should contain 1 register range (address and length).
+- interrupts-extended : Specifies which HARTs (or CPUs) are connected to
+ the CLINT. Each node pointed to should be a riscv,cpu-intc node, which
+ has a riscv node as parent.
+
+Example:
+
+ clint@2000000 {
+ compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint";
+ interrupts-extended = <
+ &cpu1-intc 3 &cpu1-intc 7
+ &cpu2-intc 3 &cpu2-intc 7
+ &cpu3-intc 3 &cpu3-intc 7
+ &cpu4-intc 3 &cpu4-intc 7>;
+ reg = <0x2000000 0x4000000>;
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings
@ 2020-06-27 16:19 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-06-27 16:19 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner
Cc: devicetree, Damien Le Moal, Palmer Dabbelt, Anup Patel,
Anup Patel, linux-kernel, Atish Patra, Alistair Francis,
linux-riscv
We add DT bindings documentation for CLINT device.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
.../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt
new file mode 100644
index 000000000000..45b75347a7d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt
@@ -0,0 +1,34 @@
+SiFive Core Local Interruptor (CLINT)
+-------------------------------------
+
+SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core
+Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts.
+
+It directly connects to the timer and inter-processor interrupt lines of
+various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt
+controller is the parent interrupt controller for CLINT device.
+
+The clock frequency of CLINT is specified via "timebase-frequency" DT
+property of "/cpus" DT node. The "timebase-frequency" DT property is
+described in: Documentation/devicetree/bindings/riscv/cpus.yaml
+
+Required properties:
+- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific
+ string identifying the actual implementation can be added if implementation
+ specific worked arounds are needed.
+- reg : Should contain 1 register range (address and length).
+- interrupts-extended : Specifies which HARTs (or CPUs) are connected to
+ the CLINT. Each node pointed to should be a riscv,cpu-intc node, which
+ has a riscv node as parent.
+
+Example:
+
+ clint@2000000 {
+ compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint";
+ interrupts-extended = <
+ &cpu1-intc 3 &cpu1-intc 7
+ &cpu2-intc 3 &cpu2-intc 7
+ &cpu3-intc 3 &cpu3-intc 7
+ &cpu4-intc 3 &cpu4-intc 7>;
+ reg = <0x2000000 0x4000000>;
+ };
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v2 3/5] clocksource/drivers/timer-riscv: Remove MMIO related stuff
2020-06-27 16:19 ` Anup Patel
(?)
@ 2020-06-29 16:03 ` kernel test robot
-1 siblings, 0 replies; 24+ messages in thread
From: kernel test robot @ 2020-06-29 16:03 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 4620 bytes --]
Hi Anup,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.8-rc3 next-20200629]
[cannot apply to tip/timers/core]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Anup-Patel/Dedicated-CLINT-timer-driver/20200628-002253
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: riscv-randconfig-r036-20200629 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project a28d38a6bca1726d56c9b373f4c7dc5264fc7716)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/hwtracing/stm/core.c:717:22: error: implicit declaration of function 'pgprot_noncached' [-Werror,-Wimplicit-function-declaration]
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
^
>> drivers/hwtracing/stm/core.c:717:20: error: assigning to 'pgprot_t' from incompatible type 'int'
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2 errors generated.
vim +/pgprot_noncached +717 drivers/hwtracing/stm/core.c
8e0469a4f3e647 Alexander Shishkin 2016-06-28 690
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 691 static int stm_char_mmap(struct file *file, struct vm_area_struct *vma)
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 692 {
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 693 struct stm_file *stmf = file->private_data;
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 694 struct stm_device *stm = stmf->stm;
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 695 unsigned long size, phys;
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 696
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 697 if (!stm->data->mmio_addr)
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 698 return -EOPNOTSUPP;
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 699
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 700 if (vma->vm_pgoff)
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 701 return -EINVAL;
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 702
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 703 size = vma->vm_end - vma->vm_start;
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 704
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 705 if (stmf->output.nr_chans * stm->data->sw_mmiosz != size)
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 706 return -EINVAL;
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 707
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 708 phys = stm->data->mmio_addr(stm->data, stmf->output.master,
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 709 stmf->output.channel,
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 710 stmf->output.nr_chans);
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 711
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 712 if (!phys)
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 713 return -EINVAL;
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 714
8e0469a4f3e647 Alexander Shishkin 2016-06-28 715 pm_runtime_get_sync(&stm->dev);
8e0469a4f3e647 Alexander Shishkin 2016-06-28 716
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 @717 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 718 vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
8e0469a4f3e647 Alexander Shishkin 2016-06-28 719 vma->vm_ops = &stm_mmap_vmops;
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 720 vm_iomap_memory(vma, phys, size);
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 721
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 722 return 0;
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 723 }
7bd1d4093c2fa3 Alexander Shishkin 2015-09-22 724
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 26096 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 4/5] clocksource/drivers: Add CLINT timer driver
2020-06-27 16:19 ` Anup Patel
(?)
@ 2020-06-29 17:44 ` kernel test robot
-1 siblings, 0 replies; 24+ messages in thread
From: kernel test robot @ 2020-06-29 17:44 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 14191 bytes --]
Hi Anup,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.8-rc3 next-20200629]
[cannot apply to tip/timers/core]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Anup-Patel/Dedicated-CLINT-timer-driver/20200628-002253
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: riscv-randconfig-r036-20200629 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project a28d38a6bca1726d56c9b373f4c7dc5264fc7716)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from drivers/clocksource/timer-clint.c:11:
In file included from include/linux/clocksource.h:21:
In file included from arch/riscv/include/asm/io.h:148:
include/asm-generic/io.h:556:9: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
return inb(addr);
^~~~~~~~~
arch/riscv/include/asm/io.h:54:76: note: expanded from macro 'inb'
#define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
~~~~~~~~~~ ^
arch/riscv/include/asm/mmio.h:93:48: note: expanded from macro 'readb_cpu'
#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
^
In file included from drivers/clocksource/timer-clint.c:11:
In file included from include/linux/clocksource.h:21:
In file included from arch/riscv/include/asm/io.h:148:
include/asm-generic/io.h:564:9: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
return inw(addr);
^~~~~~~~~
arch/riscv/include/asm/io.h:55:76: note: expanded from macro 'inw'
#define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
~~~~~~~~~~ ^
arch/riscv/include/asm/mmio.h:94:76: note: expanded from macro 'readw_cpu'
#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
^
include/uapi/linux/byteorder/little_endian.h:36:51: note: expanded from macro '__le16_to_cpu'
#define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
^
In file included from drivers/clocksource/timer-clint.c:11:
In file included from include/linux/clocksource.h:21:
In file included from arch/riscv/include/asm/io.h:148:
include/asm-generic/io.h:572:9: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
return inl(addr);
^~~~~~~~~
arch/riscv/include/asm/io.h:56:76: note: expanded from macro 'inl'
#define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
~~~~~~~~~~ ^
arch/riscv/include/asm/mmio.h:95:76: note: expanded from macro 'readl_cpu'
#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
^
include/uapi/linux/byteorder/little_endian.h:34:51: note: expanded from macro '__le32_to_cpu'
#define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
^
In file included from drivers/clocksource/timer-clint.c:11:
In file included from include/linux/clocksource.h:21:
In file included from arch/riscv/include/asm/io.h:148:
include/asm-generic/io.h:580:2: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
outb(value, addr);
^~~~~~~~~~~~~~~~~
arch/riscv/include/asm/io.h:58:68: note: expanded from macro 'outb'
#define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
~~~~~~~~~~ ^
arch/riscv/include/asm/mmio.h:97:52: note: expanded from macro 'writeb_cpu'
#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c)))
^
In file included from drivers/clocksource/timer-clint.c:11:
In file included from include/linux/clocksource.h:21:
In file included from arch/riscv/include/asm/io.h:148:
include/asm-generic/io.h:588:2: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
outw(value, addr);
^~~~~~~~~~~~~~~~~
arch/riscv/include/asm/io.h:59:68: note: expanded from macro 'outw'
#define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
~~~~~~~~~~ ^
arch/riscv/include/asm/mmio.h:98:76: note: expanded from macro 'writew_cpu'
#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
^
In file included from drivers/clocksource/timer-clint.c:11:
In file included from include/linux/clocksource.h:21:
In file included from arch/riscv/include/asm/io.h:148:
include/asm-generic/io.h:596:2: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
outl(value, addr);
^~~~~~~~~~~~~~~~~
arch/riscv/include/asm/io.h:60:68: note: expanded from macro 'outl'
#define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
~~~~~~~~~~ ^
arch/riscv/include/asm/mmio.h:99:76: note: expanded from macro 'writel_cpu'
#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
^
In file included from drivers/clocksource/timer-clint.c:11:
In file included from include/linux/clocksource.h:21:
In file included from arch/riscv/include/asm/io.h:148:
include/asm-generic/io.h:1017:55: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port;
~~~~~~~~~~ ^
>> drivers/clocksource/timer-clint.c:47:29: error: variable has incomplete type 'struct riscv_ipi_ops'
static struct riscv_ipi_ops clint_ipi_ops = {
^
drivers/clocksource/timer-clint.c:47:15: note: forward declaration of 'struct riscv_ipi_ops'
static struct riscv_ipi_ops clint_ipi_ops = {
^
>> drivers/clocksource/timer-clint.c:222:2: error: implicit declaration of function 'riscv_set_ipi_ops' [-Werror,-Wimplicit-function-declaration]
riscv_set_ipi_ops(&clint_ipi_ops);
^
7 warnings and 2 errors generated.
vim +47 drivers/clocksource/timer-clint.c
46
> 47 static struct riscv_ipi_ops clint_ipi_ops = {
48 .ipi_inject = clint_send_ipi,
49 .ipi_clear = clint_clear_ipi,
50 };
51
52 #ifdef CONFIG_64BIT
53 #define clint_get_cycles() readq_relaxed(clint_timer_val)
54 #else
55 #define clint_get_cycles() readl_relaxed(clint_timer_val)
56 #define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_timer_val) + 1)
57 #endif
58
59 #ifdef CONFIG_64BIT
60 static u64 clint_get_cycles64(void)
61 {
62 return clint_get_cycles();
63 }
64 #else /* CONFIG_64BIT */
65 static u64 clint_get_cycles64(void)
66 {
67 u32 hi, lo;
68
69 do {
70 hi = clint_get_cycles_hi();
71 lo = clint_get_cycles();
72 } while (hi != clint_get_cycles_hi());
73
74 return ((u64)hi << 32) | lo;
75 }
76 #endif /* CONFIG_64BIT */
77
78 static int clint_clock_next_event(unsigned long delta,
79 struct clock_event_device *ce)
80 {
81 void __iomem *r = clint_timer_cmp +
82 cpuid_to_hartid_map(smp_processor_id());
83
84 csr_set(CSR_IE, IE_TIE);
85 writeq_relaxed(clint_get_cycles64() + delta, r);
86 return 0;
87 }
88
89 static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = {
90 .name = "clint_clockevent",
91 .features = CLOCK_EVT_FEAT_ONESHOT,
92 .rating = 100,
93 .set_next_event = clint_clock_next_event,
94 };
95
96 static u64 clint_rdtime(struct clocksource *cs)
97 {
98 return readq_relaxed(clint_timer_val);
99 }
100
101 static u64 notrace clint_sched_clock(void)
102 {
103 return readq_relaxed(clint_timer_val);
104 }
105
106 static struct clocksource clint_clocksource = {
107 .name = "clint_clocksource",
108 .rating = 300,
109 .mask = CLOCKSOURCE_MASK(64),
110 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
111 .read = clint_rdtime,
112 };
113
114 static int clint_timer_starting_cpu(unsigned int cpu)
115 {
116 struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
117
118 ce->cpumask = cpumask_of(cpu);
119 clockevents_config_and_register(ce, clint_timer_freq, 200, ULONG_MAX);
120
121 enable_percpu_irq(clint_timer_irq,
122 irq_get_trigger_type(clint_timer_irq));
123 return 0;
124 }
125
126 static int clint_timer_dying_cpu(unsigned int cpu)
127 {
128 disable_percpu_irq(clint_timer_irq);
129 return 0;
130 }
131
132 static irqreturn_t clint_timer_interrupt(int irq, void *dev_id)
133 {
134 struct clock_event_device *evdev = this_cpu_ptr(&clint_clock_event);
135
136 csr_clear(CSR_IE, IE_TIE);
137 evdev->event_handler(evdev);
138
139 return IRQ_HANDLED;
140 }
141
142 static int __init clint_timer_init_dt(struct device_node *np)
143 {
144 int rc;
145 u32 i, nr_irqs;
146 void __iomem *base;
147 struct of_phandle_args oirq;
148
149 /*
150 * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or
151 * RV_IRQ_SOFT. If it's anything else then we ignore the device.
152 */
153 nr_irqs = of_irq_count(np);
154 for (i = 0; i < nr_irqs; i++) {
155 if (of_irq_parse_one(np, i, &oirq)) {
156 pr_err("%pOFP: failed to parse irq %d.\n", np, i);
157 continue;
158 }
159
160 if ((oirq.args_count != 1) ||
161 (oirq.args[0] != RV_IRQ_TIMER &&
162 oirq.args[0] != RV_IRQ_SOFT)) {
163 pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
164 np, i, oirq.args[0]);
165 return -ENODEV;
166 }
167
168 /* Find parent irq domain and map timer irq */
169 if (!clint_timer_irq &&
170 oirq.args[0] == RV_IRQ_TIMER &&
171 irq_find_host(oirq.np))
172 clint_timer_irq = irq_of_parse_and_map(np, i);
173 }
174
175 /* If CLINT timer irq not found then fail */
176 if (!clint_timer_irq) {
177 pr_err("%pOFP: timer irq not found\n", np);
178 return -ENODEV;
179 }
180
181 base = of_iomap(np, 0);
182 if (!base) {
183 pr_err("%pOFP: could not map registers\n", np);
184 return -ENODEV;
185 }
186
187 clint_ipi_base = base + CLINT_IPI_OFF;
188 clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
189 clint_timer_val = base + CLINT_TIMER_VAL_OFF;
190 clint_timer_freq = riscv_timebase;
191
192 pr_info("%pOFP: timer running@%ld Hz\n", np, clint_timer_freq);
193
194 rc = clocksource_register_hz(&clint_clocksource, clint_timer_freq);
195 if (rc) {
196 iounmap(base);
197 pr_err("%pOFP: clocksource register failed [%d]\n", np, rc);
198 return rc;
199 }
200
201 sched_clock_register(clint_sched_clock, 64, clint_timer_freq);
202
203 rc = request_percpu_irq(clint_timer_irq, clint_timer_interrupt,
204 "clint-timer", &clint_clock_event);
205 if (rc) {
206 iounmap(base);
207 pr_err("registering percpu irq failed [%d]\n", rc);
208 return rc;
209 }
210
211 rc = cpuhp_setup_state(CPUHP_AP_CLINT_TIMER_STARTING,
212 "clockevents/clint/timer:starting",
213 clint_timer_starting_cpu,
214 clint_timer_dying_cpu);
215 if (rc) {
216 free_irq(clint_timer_irq, &clint_clock_event);
217 iounmap(base);
218 pr_err("%pOFP: cpuhp setup state failed [%d]\n", np, rc);
219 return rc;
220 }
221
> 222 riscv_set_ipi_ops(&clint_ipi_ops);
223 clint_clear_ipi();
224
225 return 0;
226 }
227
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 26101 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 0/5] Dedicated CLINT timer driver
2020-06-27 16:19 ` Anup Patel
@ 2020-07-13 23:02 ` Palmer Dabbelt
-1 siblings, 0 replies; 24+ messages in thread
From: Palmer Dabbelt @ 2020-07-13 23:02 UTC (permalink / raw)
To: Anup Patel
Cc: Paul Walmsley, aou, robh+dt, daniel.lezcano, tglx,
Damien Le Moal, Atish Patra, Alistair Francis, anup, linux-riscv,
linux-kernel, devicetree, Anup Patel
On Sat, 27 Jun 2020 09:19:52 PDT (-0700), Anup Patel wrote:
> The current RISC-V timer driver is convoluted and implements two
> distinct timers:
> 1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The
> clocksource is implemented using TIME CSR and clockevent device
> is implemented using SBI Timer calls.
> 2. M-mode timer: This is for Linux RISC-V M-mode without MMU. The
> clocksource is implemented using CLINT MMIO time register and
> clockevent device is implemented using CLINT MMIO timecmp registers.
>
> This patchset removes clint related code from RISC-V timer driver and
> arch/riscv directory. Instead, the series adds a dedicated MMIO based
> CLINT driver under drivers/clocksource directory which can be used by
> Linux RISC-V M-mode (i.e NoMMU Linux RISC-V).
>
> The patchset is based up Linux-5.8-rc2 and can be found at riscv_clint_v2
> branch of: https://github.com/avpatel/linux.git
>
> This series is tested on:
> 1. QEMU RV64 virt machine using Linux RISC-V S-mode
> 2. QEMU RV32 virt machine using Linux RISC-V S-mode
> 3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU)
>
> Changes since v1:
> - Rebased series on Linux-5.8-rc2
> - Added pr_warn() for case where ipi_ops not available in PATCH1
> - Updated ipi_inject() prototype to use "struct cpumask *" in PATCH1
> - Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4
> - Added riscv,clint0 compatible string in DT bindings document
>
> Anup Patel (5):
> RISC-V: Add mechanism to provide custom IPI operations
> RISC-V: Remove CLINT related code
> clocksource/drivers/timer-riscv: Remove MMIO related stuff
> clocksource/drivers: Add CLINT timer driver
> dt-bindings: timer: Add CLINT bindings
This all generally LGTM, though I haven't been through the code line-by-line
yet. It touches a bunch of trees, so I'd prefer to have some Acks before
merging -- I'll dig through the RISC-V specific stuff, but the new CLINT driver
probhably deserves a look from one of the clocksource folks.
I think the only issue is that the port will be broken between patch 2 and 4,
as at that point we won't have an M-mode timer driver. I think it shouldn't be
too much to just reorder these, LMK if you want to do it or you want me to.
Thanks!
>
> .../bindings/timer/sifive,clint.txt | 34 +++
> arch/riscv/Kconfig | 2 +-
> arch/riscv/include/asm/clint.h | 39 ---
> arch/riscv/include/asm/smp.h | 11 +
> arch/riscv/include/asm/timex.h | 28 +--
> arch/riscv/kernel/Makefile | 2 +-
> arch/riscv/kernel/clint.c | 44 ----
> arch/riscv/kernel/sbi.c | 14 ++
> arch/riscv/kernel/setup.c | 2 -
> arch/riscv/kernel/smp.c | 44 ++--
> arch/riscv/kernel/smpboot.c | 4 +-
> drivers/clocksource/Kconfig | 12 +-
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++
> drivers/clocksource/timer-riscv.c | 17 +-
> include/linux/cpuhotplug.h | 1 +
> 16 files changed, 337 insertions(+), 147 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
> delete mode 100644 arch/riscv/include/asm/clint.h
> delete mode 100644 arch/riscv/kernel/clint.c
> create mode 100644 drivers/clocksource/timer-clint.c
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 0/5] Dedicated CLINT timer driver
@ 2020-07-13 23:02 ` Palmer Dabbelt
0 siblings, 0 replies; 24+ messages in thread
From: Palmer Dabbelt @ 2020-07-13 23:02 UTC (permalink / raw)
To: Anup Patel
Cc: devicetree, Damien Le Moal, aou, anup, daniel.lezcano,
linux-kernel, Atish Patra, Anup Patel, robh+dt, Alistair Francis,
Paul Walmsley, tglx, linux-riscv
On Sat, 27 Jun 2020 09:19:52 PDT (-0700), Anup Patel wrote:
> The current RISC-V timer driver is convoluted and implements two
> distinct timers:
> 1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The
> clocksource is implemented using TIME CSR and clockevent device
> is implemented using SBI Timer calls.
> 2. M-mode timer: This is for Linux RISC-V M-mode without MMU. The
> clocksource is implemented using CLINT MMIO time register and
> clockevent device is implemented using CLINT MMIO timecmp registers.
>
> This patchset removes clint related code from RISC-V timer driver and
> arch/riscv directory. Instead, the series adds a dedicated MMIO based
> CLINT driver under drivers/clocksource directory which can be used by
> Linux RISC-V M-mode (i.e NoMMU Linux RISC-V).
>
> The patchset is based up Linux-5.8-rc2 and can be found at riscv_clint_v2
> branch of: https://github.com/avpatel/linux.git
>
> This series is tested on:
> 1. QEMU RV64 virt machine using Linux RISC-V S-mode
> 2. QEMU RV32 virt machine using Linux RISC-V S-mode
> 3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU)
>
> Changes since v1:
> - Rebased series on Linux-5.8-rc2
> - Added pr_warn() for case where ipi_ops not available in PATCH1
> - Updated ipi_inject() prototype to use "struct cpumask *" in PATCH1
> - Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4
> - Added riscv,clint0 compatible string in DT bindings document
>
> Anup Patel (5):
> RISC-V: Add mechanism to provide custom IPI operations
> RISC-V: Remove CLINT related code
> clocksource/drivers/timer-riscv: Remove MMIO related stuff
> clocksource/drivers: Add CLINT timer driver
> dt-bindings: timer: Add CLINT bindings
This all generally LGTM, though I haven't been through the code line-by-line
yet. It touches a bunch of trees, so I'd prefer to have some Acks before
merging -- I'll dig through the RISC-V specific stuff, but the new CLINT driver
probhably deserves a look from one of the clocksource folks.
I think the only issue is that the port will be broken between patch 2 and 4,
as at that point we won't have an M-mode timer driver. I think it shouldn't be
too much to just reorder these, LMK if you want to do it or you want me to.
Thanks!
>
> .../bindings/timer/sifive,clint.txt | 34 +++
> arch/riscv/Kconfig | 2 +-
> arch/riscv/include/asm/clint.h | 39 ---
> arch/riscv/include/asm/smp.h | 11 +
> arch/riscv/include/asm/timex.h | 28 +--
> arch/riscv/kernel/Makefile | 2 +-
> arch/riscv/kernel/clint.c | 44 ----
> arch/riscv/kernel/sbi.c | 14 ++
> arch/riscv/kernel/setup.c | 2 -
> arch/riscv/kernel/smp.c | 44 ++--
> arch/riscv/kernel/smpboot.c | 4 +-
> drivers/clocksource/Kconfig | 12 +-
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++
> drivers/clocksource/timer-riscv.c | 17 +-
> include/linux/cpuhotplug.h | 1 +
> 16 files changed, 337 insertions(+), 147 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
> delete mode 100644 arch/riscv/include/asm/clint.h
> delete mode 100644 arch/riscv/kernel/clint.c
> create mode 100644 drivers/clocksource/timer-clint.c
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings
2020-06-27 16:19 ` Anup Patel
@ 2020-07-14 2:37 ` Rob Herring
-1 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2020-07-14 2:37 UTC (permalink / raw)
To: Anup Patel
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Daniel Lezcano,
Thomas Gleixner, Damien Le Moal, Atish Patra, Alistair Francis,
Anup Patel, linux-riscv, linux-kernel, devicetree,
Palmer Dabbelt
On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote:
> We add DT bindings documentation for CLINT device.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> ---
> .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
Bindings should be in DT schema format now.
>
> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> new file mode 100644
> index 000000000000..45b75347a7d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> @@ -0,0 +1,34 @@
> +SiFive Core Local Interruptor (CLINT)
> +-------------------------------------
> +
> +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core
> +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts.
> +
> +It directly connects to the timer and inter-processor interrupt lines of
> +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt
> +controller is the parent interrupt controller for CLINT device.
> +
> +The clock frequency of CLINT is specified via "timebase-frequency" DT
> +property of "/cpus" DT node. The "timebase-frequency" DT property is
> +described in: Documentation/devicetree/bindings/riscv/cpus.yaml
> +
> +Required properties:
> +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific
A new versioning scheme from SiFive? To review, we don't do version
numbers unless there's a well defined and documented scheme. IOW, one
that's not s/w folks just making up v1, v2, v3, etc.
> + string identifying the actual implementation can be added if implementation
> + specific worked arounds are needed.
> +- reg : Should contain 1 register range (address and length).
> +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to
> + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which
> + has a riscv node as parent.
> +
> +Example:
> +
> + clint@2000000 {
> + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint";
Doesn't match the binding.
> + interrupts-extended = <
> + &cpu1-intc 3 &cpu1-intc 7
> + &cpu2-intc 3 &cpu2-intc 7
> + &cpu3-intc 3 &cpu3-intc 7
> + &cpu4-intc 3 &cpu4-intc 7>;
> + reg = <0x2000000 0x4000000>;
> + };
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings
@ 2020-07-14 2:37 ` Rob Herring
0 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2020-07-14 2:37 UTC (permalink / raw)
To: Anup Patel
Cc: devicetree, Damien Le Moal, Albert Ou, Anup Patel,
Daniel Lezcano, linux-kernel, Atish Patra, Palmer Dabbelt,
Paul Walmsley, Palmer Dabbelt, Alistair Francis, Thomas Gleixner,
linux-riscv
On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote:
> We add DT bindings documentation for CLINT device.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> ---
> .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
Bindings should be in DT schema format now.
>
> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> new file mode 100644
> index 000000000000..45b75347a7d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> @@ -0,0 +1,34 @@
> +SiFive Core Local Interruptor (CLINT)
> +-------------------------------------
> +
> +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core
> +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts.
> +
> +It directly connects to the timer and inter-processor interrupt lines of
> +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt
> +controller is the parent interrupt controller for CLINT device.
> +
> +The clock frequency of CLINT is specified via "timebase-frequency" DT
> +property of "/cpus" DT node. The "timebase-frequency" DT property is
> +described in: Documentation/devicetree/bindings/riscv/cpus.yaml
> +
> +Required properties:
> +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific
A new versioning scheme from SiFive? To review, we don't do version
numbers unless there's a well defined and documented scheme. IOW, one
that's not s/w folks just making up v1, v2, v3, etc.
> + string identifying the actual implementation can be added if implementation
> + specific worked arounds are needed.
> +- reg : Should contain 1 register range (address and length).
> +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to
> + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which
> + has a riscv node as parent.
> +
> +Example:
> +
> + clint@2000000 {
> + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint";
Doesn't match the binding.
> + interrupts-extended = <
> + &cpu1-intc 3 &cpu1-intc 7
> + &cpu2-intc 3 &cpu2-intc 7
> + &cpu3-intc 3 &cpu3-intc 7
> + &cpu4-intc 3 &cpu4-intc 7>;
> + reg = <0x2000000 0x4000000>;
> + };
> --
> 2.25.1
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings
2020-07-14 2:37 ` Rob Herring
@ 2020-07-14 3:47 ` Anup Patel
-1 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-07-14 3:47 UTC (permalink / raw)
To: Rob Herring
Cc: Anup Patel, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Daniel Lezcano, Thomas Gleixner, Damien Le Moal, Atish Patra,
Alistair Francis, linux-riscv, linux-kernel@vger.kernel.org List,
devicetree, Palmer Dabbelt
On Tue, Jul 14, 2020 at 8:07 AM Rob Herring <robh@kernel.org> wrote:
>
> On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote:
> > We add DT bindings documentation for CLINT device.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> > ---
> > .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
>
> Bindings should be in DT schema format now.
Okay, will update.
>
> >
> > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> > new file mode 100644
> > index 000000000000..45b75347a7d5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> > @@ -0,0 +1,34 @@
> > +SiFive Core Local Interruptor (CLINT)
> > +-------------------------------------
> > +
> > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core
> > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts.
> > +
> > +It directly connects to the timer and inter-processor interrupt lines of
> > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt
> > +controller is the parent interrupt controller for CLINT device.
> > +
> > +The clock frequency of CLINT is specified via "timebase-frequency" DT
> > +property of "/cpus" DT node. The "timebase-frequency" DT property is
> > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml
> > +
> > +Required properties:
> > +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific
>
> A new versioning scheme from SiFive? To review, we don't do version
> numbers unless there's a well defined and documented scheme. IOW, one
> that's not s/w folks just making up v1, v2, v3, etc.
The "riscv,clint0" is already used by various RISC-V systems (including QEMU).
The "sifive,clint-1.0.0" is for being consistent with the PLIC
versioning scheme.
There is no clear documentation of CLINT versioning scheme. I think it's best
to just drop "sifive,clint-1.0.0" . Agree ??
>
> > + string identifying the actual implementation can be added if implementation
> > + specific worked arounds are needed.
> > +- reg : Should contain 1 register range (address and length).
> > +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to
> > + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which
> > + has a riscv node as parent.
> > +
> > +Example:
> > +
> > + clint@2000000 {
> > + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint";
>
> Doesn't match the binding.
Okay, will update.
>
> > + interrupts-extended = <
> > + &cpu1-intc 3 &cpu1-intc 7
> > + &cpu2-intc 3 &cpu2-intc 7
> > + &cpu3-intc 3 &cpu3-intc 7
> > + &cpu4-intc 3 &cpu4-intc 7>;
> > + reg = <0x2000000 0x4000000>;
> > + };
> > --
> > 2.25.1
> >
Regards,
Anup
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings
@ 2020-07-14 3:47 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-07-14 3:47 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Damien Le Moal, Daniel Lezcano, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Albert Ou,
Palmer Dabbelt, Paul Walmsley, Palmer Dabbelt, Alistair Francis,
Thomas Gleixner, linux-riscv
On Tue, Jul 14, 2020 at 8:07 AM Rob Herring <robh@kernel.org> wrote:
>
> On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote:
> > We add DT bindings documentation for CLINT device.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> > ---
> > .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
>
> Bindings should be in DT schema format now.
Okay, will update.
>
> >
> > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> > new file mode 100644
> > index 000000000000..45b75347a7d5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> > @@ -0,0 +1,34 @@
> > +SiFive Core Local Interruptor (CLINT)
> > +-------------------------------------
> > +
> > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core
> > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts.
> > +
> > +It directly connects to the timer and inter-processor interrupt lines of
> > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt
> > +controller is the parent interrupt controller for CLINT device.
> > +
> > +The clock frequency of CLINT is specified via "timebase-frequency" DT
> > +property of "/cpus" DT node. The "timebase-frequency" DT property is
> > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml
> > +
> > +Required properties:
> > +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific
>
> A new versioning scheme from SiFive? To review, we don't do version
> numbers unless there's a well defined and documented scheme. IOW, one
> that's not s/w folks just making up v1, v2, v3, etc.
The "riscv,clint0" is already used by various RISC-V systems (including QEMU).
The "sifive,clint-1.0.0" is for being consistent with the PLIC
versioning scheme.
There is no clear documentation of CLINT versioning scheme. I think it's best
to just drop "sifive,clint-1.0.0" . Agree ??
>
> > + string identifying the actual implementation can be added if implementation
> > + specific worked arounds are needed.
> > +- reg : Should contain 1 register range (address and length).
> > +- interrupts-extended : Specifies which HARTs (or CPUs) are connected to
> > + the CLINT. Each node pointed to should be a riscv,cpu-intc node, which
> > + has a riscv node as parent.
> > +
> > +Example:
> > +
> > + clint@2000000 {
> > + compatible = "sifive,clint-1.0.0", "sifive,fu540-c000-clint";
>
> Doesn't match the binding.
Okay, will update.
>
> > + interrupts-extended = <
> > + &cpu1-intc 3 &cpu1-intc 7
> > + &cpu2-intc 3 &cpu2-intc 7
> > + &cpu3-intc 3 &cpu3-intc 7
> > + &cpu4-intc 3 &cpu4-intc 7>;
> > + reg = <0x2000000 0x4000000>;
> > + };
> > --
> > 2.25.1
> >
Regards,
Anup
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 0/5] Dedicated CLINT timer driver
2020-07-13 23:02 ` Palmer Dabbelt
@ 2020-07-14 3:49 ` Anup Patel
-1 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-07-14 3:49 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Anup Patel, Paul Walmsley, Albert Ou, Rob Herring,
Daniel Lezcano, Thomas Gleixner, Damien Le Moal, Atish Patra,
Alistair Francis, linux-riscv, linux-kernel@vger.kernel.org List,
devicetree
On Tue, Jul 14, 2020 at 4:32 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Sat, 27 Jun 2020 09:19:52 PDT (-0700), Anup Patel wrote:
> > The current RISC-V timer driver is convoluted and implements two
> > distinct timers:
> > 1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The
> > clocksource is implemented using TIME CSR and clockevent device
> > is implemented using SBI Timer calls.
> > 2. M-mode timer: This is for Linux RISC-V M-mode without MMU. The
> > clocksource is implemented using CLINT MMIO time register and
> > clockevent device is implemented using CLINT MMIO timecmp registers.
> >
> > This patchset removes clint related code from RISC-V timer driver and
> > arch/riscv directory. Instead, the series adds a dedicated MMIO based
> > CLINT driver under drivers/clocksource directory which can be used by
> > Linux RISC-V M-mode (i.e NoMMU Linux RISC-V).
> >
> > The patchset is based up Linux-5.8-rc2 and can be found at riscv_clint_v2
> > branch of: https://github.com/avpatel/linux.git
> >
> > This series is tested on:
> > 1. QEMU RV64 virt machine using Linux RISC-V S-mode
> > 2. QEMU RV32 virt machine using Linux RISC-V S-mode
> > 3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU)
> >
> > Changes since v1:
> > - Rebased series on Linux-5.8-rc2
> > - Added pr_warn() for case where ipi_ops not available in PATCH1
> > - Updated ipi_inject() prototype to use "struct cpumask *" in PATCH1
> > - Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4
> > - Added riscv,clint0 compatible string in DT bindings document
> >
> > Anup Patel (5):
> > RISC-V: Add mechanism to provide custom IPI operations
> > RISC-V: Remove CLINT related code
> > clocksource/drivers/timer-riscv: Remove MMIO related stuff
> > clocksource/drivers: Add CLINT timer driver
> > dt-bindings: timer: Add CLINT bindings
>
> This all generally LGTM, though I haven't been through the code line-by-line
> yet. It touches a bunch of trees, so I'd prefer to have some Acks before
> merging -- I'll dig through the RISC-V specific stuff, but the new CLINT driver
> probhably deserves a look from one of the clocksource folks.
>
> I think the only issue is that the port will be broken between patch 2 and 4,
> as at that point we won't have an M-mode timer driver. I think it shouldn't be
> too much to just reorder these, LMK if you want to do it or you want me to.
Okay, I will try your suggestion to reorder patches. There is another minor
build issue reported by test bots which I will fix as well.
I will send v3 in a couple of days before end-of-week.
Regards,
Anup
>
> Thanks!
>
> >
> > .../bindings/timer/sifive,clint.txt | 34 +++
> > arch/riscv/Kconfig | 2 +-
> > arch/riscv/include/asm/clint.h | 39 ---
> > arch/riscv/include/asm/smp.h | 11 +
> > arch/riscv/include/asm/timex.h | 28 +--
> > arch/riscv/kernel/Makefile | 2 +-
> > arch/riscv/kernel/clint.c | 44 ----
> > arch/riscv/kernel/sbi.c | 14 ++
> > arch/riscv/kernel/setup.c | 2 -
> > arch/riscv/kernel/smp.c | 44 ++--
> > arch/riscv/kernel/smpboot.c | 4 +-
> > drivers/clocksource/Kconfig | 12 +-
> > drivers/clocksource/Makefile | 1 +
> > drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++
> > drivers/clocksource/timer-riscv.c | 17 +-
> > include/linux/cpuhotplug.h | 1 +
> > 16 files changed, 337 insertions(+), 147 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
> > delete mode 100644 arch/riscv/include/asm/clint.h
> > delete mode 100644 arch/riscv/kernel/clint.c
> > create mode 100644 drivers/clocksource/timer-clint.c
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 0/5] Dedicated CLINT timer driver
@ 2020-07-14 3:49 ` Anup Patel
0 siblings, 0 replies; 24+ messages in thread
From: Anup Patel @ 2020-07-14 3:49 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: devicetree, Damien Le Moal, Daniel Lezcano, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Thomas Gleixner, linux-riscv,
Albert Ou
On Tue, Jul 14, 2020 at 4:32 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Sat, 27 Jun 2020 09:19:52 PDT (-0700), Anup Patel wrote:
> > The current RISC-V timer driver is convoluted and implements two
> > distinct timers:
> > 1. S-mode timer: This is for Linux RISC-V S-mode with MMU. The
> > clocksource is implemented using TIME CSR and clockevent device
> > is implemented using SBI Timer calls.
> > 2. M-mode timer: This is for Linux RISC-V M-mode without MMU. The
> > clocksource is implemented using CLINT MMIO time register and
> > clockevent device is implemented using CLINT MMIO timecmp registers.
> >
> > This patchset removes clint related code from RISC-V timer driver and
> > arch/riscv directory. Instead, the series adds a dedicated MMIO based
> > CLINT driver under drivers/clocksource directory which can be used by
> > Linux RISC-V M-mode (i.e NoMMU Linux RISC-V).
> >
> > The patchset is based up Linux-5.8-rc2 and can be found at riscv_clint_v2
> > branch of: https://github.com/avpatel/linux.git
> >
> > This series is tested on:
> > 1. QEMU RV64 virt machine using Linux RISC-V S-mode
> > 2. QEMU RV32 virt machine using Linux RISC-V S-mode
> > 3. QEMU RV64 virt machine using Linux RISC-V M-mode (i.e. NoMMU)
> >
> > Changes since v1:
> > - Rebased series on Linux-5.8-rc2
> > - Added pr_warn() for case where ipi_ops not available in PATCH1
> > - Updated ipi_inject() prototype to use "struct cpumask *" in PATCH1
> > - Updated CLINT_TIMER kconfig option to depend on RISCV_M_MODE in PATCH4
> > - Added riscv,clint0 compatible string in DT bindings document
> >
> > Anup Patel (5):
> > RISC-V: Add mechanism to provide custom IPI operations
> > RISC-V: Remove CLINT related code
> > clocksource/drivers/timer-riscv: Remove MMIO related stuff
> > clocksource/drivers: Add CLINT timer driver
> > dt-bindings: timer: Add CLINT bindings
>
> This all generally LGTM, though I haven't been through the code line-by-line
> yet. It touches a bunch of trees, so I'd prefer to have some Acks before
> merging -- I'll dig through the RISC-V specific stuff, but the new CLINT driver
> probhably deserves a look from one of the clocksource folks.
>
> I think the only issue is that the port will be broken between patch 2 and 4,
> as at that point we won't have an M-mode timer driver. I think it shouldn't be
> too much to just reorder these, LMK if you want to do it or you want me to.
Okay, I will try your suggestion to reorder patches. There is another minor
build issue reported by test bots which I will fix as well.
I will send v3 in a couple of days before end-of-week.
Regards,
Anup
>
> Thanks!
>
> >
> > .../bindings/timer/sifive,clint.txt | 34 +++
> > arch/riscv/Kconfig | 2 +-
> > arch/riscv/include/asm/clint.h | 39 ---
> > arch/riscv/include/asm/smp.h | 11 +
> > arch/riscv/include/asm/timex.h | 28 +--
> > arch/riscv/kernel/Makefile | 2 +-
> > arch/riscv/kernel/clint.c | 44 ----
> > arch/riscv/kernel/sbi.c | 14 ++
> > arch/riscv/kernel/setup.c | 2 -
> > arch/riscv/kernel/smp.c | 44 ++--
> > arch/riscv/kernel/smpboot.c | 4 +-
> > drivers/clocksource/Kconfig | 12 +-
> > drivers/clocksource/Makefile | 1 +
> > drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++
> > drivers/clocksource/timer-riscv.c | 17 +-
> > include/linux/cpuhotplug.h | 1 +
> > 16 files changed, 337 insertions(+), 147 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
> > delete mode 100644 arch/riscv/include/asm/clint.h
> > delete mode 100644 arch/riscv/kernel/clint.c
> > create mode 100644 drivers/clocksource/timer-clint.c
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^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings
2020-07-14 3:47 ` Anup Patel
@ 2020-07-14 15:04 ` Rob Herring
-1 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2020-07-14 15:04 UTC (permalink / raw)
To: Anup Patel
Cc: Anup Patel, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Daniel Lezcano, Thomas Gleixner, Damien Le Moal, Atish Patra,
Alistair Francis, linux-riscv, linux-kernel@vger.kernel.org List,
devicetree, Palmer Dabbelt
On Mon, Jul 13, 2020 at 9:47 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Jul 14, 2020 at 8:07 AM Rob Herring <robh@kernel.org> wrote:
> >
> > On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote:
> > > We add DT bindings documentation for CLINT device.
> > >
> > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> > > ---
> > > .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++
> > > 1 file changed, 34 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
> >
> > Bindings should be in DT schema format now.
>
> Okay, will update.
>
> >
> > >
> > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> > > new file mode 100644
> > > index 000000000000..45b75347a7d5
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> > > @@ -0,0 +1,34 @@
> > > +SiFive Core Local Interruptor (CLINT)
> > > +-------------------------------------
> > > +
> > > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core
> > > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts.
> > > +
> > > +It directly connects to the timer and inter-processor interrupt lines of
> > > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt
> > > +controller is the parent interrupt controller for CLINT device.
> > > +
> > > +The clock frequency of CLINT is specified via "timebase-frequency" DT
> > > +property of "/cpus" DT node. The "timebase-frequency" DT property is
> > > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml
> > > +
> > > +Required properties:
> > > +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific
> >
> > A new versioning scheme from SiFive? To review, we don't do version
> > numbers unless there's a well defined and documented scheme. IOW, one
> > that's not s/w folks just making up v1, v2, v3, etc.
>
> The "riscv,clint0" is already used by various RISC-V systems (including QEMU).
Not my problem that undocumented bindings are being used.
> The "sifive,clint-1.0.0" is for being consistent with the PLIC
> versioning scheme.
Where is that documented? This is what I expect you to be following or
updating to match:
Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt
>
> There is no clear documentation of CLINT versioning scheme. I think it's best
> to just drop "sifive,clint-1.0.0" . Agree ??
No, because then you are left with a very generic compatible string.
You need something specific enough to handle any implementation
features/quirks/bugs without needing a DT update. Typically, this
means a per SoC compatible string for a block as even the same IP
version can have different integration quirks.
Rob
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings
@ 2020-07-14 15:04 ` Rob Herring
0 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2020-07-14 15:04 UTC (permalink / raw)
To: Anup Patel
Cc: devicetree, Damien Le Moal, Daniel Lezcano, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Albert Ou,
Palmer Dabbelt, Paul Walmsley, Palmer Dabbelt, Alistair Francis,
Thomas Gleixner, linux-riscv
On Mon, Jul 13, 2020 at 9:47 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Jul 14, 2020 at 8:07 AM Rob Herring <robh@kernel.org> wrote:
> >
> > On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote:
> > > We add DT bindings documentation for CLINT device.
> > >
> > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> > > ---
> > > .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++
> > > 1 file changed, 34 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
> >
> > Bindings should be in DT schema format now.
>
> Okay, will update.
>
> >
> > >
> > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> > > new file mode 100644
> > > index 000000000000..45b75347a7d5
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> > > @@ -0,0 +1,34 @@
> > > +SiFive Core Local Interruptor (CLINT)
> > > +-------------------------------------
> > > +
> > > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core
> > > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts.
> > > +
> > > +It directly connects to the timer and inter-processor interrupt lines of
> > > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt
> > > +controller is the parent interrupt controller for CLINT device.
> > > +
> > > +The clock frequency of CLINT is specified via "timebase-frequency" DT
> > > +property of "/cpus" DT node. The "timebase-frequency" DT property is
> > > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml
> > > +
> > > +Required properties:
> > > +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific
> >
> > A new versioning scheme from SiFive? To review, we don't do version
> > numbers unless there's a well defined and documented scheme. IOW, one
> > that's not s/w folks just making up v1, v2, v3, etc.
>
> The "riscv,clint0" is already used by various RISC-V systems (including QEMU).
Not my problem that undocumented bindings are being used.
> The "sifive,clint-1.0.0" is for being consistent with the PLIC
> versioning scheme.
Where is that documented? This is what I expect you to be following or
updating to match:
Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt
>
> There is no clear documentation of CLINT versioning scheme. I think it's best
> to just drop "sifive,clint-1.0.0" . Agree ??
No, because then you are left with a very generic compatible string.
You need something specific enough to handle any implementation
features/quirks/bugs without needing a DT update. Typically, this
means a per SoC compatible string for a block as even the same IP
version can have different integration quirks.
Rob
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2020-07-14 15:04 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-27 16:19 [PATCH v2 0/5] Dedicated CLINT timer driver Anup Patel
2020-06-27 16:19 ` Anup Patel
2020-06-27 16:19 ` [PATCH v2 1/5] RISC-V: Add mechanism to provide custom IPI operations Anup Patel
2020-06-27 16:19 ` Anup Patel
2020-06-27 16:19 ` [PATCH v2 2/5] RISC-V: Remove CLINT related code Anup Patel
2020-06-27 16:19 ` Anup Patel
2020-06-27 16:19 ` [PATCH v2 3/5] clocksource/drivers/timer-riscv: Remove MMIO related stuff Anup Patel
2020-06-27 16:19 ` Anup Patel
2020-06-29 16:03 ` kernel test robot
2020-06-27 16:19 ` [PATCH v2 4/5] clocksource/drivers: Add CLINT timer driver Anup Patel
2020-06-27 16:19 ` Anup Patel
2020-06-29 17:44 ` kernel test robot
2020-06-27 16:19 ` [PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings Anup Patel
2020-06-27 16:19 ` Anup Patel
2020-07-14 2:37 ` Rob Herring
2020-07-14 2:37 ` Rob Herring
2020-07-14 3:47 ` Anup Patel
2020-07-14 3:47 ` Anup Patel
2020-07-14 15:04 ` Rob Herring
2020-07-14 15:04 ` Rob Herring
2020-07-13 23:02 ` [PATCH v2 0/5] Dedicated CLINT timer driver Palmer Dabbelt
2020-07-13 23:02 ` Palmer Dabbelt
2020-07-14 3:49 ` Anup Patel
2020-07-14 3:49 ` Anup Patel
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