From: Sergio Paracuellos <sergio.paracuellos@gmail.com> To: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com>, Rob Herring <robh+dt@kernel.org>, John Crispin <john@phrozen.org>, Thomas Bogendoerfer <tsbogend@alpha.franken.de>, Greg KH <gregkh@linuxfoundation.org>, Chuanhong Guo <gch981213@gmail.com>, Weijie Gao <hackpascal@gmail.com>, "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>, linux-kernel <linux-kernel@vger.kernel.org>, "open list:MIPS" <linux-mips@vger.kernel.org>, "open list:STAGING SUBSYSTEM" <devel@driverdev.osuosl.org>, NeilBrown <neil@brown.name>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org> Subject: Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation Date: Thu, 17 Dec 2020 11:01:39 +0100 [thread overview] Message-ID: <CAMhs-H_EiDot_V4Qj1Q8noAf5RNi9BOyy0WmawE+70wY7=FxDg@mail.gmail.com> (raw) In-Reply-To: <160819550615.1580929.14234996916739809712@swboyd.mtv.corp.google.com> Hi Stephen, Thanks for the review! On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Sergio Paracuellos (2020-11-22 01:55:52) > > Adds device tree binding documentation for clocks in the > > MT7621 SOC. > > > > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> > > --- > > .../bindings/clock/mediatek,mt7621-clk.yaml | 67 +++++++++++++++++++ > > 1 file changed, 67 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > > > > Rob? > > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > > new file mode 100644 > > index 000000000000..6aca4c1a4a46 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > > @@ -0,0 +1,67 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MT7621 Clock Device Tree Bindings > > + > > +maintainers: > > + - Sergio Paracuellos <sergio.paracuellos@gmail.com> > > + > > +description: | > > + The MT7621 has a PLL controller from where the cpu clock is provided > > + as well as derived clocks for the bus and the peripherals. It also > > + can gate SoC device clocks. > > + > > + Each clock is assigned an identifier and client nodes use this identifier > > + to specify the clock which they consume. > > + > > + All these identifiers could be found in: > > + [1]: <include/dt-bindings/clock/mt7621-clk.h>. > > + > > + The mt7621 clock node should be the child of a syscon node with the > > + required property: > > + > > + - compatible: Should be one of the following: > > + "mediatek,mt7621-sysc", "syscon" > > + > > + Refer to the bindings described in > > + Documentation/devicetree/bindings/mfd/syscon.yaml > > + > > +properties: > > + compatible: > > + const: mediatek,mt7621-clk > > + > > + "#clock-cells": > > + description: > > + The first cell indicates the clock gate number, see [1] for available > > + clocks. > > + const: 1 > > + > > + clock-output-names: > > + maxItems: 8 > > + > > +required: > > + - compatible > > + - '#clock-cells' > > + - clock-output-names > > Why is clock-output-names required? Hopefully it is not required. Not really, can be removed from here. > > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt7621-clk.h> > > + > > + sysc: sysc@0 { > > syscon@0? I don't think sysc is a standard node name. Ok, I will change this into syscon@0 in both bindings and device tree file. > > > + compatible = "mediatek,mt7621-sysc", "syscon"; > > + reg = <0x0 0x100>; > > + > > + pll { > > clock-controller? Why can't the parent device be the clk provider and > have #clock-cells? > I don't get your point, sorry. Can you please explain this a bit more or point to me to an example to understand the real meaning of this? > > + compatible = "mediatek,mt7621-clk"; > > + #clock-cells = <1>; > > + clock-output-names = "xtal", "cpu", "bus", > > + "50m", "125m", "150m", > > + "250m", "270m"; > > + }; > > + }; Best regards, Sergio Paracuellos
WARNING: multiple messages have this Message-ID (diff)
From: Sergio Paracuellos <sergio.paracuellos@gmail.com> To: Stephen Boyd <sboyd@kernel.org> Cc: Weijie Gao <hackpascal@gmail.com>, "open list:STAGING SUBSYSTEM" <devel@driverdev.osuosl.org>, Thomas Bogendoerfer <tsbogend@alpha.franken.de>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, Greg KH <gregkh@linuxfoundation.org>, Michael Turquette <mturquette@baylibre.com>, linux-kernel <linux-kernel@vger.kernel.org>, "open list:MIPS" <linux-mips@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>, John Crispin <john@phrozen.org>, NeilBrown <neil@brown.name>, "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org> Subject: Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation Date: Thu, 17 Dec 2020 11:01:39 +0100 [thread overview] Message-ID: <CAMhs-H_EiDot_V4Qj1Q8noAf5RNi9BOyy0WmawE+70wY7=FxDg@mail.gmail.com> (raw) In-Reply-To: <160819550615.1580929.14234996916739809712@swboyd.mtv.corp.google.com> Hi Stephen, Thanks for the review! On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Sergio Paracuellos (2020-11-22 01:55:52) > > Adds device tree binding documentation for clocks in the > > MT7621 SOC. > > > > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> > > --- > > .../bindings/clock/mediatek,mt7621-clk.yaml | 67 +++++++++++++++++++ > > 1 file changed, 67 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > > > > Rob? > > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > > new file mode 100644 > > index 000000000000..6aca4c1a4a46 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > > @@ -0,0 +1,67 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MT7621 Clock Device Tree Bindings > > + > > +maintainers: > > + - Sergio Paracuellos <sergio.paracuellos@gmail.com> > > + > > +description: | > > + The MT7621 has a PLL controller from where the cpu clock is provided > > + as well as derived clocks for the bus and the peripherals. It also > > + can gate SoC device clocks. > > + > > + Each clock is assigned an identifier and client nodes use this identifier > > + to specify the clock which they consume. > > + > > + All these identifiers could be found in: > > + [1]: <include/dt-bindings/clock/mt7621-clk.h>. > > + > > + The mt7621 clock node should be the child of a syscon node with the > > + required property: > > + > > + - compatible: Should be one of the following: > > + "mediatek,mt7621-sysc", "syscon" > > + > > + Refer to the bindings described in > > + Documentation/devicetree/bindings/mfd/syscon.yaml > > + > > +properties: > > + compatible: > > + const: mediatek,mt7621-clk > > + > > + "#clock-cells": > > + description: > > + The first cell indicates the clock gate number, see [1] for available > > + clocks. > > + const: 1 > > + > > + clock-output-names: > > + maxItems: 8 > > + > > +required: > > + - compatible > > + - '#clock-cells' > > + - clock-output-names > > Why is clock-output-names required? Hopefully it is not required. Not really, can be removed from here. > > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt7621-clk.h> > > + > > + sysc: sysc@0 { > > syscon@0? I don't think sysc is a standard node name. Ok, I will change this into syscon@0 in both bindings and device tree file. > > > + compatible = "mediatek,mt7621-sysc", "syscon"; > > + reg = <0x0 0x100>; > > + > > + pll { > > clock-controller? Why can't the parent device be the clk provider and > have #clock-cells? > I don't get your point, sorry. Can you please explain this a bit more or point to me to an example to understand the real meaning of this? > > + compatible = "mediatek,mt7621-clk"; > > + #clock-cells = <1>; > > + clock-output-names = "xtal", "cpu", "bus", > > + "50m", "125m", "150m", > > + "250m", "270m"; > > + }; > > + }; Best regards, Sergio Paracuellos _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
next prev parent reply other threads:[~2020-12-17 10:02 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-22 9:55 [PATCH v4 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621 Sergio Paracuellos 2020-11-22 9:55 ` Sergio Paracuellos 2020-11-22 9:55 ` [PATCH v4 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks Sergio Paracuellos 2020-11-22 9:55 ` Sergio Paracuellos 2020-11-22 9:55 ` [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation Sergio Paracuellos 2020-11-22 9:55 ` Sergio Paracuellos 2020-12-17 8:58 ` Stephen Boyd 2020-12-17 8:58 ` Stephen Boyd 2020-12-17 10:01 ` Sergio Paracuellos [this message] 2020-12-17 10:01 ` Sergio Paracuellos 2020-12-17 10:07 ` Stephen Boyd 2020-12-17 10:14 ` Sergio Paracuellos 2020-12-17 10:32 ` Stephen Boyd 2020-12-17 10:38 ` Sergio Paracuellos 2020-12-17 10:50 ` Stephen Boyd 2020-12-17 10:54 ` Sergio Paracuellos 2020-12-17 15:04 ` Rob Herring 2020-12-17 15:04 ` Rob Herring 2020-12-17 15:12 ` Sergio Paracuellos 2020-12-17 15:12 ` Sergio Paracuellos 2020-11-22 9:55 ` [PATCH v4 3/6] clk: ralink: add clock driver for mt7621 SoC Sergio Paracuellos 2020-11-22 9:55 ` Sergio Paracuellos 2020-12-17 9:09 ` Stephen Boyd 2020-12-17 9:09 ` Stephen Boyd 2020-12-17 9:54 ` Sergio Paracuellos 2020-12-17 9:54 ` Sergio Paracuellos 2020-12-17 10:12 ` Stephen Boyd 2020-12-17 10:21 ` Sergio Paracuellos 2020-11-22 9:55 ` [PATCH v4 4/6] staging: mt7621-dts: make use of new 'mt7621-clk' Sergio Paracuellos 2020-11-22 9:55 ` Sergio Paracuellos 2020-11-22 9:55 ` [PATCH v4 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk' Sergio Paracuellos 2020-11-22 9:55 ` Sergio Paracuellos 2020-11-22 9:55 ` [PATCH v4 6/6] MAINTAINERS: add MT7621 CLOCK maintainer Sergio Paracuellos 2020-11-22 9:55 ` Sergio Paracuellos 2020-12-10 6:55 ` [PATCH v4 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621 Sergio Paracuellos 2020-12-10 6:55 ` Sergio Paracuellos
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