* [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-04-14 10:56 ` Igal.Liberman 0 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman @ 2015-04-14 10:56 UTC (permalink / raw) To: devicetree, linuxppc-dev; +Cc: scottwood, Igal Liberman From: Igal Liberman <Igal.Liberman@freescale.com> v3: Addressed feedback from Scott: - Removed clock specifier description. v2: Addressed feedback from Scott: - Moved the "fman-clk-mux" clock provider details under "clocks" property. Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> --- .../devicetree/bindings/clock/qoriq-clock.txt | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index b0d7b73..2bb3b38 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -65,9 +65,10 @@ Required properties: It takes parent's clock-frequency as its clock. * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) + * "fsl,fman-clk-mux" for the Frame Manager clock. - #clock-cells: From common clock binding. The number of cells in a - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" and + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll-[1,2].0". For "fsl,qoriq-core-pll-1.0" clocks, the single clock-specifier cell may take the following values: * 0 - equal to the PLL frequency @@ -145,6 +146,18 @@ Example for clock block and clock provider: clocks = <&sysclk>; clock-output-names = "platform-pll", "platform-pll-div2"; }; + + fm0clk: fm0-clk-mux { + #clock-cells = <0>; + reg = <0x10 4> + compatible = "fsl,fman-clk-mux"; + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>, + <&platform_pll 0>, <&pll1 1>, <&pll1 2>; + clock-names = "pll0", "pll0-div2", "pll0-div3", + "pll0-div4", "platform-pll", "pll1-div2", + "pll1-div3"; + clock-output-names = "fm0-clk"; + }; }; }; -- 1.7.9.5 _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-04-14 10:56 ` Igal.Liberman 0 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman @ 2015-04-14 10:56 UTC (permalink / raw) To: devicetree, linuxppc-dev; +Cc: scottwood, Igal Liberman From: Igal Liberman <Igal.Liberman@freescale.com> v3: Addressed feedback from Scott: - Removed clock specifier description. v2: Addressed feedback from Scott: - Moved the "fman-clk-mux" clock provider details under "clocks" property. Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> --- .../devicetree/bindings/clock/qoriq-clock.txt | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index b0d7b73..2bb3b38 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -65,9 +65,10 @@ Required properties: It takes parent's clock-frequency as its clock. * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) + * "fsl,fman-clk-mux" for the Frame Manager clock. - #clock-cells: From common clock binding. The number of cells in a - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" and + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll-[1,2].0". For "fsl,qoriq-core-pll-1.0" clocks, the single clock-specifier cell may take the following values: * 0 - equal to the PLL frequency @@ -145,6 +146,18 @@ Example for clock block and clock provider: clocks = <&sysclk>; clock-output-names = "platform-pll", "platform-pll-div2"; }; + + fm0clk: fm0-clk-mux { + #clock-cells = <0>; + reg = <0x10 4> + compatible = "fsl,fman-clk-mux"; + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>, + <&platform_pll 0>, <&pll1 1>, <&pll1 2>; + clock-names = "pll0", "pll0-div2", "pll0-div3", + "pll0-div4", "platform-pll", "pll1-div2", + "pll1-div3"; + clock-output-names = "fm0-clk"; + }; }; }; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux 2015-04-14 10:56 ` Igal.Liberman @ 2015-04-15 17:35 ` Scott Wood -1 siblings, 0 replies; 26+ messages in thread From: Scott Wood @ 2015-04-15 17:35 UTC (permalink / raw) To: Igal.Liberman; +Cc: devicetree, linuxppc-dev On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > From: Igal Liberman <Igal.Liberman@freescale.com> > > v3: Addressed feedback from Scott: > - Removed clock specifier description. > > v2: Addressed feedback from Scott: > - Moved the "fman-clk-mux" clock provider details > under "clocks" property. > > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> > --- > .../devicetree/bindings/clock/qoriq-clock.txt | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > index b0d7b73..2bb3b38 100644 > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > @@ -65,9 +65,10 @@ Required properties: > It takes parent's clock-frequency as its clock. > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) > + * "fsl,fman-clk-mux" for the Frame Manager clock. > - #clock-cells: From common clock binding. The number of cells in a > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" and > + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll-[1,2].0". > For "fsl,qoriq-core-pll-1.0" clocks, the single > clock-specifier cell may take the following values: > * 0 - equal to the PLL frequency > @@ -145,6 +146,18 @@ Example for clock block and clock provider: > clocks = <&sysclk>; > clock-output-names = "platform-pll", "platform-pll-div2"; > }; > + > + fm0clk: fm0-clk-mux { > + #clock-cells = <0>; > + reg = <0x10 4> > + compatible = "fsl,fman-clk-mux"; > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>, > + <&platform_pll 0>, <&pll1 1>, <&pll1 2>; > + clock-names = "pll0", "pll0-div2", "pll0-div3", > + "pll0-div4", "platform-pll", "pll1-div2", > + "pll1-div3"; > + clock-output-names = "fm0-clk"; > + }; > }; > }; > I don't see this register in the manuals for older DPAA chips, such as p4080 or p3041. Is it present but undocumented? Should I be looking somewhere other than "Clocking Memory Map"? -Scott _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-04-15 17:35 ` Scott Wood 0 siblings, 0 replies; 26+ messages in thread From: Scott Wood @ 2015-04-15 17:35 UTC (permalink / raw) To: Igal.Liberman; +Cc: devicetree, linuxppc-dev On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > From: Igal Liberman <Igal.Liberman@freescale.com> > > v3: Addressed feedback from Scott: > - Removed clock specifier description. > > v2: Addressed feedback from Scott: > - Moved the "fman-clk-mux" clock provider details > under "clocks" property. > > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> > --- > .../devicetree/bindings/clock/qoriq-clock.txt | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > index b0d7b73..2bb3b38 100644 > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > @@ -65,9 +65,10 @@ Required properties: > It takes parent's clock-frequency as its clock. > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) > + * "fsl,fman-clk-mux" for the Frame Manager clock. > - #clock-cells: From common clock binding. The number of cells in a > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" and > + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll-[1,2].0". > For "fsl,qoriq-core-pll-1.0" clocks, the single > clock-specifier cell may take the following values: > * 0 - equal to the PLL frequency > @@ -145,6 +146,18 @@ Example for clock block and clock provider: > clocks = <&sysclk>; > clock-output-names = "platform-pll", "platform-pll-div2"; > }; > + > + fm0clk: fm0-clk-mux { > + #clock-cells = <0>; > + reg = <0x10 4> > + compatible = "fsl,fman-clk-mux"; > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>, > + <&platform_pll 0>, <&pll1 1>, <&pll1 2>; > + clock-names = "pll0", "pll0-div2", "pll0-div3", > + "pll0-div4", "platform-pll", "pll1-div2", > + "pll1-div3"; > + clock-output-names = "fm0-clk"; > + }; > }; > }; > I don't see this register in the manuals for older DPAA chips, such as p4080 or p3041. Is it present but undocumented? Should I be looking somewhere other than "Clocking Memory Map"? -Scott ^ permalink raw reply [flat|nested] 26+ messages in thread
[parent not found: <1429119357.22867.724.camel-KZfg59tc24xl57MIdRCFDg@public.gmane.org>]
* RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux 2015-04-15 17:35 ` Scott Wood @ 2015-04-16 6:11 ` Igal.Liberman -1 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman-KZfg59tc24xl57MIdRCFDg @ 2015-04-16 6:11 UTC (permalink / raw) To: Scott Wood Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ Regards, Igal Liberman. > -----Original Message----- > From: Wood Scott-B07421 > Sent: Wednesday, April 15, 2015 8:36 PM > To: Liberman Igal-B31950 > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > > From: Igal Liberman <Igal.Liberman@freescale.com> > > > > v3: Addressed feedback from Scott: > > - Removed clock specifier description. > > > > v2: Addressed feedback from Scott: > > - Moved the "fman-clk-mux" clock provider details > > under "clocks" property. > > > > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> > > --- > > .../devicetree/bindings/clock/qoriq-clock.txt | 17 +++++++++++++++-- > > 1 file changed, 15 insertions(+), 2 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > index b0d7b73..2bb3b38 100644 > > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > @@ -65,9 +65,10 @@ Required properties: > > It takes parent's clock-frequency as its clock. > > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > > * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) > > + * "fsl,fman-clk-mux" for the Frame Manager clock. > > - #clock-cells: From common clock binding. The number of cells in a > > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" and > > + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll-[1,2].0". > > For "fsl,qoriq-core-pll-1.0" clocks, the single > > clock-specifier cell may take the following values: > > * 0 - equal to the PLL frequency > > @@ -145,6 +146,18 @@ Example for clock block and clock provider: > > clocks = <&sysclk>; > > clock-output-names = "platform-pll", "platform-pll- > div2"; > > }; > > + > > + fm0clk: fm0-clk-mux { > > + #clock-cells = <0>; > > + reg = <0x10 4> > > + compatible = "fsl,fman-clk-mux"; > > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>, > > + <&platform_pll 0>, <&pll1 1>, <&pll1 2>; > > + clock-names = "pll0", "pll0-div2", "pll0-div3", > > + "pll0-div4", "platform-pll", "pll1-div2", > > + "pll1-div3"; > > + clock-output-names = "fm0-clk"; > > + }; > > }; > > }; > > > > I don't see this register in the manuals for older DPAA chips, such as > p4080 or p3041. Is it present but undocumented? Should I be looking > somewhere other than "Clocking Memory Map"? > It's available only in part of the new chips (T4, T2, B4). In T1024/T1040 there's only one option for FMan clock so this register is not available. > -Scott > Igal. ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-04-16 6:11 ` Igal.Liberman 0 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman @ 2015-04-16 6:11 UTC (permalink / raw) To: Scott Wood; +Cc: devicetree, linuxppc-dev DQoNClJlZ2FyZHMsDQpJZ2FsIExpYmVybWFuLg0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0t LS0tDQo+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIxDQo+IFNlbnQ6IFdlZG5lc2RheSwgQXByaWwg MTUsIDIwMTUgODozNiBQTQ0KPiBUbzogTGliZXJtYW4gSWdhbC1CMzE5NTANCj4gQ2M6IGRldmlj ZXRyZWVAdmdlci5rZXJuZWwub3JnOyBsaW51eHBwYy1kZXZAbGlzdHMub3psYWJzLm9yZw0KPiBT dWJqZWN0OiBSZTogW3YzXSBkdC9iaW5kaW5nczogcW9yaXEtY2xvY2s6IEFkZCBiaW5kaW5nIGZv ciBGTWFuIGNsb2NrIG11eA0KPiANCj4gT24gVHVlLCAyMDE1LTA0LTE0IGF0IDEzOjU2ICswMzAw LCBJZ2FsLkxpYmVybWFuIHdyb3RlOg0KPiA+IEZyb206IElnYWwgTGliZXJtYW4gPElnYWwuTGli ZXJtYW5AZnJlZXNjYWxlLmNvbT4NCj4gPg0KPiA+IHYzOiBBZGRyZXNzZWQgZmVlZGJhY2sgZnJv bSBTY290dDoNCj4gPiAJLSBSZW1vdmVkIGNsb2NrIHNwZWNpZmllciBkZXNjcmlwdGlvbi4NCj4g Pg0KPiA+IHYyOiBBZGRyZXNzZWQgZmVlZGJhY2sgZnJvbSBTY290dDoNCj4gPiAJLSBNb3ZlZCB0 aGUgImZtYW4tY2xrLW11eCIgY2xvY2sgcHJvdmlkZXIgZGV0YWlscw0KPiA+IAkgIHVuZGVyICJj bG9ja3MiIHByb3BlcnR5Lg0KPiA+DQo+ID4gU2lnbmVkLW9mZi1ieTogSWdhbCBMaWJlcm1hbiA8 SWdhbC5MaWJlcm1hbkBmcmVlc2NhbGUuY29tPg0KPiA+IC0tLQ0KPiA+ICAuLi4vZGV2aWNldHJl ZS9iaW5kaW5ncy9jbG9jay9xb3JpcS1jbG9jay50eHQgICAgICB8ICAgMTcgKysrKysrKysrKysr KysrLS0NCj4gPiAgMSBmaWxlIGNoYW5nZWQsIDE1IGluc2VydGlvbnMoKyksIDIgZGVsZXRpb25z KC0pDQo+ID4NCj4gPiBkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRp bmdzL2Nsb2NrL3FvcmlxLWNsb2NrLnR4dA0KPiA+IGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVl L2JpbmRpbmdzL2Nsb2NrL3FvcmlxLWNsb2NrLnR4dA0KPiA+IGluZGV4IGIwZDdiNzMuLjJiYjNi MzggMTAwNjQ0DQo+ID4gLS0tIGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2Ns b2NrL3FvcmlxLWNsb2NrLnR4dA0KPiA+ICsrKyBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9i aW5kaW5ncy9jbG9jay9xb3JpcS1jbG9jay50eHQNCj4gPiBAQCAtNjUsOSArNjUsMTAgQEAgUmVx dWlyZWQgcHJvcGVydGllczoNCj4gPiAgCQlJdCB0YWtlcyBwYXJlbnQncyBjbG9jay1mcmVxdWVu Y3kgYXMgaXRzIGNsb2NrLg0KPiA+ICAJKiAiZnNsLHFvcmlxLXBsYXRmb3JtLXBsbC0xLjAiIGZv ciB0aGUgcGxhdGZvcm0gUExMIGNsb2NrICh2MS4wKQ0KPiA+ICAJKiAiZnNsLHFvcmlxLXBsYXRm b3JtLXBsbC0yLjAiIGZvciB0aGUgcGxhdGZvcm0gUExMIGNsb2NrICh2Mi4wKQ0KPiA+ICsJKiAi ZnNsLGZtYW4tY2xrLW11eCIgZm9yIHRoZSBGcmFtZSBNYW5hZ2VyIGNsb2NrLg0KPiA+ICAtICNj bG9jay1jZWxsczogRnJvbSBjb21tb24gY2xvY2sgYmluZGluZy4gVGhlIG51bWJlciBvZiBjZWxs cyBpbiBhDQo+ID4gLQljbG9jay1zcGVjaWZpZXIuIFNob3VsZCBiZSA8MD4gZm9yICJmc2wscW9y aXEtc3lzY2xrLVsxLDJdLjAiDQo+ID4gLQljbG9ja3MsIG9yIDwxPiBmb3IgImZzbCxxb3JpcS1j b3JlLXBsbC1bMSwyXS4wIiBjbG9ja3MuDQo+ID4gKwljbG9jay1zcGVjaWZpZXIuIFNob3VsZCBi ZSA8MD4gZm9yICJmc2wscW9yaXEtc3lzY2xrLVsxLDJdLjAiIGFuZA0KPiA+ICsJImZzbCxmbWFu LWNsay1tdXgiIGNsb2NrcyBvciA8MT4gZm9yICJmc2wscW9yaXEtY29yZS1wbGwtWzEsMl0uMCIu DQo+ID4gIAlGb3IgImZzbCxxb3JpcS1jb3JlLXBsbC0xLjAiIGNsb2NrcywgdGhlIHNpbmdsZQ0K PiA+ICAJY2xvY2stc3BlY2lmaWVyIGNlbGwgbWF5IHRha2UgdGhlIGZvbGxvd2luZyB2YWx1ZXM6 DQo+ID4gIAkqIDAgLSBlcXVhbCB0byB0aGUgUExMIGZyZXF1ZW5jeQ0KPiA+IEBAIC0xNDUsNiAr MTQ2LDE4IEBAIEV4YW1wbGUgZm9yIGNsb2NrIGJsb2NrIGFuZCBjbG9jayBwcm92aWRlcjoNCj4g PiAgCQkJY2xvY2tzID0gPCZzeXNjbGs+Ow0KPiA+ICAJCQljbG9jay1vdXRwdXQtbmFtZXMgPSAi cGxhdGZvcm0tcGxsIiwgInBsYXRmb3JtLXBsbC0NCj4gZGl2MiI7DQo+ID4gIAkJfTsNCj4gPiAr DQo+ID4gKwkJZm0wY2xrOiBmbTAtY2xrLW11eCB7DQo+ID4gKwkJCSNjbG9jay1jZWxscyA9IDww PjsNCj4gPiArCQkJcmVnID0gPDB4MTAgND4NCj4gPiArCQkJY29tcGF0aWJsZSA9ICJmc2wsZm1h bi1jbGstbXV4IjsNCj4gPiArCQkJY2xvY2tzID0gPCZwbGwwIDA+LCA8JnBsbDAgMT4sIDwmcGxs MCAyPiwgPCZwbGwwIDM+LA0KPiA+ICsJCQkJIDwmcGxhdGZvcm1fcGxsIDA+LCA8JnBsbDEgMT4s IDwmcGxsMSAyPjsNCj4gPiArCQkJY2xvY2stbmFtZXMgPSAicGxsMCIsICJwbGwwLWRpdjIiLCAi cGxsMC1kaXYzIiwNCj4gPiArCQkJCSAgICAgICJwbGwwLWRpdjQiLCAicGxhdGZvcm0tcGxsIiwg InBsbDEtZGl2MiIsDQo+ID4gKwkJCQkgICAgICAicGxsMS1kaXYzIjsNCj4gPiArCQkJY2xvY2st b3V0cHV0LW5hbWVzID0gImZtMC1jbGsiOw0KPiA+ICsJCX07DQo+ID4gIAl9Ow0KPiA+ICB9Ow0K PiA+DQo+IA0KPiBJIGRvbid0IHNlZSB0aGlzIHJlZ2lzdGVyIGluIHRoZSBtYW51YWxzIGZvciBv bGRlciBEUEFBIGNoaXBzLCBzdWNoIGFzDQo+IHA0MDgwIG9yIHAzMDQxLiAgSXMgaXQgcHJlc2Vu dCBidXQgdW5kb2N1bWVudGVkPyAgU2hvdWxkIEkgYmUgbG9va2luZw0KPiBzb21ld2hlcmUgb3Ro ZXIgdGhhbiAiQ2xvY2tpbmcgTWVtb3J5IE1hcCI/DQo+IA0KDQpJdCdzIGF2YWlsYWJsZSBvbmx5 IGluIHBhcnQgb2YgdGhlIG5ldyBjaGlwcyAoVDQsIFQyLCBCNCkuDQpJbiBUMTAyNC9UMTA0MCB0 aGVyZSdzIG9ubHkgb25lIG9wdGlvbiBmb3IgRk1hbiBjbG9jayBzbyB0aGlzIHJlZ2lzdGVyIGlz IG5vdCBhdmFpbGFibGUuDQoNCj4gLVNjb3R0DQo+IA0KDQpJZ2FsLg0KDQo= ^ permalink raw reply [flat|nested] 26+ messages in thread
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* Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux 2015-04-16 6:11 ` Igal.Liberman @ 2015-04-17 5:41 ` Scott Wood -1 siblings, 0 replies; 26+ messages in thread From: Scott Wood @ 2015-04-17 5:41 UTC (permalink / raw) To: Liberman Igal-B31950 Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ On Thu, 2015-04-16 at 01:11 -0500, Liberman Igal-B31950 wrote: > > > Regards, > Igal Liberman. > > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Wednesday, April 15, 2015 8:36 PM > > To: Liberman Igal-B31950 > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > > > From: Igal Liberman <Igal.Liberman-KZfg59tc24xl57MIdRCFDg@public.gmane.org> > > > > > > v3: Addressed feedback from Scott: > > > - Removed clock specifier description. > > > > > > v2: Addressed feedback from Scott: > > > - Moved the "fman-clk-mux" clock provider details > > > under "clocks" property. > > > > > > Signed-off-by: Igal Liberman <Igal.Liberman-KZfg59tc24xl57MIdRCFDg@public.gmane.org> > > > --- > > > .../devicetree/bindings/clock/qoriq-clock.txt | 17 +++++++++++++++-- > > > 1 file changed, 15 insertions(+), 2 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > index b0d7b73..2bb3b38 100644 > > > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > @@ -65,9 +65,10 @@ Required properties: > > > It takes parent's clock-frequency as its clock. > > > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > > > * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) > > > + * "fsl,fman-clk-mux" for the Frame Manager clock. > > > - #clock-cells: From common clock binding. The number of cells in a > > > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > > > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" and > > > + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll-[1,2].0". > > > For "fsl,qoriq-core-pll-1.0" clocks, the single > > > clock-specifier cell may take the following values: > > > * 0 - equal to the PLL frequency > > > @@ -145,6 +146,18 @@ Example for clock block and clock provider: > > > clocks = <&sysclk>; > > > clock-output-names = "platform-pll", "platform-pll- > > div2"; > > > }; > > > + > > > + fm0clk: fm0-clk-mux { > > > + #clock-cells = <0>; > > > + reg = <0x10 4> > > > + compatible = "fsl,fman-clk-mux"; > > > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>, > > > + <&platform_pll 0>, <&pll1 1>, <&pll1 2>; > > > + clock-names = "pll0", "pll0-div2", "pll0-div3", > > > + "pll0-div4", "platform-pll", "pll1-div2", > > > + "pll1-div3"; > > > + clock-output-names = "fm0-clk"; > > > + }; > > > }; > > > }; > > > > > > > I don't see this register in the manuals for older DPAA chips, such as > > p4080 or p3041. Is it present but undocumented? Should I be looking > > somewhere other than "Clocking Memory Map"? > > > > It's available only in part of the new chips (T4, T2, B4). > In T1024/T1040 there's only one option for FMan clock so this register is not available. So it's part of the 2.0 chassis? I'd stick a 2.0 in there, then. Who knows what we may see in the future. -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-04-17 5:41 ` Scott Wood 0 siblings, 0 replies; 26+ messages in thread From: Scott Wood @ 2015-04-17 5:41 UTC (permalink / raw) To: Liberman Igal-B31950; +Cc: devicetree, linuxppc-dev On Thu, 2015-04-16 at 01:11 -0500, Liberman Igal-B31950 wrote: > > > Regards, > Igal Liberman. > > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Wednesday, April 15, 2015 8:36 PM > > To: Liberman Igal-B31950 > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > > > From: Igal Liberman <Igal.Liberman@freescale.com> > > > > > > v3: Addressed feedback from Scott: > > > - Removed clock specifier description. > > > > > > v2: Addressed feedback from Scott: > > > - Moved the "fman-clk-mux" clock provider details > > > under "clocks" property. > > > > > > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> > > > --- > > > .../devicetree/bindings/clock/qoriq-clock.txt | 17 +++++++++++++++-- > > > 1 file changed, 15 insertions(+), 2 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > index b0d7b73..2bb3b38 100644 > > > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > @@ -65,9 +65,10 @@ Required properties: > > > It takes parent's clock-frequency as its clock. > > > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > > > * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) > > > + * "fsl,fman-clk-mux" for the Frame Manager clock. > > > - #clock-cells: From common clock binding. The number of cells in a > > > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > > > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" and > > > + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll-[1,2].0". > > > For "fsl,qoriq-core-pll-1.0" clocks, the single > > > clock-specifier cell may take the following values: > > > * 0 - equal to the PLL frequency > > > @@ -145,6 +146,18 @@ Example for clock block and clock provider: > > > clocks = <&sysclk>; > > > clock-output-names = "platform-pll", "platform-pll- > > div2"; > > > }; > > > + > > > + fm0clk: fm0-clk-mux { > > > + #clock-cells = <0>; > > > + reg = <0x10 4> > > > + compatible = "fsl,fman-clk-mux"; > > > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>, > > > + <&platform_pll 0>, <&pll1 1>, <&pll1 2>; > > > + clock-names = "pll0", "pll0-div2", "pll0-div3", > > > + "pll0-div4", "platform-pll", "pll1-div2", > > > + "pll1-div3"; > > > + clock-output-names = "fm0-clk"; > > > + }; > > > }; > > > }; > > > > > > > I don't see this register in the manuals for older DPAA chips, such as > > p4080 or p3041. Is it present but undocumented? Should I be looking > > somewhere other than "Clocking Memory Map"? > > > > It's available only in part of the new chips (T4, T2, B4). > In T1024/T1040 there's only one option for FMan clock so this register is not available. So it's part of the 2.0 chassis? I'd stick a 2.0 in there, then. Who knows what we may see in the future. -Scott ^ permalink raw reply [flat|nested] 26+ messages in thread
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* RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux 2015-04-17 5:41 ` Scott Wood @ 2015-04-20 11:07 ` Igal.Liberman -1 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman-KZfg59tc24xl57MIdRCFDg @ 2015-04-20 11:07 UTC (permalink / raw) To: Scott Wood Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ Regards, Igal Liberman. > -----Original Message----- > From: Wood Scott-B07421 > Sent: Friday, April 17, 2015 8:41 AM > To: Liberman Igal-B31950 > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > On Thu, 2015-04-16 at 01:11 -0500, Liberman Igal-B31950 wrote: > > > > > > Regards, > > Igal Liberman. > > > > > -----Original Message----- > > > From: Wood Scott-B07421 > > > Sent: Wednesday, April 15, 2015 8:36 PM > > > To: Liberman Igal-B31950 > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > clock mux > > > > > > On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > > > > From: Igal Liberman <Igal.Liberman@freescale.com> > > > > > > > > v3: Addressed feedback from Scott: > > > > - Removed clock specifier description. > > > > > > > > v2: Addressed feedback from Scott: > > > > - Moved the "fman-clk-mux" clock provider details > > > > under "clocks" property. > > > > > > > > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> > > > > --- > > > > .../devicetree/bindings/clock/qoriq-clock.txt | 17 > +++++++++++++++-- > > > > 1 file changed, 15 insertions(+), 2 deletions(-) > > > > > > > > diff --git > > > > a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > index b0d7b73..2bb3b38 100644 > > > > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > @@ -65,9 +65,10 @@ Required properties: > > > > It takes parent's clock-frequency as its clock. > > > > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > > > > * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) > > > > + * "fsl,fman-clk-mux" for the Frame Manager clock. > > > > - #clock-cells: From common clock binding. The number of cells in a > > > > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > > > > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" and > > > > + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll-[1,2].0". > > > > For "fsl,qoriq-core-pll-1.0" clocks, the single > > > > clock-specifier cell may take the following values: > > > > * 0 - equal to the PLL frequency @@ -145,6 +146,18 @@ Example > > > > for clock block and clock provider: > > > > clocks = <&sysclk>; > > > > clock-output-names = "platform-pll", "platform-pll- > > > div2"; > > > > }; > > > > + > > > > + fm0clk: fm0-clk-mux { > > > > + #clock-cells = <0>; > > > > + reg = <0x10 4> > > > > + compatible = "fsl,fman-clk-mux"; > > > > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>, > > > > + <&platform_pll 0>, <&pll1 1>, <&pll1 2>; > > > > + clock-names = "pll0", "pll0-div2", "pll0-div3", > > > > + "pll0-div4", "platform-pll", "pll1-div2", > > > > + "pll1-div3"; > > > > + clock-output-names = "fm0-clk"; > > > > + }; > > > > }; > > > > }; > > > > > > > > > > I don't see this register in the manuals for older DPAA chips, such > > > as > > > p4080 or p3041. Is it present but undocumented? Should I be > > > looking somewhere other than "Clocking Memory Map"? > > > > > > > It's available only in part of the new chips (T4, T2, B4). > > In T1024/T1040 there's only one option for FMan clock so this register is not > available. > > So it's part of the 2.0 chassis? I'd stick a 2.0 in there, then. Who knows what > we may see in the future. > OK, We can go with "fsl,fman-clk-mux-1/2-0.". In that case, we need to update FMan nodes and the clock driver: https://patchwork.ozlabs.org/patch/443973/ https://patchwork.ozlabs.org/patch/461813/ I will update those patches separately. > -Scott > Igal ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-04-20 11:07 ` Igal.Liberman 0 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman @ 2015-04-20 11:07 UTC (permalink / raw) To: Scott Wood; +Cc: devicetree, linuxppc-dev DQoNClJlZ2FyZHMsDQpJZ2FsIExpYmVybWFuLg0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0t LS0tDQo+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIxDQo+IFNlbnQ6IEZyaWRheSwgQXByaWwgMTcs IDIwMTUgODo0MSBBTQ0KPiBUbzogTGliZXJtYW4gSWdhbC1CMzE5NTANCj4gQ2M6IGRldmljZXRy ZWVAdmdlci5rZXJuZWwub3JnOyBsaW51eHBwYy1kZXZAbGlzdHMub3psYWJzLm9yZw0KPiBTdWJq ZWN0OiBSZTogW3YzXSBkdC9iaW5kaW5nczogcW9yaXEtY2xvY2s6IEFkZCBiaW5kaW5nIGZvciBG TWFuIGNsb2NrIG11eA0KPiANCj4gT24gVGh1LCAyMDE1LTA0LTE2IGF0IDAxOjExIC0wNTAwLCBM aWJlcm1hbiBJZ2FsLUIzMTk1MCB3cm90ZToNCj4gPg0KPiA+DQo+ID4gUmVnYXJkcywNCj4gPiBJ Z2FsIExpYmVybWFuLg0KPiA+DQo+ID4gPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+ ID4gRnJvbTogV29vZCBTY290dC1CMDc0MjENCj4gPiA+IFNlbnQ6IFdlZG5lc2RheSwgQXByaWwg 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* RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux 2015-04-17 5:41 ` Scott Wood @ 2015-04-20 11:40 ` Igal.Liberman -1 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman-KZfg59tc24xl57MIdRCFDg @ 2015-04-20 11:40 UTC (permalink / raw) To: Scott Wood Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #1: Type: text/plain; charset="utf-8", Size: 5420 bytes --] Regards, Igal Liberman. > -----Original Message----- > From: Liberman Igal-B31950 > Sent: Monday, April 20, 2015 2:07 PM > To: Wood Scott-B07421 > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > Subject: RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > Regards, > Igal Liberman. > > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Friday, April 17, 2015 8:41 AM > > To: Liberman Igal-B31950 > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock > > mux > > > > On Thu, 2015-04-16 at 01:11 -0500, Liberman Igal-B31950 wrote: > > > > > > > > > Regards, > > > Igal Liberman. > > > > > > > -----Original Message----- > > > > From: Wood Scott-B07421 > > > > Sent: Wednesday, April 15, 2015 8:36 PM > > > > To: Liberman Igal-B31950 > > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > > clock mux > > > > > > > > On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > > > > > From: Igal Liberman <Igal.Liberman@freescale.com> > > > > > > > > > > v3: Addressed feedback from Scott: > > > > > - Removed clock specifier description. > > > > > > > > > > v2: Addressed feedback from Scott: > > > > > - Moved the "fman-clk-mux" clock provider details > > > > > under "clocks" property. > > > > > > > > > > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> > > > > > --- > > > > > .../devicetree/bindings/clock/qoriq-clock.txt | 17 > > +++++++++++++++-- > > > > > 1 file changed, 15 insertions(+), 2 deletions(-) > > > > > > > > > > diff --git > > > > > a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > index b0d7b73..2bb3b38 100644 > > > > > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > @@ -65,9 +65,10 @@ Required properties: > > > > > It takes parent's clock-frequency as its clock. > > > > > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > > > > > * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock > > > > > (v2.0) > > > > > + * "fsl,fman-clk-mux" for the Frame Manager clock. > > > > > - #clock-cells: From common clock binding. The number of cells in a > > > > > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > > > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > > > > > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > and > > > > > + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll- > [1,2].0". > > > > > For "fsl,qoriq-core-pll-1.0" clocks, the single > > > > > clock-specifier cell may take the following values: > > > > > * 0 - equal to the PLL frequency @@ -145,6 +146,18 @@ > Example > > > > > for clock block and clock provider: > > > > > clocks = <&sysclk>; > > > > > clock-output-names = "platform-pll", > "platform-pll- > > > > div2"; > > > > > }; > > > > > + > > > > > + fm0clk: fm0-clk-mux { > > > > > + #clock-cells = <0>; > > > > > + reg = <0x10 4> > > > > > + compatible = "fsl,fman-clk-mux"; > > > > > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, > <&pll0 3>, > > > > > + <&platform_pll 0>, <&pll1 1>, <&pll1 > 2>; > > > > > + clock-names = "pll0", "pll0-div2", "pll0-div3", > > > > > + "pll0-div4", "platform-pll", "pll1- > div2", > > > > > + "pll1-div3"; > > > > > + clock-output-names = "fm0-clk"; > > > > > + }; > > > > > }; > > > > > }; > > > > > > > > > > > > > I don't see this register in the manuals for older DPAA chips, > > > > such as > > > > p4080 or p3041. Is it present but undocumented? Should I be > > > > looking somewhere other than "Clocking Memory Map"? > > > > > > > > > > It's available only in part of the new chips (T4, T2, B4). > > > In T1024/T1040 there's only one option for FMan clock so this > > > register is not > > available. > > > > So it's part of the 2.0 chassis? I'd stick a 2.0 in there, then. Who > > knows what we may see in the future. > > > > OK, > We can go with "fsl,fman-clk-mux-1/2-0.". > In that case, we need to update FMan nodes and the clock driver: > https://patchwork.ozlabs.org/patch/443973/ > https://patchwork.ozlabs.org/patch/461813/ > I will update those patches separately. > Scott, There are 2 options: Use "fsl,fman-clk-mux-1.0" for SoC without CLKCGnHWACSR register. Use "fsl,fman-clk-mux-2.0" for SoC with CLKCGnHWACSR register. Or Use "fsl,fman-clk-mux-1.0" for SoC which support FMan V2 (Pxxxx) Use "fsl,fman-clk-mux-2.0" for SoC which support FMan V3 (B/T) Using the 1st option might be confusing because core pll/mux 2.0 represents B/T devices and 1.0 represent Pxxxx. In this case, T1040 uses "fsl,qoriq-core-pll/mux-2.0" and "fsl,fman-clk-mux-1.0". On the other hand, the second option doesn't distinguishes between T4 and T1 (for example), as T1 doesn't have reg property while T4 has. What do you think? > > -Scott > > > > Igal Igal N§²æìr¸yúèØb²X¬¶Ç§vØ^)Þº{.nÇ+·zøzÚÞz)í æèw*\x1fjg¬±¨\x1e¶Ý¢j.ïÛ°\½½MúgjÌæa×\x02' ©Þ¢¸\f¢·¦j:+v¨wèjØm¶ÿ¾\a«êçzZ+ùÝ¢j"ú!¶i ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-04-20 11:40 ` Igal.Liberman 0 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman @ 2015-04-20 11:40 UTC (permalink / raw) To: Scott Wood; +Cc: devicetree, linuxppc-dev DQoNClJlZ2FyZHMsDQpJZ2FsIExpYmVybWFuLg0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0t LS0tDQo+IEZyb206IExpYmVybWFuIElnYWwtQjMxOTUwDQo+IFNlbnQ6IE1vbmRheSwgQXByaWwg MjAsIDIwMTUgMjowNyBQTQ0KPiBUbzogV29vZCBTY290dC1CMDc0MjENCj4gQ2M6IGRldmljZXRy ZWVAdmdlci5rZXJuZWwub3JnOyBsaW51eHBwYy1kZXZAbGlzdHMub3psYWJzLm9yZw0KPiBTdWJq ZWN0OiBSRTogW3YzXSBkdC9iaW5kaW5nczogcW9yaXEtY2xvY2s6IEFkZCBiaW5kaW5nIGZvciBG TWFuIGNsb2NrIG11eA0KPiANCj4gDQo+IA0KPiBSZWdhcmRzLA0KPiBJZ2FsIExpYmVybWFuLg0K PiANCj4gPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+IEZyb206IFdvb2QgU2NvdHQt QjA3NDIxDQo+ID4gU2VudDogRnJpZGF5LCBBcHJpbCAxNywgMjAxNSA4OjQxIEFNDQo+ID4gVG86 IExpYmVybWFuIElnYWwtQjMxOTUwDQo+ID4gQ2M6IGRldmljZXRyZWVAdmdlci5rZXJuZWwub3Jn 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[parent not found: <DM2PR03MB383E5F67C358CCE2E38EA71E6E00-ufbTtyGzTTRJonC5hhDUuuO6mTEJWrR4XA4E9RH9d+qIuWR1G4zioA@public.gmane.org>]
* Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux 2015-04-20 11:40 ` Igal.Liberman @ 2015-04-21 0:51 ` Scott Wood -1 siblings, 0 replies; 26+ messages in thread From: Scott Wood @ 2015-04-21 0:51 UTC (permalink / raw) To: Liberman Igal-B31950 Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Yuantian.Tang-KZfg59tc24xl57MIdRCFDg On Mon, 2015-04-20 at 06:40 -0500, Liberman Igal-B31950 wrote: > > > Regards, > Igal Liberman. > > > -----Original Message----- > > From: Liberman Igal-B31950 > > Sent: Monday, April 20, 2015 2:07 PM > > To: Wood Scott-B07421 > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org > > Subject: RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > > > > > Regards, > > Igal Liberman. > > > > > -----Original Message----- > > > From: Wood Scott-B07421 > > > Sent: Friday, April 17, 2015 8:41 AM > > > To: Liberman Igal-B31950 > > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock > > > mux > > > > > > On Thu, 2015-04-16 at 01:11 -0500, Liberman Igal-B31950 wrote: > > > > > > > > > > > > Regards, > > > > Igal Liberman. > > > > > > > > > -----Original Message----- > > > > > From: Wood Scott-B07421 > > > > > Sent: Wednesday, April 15, 2015 8:36 PM > > > > > To: Liberman Igal-B31950 > > > > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org > > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > > > clock mux > > > > > > > > > > On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > > > > > > From: Igal Liberman <Igal.Liberman-KZfg59tc24xl57MIdRCFDg@public.gmane.org> > > > > > > > > > > > > v3: Addressed feedback from Scott: > > > > > > - Removed clock specifier description. > > > > > > > > > > > > v2: Addressed feedback from Scott: > > > > > > - Moved the "fman-clk-mux" clock provider details > > > > > > under "clocks" property. > > > > > > > > > > > > Signed-off-by: Igal Liberman <Igal.Liberman-KZfg59tc24xl57MIdRCFDg@public.gmane.org> > > > > > > --- > > > > > > .../devicetree/bindings/clock/qoriq-clock.txt | 17 > > > +++++++++++++++-- > > > > > > 1 file changed, 15 insertions(+), 2 deletions(-) > > > > > > > > > > > > diff --git > > > > > > a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > index b0d7b73..2bb3b38 100644 > > > > > > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > @@ -65,9 +65,10 @@ Required properties: > > > > > > It takes parent's clock-frequency as its clock. > > > > > > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > > > > > > * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock > > > > > > (v2.0) > > > > > > + * "fsl,fman-clk-mux" for the Frame Manager clock. > > > > > > - #clock-cells: From common clock binding. The number of cells in a > > > > > > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > > > > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > > > > > > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > and > > > > > > + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll- > > [1,2].0". > > > > > > For "fsl,qoriq-core-pll-1.0" clocks, the single > > > > > > clock-specifier cell may take the following values: > > > > > > * 0 - equal to the PLL frequency @@ -145,6 +146,18 @@ > > Example > > > > > > for clock block and clock provider: > > > > > > clocks = <&sysclk>; > > > > > > clock-output-names = "platform-pll", > > "platform-pll- > > > > > div2"; > > > > > > }; > > > > > > + > > > > > > + fm0clk: fm0-clk-mux { > > > > > > + #clock-cells = <0>; > > > > > > + reg = <0x10 4> > > > > > > + compatible = "fsl,fman-clk-mux"; > > > > > > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, > > <&pll0 3>, > > > > > > + <&platform_pll 0>, <&pll1 1>, <&pll1 > > 2>; > > > > > > + clock-names = "pll0", "pll0-div2", "pll0-div3", > > > > > > + "pll0-div4", "platform-pll", "pll1- > > div2", > > > > > > + "pll1-div3"; > > > > > > + clock-output-names = "fm0-clk"; > > > > > > + }; > > > > > > }; > > > > > > }; > > > > > > > > > > > > > > > > I don't see this register in the manuals for older DPAA chips, > > > > > such as > > > > > p4080 or p3041. Is it present but undocumented? Should I be > > > > > looking somewhere other than "Clocking Memory Map"? > > > > > > > > > > > > > It's available only in part of the new chips (T4, T2, B4). > > > > In T1024/T1040 there's only one option for FMan clock so this > > > > register is not > > > available. > > > > > > So it's part of the 2.0 chassis? I'd stick a 2.0 in there, then. Who > > > knows what we may see in the future. > > > > > > > OK, > > We can go with "fsl,fman-clk-mux-1/2-0.". > > In that case, we need to update FMan nodes and the clock driver: > > https://patchwork.ozlabs.org/patch/443973/ > > https://patchwork.ozlabs.org/patch/461813/ > > I will update those patches separately. > > > > Scott, > There are 2 options: > Use "fsl,fman-clk-mux-1.0" for SoC without CLKCGnHWACSR register. > Use "fsl,fman-clk-mux-2.0" for SoC with CLKCGnHWACSR register. > Or > Use "fsl,fman-clk-mux-1.0" for SoC which support FMan V2 (Pxxxx) > Use "fsl,fman-clk-mux-2.0" for SoC which support FMan V3 (B/T) 1.0/2.0 in the clockgen node refers to chassis version. It has nothing to do with FMan version. In fact, fman should not be in the compatible because, now that I found the documentation for this, I see that it's more generic than that. "fman-clk-mux" should be replaced with "qoriq-hwacsr". > Using the 1st option might be confusing because core pll/mux 2.0 represents B/T devices and 1.0 represent Pxxxx. > In this case, T1040 uses "fsl,qoriq-core-pll/mux-2.0" and "fsl,fman-clk-mux-1.0". > On the other hand, the second option doesn't distinguishes between T4 and T1 (for example), as T1 doesn't have reg property while T4 has. How would t1040 have a so-called "fman-clk-mux" node at all if it doesn't have this register? I think we've made a mess of the clock bindings and this is only going to make it worse. We need to stay compatible with the mess we've made, but I'm inclined to say that we shouldn't add more nodes to it. Instead, have the toplevel clockgen node have a chip-based compatible in addition to version (e.g. compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0") and have the toplevel node export whatever clocks are needed. Put the logic to deal with all the different dividers, register values, and such in code, not the device tree. The binding should be focused on how to encode the specifier of the exported clocks. -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-04-21 0:51 ` Scott Wood 0 siblings, 0 replies; 26+ messages in thread From: Scott Wood @ 2015-04-21 0:51 UTC (permalink / raw) To: Liberman Igal-B31950; +Cc: devicetree, linuxppc-dev, Yuantian.Tang On Mon, 2015-04-20 at 06:40 -0500, Liberman Igal-B31950 wrote: > > > Regards, > Igal Liberman. > > > -----Original Message----- > > From: Liberman Igal-B31950 > > Sent: Monday, April 20, 2015 2:07 PM > > To: Wood Scott-B07421 > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > Subject: RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > > > > > Regards, > > Igal Liberman. > > > > > -----Original Message----- > > > From: Wood Scott-B07421 > > > Sent: Friday, April 17, 2015 8:41 AM > > > To: Liberman Igal-B31950 > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock > > > mux > > > > > > On Thu, 2015-04-16 at 01:11 -0500, Liberman Igal-B31950 wrote: > > > > > > > > > > > > Regards, > > > > Igal Liberman. > > > > > > > > > -----Original Message----- > > > > > From: Wood Scott-B07421 > > > > > Sent: Wednesday, April 15, 2015 8:36 PM > > > > > To: Liberman Igal-B31950 > > > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > > > clock mux > > > > > > > > > > On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > > > > > > From: Igal Liberman <Igal.Liberman@freescale.com> > > > > > > > > > > > > v3: Addressed feedback from Scott: > > > > > > - Removed clock specifier description. > > > > > > > > > > > > v2: Addressed feedback from Scott: > > > > > > - Moved the "fman-clk-mux" clock provider details > > > > > > under "clocks" property. > > > > > > > > > > > > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> > > > > > > --- > > > > > > .../devicetree/bindings/clock/qoriq-clock.txt | 17 > > > +++++++++++++++-- > > > > > > 1 file changed, 15 insertions(+), 2 deletions(-) > > > > > > > > > > > > diff --git > > > > > > a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > index b0d7b73..2bb3b38 100644 > > > > > > --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > @@ -65,9 +65,10 @@ Required properties: > > > > > > It takes parent's clock-frequency as its clock. > > > > > > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > > > > > > * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock > > > > > > (v2.0) > > > > > > + * "fsl,fman-clk-mux" for the Frame Manager clock. > > > > > > - #clock-cells: From common clock binding. The number of cells in a > > > > > > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > > > > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > > > > > > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > and > > > > > > + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll- > > [1,2].0". > > > > > > For "fsl,qoriq-core-pll-1.0" clocks, the single > > > > > > clock-specifier cell may take the following values: > > > > > > * 0 - equal to the PLL frequency @@ -145,6 +146,18 @@ > > Example > > > > > > for clock block and clock provider: > > > > > > clocks = <&sysclk>; > > > > > > clock-output-names = "platform-pll", > > "platform-pll- > > > > > div2"; > > > > > > }; > > > > > > + > > > > > > + fm0clk: fm0-clk-mux { > > > > > > + #clock-cells = <0>; > > > > > > + reg = <0x10 4> > > > > > > + compatible = "fsl,fman-clk-mux"; > > > > > > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, > > <&pll0 3>, > > > > > > + <&platform_pll 0>, <&pll1 1>, <&pll1 > > 2>; > > > > > > + clock-names = "pll0", "pll0-div2", "pll0-div3", > > > > > > + "pll0-div4", "platform-pll", "pll1- > > div2", > > > > > > + "pll1-div3"; > > > > > > + clock-output-names = "fm0-clk"; > > > > > > + }; > > > > > > }; > > > > > > }; > > > > > > > > > > > > > > > > I don't see this register in the manuals for older DPAA chips, > > > > > such as > > > > > p4080 or p3041. Is it present but undocumented? Should I be > > > > > looking somewhere other than "Clocking Memory Map"? > > > > > > > > > > > > > It's available only in part of the new chips (T4, T2, B4). > > > > In T1024/T1040 there's only one option for FMan clock so this > > > > register is not > > > available. > > > > > > So it's part of the 2.0 chassis? I'd stick a 2.0 in there, then. Who > > > knows what we may see in the future. > > > > > > > OK, > > We can go with "fsl,fman-clk-mux-1/2-0.". > > In that case, we need to update FMan nodes and the clock driver: > > https://patchwork.ozlabs.org/patch/443973/ > > https://patchwork.ozlabs.org/patch/461813/ > > I will update those patches separately. > > > > Scott, > There are 2 options: > Use "fsl,fman-clk-mux-1.0" for SoC without CLKCGnHWACSR register. > Use "fsl,fman-clk-mux-2.0" for SoC with CLKCGnHWACSR register. > Or > Use "fsl,fman-clk-mux-1.0" for SoC which support FMan V2 (Pxxxx) > Use "fsl,fman-clk-mux-2.0" for SoC which support FMan V3 (B/T) 1.0/2.0 in the clockgen node refers to chassis version. It has nothing to do with FMan version. In fact, fman should not be in the compatible because, now that I found the documentation for this, I see that it's more generic than that. "fman-clk-mux" should be replaced with "qoriq-hwacsr". > Using the 1st option might be confusing because core pll/mux 2.0 represents B/T devices and 1.0 represent Pxxxx. > In this case, T1040 uses "fsl,qoriq-core-pll/mux-2.0" and "fsl,fman-clk-mux-1.0". > On the other hand, the second option doesn't distinguishes between T4 and T1 (for example), as T1 doesn't have reg property while T4 has. How would t1040 have a so-called "fman-clk-mux" node at all if it doesn't have this register? I think we've made a mess of the clock bindings and this is only going to make it worse. We need to stay compatible with the mess we've made, but I'm inclined to say that we shouldn't add more nodes to it. Instead, have the toplevel clockgen node have a chip-based compatible in addition to version (e.g. compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0") and have the toplevel node export whatever clocks are needed. Put the logic to deal with all the different dividers, register values, and such in code, not the device tree. The binding should be focused on how to encode the specifier of the exported clocks. -Scott ^ permalink raw reply [flat|nested] 26+ messages in thread
[parent not found: <1429577504.4352.67.camel-KZfg59tc24xl57MIdRCFDg@public.gmane.org>]
* RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux 2015-04-21 0:51 ` Scott Wood @ 2015-04-22 10:47 ` Igal.Liberman -1 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman-KZfg59tc24xl57MIdRCFDg @ 2015-04-22 10:47 UTC (permalink / raw) To: Scott Wood Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Yuantian Tang Regards, Igal Liberman. > -----Original Message----- > From: Wood Scott-B07421 > Sent: Tuesday, April 21, 2015 3:52 AM > To: Liberman Igal-B31950 > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Tang > Yuantian-B29983 > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > On Mon, 2015-04-20 at 06:40 -0500, Liberman Igal-B31950 wrote: > > > > > > Regards, > > Igal Liberman. > > > > > -----Original Message----- > > > From: Liberman Igal-B31950 > > > Sent: Monday, April 20, 2015 2:07 PM > > > To: Wood Scott-B07421 > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > Subject: RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > clock mux > > > > > > > > > > > > Regards, > > > Igal Liberman. > > > > > > > -----Original Message----- > > > > From: Wood Scott-B07421 > > > > Sent: Friday, April 17, 2015 8:41 AM > > > > To: Liberman Igal-B31950 > > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > > clock mux > > > > > > > > On Thu, 2015-04-16 at 01:11 -0500, Liberman Igal-B31950 wrote: > > > > > > > > > > > > > > > Regards, > > > > > Igal Liberman. > > > > > > > > > > > -----Original Message----- > > > > > > From: Wood Scott-B07421 > > > > > > Sent: Wednesday, April 15, 2015 8:36 PM > > > > > > To: Liberman Igal-B31950 > > > > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for > > > > > > FMan clock mux > > > > > > > > > > > > On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > > > > > > > From: Igal Liberman <Igal.Liberman@freescale.com> > > > > > > > > > > > > > > v3: Addressed feedback from Scott: > > > > > > > - Removed clock specifier description. > > > > > > > > > > > > > > v2: Addressed feedback from Scott: > > > > > > > - Moved the "fman-clk-mux" clock provider details > > > > > > > under "clocks" property. > > > > > > > > > > > > > > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> > > > > > > > --- > > > > > > > .../devicetree/bindings/clock/qoriq-clock.txt | 17 > > > > +++++++++++++++-- > > > > > > > 1 file changed, 15 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > diff --git > > > > > > > a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > > index b0d7b73..2bb3b38 100644 > > > > > > > --- > > > > > > > a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.tx > > > > > > > +++ t > > > > > > > @@ -65,9 +65,10 @@ Required properties: > > > > > > > It takes parent's clock-frequency as its clock. > > > > > > > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > > > > > > > * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock > > > > > > > (v2.0) > > > > > > > + * "fsl,fman-clk-mux" for the Frame Manager clock. > > > > > > > - #clock-cells: From common clock binding. The number of cells in > a > > > > > > > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > > > > > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > > > > > > > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > and > > > > > > > + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll- > > > [1,2].0". > > > > > > > For "fsl,qoriq-core-pll-1.0" clocks, the single > > > > > > > clock-specifier cell may take the following values: > > > > > > > * 0 - equal to the PLL frequency @@ -145,6 +146,18 @@ > > > Example > > > > > > > for clock block and clock provider: > > > > > > > clocks = <&sysclk>; > > > > > > > clock-output-names = "platform-pll", > > > "platform-pll- > > > > > > div2"; > > > > > > > }; > > > > > > > + > > > > > > > + fm0clk: fm0-clk-mux { > > > > > > > + #clock-cells = <0>; > > > > > > > + reg = <0x10 4> > > > > > > > + compatible = "fsl,fman-clk-mux"; > > > > > > > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, > > > <&pll0 3>, > > > > > > > + <&platform_pll 0>, <&pll1 1>, <&pll1 > > > 2>; > > > > > > > + clock-names = "pll0", "pll0-div2", "pll0-div3", > > > > > > > + "pll0-div4", "platform-pll", "pll1- > > > div2", > > > > > > > + "pll1-div3"; > > > > > > > + clock-output-names = "fm0-clk"; > > > > > > > + }; > > > > > > > }; > > > > > > > }; > > > > > > > > > > > > > > > > > > > I don't see this register in the manuals for older DPAA chips, > > > > > > such as > > > > > > p4080 or p3041. Is it present but undocumented? Should I be > > > > > > looking somewhere other than "Clocking Memory Map"? > > > > > > > > > > > > > > > > It's available only in part of the new chips (T4, T2, B4). > > > > > In T1024/T1040 there's only one option for FMan clock so this > > > > > register is not > > > > available. > > > > > > > > So it's part of the 2.0 chassis? I'd stick a 2.0 in there, then. > > > > Who knows what we may see in the future. > > > > > > > > > > OK, > > > We can go with "fsl,fman-clk-mux-1/2-0.". > > > In that case, we need to update FMan nodes and the clock driver: > > > https://patchwork.ozlabs.org/patch/443973/ > > > https://patchwork.ozlabs.org/patch/461813/ > > > I will update those patches separately. > > > > > > > Scott, > > There are 2 options: > > Use "fsl,fman-clk-mux-1.0" for SoC without CLKCGnHWACSR register. > > Use "fsl,fman-clk-mux-2.0" for SoC with CLKCGnHWACSR register. > > Or > > Use "fsl,fman-clk-mux-1.0" for SoC which support FMan V2 (Pxxxx) Use > > "fsl,fman-clk-mux-2.0" for SoC which support FMan V3 (B/T) > > 1.0/2.0 in the clockgen node refers to chassis version. It has nothing to do > with FMan version. > I know. However there's a match: 1.0 chassis used in SoC with FMan v2 and 2.0 chassis in SoC with FMan v3. > In fact, fman should not be in the compatible because, now that I found the > documentation for this, I see that it's more generic than that. > "fman-clk-mux" should be replaced with "qoriq-hwacsr". > > > Using the 1st option might be confusing because core pll/mux 2.0 > represents B/T devices and 1.0 represent Pxxxx. > > In this case, T1040 uses "fsl,qoriq-core-pll/mux-2.0" and "fsl,fman-clk-mux- > 1.0". > > On the other hand, the second option doesn't distinguishes between T4 > and T1 (for example), as T1 doesn't have reg property while T4 has. > > How would t1040 have a so-called "fman-clk-mux" node at all if it doesn't > have this register? > > I think we've made a mess of the clock bindings and this is only going to make > it worse. We need to stay compatible with the mess we've made, but I'm > inclined to say that we shouldn't add more nodes to it. > > Instead, have the toplevel clockgen node have a chip-based compatible in > addition to version (e.g. compatible = "fsl,t4240-clockgen", > "fsl,qoriq-clockgen-2.0") and have the toplevel node export whatever clocks > are needed. Put the logic to deal with all the different dividers, register > values, and such in code, not the device tree. The binding should be focused > on how to encode the specifier of the exported clocks. > We have 2 cases: - Devices (T2/T4/B4) with CLKCG1HWACSR register. - Devices (Pxxxx, T1) without CLKCG1HWACSR register (Pxxxx devices have many options, T1 has only one option) For the first group, we can have " qoriq-hwacsr" property in the clock node. Currently T4 FMan clock mux node is the following: fm1clk: fm1-clk-mux { #clock-cells = <0>; compatible = "fsl,fman-clk-mux"; clocks = <&pll1 1>, <&pll1 2>, <&pll1 3>, <&platform_pll 0>, <&pll0 1>, <&pll0 2>; clock-names = "pll1-div2", "pll1-div3", "pll1-div4", "platform-pll", "pll0-div2", "pll0-div3"; clock-output-names = "fm1-clk"; }; As far as I understand we need to move the node to the top level clock node. In addition we need to add reg property and change the name of the node and the compatible. In that case, the driver can read this register instead of parsing the RCW. What about the devices of the second group? In this case we don't have a register to determine the source clock. So we need access to guts registers, like we have currently. The suggestion above doesn’t suit for those devices. > -Scott > Igal ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-04-22 10:47 ` Igal.Liberman 0 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman @ 2015-04-22 10:47 UTC (permalink / raw) To: Scott Wood; +Cc: devicetree, linuxppc-dev, Yuantian Tang DQoNClJlZ2FyZHMsDQpJZ2FsIExpYmVybWFuLg0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0t LS0tDQo+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIxDQo+IFNlbnQ6IFR1ZXNkYXksIEFwcmlsIDIx LCAyMDE1IDM6NTIgQU0NCj4gVG86IExpYmVybWFuIElnYWwtQjMxOTUwDQo+IENjOiBkZXZpY2V0 cmVlQHZnZXIua2VybmVsLm9yZzsgbGludXhwcGMtZGV2QGxpc3RzLm96bGFicy5vcmc7IFRhbmcN Cj4gWXVhbnRpYW4tQjI5OTgzDQo+IFN1YmplY3Q6IFJlOiBbdjNdIGR0L2JpbmRpbmdzOiBxb3Jp cS1jbG9jazogQWRkIGJpbmRpbmcgZm9yIEZNYW4gY2xvY2sgbXV4DQo+IA0KPiBPbiBNb24sIDIw MTUtMDQtMjAgYXQgMDY6NDAgLTA1MDAsIExpYmVybWFuIElnYWwtQjMxOTUwIHdyb3RlOg0KPiA+ DQo+ID4NCj4gPiBSZWdhcmRzLA0KPiA+IElnYWwgTGliZXJtYW4uDQo+ID4NCj4gPiA+IC0tLS0t T3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+ID4gPiBGcm9tOiBMaWJlcm1hbiBJZ2FsLUIzMTk1MA0K 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* Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux 2015-04-22 10:47 ` Igal.Liberman @ 2015-04-30 0:30 ` Scott Wood -1 siblings, 0 replies; 26+ messages in thread From: Scott Wood @ 2015-04-30 0:30 UTC (permalink / raw) To: Liberman Igal-B31950 Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Tang Yuantian-B29983 On Wed, 2015-04-22 at 05:47 -0500, Liberman Igal-B31950 wrote: > > > Regards, > Igal Liberman. > > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Tuesday, April 21, 2015 3:52 AM > > To: Liberman Igal-B31950 > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org; Tang > > Yuantian-B29983 > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > On Mon, 2015-04-20 at 06:40 -0500, Liberman Igal-B31950 wrote: > > > > > > > > > Regards, > > > Igal Liberman. > > > > > > > -----Original Message----- > > > > From: Liberman Igal-B31950 > > > > Sent: Monday, April 20, 2015 2:07 PM > > > > To: Wood Scott-B07421 > > > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org > > > > Subject: RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > > clock mux > > > > > > > > > > > > > > > > Regards, > > > > Igal Liberman. > > > > > > > > > -----Original Message----- > > > > > From: Wood Scott-B07421 > > > > > Sent: Friday, April 17, 2015 8:41 AM > > > > > To: Liberman Igal-B31950 > > > > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org > > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > > > clock mux > > > > > > > > > > On Thu, 2015-04-16 at 01:11 -0500, Liberman Igal-B31950 wrote: > > > > > > > > > > > > > > > > > > Regards, > > > > > > Igal Liberman. > > > > > > > > > > > > > -----Original Message----- > > > > > > > From: Wood Scott-B07421 > > > > > > > Sent: Wednesday, April 15, 2015 8:36 PM > > > > > > > To: Liberman Igal-B31950 > > > > > > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlazAvgg39JiuA@public.gmane.org.org > > > > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for > > > > > > > FMan clock mux > > > > > > > > > > > > > > On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > > > > > > > > From: Igal Liberman <Igal.Liberman-KZfg59tc24xl57MIdRCFDg@public.gmane.org> > > > > > > > > > > > > > > > > v3: Addressed feedback from Scott: > > > > > > > > - Removed clock specifier description. > > > > > > > > > > > > > > > > v2: Addressed feedback from Scott: > > > > > > > > - Moved the "fman-clk-mux" clock provider details > > > > > > > > under "clocks" property. > > > > > > > > > > > > > > > > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> > > > > > > > > --- > > > > > > > > .../devicetree/bindings/clock/qoriq-clock.txt | 17 > > > > > +++++++++++++++-- > > > > > > > > 1 file changed, 15 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > > > diff --git > > > > > > > > a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > > > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > > > index b0d7b73..2bb3b38 100644 > > > > > > > > --- > > > > > > > > a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > > > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.tx > > > > > > > > +++ t > > > > > > > > @@ -65,9 +65,10 @@ Required properties: > > > > > > > > It takes parent's clock-frequency as its clock. > > > > > > > > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > > > > > > > > * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock > > > > > > > > (v2.0) > > > > > > > > + * "fsl,fman-clk-mux" for the Frame Manager clock. > > > > > > > > - #clock-cells: From common clock binding. The number of cells in > > a > > > > > > > > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > > > > > > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > > > > > > > > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > > and > > > > > > > > + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll- > > > > [1,2].0". > > > > > > > > For "fsl,qoriq-core-pll-1.0" clocks, the single > > > > > > > > clock-specifier cell may take the following values: > > > > > > > > * 0 - equal to the PLL frequency @@ -145,6 +146,18 @@ > > > > Example > > > > > > > > for clock block and clock provider: > > > > > > > > clocks = <&sysclk>; > > > > > > > > clock-output-names = "platform-pll", > > > > "platform-pll- > > > > > > > div2"; > > > > > > > > }; > > > > > > > > + > > > > > > > > + fm0clk: fm0-clk-mux { > > > > > > > > + #clock-cells = <0>; > > > > > > > > + reg = <0x10 4> > > > > > > > > + compatible = "fsl,fman-clk-mux"; > > > > > > > > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, > > > > <&pll0 3>, > > > > > > > > + <&platform_pll 0>, <&pll1 1>, <&pll1 > > > > 2>; > > > > > > > > + clock-names = "pll0", "pll0-div2", "pll0-div3", > > > > > > > > + "pll0-div4", "platform-pll", "pll1- > > > > div2", > > > > > > > > + "pll1-div3"; > > > > > > > > + clock-output-names = "fm0-clk"; > > > > > > > > + }; > > > > > > > > }; > > > > > > > > }; > > > > > > > > > > > > > > > > > > > > > > I don't see this register in the manuals for older DPAA chips, > > > > > > > such as > > > > > > > p4080 or p3041. Is it present but undocumented? Should I be > > > > > > > looking somewhere other than "Clocking Memory Map"? > > > > > > > > > > > > > > > > > > > It's available only in part of the new chips (T4, T2, B4). > > > > > > In T1024/T1040 there's only one option for FMan clock so this > > > > > > register is not > > > > > available. > > > > > > > > > > So it's part of the 2.0 chassis? I'd stick a 2.0 in there, then. > > > > > Who knows what we may see in the future. > > > > > > > > > > > > > OK, > > > > We can go with "fsl,fman-clk-mux-1/2-0.". > > > > In that case, we need to update FMan nodes and the clock driver: > > > > https://patchwork.ozlabs.org/patch/443973/ > > > > https://patchwork.ozlabs.org/patch/461813/ > > > > I will update those patches separately. > > > > > > > > > > Scott, > > > There are 2 options: > > > Use "fsl,fman-clk-mux-1.0" for SoC without CLKCGnHWACSR register. > > > Use "fsl,fman-clk-mux-2.0" for SoC with CLKCGnHWACSR register. > > > Or > > > Use "fsl,fman-clk-mux-1.0" for SoC which support FMan V2 (Pxxxx) Use > > > "fsl,fman-clk-mux-2.0" for SoC which support FMan V3 (B/T) > > > > 1.0/2.0 in the clockgen node refers to chassis version. It has nothing to do > > with FMan version. > > > > I know. However there's a match: 1.0 chassis used in SoC with FMan v2 and 2.0 chassis in SoC with FMan v3. > > > In fact, fman should not be in the compatible because, now that I found the > > documentation for this, I see that it's more generic than that. > > "fman-clk-mux" should be replaced with "qoriq-hwacsr". > > > > > Using the 1st option might be confusing because core pll/mux 2.0 > > represents B/T devices and 1.0 represent Pxxxx. > > > In this case, T1040 uses "fsl,qoriq-core-pll/mux-2.0" and "fsl,fman-clk-mux- > > 1.0". > > > On the other hand, the second option doesn't distinguishes between T4 > > and T1 (for example), as T1 doesn't have reg property while T4 has. > > > > How would t1040 have a so-called "fman-clk-mux" node at all if it doesn't > > have this register? > > > > I think we've made a mess of the clock bindings and this is only going to make > > it worse. We need to stay compatible with the mess we've made, but I'm > > inclined to say that we shouldn't add more nodes to it. > > > > Instead, have the toplevel clockgen node have a chip-based compatible in > > addition to version (e.g. compatible = "fsl,t4240-clockgen", > > "fsl,qoriq-clockgen-2.0") and have the toplevel node export whatever clocks > > are needed. Put the logic to deal with all the different dividers, register > > values, and such in code, not the device tree. The binding should be focused > > on how to encode the specifier of the exported clocks. > > > > We have 2 cases: > - Devices (T2/T4/B4) with CLKCG1HWACSR register. > - Devices (Pxxxx, T1) without CLKCG1HWACSR register (Pxxxx devices have many options, T1 has only one option) > > For the first group, we can have " qoriq-hwacsr" property in the clock node. No, we're not going to describe every register with its own property. Describe the chip and let the driver be the place with the knowledge of what each chip is like. > Currently T4 FMan clock mux node is the following: > fm1clk: fm1-clk-mux { > #clock-cells = <0>; > compatible = "fsl,fman-clk-mux"; > clocks = <&pll1 1>, <&pll1 2>, <&pll1 3>, > <&platform_pll 0>, <&pll0 1>, <&pll0 2>; > clock-names = "pll1-div2", "pll1-div3", "pll1-div4", > "platform-pll", "pll0-div2", "pll0-div3"; > clock-output-names = "fm1-clk"; > }; > As far as I understand we need to move the node to the top level clock node. > In addition we need to add reg property and change the name of the node and the compatible. > In that case, the driver can read this register instead of parsing the RCW. I'm having a hard time following. What I'm suggesting is eliminating the above and having the clockgen node itself (which already has a reg property) be a clock source with a clock specifier encoding that distinguishes the fman clock from other clocks. > What about the devices of the second group? > In this case we don't have a register to determine the source clock. So we need access to guts registers, I never suggested taking away access to the guts registers. > like we have currently. > The suggestion above doesn’t suit for those devices. How is the clock determined on those chips? -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-04-30 0:30 ` Scott Wood 0 siblings, 0 replies; 26+ messages in thread From: Scott Wood @ 2015-04-30 0:30 UTC (permalink / raw) To: Liberman Igal-B31950; +Cc: devicetree, linuxppc-dev, Tang Yuantian-B29983 On Wed, 2015-04-22 at 05:47 -0500, Liberman Igal-B31950 wrote: > > > Regards, > Igal Liberman. > > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Tuesday, April 21, 2015 3:52 AM > > To: Liberman Igal-B31950 > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Tang > > Yuantian-B29983 > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > On Mon, 2015-04-20 at 06:40 -0500, Liberman Igal-B31950 wrote: > > > > > > > > > Regards, > > > Igal Liberman. > > > > > > > -----Original Message----- > > > > From: Liberman Igal-B31950 > > > > Sent: Monday, April 20, 2015 2:07 PM > > > > To: Wood Scott-B07421 > > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > > Subject: RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > > clock mux > > > > > > > > > > > > > > > > Regards, > > > > Igal Liberman. > > > > > > > > > -----Original Message----- > > > > > From: Wood Scott-B07421 > > > > > Sent: Friday, April 17, 2015 8:41 AM > > > > > To: Liberman Igal-B31950 > > > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > > > clock mux > > > > > > > > > > On Thu, 2015-04-16 at 01:11 -0500, Liberman Igal-B31950 wrote: > > > > > > > > > > > > > > > > > > Regards, > > > > > > Igal Liberman. > > > > > > > > > > > > > -----Original Message----- > > > > > > > From: Wood Scott-B07421 > > > > > > > Sent: Wednesday, April 15, 2015 8:36 PM > > > > > > > To: Liberman Igal-B31950 > > > > > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for > > > > > > > FMan clock mux > > > > > > > > > > > > > > On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > > > > > > > > From: Igal Liberman <Igal.Liberman@freescale.com> > > > > > > > > > > > > > > > > v3: Addressed feedback from Scott: > > > > > > > > - Removed clock specifier description. > > > > > > > > > > > > > > > > v2: Addressed feedback from Scott: > > > > > > > > - Moved the "fman-clk-mux" clock provider details > > > > > > > > under "clocks" property. > > > > > > > > > > > > > > > > Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> > > > > > > > > --- > > > > > > > > .../devicetree/bindings/clock/qoriq-clock.txt | 17 > > > > > +++++++++++++++-- > > > > > > > > 1 file changed, 15 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > > > diff --git > > > > > > > > a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > > > b/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > > > index b0d7b73..2bb3b38 100644 > > > > > > > > --- > > > > > > > > a/Documentation/devicetree/bindings/clock/qoriq-clock.txt > > > > > > > > +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.tx > > > > > > > > +++ t > > > > > > > > @@ -65,9 +65,10 @@ Required properties: > > > > > > > > It takes parent's clock-frequency as its clock. > > > > > > > > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > > > > > > > > * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock > > > > > > > > (v2.0) > > > > > > > > + * "fsl,fman-clk-mux" for the Frame Manager clock. > > > > > > > > - #clock-cells: From common clock binding. The number of cells in > > a > > > > > > > > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > > > > > > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > > > > > > > > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > > and > > > > > > > > + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll- > > > > [1,2].0". > > > > > > > > For "fsl,qoriq-core-pll-1.0" clocks, the single > > > > > > > > clock-specifier cell may take the following values: > > > > > > > > * 0 - equal to the PLL frequency @@ -145,6 +146,18 @@ > > > > Example > > > > > > > > for clock block and clock provider: > > > > > > > > clocks = <&sysclk>; > > > > > > > > clock-output-names = "platform-pll", > > > > "platform-pll- > > > > > > > div2"; > > > > > > > > }; > > > > > > > > + > > > > > > > > + fm0clk: fm0-clk-mux { > > > > > > > > + #clock-cells = <0>; > > > > > > > > + reg = <0x10 4> > > > > > > > > + compatible = "fsl,fman-clk-mux"; > > > > > > > > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, > > > > <&pll0 3>, > > > > > > > > + <&platform_pll 0>, <&pll1 1>, <&pll1 > > > > 2>; > > > > > > > > + clock-names = "pll0", "pll0-div2", "pll0-div3", > > > > > > > > + "pll0-div4", "platform-pll", "pll1- > > > > div2", > > > > > > > > + "pll1-div3"; > > > > > > > > + clock-output-names = "fm0-clk"; > > > > > > > > + }; > > > > > > > > }; > > > > > > > > }; > > > > > > > > > > > > > > > > > > > > > > I don't see this register in the manuals for older DPAA chips, > > > > > > > such as > > > > > > > p4080 or p3041. Is it present but undocumented? Should I be > > > > > > > looking somewhere other than "Clocking Memory Map"? > > > > > > > > > > > > > > > > > > > It's available only in part of the new chips (T4, T2, B4). > > > > > > In T1024/T1040 there's only one option for FMan clock so this > > > > > > register is not > > > > > available. > > > > > > > > > > So it's part of the 2.0 chassis? I'd stick a 2.0 in there, then. > > > > > Who knows what we may see in the future. > > > > > > > > > > > > > OK, > > > > We can go with "fsl,fman-clk-mux-1/2-0.". > > > > In that case, we need to update FMan nodes and the clock driver: > > > > https://patchwork.ozlabs.org/patch/443973/ > > > > https://patchwork.ozlabs.org/patch/461813/ > > > > I will update those patches separately. > > > > > > > > > > Scott, > > > There are 2 options: > > > Use "fsl,fman-clk-mux-1.0" for SoC without CLKCGnHWACSR register. > > > Use "fsl,fman-clk-mux-2.0" for SoC with CLKCGnHWACSR register. > > > Or > > > Use "fsl,fman-clk-mux-1.0" for SoC which support FMan V2 (Pxxxx) Use > > > "fsl,fman-clk-mux-2.0" for SoC which support FMan V3 (B/T) > > > > 1.0/2.0 in the clockgen node refers to chassis version. It has nothing to do > > with FMan version. > > > > I know. However there's a match: 1.0 chassis used in SoC with FMan v2 and 2.0 chassis in SoC with FMan v3. > > > In fact, fman should not be in the compatible because, now that I found the > > documentation for this, I see that it's more generic than that. > > "fman-clk-mux" should be replaced with "qoriq-hwacsr". > > > > > Using the 1st option might be confusing because core pll/mux 2.0 > > represents B/T devices and 1.0 represent Pxxxx. > > > In this case, T1040 uses "fsl,qoriq-core-pll/mux-2.0" and "fsl,fman-clk-mux- > > 1.0". > > > On the other hand, the second option doesn't distinguishes between T4 > > and T1 (for example), as T1 doesn't have reg property while T4 has. > > > > How would t1040 have a so-called "fman-clk-mux" node at all if it doesn't > > have this register? > > > > I think we've made a mess of the clock bindings and this is only going to make > > it worse. We need to stay compatible with the mess we've made, but I'm > > inclined to say that we shouldn't add more nodes to it. > > > > Instead, have the toplevel clockgen node have a chip-based compatible in > > addition to version (e.g. compatible = "fsl,t4240-clockgen", > > "fsl,qoriq-clockgen-2.0") and have the toplevel node export whatever clocks > > are needed. Put the logic to deal with all the different dividers, register > > values, and such in code, not the device tree. The binding should be focused > > on how to encode the specifier of the exported clocks. > > > > We have 2 cases: > - Devices (T2/T4/B4) with CLKCG1HWACSR register. > - Devices (Pxxxx, T1) without CLKCG1HWACSR register (Pxxxx devices have many options, T1 has only one option) > > For the first group, we can have " qoriq-hwacsr" property in the clock node. No, we're not going to describe every register with its own property. Describe the chip and let the driver be the place with the knowledge of what each chip is like. > Currently T4 FMan clock mux node is the following: > fm1clk: fm1-clk-mux { > #clock-cells = <0>; > compatible = "fsl,fman-clk-mux"; > clocks = <&pll1 1>, <&pll1 2>, <&pll1 3>, > <&platform_pll 0>, <&pll0 1>, <&pll0 2>; > clock-names = "pll1-div2", "pll1-div3", "pll1-div4", > "platform-pll", "pll0-div2", "pll0-div3"; > clock-output-names = "fm1-clk"; > }; > As far as I understand we need to move the node to the top level clock node. > In addition we need to add reg property and change the name of the node and the compatible. > In that case, the driver can read this register instead of parsing the RCW. I'm having a hard time following. What I'm suggesting is eliminating the above and having the clockgen node itself (which already has a reg property) be a clock source with a clock specifier encoding that distinguishes the fman clock from other clocks. > What about the devices of the second group? > In this case we don't have a register to determine the source clock. So we need access to guts registers, I never suggested taking away access to the guts registers. > like we have currently. > The suggestion above doesn’t suit for those devices. How is the clock determined on those chips? -Scott ^ permalink raw reply [flat|nested] 26+ messages in thread
[parent not found: <1430353832.16357.138.camel-KZfg59tc24xl57MIdRCFDg@public.gmane.org>]
* RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux 2015-04-30 0:30 ` Scott Wood @ 2015-04-30 14:28 ` Igal.Liberman -1 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman-KZfg59tc24xl57MIdRCFDg @ 2015-04-30 14:28 UTC (permalink / raw) To: Scott Wood Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Yuantian Tang Regards, Igal Liberman. > -----Original Message----- > From: Wood Scott-B07421 > Sent: Thursday, April 30, 2015 3:31 AM > To: Liberman Igal-B31950 > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Tang > Yuantian-B29983 > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > On Wed, 2015-04-22 at 05:47 -0500, Liberman Igal-B31950 wrote: > > > > > > Regards, > > Igal Liberman. > > > > > -----Original Message----- > > > From: Wood Scott-B07421 > > > Sent: Tuesday, April 21, 2015 3:52 AM > > > To: Liberman Igal-B31950 > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Tang > > > Yuantian-B29983 > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > clock mux > > > > > > On Mon, 2015-04-20 at 06:40 -0500, Liberman Igal-B31950 wrote: > > > > > > > > > > > > Regards, > > > > Igal Liberman. > > > > > > > > > -----Original Message----- > > > > > From: Liberman Igal-B31950 > > > > > Sent: Monday, April 20, 2015 2:07 PM > > > > > To: Wood Scott-B07421 > > > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > > > Subject: RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > > > clock mux > > > > > > > > > > > > > > > > > > > > Regards, > > > > > Igal Liberman. > > > > > > > > > > > -----Original Message----- > > > > > > From: Wood Scott-B07421 > > > > > > Sent: Friday, April 17, 2015 8:41 AM > > > > > > To: Liberman Igal-B31950 > > > > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for > > > > > > FMan clock mux > > > > > > > > > > > > On Thu, 2015-04-16 at 01:11 -0500, Liberman Igal-B31950 wrote: > > > > > > > > > > > > > > > > > > > > > Regards, > > > > > > > Igal Liberman. > > > > > > > > > > > > > > > -----Original Message----- > > > > > > > > From: Wood Scott-B07421 > > > > > > > > Sent: Wednesday, April 15, 2015 8:36 PM > > > > > > > > To: Liberman Igal-B31950 > > > > > > > > Cc: devicetree@vger.kernel.org; > > > > > > > > linuxppc-dev@lists.ozlabs.org > > > > > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding > > > > > > > > for FMan clock mux > > > > > > > > > > > > > > > > On Tue, 2015-04-14 at 13:56 +0300, Igal.Liberman wrote: > > > > > > > > > From: Igal Liberman <Igal.Liberman@freescale.com> > > > > > > > > > > > > > > > > > > v3: Addressed feedback from Scott: > > > > > > > > > - Removed clock specifier description. > > > > > > > > > > > > > > > > > > v2: Addressed feedback from Scott: > > > > > > > > > - Moved the "fman-clk-mux" clock provider details > > > > > > > > > under "clocks" property. > > > > > > > > > > > > > > > > > > Signed-off-by: Igal Liberman > > > > > > > > > <Igal.Liberman@freescale.com> > > > > > > > > > --- > > > > > > > > > .../devicetree/bindings/clock/qoriq-clock.txt | 17 > > > > > > +++++++++++++++-- > > > > > > > > > 1 file changed, 15 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > > > > > diff --git > > > > > > > > > a/Documentation/devicetree/bindings/clock/qoriq-clock.tx > > > > > > > > > t > > > > > > > > > b/Documentation/devicetree/bindings/clock/qoriq-clock.tx > > > > > > > > > t index b0d7b73..2bb3b38 100644 > > > > > > > > > --- > > > > > > > > > a/Documentation/devicetree/bindings/clock/qoriq-clock.tx > > > > > > > > > t > > > > > > > > > +++ b/Documentation/devicetree/bindings/clock/qoriq-cloc > > > > > > > > > +++ k.tx > > > > > > > > > +++ t > > > > > > > > > @@ -65,9 +65,10 @@ Required properties: > > > > > > > > > It takes parent's clock-frequency as its clock. > > > > > > > > > * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) > > > > > > > > > * "fsl,qoriq-platform-pll-2.0" for the platform PLL > > > > > > > > > clock > > > > > > > > > (v2.0) > > > > > > > > > + * "fsl,fman-clk-mux" for the Frame Manager clock. > > > > > > > > > - #clock-cells: From common clock binding. The number > > > > > > > > > of cells in > > > a > > > > > > > > > - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" > > > > > > > > > - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. > > > > > > > > > + clock-specifier. Should be <0> for "fsl,qoriq-sysclk- > [1,2].0" > > > > > and > > > > > > > > > + "fsl,fman-clk-mux" clocks or <1> for > > > > > > > > > +"fsl,qoriq-core-pll- > > > > > [1,2].0". > > > > > > > > > For "fsl,qoriq-core-pll-1.0" clocks, the single > > > > > > > > > clock-specifier cell may take the following values: > > > > > > > > > * 0 - equal to the PLL frequency @@ -145,6 +146,18 @@ > > > > > Example > > > > > > > > > for clock block and clock provider: > > > > > > > > > clocks = <&sysclk>; > > > > > > > > > clock-output-names = "platform-pll", > > > > > "platform-pll- > > > > > > > > div2"; > > > > > > > > > }; > > > > > > > > > + > > > > > > > > > + fm0clk: fm0-clk-mux { > > > > > > > > > + #clock-cells = <0>; > > > > > > > > > + reg = <0x10 4> > > > > > > > > > + compatible = "fsl,fman-clk-mux"; > > > > > > > > > + clocks = <&pll0 0>, <&pll0 1>, <&pll0 > 2>, > > > > > <&pll0 3>, > > > > > > > > > + <&platform_pll 0>, <&pll1 1>, > <&pll1 > > > > > 2>; > > > > > > > > > + clock-names = "pll0", "pll0-div2", > "pll0-div3", > > > > > > > > > + "pll0-div4", "platform-pll", > "pll1- > > > > > div2", > > > > > > > > > + "pll1-div3"; > > > > > > > > > + clock-output-names = "fm0-clk"; > > > > > > > > > + }; > > > > > > > > > }; > > > > > > > > > }; > > > > > > > > > > > > > > > > > > > > > > > > > I don't see this register in the manuals for older DPAA > > > > > > > > chips, such as > > > > > > > > p4080 or p3041. Is it present but undocumented? Should I > > > > > > > > be looking somewhere other than "Clocking Memory Map"? > > > > > > > > > > > > > > > > > > > > > > It's available only in part of the new chips (T4, T2, B4). > > > > > > > In T1024/T1040 there's only one option for FMan clock so > > > > > > > this register is not > > > > > > available. > > > > > > > > > > > > So it's part of the 2.0 chassis? I'd stick a 2.0 in there, then. > > > > > > Who knows what we may see in the future. > > > > > > > > > > > > > > > > OK, > > > > > We can go with "fsl,fman-clk-mux-1/2-0.". > > > > > In that case, we need to update FMan nodes and the clock driver: > > > > > https://patchwork.ozlabs.org/patch/443973/ > > > > > https://patchwork.ozlabs.org/patch/461813/ > > > > > I will update those patches separately. > > > > > > > > > > > > > Scott, > > > > There are 2 options: > > > > Use "fsl,fman-clk-mux-1.0" for SoC without CLKCGnHWACSR register. > > > > Use "fsl,fman-clk-mux-2.0" for SoC with CLKCGnHWACSR register. > > > > Or > > > > Use "fsl,fman-clk-mux-1.0" for SoC which support FMan V2 (Pxxxx) > > > > Use "fsl,fman-clk-mux-2.0" for SoC which support FMan V3 (B/T) > > > > > > 1.0/2.0 in the clockgen node refers to chassis version. It has > > > nothing to do with FMan version. > > > > > > > I know. However there's a match: 1.0 chassis used in SoC with FMan v2 and > 2.0 chassis in SoC with FMan v3. > > > > > In fact, fman should not be in the compatible because, now that I > > > found the documentation for this, I see that it's more generic than that. > > > "fman-clk-mux" should be replaced with "qoriq-hwacsr". > > > > > > > Using the 1st option might be confusing because core pll/mux 2.0 > > > represents B/T devices and 1.0 represent Pxxxx. > > > > In this case, T1040 uses "fsl,qoriq-core-pll/mux-2.0" and > > > > "fsl,fman-clk-mux- > > > 1.0". > > > > On the other hand, the second option doesn't distinguishes between > > > > T4 > > > and T1 (for example), as T1 doesn't have reg property while T4 has. > > > > > > How would t1040 have a so-called "fman-clk-mux" node at all if it > > > doesn't have this register? > > > > > > I think we've made a mess of the clock bindings and this is only > > > going to make it worse. We need to stay compatible with the mess > > > we've made, but I'm inclined to say that we shouldn't add more nodes to > it. > > > > > > Instead, have the toplevel clockgen node have a chip-based > > > compatible in addition to version (e.g. compatible = > > > "fsl,t4240-clockgen", > > > "fsl,qoriq-clockgen-2.0") and have the toplevel node export whatever > > > clocks are needed. Put the logic to deal with all the different > > > dividers, register values, and such in code, not the device tree. > > > The binding should be focused on how to encode the specifier of the > exported clocks. > > > > > > > We have 2 cases: > > - Devices (T2/T4/B4) with CLKCG1HWACSR register. > > - Devices (Pxxxx, T1) without CLKCG1HWACSR register (Pxxxx > devices > > have many options, T1 has only one option) > > > > For the first group, we can have " qoriq-hwacsr" property in the clock node. > > No, we're not going to describe every register with its own property. > Describe the chip and let the driver be the place with the knowledge of what > each chip is like. > I think that FMan clock mux (as we defined it) is similar to other muxes available in our SoC. If we take T4 as example, it has 3 muxes defined in the device tree (mux0, mux1 and mux2). Each mux has its own reg property (and clock providers). mux2: mux2@40 { #clock-cells = <0>; reg = <0x40 0x4>; compatible = "fsl,qoriq-core-mux-2.0"; clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>, <&pll4 0>, <&pll4 1>, <&pll4 2>; clock-names = "pll3", "pll3-div2", "pll3-div4", "pll4", "pll4-div2", "pll4-div4"; clock-output-names = "cmux2"; }; I agree that "fm1-clk-mux" need to be moved from the "guts" node to "clockgen" node. However, I'm not sure which changes you want to perform in the node (beside adding reg property for SoC which has it for FMan clock). > > Currently T4 FMan clock mux node is the following: > > fm1clk: fm1-clk-mux { > > #clock-cells = <0>; > > compatible = "fsl,fman-clk-mux"; > > clocks = <&pll1 1>, <&pll1 2>, <&pll1 3>, > > <&platform_pll 0>, <&pll0 1>, <&pll0 2>; > > clock-names = "pll1-div2", "pll1-div3", "pll1-div4", > > "platform-pll", "pll0-div2", "pll0-div3"; > > clock-output-names = "fm1-clk"; > > }; > > As far as I understand we need to move the node to the top level clock > node. > > In addition we need to add reg property and change the name of the node > and the compatible. > > In that case, the driver can read this register instead of parsing the RCW. > > I'm having a hard time following. What I'm suggesting is eliminating the > above and having the clockgen node itself (which already has a reg > property) be a clock source with a clock specifier encoding that distinguishes > the fman clock from other clocks. > > > What about the devices of the second group? > > In this case we don't have a register to determine the source clock. > > So we need access to guts registers, > > I never suggested taking away access to the guts registers. > I didn't mention that you want to remove them. Just tried to explain that for Pxxxx devices, we need to use the current method (explained later). > > like we have currently. > > The suggestion above doesn’t suit for those devices. > > How is the clock determined on those chips? > In those chips (and currently others), currently, in the device tree we have all optional FMan clock providers (different between each SoC). The clock driver reads the RCW in order to determine the clock provider and saves the index, later get_fm_clk_parent returns the index. > -Scott > Igal ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-04-30 14:28 ` Igal.Liberman 0 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman @ 2015-04-30 14:28 UTC (permalink / raw) To: Scott Wood; +Cc: devicetree, linuxppc-dev, Yuantian Tang DQoNClJlZ2FyZHMsDQpJZ2FsIExpYmVybWFuLg0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0t LS0tDQo+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIxDQo+IFNlbnQ6IFRodXJzZGF5LCBBcHJpbCAz MCwgMjAxNSAzOjMxIEFNDQo+IFRvOiBMaWJlcm1hbiBJZ2FsLUIzMTk1MA0KPiBDYzogZGV2aWNl dHJlZUB2Z2VyLmtlcm5lbC5vcmc7IGxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMub3JnOyBUYW5n DQo+IFl1YW50aWFuLUIyOTk4Mw0KPiBTdWJqZWN0OiBSZTogW3YzXSBkdC9iaW5kaW5nczogcW9y aXEtY2xvY2s6IEFkZCBiaW5kaW5nIGZvciBGTWFuIGNsb2NrIG11eA0KPiANCj4gT24gV2VkLCAy MDE1LTA0LTIyIGF0IDA1OjQ3IC0wNTAwLCBMaWJlcm1hbiBJZ2FsLUIzMTk1MCB3cm90ZToNCj4g Pg0KPiA+DQo+ID4gUmVnYXJkcywNCj4gPiBJZ2FsIExpYmVybWFuLg0KPiA+DQo+ID4gPiAtLS0t LU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+ID4gRnJvbTogV29vZCBTY290dC1CMDc0MjENCj4g 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* Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux 2015-04-30 14:28 ` Igal.Liberman @ 2015-05-01 23:42 ` Scott Wood -1 siblings, 0 replies; 26+ messages in thread From: Scott Wood @ 2015-05-01 23:42 UTC (permalink / raw) To: Liberman Igal-B31950 Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Tang Yuantian-B29983 On Thu, 2015-04-30 at 09:28 -0500, Liberman Igal-B31950 wrote: > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Thursday, April 30, 2015 3:31 AM > > To: Liberman Igal-B31950 > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org; Tang > > Yuantian-B29983 > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > On Wed, 2015-04-22 at 05:47 -0500, Liberman Igal-B31950 wrote: > > > We have 2 cases: > > > - Devices (T2/T4/B4) with CLKCG1HWACSR register. > > > - Devices (Pxxxx, T1) without CLKCG1HWACSR register (Pxxxx > > devices > > > have many options, T1 has only one option) > > > > > > For the first group, we can have " qoriq-hwacsr" property in the clock node. > > > > No, we're not going to describe every register with its own property. > > Describe the chip and let the driver be the place with the knowledge of what > > each chip is like. > > > > I think that FMan clock mux (as we defined it) is similar to other muxes available in our SoC. I realize that. I'm saying the way we described existing muxes seems to be a mistake. We're putting too much complexity in the device tree. Better to put the complexity in a place that isn't stable ABI. > If we take T4 as example, it has 3 muxes defined in the device tree (mux0, mux1 and mux2). > Each mux has its own reg property (and clock providers). > mux2: mux2@40 { > #clock-cells = <0>; > reg = <0x40 0x4>; > compatible = "fsl,qoriq-core-mux-2.0"; > clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>, > <&pll4 0>, <&pll4 1>, <&pll4 2>; > clock-names = "pll3", "pll3-div2", "pll3-div4", > "pll4", "pll4-div2", "pll4-div4"; > clock-output-names = "cmux2"; > }; > > I agree that "fm1-clk-mux" need to be moved from the "guts" node to "clockgen" node. That's not what I was saying. I'm saying get rid of the node entirely, in favor of having the clockgen node itself be a clock source with multiple post-mux outputs. > However, I'm not sure which changes you want to perform in the node (beside adding reg property for SoC which has it for FMan clock). Again, the clockgen node already has a reg property. -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-05-01 23:42 ` Scott Wood 0 siblings, 0 replies; 26+ messages in thread From: Scott Wood @ 2015-05-01 23:42 UTC (permalink / raw) To: Liberman Igal-B31950; +Cc: devicetree, linuxppc-dev, Tang Yuantian-B29983 On Thu, 2015-04-30 at 09:28 -0500, Liberman Igal-B31950 wrote: > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Thursday, April 30, 2015 3:31 AM > > To: Liberman Igal-B31950 > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Tang > > Yuantian-B29983 > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > On Wed, 2015-04-22 at 05:47 -0500, Liberman Igal-B31950 wrote: > > > We have 2 cases: > > > - Devices (T2/T4/B4) with CLKCG1HWACSR register. > > > - Devices (Pxxxx, T1) without CLKCG1HWACSR register (Pxxxx > > devices > > > have many options, T1 has only one option) > > > > > > For the first group, we can have " qoriq-hwacsr" property in the clock node. > > > > No, we're not going to describe every register with its own property. > > Describe the chip and let the driver be the place with the knowledge of what > > each chip is like. > > > > I think that FMan clock mux (as we defined it) is similar to other muxes available in our SoC. I realize that. I'm saying the way we described existing muxes seems to be a mistake. We're putting too much complexity in the device tree. Better to put the complexity in a place that isn't stable ABI. > If we take T4 as example, it has 3 muxes defined in the device tree (mux0, mux1 and mux2). > Each mux has its own reg property (and clock providers). > mux2: mux2@40 { > #clock-cells = <0>; > reg = <0x40 0x4>; > compatible = "fsl,qoriq-core-mux-2.0"; > clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>, > <&pll4 0>, <&pll4 1>, <&pll4 2>; > clock-names = "pll3", "pll3-div2", "pll3-div4", > "pll4", "pll4-div2", "pll4-div4"; > clock-output-names = "cmux2"; > }; > > I agree that "fm1-clk-mux" need to be moved from the "guts" node to "clockgen" node. That's not what I was saying. I'm saying get rid of the node entirely, in favor of having the clockgen node itself be a clock source with multiple post-mux outputs. > However, I'm not sure which changes you want to perform in the node (beside adding reg property for SoC which has it for FMan clock). Again, the clockgen node already has a reg property. -Scott ^ permalink raw reply [flat|nested] 26+ messages in thread
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* RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux 2015-05-01 23:42 ` Scott Wood @ 2015-05-05 21:02 ` Igal.Liberman -1 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman-KZfg59tc24xl57MIdRCFDg @ 2015-05-05 21:02 UTC (permalink / raw) To: Scott Wood Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Yuantian Tang Regards, Igal Liberman. > -----Original Message----- > From: Wood Scott-B07421 > Sent: Saturday, May 02, 2015 2:43 AM > To: Liberman Igal-B31950 > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Tang > Yuantian-B29983 > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > On Thu, 2015-04-30 at 09:28 -0500, Liberman Igal-B31950 wrote: > > > -----Original Message----- > > > From: Wood Scott-B07421 > > > Sent: Thursday, April 30, 2015 3:31 AM > > > To: Liberman Igal-B31950 > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Tang > > > Yuantian-B29983 > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > clock mux > > > > > > On Wed, 2015-04-22 at 05:47 -0500, Liberman Igal-B31950 wrote: > > > > We have 2 cases: > > > > - Devices (T2/T4/B4) with CLKCG1HWACSR register. > > > > - Devices (Pxxxx, T1) without CLKCG1HWACSR register (Pxxxx > > > devices > > > > have many options, T1 has only one option) > > > > > > > > For the first group, we can have " qoriq-hwacsr" property in the clock > node. > > > > > > No, we're not going to describe every register with its own property. > > > Describe the chip and let the driver be the place with the knowledge > > > of what each chip is like. > > > > > > > I think that FMan clock mux (as we defined it) is similar to other muxes > available in our SoC. > > I realize that. I'm saying the way we described existing muxes seems to be a > mistake. We're putting too much complexity in the device tree. > Better to put the complexity in a place that isn't stable ABI. > > > If we take T4 as example, it has 3 muxes defined in the device tree (mux0, > mux1 and mux2). > > Each mux has its own reg property (and clock providers). > > mux2: mux2@40 { > > #clock-cells = <0>; > > reg = <0x40 0x4>; > > compatible = "fsl,qoriq-core-mux-2.0"; > > clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>, > > <&pll4 0>, <&pll4 1>, <&pll4 2>; > > clock-names = "pll3", "pll3-div2", "pll3-div4", > > "pll4", "pll4-div2", "pll4-div4"; > > clock-output-names = "cmux2"; > > }; > > > > I agree that "fm1-clk-mux" need to be moved from the "guts" node to > "clockgen" node. > > That's not what I was saying. I'm saying get rid of the node entirely, in favor > of having the clockgen node itself be a clock source with multiple post-mux > outputs. > Scott, Currently the clockgen node has a number of sub nodes (platform clock, sysclock, PLLs and muxes, the number of muxes/PLLs is SoC dependent). The clockgen node has reg property, however, all other nodes have reg property too (The clockgen points to the clocking block address and the sub nodes point to the specific register in the clock block). Do you want to change this structure completely? I'm not sure I understand the exact way you want see those nodes (in the final state). > > However, I'm not sure which changes you want to perform in the node > (beside adding reg property for SoC which has it for FMan clock). > > Again, the clockgen node already has a reg property. > > -Scott > ^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-05-05 21:02 ` Igal.Liberman 0 siblings, 0 replies; 26+ messages in thread From: Igal.Liberman @ 2015-05-05 21:02 UTC (permalink / raw) To: Scott Wood; +Cc: devicetree, linuxppc-dev, Yuantian Tang DQoNClJlZ2FyZHMsDQpJZ2FsIExpYmVybWFuLg0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0t LS0tDQo+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIxDQo+IFNlbnQ6IFNhdHVyZGF5LCBNYXkgMDIs IDIwMTUgMjo0MyBBTQ0KPiBUbzogTGliZXJtYW4gSWdhbC1CMzE5NTANCj4gQ2M6IGRldmljZXRy ZWVAdmdlci5rZXJuZWwub3JnOyBsaW51eHBwYy1kZXZAbGlzdHMub3psYWJzLm9yZzsgVGFuZw0K PiBZdWFudGlhbi1CMjk5ODMNCj4gU3ViamVjdDogUmU6IFt2M10gZHQvYmluZGluZ3M6IHFvcmlx LWNsb2NrOiBBZGQgYmluZGluZyBmb3IgRk1hbiBjbG9jayBtdXgNCj4gDQo+IE9uIFRodSwgMjAx NS0wNC0zMCBhdCAwOToyOCAtMDUwMCwgTGliZXJtYW4gSWdhbC1CMzE5NTAgd3JvdGU6DQo+ID4g PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+ID4gRnJvbTogV29vZCBTY290dC1CMDc0 MjENCj4gPiA+IFNlbnQ6IFRodXJzZGF5LCBBcHJpbCAzMCwgMjAxNSAzOjMxIEFNDQo+ID4gPiBU bzogTGliZXJtYW4gSWdhbC1CMzE5NTANCj4gPiA+IENjOiBkZXZpY2V0cmVlQHZnZXIua2VybmVs Lm9yZzsgbGludXhwcGMtZGV2QGxpc3RzLm96bGFicy5vcmc7IFRhbmcNCj4gPiA+IFl1YW50aWFu LUIyOTk4Mw0KPiA+ID4gU3ViamVjdDogUmU6IFt2M10gZHQvYmluZGluZ3M6IHFvcmlxLWNsb2Nr OiBBZGQgYmluZGluZyBmb3IgRk1hbg0KPiA+ID4gY2xvY2sgbXV4DQo+ID4gPg0KPiA+ID4gT24g V2VkLCAyMDE1LTA0LTIyIGF0IDA1OjQ3IC0wNTAwLCBMaWJlcm1hbiBJZ2FsLUIzMTk1MCB3cm90 ZToNCj4gPiA+ID4gV2UgaGF2ZSAyIGNhc2VzOg0KPiA+ID4gPiAJLSBEZXZpY2VzIChUMi9UNC9C NCkgd2l0aCBDTEtDRzFIV0FDU1IgcmVnaXN0ZXIuDQo+ID4gPiA+IAktIERldmljZXMgKFB4eHh4 LCBUMSkgd2l0aG91dCBDTEtDRzFIV0FDU1IgcmVnaXN0ZXIgKFB4eHh4DQo+ID4gPiBkZXZpY2Vz DQo+ID4gPiA+IGhhdmUgbWFueSBvcHRpb25zLCBUMSBoYXMgb25seSBvbmUgb3B0aW9uKQ0KPiA+ ID4gPg0KPiA+ID4gPiBGb3IgdGhlIGZpcnN0IGdyb3VwLCB3ZSBjYW4gaGF2ZSAiIHFvcmlxLWh3 YWNzciIgcHJvcGVydHkgaW4gdGhlIGNsb2NrDQo+IG5vZGUuDQo+ID4gPg0KPiA+ID4gTm8sIHdl J3JlIG5vdCBnb2luZyB0byBkZXNjcmliZSBldmVyeSByZWdpc3RlciB3aXRoIGl0cyBvd24gcHJv cGVydHkuDQo+ID4gPiBEZXNjcmliZSB0aGUgY2hpcCBhbmQgbGV0IHRoZSBkcml2ZXIgYmUgdGhl IHBsYWNlIHdpdGggdGhlIGtub3dsZWRnZQ0KPiA+ID4gb2Ygd2hhdCBlYWNoIGNoaXAgaXMgbGlr ZS4NCj4gPiA+DQo+ID4NCj4gPiBJIHRoaW5rIHRoYXQgRk1hbiBjbG9jayBtdXggKGFzIHdlIGRl ZmluZWQgaXQpIGlzIHNpbWlsYXIgdG8gb3RoZXIgbXV4ZXMNCj4gYXZhaWxhYmxlIGluIG91ciBT b0MuDQo+IA0KPiBJIHJlYWxpemUgdGhhdC4gIEknbSBzYXlpbmcgdGhlIHdheSB3ZSBkZXNjcmli ZWQgZXhpc3RpbmcgbXV4ZXMgc2VlbXMgdG8gYmUgYQ0KPiBtaXN0YWtlLiAgV2UncmUgcHV0dGlu ZyB0b28gbXVjaCBjb21wbGV4aXR5IGluIHRoZSBkZXZpY2UgdHJlZS4NCj4gQmV0dGVyIHRvIHB1 dCB0aGUgY29tcGxleGl0eSBpbiBhIHBsYWNlIHRoYXQgaXNuJ3Qgc3RhYmxlIEFCSS4NCj4gDQo+ ID4gSWYgd2UgdGFrZSBUNCBhcyBleGFtcGxlLCBpdCBoYXMgMyBtdXhlcyBkZWZpbmVkIGluIHRo ZSBkZXZpY2UgdHJlZSAobXV4MCwNCj4gbXV4MSBhbmQgbXV4MikuDQo+ID4gRWFjaCBtdXggaGFz IGl0cyBvd24gcmVnIHByb3BlcnR5IChhbmQgY2xvY2sgcHJvdmlkZXJzKS4NCj4gPiAJbXV4Mjog bXV4MkA0MCB7DQo+ID4gCQkjY2xvY2stY2VsbHMgPSA8MD47DQo+ID4gCQlyZWcgPSA8MHg0MCAw eDQ+Ow0KPiA+IAkJY29tcGF0aWJsZSA9ICJmc2wscW9yaXEtY29yZS1tdXgtMi4wIjsNCj4gPiAJ CWNsb2NrcyA9IDwmcGxsMyAwPiwgPCZwbGwzIDE+LCA8JnBsbDMgMj4sDQo+ID4gCQkJPCZwbGw0 IDA+LCA8JnBsbDQgMT4sIDwmcGxsNCAyPjsNCj4gPiAJCWNsb2NrLW5hbWVzID0gInBsbDMiLCAi cGxsMy1kaXYyIiwgInBsbDMtZGl2NCIsDQo+ID4gCQkJInBsbDQiLCAicGxsNC1kaXYyIiwgInBs bDQtZGl2NCI7DQo+ID4gCQljbG9jay1vdXRwdXQtbmFtZXMgPSAiY211eDIiOw0KPiA+IAl9Ow0K PiA+DQo+ID4gSSBhZ3JlZSB0aGF0ICJmbTEtY2xrLW11eCIgbmVlZCB0byBiZSBtb3ZlZCBmcm9t IHRoZSAiZ3V0cyIgbm9kZSB0bw0KPiAiY2xvY2tnZW4iIG5vZGUuDQo+IA0KPiBUaGF0J3Mgbm90 IHdoYXQgSSB3YXMgc2F5aW5nLiAgSSdtIHNheWluZyBnZXQgcmlkIG9mIHRoZSBub2RlIGVudGly ZWx5LCBpbiBmYXZvcg0KPiBvZiBoYXZpbmcgdGhlIGNsb2NrZ2VuIG5vZGUgaXRzZWxmIGJlIGEg Y2xvY2sgc291cmNlIHdpdGggbXVsdGlwbGUgcG9zdC1tdXgNCj4gb3V0cHV0cy4NCj4gDQoNClNj b3R0LA0KQ3VycmVudGx5IHRoZSBjbG9ja2dlbiBub2RlIGhhcyBhIG51bWJlciBvZiBzdWIgbm9k ZXMgKHBsYXRmb3JtIGNsb2NrLCBzeXNjbG9jaywgUExMcyBhbmQgbXV4ZXMsIHRoZSBudW1iZXIg b2YgbXV4ZXMvUExMcyBpcyBTb0MgZGVwZW5kZW50KS4NClRoZSBjbG9ja2dlbiBub2RlIGhhcyBy ZWcgcHJvcGVydHksIGhvd2V2ZXIsIGFsbCBvdGhlciBub2RlcyBoYXZlIHJlZyBwcm9wZXJ0eSB0 b28gKFRoZSBjbG9ja2dlbiBwb2ludHMgdG8gdGhlIGNsb2NraW5nIGJsb2NrIGFkZHJlc3MgYW5k IHRoZSBzdWIgbm9kZXMgcG9pbnQgdG8gdGhlIHNwZWNpZmljIHJlZ2lzdGVyIGluIHRoZSBjbG9j ayBibG9jaykuDQpEbyB5b3Ugd2FudCB0byBjaGFuZ2UgdGhpcyBzdHJ1Y3R1cmUgY29tcGxldGVs eT8NCkknbSBub3Qgc3VyZSBJIHVuZGVyc3RhbmQgdGhlIGV4YWN0IHdheSB5b3Ugd2FudCBzZWUg dGhvc2Ugbm9kZXMgKGluIHRoZSBmaW5hbCBzdGF0ZSkuDQoNCj4gPiBIb3dldmVyLCBJJ20gbm90 IHN1cmUgd2hpY2ggY2hhbmdlcyB5b3Ugd2FudCB0byBwZXJmb3JtIGluIHRoZSBub2RlDQo+IChi ZXNpZGUgYWRkaW5nIHJlZyBwcm9wZXJ0eSBmb3IgU29DIHdoaWNoIGhhcyBpdCBmb3IgRk1hbiBj bG9jaykuDQo+IA0KPiBBZ2FpbiwgdGhlIGNsb2NrZ2VuIG5vZGUgYWxyZWFkeSBoYXMgYSByZWcg cHJvcGVydHkuDQo+IA0KPiAtU2NvdHQNCj4gDQoNCg== ^ permalink raw reply [flat|nested] 26+ messages in thread
[parent not found: <BY2PR03MB3794413FB3FF795DF520D23E6D10-+7O3WWA3DPtn35zppGJRk+O6mTEJWrR4XA4E9RH9d+qIuWR1G4zioA@public.gmane.org>]
* Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux 2015-05-05 21:02 ` Igal.Liberman @ 2015-05-05 21:16 ` Scott Wood -1 siblings, 0 replies; 26+ messages in thread From: Scott Wood @ 2015-05-05 21:16 UTC (permalink / raw) To: Liberman Igal-B31950 Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, Tang Yuantian-B29983 On Tue, 2015-05-05 at 16:02 -0500, Liberman Igal-B31950 wrote: > > > Regards, > Igal Liberman. > > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Saturday, May 02, 2015 2:43 AM > > To: Liberman Igal-B31950 > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org; Tang > > Yuantian-B29983 > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > On Thu, 2015-04-30 at 09:28 -0500, Liberman Igal-B31950 wrote: > > > > -----Original Message----- > > > > From: Wood Scott-B07421 > > > > Sent: Thursday, April 30, 2015 3:31 AM > > > > To: Liberman Igal-B31950 > > > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org; Tang > > > > Yuantian-B29983 > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > > clock mux > > > > > > > > On Wed, 2015-04-22 at 05:47 -0500, Liberman Igal-B31950 wrote: > > > > > We have 2 cases: > > > > > - Devices (T2/T4/B4) with CLKCG1HWACSR register. > > > > > - Devices (Pxxxx, T1) without CLKCG1HWACSR register (Pxxxx > > > > devices > > > > > have many options, T1 has only one option) > > > > > > > > > > For the first group, we can have " qoriq-hwacsr" property in the clock > > node. > > > > > > > > No, we're not going to describe every register with its own property. > > > > Describe the chip and let the driver be the place with the knowledge > > > > of what each chip is like. > > > > > > > > > > I think that FMan clock mux (as we defined it) is similar to other muxes > > available in our SoC. > > > > I realize that. I'm saying the way we described existing muxes seems to be a > > mistake. We're putting too much complexity in the device tree. > > Better to put the complexity in a place that isn't stable ABI. > > > > > If we take T4 as example, it has 3 muxes defined in the device tree (mux0, > > mux1 and mux2). > > > Each mux has its own reg property (and clock providers). > > > mux2: mux2@40 { > > > #clock-cells = <0>; > > > reg = <0x40 0x4>; > > > compatible = "fsl,qoriq-core-mux-2.0"; > > > clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>, > > > <&pll4 0>, <&pll4 1>, <&pll4 2>; > > > clock-names = "pll3", "pll3-div2", "pll3-div4", > > > "pll4", "pll4-div2", "pll4-div4"; > > > clock-output-names = "cmux2"; > > > }; > > > > > > I agree that "fm1-clk-mux" need to be moved from the "guts" node to > > "clockgen" node. > > > > That's not what I was saying. I'm saying get rid of the node entirely, in favor > > of having the clockgen node itself be a clock source with multiple post-mux > > outputs. > > > > Scott, > Currently the clockgen node has a number of sub nodes (platform clock, sysclock, PLLs and muxes, the number of muxes/PLLs is SoC dependent). > The clockgen node has reg property, however, all other nodes have reg property too (The clockgen points to the clocking block address and the sub nodes point to the specific register in the clock block). > Do you want to change this structure completely? Yes, I want to change it completely (while ensuring the kernel still works, albeit without new functionality, with older device trees). > I'm not sure I understand the exact way you want see those nodes (in the final state). Something like: clockgen: global-utilities@e1000 { compatible = "fsl,<whatever>-clockgen"; clock-frequency = <...>; reg = <0xe1000 0x1000>; #clock-cells = <2>; }; cpu0: PowerPC,e6500@0 { device_type = "cpu"; reg = <0 1>; clocks = <&clockgen 0 0>; next-level-cache = <&L2_1>; fsl,portid-mapping = <0x80000000>; }; cpu4: PowerPC,e6500@0 { device_type = "cpu"; reg = <4 5>; clocks = <&clockgen 0 1>; next-level-cache = <&L2_1>; fsl,portid-mapping = <0x80000000>; }; fman@... { ... clocks = <&clockgen 1 0>; ... }; ...with the clockgen binding explaining the format of the clock specifier, and the clockgen driver containing the chip-specific muxing details. -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux @ 2015-05-05 21:16 ` Scott Wood 0 siblings, 0 replies; 26+ messages in thread From: Scott Wood @ 2015-05-05 21:16 UTC (permalink / raw) To: Liberman Igal-B31950; +Cc: devicetree, linuxppc-dev, Tang Yuantian-B29983 On Tue, 2015-05-05 at 16:02 -0500, Liberman Igal-B31950 wrote: > > > Regards, > Igal Liberman. > > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Saturday, May 02, 2015 2:43 AM > > To: Liberman Igal-B31950 > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Tang > > Yuantian-B29983 > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > On Thu, 2015-04-30 at 09:28 -0500, Liberman Igal-B31950 wrote: > > > > -----Original Message----- > > > > From: Wood Scott-B07421 > > > > Sent: Thursday, April 30, 2015 3:31 AM > > > > To: Liberman Igal-B31950 > > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Tang > > > > Yuantian-B29983 > > > > Subject: Re: [v3] dt/bindings: qoriq-clock: Add binding for FMan > > > > clock mux > > > > > > > > On Wed, 2015-04-22 at 05:47 -0500, Liberman Igal-B31950 wrote: > > > > > We have 2 cases: > > > > > - Devices (T2/T4/B4) with CLKCG1HWACSR register. > > > > > - Devices (Pxxxx, T1) without CLKCG1HWACSR register (Pxxxx > > > > devices > > > > > have many options, T1 has only one option) > > > > > > > > > > For the first group, we can have " qoriq-hwacsr" property in the clock > > node. > > > > > > > > No, we're not going to describe every register with its own property. > > > > Describe the chip and let the driver be the place with the knowledge > > > > of what each chip is like. > > > > > > > > > > I think that FMan clock mux (as we defined it) is similar to other muxes > > available in our SoC. > > > > I realize that. I'm saying the way we described existing muxes seems to be a > > mistake. We're putting too much complexity in the device tree. > > Better to put the complexity in a place that isn't stable ABI. > > > > > If we take T4 as example, it has 3 muxes defined in the device tree (mux0, > > mux1 and mux2). > > > Each mux has its own reg property (and clock providers). > > > mux2: mux2@40 { > > > #clock-cells = <0>; > > > reg = <0x40 0x4>; > > > compatible = "fsl,qoriq-core-mux-2.0"; > > > clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>, > > > <&pll4 0>, <&pll4 1>, <&pll4 2>; > > > clock-names = "pll3", "pll3-div2", "pll3-div4", > > > "pll4", "pll4-div2", "pll4-div4"; > > > clock-output-names = "cmux2"; > > > }; > > > > > > I agree that "fm1-clk-mux" need to be moved from the "guts" node to > > "clockgen" node. > > > > That's not what I was saying. I'm saying get rid of the node entirely, in favor > > of having the clockgen node itself be a clock source with multiple post-mux > > outputs. > > > > Scott, > Currently the clockgen node has a number of sub nodes (platform clock, sysclock, PLLs and muxes, the number of muxes/PLLs is SoC dependent). > The clockgen node has reg property, however, all other nodes have reg property too (The clockgen points to the clocking block address and the sub nodes point to the specific register in the clock block). > Do you want to change this structure completely? Yes, I want to change it completely (while ensuring the kernel still works, albeit without new functionality, with older device trees). > I'm not sure I understand the exact way you want see those nodes (in the final state). Something like: clockgen: global-utilities@e1000 { compatible = "fsl,<whatever>-clockgen"; clock-frequency = <...>; reg = <0xe1000 0x1000>; #clock-cells = <2>; }; cpu0: PowerPC,e6500@0 { device_type = "cpu"; reg = <0 1>; clocks = <&clockgen 0 0>; next-level-cache = <&L2_1>; fsl,portid-mapping = <0x80000000>; }; cpu4: PowerPC,e6500@0 { device_type = "cpu"; reg = <4 5>; clocks = <&clockgen 0 1>; next-level-cache = <&L2_1>; fsl,portid-mapping = <0x80000000>; }; fman@... { ... clocks = <&clockgen 1 0>; ... }; ...with the clockgen binding explaining the format of the clock specifier, and the clockgen driver containing the chip-specific muxing details. -Scott ^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2015-05-05 21:16 UTC | newest] Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-04-14 10:56 [v3] dt/bindings: qoriq-clock: Add binding for FMan clock mux Igal.Liberman 2015-04-14 10:56 ` Igal.Liberman 2015-04-15 17:35 ` Scott Wood 2015-04-15 17:35 ` Scott Wood [not found] ` <1429119357.22867.724.camel-KZfg59tc24xl57MIdRCFDg@public.gmane.org> 2015-04-16 6:11 ` Igal.Liberman-KZfg59tc24xl57MIdRCFDg 2015-04-16 6:11 ` Igal.Liberman [not found] ` <DM2PR03MB38330DBBFFD1BC45D58F447E6E40-ufbTtyGzTTRJonC5hhDUuuO6mTEJWrR4XA4E9RH9d+qIuWR1G4zioA@public.gmane.org> 2015-04-17 5:41 ` Scott Wood 2015-04-17 5:41 ` Scott Wood [not found] ` <1429249281.32545.52.camel-KZfg59tc24xl57MIdRCFDg@public.gmane.org> 2015-04-20 11:07 ` Igal.Liberman-KZfg59tc24xl57MIdRCFDg 2015-04-20 11:07 ` Igal.Liberman 2015-04-20 11:40 ` Igal.Liberman-KZfg59tc24xl57MIdRCFDg 2015-04-20 11:40 ` Igal.Liberman [not found] ` <DM2PR03MB383E5F67C358CCE2E38EA71E6E00-ufbTtyGzTTRJonC5hhDUuuO6mTEJWrR4XA4E9RH9d+qIuWR1G4zioA@public.gmane.org> 2015-04-21 0:51 ` Scott Wood 2015-04-21 0:51 ` Scott Wood [not found] ` <1429577504.4352.67.camel-KZfg59tc24xl57MIdRCFDg@public.gmane.org> 2015-04-22 10:47 ` Igal.Liberman-KZfg59tc24xl57MIdRCFDg 2015-04-22 10:47 ` Igal.Liberman [not found] ` <DM2PR03MB383C35FA5959662DD48D00BE6EE0-ufbTtyGzTTRJonC5hhDUuuO6mTEJWrR4XA4E9RH9d+qIuWR1G4zioA@public.gmane.org> 2015-04-30 0:30 ` Scott Wood 2015-04-30 0:30 ` Scott Wood [not found] ` <1430353832.16357.138.camel-KZfg59tc24xl57MIdRCFDg@public.gmane.org> 2015-04-30 14:28 ` Igal.Liberman-KZfg59tc24xl57MIdRCFDg 2015-04-30 14:28 ` Igal.Liberman [not found] ` <DM2PR03MB3839C9D3FDFD7978C1A3497E6D60-ufbTtyGzTTRJonC5hhDUuuO6mTEJWrR4XA4E9RH9d+qIuWR1G4zioA@public.gmane.org> 2015-05-01 23:42 ` Scott Wood 2015-05-01 23:42 ` Scott Wood [not found] ` <1430523775.16357.177.camel-KZfg59tc24xl57MIdRCFDg@public.gmane.org> 2015-05-05 21:02 ` Igal.Liberman-KZfg59tc24xl57MIdRCFDg 2015-05-05 21:02 ` Igal.Liberman [not found] ` <BY2PR03MB3794413FB3FF795DF520D23E6D10-+7O3WWA3DPtn35zppGJRk+O6mTEJWrR4XA4E9RH9d+qIuWR1G4zioA@public.gmane.org> 2015-05-05 21:16 ` Scott Wood 2015-05-05 21:16 ` Scott Wood
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