* [PATCH 0/4] Support mipi dsi video mode on TGL
@ 2019-07-02 4:18 Vandita Kulkarni
2019-07-02 4:18 ` [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Vandita Kulkarni @ 2019-07-02 4:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
This series doesn't include the patch to add dsi init in
setup_outputs. Waiting for the platform enablemnet patches to be
merged.
Vandita Kulkarni (4):
drm/i915/tgl/dsi: Program TRANS_VBLANK register
drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl
drm/i915/tgl/dsi: Do not override TA_SURE
drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping
drivers/gpu/drm/i915/display/icl_dsi.c | 50 +++++++++++++++++---------
1 file changed, 34 insertions(+), 16 deletions(-)
--
2.21.0.5.gaeb582a
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^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register 2019-07-02 4:18 [PATCH 0/4] Support mipi dsi video mode on TGL Vandita Kulkarni @ 2019-07-02 4:18 ` Vandita Kulkarni 2019-07-16 9:58 ` Shankar, Uma 2019-07-02 4:18 ` [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl Vandita Kulkarni ` (4 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Vandita Kulkarni @ 2019-07-02 4:18 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Program vblank register for mipi dsi in video mode on TGL. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index b8673debf932..556eba2636fe 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -866,6 +866,15 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, dsi_trans = dsi_port_to_transcoder(port); I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift); } + + /* program TRANS_VBLANK register, should be same as vtotal progammed */ + if (INTEL_GEN(dev_priv) >= 12) { + for_each_dsi_port(port, intel_dsi->ports) { + dsi_trans = dsi_port_to_transcoder(port); + I915_WRITE(VBLANK(dsi_trans), + (vactive - 1) | ((vtotal - 1) << 16)); + } + } } static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) -- 2.21.0.5.gaeb582a _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register 2019-07-02 4:18 ` [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni @ 2019-07-16 9:58 ` Shankar, Uma 2019-07-30 6:24 ` Kulkarni, Vandita 0 siblings, 1 reply; 12+ messages in thread From: Shankar, Uma @ 2019-07-16 9:58 UTC (permalink / raw) To: Kulkarni, Vandita, intel-gfx; +Cc: Nikula, Jani >-----Original Message----- >From: Kulkarni, Vandita >Sent: Tuesday, July 2, 2019 9:49 AM >To: intel-gfx@lists.freedesktop.org >Cc: ville.syrjala@linux.intel.com; Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma ><uma.shankar@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com> >Subject: [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register > >Program vblank register for mipi dsi in video mode on TGL. > >Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> >--- > drivers/gpu/drm/i915/display/icl_dsi.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > >diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c >b/drivers/gpu/drm/i915/display/icl_dsi.c >index b8673debf932..556eba2636fe 100644 >--- a/drivers/gpu/drm/i915/display/icl_dsi.c >+++ b/drivers/gpu/drm/i915/display/icl_dsi.c >@@ -866,6 +866,15 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder >*encoder, > dsi_trans = dsi_port_to_transcoder(port); > I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift); > } >+ >+ /* program TRANS_VBLANK register, should be same as vtotal progammed */ Typo here in programmed. >+ if (INTEL_GEN(dev_priv) >= 12) { >+ for_each_dsi_port(port, intel_dsi->ports) { >+ dsi_trans = dsi_port_to_transcoder(port); >+ I915_WRITE(VBLANK(dsi_trans), >+ (vactive - 1) | ((vtotal - 1) << 16)); We can put this line along with VTOTAL and get rid of this extra for loop. >+ } >+ } > } > > static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) >-- >2.21.0.5.gaeb582a _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register 2019-07-16 9:58 ` Shankar, Uma @ 2019-07-30 6:24 ` Kulkarni, Vandita 0 siblings, 0 replies; 12+ messages in thread From: Kulkarni, Vandita @ 2019-07-30 6:24 UTC (permalink / raw) To: Shankar, Uma, intel-gfx; +Cc: Nikula, Jani > -----Original Message----- > From: Shankar, Uma > Sent: Tuesday, July 16, 2019 3:29 PM > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel- > gfx@lists.freedesktop.org > Cc: ville.syrjala@linux.intel.com; Nikula, Jani <jani.nikula@intel.com> > Subject: RE: [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register > > > > >-----Original Message----- > >From: Kulkarni, Vandita > >Sent: Tuesday, July 2, 2019 9:49 AM > >To: intel-gfx@lists.freedesktop.org > >Cc: ville.syrjala@linux.intel.com; Nikula, Jani > ><jani.nikula@intel.com>; Shankar, Uma <uma.shankar@intel.com>; > >Kulkarni, Vandita <vandita.kulkarni@intel.com> > >Subject: [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register > > > >Program vblank register for mipi dsi in video mode on TGL. > > > >Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > >--- > > drivers/gpu/drm/i915/display/icl_dsi.c | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > >diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > >b/drivers/gpu/drm/i915/display/icl_dsi.c > >index b8673debf932..556eba2636fe 100644 > >--- a/drivers/gpu/drm/i915/display/icl_dsi.c > >+++ b/drivers/gpu/drm/i915/display/icl_dsi.c > >@@ -866,6 +866,15 @@ gen11_dsi_set_transcoder_timings(struct > >intel_encoder *encoder, > > dsi_trans = dsi_port_to_transcoder(port); > > I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift); > > } > >+ > >+ /* program TRANS_VBLANK register, should be same as vtotal > progammed > >+*/ > > Typo here in programmed. Thanks for the review. Will fix. > > >+ if (INTEL_GEN(dev_priv) >= 12) { > >+ for_each_dsi_port(port, intel_dsi->ports) { > >+ dsi_trans = dsi_port_to_transcoder(port); > >+ I915_WRITE(VBLANK(dsi_trans), > >+ (vactive - 1) | ((vtotal - 1) << 16)); > > We can put this line along with VTOTAL and get rid of this extra for loop. But looks like the rest of the code is written in the similar fashion. It gives better readability as it has platform check too. Also it is called during modeset, it is not very clear to me if it is significant enough. -Thanks Vandita > > >+ } > >+ } > > } > > > > static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) > >-- > >2.21.0.5.gaeb582a _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl 2019-07-02 4:18 [PATCH 0/4] Support mipi dsi video mode on TGL Vandita Kulkarni 2019-07-02 4:18 ` [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni @ 2019-07-02 4:18 ` Vandita Kulkarni 2019-07-16 10:12 ` Shankar, Uma 2019-07-02 4:18 ` [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE Vandita Kulkarni ` (3 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Vandita Kulkarni @ 2019-07-02 4:18 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Rest of the latency programming remains same as that of ICL. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 556eba2636fe..e3980676bcef 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -404,8 +404,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) tmp |= FRC_LATENCY_OPTIM_VAL(0x5); I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp); - /* For EHL set latency optimization for PCS_DW1 lanes */ - if (IS_ELKHARTLAKE(dev_priv)) { + /* EHL and TGL, set latency optimization for PCS_DW1 lanes */ + if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) { tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port)); tmp &= ~LATENCY_OPTIM_MASK; tmp |= LATENCY_OPTIM_VAL(0); -- 2.21.0.5.gaeb582a _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl 2019-07-02 4:18 ` [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl Vandita Kulkarni @ 2019-07-16 10:12 ` Shankar, Uma 0 siblings, 0 replies; 12+ messages in thread From: Shankar, Uma @ 2019-07-16 10:12 UTC (permalink / raw) To: Kulkarni, Vandita, intel-gfx; +Cc: Nikula, Jani >-----Original Message----- >From: Kulkarni, Vandita >Sent: Tuesday, July 2, 2019 9:49 AM >To: intel-gfx@lists.freedesktop.org >Cc: ville.syrjala@linux.intel.com; Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma ><uma.shankar@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com> >Subject: [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl > >Rest of the latency programming remains same as that of ICL. You can put this as "latency programming for TGL remains same as that of ICL and EHL. Extended the same for TGL" With this minor nit fixed. Reviewed-by: Uma Shankar <uma.shankar@intel.com> >Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> >--- > drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c >b/drivers/gpu/drm/i915/display/icl_dsi.c >index 556eba2636fe..e3980676bcef 100644 >--- a/drivers/gpu/drm/i915/display/icl_dsi.c >+++ b/drivers/gpu/drm/i915/display/icl_dsi.c >@@ -404,8 +404,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct >intel_encoder *encoder) > tmp |= FRC_LATENCY_OPTIM_VAL(0x5); > I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp); > >- /* For EHL set latency optimization for PCS_DW1 lanes */ >- if (IS_ELKHARTLAKE(dev_priv)) { >+ /* EHL and TGL, set latency optimization for PCS_DW1 lanes */ >+ if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) { > tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port)); > tmp &= ~LATENCY_OPTIM_MASK; > tmp |= LATENCY_OPTIM_VAL(0); >-- >2.21.0.5.gaeb582a _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE 2019-07-02 4:18 [PATCH 0/4] Support mipi dsi video mode on TGL Vandita Kulkarni 2019-07-02 4:18 ` [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni 2019-07-02 4:18 ` [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl Vandita Kulkarni @ 2019-07-02 4:18 ` Vandita Kulkarni 2019-07-16 10:16 ` Shankar, Uma 2019-07-02 4:18 ` [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping Vandita Kulkarni ` (2 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Vandita Kulkarni @ 2019-07-02 4:18 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Do not override TA_SURE timing parameter to zero for DSI 8X frequency 800MHz or below on TGL. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index e3980676bcef..d1c50a4186f0 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -530,18 +530,20 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) * a value '0' inside TA_PARAM_REGISTERS otherwise * leave all fields at HW default values. */ - if (intel_dsi_bitrate(intel_dsi) <= 800000) { - for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(DPHY_TA_TIMING_PARAM(port)); - tmp &= ~TA_SURE_MASK; - tmp |= TA_SURE_OVERRIDE | TA_SURE(0); - I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp); - - /* shadow register inside display core */ - tmp = I915_READ(DSI_TA_TIMING_PARAM(port)); - tmp &= ~TA_SURE_MASK; - tmp |= TA_SURE_OVERRIDE | TA_SURE(0); - I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp); + if (IS_GEN(dev_priv, 11)) { + if (intel_dsi_bitrate(intel_dsi) <= 800000) { + for_each_dsi_port(port, intel_dsi->ports) { + tmp = I915_READ(DPHY_TA_TIMING_PARAM(port)); + tmp &= ~TA_SURE_MASK; + tmp |= TA_SURE_OVERRIDE | TA_SURE(0); + I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp); + + /* shadow register inside display core */ + tmp = I915_READ(DSI_TA_TIMING_PARAM(port)); + tmp &= ~TA_SURE_MASK; + tmp |= TA_SURE_OVERRIDE | TA_SURE(0); + I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp); + } } } -- 2.21.0.5.gaeb582a _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE 2019-07-02 4:18 ` [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE Vandita Kulkarni @ 2019-07-16 10:16 ` Shankar, Uma 0 siblings, 0 replies; 12+ messages in thread From: Shankar, Uma @ 2019-07-16 10:16 UTC (permalink / raw) To: Kulkarni, Vandita, intel-gfx; +Cc: Nikula, Jani >-----Original Message----- >From: Kulkarni, Vandita >Sent: Tuesday, July 2, 2019 9:49 AM >To: intel-gfx@lists.freedesktop.org >Cc: ville.syrjala@linux.intel.com; Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma ><uma.shankar@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com> >Subject: [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE > >Do not override TA_SURE timing parameter to zero for DSI 8X frequency 800MHz or >below on TGL. Looks good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> >Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> >--- > drivers/gpu/drm/i915/display/icl_dsi.c | 26 ++++++++++++++------------ > 1 file changed, 14 insertions(+), 12 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c >b/drivers/gpu/drm/i915/display/icl_dsi.c >index e3980676bcef..d1c50a4186f0 100644 >--- a/drivers/gpu/drm/i915/display/icl_dsi.c >+++ b/drivers/gpu/drm/i915/display/icl_dsi.c >@@ -530,18 +530,20 @@ static void gen11_dsi_setup_dphy_timings(struct >intel_encoder *encoder) > * a value '0' inside TA_PARAM_REGISTERS otherwise > * leave all fields at HW default values. > */ >- if (intel_dsi_bitrate(intel_dsi) <= 800000) { >- for_each_dsi_port(port, intel_dsi->ports) { >- tmp = I915_READ(DPHY_TA_TIMING_PARAM(port)); >- tmp &= ~TA_SURE_MASK; >- tmp |= TA_SURE_OVERRIDE | TA_SURE(0); >- I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp); >- >- /* shadow register inside display core */ >- tmp = I915_READ(DSI_TA_TIMING_PARAM(port)); >- tmp &= ~TA_SURE_MASK; >- tmp |= TA_SURE_OVERRIDE | TA_SURE(0); >- I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp); >+ if (IS_GEN(dev_priv, 11)) { >+ if (intel_dsi_bitrate(intel_dsi) <= 800000) { >+ for_each_dsi_port(port, intel_dsi->ports) { >+ tmp = I915_READ(DPHY_TA_TIMING_PARAM(port)); >+ tmp &= ~TA_SURE_MASK; >+ tmp |= TA_SURE_OVERRIDE | TA_SURE(0); >+ I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp); >+ >+ /* shadow register inside display core */ >+ tmp = I915_READ(DSI_TA_TIMING_PARAM(port)); >+ tmp &= ~TA_SURE_MASK; >+ tmp |= TA_SURE_OVERRIDE | TA_SURE(0); >+ I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp); >+ } > } > } > >-- >2.21.0.5.gaeb582a _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping 2019-07-02 4:18 [PATCH 0/4] Support mipi dsi video mode on TGL Vandita Kulkarni ` (2 preceding siblings ...) 2019-07-02 4:18 ` [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE Vandita Kulkarni @ 2019-07-02 4:18 ` Vandita Kulkarni 2019-07-16 10:24 ` Shankar, Uma 2019-07-02 5:21 ` ✓ Fi.CI.BAT: success for Support mipi dsi video mode on TGL Patchwork 2019-07-03 2:02 ` ✓ Fi.CI.IGT: " Patchwork 5 siblings, 1 reply; 12+ messages in thread From: Vandita Kulkarni @ 2019-07-02 4:18 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula No need to keep it on till IO enabling. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index d1c50a4186f0..99ce8c708353 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -609,8 +609,12 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, I915_WRITE(DPCLKA_CFGCR0_ICL, val); for_each_dsi_port(port, intel_dsi->ports) { - val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); + if (INTEL_GEN(dev_priv) >= 12) + val |= DPCLKA_CFGCR0_DDI_CLK_OFF(port); + else + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); } + I915_WRITE(DPCLKA_CFGCR0_ICL, val); POSTING_READ(DPCLKA_CFGCR0_ICL); @@ -955,6 +959,8 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + /* step 4a: power up all lanes of the DDI used by DSI */ gen11_dsi_power_up_lanes(encoder); @@ -977,7 +983,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, gen11_dsi_configure_transcoder(encoder, pipe_config); /* Step 4l: Gate DDI clocks */ - gen11_dsi_gate_clocks(encoder); + if (IS_GEN(dev_priv, 11)) + gen11_dsi_gate_clocks(encoder); } static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) -- 2.21.0.5.gaeb582a _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping 2019-07-02 4:18 ` [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping Vandita Kulkarni @ 2019-07-16 10:24 ` Shankar, Uma 0 siblings, 0 replies; 12+ messages in thread From: Shankar, Uma @ 2019-07-16 10:24 UTC (permalink / raw) To: Kulkarni, Vandita, intel-gfx; +Cc: Nikula, Jani >-----Original Message----- >From: Kulkarni, Vandita >Sent: Tuesday, July 2, 2019 9:49 AM >To: intel-gfx@lists.freedesktop.org >Cc: ville.syrjala@linux.intel.com; Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma ><uma.shankar@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com> >Subject: [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping > >No need to keep it on till IO enabling. Minor nit: You can replace "it" by "ddi clock". Also add that when (at what stage) they get enabled to give a relative picture. With this fixed. Reviewed-by: Uma Shankar <uma.shankar@intel.com> >Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> >--- > drivers/gpu/drm/i915/display/icl_dsi.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c >b/drivers/gpu/drm/i915/display/icl_dsi.c >index d1c50a4186f0..99ce8c708353 100644 >--- a/drivers/gpu/drm/i915/display/icl_dsi.c >+++ b/drivers/gpu/drm/i915/display/icl_dsi.c >@@ -609,8 +609,12 @@ static void gen11_dsi_map_pll(struct intel_encoder >*encoder, > I915_WRITE(DPCLKA_CFGCR0_ICL, val); > > for_each_dsi_port(port, intel_dsi->ports) { >- val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); >+ if (INTEL_GEN(dev_priv) >= 12) >+ val |= DPCLKA_CFGCR0_DDI_CLK_OFF(port); >+ else >+ val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); > } >+ > I915_WRITE(DPCLKA_CFGCR0_ICL, val); > > POSTING_READ(DPCLKA_CFGCR0_ICL); >@@ -955,6 +959,8 @@ static void > gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, > const struct intel_crtc_state *pipe_config) { >+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >+ > /* step 4a: power up all lanes of the DDI used by DSI */ > gen11_dsi_power_up_lanes(encoder); > >@@ -977,7 +983,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder >*encoder, > gen11_dsi_configure_transcoder(encoder, pipe_config); > > /* Step 4l: Gate DDI clocks */ >- gen11_dsi_gate_clocks(encoder); >+ if (IS_GEN(dev_priv, 11)) >+ gen11_dsi_gate_clocks(encoder); > } > > static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) >-- >2.21.0.5.gaeb582a _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for Support mipi dsi video mode on TGL 2019-07-02 4:18 [PATCH 0/4] Support mipi dsi video mode on TGL Vandita Kulkarni ` (3 preceding siblings ...) 2019-07-02 4:18 ` [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping Vandita Kulkarni @ 2019-07-02 5:21 ` Patchwork 2019-07-03 2:02 ` ✓ Fi.CI.IGT: " Patchwork 5 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2019-07-02 5:21 UTC (permalink / raw) To: Vandita Kulkarni; +Cc: intel-gfx == Series Details == Series: Support mipi dsi video mode on TGL URL : https://patchwork.freedesktop.org/series/63058/ State : success == Summary == CI Bug Log - changes from CI_DRM_6394 -> Patchwork_13486 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/ Known issues ------------ Here are the changes found in Patchwork_13486 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_reloc@basic-gtt-cpu: - fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-icl-dsi/igt@gem_exec_reloc@basic-gtt-cpu.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/fi-icl-dsi/igt@gem_exec_reloc@basic-gtt-cpu.html * igt@i915_selftest@live_blt: - fi-skl-iommu: [PASS][3] -> [INCOMPLETE][4] ([fdo#108602]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-skl-iommu/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/fi-skl-iommu/igt@i915_selftest@live_blt.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html * igt@gem_mmap_gtt@basic-small-bo-tiledy: - fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledy.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-skl-6600u: [DMESG-WARN][9] ([fdo#111012]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html * igt@i915_selftest@live_blt: - fi-cfl-guc: [DMESG-WARN][11] ([fdo#110943]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-cfl-guc/igt@i915_selftest@live_blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/fi-cfl-guc/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hugepages: - fi-skl-gvtdvm: [DMESG-WARN][13] ([fdo#110976]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-skl-gvtdvm/igt@i915_selftest@live_hugepages.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/fi-skl-gvtdvm/igt@i915_selftest@live_hugepages.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][15] ([fdo#109485]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: [FAIL][17] ([fdo#103167]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html - fi-icl-u2: [FAIL][19] ([fdo#103167]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html * igt@prime_vgem@basic-fence-flip: - fi-ilk-650: [DMESG-WARN][21] ([fdo#106387]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#110943]: https://bugs.freedesktop.org/show_bug.cgi?id=110943 [fdo#110976]: https://bugs.freedesktop.org/show_bug.cgi?id=110976 [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012 Participating hosts (50 -> 45) ------------------------------ Additional (2): fi-icl-guc fi-cml-u Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper Build changes ------------- * Linux: CI_DRM_6394 -> Patchwork_13486 CI_DRM_6394: ad42b755acd3c10f7a8e23309189f0a850ec92c5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5075: 03779dd3de8a57544f124d9952a6d2b3e34e34ca @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13486: eb32151c7ed411239b1ca6f85eb88b4065caa9cd @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/build_32bit.log CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == eb32151c7ed4 drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping 2ed0acf47c1d drm/i915/tgl/dsi: Do not override TA_SURE 3714096ad52e drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl 029a9c99e898 drm/i915/tgl/dsi: Program TRANS_VBLANK register == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.IGT: success for Support mipi dsi video mode on TGL 2019-07-02 4:18 [PATCH 0/4] Support mipi dsi video mode on TGL Vandita Kulkarni ` (4 preceding siblings ...) 2019-07-02 5:21 ` ✓ Fi.CI.BAT: success for Support mipi dsi video mode on TGL Patchwork @ 2019-07-03 2:02 ` Patchwork 5 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2019-07-03 2:02 UTC (permalink / raw) To: Vandita Kulkarni; +Cc: intel-gfx == Series Details == Series: Support mipi dsi video mode on TGL URL : https://patchwork.freedesktop.org/series/63058/ State : success == Summary == CI Bug Log - changes from CI_DRM_6394_full -> Patchwork_13486_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_13486_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_tiled_swapping@non-threaded: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108686]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-kbl1/igt@gem_tiled_swapping@non-threaded.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-kbl2/igt@gem_tiled_swapping@non-threaded.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html * igt@i915_suspend@forcewake: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#103313]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-kbl4/igt@i915_suspend@forcewake.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-kbl3/igt@i915_suspend@forcewake.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbc-tilingchange: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-tilingchange.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-tilingchange.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [fdo#110403]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103166]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-y.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb2/igt@kms_psr@psr2_dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-iclb5/igt@kms_psr@psr2_dpms.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#104108]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-skl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@perf@blocking: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#110728]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl2/igt@perf@blocking.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-skl7/igt@perf@blocking.html #### Possible fixes #### * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][21] ([fdo#110854]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb5/igt@gem_exec_balancer@smoke.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-iclb2/igt@gem_exec_balancer@smoke.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [DMESG-WARN][23] ([fdo#108686]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk4/igt@gem_tiled_swapping@non-threaded.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-glk7/igt@gem_tiled_swapping@non-threaded.html * igt@i915_selftest@mock_requests: - shard-glk: [INCOMPLETE][25] ([fdo#103359] / [k.org#198133]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk2/igt@i915_selftest@mock_requests.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-glk2/igt@i915_selftest@mock_requests.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [DMESG-WARN][27] ([fdo#108566]) -> [PASS][28] +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-apl5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions: - shard-hsw: [FAIL][29] ([fdo#103355]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-hsw4/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [FAIL][31] ([fdo#105363]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [FAIL][33] ([fdo#103167]) -> [PASS][34] +5 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc: - shard-glk: [FAIL][35] ([fdo#103167]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-glk7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-glk2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-iclb: [INCOMPLETE][37] ([fdo#107713] / [fdo#110042]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-iclb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][39] ([fdo#108145]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][41] ([fdo#109441]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-iclb3/igt@kms_psr@psr2_primary_page_flip.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_setmode@basic: - shard-skl: [FAIL][43] ([fdo#99912]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6394/shard-skl2/igt@kms_setmode@basic.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/shard-skl3/igt@kms_setmode@basic.html [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313 [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110042]: https://bugs.freedesktop.org/show_bug.cgi?id=110042 [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403 [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728 [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_6394 -> Patchwork_13486 CI_DRM_6394: ad42b755acd3c10f7a8e23309189f0a850ec92c5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5075: 03779dd3de8a57544f124d9952a6d2b3e34e34ca @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13486: eb32151c7ed411239b1ca6f85eb88b4065caa9cd @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13486/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-07-30 6:24 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-07-02 4:18 [PATCH 0/4] Support mipi dsi video mode on TGL Vandita Kulkarni 2019-07-02 4:18 ` [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni 2019-07-16 9:58 ` Shankar, Uma 2019-07-30 6:24 ` Kulkarni, Vandita 2019-07-02 4:18 ` [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl Vandita Kulkarni 2019-07-16 10:12 ` Shankar, Uma 2019-07-02 4:18 ` [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE Vandita Kulkarni 2019-07-16 10:16 ` Shankar, Uma 2019-07-02 4:18 ` [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping Vandita Kulkarni 2019-07-16 10:24 ` Shankar, Uma 2019-07-02 5:21 ` ✓ Fi.CI.BAT: success for Support mipi dsi video mode on TGL Patchwork 2019-07-03 2:02 ` ✓ Fi.CI.IGT: " Patchwork
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