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* [PATCH v5 00/13] ICELAKE DSI DRIVER
@ 2018-07-10  9:40 Madhav Chauhan
  2018-07-10  9:40 ` [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
                   ` (17 more replies)
  0 siblings, 18 replies; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to
GPU/Display Engine and same could be extended for future Intel platforms as well.
DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification.

So, a new DSI driver has been added inside I915.

Given below patches are the part of new DSI driver which implements BSPEC
sequence till transcoder configuration. Rest of the patches published to GITHUB
and latest snapshot can be downloaded using:
#git clone https://github.com/madhavchauhan/Intel-DSI-Driver.git

v2: Addressed review comments from Jani N for Patches 1-6 and rebase for some
other few patches.
v3: Renamed intel_dsi_new.c to gen11_dsi.c as per discussion with Jani, Daniel,
    Ville. Also addressed review comments for couple of patches.
v4: Rename gen11_dsi.c to icl_dsi.c (Ville). No functional changes.
v5: Rebase on drm-tip after initial 7 patches got merged.

Madhav Chauhan (13):
  drm/i915/icl: Configure lane sequencing of combo phy transmitter
  drm/i915/icl: DSI vswing programming sequence
  drm/i915/icl: Enable DDI Buffer
  drm/i915/icl: Define T_INIT_MASTER registers
  drm/i915/icl: Program T_INIT_MASTER registers
  drm/i915/icl: Define data/clock lanes dphy timing registers
  drm/i915/icl: Program DSI clock and data lane timing params
  drm/i915/icl: Define TA_TIMING_PARAM registers
  drm/i915/icl: Program TA_TIMING_PARAM registers
  drm/i915/icl: Get DSI transcoder for a given port
  drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
  drm/i915/icl: Configure DSI transcoders

 drivers/gpu/drm/i915/i915_reg.h      | 112 ++++++++++++
 drivers/gpu/drm/i915/icl_dsi.c       | 324 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.h |   6 +-
 drivers/gpu/drm/i915/intel_dsi.h     |   7 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 202 ++++++++++++++++------
 5 files changed, 593 insertions(+), 58 deletions(-)

-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-07-19 16:11   ` Ville Syrjälä
  2018-09-10 12:20   ` Lisovskiy, Stanislav
  2018-07-10  9:40 ` [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
                   ` (16 subsequent siblings)
  17 siblings, 2 replies; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch set the loadgen select and latency optimization for
aux and transmit lanes of combo phy transmitters. It will be
used for MIPI DSI HS operations.

v2: Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 13830e4..a571339 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp;
+	int lane;
+
+	/* Step 4b(i) set loadgen select for transmit and aux lanes */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+		tmp &= ~LOADGEN_SELECT;
+		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+		for (lane = 0; lane <= 3; lane++) {
+			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
+			tmp &= ~LOADGEN_SELECT;
+			if (lane != 2)
+				tmp |= LOADGEN_SELECT;
+			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
+		}
+	}
+
+	/* Step 4b(ii) set latency optimization for transmit and aux lanes */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+		tmp &= ~FRC_LATENCY_OPTIM_MASK;
+		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
+		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+		tmp &= ~FRC_LATENCY_OPTIM_MASK;
+		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
+		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
 	gen11_dsi_power_up_lanes(encoder);
+
+	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
+	gen11_dsi_config_phy_lanes_sequence(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.7.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 63+ messages in thread
* [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
  2018-07-10  9:40 ` [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-09-06 14:01   ` [v5, " Kulkarni, Vandita
  2018-09-11 18:50   ` [PATCH v5 " Jani Nikula
  2018-07-10  9:40 ` [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
                   ` (15 subsequent siblings)
  17 siblings, 2 replies; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch setup voltage swing before enabling
combo PHY DDI (shared with DSI).
Note that DSI voltage swing programming is for
high speed data buffers. HW automatically handles
the voltage swing for the low power data buffers.

v2: Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 114 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index a571339..dc16c1f 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -27,6 +27,65 @@
 
 #include "intel_dsi.h"
 
+static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp;
+	int lane;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+
+		/* Bspec: set scaling mode to 0x6 */
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp |= SCALING_MODE_SEL(6);
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp |= SCALING_MODE_SEL(6);
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp |= TAP2_DISABLE | TAP3_DISABLE;
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp |= TAP2_DISABLE | TAP3_DISABLE;
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+
+		/*
+		 * swing and scaling values are taken from DSI
+		 * table under vswing programming sequence for
+		 * combo phy ddi in BSPEC.
+		 * program swing values
+		 */
+		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+		tmp |= SWING_SEL_UPPER(0x2);
+		tmp |= SWING_SEL_LOWER(0x2);
+		tmp |= RCOMP_SCALAR(0x98);
+		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+		tmp |= SWING_SEL_UPPER(0x2);
+		tmp |= SWING_SEL_LOWER(0x2);
+		tmp |= RCOMP_SCALAR(0x98);
+		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+
+		/* program scaling values */
+		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+		tmp |= POST_CURSOR_1(0x0);
+		tmp |= POST_CURSOR_2(0x0);
+		tmp |= CURSOR_COEFF(0x18);
+		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+
+		for (lane = 0; lane <= 3; lane++) {
+			/* Bspec: must not use GRP register for write */
+			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
+			tmp |= POST_CURSOR_1(0x0);
+			tmp |= POST_CURSOR_2(0x0);
+			tmp |= CURSOR_COEFF(0x18);
+			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
+		}
+	}
+}
+
 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -140,6 +199,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+
+	/* Step C.1:clear common keeper enable bit */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
+		tmp &= ~COMMON_KEEPER_EN;
+		I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
+		tmp &= ~COMMON_KEEPER_EN;
+		I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
+	}
+
+	/*
+	 * Step C.3: Set SUS Clock Config bitfield to 11b
+	 * Note: Step C.2 (loadgen select program) is done
+	 * as part of lane phy sequence configuration
+	 */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_CL_DW5(port));
+		tmp |= SUS_CLOCK_CONFIG;
+		I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
+	}
+
+	/* Step C.4: Clear training enable to change swing values */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp &= ~TX_TRAINING_EN;
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp &= ~TX_TRAINING_EN;
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+	}
+
+	/* Step C.5: Program swing and de-emphasis */
+	dsi_program_swing_and_deemphasis(encoder);
+
+	/* Step: C.6: Set training enable to trigger update */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp |= TX_TRAINING_EN;
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp |= TX_TRAINING_EN;
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -147,6 +258,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
 	gen11_dsi_config_phy_lanes_sequence(encoder);
+
+	/* step 4c: configure voltage swing and skew */
+	gen11_dsi_voltage_swing_program_seq(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 63+ messages in thread
* [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
  2018-07-10  9:40 ` [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
  2018-07-10  9:40 ` [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-09-11 18:54   ` Jani Nikula
  2018-07-10  9:40 ` [PATCH v5 04/13] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
                   ` (14 subsequent siblings)
  17 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch enables DDI buffer by writing to DDI_BUF_CTL
register and wait for DDI status to be *not idle* for a
port.

v2: Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index dc16c1f..41faa19 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -251,6 +251,25 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(DDI_BUF_CTL(port));
+		tmp |= DDI_BUF_CTL_ENABLE;
+		I915_WRITE(DDI_BUF_CTL(port), tmp);
+
+		if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
+				  DDI_BUF_IS_IDLE),
+				  500))
+			DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -261,6 +280,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* step 4c: configure voltage swing and skew */
 	gen11_dsi_voltage_swing_program_seq(encoder);
+
+	/* step 4d: enable DDI buffer */
+	gen11_dsi_enable_ddi_buffer(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 63+ messages in thread
* [PATCH v5 04/13] drm/i915/icl: Define T_INIT_MASTER registers
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (2 preceding siblings ...)
  2018-07-10  9:40 ` [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-09-11 19:18   ` Jani Nikula
  2018-07-10  9:40 ` [PATCH v5 05/13] drm/i915/icl: Program " Madhav Chauhan
                   ` (13 subsequent siblings)
  17 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch defines DSI_T_INIT_MASTER register for DSI ports
0/1 which will be used in dphy programming.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0424e45..6129372 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10069,6 +10069,12 @@ enum skl_power_gate {
 #define  PREPARE_COUNT_SHIFT				0
 #define  PREPARE_COUNT_MASK				(0x3f << 0)
 
+#define _ICL_DSI_T_INIT_MASTER_0	0x6b088
+#define _ICL_DSI_T_INIT_MASTER_1	0x6b888
+#define ICL_DSI_T_INIT_MASTER(port)	_MMIO_PORT(port,	\
+						   _ICL_DSI_T_INIT_MASTER_0,\
+						   _ICL_DSI_T_INIT_MASTER_1)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 63+ messages in thread
* [PATCH v5 05/13] drm/i915/icl: Program T_INIT_MASTER registers
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (3 preceding siblings ...)
  2018-07-10  9:40 ` [PATCH v5 04/13] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-09-11 19:17   ` Jani Nikula
  2018-07-10  9:40 ` [PATCH v5 06/13] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
                   ` (12 subsequent siblings)
  17 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch programs the time (in escape clocks) to drive
the link in the initialization (i.e. LP-11) state.

v2: Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 41faa19..bc27e34 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -270,6 +270,22 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+
+	/* Program T-INIT master registers */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port));
+		tmp &= ~MASTER_INIT_TIMER_MASK;
+		tmp |= intel_dsi->init_count;
+		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -283,6 +299,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* step 4d: enable DDI buffer */
 	gen11_dsi_enable_ddi_buffer(encoder);
+
+	/* step 4e: setup D-PHY timings */
+	gen11_dsi_setup_dphy_timings(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 63+ messages in thread
* [PATCH v5 06/13] drm/i915/icl: Define data/clock lanes dphy timing registers
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (4 preceding siblings ...)
  2018-07-10  9:40 ` [PATCH v5 05/13] drm/i915/icl: Program " Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-09-11 19:14   ` Jani Nikula
  2018-07-10  9:40 ` [PATCH v5 07/13] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
                   ` (11 subsequent siblings)
  17 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6129372..0dbdd57 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10075,6 +10075,46 @@ enum skl_power_gate {
 						   _ICL_DSI_T_INIT_MASTER_0,\
 						   _ICL_DSI_T_INIT_MASTER_1)
 
+#define _DPHY_CLK_TIMING_PARAM_0	0x162180
+#define _DPHY_CLK_TIMING_PARAM_1	0x6c180
+#define DPHY_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DPHY_CLK_TIMING_PARAM_0,\
+						   _DPHY_CLK_TIMING_PARAM_1)
+#define _DSI_CLK_TIMING_PARAM_0		0x6b080
+#define _DSI_CLK_TIMING_PARAM_1		0x6b880
+#define DSI_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DSI_CLK_TIMING_PARAM_0,\
+						   _DSI_CLK_TIMING_PARAM_1)
+#define  CLK_PREP_OVERRIDE		(1 << 31)
+#define  CLK_PREP_TIME(x)		(x << 28)
+#define  CLK_ZERO_OVERRIDE		(1 << 27)
+#define  CLK_ZERO_TIME(x)		(x << 20)
+#define  CLK_PRE_OVERRIDE		(1 << 19)
+#define  CLK_PRE_TIME(x)		(x << 16)
+#define  CLK_POST_OVERRIDE		(1 << 15)
+#define  CLK_POST_TIME(x)		(x << 8)
+#define  CLK_TRAIL_OVERRIDE		(1 << 7)
+#define  CLK_TRAIL_TIME(x)		(x << 0)
+
+#define _DPHY_DATA_TIMING_PARAM_0	0x162184
+#define _DPHY_DATA_TIMING_PARAM_1	0x6c184
+#define DPHY_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DPHY_DATA_TIMING_PARAM_0,\
+						   _DPHY_DATA_TIMING_PARAM_1)
+#define _DSI_DATA_TIMING_PARAM_0	0x6B084
+#define _DSI_DATA_TIMING_PARAM_1	0x6B884
+#define DSI_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DSI_DATA_TIMING_PARAM_0,\
+						   _DSI_DATA_TIMING_PARAM_1)
+#define  HS_PREP_OVERRIDE		(1 << 31)
+#define  HS_PREP_TIME(x)		(x << 24)
+#define  HS_ZERO_OVERRIDE		(1 << 23)
+#define  HS_ZERO_TIME(x)		(x << 16)
+#define  HS_TRAIL_OVERRIDE		(1 << 15)
+#define  HS_TRAIL_TIME(x)		(x << 8)
+#define  HS_EXIT_OVERRIDE		(1 << 7)
+#define  HS_EXIT_TIME(x)		(x << 0)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 63+ messages in thread
* [PATCH v5 07/13] drm/i915/icl: Program DSI clock and data lane timing params
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (5 preceding siblings ...)
  2018-07-10  9:40 ` [PATCH v5 06/13] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-07-19 16:17   ` Ville Syrjälä
  2018-07-10  9:40 ` [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
                   ` (10 subsequent siblings)
  17 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       |  18 ++++
 drivers/gpu/drm/i915/intel_dsi.h     |   3 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 200 +++++++++++++++++++++++++----------
 3 files changed, 165 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index bc27e34..832772d 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -284,6 +284,24 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 		tmp |= intel_dsi->init_count;
 		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
 	}
+
+	/* Program DPHY clock lanes timings */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
+
+		/* shadow register inside display core */
+		I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
+	}
+
+	/* Program DPHY data lanes timings */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
+			   intel_dsi->dphy_data_lane_reg);
+
+		/* shadow register inside display core */
+		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
+			   intel_dsi->dphy_data_lane_reg);
+	}
 }
 
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index ad7c1cb..9fd8526 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -85,6 +85,9 @@ struct intel_dsi {
 	u32 port_bits;
 	u32 bw_timer;
 	u32 dphy_reg;
+
+	/* data lanes dphy timing */
+	u32 dphy_data_lane_reg;
 	u32 video_frmt_cfg_bits;
 	u16 lp_byte_clk;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index ac83d6b..428290d 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -509,7 +509,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	u32 bpp;
 	u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
 	u32 ui_num, ui_den;
-	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
+	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt, hs_zero_cnt;
+	u32 tclk_pre_cnt, tclk_post_cnt;
+	u32 tclk_pre_ns, tclk_post_ns;
 	u32 ths_prepare_ns, tclk_trail_ns;
 	u32 tclk_prepare_clkzero, ths_prepare_hszero;
 	u32 lp_to_hs_switch, hs_to_lp_switch;
@@ -624,76 +626,157 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
 	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
-
+	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
+	ths_prepare_ns = max(mipi_config->ths_prepare,
+				mipi_config->tclk_prepare);
 	/*
 	 * B060
 	 * LP byte clock = TLPX/ (8UI)
 	 */
 	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
 
-	/* DDR clock period = 2 * UI
-	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
-	 * UI(nsec) = 10^6 / bitrate
-	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
-	 * DDR clock count  = ns_value / DDR clock period
-	 *
+	/*
 	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
 	 * HS byte clock count for other platform in HS ddr clock count
 	 */
 	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
-	ths_prepare_ns = max(mipi_config->ths_prepare,
-			     mipi_config->tclk_prepare);
 
-	/* prepare count */
-	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
+	if (IS_ICELAKE(dev_priv)) {
+		/*
+		 * prepare cnt in escape clocks
+		 * this field represents a hexadecimal value with a precision
+		 * of 1.2 – i.e. the most significant bit is the integer
+		 * and the least significant 2 bits are fraction bits.
+		 * so, the field can represent a range of 0.25 to 1.75
+		 */
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
+
+		/* clk zero count in escape clocks */
+		clk_zero_cnt = DIV_ROUND_UP(
+					(tclk_prepare_clkzero - ths_prepare_ns),
+					tlpx_ns);
+
+		/* trail cnt in escape clocks*/
+		trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
+
+		/* tclk pre/post count in escape clocks */
+		tclk_post_ns = mipi_config->tclk_post;
+		tclk_pre_ns = mipi_config->tclk_pre;
+		tclk_pre_cnt = DIV_ROUND_UP(tclk_pre_ns, tlpx_ns);
+		tclk_post_cnt = DIV_ROUND_UP(tclk_post_ns, tlpx_ns);
+
+		/* hs zero cnt in escape clocks */
+		hs_zero_cnt = DIV_ROUND_UP(
+					(ths_prepare_hszero - ths_prepare_ns),
+					tlpx_ns);
+
+		/* hs exit zero cnt in escape clocks */
+		exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
+
+		if (prepare_cnt > 0x7 ||
+		    clk_zero_cnt > 0xF ||
+		    tclk_pre_cnt > 0x3 ||
+		    tclk_post_cnt > 0x7 ||
+		    trail_cnt > 0x7 ||
+		    hs_zero_cnt > 0xF ||
+		    exit_zero_cnt > 0x7) {
+			DRM_DEBUG_DRIVER("DPHY values crossing max limits,");
+			DRM_DEBUG_DRIVER("restricting to max values\n");
+		}
+
+		prepare_cnt = (prepare_cnt > 0x7) ? 0x7 : prepare_cnt;
+		clk_zero_cnt = (clk_zero_cnt > 0xF) ? 0xF : clk_zero_cnt;
+		tclk_pre_cnt = (tclk_pre_cnt > 0x3) ? 0x3 : tclk_pre_cnt;
+		tclk_post_cnt = (tclk_post_cnt > 0x7) ? 0x7 : tclk_post_cnt;
+		trail_cnt = (trail_cnt > 0x7) ? 0x7 : trail_cnt;
+		hs_zero_cnt = (hs_zero_cnt > 0xF) ? 0xF : hs_zero_cnt;
+		exit_zero_cnt = (exit_zero_cnt > 0x7) ? 0x7 : exit_zero_cnt;
+
+		/* clock lane dphy timings */
+		intel_dsi->dphy_reg |= (CLK_PREP_OVERRIDE |
+					CLK_PREP_TIME(prepare_cnt) |
+					CLK_ZERO_OVERRIDE |
+					CLK_ZERO_TIME(clk_zero_cnt) |
+					CLK_PRE_OVERRIDE |
+					CLK_PRE_TIME(tclk_pre_cnt) |
+					CLK_POST_OVERRIDE |
+					CLK_POST_TIME(tclk_post_cnt) |
+					CLK_TRAIL_OVERRIDE |
+					CLK_TRAIL_TIME(trail_cnt));
+
+		/* data lanes dphy timings */
+		intel_dsi->dphy_data_lane_reg = HS_PREP_OVERRIDE |
+						HS_PREP_TIME(prepare_cnt) |
+						HS_ZERO_OVERRIDE |
+						HS_ZERO_TIME(hs_zero_cnt) |
+						HS_TRAIL_OVERRIDE |
+						HS_TRAIL_TIME(trail_cnt) |
+						HS_EXIT_OVERRIDE |
+						HS_EXIT_TIME(exit_zero_cnt);
+	} else {
+		/*
+		 * DDR clock period = 2 * UI
+		 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
+		 * UI(nsec) = 10^6 / bitrate
+		 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
+		 * DDR clock count  = ns_value / DDR clock period
+		 */
 
-	if (prepare_cnt > PREPARE_CNT_MAX) {
-		DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
-		prepare_cnt = PREPARE_CNT_MAX;
-	}
+		/* prepare count */
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
+							ui_num * mul);
 
-	/* exit zero count */
-	exit_zero_cnt = DIV_ROUND_UP(
+		if (prepare_cnt > PREPARE_CNT_MAX) {
+			DRM_DEBUG_KMS("prepare count too high %u\n",
+								prepare_cnt);
+			prepare_cnt = PREPARE_CNT_MAX;
+		}
+
+		/* exit zero count */
+		exit_zero_cnt = DIV_ROUND_UP(
 				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
 				ui_num * mul
 				);
 
-	/*
-	 * Exit zero is unified val ths_zero and ths_exit
-	 * minimum value for ths_exit = 110ns
-	 * min (exit_zero_cnt * 2) = 110/UI
-	 * exit_zero_cnt = 55/UI
-	 */
-	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
-		exit_zero_cnt += 1;
-
-	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
-		DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
-		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
-	}
+		/*
+		 * Exit zero is unified val ths_zero and ths_exit
+		 * minimum value for ths_exit = 110ns
+		 * min (exit_zero_cnt * 2) = 110/UI
+		 * exit_zero_cnt = 55/UI
+		 */
+		if (exit_zero_cnt < (55 * ui_den / ui_num) &&
+					(55 * ui_den) % ui_num)
+			exit_zero_cnt += 1;
+
+		if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
+			DRM_DEBUG_KMS("exit zero count too high %u\n",
+								exit_zero_cnt);
+			exit_zero_cnt = EXIT_ZERO_CNT_MAX;
+		}
 
-	/* clk zero count */
-	clk_zero_cnt = DIV_ROUND_UP(
-				(tclk_prepare_clkzero -	ths_prepare_ns)
-				* ui_den, ui_num * mul);
+		/* clk zero count */
+		clk_zero_cnt = DIV_ROUND_UP((tclk_prepare_clkzero -
+						ths_prepare_ns)
+						* ui_den, ui_num * mul);
 
-	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
-		DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
-		clk_zero_cnt = CLK_ZERO_CNT_MAX;
-	}
+		if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
+			DRM_DEBUG_KMS("clock zero count too high %u\n",
+								clk_zero_cnt);
+			clk_zero_cnt = CLK_ZERO_CNT_MAX;
+		}
 
-	/* trail count */
-	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
-	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
+		/* trail cnt */
+		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
 
-	if (trail_cnt > TRAIL_CNT_MAX) {
-		DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
-		trail_cnt = TRAIL_CNT_MAX;
-	}
+		if (trail_cnt > TRAIL_CNT_MAX) {
+			DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
+			trail_cnt = TRAIL_CNT_MAX;
+		}
 
-	/* B080 */
-	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
+		/* B080 */
+		intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
 						clk_zero_cnt << 8 | prepare_cnt;
+	}
 
 	/*
 	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
@@ -707,9 +790,10 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	 */
 	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
 
-	/* B044 */
-	/* FIXME:
-	 * The comment above does not match with the code */
+	/*
+	 * B044
+	 * FIXME: comment above does not match with the code
+	 */
 	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
 						exit_zero_cnt * mul + 10, 8);
 
@@ -718,8 +802,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
 	intel_dsi->hs_to_lp_count += extra_byte_count;
 
-	/* B088 */
-	/* LP -> HS for clock lanes
+	/*
+	 * B088
+	 * LP -> HS for clock lanes
 	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
 	 *						extra byte count
 	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
@@ -735,7 +820,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
 
-	/* HS->LP for Clock Lanes
+	/*
+	 * HS->LP for Clock Lanes
 	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
 	 *						Extra byte count
 	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
@@ -782,9 +868,11 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	DRM_DEBUG_KMS("BTA %s\n",
 			enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
 
-	/* delays in VBT are in unit of 100us, so need to convert
+	/*
+	 * delays in VBT are in unit of 100us, so need to convert
 	 * here in ms
-	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
+	 * Delay (100us) * 100 /1000 = Delay / 10 (ms)
+	 */
 	intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
 	intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
 	intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
-- 
2.7.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 63+ messages in thread
* [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (6 preceding siblings ...)
  2018-07-10  9:40 ` [PATCH v5 07/13] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-09-11 19:23   ` Jani Nikula
  2018-07-10  9:40 ` [PATCH v5 09/13] drm/i915/icl: Program " Madhav Chauhan
                   ` (9 subsequent siblings)
  17 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0dbdd57..1d13ba9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10115,6 +10115,20 @@ enum skl_power_gate {
 #define  HS_EXIT_OVERRIDE		(1 << 7)
 #define  HS_EXIT_TIME(x)		(x << 0)
 
+#define _DPHY_TA_TIMING_PARAM_0		0x162188
+#define _DPHY_TA_TIMING_PARAM_1		0x6c188
+#define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DPHY_TA_TIMING_PARAM_0,\
+						   _DPHY_TA_TIMING_PARAM_1)
+#define _DSI_TA_TIMING_PARAM_0		0x6b098
+#define _DSI_TA_TIMING_PARAM_1		0x6b898
+#define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DSI_TA_TIMING_PARAM_0,\
+						   _DSI_TA_TIMING_PARAM_1)
+#define  TA_SURE_OVERRIDE		(1 << 31)
+#define  TA_SURE_TIME(x)		(x << 16)
+#define  TA_SURE_TIME_MASK		(0x1f << 16)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 63+ messages in thread
* [PATCH v5 09/13] drm/i915/icl: Program TA_TIMING_PARAM registers
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (7 preceding siblings ...)
  2018-07-10  9:40 ` [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-07-19 16:21   ` Ville Syrjälä
  2018-07-10  9:40 ` [PATCH v5 10/13] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
                   ` (8 subsequent siblings)
  17 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi.h     |  1 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 832772d..8fd5284 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -302,6 +302,27 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
 			   intel_dsi->dphy_data_lane_reg);
 	}
+
+	/*
+	 * If DSI link operating at or below an 800 MHz,
+	 * TA_SURE should be override and programmed to
+	 * a value '0' inside TA_PARAM_REGISTERS otherwise
+	 * leave all fields at HW default values.
+	 */
+	if (intel_dsi->bitrate_khz <= KHz(800)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
+			tmp &= ~TA_SURE_TIME_MASK;
+			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
+			I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
+
+			/* shadow register inside display core */
+			tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
+			tmp &= ~TA_SURE_TIME_MASK;
+			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
+			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+		}
+	}
 }
 
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 9fd8526..25e7396 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -101,6 +101,7 @@ struct intel_dsi {
 
 	u16 init_count;
 	u32 pclk;
+	u32 bitrate_khz;
 	u16 burst_mode_ratio;
 
 	/* all delays in ms */
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 428290d..a9a98a4 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -589,6 +589,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->pclk = pclk;
 
 	bitrate = (pclk * bpp) / intel_dsi->lane_count;
+	intel_dsi->bitrate_khz = bitrate;
 
 	switch (intel_dsi->escape_clk_div) {
 	case 0:
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 63+ messages in thread
* [PATCH v5 10/13] drm/i915/icl: Get DSI transcoder for a given port
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (8 preceding siblings ...)
  2018-07-10  9:40 ` [PATCH v5 09/13] drm/i915/icl: Program " Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-07-10  9:40 ` [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
                   ` (7 subsequent siblings)
  17 siblings, 0 replies; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch adds a helper function to retrieve DSI
transcoder for a given DSI port using newly defined
enum names for DSI transcoders.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       | 9 +++++++++
 drivers/gpu/drm/i915/intel_display.h | 6 ++++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 8fd5284..243f434 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -27,6 +27,15 @@
 
 #include "intel_dsi.h"
 
+static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(
+								enum port port)
+{
+	if (port == PORT_A)
+		return TRANSCODER_DSI_0;
+	else
+		return TRANSCODER_DSI_1;
+}
+
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index ca5a10f..de1bc9d 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -43,8 +43,10 @@ enum transcoder {
 	TRANSCODER_B,
 	TRANSCODER_C,
 	TRANSCODER_EDP,
-	TRANSCODER_DSI_A,
-	TRANSCODER_DSI_C,
+	TRANSCODER_DSI_0,
+	TRANSCODER_DSI_1,
+	TRANSCODER_DSI_A = TRANSCODER_DSI_0,	/* legacy DSI */
+	TRANSCODER_DSI_C = TRANSCODER_DSI_1,	/* legacy DSI */
 
 	I915_MAX_TRANSCODERS
 };
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 63+ messages in thread
* [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (9 preceding siblings ...)
  2018-07-10  9:40 ` [PATCH v5 10/13] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-07-19 16:22   ` Ville Syrjälä
  2018-07-10  9:40 ` [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
                   ` (6 subsequent siblings)
  17 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
DSI transcoder registers.

Credits-to: Jani N

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1d13ba9..62bc76e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9576,6 +9576,11 @@ enum skl_power_gate {
 #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
 #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
 
+/* gen11 DSI */
+#define _DSI_TRANS(tc, dsi0, dsi1)	(((tc) == TRANSCODER_DSI_0) ?	\
+					 (dsi0) : (dsi1))
+#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO(_DSI_TRANS(tc, dsi0, dsi1))
+
 #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
 #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
 #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
-- 
2.7.4

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 63+ messages in thread
* [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (10 preceding siblings ...)
  2018-07-10  9:40 ` [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-09-11 19:30   ` Jani Nikula
  2018-07-10  9:40 ` [PATCH v5 13/13] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
                   ` (5 subsequent siblings)
  17 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 47 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 62bc76e..71ce6ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10134,6 +10134,53 @@ enum skl_power_gate {
 #define  TA_SURE_TIME(x)		(x << 16)
 #define  TA_SURE_TIME_MASK		(0x1f << 16)
 
+/* DSI transcoder configuration */
+#define _DSI_TRANS_FUNC_CONF_0		0x6b030
+#define _DSI_TRANS_FUNC_CONF_1		0x6b830
+#define DSI_TRANS_FUNC_CONF(tc)		_MMIO_DSI(tc,	\
+						  _DSI_TRANS_FUNC_CONF_0,\
+						  _DSI_TRANS_FUNC_CONF_1)
+#define  OP_MODE(x)			(x << 28)
+#define  OP_MODE_MASK			(0x3 << 28)
+#define  CMD_MODE_NO_GATE		0x0
+#define  CMD_MODE_TE_GATE		0x1
+#define  VIDEO_MODE_SYNC_EVENT		0x2
+#define  VIDEO_MODE_SYNC_PULSE		0x3
+#define  LINK_READY			(1 << 20)
+#define  PIX_FMT(x)			(x << 16)
+#define  PIX_FMT_MASK			(0x3 << 16)
+#define  PIX_FMT_RGB565		0x0
+#define  PIX_FMT_RGB666_PACKED		0x1
+#define  PIX_FMT_RGB666_LOOSE		0x2
+#define  PIX_FMT_RGB888		0x3
+#define  PIX_FMT_RGB101010		0x4
+#define  PIX_FMT_RGB121212		0x5
+#define  PIX_FMT_COMPRESSED		0x6
+#define  BGR_TRANSMISSION		(1 << 15)
+#define  PIX_VIRT_CHAN(x)		(x << 12)
+#define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
+#define  PIX_BUF_THRESHOLD(x)		((x & 0x3) << 10)
+#define  PIX_BUF_THRESHOLD_MASK	(0x3 << 10)
+#define  PIX_BUF_THRESHOLD_1_4		0x0
+#define  PIX_BUF_THRESHOLD_1_2		0x1
+#define  PIX_BUF_THRESHOLD_3_4		0x2
+#define  PIX_BUF_THRESHOLD_FULL	0x3
+#define  CONTINUOUS_CLK(x)		(x << 8)
+#define  CONTINUOUS_CLK_MASK		(0x3 << 8)
+#define  CLK_ENTER_LP_AFTER_DATA	0x0
+#define  CLK_HS_OR_LP			0x2
+#define  CLK_HS_CONTINUOUS		0x3
+#define  LINK_CALIBRATION(x)		(x << 4)
+#define  LINK_CALIBRATION_MASK		(0x3 << 4)
+#define  CALIBRATION_DISABLED		0x0
+#define  CALIBRATION_ENABLED_INITIAL_ONLY	0x2
+#define  CALIBRATION_ENABLED_INITIAL_PERIODIC	0x3
+#define  S3D_ORIENTATION(x)		(x << 1)
+#define  S3D_ORIENTATION_MASK		(0x1 << 1)
+#define  S3D_ORIENTATION_PORTRAIT	0x0
+#define  S3D_ORIENTATION_LANDSCAPE	0x1
+#define  EOTP_DISABLED			(1 << 0)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 63+ messages in thread
* [PATCH v5 13/13] drm/i915/icl: Configure DSI transcoders
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (11 preceding siblings ...)
  2018-07-10  9:40 ` [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
@ 2018-07-10  9:40 ` Madhav Chauhan
  2018-07-10 10:46 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev5) Patchwork
                   ` (4 subsequent siblings)
  17 siblings, 0 replies; 63+ messages in thread
From: Madhav Chauhan @ 2018-07-10  9:40 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring DSI transcoder.

v2: Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       | 87 +++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dsi.h     |  3 ++
 drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
 3 files changed, 89 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 243f434..be20d3f 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -27,8 +27,7 @@
 
 #include "intel_dsi.h"
 
-static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(
-								enum port port)
+static enum transcoder dsi_port_to_transcoder(enum port port)
 {
 	if (port == PORT_A)
 		return TRANSCODER_DSI_0;
@@ -334,6 +333,87 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+	enum transcoder dsi_trans;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+
+		if (intel_dsi->eotp_pkt == 0)
+			tmp |= EOTP_DISABLED;
+		else
+			tmp &= ~EOTP_DISABLED;
+
+		/* enable link calibration if freq > 1.5Gbps */
+		if (intel_dsi->bitrate_khz >= (1500 * 1000)) {
+			tmp &= ~LINK_CALIBRATION_MASK;
+			tmp |= LINK_CALIBRATION(
+					CALIBRATION_ENABLED_INITIAL_ONLY);
+		}
+
+		/* configure continuous clock */
+		tmp &= ~CONTINUOUS_CLK_MASK;
+		if (intel_dsi->clock_stop)
+			tmp |= CONTINUOUS_CLK(CLK_ENTER_LP_AFTER_DATA);
+		else
+			tmp |= CONTINUOUS_CLK(CLK_HS_CONTINUOUS);
+
+		/* configure buffer threshold limit to minimum */
+		tmp &= ~PIX_BUF_THRESHOLD_MASK;
+		tmp |= PIX_BUF_THRESHOLD(PIX_BUF_THRESHOLD_1_4);
+
+		/* set virtual channel to '0' */
+		tmp &= ~PIX_VIRT_CHAN_MASK;
+		tmp |= PIX_VIRT_CHAN(0x0);
+
+		/* program BGR transmission */
+		if (intel_dsi->bgr_enabled)
+			tmp |= BGR_TRANSMISSION;
+
+		/* select pixel format */
+		tmp &= ~PIX_FMT_MASK;
+
+		switch (intel_dsi->pixel_format) {
+		case MIPI_DSI_FMT_RGB888:
+			tmp |= PIX_FMT(PIX_FMT_RGB888);
+			break;
+		case MIPI_DSI_FMT_RGB666:
+			tmp |= PIX_FMT(PIX_FMT_RGB666_LOOSE);
+			break;
+		case MIPI_DSI_FMT_RGB666_PACKED:
+			tmp |= PIX_FMT(PIX_FMT_RGB666_PACKED);
+			break;
+		case MIPI_DSI_FMT_RGB565:
+			tmp |= PIX_FMT(PIX_FMT_RGB565);
+			break;
+		default:
+			DRM_ERROR("DSI pixel format unsupported\n");
+		}
+
+		/* program DSI operation mode */
+		if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+			tmp &= ~OP_MODE_MASK;
+			if (intel_dsi->video_mode_format ==
+					VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
+				tmp |= OP_MODE(VIDEO_MODE_SYNC_PULSE);
+			} else if (intel_dsi->video_mode_format ==
+					VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS) {
+				tmp |= OP_MODE(VIDEO_MODE_SYNC_EVENT);
+			} else {
+				DRM_ERROR("DSI Video Mode unsupported\n");
+			}
+		}
+
+		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -350,6 +430,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* step 4e: setup D-PHY timings */
 	gen11_dsi_setup_dphy_timings(encoder);
+
+	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
+	gen11_dsi_configure_transcoder(encoder);
 }
 
 static void __attribute__((unused))
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 25e7396..e3225cd 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -81,6 +81,9 @@ struct intel_dsi {
 	u16 dcs_backlight_ports;
 	u16 dcs_cabc_ports;
 
+	/* RGB or BGR */
+	unsigned int bgr_enabled;
+
 	u8 pixel_overlap;
 	u32 port_bits;
 	u32 bw_timer;
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index a9a98a4..675701b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -542,6 +542,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 	intel_dsi->video_frmt_cfg_bits =
 		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
+	intel_dsi->bgr_enabled = mipi_config->rgb_flip;
 
 	pclk = mode->clock;
 
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 63+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev5)
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (12 preceding siblings ...)
  2018-07-10  9:40 ` [PATCH v5 13/13] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
@ 2018-07-10 10:46 ` Patchwork
  2018-07-10 10:51 ` ✗ Fi.CI.SPARSE: " Patchwork
                   ` (3 subsequent siblings)
  17 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2018-07-10 10:46 UTC (permalink / raw)
  To: Madhav Chauhan; +Cc: intel-gfx

== Series Details ==

Series: ICELAKE DSI DRIVER (rev5)
URL   : https://patchwork.freedesktop.org/series/44823/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
30f4f160de53 drm/i915/icl: Configure lane sequencing of combo phy transmitter
c677ebaee69e drm/i915/icl: DSI vswing programming sequence
-:33: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#33: FILE: drivers/gpu/drm/i915/icl_dsi.c:39:
+	for_each_dsi_port(port, intel_dsi->ports) {
+

total: 0 errors, 0 warnings, 1 checks, 132 lines checked
392c529052c6 drm/i915/icl: Enable DDI Buffer
e255c1a37c33 drm/i915/icl: Define T_INIT_MASTER registers
c76c29dcd686 drm/i915/icl: Program T_INIT_MASTER registers
5f50bd44df15 drm/i915/icl: Define data/clock lanes dphy timing registers
-:31: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#31: FILE: drivers/gpu/drm/i915/i915_reg.h:10089:
+#define  CLK_PREP_TIME(x)		(x << 28)

-:33: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#33: FILE: drivers/gpu/drm/i915/i915_reg.h:10091:
+#define  CLK_ZERO_TIME(x)		(x << 20)

-:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:10093:
+#define  CLK_PRE_TIME(x)		(x << 16)

-:37: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#37: FILE: drivers/gpu/drm/i915/i915_reg.h:10095:
+#define  CLK_POST_TIME(x)		(x << 8)

-:39: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#39: FILE: drivers/gpu/drm/i915/i915_reg.h:10097:
+#define  CLK_TRAIL_TIME(x)		(x << 0)

-:52: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#52: FILE: drivers/gpu/drm/i915/i915_reg.h:10110:
+#define  HS_PREP_TIME(x)		(x << 24)

-:54: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#54: FILE: drivers/gpu/drm/i915/i915_reg.h:10112:
+#define  HS_ZERO_TIME(x)		(x << 16)

-:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#56: FILE: drivers/gpu/drm/i915/i915_reg.h:10114:
+#define  HS_TRAIL_TIME(x)		(x << 8)

-:58: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#58: FILE: drivers/gpu/drm/i915/i915_reg.h:10116:
+#define  HS_EXIT_TIME(x)		(x << 0)

total: 0 errors, 0 warnings, 9 checks, 46 lines checked
647b5964795f drm/i915/icl: Program DSI clock and data lane timing params
-:80: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#80: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:631:
+	ths_prepare_ns = max(mipi_config->ths_prepare,
+				mipi_config->tclk_prepare);

-:114: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#114: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:655:
+		clk_zero_cnt = DIV_ROUND_UP(

-:128: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#128: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:669:
+		hs_zero_cnt = DIV_ROUND_UP(

-:190: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#190: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:727:
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
+							ui_num * mul);

-:196: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#196: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:731:
+			DRM_DEBUG_KMS("prepare count too high %u\n",
+								prepare_cnt);

-:201: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#201: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:736:
+		exit_zero_cnt = DIV_ROUND_UP(

-:226: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#226: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:748:
+		if (exit_zero_cnt < (55 * ui_den / ui_num) &&
+					(55 * ui_den) % ui_num)

-:231: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#231: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:753:
+			DRM_DEBUG_KMS("exit zero count too high %u\n",
+								exit_zero_cnt);

-:250: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#250: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:764:
+			DRM_DEBUG_KMS("clock zero count too high %u\n",
+								clk_zero_cnt);

total: 0 errors, 0 warnings, 9 checks, 293 lines checked
d6b44b4626d5 drm/i915/icl: Define TA_TIMING_PARAM registers
-:31: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#31: FILE: drivers/gpu/drm/i915/i915_reg.h:10129:
+#define  TA_SURE_TIME(x)		(x << 16)

total: 0 errors, 0 warnings, 1 checks, 20 lines checked
4140659db9be drm/i915/icl: Program TA_TIMING_PARAM registers
77e315ff7682 drm/i915/icl: Get DSI transcoder for a given port
-:20: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#20: FILE: drivers/gpu/drm/i915/icl_dsi.c:30:
+static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(

total: 0 errors, 0 warnings, 1 checks, 27 lines checked
2fa57a5edb01 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
0120accb0f10 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
-:26: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:10143:
+#define  OP_MODE(x)			(x << 28)

-:33: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#33: FILE: drivers/gpu/drm/i915/i915_reg.h:10150:
+#define  PIX_FMT(x)			(x << 16)

-:43: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#43: FILE: drivers/gpu/drm/i915/i915_reg.h:10160:
+#define  PIX_VIRT_CHAN(x)		(x << 12)

-:45: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#45: FILE: drivers/gpu/drm/i915/i915_reg.h:10162:
+#define  PIX_BUF_THRESHOLD(x)		((x & 0x3) << 10)

-:51: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#51: FILE: drivers/gpu/drm/i915/i915_reg.h:10168:
+#define  CONTINUOUS_CLK(x)		(x << 8)

-:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#56: FILE: drivers/gpu/drm/i915/i915_reg.h:10173:
+#define  LINK_CALIBRATION(x)		(x << 4)

-:61: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#61: FILE: drivers/gpu/drm/i915/i915_reg.h:10178:
+#define  S3D_ORIENTATION(x)		(x << 1)

total: 0 errors, 0 warnings, 7 checks, 53 lines checked
e04c020b5429 drm/i915/icl: Configure DSI transcoders
-:54: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#54: FILE: drivers/gpu/drm/i915/icl_dsi.c:356:
+			tmp |= LINK_CALIBRATION(

total: 0 errors, 0 warnings, 1 checks, 121 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* ✗ Fi.CI.SPARSE: warning for ICELAKE DSI DRIVER (rev5)
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (13 preceding siblings ...)
  2018-07-10 10:46 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev5) Patchwork
@ 2018-07-10 10:51 ` Patchwork
  2018-07-10 11:04 ` ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  17 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2018-07-10 10:51 UTC (permalink / raw)
  To: Madhav Chauhan; +Cc: intel-gfx

== Series Details ==

Series: ICELAKE DSI DRIVER (rev5)
URL   : https://patchwork.freedesktop.org/series/44823/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Configure lane sequencing of combo phy transmitter
Okay!

Commit: drm/i915/icl: DSI vswing programming sequence
Okay!

Commit: drm/i915/icl: Enable DDI Buffer
Okay!

Commit: drm/i915/icl: Define T_INIT_MASTER registers
Okay!

Commit: drm/i915/icl: Program T_INIT_MASTER registers
Okay!

Commit: drm/i915/icl: Define data/clock lanes dphy timing registers
Okay!

Commit: drm/i915/icl: Program DSI clock and data lane timing params
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:644:26: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:644:26: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:686:25: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:686:25: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:718:37: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:718:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:629:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:629:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:630:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:630:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:802:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:802:37: warning: expression using sizeof(void)

Commit: drm/i915/icl: Define TA_TIMING_PARAM registers
Okay!

Commit: drm/i915/icl: Program TA_TIMING_PARAM registers
Okay!

Commit: drm/i915/icl: Get DSI transcoder for a given port
Okay!

Commit: drm/i915/icl: Add macros for MMIO of DSI transcoder registers
Okay!

Commit: drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
Okay!

Commit: drm/i915/icl: Configure DSI transcoders
Okay!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* ✓ Fi.CI.BAT: success for ICELAKE DSI DRIVER (rev5)
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (14 preceding siblings ...)
  2018-07-10 10:51 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-07-10 11:04 ` Patchwork
  2018-07-10 16:28 ` ✓ Fi.CI.IGT: " Patchwork
  2018-09-11 19:35 ` [PATCH v5 00/13] ICELAKE DSI DRIVER Jani Nikula
  17 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2018-07-10 11:04 UTC (permalink / raw)
  To: Madhav Chauhan; +Cc: intel-gfx

== Series Details ==

Series: ICELAKE DSI DRIVER (rev5)
URL   : https://patchwork.freedesktop.org/series/44823/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4462 -> Patchwork_9603 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/44823/revisions/5/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9603 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s4-devices:
      fi-kbl-7500u:       PASS -> DMESG-WARN (fdo#105128, fdo#107139)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       PASS -> INCOMPLETE (fdo#103713)

    
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139


== Participating hosts (47 -> 40) ==

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-kbl-guc fi-ctg-p8600 


== Build changes ==

    * Linux: CI_DRM_4462 -> Patchwork_9603

  CI_DRM_4462: d4e71d9d380fd82c93708cc29704a011dc9948ae @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4544: 764160f214cd916ddb79408b9f28ac0ad2df40e0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9603: e04c020b54297b15e459bc86b3355202107738ea @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

e04c020b5429 drm/i915/icl: Configure DSI transcoders
0120accb0f10 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
2fa57a5edb01 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
77e315ff7682 drm/i915/icl: Get DSI transcoder for a given port
4140659db9be drm/i915/icl: Program TA_TIMING_PARAM registers
d6b44b4626d5 drm/i915/icl: Define TA_TIMING_PARAM registers
647b5964795f drm/i915/icl: Program DSI clock and data lane timing params
5f50bd44df15 drm/i915/icl: Define data/clock lanes dphy timing registers
c76c29dcd686 drm/i915/icl: Program T_INIT_MASTER registers
e255c1a37c33 drm/i915/icl: Define T_INIT_MASTER registers
392c529052c6 drm/i915/icl: Enable DDI Buffer
c677ebaee69e drm/i915/icl: DSI vswing programming sequence
30f4f160de53 drm/i915/icl: Configure lane sequencing of combo phy transmitter

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9603/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* ✓ Fi.CI.IGT: success for ICELAKE DSI DRIVER (rev5)
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (15 preceding siblings ...)
  2018-07-10 11:04 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-07-10 16:28 ` Patchwork
  2018-09-11 19:35 ` [PATCH v5 00/13] ICELAKE DSI DRIVER Jani Nikula
  17 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2018-07-10 16:28 UTC (permalink / raw)
  To: Madhav Chauhan; +Cc: intel-gfx

== Series Details ==

Series: ICELAKE DSI DRIVER (rev5)
URL   : https://patchwork.freedesktop.org/series/44823/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4462_full -> Patchwork_9603_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9603_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9603_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9603_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_schedule@deep-vebox:
      shard-kbl:          SKIP -> PASS +1

    
== Known issues ==

  Here are the changes found in Patchwork_9603_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_schedule@pi-ringfull-blt:
      shard-glk:          NOTRUN -> FAIL (fdo#103158)

    igt@gem_mmap_gtt@coherency:
      shard-glk:          NOTRUN -> FAIL (fdo#100587)

    igt@gem_ppgtt@blt-vs-render-ctx0:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665, fdo#106023)

    igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
      shard-glk:          PASS -> FAIL (fdo#105454, fdo#106509)

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-glk:          PASS -> FAIL (fdo#102887)

    igt@kms_flip_tiling@flip-to-x-tiled:
      shard-glk:          PASS -> FAIL (fdo#107161, fdo#103822)

    igt@kms_setmode@basic:
      shard-kbl:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
      shard-glk:          FAIL (fdo#105363) -> PASS

    igt@kms_flip_tiling@flip-to-y-tiled:
      shard-glk:          FAIL (fdo#107161, fdo#103822) -> PASS

    
  fdo#100587 https://bugs.freedesktop.org/show_bug.cgi?id=100587
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#107161 https://bugs.freedesktop.org/show_bug.cgi?id=107161
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4462 -> Patchwork_9603

  CI_DRM_4462: d4e71d9d380fd82c93708cc29704a011dc9948ae @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4544: 764160f214cd916ddb79408b9f28ac0ad2df40e0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9603: e04c020b54297b15e459bc86b3355202107738ea @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9603/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter
  2018-07-10  9:40 ` [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
@ 2018-07-19 16:11   ` Ville Syrjälä
  2018-07-19 18:35     ` Chauhan, Madhav
  2018-09-10 12:20   ` Lisovskiy, Stanislav
  1 sibling, 1 reply; 63+ messages in thread
From: Ville Syrjälä @ 2018-07-19 16:11 UTC (permalink / raw)
  To: Madhav Chauhan; +Cc: jani.nikula, intel-gfx, paulo.r.zanoni, rodrigo.vivi

On Tue, Jul 10, 2018 at 03:10:02PM +0530, Madhav Chauhan wrote:
> This patch set the loadgen select and latency optimization for
> aux and transmit lanes of combo phy transmitters. It will be
> used for MIPI DSI HS operations.
> 
> v2: Rebase
> 
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/icl_dsi.c | 38 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 13830e4..a571339 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
>  	}
>  }
>  
> +static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 tmp;
> +	int lane;

tmp/lane could be moved to into the loops.

Same in other patches.

> +
> +	/* Step 4b(i) set loadgen select for transmit and aux lanes */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> +		tmp &= ~LOADGEN_SELECT;
> +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> +		for (lane = 0; lane <= 3; lane++) {
> +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
> +			tmp &= ~LOADGEN_SELECT;
> +			if (lane != 2)
> +				tmp |= LOADGEN_SELECT;
> +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
> +		}
> +	}
> +
> +	/* Step 4b(ii) set latency optimization for transmit and aux lanes */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> +	}

An empty line here and there would make this a bit more legible.

Same in other patches.

> +}
> +
>  static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>  {
>  	/* step 4a: power up all lanes of the DDI used by DSI */
>  	gen11_dsi_power_up_lanes(encoder);
> +
> +	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
> +	gen11_dsi_config_phy_lanes_sequence(encoder);
>  }
>  
>  static void __attribute__((unused))
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 07/13] drm/i915/icl: Program DSI clock and data lane timing params
  2018-07-10  9:40 ` [PATCH v5 07/13] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
@ 2018-07-19 16:17   ` Ville Syrjälä
  0 siblings, 0 replies; 63+ messages in thread
From: Ville Syrjälä @ 2018-07-19 16:17 UTC (permalink / raw)
  To: Madhav Chauhan; +Cc: jani.nikula, intel-gfx, paulo.r.zanoni, rodrigo.vivi

On Tue, Jul 10, 2018 at 03:10:08PM +0530, Madhav Chauhan wrote:
> This patch programs D-PHY timing parameters for the
> clock and data lane (in escape clocks) of DSI
> controller (DSI port 0 and 1).
> These programmed timings would be used by DSI Controller
> to calculate link transition latencies of the data and
> clock lanes.
> 
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/icl_dsi.c       |  18 ++++
>  drivers/gpu/drm/i915/intel_dsi.h     |   3 +
>  drivers/gpu/drm/i915/intel_dsi_vbt.c | 200 +++++++++++++++++++++++++----------
>  3 files changed, 165 insertions(+), 56 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index bc27e34..832772d 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -284,6 +284,24 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>  		tmp |= intel_dsi->init_count;
>  		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
>  	}
> +
> +	/* Program DPHY clock lanes timings */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
> +
> +		/* shadow register inside display core */
> +		I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
> +	}
> +
> +	/* Program DPHY data lanes timings */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
> +			   intel_dsi->dphy_data_lane_reg);
> +
> +		/* shadow register inside display core */
> +		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
> +			   intel_dsi->dphy_data_lane_reg);
> +	}
>  }
>  
>  static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index ad7c1cb..9fd8526 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -85,6 +85,9 @@ struct intel_dsi {
>  	u32 port_bits;
>  	u32 bw_timer;
>  	u32 dphy_reg;
> +
> +	/* data lanes dphy timing */
> +	u32 dphy_data_lane_reg;
>  	u32 video_frmt_cfg_bits;
>  	u16 lp_byte_clk;
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index ac83d6b..428290d 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -509,7 +509,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  	u32 bpp;
>  	u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
>  	u32 ui_num, ui_den;
> -	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
> +	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt, hs_zero_cnt;
> +	u32 tclk_pre_cnt, tclk_post_cnt;
> +	u32 tclk_pre_ns, tclk_post_ns;
>  	u32 ths_prepare_ns, tclk_trail_ns;
>  	u32 tclk_prepare_clkzero, ths_prepare_hszero;
>  	u32 lp_to_hs_switch, hs_to_lp_switch;
> @@ -624,76 +626,157 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  
>  	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
>  	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
> -
> +	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> +	ths_prepare_ns = max(mipi_config->ths_prepare,
> +				mipi_config->tclk_prepare);
>  	/*
>  	 * B060
>  	 * LP byte clock = TLPX/ (8UI)
>  	 */
>  	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
>  
> -	/* DDR clock period = 2 * UI
> -	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> -	 * UI(nsec) = 10^6 / bitrate
> -	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> -	 * DDR clock count  = ns_value / DDR clock period
> -	 *
> +	/*
>  	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
>  	 * HS byte clock count for other platform in HS ddr clock count
>  	 */
>  	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
> -	ths_prepare_ns = max(mipi_config->ths_prepare,
> -			     mipi_config->tclk_prepare);
>  
> -	/* prepare count */
> -	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
> +	if (IS_ICELAKE(dev_priv)) {

I'd suggest extracting the icl vs. old things into separate functions.

> +		/*
> +		 * prepare cnt in escape clocks
> +		 * this field represents a hexadecimal value with a precision
> +		 * of 1.2 – i.e. the most significant bit is the integer
> +		 * and the least significant 2 bits are fraction bits.
> +		 * so, the field can represent a range of 0.25 to 1.75
> +		 */
> +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
> +
> +		/* clk zero count in escape clocks */
> +		clk_zero_cnt = DIV_ROUND_UP(
> +					(tclk_prepare_clkzero - ths_prepare_ns),
> +					tlpx_ns);
> +
> +		/* trail cnt in escape clocks*/
> +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
> +
> +		/* tclk pre/post count in escape clocks */
> +		tclk_post_ns = mipi_config->tclk_post;
> +		tclk_pre_ns = mipi_config->tclk_pre;
> +		tclk_pre_cnt = DIV_ROUND_UP(tclk_pre_ns, tlpx_ns);
> +		tclk_post_cnt = DIV_ROUND_UP(tclk_post_ns, tlpx_ns);
> +
> +		/* hs zero cnt in escape clocks */
> +		hs_zero_cnt = DIV_ROUND_UP(
> +					(ths_prepare_hszero - ths_prepare_ns),
> +					tlpx_ns);
> +
> +		/* hs exit zero cnt in escape clocks */
> +		exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
> +
> +		if (prepare_cnt > 0x7 ||
> +		    clk_zero_cnt > 0xF ||
> +		    tclk_pre_cnt > 0x3 ||
> +		    tclk_post_cnt > 0x7 ||
> +		    trail_cnt > 0x7 ||
> +		    hs_zero_cnt > 0xF ||
> +		    exit_zero_cnt > 0x7) {
> +			DRM_DEBUG_DRIVER("DPHY values crossing max limits,");
> +			DRM_DEBUG_DRIVER("restricting to max values\n");
> +		}

This doesn't match how we do it on the older platforms. Would be nice to
stick to a uniform apporoach across the board.

Maybe add some kind of small helper to make this stuff less repetitive:

void clamp_val(u32 *val, u32 limit, const char *name)
{
	if (*val <= limit)
		return;
	
	DEBUG("%s...\n", name, ...);
	*val = limit;
}

Could even mix in some cpp magic to stringify the name automagically.

> +
> +		prepare_cnt = (prepare_cnt > 0x7) ? 0x7 : prepare_cnt;
> +		clk_zero_cnt = (clk_zero_cnt > 0xF) ? 0xF : clk_zero_cnt;
> +		tclk_pre_cnt = (tclk_pre_cnt > 0x3) ? 0x3 : tclk_pre_cnt;
> +		tclk_post_cnt = (tclk_post_cnt > 0x7) ? 0x7 : tclk_post_cnt;
> +		trail_cnt = (trail_cnt > 0x7) ? 0x7 : trail_cnt;
> +		hs_zero_cnt = (hs_zero_cnt > 0xF) ? 0xF : hs_zero_cnt;
> +		exit_zero_cnt = (exit_zero_cnt > 0x7) ? 0x7 : exit_zero_cnt;
> +
> +		/* clock lane dphy timings */
> +		intel_dsi->dphy_reg |= (CLK_PREP_OVERRIDE |
> +					CLK_PREP_TIME(prepare_cnt) |
> +					CLK_ZERO_OVERRIDE |
> +					CLK_ZERO_TIME(clk_zero_cnt) |
> +					CLK_PRE_OVERRIDE |
> +					CLK_PRE_TIME(tclk_pre_cnt) |
> +					CLK_POST_OVERRIDE |
> +					CLK_POST_TIME(tclk_post_cnt) |
> +					CLK_TRAIL_OVERRIDE |
> +					CLK_TRAIL_TIME(trail_cnt));
> +
> +		/* data lanes dphy timings */
> +		intel_dsi->dphy_data_lane_reg = HS_PREP_OVERRIDE |
> +						HS_PREP_TIME(prepare_cnt) |
> +						HS_ZERO_OVERRIDE |
> +						HS_ZERO_TIME(hs_zero_cnt) |
> +						HS_TRAIL_OVERRIDE |
> +						HS_TRAIL_TIME(trail_cnt) |
> +						HS_EXIT_OVERRIDE |
> +						HS_EXIT_TIME(exit_zero_cnt);
> +	} else {
> +		/*
> +		 * DDR clock period = 2 * UI
> +		 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> +		 * UI(nsec) = 10^6 / bitrate
> +		 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> +		 * DDR clock count  = ns_value / DDR clock period
> +		 */
>  
> -	if (prepare_cnt > PREPARE_CNT_MAX) {
> -		DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
> -		prepare_cnt = PREPARE_CNT_MAX;
> -	}
> +		/* prepare count */
> +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
> +							ui_num * mul);
>  
> -	/* exit zero count */
> -	exit_zero_cnt = DIV_ROUND_UP(
> +		if (prepare_cnt > PREPARE_CNT_MAX) {
> +			DRM_DEBUG_KMS("prepare count too high %u\n",
> +								prepare_cnt);
> +			prepare_cnt = PREPARE_CNT_MAX;
> +		}
> +
> +		/* exit zero count */
> +		exit_zero_cnt = DIV_ROUND_UP(
>  				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
>  				ui_num * mul
>  				);
>  
> -	/*
> -	 * Exit zero is unified val ths_zero and ths_exit
> -	 * minimum value for ths_exit = 110ns
> -	 * min (exit_zero_cnt * 2) = 110/UI
> -	 * exit_zero_cnt = 55/UI
> -	 */
> -	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
> -		exit_zero_cnt += 1;
> -
> -	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
> -		DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
> -		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
> -	}
> +		/*
> +		 * Exit zero is unified val ths_zero and ths_exit
> +		 * minimum value for ths_exit = 110ns
> +		 * min (exit_zero_cnt * 2) = 110/UI
> +		 * exit_zero_cnt = 55/UI
> +		 */
> +		if (exit_zero_cnt < (55 * ui_den / ui_num) &&
> +					(55 * ui_den) % ui_num)
> +			exit_zero_cnt += 1;
> +
> +		if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
> +			DRM_DEBUG_KMS("exit zero count too high %u\n",
> +								exit_zero_cnt);
> +			exit_zero_cnt = EXIT_ZERO_CNT_MAX;
> +		}
>  
> -	/* clk zero count */
> -	clk_zero_cnt = DIV_ROUND_UP(
> -				(tclk_prepare_clkzero -	ths_prepare_ns)
> -				* ui_den, ui_num * mul);
> +		/* clk zero count */
> +		clk_zero_cnt = DIV_ROUND_UP((tclk_prepare_clkzero -
> +						ths_prepare_ns)
> +						* ui_den, ui_num * mul);
>  
> -	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
> -		DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
> -		clk_zero_cnt = CLK_ZERO_CNT_MAX;
> -	}
> +		if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
> +			DRM_DEBUG_KMS("clock zero count too high %u\n",
> +								clk_zero_cnt);
> +			clk_zero_cnt = CLK_ZERO_CNT_MAX;
> +		}
>  
> -	/* trail count */
> -	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> -	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
> +		/* trail cnt */
> +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
>  
> -	if (trail_cnt > TRAIL_CNT_MAX) {
> -		DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
> -		trail_cnt = TRAIL_CNT_MAX;
> -	}
> +		if (trail_cnt > TRAIL_CNT_MAX) {
> +			DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
> +			trail_cnt = TRAIL_CNT_MAX;
> +		}
>  
> -	/* B080 */
> -	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
> +		/* B080 */
> +		intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
>  						clk_zero_cnt << 8 | prepare_cnt;
> +	}
>  
>  	/*
>  	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
> @@ -707,9 +790,10 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  	 */
>  	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
>  
> -	/* B044 */
> -	/* FIXME:
> -	 * The comment above does not match with the code */
> +	/*
> +	 * B044
> +	 * FIXME: comment above does not match with the code
> +	 */

Unrelated changes.

>  	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
>  						exit_zero_cnt * mul + 10, 8);
>  
> @@ -718,8 +802,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
>  	intel_dsi->hs_to_lp_count += extra_byte_count;
>  
> -	/* B088 */
> -	/* LP -> HS for clock lanes
> +	/*
> +	 * B088
> +	 * LP -> HS for clock lanes
>  	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
>  	 *						extra byte count
>  	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
> @@ -735,7 +820,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  
>  	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
>  
> -	/* HS->LP for Clock Lanes
> +	/*
> +	 * HS->LP for Clock Lanes
>  	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
>  	 *						Extra byte count
>  	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
> @@ -782,9 +868,11 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  	DRM_DEBUG_KMS("BTA %s\n",
>  			enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
>  
> -	/* delays in VBT are in unit of 100us, so need to convert
> +	/*
> +	 * delays in VBT are in unit of 100us, so need to convert
>  	 * here in ms
> -	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
> +	 * Delay (100us) * 100 /1000 = Delay / 10 (ms)
> +	 */
>  	intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
>  	intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
>  	intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 09/13] drm/i915/icl: Program TA_TIMING_PARAM registers
  2018-07-10  9:40 ` [PATCH v5 09/13] drm/i915/icl: Program " Madhav Chauhan
@ 2018-07-19 16:21   ` Ville Syrjälä
  2018-07-20  8:08     ` Chauhan, Madhav
  0 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjälä @ 2018-07-19 16:21 UTC (permalink / raw)
  To: Madhav Chauhan; +Cc: jani.nikula, intel-gfx, paulo.r.zanoni, rodrigo.vivi

On Tue, Jul 10, 2018 at 03:10:10PM +0530, Madhav Chauhan wrote:
> This patch programs D-PHY timing parameters for the
> bus turn around flow(in escape clocks) only if dsi link
> frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
> identical register DSI_TA_TIMING_PARAM (inside DSI
> Controller within the Display Core).
> 
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/icl_dsi.c       | 21 +++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dsi.h     |  1 +
>  drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
>  3 files changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 832772d..8fd5284 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -302,6 +302,27 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>  		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
>  			   intel_dsi->dphy_data_lane_reg);
>  	}
> +
> +	/*
> +	 * If DSI link operating at or below an 800 MHz,
> +	 * TA_SURE should be override and programmed to
> +	 * a value '0' inside TA_PARAM_REGISTERS otherwise
> +	 * leave all fields at HW default values.
> +	 */
> +	if (intel_dsi->bitrate_khz <= KHz(800)) {

The KHz(800) confuses me. My brain thinks this value is 800 kHz when
it's not. So I'd write it without the KHz() macro.

> +		for_each_dsi_port(port, intel_dsi->ports) {
> +			tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
> +			tmp &= ~TA_SURE_TIME_MASK;
> +			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
> +			I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
> +
> +			/* shadow register inside display core */
> +			tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
> +			tmp &= ~TA_SURE_TIME_MASK;
> +			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
> +			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
> +		}
> +	}
>  }
>  
>  static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 9fd8526..25e7396 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -101,6 +101,7 @@ struct intel_dsi {
>  
>  	u16 init_count;
>  	u32 pclk;
> +	u32 bitrate_khz;
>  	u16 burst_mode_ratio;
>  
>  	/* all delays in ms */
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 428290d..a9a98a4 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -589,6 +589,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  	intel_dsi->pclk = pclk;
>  
>  	bitrate = (pclk * bpp) / intel_dsi->lane_count;
> +	intel_dsi->bitrate_khz = bitrate;
>  
>  	switch (intel_dsi->escape_clk_div) {
>  	case 0:
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  2018-07-10  9:40 ` [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
@ 2018-07-19 16:22   ` Ville Syrjälä
  2018-07-20  8:55     ` Chauhan, Madhav
  2018-09-12  9:36     ` Madhav Chauhan
  0 siblings, 2 replies; 63+ messages in thread
From: Ville Syrjälä @ 2018-07-19 16:22 UTC (permalink / raw)
  To: Madhav Chauhan; +Cc: jani.nikula, intel-gfx, paulo.r.zanoni, rodrigo.vivi

On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
> This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
> DSI transcoder registers.
> 
> Credits-to: Jani N
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1d13ba9..62bc76e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9576,6 +9576,11 @@ enum skl_power_gate {
>  #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
>  #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
>  
> +/* gen11 DSI */
> +#define _DSI_TRANS(tc, dsi0, dsi1)	(((tc) == TRANSCODER_DSI_0) ?	\
> +					 (dsi0) : (dsi1))

_PIPE() etc. should result in slughtly better code IIRC.

> +#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO(_DSI_TRANS(tc, dsi0, dsi1))
> +
>  #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
>  #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
>  #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter
  2018-07-19 16:11   ` Ville Syrjälä
@ 2018-07-19 18:35     ` Chauhan, Madhav
  2018-07-27 11:57       ` Chauhan, Madhav
  0 siblings, 1 reply; 63+ messages in thread
From: Chauhan, Madhav @ 2018-07-19 18:35 UTC (permalink / raw)
  To: Ville Syrjälä
  Cc: Nikula, Jani, intel-gfx, Zanoni, Paulo R, Vivi, Rodrigo

> -----Original Message-----
> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
> Sent: Thursday, July 19, 2018 9:42 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> Zanoni, Paulo R <paulo.r.zanoni@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v5 01/13] drm/i915/icl: Configure lane
> sequencing of combo phy transmitter
> 
> On Tue, Jul 10, 2018 at 03:10:02PM +0530, Madhav Chauhan wrote:
> > This patch set the loadgen select and latency optimization for aux and
> > transmit lanes of combo phy transmitters. It will be used for MIPI DSI
> > HS operations.

Thanks for reviewing DSI patches.

> >
> > v2: Rebase
> >
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/icl_dsi.c | 38
> > ++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 38 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> > b/drivers/gpu/drm/i915/icl_dsi.c index 13830e4..a571339 100644
> > --- a/drivers/gpu/drm/i915/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/icl_dsi.c
> > @@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct
> intel_encoder *encoder)
> >  	}
> >  }
> >
> > +static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder
> > +*encoder) {
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > +	enum port port;
> > +	u32 tmp;
> > +	int lane;
> 
> tmp/lane could be moved to into the loops.
> 
> Same in other patches.

Agree, make sense.

> 
> > +
> > +	/* Step 4b(i) set loadgen select for transmit and aux lanes */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> > +		tmp &= ~LOADGEN_SELECT;
> > +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> > +		for (lane = 0; lane <= 3; lane++) {
> > +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port,
> lane));
> > +			tmp &= ~LOADGEN_SELECT;
> > +			if (lane != 2)
> > +				tmp |= LOADGEN_SELECT;
> > +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane),
> tmp);
> > +		}
> > +	}
> > +
> > +	/* Step 4b(ii) set latency optimization for transmit and aux lanes */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> > +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> > +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> > +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> > +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> > +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> > +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> > +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> > +	}
> 
> An empty line here and there would make this a bit more legible.
> 
> Same in other patches.

Ok.  Thought this will be additional line, multiple
Places in code use this :)

Regards,
Madhav

> 
> > +}
> > +
> >  static void gen11_dsi_enable_port_and_phy(struct intel_encoder
> > *encoder)  {
> >  	/* step 4a: power up all lanes of the DDI used by DSI */
> >  	gen11_dsi_power_up_lanes(encoder);
> > +
> > +	/* step 4b: configure lane sequencing of the Combo-PHY transmitters
> */
> > +	gen11_dsi_config_phy_lanes_sequence(encoder);
> >  }
> >
> >  static void __attribute__((unused))
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 09/13] drm/i915/icl: Program TA_TIMING_PARAM registers
  2018-07-19 16:21   ` Ville Syrjälä
@ 2018-07-20  8:08     ` Chauhan, Madhav
  2018-09-11 19:26       ` Jani Nikula
  0 siblings, 1 reply; 63+ messages in thread
From: Chauhan, Madhav @ 2018-07-20  8:08 UTC (permalink / raw)
  To: Ville Syrjälä
  Cc: Nikula, Jani, intel-gfx, Zanoni, Paulo R, Vivi, Rodrigo

> -----Original Message-----
> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
> Sent: Thursday, July 19, 2018 9:51 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> Zanoni, Paulo R <paulo.r.zanoni@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v5 09/13] drm/i915/icl: Program
> TA_TIMING_PARAM registers
> 
> On Tue, Jul 10, 2018 at 03:10:10PM +0530, Madhav Chauhan wrote:
> > This patch programs D-PHY timing parameters for the bus turn around
> > flow(in escape clocks) only if dsi link frequency <=800 MHz using
> > DPHY_TA_TIMING_PARAM and its identical register
> DSI_TA_TIMING_PARAM
> > (inside DSI Controller within the Display Core).
> >
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/icl_dsi.c       | 21 +++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_dsi.h     |  1 +
> >  drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
> >  3 files changed, 23 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> > b/drivers/gpu/drm/i915/icl_dsi.c index 832772d..8fd5284 100644
> > --- a/drivers/gpu/drm/i915/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/icl_dsi.c
> > @@ -302,6 +302,27 @@ static void gen11_dsi_setup_dphy_timings(struct
> intel_encoder *encoder)
> >  		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
> >  			   intel_dsi->dphy_data_lane_reg);
> >  	}
> > +
> > +	/*
> > +	 * If DSI link operating at or below an 800 MHz,
> > +	 * TA_SURE should be override and programmed to
> > +	 * a value '0' inside TA_PARAM_REGISTERS otherwise
> > +	 * leave all fields at HW default values.
> > +	 */
> > +	if (intel_dsi->bitrate_khz <= KHz(800)) {
> 
> The KHz(800) confuses me. My brain thinks this value is 800 kHz when it's
> not. So I'd write it without the KHz() macro.

Ok. Initially I wrote without using KHz macro, but got comment to use KHz macro :)

Regards,
Madhav

> 
> > +		for_each_dsi_port(port, intel_dsi->ports) {
> > +			tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
> > +			tmp &= ~TA_SURE_TIME_MASK;
> > +			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
> > +			I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
> > +
> > +			/* shadow register inside display core */
> > +			tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
> > +			tmp &= ~TA_SURE_TIME_MASK;
> > +			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
> > +			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
> > +		}
> > +	}
> >  }
> >
> >  static void gen11_dsi_enable_port_and_phy(struct intel_encoder
> > *encoder) diff --git a/drivers/gpu/drm/i915/intel_dsi.h
> > b/drivers/gpu/drm/i915/intel_dsi.h
> > index 9fd8526..25e7396 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.h
> > +++ b/drivers/gpu/drm/i915/intel_dsi.h
> > @@ -101,6 +101,7 @@ struct intel_dsi {
> >
> >  	u16 init_count;
> >  	u32 pclk;
> > +	u32 bitrate_khz;
> >  	u16 burst_mode_ratio;
> >
> >  	/* all delays in ms */
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> > b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> > index 428290d..a9a98a4 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> > @@ -589,6 +589,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi,
> u16 panel_id)
> >  	intel_dsi->pclk = pclk;
> >
> >  	bitrate = (pclk * bpp) / intel_dsi->lane_count;
> > +	intel_dsi->bitrate_khz = bitrate;
> >
> >  	switch (intel_dsi->escape_clk_div) {
> >  	case 0:
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  2018-07-19 16:22   ` Ville Syrjälä
@ 2018-07-20  8:55     ` Chauhan, Madhav
  2018-09-12  9:36     ` Madhav Chauhan
  1 sibling, 0 replies; 63+ messages in thread
From: Chauhan, Madhav @ 2018-07-20  8:55 UTC (permalink / raw)
  To: Ville Syrjälä
  Cc: Nikula, Jani, intel-gfx, Zanoni, Paulo R, Vivi, Rodrigo

> -----Original Message-----
> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
> Sent: Thursday, July 19, 2018 9:53 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> Zanoni, Paulo R <paulo.r.zanoni@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO
> of DSI transcoder registers
> 
> On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
> > This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing DSI
> > transcoder registers.
> >
> > Credits-to: Jani N
> >
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 1d13ba9..62bc76e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9576,6 +9576,11 @@ enum skl_power_gate {
> >  #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/*
> ports A and C only */
> >  #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
> >
> > +/* gen11 DSI */
> > +#define _DSI_TRANS(tc, dsi0, dsi1)	(((tc) == TRANSCODER_DSI_0) ?	\
> > +					 (dsi0) : (dsi1))
> 
> _PIPE() etc. should result in slughtly better code IIRC.

Are you suggesting to use following, please clarify??
#define _DSI_TRANS(tc, dsi0, dsi1)  _PIPE(tc, dsi0, dsi1)

Regards,
Madhav

> 
> > +#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO(_DSI_TRANS(tc, dsi0, dsi1))
> > +
> >  #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
> >  #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
> >  #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter
  2018-07-19 18:35     ` Chauhan, Madhav
@ 2018-07-27 11:57       ` Chauhan, Madhav
  2018-09-11 17:46         ` Jani Nikula
  0 siblings, 1 reply; 63+ messages in thread
From: Chauhan, Madhav @ 2018-07-27 11:57 UTC (permalink / raw)
  To: 'Ville Syrjälä'
  Cc: Nikula, Jani, 'intel-gfx@lists.freedesktop.org',
	Zanoni, Paulo R, Vivi, Rodrigo

> -----Original Message-----
> From: Chauhan, Madhav
> Sent: Friday, July 20, 2018 12:06 AM
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> Zanoni, Paulo R <paulo.r.zanoni@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>
> Subject: RE: [Intel-gfx] [PATCH v5 01/13] drm/i915/icl: Configure lane
> sequencing of combo phy transmitter
> 
> > -----Original Message-----
> > From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
> > Sent: Thursday, July 19, 2018 9:42 PM
> > To: Chauhan, Madhav <madhav.chauhan@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> > <jani.nikula@intel.com>; Zanoni, Paulo R <paulo.r.zanoni@intel.com>;
> > Vivi, Rodrigo <rodrigo.vivi@intel.com>
> > Subject: Re: [Intel-gfx] [PATCH v5 01/13] drm/i915/icl: Configure lane
> > sequencing of combo phy transmitter
> >
> > On Tue, Jul 10, 2018 at 03:10:02PM +0530, Madhav Chauhan wrote:
> > > This patch set the loadgen select and latency optimization for aux
> > > and transmit lanes of combo phy transmitters. It will be used for
> > > MIPI DSI HS operations.
> 
> Thanks for reviewing DSI patches.
> 
> > >
> > > v2: Rebase
> > >
> > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/icl_dsi.c | 38
> > > ++++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 38 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> > > b/drivers/gpu/drm/i915/icl_dsi.c index 13830e4..a571339 100644
> > > --- a/drivers/gpu/drm/i915/icl_dsi.c
> > > +++ b/drivers/gpu/drm/i915/icl_dsi.c
> > > @@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct
> > intel_encoder *encoder)
> > >  	}
> > >  }
> > >
> > > +static void gen11_dsi_config_phy_lanes_sequence(struct
> > > +intel_encoder
> > > +*encoder) {
> > > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > > +	enum port port;
> > > +	u32 tmp;
> > > +	int lane;
> >
> > tmp/lane could be moved to into the loops.

Was it due to intel_dsi->ports have no port assigned and
loop for_each_dsi_port() will not proceed further??
If that's the case, these encoder enable/disable function should be called
Only when dsi_init is success and then, intel_dsi->ports have some valid port value.

Please clarify.

Regards,
Madhav

> >
> > Same in other patches.
> 
> Agree, make sense.

Just to understand 
> 
> >
> > > +
> > > +	/* Step 4b(i) set loadgen select for transmit and aux lanes */
> > > +	for_each_dsi_port(port, intel_dsi->ports) {
> > > +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> > > +		tmp &= ~LOADGEN_SELECT;
> > > +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> > > +		for (lane = 0; lane <= 3; lane++) {
> > > +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port,
> > lane));
> > > +			tmp &= ~LOADGEN_SELECT;
> > > +			if (lane != 2)
> > > +				tmp |= LOADGEN_SELECT;
> > > +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane),
> > tmp);
> > > +		}
> > > +	}
> > > +
> > > +	/* Step 4b(ii) set latency optimization for transmit and aux lanes */
> > > +	for_each_dsi_port(port, intel_dsi->ports) {
> > > +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> > > +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> > > +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> > > +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> > > +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> > > +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> > > +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> > > +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> > > +	}
> >
> > An empty line here and there would make this a bit more legible.
> >
> > Same in other patches.
> 
> Ok.  Thought this will be additional line, multiple Places in code use this :)
> 
> Regards,
> Madhav
> 
> >
> > > +}
> > > +
> > >  static void gen11_dsi_enable_port_and_phy(struct intel_encoder
> > > *encoder)  {
> > >  	/* step 4a: power up all lanes of the DDI used by DSI */
> > >  	gen11_dsi_power_up_lanes(encoder);
> > > +
> > > +	/* step 4b: configure lane sequencing of the Combo-PHY
> > > +transmitters
> > */
> > > +	gen11_dsi_config_phy_lanes_sequence(encoder);
> > >  }
> > >
> > >  static void __attribute__((unused))
> > > --
> > > 2.7.4
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [v5, 02/13] drm/i915/icl: DSI vswing programming sequence
  2018-07-10  9:40 ` [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
@ 2018-09-06 14:01   ` Kulkarni, Vandita
  2018-09-10  7:43     ` Madhav Chauhan
  2018-09-11 18:50   ` [PATCH v5 " Jani Nikula
  1 sibling, 1 reply; 63+ messages in thread
From: Kulkarni, Vandita @ 2018-09-06 14:01 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi


[-- Attachment #1.1: Type: text/plain, Size: 5757 bytes --]



On 7/10/2018 3:10 PM, Madhav Chauhan wrote:
> This patch setup voltage swing before enabling
> combo PHY DDI (shared with DSI).
> Note that DSI voltage swing programming is for
> high speed data buffers. HW automatically handles
> the voltage swing for the low power data buffers.
>
> v2: Rebase
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>   drivers/gpu/drm/i915/icl_dsi.c | 114 +++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 114 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index a571339..dc16c1f 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -27,6 +27,65 @@
>   
>   #include "intel_dsi.h"
>   
> +static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 tmp;
> +	int lane;
> +
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +
> +		/* Bspec: set scaling mode to 0x6 */
> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> +		tmp |= SCALING_MODE_SEL(6);
> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> +		tmp |= SCALING_MODE_SEL(6);
> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> +
> +		/*
> +		 * swing and scaling values are taken from DSI
> +		 * table under vswing programming sequence for
> +		 * combo phy ddi in BSPEC.
> +		 * program swing values
> +		 */
> +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> +		tmp |= SWING_SEL_UPPER(0x2);
> +		tmp |= SWING_SEL_LOWER(0x2);
> +		tmp |= RCOMP_SCALAR(0x98);
> +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> +		tmp |= SWING_SEL_UPPER(0x2);
> +		tmp |= SWING_SEL_LOWER(0x2);
> +		tmp |= RCOMP_SCALAR(0x98);
> +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> +
> +		/* program scaling values */
> +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> +		tmp |= POST_CURSOR_1(0x0);
> +		tmp |= POST_CURSOR_2(0x0);
> +		tmp |= CURSOR_COEFF(0x18);
> +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> +
> +		for (lane = 0; lane <= 3; lane++) {
> +			/* Bspec: must not use GRP register for write */
> +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
> +			tmp |= POST_CURSOR_1(0x0);
> +			tmp |= POST_CURSOR_2(0x0);
> +			tmp |= CURSOR_COEFF(0x18);
> +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
> +		}
> +	}
> +}
> +
>   static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
>   {
>   	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -140,6 +199,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>   	}
>   }
>   

I see from the bspec that except for the Loadgen Select and Latency 
Optimization all other DDI buffer programming can be taken from the DDI 
Buffer section.

Can we use this function "icl_ddi_combo_vswing_program" function which 
is already there
patch for reference:
https://patchwork.freedesktop.org/patch/213515/

Thanks,
Vandita

> +static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	u32 tmp;
> +	enum port port;
> +
> +	/* Step C.1:clear common keeper enable bit */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
> +		tmp &= ~COMMON_KEEPER_EN;
> +		I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
> +		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
> +		tmp &= ~COMMON_KEEPER_EN;
> +		I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
> +	}
> +
> +	/*
> +	 * Step C.3: Set SUS Clock Config bitfield to 11b
> +	 * Note: Step C.2 (loadgen select program) is done
> +	 * as part of lane phy sequence configuration
> +	 */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_PORT_CL_DW5(port));
> +		tmp |= SUS_CLOCK_CONFIG;
> +		I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
> +	}
> +
> +	/* Step C.4: Clear training enable to change swing values */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> +		tmp &= ~TX_TRAINING_EN;
> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> +		tmp &= ~TX_TRAINING_EN;
> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> +	}
> +
> +	/* Step C.5: Program swing and de-emphasis */
> +	dsi_program_swing_and_deemphasis(encoder);
> +
> +	/* Step: C.6: Set training enable to trigger update */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> +		tmp |= TX_TRAINING_EN;
> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> +		tmp |= TX_TRAINING_EN;
> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> +	}
> +}
> +
>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>   {
>   	/* step 4a: power up all lanes of the DDI used by DSI */
> @@ -147,6 +258,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>   
>   	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
>   	gen11_dsi_config_phy_lanes_sequence(encoder);
> +
> +	/* step 4c: configure voltage swing and skew */
> +	gen11_dsi_voltage_swing_program_seq(encoder);
>   }
>   
>   static void __attribute__((unused))


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^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [v5, 02/13] drm/i915/icl: DSI vswing programming sequence
  2018-09-06 14:01   ` [v5, " Kulkarni, Vandita
@ 2018-09-10  7:43     ` Madhav Chauhan
  2018-09-11 18:16       ` Jani Nikula
  0 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-10  7:43 UTC (permalink / raw)
  To: Kulkarni, Vandita, intel-gfx; +Cc: jani.nikula, paulo.r.zanoni, rodrigo.vivi

On 9/6/2018 7:31 PM, Kulkarni, Vandita wrote:
>
>
>
> On 7/10/2018 3:10 PM, Madhav Chauhan wrote:
>> This patch setup voltage swing before enabling
>> combo PHY DDI (shared with DSI).
>> Note that DSI voltage swing programming is for
>> high speed data buffers. HW automatically handles
>> the voltage swing for the low power data buffers.
>>
>> v2: Rebase
>>
>> Signed-off-by: Madhav Chauhan<madhav.chauhan@intel.com>
>> ---
>>   drivers/gpu/drm/i915/icl_dsi.c | 114 +++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 114 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> index a571339..dc16c1f 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -27,6 +27,65 @@
>>   
>>   #include "intel_dsi.h"
>>   
>> +static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> +	enum port port;
>> +	u32 tmp;
>> +	int lane;
>> +
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +
>> +		/* Bspec: set scaling mode to 0x6 */
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>> +		tmp |= SCALING_MODE_SEL(6);
>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>> +		tmp |= SCALING_MODE_SEL(6);
>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>> +
>> +		/*
>> +		 * swing and scaling values are taken from DSI
>> +		 * table under vswing programming sequence for
>> +		 * combo phy ddi in BSPEC.
>> +		 * program swing values
>> +		 */
>> +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>> +		tmp |= SWING_SEL_UPPER(0x2);
>> +		tmp |= SWING_SEL_LOWER(0x2);
>> +		tmp |= RCOMP_SCALAR(0x98);
>> +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
>> +		tmp |= SWING_SEL_UPPER(0x2);
>> +		tmp |= SWING_SEL_LOWER(0x2);
>> +		tmp |= RCOMP_SCALAR(0x98);
>> +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
>> +
>> +		/* program scaling values */
>> +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
>> +		tmp |= POST_CURSOR_1(0x0);
>> +		tmp |= POST_CURSOR_2(0x0);
>> +		tmp |= CURSOR_COEFF(0x18);
>> +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
>> +
>> +		for (lane = 0; lane <= 3; lane++) {
>> +			/* Bspec: must not use GRP register for write */
>> +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
>> +			tmp |= POST_CURSOR_1(0x0);
>> +			tmp |= POST_CURSOR_2(0x0);
>> +			tmp |= CURSOR_COEFF(0x18);
>> +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
>> +		}
>> +	}
>> +}
>> +
>>   static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
>>   {
>>   	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> @@ -140,6 +199,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>>   	}
>>   }
>>   
>
> I see from the bspec that except for the Loadgen Select and Latency 
> Optimization all other DDI buffer programming can be taken from the 
> DDI Buffer section.
>
> Can we use this function "icl_ddi_combo_vswing_program" function which 
> is already there
> patch for reference:
> https://patchwork.freedesktop.org/patch/213515/
>

We can't directly use that implementation. Reasons:
1. For DSI we use AUX register as well to write which is not the case 
for DDI. We need to add multiple INTEL_OUTPUT_DSI
checks .
2. DSI specific icl_combo_phy_ddi_buf_trans not added in intel_ddi.c 
which will be used while doing vswing programming
3. intel_ddi_dp_level doesn't support "level" calculation for DSI.

Also in past we had similar discussion (with Jani N) to keep DSI 
specific entries/code in DSI encoder.

Jani N whats the suggestion here??

Regards,
Madhav

>
> Thanks,
> Vandita
>
>> +static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> +	u32 tmp;
>> +	enum port port;
>> +
>> +	/* Step C.1:clear common keeper enable bit */
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
>> +		tmp &= ~COMMON_KEEPER_EN;
>> +		I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
>> +		tmp &= ~COMMON_KEEPER_EN;
>> +		I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
>> +	}
>> +
>> +	/*
>> +	 * Step C.3: Set SUS Clock Config bitfield to 11b
>> +	 * Note: Step C.2 (loadgen select program) is done
>> +	 * as part of lane phy sequence configuration
>> +	 */
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		tmp = I915_READ(ICL_PORT_CL_DW5(port));
>> +		tmp |= SUS_CLOCK_CONFIG;
>> +		I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
>> +	}
>> +
>> +	/* Step C.4: Clear training enable to change swing values */
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>> +		tmp &= ~TX_TRAINING_EN;
>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>> +		tmp &= ~TX_TRAINING_EN;
>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>> +	}
>> +
>> +	/* Step C.5: Program swing and de-emphasis */
>> +	dsi_program_swing_and_deemphasis(encoder);
>> +
>> +	/* Step: C.6: Set training enable to trigger update */
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>> +		tmp |= TX_TRAINING_EN;
>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>> +		tmp |= TX_TRAINING_EN;
>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>> +	}
>> +}
>> +
>>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>   {
>>   	/* step 4a: power up all lanes of the DDI used by DSI */
>> @@ -147,6 +258,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>   
>>   	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
>>   	gen11_dsi_config_phy_lanes_sequence(encoder);
>> +
>> +	/* step 4c: configure voltage swing and skew */
>> +	gen11_dsi_voltage_swing_program_seq(encoder);
>>   }
>>   
>>   static void __attribute__((unused))
>

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^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter
  2018-07-10  9:40 ` [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
  2018-07-19 16:11   ` Ville Syrjälä
@ 2018-09-10 12:20   ` Lisovskiy, Stanislav
  2018-09-10 15:27     ` Madhav Chauhan
  1 sibling, 1 reply; 63+ messages in thread
From: Lisovskiy, Stanislav @ 2018-09-10 12:20 UTC (permalink / raw)
  To: intel-gfx, Chauhan, Madhav; +Cc: Nikula, Jani, Zanoni, Paulo R, Vivi, Rodrigo

On Tue, 2018-07-10 at 15:10 +0530, Madhav Chauhan wrote:
> This patch set the loadgen select and latency optimization for
> aux and transmit lanes of combo phy transmitters. It will be
> used for MIPI DSI HS operations.
> 
> v2: Rebase
> 
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/icl_dsi.c | 38
> ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> b/drivers/gpu/drm/i915/icl_dsi.c
> index 13830e4..a571339 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct
> intel_encoder *encoder)
>  	}
>  }
>  
> +static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder
> *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder-
> >base);
> +	enum port port;
> +	u32 tmp;
> +	int lane;
> +
> +	/* Step 4b(i) set loadgen select for transmit and aux lanes
> */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> +		tmp &= ~LOADGEN_SELECT;
> +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> +		for (lane = 0; lane <= 3; lane++) {
> +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port,
> lane));
> +			tmp &= ~LOADGEN_SELECT;
> +			if (lane != 2)
> +				tmp |= LOADGEN_SELECT;
> +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane),
> tmp);
> +		}
> +	}
> +
> +	/* Step 4b(ii) set latency optimization for transmit and aux
> lanes */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> +	}
> +}
> 

I think bspec states that latency optimization should be set only for
Transmit lanes 0, 1, 3. Is it fine to use a group access(i.e
ICL_PORT_TX_DW2_GRP) here? I think it states also that no latency
optimization is needed for the clock lane.

-- 
Best Regards,

Lisovskiy Stanislav
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^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter
  2018-09-10 12:20   ` Lisovskiy, Stanislav
@ 2018-09-10 15:27     ` Madhav Chauhan
  2018-09-11  8:08       ` Lisovskiy, Stanislav
  0 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-10 15:27 UTC (permalink / raw)
  To: Lisovskiy, Stanislav, intel-gfx
  Cc: Nikula, Jani, Zanoni, Paulo R, Vivi, Rodrigo

On 9/10/2018 5:50 PM, Lisovskiy, Stanislav wrote:
> On Tue, 2018-07-10 at 15:10 +0530, Madhav Chauhan wrote:
>> This patch set the loadgen select and latency optimization for
>> aux and transmit lanes of combo phy transmitters. It will be
>> used for MIPI DSI HS operations.
>>
>> v2: Rebase
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> ---
>>   drivers/gpu/drm/i915/icl_dsi.c | 38
>> ++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 38 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>> b/drivers/gpu/drm/i915/icl_dsi.c
>> index 13830e4..a571339 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct
>> intel_encoder *encoder)
>>   	}
>>   }
>>   
>> +static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder
>> *encoder)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(encoder-
>>> base.dev);
>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder-
>>> base);
>> +	enum port port;
>> +	u32 tmp;
>> +	int lane;
>> +
>> +	/* Step 4b(i) set loadgen select for transmit and aux lanes
>> */
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
>> +		tmp &= ~LOADGEN_SELECT;
>> +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
>> +		for (lane = 0; lane <= 3; lane++) {
>> +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port,
>> lane));
>> +			tmp &= ~LOADGEN_SELECT;
>> +			if (lane != 2)
>> +				tmp |= LOADGEN_SELECT;
>> +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane),
>> tmp);
>> +		}
>> +	}
>> +
>> +	/* Step 4b(ii) set latency optimization for transmit and aux
>> lanes */
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
>> +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
>> +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
>> +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>> +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
>> +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
>> +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
>> +	}
>> +}
>>
> I think bspec states that latency optimization should be set only for
> Transmit lanes 0, 1, 3. Is it fine to use a group access(i.e
> ICL_PORT_TX_DW2_GRP) here? I think it states also that no latency
> optimization is needed for the clock lane.

There is a separate comment added in BSPEC :
"The Latency Optimization of the Clock Lane can be either left at it's 
default value ('h0)
or programmed to the same value as the other lanes. If programmed with 
the same
value as the other lanes,  then the Group access can be used for 
PORT_TX_DW2 programming"

Regards,
Madhav

>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter
  2018-09-10 15:27     ` Madhav Chauhan
@ 2018-09-11  8:08       ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 63+ messages in thread
From: Lisovskiy, Stanislav @ 2018-09-11  8:08 UTC (permalink / raw)
  To: intel-gfx, Chauhan, Madhav; +Cc: Nikula, Jani, Zanoni, Paulo R, Vivi, Rodrigo

On Mon, 2018-09-10 at 20:57 +0530, Madhav Chauhan wrote:
> On 9/10/2018 5:50 PM, Lisovskiy, Stanislav wrote:
> > On Tue, 2018-07-10 at 15:10 +0530, Madhav Chauhan wrote:
> > > This patch set the loadgen select and latency optimization for
> > > aux and transmit lanes of combo phy transmitters. It will be
> > > used for MIPI DSI HS operations.
> > > 
> > > v2: Rebase
> > > 
> > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/icl_dsi.c | 38
> > > ++++++++++++++++++++++++++++++++++++++
> > >   1 file changed, 38 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> > > b/drivers/gpu/drm/i915/icl_dsi.c
> > > index 13830e4..a571339 100644
> > > --- a/drivers/gpu/drm/i915/icl_dsi.c
> > > +++ b/drivers/gpu/drm/i915/icl_dsi.c
> > > @@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct
> > > intel_encoder *encoder)
> > >   	}
> > >   }
> > >   
> > > +static void gen11_dsi_config_phy_lanes_sequence(struct
> > > intel_encoder
> > > *encoder)
> > > +{
> > > +	struct drm_i915_private *dev_priv = to_i915(encoder-
> > > > base.dev);
> > > 
> > > +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder-
> > > > base);
> > > 
> > > +	enum port port;
> > > +	u32 tmp;
> > > +	int lane;
> > > +
> > > +	/* Step 4b(i) set loadgen select for transmit and aux
> > > lanes
> > > */
> > > +	for_each_dsi_port(port, intel_dsi->ports) {
> > > +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> > > +		tmp &= ~LOADGEN_SELECT;
> > > +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> > > +		for (lane = 0; lane <= 3; lane++) {
> > > +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port,
> > > lane));
> > > +			tmp &= ~LOADGEN_SELECT;
> > > +			if (lane != 2)
> > > +				tmp |= LOADGEN_SELECT;
> > > +			I915_WRITE(ICL_PORT_TX_DW4_LN(port,
> > > lane),
> > > tmp);
> > > +		}
> > > +	}
> > > +
> > > +	/* Step 4b(ii) set latency optimization for transmit and
> > > aux
> > > lanes */
> > > +	for_each_dsi_port(port, intel_dsi->ports) {
> > > +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> > > +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> > > +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> > > +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> > > +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> > > +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> > > +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> > > +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> > > +	}
> > > +}
> > > 
> > 
> > I think bspec states that latency optimization should be set only
> > for
> > Transmit lanes 0, 1, 3. Is it fine to use a group access(i.e
> > ICL_PORT_TX_DW2_GRP) here? I think it states also that no latency
> > optimization is needed for the clock lane.
> 
> There is a separate comment added in BSPEC :
> "The Latency Optimization of the Clock Lane can be either left at
> it's 
> default value ('h0)
> or programmed to the same value as the other lanes. If programmed
> with 
> the same
> value as the other lanes,  then the Group access can be used for 
> PORT_TX_DW2 programming"

Yep, I saw that, however just wasn't sure did they mean we actually
should leave it untouched. Is there actually any difference, if it is
programmed or not? If the value is discarded anyway, I guess it should
have been stated explicitly. Nevermind then.

> 
> Regards,
> Madhav
> 
> > 
> 
> 
-- 
Best Regards,

Lisovskiy Stanislav
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter
  2018-07-27 11:57       ` Chauhan, Madhav
@ 2018-09-11 17:46         ` Jani Nikula
  2018-09-12  6:32           ` Madhav Chauhan
  0 siblings, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2018-09-11 17:46 UTC (permalink / raw)
  To: Chauhan, Madhav, 'Ville Syrjälä'
  Cc: 'intel-gfx@lists.freedesktop.org',
	Zanoni, Paulo R, Vivi, Rodrigo

On Fri, 27 Jul 2018, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>> -----Original Message-----
>> From: Chauhan, Madhav
>> Sent: Friday, July 20, 2018 12:06 AM
>> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
>> Zanoni, Paulo R <paulo.r.zanoni@intel.com>; Vivi, Rodrigo
>> <rodrigo.vivi@intel.com>
>> Subject: RE: [Intel-gfx] [PATCH v5 01/13] drm/i915/icl: Configure lane
>> sequencing of combo phy transmitter
>> 
>> > -----Original Message-----
>> > From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>> > Sent: Thursday, July 19, 2018 9:42 PM
>> > To: Chauhan, Madhav <madhav.chauhan@intel.com>
>> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
>> > <jani.nikula@intel.com>; Zanoni, Paulo R <paulo.r.zanoni@intel.com>;
>> > Vivi, Rodrigo <rodrigo.vivi@intel.com>
>> > Subject: Re: [Intel-gfx] [PATCH v5 01/13] drm/i915/icl: Configure lane
>> > sequencing of combo phy transmitter
>> >
>> > On Tue, Jul 10, 2018 at 03:10:02PM +0530, Madhav Chauhan wrote:
>> > > This patch set the loadgen select and latency optimization for aux
>> > > and transmit lanes of combo phy transmitters. It will be used for
>> > > MIPI DSI HS operations.
>> 
>> Thanks for reviewing DSI patches.
>> 
>> > >
>> > > v2: Rebase
>> > >
>> > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> > > ---
>> > >  drivers/gpu/drm/i915/icl_dsi.c | 38
>> > > ++++++++++++++++++++++++++++++++++++++
>> > >  1 file changed, 38 insertions(+)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>> > > b/drivers/gpu/drm/i915/icl_dsi.c index 13830e4..a571339 100644
>> > > --- a/drivers/gpu/drm/i915/icl_dsi.c
>> > > +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> > > @@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct
>> > intel_encoder *encoder)
>> > >  	}
>> > >  }
>> > >
>> > > +static void gen11_dsi_config_phy_lanes_sequence(struct
>> > > +intel_encoder
>> > > +*encoder) {
>> > > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> > > +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> > > +	enum port port;
>> > > +	u32 tmp;
>> > > +	int lane;
>> >
>> > tmp/lane could be moved to into the loops.
>
> Was it due to intel_dsi->ports have no port assigned and
> loop for_each_dsi_port() will not proceed further??
> If that's the case, these encoder enable/disable function should be called
> Only when dsi_init is success and then, intel_dsi->ports have some valid port value.
>
> Please clarify.

Ville's comments are purely about style and readability.

>
> Regards,
> Madhav
>
>> >
>> > Same in other patches.
>> 
>> Agree, make sense.
>
> Just to understand 
>> 
>> >
>> > > +
>> > > +	/* Step 4b(i) set loadgen select for transmit and aux lanes */
>> > > +	for_each_dsi_port(port, intel_dsi->ports) {
>> > > +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
>> > > +		tmp &= ~LOADGEN_SELECT;
>> > > +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
>> > > +		for (lane = 0; lane <= 3; lane++) {
>> > > +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port,
>> > lane));
>> > > +			tmp &= ~LOADGEN_SELECT;
>> > > +			if (lane != 2)
>> > > +				tmp |= LOADGEN_SELECT;
>> > > +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane),
>> > tmp);
>> > > +		}
>> > > +	}
>> > > +
>> > > +	/* Step 4b(ii) set latency optimization for transmit and aux lanes */
>> > > +	for_each_dsi_port(port, intel_dsi->ports) {
>> > > +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
>> > > +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
>> > > +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
>> > > +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
>> > > +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>> > > +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
>> > > +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
>> > > +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);

The "read something, modify, write something else" pattern always gives
me the creeps. But I guess reading _GRP is not an option?

Anyway, for the actual content,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>> > > +	}
>> >
>> > An empty line here and there would make this a bit more legible.
>> >
>> > Same in other patches.
>> 
>> Ok.  Thought this will be additional line, multiple Places in code use this :)
>> 
>> Regards,
>> Madhav
>> 
>> >
>> > > +}
>> > > +
>> > >  static void gen11_dsi_enable_port_and_phy(struct intel_encoder
>> > > *encoder)  {
>> > >  	/* step 4a: power up all lanes of the DDI used by DSI */
>> > >  	gen11_dsi_power_up_lanes(encoder);
>> > > +
>> > > +	/* step 4b: configure lane sequencing of the Combo-PHY
>> > > +transmitters
>> > */
>> > > +	gen11_dsi_config_phy_lanes_sequence(encoder);
>> > >  }
>> > >
>> > >  static void __attribute__((unused))
>> > > --
>> > > 2.7.4
>> > >
>> > > _______________________________________________
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >
>> > --
>> > Ville Syrjälä
>> > Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [v5, 02/13] drm/i915/icl: DSI vswing programming sequence
  2018-09-10  7:43     ` Madhav Chauhan
@ 2018-09-11 18:16       ` Jani Nikula
  2018-09-12  6:34         ` Madhav Chauhan
  0 siblings, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2018-09-11 18:16 UTC (permalink / raw)
  To: Madhav Chauhan, Kulkarni, Vandita, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Mon, 10 Sep 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 9/6/2018 7:31 PM, Kulkarni, Vandita wrote:
>>
>>
>>
>> On 7/10/2018 3:10 PM, Madhav Chauhan wrote:
>>> This patch setup voltage swing before enabling
>>> combo PHY DDI (shared with DSI).
>>> Note that DSI voltage swing programming is for
>>> high speed data buffers. HW automatically handles
>>> the voltage swing for the low power data buffers.
>>>
>>> v2: Rebase
>>>
>>> Signed-off-by: Madhav Chauhan<madhav.chauhan@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/icl_dsi.c | 114 +++++++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 114 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>>> index a571339..dc16c1f 100644
>>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>>> @@ -27,6 +27,65 @@
>>>   
>>>   #include "intel_dsi.h"
>>>   
>>> +static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
>>> +{
>>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>> +	enum port port;
>>> +	u32 tmp;
>>> +	int lane;
>>> +
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +
>>> +		/* Bspec: set scaling mode to 0x6 */
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>> +		tmp |= SCALING_MODE_SEL(6);
>>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>> +		tmp |= SCALING_MODE_SEL(6);
>>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
>>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
>>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>> +
>>> +		/*
>>> +		 * swing and scaling values are taken from DSI
>>> +		 * table under vswing programming sequence for
>>> +		 * combo phy ddi in BSPEC.
>>> +		 * program swing values
>>> +		 */
>>> +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>>> +		tmp |= SWING_SEL_UPPER(0x2);
>>> +		tmp |= SWING_SEL_LOWER(0x2);
>>> +		tmp |= RCOMP_SCALAR(0x98);
>>> +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
>>> +		tmp |= SWING_SEL_UPPER(0x2);
>>> +		tmp |= SWING_SEL_LOWER(0x2);
>>> +		tmp |= RCOMP_SCALAR(0x98);
>>> +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
>>> +
>>> +		/* program scaling values */
>>> +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
>>> +		tmp |= POST_CURSOR_1(0x0);
>>> +		tmp |= POST_CURSOR_2(0x0);
>>> +		tmp |= CURSOR_COEFF(0x18);
>>> +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
>>> +
>>> +		for (lane = 0; lane <= 3; lane++) {
>>> +			/* Bspec: must not use GRP register for write */
>>> +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
>>> +			tmp |= POST_CURSOR_1(0x0);
>>> +			tmp |= POST_CURSOR_2(0x0);
>>> +			tmp |= CURSOR_COEFF(0x18);
>>> +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
>>> +		}
>>> +	}
>>> +}
>>> +
>>>   static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
>>>   {
>>>   	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>> @@ -140,6 +199,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>>>   	}
>>>   }
>>>   
>>
>> I see from the bspec that except for the Loadgen Select and Latency 
>> Optimization all other DDI buffer programming can be taken from the 
>> DDI Buffer section.
>>
>> Can we use this function "icl_ddi_combo_vswing_program" function which 
>> is already there
>> patch for reference:
>> https://patchwork.freedesktop.org/patch/213515/

For code already merged upstream, please use commit id or file
references.

>
> We can't directly use that implementation. Reasons:
> 1. For DSI we use AUX register as well to write which is not the case 
> for DDI. We need to add multiple INTEL_OUTPUT_DSI
> checks .
> 2. DSI specific icl_combo_phy_ddi_buf_trans not added in intel_ddi.c 
> which will be used while doing vswing programming
> 3. intel_ddi_dp_level doesn't support "level" calculation for DSI.
>
> Also in past we had similar discussion (with Jani N) to keep DSI 
> specific entries/code in DSI encoder.
>
> Jani N whats the suggestion here??

Let's go with the slightly duplicated code, at least for now to get this
merged. This is tedious stuff to review, and combining that with merging
to DP/HDMI buf programming makes it unnecessarily hard. We can refactor
afterwards as needed.

BR,
Jani.


>
> Regards,
> Madhav
>
>>
>> Thanks,
>> Vandita
>>
>>> +static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
>>> +{
>>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>> +	u32 tmp;
>>> +	enum port port;
>>> +
>>> +	/* Step C.1:clear common keeper enable bit */
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
>>> +		tmp &= ~COMMON_KEEPER_EN;
>>> +		I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
>>> +		tmp &= ~COMMON_KEEPER_EN;
>>> +		I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
>>> +	}
>>> +
>>> +	/*
>>> +	 * Step C.3: Set SUS Clock Config bitfield to 11b
>>> +	 * Note: Step C.2 (loadgen select program) is done
>>> +	 * as part of lane phy sequence configuration
>>> +	 */
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +		tmp = I915_READ(ICL_PORT_CL_DW5(port));
>>> +		tmp |= SUS_CLOCK_CONFIG;
>>> +		I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
>>> +	}
>>> +
>>> +	/* Step C.4: Clear training enable to change swing values */
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>> +		tmp &= ~TX_TRAINING_EN;
>>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>> +		tmp &= ~TX_TRAINING_EN;
>>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>> +	}
>>> +
>>> +	/* Step C.5: Program swing and de-emphasis */
>>> +	dsi_program_swing_and_deemphasis(encoder);
>>> +
>>> +	/* Step: C.6: Set training enable to trigger update */
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>> +		tmp |= TX_TRAINING_EN;
>>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>> +		tmp |= TX_TRAINING_EN;
>>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>> +	}
>>> +}
>>> +
>>>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>>   {
>>>   	/* step 4a: power up all lanes of the DDI used by DSI */
>>> @@ -147,6 +258,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>>   
>>>   	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
>>>   	gen11_dsi_config_phy_lanes_sequence(encoder);
>>> +
>>> +	/* step 4c: configure voltage swing and skew */
>>> +	gen11_dsi_voltage_swing_program_seq(encoder);
>>>   }
>>>   
>>>   static void __attribute__((unused))
>>
>

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence
  2018-07-10  9:40 ` [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
  2018-09-06 14:01   ` [v5, " Kulkarni, Vandita
@ 2018-09-11 18:50   ` Jani Nikula
  2018-09-12  9:03     ` Madhav Chauhan
  1 sibling, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2018-09-11 18:50 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch setup voltage swing before enabling
> combo PHY DDI (shared with DSI).
> Note that DSI voltage swing programming is for
> high speed data buffers. HW automatically handles
> the voltage swing for the low power data buffers.
>
> v2: Rebase
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/icl_dsi.c | 114 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 114 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index a571339..dc16c1f 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -27,6 +27,65 @@
>  
>  #include "intel_dsi.h"
>  
> +static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 tmp;
> +	int lane;
> +
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +
> +		/* Bspec: set scaling mode to 0x6 */

Today bspec says 2. Also, please don't duplicate the value in the
comment.

> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> +		tmp |= SCALING_MODE_SEL(6);
> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);

Like Ville said, adding a blank line between each read-modify-write
group helps readability. Perhaps add /* DW5 */ etc. comments to group
the, eh, groups.

> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> +		tmp |= SCALING_MODE_SEL(6);
> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);

Are you missing RTERM_SELECT?

Why do you do two read-modify-writes (RMW) on both GRP and AUX, instead
of doing all the changes at once?

The RMW doesn't actually clear the fields before changing them, just ORs
more stuff on top of them, and cursor program or coeff polarity might
contain garbage (at least in theory). The same below.

> +
> +		/*
> +		 * swing and scaling values are taken from DSI
> +		 * table under vswing programming sequence for
> +		 * combo phy ddi in BSPEC.
> +		 * program swing values
> +		 */

Please reflow the comment.

> +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> +		tmp |= SWING_SEL_UPPER(0x2);
> +		tmp |= SWING_SEL_LOWER(0x2);

This would benefit from

+#define   SWING_SEL_MASK		(SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK)
+#define   SWING_SEL(x)			(SWING_SEL_UPPER(x) | SWING_SEL_LOWER(x))

in i915_reg.h. But I can look the other way and fix it myself later...

> +		tmp |= RCOMP_SCALAR(0x98);
> +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> +		tmp |= SWING_SEL_UPPER(0x2);
> +		tmp |= SWING_SEL_LOWER(0x2);
> +		tmp |= RCOMP_SCALAR(0x98);
> +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> +
> +		/* program scaling values */
> +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> +		tmp |= POST_CURSOR_1(0x0);
> +		tmp |= POST_CURSOR_2(0x0);
> +		tmp |= CURSOR_COEFF(0x18);

0x3f?

Again, you need to zero the fields before ORin the new values into them.

> +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> +
> +		for (lane = 0; lane <= 3; lane++) {
> +			/* Bspec: must not use GRP register for write */

I'll take your word for it, although I've missed such a requirement.

> +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
> +			tmp |= POST_CURSOR_1(0x0);
> +			tmp |= POST_CURSOR_2(0x0);
> +			tmp |= CURSOR_COEFF(0x18);

0x3f?

> +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
> +		}
> +	}
> +}
> +
>  static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -140,6 +199,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>  	}
>  }
>  
> +static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	u32 tmp;
> +	enum port port;
> +

The step numbering below has changed in bspec. Please update. Maybe drop
the numbering, and use just the headings.

Otherwise, the bits here look ok.

BR,
Jani.

> +	/* Step C.1:clear common keeper enable bit */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
> +		tmp &= ~COMMON_KEEPER_EN;
> +		I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
> +		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
> +		tmp &= ~COMMON_KEEPER_EN;
> +		I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
> +	}
> +
> +	/*
> +	 * Step C.3: Set SUS Clock Config bitfield to 11b
> +	 * Note: Step C.2 (loadgen select program) is done
> +	 * as part of lane phy sequence configuration
> +	 */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_PORT_CL_DW5(port));
> +		tmp |= SUS_CLOCK_CONFIG;
> +		I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
> +	}
> +
> +	/* Step C.4: Clear training enable to change swing values */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> +		tmp &= ~TX_TRAINING_EN;
> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> +		tmp &= ~TX_TRAINING_EN;
> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> +	}
> +
> +	/* Step C.5: Program swing and de-emphasis */
> +	dsi_program_swing_and_deemphasis(encoder);
> +
> +	/* Step: C.6: Set training enable to trigger update */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> +		tmp |= TX_TRAINING_EN;
> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> +		tmp |= TX_TRAINING_EN;
> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> +	}
> +}
> +
>  static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>  {
>  	/* step 4a: power up all lanes of the DDI used by DSI */
> @@ -147,6 +258,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>  
>  	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
>  	gen11_dsi_config_phy_lanes_sequence(encoder);
> +
> +	/* step 4c: configure voltage swing and skew */
> +	gen11_dsi_voltage_swing_program_seq(encoder);
>  }
>  
>  static void __attribute__((unused))

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer
  2018-07-10  9:40 ` [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
@ 2018-09-11 18:54   ` Jani Nikula
  2018-09-12  9:06     ` Madhav Chauhan
  0 siblings, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2018-09-11 18:54 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch enables DDI buffer by writing to DDI_BUF_CTL
> register and wait for DDI status to be *not idle* for a
> port.
>
> v2: Rebase
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/icl_dsi.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index dc16c1f..41faa19 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -251,6 +251,25 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
>  	}
>  }
>  
> +static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	u32 tmp;
> +	enum port port;
> +
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(DDI_BUF_CTL(port));
> +		tmp |= DDI_BUF_CTL_ENABLE;
> +		I915_WRITE(DDI_BUF_CTL(port), tmp);
> +
> +		if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
> +				  DDI_BUF_IS_IDLE),
> +				  500))

IMO a "== 0" check reads better in wait_for_us.

> +			DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
> +	}
> +}
> +
>  static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>  {
>  	/* step 4a: power up all lanes of the DDI used by DSI */
> @@ -261,6 +280,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>  
>  	/* step 4c: configure voltage swing and skew */
>  	gen11_dsi_voltage_swing_program_seq(encoder);
> +
> +	/* step 4d: enable DDI buffer */

Alas, this is step 4e now, and you have a new 4d to take care of for
B0+.

Regardless,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +	gen11_dsi_enable_ddi_buffer(encoder);
>  }
>  
>  static void __attribute__((unused))

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 06/13] drm/i915/icl: Define data/clock lanes dphy timing registers
  2018-07-10  9:40 ` [PATCH v5 06/13] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
@ 2018-09-11 19:14   ` Jani Nikula
  2018-09-12  9:11     ` Madhav Chauhan
  0 siblings, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2018-09-11 19:14 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
> DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
> dphy programming.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6129372..0dbdd57 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10075,6 +10075,46 @@ enum skl_power_gate {
>  						   _ICL_DSI_T_INIT_MASTER_0,\
>  						   _ICL_DSI_T_INIT_MASTER_1)
>  
> +#define _DPHY_CLK_TIMING_PARAM_0	0x162180
> +#define _DPHY_CLK_TIMING_PARAM_1	0x6c180
> +#define DPHY_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
> +						   _DPHY_CLK_TIMING_PARAM_0,\
> +						   _DPHY_CLK_TIMING_PARAM_1)
> +#define _DSI_CLK_TIMING_PARAM_0		0x6b080
> +#define _DSI_CLK_TIMING_PARAM_1		0x6b880
> +#define DSI_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
> +						   _DSI_CLK_TIMING_PARAM_0,\
> +						   _DSI_CLK_TIMING_PARAM_1)
> +#define  CLK_PREP_OVERRIDE		(1 << 31)
> +#define  CLK_PREP_TIME(x)		(x << 28)
> +#define  CLK_ZERO_OVERRIDE		(1 << 27)
> +#define  CLK_ZERO_TIME(x)		(x << 20)
> +#define  CLK_PRE_OVERRIDE		(1 << 19)
> +#define  CLK_PRE_TIME(x)		(x << 16)
> +#define  CLK_POST_OVERRIDE		(1 << 15)
> +#define  CLK_POST_TIME(x)		(x << 8)
> +#define  CLK_TRAIL_OVERRIDE		(1 << 7)
> +#define  CLK_TRAIL_TIME(x)		(x << 0)

I would prefer we stuck to the convention of defining _SHIFT and _MASK
macros for the bitfields. Even if the above style has started to creep
in without proper discussion. (I approve of the function-like macros for
things that aren't straight shifts; stuff with split bitfields or
calculations.)

No matter what, you need to wrap the macro arguments in parens!

Also, please don't do your own abbreviations or renames of the field
names when the bspec name is short/good enough.

> +
> +#define _DPHY_DATA_TIMING_PARAM_0	0x162184
> +#define _DPHY_DATA_TIMING_PARAM_1	0x6c184
> +#define DPHY_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
> +						   _DPHY_DATA_TIMING_PARAM_0,\
> +						   _DPHY_DATA_TIMING_PARAM_1)
> +#define _DSI_DATA_TIMING_PARAM_0	0x6B084
> +#define _DSI_DATA_TIMING_PARAM_1	0x6B884
> +#define DSI_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
> +						   _DSI_DATA_TIMING_PARAM_0,\
> +						   _DSI_DATA_TIMING_PARAM_1)
> +#define  HS_PREP_OVERRIDE		(1 << 31)
> +#define  HS_PREP_TIME(x)		(x << 24)
> +#define  HS_ZERO_OVERRIDE		(1 << 23)
> +#define  HS_ZERO_TIME(x)		(x << 16)
> +#define  HS_TRAIL_OVERRIDE		(1 << 15)
> +#define  HS_TRAIL_TIME(x)		(x << 8)
> +#define  HS_EXIT_OVERRIDE		(1 << 7)
> +#define  HS_EXIT_TIME(x)		(x << 0)

Same as above.

The register offsets and shifts etc. look ok.

BR,
Jani.

> +
>  /* bits 31:0 */
>  #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
>  #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 05/13] drm/i915/icl: Program T_INIT_MASTER registers
  2018-07-10  9:40 ` [PATCH v5 05/13] drm/i915/icl: Program " Madhav Chauhan
@ 2018-09-11 19:17   ` Jani Nikula
  0 siblings, 0 replies; 63+ messages in thread
From: Jani Nikula @ 2018-09-11 19:17 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch programs the time (in escape clocks) to drive
> the link in the initialization (i.e. LP-11) state.
>
> v2: Rebase
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/icl_dsi.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 41faa19..bc27e34 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -270,6 +270,22 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
>  	}
>  }
>  
> +static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	u32 tmp;
> +	enum port port;
> +
> +	/* Program T-INIT master registers */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port));
> +		tmp &= ~MASTER_INIT_TIMER_MASK;
> +		tmp |= intel_dsi->init_count;
> +		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
> +	}

Mmh, the high word is MBZ so the RMW is unnecessary. But *shrug*.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +}
> +
>  static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>  {
>  	/* step 4a: power up all lanes of the DDI used by DSI */
> @@ -283,6 +299,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>  
>  	/* step 4d: enable DDI buffer */
>  	gen11_dsi_enable_ddi_buffer(encoder);
> +
> +	/* step 4e: setup D-PHY timings */
> +	gen11_dsi_setup_dphy_timings(encoder);
>  }
>  
>  static void __attribute__((unused))

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 04/13] drm/i915/icl: Define T_INIT_MASTER registers
  2018-07-10  9:40 ` [PATCH v5 04/13] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
@ 2018-09-11 19:18   ` Jani Nikula
  0 siblings, 0 replies; 63+ messages in thread
From: Jani Nikula @ 2018-09-11 19:18 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch defines DSI_T_INIT_MASTER register for DSI ports
> 0/1 which will be used in dphy programming.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>

Thanks, pushed to dinq.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0424e45..6129372 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10069,6 +10069,12 @@ enum skl_power_gate {
>  #define  PREPARE_COUNT_SHIFT				0
>  #define  PREPARE_COUNT_MASK				(0x3f << 0)
>  
> +#define _ICL_DSI_T_INIT_MASTER_0	0x6b088
> +#define _ICL_DSI_T_INIT_MASTER_1	0x6b888
> +#define ICL_DSI_T_INIT_MASTER(port)	_MMIO_PORT(port,	\
> +						   _ICL_DSI_T_INIT_MASTER_0,\
> +						   _ICL_DSI_T_INIT_MASTER_1)
> +
>  /* bits 31:0 */
>  #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
>  #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers
  2018-07-10  9:40 ` [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
@ 2018-09-11 19:23   ` Jani Nikula
  2018-09-12  9:13     ` Madhav Chauhan
  0 siblings, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2018-09-11 19:23 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch defines DSI_TA_TIMING_PARAM and
> DPHY_TA_TIMING_PARAM registers used in
> dphy programming.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0dbdd57..1d13ba9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10115,6 +10115,20 @@ enum skl_power_gate {
>  #define  HS_EXIT_OVERRIDE		(1 << 7)
>  #define  HS_EXIT_TIME(x)		(x << 0)
>  
> +#define _DPHY_TA_TIMING_PARAM_0		0x162188
> +#define _DPHY_TA_TIMING_PARAM_1		0x6c188
> +#define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
> +						   _DPHY_TA_TIMING_PARAM_0,\
> +						   _DPHY_TA_TIMING_PARAM_1)
> +#define _DSI_TA_TIMING_PARAM_0		0x6b098
> +#define _DSI_TA_TIMING_PARAM_1		0x6b898
> +#define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
> +						   _DSI_TA_TIMING_PARAM_0,\
> +						   _DSI_TA_TIMING_PARAM_1)
> +#define  TA_SURE_OVERRIDE		(1 << 31)
> +#define  TA_SURE_TIME(x)		(x << 16)
> +#define  TA_SURE_TIME_MASK		(0x1f << 16)

Please stick to _SHIFT. And in any case macro arguments need parens
around them.

Please add all the fields for the registers in one go.

BR,
Jani.


> +
>  /* bits 31:0 */
>  #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
>  #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 09/13] drm/i915/icl: Program TA_TIMING_PARAM registers
  2018-07-20  8:08     ` Chauhan, Madhav
@ 2018-09-11 19:26       ` Jani Nikula
  2018-09-12  9:25         ` Madhav Chauhan
  0 siblings, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2018-09-11 19:26 UTC (permalink / raw)
  To: Chauhan, Madhav, Ville Syrjälä
  Cc: intel-gfx, Zanoni, Paulo R, Vivi, Rodrigo

On Fri, 20 Jul 2018, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>> -----Original Message-----
>> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>> Sent: Thursday, July 19, 2018 9:51 PM
>> To: Chauhan, Madhav <madhav.chauhan@intel.com>
>> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
>> Zanoni, Paulo R <paulo.r.zanoni@intel.com>; Vivi, Rodrigo
>> <rodrigo.vivi@intel.com>
>> Subject: Re: [Intel-gfx] [PATCH v5 09/13] drm/i915/icl: Program
>> TA_TIMING_PARAM registers
>> 
>> On Tue, Jul 10, 2018 at 03:10:10PM +0530, Madhav Chauhan wrote:
>> > This patch programs D-PHY timing parameters for the bus turn around
>> > flow(in escape clocks) only if dsi link frequency <=800 MHz using
>> > DPHY_TA_TIMING_PARAM and its identical register
>> DSI_TA_TIMING_PARAM
>> > (inside DSI Controller within the Display Core).
>> >
>> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/icl_dsi.c       | 21 +++++++++++++++++++++
>> >  drivers/gpu/drm/i915/intel_dsi.h     |  1 +
>> >  drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
>> >  3 files changed, 23 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>> > b/drivers/gpu/drm/i915/icl_dsi.c index 832772d..8fd5284 100644
>> > --- a/drivers/gpu/drm/i915/icl_dsi.c
>> > +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> > @@ -302,6 +302,27 @@ static void gen11_dsi_setup_dphy_timings(struct
>> intel_encoder *encoder)
>> >  		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
>> >  			   intel_dsi->dphy_data_lane_reg);
>> >  	}
>> > +
>> > +	/*
>> > +	 * If DSI link operating at or below an 800 MHz,
>> > +	 * TA_SURE should be override and programmed to
>> > +	 * a value '0' inside TA_PARAM_REGISTERS otherwise
>> > +	 * leave all fields at HW default values.
>> > +	 */
>> > +	if (intel_dsi->bitrate_khz <= KHz(800)) {
>> 
>> The KHz(800) confuses me. My brain thinks this value is 800 kHz when it's
>> not. So I'd write it without the KHz() macro.
>
> Ok. Initially I wrote without using KHz macro, but got comment to use KHz macro :)

Did I? Oh well. Go with 800000.

Please don't add additional state with intel_dsi->bitrate_khz when you
can calculate the bitrate at any time. Add a function to do it if you
like, and use it in both places.

BR,
Jani.


>
> Regards,
> Madhav
>
>> 
>> > +		for_each_dsi_port(port, intel_dsi->ports) {
>> > +			tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
>> > +			tmp &= ~TA_SURE_TIME_MASK;
>> > +			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
>> > +			I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
>> > +
>> > +			/* shadow register inside display core */
>> > +			tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
>> > +			tmp &= ~TA_SURE_TIME_MASK;
>> > +			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
>> > +			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
>> > +		}
>> > +	}
>> >  }
>> >
>> >  static void gen11_dsi_enable_port_and_phy(struct intel_encoder
>> > *encoder) diff --git a/drivers/gpu/drm/i915/intel_dsi.h
>> > b/drivers/gpu/drm/i915/intel_dsi.h
>> > index 9fd8526..25e7396 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi.h
>> > +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> > @@ -101,6 +101,7 @@ struct intel_dsi {
>> >
>> >  	u16 init_count;
>> >  	u32 pclk;
>> > +	u32 bitrate_khz;
>> >  	u16 burst_mode_ratio;
>> >
>> >  	/* all delays in ms */
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> > b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> > index 428290d..a9a98a4 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> > +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> > @@ -589,6 +589,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi,
>> u16 panel_id)
>> >  	intel_dsi->pclk = pclk;
>> >
>> >  	bitrate = (pclk * bpp) / intel_dsi->lane_count;
>> > +	intel_dsi->bitrate_khz = bitrate;
>> >
>> >  	switch (intel_dsi->escape_clk_div) {
>> >  	case 0:
>> > --
>> > 2.7.4
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> 
>> --
>> Ville Syrjälä
>> Intel

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
  2018-07-10  9:40 ` [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
@ 2018-09-11 19:30   ` Jani Nikula
  2018-09-12  9:35     ` Madhav Chauhan
  0 siblings, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2018-09-11 19:30 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch defines transcoder function configuration
> registers and its bitfields for both DSI ports.
> Used while programming/enabling DSI transcoder.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 47 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 62bc76e..71ce6ba 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10134,6 +10134,53 @@ enum skl_power_gate {
>  #define  TA_SURE_TIME(x)		(x << 16)
>  #define  TA_SURE_TIME_MASK		(0x1f << 16)
>  
> +/* DSI transcoder configuration */
> +#define _DSI_TRANS_FUNC_CONF_0		0x6b030
> +#define _DSI_TRANS_FUNC_CONF_1		0x6b830
> +#define DSI_TRANS_FUNC_CONF(tc)		_MMIO_DSI(tc,	\
> +						  _DSI_TRANS_FUNC_CONF_0,\
> +						  _DSI_TRANS_FUNC_CONF_1)
> +#define  OP_MODE(x)			(x << 28)
> +#define  OP_MODE_MASK			(0x3 << 28)
> +#define  CMD_MODE_NO_GATE		0x0
> +#define  CMD_MODE_TE_GATE		0x1
> +#define  VIDEO_MODE_SYNC_EVENT		0x2
> +#define  VIDEO_MODE_SYNC_PULSE		0x3

The convention is to define macros for field values that you can OR
directly in place instead of requiring a shift. Please stick to the
conventions. Use _SHIFT and _MASK.

We can debate the relative merits of both approaches at some point, but
this is not the time.

BR,
Jani.

> +#define  LINK_READY			(1 << 20)
> +#define  PIX_FMT(x)			(x << 16)
> +#define  PIX_FMT_MASK			(0x3 << 16)
> +#define  PIX_FMT_RGB565		0x0
> +#define  PIX_FMT_RGB666_PACKED		0x1
> +#define  PIX_FMT_RGB666_LOOSE		0x2
> +#define  PIX_FMT_RGB888		0x3
> +#define  PIX_FMT_RGB101010		0x4
> +#define  PIX_FMT_RGB121212		0x5
> +#define  PIX_FMT_COMPRESSED		0x6
> +#define  BGR_TRANSMISSION		(1 << 15)
> +#define  PIX_VIRT_CHAN(x)		(x << 12)
> +#define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
> +#define  PIX_BUF_THRESHOLD(x)		((x & 0x3) << 10)
> +#define  PIX_BUF_THRESHOLD_MASK	(0x3 << 10)
> +#define  PIX_BUF_THRESHOLD_1_4		0x0
> +#define  PIX_BUF_THRESHOLD_1_2		0x1
> +#define  PIX_BUF_THRESHOLD_3_4		0x2
> +#define  PIX_BUF_THRESHOLD_FULL	0x3
> +#define  CONTINUOUS_CLK(x)		(x << 8)
> +#define  CONTINUOUS_CLK_MASK		(0x3 << 8)
> +#define  CLK_ENTER_LP_AFTER_DATA	0x0
> +#define  CLK_HS_OR_LP			0x2
> +#define  CLK_HS_CONTINUOUS		0x3
> +#define  LINK_CALIBRATION(x)		(x << 4)
> +#define  LINK_CALIBRATION_MASK		(0x3 << 4)
> +#define  CALIBRATION_DISABLED		0x0
> +#define  CALIBRATION_ENABLED_INITIAL_ONLY	0x2
> +#define  CALIBRATION_ENABLED_INITIAL_PERIODIC	0x3
> +#define  S3D_ORIENTATION(x)		(x << 1)
> +#define  S3D_ORIENTATION_MASK		(0x1 << 1)
> +#define  S3D_ORIENTATION_PORTRAIT	0x0
> +#define  S3D_ORIENTATION_LANDSCAPE	0x1
> +#define  EOTP_DISABLED			(1 << 0)
> +
>  /* bits 31:0 */
>  #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
>  #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 00/13] ICELAKE DSI DRIVER
  2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
                   ` (16 preceding siblings ...)
  2018-07-10 16:28 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-09-11 19:35 ` Jani Nikula
  2018-09-12  6:16   ` Madhav Chauhan
  17 siblings, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2018-09-11 19:35 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to
> GPU/Display Engine and same could be extended for future Intel platforms as well.
> DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification.
>
> So, a new DSI driver has been added inside I915.
>
> Given below patches are the part of new DSI driver which implements BSPEC
> sequence till transcoder configuration. Rest of the patches published to GITHUB
> and latest snapshot can be downloaded using:
> #git clone https://github.com/madhavchauhan/Intel-DSI-Driver.git
>
> v2: Addressed review comments from Jani N for Patches 1-6 and rebase for some
> other few patches.
> v3: Renamed intel_dsi_new.c to gen11_dsi.c as per discussion with Jani, Daniel,
>     Ville. Also addressed review comments for couple of patches.
> v4: Rename gen11_dsi.c to icl_dsi.c (Ville). No functional changes.
> v5: Rebase on drm-tip after initial 7 patches got merged.

Hi Madhav, I think there's enough review here to warrant a revised
set. I regret I haven't been able to review this earlier, and I'm now
throwing the ball back in your court... with the added pressure that I'd
really like to get this merged for v4.20. Which means the deadline for
merging is about 1½ weeks away. Is there any chance?

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 00/13] ICELAKE DSI DRIVER
  2018-09-11 19:35 ` [PATCH v5 00/13] ICELAKE DSI DRIVER Jani Nikula
@ 2018-09-12  6:16   ` Madhav Chauhan
  2018-09-12  7:31     ` Jani Nikula
  0 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-12  6:16 UTC (permalink / raw)
  To: Jani Nikula, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On 9/12/2018 1:05 AM, Jani Nikula wrote:
> On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>>  From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to
>> GPU/Display Engine and same could be extended for future Intel platforms as well.
>> DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification.
>>
>> So, a new DSI driver has been added inside I915.
>>
>> Given below patches are the part of new DSI driver which implements BSPEC
>> sequence till transcoder configuration. Rest of the patches published to GITHUB
>> and latest snapshot can be downloaded using:
>> #git clone https://github.com/madhavchauhan/Intel-DSI-Driver.git
>>
>> v2: Addressed review comments from Jani N for Patches 1-6 and rebase for some
>> other few patches.
>> v3: Renamed intel_dsi_new.c to gen11_dsi.c as per discussion with Jani, Daniel,
>>      Ville. Also addressed review comments for couple of patches.
>> v4: Rename gen11_dsi.c to icl_dsi.c (Ville). No functional changes.
>> v5: Rebase on drm-tip after initial 7 patches got merged.
> Hi Madhav, I think there's enough review here to warrant a revised
> set. I regret I haven't been able to review this earlier, and I'm now
> throwing the ball back in your court... with the added pressure that I'd
> really like to get this merged for v4.20. Which means the deadline for
> merging is about 1½ weeks away. Is there any chance?

Agree, i will publish next series soon.
Do you mean to merge these 13 patches to 4.20 or the complete 
implementation of 65 patches??

Regards,
Madhav
>
> BR,
> Jani.
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter
  2018-09-11 17:46         ` Jani Nikula
@ 2018-09-12  6:32           ` Madhav Chauhan
  0 siblings, 0 replies; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-12  6:32 UTC (permalink / raw)
  To: Jani Nikula, 'Ville Syrjälä'
  Cc: 'intel-gfx@lists.freedesktop.org',
	Zanoni, Paulo R, Vivi, Rodrigo

On 9/11/2018 11:16 PM, Jani Nikula wrote:
> On Fri, 27 Jul 2018, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>>> -----Original Message-----
>>> From: Chauhan, Madhav
>>> Sent: Friday, July 20, 2018 12:06 AM
>>> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
>>> Zanoni, Paulo R <paulo.r.zanoni@intel.com>; Vivi, Rodrigo
>>> <rodrigo.vivi@intel.com>
>>> Subject: RE: [Intel-gfx] [PATCH v5 01/13] drm/i915/icl: Configure lane
>>> sequencing of combo phy transmitter
>>>
>>>> -----Original Message-----
>>>> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>>>> Sent: Thursday, July 19, 2018 9:42 PM
>>>> To: Chauhan, Madhav <madhav.chauhan@intel.com>
>>>> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
>>>> <jani.nikula@intel.com>; Zanoni, Paulo R <paulo.r.zanoni@intel.com>;
>>>> Vivi, Rodrigo <rodrigo.vivi@intel.com>
>>>> Subject: Re: [Intel-gfx] [PATCH v5 01/13] drm/i915/icl: Configure lane
>>>> sequencing of combo phy transmitter
>>>>
>>>> On Tue, Jul 10, 2018 at 03:10:02PM +0530, Madhav Chauhan wrote:
>>>>> This patch set the loadgen select and latency optimization for aux
>>>>> and transmit lanes of combo phy transmitters. It will be used for
>>>>> MIPI DSI HS operations.
>>> Thanks for reviewing DSI patches.
>>>
>>>>> v2: Rebase
>>>>>
>>>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>>>>> ---
>>>>>   drivers/gpu/drm/i915/icl_dsi.c | 38
>>>>> ++++++++++++++++++++++++++++++++++++++
>>>>>   1 file changed, 38 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>>>>> b/drivers/gpu/drm/i915/icl_dsi.c index 13830e4..a571339 100644
>>>>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>>>>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>>>>> @@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct
>>>> intel_encoder *encoder)
>>>>>   	}
>>>>>   }
>>>>>
>>>>> +static void gen11_dsi_config_phy_lanes_sequence(struct
>>>>> +intel_encoder
>>>>> +*encoder) {
>>>>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>>>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>>>> +	enum port port;
>>>>> +	u32 tmp;
>>>>> +	int lane;
>>>> tmp/lane could be moved to into the loops.
>> Was it due to intel_dsi->ports have no port assigned and
>> loop for_each_dsi_port() will not proceed further??
>> If that's the case, these encoder enable/disable function should be called
>> Only when dsi_init is success and then, intel_dsi->ports have some valid port value.
>>
>> Please clarify.
> Ville's comments are purely about style and readability.
>
>> Regards,
>> Madhav
>>
>>>> Same in other patches.
>>> Agree, make sense.
>> Just to understand
>>>>> +
>>>>> +	/* Step 4b(i) set loadgen select for transmit and aux lanes */
>>>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>>>> +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
>>>>> +		tmp &= ~LOADGEN_SELECT;
>>>>> +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
>>>>> +		for (lane = 0; lane <= 3; lane++) {
>>>>> +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port,
>>>> lane));
>>>>> +			tmp &= ~LOADGEN_SELECT;
>>>>> +			if (lane != 2)
>>>>> +				tmp |= LOADGEN_SELECT;
>>>>> +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane),
>>>> tmp);
>>>>> +		}
>>>>> +	}
>>>>> +
>>>>> +	/* Step 4b(ii) set latency optimization for transmit and aux lanes */
>>>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>>>> +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
>>>>> +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
>>>>> +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
>>>>> +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
>>>>> +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>>>>> +		tmp &= ~FRC_LATENCY_OPTIM_MASK;
>>>>> +		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
>>>>> +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> The "read something, modify, write something else" pattern always gives
> me the creeps. But I guess reading _GRP is not an option?
>
> Anyway, for the actual content,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Thanks for the review. Yes, we need to read *only* LN0 and if same 
value, then write through GRP
register.

Regards,
Madhav

>
>>>>> +	}
>>>> An empty line here and there would make this a bit more legible.
>>>>
>>>> Same in other patches.
>>> Ok.  Thought this will be additional line, multiple Places in code use this :)
>>>
>>> Regards,
>>> Madhav
>>>
>>>>> +}
>>>>> +
>>>>>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder
>>>>> *encoder)  {
>>>>>   	/* step 4a: power up all lanes of the DDI used by DSI */
>>>>>   	gen11_dsi_power_up_lanes(encoder);
>>>>> +
>>>>> +	/* step 4b: configure lane sequencing of the Combo-PHY
>>>>> +transmitters
>>>> */
>>>>> +	gen11_dsi_config_phy_lanes_sequence(encoder);
>>>>>   }
>>>>>
>>>>>   static void __attribute__((unused))
>>>>> --
>>>>> 2.7.4
>>>>>
>>>>> _______________________________________________
>>>>> Intel-gfx mailing list
>>>>> Intel-gfx@lists.freedesktop.org
>>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>> --
>>>> Ville Syrjälä
>>>> Intel
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
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^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [v5, 02/13] drm/i915/icl: DSI vswing programming sequence
  2018-09-11 18:16       ` Jani Nikula
@ 2018-09-12  6:34         ` Madhav Chauhan
  0 siblings, 0 replies; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-12  6:34 UTC (permalink / raw)
  To: Jani Nikula, Kulkarni, Vandita, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On 9/11/2018 11:46 PM, Jani Nikula wrote:
> On Mon, 10 Sep 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>> On 9/6/2018 7:31 PM, Kulkarni, Vandita wrote:
>>>
>>>
>>> On 7/10/2018 3:10 PM, Madhav Chauhan wrote:
>>>> This patch setup voltage swing before enabling
>>>> combo PHY DDI (shared with DSI).
>>>> Note that DSI voltage swing programming is for
>>>> high speed data buffers. HW automatically handles
>>>> the voltage swing for the low power data buffers.
>>>>
>>>> v2: Rebase
>>>>
>>>> Signed-off-by: Madhav Chauhan<madhav.chauhan@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/icl_dsi.c | 114 +++++++++++++++++++++++++++++++++++++++++
>>>>    1 file changed, 114 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>>>> index a571339..dc16c1f 100644
>>>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>>>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>>>> @@ -27,6 +27,65 @@
>>>>    
>>>>    #include "intel_dsi.h"
>>>>    
>>>> +static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
>>>> +{
>>>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>>> +	enum port port;
>>>> +	u32 tmp;
>>>> +	int lane;
>>>> +
>>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>>> +
>>>> +		/* Bspec: set scaling mode to 0x6 */
>>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>>> +		tmp |= SCALING_MODE_SEL(6);
>>>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>>> +		tmp |= SCALING_MODE_SEL(6);
>>>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>>> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
>>>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>>> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
>>>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>>> +
>>>> +		/*
>>>> +		 * swing and scaling values are taken from DSI
>>>> +		 * table under vswing programming sequence for
>>>> +		 * combo phy ddi in BSPEC.
>>>> +		 * program swing values
>>>> +		 */
>>>> +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>>>> +		tmp |= SWING_SEL_UPPER(0x2);
>>>> +		tmp |= SWING_SEL_LOWER(0x2);
>>>> +		tmp |= RCOMP_SCALAR(0x98);
>>>> +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
>>>> +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
>>>> +		tmp |= SWING_SEL_UPPER(0x2);
>>>> +		tmp |= SWING_SEL_LOWER(0x2);
>>>> +		tmp |= RCOMP_SCALAR(0x98);
>>>> +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
>>>> +
>>>> +		/* program scaling values */
>>>> +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
>>>> +		tmp |= POST_CURSOR_1(0x0);
>>>> +		tmp |= POST_CURSOR_2(0x0);
>>>> +		tmp |= CURSOR_COEFF(0x18);
>>>> +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
>>>> +
>>>> +		for (lane = 0; lane <= 3; lane++) {
>>>> +			/* Bspec: must not use GRP register for write */
>>>> +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
>>>> +			tmp |= POST_CURSOR_1(0x0);
>>>> +			tmp |= POST_CURSOR_2(0x0);
>>>> +			tmp |= CURSOR_COEFF(0x18);
>>>> +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
>>>> +		}
>>>> +	}
>>>> +}
>>>> +
>>>>    static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
>>>>    {
>>>>    	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>>> @@ -140,6 +199,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>>>>    	}
>>>>    }
>>>>    
>>> I see from the bspec that except for the Loadgen Select and Latency
>>> Optimization all other DDI buffer programming can be taken from the
>>> DDI Buffer section.
>>>
>>> Can we use this function "icl_ddi_combo_vswing_program" function which
>>> is already there
>>> patch for reference:
>>> https://patchwork.freedesktop.org/patch/213515/
> For code already merged upstream, please use commit id or file
> references.
>
>> We can't directly use that implementation. Reasons:
>> 1. For DSI we use AUX register as well to write which is not the case
>> for DDI. We need to add multiple INTEL_OUTPUT_DSI
>> checks .
>> 2. DSI specific icl_combo_phy_ddi_buf_trans not added in intel_ddi.c
>> which will be used while doing vswing programming
>> 3. intel_ddi_dp_level doesn't support "level" calculation for DSI.
>>
>> Also in past we had similar discussion (with Jani N) to keep DSI
>> specific entries/code in DSI encoder.
>>
>> Jani N whats the suggestion here??
> Let's go with the slightly duplicated code, at least for now to get this
> merged. This is tedious stuff to review, and combining that with merging
> to DP/HDMI buf programming makes it unnecessarily hard. We can refactor
> afterwards as needed.
>
> BR,
> Jani.

Thanks for clarification Jani.

Regards,
Madhav

>
>
>> Regards,
>> Madhav
>>
>>> Thanks,
>>> Vandita
>>>
>>>> +static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
>>>> +{
>>>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>>> +	u32 tmp;
>>>> +	enum port port;
>>>> +
>>>> +	/* Step C.1:clear common keeper enable bit */
>>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>>> +		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
>>>> +		tmp &= ~COMMON_KEEPER_EN;
>>>> +		I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
>>>> +		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
>>>> +		tmp &= ~COMMON_KEEPER_EN;
>>>> +		I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
>>>> +	}
>>>> +
>>>> +	/*
>>>> +	 * Step C.3: Set SUS Clock Config bitfield to 11b
>>>> +	 * Note: Step C.2 (loadgen select program) is done
>>>> +	 * as part of lane phy sequence configuration
>>>> +	 */
>>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>>> +		tmp = I915_READ(ICL_PORT_CL_DW5(port));
>>>> +		tmp |= SUS_CLOCK_CONFIG;
>>>> +		I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
>>>> +	}
>>>> +
>>>> +	/* Step C.4: Clear training enable to change swing values */
>>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>>> +		tmp &= ~TX_TRAINING_EN;
>>>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>>> +		tmp &= ~TX_TRAINING_EN;
>>>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>>> +	}
>>>> +
>>>> +	/* Step C.5: Program swing and de-emphasis */
>>>> +	dsi_program_swing_and_deemphasis(encoder);
>>>> +
>>>> +	/* Step: C.6: Set training enable to trigger update */
>>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>>> +		tmp |= TX_TRAINING_EN;
>>>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>>> +		tmp |= TX_TRAINING_EN;
>>>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>>> +	}
>>>> +}
>>>> +
>>>>    static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>>>    {
>>>>    	/* step 4a: power up all lanes of the DDI used by DSI */
>>>> @@ -147,6 +258,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>>>    
>>>>    	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
>>>>    	gen11_dsi_config_phy_lanes_sequence(encoder);
>>>> +
>>>> +	/* step 4c: configure voltage swing and skew */
>>>> +	gen11_dsi_voltage_swing_program_seq(encoder);
>>>>    }
>>>>    
>>>>    static void __attribute__((unused))

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^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 00/13] ICELAKE DSI DRIVER
  2018-09-12  6:16   ` Madhav Chauhan
@ 2018-09-12  7:31     ` Jani Nikula
  0 siblings, 0 replies; 63+ messages in thread
From: Jani Nikula @ 2018-09-12  7:31 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Wed, 12 Sep 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 9/12/2018 1:05 AM, Jani Nikula wrote:
>> On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>>>  From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to
>>> GPU/Display Engine and same could be extended for future Intel platforms as well.
>>> DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification.
>>>
>>> So, a new DSI driver has been added inside I915.
>>>
>>> Given below patches are the part of new DSI driver which implements BSPEC
>>> sequence till transcoder configuration. Rest of the patches published to GITHUB
>>> and latest snapshot can be downloaded using:
>>> #git clone https://github.com/madhavchauhan/Intel-DSI-Driver.git
>>>
>>> v2: Addressed review comments from Jani N for Patches 1-6 and rebase for some
>>> other few patches.
>>> v3: Renamed intel_dsi_new.c to gen11_dsi.c as per discussion with Jani, Daniel,
>>>      Ville. Also addressed review comments for couple of patches.
>>> v4: Rename gen11_dsi.c to icl_dsi.c (Ville). No functional changes.
>>> v5: Rebase on drm-tip after initial 7 patches got merged.
>> Hi Madhav, I think there's enough review here to warrant a revised
>> set. I regret I haven't been able to review this earlier, and I'm now
>> throwing the ball back in your court... with the added pressure that I'd
>> really like to get this merged for v4.20. Which means the deadline for
>> merging is about 1½ weeks away. Is there any chance?
>
> Agree, i will publish next series soon.
> Do you mean to merge these 13 patches to 4.20 or the complete 
> implementation of 65 patches??

Let's start with these.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence
  2018-09-11 18:50   ` [PATCH v5 " Jani Nikula
@ 2018-09-12  9:03     ` Madhav Chauhan
  2018-09-12  9:10       ` Jani Nikula
  0 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-12  9:03 UTC (permalink / raw)
  To: Jani Nikula, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On 9/12/2018 12:20 AM, Jani Nikula wrote:
> On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>> This patch setup voltage swing before enabling
>> combo PHY DDI (shared with DSI).
>> Note that DSI voltage swing programming is for
>> high speed data buffers. HW automatically handles
>> the voltage swing for the low power data buffers.
>>
>> v2: Rebase
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> ---
>>   drivers/gpu/drm/i915/icl_dsi.c | 114 +++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 114 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> index a571339..dc16c1f 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -27,6 +27,65 @@
>>   
>>   #include "intel_dsi.h"
>>   
>> +static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> +	enum port port;
>> +	u32 tmp;
>> +	int lane;
>> +
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +
>> +		/* Bspec: set scaling mode to 0x6 */
> Today bspec says 2. Also, please don't duplicate the value in the
> comment.

Right..thanks for catching :)

>
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>> +		tmp |= SCALING_MODE_SEL(6);
>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> Like Ville said, adding a blank line between each read-modify-write
> group helps readability. Perhaps add /* DW5 */ etc. comments to group
> the, eh, groups.

Ok.

>
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>> +		tmp |= SCALING_MODE_SEL(6);
>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> Are you missing RTERM_SELECT?

Looks this was not earlier and added recently. Will program in next version.

>
> Why do you do two read-modify-writes (RMW) on both GRP and AUX, instead
> of doing all the changes at once?

Do you mean for  tmp |= TAP2_DISABLE | TAP3_DISABLE ??  If yes, because 
GRP and AUX
might contain different values and need to read them explicitly.

>
> The RMW doesn't actually clear the fields before changing them, just ORs
> more stuff on top of them, and cursor program or coeff polarity might
> contain garbage (at least in theory). The same below.

Yeah, we need to reset those bits using MASK and then do 'OR'.
Or are you suggesting something else??

>
>> +
>> +		/*
>> +		 * swing and scaling values are taken from DSI
>> +		 * table under vswing programming sequence for
>> +		 * combo phy ddi in BSPEC.
>> +		 * program swing values
>> +		 */
> Please reflow the comment.

Ok.

>
>> +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>> +		tmp |= SWING_SEL_UPPER(0x2);
>> +		tmp |= SWING_SEL_LOWER(0x2);
> This would benefit from
>
> +#define   SWING_SEL_MASK		(SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK)
> +#define   SWING_SEL(x)			(SWING_SEL_UPPER(x) | SWING_SEL_LOWER(x))
>
> in i915_reg.h. But I can look the other way and fix it myself later...
>
>> +		tmp |= RCOMP_SCALAR(0x98);
>> +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
>> +		tmp |= SWING_SEL_UPPER(0x2);
>> +		tmp |= SWING_SEL_LOWER(0x2);
>> +		tmp |= RCOMP_SCALAR(0x98);
>> +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
>> +
>> +		/* program scaling values */
>> +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
>> +		tmp |= POST_CURSOR_1(0x0);
>> +		tmp |= POST_CURSOR_2(0x0);
>> +		tmp |= CURSOR_COEFF(0x18);
> 0x3f?

Yes, now its changed to 0x3f.

>
> Again, you need to zero the fields before ORin the new values into them.

Agree.

>
>> +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
>> +
>> +		for (lane = 0; lane <= 3; lane++) {
>> +			/* Bspec: must not use GRP register for write */
> I'll take your word for it, although I've missed such a requirement.

:-)

>
>> +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
>> +			tmp |= POST_CURSOR_1(0x0);
>> +			tmp |= POST_CURSOR_2(0x0);
>> +			tmp |= CURSOR_COEFF(0x18);
> 0x3f?

Yes.

>
>> +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
>> +		}
>> +	}
>> +}
>> +
>>   static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
>>   {
>>   	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> @@ -140,6 +199,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>>   	}
>>   }
>>   
>> +static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> +	u32 tmp;
>> +	enum port port;
>> +
> The step numbering below has changed in bspec. Please update. Maybe drop
> the numbering, and use just the headings.

Ok.

Regards,
Madhav

>
> Otherwise, the bits here look ok.
>
> BR,
> Jani.
>
>> +	/* Step C.1:clear common keeper enable bit */
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
>> +		tmp &= ~COMMON_KEEPER_EN;
>> +		I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
>> +		tmp &= ~COMMON_KEEPER_EN;
>> +		I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
>> +	}
>> +
>> +	/*
>> +	 * Step C.3: Set SUS Clock Config bitfield to 11b
>> +	 * Note: Step C.2 (loadgen select program) is done
>> +	 * as part of lane phy sequence configuration
>> +	 */
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		tmp = I915_READ(ICL_PORT_CL_DW5(port));
>> +		tmp |= SUS_CLOCK_CONFIG;
>> +		I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
>> +	}
>> +
>> +	/* Step C.4: Clear training enable to change swing values */
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>> +		tmp &= ~TX_TRAINING_EN;
>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>> +		tmp &= ~TX_TRAINING_EN;
>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>> +	}
>> +
>> +	/* Step C.5: Program swing and de-emphasis */
>> +	dsi_program_swing_and_deemphasis(encoder);
>> +
>> +	/* Step: C.6: Set training enable to trigger update */
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>> +		tmp |= TX_TRAINING_EN;
>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>> +		tmp |= TX_TRAINING_EN;
>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>> +	}
>> +}
>> +
>>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>   {
>>   	/* step 4a: power up all lanes of the DDI used by DSI */
>> @@ -147,6 +258,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>   
>>   	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
>>   	gen11_dsi_config_phy_lanes_sequence(encoder);
>> +
>> +	/* step 4c: configure voltage swing and skew */
>> +	gen11_dsi_voltage_swing_program_seq(encoder);
>>   }
>>   
>>   static void __attribute__((unused))

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^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer
  2018-09-11 18:54   ` Jani Nikula
@ 2018-09-12  9:06     ` Madhav Chauhan
  2018-09-12  9:10       ` Jani Nikula
  0 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-12  9:06 UTC (permalink / raw)
  To: Jani Nikula, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On 9/12/2018 12:24 AM, Jani Nikula wrote:
> On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>> This patch enables DDI buffer by writing to DDI_BUF_CTL
>> register and wait for DDI status to be *not idle* for a
>> port.
>>
>> v2: Rebase
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> ---
>>   drivers/gpu/drm/i915/icl_dsi.c | 22 ++++++++++++++++++++++
>>   1 file changed, 22 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> index dc16c1f..41faa19 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -251,6 +251,25 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
>>   	}
>>   }
>>   
>> +static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> +	u32 tmp;
>> +	enum port port;
>> +
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>> +		tmp = I915_READ(DDI_BUF_CTL(port));
>> +		tmp |= DDI_BUF_CTL_ENABLE;
>> +		I915_WRITE(DDI_BUF_CTL(port), tmp);
>> +
>> +		if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
>> +				  DDI_BUF_IS_IDLE),
>> +				  500))
> IMO a "== 0" check reads better in wait_for_us.
>
>> +			DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
>> +	}
>> +}
>> +
>>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>   {
>>   	/* step 4a: power up all lanes of the DDI used by DSI */
>> @@ -261,6 +280,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>   
>>   	/* step 4c: configure voltage swing and skew */
>>   	gen11_dsi_voltage_swing_program_seq(encoder);
>> +
>> +	/* step 4d: enable DDI buffer */
> Alas, this is step 4e now, and you have a new 4d to take care of for
> B0+.

Yes. Will remove  step hardcoding  comments from patch.

Regards,
Madhav

>
> Regardless,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>> +	gen11_dsi_enable_ddi_buffer(encoder);
>>   }
>>   
>>   static void __attribute__((unused))

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^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence
  2018-09-12  9:03     ` Madhav Chauhan
@ 2018-09-12  9:10       ` Jani Nikula
  0 siblings, 0 replies; 63+ messages in thread
From: Jani Nikula @ 2018-09-12  9:10 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Wed, 12 Sep 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 9/12/2018 12:20 AM, Jani Nikula wrote:
>> On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>>> This patch setup voltage swing before enabling
>>> combo PHY DDI (shared with DSI).
>>> Note that DSI voltage swing programming is for
>>> high speed data buffers. HW automatically handles
>>> the voltage swing for the low power data buffers.
>>>
>>> v2: Rebase
>>>
>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/icl_dsi.c | 114 +++++++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 114 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>>> index a571339..dc16c1f 100644
>>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>>> @@ -27,6 +27,65 @@
>>>   
>>>   #include "intel_dsi.h"
>>>   
>>> +static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
>>> +{
>>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>> +	enum port port;
>>> +	u32 tmp;
>>> +	int lane;
>>> +
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +
>>> +		/* Bspec: set scaling mode to 0x6 */
>> Today bspec says 2. Also, please don't duplicate the value in the
>> comment.
>
> Right..thanks for catching :)
>
>>
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>> +		tmp |= SCALING_MODE_SEL(6);
>>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>> Like Ville said, adding a blank line between each read-modify-write
>> group helps readability. Perhaps add /* DW5 */ etc. comments to group
>> the, eh, groups.
>
> Ok.
>
>>
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>> +		tmp |= SCALING_MODE_SEL(6);
>>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
>>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>> +		tmp |= TAP2_DISABLE | TAP3_DISABLE;
>>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>> Are you missing RTERM_SELECT?
>
> Looks this was not earlier and added recently. Will program in next version.
>
>>
>> Why do you do two read-modify-writes (RMW) on both GRP and AUX, instead
>> of doing all the changes at once?
>
> Do you mean for  tmp |= TAP2_DISABLE | TAP3_DISABLE ??  If yes, because 
> GRP and AUX
> might contain different values and need to read them explicitly.

No, I mean first you RMW scaling mode for GRP and AUX, then you do
TAP2/3 disable for GRP and AUX. Why not scaling mode *and* TAP2/3
disable in one go, for GRP and AUX separately of course.

>
>>
>> The RMW doesn't actually clear the fields before changing them, just ORs
>> more stuff on top of them, and cursor program or coeff polarity might
>> contain garbage (at least in theory). The same below.
>
> Yeah, we need to reset those bits using MASK and then do 'OR'.

Yes.

> Or are you suggesting something else??

No, that's just it.

BR,
Jani.

>
>>
>>> +
>>> +		/*
>>> +		 * swing and scaling values are taken from DSI
>>> +		 * table under vswing programming sequence for
>>> +		 * combo phy ddi in BSPEC.
>>> +		 * program swing values
>>> +		 */
>> Please reflow the comment.
>
> Ok.
>
>>
>>> +		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>>> +		tmp |= SWING_SEL_UPPER(0x2);
>>> +		tmp |= SWING_SEL_LOWER(0x2);
>> This would benefit from
>>
>> +#define   SWING_SEL_MASK		(SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK)
>> +#define   SWING_SEL(x)			(SWING_SEL_UPPER(x) | SWING_SEL_LOWER(x))
>>
>> in i915_reg.h. But I can look the other way and fix it myself later...
>>
>>> +		tmp |= RCOMP_SCALAR(0x98);
>>> +		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
>>> +		tmp |= SWING_SEL_UPPER(0x2);
>>> +		tmp |= SWING_SEL_LOWER(0x2);
>>> +		tmp |= RCOMP_SCALAR(0x98);
>>> +		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
>>> +
>>> +		/* program scaling values */
>>> +		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
>>> +		tmp |= POST_CURSOR_1(0x0);
>>> +		tmp |= POST_CURSOR_2(0x0);
>>> +		tmp |= CURSOR_COEFF(0x18);
>> 0x3f?
>
> Yes, now its changed to 0x3f.
>
>>
>> Again, you need to zero the fields before ORin the new values into them.
>
> Agree.
>
>>
>>> +		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
>>> +
>>> +		for (lane = 0; lane <= 3; lane++) {
>>> +			/* Bspec: must not use GRP register for write */
>> I'll take your word for it, although I've missed such a requirement.
>
> :-)
>
>>
>>> +			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
>>> +			tmp |= POST_CURSOR_1(0x0);
>>> +			tmp |= POST_CURSOR_2(0x0);
>>> +			tmp |= CURSOR_COEFF(0x18);
>> 0x3f?
>
> Yes.
>
>>
>>> +			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
>>> +		}
>>> +	}
>>> +}
>>> +
>>>   static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
>>>   {
>>>   	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>> @@ -140,6 +199,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>>>   	}
>>>   }
>>>   
>>> +static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
>>> +{
>>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>> +	u32 tmp;
>>> +	enum port port;
>>> +
>> The step numbering below has changed in bspec. Please update. Maybe drop
>> the numbering, and use just the headings.
>
> Ok.
>
> Regards,
> Madhav
>
>>
>> Otherwise, the bits here look ok.
>>
>> BR,
>> Jani.
>>
>>> +	/* Step C.1:clear common keeper enable bit */
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
>>> +		tmp &= ~COMMON_KEEPER_EN;
>>> +		I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
>>> +		tmp &= ~COMMON_KEEPER_EN;
>>> +		I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
>>> +	}
>>> +
>>> +	/*
>>> +	 * Step C.3: Set SUS Clock Config bitfield to 11b
>>> +	 * Note: Step C.2 (loadgen select program) is done
>>> +	 * as part of lane phy sequence configuration
>>> +	 */
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +		tmp = I915_READ(ICL_PORT_CL_DW5(port));
>>> +		tmp |= SUS_CLOCK_CONFIG;
>>> +		I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
>>> +	}
>>> +
>>> +	/* Step C.4: Clear training enable to change swing values */
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>> +		tmp &= ~TX_TRAINING_EN;
>>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>> +		tmp &= ~TX_TRAINING_EN;
>>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>> +	}
>>> +
>>> +	/* Step C.5: Program swing and de-emphasis */
>>> +	dsi_program_swing_and_deemphasis(encoder);
>>> +
>>> +	/* Step: C.6: Set training enable to trigger update */
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>> +		tmp |= TX_TRAINING_EN;
>>> +		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>> +		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>> +		tmp |= TX_TRAINING_EN;
>>> +		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>> +	}
>>> +}
>>> +
>>>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>>   {
>>>   	/* step 4a: power up all lanes of the DDI used by DSI */
>>> @@ -147,6 +258,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>>   
>>>   	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
>>>   	gen11_dsi_config_phy_lanes_sequence(encoder);
>>> +
>>> +	/* step 4c: configure voltage swing and skew */
>>> +	gen11_dsi_voltage_swing_program_seq(encoder);
>>>   }
>>>   
>>>   static void __attribute__((unused))
>

-- 
Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer
  2018-09-12  9:06     ` Madhav Chauhan
@ 2018-09-12  9:10       ` Jani Nikula
  0 siblings, 0 replies; 63+ messages in thread
From: Jani Nikula @ 2018-09-12  9:10 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Wed, 12 Sep 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 9/12/2018 12:24 AM, Jani Nikula wrote:
>> On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>>> This patch enables DDI buffer by writing to DDI_BUF_CTL
>>> register and wait for DDI status to be *not idle* for a
>>> port.
>>>
>>> v2: Rebase
>>>
>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/icl_dsi.c | 22 ++++++++++++++++++++++
>>>   1 file changed, 22 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>>> index dc16c1f..41faa19 100644
>>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>>> @@ -251,6 +251,25 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
>>>   	}
>>>   }
>>>   
>>> +static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
>>> +{
>>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>> +	u32 tmp;
>>> +	enum port port;
>>> +
>>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>> +		tmp = I915_READ(DDI_BUF_CTL(port));
>>> +		tmp |= DDI_BUF_CTL_ENABLE;
>>> +		I915_WRITE(DDI_BUF_CTL(port), tmp);
>>> +
>>> +		if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
>>> +				  DDI_BUF_IS_IDLE),
>>> +				  500))
>> IMO a "== 0" check reads better in wait_for_us.
>>
>>> +			DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
>>> +	}
>>> +}
>>> +
>>>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>>   {
>>>   	/* step 4a: power up all lanes of the DDI used by DSI */
>>> @@ -261,6 +280,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>>>   
>>>   	/* step 4c: configure voltage swing and skew */
>>>   	gen11_dsi_voltage_swing_program_seq(encoder);
>>> +
>>> +	/* step 4d: enable DDI buffer */
>> Alas, this is step 4e now, and you have a new 4d to take care of for
>> B0+.
>
> Yes. Will remove  step hardcoding  comments from patch.

It's unfortunate; the comments do help in review *now* but alas they
might confuse the reader tomorrow. :(

BR,
Jani.


>
> Regards,
> Madhav
>
>>
>> Regardless,
>>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>
>>
>>> +	gen11_dsi_enable_ddi_buffer(encoder);
>>>   }
>>>   
>>>   static void __attribute__((unused))
>

-- 
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^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 06/13] drm/i915/icl: Define data/clock lanes dphy timing registers
  2018-09-11 19:14   ` Jani Nikula
@ 2018-09-12  9:11     ` Madhav Chauhan
  0 siblings, 0 replies; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-12  9:11 UTC (permalink / raw)
  To: Jani Nikula, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On 9/12/2018 12:44 AM, Jani Nikula wrote:
> On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>> This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
>> DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
>> dphy programming.
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 40 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 6129372..0dbdd57 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -10075,6 +10075,46 @@ enum skl_power_gate {
>>   						   _ICL_DSI_T_INIT_MASTER_0,\
>>   						   _ICL_DSI_T_INIT_MASTER_1)
>>   
>> +#define _DPHY_CLK_TIMING_PARAM_0	0x162180
>> +#define _DPHY_CLK_TIMING_PARAM_1	0x6c180
>> +#define DPHY_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
>> +						   _DPHY_CLK_TIMING_PARAM_0,\
>> +						   _DPHY_CLK_TIMING_PARAM_1)
>> +#define _DSI_CLK_TIMING_PARAM_0		0x6b080
>> +#define _DSI_CLK_TIMING_PARAM_1		0x6b880
>> +#define DSI_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
>> +						   _DSI_CLK_TIMING_PARAM_0,\
>> +						   _DSI_CLK_TIMING_PARAM_1)
>> +#define  CLK_PREP_OVERRIDE		(1 << 31)
>> +#define  CLK_PREP_TIME(x)		(x << 28)
>> +#define  CLK_ZERO_OVERRIDE		(1 << 27)
>> +#define  CLK_ZERO_TIME(x)		(x << 20)
>> +#define  CLK_PRE_OVERRIDE		(1 << 19)
>> +#define  CLK_PRE_TIME(x)		(x << 16)
>> +#define  CLK_POST_OVERRIDE		(1 << 15)
>> +#define  CLK_POST_TIME(x)		(x << 8)
>> +#define  CLK_TRAIL_OVERRIDE		(1 << 7)
>> +#define  CLK_TRAIL_TIME(x)		(x << 0)
> I would prefer we stuck to the convention of defining _SHIFT and _MASK
> macros for the bitfields. Even if the above style has started to creep
> in without proper discussion. (I approve of the function-like macros for
> things that aren't straight shifts; stuff with split bitfields or
> calculations.)
>
> No matter what, you need to wrap the macro arguments in parens!
>
> Also, please don't do your own abbreviations or renames of the field
> names when the bspec name is short/good enough.

Ok. I will add the mask and wrap the arguments in parens.
Also will recheck the names as per BSPEC.

Regards,
Madhav

>
>> +
>> +#define _DPHY_DATA_TIMING_PARAM_0	0x162184
>> +#define _DPHY_DATA_TIMING_PARAM_1	0x6c184
>> +#define DPHY_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
>> +						   _DPHY_DATA_TIMING_PARAM_0,\
>> +						   _DPHY_DATA_TIMING_PARAM_1)
>> +#define _DSI_DATA_TIMING_PARAM_0	0x6B084
>> +#define _DSI_DATA_TIMING_PARAM_1	0x6B884
>> +#define DSI_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
>> +						   _DSI_DATA_TIMING_PARAM_0,\
>> +						   _DSI_DATA_TIMING_PARAM_1)
>> +#define  HS_PREP_OVERRIDE		(1 << 31)
>> +#define  HS_PREP_TIME(x)		(x << 24)
>> +#define  HS_ZERO_OVERRIDE		(1 << 23)
>> +#define  HS_ZERO_TIME(x)		(x << 16)
>> +#define  HS_TRAIL_OVERRIDE		(1 << 15)
>> +#define  HS_TRAIL_TIME(x)		(x << 8)
>> +#define  HS_EXIT_OVERRIDE		(1 << 7)
>> +#define  HS_EXIT_TIME(x)		(x << 0)
> Same as above.
>
> The register offsets and shifts etc. look ok.
>
> BR,
> Jani.
>
>> +
>>   /* bits 31:0 */
>>   #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
>>   #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

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^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers
  2018-09-11 19:23   ` Jani Nikula
@ 2018-09-12  9:13     ` Madhav Chauhan
  0 siblings, 0 replies; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-12  9:13 UTC (permalink / raw)
  To: Jani Nikula, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On 9/12/2018 12:53 AM, Jani Nikula wrote:
> On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>> This patch defines DSI_TA_TIMING_PARAM and
>> DPHY_TA_TIMING_PARAM registers used in
>> dphy programming.
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 0dbdd57..1d13ba9 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -10115,6 +10115,20 @@ enum skl_power_gate {
>>   #define  HS_EXIT_OVERRIDE		(1 << 7)
>>   #define  HS_EXIT_TIME(x)		(x << 0)
>>   
>> +#define _DPHY_TA_TIMING_PARAM_0		0x162188
>> +#define _DPHY_TA_TIMING_PARAM_1		0x6c188
>> +#define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
>> +						   _DPHY_TA_TIMING_PARAM_0,\
>> +						   _DPHY_TA_TIMING_PARAM_1)
>> +#define _DSI_TA_TIMING_PARAM_0		0x6b098
>> +#define _DSI_TA_TIMING_PARAM_1		0x6b898
>> +#define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
>> +						   _DSI_TA_TIMING_PARAM_0,\
>> +						   _DSI_TA_TIMING_PARAM_1)
>> +#define  TA_SURE_OVERRIDE		(1 << 31)
>> +#define  TA_SURE_TIME(x)		(x << 16)
>> +#define  TA_SURE_TIME_MASK		(0x1f << 16)
> Please stick to _SHIFT. And in any case macro arguments need parens
> around them.
>
> Please add all the fields for the registers in one go.

Ok. Thanks!!

Regards,
Madhav

>
> BR,
> Jani.
>
>
>> +
>>   /* bits 31:0 */
>>   #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
>>   #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 09/13] drm/i915/icl: Program TA_TIMING_PARAM registers
  2018-09-11 19:26       ` Jani Nikula
@ 2018-09-12  9:25         ` Madhav Chauhan
  2018-09-12  9:39           ` Jani Nikula
  0 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-12  9:25 UTC (permalink / raw)
  To: Jani Nikula, Ville Syrjälä
  Cc: intel-gfx, Zanoni, Paulo R, Vivi, Rodrigo

On 9/12/2018 12:56 AM, Jani Nikula wrote:
> On Fri, 20 Jul 2018, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>>> -----Original Message-----
>>> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>>> Sent: Thursday, July 19, 2018 9:51 PM
>>> To: Chauhan, Madhav <madhav.chauhan@intel.com>
>>> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
>>> Zanoni, Paulo R <paulo.r.zanoni@intel.com>; Vivi, Rodrigo
>>> <rodrigo.vivi@intel.com>
>>> Subject: Re: [Intel-gfx] [PATCH v5 09/13] drm/i915/icl: Program
>>> TA_TIMING_PARAM registers
>>>
>>> On Tue, Jul 10, 2018 at 03:10:10PM +0530, Madhav Chauhan wrote:
>>>> This patch programs D-PHY timing parameters for the bus turn around
>>>> flow(in escape clocks) only if dsi link frequency <=800 MHz using
>>>> DPHY_TA_TIMING_PARAM and its identical register
>>> DSI_TA_TIMING_PARAM
>>>> (inside DSI Controller within the Display Core).
>>>>
>>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/i915/icl_dsi.c       | 21 +++++++++++++++++++++
>>>>   drivers/gpu/drm/i915/intel_dsi.h     |  1 +
>>>>   drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
>>>>   3 files changed, 23 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>>>> b/drivers/gpu/drm/i915/icl_dsi.c index 832772d..8fd5284 100644
>>>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>>>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>>>> @@ -302,6 +302,27 @@ static void gen11_dsi_setup_dphy_timings(struct
>>> intel_encoder *encoder)
>>>>   		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
>>>>   			   intel_dsi->dphy_data_lane_reg);
>>>>   	}
>>>> +
>>>> +	/*
>>>> +	 * If DSI link operating at or below an 800 MHz,
>>>> +	 * TA_SURE should be override and programmed to
>>>> +	 * a value '0' inside TA_PARAM_REGISTERS otherwise
>>>> +	 * leave all fields at HW default values.
>>>> +	 */
>>>> +	if (intel_dsi->bitrate_khz <= KHz(800)) {
>>> The KHz(800) confuses me. My brain thinks this value is 800 kHz when it's
>>> not. So I'd write it without the KHz() macro.
>> Ok. Initially I wrote without using KHz macro, but got comment to use KHz macro :)
> Did I? Oh well. Go with 800000.

Ok  :)

>
> Please don't add additional state with intel_dsi->bitrate_khz when you
> can calculate the bitrate at any time. Add a function to do it if you
> like, and use it in both places.

Ok. But we will reusing this bitrate(same value) in multiple place. 
Shouldn't
we cache it rather than calculating everytime??

Regards,
Madhav

>
> BR,
> Jani.
>
>
>> Regards,
>> Madhav
>>
>>>> +		for_each_dsi_port(port, intel_dsi->ports) {
>>>> +			tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
>>>> +			tmp &= ~TA_SURE_TIME_MASK;
>>>> +			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
>>>> +			I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
>>>> +
>>>> +			/* shadow register inside display core */
>>>> +			tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
>>>> +			tmp &= ~TA_SURE_TIME_MASK;
>>>> +			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
>>>> +			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
>>>> +		}
>>>> +	}
>>>>   }
>>>>
>>>>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder
>>>> *encoder) diff --git a/drivers/gpu/drm/i915/intel_dsi.h
>>>> b/drivers/gpu/drm/i915/intel_dsi.h
>>>> index 9fd8526..25e7396 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>>> @@ -101,6 +101,7 @@ struct intel_dsi {
>>>>
>>>>   	u16 init_count;
>>>>   	u32 pclk;
>>>> +	u32 bitrate_khz;
>>>>   	u16 burst_mode_ratio;
>>>>
>>>>   	/* all delays in ms */
>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>>> b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>>> index 428290d..a9a98a4 100644
>>>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>>> @@ -589,6 +589,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi,
>>> u16 panel_id)
>>>>   	intel_dsi->pclk = pclk;
>>>>
>>>>   	bitrate = (pclk * bpp) / intel_dsi->lane_count;
>>>> +	intel_dsi->bitrate_khz = bitrate;
>>>>
>>>>   	switch (intel_dsi->escape_clk_div) {
>>>>   	case 0:
>>>> --
>>>> 2.7.4
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>> --
>>> Ville Syrjälä
>>> Intel

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^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
  2018-09-11 19:30   ` Jani Nikula
@ 2018-09-12  9:35     ` Madhav Chauhan
  2018-09-12  9:47       ` Jani Nikula
  0 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-12  9:35 UTC (permalink / raw)
  To: Jani Nikula, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On 9/12/2018 1:00 AM, Jani Nikula wrote:
> On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>> This patch defines transcoder function configuration
>> registers and its bitfields for both DSI ports.
>> Used while programming/enabling DSI transcoder.
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h | 47 +++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 47 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 62bc76e..71ce6ba 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -10134,6 +10134,53 @@ enum skl_power_gate {
>>   #define  TA_SURE_TIME(x)		(x << 16)
>>   #define  TA_SURE_TIME_MASK		(0x1f << 16)
>>   
>> +/* DSI transcoder configuration */
>> +#define _DSI_TRANS_FUNC_CONF_0		0x6b030
>> +#define _DSI_TRANS_FUNC_CONF_1		0x6b830
>> +#define DSI_TRANS_FUNC_CONF(tc)		_MMIO_DSI(tc,	\
>> +						  _DSI_TRANS_FUNC_CONF_0,\
>> +						  _DSI_TRANS_FUNC_CONF_1)
>> +#define  OP_MODE(x)			(x << 28)
>> +#define  OP_MODE_MASK			(0x3 << 28)
>> +#define  CMD_MODE_NO_GATE		0x0
>> +#define  CMD_MODE_TE_GATE		0x1
>> +#define  VIDEO_MODE_SYNC_EVENT		0x2
>> +#define  VIDEO_MODE_SYNC_PULSE		0x3
> The convention is to define macros for field values that you can OR
> directly in place instead of requiring a shift. Please stick to the
> conventions. Use _SHIFT and _MASK.
>
> We can debate the relative merits of both approaches at some point, but
> this is not the time.

Just to understand this point correctly,

#define  OP_MODE(x)			((x) << 28) is OK
but
#define  OP_MODE_MASK			(0x3 << 28) is NOT OK
and should be:
#define  OP_MODE_MASK                    0x3
#define  OP_MODE_SHIFT			 28

Regards,
Madhav

>
> BR,
> Jani.
>
>> +#define  LINK_READY			(1 << 20)
>> +#define  PIX_FMT(x)			(x << 16)
>> +#define  PIX_FMT_MASK			(0x3 << 16)
>> +#define  PIX_FMT_RGB565		0x0
>> +#define  PIX_FMT_RGB666_PACKED		0x1
>> +#define  PIX_FMT_RGB666_LOOSE		0x2
>> +#define  PIX_FMT_RGB888		0x3
>> +#define  PIX_FMT_RGB101010		0x4
>> +#define  PIX_FMT_RGB121212		0x5
>> +#define  PIX_FMT_COMPRESSED		0x6
>> +#define  BGR_TRANSMISSION		(1 << 15)
>> +#define  PIX_VIRT_CHAN(x)		(x << 12)
>> +#define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
>> +#define  PIX_BUF_THRESHOLD(x)		((x & 0x3) << 10)
>> +#define  PIX_BUF_THRESHOLD_MASK	(0x3 << 10)
>> +#define  PIX_BUF_THRESHOLD_1_4		0x0
>> +#define  PIX_BUF_THRESHOLD_1_2		0x1
>> +#define  PIX_BUF_THRESHOLD_3_4		0x2
>> +#define  PIX_BUF_THRESHOLD_FULL	0x3
>> +#define  CONTINUOUS_CLK(x)		(x << 8)
>> +#define  CONTINUOUS_CLK_MASK		(0x3 << 8)
>> +#define  CLK_ENTER_LP_AFTER_DATA	0x0
>> +#define  CLK_HS_OR_LP			0x2
>> +#define  CLK_HS_CONTINUOUS		0x3
>> +#define  LINK_CALIBRATION(x)		(x << 4)
>> +#define  LINK_CALIBRATION_MASK		(0x3 << 4)
>> +#define  CALIBRATION_DISABLED		0x0
>> +#define  CALIBRATION_ENABLED_INITIAL_ONLY	0x2
>> +#define  CALIBRATION_ENABLED_INITIAL_PERIODIC	0x3
>> +#define  S3D_ORIENTATION(x)		(x << 1)
>> +#define  S3D_ORIENTATION_MASK		(0x1 << 1)
>> +#define  S3D_ORIENTATION_PORTRAIT	0x0
>> +#define  S3D_ORIENTATION_LANDSCAPE	0x1
>> +#define  EOTP_DISABLED			(1 << 0)
>> +
>>   /* bits 31:0 */
>>   #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
>>   #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  2018-07-19 16:22   ` Ville Syrjälä
  2018-07-20  8:55     ` Chauhan, Madhav
@ 2018-09-12  9:36     ` Madhav Chauhan
  2018-09-12 18:00       ` Ville Syrjälä
  1 sibling, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-12  9:36 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx, paulo.r.zanoni, rodrigo.vivi

On 7/19/2018 9:52 PM, Ville Syrjälä wrote:
> On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
>> This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
>> DSI transcoder registers.
>>
>> Credits-to: Jani N
>>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 1d13ba9..62bc76e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9576,6 +9576,11 @@ enum skl_power_gate {
>>   #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
>>   #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
>>   
>> +/* gen11 DSI */
>> +#define _DSI_TRANS(tc, dsi0, dsi1)	(((tc) == TRANSCODER_DSI_0) ?	\
>> +					 (dsi0) : (dsi1))
> _PIPE() etc. should result in slughtly better code IIRC.

Can you please clarify on this??

Regards,
Madhav

>
>> +#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO(_DSI_TRANS(tc, dsi0, dsi1))
>> +
>>   #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
>>   #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
>>   #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
>> -- 
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 09/13] drm/i915/icl: Program TA_TIMING_PARAM registers
  2018-09-12  9:25         ` Madhav Chauhan
@ 2018-09-12  9:39           ` Jani Nikula
  0 siblings, 0 replies; 63+ messages in thread
From: Jani Nikula @ 2018-09-12  9:39 UTC (permalink / raw)
  To: Madhav Chauhan, Ville Syrjälä
  Cc: intel-gfx, Zanoni, Paulo R, Vivi, Rodrigo

On Wed, 12 Sep 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 9/12/2018 12:56 AM, Jani Nikula wrote:
>> On Fri, 20 Jul 2018, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>>>> -----Original Message-----
>>>> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>>>> Sent: Thursday, July 19, 2018 9:51 PM
>>>> To: Chauhan, Madhav <madhav.chauhan@intel.com>
>>>> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
>>>> Zanoni, Paulo R <paulo.r.zanoni@intel.com>; Vivi, Rodrigo
>>>> <rodrigo.vivi@intel.com>
>>>> Subject: Re: [Intel-gfx] [PATCH v5 09/13] drm/i915/icl: Program
>>>> TA_TIMING_PARAM registers
>>>>
>>>> On Tue, Jul 10, 2018 at 03:10:10PM +0530, Madhav Chauhan wrote:
>>>>> This patch programs D-PHY timing parameters for the bus turn around
>>>>> flow(in escape clocks) only if dsi link frequency <=800 MHz using
>>>>> DPHY_TA_TIMING_PARAM and its identical register
>>>> DSI_TA_TIMING_PARAM
>>>>> (inside DSI Controller within the Display Core).
>>>>>
>>>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>>>>> ---
>>>>>   drivers/gpu/drm/i915/icl_dsi.c       | 21 +++++++++++++++++++++
>>>>>   drivers/gpu/drm/i915/intel_dsi.h     |  1 +
>>>>>   drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
>>>>>   3 files changed, 23 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>>>>> b/drivers/gpu/drm/i915/icl_dsi.c index 832772d..8fd5284 100644
>>>>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>>>>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>>>>> @@ -302,6 +302,27 @@ static void gen11_dsi_setup_dphy_timings(struct
>>>> intel_encoder *encoder)
>>>>>   		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
>>>>>   			   intel_dsi->dphy_data_lane_reg);
>>>>>   	}
>>>>> +
>>>>> +	/*
>>>>> +	 * If DSI link operating at or below an 800 MHz,
>>>>> +	 * TA_SURE should be override and programmed to
>>>>> +	 * a value '0' inside TA_PARAM_REGISTERS otherwise
>>>>> +	 * leave all fields at HW default values.
>>>>> +	 */
>>>>> +	if (intel_dsi->bitrate_khz <= KHz(800)) {
>>>> The KHz(800) confuses me. My brain thinks this value is 800 kHz when it's
>>>> not. So I'd write it without the KHz() macro.
>>> Ok. Initially I wrote without using KHz macro, but got comment to use KHz macro :)
>> Did I? Oh well. Go with 800000.
>
> Ok  :)
>
>>
>> Please don't add additional state with intel_dsi->bitrate_khz when you
>> can calculate the bitrate at any time. Add a function to do it if you
>> like, and use it in both places.
>
> Ok. But we will reusing this bitrate(same value) in multiple place.
> Shouldn't we cache it rather than calculating everytime??

Depends. The performance impact is neglible. Caching has its own
problems, but here I suppose you don't need to invalidate it. In the
end, I think it boils down to code readability. In this case, I guess go
with what you have then.

BR,
Jani.

>
> Regards,
> Madhav
>
>>
>> BR,
>> Jani.
>>
>>
>>> Regards,
>>> Madhav
>>>
>>>>> +		for_each_dsi_port(port, intel_dsi->ports) {
>>>>> +			tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
>>>>> +			tmp &= ~TA_SURE_TIME_MASK;
>>>>> +			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
>>>>> +			I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
>>>>> +
>>>>> +			/* shadow register inside display core */
>>>>> +			tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
>>>>> +			tmp &= ~TA_SURE_TIME_MASK;
>>>>> +			tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
>>>>> +			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
>>>>> +		}
>>>>> +	}
>>>>>   }
>>>>>
>>>>>   static void gen11_dsi_enable_port_and_phy(struct intel_encoder
>>>>> *encoder) diff --git a/drivers/gpu/drm/i915/intel_dsi.h
>>>>> b/drivers/gpu/drm/i915/intel_dsi.h
>>>>> index 9fd8526..25e7396 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>>>>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>>>>> @@ -101,6 +101,7 @@ struct intel_dsi {
>>>>>
>>>>>   	u16 init_count;
>>>>>   	u32 pclk;
>>>>> +	u32 bitrate_khz;
>>>>>   	u16 burst_mode_ratio;
>>>>>
>>>>>   	/* all delays in ms */
>>>>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>>>> b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>>>> index 428290d..a9a98a4 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>>>>> @@ -589,6 +589,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi,
>>>> u16 panel_id)
>>>>>   	intel_dsi->pclk = pclk;
>>>>>
>>>>>   	bitrate = (pclk * bpp) / intel_dsi->lane_count;
>>>>> +	intel_dsi->bitrate_khz = bitrate;
>>>>>
>>>>>   	switch (intel_dsi->escape_clk_div) {
>>>>>   	case 0:
>>>>> --
>>>>> 2.7.4
>>>>>
>>>>> _______________________________________________
>>>>> Intel-gfx mailing list
>>>>> Intel-gfx@lists.freedesktop.org
>>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>> --
>>>> Ville Syrjälä
>>>> Intel
>

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
  2018-09-12  9:35     ` Madhav Chauhan
@ 2018-09-12  9:47       ` Jani Nikula
  0 siblings, 0 replies; 63+ messages in thread
From: Jani Nikula @ 2018-09-12  9:47 UTC (permalink / raw)
  To: Madhav Chauhan, intel-gfx; +Cc: paulo.r.zanoni, rodrigo.vivi

On Wed, 12 Sep 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 9/12/2018 1:00 AM, Jani Nikula wrote:
>> On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>> The convention is to define macros for field values that you can OR
>> directly in place instead of requiring a shift. Please stick to the
>> conventions. Use _SHIFT and _MASK.
>>
>> We can debate the relative merits of both approaches at some point, but
>> this is not the time.
>
> Just to understand this point correctly,
>
> #define  OP_MODE(x)			((x) << 28) is OK

This is acceptable when the values for the field are *not* defined as
separate macros. The convention is that the values for fields are
defined already shifted in place, and that would conflict.

> but
> #define  OP_MODE_MASK			(0x3 << 28) is NOT OK

This is okay and recommended.

> and should be:
> #define  OP_MODE_MASK                    0x3

This is not okay.

> #define  OP_MODE_SHIFT			 28

This is okay.

Please read the big comment with examples near the top of i915_reg.h,
and let me know which part is not clear from that.

BR,
Jani.



-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  2018-09-12  9:36     ` Madhav Chauhan
@ 2018-09-12 18:00       ` Ville Syrjälä
  2018-09-14  6:12         ` Madhav Chauhan
  0 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjälä @ 2018-09-12 18:00 UTC (permalink / raw)
  To: Madhav Chauhan; +Cc: Jani Nikula, intel-gfx, paulo.r.zanoni, rodrigo.vivi

On Wed, Sep 12, 2018 at 03:06:41PM +0530, Madhav Chauhan wrote:
> On 7/19/2018 9:52 PM, Ville Syrjälä wrote:
> > On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
> >> This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
> >> DSI transcoder registers.
> >>
> >> Credits-to: Jani N
> >>
> >> Cc: Jani Nikula <jani.nikula@intel.com>
> >> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> >>   1 file changed, 5 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 1d13ba9..62bc76e 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -9576,6 +9576,11 @@ enum skl_power_gate {
> >>   #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
> >>   #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
> >>   
> >> +/* gen11 DSI */
> >> +#define _DSI_TRANS(tc, dsi0, dsi1)	(((tc) == TRANSCODER_DSI_0) ?	\
> >> +					 (dsi0) : (dsi1))
> > _PIPE() etc. should result in slughtly better code IIRC.
> 
> Can you please clarify on this??

Plenty of examples in i915_reg.h for using _PIPE().

> 
> Regards,
> Madhav
> 
> >
> >> +#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO(_DSI_TRANS(tc, dsi0, dsi1))
> >> +
> >>   #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
> >>   #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
> >>   #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
> >> -- 
> >> 2.7.4
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  2018-09-12 18:00       ` Ville Syrjälä
@ 2018-09-14  6:12         ` Madhav Chauhan
  2018-09-14 12:25           ` Ville Syrjälä
  0 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-14  6:12 UTC (permalink / raw)
  To: Ville Syrjälä
  Cc: Jani Nikula, intel-gfx, paulo.r.zanoni, rodrigo.vivi

On 9/12/2018 11:30 PM, Ville Syrjälä wrote:
> On Wed, Sep 12, 2018 at 03:06:41PM +0530, Madhav Chauhan wrote:
>> On 7/19/2018 9:52 PM, Ville Syrjälä wrote:
>>> On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
>>>> This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
>>>> DSI transcoder registers.
>>>>
>>>> Credits-to: Jani N
>>>>
>>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/i915_reg.h | 5 +++++
>>>>    1 file changed, 5 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>> index 1d13ba9..62bc76e 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -9576,6 +9576,11 @@ enum skl_power_gate {
>>>>    #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
>>>>    #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
>>>>    
>>>> +/* gen11 DSI */
>>>> +#define _DSI_TRANS(tc, dsi0, dsi1)	(((tc) == TRANSCODER_DSI_0) ?	\
>>>> +					 (dsi0) : (dsi1))
>>> _PIPE() etc. should result in slughtly better code IIRC.
>> Can you please clarify on this??
> Plenty of examples in i915_reg.h for using _PIPE().

I meant what are advantages of using _PIPE against the current approach??

Also if we use _PIPE, are you suggesting something below:
#define _MMIO_DSI(tc, dsi0, dsi1)    _MMIO_PIPE(tc, dsi0, dsi1))
Using above macro we will get wrong DSI addresses as TRANS_DSI_0 value is 5.

Or do you mean to use PORT instead of TRANS_DSI_0/1 to _MMIO_DSI??

Regards,
Madhav

>
>> Regards,
>> Madhav
>>
>>>> +#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO(_DSI_TRANS(tc, dsi0, dsi1))
>>>> +
>>>>    #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
>>>>    #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
>>>>    #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
>>>> -- 
>>>> 2.7.4
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  2018-09-14  6:12         ` Madhav Chauhan
@ 2018-09-14 12:25           ` Ville Syrjälä
  2018-09-14 13:06             ` Madhav Chauhan
  0 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjälä @ 2018-09-14 12:25 UTC (permalink / raw)
  To: Madhav Chauhan; +Cc: Jani Nikula, intel-gfx, paulo.r.zanoni, rodrigo.vivi

On Fri, Sep 14, 2018 at 11:42:33AM +0530, Madhav Chauhan wrote:
> On 9/12/2018 11:30 PM, Ville Syrjälä wrote:
> > On Wed, Sep 12, 2018 at 03:06:41PM +0530, Madhav Chauhan wrote:
> >> On 7/19/2018 9:52 PM, Ville Syrjälä wrote:
> >>> On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
> >>>> This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
> >>>> DSI transcoder registers.
> >>>>
> >>>> Credits-to: Jani N
> >>>>
> >>>> Cc: Jani Nikula <jani.nikula@intel.com>
> >>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> >>>> ---
> >>>>    drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> >>>>    1 file changed, 5 insertions(+)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >>>> index 1d13ba9..62bc76e 100644
> >>>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>>> @@ -9576,6 +9576,11 @@ enum skl_power_gate {
> >>>>    #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
> >>>>    #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
> >>>>    
> >>>> +/* gen11 DSI */
> >>>> +#define _DSI_TRANS(tc, dsi0, dsi1)	(((tc) == TRANSCODER_DSI_0) ?	\
> >>>> +					 (dsi0) : (dsi1))
> >>> _PIPE() etc. should result in slughtly better code IIRC.
> >> Can you please clarify on this??
> > Plenty of examples in i915_reg.h for using _PIPE().
> 
> I meant what are advantages of using _PIPE against the current approach??

Uniform style, better generated code usually (look at the generated asm
to verify).

> 
> Also if we use _PIPE, are you suggesting something below:
> #define _MMIO_DSI(tc, dsi0, dsi1)    _MMIO_PIPE(tc, dsi0, dsi1))
> Using above macro we will get wrong DSI addresses as TRANS_DSI_0 value is 5.

(tc)-TRANSCODER_DSI_0

> 
> Or do you mean to use PORT instead of TRANS_DSI_0/1 to _MMIO_DSI??
> 
> Regards,
> Madhav
> 
> >
> >> Regards,
> >> Madhav
> >>
> >>>> +#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO(_DSI_TRANS(tc, dsi0, dsi1))
> >>>> +
> >>>>    #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
> >>>>    #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
> >>>>    #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
> >>>> -- 
> >>>> 2.7.4
> >>>>
> >>>> _______________________________________________
> >>>> Intel-gfx mailing list
> >>>> Intel-gfx@lists.freedesktop.org
> >>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  2018-09-14 12:25           ` Ville Syrjälä
@ 2018-09-14 13:06             ` Madhav Chauhan
  2018-09-14 13:27               ` Madhav Chauhan
  0 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-14 13:06 UTC (permalink / raw)
  To: Ville Syrjälä
  Cc: Jani Nikula, intel-gfx, paulo.r.zanoni, rodrigo.vivi

On 9/14/2018 5:55 PM, Ville Syrjälä wrote:
> On Fri, Sep 14, 2018 at 11:42:33AM +0530, Madhav Chauhan wrote:
>> On 9/12/2018 11:30 PM, Ville Syrjälä wrote:
>>> On Wed, Sep 12, 2018 at 03:06:41PM +0530, Madhav Chauhan wrote:
>>>> On 7/19/2018 9:52 PM, Ville Syrjälä wrote:
>>>>> On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
>>>>>> This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
>>>>>> DSI transcoder registers.
>>>>>>
>>>>>> Credits-to: Jani N
>>>>>>
>>>>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>>>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>>>>>> ---
>>>>>>     drivers/gpu/drm/i915/i915_reg.h | 5 +++++
>>>>>>     1 file changed, 5 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>>>> index 1d13ba9..62bc76e 100644
>>>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>>>> @@ -9576,6 +9576,11 @@ enum skl_power_gate {
>>>>>>     #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
>>>>>>     #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
>>>>>>     
>>>>>> +/* gen11 DSI */
>>>>>> +#define _DSI_TRANS(tc, dsi0, dsi1)	(((tc) == TRANSCODER_DSI_0) ?	\
>>>>>> +					 (dsi0) : (dsi1))
>>>>> _PIPE() etc. should result in slughtly better code IIRC.
>>>> Can you please clarify on this??
>>> Plenty of examples in i915_reg.h for using _PIPE().
>> I meant what are advantages of using _PIPE against the current approach??
> Uniform style, better generated code usually (look at the generated asm
> to verify).

Got it.

>
>> Also if we use _PIPE, are you suggesting something below:
>> #define _MMIO_DSI(tc, dsi0, dsi1)    _MMIO_PIPE(tc, dsi0, dsi1))
>> Using above macro we will get wrong DSI addresses as TRANS_DSI_0 value is 5.
> (tc)-TRANSCODER_DSI_0

Thanks for clarification Ville, will use _PIPE().

Regards,
Madhav

>
>> Or do you mean to use PORT instead of TRANS_DSI_0/1 to _MMIO_DSI??
>>
>> Regards,
>> Madhav
>>
>>>> Regards,
>>>> Madhav
>>>>
>>>>>> +#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO(_DSI_TRANS(tc, dsi0, dsi1))
>>>>>> +
>>>>>>     #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
>>>>>>     #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
>>>>>>     #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
>>>>>> -- 
>>>>>> 2.7.4
>>>>>>
>>>>>> _______________________________________________
>>>>>> Intel-gfx mailing list
>>>>>> Intel-gfx@lists.freedesktop.org
>>>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  2018-09-14 13:06             ` Madhav Chauhan
@ 2018-09-14 13:27               ` Madhav Chauhan
  2018-09-14 13:41                 ` Ville Syrjälä
  0 siblings, 1 reply; 63+ messages in thread
From: Madhav Chauhan @ 2018-09-14 13:27 UTC (permalink / raw)
  To: Ville Syrjälä
  Cc: Jani Nikula, intel-gfx, paulo.r.zanoni, rodrigo.vivi

On 9/14/2018 6:36 PM, Madhav Chauhan wrote:
> On 9/14/2018 5:55 PM, Ville Syrjälä wrote:
>> On Fri, Sep 14, 2018 at 11:42:33AM +0530, Madhav Chauhan wrote:
>>> On 9/12/2018 11:30 PM, Ville Syrjälä wrote:
>>>> On Wed, Sep 12, 2018 at 03:06:41PM +0530, Madhav Chauhan wrote:
>>>>> On 7/19/2018 9:52 PM, Ville Syrjälä wrote:
>>>>>> On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
>>>>>>> This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
>>>>>>> DSI transcoder registers.
>>>>>>>
>>>>>>> Credits-to: Jani N
>>>>>>>
>>>>>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>>>>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>>>>>>> ---
>>>>>>>     drivers/gpu/drm/i915/i915_reg.h | 5 +++++
>>>>>>>     1 file changed, 5 insertions(+)
>>>>>>>
>>>>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>>>>>>> b/drivers/gpu/drm/i915/i915_reg.h
>>>>>>> index 1d13ba9..62bc76e 100644
>>>>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>>>>> @@ -9576,6 +9576,11 @@ enum skl_power_gate {
>>>>>>>     #define _MIPI_PORT(port, a, c)    (((port) == PORT_A) ? a : 
>>>>>>> c)    /* ports A and C only */
>>>>>>>     #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
>>>>>>>     +/* gen11 DSI */
>>>>>>> +#define _DSI_TRANS(tc, dsi0, dsi1)    (((tc) == 
>>>>>>> TRANSCODER_DSI_0) ?    \
>>>>>>> +                     (dsi0) : (dsi1))
>>>>>> _PIPE() etc. should result in slughtly better code IIRC.
>>>>> Can you please clarify on this??
>>>> Plenty of examples in i915_reg.h for using _PIPE().
>>> I meant what are advantages of using _PIPE against the current 
>>> approach??
>> Uniform style, better generated code usually (look at the generated asm
>> to verify).
>
> Got it.
>
>>
>>> Also if we use _PIPE, are you suggesting something below:
>>> #define _MMIO_DSI(tc, dsi0, dsi1)    _MMIO_PIPE(tc, dsi0, dsi1))
>>> Using above macro we will get wrong DSI addresses as TRANS_DSI_0 
>>> value is 5.
>> (tc)-TRANSCODER_DSI_0

Can we use _MMIO_TRANS here, _TRANS & _PIPE have same definition??
That will emphasize that these registers are transcoder specific not the 
PIPE.

Regards,
Madhav

>
> Thanks for clarification Ville, will use _PIPE().
>
> Regards,
> Madhav
>
>>
>>> Or do you mean to use PORT instead of TRANS_DSI_0/1 to _MMIO_DSI??
>>>
>>> Regards,
>>> Madhav
>>>
>>>>> Regards,
>>>>> Madhav
>>>>>
>>>>>>> +#define _MMIO_DSI(tc, dsi0, dsi1)    _MMIO(_DSI_TRANS(tc, dsi0, 
>>>>>>> dsi1))
>>>>>>> +
>>>>>>>     #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
>>>>>>>     #define  GLK_TX_ESC_CLK_DIV1_MASK            0x3FF
>>>>>>>     #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
>>>>>>> -- 
>>>>>>> 2.7.4
>>>>>>>
>>>>>>> _______________________________________________
>>>>>>> Intel-gfx mailing list
>>>>>>> Intel-gfx@lists.freedesktop.org
>>>>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
* Re: [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  2018-09-14 13:27               ` Madhav Chauhan
@ 2018-09-14 13:41                 ` Ville Syrjälä
  0 siblings, 0 replies; 63+ messages in thread
From: Ville Syrjälä @ 2018-09-14 13:41 UTC (permalink / raw)
  To: Madhav Chauhan; +Cc: Jani Nikula, intel-gfx, paulo.r.zanoni, rodrigo.vivi

On Fri, Sep 14, 2018 at 06:57:23PM +0530, Madhav Chauhan wrote:
> On 9/14/2018 6:36 PM, Madhav Chauhan wrote:
> > On 9/14/2018 5:55 PM, Ville Syrjälä wrote:
> >> On Fri, Sep 14, 2018 at 11:42:33AM +0530, Madhav Chauhan wrote:
> >>> On 9/12/2018 11:30 PM, Ville Syrjälä wrote:
> >>>> On Wed, Sep 12, 2018 at 03:06:41PM +0530, Madhav Chauhan wrote:
> >>>>> On 7/19/2018 9:52 PM, Ville Syrjälä wrote:
> >>>>>> On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
> >>>>>>> This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
> >>>>>>> DSI transcoder registers.
> >>>>>>>
> >>>>>>> Credits-to: Jani N
> >>>>>>>
> >>>>>>> Cc: Jani Nikula <jani.nikula@intel.com>
> >>>>>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> >>>>>>> ---
> >>>>>>>     drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> >>>>>>>     1 file changed, 5 insertions(+)
> >>>>>>>
> >>>>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> >>>>>>> b/drivers/gpu/drm/i915/i915_reg.h
> >>>>>>> index 1d13ba9..62bc76e 100644
> >>>>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>>>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>>>>>> @@ -9576,6 +9576,11 @@ enum skl_power_gate {
> >>>>>>>     #define _MIPI_PORT(port, a, c)    (((port) == PORT_A) ? a : 
> >>>>>>> c)    /* ports A and C only */
> >>>>>>>     #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
> >>>>>>>     +/* gen11 DSI */
> >>>>>>> +#define _DSI_TRANS(tc, dsi0, dsi1)    (((tc) == 
> >>>>>>> TRANSCODER_DSI_0) ?    \
> >>>>>>> +                     (dsi0) : (dsi1))
> >>>>>> _PIPE() etc. should result in slughtly better code IIRC.
> >>>>> Can you please clarify on this??
> >>>> Plenty of examples in i915_reg.h for using _PIPE().
> >>> I meant what are advantages of using _PIPE against the current 
> >>> approach??
> >> Uniform style, better generated code usually (look at the generated asm
> >> to verify).
> >
> > Got it.
> >
> >>
> >>> Also if we use _PIPE, are you suggesting something below:
> >>> #define _MMIO_DSI(tc, dsi0, dsi1)    _MMIO_PIPE(tc, dsi0, dsi1))
> >>> Using above macro we will get wrong DSI addresses as TRANS_DSI_0 
> >>> value is 5.
> >> (tc)-TRANSCODER_DSI_0
> 
> Can we use _MMIO_TRANS here, _TRANS & _PIPE have same definition??
> That will emphasize that these registers are transcoder specific not the 
> PIPE.

Sure. Could perhaps even add a _MMIO_DSI_TRANS() for cases where
the registers only apply to the DSI transcoders.

> 
> Regards,
> Madhav
> 
> >
> > Thanks for clarification Ville, will use _PIPE().
> >
> > Regards,
> > Madhav
> >
> >>
> >>> Or do you mean to use PORT instead of TRANS_DSI_0/1 to _MMIO_DSI??
> >>>
> >>> Regards,
> >>> Madhav
> >>>
> >>>>> Regards,
> >>>>> Madhav
> >>>>>
> >>>>>>> +#define _MMIO_DSI(tc, dsi0, dsi1)    _MMIO(_DSI_TRANS(tc, dsi0, 
> >>>>>>> dsi1))
> >>>>>>> +
> >>>>>>>     #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
> >>>>>>>     #define  GLK_TX_ESC_CLK_DIV1_MASK            0x3FF
> >>>>>>>     #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
> >>>>>>> -- 
> >>>>>>> 2.7.4
> >>>>>>>
> >>>>>>> _______________________________________________
> >>>>>>> Intel-gfx mailing list
> >>>>>>> Intel-gfx@lists.freedesktop.org
> >>>>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 63+ messages in thread
end of thread, other threads:[~2018-09-14 13:41 UTC | newest]

Thread overview: 63+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
2018-07-10  9:40 ` [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
2018-07-19 16:11   ` Ville Syrjälä
2018-07-19 18:35     ` Chauhan, Madhav
2018-07-27 11:57       ` Chauhan, Madhav
2018-09-11 17:46         ` Jani Nikula
2018-09-12  6:32           ` Madhav Chauhan
2018-09-10 12:20   ` Lisovskiy, Stanislav
2018-09-10 15:27     ` Madhav Chauhan
2018-09-11  8:08       ` Lisovskiy, Stanislav
2018-07-10  9:40 ` [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
2018-09-06 14:01   ` [v5, " Kulkarni, Vandita
2018-09-10  7:43     ` Madhav Chauhan
2018-09-11 18:16       ` Jani Nikula
2018-09-12  6:34         ` Madhav Chauhan
2018-09-11 18:50   ` [PATCH v5 " Jani Nikula
2018-09-12  9:03     ` Madhav Chauhan
2018-09-12  9:10       ` Jani Nikula
2018-07-10  9:40 ` [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
2018-09-11 18:54   ` Jani Nikula
2018-09-12  9:06     ` Madhav Chauhan
2018-09-12  9:10       ` Jani Nikula
2018-07-10  9:40 ` [PATCH v5 04/13] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
2018-09-11 19:18   ` Jani Nikula
2018-07-10  9:40 ` [PATCH v5 05/13] drm/i915/icl: Program " Madhav Chauhan
2018-09-11 19:17   ` Jani Nikula
2018-07-10  9:40 ` [PATCH v5 06/13] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
2018-09-11 19:14   ` Jani Nikula
2018-09-12  9:11     ` Madhav Chauhan
2018-07-10  9:40 ` [PATCH v5 07/13] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
2018-07-19 16:17   ` Ville Syrjälä
2018-07-10  9:40 ` [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
2018-09-11 19:23   ` Jani Nikula
2018-09-12  9:13     ` Madhav Chauhan
2018-07-10  9:40 ` [PATCH v5 09/13] drm/i915/icl: Program " Madhav Chauhan
2018-07-19 16:21   ` Ville Syrjälä
2018-07-20  8:08     ` Chauhan, Madhav
2018-09-11 19:26       ` Jani Nikula
2018-09-12  9:25         ` Madhav Chauhan
2018-09-12  9:39           ` Jani Nikula
2018-07-10  9:40 ` [PATCH v5 10/13] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
2018-07-10  9:40 ` [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
2018-07-19 16:22   ` Ville Syrjälä
2018-07-20  8:55     ` Chauhan, Madhav
2018-09-12  9:36     ` Madhav Chauhan
2018-09-12 18:00       ` Ville Syrjälä
2018-09-14  6:12         ` Madhav Chauhan
2018-09-14 12:25           ` Ville Syrjälä
2018-09-14 13:06             ` Madhav Chauhan
2018-09-14 13:27               ` Madhav Chauhan
2018-09-14 13:41                 ` Ville Syrjälä
2018-07-10  9:40 ` [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
2018-09-11 19:30   ` Jani Nikula
2018-09-12  9:35     ` Madhav Chauhan
2018-09-12  9:47       ` Jani Nikula
2018-07-10  9:40 ` [PATCH v5 13/13] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
2018-07-10 10:46 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev5) Patchwork
2018-07-10 10:51 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-10 11:04 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-10 16:28 ` ✓ Fi.CI.IGT: " Patchwork
2018-09-11 19:35 ` [PATCH v5 00/13] ICELAKE DSI DRIVER Jani Nikula
2018-09-12  6:16   ` Madhav Chauhan
2018-09-12  7:31     ` Jani Nikula

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