From: Chester Lin <clin@suse.com> To: Marc Zyngier <maz@kernel.org> Cc: "Andreas Färber" <afaerber@suse.de>, "Rob Herring" <robh+dt@kernel.org>, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "Shawn Guo" <shawnguo@kernel.org>, "Krzysztof Kozlowski" <krzk@kernel.org>, "Oleksij Rempel" <linux@rempel-privat.de>, "Stefan Riedmueller" <s.riedmueller@phytec.de>, "Matthias Schiffer" <matthias.schiffer@ew.tq-group.com>, "Li Yang" <leoyang.li@nxp.com>, "Fabio Estevam" <festevam@gmail.com>, "Matteo Lisi" <matteo.lisi@engicam.com>, "Frieder Schrempf" <frieder.schrempf@kontron.de>, "Tim Harvey" <tharvey@gateworks.com>, "Jagan Teki" <jagan@amarulasolutions.com>, catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com, bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com, radu-nicolae.pirea@nxp.com, ghennadi.procopciuc@nxp.com, "Matthias Brugger" <matthias.bgg@gmail.com>, "Ivan T . Ivanov" <iivanov@suse.de>, "Lee, Chun-Yi" <jlee@suse.com> Subject: Re: [PATCH 4/8] arm64: dts: add NXP S32G2 support Date: Fri, 20 Aug 2021 23:15:49 +0800 [thread overview] Message-ID: <YR/HJQDGJ1C+ku6O@linux-8mug> (raw) In-Reply-To: <87o89sqmz6.wl-maz@kernel.org> On Fri, Aug 20, 2021 at 02:12:13PM +0100, Marc Zyngier wrote: > On Thu, 12 Aug 2021 18:26:28 +0100, > Andreas Färber <afaerber@suse.de> wrote: > > > > Hi Chester et al., > > > > On 05.08.21 08:54, Chester Lin wrote: > > > Add an initial dtsi file for generic SoC features of NXP S32G2. > > > > > > Signed-off-by: Chester Lin <clin@suse.com> > > > --- > > > arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++ > > > 1 file changed, 98 insertions(+) > > > create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi > > > > > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > > > new file mode 100644 > > > index 000000000000..3321819c1a2d > > > --- /dev/null > > > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi > > [...] > > > > + gic: interrupt-controller@50800000 { > > > + compatible = "arm,gic-v3"; > > > + #interrupt-cells = <3>; > > > + interrupt-controller; > > > + reg = <0 0x50800000 0 0x10000>, > > > + <0 0x50880000 0 0x200000>, > > That's enough redistributor space for 16 CPUs. However, you only > describe 4. Either the number of CPUs is wrong, the size is wrong, or > the GIC has been configured for more cores than the SoC has. Confirmed the SoC can only find 4 redistributors: localhost:~ # dmesg | grep CPU [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: GIC system register CPU interface [ 0.000000] CPU features: detected: ARM erratum 845719 [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=480 to nr_cpu_ids=4. [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000050880000 [ 0.063865] smp: Bringing up secondary CPUs ... [ 0.068852] Detected VIPT I-cache on CPU1 [ 0.068894] GICv3: CPU1: found redistributor 1 region 0:0x00000000508a0000 [ 0.068963] CPU1: Booted secondary processor 0x0000000001 [0x410fd034] [ 0.069809] Detected VIPT I-cache on CPU2 [ 0.069851] GICv3: CPU2: found redistributor 100 region 0:0x00000000508c0000 [ 0.069903] CPU2: Booted secondary processor 0x0000000100 [0x410fd034] [ 0.070698] Detected VIPT I-cache on CPU3 [ 0.070722] GICv3: CPU3: found redistributor 101 region 0:0x00000000508e0000 [ 0.070749] CPU3: Booted secondary processor 0x0000000101 [0x410fd034] [ 0.070847] smp: Brought up 1 node, 4 CPUs <..snip..> I will correct the size to 0x80000, thanks! > > > > + <0 0x50400000 0 0x2000>, > > > + <0 0x50410000 0 0x2000>, > > > + <0 0x50420000 0 0x2000>; > > > > Please order reg after compatible by convention, and sort > > interrupt-controller or at least #interrupt-cells (applying to > > consumers) last, after the below one applying to this device itself. > > > > > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | > > > + IRQ_TYPE_LEVEL_HIGH)>; > > > + }; > > > > CC'ing Marc for additional GIC scrutiny, often the sizes are wrong. > > There is more than just sizes. The interrupt specifier for the > maintenance interrupt is also wrong. > > M. I will remove the wrong interrupt specifier. Thanks! Chester. > > -- > Without deviation from the norm, progress is not possible. >
WARNING: multiple messages have this Message-ID (diff)
From: Chester Lin <clin@suse.com> To: Marc Zyngier <maz@kernel.org> Cc: "Andreas Färber" <afaerber@suse.de>, "Rob Herring" <robh+dt@kernel.org>, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "Shawn Guo" <shawnguo@kernel.org>, "Krzysztof Kozlowski" <krzk@kernel.org>, "Oleksij Rempel" <linux@rempel-privat.de>, "Stefan Riedmueller" <s.riedmueller@phytec.de>, "Matthias Schiffer" <matthias.schiffer@ew.tq-group.com>, "Li Yang" <leoyang.li@nxp.com>, "Fabio Estevam" <festevam@gmail.com>, "Matteo Lisi" <matteo.lisi@engicam.com>, "Frieder Schrempf" <frieder.schrempf@kontron.de>, "Tim Harvey" <tharvey@gateworks.com>, "Jagan Teki" <jagan@amarulasolutions.com>, catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com, bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com, radu-nicolae.pirea@nxp.com, ghennadi.procopciuc@nxp.com, "Matthias Brugger" <matthias.bgg@gmail.com>, "Ivan T . Ivanov" <iivanov@suse.de>, "Lee, Chun-Yi" <jlee@suse.com> Subject: Re: [PATCH 4/8] arm64: dts: add NXP S32G2 support Date: Fri, 20 Aug 2021 23:15:49 +0800 [thread overview] Message-ID: <YR/HJQDGJ1C+ku6O@linux-8mug> (raw) In-Reply-To: <87o89sqmz6.wl-maz@kernel.org> On Fri, Aug 20, 2021 at 02:12:13PM +0100, Marc Zyngier wrote: > On Thu, 12 Aug 2021 18:26:28 +0100, > Andreas Färber <afaerber@suse.de> wrote: > > > > Hi Chester et al., > > > > On 05.08.21 08:54, Chester Lin wrote: > > > Add an initial dtsi file for generic SoC features of NXP S32G2. > > > > > > Signed-off-by: Chester Lin <clin@suse.com> > > > --- > > > arch/arm64/boot/dts/freescale/s32g2.dtsi | 98 ++++++++++++++++++++++++ > > > 1 file changed, 98 insertions(+) > > > create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi > > > > > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > > > new file mode 100644 > > > index 000000000000..3321819c1a2d > > > --- /dev/null > > > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi > > [...] > > > > + gic: interrupt-controller@50800000 { > > > + compatible = "arm,gic-v3"; > > > + #interrupt-cells = <3>; > > > + interrupt-controller; > > > + reg = <0 0x50800000 0 0x10000>, > > > + <0 0x50880000 0 0x200000>, > > That's enough redistributor space for 16 CPUs. However, you only > describe 4. Either the number of CPUs is wrong, the size is wrong, or > the GIC has been configured for more cores than the SoC has. Confirmed the SoC can only find 4 redistributors: localhost:~ # dmesg | grep CPU [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: GIC system register CPU interface [ 0.000000] CPU features: detected: ARM erratum 845719 [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=480 to nr_cpu_ids=4. [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000050880000 [ 0.063865] smp: Bringing up secondary CPUs ... [ 0.068852] Detected VIPT I-cache on CPU1 [ 0.068894] GICv3: CPU1: found redistributor 1 region 0:0x00000000508a0000 [ 0.068963] CPU1: Booted secondary processor 0x0000000001 [0x410fd034] [ 0.069809] Detected VIPT I-cache on CPU2 [ 0.069851] GICv3: CPU2: found redistributor 100 region 0:0x00000000508c0000 [ 0.069903] CPU2: Booted secondary processor 0x0000000100 [0x410fd034] [ 0.070698] Detected VIPT I-cache on CPU3 [ 0.070722] GICv3: CPU3: found redistributor 101 region 0:0x00000000508e0000 [ 0.070749] CPU3: Booted secondary processor 0x0000000101 [0x410fd034] [ 0.070847] smp: Brought up 1 node, 4 CPUs <..snip..> I will correct the size to 0x80000, thanks! > > > > + <0 0x50400000 0 0x2000>, > > > + <0 0x50410000 0 0x2000>, > > > + <0 0x50420000 0 0x2000>; > > > > Please order reg after compatible by convention, and sort > > interrupt-controller or at least #interrupt-cells (applying to > > consumers) last, after the below one applying to this device itself. > > > > > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | > > > + IRQ_TYPE_LEVEL_HIGH)>; > > > + }; > > > > CC'ing Marc for additional GIC scrutiny, often the sizes are wrong. > > There is more than just sizes. The interrupt specifier for the > maintenance interrupt is also wrong. > > M. I will remove the wrong interrupt specifier. Thanks! Chester. > > -- > Without deviation from the norm, progress is not possible. > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-08-20 15:16 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-05 6:54 [PATCH 0/8] arm64: dts: initial NXP S32G2 support Chester Lin 2021-08-05 6:54 ` Chester Lin 2021-08-05 6:54 ` [PATCH 1/8] dt-bindings: arm: fsl: add NXP S32G2 boards Chester Lin 2021-08-05 6:54 ` Chester Lin 2021-08-12 15:46 ` Andreas Färber 2021-08-12 15:46 ` Andreas Färber 2021-08-13 17:49 ` Rob Herring 2021-08-13 17:49 ` Rob Herring 2021-08-13 17:53 ` Rob Herring 2021-08-13 17:53 ` Rob Herring 2021-08-18 14:34 ` Chester Lin 2021-08-18 14:34 ` Chester Lin 2021-09-06 20:38 ` Andreas Färber 2021-09-06 20:38 ` Andreas Färber 2021-09-07 6:59 ` Krzysztof Kozlowski 2021-09-07 6:59 ` Krzysztof Kozlowski 2021-09-07 8:59 ` Andreas Färber 2021-09-07 8:59 ` Andreas Färber 2021-09-06 19:35 ` Andreas Färber 2021-09-06 19:35 ` Andreas Färber 2021-08-05 6:54 ` [PATCH 2/8] dt-bindings: serial: fsl-linflexuart: convert to json-schema format Chester Lin 2021-08-05 6:54 ` Chester Lin 2021-08-12 16:04 ` Andreas Färber 2021-08-12 16:04 ` Andreas Färber 2021-08-13 11:11 ` Chester Lin 2021-08-13 11:11 ` Chester Lin 2021-08-13 11:28 ` Krzysztof Kozlowski 2021-08-13 11:28 ` Krzysztof Kozlowski 2021-08-13 11:43 ` Chester Lin 2021-08-13 11:43 ` Chester Lin 2021-08-13 18:04 ` Rob Herring 2021-08-13 18:04 ` Rob Herring 2021-08-13 18:07 ` Rob Herring 2021-08-13 18:07 ` Rob Herring 2021-08-05 6:54 ` [PATCH 3/8] dt-bindings: serial: fsl-linflexuart: Add compatible for S32G2 Chester Lin 2021-08-05 6:54 ` Chester Lin 2021-08-12 16:27 ` Andreas Färber 2021-08-12 16:27 ` Andreas Färber 2021-08-13 14:27 ` Radu Nicolae Pirea (NXP OSS) 2021-08-13 14:27 ` Radu Nicolae Pirea (NXP OSS) 2021-08-13 18:11 ` Rob Herring 2021-08-13 18:11 ` Rob Herring 2021-08-13 18:09 ` Rob Herring 2021-08-13 18:09 ` Rob Herring 2021-08-05 6:54 ` [PATCH 4/8] arm64: dts: add NXP S32G2 support Chester Lin 2021-08-05 6:54 ` Chester Lin 2021-08-12 17:26 ` Andreas Färber 2021-08-12 17:26 ` Andreas Färber 2021-08-13 3:28 ` Chester Lin 2021-08-13 3:28 ` Chester Lin 2021-08-13 7:05 ` Andreas Färber 2021-08-13 7:05 ` Andreas Färber 2021-08-20 13:12 ` Marc Zyngier 2021-08-20 13:12 ` Marc Zyngier 2021-08-20 15:15 ` Chester Lin [this message] 2021-08-20 15:15 ` Chester Lin 2021-08-20 15:29 ` Marc Zyngier 2021-08-20 15:29 ` Marc Zyngier 2021-08-21 12:39 ` Chester Lin 2021-08-21 12:39 ` Chester Lin 2021-08-21 14:20 ` Marc Zyngier 2021-08-21 14:20 ` Marc Zyngier 2021-08-05 6:54 ` [PATCH 5/8] arm64: dts: s32g2: add serial/uart support Chester Lin 2021-08-05 6:54 ` Chester Lin 2021-08-12 17:42 ` Andreas Färber 2021-08-12 17:42 ` Andreas Färber 2021-08-13 9:54 ` Radu Nicolae Pirea (NXP OSS) 2021-08-13 9:54 ` Radu Nicolae Pirea (NXP OSS) 2021-08-05 6:54 ` [PATCH 6/8] arm64: dts: s32g2: add VNP-EVB and VNP-RDB2 support Chester Lin 2021-08-05 6:54 ` Chester Lin 2021-08-12 18:00 ` Andreas Färber 2021-08-12 18:00 ` Andreas Färber 2021-08-13 8:47 ` Chester Lin 2021-08-13 8:47 ` Chester Lin 2021-08-05 6:54 ` [PATCH 7/8] arm64: dts: s32g2: add memory nodes for evb and rdb2 Chester Lin 2021-08-05 6:54 ` Chester Lin 2021-08-12 18:25 ` Andreas Färber 2021-08-12 18:25 ` Andreas Färber 2021-08-13 14:58 ` Chester Lin 2021-08-13 14:58 ` Chester Lin 2021-08-05 6:54 ` [PATCH 8/8] MAINTAINERS: Add an entry for NXP S32G2 boards Chester Lin 2021-08-05 6:54 ` Chester Lin 2021-08-05 7:49 ` Krzysztof Kozlowski 2021-08-05 7:49 ` Krzysztof Kozlowski 2021-08-09 8:03 ` Shawn Guo 2021-08-09 8:03 ` Shawn Guo 2021-08-12 15:30 ` Andreas Färber 2021-08-12 15:30 ` Andreas Färber 2021-08-12 15:54 ` Krzysztof Kozlowski 2021-08-12 15:54 ` Krzysztof Kozlowski 2021-08-09 8:06 ` [PATCH 0/8] arm64: dts: initial NXP S32G2 support Shawn Guo 2021-08-09 8:06 ` Shawn Guo
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