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* [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers
@ 2022-05-10 16:11 Mark Brown
  2022-05-10 16:11 ` [PATCH v1 01/12] arm64/fp: Make SVE and SME length register definition match architecture Mark Brown
                   ` (12 more replies)
  0 siblings, 13 replies; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:11 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

This series builds on top of the recently applied series for system
register generation, converting the floating point registers to
automatic generation. There's nothing remarkable in here, just a bunch
of straightforward cleanups and the addition of support for RAZ fields
followed by the actual conversions.

It does skip over the SVCRSM, SVCRZA and SVCRSMZA aliases for now since
I need to think a little about what to do with those.

Since the series includes conversion of the SME registers it is based on
for-next/core rather than for-next/sysreg-gen to pick up for-next/sme as
well.

Mark Brown (12):
  arm64/fp: Make SVE and SME length register definition match
    architecture
  arm64/fp: Rename SVE and SME LEN field name to _WIDTH
  arm64/sme: Drop SYS_ from SMIDR_EL1 defines
  arm64/sme: Standardise bitfield names for SVCR
  arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h
  arm64/sysreg: Support generation of RAZ fields
  arm64/sme: Automatically generate defines for SMCR
  arm64/sme: Automatically generate SMIDR_EL1 defines
  arm64/sme: Automatically generate SMPRIMAP_EL2 definitions
  arm64/sme: Generate SMPRI_EL1 definitions
  arm64/sme: Generate defintions for SVCR
  arm64/sve: Generate ZCR definitions

 arch/arm64/include/asm/el2_setup.h |  2 +-
 arch/arm64/include/asm/fpsimd.h    |  4 +-
 arch/arm64/include/asm/processor.h |  2 +-
 arch/arm64/include/asm/sysreg.h    | 42 ++--------------
 arch/arm64/kernel/cpufeature.c     |  4 +-
 arch/arm64/kernel/fpsimd.c         | 26 +++++-----
 arch/arm64/kernel/ptrace.c         |  8 ++--
 arch/arm64/kernel/signal.c         | 14 +++---
 arch/arm64/kernel/syscall.c        |  4 +-
 arch/arm64/kvm/fpsimd.c            |  4 +-
 arch/arm64/kvm/sys_regs.c          |  2 +-
 arch/arm64/tools/gen-sysreg.awk    |  7 +++
 arch/arm64/tools/sysreg            | 77 ++++++++++++++++++++++++++++++
 13 files changed, 122 insertions(+), 74 deletions(-)


base-commit: 01ce2f5af527043a591208fe26788f55101b90bd
-- 
2.30.2


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 23+ messages in thread
* [PATCH v1 01/12] arm64/fp: Make SVE and SME length register definition match architecture
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
@ 2022-05-10 16:11 ` Mark Brown
  2022-05-10 16:11 ` [PATCH v1 02/12] arm64/fp: Rename SVE and SME LEN field name to _WIDTH Mark Brown
                   ` (11 subsequent siblings)
  12 siblings, 0 replies; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:11 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

Currently (as of DDI0487H.a) the architecture defines the vector length
control field in ZCR and SMCR as being 4 bits wide with an additional 5
bits reserved above it marked as RAZ/WI for future expansion. The kernel
currently attempts to anticipate such expansion by treating these extra
bits as part of the LEN field but this will be inconvenient when we start
generating the defines and would cause problems in the event that the
architecture goes a different direction with these fields. Let's instead
change the defines to reflect the currently defined architecture, we can
update in future as needed.

No change in behaviour should be seen in any system, even emulated systems
using the maximum allowed vector length for the current architecture.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 18 ++++--------------
 1 file changed, 4 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 422741ca5631..4d78b6aeebb4 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1113,26 +1113,16 @@
 #define DCZID_DZP_SHIFT			4
 #define DCZID_BS_SHIFT			0
 
-/*
- * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
- * are reserved by the SVE architecture for future expansion of the LEN
- * field, with compatible semantics.
- */
 #define ZCR_ELx_LEN_SHIFT	0
-#define ZCR_ELx_LEN_SIZE	9
-#define ZCR_ELx_LEN_MASK	0x1ff
+#define ZCR_ELx_LEN_SIZE	4
+#define ZCR_ELx_LEN_MASK	0xf
 
 #define SMCR_ELx_FA64_SHIFT	31
 #define SMCR_ELx_FA64_MASK	(1 << SMCR_ELx_FA64_SHIFT)
 
-/*
- * The SMCR_ELx_LEN_* definitions intentionally include bits [8:4] which
- * are reserved by the SME architecture for future expansion of the LEN
- * field, with compatible semantics.
- */
 #define SMCR_ELx_LEN_SHIFT	0
-#define SMCR_ELx_LEN_SIZE	9
-#define SMCR_ELx_LEN_MASK	0x1ff
+#define SMCR_ELx_LEN_SIZE	4
+#define SMCR_ELx_LEN_MASK	0xf
 
 #define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
 #define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH v1 02/12] arm64/fp: Rename SVE and SME LEN field name to _WIDTH
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
  2022-05-10 16:11 ` [PATCH v1 01/12] arm64/fp: Make SVE and SME length register definition match architecture Mark Brown
@ 2022-05-10 16:11 ` Mark Brown
  2022-05-10 16:11 ` [PATCH v1 03/12] arm64/sme: Drop SYS_ from SMIDR_EL1 defines Mark Brown
                   ` (10 subsequent siblings)
  12 siblings, 0 replies; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:11 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

The SVE and SVE length configuration field LEN have constants specifying
their width called _SIZE rather than the more normal _WIDTH, in preparation
for automatic generation rename to _WIDTH. No functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 4 ++--
 arch/arm64/kernel/cpufeature.c  | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 4d78b6aeebb4..b83808ebc58f 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1114,14 +1114,14 @@
 #define DCZID_BS_SHIFT			0
 
 #define ZCR_ELx_LEN_SHIFT	0
-#define ZCR_ELx_LEN_SIZE	4
+#define ZCR_ELx_LEN_WIDTH	4
 #define ZCR_ELx_LEN_MASK	0xf
 
 #define SMCR_ELx_FA64_SHIFT	31
 #define SMCR_ELx_FA64_MASK	(1 << SMCR_ELx_FA64_SHIFT)
 
 #define SMCR_ELx_LEN_SHIFT	0
-#define SMCR_ELx_LEN_SIZE	4
+#define SMCR_ELx_LEN_WIDTH	4
 #define SMCR_ELx_LEN_MASK	0xf
 
 #define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 08689362cd89..665ad380c07f 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -577,13 +577,13 @@ static const struct arm64_ftr_bits ftr_id_dfr1[] = {
 
 static const struct arm64_ftr_bits ftr_zcr[] = {
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
-		ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),	/* LEN */
+		ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0),	/* LEN */
 	ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_smcr[] = {
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
-		SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_SIZE, 0),	/* LEN */
+		SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0),	/* LEN */
 	ARM64_FTR_END,
 };
 
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH v1 03/12] arm64/sme: Drop SYS_ from SMIDR_EL1 defines
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
  2022-05-10 16:11 ` [PATCH v1 01/12] arm64/fp: Make SVE and SME length register definition match architecture Mark Brown
  2022-05-10 16:11 ` [PATCH v1 02/12] arm64/fp: Rename SVE and SME LEN field name to _WIDTH Mark Brown
@ 2022-05-10 16:11 ` Mark Brown
  2022-05-10 16:12 ` [PATCH v1 04/12] arm64/sme: Standardise bitfield names for SVCR Mark Brown
                   ` (9 subsequent siblings)
  12 siblings, 0 replies; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:11 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

We currently have a non-standard SYS_ prefix in the constants generated
for SMIDR_EL1 bitfields. Drop this in preparation for automatic register
definition generation, no functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/el2_setup.h | 2 +-
 arch/arm64/include/asm/sysreg.h    | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index fabdbde0fe02..34ceff08cac4 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -171,7 +171,7 @@
 	msr_s	SYS_SMCR_EL2, x1		// length for EL1.
 
 	mrs_s	x1, SYS_SMIDR_EL1		// Priority mapping supported?
-	ubfx    x1, x1, #SYS_SMIDR_EL1_SMPS_SHIFT, #1
+	ubfx    x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1
 	cbz     x1, .Lskip_sme_\@
 
 	msr_s	SYS_SMPRIMAP_EL2, xzr		// Make all priorities equal
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b83808ebc58f..ab2d7cbc63fc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -467,9 +467,9 @@
 #define SYS_SMIDR_EL1			sys_reg(3, 1, 0, 0, 6)
 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
 
-#define SYS_SMIDR_EL1_IMPLEMENTER_SHIFT	24
-#define SYS_SMIDR_EL1_SMPS_SHIFT	15
-#define SYS_SMIDR_EL1_AFFINITY_SHIFT	0
+#define SMIDR_EL1_IMPLEMENTER_SHIFT	24
+#define SMIDR_EL1_SMPS_SHIFT	15
+#define SMIDR_EL1_AFFINITY_SHIFT	0
 
 #define SYS_CSSELR_EL1			sys_reg(3, 2, 0, 0, 0)
 
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH v1 04/12] arm64/sme: Standardise bitfield names for SVCR
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
                   ` (2 preceding siblings ...)
  2022-05-10 16:11 ` [PATCH v1 03/12] arm64/sme: Drop SYS_ from SMIDR_EL1 defines Mark Brown
@ 2022-05-10 16:12 ` Mark Brown
  2022-05-10 16:12 ` [PATCH v1 05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h Mark Brown
                   ` (8 subsequent siblings)
  12 siblings, 0 replies; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:12 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

The bitfield definitions for SVCR have a SYS_ added to the names of the
constant which will be a problem for automatic generation. Remove the
prefixes, no functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/fpsimd.h    | 4 ++--
 arch/arm64/include/asm/processor.h | 2 +-
 arch/arm64/include/asm/sysreg.h    | 4 ++--
 arch/arm64/kernel/fpsimd.c         | 6 +++---
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
index 75caa2098d5b..aa11dbec0d70 100644
--- a/arch/arm64/include/asm/fpsimd.h
+++ b/arch/arm64/include/asm/fpsimd.h
@@ -67,12 +67,12 @@ extern void fpsimd_save_and_flush_cpu_state(void);
 
 static inline bool thread_sm_enabled(struct thread_struct *thread)
 {
-	return system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_SM_MASK);
+	return system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK);
 }
 
 static inline bool thread_za_enabled(struct thread_struct *thread)
 {
-	return system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_ZA_MASK);
+	return system_supports_sme() && (thread->svcr & SVCR_EL0_ZA_MASK);
 }
 
 /* Maximum VL that SVE/SME VL-agnostic software can transparently support */
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 1d2ca4870b84..69ce163d2fb2 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -192,7 +192,7 @@ static inline unsigned int thread_get_sme_vl(struct thread_struct *thread)
 
 static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
 {
-	if (system_supports_sme() && (thread->svcr & SYS_SVCR_EL0_SM_MASK))
+	if (system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK))
 		return thread_get_sme_vl(thread);
 	else
 		return thread_get_sve_vl(thread);
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index ab2d7cbc63fc..4459cd4a37f5 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -480,8 +480,8 @@
 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
 
 #define SYS_SVCR_EL0			sys_reg(3, 3, 4, 2, 2)
-#define SYS_SVCR_EL0_ZA_MASK		2
-#define SYS_SVCR_EL0_SM_MASK		1
+#define SVCR_EL0_ZA_MASK		2
+#define SVCR_EL0_SM_MASK		1
 
 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 95a733d3b253..8b48e870e14e 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1893,7 +1893,7 @@ void __efi_fpsimd_begin(void)
 				svcr = read_sysreg_s(SYS_SVCR_EL0);
 
 				if (!system_supports_fa64())
-					ffr = svcr & SYS_SVCR_EL0_SM_MASK;
+					ffr = svcr & SVCR_EL0_SM_MASK;
 
 				__this_cpu_write(efi_sm_state, ffr);
 			}
@@ -1904,7 +1904,7 @@ void __efi_fpsimd_begin(void)
 
 			if (system_supports_sme())
 				sysreg_clear_set_s(SYS_SVCR_EL0,
-						   SYS_SVCR_EL0_SM_MASK, 0);
+						   SVCR_EL0_SM_MASK, 0);
 
 		} else {
 			fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state));
@@ -1939,7 +1939,7 @@ void __efi_fpsimd_end(void)
 				if (__this_cpu_read(efi_sm_state)) {
 					sysreg_clear_set_s(SYS_SVCR_EL0,
 							   0,
-							   SYS_SVCR_EL0_SM_MASK);
+							   SVCR_EL0_SM_MASK);
 					if (!system_supports_fa64())
 						ffr = efi_sm_state;
 				}
-- 
2.30.2


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH v1 05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
                   ` (3 preceding siblings ...)
  2022-05-10 16:12 ` [PATCH v1 04/12] arm64/sme: Standardise bitfield names for SVCR Mark Brown
@ 2022-05-10 16:12 ` Mark Brown
  2022-05-13 14:16   ` Mark Rutland
  2022-05-10 16:12 ` [PATCH v1 06/12] arm64/sysreg: Support generation of RAZ fields Mark Brown
                   ` (7 subsequent siblings)
  12 siblings, 1 reply; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:12 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

The defines for SVCR call it SVCR_EL0 however the architecture calls the
register SVCR with no _EL0 suffix. In preparation for generating the sysreg
definitions rename to match the architecture, no functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/fpsimd.h    |  4 ++--
 arch/arm64/include/asm/processor.h |  2 +-
 arch/arm64/include/asm/sysreg.h    |  6 +++---
 arch/arm64/kernel/fpsimd.c         | 26 +++++++++++++-------------
 arch/arm64/kernel/ptrace.c         |  8 ++++----
 arch/arm64/kernel/signal.c         | 14 +++++++-------
 arch/arm64/kernel/syscall.c        |  4 ++--
 arch/arm64/kvm/fpsimd.c            |  4 ++--
 arch/arm64/kvm/sys_regs.c          |  2 +-
 9 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
index aa11dbec0d70..9bb1873f5295 100644
--- a/arch/arm64/include/asm/fpsimd.h
+++ b/arch/arm64/include/asm/fpsimd.h
@@ -67,12 +67,12 @@ extern void fpsimd_save_and_flush_cpu_state(void);
 
 static inline bool thread_sm_enabled(struct thread_struct *thread)
 {
-	return system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK);
+	return system_supports_sme() && (thread->svcr & SVCR_SM_MASK);
 }
 
 static inline bool thread_za_enabled(struct thread_struct *thread)
 {
-	return system_supports_sme() && (thread->svcr & SVCR_EL0_ZA_MASK);
+	return system_supports_sme() && (thread->svcr & SVCR_ZA_MASK);
 }
 
 /* Maximum VL that SVE/SME VL-agnostic software can transparently support */
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 69ce163d2fb2..8de5a4fc06e3 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -192,7 +192,7 @@ static inline unsigned int thread_get_sme_vl(struct thread_struct *thread)
 
 static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
 {
-	if (system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK))
+	if (system_supports_sme() && (thread->svcr & SVCR_SM_MASK))
 		return thread_get_sme_vl(thread);
 	else
 		return thread_get_sve_vl(thread);
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 4459cd4a37f5..a2f0759f65b2 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -479,9 +479,9 @@
 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
 
-#define SYS_SVCR_EL0			sys_reg(3, 3, 4, 2, 2)
-#define SVCR_EL0_ZA_MASK		2
-#define SVCR_EL0_SM_MASK		1
+#define SYS_SVCR			sys_reg(3, 3, 4, 2, 2)
+#define SVCR_ZA_MASK			2
+#define SVCR_SM_MASK			1
 
 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 8b48e870e14e..fbffafb55552 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -398,7 +398,7 @@ static void task_fpsimd_load(void)
 		if (test_thread_flag(TIF_SME))
 			sme_set_vq(sve_vq_from_vl(sme_vl) - 1);
 
-		write_sysreg_s(current->thread.svcr, SYS_SVCR_EL0);
+		write_sysreg_s(current->thread.svcr, SYS_SVCR);
 
 		if (thread_za_enabled(&current->thread))
 			za_load_state(current->thread.za_state);
@@ -450,15 +450,15 @@ static void fpsimd_save(void)
 
 	if (system_supports_sme()) {
 		u64 *svcr = last->svcr;
-		*svcr = read_sysreg_s(SYS_SVCR_EL0);
+		*svcr = read_sysreg_s(SYS_SVCR);
 
-		*svcr = read_sysreg_s(SYS_SVCR_EL0);
+		*svcr = read_sysreg_s(SYS_SVCR);
 
-		if (*svcr & SYS_SVCR_EL0_ZA_MASK)
+		if (*svcr & SVCR_ZA_MASK)
 			za_save_state(last->za_state);
 
 		/* If we are in streaming mode override regular SVE. */
-		if (*svcr & SYS_SVCR_EL0_SM_MASK) {
+		if (*svcr & SVCR_SM_MASK) {
 			save_sve_regs = true;
 			save_ffr = system_supports_fa64();
 			vl = last->sme_vl;
@@ -840,8 +840,8 @@ int vec_set_vector_length(struct task_struct *task, enum vec_type type,
 		sve_to_fpsimd(task);
 
 	if (system_supports_sme() && type == ARM64_VEC_SME) {
-		task->thread.svcr &= ~(SYS_SVCR_EL0_SM_MASK |
-				       SYS_SVCR_EL0_ZA_MASK);
+		task->thread.svcr &= ~(SVCR_SM_MASK |
+				       SVCR_ZA_MASK);
 		clear_thread_flag(TIF_SME);
 	}
 
@@ -1890,10 +1890,10 @@ void __efi_fpsimd_begin(void)
 			__this_cpu_write(efi_sve_state_used, true);
 
 			if (system_supports_sme()) {
-				svcr = read_sysreg_s(SYS_SVCR_EL0);
+				svcr = read_sysreg_s(SYS_SVCR);
 
 				if (!system_supports_fa64())
-					ffr = svcr & SVCR_EL0_SM_MASK;
+					ffr = svcr & SVCR_SM_MASK;
 
 				__this_cpu_write(efi_sm_state, ffr);
 			}
@@ -1903,8 +1903,8 @@ void __efi_fpsimd_begin(void)
 				       ffr);
 
 			if (system_supports_sme())
-				sysreg_clear_set_s(SYS_SVCR_EL0,
-						   SVCR_EL0_SM_MASK, 0);
+				sysreg_clear_set_s(SYS_SVCR,
+						   SVCR_SM_MASK, 0);
 
 		} else {
 			fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state));
@@ -1937,9 +1937,9 @@ void __efi_fpsimd_end(void)
 			 */
 			if (system_supports_sme()) {
 				if (__this_cpu_read(efi_sm_state)) {
-					sysreg_clear_set_s(SYS_SVCR_EL0,
+					sysreg_clear_set_s(SYS_SVCR,
 							   0,
-							   SVCR_EL0_SM_MASK);
+							   SVCR_SM_MASK);
 					if (!system_supports_fa64())
 						ffr = efi_sm_state;
 				}
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index 60ebc3060cf1..21da83187a60 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -867,10 +867,10 @@ static int sve_set_common(struct task_struct *target,
 
 		switch (type) {
 		case ARM64_VEC_SVE:
-			target->thread.svcr &= ~SYS_SVCR_EL0_SM_MASK;
+			target->thread.svcr &= ~SVCR_SM_MASK;
 			break;
 		case ARM64_VEC_SME:
-			target->thread.svcr |= SYS_SVCR_EL0_SM_MASK;
+			target->thread.svcr |= SVCR_SM_MASK;
 			break;
 		default:
 			WARN_ON_ONCE(1);
@@ -1100,7 +1100,7 @@ static int za_set(struct task_struct *target,
 
 	/* If there is no data then disable ZA */
 	if (!count) {
-		target->thread.svcr &= ~SYS_SVCR_EL0_ZA_MASK;
+		target->thread.svcr &= ~SVCR_ZA_MASK;
 		goto out;
 	}
 
@@ -1125,7 +1125,7 @@ static int za_set(struct task_struct *target,
 
 	/* Mark ZA as active and let userspace use it */
 	set_tsk_thread_flag(target, TIF_SME);
-	target->thread.svcr |= SYS_SVCR_EL0_ZA_MASK;
+	target->thread.svcr |= SVCR_ZA_MASK;
 
 out:
 	fpsimd_flush_task_state(target);
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
index 2295948d97fd..18bf590dc1c7 100644
--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
@@ -288,7 +288,7 @@ static int restore_sve_fpsimd_context(struct user_ctxs *user)
 
 	if (sve.head.size <= sizeof(*user->sve)) {
 		clear_thread_flag(TIF_SVE);
-		current->thread.svcr &= ~SYS_SVCR_EL0_SM_MASK;
+		current->thread.svcr &= ~SVCR_SM_MASK;
 		goto fpsimd_only;
 	}
 
@@ -321,7 +321,7 @@ static int restore_sve_fpsimd_context(struct user_ctxs *user)
 		return -EFAULT;
 
 	if (sve.flags & SVE_SIG_FLAG_SM)
-		current->thread.svcr |= SYS_SVCR_EL0_SM_MASK;
+		current->thread.svcr |= SVCR_SM_MASK;
 	else
 		set_thread_flag(TIF_SVE);
 
@@ -398,7 +398,7 @@ static int restore_za_context(struct user_ctxs __user *user)
 		return -EINVAL;
 
 	if (za.head.size <= sizeof(*user->za)) {
-		current->thread.svcr &= ~SYS_SVCR_EL0_ZA_MASK;
+		current->thread.svcr &= ~SVCR_ZA_MASK;
 		return 0;
 	}
 
@@ -419,7 +419,7 @@ static int restore_za_context(struct user_ctxs __user *user)
 
 	sme_alloc(current);
 	if (!current->thread.za_state) {
-		current->thread.svcr &= ~SYS_SVCR_EL0_ZA_MASK;
+		current->thread.svcr &= ~SVCR_ZA_MASK;
 		clear_thread_flag(TIF_SME);
 		return -ENOMEM;
 	}
@@ -432,7 +432,7 @@ static int restore_za_context(struct user_ctxs __user *user)
 		return -EFAULT;
 
 	set_thread_flag(TIF_SME);
-	current->thread.svcr |= SYS_SVCR_EL0_ZA_MASK;
+	current->thread.svcr |= SVCR_ZA_MASK;
 
 	return 0;
 }
@@ -922,8 +922,8 @@ static void setup_return(struct pt_regs *regs, struct k_sigaction *ka,
 
 	/* Signal handlers are invoked with ZA and streaming mode disabled */
 	if (system_supports_sme()) {
-		current->thread.svcr &= ~(SYS_SVCR_EL0_ZA_MASK |
-					  SYS_SVCR_EL0_SM_MASK);
+		current->thread.svcr &= ~(SVCR_ZA_MASK |
+					  SVCR_SM_MASK);
 		sme_smstop();
 	}
 
diff --git a/arch/arm64/kernel/syscall.c b/arch/arm64/kernel/syscall.c
index 92c69e5ac269..733451fe7e41 100644
--- a/arch/arm64/kernel/syscall.c
+++ b/arch/arm64/kernel/syscall.c
@@ -174,9 +174,9 @@ static inline void fp_user_discard(void)
 	 * need updating.
 	 */
 	if (system_supports_sme() && test_thread_flag(TIF_SME)) {
-		u64 svcr = read_sysreg_s(SYS_SVCR_EL0);
+		u64 svcr = read_sysreg_s(SYS_SVCR);
 
-		if (svcr & SYS_SVCR_EL0_SM_MASK)
+		if (svcr & SVCR_SM_MASK)
 			sme_smstop_sm();
 	}
 
diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c
index 441edb9c398c..3d251a4d2cf7 100644
--- a/arch/arm64/kvm/fpsimd.c
+++ b/arch/arm64/kvm/fpsimd.c
@@ -96,8 +96,8 @@ void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu)
 		if (read_sysreg(cpacr_el1) & CPACR_EL1_SMEN_EL0EN)
 			vcpu->arch.flags |= KVM_ARM64_HOST_SME_ENABLED;
 
-		if (read_sysreg_s(SYS_SVCR_EL0) &
-		    (SYS_SVCR_EL0_SM_MASK | SYS_SVCR_EL0_ZA_MASK)) {
+		if (read_sysreg_s(SYS_SVCR) &
+		    (SVCR_SM_MASK | SVCR_ZA_MASK)) {
 			vcpu->arch.flags &= ~KVM_ARM64_FP_HOST;
 			fpsimd_save_and_flush_cpu_state();
 		}
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index a4ef986adb5e..f7f494961eda 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1685,7 +1685,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	{ SYS_DESC(SYS_SMIDR_EL1), undef_access },
 	{ SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
 	{ SYS_DESC(SYS_CTR_EL0), access_ctr },
-	{ SYS_DESC(SYS_SVCR_EL0), undef_access },
+	{ SYS_DESC(SYS_SVCR), undef_access },
 
 	{ PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr,
 	  .reset = reset_pmcr, .reg = PMCR_EL0 },
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH v1 06/12] arm64/sysreg: Support generation of RAZ fields
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
                   ` (4 preceding siblings ...)
  2022-05-10 16:12 ` [PATCH v1 05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h Mark Brown
@ 2022-05-10 16:12 ` Mark Brown
  2022-05-13 14:18   ` Mark Rutland
  2022-05-10 16:12 ` [PATCH v1 07/12] arm64/sme: Automatically generate defines for SMCR Mark Brown
                   ` (6 subsequent siblings)
  12 siblings, 1 reply; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:12 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

Add a statement for RAZ bitfields to the automatic register generation
script. Nothing is emitted to the header for these fields.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/tools/gen-sysreg.awk | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
index 3ffd77cbb499..b3f2bc072151 100755
--- a/arch/arm64/tools/gen-sysreg.awk
+++ b/arch/arm64/tools/gen-sysreg.awk
@@ -226,6 +226,13 @@ END {
 	next
 }
 
+/^Raz/ && (block == "Sysreg" || block == "SysregFields") {
+	expect_fields(2)
+	parse_bitdef(reg, field, $2)
+
+	next
+}
+
 /^Enum/ {
 	change_block("Enum", "Sysreg", "Enum")
 	expect_fields(3)
-- 
2.30.2


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH v1 07/12] arm64/sme: Automatically generate defines for SMCR
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
                   ` (5 preceding siblings ...)
  2022-05-10 16:12 ` [PATCH v1 06/12] arm64/sysreg: Support generation of RAZ fields Mark Brown
@ 2022-05-10 16:12 ` Mark Brown
  2022-05-13 14:31   ` Mark Rutland
  2022-05-10 16:12 ` [PATCH v1 08/12] arm64/sme: Automatically generate SMIDR_EL1 defines Mark Brown
                   ` (5 subsequent siblings)
  12 siblings, 1 reply; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:12 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

Convert SMCR to use the register definition code, no functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 10 ----------
 arch/arm64/tools/sysreg         | 20 ++++++++++++++++++++
 2 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index a2f0759f65b2..cbf03a1f316e 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -216,7 +216,6 @@
 #define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
 #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
 #define SYS_SMPRI_EL1			sys_reg(3, 0, 1, 2, 4)
-#define SYS_SMCR_EL1			sys_reg(3, 0, 1, 2, 6)
 
 #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
 
@@ -571,7 +570,6 @@
 #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
 #define SYS_HCRX_EL2			sys_reg(3, 4, 1, 2, 2)
 #define SYS_SMPRIMAP_EL2		sys_reg(3, 4, 1, 2, 5)
-#define SYS_SMCR_EL2			sys_reg(3, 4, 1, 2, 6)
 #define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
 #define SYS_HDFGRTR_EL2			sys_reg(3, 4, 3, 1, 4)
 #define SYS_HDFGWTR_EL2			sys_reg(3, 4, 3, 1, 5)
@@ -631,7 +629,6 @@
 #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
 #define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
 #define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)
-#define SYS_SMCR_EL12			sys_reg(3, 5, 1, 2, 6)
 #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
 #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
 #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
@@ -1117,13 +1114,6 @@
 #define ZCR_ELx_LEN_WIDTH	4
 #define ZCR_ELx_LEN_MASK	0xf
 
-#define SMCR_ELx_FA64_SHIFT	31
-#define SMCR_ELx_FA64_MASK	(1 << SMCR_ELx_FA64_SHIFT)
-
-#define SMCR_ELx_LEN_SHIFT	0
-#define SMCR_ELx_LEN_WIDTH	4
-#define SMCR_ELx_LEN_MASK	0xf
-
 #define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
 #define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
 
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c5619629bf9c..d0ac57648000 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -185,6 +185,26 @@ Field	1	A
 Field	0	M
 EndSysreg
 
+SysregFields	SMCR_ELx
+Res0	63:32
+Field	31	FA64
+Res0	30:9
+Raz	8:4
+Field	3:0	LEN
+EndSysregFields
+
+Sysreg	SMCR_EL1	3	0	1	2	6
+Fields	SMCR_ELx
+EndSysreg
+
+Sysreg	SMCR_EL2	3	4	1	2	6
+Fields	SMCR_ELx
+EndSysreg
+
+Sysreg	SMCR_EL12	3	5	1	2	6
+Fields	SMCR_ELx
+EndSysreg
+
 SysregFields TTBRx_EL1
 Field	63:48	ASID
 Field	47:1	BADDR
-- 
2.30.2


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH v1 08/12] arm64/sme: Automatically generate SMIDR_EL1 defines
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
                   ` (6 preceding siblings ...)
  2022-05-10 16:12 ` [PATCH v1 07/12] arm64/sme: Automatically generate defines for SMCR Mark Brown
@ 2022-05-10 16:12 ` Mark Brown
  2022-05-13 14:35   ` Mark Rutland
  2022-05-10 16:12 ` [PATCH v1 09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions Mark Brown
                   ` (4 subsequent siblings)
  12 siblings, 1 reply; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:12 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

Automatically generate the defines for SMIDR_EL1, no functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 1 -
 arch/arm64/tools/sysreg         | 9 +++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index cbf03a1f316e..ce08a42637bc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -463,7 +463,6 @@
 #define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)
 #define SYS_CLIDR_EL1			sys_reg(3, 1, 0, 0, 1)
 #define SYS_GMID_EL1			sys_reg(3, 1, 0, 0, 4)
-#define SYS_SMIDR_EL1			sys_reg(3, 1, 0, 0, 6)
 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
 
 #define SMIDR_EL1_IMPLEMENTER_SHIFT	24
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index d0ac57648000..1bf88ca3da5b 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -197,6 +197,15 @@ Sysreg	SMCR_EL1	3	0	1	2	6
 Fields	SMCR_ELx
 EndSysreg
 
+Sysreg	SMIDR_EL1	3	1	0	0	6
+Res0	63:32
+Field	31:24	IMPLEMENTER
+Field	23:16	REVISION
+Field	15	SMPS
+Res0	14:12
+Field	11:0	AFFINITY
+EndSysreg
+
 Sysreg	SMCR_EL2	3	4	1	2	6
 Fields	SMCR_ELx
 EndSysreg
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH v1 09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
                   ` (7 preceding siblings ...)
  2022-05-10 16:12 ` [PATCH v1 08/12] arm64/sme: Automatically generate SMIDR_EL1 defines Mark Brown
@ 2022-05-10 16:12 ` Mark Brown
  2022-05-13 14:38   ` Mark Rutland
  2022-05-10 16:12 ` [PATCH v1 10/12] arm64/sme: Generate SMPRI_EL1 definitions Mark Brown
                   ` (3 subsequent siblings)
  12 siblings, 1 reply; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:12 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

No functional change should be seen from converting SMPRIMAP_EL2 to be
generated.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h |  1 -
 arch/arm64/tools/sysreg         | 19 +++++++++++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index ce08a42637bc..2a9468d449fa 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -568,7 +568,6 @@
 #define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)
 #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
 #define SYS_HCRX_EL2			sys_reg(3, 4, 1, 2, 2)
-#define SYS_SMPRIMAP_EL2		sys_reg(3, 4, 1, 2, 5)
 #define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
 #define SYS_HDFGRTR_EL2			sys_reg(3, 4, 3, 1, 4)
 #define SYS_HDFGWTR_EL2			sys_reg(3, 4, 3, 1, 5)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 1bf88ca3da5b..2cdcdac0465e 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -206,6 +206,25 @@ Res0	14:12
 Field	11:0	AFFINITY
 EndSysreg
 
+Sysreg	SMPRIMAP_EL2	3	4	1	2	5
+Field	63:60	P15
+Field	59:56	P14
+Field	55:52	P13
+Field	51:48	P12
+Field	47:44	P11
+Field	43:40	P10
+Field	39:36	F9
+Field	35:32	P8
+Field	31:28	P7
+Field	27:24	P6
+Field	23:20	P5
+Field	19:16	P4
+Field	15:12	P3
+Field	11:8	P2
+Field	7:4	P1
+Field	3:0	P0
+EndSysreg
+
 Sysreg	SMCR_EL2	3	4	1	2	6
 Fields	SMCR_ELx
 EndSysreg
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH v1 10/12] arm64/sme: Generate SMPRI_EL1 definitions
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
                   ` (8 preceding siblings ...)
  2022-05-10 16:12 ` [PATCH v1 09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions Mark Brown
@ 2022-05-10 16:12 ` Mark Brown
  2022-05-13 14:39   ` Mark Rutland
  2022-05-10 16:12 ` [PATCH v1 11/12] arm64/sme: Generate defintions for SVCR Mark Brown
                   ` (2 subsequent siblings)
  12 siblings, 1 reply; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:12 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

Convert SMPRI_EL1 to be generated. No functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 3 ---
 arch/arm64/tools/sysreg         | 5 +++++
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 2a9468d449fa..b4affc3fd569 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -215,7 +215,6 @@
 
 #define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
 #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
-#define SYS_SMPRI_EL1			sys_reg(3, 0, 1, 2, 4)
 
 #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
 
@@ -406,8 +405,6 @@
 #define TRBIDR_ALIGN_MASK		GENMASK(3, 0)
 #define TRBIDR_ALIGN_SHIFT		0
 
-#define SMPRI_EL1_PRIORITY_MASK		0xf
-
 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
 
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 2cdcdac0465e..d29bc429f504 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -185,6 +185,11 @@ Field	1	A
 Field	0	M
 EndSysreg
 
+Sysreg	SMPRI_EL1	3	0	1	2	4
+Res0	63:4
+Field	3:0	PRIORITY
+EndSysreg
+
 SysregFields	SMCR_ELx
 Res0	63:32
 Field	31	FA64
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH v1 11/12] arm64/sme: Generate defintions for SVCR
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
                   ` (9 preceding siblings ...)
  2022-05-10 16:12 ` [PATCH v1 10/12] arm64/sme: Generate SMPRI_EL1 definitions Mark Brown
@ 2022-05-10 16:12 ` Mark Brown
  2022-05-13 14:41   ` Mark Rutland
  2022-05-10 16:12 ` [PATCH v1 12/12] arm64/sve: Generate ZCR definitions Mark Brown
  2022-05-16 19:08 ` [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Catalin Marinas
  12 siblings, 1 reply; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:12 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

Convert SVCR to automatic generation, no functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 4 ----
 arch/arm64/tools/sysreg         | 6 ++++++
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b4affc3fd569..804b5326c393 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -474,10 +474,6 @@
 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
 
-#define SYS_SVCR			sys_reg(3, 3, 4, 2, 2)
-#define SVCR_ZA_MASK			2
-#define SVCR_SM_MASK			1
-
 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
 #define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index d29bc429f504..7888603db50a 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -211,6 +211,12 @@ Res0	14:12
 Field	11:0	AFFINITY
 EndSysreg
 
+Sysreg	SVCR	3	3	4	2	2
+Res0	63:2
+Field	1	ZA
+Field	0	SM
+EndSysreg
+
 Sysreg	SMPRIMAP_EL2	3	4	1	2	5
 Field	63:60	P15
 Field	59:56	P14
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH v1 12/12] arm64/sve: Generate ZCR definitions
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
                   ` (10 preceding siblings ...)
  2022-05-10 16:12 ` [PATCH v1 11/12] arm64/sme: Generate defintions for SVCR Mark Brown
@ 2022-05-10 16:12 ` Mark Brown
  2022-05-13 14:46   ` Mark Rutland
  2022-05-16 19:08 ` [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Catalin Marinas
  12 siblings, 1 reply; 23+ messages in thread
From: Mark Brown @ 2022-05-10 16:12 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, linux-arm-kernel, Mark Brown

Convert the various ZCR instances to automatic generation, no functional
changes expected.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h |  7 -------
 arch/arm64/tools/sysreg         | 18 ++++++++++++++++++
 2 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 804b5326c393..91e4f8601393 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -213,7 +213,6 @@
 #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
 #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
 
-#define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
 #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
 
 #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
@@ -558,7 +557,6 @@
 #define SYS_HFGRTR_EL2			sys_reg(3, 4, 1, 1, 4)
 #define SYS_HFGWTR_EL2			sys_reg(3, 4, 1, 1, 5)
 #define SYS_HFGITR_EL2			sys_reg(3, 4, 1, 1, 6)
-#define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)
 #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
 #define SYS_HCRX_EL2			sys_reg(3, 4, 1, 2, 2)
 #define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
@@ -619,7 +617,6 @@
 /* VHE encodings for architectural EL0/1 system registers */
 #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
 #define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
-#define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)
 #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
 #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
 #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
@@ -1101,10 +1098,6 @@
 #define DCZID_DZP_SHIFT			4
 #define DCZID_BS_SHIFT			0
 
-#define ZCR_ELx_LEN_SHIFT	0
-#define ZCR_ELx_LEN_WIDTH	4
-#define ZCR_ELx_LEN_MASK	0xf
-
 #define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
 #define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
 
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 7888603db50a..a236d7a821b4 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -190,6 +190,16 @@ Res0	63:4
 Field	3:0	PRIORITY
 EndSysreg
 
+SysregFields	ZCR_ELx
+Res0	63:9
+Raz	8:4
+Field	3:0	LEN
+EndSysregFields
+
+Sysreg ZCR_EL1	3	0	1	2	0
+Fields ZCR_ELx
+EndSysreg
+
 SysregFields	SMCR_ELx
 Res0	63:32
 Field	31	FA64
@@ -217,6 +227,10 @@ Field	1	ZA
 Field	0	SM
 EndSysreg
 
+Sysreg	ZCR_EL2	3	4	1	2	0
+Fields	ZCR_ELx
+EndSysreg
+
 Sysreg	SMPRIMAP_EL2	3	4	1	2	5
 Field	63:60	P15
 Field	59:56	P14
@@ -240,6 +254,10 @@ Sysreg	SMCR_EL2	3	4	1	2	6
 Fields	SMCR_ELx
 EndSysreg
 
+Sysreg	ZCR_EL12	3	5	1	2	0
+Fields	ZCR_ELx
+EndSysreg
+
 Sysreg	SMCR_EL12	3	5	1	2	6
 Fields	SMCR_ELx
 EndSysreg
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* Re: [PATCH v1 05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h
  2022-05-10 16:12 ` [PATCH v1 05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h Mark Brown
@ 2022-05-13 14:16   ` Mark Rutland
  2022-05-13 19:39     ` Mark Brown
  0 siblings, 1 reply; 23+ messages in thread
From: Mark Rutland @ 2022-05-13 14:16 UTC (permalink / raw)
  To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, Marc Zyngier, linux-arm-kernel

On Tue, May 10, 2022 at 05:12:01PM +0100, Mark Brown wrote:
> The defines for SVCR call it SVCR_EL0 however the architecture calls the
> register SVCR with no _EL0 suffix. In preparation for generating the sysreg
> definitions rename to match the architecture, no functional change.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>

What's the "FIXME sysreg.h" in the title for? Is that an accidental
leftover, or is there something to do there?

Other than that this looks fine to me.

Thanks,
Mark.

> ---
>  arch/arm64/include/asm/fpsimd.h    |  4 ++--
>  arch/arm64/include/asm/processor.h |  2 +-
>  arch/arm64/include/asm/sysreg.h    |  6 +++---
>  arch/arm64/kernel/fpsimd.c         | 26 +++++++++++++-------------
>  arch/arm64/kernel/ptrace.c         |  8 ++++----
>  arch/arm64/kernel/signal.c         | 14 +++++++-------
>  arch/arm64/kernel/syscall.c        |  4 ++--
>  arch/arm64/kvm/fpsimd.c            |  4 ++--
>  arch/arm64/kvm/sys_regs.c          |  2 +-
>  9 files changed, 35 insertions(+), 35 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
> index aa11dbec0d70..9bb1873f5295 100644
> --- a/arch/arm64/include/asm/fpsimd.h
> +++ b/arch/arm64/include/asm/fpsimd.h
> @@ -67,12 +67,12 @@ extern void fpsimd_save_and_flush_cpu_state(void);
>  
>  static inline bool thread_sm_enabled(struct thread_struct *thread)
>  {
> -	return system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK);
> +	return system_supports_sme() && (thread->svcr & SVCR_SM_MASK);
>  }
>  
>  static inline bool thread_za_enabled(struct thread_struct *thread)
>  {
> -	return system_supports_sme() && (thread->svcr & SVCR_EL0_ZA_MASK);
> +	return system_supports_sme() && (thread->svcr & SVCR_ZA_MASK);
>  }
>  
>  /* Maximum VL that SVE/SME VL-agnostic software can transparently support */
> diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
> index 69ce163d2fb2..8de5a4fc06e3 100644
> --- a/arch/arm64/include/asm/processor.h
> +++ b/arch/arm64/include/asm/processor.h
> @@ -192,7 +192,7 @@ static inline unsigned int thread_get_sme_vl(struct thread_struct *thread)
>  
>  static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
>  {
> -	if (system_supports_sme() && (thread->svcr & SVCR_EL0_SM_MASK))
> +	if (system_supports_sme() && (thread->svcr & SVCR_SM_MASK))
>  		return thread_get_sme_vl(thread);
>  	else
>  		return thread_get_sve_vl(thread);
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 4459cd4a37f5..a2f0759f65b2 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -479,9 +479,9 @@
>  #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
>  #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
>  
> -#define SYS_SVCR_EL0			sys_reg(3, 3, 4, 2, 2)
> -#define SVCR_EL0_ZA_MASK		2
> -#define SVCR_EL0_SM_MASK		1
> +#define SYS_SVCR			sys_reg(3, 3, 4, 2, 2)
> +#define SVCR_ZA_MASK			2
> +#define SVCR_SM_MASK			1
>  
>  #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
>  #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
> diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
> index 8b48e870e14e..fbffafb55552 100644
> --- a/arch/arm64/kernel/fpsimd.c
> +++ b/arch/arm64/kernel/fpsimd.c
> @@ -398,7 +398,7 @@ static void task_fpsimd_load(void)
>  		if (test_thread_flag(TIF_SME))
>  			sme_set_vq(sve_vq_from_vl(sme_vl) - 1);
>  
> -		write_sysreg_s(current->thread.svcr, SYS_SVCR_EL0);
> +		write_sysreg_s(current->thread.svcr, SYS_SVCR);
>  
>  		if (thread_za_enabled(&current->thread))
>  			za_load_state(current->thread.za_state);
> @@ -450,15 +450,15 @@ static void fpsimd_save(void)
>  
>  	if (system_supports_sme()) {
>  		u64 *svcr = last->svcr;
> -		*svcr = read_sysreg_s(SYS_SVCR_EL0);
> +		*svcr = read_sysreg_s(SYS_SVCR);
>  
> -		*svcr = read_sysreg_s(SYS_SVCR_EL0);
> +		*svcr = read_sysreg_s(SYS_SVCR);
>  
> -		if (*svcr & SYS_SVCR_EL0_ZA_MASK)
> +		if (*svcr & SVCR_ZA_MASK)
>  			za_save_state(last->za_state);
>  
>  		/* If we are in streaming mode override regular SVE. */
> -		if (*svcr & SYS_SVCR_EL0_SM_MASK) {
> +		if (*svcr & SVCR_SM_MASK) {
>  			save_sve_regs = true;
>  			save_ffr = system_supports_fa64();
>  			vl = last->sme_vl;
> @@ -840,8 +840,8 @@ int vec_set_vector_length(struct task_struct *task, enum vec_type type,
>  		sve_to_fpsimd(task);
>  
>  	if (system_supports_sme() && type == ARM64_VEC_SME) {
> -		task->thread.svcr &= ~(SYS_SVCR_EL0_SM_MASK |
> -				       SYS_SVCR_EL0_ZA_MASK);
> +		task->thread.svcr &= ~(SVCR_SM_MASK |
> +				       SVCR_ZA_MASK);
>  		clear_thread_flag(TIF_SME);
>  	}
>  
> @@ -1890,10 +1890,10 @@ void __efi_fpsimd_begin(void)
>  			__this_cpu_write(efi_sve_state_used, true);
>  
>  			if (system_supports_sme()) {
> -				svcr = read_sysreg_s(SYS_SVCR_EL0);
> +				svcr = read_sysreg_s(SYS_SVCR);
>  
>  				if (!system_supports_fa64())
> -					ffr = svcr & SVCR_EL0_SM_MASK;
> +					ffr = svcr & SVCR_SM_MASK;
>  
>  				__this_cpu_write(efi_sm_state, ffr);
>  			}
> @@ -1903,8 +1903,8 @@ void __efi_fpsimd_begin(void)
>  				       ffr);
>  
>  			if (system_supports_sme())
> -				sysreg_clear_set_s(SYS_SVCR_EL0,
> -						   SVCR_EL0_SM_MASK, 0);
> +				sysreg_clear_set_s(SYS_SVCR,
> +						   SVCR_SM_MASK, 0);
>  
>  		} else {
>  			fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state));
> @@ -1937,9 +1937,9 @@ void __efi_fpsimd_end(void)
>  			 */
>  			if (system_supports_sme()) {
>  				if (__this_cpu_read(efi_sm_state)) {
> -					sysreg_clear_set_s(SYS_SVCR_EL0,
> +					sysreg_clear_set_s(SYS_SVCR,
>  							   0,
> -							   SVCR_EL0_SM_MASK);
> +							   SVCR_SM_MASK);
>  					if (!system_supports_fa64())
>  						ffr = efi_sm_state;
>  				}
> diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
> index 60ebc3060cf1..21da83187a60 100644
> --- a/arch/arm64/kernel/ptrace.c
> +++ b/arch/arm64/kernel/ptrace.c
> @@ -867,10 +867,10 @@ static int sve_set_common(struct task_struct *target,
>  
>  		switch (type) {
>  		case ARM64_VEC_SVE:
> -			target->thread.svcr &= ~SYS_SVCR_EL0_SM_MASK;
> +			target->thread.svcr &= ~SVCR_SM_MASK;
>  			break;
>  		case ARM64_VEC_SME:
> -			target->thread.svcr |= SYS_SVCR_EL0_SM_MASK;
> +			target->thread.svcr |= SVCR_SM_MASK;
>  			break;
>  		default:
>  			WARN_ON_ONCE(1);
> @@ -1100,7 +1100,7 @@ static int za_set(struct task_struct *target,
>  
>  	/* If there is no data then disable ZA */
>  	if (!count) {
> -		target->thread.svcr &= ~SYS_SVCR_EL0_ZA_MASK;
> +		target->thread.svcr &= ~SVCR_ZA_MASK;
>  		goto out;
>  	}
>  
> @@ -1125,7 +1125,7 @@ static int za_set(struct task_struct *target,
>  
>  	/* Mark ZA as active and let userspace use it */
>  	set_tsk_thread_flag(target, TIF_SME);
> -	target->thread.svcr |= SYS_SVCR_EL0_ZA_MASK;
> +	target->thread.svcr |= SVCR_ZA_MASK;
>  
>  out:
>  	fpsimd_flush_task_state(target);
> diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
> index 2295948d97fd..18bf590dc1c7 100644
> --- a/arch/arm64/kernel/signal.c
> +++ b/arch/arm64/kernel/signal.c
> @@ -288,7 +288,7 @@ static int restore_sve_fpsimd_context(struct user_ctxs *user)
>  
>  	if (sve.head.size <= sizeof(*user->sve)) {
>  		clear_thread_flag(TIF_SVE);
> -		current->thread.svcr &= ~SYS_SVCR_EL0_SM_MASK;
> +		current->thread.svcr &= ~SVCR_SM_MASK;
>  		goto fpsimd_only;
>  	}
>  
> @@ -321,7 +321,7 @@ static int restore_sve_fpsimd_context(struct user_ctxs *user)
>  		return -EFAULT;
>  
>  	if (sve.flags & SVE_SIG_FLAG_SM)
> -		current->thread.svcr |= SYS_SVCR_EL0_SM_MASK;
> +		current->thread.svcr |= SVCR_SM_MASK;
>  	else
>  		set_thread_flag(TIF_SVE);
>  
> @@ -398,7 +398,7 @@ static int restore_za_context(struct user_ctxs __user *user)
>  		return -EINVAL;
>  
>  	if (za.head.size <= sizeof(*user->za)) {
> -		current->thread.svcr &= ~SYS_SVCR_EL0_ZA_MASK;
> +		current->thread.svcr &= ~SVCR_ZA_MASK;
>  		return 0;
>  	}
>  
> @@ -419,7 +419,7 @@ static int restore_za_context(struct user_ctxs __user *user)
>  
>  	sme_alloc(current);
>  	if (!current->thread.za_state) {
> -		current->thread.svcr &= ~SYS_SVCR_EL0_ZA_MASK;
> +		current->thread.svcr &= ~SVCR_ZA_MASK;
>  		clear_thread_flag(TIF_SME);
>  		return -ENOMEM;
>  	}
> @@ -432,7 +432,7 @@ static int restore_za_context(struct user_ctxs __user *user)
>  		return -EFAULT;
>  
>  	set_thread_flag(TIF_SME);
> -	current->thread.svcr |= SYS_SVCR_EL0_ZA_MASK;
> +	current->thread.svcr |= SVCR_ZA_MASK;
>  
>  	return 0;
>  }
> @@ -922,8 +922,8 @@ static void setup_return(struct pt_regs *regs, struct k_sigaction *ka,
>  
>  	/* Signal handlers are invoked with ZA and streaming mode disabled */
>  	if (system_supports_sme()) {
> -		current->thread.svcr &= ~(SYS_SVCR_EL0_ZA_MASK |
> -					  SYS_SVCR_EL0_SM_MASK);
> +		current->thread.svcr &= ~(SVCR_ZA_MASK |
> +					  SVCR_SM_MASK);
>  		sme_smstop();
>  	}
>  
> diff --git a/arch/arm64/kernel/syscall.c b/arch/arm64/kernel/syscall.c
> index 92c69e5ac269..733451fe7e41 100644
> --- a/arch/arm64/kernel/syscall.c
> +++ b/arch/arm64/kernel/syscall.c
> @@ -174,9 +174,9 @@ static inline void fp_user_discard(void)
>  	 * need updating.
>  	 */
>  	if (system_supports_sme() && test_thread_flag(TIF_SME)) {
> -		u64 svcr = read_sysreg_s(SYS_SVCR_EL0);
> +		u64 svcr = read_sysreg_s(SYS_SVCR);
>  
> -		if (svcr & SYS_SVCR_EL0_SM_MASK)
> +		if (svcr & SVCR_SM_MASK)
>  			sme_smstop_sm();
>  	}
>  
> diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c
> index 441edb9c398c..3d251a4d2cf7 100644
> --- a/arch/arm64/kvm/fpsimd.c
> +++ b/arch/arm64/kvm/fpsimd.c
> @@ -96,8 +96,8 @@ void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu)
>  		if (read_sysreg(cpacr_el1) & CPACR_EL1_SMEN_EL0EN)
>  			vcpu->arch.flags |= KVM_ARM64_HOST_SME_ENABLED;
>  
> -		if (read_sysreg_s(SYS_SVCR_EL0) &
> -		    (SYS_SVCR_EL0_SM_MASK | SYS_SVCR_EL0_ZA_MASK)) {
> +		if (read_sysreg_s(SYS_SVCR) &
> +		    (SVCR_SM_MASK | SVCR_ZA_MASK)) {
>  			vcpu->arch.flags &= ~KVM_ARM64_FP_HOST;
>  			fpsimd_save_and_flush_cpu_state();
>  		}
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index a4ef986adb5e..f7f494961eda 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -1685,7 +1685,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>  	{ SYS_DESC(SYS_SMIDR_EL1), undef_access },
>  	{ SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
>  	{ SYS_DESC(SYS_CTR_EL0), access_ctr },
> -	{ SYS_DESC(SYS_SVCR_EL0), undef_access },
> +	{ SYS_DESC(SYS_SVCR), undef_access },
>  
>  	{ PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr,
>  	  .reset = reset_pmcr, .reg = PMCR_EL0 },
> -- 
> 2.30.2
> 

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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v1 06/12] arm64/sysreg: Support generation of RAZ fields
  2022-05-10 16:12 ` [PATCH v1 06/12] arm64/sysreg: Support generation of RAZ fields Mark Brown
@ 2022-05-13 14:18   ` Mark Rutland
  0 siblings, 0 replies; 23+ messages in thread
From: Mark Rutland @ 2022-05-13 14:18 UTC (permalink / raw)
  To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, Marc Zyngier, linux-arm-kernel

On Tue, May 10, 2022 at 05:12:02PM +0100, Mark Brown wrote:
> Add a statement for RAZ bitfields to the automatic register generation
> script. Nothing is emitted to the header for these fields.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>

Makes sense to me:

Acked-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> ---
>  arch/arm64/tools/gen-sysreg.awk | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
> index 3ffd77cbb499..b3f2bc072151 100755
> --- a/arch/arm64/tools/gen-sysreg.awk
> +++ b/arch/arm64/tools/gen-sysreg.awk
> @@ -226,6 +226,13 @@ END {
>  	next
>  }
>  
> +/^Raz/ && (block == "Sysreg" || block == "SysregFields") {
> +	expect_fields(2)
> +	parse_bitdef(reg, field, $2)
> +
> +	next
> +}
> +
>  /^Enum/ {
>  	change_block("Enum", "Sysreg", "Enum")
>  	expect_fields(3)
> -- 
> 2.30.2
> 

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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v1 07/12] arm64/sme: Automatically generate defines for SMCR
  2022-05-10 16:12 ` [PATCH v1 07/12] arm64/sme: Automatically generate defines for SMCR Mark Brown
@ 2022-05-13 14:31   ` Mark Rutland
  0 siblings, 0 replies; 23+ messages in thread
From: Mark Rutland @ 2022-05-13 14:31 UTC (permalink / raw)
  To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, Marc Zyngier, linux-arm-kernel

On Tue, May 10, 2022 at 05:12:03PM +0100, Mark Brown wrote:
> Convert SMCR to use the register definition code, no functional change.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 10 ----------
>  arch/arm64/tools/sysreg         | 20 ++++++++++++++++++++
>  2 files changed, 20 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index a2f0759f65b2..cbf03a1f316e 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -216,7 +216,6 @@
>  #define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
>  #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
>  #define SYS_SMPRI_EL1			sys_reg(3, 0, 1, 2, 4)
> -#define SYS_SMCR_EL1			sys_reg(3, 0, 1, 2, 6)
>  
>  #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
>  
> @@ -571,7 +570,6 @@
>  #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
>  #define SYS_HCRX_EL2			sys_reg(3, 4, 1, 2, 2)
>  #define SYS_SMPRIMAP_EL2		sys_reg(3, 4, 1, 2, 5)
> -#define SYS_SMCR_EL2			sys_reg(3, 4, 1, 2, 6)
>  #define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
>  #define SYS_HDFGRTR_EL2			sys_reg(3, 4, 3, 1, 4)
>  #define SYS_HDFGWTR_EL2			sys_reg(3, 4, 3, 1, 5)
> @@ -631,7 +629,6 @@
>  #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
>  #define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
>  #define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)
> -#define SYS_SMCR_EL12			sys_reg(3, 5, 1, 2, 6)
>  #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
>  #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
>  #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
> @@ -1117,13 +1114,6 @@
>  #define ZCR_ELx_LEN_WIDTH	4
>  #define ZCR_ELx_LEN_MASK	0xf
>  
> -#define SMCR_ELx_FA64_SHIFT	31
> -#define SMCR_ELx_FA64_MASK	(1 << SMCR_ELx_FA64_SHIFT)
> -
> -#define SMCR_ELx_LEN_SHIFT	0
> -#define SMCR_ELx_LEN_WIDTH	4
> -#define SMCR_ELx_LEN_MASK	0xf
> -
>  #define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
>  #define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
>  
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index c5619629bf9c..d0ac57648000 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -185,6 +185,26 @@ Field	1	A
>  Field	0	M
>  EndSysreg
>  
> +SysregFields	SMCR_ELx
> +Res0	63:32
> +Field	31	FA64
> +Res0	30:9
> +Raz	8:4
> +Field	3:0	LEN
> +EndSysregFields
> +
> +Sysreg	SMCR_EL1	3	0	1	2	6
> +Fields	SMCR_ELx
> +EndSysreg
> +
> +Sysreg	SMCR_EL2	3	4	1	2	6
> +Fields	SMCR_ELx
> +EndSysreg
> +
> +Sysreg	SMCR_EL12	3	5	1	2	6
> +Fields	SMCR_ELx
> +EndSysreg

These all look right to me, per ARM DDI 0487H.a, so:

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

One minor thing for the benefit of other reviewers: the ARM ARM
describes SMCR_ELx[8:4] as RAZ/WI. I think it's fine to capture that as
RAZ (since the script won't output anything, and just needs some field
type to check we've described all bits), but if other folk want that
captured as RAZ/WI specifically that's also fine by me.

Thanks,
Mark.

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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v1 08/12] arm64/sme: Automatically generate SMIDR_EL1 defines
  2022-05-10 16:12 ` [PATCH v1 08/12] arm64/sme: Automatically generate SMIDR_EL1 defines Mark Brown
@ 2022-05-13 14:35   ` Mark Rutland
  0 siblings, 0 replies; 23+ messages in thread
From: Mark Rutland @ 2022-05-13 14:35 UTC (permalink / raw)
  To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, Marc Zyngier, linux-arm-kernel

On Tue, May 10, 2022 at 05:12:04PM +0100, Mark Brown wrote:
> Automatically generate the defines for SMIDR_EL1, no functional change.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 1 -
>  arch/arm64/tools/sysreg         | 9 +++++++++
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index cbf03a1f316e..ce08a42637bc 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -463,7 +463,6 @@
>  #define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)
>  #define SYS_CLIDR_EL1			sys_reg(3, 1, 0, 0, 1)
>  #define SYS_GMID_EL1			sys_reg(3, 1, 0, 0, 4)
> -#define SYS_SMIDR_EL1			sys_reg(3, 1, 0, 0, 6)
>  #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
>  
>  #define SMIDR_EL1_IMPLEMENTER_SHIFT	24
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index d0ac57648000..1bf88ca3da5b 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -197,6 +197,15 @@ Sysreg	SMCR_EL1	3	0	1	2	6
>  Fields	SMCR_ELx
>  EndSysreg
>  
> +Sysreg	SMIDR_EL1	3	1	0	0	6
> +Res0	63:32
> +Field	31:24	IMPLEMENTER
> +Field	23:16	REVISION
> +Field	15	SMPS
> +Res0	14:12
> +Field	11:0	AFFINITY
> +EndSysreg

These all look right to me per ARM DDI 0487H.a, section D13.2.128, pages
D13-5937 to D13-5938.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> +
>  Sysreg	SMCR_EL2	3	4	1	2	6
>  Fields	SMCR_ELx
>  EndSysreg
> -- 
> 2.30.2
> 

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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v1 09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions
  2022-05-10 16:12 ` [PATCH v1 09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions Mark Brown
@ 2022-05-13 14:38   ` Mark Rutland
  0 siblings, 0 replies; 23+ messages in thread
From: Mark Rutland @ 2022-05-13 14:38 UTC (permalink / raw)
  To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, Marc Zyngier, linux-arm-kernel

On Tue, May 10, 2022 at 05:12:05PM +0100, Mark Brown wrote:
> No functional change should be seen from converting SMPRIMAP_EL2 to be
> generated.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h |  1 -
>  arch/arm64/tools/sysreg         | 19 +++++++++++++++++++
>  2 files changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index ce08a42637bc..2a9468d449fa 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -568,7 +568,6 @@
>  #define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)
>  #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
>  #define SYS_HCRX_EL2			sys_reg(3, 4, 1, 2, 2)
> -#define SYS_SMPRIMAP_EL2		sys_reg(3, 4, 1, 2, 5)
>  #define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
>  #define SYS_HDFGRTR_EL2			sys_reg(3, 4, 3, 1, 4)
>  #define SYS_HDFGWTR_EL2			sys_reg(3, 4, 3, 1, 5)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 1bf88ca3da5b..2cdcdac0465e 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -206,6 +206,25 @@ Res0	14:12
>  Field	11:0	AFFINITY
>  EndSysreg
>  
> +Sysreg	SMPRIMAP_EL2	3	4	1	2	5
> +Field	63:60	P15
> +Field	59:56	P14
> +Field	55:52	P13
> +Field	51:48	P12
> +Field	47:44	P11
> +Field	43:40	P10
> +Field	39:36	F9
> +Field	35:32	P8
> +Field	31:28	P7
> +Field	27:24	P6
> +Field	23:20	P5
> +Field	19:16	P4
> +Field	15:12	P3
> +Field	11:8	P2
> +Field	7:4	P1
> +Field	3:0	P0
> +EndSysreg

These all look right to me per ARM DDI 0487H.a, section D13.2.129, pages
D13-5939 to D13-5942.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> +
>  Sysreg	SMCR_EL2	3	4	1	2	6
>  Fields	SMCR_ELx
>  EndSysreg
> -- 
> 2.30.2
> 

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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v1 10/12] arm64/sme: Generate SMPRI_EL1 definitions
  2022-05-10 16:12 ` [PATCH v1 10/12] arm64/sme: Generate SMPRI_EL1 definitions Mark Brown
@ 2022-05-13 14:39   ` Mark Rutland
  0 siblings, 0 replies; 23+ messages in thread
From: Mark Rutland @ 2022-05-13 14:39 UTC (permalink / raw)
  To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, Marc Zyngier, linux-arm-kernel

On Tue, May 10, 2022 at 05:12:06PM +0100, Mark Brown wrote:
> Convert SMPRI_EL1 to be generated. No functional change.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 3 ---
>  arch/arm64/tools/sysreg         | 5 +++++
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 2a9468d449fa..b4affc3fd569 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -215,7 +215,6 @@
>  
>  #define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
>  #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
> -#define SYS_SMPRI_EL1			sys_reg(3, 0, 1, 2, 4)
>  
>  #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
>  
> @@ -406,8 +405,6 @@
>  #define TRBIDR_ALIGN_MASK		GENMASK(3, 0)
>  #define TRBIDR_ALIGN_SHIFT		0
>  
> -#define SMPRI_EL1_PRIORITY_MASK		0xf
> -
>  #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
>  #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
>  
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 2cdcdac0465e..d29bc429f504 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -185,6 +185,11 @@ Field	1	A
>  Field	0	M
>  EndSysreg
>  
> +Sysreg	SMPRI_EL1	3	0	1	2	4
> +Res0	63:4
> +Field	3:0	PRIORITY
> +EndSysreg

These all look right to me per ARM DDI 0487H.a, section D13.2.130, pages
D13-5943 to D13-5945.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> +
>  SysregFields	SMCR_ELx
>  Res0	63:32
>  Field	31	FA64
> -- 
> 2.30.2
> 

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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v1 11/12] arm64/sme: Generate defintions for SVCR
  2022-05-10 16:12 ` [PATCH v1 11/12] arm64/sme: Generate defintions for SVCR Mark Brown
@ 2022-05-13 14:41   ` Mark Rutland
  0 siblings, 0 replies; 23+ messages in thread
From: Mark Rutland @ 2022-05-13 14:41 UTC (permalink / raw)
  To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, Marc Zyngier, linux-arm-kernel

On Tue, May 10, 2022 at 05:12:07PM +0100, Mark Brown wrote:
> Convert SVCR to automatic generation, no functional change.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 4 ----
>  arch/arm64/tools/sysreg         | 6 ++++++
>  2 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index b4affc3fd569..804b5326c393 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -474,10 +474,6 @@
>  #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
>  #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
>  
> -#define SYS_SVCR			sys_reg(3, 3, 4, 2, 2)
> -#define SVCR_ZA_MASK			2
> -#define SVCR_SM_MASK			1
> -
>  #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
>  #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
>  #define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index d29bc429f504..7888603db50a 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -211,6 +211,12 @@ Res0	14:12
>  Field	11:0	AFFINITY
>  EndSysreg
>  
> +Sysreg	SVCR	3	3	4	2	2
> +Res0	63:2
> +Field	1	ZA
> +Field	0	SM
> +EndSysreg

These all look right to me per ARM DDI 0487H.a, section C5.2.25, pages
C5-747 to C5-749.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> +
>  Sysreg	SMPRIMAP_EL2	3	4	1	2	5
>  Field	63:60	P15
>  Field	59:56	P14
> -- 
> 2.30.2
> 

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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v1 12/12] arm64/sve: Generate ZCR definitions
  2022-05-10 16:12 ` [PATCH v1 12/12] arm64/sve: Generate ZCR definitions Mark Brown
@ 2022-05-13 14:46   ` Mark Rutland
  0 siblings, 0 replies; 23+ messages in thread
From: Mark Rutland @ 2022-05-13 14:46 UTC (permalink / raw)
  To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, Marc Zyngier, linux-arm-kernel

On Tue, May 10, 2022 at 05:12:08PM +0100, Mark Brown wrote:
> Convert the various ZCR instances to automatic generation, no functional
> changes expected.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h |  7 -------
>  arch/arm64/tools/sysreg         | 18 ++++++++++++++++++
>  2 files changed, 18 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 804b5326c393..91e4f8601393 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -213,7 +213,6 @@
>  #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
>  #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
>  
> -#define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
>  #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
>  
>  #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
> @@ -558,7 +557,6 @@
>  #define SYS_HFGRTR_EL2			sys_reg(3, 4, 1, 1, 4)
>  #define SYS_HFGWTR_EL2			sys_reg(3, 4, 1, 1, 5)
>  #define SYS_HFGITR_EL2			sys_reg(3, 4, 1, 1, 6)
> -#define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)
>  #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
>  #define SYS_HCRX_EL2			sys_reg(3, 4, 1, 2, 2)
>  #define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
> @@ -619,7 +617,6 @@
>  /* VHE encodings for architectural EL0/1 system registers */
>  #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
>  #define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
> -#define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)
>  #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
>  #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
>  #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
> @@ -1101,10 +1098,6 @@
>  #define DCZID_DZP_SHIFT			4
>  #define DCZID_BS_SHIFT			0
>  
> -#define ZCR_ELx_LEN_SHIFT	0
> -#define ZCR_ELx_LEN_WIDTH	4
> -#define ZCR_ELx_LEN_MASK	0xf
> -
>  #define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
>  #define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
>  
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 7888603db50a..a236d7a821b4 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -190,6 +190,16 @@ Res0	63:4
>  Field	3:0	PRIORITY
>  EndSysreg
>  
> +SysregFields	ZCR_ELx
> +Res0	63:9
> +Raz	8:4
> +Field	3:0	LEN
> +EndSysregFields
> +
> +Sysreg ZCR_EL1	3	0	1	2	0
> +Fields ZCR_ELx
> +EndSysreg
> +
>  SysregFields	SMCR_ELx
>  Res0	63:32
>  Field	31	FA64
> @@ -217,6 +227,10 @@ Field	1	ZA
>  Field	0	SM
>  EndSysreg
>  
> +Sysreg	ZCR_EL2	3	4	1	2	0
> +Fields	ZCR_ELx
> +EndSysreg
> +
>  Sysreg	SMPRIMAP_EL2	3	4	1	2	5
>  Field	63:60	P15
>  Field	59:56	P14
> @@ -240,6 +254,10 @@ Sysreg	SMCR_EL2	3	4	1	2	6
>  Fields	SMCR_ELx
>  EndSysreg
>  
> +Sysreg	ZCR_EL12	3	5	1	2	0
> +Fields	ZCR_ELx
> +EndSysreg
> +
>  Sysreg	SMCR_EL12	3	5	1	2	6
>  Fields	SMCR_ELx
>  EndSysreg

These all look right to me per ARM DDI 0487H.a:

* ZCR_EL1:  pages D13-6071 to D13-6072
* ZCR_EL12: pages D13-6073 to D13-6074
* ZCR_EL2:  pages D13-6076 to D13-6077

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

As on another patch, I'm fine either way with capturing RAZ/WI as RAZ.

Mark.

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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v1 05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h
  2022-05-13 14:16   ` Mark Rutland
@ 2022-05-13 19:39     ` Mark Brown
  0 siblings, 0 replies; 23+ messages in thread
From: Mark Brown @ 2022-05-13 19:39 UTC (permalink / raw)
  To: Mark Rutland; +Cc: Catalin Marinas, Will Deacon, Marc Zyngier, linux-arm-kernel


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On Fri, May 13, 2022 at 03:16:44PM +0100, Mark Rutland wrote:
> On Tue, May 10, 2022 at 05:12:01PM +0100, Mark Brown wrote:
> > The defines for SVCR call it SVCR_EL0 however the architecture calls the
> > register SVCR with no _EL0 suffix. In preparation for generating the sysreg
> > definitions rename to match the architecture, no functional change.

> What's the "FIXME sysreg.h" in the title for? Is that an accidental
> leftover, or is there something to do there?

That's an accidental leftover, sorry.

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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers
  2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
                   ` (11 preceding siblings ...)
  2022-05-10 16:12 ` [PATCH v1 12/12] arm64/sve: Generate ZCR definitions Mark Brown
@ 2022-05-16 19:08 ` Catalin Marinas
  12 siblings, 0 replies; 23+ messages in thread
From: Catalin Marinas @ 2022-05-16 19:08 UTC (permalink / raw)
  To: Mark Brown, Will Deacon; +Cc: Mark Rutland, linux-arm-kernel, Marc Zyngier

On Tue, 10 May 2022 17:11:56 +0100, Mark Brown wrote:
> This series builds on top of the recently applied series for system
> register generation, converting the floating point registers to
> automatic generation. There's nothing remarkable in here, just a bunch
> of straightforward cleanups and the addition of support for RAZ fields
> followed by the actual conversions.
> 
> It does skip over the SVCRSM, SVCRZA and SVCRSMZA aliases for now since
> I need to think a little about what to do with those.
> 
> [...]

Applied to arm64 (for-next/sysreg-gen), thanks!

(I merged for-next/sme into this branch for dependencies)

[01/12] arm64/fp: Make SVE and SME length register definition match architecture
        https://git.kernel.org/arm64/c/f171f9e4097d
[02/12] arm64/fp: Rename SVE and SME LEN field name to _WIDTH
        https://git.kernel.org/arm64/c/5b06dcfd9e0a
[03/12] arm64/sme: Drop SYS_ from SMIDR_EL1 defines
        https://git.kernel.org/arm64/c/a6dab6cc0f4c
[04/12] arm64/sme: Standardise bitfield names for SVCR
        https://git.kernel.org/arm64/c/e65fc01bf271
[05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h
        https://git.kernel.org/arm64/c/ec0067a63e5a
[06/12] arm64/sysreg: Support generation of RAZ fields
        https://git.kernel.org/arm64/c/9e2c0819ac85
[07/12] arm64/sme: Automatically generate defines for SMCR
        https://git.kernel.org/arm64/c/0d1322e7ea75
[08/12] arm64/sme: Automatically generate SMIDR_EL1 defines
        https://git.kernel.org/arm64/c/c37b8700b723
[09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions
        https://git.kernel.org/arm64/c/8e053810e6ce
[10/12] arm64/sme: Generate SMPRI_EL1 definitions
        https://git.kernel.org/arm64/c/9321f0492b89
[11/12] arm64/sme: Generate defintions for SVCR
        https://git.kernel.org/arm64/c/11e12a91c118
[12/12] arm64/sve: Generate ZCR definitions
        https://git.kernel.org/arm64/c/89e9fb327421

-- 
Catalin


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^ permalink raw reply	[flat|nested] 23+ messages in thread
end of thread, other threads:[~2022-05-16 19:09 UTC | newest]

Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
2022-05-10 16:11 ` [PATCH v1 01/12] arm64/fp: Make SVE and SME length register definition match architecture Mark Brown
2022-05-10 16:11 ` [PATCH v1 02/12] arm64/fp: Rename SVE and SME LEN field name to _WIDTH Mark Brown
2022-05-10 16:11 ` [PATCH v1 03/12] arm64/sme: Drop SYS_ from SMIDR_EL1 defines Mark Brown
2022-05-10 16:12 ` [PATCH v1 04/12] arm64/sme: Standardise bitfield names for SVCR Mark Brown
2022-05-10 16:12 ` [PATCH v1 05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h Mark Brown
2022-05-13 14:16   ` Mark Rutland
2022-05-13 19:39     ` Mark Brown
2022-05-10 16:12 ` [PATCH v1 06/12] arm64/sysreg: Support generation of RAZ fields Mark Brown
2022-05-13 14:18   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 07/12] arm64/sme: Automatically generate defines for SMCR Mark Brown
2022-05-13 14:31   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 08/12] arm64/sme: Automatically generate SMIDR_EL1 defines Mark Brown
2022-05-13 14:35   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions Mark Brown
2022-05-13 14:38   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 10/12] arm64/sme: Generate SMPRI_EL1 definitions Mark Brown
2022-05-13 14:39   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 11/12] arm64/sme: Generate defintions for SVCR Mark Brown
2022-05-13 14:41   ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 12/12] arm64/sve: Generate ZCR definitions Mark Brown
2022-05-13 14:46   ` Mark Rutland
2022-05-16 19:08 ` [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Catalin Marinas

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