[PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

This is an attempt to resurrect the mainline WNR854T support (I had no
luck getting a non-DT kernel to boot). First 2 patches are trivial,
the next 3 add DT bindings for the SoC, then the old board file is
swapped out for DT. The final 3 patches configure the PHY leds as
Netgear intended.

There's one major flaw; unicast traffic is never received on any port.
Broadcast traffic is received however, and on the correct port. Thus
an external machine can make an ARP request and get a response, for
example. With a manually-entered ARP entry, the router can send pings
out to a remote machine which responds, and the response is lost in the
DSA switch. "ethtool -S" reports pings received on "in_unicast" but
nothing makes it through the switch. This thread[0] seems very similar.
I've run out of ideas here and can't find any switch datasheets to give
me pointers so any suggestions greatly appreciated.

I've not tried to move the PCI support into DT yet. Are there other
branches that tackle this already?

Patch 8 is the least-intrusive patch I could think of to find the PHY
node, but I'm not sure it's the best approach. I tried to get
dsa_slave_phy_connect() to wire up the OF node correctly[1], but doing
this properly would require changes to the mdiobus api, any exposed
methods register all nodes in an MDIO bus node, which doesn't exist in
this case.

Applied against v4.6 mainline, .config:
http://jamie.lentin.co.uk/devices/netgear-wnr854t/wnr854t-support-v0a/kernel-config.txt
Log output:
http://jamie.lentin.co.uk/devices/netgear-wnr854t/wnr854t-support-v0a/u-boot.dmesg.txt

The patchset is also available here:
https://github.com/lentinj/linux/commits/wnr854t-support-v0a

To use the supplied PCI Wifi card see the following patch:
https://github.com/lentinj/linux/commit/d6b7b4695b7dcbf36d0663aea9cb4ecd65a1ada8
...but this is probably a matter for another thread.

Cheers,

[0] http://thread.gmane.org/gmane.linux.network/120616/focus=121320
[1] https://github.com/lentinj/linux/commit/a4bceebb08ecdc25a4d49e23f2abad214868460e

Jamie Lentin (10):
  arm: orion5x: Add required properties for orion-wdt to DT node
  arm: orion5x: Add documentation for SoC and board bindings
  arm: orion5x: Add clk support for mv88f5181
  arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181
  arm: orion5x: Add DT include for mv88f5181
  arm: orion5x: Add DT-based support for Netgear WNR854T
  arm: orion5x: Remove old non-DT-based WNR854T support
  net: phy: Try looking for a phy-handle property to find the OF node
  net: phy: Re-attempt custom DT configuration after configuration
  arm: orion5x: Configure Netgear WNR854T network port LEDs

 .../bindings/arm/marvell/marvell,orion5x.txt       |  25 +++
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   1 +
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |   4 +-
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           |  35 +++
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 245 +++++++++++++++++++++
 arch/arm/boot/dts/orion5x.dtsi                     |   3 +-
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   2 +-
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 +++++++
 arch/arm/mach-orion5x/wnr854t-setup.c              | 185 ----------------
 drivers/clk/mvebu/orion.c                          |  70 ++++++
 drivers/net/phy/marvell.c                          |  26 ++-
 drivers/pinctrl/mvebu/pinctrl-orion.c              |  23 +-
 14 files changed, 498 insertions(+), 206 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
 delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c

-- 
2.8.1

[PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

This is an attempt to resurrect the mainline WNR854T support (I had no
luck getting a non-DT kernel to boot). First 2 patches are trivial,
the next 3 add DT bindings for the SoC, then the old board file is
swapped out for DT. The final 3 patches configure the PHY leds as
Netgear intended.

There's one major flaw; unicast traffic is never received on any port.
Broadcast traffic is received however, and on the correct port. Thus
an external machine can make an ARP request and get a response, for
example. With a manually-entered ARP entry, the router can send pings
out to a remote machine which responds, and the response is lost in the
DSA switch. "ethtool -S" reports pings received on "in_unicast" but
nothing makes it through the switch. This thread[0] seems very similar.
I've run out of ideas here and can't find any switch datasheets to give
me pointers so any suggestions greatly appreciated.

I've not tried to move the PCI support into DT yet. Are there other
branches that tackle this already?

Patch 8 is the least-intrusive patch I could think of to find the PHY
node, but I'm not sure it's the best approach. I tried to get
dsa_slave_phy_connect() to wire up the OF node correctly[1], but doing
this properly would require changes to the mdiobus api, any exposed
methods register all nodes in an MDIO bus node, which doesn't exist in
this case.

Applied against v4.6 mainline, .config:
http://jamie.lentin.co.uk/devices/netgear-wnr854t/wnr854t-support-v0a/kernel-config.txt
Log output:
http://jamie.lentin.co.uk/devices/netgear-wnr854t/wnr854t-support-v0a/u-boot.dmesg.txt

The patchset is also available here:
https://github.com/lentinj/linux/commits/wnr854t-support-v0a

To use the supplied PCI Wifi card see the following patch:
https://github.com/lentinj/linux/commit/d6b7b4695b7dcbf36d0663aea9cb4ecd65a1ada8
...but this is probably a matter for another thread.

Cheers,

[0] http://thread.gmane.org/gmane.linux.network/120616/focus=121320
[1] https://github.com/lentinj/linux/commit/a4bceebb08ecdc25a4d49e23f2abad214868460e

Jamie Lentin (10):
  arm: orion5x: Add required properties for orion-wdt to DT node
  arm: orion5x: Add documentation for SoC and board bindings
  arm: orion5x: Add clk support for mv88f5181
  arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181
  arm: orion5x: Add DT include for mv88f5181
  arm: orion5x: Add DT-based support for Netgear WNR854T
  arm: orion5x: Remove old non-DT-based WNR854T support
  net: phy: Try looking for a phy-handle property to find the OF node
  net: phy: Re-attempt custom DT configuration after configuration
  arm: orion5x: Configure Netgear WNR854T network port LEDs

 .../bindings/arm/marvell/marvell,orion5x.txt       |  25 +++
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   1 +
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |   4 +-
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           |  35 +++
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 245 +++++++++++++++++++++
 arch/arm/boot/dts/orion5x.dtsi                     |   3 +-
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   2 +-
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 +++++++
 arch/arm/mach-orion5x/wnr854t-setup.c              | 185 ----------------
 drivers/clk/mvebu/orion.c                          |  70 ++++++
 drivers/net/phy/marvell.c                          |  26 ++-
 drivers/pinctrl/mvebu/pinctrl-orion.c              |  23 +-
 14 files changed, 498 insertions(+), 206 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
 delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c

-- 
2.8.1

[PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

This is an attempt to resurrect the mainline WNR854T support (I had no
luck getting a non-DT kernel to boot). First 2 patches are trivial,
the next 3 add DT bindings for the SoC, then the old board file is
swapped out for DT. The final 3 patches configure the PHY leds as
Netgear intended.

There's one major flaw; unicast traffic is never received on any port.
Broadcast traffic is received however, and on the correct port. Thus
an external machine can make an ARP request and get a response, for
example. With a manually-entered ARP entry, the router can send pings
out to a remote machine which responds, and the response is lost in the
DSA switch. "ethtool -S" reports pings received on "in_unicast" but
nothing makes it through the switch. This thread[0] seems very similar.
I've run out of ideas here and can't find any switch datasheets to give
me pointers so any suggestions greatly appreciated.

I've not tried to move the PCI support into DT yet. Are there other
branches that tackle this already?

Patch 8 is the least-intrusive patch I could think of to find the PHY
node, but I'm not sure it's the best approach. I tried to get
dsa_slave_phy_connect() to wire up the OF node correctly[1], but doing
this properly would require changes to the mdiobus api, any exposed
methods register all nodes in an MDIO bus node, which doesn't exist in
this case.

Applied against v4.6 mainline, .config:
http://jamie.lentin.co.uk/devices/netgear-wnr854t/wnr854t-support-v0a/kernel-config.txt
Log output:
http://jamie.lentin.co.uk/devices/netgear-wnr854t/wnr854t-support-v0a/u-boot.dmesg.txt

The patchset is also available here:
https://github.com/lentinj/linux/commits/wnr854t-support-v0a

To use the supplied PCI Wifi card see the following patch:
https://github.com/lentinj/linux/commit/d6b7b4695b7dcbf36d0663aea9cb4ecd65a1ada8
...but this is probably a matter for another thread.

Cheers,

[0] http://thread.gmane.org/gmane.linux.network/120616/focus=121320
[1] https://github.com/lentinj/linux/commit/a4bceebb08ecdc25a4d49e23f2abad214868460e

Jamie Lentin (10):
  arm: orion5x: Add required properties for orion-wdt to DT node
  arm: orion5x: Add documentation for SoC and board bindings
  arm: orion5x: Add clk support for mv88f5181
  arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181
  arm: orion5x: Add DT include for mv88f5181
  arm: orion5x: Add DT-based support for Netgear WNR854T
  arm: orion5x: Remove old non-DT-based WNR854T support
  net: phy: Try looking for a phy-handle property to find the OF node
  net: phy: Re-attempt custom DT configuration after configuration
  arm: orion5x: Configure Netgear WNR854T network port LEDs

 .../bindings/arm/marvell/marvell,orion5x.txt       |  25 +++
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   1 +
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |   4 +-
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           |  35 +++
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 245 +++++++++++++++++++++
 arch/arm/boot/dts/orion5x.dtsi                     |   3 +-
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   2 +-
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 +++++++
 arch/arm/mach-orion5x/wnr854t-setup.c              | 185 ----------------
 drivers/clk/mvebu/orion.c                          |  70 ++++++
 drivers/net/phy/marvell.c                          |  26 ++-
 drivers/pinctrl/mvebu/pinctrl-orion.c              |  23 +-
 14 files changed, 498 insertions(+), 206 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
 delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c

-- 
2.8.1

[PATCH v0 01/10] arm: orion5x: Add required properties for orion-wdt to DT node

[Jamie Lentin]

orion-wdt refuses to start without these properties defined, so lift
definitions out of kirkwood/dove.dtsi

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 arch/arm/boot/dts/orion5x.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index e1b6d2a..fbccfbb 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -144,9 +144,10 @@
 
 			wdt: wdt@20300 {
 				compatible = "marvell,orion-wdt";
-				reg = <0x20300 0x28>;
+				reg = <0x20300 0x28>, <0x20108 0x4>;
 				interrupt-parent = <&bridge_intc>;
 				interrupts = <3>;
+				clocks = <&core_clk 0>;
 				status = "okay";
 			};
 
-- 
2.8.1

[PATCH v0 01/10] arm: orion5x: Add required properties for orion-wdt to DT node

[Jamie Lentin]

orion-wdt refuses to start without these properties defined, so lift
definitions out of kirkwood/dove.dtsi

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 arch/arm/boot/dts/orion5x.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index e1b6d2a..fbccfbb 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -144,9 +144,10 @@
 
 			wdt: wdt at 20300 {
 				compatible = "marvell,orion-wdt";
-				reg = <0x20300 0x28>;
+				reg = <0x20300 0x28>, <0x20108 0x4>;
 				interrupt-parent = <&bridge_intc>;
 				interrupts = <3>;
+				clocks = <&core_clk 0>;
 				status = "okay";
 			};
 
-- 
2.8.1

[PATCH v0 01/10] arm: orion5x: Add required properties for orion-wdt to DT node

[Jamie Lentin]

orion-wdt refuses to start without these properties defined, so lift
definitions out of kirkwood/dove.dtsi

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 arch/arm/boot/dts/orion5x.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index e1b6d2a..fbccfbb 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -144,9 +144,10 @@
 
 			wdt: wdt@20300 {
 				compatible = "marvell,orion-wdt";
-				reg = <0x20300 0x28>;
+				reg = <0x20300 0x28>, <0x20108 0x4>;
 				interrupt-parent = <&bridge_intc>;
 				interrupts = <3>;
+				clocks = <&core_clk 0>;
 				status = "okay";
 			};
 
-- 
2.8.1

Re: [PATCH v0 01/10] arm: orion5x: Add required properties for orion-wdt to DT node

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:28:59PM +0100, Jamie Lentin wrote:
> orion-wdt refuses to start without these properties defined, so lift
> definitions out of kirkwood/dove.dtsi
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew


> ---
>  arch/arm/boot/dts/orion5x.dtsi | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
> index e1b6d2a..fbccfbb 100644
> --- a/arch/arm/boot/dts/orion5x.dtsi
> +++ b/arch/arm/boot/dts/orion5x.dtsi
> @@ -144,9 +144,10 @@
>  
>  			wdt: wdt@20300 {
>  				compatible = "marvell,orion-wdt";
> -				reg = <0x20300 0x28>;
> +				reg = <0x20300 0x28>, <0x20108 0x4>;
>  				interrupt-parent = <&bridge_intc>;
>  				interrupts = <3>;
> +				clocks = <&core_clk 0>;
>  				status = "okay";
>  			};
>  
> -- 
> 2.8.1
> 

[PATCH v0 01/10] arm: orion5x: Add required properties for orion-wdt to DT node

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:28:59PM +0100, Jamie Lentin wrote:
> orion-wdt refuses to start without these properties defined, so lift
> definitions out of kirkwood/dove.dtsi
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew


> ---
>  arch/arm/boot/dts/orion5x.dtsi | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
> index e1b6d2a..fbccfbb 100644
> --- a/arch/arm/boot/dts/orion5x.dtsi
> +++ b/arch/arm/boot/dts/orion5x.dtsi
> @@ -144,9 +144,10 @@
>  
>  			wdt: wdt at 20300 {
>  				compatible = "marvell,orion-wdt";
> -				reg = <0x20300 0x28>;
> +				reg = <0x20300 0x28>, <0x20108 0x4>;
>  				interrupt-parent = <&bridge_intc>;
>  				interrupts = <3>;
> +				clocks = <&core_clk 0>;
>  				status = "okay";
>  			};
>  
> -- 
> 2.8.1
> 

[PATCH v0 02/10] arm: orion5x: Add documentation for SoC and board bindings

[Jamie Lentin]

Copy the format for kirkwood/dove to orion5x

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
new file mode 100644
index 0000000..a888011
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -0,0 +1,23 @@
+Marvell Orion SoC Family Device Tree Bindings
+---------------------------------------------
+
+Boards with a SoC of the Marvell Orion family, eg 88f5181
+
+* Required root node properties:
+compatible: must contain "marvell,orion5x"
+
+In addition, the above compatible shall be extended with the specific
+SoC. Currently known SoC compatibles are:
+
+"marvell,orion5x-88f5182"
+
+And in addition, the compatible shall be extended with the specific
+board. Currently known boards are:
+
+"buffalo,lsgl"
+"buffalo,lswsgl"
+"buffalo,lswtgl"
+"lacie,ethernet-disk-mini-v2"
+"lacie,d2-network"
+"marvell,rd-88f5182-nas"
+"maxtor,shared-storage-2"
-- 
2.8.1

[PATCH v0 02/10] arm: orion5x: Add documentation for SoC and board bindings

[Jamie Lentin]

Copy the format for kirkwood/dove to orion5x

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
new file mode 100644
index 0000000..a888011
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -0,0 +1,23 @@
+Marvell Orion SoC Family Device Tree Bindings
+---------------------------------------------
+
+Boards with a SoC of the Marvell Orion family, eg 88f5181
+
+* Required root node properties:
+compatible: must contain "marvell,orion5x"
+
+In addition, the above compatible shall be extended with the specific
+SoC. Currently known SoC compatibles are:
+
+"marvell,orion5x-88f5182"
+
+And in addition, the compatible shall be extended with the specific
+board. Currently known boards are:
+
+"buffalo,lsgl"
+"buffalo,lswsgl"
+"buffalo,lswtgl"
+"lacie,ethernet-disk-mini-v2"
+"lacie,d2-network"
+"marvell,rd-88f5182-nas"
+"maxtor,shared-storage-2"
-- 
2.8.1

[PATCH v0 02/10] arm: orion5x: Add documentation for SoC and board bindings

[Jamie Lentin]

Copy the format for kirkwood/dove to orion5x

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
new file mode 100644
index 0000000..a888011
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -0,0 +1,23 @@
+Marvell Orion SoC Family Device Tree Bindings
+---------------------------------------------
+
+Boards with a SoC of the Marvell Orion family, eg 88f5181
+
+* Required root node properties:
+compatible: must contain "marvell,orion5x"
+
+In addition, the above compatible shall be extended with the specific
+SoC. Currently known SoC compatibles are:
+
+"marvell,orion5x-88f5182"
+
+And in addition, the compatible shall be extended with the specific
+board. Currently known boards are:
+
+"buffalo,lsgl"
+"buffalo,lswsgl"
+"buffalo,lswtgl"
+"lacie,ethernet-disk-mini-v2"
+"lacie,d2-network"
+"marvell,rd-88f5182-nas"
+"maxtor,shared-storage-2"
-- 
2.8.1

Re: [PATCH v0 02/10] arm: orion5x: Add documentation for SoC and board bindings

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:00PM +0100, Jamie Lentin wrote:
> Copy the format for kirkwood/dove to orion5x
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

[PATCH v0 02/10] arm: orion5x: Add documentation for SoC and board bindings

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:00PM +0100, Jamie Lentin wrote:
> Copy the format for kirkwood/dove to orion5x
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH v0 02/10] arm: orion5x: Add documentation for SoC and board bindings

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:00PM +0100, Jamie Lentin wrote:
> Copy the format for kirkwood/dove to orion5x
> 
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>

Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>

    Andrew
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Re: [PATCH v0 02/10] arm: orion5x: Add documentation for SoC and board bindings

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:00PM +0100, Jamie Lentin wrote:
> Copy the format for kirkwood/dove to orion5x
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v0 02/10] arm: orion5x: Add documentation for SoC and board bindings

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:00PM +0100, Jamie Lentin wrote:
> Copy the format for kirkwood/dove to orion5x
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v0 02/10] arm: orion5x: Add documentation for SoC and board bindings

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:00PM +0100, Jamie Lentin wrote:
> Copy the format for kirkwood/dove to orion5x
> 
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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[PATCH v0 03/10] arm: orion5x: Add clk support for mv88f5181

[Jamie Lentin]

Referring to values in the u-boot port, add support for the mv88f5181

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |  1 +
 drivers/clk/mvebu/orion.c                          | 70 ++++++++++++++++++++++
 2 files changed, 71 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 670c2af..eb985a6 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -52,6 +52,7 @@ Required properties:
 	"marvell,dove-core-clock" - for Dove SoC core clocks
 	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
 	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
+	"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
 	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
 	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
 	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
index fd12956..a6e5bee 100644
--- a/drivers/clk/mvebu/orion.c
+++ b/drivers/clk/mvebu/orion.c
@@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
 };
 
 /*
+ * Orion 5181
+ */
+
+#define SAR_MV88F5181_TCLK_FREQ      8
+#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
+
+static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
+		SAR_MV88F5181_TCLK_FREQ_MASK;
+	if (opt == 0)
+		return 133333333;
+	else if (opt == 1)
+		return 150000000;
+	else if (opt == 2)
+		return 166666667;
+	else
+		return 0;
+}
+
+#define SAR_MV88F5181_CPU_FREQ       4
+#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
+
+static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0)
+		return 333333333;
+	else if (opt == 1 || opt == 2)
+		return 400000000;
+	else if (opt == 3)
+		return 500000000;
+	else
+		return 0;
+}
+
+static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0 || opt == 1) {
+		*mult = 1;
+		*div  = 2;
+	} else if (opt == 2 || opt == 3) {
+		*mult = 1;
+		*div  = 3;
+	} else {
+		*mult = 0;
+		*div  = 1;
+	}
+}
+
+static const struct coreclk_soc_desc mv88f5181_coreclks = {
+	.get_tclk_freq = mv88f5181_get_tclk_freq,
+	.get_cpu_freq = mv88f5181_get_cpu_freq,
+	.get_clk_ratio = mv88f5181_get_clk_ratio,
+	.ratios = orion_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
+};
+
+static void __init mv88f5181_clk_init(struct device_node *np)
+{
+	return mvebu_coreclk_setup(np, &mv88f5181_coreclks);
+}
+
+CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);
+
+/*
  * Orion 5182
  */
 
-- 
2.8.1

[PATCH v0 03/10] arm: orion5x: Add clk support for mv88f5181

[Jamie Lentin]

Referring to values in the u-boot port, add support for the mv88f5181

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |  1 +
 drivers/clk/mvebu/orion.c                          | 70 ++++++++++++++++++++++
 2 files changed, 71 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 670c2af..eb985a6 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -52,6 +52,7 @@ Required properties:
 	"marvell,dove-core-clock" - for Dove SoC core clocks
 	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
 	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
+	"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
 	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
 	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
 	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
index fd12956..a6e5bee 100644
--- a/drivers/clk/mvebu/orion.c
+++ b/drivers/clk/mvebu/orion.c
@@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
 };
 
 /*
+ * Orion 5181
+ */
+
+#define SAR_MV88F5181_TCLK_FREQ      8
+#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
+
+static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
+		SAR_MV88F5181_TCLK_FREQ_MASK;
+	if (opt == 0)
+		return 133333333;
+	else if (opt == 1)
+		return 150000000;
+	else if (opt == 2)
+		return 166666667;
+	else
+		return 0;
+}
+
+#define SAR_MV88F5181_CPU_FREQ       4
+#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
+
+static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0)
+		return 333333333;
+	else if (opt == 1 || opt == 2)
+		return 400000000;
+	else if (opt == 3)
+		return 500000000;
+	else
+		return 0;
+}
+
+static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0 || opt == 1) {
+		*mult = 1;
+		*div  = 2;
+	} else if (opt == 2 || opt == 3) {
+		*mult = 1;
+		*div  = 3;
+	} else {
+		*mult = 0;
+		*div  = 1;
+	}
+}
+
+static const struct coreclk_soc_desc mv88f5181_coreclks = {
+	.get_tclk_freq = mv88f5181_get_tclk_freq,
+	.get_cpu_freq = mv88f5181_get_cpu_freq,
+	.get_clk_ratio = mv88f5181_get_clk_ratio,
+	.ratios = orion_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
+};
+
+static void __init mv88f5181_clk_init(struct device_node *np)
+{
+	return mvebu_coreclk_setup(np, &mv88f5181_coreclks);
+}
+
+CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);
+
+/*
  * Orion 5182
  */
 
-- 
2.8.1

[PATCH v0 03/10] arm: orion5x: Add clk support for mv88f5181

[Jamie Lentin]

Referring to values in the u-boot port, add support for the mv88f5181

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |  1 +
 drivers/clk/mvebu/orion.c                          | 70 ++++++++++++++++++++++
 2 files changed, 71 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 670c2af..eb985a6 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -52,6 +52,7 @@ Required properties:
 	"marvell,dove-core-clock" - for Dove SoC core clocks
 	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
 	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
+	"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
 	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
 	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
 	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
index fd12956..a6e5bee 100644
--- a/drivers/clk/mvebu/orion.c
+++ b/drivers/clk/mvebu/orion.c
@@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
 };
 
 /*
+ * Orion 5181
+ */
+
+#define SAR_MV88F5181_TCLK_FREQ      8
+#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
+
+static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
+		SAR_MV88F5181_TCLK_FREQ_MASK;
+	if (opt == 0)
+		return 133333333;
+	else if (opt == 1)
+		return 150000000;
+	else if (opt == 2)
+		return 166666667;
+	else
+		return 0;
+}
+
+#define SAR_MV88F5181_CPU_FREQ       4
+#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
+
+static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0)
+		return 333333333;
+	else if (opt == 1 || opt == 2)
+		return 400000000;
+	else if (opt == 3)
+		return 500000000;
+	else
+		return 0;
+}
+
+static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0 || opt == 1) {
+		*mult = 1;
+		*div  = 2;
+	} else if (opt == 2 || opt == 3) {
+		*mult = 1;
+		*div  = 3;
+	} else {
+		*mult = 0;
+		*div  = 1;
+	}
+}
+
+static const struct coreclk_soc_desc mv88f5181_coreclks = {
+	.get_tclk_freq = mv88f5181_get_tclk_freq,
+	.get_cpu_freq = mv88f5181_get_cpu_freq,
+	.get_clk_ratio = mv88f5181_get_clk_ratio,
+	.ratios = orion_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
+};
+
+static void __init mv88f5181_clk_init(struct device_node *np)
+{
+	return mvebu_coreclk_setup(np, &mv88f5181_coreclks);
+}
+
+CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);
+
+/*
  * Orion 5182
  */
 
-- 
2.8.1

Re: [PATCH v0 03/10] arm: orion5x: Add clk support for mv88f5181

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:01PM +0100, Jamie Lentin wrote:
> Referring to values in the u-boot port, add support for the mv88f5181
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

[PATCH v0 03/10] arm: orion5x: Add clk support for mv88f5181

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:01PM +0100, Jamie Lentin wrote:
> Referring to values in the u-boot port, add support for the mv88f5181
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH v0 03/10] arm: orion5x: Add clk support for mv88f5181

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:01PM +0100, Jamie Lentin wrote:
> Referring to values in the u-boot port, add support for the mv88f5181
> 
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>

Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>

    Andrew
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Re: [PATCH v0 03/10] arm: orion5x: Add clk support for mv88f5181

[Sergei Shtylyov]

Hello.

On 7/16/2016 5:29 PM, Jamie Lentin wrote:

> Referring to values in the u-boot port, add support for the mv88f5181
>
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>

[...]
> diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
> index fd12956..a6e5bee 100644
> --- a/drivers/clk/mvebu/orion.c
> +++ b/drivers/clk/mvebu/orion.c
> @@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
>  };
>
>  /*
> + * Orion 5181
> + */
> +
> +#define SAR_MV88F5181_TCLK_FREQ      8
> +#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
> +
> +static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
> +		SAR_MV88F5181_TCLK_FREQ_MASK;
> +	if (opt == 0)
> +		return 133333333;
> +	else if (opt == 1)
> +		return 150000000;
> +	else if (opt == 2)
> +		return 166666667;

    Do you know about the *switch* statement? :-)

> +	else
> +		return 0;
> +}
> +
> +#define SAR_MV88F5181_CPU_FREQ       4
> +#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
> +
> +static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
> +		SAR_MV88F5181_CPU_FREQ_MASK;
> +	if (opt == 0)
> +		return 333333333;
> +	else if (opt == 1 || opt == 2)
> +		return 400000000;
> +	else if (opt == 3)
> +		return 500000000;

    Asks to be a *switch* as well...

> +	else
> +		return 0;
> +}
> +
> +static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
> +					   int *mult, int *div)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
> +		SAR_MV88F5181_CPU_FREQ_MASK;
> +	if (opt == 0 || opt == 1) {
> +		*mult = 1;
> +		*div  = 2;
> +	} else if (opt == 2 || opt == 3) {
> +		*mult = 1;
> +		*div  = 3;
> +	} else {
> +		*mult = 0;
> +		*div  = 1;
> +	}

     This one too...

[...]

MBR, Sergei

[PATCH v0 03/10] arm: orion5x: Add clk support for mv88f5181

[Sergei Shtylyov]

Hello.

On 7/16/2016 5:29 PM, Jamie Lentin wrote:

> Referring to values in the u-boot port, add support for the mv88f5181
>
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>

[...]
> diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
> index fd12956..a6e5bee 100644
> --- a/drivers/clk/mvebu/orion.c
> +++ b/drivers/clk/mvebu/orion.c
> @@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
>  };
>
>  /*
> + * Orion 5181
> + */
> +
> +#define SAR_MV88F5181_TCLK_FREQ      8
> +#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
> +
> +static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
> +		SAR_MV88F5181_TCLK_FREQ_MASK;
> +	if (opt == 0)
> +		return 133333333;
> +	else if (opt == 1)
> +		return 150000000;
> +	else if (opt == 2)
> +		return 166666667;

    Do you know about the *switch* statement? :-)

> +	else
> +		return 0;
> +}
> +
> +#define SAR_MV88F5181_CPU_FREQ       4
> +#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
> +
> +static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
> +		SAR_MV88F5181_CPU_FREQ_MASK;
> +	if (opt == 0)
> +		return 333333333;
> +	else if (opt == 1 || opt == 2)
> +		return 400000000;
> +	else if (opt == 3)
> +		return 500000000;

    Asks to be a *switch* as well...

> +	else
> +		return 0;
> +}
> +
> +static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
> +					   int *mult, int *div)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
> +		SAR_MV88F5181_CPU_FREQ_MASK;
> +	if (opt == 0 || opt == 1) {
> +		*mult = 1;
> +		*div  = 2;
> +	} else if (opt == 2 || opt == 3) {
> +		*mult = 1;
> +		*div  = 3;
> +	} else {
> +		*mult = 0;
> +		*div  = 1;
> +	}

     This one too...

[...]

MBR, Sergei

Re: [PATCH v0 03/10] arm: orion5x: Add clk support for mv88f5181

[Sergei Shtylyov]

Hello.

On 7/16/2016 5:29 PM, Jamie Lentin wrote:

> Referring to values in the u-boot port, add support for the mv88f5181
>
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>

[...]
> diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
> index fd12956..a6e5bee 100644
> --- a/drivers/clk/mvebu/orion.c
> +++ b/drivers/clk/mvebu/orion.c
> @@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
>  };
>
>  /*
> + * Orion 5181
> + */
> +
> +#define SAR_MV88F5181_TCLK_FREQ      8
> +#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
> +
> +static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
> +		SAR_MV88F5181_TCLK_FREQ_MASK;
> +	if (opt == 0)
> +		return 133333333;
> +	else if (opt == 1)
> +		return 150000000;
> +	else if (opt == 2)
> +		return 166666667;

    Do you know about the *switch* statement? :-)

> +	else
> +		return 0;
> +}
> +
> +#define SAR_MV88F5181_CPU_FREQ       4
> +#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
> +
> +static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
> +		SAR_MV88F5181_CPU_FREQ_MASK;
> +	if (opt == 0)
> +		return 333333333;
> +	else if (opt == 1 || opt == 2)
> +		return 400000000;
> +	else if (opt == 3)
> +		return 500000000;

    Asks to be a *switch* as well...

> +	else
> +		return 0;
> +}
> +
> +static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
> +					   int *mult, int *div)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
> +		SAR_MV88F5181_CPU_FREQ_MASK;
> +	if (opt == 0 || opt == 1) {
> +		*mult = 1;
> +		*div  = 2;
> +	} else if (opt == 2 || opt == 3) {
> +		*mult = 1;
> +		*div  = 3;
> +	} else {
> +		*mult = 0;
> +		*div  = 1;
> +	}

     This one too...

[...]

MBR, Sergei

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Re: [PATCH v0 03/10] arm: orion5x: Add clk support for mv88f5181

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:01PM +0100, Jamie Lentin wrote:
> Referring to values in the u-boot port, add support for the mv88f5181
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../devicetree/bindings/clock/mvebu-core-clock.txt |  1 +

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/clk/mvebu/orion.c                          | 70 ++++++++++++++++++++++
>  2 files changed, 71 insertions(+)

[PATCH v0 03/10] arm: orion5x: Add clk support for mv88f5181

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:01PM +0100, Jamie Lentin wrote:
> Referring to values in the u-boot port, add support for the mv88f5181
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../devicetree/bindings/clock/mvebu-core-clock.txt |  1 +

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/clk/mvebu/orion.c                          | 70 ++++++++++++++++++++++
>  2 files changed, 71 insertions(+)

Re: [PATCH v0 03/10] arm: orion5x: Add clk support for mv88f5181

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:01PM +0100, Jamie Lentin wrote:
> Referring to values in the u-boot port, add support for the mv88f5181
> 
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
> ---
>  .../devicetree/bindings/clock/mvebu-core-clock.txt |  1 +

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

>  drivers/clk/mvebu/orion.c                          | 70 ++++++++++++++++++++++
>  2 files changed, 71 insertions(+)
--
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[PATCH v0 04/10] arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181

[Jamie Lentin]

As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
pinctrl level, so re-use the definitions for both.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  4 ++--
 drivers/pinctrl/mvebu/pinctrl-orion.c              | 23 +++++++++++-----------
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
index 27570a3..5a79bad 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
@@ -4,8 +4,8 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
 part and usage.
 
 Required properties:
-- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
-              "marvell,88f5281-pinctrl"
+- compatible: "marvell,88f5181-pinctrl", "marvell,88f5181l-pinctrl",
+              "marvell,88f5182-pinctrl", "marvell,88f5281-pinctrl"
 
 - reg: two register areas, the first one describing the first two
   contiguous MPP registers, and the second one describing the single
diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c
index 3b7122d..6f9c8ee 100644
--- a/drivers/pinctrl/mvebu/pinctrl-orion.c
+++ b/drivers/pinctrl/mvebu/pinctrl-orion.c
@@ -64,11 +64,11 @@ static int orion_mpp_ctrl_set(unsigned pid, unsigned long config)
 	return 0;
 }
 
-#define V(f5181l, f5182, f5281) \
-	((f5181l << 0) | (f5182 << 1) | (f5281 << 2))
+#define V(f5181, f5182, f5281) \
+	((f5181 << 0) | (f5182 << 1) | (f5281 << 2))
 
 enum orion_variant {
-	V_5181L = V(1, 0, 0),
+	V_5181  = V(1, 0, 0),
 	V_5182  = V(0, 1, 0),
 	V_5281  = V(0, 0, 1),
 	V_ALL   = V(1, 1, 1),
@@ -103,13 +103,13 @@ static struct mvebu_mpp_mode orion_mpp_modes[] = {
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
 		 MPP_VAR_FUNCTION(0x2, "pci", "req5",       V_ALL),
 		 MPP_VAR_FUNCTION(0x4, "nand", "re0",       V_5182 | V_5281),
-		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
 		 MPP_VAR_FUNCTION(0x5, "sata0", "act",      V_5182)),
 	MPP_MODE(7,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
 		 MPP_VAR_FUNCTION(0x2, "pci", "gnt5",       V_ALL),
 		 MPP_VAR_FUNCTION(0x4, "nand", "we0",       V_5182 | V_5281),
-		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
 		 MPP_VAR_FUNCTION(0x5, "sata1", "act",      V_5182)),
 	MPP_MODE(8,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
@@ -165,7 +165,7 @@ static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
 	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
 };
 
-static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
+static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
 	MPP_GPIO_RANGE(0, 0, 0, 16),
 };
 
@@ -177,14 +177,14 @@ static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
 	MPP_GPIO_RANGE(0, 0, 0, 16),
 };
 
-static struct mvebu_pinctrl_soc_info mv88f5181l_info = {
-	.variant = V_5181L,
+static struct mvebu_pinctrl_soc_info mv88f5181_info = {
+	.variant = V_5181,
 	.controls = orion_mpp_controls,
 	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
 	.modes = orion_mpp_modes,
 	.nmodes = ARRAY_SIZE(orion_mpp_modes),
-	.gpioranges = mv88f5181l_gpio_ranges,
-	.ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges),
+	.gpioranges = mv88f5181_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
 };
 
 static struct mvebu_pinctrl_soc_info mv88f5182_info = {
@@ -212,7 +212,8 @@ static struct mvebu_pinctrl_soc_info mv88f5281_info = {
  * muxing, they are identical.
  */
 static const struct of_device_id orion_pinctrl_of_match[] = {
-	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info },
+	{ .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
+	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
 	{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
 	{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
 	{ }
-- 
2.8.1

[PATCH v0 04/10] arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181

[Jamie Lentin]

As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
pinctrl level, so re-use the definitions for both.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  4 ++--
 drivers/pinctrl/mvebu/pinctrl-orion.c              | 23 +++++++++++-----------
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
index 27570a3..5a79bad 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
@@ -4,8 +4,8 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
 part and usage.
 
 Required properties:
-- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
-              "marvell,88f5281-pinctrl"
+- compatible: "marvell,88f5181-pinctrl", "marvell,88f5181l-pinctrl",
+              "marvell,88f5182-pinctrl", "marvell,88f5281-pinctrl"
 
 - reg: two register areas, the first one describing the first two
   contiguous MPP registers, and the second one describing the single
diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c
index 3b7122d..6f9c8ee 100644
--- a/drivers/pinctrl/mvebu/pinctrl-orion.c
+++ b/drivers/pinctrl/mvebu/pinctrl-orion.c
@@ -64,11 +64,11 @@ static int orion_mpp_ctrl_set(unsigned pid, unsigned long config)
 	return 0;
 }
 
-#define V(f5181l, f5182, f5281) \
-	((f5181l << 0) | (f5182 << 1) | (f5281 << 2))
+#define V(f5181, f5182, f5281) \
+	((f5181 << 0) | (f5182 << 1) | (f5281 << 2))
 
 enum orion_variant {
-	V_5181L = V(1, 0, 0),
+	V_5181  = V(1, 0, 0),
 	V_5182  = V(0, 1, 0),
 	V_5281  = V(0, 0, 1),
 	V_ALL   = V(1, 1, 1),
@@ -103,13 +103,13 @@ static struct mvebu_mpp_mode orion_mpp_modes[] = {
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
 		 MPP_VAR_FUNCTION(0x2, "pci", "req5",       V_ALL),
 		 MPP_VAR_FUNCTION(0x4, "nand", "re0",       V_5182 | V_5281),
-		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
 		 MPP_VAR_FUNCTION(0x5, "sata0", "act",      V_5182)),
 	MPP_MODE(7,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
 		 MPP_VAR_FUNCTION(0x2, "pci", "gnt5",       V_ALL),
 		 MPP_VAR_FUNCTION(0x4, "nand", "we0",       V_5182 | V_5281),
-		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
 		 MPP_VAR_FUNCTION(0x5, "sata1", "act",      V_5182)),
 	MPP_MODE(8,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
@@ -165,7 +165,7 @@ static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
 	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
 };
 
-static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
+static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
 	MPP_GPIO_RANGE(0, 0, 0, 16),
 };
 
@@ -177,14 +177,14 @@ static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
 	MPP_GPIO_RANGE(0, 0, 0, 16),
 };
 
-static struct mvebu_pinctrl_soc_info mv88f5181l_info = {
-	.variant = V_5181L,
+static struct mvebu_pinctrl_soc_info mv88f5181_info = {
+	.variant = V_5181,
 	.controls = orion_mpp_controls,
 	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
 	.modes = orion_mpp_modes,
 	.nmodes = ARRAY_SIZE(orion_mpp_modes),
-	.gpioranges = mv88f5181l_gpio_ranges,
-	.ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges),
+	.gpioranges = mv88f5181_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
 };
 
 static struct mvebu_pinctrl_soc_info mv88f5182_info = {
@@ -212,7 +212,8 @@ static struct mvebu_pinctrl_soc_info mv88f5281_info = {
  * muxing, they are identical.
  */
 static const struct of_device_id orion_pinctrl_of_match[] = {
-	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info },
+	{ .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
+	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
 	{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
 	{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
 	{ }
-- 
2.8.1

[PATCH v0 04/10] arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181

[Jamie Lentin]

As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
pinctrl level, so re-use the definitions for both.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  4 ++--
 drivers/pinctrl/mvebu/pinctrl-orion.c              | 23 +++++++++++-----------
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
index 27570a3..5a79bad 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
@@ -4,8 +4,8 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
 part and usage.
 
 Required properties:
-- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
-              "marvell,88f5281-pinctrl"
+- compatible: "marvell,88f5181-pinctrl", "marvell,88f5181l-pinctrl",
+              "marvell,88f5182-pinctrl", "marvell,88f5281-pinctrl"
 
 - reg: two register areas, the first one describing the first two
   contiguous MPP registers, and the second one describing the single
diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c
index 3b7122d..6f9c8ee 100644
--- a/drivers/pinctrl/mvebu/pinctrl-orion.c
+++ b/drivers/pinctrl/mvebu/pinctrl-orion.c
@@ -64,11 +64,11 @@ static int orion_mpp_ctrl_set(unsigned pid, unsigned long config)
 	return 0;
 }
 
-#define V(f5181l, f5182, f5281) \
-	((f5181l << 0) | (f5182 << 1) | (f5281 << 2))
+#define V(f5181, f5182, f5281) \
+	((f5181 << 0) | (f5182 << 1) | (f5281 << 2))
 
 enum orion_variant {
-	V_5181L = V(1, 0, 0),
+	V_5181  = V(1, 0, 0),
 	V_5182  = V(0, 1, 0),
 	V_5281  = V(0, 0, 1),
 	V_ALL   = V(1, 1, 1),
@@ -103,13 +103,13 @@ static struct mvebu_mpp_mode orion_mpp_modes[] = {
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
 		 MPP_VAR_FUNCTION(0x2, "pci", "req5",       V_ALL),
 		 MPP_VAR_FUNCTION(0x4, "nand", "re0",       V_5182 | V_5281),
-		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
 		 MPP_VAR_FUNCTION(0x5, "sata0", "act",      V_5182)),
 	MPP_MODE(7,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
 		 MPP_VAR_FUNCTION(0x2, "pci", "gnt5",       V_ALL),
 		 MPP_VAR_FUNCTION(0x4, "nand", "we0",       V_5182 | V_5281),
-		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
 		 MPP_VAR_FUNCTION(0x5, "sata1", "act",      V_5182)),
 	MPP_MODE(8,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
@@ -165,7 +165,7 @@ static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
 	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
 };
 
-static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
+static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
 	MPP_GPIO_RANGE(0, 0, 0, 16),
 };
 
@@ -177,14 +177,14 @@ static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
 	MPP_GPIO_RANGE(0, 0, 0, 16),
 };
 
-static struct mvebu_pinctrl_soc_info mv88f5181l_info = {
-	.variant = V_5181L,
+static struct mvebu_pinctrl_soc_info mv88f5181_info = {
+	.variant = V_5181,
 	.controls = orion_mpp_controls,
 	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
 	.modes = orion_mpp_modes,
 	.nmodes = ARRAY_SIZE(orion_mpp_modes),
-	.gpioranges = mv88f5181l_gpio_ranges,
-	.ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges),
+	.gpioranges = mv88f5181_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
 };
 
 static struct mvebu_pinctrl_soc_info mv88f5182_info = {
@@ -212,7 +212,8 @@ static struct mvebu_pinctrl_soc_info mv88f5281_info = {
  * muxing, they are identical.
  */
 static const struct of_device_id orion_pinctrl_of_match[] = {
-	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info },
+	{ .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
+	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
 	{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
 	{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
 	{ }
-- 
2.8.1

Re: [PATCH v0 04/10] arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:02PM +0100, Jamie Lentin wrote:
> As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
> pinctrl level, so re-use the definitions for both.

Good, you add a new compatibile string. So it if turns out they are
not identical, we can fix it later without causing problems.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

[PATCH v0 04/10] arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:02PM +0100, Jamie Lentin wrote:
> As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
> pinctrl level, so re-use the definitions for both.

Good, you add a new compatibile string. So it if turns out they are
not identical, we can fix it later without causing problems.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH v0 04/10] arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:02PM +0100, Jamie Lentin wrote:
> As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
> pinctrl level, so re-use the definitions for both.
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  4 ++--
>  drivers/pinctrl/mvebu/pinctrl-orion.c              | 23 +++++++++++-----------
>  2 files changed, 14 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
> index 27570a3..5a79bad 100644
> --- a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
> @@ -4,8 +4,8 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
>  part and usage.
>  
>  Required properties:
> -- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
> -              "marvell,88f5281-pinctrl"
> +- compatible: "marvell,88f5181-pinctrl", "marvell,88f5181l-pinctrl",
> +              "marvell,88f5182-pinctrl", "marvell,88f5281-pinctrl"

Please reformat to one per line. Otherwise,

Acked-by: Rob Herring <robh@kernel.org>


>  
>  - reg: two register areas, the first one describing the first two
>    contiguous MPP registers, and the second one describing the single

[PATCH v0 04/10] arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:02PM +0100, Jamie Lentin wrote:
> As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
> pinctrl level, so re-use the definitions for both.
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  4 ++--
>  drivers/pinctrl/mvebu/pinctrl-orion.c              | 23 +++++++++++-----------
>  2 files changed, 14 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
> index 27570a3..5a79bad 100644
> --- a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
> @@ -4,8 +4,8 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
>  part and usage.
>  
>  Required properties:
> -- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
> -              "marvell,88f5281-pinctrl"
> +- compatible: "marvell,88f5181-pinctrl", "marvell,88f5181l-pinctrl",
> +              "marvell,88f5182-pinctrl", "marvell,88f5281-pinctrl"

Please reformat to one per line. Otherwise,

Acked-by: Rob Herring <robh@kernel.org>


>  
>  - reg: two register areas, the first one describing the first two
>    contiguous MPP registers, and the second one describing the single

Re: [PATCH v0 04/10] arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:02PM +0100, Jamie Lentin wrote:
> As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
> pinctrl level, so re-use the definitions for both.
> 
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
> ---
>  .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  4 ++--
>  drivers/pinctrl/mvebu/pinctrl-orion.c              | 23 +++++++++++-----------
>  2 files changed, 14 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
> index 27570a3..5a79bad 100644
> --- a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
> @@ -4,8 +4,8 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
>  part and usage.
>  
>  Required properties:
> -- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
> -              "marvell,88f5281-pinctrl"
> +- compatible: "marvell,88f5181-pinctrl", "marvell,88f5181l-pinctrl",
> +              "marvell,88f5182-pinctrl", "marvell,88f5281-pinctrl"

Please reformat to one per line. Otherwise,

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>


>  
>  - reg: two register areas, the first one describing the first two
>    contiguous MPP registers, and the second one describing the single
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[PATCH v0 05/10] arm: orion5x: Add DT include for mv88f5181

[Jamie Lentin]

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 35 ++++++++++++++++++++++
 2 files changed, 36 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
index a888011..ff3c120 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -9,6 +9,7 @@ compatible: must contain "marvell,orion5x"
 In addition, the above compatible shall be extended with the specific
 SoC. Currently known SoC compatibles are:
 
+"marvell,orion5x-88f5181"
 "marvell,orion5x-88f5182"
 
 And in addition, the compatible shall be extended with the specific
diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
new file mode 100644
index 0000000..b51e7ac
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "orion5x.dtsi"
+
+/ {
+	compatible = "marvell,orion5x-88f5181", "marvell,orion5x";
+
+	soc {
+		compatible = "marvell,orion5x-88f5181-mbus", "simple-bus";
+
+		internal-regs {
+			pinctrl: pinctrl@10000 {
+				compatible = "marvell,88f5181-pinctrl";
+				reg = <0x10000 0x8>, <0x10050 0x4>;
+			};
+
+			core_clk: core-clocks@10030 {
+				compatible = "marvell,mv88f5181-core-clock";
+				reg = <0x10010 0x4>;
+				#clock-cells = <1>;
+			};
+
+			mbusc: mbus-controller@20000 {
+				compatible = "marvell,mbus-controller";
+				reg = <0x20000 0x100>, <0x1500 0x20>;
+			};
+		};
+	};
+};
-- 
2.8.1

[PATCH v0 05/10] arm: orion5x: Add DT include for mv88f5181

[Jamie Lentin]

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 35 ++++++++++++++++++++++
 2 files changed, 36 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
index a888011..ff3c120 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -9,6 +9,7 @@ compatible: must contain "marvell,orion5x"
 In addition, the above compatible shall be extended with the specific
 SoC. Currently known SoC compatibles are:
 
+"marvell,orion5x-88f5181"
 "marvell,orion5x-88f5182"
 
 And in addition, the compatible shall be extended with the specific
diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
new file mode 100644
index 0000000..b51e7ac
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "orion5x.dtsi"
+
+/ {
+	compatible = "marvell,orion5x-88f5181", "marvell,orion5x";
+
+	soc {
+		compatible = "marvell,orion5x-88f5181-mbus", "simple-bus";
+
+		internal-regs {
+			pinctrl: pinctrl at 10000 {
+				compatible = "marvell,88f5181-pinctrl";
+				reg = <0x10000 0x8>, <0x10050 0x4>;
+			};
+
+			core_clk: core-clocks at 10030 {
+				compatible = "marvell,mv88f5181-core-clock";
+				reg = <0x10010 0x4>;
+				#clock-cells = <1>;
+			};
+
+			mbusc: mbus-controller at 20000 {
+				compatible = "marvell,mbus-controller";
+				reg = <0x20000 0x100>, <0x1500 0x20>;
+			};
+		};
+	};
+};
-- 
2.8.1

[PATCH v0 05/10] arm: orion5x: Add DT include for mv88f5181

[Jamie Lentin]

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 35 ++++++++++++++++++++++
 2 files changed, 36 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
index a888011..ff3c120 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -9,6 +9,7 @@ compatible: must contain "marvell,orion5x"
 In addition, the above compatible shall be extended with the specific
 SoC. Currently known SoC compatibles are:
 
+"marvell,orion5x-88f5181"
 "marvell,orion5x-88f5182"
 
 And in addition, the compatible shall be extended with the specific
diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
new file mode 100644
index 0000000..b51e7ac
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "orion5x.dtsi"
+
+/ {
+	compatible = "marvell,orion5x-88f5181", "marvell,orion5x";
+
+	soc {
+		compatible = "marvell,orion5x-88f5181-mbus", "simple-bus";
+
+		internal-regs {
+			pinctrl: pinctrl@10000 {
+				compatible = "marvell,88f5181-pinctrl";
+				reg = <0x10000 0x8>, <0x10050 0x4>;
+			};
+
+			core_clk: core-clocks@10030 {
+				compatible = "marvell,mv88f5181-core-clock";
+				reg = <0x10010 0x4>;
+				#clock-cells = <1>;
+			};
+
+			mbusc: mbus-controller@20000 {
+				compatible = "marvell,mbus-controller";
+				reg = <0x20000 0x100>, <0x1500 0x20>;
+			};
+		};
+	};
+};
-- 
2.8.1

Re: [PATCH v0 05/10] arm: orion5x: Add DT include for mv88f5181

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:03PM +0100, Jamie Lentin wrote:

You need to put somewhere here for the commit log.

Otherwise this looks O.K.

	  Andrew

> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
>  arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 35 ++++++++++++++++++++++
>  2 files changed, 36 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi
> 
> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> index a888011..ff3c120 100644
> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> @@ -9,6 +9,7 @@ compatible: must contain "marvell,orion5x"
>  In addition, the above compatible shall be extended with the specific
>  SoC. Currently known SoC compatibles are:
>  
> +"marvell,orion5x-88f5181"
>  "marvell,orion5x-88f5182"
>  
>  And in addition, the compatible shall be extended with the specific
> diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
> new file mode 100644
> index 0000000..b51e7ac
> --- /dev/null
> +++ b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include "orion5x.dtsi"
> +
> +/ {
> +	compatible = "marvell,orion5x-88f5181", "marvell,orion5x";
> +
> +	soc {
> +		compatible = "marvell,orion5x-88f5181-mbus", "simple-bus";
> +
> +		internal-regs {
> +			pinctrl: pinctrl@10000 {
> +				compatible = "marvell,88f5181-pinctrl";
> +				reg = <0x10000 0x8>, <0x10050 0x4>;
> +			};
> +
> +			core_clk: core-clocks@10030 {
> +				compatible = "marvell,mv88f5181-core-clock";
> +				reg = <0x10010 0x4>;
> +				#clock-cells = <1>;
> +			};
> +
> +			mbusc: mbus-controller@20000 {
> +				compatible = "marvell,mbus-controller";
> +				reg = <0x20000 0x100>, <0x1500 0x20>;
> +			};
> +		};
> +	};
> +};
> -- 
> 2.8.1
> 

[PATCH v0 05/10] arm: orion5x: Add DT include for mv88f5181

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:03PM +0100, Jamie Lentin wrote:

You need to put somewhere here for the commit log.

Otherwise this looks O.K.

	  Andrew

> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
>  arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 35 ++++++++++++++++++++++
>  2 files changed, 36 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi
> 
> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> index a888011..ff3c120 100644
> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> @@ -9,6 +9,7 @@ compatible: must contain "marvell,orion5x"
>  In addition, the above compatible shall be extended with the specific
>  SoC. Currently known SoC compatibles are:
>  
> +"marvell,orion5x-88f5181"
>  "marvell,orion5x-88f5182"
>  
>  And in addition, the compatible shall be extended with the specific
> diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
> new file mode 100644
> index 0000000..b51e7ac
> --- /dev/null
> +++ b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include "orion5x.dtsi"
> +
> +/ {
> +	compatible = "marvell,orion5x-88f5181", "marvell,orion5x";
> +
> +	soc {
> +		compatible = "marvell,orion5x-88f5181-mbus", "simple-bus";
> +
> +		internal-regs {
> +			pinctrl: pinctrl at 10000 {
> +				compatible = "marvell,88f5181-pinctrl";
> +				reg = <0x10000 0x8>, <0x10050 0x4>;
> +			};
> +
> +			core_clk: core-clocks at 10030 {
> +				compatible = "marvell,mv88f5181-core-clock";
> +				reg = <0x10010 0x4>;
> +				#clock-cells = <1>;
> +			};
> +
> +			mbusc: mbus-controller at 20000 {
> +				compatible = "marvell,mbus-controller";
> +				reg = <0x20000 0x100>, <0x1500 0x20>;
> +			};
> +		};
> +	};
> +};
> -- 
> 2.8.1
> 

Re: [PATCH v0 05/10] arm: orion5x: Add DT include for mv88f5181

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:03PM +0100, Jamie Lentin wrote:

You need to put somewhere here for the commit log.

Otherwise this looks O.K.

	  Andrew

> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
>  arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 35 ++++++++++++++++++++++
>  2 files changed, 36 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi
> 
> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> index a888011..ff3c120 100644
> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> @@ -9,6 +9,7 @@ compatible: must contain "marvell,orion5x"
>  In addition, the above compatible shall be extended with the specific
>  SoC. Currently known SoC compatibles are:
>  
> +"marvell,orion5x-88f5181"
>  "marvell,orion5x-88f5182"
>  
>  And in addition, the compatible shall be extended with the specific
> diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
> new file mode 100644
> index 0000000..b51e7ac
> --- /dev/null
> +++ b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright (C) 2016 Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include "orion5x.dtsi"
> +
> +/ {
> +	compatible = "marvell,orion5x-88f5181", "marvell,orion5x";
> +
> +	soc {
> +		compatible = "marvell,orion5x-88f5181-mbus", "simple-bus";
> +
> +		internal-regs {
> +			pinctrl: pinctrl@10000 {
> +				compatible = "marvell,88f5181-pinctrl";
> +				reg = <0x10000 0x8>, <0x10050 0x4>;
> +			};
> +
> +			core_clk: core-clocks@10030 {
> +				compatible = "marvell,mv88f5181-core-clock";
> +				reg = <0x10010 0x4>;
> +				#clock-cells = <1>;
> +			};
> +
> +			mbusc: mbus-controller@20000 {
> +				compatible = "marvell,mbus-controller";
> +				reg = <0x20000 0x100>, <0x1500 0x20>;
> +			};
> +		};
> +	};
> +};
> -- 
> 2.8.1
> 
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Re: [PATCH v0 05/10] arm: orion5x: Add DT include for mv88f5181

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:03PM +0100, Jamie Lentin wrote:
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
>  arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 35 ++++++++++++++++++++++
>  2 files changed, 36 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v0 05/10] arm: orion5x: Add DT include for mv88f5181

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:03PM +0100, Jamie Lentin wrote:
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
>  arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 35 ++++++++++++++++++++++
>  2 files changed, 36 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 200 +++++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
 6 files changed, 287 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
index ff3c120..748a8f2 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -22,3 +22,4 @@ board. Currently known boards are:
 "lacie,d2-network"
 "marvell,rd-88f5182-nas"
 "maxtor,shared-storage-2"
+"netgear,wnr854t"
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 95c1923..63b9202 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -535,6 +535,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-linkstation-lswtgl.dtb \
 	orion5x-lswsgl.dtb \
 	orion5x-maxtor-shared-storage-2.dtb \
+	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb
diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
new file mode 100644
index 0000000..a8e89d8
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2014 Jamie Lentin <jm@lentin.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+	model = "Netgear WNR854-t";
+	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
+			"marvell,orion5x";
+
+	memory {
+		reg = <0x00000000 0x2000000>; /* 32 MB */
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		linux,stdout-path = &uart0;
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			<MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			<MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_reset_switch>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
+		pinctrl-names = "default";
+
+		led@0 {
+			label = "power:green";
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led@1 {
+			label = "power:blink";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led@2 {
+			label = "wan:green";
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	dsa@0 {
+		compatible = "marvell,dsa";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dsa,ethernet = <&ethport>;
+		dsa,mii-bus = <&mdio>;
+
+		switch@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
+
+			port@0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "wan";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "cpu";
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "lan1";
+			};
+
+			port@7 {
+				reg = <7>;
+				label = "lan2";
+			};
+		};
+	};
+};
+
+&devbus_bootcs {
+	status = "okay";
+
+	devbus,keep-config;
+
+	flash@0 {
+		compatible = "cfi-flash";
+		reg = <0 0x800000>;
+		bank-width = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "kernel";
+			reg = <0x0 0x100000>;
+		};
+
+		partition@100000 {
+			label = "rootfs";
+			reg = <0x100000 0x660000>;
+		};
+
+		partition@760000 {
+			label = "uboot_env";
+			reg = <0x760000 0x20000>;
+		};
+
+		partition@780000 {
+			label = "uboot";
+			reg = <0x780000 0x80000>;
+			read-only;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+	ethernet-port@0 {
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
+	pinctrl-names = "default";
+
+	pmx_power_led: pmx-power-led {
+		marvell,pins = "mpp0";
+		marvell,function = "gpio";
+	};
+
+	pmx_reset_switch: pmx-reset-switch {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_led_blink: pmx-power-led-blink {
+		marvell,pins = "mpp2";
+		marvell,function = "gpio";
+	};
+
+	pmx_wan_led: pmx-wan-led {
+		marvell,pins = "mpp3";
+		marvell,function = "gpio";
+	};
+
+	pmx_pci_gpios: pmx-pci-gpios {
+		marvell,pins = "mpp4";
+		marvell,function = "gpio";
+	};
+
+	pmx_ge: pmx-ge {
+		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
+				"mpp16", "mpp17", "mpp18", "mpp19";
+		marvell,function = "ge";
+	};
+};
+
+&uart0 {
+	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
+	status = "okay";
+};
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index a2af158..1fdb95d 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -151,6 +151,12 @@ config MACH_MSS2_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Maxtor Shared Storage II platform.
 
+config MACH_WNR854T_DT
+	bool "Netgear WNR854T (Flattened Device Tree)"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Netgear WNR854T platform.
+
 config MACH_WNR854T
 	bool "Netgear WNR854T"
 	help
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 4b2502b..9dff2d3 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
 obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
 obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
 obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
+obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o
diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c
new file mode 100644
index 0000000..c506e33
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-wnr854t.c
@@ -0,0 +1,78 @@
+/*
+ * Netgear WNR854T PCI setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <asm/mach/pci.h>
+#include "common.h"
+#include "orion5x.h"
+
+#define WNR854T_PCI_SLOT0_OFFS	7
+#define WNR854T_PCI_SLOT0_IRQ_PIN	4
+
+static void __init wnr854t_pci_preinit(void)
+{
+	int pin;
+
+	/*
+	 * Configure PCI GPIO IRQ pins
+	 */
+	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
+	if (gpio_request(pin, "PCI Int") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
+				pin);
+			gpio_free(pin);
+		}
+	} else {
+		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
+	}
+}
+
+static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
+	u8 pin)
+{
+	int irq;
+
+	/*
+	 * Check for devices with hard-wired IRQs.
+	 */
+	irq = orion5x_pci_map_irq(dev, slot, pin);
+	if (irq != -1)
+		return irq;
+
+	/*
+	 * PCI IRQs are connected via GPIOs
+	 */
+	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
+	case 0:
+		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
+	default:
+		return -1;
+	}
+}
+
+static struct hw_pci wnr854t_pci __initdata = {
+	.nr_controllers	= 2,
+	.preinit	= wnr854t_pci_preinit,
+	.setup		= orion5x_pci_sys_setup,
+	.scan		= orion5x_pci_sys_scan_bus,
+	.map_irq	= wnr854t_pci_map_irq,
+};
+
+static int __init wnr854t_pci_init(void)
+{
+	if (of_machine_is_compatible("netgear,wnr854t"))
+		pci_common_init(&wnr854t_pci);
+
+	return 0;
+}
+/* NB: Use late_initcall so we can gpio_request() without being deferred */
+late_initcall(wnr854t_pci_init);
-- 
2.8.1

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 200 +++++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
 6 files changed, 287 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
index ff3c120..748a8f2 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -22,3 +22,4 @@ board. Currently known boards are:
 "lacie,d2-network"
 "marvell,rd-88f5182-nas"
 "maxtor,shared-storage-2"
+"netgear,wnr854t"
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 95c1923..63b9202 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -535,6 +535,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-linkstation-lswtgl.dtb \
 	orion5x-lswsgl.dtb \
 	orion5x-maxtor-shared-storage-2.dtb \
+	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb
diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
new file mode 100644
index 0000000..a8e89d8
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2014 Jamie Lentin <jm@lentin.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+	model = "Netgear WNR854-t";
+	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
+			"marvell,orion5x";
+
+	memory {
+		reg = <0x00000000 0x2000000>; /* 32 MB */
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		linux,stdout-path = &uart0;
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			<MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			<MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_reset_switch>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
+		pinctrl-names = "default";
+
+		led at 0 {
+			label = "power:green";
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 1 {
+			label = "power:blink";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 2 {
+			label = "wan:green";
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	dsa at 0 {
+		compatible = "marvell,dsa";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dsa,ethernet = <&ethport>;
+		dsa,mii-bus = <&mdio>;
+
+		switch at 0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
+
+			port at 0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "wan";
+			};
+
+			port at 3 {
+				reg = <3>;
+				label = "cpu";
+			};
+
+			port at 5 {
+				reg = <5>;
+				label = "lan1";
+			};
+
+			port at 7 {
+				reg = <7>;
+				label = "lan2";
+			};
+		};
+	};
+};
+
+&devbus_bootcs {
+	status = "okay";
+
+	devbus,keep-config;
+
+	flash at 0 {
+		compatible = "cfi-flash";
+		reg = <0 0x800000>;
+		bank-width = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition at 0 {
+			label = "kernel";
+			reg = <0x0 0x100000>;
+		};
+
+		partition at 100000 {
+			label = "rootfs";
+			reg = <0x100000 0x660000>;
+		};
+
+		partition at 760000 {
+			label = "uboot_env";
+			reg = <0x760000 0x20000>;
+		};
+
+		partition at 780000 {
+			label = "uboot";
+			reg = <0x780000 0x80000>;
+			read-only;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+	ethernet-port at 0 {
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
+	pinctrl-names = "default";
+
+	pmx_power_led: pmx-power-led {
+		marvell,pins = "mpp0";
+		marvell,function = "gpio";
+	};
+
+	pmx_reset_switch: pmx-reset-switch {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_led_blink: pmx-power-led-blink {
+		marvell,pins = "mpp2";
+		marvell,function = "gpio";
+	};
+
+	pmx_wan_led: pmx-wan-led {
+		marvell,pins = "mpp3";
+		marvell,function = "gpio";
+	};
+
+	pmx_pci_gpios: pmx-pci-gpios {
+		marvell,pins = "mpp4";
+		marvell,function = "gpio";
+	};
+
+	pmx_ge: pmx-ge {
+		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
+				"mpp16", "mpp17", "mpp18", "mpp19";
+		marvell,function = "ge";
+	};
+};
+
+&uart0 {
+	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
+	status = "okay";
+};
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index a2af158..1fdb95d 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -151,6 +151,12 @@ config MACH_MSS2_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Maxtor Shared Storage II platform.
 
+config MACH_WNR854T_DT
+	bool "Netgear WNR854T (Flattened Device Tree)"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Netgear WNR854T platform.
+
 config MACH_WNR854T
 	bool "Netgear WNR854T"
 	help
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 4b2502b..9dff2d3 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
 obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
 obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
 obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
+obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o
diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c
new file mode 100644
index 0000000..c506e33
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-wnr854t.c
@@ -0,0 +1,78 @@
+/*
+ * Netgear WNR854T PCI setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <asm/mach/pci.h>
+#include "common.h"
+#include "orion5x.h"
+
+#define WNR854T_PCI_SLOT0_OFFS	7
+#define WNR854T_PCI_SLOT0_IRQ_PIN	4
+
+static void __init wnr854t_pci_preinit(void)
+{
+	int pin;
+
+	/*
+	 * Configure PCI GPIO IRQ pins
+	 */
+	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
+	if (gpio_request(pin, "PCI Int") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
+				pin);
+			gpio_free(pin);
+		}
+	} else {
+		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
+	}
+}
+
+static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
+	u8 pin)
+{
+	int irq;
+
+	/*
+	 * Check for devices with hard-wired IRQs.
+	 */
+	irq = orion5x_pci_map_irq(dev, slot, pin);
+	if (irq != -1)
+		return irq;
+
+	/*
+	 * PCI IRQs are connected via GPIOs
+	 */
+	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
+	case 0:
+		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
+	default:
+		return -1;
+	}
+}
+
+static struct hw_pci wnr854t_pci __initdata = {
+	.nr_controllers	= 2,
+	.preinit	= wnr854t_pci_preinit,
+	.setup		= orion5x_pci_sys_setup,
+	.scan		= orion5x_pci_sys_scan_bus,
+	.map_irq	= wnr854t_pci_map_irq,
+};
+
+static int __init wnr854t_pci_init(void)
+{
+	if (of_machine_is_compatible("netgear,wnr854t"))
+		pci_common_init(&wnr854t_pci);
+
+	return 0;
+}
+/* NB: Use late_initcall so we can gpio_request() without being deferred */
+late_initcall(wnr854t_pci_init);
-- 
2.8.1

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 200 +++++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
 6 files changed, 287 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
index ff3c120..748a8f2 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -22,3 +22,4 @@ board. Currently known boards are:
 "lacie,d2-network"
 "marvell,rd-88f5182-nas"
 "maxtor,shared-storage-2"
+"netgear,wnr854t"
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 95c1923..63b9202 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -535,6 +535,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-linkstation-lswtgl.dtb \
 	orion5x-lswsgl.dtb \
 	orion5x-maxtor-shared-storage-2.dtb \
+	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb
diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
new file mode 100644
index 0000000..a8e89d8
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2014 Jamie Lentin <jm@lentin.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+	model = "Netgear WNR854-t";
+	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
+			"marvell,orion5x";
+
+	memory {
+		reg = <0x00000000 0x2000000>; /* 32 MB */
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		linux,stdout-path = &uart0;
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			<MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			<MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_reset_switch>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
+		pinctrl-names = "default";
+
+		led@0 {
+			label = "power:green";
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led@1 {
+			label = "power:blink";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led@2 {
+			label = "wan:green";
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	dsa@0 {
+		compatible = "marvell,dsa";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dsa,ethernet = <&ethport>;
+		dsa,mii-bus = <&mdio>;
+
+		switch@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
+
+			port@0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "wan";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "cpu";
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "lan1";
+			};
+
+			port@7 {
+				reg = <7>;
+				label = "lan2";
+			};
+		};
+	};
+};
+
+&devbus_bootcs {
+	status = "okay";
+
+	devbus,keep-config;
+
+	flash@0 {
+		compatible = "cfi-flash";
+		reg = <0 0x800000>;
+		bank-width = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "kernel";
+			reg = <0x0 0x100000>;
+		};
+
+		partition@100000 {
+			label = "rootfs";
+			reg = <0x100000 0x660000>;
+		};
+
+		partition@760000 {
+			label = "uboot_env";
+			reg = <0x760000 0x20000>;
+		};
+
+		partition@780000 {
+			label = "uboot";
+			reg = <0x780000 0x80000>;
+			read-only;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+	ethernet-port@0 {
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
+	pinctrl-names = "default";
+
+	pmx_power_led: pmx-power-led {
+		marvell,pins = "mpp0";
+		marvell,function = "gpio";
+	};
+
+	pmx_reset_switch: pmx-reset-switch {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_led_blink: pmx-power-led-blink {
+		marvell,pins = "mpp2";
+		marvell,function = "gpio";
+	};
+
+	pmx_wan_led: pmx-wan-led {
+		marvell,pins = "mpp3";
+		marvell,function = "gpio";
+	};
+
+	pmx_pci_gpios: pmx-pci-gpios {
+		marvell,pins = "mpp4";
+		marvell,function = "gpio";
+	};
+
+	pmx_ge: pmx-ge {
+		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
+				"mpp16", "mpp17", "mpp18", "mpp19";
+		marvell,function = "ge";
+	};
+};
+
+&uart0 {
+	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
+	status = "okay";
+};
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index a2af158..1fdb95d 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -151,6 +151,12 @@ config MACH_MSS2_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Maxtor Shared Storage II platform.
 
+config MACH_WNR854T_DT
+	bool "Netgear WNR854T (Flattened Device Tree)"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Netgear WNR854T platform.
+
 config MACH_WNR854T
 	bool "Netgear WNR854T"
 	help
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 4b2502b..9dff2d3 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
 obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
 obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
 obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
+obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o
diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c
new file mode 100644
index 0000000..c506e33
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-wnr854t.c
@@ -0,0 +1,78 @@
+/*
+ * Netgear WNR854T PCI setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <asm/mach/pci.h>
+#include "common.h"
+#include "orion5x.h"
+
+#define WNR854T_PCI_SLOT0_OFFS	7
+#define WNR854T_PCI_SLOT0_IRQ_PIN	4
+
+static void __init wnr854t_pci_preinit(void)
+{
+	int pin;
+
+	/*
+	 * Configure PCI GPIO IRQ pins
+	 */
+	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
+	if (gpio_request(pin, "PCI Int") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
+				pin);
+			gpio_free(pin);
+		}
+	} else {
+		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
+	}
+}
+
+static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
+	u8 pin)
+{
+	int irq;
+
+	/*
+	 * Check for devices with hard-wired IRQs.
+	 */
+	irq = orion5x_pci_map_irq(dev, slot, pin);
+	if (irq != -1)
+		return irq;
+
+	/*
+	 * PCI IRQs are connected via GPIOs
+	 */
+	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
+	case 0:
+		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
+	default:
+		return -1;
+	}
+}
+
+static struct hw_pci wnr854t_pci __initdata = {
+	.nr_controllers	= 2,
+	.preinit	= wnr854t_pci_preinit,
+	.setup		= orion5x_pci_sys_setup,
+	.scan		= orion5x_pci_sys_scan_bus,
+	.map_irq	= wnr854t_pci_map_irq,
+};
+
+static int __init wnr854t_pci_init(void)
+{
+	if (of_machine_is_compatible("netgear,wnr854t"))
+		pci_common_init(&wnr854t_pci);
+
+	return 0;
+}
+/* NB: Use late_initcall so we can gpio_request() without being deferred */
+late_initcall(wnr854t_pci_init);
-- 
2.8.1

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Andrew Lunn]

> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +		linux,stdout-path = &uart0;
> +	};

You can put the board rate etc in the stdout-patch. Something like:

                stdout-path = "serial0:115200n8";

> +	gpio-leds {
> +		compatible = "gpio-leds";
> +		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
> +		pinctrl-names = "default";
> +
> +		led@0 {
> +			label = "power:green";

Documentation/leds/leds-class.txt says:

LED Device Naming
=================

Is currently of the form:

"devicename:colour:function"

> +	dsa@0 {
> +		compatible = "marvell,dsa";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		dsa,ethernet = <&ethport>;
> +		dsa,mii-bus = <&mdio>;
> +
> +		switch@0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
> +
> +			port@0 {
> +				reg = <0>;
> +				label = "lan3";
> +			};
> +
> +			port@1 {
> +				reg = <1>;
> +				label = "lan4";
> +			};
> +
> +			port@2 {
> +				reg = <2>;
> +				label = "wan";
> +			};
> +
> +			port@3 {
> +				reg = <3>;
> +				label = "cpu";
> +			};
> +
> +			port@5 {
> +				reg = <5>;
> +				label = "lan1";
> +			};
> +
> +			port@7 {
> +				reg = <7>;
> +				label = "lan2";
> +			};
> +		};
> +	};
> +};

This all looks sensible, if a bit mixed up. Lets discuss the switch
issue in a different thread.

> +&devbus_bootcs {
> +	status = "okay";
> +
> +	devbus,keep-config;
> +
> +	flash@0 {
> +		compatible = "cfi-flash";
> +		reg = <0 0x800000>;
> +		bank-width = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;

Documentation/devicetree/bindings/mtd/partition.txt says the
partitions should be placed under a partitions node. There are some
conditions when that does not work. So please try it, and if it does
not, ignore my comment...

> +
> +		partition@0 {
> +			label = "kernel";
> +			reg = <0x0 0x100000>;
> +		};
> +
> +		partition@100000 {
> +			label = "rootfs";
> +			reg = <0x100000 0x660000>;
> +		};
> +
> +		partition@760000 {
> +			label = "uboot_env";
> +			reg = <0x760000 0x20000>;
> +		};
> +
> +		partition@780000 {
> +			label = "uboot";
> +			reg = <0x780000 0x80000>;
> +			read-only;
> +		};
> +	};
> +};

> +&pinctrl {
> +	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
> +	pinctrl-names = "default";
> +
> +	pmx_power_led: pmx-power-led {
> +		marvell,pins = "mpp0";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_reset_switch: pmx-reset-switch {
> +		marvell,pins = "mpp1";
> +		marvell,function = "gpio";
> +	};

Ah, this is missing from your DSA node. You can then add:

reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;

inside the switch@0 node.

> +	pmx_ge: pmx-ge {
> +		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
> +				"mpp16", "mpp17", "mpp18", "mpp19";
> +		marvell,function = "ge";
> +	};
> +};

This can go into the .dtsi file your previous patch added. 

> +
> +&uart0 {
> +	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
> +	status = "okay";

Nice to see the comment.

     Andrew

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Andrew Lunn]

> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +		linux,stdout-path = &uart0;
> +	};

You can put the board rate etc in the stdout-patch. Something like:

                stdout-path = "serial0:115200n8";

> +	gpio-leds {
> +		compatible = "gpio-leds";
> +		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
> +		pinctrl-names = "default";
> +
> +		led at 0 {
> +			label = "power:green";

Documentation/leds/leds-class.txt says:

LED Device Naming
=================

Is currently of the form:

"devicename:colour:function"

> +	dsa at 0 {
> +		compatible = "marvell,dsa";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		dsa,ethernet = <&ethport>;
> +		dsa,mii-bus = <&mdio>;
> +
> +		switch at 0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
> +
> +			port at 0 {
> +				reg = <0>;
> +				label = "lan3";
> +			};
> +
> +			port at 1 {
> +				reg = <1>;
> +				label = "lan4";
> +			};
> +
> +			port at 2 {
> +				reg = <2>;
> +				label = "wan";
> +			};
> +
> +			port at 3 {
> +				reg = <3>;
> +				label = "cpu";
> +			};
> +
> +			port at 5 {
> +				reg = <5>;
> +				label = "lan1";
> +			};
> +
> +			port at 7 {
> +				reg = <7>;
> +				label = "lan2";
> +			};
> +		};
> +	};
> +};

This all looks sensible, if a bit mixed up. Lets discuss the switch
issue in a different thread.

> +&devbus_bootcs {
> +	status = "okay";
> +
> +	devbus,keep-config;
> +
> +	flash at 0 {
> +		compatible = "cfi-flash";
> +		reg = <0 0x800000>;
> +		bank-width = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;

Documentation/devicetree/bindings/mtd/partition.txt says the
partitions should be placed under a partitions node. There are some
conditions when that does not work. So please try it, and if it does
not, ignore my comment...

> +
> +		partition at 0 {
> +			label = "kernel";
> +			reg = <0x0 0x100000>;
> +		};
> +
> +		partition at 100000 {
> +			label = "rootfs";
> +			reg = <0x100000 0x660000>;
> +		};
> +
> +		partition at 760000 {
> +			label = "uboot_env";
> +			reg = <0x760000 0x20000>;
> +		};
> +
> +		partition at 780000 {
> +			label = "uboot";
> +			reg = <0x780000 0x80000>;
> +			read-only;
> +		};
> +	};
> +};

> +&pinctrl {
> +	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
> +	pinctrl-names = "default";
> +
> +	pmx_power_led: pmx-power-led {
> +		marvell,pins = "mpp0";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_reset_switch: pmx-reset-switch {
> +		marvell,pins = "mpp1";
> +		marvell,function = "gpio";
> +	};

Ah, this is missing from your DSA node. You can then add:

reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;

inside the switch at 0 node.

> +	pmx_ge: pmx-ge {
> +		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
> +				"mpp16", "mpp17", "mpp18", "mpp19";
> +		marvell,function = "ge";
> +	};
> +};

This can go into the .dtsi file your previous patch added. 

> +
> +&uart0 {
> +	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
> +	status = "okay";

Nice to see the comment.

     Andrew

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Andrew Lunn]

> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +		linux,stdout-path = &uart0;
> +	};

You can put the board rate etc in the stdout-patch. Something like:

                stdout-path = "serial0:115200n8";

> +	gpio-leds {
> +		compatible = "gpio-leds";
> +		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
> +		pinctrl-names = "default";
> +
> +		led@0 {
> +			label = "power:green";

Documentation/leds/leds-class.txt says:

LED Device Naming
=================

Is currently of the form:

"devicename:colour:function"

> +	dsa@0 {
> +		compatible = "marvell,dsa";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		dsa,ethernet = <&ethport>;
> +		dsa,mii-bus = <&mdio>;
> +
> +		switch@0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
> +
> +			port@0 {
> +				reg = <0>;
> +				label = "lan3";
> +			};
> +
> +			port@1 {
> +				reg = <1>;
> +				label = "lan4";
> +			};
> +
> +			port@2 {
> +				reg = <2>;
> +				label = "wan";
> +			};
> +
> +			port@3 {
> +				reg = <3>;
> +				label = "cpu";
> +			};
> +
> +			port@5 {
> +				reg = <5>;
> +				label = "lan1";
> +			};
> +
> +			port@7 {
> +				reg = <7>;
> +				label = "lan2";
> +			};
> +		};
> +	};
> +};

This all looks sensible, if a bit mixed up. Lets discuss the switch
issue in a different thread.

> +&devbus_bootcs {
> +	status = "okay";
> +
> +	devbus,keep-config;
> +
> +	flash@0 {
> +		compatible = "cfi-flash";
> +		reg = <0 0x800000>;
> +		bank-width = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;

Documentation/devicetree/bindings/mtd/partition.txt says the
partitions should be placed under a partitions node. There are some
conditions when that does not work. So please try it, and if it does
not, ignore my comment...

> +
> +		partition@0 {
> +			label = "kernel";
> +			reg = <0x0 0x100000>;
> +		};
> +
> +		partition@100000 {
> +			label = "rootfs";
> +			reg = <0x100000 0x660000>;
> +		};
> +
> +		partition@760000 {
> +			label = "uboot_env";
> +			reg = <0x760000 0x20000>;
> +		};
> +
> +		partition@780000 {
> +			label = "uboot";
> +			reg = <0x780000 0x80000>;
> +			read-only;
> +		};
> +	};
> +};

> +&pinctrl {
> +	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
> +	pinctrl-names = "default";
> +
> +	pmx_power_led: pmx-power-led {
> +		marvell,pins = "mpp0";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_reset_switch: pmx-reset-switch {
> +		marvell,pins = "mpp1";
> +		marvell,function = "gpio";
> +	};

Ah, this is missing from your DSA node. You can then add:

reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;

inside the switch@0 node.

> +	pmx_ge: pmx-ge {
> +		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
> +				"mpp16", "mpp17", "mpp18", "mpp19";
> +		marvell,function = "ge";
> +	};
> +};

This can go into the .dtsi file your previous patch added. 

> +
> +&uart0 {
> +	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
> +	status = "okay";

Nice to see the comment.

     Andrew
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Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Andrew Lunn]

> +	pmx_reset_switch: pmx-reset-switch {
> +		marvell,pins = "mpp1";
> +		marvell,function = "gpio";
> +	};

Ah! I think i interpreted that wrong. This does not reset the Ethernet
switch. It is actually a switch on the front to reset the whole box?

How about calling it button, not switch?

    Andrew

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Andrew Lunn]

> +	pmx_reset_switch: pmx-reset-switch {
> +		marvell,pins = "mpp1";
> +		marvell,function = "gpio";
> +	};

Ah! I think i interpreted that wrong. This does not reset the Ethernet
switch. It is actually a switch on the front to reset the whole box?

How about calling it button, not switch?

    Andrew

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Saturday, July 16, 2016 3:29:04 PM CEST Jamie Lentin wrote:
> +
> +#define WNR854T_PCI_SLOT0_OFFS	7
> +#define WNR854T_PCI_SLOT0_IRQ_PIN	4
> +
> +static void __init wnr854t_pci_preinit(void)
> +{
> +	int pin;
> +
> +	/*
> +	 * Configure PCI GPIO IRQ pins
> +	 */
> +	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
> +	if (gpio_request(pin, "PCI Int") == 0) {
> +		if (gpio_direction_input(pin) == 0) {
> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
> +		} else {
> +			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
> +				pin);
> +			gpio_free(pin);
> +		}
> +	} else {
> +		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
> +	}
> +}
> +
> +static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
> +	u8 pin)
> +{
> +	int irq;
> +
> +	/*
> +	 * Check for devices with hard-wired IRQs.
> +	 */
> +	irq = orion5x_pci_map_irq(dev, slot, pin);
> +	if (irq != -1)
> +		return irq;
> +
> +	/*
> +	 * PCI IRQs are connected via GPIOs
> +	 */
> +	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
> +	case 0:
> +		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
> +	default:
> +		return -1;
> +	}
> +}

The other patches all appear good to me, but I find this one suspicious.

Why are you not using the device tree for probing PCI? Is there anything
missing in drivers/pci/host/pci-mvebu.c, or do you just need help
describing it in DT?

	Arnd

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Saturday, July 16, 2016 3:29:04 PM CEST Jamie Lentin wrote:
> +
> +#define WNR854T_PCI_SLOT0_OFFS	7
> +#define WNR854T_PCI_SLOT0_IRQ_PIN	4
> +
> +static void __init wnr854t_pci_preinit(void)
> +{
> +	int pin;
> +
> +	/*
> +	 * Configure PCI GPIO IRQ pins
> +	 */
> +	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
> +	if (gpio_request(pin, "PCI Int") == 0) {
> +		if (gpio_direction_input(pin) == 0) {
> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
> +		} else {
> +			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
> +				pin);
> +			gpio_free(pin);
> +		}
> +	} else {
> +		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
> +	}
> +}
> +
> +static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
> +	u8 pin)
> +{
> +	int irq;
> +
> +	/*
> +	 * Check for devices with hard-wired IRQs.
> +	 */
> +	irq = orion5x_pci_map_irq(dev, slot, pin);
> +	if (irq != -1)
> +		return irq;
> +
> +	/*
> +	 * PCI IRQs are connected via GPIOs
> +	 */
> +	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
> +	case 0:
> +		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
> +	default:
> +		return -1;
> +	}
> +}

The other patches all appear good to me, but I find this one suspicious.

Why are you not using the device tree for probing PCI? Is there anything
missing in drivers/pci/host/pci-mvebu.c, or do you just need help
describing it in DT?

	Arnd

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On Sat, 16 Jul 2016, Arnd Bergmann wrote:

> On Saturday, July 16, 2016 3:29:04 PM CEST Jamie Lentin wrote:
>> +
>> +#define WNR854T_PCI_SLOT0_OFFS	7
>> +#define WNR854T_PCI_SLOT0_IRQ_PIN	4
>> +
>> +static void __init wnr854t_pci_preinit(void)
>> +{
>> +	int pin;
>> +
>> +	/*
>> +	 * Configure PCI GPIO IRQ pins
>> +	 */
>> +	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
>> +	if (gpio_request(pin, "PCI Int") == 0) {
>> +		if (gpio_direction_input(pin) == 0) {
>> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
>> +		} else {
>> +			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
>> +				pin);
>> +			gpio_free(pin);
>> +		}
>> +	} else {
>> +		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
>> +	}
>> +}
>> +
>> +static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
>> +	u8 pin)
>> +{
>> +	int irq;
>> +
>> +	/*
>> +	 * Check for devices with hard-wired IRQs.
>> +	 */
>> +	irq = orion5x_pci_map_irq(dev, slot, pin);
>> +	if (irq != -1)
>> +		return irq;
>> +
>> +	/*
>> +	 * PCI IRQs are connected via GPIOs
>> +	 */
>> +	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
>> +	case 0:
>> +		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
>> +	default:
>> +		return -1;
>> +	}
>> +}
>
> The other patches all appear good to me, but I find this one suspicious.
>
> Why are you not using the device tree for probing PCI? Is there anything
> missing in drivers/pci/host/pci-mvebu.c, or do you just need help
> describing it in DT?

Unlike the other SoC's supported by pci-mvebu.c, orion5x has one PCI port 
as well as a PCIe port. Given no other orion5x boards seem to use 
pci-mvebu, I'm assuming there's work to be done before the PCI port can be 
used via. pci-mvebu.c

This is something I can look into if there aren't patches out there, but 
wanted to get the rest into a reasonable state first.

>
> 	Arnd
>

-- 
Jamie Lentin

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On Sat, 16 Jul 2016, Arnd Bergmann wrote:

> On Saturday, July 16, 2016 3:29:04 PM CEST Jamie Lentin wrote:
>> +
>> +#define WNR854T_PCI_SLOT0_OFFS	7
>> +#define WNR854T_PCI_SLOT0_IRQ_PIN	4
>> +
>> +static void __init wnr854t_pci_preinit(void)
>> +{
>> +	int pin;
>> +
>> +	/*
>> +	 * Configure PCI GPIO IRQ pins
>> +	 */
>> +	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
>> +	if (gpio_request(pin, "PCI Int") == 0) {
>> +		if (gpio_direction_input(pin) == 0) {
>> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
>> +		} else {
>> +			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
>> +				pin);
>> +			gpio_free(pin);
>> +		}
>> +	} else {
>> +		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
>> +	}
>> +}
>> +
>> +static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
>> +	u8 pin)
>> +{
>> +	int irq;
>> +
>> +	/*
>> +	 * Check for devices with hard-wired IRQs.
>> +	 */
>> +	irq = orion5x_pci_map_irq(dev, slot, pin);
>> +	if (irq != -1)
>> +		return irq;
>> +
>> +	/*
>> +	 * PCI IRQs are connected via GPIOs
>> +	 */
>> +	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
>> +	case 0:
>> +		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
>> +	default:
>> +		return -1;
>> +	}
>> +}
>
> The other patches all appear good to me, but I find this one suspicious.
>
> Why are you not using the device tree for probing PCI? Is there anything
> missing in drivers/pci/host/pci-mvebu.c, or do you just need help
> describing it in DT?

Unlike the other SoC's supported by pci-mvebu.c, orion5x has one PCI port 
as well as a PCIe port. Given no other orion5x boards seem to use 
pci-mvebu, I'm assuming there's work to be done before the PCI port can be 
used via. pci-mvebu.c

This is something I can look into if there aren't patches out there, but 
wanted to get the rest into a reasonable state first.

>
> 	Arnd
>

-- 
Jamie Lentin

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On Sat, 16 Jul 2016, Arnd Bergmann wrote:

> On Saturday, July 16, 2016 3:29:04 PM CEST Jamie Lentin wrote:
>> +
>> +#define WNR854T_PCI_SLOT0_OFFS	7
>> +#define WNR854T_PCI_SLOT0_IRQ_PIN	4
>> +
>> +static void __init wnr854t_pci_preinit(void)
>> +{
>> +	int pin;
>> +
>> +	/*
>> +	 * Configure PCI GPIO IRQ pins
>> +	 */
>> +	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
>> +	if (gpio_request(pin, "PCI Int") == 0) {
>> +		if (gpio_direction_input(pin) == 0) {
>> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
>> +		} else {
>> +			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
>> +				pin);
>> +			gpio_free(pin);
>> +		}
>> +	} else {
>> +		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
>> +	}
>> +}
>> +
>> +static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
>> +	u8 pin)
>> +{
>> +	int irq;
>> +
>> +	/*
>> +	 * Check for devices with hard-wired IRQs.
>> +	 */
>> +	irq = orion5x_pci_map_irq(dev, slot, pin);
>> +	if (irq != -1)
>> +		return irq;
>> +
>> +	/*
>> +	 * PCI IRQs are connected via GPIOs
>> +	 */
>> +	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
>> +	case 0:
>> +		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
>> +	default:
>> +		return -1;
>> +	}
>> +}
>
> The other patches all appear good to me, but I find this one suspicious.
>
> Why are you not using the device tree for probing PCI? Is there anything
> missing in drivers/pci/host/pci-mvebu.c, or do you just need help
> describing it in DT?

Unlike the other SoC's supported by pci-mvebu.c, orion5x has one PCI port 
as well as a PCIe port. Given no other orion5x boards seem to use 
pci-mvebu, I'm assuming there's work to be done before the PCI port can be 
used via. pci-mvebu.c

This is something I can look into if there aren't patches out there, but 
wanted to get the rest into a reasonable state first.

>
> 	Arnd
>

-- 
Jamie Lentin

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Sunday, July 17, 2016 10:39:01 AM CEST Jamie Lentin wrote:
> On Sat, 16 Jul 2016, Arnd Bergmann wrote:

> > The other patches all appear good to me, but I find this one suspicious.
> >
> > Why are you not using the device tree for probing PCI? Is there anything
> > missing in drivers/pci/host/pci-mvebu.c, or do you just need help
> > describing it in DT?
> 
> Unlike the other SoC's supported by pci-mvebu.c, orion5x has one PCI port 
> as well as a PCIe port. Given no other orion5x boards seem to use 
> pci-mvebu, I'm assuming there's work to be done before the PCI port can be 
> used via. pci-mvebu.c
> 
> This is something I can look into if there aren't patches out there, but 
> wanted to get the rest into a reasonable state first.

Ok, I see your point. However, we also don't have any other Orion5x machines
using DT that rely on old probe method, and I this is something that
is particularly hard to retrofit later.

I would assume that the PCIe port should work out of the box with the driver
we have, but the PCI controller does not, and it will require some work.
Looking at https://wiki.openwrt.org/toh/netgear/wnr854t, I assume that
you want only PCI but not PCIe, correct?

The good news is that we can completely separate the two, we just have two
different PCI domains if both are enabled, so we just need to add a new
driver for the PCI port to drivers/pci/host. The pci_ops can be copied
from the existing driver, although a couple of minor cleanups would be
possible. The special handling of bus numbers and the rc_pci_fixup()
can probably just go away, and the latter part is particularly
important, because building a kernel with the fixup included might
break any system with a Marvell host bridge.

We also don't seem to need any MBUS window setup for the I/O and
memory spaces, which greatly simplifies the driver compared to the
pci-mvebu one, it would be a fairly straightforward implementation
based on pci-host-generic.c (which unfortunately just got way
more complicated and might need to go on a diet).

	Arnd

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Sunday, July 17, 2016 10:39:01 AM CEST Jamie Lentin wrote:
> On Sat, 16 Jul 2016, Arnd Bergmann wrote:

> > The other patches all appear good to me, but I find this one suspicious.
> >
> > Why are you not using the device tree for probing PCI? Is there anything
> > missing in drivers/pci/host/pci-mvebu.c, or do you just need help
> > describing it in DT?
> 
> Unlike the other SoC's supported by pci-mvebu.c, orion5x has one PCI port 
> as well as a PCIe port. Given no other orion5x boards seem to use 
> pci-mvebu, I'm assuming there's work to be done before the PCI port can be 
> used via. pci-mvebu.c
> 
> This is something I can look into if there aren't patches out there, but 
> wanted to get the rest into a reasonable state first.

Ok, I see your point. However, we also don't have any other Orion5x machines
using DT that rely on old probe method, and I this is something that
is particularly hard to retrofit later.

I would assume that the PCIe port should work out of the box with the driver
we have, but the PCI controller does not, and it will require some work.
Looking at https://wiki.openwrt.org/toh/netgear/wnr854t, I assume that
you want only PCI but not PCIe, correct?

The good news is that we can completely separate the two, we just have two
different PCI domains if both are enabled, so we just need to add a new
driver for the PCI port to drivers/pci/host. The pci_ops can be copied
from the existing driver, although a couple of minor cleanups would be
possible. The special handling of bus numbers and the rc_pci_fixup()
can probably just go away, and the latter part is particularly
important, because building a kernel with the fixup included might
break any system with a Marvell host bridge.

We also don't seem to need any MBUS window setup for the I/O and
memory spaces, which greatly simplifies the driver compared to the
pci-mvebu one, it would be a fairly straightforward implementation
based on pci-host-generic.c (which unfortunately just got way
more complicated and might need to go on a diet).

	Arnd

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Thomas Petazzoni]

Hello,

On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:

> I would assume that the PCIe port should work out of the box with the driver

Unfortunately, no. The PCIe on Orion5x requires a workaround for
reading/writing the PCI configuration space. Instead of doing MMIO
accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
MBus window, which provides a memory-mapped view of the PCI
configuration space.

Definitely not impossible to implement, but the driver doesn't work
as-is.

> We also don't seem to need any MBUS window setup for the I/O and
> memory spaces, which greatly simplifies the driver compared to the
> pci-mvebu one, it would be a fairly straightforward implementation
> based on pci-host-generic.c (which unfortunately just got way
> more complicated and might need to go on a diet).

MBus windows are needed. See:

        mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
                                          ORION_MBUS_PCI_IO_ATTR,
                                          ORION5X_PCI_IO_PHYS_BASE,
                                          ORION5X_PCI_IO_SIZE,
                                          ORION5X_PCI_IO_BUS_BASE);
        mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
                                    ORION_MBUS_PCI_MEM_ATTR,
                                    ORION5X_PCI_MEM_PHYS_BASE,
                                    ORION5X_PCI_MEM_SIZE);

in orion5x_setup_wins().

Note that we already have some Orion5x converted to DT, and that use
PCI: board-rd88f5182.c is an example. So we could very well take Jamie
patches as-is, and move later to a DT-representation for PCI/PCIe.

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Thomas Petazzoni]

Hello,

On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:

> I would assume that the PCIe port should work out of the box with the driver

Unfortunately, no. The PCIe on Orion5x requires a workaround for
reading/writing the PCI configuration space. Instead of doing MMIO
accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
MBus window, which provides a memory-mapped view of the PCI
configuration space.

Definitely not impossible to implement, but the driver doesn't work
as-is.

> We also don't seem to need any MBUS window setup for the I/O and
> memory spaces, which greatly simplifies the driver compared to the
> pci-mvebu one, it would be a fairly straightforward implementation
> based on pci-host-generic.c (which unfortunately just got way
> more complicated and might need to go on a diet).

MBus windows are needed. See:

        mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
                                          ORION_MBUS_PCI_IO_ATTR,
                                          ORION5X_PCI_IO_PHYS_BASE,
                                          ORION5X_PCI_IO_SIZE,
                                          ORION5X_PCI_IO_BUS_BASE);
        mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
                                    ORION_MBUS_PCI_MEM_ATTR,
                                    ORION5X_PCI_MEM_PHYS_BASE,
                                    ORION5X_PCI_MEM_SIZE);

in orion5x_setup_wins().

Note that we already have some Orion5x converted to DT, and that use
PCI: board-rd88f5182.c is an example. So we could very well take Jamie
patches as-is, and move later to a DT-representation for PCI/PCIe.

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
> 
> On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
> 
> > I would assume that the PCIe port should work out of the box with the driver
> 
> Unfortunately, no. The PCIe on Orion5x requires a workaround for
> reading/writing the PCI configuration space. Instead of doing MMIO
> accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
> MBus window, which provides a memory-mapped view of the PCI
> configuration space.
> 
> Definitely not impossible to implement, but the driver doesn't work
> as-is.

Ok.

> > We also don't seem to need any MBUS window setup for the I/O and
> > memory spaces, which greatly simplifies the driver compared to the
> > pci-mvebu one, it would be a fairly straightforward implementation
> > based on pci-host-generic.c (which unfortunately just got way
> > more complicated and might need to go on a diet).
> 
> MBus windows are needed. See:
> 
>         mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
>                                           ORION_MBUS_PCI_IO_ATTR,
>                                           ORION5X_PCI_IO_PHYS_BASE,
>                                           ORION5X_PCI_IO_SIZE,
>                                           ORION5X_PCI_IO_BUS_BASE);
>         mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
>                                     ORION_MBUS_PCI_MEM_ATTR,
>                                     ORION5X_PCI_MEM_PHYS_BASE,
>                                     ORION5X_PCI_MEM_SIZE);
> 
> in orion5x_setup_wins().

Ok, I was just looking at the wrong file, as they are set up from
common.c, not pci.c.

> Note that we already have some Orion5x converted to DT, and that use
> PCI: board-rd88f5182.c is an example. So we could very well take Jamie
> patches as-is, and move later to a DT-representation for PCI/PCIe.

Ah, I thought all the DT users were moved to mach-mvebu. I agree
this new patch isn't introducing anything we don't already have then,
so we can just take it, but the conversion will not be nice when
we do that.

I was also hoping that we could get to the point where pci_common_init()
is only used for legacy machines without DT and without multiplatform,
it seems I missed a couple of users here.

	Arnd

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
> 
> On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
> 
> > I would assume that the PCIe port should work out of the box with the driver
> 
> Unfortunately, no. The PCIe on Orion5x requires a workaround for
> reading/writing the PCI configuration space. Instead of doing MMIO
> accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
> MBus window, which provides a memory-mapped view of the PCI
> configuration space.
> 
> Definitely not impossible to implement, but the driver doesn't work
> as-is.

Ok.

> > We also don't seem to need any MBUS window setup for the I/O and
> > memory spaces, which greatly simplifies the driver compared to the
> > pci-mvebu one, it would be a fairly straightforward implementation
> > based on pci-host-generic.c (which unfortunately just got way
> > more complicated and might need to go on a diet).
> 
> MBus windows are needed. See:
> 
>         mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
>                                           ORION_MBUS_PCI_IO_ATTR,
>                                           ORION5X_PCI_IO_PHYS_BASE,
>                                           ORION5X_PCI_IO_SIZE,
>                                           ORION5X_PCI_IO_BUS_BASE);
>         mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
>                                     ORION_MBUS_PCI_MEM_ATTR,
>                                     ORION5X_PCI_MEM_PHYS_BASE,
>                                     ORION5X_PCI_MEM_SIZE);
> 
> in orion5x_setup_wins().

Ok, I was just looking at the wrong file, as they are set up from
common.c, not pci.c.

> Note that we already have some Orion5x converted to DT, and that use
> PCI: board-rd88f5182.c is an example. So we could very well take Jamie
> patches as-is, and move later to a DT-representation for PCI/PCIe.

Ah, I thought all the DT users were moved to mach-mvebu. I agree
this new patch isn't introducing anything we don't already have then,
so we can just take it, but the conversion will not be nice when
we do that.

I was also hoping that we could get to the point where pci_common_init()
is only used for legacy machines without DT and without multiplatform,
it seems I missed a couple of users here.

	Arnd

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
> 
> On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
> 
> > I would assume that the PCIe port should work out of the box with the driver
> 
> Unfortunately, no. The PCIe on Orion5x requires a workaround for
> reading/writing the PCI configuration space. Instead of doing MMIO
> accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
> MBus window, which provides a memory-mapped view of the PCI
> configuration space.
> 
> Definitely not impossible to implement, but the driver doesn't work
> as-is.

Ok.

> > We also don't seem to need any MBUS window setup for the I/O and
> > memory spaces, which greatly simplifies the driver compared to the
> > pci-mvebu one, it would be a fairly straightforward implementation
> > based on pci-host-generic.c (which unfortunately just got way
> > more complicated and might need to go on a diet).
> 
> MBus windows are needed. See:
> 
>         mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
>                                           ORION_MBUS_PCI_IO_ATTR,
>                                           ORION5X_PCI_IO_PHYS_BASE,
>                                           ORION5X_PCI_IO_SIZE,
>                                           ORION5X_PCI_IO_BUS_BASE);
>         mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
>                                     ORION_MBUS_PCI_MEM_ATTR,
>                                     ORION5X_PCI_MEM_PHYS_BASE,
>                                     ORION5X_PCI_MEM_SIZE);
> 
> in orion5x_setup_wins().

Ok, I was just looking at the wrong file, as they are set up from
common.c, not pci.c.

> Note that we already have some Orion5x converted to DT, and that use
> PCI: board-rd88f5182.c is an example. So we could very well take Jamie
> patches as-is, and move later to a DT-representation for PCI/PCIe.

Ah, I thought all the DT users were moved to mach-mvebu. I agree
this new patch isn't introducing anything we don't already have then,
so we can just take it, but the conversion will not be nice when
we do that.

I was also hoping that we could get to the point where pci_common_init()
is only used for legacy machines without DT and without multiplatform,
it seems I missed a couple of users here.

	Arnd

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On Mon, 18 Jul 2016, Arnd Bergmann wrote:

> On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
>>
>> On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
>>
>>> I would assume that the PCIe port should work out of the box with the driver
>>
>> Unfortunately, no. The PCIe on Orion5x requires a workaround for
>> reading/writing the PCI configuration space. Instead of doing MMIO
>> accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
>> MBus window, which provides a memory-mapped view of the PCI
>> configuration space.
>>
>> Definitely not impossible to implement, but the driver doesn't work
>> as-is.
>
> Ok.

Unfortunately this isn't something I can test as the PCIe port on the SoC 
doesn't go anywhere in my case.

>>> We also don't seem to need any MBUS window setup for the I/O and
>>> memory spaces, which greatly simplifies the driver compared to the
>>> pci-mvebu one, it would be a fairly straightforward implementation
>>> based on pci-host-generic.c (which unfortunately just got way
>>> more complicated and might need to go on a diet).
>>
>> MBus windows are needed. See:
>>
>>         mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
>>                                           ORION_MBUS_PCI_IO_ATTR,
>>                                           ORION5X_PCI_IO_PHYS_BASE,
>>                                           ORION5X_PCI_IO_SIZE,
>>                                           ORION5X_PCI_IO_BUS_BASE);
>>         mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
>>                                     ORION_MBUS_PCI_MEM_ATTR,
>>                                     ORION5X_PCI_MEM_PHYS_BASE,
>>                                     ORION5X_PCI_MEM_SIZE);
>>
>> in orion5x_setup_wins().
>
> Ok, I was just looking at the wrong file, as they are set up from
> common.c, not pci.c.
>
>> Note that we already have some Orion5x converted to DT, and that use
>> PCI: board-rd88f5182.c is an example. So we could very well take Jamie
>> patches as-is, and move later to a DT-representation for PCI/PCIe.
>
> Ah, I thought all the DT users were moved to mach-mvebu. I agree
> this new patch isn't introducing anything we don't already have then,
> so we can just take it, but the conversion will not be nice when
> we do that.

Yes, board-wnr854t.c is a clone of the existing board-rd88f5182.c. 
Although I'd presume that it too would need late_initcall() or somesuch 
mechanism to probe PCI once the GPIO controller is available.

> I was also hoping that we could get to the point where pci_common_init()
> is only used for legacy machines without DT and without multiplatform,
> it seems I missed a couple of users here.
>
> 	Arnd
>

-- 
Jamie Lentin

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On Mon, 18 Jul 2016, Arnd Bergmann wrote:

> On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
>>
>> On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
>>
>>> I would assume that the PCIe port should work out of the box with the driver
>>
>> Unfortunately, no. The PCIe on Orion5x requires a workaround for
>> reading/writing the PCI configuration space. Instead of doing MMIO
>> accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
>> MBus window, which provides a memory-mapped view of the PCI
>> configuration space.
>>
>> Definitely not impossible to implement, but the driver doesn't work
>> as-is.
>
> Ok.

Unfortunately this isn't something I can test as the PCIe port on the SoC 
doesn't go anywhere in my case.

>>> We also don't seem to need any MBUS window setup for the I/O and
>>> memory spaces, which greatly simplifies the driver compared to the
>>> pci-mvebu one, it would be a fairly straightforward implementation
>>> based on pci-host-generic.c (which unfortunately just got way
>>> more complicated and might need to go on a diet).
>>
>> MBus windows are needed. See:
>>
>>         mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
>>                                           ORION_MBUS_PCI_IO_ATTR,
>>                                           ORION5X_PCI_IO_PHYS_BASE,
>>                                           ORION5X_PCI_IO_SIZE,
>>                                           ORION5X_PCI_IO_BUS_BASE);
>>         mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
>>                                     ORION_MBUS_PCI_MEM_ATTR,
>>                                     ORION5X_PCI_MEM_PHYS_BASE,
>>                                     ORION5X_PCI_MEM_SIZE);
>>
>> in orion5x_setup_wins().
>
> Ok, I was just looking at the wrong file, as they are set up from
> common.c, not pci.c.
>
>> Note that we already have some Orion5x converted to DT, and that use
>> PCI: board-rd88f5182.c is an example. So we could very well take Jamie
>> patches as-is, and move later to a DT-representation for PCI/PCIe.
>
> Ah, I thought all the DT users were moved to mach-mvebu. I agree
> this new patch isn't introducing anything we don't already have then,
> so we can just take it, but the conversion will not be nice when
> we do that.

Yes, board-wnr854t.c is a clone of the existing board-rd88f5182.c. 
Although I'd presume that it too would need late_initcall() or somesuch 
mechanism to probe PCI once the GPIO controller is available.

> I was also hoping that we could get to the point where pci_common_init()
> is only used for legacy machines without DT and without multiplatform,
> it seems I missed a couple of users here.
>
> 	Arnd
>

-- 
Jamie Lentin

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Tuesday, July 19, 2016 10:40:16 AM CEST Jamie Lentin wrote:
> On Mon, 18 Jul 2016, Arnd Bergmann wrote:
> 
> > On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
> >>
> >> On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
> >>
> >>> I would assume that the PCIe port should work out of the box with the driver
> >>
> >> Unfortunately, no. The PCIe on Orion5x requires a workaround for
> >> reading/writing the PCI configuration space. Instead of doing MMIO
> >> accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
> >> MBus window, which provides a memory-mapped view of the PCI
> >> configuration space.
> >>
> >> Definitely not impossible to implement, but the driver doesn't work
> >> as-is.
> >
> > Ok.
> 
> Unfortunately this isn't something I can test as the PCIe port on the SoC 
> doesn't go anywhere in my case.

As I said, this wouldn't be a problem: we should consider the PCI and PCIe
ports on this chip as completely separate anyway, so we can work on
the drivers independently.

> >>> We also don't seem to need any MBUS window setup for the I/O and
> >>> memory spaces, which greatly simplifies the driver compared to the
> >>> pci-mvebu one, it would be a fairly straightforward implementation
> >>> based on pci-host-generic.c (which unfortunately just got way
> >>> more complicated and might need to go on a diet).
> >>
> >> MBus windows are needed. See:
> >>
> >>         mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
> >>                                           ORION_MBUS_PCI_IO_ATTR,
> >>                                           ORION5X_PCI_IO_PHYS_BASE,
> >>                                           ORION5X_PCI_IO_SIZE,
> >>                                           ORION5X_PCI_IO_BUS_BASE);
> >>         mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
> >>                                     ORION_MBUS_PCI_MEM_ATTR,
> >>                                     ORION5X_PCI_MEM_PHYS_BASE,
> >>                                     ORION5X_PCI_MEM_SIZE);
> >>
> >> in orion5x_setup_wins().
> >
> > Ok, I was just looking at the wrong file, as they are set up from
> > common.c, not pci.c.
> >
> >> Note that we already have some Orion5x converted to DT, and that use
> >> PCI: board-rd88f5182.c is an example. So we could very well take Jamie
> >> patches as-is, and move later to a DT-representation for PCI/PCIe.
> >
> > Ah, I thought all the DT users were moved to mach-mvebu. I agree
> > this new patch isn't introducing anything we don't already have then,
> > so we can just take it, but the conversion will not be nice when
> > we do that.
> 
> Yes, board-wnr854t.c is a clone of the existing board-rd88f5182.c. 
> Although I'd presume that it too would need late_initcall() or somesuch 
> mechanism to probe PCI once the GPIO controller is available.

Deferred probing should be fine once the driver is migrated from
pci_common_init() to registering the host bridge directly.

	Arnd

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Tuesday, July 19, 2016 10:40:16 AM CEST Jamie Lentin wrote:
> On Mon, 18 Jul 2016, Arnd Bergmann wrote:
> 
> > On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
> >>
> >> On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
> >>
> >>> I would assume that the PCIe port should work out of the box with the driver
> >>
> >> Unfortunately, no. The PCIe on Orion5x requires a workaround for
> >> reading/writing the PCI configuration space. Instead of doing MMIO
> >> accesses to PCIE_CONF_ADDR_OFF / PCIE_CONF_DATA_OFF, you must map a
> >> MBus window, which provides a memory-mapped view of the PCI
> >> configuration space.
> >>
> >> Definitely not impossible to implement, but the driver doesn't work
> >> as-is.
> >
> > Ok.
> 
> Unfortunately this isn't something I can test as the PCIe port on the SoC 
> doesn't go anywhere in my case.

As I said, this wouldn't be a problem: we should consider the PCI and PCIe
ports on this chip as completely separate anyway, so we can work on
the drivers independently.

> >>> We also don't seem to need any MBUS window setup for the I/O and
> >>> memory spaces, which greatly simplifies the driver compared to the
> >>> pci-mvebu one, it would be a fairly straightforward implementation
> >>> based on pci-host-generic.c (which unfortunately just got way
> >>> more complicated and might need to go on a diet).
> >>
> >> MBus windows are needed. See:
> >>
> >>         mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
> >>                                           ORION_MBUS_PCI_IO_ATTR,
> >>                                           ORION5X_PCI_IO_PHYS_BASE,
> >>                                           ORION5X_PCI_IO_SIZE,
> >>                                           ORION5X_PCI_IO_BUS_BASE);
> >>         mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
> >>                                     ORION_MBUS_PCI_MEM_ATTR,
> >>                                     ORION5X_PCI_MEM_PHYS_BASE,
> >>                                     ORION5X_PCI_MEM_SIZE);
> >>
> >> in orion5x_setup_wins().
> >
> > Ok, I was just looking at the wrong file, as they are set up from
> > common.c, not pci.c.
> >
> >> Note that we already have some Orion5x converted to DT, and that use
> >> PCI: board-rd88f5182.c is an example. So we could very well take Jamie
> >> patches as-is, and move later to a DT-representation for PCI/PCIe.
> >
> > Ah, I thought all the DT users were moved to mach-mvebu. I agree
> > this new patch isn't introducing anything we don't already have then,
> > so we can just take it, but the conversion will not be nice when
> > we do that.
> 
> Yes, board-wnr854t.c is a clone of the existing board-rd88f5182.c. 
> Although I'd presume that it too would need late_initcall() or somesuch 
> mechanism to probe PCI once the GPIO controller is available.

Deferred probing should be fine once the driver is migrated from
pci_common_init() to registering the host bridge directly.

	Arnd

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:04PM +0100, Jamie Lentin wrote:
> This is a router based on the mv88f5181 chipset.
> 
> http://www.netgear.com/support/product/WNR854T.aspx
> http://wiki.openwrt.org/toh/netgear/wnr854t
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 200 +++++++++++++++++++++
>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>  arch/arm/mach-orion5x/Makefile                     |   1 +
>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
>  6 files changed, 287 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>  create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> index ff3c120..748a8f2 100644
> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> @@ -22,3 +22,4 @@ board. Currently known boards are:
>  "lacie,d2-network"
>  "marvell,rd-88f5182-nas"
>  "maxtor,shared-storage-2"
> +"netgear,wnr854t"
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 95c1923..63b9202 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -535,6 +535,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
>  	orion5x-linkstation-lswtgl.dtb \
>  	orion5x-lswsgl.dtb \
>  	orion5x-maxtor-shared-storage-2.dtb \
> +	orion5x-netgear-wnr854t.dtb \
>  	orion5x-rd88f5182-nas.dtb
>  dtb-$(CONFIG_ARCH_PRIMA2) += \
>  	prima2-evb.dtb
> diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
> new file mode 100644
> index 0000000..a8e89d8
> --- /dev/null
> +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
> @@ -0,0 +1,200 @@
> +/*
> + * Copyright (C) 2014 Jamie Lentin <jm@lentin.co.uk>

It's 2016 now.

> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "orion5x-mv88f5181.dtsi"
> +
> +/ {
> +	model = "Netgear WNR854-t";
> +	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
> +			"marvell,orion5x";
> +
> +	memory {
> +		reg = <0x00000000 0x2000000>; /* 32 MB */
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +		linux,stdout-path = &uart0;

As kind of mentioned, drop the linux prefix here.

> +	};
> +
> +	soc {
> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
> +			<MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
> +			<MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-0 = <&pmx_reset_switch>;
> +		pinctrl-names = "default";
> +
> +		reset {
> +			label = "Reset Button";
> +			linux,code = <KEY_RESTART>;
> +			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
> +		pinctrl-names = "default";
> +
> +		led@0 {
> +			label = "power:green";
> +			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		led@1 {
> +			label = "power:blink";
> +			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		led@2 {
> +			label = "wan:green";
> +			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +
> +	dsa@0 {
> +		compatible = "marvell,dsa";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		dsa,ethernet = <&ethport>;
> +		dsa,mii-bus = <&mdio>;
> +
> +		switch@0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
> +
> +			port@0 {
> +				reg = <0>;
> +				label = "lan3";
> +			};
> +
> +			port@1 {
> +				reg = <1>;
> +				label = "lan4";
> +			};
> +
> +			port@2 {
> +				reg = <2>;
> +				label = "wan";
> +			};
> +
> +			port@3 {
> +				reg = <3>;
> +				label = "cpu";
> +			};
> +
> +			port@5 {
> +				reg = <5>;
> +				label = "lan1";
> +			};
> +
> +			port@7 {
> +				reg = <7>;
> +				label = "lan2";
> +			};
> +		};
> +	};
> +};
> +
> +&devbus_bootcs {
> +	status = "okay";
> +
> +	devbus,keep-config;
> +
> +	flash@0 {
> +		compatible = "cfi-flash";
> +		reg = <0 0x800000>;
> +		bank-width = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		partition@0 {

The new recommended style adds a level here with a partitions node and 
the type of partitioning.

> +			label = "kernel";
> +			reg = <0x0 0x100000>;
> +		};
> +
> +		partition@100000 {
> +			label = "rootfs";
> +			reg = <0x100000 0x660000>;
> +		};
> +
> +		partition@760000 {
> +			label = "uboot_env";
> +			reg = <0x760000 0x20000>;
> +		};
> +
> +		partition@780000 {
> +			label = "uboot";
> +			reg = <0x780000 0x80000>;
> +			read-only;
> +		};
> +	};
> +};
> +
> +&mdio {
> +	status = "okay";
> +};
> +
> +&eth {
> +	status = "okay";
> +	ethernet-port@0 {
> +		speed = <1000>;
> +		duplex = <1>;
> +	};
> +};
> +
> +&pinctrl {
> +	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
> +	pinctrl-names = "default";
> +
> +	pmx_power_led: pmx-power-led {
> +		marvell,pins = "mpp0";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_reset_switch: pmx-reset-switch {
> +		marvell,pins = "mpp1";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_power_led_blink: pmx-power-led-blink {
> +		marvell,pins = "mpp2";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_wan_led: pmx-wan-led {
> +		marvell,pins = "mpp3";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_pci_gpios: pmx-pci-gpios {
> +		marvell,pins = "mpp4";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_ge: pmx-ge {
> +		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
> +				"mpp16", "mpp17", "mpp18", "mpp19";
> +		marvell,function = "ge";
> +	};
> +};
> +
> +&uart0 {
> +	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
> +	status = "okay";
> +};
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index a2af158..1fdb95d 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -151,6 +151,12 @@ config MACH_MSS2_DT
>  	  Say 'Y' here if you want your kernel to support the
>  	  Maxtor Shared Storage II platform.
>  
> +config MACH_WNR854T_DT

There should only be at most 1 kconfig entry for all orion5x DT based 
platforms.

> +	bool "Netgear WNR854T (Flattened Device Tree)"
> +	help
> +	  Say 'Y' here if you want your kernel to support the
> +	  Netgear WNR854T platform.
> +
>  config MACH_WNR854T
>  	bool "Netgear WNR854T"
>  	help

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Rob Herring]

On Sat, Jul 16, 2016 at 03:29:04PM +0100, Jamie Lentin wrote:
> This is a router based on the mv88f5181 chipset.
> 
> http://www.netgear.com/support/product/WNR854T.aspx
> http://wiki.openwrt.org/toh/netgear/wnr854t
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 200 +++++++++++++++++++++
>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>  arch/arm/mach-orion5x/Makefile                     |   1 +
>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
>  6 files changed, 287 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>  create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> index ff3c120..748a8f2 100644
> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> @@ -22,3 +22,4 @@ board. Currently known boards are:
>  "lacie,d2-network"
>  "marvell,rd-88f5182-nas"
>  "maxtor,shared-storage-2"
> +"netgear,wnr854t"
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 95c1923..63b9202 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -535,6 +535,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
>  	orion5x-linkstation-lswtgl.dtb \
>  	orion5x-lswsgl.dtb \
>  	orion5x-maxtor-shared-storage-2.dtb \
> +	orion5x-netgear-wnr854t.dtb \
>  	orion5x-rd88f5182-nas.dtb
>  dtb-$(CONFIG_ARCH_PRIMA2) += \
>  	prima2-evb.dtb
> diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
> new file mode 100644
> index 0000000..a8e89d8
> --- /dev/null
> +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
> @@ -0,0 +1,200 @@
> +/*
> + * Copyright (C) 2014 Jamie Lentin <jm@lentin.co.uk>

It's 2016 now.

> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "orion5x-mv88f5181.dtsi"
> +
> +/ {
> +	model = "Netgear WNR854-t";
> +	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
> +			"marvell,orion5x";
> +
> +	memory {
> +		reg = <0x00000000 0x2000000>; /* 32 MB */
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +		linux,stdout-path = &uart0;

As kind of mentioned, drop the linux prefix here.

> +	};
> +
> +	soc {
> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
> +			<MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
> +			<MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-0 = <&pmx_reset_switch>;
> +		pinctrl-names = "default";
> +
> +		reset {
> +			label = "Reset Button";
> +			linux,code = <KEY_RESTART>;
> +			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
> +		pinctrl-names = "default";
> +
> +		led at 0 {
> +			label = "power:green";
> +			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		led at 1 {
> +			label = "power:blink";
> +			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		led at 2 {
> +			label = "wan:green";
> +			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +
> +	dsa at 0 {
> +		compatible = "marvell,dsa";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		dsa,ethernet = <&ethport>;
> +		dsa,mii-bus = <&mdio>;
> +
> +		switch at 0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
> +
> +			port at 0 {
> +				reg = <0>;
> +				label = "lan3";
> +			};
> +
> +			port at 1 {
> +				reg = <1>;
> +				label = "lan4";
> +			};
> +
> +			port at 2 {
> +				reg = <2>;
> +				label = "wan";
> +			};
> +
> +			port at 3 {
> +				reg = <3>;
> +				label = "cpu";
> +			};
> +
> +			port at 5 {
> +				reg = <5>;
> +				label = "lan1";
> +			};
> +
> +			port at 7 {
> +				reg = <7>;
> +				label = "lan2";
> +			};
> +		};
> +	};
> +};
> +
> +&devbus_bootcs {
> +	status = "okay";
> +
> +	devbus,keep-config;
> +
> +	flash at 0 {
> +		compatible = "cfi-flash";
> +		reg = <0 0x800000>;
> +		bank-width = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		partition at 0 {

The new recommended style adds a level here with a partitions node and 
the type of partitioning.

> +			label = "kernel";
> +			reg = <0x0 0x100000>;
> +		};
> +
> +		partition at 100000 {
> +			label = "rootfs";
> +			reg = <0x100000 0x660000>;
> +		};
> +
> +		partition at 760000 {
> +			label = "uboot_env";
> +			reg = <0x760000 0x20000>;
> +		};
> +
> +		partition at 780000 {
> +			label = "uboot";
> +			reg = <0x780000 0x80000>;
> +			read-only;
> +		};
> +	};
> +};
> +
> +&mdio {
> +	status = "okay";
> +};
> +
> +&eth {
> +	status = "okay";
> +	ethernet-port at 0 {
> +		speed = <1000>;
> +		duplex = <1>;
> +	};
> +};
> +
> +&pinctrl {
> +	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
> +	pinctrl-names = "default";
> +
> +	pmx_power_led: pmx-power-led {
> +		marvell,pins = "mpp0";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_reset_switch: pmx-reset-switch {
> +		marvell,pins = "mpp1";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_power_led_blink: pmx-power-led-blink {
> +		marvell,pins = "mpp2";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_wan_led: pmx-wan-led {
> +		marvell,pins = "mpp3";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_pci_gpios: pmx-pci-gpios {
> +		marvell,pins = "mpp4";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_ge: pmx-ge {
> +		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
> +				"mpp16", "mpp17", "mpp18", "mpp19";
> +		marvell,function = "ge";
> +	};
> +};
> +
> +&uart0 {
> +	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
> +	status = "okay";
> +};
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index a2af158..1fdb95d 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -151,6 +151,12 @@ config MACH_MSS2_DT
>  	  Say 'Y' here if you want your kernel to support the
>  	  Maxtor Shared Storage II platform.
>  
> +config MACH_WNR854T_DT

There should only be at most 1 kconfig entry for all orion5x DT based 
platforms.

> +	bool "Netgear WNR854T (Flattened Device Tree)"
> +	help
> +	  Say 'Y' here if you want your kernel to support the
> +	  Netgear WNR854T platform.
> +
>  config MACH_WNR854T
>  	bool "Netgear WNR854T"
>  	help

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On Sun, 17 Jul 2016, Rob Herring wrote:

> On Sat, Jul 16, 2016 at 03:29:04PM +0100, Jamie Lentin wrote:
>> This is a router based on the mv88f5181 chipset.
>>
>> http://www.netgear.com/support/product/WNR854T.aspx
>> http://wiki.openwrt.org/toh/netgear/wnr854t
>>
>> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
>> ---
>>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>>  arch/arm/boot/dts/Makefile                         |   1 +
>>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 200 +++++++++++++++++++++
>>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>>  arch/arm/mach-orion5x/Makefile                     |   1 +
>>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
>>  6 files changed, 287 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>>  create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
>>
>> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> index ff3c120..748a8f2 100644
>> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> @@ -22,3 +22,4 @@ board. Currently known boards are:
>>  "lacie,d2-network"
>>  "marvell,rd-88f5182-nas"
>>  "maxtor,shared-storage-2"
>> +"netgear,wnr854t"
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 95c1923..63b9202 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -535,6 +535,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
>>  	orion5x-linkstation-lswtgl.dtb \
>>  	orion5x-lswsgl.dtb \
>>  	orion5x-maxtor-shared-storage-2.dtb \
>> +	orion5x-netgear-wnr854t.dtb \
>>  	orion5x-rd88f5182-nas.dtb
>>  dtb-$(CONFIG_ARCH_PRIMA2) += \
>>  	prima2-evb.dtb
>> diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>> new file mode 100644
>> index 0000000..a8e89d8
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>> @@ -0,0 +1,200 @@
>> +/*
>> + * Copyright (C) 2014 Jamie Lentin <jm@lentin.co.uk>
>
> It's 2016 now.
>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +#include "orion5x-mv88f5181.dtsi"
>> +
>> +/ {
>> +	model = "Netgear WNR854-t";
>> +	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
>> +			"marvell,orion5x";
>> +
>> +	memory {
>> +		reg = <0x00000000 0x2000000>; /* 32 MB */
>> +	};
>> +
>> +	chosen {
>> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
>> +		linux,stdout-path = &uart0;
>
> As kind of mentioned, drop the linux prefix here.
>
>> +	};
>> +
>> +	soc {
>> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
>> +			<MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
>> +			<MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
>> +	};
>> +
>> +	gpio-keys {
>> +		compatible = "gpio-keys";
>> +		pinctrl-0 = <&pmx_reset_switch>;
>> +		pinctrl-names = "default";
>> +
>> +		reset {
>> +			label = "Reset Button";
>> +			linux,code = <KEY_RESTART>;
>> +			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
>> +		};
>> +	};
>> +
>> +	gpio-leds {
>> +		compatible = "gpio-leds";
>> +		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
>> +		pinctrl-names = "default";
>> +
>> +		led@0 {
>> +			label = "power:green";
>> +			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
>> +		};
>> +
>> +		led@1 {
>> +			label = "power:blink";
>> +			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
>> +		};
>> +
>> +		led@2 {
>> +			label = "wan:green";
>> +			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
>> +		};
>> +	};
>> +
>> +	dsa@0 {
>> +		compatible = "marvell,dsa";
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		dsa,ethernet = <&ethport>;
>> +		dsa,mii-bus = <&mdio>;
>> +
>> +		switch@0 {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
>> +
>> +			port@0 {
>> +				reg = <0>;
>> +				label = "lan3";
>> +			};
>> +
>> +			port@1 {
>> +				reg = <1>;
>> +				label = "lan4";
>> +			};
>> +
>> +			port@2 {
>> +				reg = <2>;
>> +				label = "wan";
>> +			};
>> +
>> +			port@3 {
>> +				reg = <3>;
>> +				label = "cpu";
>> +			};
>> +
>> +			port@5 {
>> +				reg = <5>;
>> +				label = "lan1";
>> +			};
>> +
>> +			port@7 {
>> +				reg = <7>;
>> +				label = "lan2";
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&devbus_bootcs {
>> +	status = "okay";
>> +
>> +	devbus,keep-config;
>> +
>> +	flash@0 {
>> +		compatible = "cfi-flash";
>> +		reg = <0 0x800000>;
>> +		bank-width = <1>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +
>> +		partition@0 {
>
> The new recommended style adds a level here with a partitions node and
> the type of partitioning.
>
>> +			label = "kernel";
>> +			reg = <0x0 0x100000>;
>> +		};
>> +
>> +		partition@100000 {
>> +			label = "rootfs";
>> +			reg = <0x100000 0x660000>;
>> +		};
>> +
>> +		partition@760000 {
>> +			label = "uboot_env";
>> +			reg = <0x760000 0x20000>;
>> +		};
>> +
>> +		partition@780000 {
>> +			label = "uboot";
>> +			reg = <0x780000 0x80000>;
>> +			read-only;
>> +		};
>> +	};
>> +};
>> +
>> +&mdio {
>> +	status = "okay";
>> +};
>> +
>> +&eth {
>> +	status = "okay";
>> +	ethernet-port@0 {
>> +		speed = <1000>;
>> +		duplex = <1>;
>> +	};
>> +};
>> +
>> +&pinctrl {
>> +	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
>> +	pinctrl-names = "default";
>> +
>> +	pmx_power_led: pmx-power-led {
>> +		marvell,pins = "mpp0";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_reset_switch: pmx-reset-switch {
>> +		marvell,pins = "mpp1";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_power_led_blink: pmx-power-led-blink {
>> +		marvell,pins = "mpp2";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_wan_led: pmx-wan-led {
>> +		marvell,pins = "mpp3";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_pci_gpios: pmx-pci-gpios {
>> +		marvell,pins = "mpp4";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_ge: pmx-ge {
>> +		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
>> +				"mpp16", "mpp17", "mpp18", "mpp19";
>> +		marvell,function = "ge";
>> +	};
>> +};
>> +
>> +&uart0 {
>> +	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
>> index a2af158..1fdb95d 100644
>> --- a/arch/arm/mach-orion5x/Kconfig
>> +++ b/arch/arm/mach-orion5x/Kconfig
>> @@ -151,6 +151,12 @@ config MACH_MSS2_DT
>>  	  Say 'Y' here if you want your kernel to support the
>>  	  Maxtor Shared Storage II platform.
>>
>> +config MACH_WNR854T_DT
>
> There should only be at most 1 kconfig entry for all orion5x DT based
> platforms.

Even though it needs arch/arm/mach-orion5x/board-wnr854t.c to init the 
PCI? orion5x currently has other board _DT options, I presumed for this 
reason.

>> +	bool "Netgear WNR854T (Flattened Device Tree)"
>> +	help
>> +	  Say 'Y' here if you want your kernel to support the
>> +	  Netgear WNR854T platform.
>> +
>>  config MACH_WNR854T
>>  	bool "Netgear WNR854T"
>>  	help
>

-- 
Jamie Lentin

[PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On Sun, 17 Jul 2016, Rob Herring wrote:

> On Sat, Jul 16, 2016 at 03:29:04PM +0100, Jamie Lentin wrote:
>> This is a router based on the mv88f5181 chipset.
>>
>> http://www.netgear.com/support/product/WNR854T.aspx
>> http://wiki.openwrt.org/toh/netgear/wnr854t
>>
>> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
>> ---
>>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>>  arch/arm/boot/dts/Makefile                         |   1 +
>>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 200 +++++++++++++++++++++
>>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>>  arch/arm/mach-orion5x/Makefile                     |   1 +
>>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
>>  6 files changed, 287 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>>  create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
>>
>> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> index ff3c120..748a8f2 100644
>> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> @@ -22,3 +22,4 @@ board. Currently known boards are:
>>  "lacie,d2-network"
>>  "marvell,rd-88f5182-nas"
>>  "maxtor,shared-storage-2"
>> +"netgear,wnr854t"
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 95c1923..63b9202 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -535,6 +535,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
>>  	orion5x-linkstation-lswtgl.dtb \
>>  	orion5x-lswsgl.dtb \
>>  	orion5x-maxtor-shared-storage-2.dtb \
>> +	orion5x-netgear-wnr854t.dtb \
>>  	orion5x-rd88f5182-nas.dtb
>>  dtb-$(CONFIG_ARCH_PRIMA2) += \
>>  	prima2-evb.dtb
>> diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>> new file mode 100644
>> index 0000000..a8e89d8
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>> @@ -0,0 +1,200 @@
>> +/*
>> + * Copyright (C) 2014 Jamie Lentin <jm@lentin.co.uk>
>
> It's 2016 now.
>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +#include "orion5x-mv88f5181.dtsi"
>> +
>> +/ {
>> +	model = "Netgear WNR854-t";
>> +	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
>> +			"marvell,orion5x";
>> +
>> +	memory {
>> +		reg = <0x00000000 0x2000000>; /* 32 MB */
>> +	};
>> +
>> +	chosen {
>> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
>> +		linux,stdout-path = &uart0;
>
> As kind of mentioned, drop the linux prefix here.
>
>> +	};
>> +
>> +	soc {
>> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
>> +			<MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
>> +			<MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
>> +	};
>> +
>> +	gpio-keys {
>> +		compatible = "gpio-keys";
>> +		pinctrl-0 = <&pmx_reset_switch>;
>> +		pinctrl-names = "default";
>> +
>> +		reset {
>> +			label = "Reset Button";
>> +			linux,code = <KEY_RESTART>;
>> +			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
>> +		};
>> +	};
>> +
>> +	gpio-leds {
>> +		compatible = "gpio-leds";
>> +		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
>> +		pinctrl-names = "default";
>> +
>> +		led at 0 {
>> +			label = "power:green";
>> +			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
>> +		};
>> +
>> +		led at 1 {
>> +			label = "power:blink";
>> +			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
>> +		};
>> +
>> +		led at 2 {
>> +			label = "wan:green";
>> +			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
>> +		};
>> +	};
>> +
>> +	dsa at 0 {
>> +		compatible = "marvell,dsa";
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		dsa,ethernet = <&ethport>;
>> +		dsa,mii-bus = <&mdio>;
>> +
>> +		switch at 0 {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
>> +
>> +			port at 0 {
>> +				reg = <0>;
>> +				label = "lan3";
>> +			};
>> +
>> +			port at 1 {
>> +				reg = <1>;
>> +				label = "lan4";
>> +			};
>> +
>> +			port at 2 {
>> +				reg = <2>;
>> +				label = "wan";
>> +			};
>> +
>> +			port at 3 {
>> +				reg = <3>;
>> +				label = "cpu";
>> +			};
>> +
>> +			port at 5 {
>> +				reg = <5>;
>> +				label = "lan1";
>> +			};
>> +
>> +			port at 7 {
>> +				reg = <7>;
>> +				label = "lan2";
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&devbus_bootcs {
>> +	status = "okay";
>> +
>> +	devbus,keep-config;
>> +
>> +	flash at 0 {
>> +		compatible = "cfi-flash";
>> +		reg = <0 0x800000>;
>> +		bank-width = <1>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +
>> +		partition at 0 {
>
> The new recommended style adds a level here with a partitions node and
> the type of partitioning.
>
>> +			label = "kernel";
>> +			reg = <0x0 0x100000>;
>> +		};
>> +
>> +		partition at 100000 {
>> +			label = "rootfs";
>> +			reg = <0x100000 0x660000>;
>> +		};
>> +
>> +		partition at 760000 {
>> +			label = "uboot_env";
>> +			reg = <0x760000 0x20000>;
>> +		};
>> +
>> +		partition at 780000 {
>> +			label = "uboot";
>> +			reg = <0x780000 0x80000>;
>> +			read-only;
>> +		};
>> +	};
>> +};
>> +
>> +&mdio {
>> +	status = "okay";
>> +};
>> +
>> +&eth {
>> +	status = "okay";
>> +	ethernet-port at 0 {
>> +		speed = <1000>;
>> +		duplex = <1>;
>> +	};
>> +};
>> +
>> +&pinctrl {
>> +	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
>> +	pinctrl-names = "default";
>> +
>> +	pmx_power_led: pmx-power-led {
>> +		marvell,pins = "mpp0";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_reset_switch: pmx-reset-switch {
>> +		marvell,pins = "mpp1";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_power_led_blink: pmx-power-led-blink {
>> +		marvell,pins = "mpp2";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_wan_led: pmx-wan-led {
>> +		marvell,pins = "mpp3";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_pci_gpios: pmx-pci-gpios {
>> +		marvell,pins = "mpp4";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_ge: pmx-ge {
>> +		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
>> +				"mpp16", "mpp17", "mpp18", "mpp19";
>> +		marvell,function = "ge";
>> +	};
>> +};
>> +
>> +&uart0 {
>> +	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
>> index a2af158..1fdb95d 100644
>> --- a/arch/arm/mach-orion5x/Kconfig
>> +++ b/arch/arm/mach-orion5x/Kconfig
>> @@ -151,6 +151,12 @@ config MACH_MSS2_DT
>>  	  Say 'Y' here if you want your kernel to support the
>>  	  Maxtor Shared Storage II platform.
>>
>> +config MACH_WNR854T_DT
>
> There should only be at most 1 kconfig entry for all orion5x DT based
> platforms.

Even though it needs arch/arm/mach-orion5x/board-wnr854t.c to init the 
PCI? orion5x currently has other board _DT options, I presumed for this 
reason.

>> +	bool "Netgear WNR854T (Flattened Device Tree)"
>> +	help
>> +	  Say 'Y' here if you want your kernel to support the
>> +	  Netgear WNR854T platform.
>> +
>>  config MACH_WNR854T
>>  	bool "Netgear WNR854T"
>>  	help
>

-- 
Jamie Lentin

Re: [PATCH v0 06/10] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On Sun, 17 Jul 2016, Rob Herring wrote:

> On Sat, Jul 16, 2016 at 03:29:04PM +0100, Jamie Lentin wrote:
>> This is a router based on the mv88f5181 chipset.
>>
>> http://www.netgear.com/support/product/WNR854T.aspx
>> http://wiki.openwrt.org/toh/netgear/wnr854t
>>
>> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
>> ---
>>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>>  arch/arm/boot/dts/Makefile                         |   1 +
>>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 200 +++++++++++++++++++++
>>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>>  arch/arm/mach-orion5x/Makefile                     |   1 +
>>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
>>  6 files changed, 287 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>>  create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
>>
>> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> index ff3c120..748a8f2 100644
>> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> @@ -22,3 +22,4 @@ board. Currently known boards are:
>>  "lacie,d2-network"
>>  "marvell,rd-88f5182-nas"
>>  "maxtor,shared-storage-2"
>> +"netgear,wnr854t"
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 95c1923..63b9202 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -535,6 +535,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
>>  	orion5x-linkstation-lswtgl.dtb \
>>  	orion5x-lswsgl.dtb \
>>  	orion5x-maxtor-shared-storage-2.dtb \
>> +	orion5x-netgear-wnr854t.dtb \
>>  	orion5x-rd88f5182-nas.dtb
>>  dtb-$(CONFIG_ARCH_PRIMA2) += \
>>  	prima2-evb.dtb
>> diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>> new file mode 100644
>> index 0000000..a8e89d8
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>> @@ -0,0 +1,200 @@
>> +/*
>> + * Copyright (C) 2014 Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
>
> It's 2016 now.
>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +#include "orion5x-mv88f5181.dtsi"
>> +
>> +/ {
>> +	model = "Netgear WNR854-t";
>> +	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
>> +			"marvell,orion5x";
>> +
>> +	memory {
>> +		reg = <0x00000000 0x2000000>; /* 32 MB */
>> +	};
>> +
>> +	chosen {
>> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
>> +		linux,stdout-path = &uart0;
>
> As kind of mentioned, drop the linux prefix here.
>
>> +	};
>> +
>> +	soc {
>> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
>> +			<MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
>> +			<MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
>> +	};
>> +
>> +	gpio-keys {
>> +		compatible = "gpio-keys";
>> +		pinctrl-0 = <&pmx_reset_switch>;
>> +		pinctrl-names = "default";
>> +
>> +		reset {
>> +			label = "Reset Button";
>> +			linux,code = <KEY_RESTART>;
>> +			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
>> +		};
>> +	};
>> +
>> +	gpio-leds {
>> +		compatible = "gpio-leds";
>> +		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
>> +		pinctrl-names = "default";
>> +
>> +		led@0 {
>> +			label = "power:green";
>> +			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
>> +		};
>> +
>> +		led@1 {
>> +			label = "power:blink";
>> +			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
>> +		};
>> +
>> +		led@2 {
>> +			label = "wan:green";
>> +			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
>> +		};
>> +	};
>> +
>> +	dsa@0 {
>> +		compatible = "marvell,dsa";
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		dsa,ethernet = <&ethport>;
>> +		dsa,mii-bus = <&mdio>;
>> +
>> +		switch@0 {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			reg = <0 0>;	/* MDIO address 0, switch 0 in tree */
>> +
>> +			port@0 {
>> +				reg = <0>;
>> +				label = "lan3";
>> +			};
>> +
>> +			port@1 {
>> +				reg = <1>;
>> +				label = "lan4";
>> +			};
>> +
>> +			port@2 {
>> +				reg = <2>;
>> +				label = "wan";
>> +			};
>> +
>> +			port@3 {
>> +				reg = <3>;
>> +				label = "cpu";
>> +			};
>> +
>> +			port@5 {
>> +				reg = <5>;
>> +				label = "lan1";
>> +			};
>> +
>> +			port@7 {
>> +				reg = <7>;
>> +				label = "lan2";
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&devbus_bootcs {
>> +	status = "okay";
>> +
>> +	devbus,keep-config;
>> +
>> +	flash@0 {
>> +		compatible = "cfi-flash";
>> +		reg = <0 0x800000>;
>> +		bank-width = <1>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +
>> +		partition@0 {
>
> The new recommended style adds a level here with a partitions node and
> the type of partitioning.
>
>> +			label = "kernel";
>> +			reg = <0x0 0x100000>;
>> +		};
>> +
>> +		partition@100000 {
>> +			label = "rootfs";
>> +			reg = <0x100000 0x660000>;
>> +		};
>> +
>> +		partition@760000 {
>> +			label = "uboot_env";
>> +			reg = <0x760000 0x20000>;
>> +		};
>> +
>> +		partition@780000 {
>> +			label = "uboot";
>> +			reg = <0x780000 0x80000>;
>> +			read-only;
>> +		};
>> +	};
>> +};
>> +
>> +&mdio {
>> +	status = "okay";
>> +};
>> +
>> +&eth {
>> +	status = "okay";
>> +	ethernet-port@0 {
>> +		speed = <1000>;
>> +		duplex = <1>;
>> +	};
>> +};
>> +
>> +&pinctrl {
>> +	pinctrl-0 = <&pmx_pci_gpios &pmx_ge>;
>> +	pinctrl-names = "default";
>> +
>> +	pmx_power_led: pmx-power-led {
>> +		marvell,pins = "mpp0";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_reset_switch: pmx-reset-switch {
>> +		marvell,pins = "mpp1";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_power_led_blink: pmx-power-led-blink {
>> +		marvell,pins = "mpp2";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_wan_led: pmx-wan-led {
>> +		marvell,pins = "mpp3";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_pci_gpios: pmx-pci-gpios {
>> +		marvell,pins = "mpp4";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_ge: pmx-ge {
>> +		marvell,pins = "mpp9", "mpp12",	"mpp13", "mpp14", "mpp15",
>> +				"mpp16", "mpp17", "mpp18", "mpp19";
>> +		marvell,function = "ge";
>> +	};
>> +};
>> +
>> +&uart0 {
>> +	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
>> index a2af158..1fdb95d 100644
>> --- a/arch/arm/mach-orion5x/Kconfig
>> +++ b/arch/arm/mach-orion5x/Kconfig
>> @@ -151,6 +151,12 @@ config MACH_MSS2_DT
>>  	  Say 'Y' here if you want your kernel to support the
>>  	  Maxtor Shared Storage II platform.
>>
>> +config MACH_WNR854T_DT
>
> There should only be at most 1 kconfig entry for all orion5x DT based
> platforms.

Even though it needs arch/arm/mach-orion5x/board-wnr854t.c to init the 
PCI? orion5x currently has other board _DT options, I presumed for this 
reason.

>> +	bool "Netgear WNR854T (Flattened Device Tree)"
>> +	help
>> +	  Say 'Y' here if you want your kernel to support the
>> +	  Netgear WNR854T platform.
>> +
>>  config MACH_WNR854T
>>  	bool "Netgear WNR854T"
>>  	help
>

-- 
Jamie Lentin
--
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[PATCH v0 07/10] arm: orion5x: Remove old non-DT-based WNR854T support

[Jamie Lentin]

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 arch/arm/mach-orion5x/Makefile        |   1 -
 arch/arm/mach-orion5x/wnr854t-setup.c | 185 ----------------------------------
 2 files changed, 186 deletions(-)
 delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c

diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 9dff2d3..a2c9ebc 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_MACH_WRT350N_V2)	+= wrt350n-v2-setup.o
 obj-$(CONFIG_MACH_TS78XX)	+= ts78xx-setup.o
 obj-$(CONFIG_MACH_MV2120)	+= mv2120-setup.o
 obj-$(CONFIG_MACH_NET2BIG)	+= net2big-setup.o
-obj-$(CONFIG_MACH_WNR854T)	+= wnr854t-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_GE)	+= rd88f5181l-ge-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_FXO)	+= rd88f5181l-fxo-setup.o
 obj-$(CONFIG_MACH_RD88F6183AP_GE)	+= rd88f6183ap-ge-setup.o
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
deleted file mode 100644
index 4e1e5c8..0000000
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * arch/arm/mach-orion5x/wnr854t-setup.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <net/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "orion5x.h"
-#include "common.h"
-#include "mpp.h"
-
-static unsigned int wnr854t_mpp_modes[] __initdata = {
-	MPP0_GPIO,		/* Power LED green (0=on) */
-	MPP1_GPIO,		/* Reset Button (0=off) */
-	MPP2_GPIO,		/* Power LED blink (0=off) */
-	MPP3_GPIO,		/* WAN Status LED amber (0=off) */
-	MPP4_GPIO,		/* PCI int */
-	MPP5_GPIO,		/* ??? */
-	MPP6_GPIO,		/* ??? */
-	MPP7_GPIO,		/* ??? */
-	MPP8_UNUSED,		/* ??? */
-	MPP9_GIGE,		/* GE_RXERR */
-	MPP10_UNUSED,		/* ??? */
-	MPP11_UNUSED,		/* ??? */
-	MPP12_GIGE,		/* GE_TXD[4] */
-	MPP13_GIGE,		/* GE_TXD[5] */
-	MPP14_GIGE,		/* GE_TXD[6] */
-	MPP15_GIGE,		/* GE_TXD[7] */
-	MPP16_GIGE,		/* GE_RXD[4] */
-	MPP17_GIGE,		/* GE_RXD[5] */
-	MPP18_GIGE,		/* GE_RXD[6] */
-	MPP19_GIGE,		/* GE_RXD[7] */
-	0,
-};
-
-/*
- * 8M NOR flash Device bus boot chip select
- */
-#define WNR854T_NOR_BOOT_BASE	0xf4000000
-#define WNR854T_NOR_BOOT_SIZE	SZ_8M
-
-static struct mtd_partition wnr854t_nor_flash_partitions[] = {
-	{
-		.name		= "kernel",
-		.offset		= 0x00000000,
-		.size		= 0x00100000,
-	}, {
-		.name		= "rootfs",
-		.offset		= 0x00100000,
-		.size		= 0x00660000,
-	}, {
-		.name		= "uboot",
-		.offset		= 0x00760000,
-		.size		= 0x00040000,
-	},
-};
-
-static struct physmap_flash_data wnr854t_nor_flash_data = {
-	.width		= 2,
-	.parts		= wnr854t_nor_flash_partitions,
-	.nr_parts	= ARRAY_SIZE(wnr854t_nor_flash_partitions),
-};
-
-static struct resource wnr854t_nor_flash_resource = {
-	.flags		= IORESOURCE_MEM,
-	.start		= WNR854T_NOR_BOOT_BASE,
-	.end		= WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device wnr854t_nor_flash = {
-	.name			= "physmap-flash",
-	.id			= 0,
-	.dev		= {
-		.platform_data	= &wnr854t_nor_flash_data,
-	},
-	.num_resources		= 1,
-	.resource		= &wnr854t_nor_flash_resource,
-};
-
-static struct mv643xx_eth_platform_data wnr854t_eth_data = {
-	.phy_addr	= MV643XX_ETH_PHY_NONE,
-	.speed		= SPEED_1000,
-	.duplex		= DUPLEX_FULL,
-};
-
-static struct dsa_chip_data wnr854t_switch_chip_data = {
-	.port_names[0] = "lan3",
-	.port_names[1] = "lan4",
-	.port_names[2] = "wan",
-	.port_names[3] = "cpu",
-	.port_names[5] = "lan1",
-	.port_names[7] = "lan2",
-};
-
-static struct dsa_platform_data wnr854t_switch_plat_data = {
-	.nr_chips	= 1,
-	.chip		= &wnr854t_switch_chip_data,
-};
-
-static void __init wnr854t_init(void)
-{
-	/*
-	 * Setup basic Orion functions. Need to be called early.
-	 */
-	orion5x_init();
-
-	orion5x_mpp_conf(wnr854t_mpp_modes);
-
-	/*
-	 * Configure peripherals.
-	 */
-	orion5x_eth_init(&wnr854t_eth_data);
-	orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
-	orion5x_uart0_init();
-
-	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
-				    ORION_MBUS_DEVBUS_BOOT_ATTR,
-				    WNR854T_NOR_BOOT_BASE,
-				    WNR854T_NOR_BOOT_SIZE);
-	platform_device_register(&wnr854t_nor_flash);
-}
-
-static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
-	u8 pin)
-{
-	int irq;
-
-	/*
-	 * Check for devices with hard-wired IRQs.
-	 */
-	irq = orion5x_pci_map_irq(dev, slot, pin);
-	if (irq != -1)
-		return irq;
-
-	/*
-	 * Mini-PCI slot.
-	 */
-	if (slot == 7)
-		return gpio_to_irq(4);
-
-	return -1;
-}
-
-static struct hw_pci wnr854t_pci __initdata = {
-	.nr_controllers	= 2,
-	.setup		= orion5x_pci_sys_setup,
-	.scan		= orion5x_pci_sys_scan_bus,
-	.map_irq	= wnr854t_pci_map_irq,
-};
-
-static int __init wnr854t_pci_init(void)
-{
-	if (machine_is_wnr854t())
-		pci_common_init(&wnr854t_pci);
-
-	return 0;
-}
-subsys_initcall(wnr854t_pci_init);
-
-MACHINE_START(WNR854T, "Netgear WNR854T")
-	/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-	.atag_offset	= 0x100,
-	.nr_irqs	= ORION5X_NR_IRQS,
-	.init_machine	= wnr854t_init,
-	.map_io		= orion5x_map_io,
-	.init_early	= orion5x_init_early,
-	.init_irq	= orion5x_init_irq,
-	.init_time	= orion5x_timer_init,
-	.fixup		= tag_fixup_mem32,
-	.restart	= orion5x_restart,
-MACHINE_END
-- 
2.8.1

[PATCH v0 07/10] arm: orion5x: Remove old non-DT-based WNR854T support

[Jamie Lentin]

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 arch/arm/mach-orion5x/Makefile        |   1 -
 arch/arm/mach-orion5x/wnr854t-setup.c | 185 ----------------------------------
 2 files changed, 186 deletions(-)
 delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c

diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 9dff2d3..a2c9ebc 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_MACH_WRT350N_V2)	+= wrt350n-v2-setup.o
 obj-$(CONFIG_MACH_TS78XX)	+= ts78xx-setup.o
 obj-$(CONFIG_MACH_MV2120)	+= mv2120-setup.o
 obj-$(CONFIG_MACH_NET2BIG)	+= net2big-setup.o
-obj-$(CONFIG_MACH_WNR854T)	+= wnr854t-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_GE)	+= rd88f5181l-ge-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_FXO)	+= rd88f5181l-fxo-setup.o
 obj-$(CONFIG_MACH_RD88F6183AP_GE)	+= rd88f6183ap-ge-setup.o
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
deleted file mode 100644
index 4e1e5c8..0000000
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * arch/arm/mach-orion5x/wnr854t-setup.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <net/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "orion5x.h"
-#include "common.h"
-#include "mpp.h"
-
-static unsigned int wnr854t_mpp_modes[] __initdata = {
-	MPP0_GPIO,		/* Power LED green (0=on) */
-	MPP1_GPIO,		/* Reset Button (0=off) */
-	MPP2_GPIO,		/* Power LED blink (0=off) */
-	MPP3_GPIO,		/* WAN Status LED amber (0=off) */
-	MPP4_GPIO,		/* PCI int */
-	MPP5_GPIO,		/* ??? */
-	MPP6_GPIO,		/* ??? */
-	MPP7_GPIO,		/* ??? */
-	MPP8_UNUSED,		/* ??? */
-	MPP9_GIGE,		/* GE_RXERR */
-	MPP10_UNUSED,		/* ??? */
-	MPP11_UNUSED,		/* ??? */
-	MPP12_GIGE,		/* GE_TXD[4] */
-	MPP13_GIGE,		/* GE_TXD[5] */
-	MPP14_GIGE,		/* GE_TXD[6] */
-	MPP15_GIGE,		/* GE_TXD[7] */
-	MPP16_GIGE,		/* GE_RXD[4] */
-	MPP17_GIGE,		/* GE_RXD[5] */
-	MPP18_GIGE,		/* GE_RXD[6] */
-	MPP19_GIGE,		/* GE_RXD[7] */
-	0,
-};
-
-/*
- * 8M NOR flash Device bus boot chip select
- */
-#define WNR854T_NOR_BOOT_BASE	0xf4000000
-#define WNR854T_NOR_BOOT_SIZE	SZ_8M
-
-static struct mtd_partition wnr854t_nor_flash_partitions[] = {
-	{
-		.name		= "kernel",
-		.offset		= 0x00000000,
-		.size		= 0x00100000,
-	}, {
-		.name		= "rootfs",
-		.offset		= 0x00100000,
-		.size		= 0x00660000,
-	}, {
-		.name		= "uboot",
-		.offset		= 0x00760000,
-		.size		= 0x00040000,
-	},
-};
-
-static struct physmap_flash_data wnr854t_nor_flash_data = {
-	.width		= 2,
-	.parts		= wnr854t_nor_flash_partitions,
-	.nr_parts	= ARRAY_SIZE(wnr854t_nor_flash_partitions),
-};
-
-static struct resource wnr854t_nor_flash_resource = {
-	.flags		= IORESOURCE_MEM,
-	.start		= WNR854T_NOR_BOOT_BASE,
-	.end		= WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device wnr854t_nor_flash = {
-	.name			= "physmap-flash",
-	.id			= 0,
-	.dev		= {
-		.platform_data	= &wnr854t_nor_flash_data,
-	},
-	.num_resources		= 1,
-	.resource		= &wnr854t_nor_flash_resource,
-};
-
-static struct mv643xx_eth_platform_data wnr854t_eth_data = {
-	.phy_addr	= MV643XX_ETH_PHY_NONE,
-	.speed		= SPEED_1000,
-	.duplex		= DUPLEX_FULL,
-};
-
-static struct dsa_chip_data wnr854t_switch_chip_data = {
-	.port_names[0] = "lan3",
-	.port_names[1] = "lan4",
-	.port_names[2] = "wan",
-	.port_names[3] = "cpu",
-	.port_names[5] = "lan1",
-	.port_names[7] = "lan2",
-};
-
-static struct dsa_platform_data wnr854t_switch_plat_data = {
-	.nr_chips	= 1,
-	.chip		= &wnr854t_switch_chip_data,
-};
-
-static void __init wnr854t_init(void)
-{
-	/*
-	 * Setup basic Orion functions. Need to be called early.
-	 */
-	orion5x_init();
-
-	orion5x_mpp_conf(wnr854t_mpp_modes);
-
-	/*
-	 * Configure peripherals.
-	 */
-	orion5x_eth_init(&wnr854t_eth_data);
-	orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
-	orion5x_uart0_init();
-
-	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
-				    ORION_MBUS_DEVBUS_BOOT_ATTR,
-				    WNR854T_NOR_BOOT_BASE,
-				    WNR854T_NOR_BOOT_SIZE);
-	platform_device_register(&wnr854t_nor_flash);
-}
-
-static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
-	u8 pin)
-{
-	int irq;
-
-	/*
-	 * Check for devices with hard-wired IRQs.
-	 */
-	irq = orion5x_pci_map_irq(dev, slot, pin);
-	if (irq != -1)
-		return irq;
-
-	/*
-	 * Mini-PCI slot.
-	 */
-	if (slot == 7)
-		return gpio_to_irq(4);
-
-	return -1;
-}
-
-static struct hw_pci wnr854t_pci __initdata = {
-	.nr_controllers	= 2,
-	.setup		= orion5x_pci_sys_setup,
-	.scan		= orion5x_pci_sys_scan_bus,
-	.map_irq	= wnr854t_pci_map_irq,
-};
-
-static int __init wnr854t_pci_init(void)
-{
-	if (machine_is_wnr854t())
-		pci_common_init(&wnr854t_pci);
-
-	return 0;
-}
-subsys_initcall(wnr854t_pci_init);
-
-MACHINE_START(WNR854T, "Netgear WNR854T")
-	/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-	.atag_offset	= 0x100,
-	.nr_irqs	= ORION5X_NR_IRQS,
-	.init_machine	= wnr854t_init,
-	.map_io		= orion5x_map_io,
-	.init_early	= orion5x_init_early,
-	.init_irq	= orion5x_init_irq,
-	.init_time	= orion5x_timer_init,
-	.fixup		= tag_fixup_mem32,
-	.restart	= orion5x_restart,
-MACHINE_END
-- 
2.8.1

[PATCH v0 07/10] arm: orion5x: Remove old non-DT-based WNR854T support

[Jamie Lentin]

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 arch/arm/mach-orion5x/Makefile        |   1 -
 arch/arm/mach-orion5x/wnr854t-setup.c | 185 ----------------------------------
 2 files changed, 186 deletions(-)
 delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c

diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 9dff2d3..a2c9ebc 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_MACH_WRT350N_V2)	+= wrt350n-v2-setup.o
 obj-$(CONFIG_MACH_TS78XX)	+= ts78xx-setup.o
 obj-$(CONFIG_MACH_MV2120)	+= mv2120-setup.o
 obj-$(CONFIG_MACH_NET2BIG)	+= net2big-setup.o
-obj-$(CONFIG_MACH_WNR854T)	+= wnr854t-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_GE)	+= rd88f5181l-ge-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_FXO)	+= rd88f5181l-fxo-setup.o
 obj-$(CONFIG_MACH_RD88F6183AP_GE)	+= rd88f6183ap-ge-setup.o
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
deleted file mode 100644
index 4e1e5c8..0000000
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * arch/arm/mach-orion5x/wnr854t-setup.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <net/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "orion5x.h"
-#include "common.h"
-#include "mpp.h"
-
-static unsigned int wnr854t_mpp_modes[] __initdata = {
-	MPP0_GPIO,		/* Power LED green (0=on) */
-	MPP1_GPIO,		/* Reset Button (0=off) */
-	MPP2_GPIO,		/* Power LED blink (0=off) */
-	MPP3_GPIO,		/* WAN Status LED amber (0=off) */
-	MPP4_GPIO,		/* PCI int */
-	MPP5_GPIO,		/* ??? */
-	MPP6_GPIO,		/* ??? */
-	MPP7_GPIO,		/* ??? */
-	MPP8_UNUSED,		/* ??? */
-	MPP9_GIGE,		/* GE_RXERR */
-	MPP10_UNUSED,		/* ??? */
-	MPP11_UNUSED,		/* ??? */
-	MPP12_GIGE,		/* GE_TXD[4] */
-	MPP13_GIGE,		/* GE_TXD[5] */
-	MPP14_GIGE,		/* GE_TXD[6] */
-	MPP15_GIGE,		/* GE_TXD[7] */
-	MPP16_GIGE,		/* GE_RXD[4] */
-	MPP17_GIGE,		/* GE_RXD[5] */
-	MPP18_GIGE,		/* GE_RXD[6] */
-	MPP19_GIGE,		/* GE_RXD[7] */
-	0,
-};
-
-/*
- * 8M NOR flash Device bus boot chip select
- */
-#define WNR854T_NOR_BOOT_BASE	0xf4000000
-#define WNR854T_NOR_BOOT_SIZE	SZ_8M
-
-static struct mtd_partition wnr854t_nor_flash_partitions[] = {
-	{
-		.name		= "kernel",
-		.offset		= 0x00000000,
-		.size		= 0x00100000,
-	}, {
-		.name		= "rootfs",
-		.offset		= 0x00100000,
-		.size		= 0x00660000,
-	}, {
-		.name		= "uboot",
-		.offset		= 0x00760000,
-		.size		= 0x00040000,
-	},
-};
-
-static struct physmap_flash_data wnr854t_nor_flash_data = {
-	.width		= 2,
-	.parts		= wnr854t_nor_flash_partitions,
-	.nr_parts	= ARRAY_SIZE(wnr854t_nor_flash_partitions),
-};
-
-static struct resource wnr854t_nor_flash_resource = {
-	.flags		= IORESOURCE_MEM,
-	.start		= WNR854T_NOR_BOOT_BASE,
-	.end		= WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device wnr854t_nor_flash = {
-	.name			= "physmap-flash",
-	.id			= 0,
-	.dev		= {
-		.platform_data	= &wnr854t_nor_flash_data,
-	},
-	.num_resources		= 1,
-	.resource		= &wnr854t_nor_flash_resource,
-};
-
-static struct mv643xx_eth_platform_data wnr854t_eth_data = {
-	.phy_addr	= MV643XX_ETH_PHY_NONE,
-	.speed		= SPEED_1000,
-	.duplex		= DUPLEX_FULL,
-};
-
-static struct dsa_chip_data wnr854t_switch_chip_data = {
-	.port_names[0] = "lan3",
-	.port_names[1] = "lan4",
-	.port_names[2] = "wan",
-	.port_names[3] = "cpu",
-	.port_names[5] = "lan1",
-	.port_names[7] = "lan2",
-};
-
-static struct dsa_platform_data wnr854t_switch_plat_data = {
-	.nr_chips	= 1,
-	.chip		= &wnr854t_switch_chip_data,
-};
-
-static void __init wnr854t_init(void)
-{
-	/*
-	 * Setup basic Orion functions. Need to be called early.
-	 */
-	orion5x_init();
-
-	orion5x_mpp_conf(wnr854t_mpp_modes);
-
-	/*
-	 * Configure peripherals.
-	 */
-	orion5x_eth_init(&wnr854t_eth_data);
-	orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
-	orion5x_uart0_init();
-
-	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
-				    ORION_MBUS_DEVBUS_BOOT_ATTR,
-				    WNR854T_NOR_BOOT_BASE,
-				    WNR854T_NOR_BOOT_SIZE);
-	platform_device_register(&wnr854t_nor_flash);
-}
-
-static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
-	u8 pin)
-{
-	int irq;
-
-	/*
-	 * Check for devices with hard-wired IRQs.
-	 */
-	irq = orion5x_pci_map_irq(dev, slot, pin);
-	if (irq != -1)
-		return irq;
-
-	/*
-	 * Mini-PCI slot.
-	 */
-	if (slot == 7)
-		return gpio_to_irq(4);
-
-	return -1;
-}
-
-static struct hw_pci wnr854t_pci __initdata = {
-	.nr_controllers	= 2,
-	.setup		= orion5x_pci_sys_setup,
-	.scan		= orion5x_pci_sys_scan_bus,
-	.map_irq	= wnr854t_pci_map_irq,
-};
-
-static int __init wnr854t_pci_init(void)
-{
-	if (machine_is_wnr854t())
-		pci_common_init(&wnr854t_pci);
-
-	return 0;
-}
-subsys_initcall(wnr854t_pci_init);
-
-MACHINE_START(WNR854T, "Netgear WNR854T")
-	/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-	.atag_offset	= 0x100,
-	.nr_irqs	= ORION5X_NR_IRQS,
-	.init_machine	= wnr854t_init,
-	.map_io		= orion5x_map_io,
-	.init_early	= orion5x_init_early,
-	.init_irq	= orion5x_init_irq,
-	.init_time	= orion5x_timer_init,
-	.fixup		= tag_fixup_mem32,
-	.restart	= orion5x_restart,
-MACHINE_END
-- 
2.8.1

Re: [PATCH v0 07/10] arm: orion5x: Remove old non-DT-based WNR854T support

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:05PM +0100, Jamie Lentin wrote:

Again, you need a commit log. It could be something like:

The setup file for the wnr854t has bit rotted to such an extent it no
longer works. Replace it with a working device tree description.

       Andrew

[PATCH v0 07/10] arm: orion5x: Remove old non-DT-based WNR854T support

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:05PM +0100, Jamie Lentin wrote:

Again, you need a commit log. It could be something like:

The setup file for the wnr854t has bit rotted to such an extent it no
longer works. Replace it with a working device tree description.

       Andrew

[PATCH v0 08/10] net: phy: Try looking for a phy-handle property to find the OF node

[Jamie Lentin]

If PHY is registered via. a DSA switch, the MDIO bus the phy is on does
not exist in devicetree, but there may be a reference to the PHY node
on the physical MDIO bus to use.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 drivers/net/phy/marvell.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 280e879..c2ca347 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -302,14 +302,24 @@ static int marvell_config_aneg(struct phy_device *phydev)
  */
 static int marvell_of_reg_init(struct phy_device *phydev)
 {
-	const __be32 *paddr;
+	const __be32 *paddr = NULL;
 	int len, i, saved_page, current_page, page_changed, ret;
+	struct device_node *phy_dn;
+
+	if (phydev->mdio.dev.of_node)
+		paddr = of_get_property(phydev->mdio.dev.of_node,
+					"marvell,reg-init", &len);
+	else if (phydev->attached_dev->dev.of_node) {
+		/* A DSA slave-mii-bus has no OF node, but the PHY might */
+		phy_dn = of_parse_phandle(phydev->attached_dev->dev.of_node,
+					  "phy-handle", 0);
+		if (phy_dn) {
+			paddr = of_get_property(phy_dn,
+						"marvell,reg-init", &len);
+			of_node_put(phy_dn);
+		}
+	}
 
-	if (!phydev->mdio.dev.of_node)
-		return 0;
-
-	paddr = of_get_property(phydev->mdio.dev.of_node,
-				"marvell,reg-init", &len);
 	if (!paddr || len < (4 * sizeof(*paddr)))
 		return 0;
 
-- 
2.8.1

[PATCH v0 08/10] net: phy: Try looking for a phy-handle property to find the OF node

[Jamie Lentin]

If PHY is registered via. a DSA switch, the MDIO bus the phy is on does
not exist in devicetree, but there may be a reference to the PHY node
on the physical MDIO bus to use.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 drivers/net/phy/marvell.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 280e879..c2ca347 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -302,14 +302,24 @@ static int marvell_config_aneg(struct phy_device *phydev)
  */
 static int marvell_of_reg_init(struct phy_device *phydev)
 {
-	const __be32 *paddr;
+	const __be32 *paddr = NULL;
 	int len, i, saved_page, current_page, page_changed, ret;
+	struct device_node *phy_dn;
+
+	if (phydev->mdio.dev.of_node)
+		paddr = of_get_property(phydev->mdio.dev.of_node,
+					"marvell,reg-init", &len);
+	else if (phydev->attached_dev->dev.of_node) {
+		/* A DSA slave-mii-bus has no OF node, but the PHY might */
+		phy_dn = of_parse_phandle(phydev->attached_dev->dev.of_node,
+					  "phy-handle", 0);
+		if (phy_dn) {
+			paddr = of_get_property(phy_dn,
+						"marvell,reg-init", &len);
+			of_node_put(phy_dn);
+		}
+	}
 
-	if (!phydev->mdio.dev.of_node)
-		return 0;
-
-	paddr = of_get_property(phydev->mdio.dev.of_node,
-				"marvell,reg-init", &len);
 	if (!paddr || len < (4 * sizeof(*paddr)))
 		return 0;
 
-- 
2.8.1

[PATCH v0 08/10] net: phy: Try looking for a phy-handle property to find the OF node

[Jamie Lentin]

If PHY is registered via. a DSA switch, the MDIO bus the phy is on does
not exist in devicetree, but there may be a reference to the PHY node
on the physical MDIO bus to use.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 drivers/net/phy/marvell.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 280e879..c2ca347 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -302,14 +302,24 @@ static int marvell_config_aneg(struct phy_device *phydev)
  */
 static int marvell_of_reg_init(struct phy_device *phydev)
 {
-	const __be32 *paddr;
+	const __be32 *paddr = NULL;
 	int len, i, saved_page, current_page, page_changed, ret;
+	struct device_node *phy_dn;
+
+	if (phydev->mdio.dev.of_node)
+		paddr = of_get_property(phydev->mdio.dev.of_node,
+					"marvell,reg-init", &len);
+	else if (phydev->attached_dev->dev.of_node) {
+		/* A DSA slave-mii-bus has no OF node, but the PHY might */
+		phy_dn = of_parse_phandle(phydev->attached_dev->dev.of_node,
+					  "phy-handle", 0);
+		if (phy_dn) {
+			paddr = of_get_property(phy_dn,
+						"marvell,reg-init", &len);
+			of_node_put(phy_dn);
+		}
+	}
 
-	if (!phydev->mdio.dev.of_node)
-		return 0;
-
-	paddr = of_get_property(phydev->mdio.dev.of_node,
-				"marvell,reg-init", &len);
 	if (!paddr || len < (4 * sizeof(*paddr)))
 		return 0;
 
-- 
2.8.1

Re: [PATCH v0 08/10] net: phy: Try looking for a phy-handle property to find the OF node

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:06PM +0100, Jamie Lentin wrote:
> If PHY is registered via. a DSA switch, the MDIO bus the phy is on does
> not exist in devicetree, but there may be a reference to the PHY node
> on the physical MDIO bus to use.

O.K, i see what you are trying to achieve, it makes sense, but sorry,
NACK.

There is however a nice solution :-)

If you look in net-next, you will notice a big change to DSA. There is
a new binding, and the mv88e6xxx driver now exports the switch
internal MDIO bus just like any other MDIO bus. So you can have a phy
on the MDIO bus, and that phy can have "marvell,reg-init" properties.

     Andrew

> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  drivers/net/phy/marvell.c | 22 ++++++++++++++++------
>  1 file changed, 16 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
> index 280e879..c2ca347 100644
> --- a/drivers/net/phy/marvell.c
> +++ b/drivers/net/phy/marvell.c
> @@ -302,14 +302,24 @@ static int marvell_config_aneg(struct phy_device *phydev)
>   */
>  static int marvell_of_reg_init(struct phy_device *phydev)
>  {
> -	const __be32 *paddr;
> +	const __be32 *paddr = NULL;
>  	int len, i, saved_page, current_page, page_changed, ret;
> +	struct device_node *phy_dn;
> +
> +	if (phydev->mdio.dev.of_node)
> +		paddr = of_get_property(phydev->mdio.dev.of_node,
> +					"marvell,reg-init", &len);
> +	else if (phydev->attached_dev->dev.of_node) {
> +		/* A DSA slave-mii-bus has no OF node, but the PHY might */
> +		phy_dn = of_parse_phandle(phydev->attached_dev->dev.of_node,
> +					  "phy-handle", 0);
> +		if (phy_dn) {
> +			paddr = of_get_property(phy_dn,
> +						"marvell,reg-init", &len);
> +			of_node_put(phy_dn);
> +		}
> +	}
>  
> -	if (!phydev->mdio.dev.of_node)
> -		return 0;
> -
> -	paddr = of_get_property(phydev->mdio.dev.of_node,
> -				"marvell,reg-init", &len);
>  	if (!paddr || len < (4 * sizeof(*paddr)))
>  		return 0;
>  
> -- 
> 2.8.1
> 

[PATCH v0 08/10] net: phy: Try looking for a phy-handle property to find the OF node

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:06PM +0100, Jamie Lentin wrote:
> If PHY is registered via. a DSA switch, the MDIO bus the phy is on does
> not exist in devicetree, but there may be a reference to the PHY node
> on the physical MDIO bus to use.

O.K, i see what you are trying to achieve, it makes sense, but sorry,
NACK.

There is however a nice solution :-)

If you look in net-next, you will notice a big change to DSA. There is
a new binding, and the mv88e6xxx driver now exports the switch
internal MDIO bus just like any other MDIO bus. So you can have a phy
on the MDIO bus, and that phy can have "marvell,reg-init" properties.

     Andrew

> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  drivers/net/phy/marvell.c | 22 ++++++++++++++++------
>  1 file changed, 16 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
> index 280e879..c2ca347 100644
> --- a/drivers/net/phy/marvell.c
> +++ b/drivers/net/phy/marvell.c
> @@ -302,14 +302,24 @@ static int marvell_config_aneg(struct phy_device *phydev)
>   */
>  static int marvell_of_reg_init(struct phy_device *phydev)
>  {
> -	const __be32 *paddr;
> +	const __be32 *paddr = NULL;
>  	int len, i, saved_page, current_page, page_changed, ret;
> +	struct device_node *phy_dn;
> +
> +	if (phydev->mdio.dev.of_node)
> +		paddr = of_get_property(phydev->mdio.dev.of_node,
> +					"marvell,reg-init", &len);
> +	else if (phydev->attached_dev->dev.of_node) {
> +		/* A DSA slave-mii-bus has no OF node, but the PHY might */
> +		phy_dn = of_parse_phandle(phydev->attached_dev->dev.of_node,
> +					  "phy-handle", 0);
> +		if (phy_dn) {
> +			paddr = of_get_property(phy_dn,
> +						"marvell,reg-init", &len);
> +			of_node_put(phy_dn);
> +		}
> +	}
>  
> -	if (!phydev->mdio.dev.of_node)
> -		return 0;
> -
> -	paddr = of_get_property(phydev->mdio.dev.of_node,
> -				"marvell,reg-init", &len);
>  	if (!paddr || len < (4 * sizeof(*paddr)))
>  		return 0;
>  
> -- 
> 2.8.1
> 

[PATCH v0 09/10] net: phy: Re-attempt custom DT configuration after configuration

[Jamie Lentin]

marvell,reg-init is generally used to apply a custom LED configuration
on boot. However this is then blatted in m88e1121_config_aneg when the
interface is brought up. Re-apply any custom configuration afterwards,
to keep custom LED configuration.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 drivers/net/phy/marvell.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index c2ca347..b55e4e0 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -424,6 +424,10 @@ static int m88e1121_config_aneg(struct phy_device *phydev)
 	phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 
 	err = genphy_config_aneg(phydev);
+	if (err < 0)
+		return err;
+
+	err = marvell_of_reg_init(phydev);
 
 	return err;
 }
-- 
2.8.1

[PATCH v0 09/10] net: phy: Re-attempt custom DT configuration after configuration

[Jamie Lentin]

marvell,reg-init is generally used to apply a custom LED configuration
on boot. However this is then blatted in m88e1121_config_aneg when the
interface is brought up. Re-apply any custom configuration afterwards,
to keep custom LED configuration.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 drivers/net/phy/marvell.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index c2ca347..b55e4e0 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -424,6 +424,10 @@ static int m88e1121_config_aneg(struct phy_device *phydev)
 	phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 
 	err = genphy_config_aneg(phydev);
+	if (err < 0)
+		return err;
+
+	err = marvell_of_reg_init(phydev);
 
 	return err;
 }
-- 
2.8.1

[PATCH v0 09/10] net: phy: Re-attempt custom DT configuration after configuration

[Jamie Lentin]

marvell,reg-init is generally used to apply a custom LED configuration
on boot. However this is then blatted in m88e1121_config_aneg when the
interface is brought up. Re-apply any custom configuration afterwards,
to keep custom LED configuration.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 drivers/net/phy/marvell.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index c2ca347..b55e4e0 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -424,6 +424,10 @@ static int m88e1121_config_aneg(struct phy_device *phydev)
 	phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 
 	err = genphy_config_aneg(phydev);
+	if (err < 0)
+		return err;
+
+	err = marvell_of_reg_init(phydev);
 
 	return err;
 }
-- 
2.8.1

Re: [PATCH v0 09/10] net: phy: Re-attempt custom DT configuration after configuration

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:07PM +0100, Jamie Lentin wrote:
> marvell,reg-init is generally used to apply a custom LED configuration
> on boot. However this is then blatted in m88e1121_config_aneg when the
> interface is brought up. Re-apply any custom configuration afterwards,
> to keep custom LED configuration.

This has been fixed in net-next.

     Andrew

[PATCH v0 09/10] net: phy: Re-attempt custom DT configuration after configuration

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:07PM +0100, Jamie Lentin wrote:
> marvell,reg-init is generally used to apply a custom LED configuration
> on boot. However this is then blatted in m88e1121_config_aneg when the
> interface is brought up. Re-apply any custom configuration afterwards,
> to keep custom LED configuration.

This has been fixed in net-next.

     Andrew

Re: [PATCH v0 09/10] net: phy: Re-attempt custom DT configuration after configuration

[Andrew Lunn]

On Sat, Jul 16, 2016 at 03:29:07PM +0100, Jamie Lentin wrote:
> marvell,reg-init is generally used to apply a custom LED configuration
> on boot. However this is then blatted in m88e1121_config_aneg when the
> interface is brought up. Re-apply any custom configuration afterwards,
> to keep custom LED configuration.

This has been fixed in net-next.

     Andrew
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[PATCH v0 10/10] arm: orion5x: Configure Netgear WNR854T network port LEDs

[Jamie Lentin]

The default bootloader leaves the LEDs orange, and the 88E1121R driver
applies it's own inappropriate configuration. Configure as per manual,
i.e. orange = 100 / green = 1000 / blink = activity

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 45 +++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
index a8e89d8..635b396 100644
--- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -81,16 +81,19 @@
 			port@0 {
 				reg = <0>;
 				label = "lan3";
+				phy-handle = <&lan3phy>;
 			};
 
 			port@1 {
 				reg = <1>;
 				label = "lan4";
+				phy-handle = <&lan4phy>;
 			};
 
 			port@2 {
 				reg = <2>;
 				label = "wan";
+				phy-handle = <&wanphy>;
 			};
 
 			port@3 {
@@ -101,11 +104,13 @@
 			port@5 {
 				reg = <5>;
 				label = "lan1";
+				phy-handle = <&lan1phy>;
 			};
 
 			port@7 {
 				reg = <7>;
 				label = "lan2";
+				phy-handle = <&lan2phy>;
 			};
 		};
 	};
@@ -148,6 +153,46 @@
 
 &mdio {
 	status = "okay";
+
+	lan3phy: ethernet-phy@0 {
+		/* Marvell 88E1121R (port 1) */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
+
+	lan4phy: ethernet-phy@1 {
+		/* Marvell 88E1121R (port 2) */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
+
+	wanphy: ethernet-phy@2 {
+		/* Marvell 88E1121R (port 1) */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <2>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
+
+	lan1phy: ethernet-phy@5 {
+		/* Marvell 88E1112 */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <5>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
+
+	lan2phy: ethernet-phy@7 {
+		/* Marvell 88E1112 */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <7>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
 };
 
 &eth {
-- 
2.8.1

[PATCH v0 10/10] arm: orion5x: Configure Netgear WNR854T network port LEDs

[Jamie Lentin]

The default bootloader leaves the LEDs orange, and the 88E1121R driver
applies it's own inappropriate configuration. Configure as per manual,
i.e. orange = 100 / green = 1000 / blink = activity

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 45 +++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
index a8e89d8..635b396 100644
--- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -81,16 +81,19 @@
 			port at 0 {
 				reg = <0>;
 				label = "lan3";
+				phy-handle = <&lan3phy>;
 			};
 
 			port at 1 {
 				reg = <1>;
 				label = "lan4";
+				phy-handle = <&lan4phy>;
 			};
 
 			port at 2 {
 				reg = <2>;
 				label = "wan";
+				phy-handle = <&wanphy>;
 			};
 
 			port at 3 {
@@ -101,11 +104,13 @@
 			port at 5 {
 				reg = <5>;
 				label = "lan1";
+				phy-handle = <&lan1phy>;
 			};
 
 			port at 7 {
 				reg = <7>;
 				label = "lan2";
+				phy-handle = <&lan2phy>;
 			};
 		};
 	};
@@ -148,6 +153,46 @@
 
 &mdio {
 	status = "okay";
+
+	lan3phy: ethernet-phy at 0 {
+		/* Marvell 88E1121R (port 1) */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
+
+	lan4phy: ethernet-phy at 1 {
+		/* Marvell 88E1121R (port 2) */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
+
+	wanphy: ethernet-phy at 2 {
+		/* Marvell 88E1121R (port 1) */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <2>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
+
+	lan1phy: ethernet-phy at 5 {
+		/* Marvell 88E1112 */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <5>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
+
+	lan2phy: ethernet-phy at 7 {
+		/* Marvell 88E1112 */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <7>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
 };
 
 &eth {
-- 
2.8.1

[PATCH v0 10/10] arm: orion5x: Configure Netgear WNR854T network port LEDs

[Jamie Lentin]

The default bootloader leaves the LEDs orange, and the 88E1121R driver
applies it's own inappropriate configuration. Configure as per manual,
i.e. orange = 100 / green = 1000 / blink = activity

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 45 +++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
index a8e89d8..635b396 100644
--- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -81,16 +81,19 @@
 			port@0 {
 				reg = <0>;
 				label = "lan3";
+				phy-handle = <&lan3phy>;
 			};
 
 			port@1 {
 				reg = <1>;
 				label = "lan4";
+				phy-handle = <&lan4phy>;
 			};
 
 			port@2 {
 				reg = <2>;
 				label = "wan";
+				phy-handle = <&wanphy>;
 			};
 
 			port@3 {
@@ -101,11 +104,13 @@
 			port@5 {
 				reg = <5>;
 				label = "lan1";
+				phy-handle = <&lan1phy>;
 			};
 
 			port@7 {
 				reg = <7>;
 				label = "lan2";
+				phy-handle = <&lan2phy>;
 			};
 		};
 	};
@@ -148,6 +153,46 @@
 
 &mdio {
 	status = "okay";
+
+	lan3phy: ethernet-phy@0 {
+		/* Marvell 88E1121R (port 1) */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
+
+	lan4phy: ethernet-phy@1 {
+		/* Marvell 88E1121R (port 2) */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
+
+	wanphy: ethernet-phy@2 {
+		/* Marvell 88E1121R (port 1) */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <2>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
+
+	lan1phy: ethernet-phy@5 {
+		/* Marvell 88E1112 */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <5>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
+
+	lan2phy: ethernet-phy@7 {
+		/* Marvell 88E1112 */
+		compatible = "ethernet-phy-id0141.0cb0",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <7>;
+		marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+	};
 };
 
 &eth {
-- 
2.8.1

Re: [PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Andrew Lunn]

> There's one major flaw; unicast traffic is never received on any port.
> Broadcast traffic is received however, and on the correct port. Thus
> an external machine can make an ARP request and get a response, for
> example. With a manually-entered ARP entry, the router can send pings
> out to a remote machine which responds, and the response is lost in the
> DSA switch. "ethtool -S" reports pings received on "in_unicast" but
> nothing makes it through the switch. This thread[0] seems very similar.
> I've run out of ideas here and can't find any switch datasheets to give
> me pointers so any suggestions greatly appreciated.

Hi Jamie

So it is 6131? So part of the 6185 family. 

I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your
configuration. Try swapping to EDSA. I even removed support for
TAG_DSA in one of the recent patches.

Please also can you get https://github.com/vivien/linux.git commit
323321875671dfe95b6b91ce051a74d415c7158c which will give you some
extra debug files /sys/kernel/debug/mv88e6xxx. 

The reg, stats, and atu would be interesting.

    Andrew

[PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Andrew Lunn]

> There's one major flaw; unicast traffic is never received on any port.
> Broadcast traffic is received however, and on the correct port. Thus
> an external machine can make an ARP request and get a response, for
> example. With a manually-entered ARP entry, the router can send pings
> out to a remote machine which responds, and the response is lost in the
> DSA switch. "ethtool -S" reports pings received on "in_unicast" but
> nothing makes it through the switch. This thread[0] seems very similar.
> I've run out of ideas here and can't find any switch datasheets to give
> me pointers so any suggestions greatly appreciated.

Hi Jamie

So it is 6131? So part of the 6185 family. 

I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your
configuration. Try swapping to EDSA. I even removed support for
TAG_DSA in one of the recent patches.

Please also can you get https://github.com/vivien/linux.git commit
323321875671dfe95b6b91ce051a74d415c7158c which will give you some
extra debug files /sys/kernel/debug/mv88e6xxx. 

The reg, stats, and atu would be interesting.

    Andrew

Re: [PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

On Sat, 16 Jul 2016, Andrew Lunn wrote:

>> There's one major flaw; unicast traffic is never received on any port.
>> Broadcast traffic is received however, and on the correct port. Thus
>> an external machine can make an ARP request and get a response, for
>> example. With a manually-entered ARP entry, the router can send pings
>> out to a remote machine which responds, and the response is lost in the
>> DSA switch. "ethtool -S" reports pings received on "in_unicast" but
>> nothing makes it through the switch. This thread[0] seems very similar.
>> I've run out of ideas here and can't find any switch datasheets to give
>> me pointers so any suggestions greatly appreciated.
>
> Hi Jamie
>
> So it is 6131? So part of the 6185 family.

Yes, that's what's detected and the OpenWRT page says 88E6131-LAR1. And my 
test setup looks like:

88e6131
   |- lan1:10.100.1.55 <-- switch --> eth0:10.100.1.41 -|
   |- lan4:10.100.4.55 <-- cable  --> enp0:10.100.4.41 -|
                                                     laptop
enp0 is a 100M USB network card, the switch is gigabit and on the rest of 
my network here, so there's assorted background broadcast chatter. If the 
noise is confusing matters then can disconnect it.

Firstly I've tried to to rebase against net-next[0], but after adding 6131 
to mv88e6xxx_of_match, &chip->ppu_work seems to be causing a NULL pointer 
ooops. I'll assume it's not done yet and ignore net-next for now.

> I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your
> configuration. Try swapping to EDSA. I even removed support for
> TAG_DSA in one of the recent patches.

Okay, back to my original wnr854t-support-v0a branch based on 4.6, 
switched to .tag_protocol = DSA_TAG_PROTO_EDSA and reconfig'ed to 
add support, but there's no traffic in/out of any port. tcpdump on the 
underlying ethernet port shows encapsulated broadcast traffic, e.g. this 
ARP request from enp0:10.100.4.41:

00:15:31.173399 1a:ff:0f:fe:10:22 (oui Unknown) > Broadcast, ethertype 
Unknown (0xc008), length 64:
         0x0000:  0000 0806 0001 0800 0604 0001 1aff 0ffe  ................
         0x0010:  1022 0a64 0429 0000 0000 0000 0a64 0437  .".d.).......d.7
         0x0020:  0000 0000 0000 0000 0000 0000 0000 0000  ................
         0x0030:  0000                                     ..

...but no unicast traffic.

> Please also can you get https://github.com/vivien/linux.git commit
> 323321875671dfe95b6b91ce051a74d415c7158c which will give you some
> extra debug files /sys/kernel/debug/mv88e6xxx.
>
> The reg, stats, and atu would be interesting.

Okay, I rebased 4.7-rc7, ignoring my ropey attempts to configure the LEDs, 
cherry-picked the above commit. Pushed the result if it's useful[1]. The 
debugfs code wouldn't patch cleanly onto 4.6 or net-next.

On boot up I get:

mdio_bus f1072004.mdio-bu: switch 0x106 probed: Marvell 88E6131, revision 6
mv643xx_eth_port mv643xx_eth_port.0 eth0: [0]: detected a Marvell 88E6131 switch
libphy: dsa slave smi: probed
Marvell 88E1121R dsa-0:00:00: attached PHY driver [Marvell 88E1121R]  (mii_bus:phy_addr=dsa-0:00:00, irq=-1)
Marvell 88E1121R dsa-0:00:01: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:01, irq=-1)
Marvell 88E1121R dsa-0:00:02: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:02, irq=-1)
Marvell 88E1112 dsa-0:00:05: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:05, irq=-1)
Marvell 88E1112 dsa-0:00:07: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:07, irq=-1)

Like above (since 4.7 seems to use DSA_TAG_PROTO_EDSA), there's no 
traffic visible with tcpdump on lan1/4 (broadcast or unicast), only 
broadcast traffic on the backing port, eth0.

# cat /sys/kernel/debug/mv88e6xxx.0/regs
     GLOBAL GLOBAL2 SERDES     0    1    2    3    4    5    6    7
  0:  c800       0       0  7080 7d80 7080 6e88 6086 7e86 6086 7086
  1:    1b       0       0     3    3    3   3e  403  403  403  403
  2:  2fd5       0       0     0    0    0    0    0    0    0    0
  3:  9df4    ffff       0  1066 1066 1066 1066 1066 1066 1066 1066
  4:  4000     191       0   433  433  433 3533  433  433  433  433
  5:  1000      ff       0     0    0    0    0    0    0    0    0
  6:  c000    1f0f       0   708  708  708  7f7  708  708  708  708
  7:     0    70ff       0     0    0    0    0    0    0    0    0
  8:     0    7800       0    83   83   83   c3   83   83   83   83
  9:     0       0       0     1    1    1    1    1    1    1    1
  a:  f148       0       0     0    0    0    0    0    0    0    0
  b:  400f       0       0     1    2    4    0   10   20   40   80
  c:     0       0       0     0    0    0    0    0    0    0    0
  d:  ffff       0       0     0    0    0    0    0    0    0    0
  e:  ffff       0       0     0    0    0    0    0    0    0    0
  f:  ffff      77       0     0    0    0    0    0    0    0    0
10:     0       0       0     0    0    0    0    0    0    0    0
11:     0       0       0     0    0    0    0    0    0    0    0
12:  5555       0       0     0    0    0   12    0    0    0    0
13:  5555       0       0     0    0    0    0    0    0    0    0
14:  aaaa       0       0   403  403  403 8403  403  403  403  403
15:  aaaa       0       0     0    0    0    0    0    0    0    0
16:  ffff       0       0   700  70d  700  700  f41  f0e  f41  f02
17:  ffff       0       0     0    0    0    0    0    0    0    0
18:  fa41       0       0  3210 3210 3210 3210 3210 3210 3210 3210
19:  8100       0       0  7654 7654 7654 7654 7654 7654 7654 7654
1a:  3330       0       0     -    -    -    -    -    -    -    -
1b:    f4       0       0     -    -    -    -    -    -    -    -
1c:  f000       0       0     -    -    -    -    -    -    -    -
1d:  5c07       0       0     -    -    -    -    -    -    -    -
1e:     0      f0       0     -    -    -    -    -    -    -    -
1f:     0       0       0     -    -    -    -    -    -    -    -

# cat /sys/kernel/debug/mv88e6xxx.0/stats
                                (lan4)             (cpu)             (lan1)
           Statistic   Port  0  Port  1  Port  2  Port  3  Port  4  Port  5  Port  6  Port  7
      in_good_octets:        0     1064        0     1152        0   112155        0        0
       in_bad_octets:        0        0        0        0        0        0        0        0
          in_unicast:        0        0        0        0        0        0        0        0
       in_broadcasts:        0        6        0       18        0      335        0        0
       in_multicasts:        0        8        0        0        0      490        0        0
            in_pause:        0        0        0        0        0        0        0        0
        in_undersize:        0        0        0        0        0        0        0        0
        in_fragments:        0        0        0        0        0        0        0        0
         in_oversize:        0        0        0        0        0        0        0        0
           in_jabber:        0        0        0        0        0        0        0        0
         in_rx_error:        0        0        0        0        0        0        0        0
        in_fcs_error:        0        0        0        0        0        0        0        0
          out_octets:        0        0        0   131331        0        0        0        0
         out_unicast:        0        0        0        0        0        0        0        0
      out_broadcasts:        0        0        0      558        0        0        0        0
      out_multicasts:        0        0        0      498        0        0        0        0
           out_pause:        0        0        0        0        0        0        0        0
           excessive:        0        0        0        0        0        0        0        0
          collisions:        0        0        0        0        0        0        0        0
            deferred:        0        0        0        0        0        0        0        0
              single:        0        0        0        0        0        0        0        0
            multiple:        0        0        0        0        0        0        0        0
       out_fcs_error:        0        0        0        0        0        0        0        0
                late:        0        0        0        0        0        0        0        0
        hist_64bytes:        0        6        0       18        0      188        0        0
    hist_65_127bytes:        0        8        0      440        0       69        0        0
   hist_128_255bytes:        0        0        0      376        0      376        0        0
   hist_256_511bytes:        0        0        0        0        0        0        0        0
  hist_512_1023bytes:        0        0        0        0        0        0        0        0
hist_1024_max_bytes:        0        0        0        0        0        0        0        0
      sw_in_discards:        0        0        0        0        0        0        0        0
      sw_in_filtered:        0        0        0       18        0        0        0        0
     sw_out_filtered:        0        0        0        0        0        0        0        0

# cat /sys/kernel/debug/mv88e6xxx.0/atu
  FID  MAC Addr                  State         Trunk?  DPV/Trunk ID
    0  (dhcp server)                    Age 6       n  - - - - - 5 - -
    0  (access point)          Age 7 (newest)       n  - - - - - 5 - -
    0  (laptop enp0)                    Age 4       n  - 1 - - - - - -
    0  (android phone)                  Age 2       n  - - - - - 5 - -
    0  (android phone)                  Age 5       n  - - - - - 5 - -
    0  (openelec box w/kodi)   Age 7 (newest)       n  - - - - - 5 - -
    0  (android phone)         Age 7 (newest)       n  - - - - - 5 - -
    0  (laptop eth0)                    Age 5       n  - - - - - 5 - -
    0  (android phone)                  Age 3       n  - - - - - 5 - -

Apart from (laptop enp0), everything is on lan1/port 5. Let me know if 
it's useful to shed the background noise and/or try something in 
particular. Thanks for the help!

>
>    Andrew
>

[0] https://github.com/lentinj/linux/tree/wnr854t-support-v0b-net-next-experiment
[1] https://github.com/lentinj/linux/tree/wnr854t-support-v0a-rebase-4.7-rc7

-- 
Jamie Lentin

[PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

On Sat, 16 Jul 2016, Andrew Lunn wrote:

>> There's one major flaw; unicast traffic is never received on any port.
>> Broadcast traffic is received however, and on the correct port. Thus
>> an external machine can make an ARP request and get a response, for
>> example. With a manually-entered ARP entry, the router can send pings
>> out to a remote machine which responds, and the response is lost in the
>> DSA switch. "ethtool -S" reports pings received on "in_unicast" but
>> nothing makes it through the switch. This thread[0] seems very similar.
>> I've run out of ideas here and can't find any switch datasheets to give
>> me pointers so any suggestions greatly appreciated.
>
> Hi Jamie
>
> So it is 6131? So part of the 6185 family.

Yes, that's what's detected and the OpenWRT page says 88E6131-LAR1. And my 
test setup looks like:

88e6131
   |- lan1:10.100.1.55 <-- switch --> eth0:10.100.1.41 -|
   |- lan4:10.100.4.55 <-- cable  --> enp0:10.100.4.41 -|
                                                     laptop
enp0 is a 100M USB network card, the switch is gigabit and on the rest of 
my network here, so there's assorted background broadcast chatter. If the 
noise is confusing matters then can disconnect it.

Firstly I've tried to to rebase against net-next[0], but after adding 6131 
to mv88e6xxx_of_match, &chip->ppu_work seems to be causing a NULL pointer 
ooops. I'll assume it's not done yet and ignore net-next for now.

> I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your
> configuration. Try swapping to EDSA. I even removed support for
> TAG_DSA in one of the recent patches.

Okay, back to my original wnr854t-support-v0a branch based on 4.6, 
switched to .tag_protocol = DSA_TAG_PROTO_EDSA and reconfig'ed to 
add support, but there's no traffic in/out of any port. tcpdump on the 
underlying ethernet port shows encapsulated broadcast traffic, e.g. this 
ARP request from enp0:10.100.4.41:

00:15:31.173399 1a:ff:0f:fe:10:22 (oui Unknown) > Broadcast, ethertype 
Unknown (0xc008), length 64:
         0x0000:  0000 0806 0001 0800 0604 0001 1aff 0ffe  ................
         0x0010:  1022 0a64 0429 0000 0000 0000 0a64 0437  .".d.).......d.7
         0x0020:  0000 0000 0000 0000 0000 0000 0000 0000  ................
         0x0030:  0000                                     ..

...but no unicast traffic.

> Please also can you get https://github.com/vivien/linux.git commit
> 323321875671dfe95b6b91ce051a74d415c7158c which will give you some
> extra debug files /sys/kernel/debug/mv88e6xxx.
>
> The reg, stats, and atu would be interesting.

Okay, I rebased 4.7-rc7, ignoring my ropey attempts to configure the LEDs, 
cherry-picked the above commit. Pushed the result if it's useful[1]. The 
debugfs code wouldn't patch cleanly onto 4.6 or net-next.

On boot up I get:

mdio_bus f1072004.mdio-bu: switch 0x106 probed: Marvell 88E6131, revision 6
mv643xx_eth_port mv643xx_eth_port.0 eth0: [0]: detected a Marvell 88E6131 switch
libphy: dsa slave smi: probed
Marvell 88E1121R dsa-0:00:00: attached PHY driver [Marvell 88E1121R]  (mii_bus:phy_addr=dsa-0:00:00, irq=-1)
Marvell 88E1121R dsa-0:00:01: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:01, irq=-1)
Marvell 88E1121R dsa-0:00:02: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:02, irq=-1)
Marvell 88E1112 dsa-0:00:05: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:05, irq=-1)
Marvell 88E1112 dsa-0:00:07: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:07, irq=-1)

Like above (since 4.7 seems to use DSA_TAG_PROTO_EDSA), there's no 
traffic visible with tcpdump on lan1/4 (broadcast or unicast), only 
broadcast traffic on the backing port, eth0.

# cat /sys/kernel/debug/mv88e6xxx.0/regs
     GLOBAL GLOBAL2 SERDES     0    1    2    3    4    5    6    7
  0:  c800       0       0  7080 7d80 7080 6e88 6086 7e86 6086 7086
  1:    1b       0       0     3    3    3   3e  403  403  403  403
  2:  2fd5       0       0     0    0    0    0    0    0    0    0
  3:  9df4    ffff       0  1066 1066 1066 1066 1066 1066 1066 1066
  4:  4000     191       0   433  433  433 3533  433  433  433  433
  5:  1000      ff       0     0    0    0    0    0    0    0    0
  6:  c000    1f0f       0   708  708  708  7f7  708  708  708  708
  7:     0    70ff       0     0    0    0    0    0    0    0    0
  8:     0    7800       0    83   83   83   c3   83   83   83   83
  9:     0       0       0     1    1    1    1    1    1    1    1
  a:  f148       0       0     0    0    0    0    0    0    0    0
  b:  400f       0       0     1    2    4    0   10   20   40   80
  c:     0       0       0     0    0    0    0    0    0    0    0
  d:  ffff       0       0     0    0    0    0    0    0    0    0
  e:  ffff       0       0     0    0    0    0    0    0    0    0
  f:  ffff      77       0     0    0    0    0    0    0    0    0
10:     0       0       0     0    0    0    0    0    0    0    0
11:     0       0       0     0    0    0    0    0    0    0    0
12:  5555       0       0     0    0    0   12    0    0    0    0
13:  5555       0       0     0    0    0    0    0    0    0    0
14:  aaaa       0       0   403  403  403 8403  403  403  403  403
15:  aaaa       0       0     0    0    0    0    0    0    0    0
16:  ffff       0       0   700  70d  700  700  f41  f0e  f41  f02
17:  ffff       0       0     0    0    0    0    0    0    0    0
18:  fa41       0       0  3210 3210 3210 3210 3210 3210 3210 3210
19:  8100       0       0  7654 7654 7654 7654 7654 7654 7654 7654
1a:  3330       0       0     -    -    -    -    -    -    -    -
1b:    f4       0       0     -    -    -    -    -    -    -    -
1c:  f000       0       0     -    -    -    -    -    -    -    -
1d:  5c07       0       0     -    -    -    -    -    -    -    -
1e:     0      f0       0     -    -    -    -    -    -    -    -
1f:     0       0       0     -    -    -    -    -    -    -    -

# cat /sys/kernel/debug/mv88e6xxx.0/stats
                                (lan4)             (cpu)             (lan1)
           Statistic   Port  0  Port  1  Port  2  Port  3  Port  4  Port  5  Port  6  Port  7
      in_good_octets:        0     1064        0     1152        0   112155        0        0
       in_bad_octets:        0        0        0        0        0        0        0        0
          in_unicast:        0        0        0        0        0        0        0        0
       in_broadcasts:        0        6        0       18        0      335        0        0
       in_multicasts:        0        8        0        0        0      490        0        0
            in_pause:        0        0        0        0        0        0        0        0
        in_undersize:        0        0        0        0        0        0        0        0
        in_fragments:        0        0        0        0        0        0        0        0
         in_oversize:        0        0        0        0        0        0        0        0
           in_jabber:        0        0        0        0        0        0        0        0
         in_rx_error:        0        0        0        0        0        0        0        0
        in_fcs_error:        0        0        0        0        0        0        0        0
          out_octets:        0        0        0   131331        0        0        0        0
         out_unicast:        0        0        0        0        0        0        0        0
      out_broadcasts:        0        0        0      558        0        0        0        0
      out_multicasts:        0        0        0      498        0        0        0        0
           out_pause:        0        0        0        0        0        0        0        0
           excessive:        0        0        0        0        0        0        0        0
          collisions:        0        0        0        0        0        0        0        0
            deferred:        0        0        0        0        0        0        0        0
              single:        0        0        0        0        0        0        0        0
            multiple:        0        0        0        0        0        0        0        0
       out_fcs_error:        0        0        0        0        0        0        0        0
                late:        0        0        0        0        0        0        0        0
        hist_64bytes:        0        6        0       18        0      188        0        0
    hist_65_127bytes:        0        8        0      440        0       69        0        0
   hist_128_255bytes:        0        0        0      376        0      376        0        0
   hist_256_511bytes:        0        0        0        0        0        0        0        0
  hist_512_1023bytes:        0        0        0        0        0        0        0        0
hist_1024_max_bytes:        0        0        0        0        0        0        0        0
      sw_in_discards:        0        0        0        0        0        0        0        0
      sw_in_filtered:        0        0        0       18        0        0        0        0
     sw_out_filtered:        0        0        0        0        0        0        0        0

# cat /sys/kernel/debug/mv88e6xxx.0/atu
  FID  MAC Addr                  State         Trunk?  DPV/Trunk ID
    0  (dhcp server)                    Age 6       n  - - - - - 5 - -
    0  (access point)          Age 7 (newest)       n  - - - - - 5 - -
    0  (laptop enp0)                    Age 4       n  - 1 - - - - - -
    0  (android phone)                  Age 2       n  - - - - - 5 - -
    0  (android phone)                  Age 5       n  - - - - - 5 - -
    0  (openelec box w/kodi)   Age 7 (newest)       n  - - - - - 5 - -
    0  (android phone)         Age 7 (newest)       n  - - - - - 5 - -
    0  (laptop eth0)                    Age 5       n  - - - - - 5 - -
    0  (android phone)                  Age 3       n  - - - - - 5 - -

Apart from (laptop enp0), everything is on lan1/port 5. Let me know if 
it's useful to shed the background noise and/or try something in 
particular. Thanks for the help!

>
>    Andrew
>

[0] https://github.com/lentinj/linux/tree/wnr854t-support-v0b-net-next-experiment
[1] https://github.com/lentinj/linux/tree/wnr854t-support-v0a-rebase-4.7-rc7

-- 
Jamie Lentin

Re: [PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Andrew Lunn]

> Firstly I've tried to to rebase against net-next[0], but after
> adding 6131 to mv88e6xxx_of_match, &chip->ppu_work seems to be
> causing a NULL pointer ooops. I'll assume it's not done yet and
> ignore net-next for now.

You don't need to modify mv88e6xxx_of_match, the 6131 is compatible
with the mv88e6085. Just use the compatible string of
"marvell,mv88e6085". So far, ever Marvell chip we support is
compatible with the mv88e6085, in terms of probing. Once the driver
has probed, and read the device ID from a register, it knows enough to
decide for itself what features the chip has.

In order to get the LEDs working as you want, you are going to have to
use the new binding. So i would suggest sticking with that.

> >I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your
> >configuration. Try swapping to EDSA. I even removed support for
> >TAG_DSA in one of the recent patches.
> 
> Okay, back to my original wnr854t-support-v0a branch based on 4.6,
> switched to .tag_protocol = DSA_TAG_PROTO_EDSA and reconfig'ed to
> add support, but there's no traffic in/out of any port. tcpdump on
> the underlying ethernet port shows encapsulated broadcast traffic,
> e.g. this ARP request from enp0:10.100.4.41:
> 
> 00:15:31.173399 1a:ff:0f:fe:10:22 (oui Unknown) > Broadcast,
> ethertype Unknown (0xc008), length 64:
>         0x0000:  0000 0806 0001 0800 0604 0001 1aff 0ffe  ................
>         0x0010:  1022 0a64 0429 0000 0000 0000 0a64 0437  .".d.).......d.7
>         0x0020:  0000 0000 0000 0000 0000 0000 0000 0000  ................
>         0x0030:  0000                                     ..
> 
> ...but no unicast traffic.

Uh, that does not look like EDSA tagging. Expect an ethertype of
0xdada. Also, if you get the latest tcpdump sources, it knows how to
decode the additional EDSA header which is added.

> 
> >Please also can you get https://github.com/vivien/linux.git commit
> >323321875671dfe95b6b91ce051a74d415c7158c which will give you some
> >extra debug files /sys/kernel/debug/mv88e6xxx.
> >
> >The reg, stats, and atu would be interesting.
> 
> Okay, I rebased 4.7-rc7, ignoring my ropey attempts to configure the
> LEDs, cherry-picked the above commit. Pushed the result if it's
> useful[1]. The debugfs code wouldn't patch cleanly onto 4.6 or
> net-next.

Yes, the debug code is a real pain. Something i'm working on in the
background, get something generic which is acceptable for mainline.
 
> On boot up I get:
> 
> mdio_bus f1072004.mdio-bu: switch 0x106 probed: Marvell 88E6131, revision 6
> mv643xx_eth_port mv643xx_eth_port.0 eth0: [0]: detected a Marvell 88E6131 switch
> libphy: dsa slave smi: probed
> Marvell 88E1121R dsa-0:00:00: attached PHY driver [Marvell 88E1121R]  (mii_bus:phy_addr=dsa-0:00:00, irq=-1)
> Marvell 88E1121R dsa-0:00:01: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:01, irq=-1)
> Marvell 88E1121R dsa-0:00:02: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:02, irq=-1)
> Marvell 88E1112 dsa-0:00:05: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:05, irq=-1)
> Marvell 88E1112 dsa-0:00:07: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:07, irq=-1)

That looks good, it found the PHYs etc.

> Like above (since 4.7 seems to use DSA_TAG_PROTO_EDSA), there's no
> traffic visible with tcpdump on lan1/4 (broadcast or unicast), only
> broadcast traffic on the backing port, eth0.
> 
> # cat /sys/kernel/debug/mv88e6xxx.0/regs
>     GLOBAL GLOBAL2 SERDES     0    1    2    3    4    5    6    7
>  0:  c800       0       0  7080 7d80 7080 6e88 6086 7e86 6086 7086
>  1:    1b       0       0     3    3    3   3e  403  403  403  403
>  2:  2fd5       0       0     0    0    0    0    0    0    0    0
>  3:  9df4    ffff       0  1066 1066 1066 1066 1066 1066 1066 1066
>  4:  4000     191       0   433  433  433 3533  433  433  433  433
>  5:  1000      ff       0     0    0    0    0    0    0    0    0
>  6:  c000    1f0f       0   708  708  708  7f7  708  708  708  708
>  7:     0    70ff       0     0    0    0    0    0    0    0    0
>  8:     0    7800       0    83   83   83   c3   83   83   83   83
>  9:     0       0       0     1    1    1    1    1    1    1    1
>  a:  f148       0       0     0    0    0    0    0    0    0    0
>  b:  400f       0       0     1    2    4    0   10   20   40   80
>  c:     0       0       0     0    0    0    0    0    0    0    0
>  d:  ffff       0       0     0    0    0    0    0    0    0    0
>  e:  ffff       0       0     0    0    0    0    0    0    0    0
>  f:  ffff      77       0     0    0    0    0    0    0    0    0
> 10:     0       0       0     0    0    0    0    0    0    0    0
> 11:     0       0       0     0    0    0    0    0    0    0    0
> 12:  5555       0       0     0    0    0   12    0    0    0    0
> 13:  5555       0       0     0    0    0    0    0    0    0    0
> 14:  aaaa       0       0   403  403  403 8403  403  403  403  403
> 15:  aaaa       0       0     0    0    0    0    0    0    0    0
> 16:  ffff       0       0   700  70d  700  700  f41  f0e  f41  f02
> 17:  ffff       0       0     0    0    0    0    0    0    0    0
> 18:  fa41       0       0  3210 3210 3210 3210 3210 3210 3210 3210
> 19:  8100       0       0  7654 7654 7654 7654 7654 7654 7654 7654
> 1a:  3330       0       0     -    -    -    -    -    -    -    -
> 1b:    f4       0       0     -    -    -    -    -    -    -    -
> 1c:  f000       0       0     -    -    -    -    -    -    -    -
> 1d:  5c07       0       0     -    -    -    -    -    -    -    -
> 1e:     0      f0       0     -    -    -    -    -    -    -    -
> 1f:     0       0       0     -    -    -    -    -    -    -    -
> 
> # cat /sys/kernel/debug/mv88e6xxx.0/stats
>                                (lan4)             (cpu)             (lan1)
>           Statistic   Port  0  Port  1  Port  2  Port  3  Port  4  Port  5  Port  6  Port  7
>      in_good_octets:        0     1064        0     1152        0   112155        0        0
>       in_bad_octets:        0        0        0        0        0        0        0        0
>          in_unicast:        0        0        0        0        0        0        0        0
>       in_broadcasts:        0        6        0       18        0      335        0        0
>       in_multicasts:        0        8        0        0        0      490        0        0
>            in_pause:        0        0        0        0        0        0        0        0
>        in_undersize:        0        0        0        0        0        0        0        0
>        in_fragments:        0        0        0        0        0        0        0        0
>         in_oversize:        0        0        0        0        0        0        0        0
>           in_jabber:        0        0        0        0        0        0        0        0
>         in_rx_error:        0        0        0        0        0        0        0        0
>        in_fcs_error:        0        0        0        0        0        0        0        0
>          out_octets:        0        0        0   131331        0        0        0        0
>         out_unicast:        0        0        0        0        0        0        0        0
>      out_broadcasts:        0        0        0      558        0        0        0        0
>      out_multicasts:        0        0        0      498        0        0        0        0
>           out_pause:        0        0        0        0        0        0        0        0
>           excessive:        0        0        0        0        0        0        0        0
>          collisions:        0        0        0        0        0        0        0        0
>            deferred:        0        0        0        0        0        0        0        0
>              single:        0        0        0        0        0        0        0        0
>            multiple:        0        0        0        0        0        0        0        0
>       out_fcs_error:        0        0        0        0        0        0        0        0
>                late:        0        0        0        0        0        0        0        0
>        hist_64bytes:        0        6        0       18        0      188        0        0
>    hist_65_127bytes:        0        8        0      440        0       69        0        0
>   hist_128_255bytes:        0        0        0      376        0      376        0        0
>   hist_256_511bytes:        0        0        0        0        0        0        0        0
>  hist_512_1023bytes:        0        0        0        0        0        0        0        0
> hist_1024_max_bytes:        0        0        0        0        0        0        0        0
>      sw_in_discards:        0        0        0        0        0        0        0        0
>      sw_in_filtered:        0        0        0       18        0        0        0        0
>     sw_out_filtered:        0        0        0        0        0        0        0        0

So as you say, no unicast traffic to/from the CPU port. The 18
sw_in_filtered also look suspicious.
 
> [0] https://github.com/lentinj/linux/tree/wnr854t-support-v0b-net-next-experiment

+	port@3 {
+			reg = <3>;
+			label = "cpu";
+			ethernet = <&eth>;
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};

You don't need a fixed-link here. The cpu port is automatically
configured fixed at the highest speed the port will do.

However, 

 &eth {
      status = "okay";
-     ethernet-port@0 {
-     		speed = <1000>;
-		duplex = <1>;
-    };
 };

here you do need the fixed link, otherwise it thinks there is a PHY
connected and tried to do auto-negotiation. That will never work.

	  Andrew

[PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Andrew Lunn]

> Firstly I've tried to to rebase against net-next[0], but after
> adding 6131 to mv88e6xxx_of_match, &chip->ppu_work seems to be
> causing a NULL pointer ooops. I'll assume it's not done yet and
> ignore net-next for now.

You don't need to modify mv88e6xxx_of_match, the 6131 is compatible
with the mv88e6085. Just use the compatible string of
"marvell,mv88e6085". So far, ever Marvell chip we support is
compatible with the mv88e6085, in terms of probing. Once the driver
has probed, and read the device ID from a register, it knows enough to
decide for itself what features the chip has.

In order to get the LEDs working as you want, you are going to have to
use the new binding. So i would suggest sticking with that.

> >I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your
> >configuration. Try swapping to EDSA. I even removed support for
> >TAG_DSA in one of the recent patches.
> 
> Okay, back to my original wnr854t-support-v0a branch based on 4.6,
> switched to .tag_protocol = DSA_TAG_PROTO_EDSA and reconfig'ed to
> add support, but there's no traffic in/out of any port. tcpdump on
> the underlying ethernet port shows encapsulated broadcast traffic,
> e.g. this ARP request from enp0:10.100.4.41:
> 
> 00:15:31.173399 1a:ff:0f:fe:10:22 (oui Unknown) > Broadcast,
> ethertype Unknown (0xc008), length 64:
>         0x0000:  0000 0806 0001 0800 0604 0001 1aff 0ffe  ................
>         0x0010:  1022 0a64 0429 0000 0000 0000 0a64 0437  .".d.).......d.7
>         0x0020:  0000 0000 0000 0000 0000 0000 0000 0000  ................
>         0x0030:  0000                                     ..
> 
> ...but no unicast traffic.

Uh, that does not look like EDSA tagging. Expect an ethertype of
0xdada. Also, if you get the latest tcpdump sources, it knows how to
decode the additional EDSA header which is added.

> 
> >Please also can you get https://github.com/vivien/linux.git commit
> >323321875671dfe95b6b91ce051a74d415c7158c which will give you some
> >extra debug files /sys/kernel/debug/mv88e6xxx.
> >
> >The reg, stats, and atu would be interesting.
> 
> Okay, I rebased 4.7-rc7, ignoring my ropey attempts to configure the
> LEDs, cherry-picked the above commit. Pushed the result if it's
> useful[1]. The debugfs code wouldn't patch cleanly onto 4.6 or
> net-next.

Yes, the debug code is a real pain. Something i'm working on in the
background, get something generic which is acceptable for mainline.
 
> On boot up I get:
> 
> mdio_bus f1072004.mdio-bu: switch 0x106 probed: Marvell 88E6131, revision 6
> mv643xx_eth_port mv643xx_eth_port.0 eth0: [0]: detected a Marvell 88E6131 switch
> libphy: dsa slave smi: probed
> Marvell 88E1121R dsa-0:00:00: attached PHY driver [Marvell 88E1121R]  (mii_bus:phy_addr=dsa-0:00:00, irq=-1)
> Marvell 88E1121R dsa-0:00:01: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:01, irq=-1)
> Marvell 88E1121R dsa-0:00:02: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:02, irq=-1)
> Marvell 88E1112 dsa-0:00:05: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:05, irq=-1)
> Marvell 88E1112 dsa-0:00:07: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:07, irq=-1)

That looks good, it found the PHYs etc.

> Like above (since 4.7 seems to use DSA_TAG_PROTO_EDSA), there's no
> traffic visible with tcpdump on lan1/4 (broadcast or unicast), only
> broadcast traffic on the backing port, eth0.
> 
> # cat /sys/kernel/debug/mv88e6xxx.0/regs
>     GLOBAL GLOBAL2 SERDES     0    1    2    3    4    5    6    7
>  0:  c800       0       0  7080 7d80 7080 6e88 6086 7e86 6086 7086
>  1:    1b       0       0     3    3    3   3e  403  403  403  403
>  2:  2fd5       0       0     0    0    0    0    0    0    0    0
>  3:  9df4    ffff       0  1066 1066 1066 1066 1066 1066 1066 1066
>  4:  4000     191       0   433  433  433 3533  433  433  433  433
>  5:  1000      ff       0     0    0    0    0    0    0    0    0
>  6:  c000    1f0f       0   708  708  708  7f7  708  708  708  708
>  7:     0    70ff       0     0    0    0    0    0    0    0    0
>  8:     0    7800       0    83   83   83   c3   83   83   83   83
>  9:     0       0       0     1    1    1    1    1    1    1    1
>  a:  f148       0       0     0    0    0    0    0    0    0    0
>  b:  400f       0       0     1    2    4    0   10   20   40   80
>  c:     0       0       0     0    0    0    0    0    0    0    0
>  d:  ffff       0       0     0    0    0    0    0    0    0    0
>  e:  ffff       0       0     0    0    0    0    0    0    0    0
>  f:  ffff      77       0     0    0    0    0    0    0    0    0
> 10:     0       0       0     0    0    0    0    0    0    0    0
> 11:     0       0       0     0    0    0    0    0    0    0    0
> 12:  5555       0       0     0    0    0   12    0    0    0    0
> 13:  5555       0       0     0    0    0    0    0    0    0    0
> 14:  aaaa       0       0   403  403  403 8403  403  403  403  403
> 15:  aaaa       0       0     0    0    0    0    0    0    0    0
> 16:  ffff       0       0   700  70d  700  700  f41  f0e  f41  f02
> 17:  ffff       0       0     0    0    0    0    0    0    0    0
> 18:  fa41       0       0  3210 3210 3210 3210 3210 3210 3210 3210
> 19:  8100       0       0  7654 7654 7654 7654 7654 7654 7654 7654
> 1a:  3330       0       0     -    -    -    -    -    -    -    -
> 1b:    f4       0       0     -    -    -    -    -    -    -    -
> 1c:  f000       0       0     -    -    -    -    -    -    -    -
> 1d:  5c07       0       0     -    -    -    -    -    -    -    -
> 1e:     0      f0       0     -    -    -    -    -    -    -    -
> 1f:     0       0       0     -    -    -    -    -    -    -    -
> 
> # cat /sys/kernel/debug/mv88e6xxx.0/stats
>                                (lan4)             (cpu)             (lan1)
>           Statistic   Port  0  Port  1  Port  2  Port  3  Port  4  Port  5  Port  6  Port  7
>      in_good_octets:        0     1064        0     1152        0   112155        0        0
>       in_bad_octets:        0        0        0        0        0        0        0        0
>          in_unicast:        0        0        0        0        0        0        0        0
>       in_broadcasts:        0        6        0       18        0      335        0        0
>       in_multicasts:        0        8        0        0        0      490        0        0
>            in_pause:        0        0        0        0        0        0        0        0
>        in_undersize:        0        0        0        0        0        0        0        0
>        in_fragments:        0        0        0        0        0        0        0        0
>         in_oversize:        0        0        0        0        0        0        0        0
>           in_jabber:        0        0        0        0        0        0        0        0
>         in_rx_error:        0        0        0        0        0        0        0        0
>        in_fcs_error:        0        0        0        0        0        0        0        0
>          out_octets:        0        0        0   131331        0        0        0        0
>         out_unicast:        0        0        0        0        0        0        0        0
>      out_broadcasts:        0        0        0      558        0        0        0        0
>      out_multicasts:        0        0        0      498        0        0        0        0
>           out_pause:        0        0        0        0        0        0        0        0
>           excessive:        0        0        0        0        0        0        0        0
>          collisions:        0        0        0        0        0        0        0        0
>            deferred:        0        0        0        0        0        0        0        0
>              single:        0        0        0        0        0        0        0        0
>            multiple:        0        0        0        0        0        0        0        0
>       out_fcs_error:        0        0        0        0        0        0        0        0
>                late:        0        0        0        0        0        0        0        0
>        hist_64bytes:        0        6        0       18        0      188        0        0
>    hist_65_127bytes:        0        8        0      440        0       69        0        0
>   hist_128_255bytes:        0        0        0      376        0      376        0        0
>   hist_256_511bytes:        0        0        0        0        0        0        0        0
>  hist_512_1023bytes:        0        0        0        0        0        0        0        0
> hist_1024_max_bytes:        0        0        0        0        0        0        0        0
>      sw_in_discards:        0        0        0        0        0        0        0        0
>      sw_in_filtered:        0        0        0       18        0        0        0        0
>     sw_out_filtered:        0        0        0        0        0        0        0        0

So as you say, no unicast traffic to/from the CPU port. The 18
sw_in_filtered also look suspicious.
 
> [0] https://github.com/lentinj/linux/tree/wnr854t-support-v0b-net-next-experiment

+	port at 3 {
+			reg = <3>;
+			label = "cpu";
+			ethernet = <&eth>;
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};

You don't need a fixed-link here. The cpu port is automatically
configured fixed at the highest speed the port will do.

However, 

 &eth {
      status = "okay";
-     ethernet-port at 0 {
-     		speed = <1000>;
-		duplex = <1>;
-    };
 };

here you do need the fixed link, otherwise it thinks there is a PHY
connected and tried to do auto-negotiation. That will never work.

	  Andrew

Re: [PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

On Sun, 17 Jul 2016, Andrew Lunn wrote:

>> Firstly I've tried to to rebase against net-next[0], but after
>> adding 6131 to mv88e6xxx_of_match, &chip->ppu_work seems to be
>> causing a NULL pointer ooops. I'll assume it's not done yet and
>> ignore net-next for now.
>
> You don't need to modify mv88e6xxx_of_match, the 6131 is compatible
> with the mv88e6085. Just use the compatible string of
> "marvell,mv88e6085". So far, ever Marvell chip we support is
> compatible with the mv88e6085, in terms of probing. Once the driver
> has probed, and read the device ID from a register, it knows enough to
> decide for itself what features the chip has.

Okay, besides the DT mistakes you mention below (changes are pushed to the 
same branch), I've worked out out what my problem was here. The switch was 
probed before the ethernet device is available, so mv88e6xxx_probe() has 
to back out with EPROBE_DEFER at mv88e6xxx_register_switch().

However mv88e6xxx_mdio_unregister() doesn't tidy up fully. The following 
lets me boot, but I'm not really clear what the usleep is helping solve 
and don't like it:

diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 5cb06f7..c46ac54 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -3387,6 +3387,10 @@ static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
  {
  	struct mii_bus *bus = chip->mdio_bus;

+	/* Stop any timers attempting to re-activate the PPU */
+	del_timer(&chip->ppu_timer);
+	usleep_range(1000, 2000);
+
  	mdiobus_unregister(bus);

  	if (chip->mdio_np)

FWIW I now get:

libphy: Fixed MDIO Bus: probed
libphy: mdio_driver_register: mv88e6085
libphy: orion_mdio_bus: probed
mdio_bus f1072004.mdio-bu:00: mdio_device_register
mv88e6085 f1072004.mdio-bu:00: switch 0x106 detected: Marvell 88E6131, revision 6
libphy: /soc/internal-regs/mdio-bus@72004/switch@0: probed
mv643xx_eth: MV-643xx 10/100/1000 ethernet driver version 1.4
mv643xx_eth_port mv643xx_eth_port.0 eth0: port 0 with MAC address 00:1b:2f:d5:9d:f4
  . . .
mv88e6085 f1072004.mdio-bu:00: switch 0x106 detected: Marvell 88E6131, revision 6
libphy: /soc/internal-regs/mdio-bus@72004/switch@0: probed
DSA: switch 0 0 parsed
DSA: tree 0 parsed
Marvell 88E1121R !soc!internal-re:00: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=!soc!internal-re:00, irq=-1)
Marvell 88E1121R !soc!internal-re:01: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=!soc!internal-re:01, irq=-1)
Marvell 88E1121R !soc!internal-re:02: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=!soc!internal-re:02, irq=-1)
Marvell 88E1112 !soc!internal-re:05: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=!soc!internal-re:05, irq=-1)
Marvell 88E1112 !soc!internal-re:07: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=!soc!internal-re:07, irq=-1)

However, nothing's changed since 4.7-rc7 in terms of getting the switch 
to work.

> In order to get the LEDs working as you want, you are going to have to
> use the new binding. So i would suggest sticking with that.

Some have suggested I should be more worried about being able to shift 
packets than getting the LEDs working, but where's the fun in that? :)

>>> I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your
>>> configuration. Try swapping to EDSA. I even removed support for
>>> TAG_DSA in one of the recent patches.
>>
>> Okay, back to my original wnr854t-support-v0a branch based on 4.6,
>> switched to .tag_protocol = DSA_TAG_PROTO_EDSA and reconfig'ed to
>> add support, but there's no traffic in/out of any port. tcpdump on
>> the underlying ethernet port shows encapsulated broadcast traffic,
>> e.g. this ARP request from enp0:10.100.4.41:
>>
>> 00:15:31.173399 1a:ff:0f:fe:10:22 (oui Unknown) > Broadcast,
>> ethertype Unknown (0xc008), length 64:
>>         0x0000:  0000 0806 0001 0800 0604 0001 1aff 0ffe  ................
>>         0x0010:  1022 0a64 0429 0000 0000 0000 0a64 0437  .".d.).......d.7
>>         0x0020:  0000 0000 0000 0000 0000 0000 0000 0000  ................
>>         0x0030:  0000                                     ..
>>
>> ...but no unicast traffic.
>
> Uh, that does not look like EDSA tagging. Expect an ethertype of
> 0xdada. Also, if you get the latest tcpdump sources, it knows how to
> decode the additional EDSA header which is added.

Okay. Frames sent from the port are EDSA-tagged (which isn't exactly 
surprising), but I'm yet to see the switch receive 0xdada frames. Even 
with the net-next branch which uses DSA_TAG_PROTO_EDSA for all chip types.

However, the ethertype is reflecting the port:-

lan1/5 : ethertype Unknown (0xc028), length 176:
lan2/7 : ethertype Unknown (0xc038), length 176:
lan3/0 : ethertype Unknown (0xc000), length 176:
lan4/1 : ethertype Unknown (0xc008), length 176:
wan/2  : ethertype Unknown (0xc010), length 176:

My other one of these routers, running OpenWRT / Linux 3.3.8, shows the 
same ethertypes, which suggests that the switch is still in DSA tagging 
mode. I'll poke around further and see what I find.

>>> Please also can you get https://github.com/vivien/linux.git commit
>>> 323321875671dfe95b6b91ce051a74d415c7158c which will give you some
>>> extra debug files /sys/kernel/debug/mv88e6xxx.
>>>
>>> The reg, stats, and atu would be interesting.
>>
>> Okay, I rebased 4.7-rc7, ignoring my ropey attempts to configure the
>> LEDs, cherry-picked the above commit. Pushed the result if it's
>> useful[1]. The debugfs code wouldn't patch cleanly onto 4.6 or
>> net-next.
>
> Yes, the debug code is a real pain. Something i'm working on in the
> background, get something generic which is acceptable for mainline.
>
>> On boot up I get:
>>
>> mdio_bus f1072004.mdio-bu: switch 0x106 probed: Marvell 88E6131, revision 6
>> mv643xx_eth_port mv643xx_eth_port.0 eth0: [0]: detected a Marvell 88E6131 switch
>> libphy: dsa slave smi: probed
>> Marvell 88E1121R dsa-0:00:00: attached PHY driver [Marvell 88E1121R]  (mii_bus:phy_addr=dsa-0:00:00, irq=-1)
>> Marvell 88E1121R dsa-0:00:01: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:01, irq=-1)
>> Marvell 88E1121R dsa-0:00:02: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:02, irq=-1)
>> Marvell 88E1112 dsa-0:00:05: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:05, irq=-1)
>> Marvell 88E1112 dsa-0:00:07: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:07, irq=-1)
>
> That looks good, it found the PHYs etc.
>
>> Like above (since 4.7 seems to use DSA_TAG_PROTO_EDSA), there's no
>> traffic visible with tcpdump on lan1/4 (broadcast or unicast), only
>> broadcast traffic on the backing port, eth0.
>>
>> # cat /sys/kernel/debug/mv88e6xxx.0/regs
>>     GLOBAL GLOBAL2 SERDES     0    1    2    3    4    5    6    7
>>  0:  c800       0       0  7080 7d80 7080 6e88 6086 7e86 6086 7086
>>  1:    1b       0       0     3    3    3   3e  403  403  403  403
>>  2:  2fd5       0       0     0    0    0    0    0    0    0    0
>>  3:  9df4    ffff       0  1066 1066 1066 1066 1066 1066 1066 1066
>>  4:  4000     191       0   433  433  433 3533  433  433  433  433
>>  5:  1000      ff       0     0    0    0    0    0    0    0    0
>>  6:  c000    1f0f       0   708  708  708  7f7  708  708  708  708
>>  7:     0    70ff       0     0    0    0    0    0    0    0    0
>>  8:     0    7800       0    83   83   83   c3   83   83   83   83
>>  9:     0       0       0     1    1    1    1    1    1    1    1
>>  a:  f148       0       0     0    0    0    0    0    0    0    0
>>  b:  400f       0       0     1    2    4    0   10   20   40   80
>>  c:     0       0       0     0    0    0    0    0    0    0    0
>>  d:  ffff       0       0     0    0    0    0    0    0    0    0
>>  e:  ffff       0       0     0    0    0    0    0    0    0    0
>>  f:  ffff      77       0     0    0    0    0    0    0    0    0
>> 10:     0       0       0     0    0    0    0    0    0    0    0
>> 11:     0       0       0     0    0    0    0    0    0    0    0
>> 12:  5555       0       0     0    0    0   12    0    0    0    0
>> 13:  5555       0       0     0    0    0    0    0    0    0    0
>> 14:  aaaa       0       0   403  403  403 8403  403  403  403  403
>> 15:  aaaa       0       0     0    0    0    0    0    0    0    0
>> 16:  ffff       0       0   700  70d  700  700  f41  f0e  f41  f02
>> 17:  ffff       0       0     0    0    0    0    0    0    0    0
>> 18:  fa41       0       0  3210 3210 3210 3210 3210 3210 3210 3210
>> 19:  8100       0       0  7654 7654 7654 7654 7654 7654 7654 7654
>> 1a:  3330       0       0     -    -    -    -    -    -    -    -
>> 1b:    f4       0       0     -    -    -    -    -    -    -    -
>> 1c:  f000       0       0     -    -    -    -    -    -    -    -
>> 1d:  5c07       0       0     -    -    -    -    -    -    -    -
>> 1e:     0      f0       0     -    -    -    -    -    -    -    -
>> 1f:     0       0       0     -    -    -    -    -    -    -    -
>>
>> # cat /sys/kernel/debug/mv88e6xxx.0/stats
>>                                (lan4)             (cpu)             (lan1)
>>           Statistic   Port  0  Port  1  Port  2  Port  3  Port  4  Port  5  Port  6  Port  7
>>      in_good_octets:        0     1064        0     1152        0   112155        0        0
>>       in_bad_octets:        0        0        0        0        0        0        0        0
>>          in_unicast:        0        0        0        0        0        0        0        0
>>       in_broadcasts:        0        6        0       18        0      335        0        0
>>       in_multicasts:        0        8        0        0        0      490        0        0
>>            in_pause:        0        0        0        0        0        0        0        0
>>        in_undersize:        0        0        0        0        0        0        0        0
>>        in_fragments:        0        0        0        0        0        0        0        0
>>         in_oversize:        0        0        0        0        0        0        0        0
>>           in_jabber:        0        0        0        0        0        0        0        0
>>         in_rx_error:        0        0        0        0        0        0        0        0
>>        in_fcs_error:        0        0        0        0        0        0        0        0
>>          out_octets:        0        0        0   131331        0        0        0        0
>>         out_unicast:        0        0        0        0        0        0        0        0
>>      out_broadcasts:        0        0        0      558        0        0        0        0
>>      out_multicasts:        0        0        0      498        0        0        0        0
>>           out_pause:        0        0        0        0        0        0        0        0
>>           excessive:        0        0        0        0        0        0        0        0
>>          collisions:        0        0        0        0        0        0        0        0
>>            deferred:        0        0        0        0        0        0        0        0
>>              single:        0        0        0        0        0        0        0        0
>>            multiple:        0        0        0        0        0        0        0        0
>>       out_fcs_error:        0        0        0        0        0        0        0        0
>>                late:        0        0        0        0        0        0        0        0
>>        hist_64bytes:        0        6        0       18        0      188        0        0
>>    hist_65_127bytes:        0        8        0      440        0       69        0        0
>>   hist_128_255bytes:        0        0        0      376        0      376        0        0
>>   hist_256_511bytes:        0        0        0        0        0        0        0        0
>>  hist_512_1023bytes:        0        0        0        0        0        0        0        0
>> hist_1024_max_bytes:        0        0        0        0        0        0        0        0
>>      sw_in_discards:        0        0        0        0        0        0        0        0
>>      sw_in_filtered:        0        0        0       18        0        0        0        0
>>     sw_out_filtered:        0        0        0        0        0        0        0        0
>
> So as you say, no unicast traffic to/from the CPU port. The 18
> sw_in_filtered also look suspicious.

Yes, I've also noticed this, but not got anywhere in finding out what 
filtered means---is it a set of rules the PHY applies, if so where do they 
come from?

>> [0] https://github.com/lentinj/linux/tree/wnr854t-support-v0b-net-next-experiment
>
> +	port@3 {
> +			reg = <3>;
> +			label = "cpu";
> +			ethernet = <&eth>;
> +			fixed-link {
> +				speed = <1000>;
> +				full-duplex;
> +			};
>
> You don't need a fixed-link here. The cpu port is automatically
> configured fixed at the highest speed the port will do.
>
> However,
>
> &eth {
>      status = "okay";
> -     ethernet-port@0 {
> -     		speed = <1000>;
> -		duplex = <1>;
> -    };
> };
>
> here you do need the fixed link, otherwise it thinks there is a PHY
> connected and tried to do auto-negotiation. That will never work.
>
> 	  Andrew
>

-- 
Jamie Lentin

[PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

On Sun, 17 Jul 2016, Andrew Lunn wrote:

>> Firstly I've tried to to rebase against net-next[0], but after
>> adding 6131 to mv88e6xxx_of_match, &chip->ppu_work seems to be
>> causing a NULL pointer ooops. I'll assume it's not done yet and
>> ignore net-next for now.
>
> You don't need to modify mv88e6xxx_of_match, the 6131 is compatible
> with the mv88e6085. Just use the compatible string of
> "marvell,mv88e6085". So far, ever Marvell chip we support is
> compatible with the mv88e6085, in terms of probing. Once the driver
> has probed, and read the device ID from a register, it knows enough to
> decide for itself what features the chip has.

Okay, besides the DT mistakes you mention below (changes are pushed to the 
same branch), I've worked out out what my problem was here. The switch was 
probed before the ethernet device is available, so mv88e6xxx_probe() has 
to back out with EPROBE_DEFER at mv88e6xxx_register_switch().

However mv88e6xxx_mdio_unregister() doesn't tidy up fully. The following 
lets me boot, but I'm not really clear what the usleep is helping solve 
and don't like it:

diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 5cb06f7..c46ac54 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -3387,6 +3387,10 @@ static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
  {
  	struct mii_bus *bus = chip->mdio_bus;

+	/* Stop any timers attempting to re-activate the PPU */
+	del_timer(&chip->ppu_timer);
+	usleep_range(1000, 2000);
+
  	mdiobus_unregister(bus);

  	if (chip->mdio_np)

FWIW I now get:

libphy: Fixed MDIO Bus: probed
libphy: mdio_driver_register: mv88e6085
libphy: orion_mdio_bus: probed
mdio_bus f1072004.mdio-bu:00: mdio_device_register
mv88e6085 f1072004.mdio-bu:00: switch 0x106 detected: Marvell 88E6131, revision 6
libphy: /soc/internal-regs/mdio-bus at 72004/switch at 0: probed
mv643xx_eth: MV-643xx 10/100/1000 ethernet driver version 1.4
mv643xx_eth_port mv643xx_eth_port.0 eth0: port 0 with MAC address 00:1b:2f:d5:9d:f4
  . . .
mv88e6085 f1072004.mdio-bu:00: switch 0x106 detected: Marvell 88E6131, revision 6
libphy: /soc/internal-regs/mdio-bus at 72004/switch at 0: probed
DSA: switch 0 0 parsed
DSA: tree 0 parsed
Marvell 88E1121R !soc!internal-re:00: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=!soc!internal-re:00, irq=-1)
Marvell 88E1121R !soc!internal-re:01: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=!soc!internal-re:01, irq=-1)
Marvell 88E1121R !soc!internal-re:02: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=!soc!internal-re:02, irq=-1)
Marvell 88E1112 !soc!internal-re:05: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=!soc!internal-re:05, irq=-1)
Marvell 88E1112 !soc!internal-re:07: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=!soc!internal-re:07, irq=-1)

However, nothing's changed since 4.7-rc7 in terms of getting the switch 
to work.

> In order to get the LEDs working as you want, you are going to have to
> use the new binding. So i would suggest sticking with that.

Some have suggested I should be more worried about being able to shift 
packets than getting the LEDs working, but where's the fun in that? :)

>>> I see you have NET_TAG_DSA, but not NET_TAG_EDSA in your
>>> configuration. Try swapping to EDSA. I even removed support for
>>> TAG_DSA in one of the recent patches.
>>
>> Okay, back to my original wnr854t-support-v0a branch based on 4.6,
>> switched to .tag_protocol = DSA_TAG_PROTO_EDSA and reconfig'ed to
>> add support, but there's no traffic in/out of any port. tcpdump on
>> the underlying ethernet port shows encapsulated broadcast traffic,
>> e.g. this ARP request from enp0:10.100.4.41:
>>
>> 00:15:31.173399 1a:ff:0f:fe:10:22 (oui Unknown) > Broadcast,
>> ethertype Unknown (0xc008), length 64:
>>         0x0000:  0000 0806 0001 0800 0604 0001 1aff 0ffe  ................
>>         0x0010:  1022 0a64 0429 0000 0000 0000 0a64 0437  .".d.).......d.7
>>         0x0020:  0000 0000 0000 0000 0000 0000 0000 0000  ................
>>         0x0030:  0000                                     ..
>>
>> ...but no unicast traffic.
>
> Uh, that does not look like EDSA tagging. Expect an ethertype of
> 0xdada. Also, if you get the latest tcpdump sources, it knows how to
> decode the additional EDSA header which is added.

Okay. Frames sent from the port are EDSA-tagged (which isn't exactly 
surprising), but I'm yet to see the switch receive 0xdada frames. Even 
with the net-next branch which uses DSA_TAG_PROTO_EDSA for all chip types.

However, the ethertype is reflecting the port:-

lan1/5 : ethertype Unknown (0xc028), length 176:
lan2/7 : ethertype Unknown (0xc038), length 176:
lan3/0 : ethertype Unknown (0xc000), length 176:
lan4/1 : ethertype Unknown (0xc008), length 176:
wan/2  : ethertype Unknown (0xc010), length 176:

My other one of these routers, running OpenWRT / Linux 3.3.8, shows the 
same ethertypes, which suggests that the switch is still in DSA tagging 
mode. I'll poke around further and see what I find.

>>> Please also can you get https://github.com/vivien/linux.git commit
>>> 323321875671dfe95b6b91ce051a74d415c7158c which will give you some
>>> extra debug files /sys/kernel/debug/mv88e6xxx.
>>>
>>> The reg, stats, and atu would be interesting.
>>
>> Okay, I rebased 4.7-rc7, ignoring my ropey attempts to configure the
>> LEDs, cherry-picked the above commit. Pushed the result if it's
>> useful[1]. The debugfs code wouldn't patch cleanly onto 4.6 or
>> net-next.
>
> Yes, the debug code is a real pain. Something i'm working on in the
> background, get something generic which is acceptable for mainline.
>
>> On boot up I get:
>>
>> mdio_bus f1072004.mdio-bu: switch 0x106 probed: Marvell 88E6131, revision 6
>> mv643xx_eth_port mv643xx_eth_port.0 eth0: [0]: detected a Marvell 88E6131 switch
>> libphy: dsa slave smi: probed
>> Marvell 88E1121R dsa-0:00:00: attached PHY driver [Marvell 88E1121R]  (mii_bus:phy_addr=dsa-0:00:00, irq=-1)
>> Marvell 88E1121R dsa-0:00:01: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:01, irq=-1)
>> Marvell 88E1121R dsa-0:00:02: attached PHY driver [Marvell 88E1121R] (mii_bus:phy_addr=dsa-0:00:02, irq=-1)
>> Marvell 88E1112 dsa-0:00:05: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:05, irq=-1)
>> Marvell 88E1112 dsa-0:00:07: attached PHY driver [Marvell 88E1112] (mii_bus:phy_addr=dsa-0:00:07, irq=-1)
>
> That looks good, it found the PHYs etc.
>
>> Like above (since 4.7 seems to use DSA_TAG_PROTO_EDSA), there's no
>> traffic visible with tcpdump on lan1/4 (broadcast or unicast), only
>> broadcast traffic on the backing port, eth0.
>>
>> # cat /sys/kernel/debug/mv88e6xxx.0/regs
>>     GLOBAL GLOBAL2 SERDES     0    1    2    3    4    5    6    7
>>  0:  c800       0       0  7080 7d80 7080 6e88 6086 7e86 6086 7086
>>  1:    1b       0       0     3    3    3   3e  403  403  403  403
>>  2:  2fd5       0       0     0    0    0    0    0    0    0    0
>>  3:  9df4    ffff       0  1066 1066 1066 1066 1066 1066 1066 1066
>>  4:  4000     191       0   433  433  433 3533  433  433  433  433
>>  5:  1000      ff       0     0    0    0    0    0    0    0    0
>>  6:  c000    1f0f       0   708  708  708  7f7  708  708  708  708
>>  7:     0    70ff       0     0    0    0    0    0    0    0    0
>>  8:     0    7800       0    83   83   83   c3   83   83   83   83
>>  9:     0       0       0     1    1    1    1    1    1    1    1
>>  a:  f148       0       0     0    0    0    0    0    0    0    0
>>  b:  400f       0       0     1    2    4    0   10   20   40   80
>>  c:     0       0       0     0    0    0    0    0    0    0    0
>>  d:  ffff       0       0     0    0    0    0    0    0    0    0
>>  e:  ffff       0       0     0    0    0    0    0    0    0    0
>>  f:  ffff      77       0     0    0    0    0    0    0    0    0
>> 10:     0       0       0     0    0    0    0    0    0    0    0
>> 11:     0       0       0     0    0    0    0    0    0    0    0
>> 12:  5555       0       0     0    0    0   12    0    0    0    0
>> 13:  5555       0       0     0    0    0    0    0    0    0    0
>> 14:  aaaa       0       0   403  403  403 8403  403  403  403  403
>> 15:  aaaa       0       0     0    0    0    0    0    0    0    0
>> 16:  ffff       0       0   700  70d  700  700  f41  f0e  f41  f02
>> 17:  ffff       0       0     0    0    0    0    0    0    0    0
>> 18:  fa41       0       0  3210 3210 3210 3210 3210 3210 3210 3210
>> 19:  8100       0       0  7654 7654 7654 7654 7654 7654 7654 7654
>> 1a:  3330       0       0     -    -    -    -    -    -    -    -
>> 1b:    f4       0       0     -    -    -    -    -    -    -    -
>> 1c:  f000       0       0     -    -    -    -    -    -    -    -
>> 1d:  5c07       0       0     -    -    -    -    -    -    -    -
>> 1e:     0      f0       0     -    -    -    -    -    -    -    -
>> 1f:     0       0       0     -    -    -    -    -    -    -    -
>>
>> # cat /sys/kernel/debug/mv88e6xxx.0/stats
>>                                (lan4)             (cpu)             (lan1)
>>           Statistic   Port  0  Port  1  Port  2  Port  3  Port  4  Port  5  Port  6  Port  7
>>      in_good_octets:        0     1064        0     1152        0   112155        0        0
>>       in_bad_octets:        0        0        0        0        0        0        0        0
>>          in_unicast:        0        0        0        0        0        0        0        0
>>       in_broadcasts:        0        6        0       18        0      335        0        0
>>       in_multicasts:        0        8        0        0        0      490        0        0
>>            in_pause:        0        0        0        0        0        0        0        0
>>        in_undersize:        0        0        0        0        0        0        0        0
>>        in_fragments:        0        0        0        0        0        0        0        0
>>         in_oversize:        0        0        0        0        0        0        0        0
>>           in_jabber:        0        0        0        0        0        0        0        0
>>         in_rx_error:        0        0        0        0        0        0        0        0
>>        in_fcs_error:        0        0        0        0        0        0        0        0
>>          out_octets:        0        0        0   131331        0        0        0        0
>>         out_unicast:        0        0        0        0        0        0        0        0
>>      out_broadcasts:        0        0        0      558        0        0        0        0
>>      out_multicasts:        0        0        0      498        0        0        0        0
>>           out_pause:        0        0        0        0        0        0        0        0
>>           excessive:        0        0        0        0        0        0        0        0
>>          collisions:        0        0        0        0        0        0        0        0
>>            deferred:        0        0        0        0        0        0        0        0
>>              single:        0        0        0        0        0        0        0        0
>>            multiple:        0        0        0        0        0        0        0        0
>>       out_fcs_error:        0        0        0        0        0        0        0        0
>>                late:        0        0        0        0        0        0        0        0
>>        hist_64bytes:        0        6        0       18        0      188        0        0
>>    hist_65_127bytes:        0        8        0      440        0       69        0        0
>>   hist_128_255bytes:        0        0        0      376        0      376        0        0
>>   hist_256_511bytes:        0        0        0        0        0        0        0        0
>>  hist_512_1023bytes:        0        0        0        0        0        0        0        0
>> hist_1024_max_bytes:        0        0        0        0        0        0        0        0
>>      sw_in_discards:        0        0        0        0        0        0        0        0
>>      sw_in_filtered:        0        0        0       18        0        0        0        0
>>     sw_out_filtered:        0        0        0        0        0        0        0        0
>
> So as you say, no unicast traffic to/from the CPU port. The 18
> sw_in_filtered also look suspicious.

Yes, I've also noticed this, but not got anywhere in finding out what 
filtered means---is it a set of rules the PHY applies, if so where do they 
come from?

>> [0] https://github.com/lentinj/linux/tree/wnr854t-support-v0b-net-next-experiment
>
> +	port at 3 {
> +			reg = <3>;
> +			label = "cpu";
> +			ethernet = <&eth>;
> +			fixed-link {
> +				speed = <1000>;
> +				full-duplex;
> +			};
>
> You don't need a fixed-link here. The cpu port is automatically
> configured fixed at the highest speed the port will do.
>
> However,
>
> &eth {
>      status = "okay";
> -     ethernet-port at 0 {
> -     		speed = <1000>;
> -		duplex = <1>;
> -    };
> };
>
> here you do need the fixed link, otherwise it thinks there is a PHY
> connected and tried to do auto-negotiation. That will never work.
>
> 	  Andrew
>

-- 
Jamie Lentin

Re: [PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Andrew Lunn]

> However, the ethertype is reflecting the port:-
> 
> lan1/5 : ethertype Unknown (0xc028), length 176:
> lan2/7 : ethertype Unknown (0xc038), length 176:
> lan3/0 : ethertype Unknown (0xc000), length 176:
> lan4/1 : ethertype Unknown (0xc008), length 176:
> wan/2  : ethertype Unknown (0xc010), length 176:
> 
> My other one of these routers, running OpenWRT / Linux 3.3.8, shows
> the same ethertypes, which suggests that the switch is still in DSA
> tagging mode. I'll poke around further and see what I find.

O.K. With this wrong, nothing is going to work.

I will check that the 6131 actually supports EDSA!

  Andrew

[PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Andrew Lunn]

> However, the ethertype is reflecting the port:-
> 
> lan1/5 : ethertype Unknown (0xc028), length 176:
> lan2/7 : ethertype Unknown (0xc038), length 176:
> lan3/0 : ethertype Unknown (0xc000), length 176:
> lan4/1 : ethertype Unknown (0xc008), length 176:
> wan/2  : ethertype Unknown (0xc010), length 176:
> 
> My other one of these routers, running OpenWRT / Linux 3.3.8, shows
> the same ethertypes, which suggests that the switch is still in DSA
> tagging mode. I'll poke around further and see what I find.

O.K. With this wrong, nothing is going to work.

I will check that the 6131 actually supports EDSA!

  Andrew

Re: [PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Andrew Lunn]

[Reducing the Cc: list a bit to networking people]

> Okay. Frames sent from the port are EDSA-tagged (which isn't exactly
> surprising), but I'm yet to see the switch receive 0xdada frames.
> Even with the net-next branch which uses DSA_TAG_PROTO_EDSA for all
> chip types.
> 
> However, the ethertype is reflecting the port:-
> 
> lan1/5 : ethertype Unknown (0xc028), length 176:
> lan2/7 : ethertype Unknown (0xc038), length 176:
> lan3/0 : ethertype Unknown (0xc000), length 176:
> lan4/1 : ethertype Unknown (0xc008), length 176:
> wan/2  : ethertype Unknown (0xc010), length 176:

O.K, we broke it :-(

The 6185 does not support EDSA, only DSA.

Vivien, this is going to cause us problems. We need two different
dsa_switch_driver structures, one for EDSA capable devices, and one
for those which are not.

Or we do something more radical, like add a driver callback to return
the tagging protocol, rather than hard code it in the structure? We
can then use a capability flag.

    Andrew

Re: [PATCH v0 00/10] Convert Netgear WNR854T to devicetree

[Vivien Didelot]

Hi Andrew,

Andrew Lunn <andrew@lunn.ch> writes:

> [Reducing the Cc: list a bit to networking people]
>
>> Okay. Frames sent from the port are EDSA-tagged (which isn't exactly
>> surprising), but I'm yet to see the switch receive 0xdada frames.
>> Even with the net-next branch which uses DSA_TAG_PROTO_EDSA for all
>> chip types.
>> 
>> However, the ethertype is reflecting the port:-
>> 
>> lan1/5 : ethertype Unknown (0xc028), length 176:
>> lan2/7 : ethertype Unknown (0xc038), length 176:
>> lan3/0 : ethertype Unknown (0xc000), length 176:
>> lan4/1 : ethertype Unknown (0xc008), length 176:
>> wan/2  : ethertype Unknown (0xc010), length 176:
>
> O.K, we broke it :-(
>
> The 6185 does not support EDSA, only DSA.

I'm wondering if EDSA could be simulated on 6185 (only) with the
CoreTagType register (0x19) and DoubleTag bit in Port Control (0x04)...

> Or we do something more radical, like add a driver callback to return
> the tagging protocol, rather than hard code it in the structure? We
> can then use a capability flag.

The driver callback is the way to go. The supported tag format is
identifiable via the register layout. 6352 and newer have a 2-bit
FrameMode in Port Control (0x04), while 6185 has a single DSA_Tag bit.

A new switch operation can return the tag protocol enum, or an exposed
xmit/recv pair from net/dsa/tag_*.c, which must be used by the CPU.

Note: 88E6060 (which is likely to be supported by mv88e6xxx) has the
same issue and requires this, since it uses the Trailer tagging format.

Thanks,

        Vivien

[PATCH 0/8] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

This is an attempt to resurrect the mainline WNR854T support and
convert to device tree. The major change since v0 is the embedded
ethernet switch is now functional, thanks to Andrew Lunn, making the
device actually useful. Full list of changes:

* The DT definition for the switch in this patchset has changed to
match the 88e6131 DSA driver currently in net-next, and all
now-superflous attempts at fixing up the DSA driver have been removed
from this patchset.

* Use Flash partition scheme from original netgear Linux image (but
keeping the uboot/uboot_env split) instead of the partition scheme from
the old non-DT support, which didn't match either Netgear's layout,
u-boot or openWRT. NB: I've no copy of the original flash contents
(Netgear's firmware images only contain a squashfs image of the rootfs),
so I can't confirm the other partitions are accurately named.

* Set NOR Flash bank-width to correct value

* Reassign defconfig entries pointing at CONFIG_MACH_WNR854T (old
non-DT support) to CONFIG_MACH_WNR854T_DT

* Move eth0 pinctrl definitions and assignment to
orion5x-mv88f5181.dtsi [Andrew Lunn]

* Get the copyright year right [Rob Herring]

* Reformat pinctrl docs to one-compatible-string-per-line [Rob Herring]

* Rename reset button pinctrl to pmx_reset_button [Andrew Lunn]

* Move pmx_ge pinctrl definition to SoC include [Andrew Lunn]

* Put flash partitions into their own node [Andrew Lunn]

* Make LED names standards-compliant [Andrew Lunn]

* Use standard stdout-path definition for bootargs [Andrew Lunn]

The patches are also available at https://github.com/lentinj/linux
wnr854t-support-v1 - this is based on net-next to use in the
88e6131 changes there, and applies the patch in
https://lkml.org/lkml/2016/8/3/93 to allow the device to boot.

Thanks,

Jamie Lentin (8):
  arm: orion5x: Add documentation for SoC and board bindings
  arm: orion5x: Add clk support for mv88f5181
  arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181
  arm: orion5x: Alias uart0 to serial0 for all orion5x
  arm: orion5x: Add DT include for mv88f5181
  arm: orion5x: Add DT-based support for Netgear WNR854T
  arm: orion5x: Remove old non-DT-based WNR854T support
  arm: orion5x: Configure WNR854T ethernet PHY LEDs

 .../bindings/arm/marvell/marvell,orion5x.txt       |  25 ++
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   1 +
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |   4 +-
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           |  49 ++++
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 263 +++++++++++++++++++++
 arch/arm/boot/dts/orion5x.dtsi                     |   1 +
 arch/arm/configs/multi_v5_defconfig                |   2 +-
 arch/arm/configs/mvebu_v5_defconfig                |   2 +-
 arch/arm/configs/orion5x_defconfig                 |   2 +-
 arch/arm/mach-orion5x/Kconfig                      |   4 +-
 arch/arm/mach-orion5x/Makefile                     |   2 +-
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++
 arch/arm/mach-orion5x/wnr854t-setup.c              | 185 ---------------
 drivers/clk/mvebu/orion.c                          |  70 ++++++
 drivers/pinctrl/mvebu/pinctrl-orion.c              |  23 +-
 16 files changed, 509 insertions(+), 203 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
 delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c

-- 
2.8.1

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[PATCH 0/8] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

This is an attempt to resurrect the mainline WNR854T support and
convert to device tree. The major change since v0 is the embedded
ethernet switch is now functional, thanks to Andrew Lunn, making the
device actually useful. Full list of changes:

* The DT definition for the switch in this patchset has changed to
match the 88e6131 DSA driver currently in net-next, and all
now-superflous attempts at fixing up the DSA driver have been removed
from this patchset.

* Use Flash partition scheme from original netgear Linux image (but
keeping the uboot/uboot_env split) instead of the partition scheme from
the old non-DT support, which didn't match either Netgear's layout,
u-boot or openWRT. NB: I've no copy of the original flash contents
(Netgear's firmware images only contain a squashfs image of the rootfs),
so I can't confirm the other partitions are accurately named.

* Set NOR Flash bank-width to correct value

* Reassign defconfig entries pointing at CONFIG_MACH_WNR854T (old
non-DT support) to CONFIG_MACH_WNR854T_DT

* Move eth0 pinctrl definitions and assignment to
orion5x-mv88f5181.dtsi [Andrew Lunn]

* Get the copyright year right [Rob Herring]

* Reformat pinctrl docs to one-compatible-string-per-line [Rob Herring]

* Rename reset button pinctrl to pmx_reset_button [Andrew Lunn]

* Move pmx_ge pinctrl definition to SoC include [Andrew Lunn]

* Put flash partitions into their own node [Andrew Lunn]

* Make LED names standards-compliant [Andrew Lunn]

* Use standard stdout-path definition for bootargs [Andrew Lunn]

The patches are also available at https://github.com/lentinj/linux
wnr854t-support-v1 - this is based on net-next to use in the
88e6131 changes there, and applies the patch in
https://lkml.org/lkml/2016/8/3/93 to allow the device to boot.

Thanks,

Jamie Lentin (8):
  arm: orion5x: Add documentation for SoC and board bindings
  arm: orion5x: Add clk support for mv88f5181
  arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181
  arm: orion5x: Alias uart0 to serial0 for all orion5x
  arm: orion5x: Add DT include for mv88f5181
  arm: orion5x: Add DT-based support for Netgear WNR854T
  arm: orion5x: Remove old non-DT-based WNR854T support
  arm: orion5x: Configure WNR854T ethernet PHY LEDs

 .../bindings/arm/marvell/marvell,orion5x.txt       |  25 ++
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   1 +
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |   4 +-
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           |  49 ++++
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 263 +++++++++++++++++++++
 arch/arm/boot/dts/orion5x.dtsi                     |   1 +
 arch/arm/configs/multi_v5_defconfig                |   2 +-
 arch/arm/configs/mvebu_v5_defconfig                |   2 +-
 arch/arm/configs/orion5x_defconfig                 |   2 +-
 arch/arm/mach-orion5x/Kconfig                      |   4 +-
 arch/arm/mach-orion5x/Makefile                     |   2 +-
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++
 arch/arm/mach-orion5x/wnr854t-setup.c              | 185 ---------------
 drivers/clk/mvebu/orion.c                          |  70 ++++++
 drivers/pinctrl/mvebu/pinctrl-orion.c              |  23 +-
 16 files changed, 509 insertions(+), 203 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
 delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c

-- 
2.8.1

[PATCH 1/8] arm: orion5x: Add documentation for SoC and board bindings

[Jamie Lentin]

Copy the format for kirkwood/dove to orion5x

Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
new file mode 100644
index 0000000..a888011
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -0,0 +1,23 @@
+Marvell Orion SoC Family Device Tree Bindings
+---------------------------------------------
+
+Boards with a SoC of the Marvell Orion family, eg 88f5181
+
+* Required root node properties:
+compatible: must contain "marvell,orion5x"
+
+In addition, the above compatible shall be extended with the specific
+SoC. Currently known SoC compatibles are:
+
+"marvell,orion5x-88f5182"
+
+And in addition, the compatible shall be extended with the specific
+board. Currently known boards are:
+
+"buffalo,lsgl"
+"buffalo,lswsgl"
+"buffalo,lswtgl"
+"lacie,ethernet-disk-mini-v2"
+"lacie,d2-network"
+"marvell,rd-88f5182-nas"
+"maxtor,shared-storage-2"
-- 
2.8.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH 1/8] arm: orion5x: Add documentation for SoC and board bindings

[Jamie Lentin]

Copy the format for kirkwood/dove to orion5x

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
new file mode 100644
index 0000000..a888011
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -0,0 +1,23 @@
+Marvell Orion SoC Family Device Tree Bindings
+---------------------------------------------
+
+Boards with a SoC of the Marvell Orion family, eg 88f5181
+
+* Required root node properties:
+compatible: must contain "marvell,orion5x"
+
+In addition, the above compatible shall be extended with the specific
+SoC. Currently known SoC compatibles are:
+
+"marvell,orion5x-88f5182"
+
+And in addition, the compatible shall be extended with the specific
+board. Currently known boards are:
+
+"buffalo,lsgl"
+"buffalo,lswsgl"
+"buffalo,lswtgl"
+"lacie,ethernet-disk-mini-v2"
+"lacie,d2-network"
+"marvell,rd-88f5182-nas"
+"maxtor,shared-storage-2"
-- 
2.8.1

[PATCH 2/8] arm: orion5x: Add clk support for mv88f5181

[Jamie Lentin]

Referring to the u-boot sources for the Netgear WNR854T, add support
for the mv88f5181.

Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |  1 +
 drivers/clk/mvebu/orion.c                          | 70 ++++++++++++++++++++++
 2 files changed, 71 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 670c2af..eb985a6 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -52,6 +52,7 @@ Required properties:
 	"marvell,dove-core-clock" - for Dove SoC core clocks
 	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
 	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
+	"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
 	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
 	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
 	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
index fd12956..a6e5bee 100644
--- a/drivers/clk/mvebu/orion.c
+++ b/drivers/clk/mvebu/orion.c
@@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
 };
 
 /*
+ * Orion 5181
+ */
+
+#define SAR_MV88F5181_TCLK_FREQ      8
+#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
+
+static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
+		SAR_MV88F5181_TCLK_FREQ_MASK;
+	if (opt == 0)
+		return 133333333;
+	else if (opt == 1)
+		return 150000000;
+	else if (opt == 2)
+		return 166666667;
+	else
+		return 0;
+}
+
+#define SAR_MV88F5181_CPU_FREQ       4
+#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
+
+static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0)
+		return 333333333;
+	else if (opt == 1 || opt == 2)
+		return 400000000;
+	else if (opt == 3)
+		return 500000000;
+	else
+		return 0;
+}
+
+static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0 || opt == 1) {
+		*mult = 1;
+		*div  = 2;
+	} else if (opt == 2 || opt == 3) {
+		*mult = 1;
+		*div  = 3;
+	} else {
+		*mult = 0;
+		*div  = 1;
+	}
+}
+
+static const struct coreclk_soc_desc mv88f5181_coreclks = {
+	.get_tclk_freq = mv88f5181_get_tclk_freq,
+	.get_cpu_freq = mv88f5181_get_cpu_freq,
+	.get_clk_ratio = mv88f5181_get_clk_ratio,
+	.ratios = orion_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
+};
+
+static void __init mv88f5181_clk_init(struct device_node *np)
+{
+	return mvebu_coreclk_setup(np, &mv88f5181_coreclks);
+}
+
+CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);
+
+/*
  * Orion 5182
  */
 
-- 
2.8.1

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[PATCH 2/8] arm: orion5x: Add clk support for mv88f5181

[Jamie Lentin]

Referring to the u-boot sources for the Netgear WNR854T, add support
for the mv88f5181.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |  1 +
 drivers/clk/mvebu/orion.c                          | 70 ++++++++++++++++++++++
 2 files changed, 71 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 670c2af..eb985a6 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -52,6 +52,7 @@ Required properties:
 	"marvell,dove-core-clock" - for Dove SoC core clocks
 	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
 	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
+	"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
 	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
 	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
 	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
index fd12956..a6e5bee 100644
--- a/drivers/clk/mvebu/orion.c
+++ b/drivers/clk/mvebu/orion.c
@@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
 };
 
 /*
+ * Orion 5181
+ */
+
+#define SAR_MV88F5181_TCLK_FREQ      8
+#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
+
+static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
+		SAR_MV88F5181_TCLK_FREQ_MASK;
+	if (opt == 0)
+		return 133333333;
+	else if (opt == 1)
+		return 150000000;
+	else if (opt == 2)
+		return 166666667;
+	else
+		return 0;
+}
+
+#define SAR_MV88F5181_CPU_FREQ       4
+#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
+
+static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0)
+		return 333333333;
+	else if (opt == 1 || opt == 2)
+		return 400000000;
+	else if (opt == 3)
+		return 500000000;
+	else
+		return 0;
+}
+
+static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+		SAR_MV88F5181_CPU_FREQ_MASK;
+	if (opt == 0 || opt == 1) {
+		*mult = 1;
+		*div  = 2;
+	} else if (opt == 2 || opt == 3) {
+		*mult = 1;
+		*div  = 3;
+	} else {
+		*mult = 0;
+		*div  = 1;
+	}
+}
+
+static const struct coreclk_soc_desc mv88f5181_coreclks = {
+	.get_tclk_freq = mv88f5181_get_tclk_freq,
+	.get_cpu_freq = mv88f5181_get_cpu_freq,
+	.get_clk_ratio = mv88f5181_get_clk_ratio,
+	.ratios = orion_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
+};
+
+static void __init mv88f5181_clk_init(struct device_node *np)
+{
+	return mvebu_coreclk_setup(np, &mv88f5181_coreclks);
+}
+
+CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);
+
+/*
  * Orion 5182
  */
 
-- 
2.8.1

Re: [PATCH 2/8] arm: orion5x: Add clk support for mv88f5181

[LABBE Corentin]

Hello

I have some minor comments below

[...]
> +
> +static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
> +		SAR_MV88F5181_TCLK_FREQ_MASK;

Checkpatch complain about a missing blank line after declaration.
And spliting the read and the & operation will prevent this line breaking

> +	if (opt == 0)
> +		return 133333333;
> +	else if (opt == 1)
> +		return 150000000;
> +	else if (opt == 2)
> +		return 166666667;
> +	else
> +		return 0;
> +}

Why not using a switch here ?

> +
> +#define SAR_MV88F5181_CPU_FREQ       4
> +#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
> +
> +static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
> +		SAR_MV88F5181_CPU_FREQ_MASK;
> +	if (opt == 0)
> +		return 333333333;
> +	else if (opt == 1 || opt == 2)
> +		return 400000000;
> +	else if (opt == 3)
> +		return 500000000;
> +	else
> +		return 0;
> +}

Same comments

> +
> +static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
> +					   int *mult, int *div)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
> +		SAR_MV88F5181_CPU_FREQ_MASK;
> +	if (opt == 0 || opt == 1) {
> +		*mult = 1;
> +		*div  = 2;
> +	} else if (opt == 2 || opt == 3) {
> +		*mult = 1;
> +		*div  = 3;
> +	} else {
> +		*mult = 0;
> +		*div  = 1;
> +	}
> +}

Same comments

Regards

--
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[PATCH 2/8] arm: orion5x: Add clk support for mv88f5181

[LABBE Corentin]

Hello

I have some minor comments below

[...]
> +
> +static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
> +		SAR_MV88F5181_TCLK_FREQ_MASK;

Checkpatch complain about a missing blank line after declaration.
And spliting the read and the & operation will prevent this line breaking

> +	if (opt == 0)
> +		return 133333333;
> +	else if (opt == 1)
> +		return 150000000;
> +	else if (opt == 2)
> +		return 166666667;
> +	else
> +		return 0;
> +}

Why not using a switch here ?

> +
> +#define SAR_MV88F5181_CPU_FREQ       4
> +#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
> +
> +static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
> +		SAR_MV88F5181_CPU_FREQ_MASK;
> +	if (opt == 0)
> +		return 333333333;
> +	else if (opt == 1 || opt == 2)
> +		return 400000000;
> +	else if (opt == 3)
> +		return 500000000;
> +	else
> +		return 0;
> +}

Same comments

> +
> +static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
> +					   int *mult, int *div)
> +{
> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
> +		SAR_MV88F5181_CPU_FREQ_MASK;
> +	if (opt == 0 || opt == 1) {
> +		*mult = 1;
> +		*div  = 2;
> +	} else if (opt == 2 || opt == 3) {
> +		*mult = 1;
> +		*div  = 3;
> +	} else {
> +		*mult = 0;
> +		*div  = 1;
> +	}
> +}

Same comments

Regards

Re: [PATCH 2/8] arm: orion5x: Add clk support for mv88f5181

[Jamie Lentin]

On Fri, 26 Aug 2016, LABBE Corentin wrote:

> Hello
>
> I have some minor comments below
>
> [...]
>> +
>> +static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
>> +{
>> +	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
>> +		SAR_MV88F5181_TCLK_FREQ_MASK;
>
> Checkpatch complain about a missing blank line after declaration.
> And spliting the read and the & operation will prevent this line breaking

It isn't here, although I'm not arguing the line is missing. Is there an 
extra switch I'm missing?

>> +	if (opt == 0)
>> +		return 133333333;
>> +	else if (opt == 1)
>> +		return 150000000;
>> +	else if (opt == 2)
>> +		return 166666667;
>> +	else
>> +		return 0;
>> +}
>
> Why not using a switch here ?

If you look at this in context[0], this is one of several code-as-config 
declarations, none of which use a switch. IMO it's more useful to make the 
similarity as obvious as possible if this is ever refactored.

Obviously the rest of the file could also be refactored with switch 
statements, but instead of doing that it seems more tempting to move the 
config into the DT binding, e.g.

   cpu-freq-addr = <4>;
   cpu-freq-mask = <0xf>;
   cpu-freqs = <0 333333333 400000000 400000000 500000000>;
   clk-ratios = <0 1 1 2 1 2 1 3 1 3>;

...this is completely off the top of my head mind, so could easily be 
missing something obvious / some prior art.

[0] http://lxr.free-electrons.com/source/drivers/clk/mvebu/orion.c

>> +
>> +#define SAR_MV88F5181_CPU_FREQ       4
>> +#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
>> +
>> +static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
>> +{
>> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
>> +		SAR_MV88F5181_CPU_FREQ_MASK;
>> +	if (opt == 0)
>> +		return 333333333;
>> +	else if (opt == 1 || opt == 2)
>> +		return 400000000;
>> +	else if (opt == 3)
>> +		return 500000000;
>> +	else
>> +		return 0;
>> +}
>
> Same comments
>
>> +
>> +static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
>> +					   int *mult, int *div)
>> +{
>> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
>> +		SAR_MV88F5181_CPU_FREQ_MASK;
>> +	if (opt == 0 || opt == 1) {
>> +		*mult = 1;
>> +		*div  = 2;
>> +	} else if (opt == 2 || opt == 3) {
>> +		*mult = 1;
>> +		*div  = 3;
>> +	} else {
>> +		*mult = 0;
>> +		*div  = 1;
>> +	}
>> +}
>
> Same comments
>
> Regards
>
>

-- 
Jamie Lentin
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH 2/8] arm: orion5x: Add clk support for mv88f5181

[Jamie Lentin]

On Fri, 26 Aug 2016, LABBE Corentin wrote:

> Hello
>
> I have some minor comments below
>
> [...]
>> +
>> +static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
>> +{
>> +	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
>> +		SAR_MV88F5181_TCLK_FREQ_MASK;
>
> Checkpatch complain about a missing blank line after declaration.
> And spliting the read and the & operation will prevent this line breaking

It isn't here, although I'm not arguing the line is missing. Is there an 
extra switch I'm missing?

>> +	if (opt == 0)
>> +		return 133333333;
>> +	else if (opt == 1)
>> +		return 150000000;
>> +	else if (opt == 2)
>> +		return 166666667;
>> +	else
>> +		return 0;
>> +}
>
> Why not using a switch here ?

If you look at this in context[0], this is one of several code-as-config 
declarations, none of which use a switch. IMO it's more useful to make the 
similarity as obvious as possible if this is ever refactored.

Obviously the rest of the file could also be refactored with switch 
statements, but instead of doing that it seems more tempting to move the 
config into the DT binding, e.g.

   cpu-freq-addr = <4>;
   cpu-freq-mask = <0xf>;
   cpu-freqs = <0 333333333 400000000 400000000 500000000>;
   clk-ratios = <0 1 1 2 1 2 1 3 1 3>;

...this is completely off the top of my head mind, so could easily be 
missing something obvious / some prior art.

[0] http://lxr.free-electrons.com/source/drivers/clk/mvebu/orion.c

>> +
>> +#define SAR_MV88F5181_CPU_FREQ       4
>> +#define SAR_MV88F5181_CPU_FREQ_MASK  0xf
>> +
>> +static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
>> +{
>> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
>> +		SAR_MV88F5181_CPU_FREQ_MASK;
>> +	if (opt == 0)
>> +		return 333333333;
>> +	else if (opt == 1 || opt == 2)
>> +		return 400000000;
>> +	else if (opt == 3)
>> +		return 500000000;
>> +	else
>> +		return 0;
>> +}
>
> Same comments
>
>> +
>> +static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
>> +					   int *mult, int *div)
>> +{
>> +	u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
>> +		SAR_MV88F5181_CPU_FREQ_MASK;
>> +	if (opt == 0 || opt == 1) {
>> +		*mult = 1;
>> +		*div  = 2;
>> +	} else if (opt == 2 || opt == 3) {
>> +		*mult = 1;
>> +		*div  = 3;
>> +	} else {
>> +		*mult = 0;
>> +		*div  = 1;
>> +	}
>> +}
>
> Same comments
>
> Regards
>
>

-- 
Jamie Lentin

Re: [PATCH 2/8] arm: orion5x: Add clk support for mv88f5181

[Andrew Lunn]

On Fri, Aug 26, 2016 at 01:24:18PM +0100, Jamie Lentin wrote:
> On Fri, 26 Aug 2016, LABBE Corentin wrote:
> 
> >Hello
> >
> >I have some minor comments below
> >
> >[...]
> >>+
> >>+static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
> >>+{
> >>+	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
> >>+		SAR_MV88F5181_TCLK_FREQ_MASK;
> >
> >Checkpatch complain about a missing blank line after declaration.
> >And spliting the read and the & operation will prevent this line breaking
> 
> It isn't here, although I'm not arguing the line is missing. Is
> there an extra switch I'm missing?

I agree it is a false positive.

Probably the best action is to report it to the checkpatch people.

> >>+	if (opt == 0)
> >>+		return 133333333;
> >>+	else if (opt == 1)
> >>+		return 150000000;
> >>+	else if (opt == 2)
> >>+		return 166666667;
> >>+	else
> >>+		return 0;
> >>+}
> >
> >Why not using a switch here ?
> 
> If you look at this in context[0], this is one of several
> code-as-config declarations, none of which use a switch. IMO it's
> more useful to make the similarity as obvious as possible if this is
> ever refactored.

Agreed. Please leave it as is, and if anybody does care about this,
they can submit a followup patch refactoring all instances.
 
	Andrew

[PATCH 2/8] arm: orion5x: Add clk support for mv88f5181

[Andrew Lunn]

On Fri, Aug 26, 2016 at 01:24:18PM +0100, Jamie Lentin wrote:
> On Fri, 26 Aug 2016, LABBE Corentin wrote:
> 
> >Hello
> >
> >I have some minor comments below
> >
> >[...]
> >>+
> >>+static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
> >>+{
> >>+	u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
> >>+		SAR_MV88F5181_TCLK_FREQ_MASK;
> >
> >Checkpatch complain about a missing blank line after declaration.
> >And spliting the read and the & operation will prevent this line breaking
> 
> It isn't here, although I'm not arguing the line is missing. Is
> there an extra switch I'm missing?

I agree it is a false positive.

Probably the best action is to report it to the checkpatch people.

> >>+	if (opt == 0)
> >>+		return 133333333;
> >>+	else if (opt == 1)
> >>+		return 150000000;
> >>+	else if (opt == 2)
> >>+		return 166666667;
> >>+	else
> >>+		return 0;
> >>+}
> >
> >Why not using a switch here ?
> 
> If you look at this in context[0], this is one of several
> code-as-config declarations, none of which use a switch. IMO it's
> more useful to make the similarity as obvious as possible if this is
> ever refactored.

Agreed. Please leave it as is, and if anybody does care about this,
they can submit a followup patch refactoring all instances.
 
	Andrew

[PATCH 3/8] arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181

[Jamie Lentin]

As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
pinctrl level, so re-use the definitions for both.

Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  4 +++-
 drivers/pinctrl/mvebu/pinctrl-orion.c              | 23 +++++++++++-----------
 2 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
index 27570a3..ec8aa3c 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
@@ -4,7 +4,9 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
 part and usage.
 
 Required properties:
-- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
+- compatible: "marvell,88f5181-pinctrl",
+              "marvell,88f5181l-pinctrl",
+              "marvell,88f5182-pinctrl",
               "marvell,88f5281-pinctrl"
 
 - reg: two register areas, the first one describing the first two
diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c
index 345c3df..84e1441 100644
--- a/drivers/pinctrl/mvebu/pinctrl-orion.c
+++ b/drivers/pinctrl/mvebu/pinctrl-orion.c
@@ -64,11 +64,11 @@ static int orion_mpp_ctrl_set(unsigned pid, unsigned long config)
 	return 0;
 }
 
-#define V(f5181l, f5182, f5281) \
-	((f5181l << 0) | (f5182 << 1) | (f5281 << 2))
+#define V(f5181, f5182, f5281) \
+	((f5181 << 0) | (f5182 << 1) | (f5281 << 2))
 
 enum orion_variant {
-	V_5181L = V(1, 0, 0),
+	V_5181  = V(1, 0, 0),
 	V_5182  = V(0, 1, 0),
 	V_5281  = V(0, 0, 1),
 	V_ALL   = V(1, 1, 1),
@@ -103,13 +103,13 @@ static struct mvebu_mpp_mode orion_mpp_modes[] = {
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
 		 MPP_VAR_FUNCTION(0x2, "pci", "req5",       V_ALL),
 		 MPP_VAR_FUNCTION(0x4, "nand", "re0",       V_5182 | V_5281),
-		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
 		 MPP_VAR_FUNCTION(0x5, "sata0", "act",      V_5182)),
 	MPP_MODE(7,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
 		 MPP_VAR_FUNCTION(0x2, "pci", "gnt5",       V_ALL),
 		 MPP_VAR_FUNCTION(0x4, "nand", "we0",       V_5182 | V_5281),
-		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
 		 MPP_VAR_FUNCTION(0x5, "sata1", "act",      V_5182)),
 	MPP_MODE(8,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
@@ -165,7 +165,7 @@ static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
 	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
 };
 
-static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
+static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
 	MPP_GPIO_RANGE(0, 0, 0, 16),
 };
 
@@ -177,14 +177,14 @@ static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
 	MPP_GPIO_RANGE(0, 0, 0, 16),
 };
 
-static struct mvebu_pinctrl_soc_info mv88f5181l_info = {
-	.variant = V_5181L,
+static struct mvebu_pinctrl_soc_info mv88f5181_info = {
+	.variant = V_5181,
 	.controls = orion_mpp_controls,
 	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
 	.modes = orion_mpp_modes,
 	.nmodes = ARRAY_SIZE(orion_mpp_modes),
-	.gpioranges = mv88f5181l_gpio_ranges,
-	.ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges),
+	.gpioranges = mv88f5181_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
 };
 
 static struct mvebu_pinctrl_soc_info mv88f5182_info = {
@@ -212,7 +212,8 @@ static struct mvebu_pinctrl_soc_info mv88f5281_info = {
  * muxing, they are identical.
  */
 static const struct of_device_id orion_pinctrl_of_match[] = {
-	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info },
+	{ .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
+	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
 	{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
 	{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
 	{ }
-- 
2.8.1

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[PATCH 3/8] arm: orion5x: Generalise mv88f5181l pinctrl support for 88f5181

[Jamie Lentin]

As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the
pinctrl level, so re-use the definitions for both.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  4 +++-
 drivers/pinctrl/mvebu/pinctrl-orion.c              | 23 +++++++++++-----------
 2 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
index 27570a3..ec8aa3c 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt
@@ -4,7 +4,9 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
 part and usage.
 
 Required properties:
-- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
+- compatible: "marvell,88f5181-pinctrl",
+              "marvell,88f5181l-pinctrl",
+              "marvell,88f5182-pinctrl",
               "marvell,88f5281-pinctrl"
 
 - reg: two register areas, the first one describing the first two
diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c
index 345c3df..84e1441 100644
--- a/drivers/pinctrl/mvebu/pinctrl-orion.c
+++ b/drivers/pinctrl/mvebu/pinctrl-orion.c
@@ -64,11 +64,11 @@ static int orion_mpp_ctrl_set(unsigned pid, unsigned long config)
 	return 0;
 }
 
-#define V(f5181l, f5182, f5281) \
-	((f5181l << 0) | (f5182 << 1) | (f5281 << 2))
+#define V(f5181, f5182, f5281) \
+	((f5181 << 0) | (f5182 << 1) | (f5281 << 2))
 
 enum orion_variant {
-	V_5181L = V(1, 0, 0),
+	V_5181  = V(1, 0, 0),
 	V_5182  = V(0, 1, 0),
 	V_5281  = V(0, 0, 1),
 	V_ALL   = V(1, 1, 1),
@@ -103,13 +103,13 @@ static struct mvebu_mpp_mode orion_mpp_modes[] = {
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
 		 MPP_VAR_FUNCTION(0x2, "pci", "req5",       V_ALL),
 		 MPP_VAR_FUNCTION(0x4, "nand", "re0",       V_5182 | V_5281),
-		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
 		 MPP_VAR_FUNCTION(0x5, "sata0", "act",      V_5182)),
 	MPP_MODE(7,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
 		 MPP_VAR_FUNCTION(0x2, "pci", "gnt5",       V_ALL),
 		 MPP_VAR_FUNCTION(0x4, "nand", "we0",       V_5182 | V_5281),
-		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
 		 MPP_VAR_FUNCTION(0x5, "sata1", "act",      V_5182)),
 	MPP_MODE(8,
 		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
@@ -165,7 +165,7 @@ static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
 	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
 };
 
-static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
+static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
 	MPP_GPIO_RANGE(0, 0, 0, 16),
 };
 
@@ -177,14 +177,14 @@ static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
 	MPP_GPIO_RANGE(0, 0, 0, 16),
 };
 
-static struct mvebu_pinctrl_soc_info mv88f5181l_info = {
-	.variant = V_5181L,
+static struct mvebu_pinctrl_soc_info mv88f5181_info = {
+	.variant = V_5181,
 	.controls = orion_mpp_controls,
 	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
 	.modes = orion_mpp_modes,
 	.nmodes = ARRAY_SIZE(orion_mpp_modes),
-	.gpioranges = mv88f5181l_gpio_ranges,
-	.ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges),
+	.gpioranges = mv88f5181_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
 };
 
 static struct mvebu_pinctrl_soc_info mv88f5182_info = {
@@ -212,7 +212,8 @@ static struct mvebu_pinctrl_soc_info mv88f5281_info = {
  * muxing, they are identical.
  */
 static const struct of_device_id orion_pinctrl_of_match[] = {
-	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info },
+	{ .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
+	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
 	{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
 	{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
 	{ }
-- 
2.8.1

[PATCH 4/8] arm: orion5x: Alias uart0 to serial0 for all orion5x

[Jamie Lentin]

Allowing us to specify boot console in a standard manner in board DTs.

Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
---
 arch/arm/boot/dts/orion5x.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index fbccfbb..001613d 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -17,6 +17,7 @@
 
 	aliases {
 		gpio0 = &gpio0;
+		serial0 = &uart0;
 	};
 
 	soc {
-- 
2.8.1

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[PATCH 4/8] arm: orion5x: Alias uart0 to serial0 for all orion5x

[Jamie Lentin]

Allowing us to specify boot console in a standard manner in board DTs.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 arch/arm/boot/dts/orion5x.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index fbccfbb..001613d 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -17,6 +17,7 @@
 
 	aliases {
 		gpio0 = &gpio0;
+		serial0 = &uart0;
 	};
 
 	soc {
-- 
2.8.1

Re: [PATCH 4/8] arm: orion5x: Alias uart0 to serial0 for all orion5x

[Andrew Lunn]

On Fri, Aug 26, 2016 at 10:21:00AM +0100, Jamie Lentin wrote:
> Allowing us to specify boot console in a standard manner in board DTs.
> 
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>

Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>

    Andrew
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[PATCH 4/8] arm: orion5x: Alias uart0 to serial0 for all orion5x

[Andrew Lunn]

On Fri, Aug 26, 2016 at 10:21:00AM +0100, Jamie Lentin wrote:
> Allowing us to specify boot console in a standard manner in board DTs.
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH 4/8] arm: orion5x: Alias uart0 to serial0 for all orion5x

[Arnd Bergmann]

On Friday, August 26, 2016 10:21:00 AM CEST Jamie Lentin wrote:
> diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
> index fbccfbb..001613d 100644
> --- a/arch/arm/boot/dts/orion5x.dtsi
> +++ b/arch/arm/boot/dts/orion5x.dtsi
> @@ -17,6 +17,7 @@
>  
>         aliases {
>                 gpio0 = &gpio0;
> +               serial0 = &uart0;
>         };
>  
> 

Please put the alias for the serial port in the board specific .dts file,
it's possible that some boards have more than one uart in use,
and that they don't label them the same way as the SoC internal numbering.

	Arnd

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[PATCH 4/8] arm: orion5x: Alias uart0 to serial0 for all orion5x

[Arnd Bergmann]

On Friday, August 26, 2016 10:21:00 AM CEST Jamie Lentin wrote:
> diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
> index fbccfbb..001613d 100644
> --- a/arch/arm/boot/dts/orion5x.dtsi
> +++ b/arch/arm/boot/dts/orion5x.dtsi
> @@ -17,6 +17,7 @@
>  
>         aliases {
>                 gpio0 = &gpio0;
> +               serial0 = &uart0;
>         };
>  
> 

Please put the alias for the serial port in the board specific .dts file,
it's possible that some boards have more than one uart in use,
and that they don't label them the same way as the SoC internal numbering.

	Arnd

[PATCH 5/8] arm: orion5x: Add DT include for mv88f5181

[Jamie Lentin]

Common definitions for the SoC for board definitions to use.

Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 49 ++++++++++++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
index a888011..ff3c120 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -9,6 +9,7 @@ compatible: must contain "marvell,orion5x"
 In addition, the above compatible shall be extended with the specific
 SoC. Currently known SoC compatibles are:
 
+"marvell,orion5x-88f5181"
 "marvell,orion5x-88f5182"
 
 And in addition, the compatible shall be extended with the specific
diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
new file mode 100644
index 0000000..f667012
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2016 Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "orion5x.dtsi"
+
+/ {
+	compatible = "marvell,orion5x-88f5181", "marvell,orion5x";
+
+	soc {
+		compatible = "marvell,orion5x-88f5181-mbus", "simple-bus";
+
+		internal-regs {
+			pinctrl: pinctrl@10000 {
+				compatible = "marvell,88f5181-pinctrl";
+				reg = <0x10000 0x8>, <0x10050 0x4>;
+			};
+
+			core_clk: core-clocks@10030 {
+				compatible = "marvell,mv88f5181-core-clock";
+				reg = <0x10010 0x4>;
+				#clock-cells = <1>;
+			};
+
+			mbusc: mbus-controller@20000 {
+				compatible = "marvell,mbus-controller";
+				reg = <0x20000 0x100>, <0x1500 0x20>;
+			};
+		};
+	};
+};
+
+&pinctrl {
+	pmx_ge: pmx-ge {
+		marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11",
+			       "mpp12", "mpp13", "mpp14", "mpp15",
+			       "mpp16", "mpp17", "mpp18", "mpp19";
+		marvell,function = "ge";
+	};
+};
+
+&eth {
+	pinctrl-0 = <&pmx_ge>;
+	pinctrl-names = "default";
+};
-- 
2.8.1

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[PATCH 5/8] arm: orion5x: Add DT include for mv88f5181

[Jamie Lentin]

Common definitions for the SoC for board definitions to use.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
 arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 49 ++++++++++++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
index a888011..ff3c120 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -9,6 +9,7 @@ compatible: must contain "marvell,orion5x"
 In addition, the above compatible shall be extended with the specific
 SoC. Currently known SoC compatibles are:
 
+"marvell,orion5x-88f5181"
 "marvell,orion5x-88f5182"
 
 And in addition, the compatible shall be extended with the specific
diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
new file mode 100644
index 0000000..f667012
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "orion5x.dtsi"
+
+/ {
+	compatible = "marvell,orion5x-88f5181", "marvell,orion5x";
+
+	soc {
+		compatible = "marvell,orion5x-88f5181-mbus", "simple-bus";
+
+		internal-regs {
+			pinctrl: pinctrl at 10000 {
+				compatible = "marvell,88f5181-pinctrl";
+				reg = <0x10000 0x8>, <0x10050 0x4>;
+			};
+
+			core_clk: core-clocks at 10030 {
+				compatible = "marvell,mv88f5181-core-clock";
+				reg = <0x10010 0x4>;
+				#clock-cells = <1>;
+			};
+
+			mbusc: mbus-controller at 20000 {
+				compatible = "marvell,mbus-controller";
+				reg = <0x20000 0x100>, <0x1500 0x20>;
+			};
+		};
+	};
+};
+
+&pinctrl {
+	pmx_ge: pmx-ge {
+		marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11",
+			       "mpp12", "mpp13", "mpp14", "mpp15",
+			       "mpp16", "mpp17", "mpp18", "mpp19";
+		marvell,function = "ge";
+	};
+};
+
+&eth {
+	pinctrl-0 = <&pmx_ge>;
+	pinctrl-names = "default";
+};
-- 
2.8.1

Re: [PATCH 5/8] arm: orion5x: Add DT include for mv88f5181

[Andrew Lunn]

On Fri, Aug 26, 2016 at 10:21:01AM +0100, Jamie Lentin wrote:
> Common definitions for the SoC for board definitions to use.
> 
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>

Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>

    Andrew
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[PATCH 5/8] arm: orion5x: Add DT include for mv88f5181

[Andrew Lunn]

On Fri, Aug 26, 2016 at 10:21:01AM +0100, Jamie Lentin wrote:
> Common definitions for the SoC for board definitions to use.
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH 5/8] arm: orion5x: Add DT include for mv88f5181

[Rob Herring]

On Fri, Aug 26, 2016 at 10:21:01AM +0100, Jamie Lentin wrote:
> Common definitions for the SoC for board definitions to use.
> 
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
>  arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 49 ++++++++++++++++++++++
>  2 files changed, 50 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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[PATCH 5/8] arm: orion5x: Add DT include for mv88f5181

[Rob Herring]

On Fri, Aug 26, 2016 at 10:21:01AM +0100, Jamie Lentin wrote:
> Common definitions for the SoC for board definitions to use.
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |  1 +
>  arch/arm/boot/dts/orion5x-mv88f5181.dtsi           | 49 ++++++++++++++++++++++
>  2 files changed, 50 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 6/8] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 212 +++++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
 6 files changed, 299 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
index ff3c120..748a8f2 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -22,3 +22,4 @@ board. Currently known boards are:
 "lacie,d2-network"
 "marvell,rd-88f5182-nas"
 "maxtor,shared-storage-2"
+"netgear,wnr854t"
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index faacd52..4588b3c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-linkstation-lswtgl.dtb \
 	orion5x-lswsgl.dtb \
 	orion5x-maxtor-shared-storage-2.dtb \
+	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb
diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
new file mode 100644
index 0000000..402a364
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) 2016 Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+	model = "Netgear WNR854-t";
+	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
+		     "marvell,orion5x";
+
+	memory {
+		reg = <0x00000000 0x2000000>; /* 32 MB */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_reset_button>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
+		pinctrl-names = "default";
+
+		led@0 {
+			label = "wnr854t:green:power";
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led@1 {
+			label = "wnr854t:blink:power";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led@2 {
+			label = "wnr854t:green:wan";
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&devbus_bootcs {
+	status = "okay";
+
+	devbus,keep-config;
+
+	flash@0 {
+		compatible = "cfi-flash";
+		reg = <0 0x800000>;
+		bank-width = <2>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "rootfs";
+				reg = <0x0 0x600000>;
+			};
+
+			partition@600000 {
+				label = "nvram";
+				reg = <0x600000 0x20000>;
+			};
+
+			partition@620000 {
+				label = "nvram_default";
+				reg = <0x620000 0x20000>;
+			};
+
+			partition@640000 {
+				label = "POT";
+				reg = <0x640000 0x20000>;
+			};
+
+			partition@660000 {
+				label = "traffic_meter";
+				reg = <0x660000 0x20000>;
+			};
+
+			partition@760000 {
+				label = "uboot_env";
+				reg = <0x760000 0x20000>;
+			};
+
+			partition@780000 {
+				label = "uboot";
+				reg = <0x780000 0x80000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	switch: switch@0 {
+		compatible = "marvell,mv88e6085";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		dsa,member = <0 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "wan";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "cpu";
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "lan1";
+			};
+
+			port@7 {
+				reg = <7>;
+				label = "lan2";
+			};
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+
+	ethernet-port@0 {
+		/* Hardwired to DSA switch */
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_pci_gpios>;
+	pinctrl-names = "default";
+
+	pmx_power_led: pmx-power-led {
+		marvell,pins = "mpp0";
+		marvell,function = "gpio";
+	};
+
+	pmx_reset_button: pmx-reset-button {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_led_blink: pmx-power-led-blink {
+		marvell,pins = "mpp2";
+		marvell,function = "gpio";
+	};
+
+	pmx_wan_led: pmx-wan-led {
+		marvell,pins = "mpp3";
+		marvell,function = "gpio";
+	};
+
+	pmx_pci_gpios: pmx-pci-gpios {
+		marvell,pins = "mpp4";
+		marvell,function = "gpio";
+	};
+};
+
+&uart0 {
+	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
+	status = "okay";
+};
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 89bb0fc..9acb37b 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -151,6 +151,12 @@ config MACH_MSS2_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Maxtor Shared Storage II platform.
 
+config MACH_WNR854T_DT
+	bool "Netgear WNR854T (Flattened Device Tree)"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Netgear WNR854T platform.
+
 config MACH_WNR854T
 	bool "Netgear WNR854T"
 	help
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 4b2502b..9dff2d3 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
 obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
 obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
 obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
+obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o
diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c
new file mode 100644
index 0000000..c506e33
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-wnr854t.c
@@ -0,0 +1,78 @@
+/*
+ * Netgear WNR854T PCI setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <asm/mach/pci.h>
+#include "common.h"
+#include "orion5x.h"
+
+#define WNR854T_PCI_SLOT0_OFFS	7
+#define WNR854T_PCI_SLOT0_IRQ_PIN	4
+
+static void __init wnr854t_pci_preinit(void)
+{
+	int pin;
+
+	/*
+	 * Configure PCI GPIO IRQ pins
+	 */
+	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
+	if (gpio_request(pin, "PCI Int") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
+				pin);
+			gpio_free(pin);
+		}
+	} else {
+		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
+	}
+}
+
+static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
+	u8 pin)
+{
+	int irq;
+
+	/*
+	 * Check for devices with hard-wired IRQs.
+	 */
+	irq = orion5x_pci_map_irq(dev, slot, pin);
+	if (irq != -1)
+		return irq;
+
+	/*
+	 * PCI IRQs are connected via GPIOs
+	 */
+	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
+	case 0:
+		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
+	default:
+		return -1;
+	}
+}
+
+static struct hw_pci wnr854t_pci __initdata = {
+	.nr_controllers	= 2,
+	.preinit	= wnr854t_pci_preinit,
+	.setup		= orion5x_pci_sys_setup,
+	.scan		= orion5x_pci_sys_scan_bus,
+	.map_irq	= wnr854t_pci_map_irq,
+};
+
+static int __init wnr854t_pci_init(void)
+{
+	if (of_machine_is_compatible("netgear,wnr854t"))
+		pci_common_init(&wnr854t_pci);
+
+	return 0;
+}
+/* NB: Use late_initcall so we can gpio_request() without being deferred */
+late_initcall(wnr854t_pci_init);
-- 
2.8.1

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[PATCH 6/8] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 212 +++++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
 6 files changed, 299 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
index ff3c120..748a8f2 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -22,3 +22,4 @@ board. Currently known boards are:
 "lacie,d2-network"
 "marvell,rd-88f5182-nas"
 "maxtor,shared-storage-2"
+"netgear,wnr854t"
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index faacd52..4588b3c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-linkstation-lswtgl.dtb \
 	orion5x-lswsgl.dtb \
 	orion5x-maxtor-shared-storage-2.dtb \
+	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb
diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
new file mode 100644
index 0000000..402a364
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+	model = "Netgear WNR854-t";
+	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
+		     "marvell,orion5x";
+
+	memory {
+		reg = <0x00000000 0x2000000>; /* 32 MB */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_reset_button>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
+		pinctrl-names = "default";
+
+		led at 0 {
+			label = "wnr854t:green:power";
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 1 {
+			label = "wnr854t:blink:power";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 2 {
+			label = "wnr854t:green:wan";
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&devbus_bootcs {
+	status = "okay";
+
+	devbus,keep-config;
+
+	flash at 0 {
+		compatible = "cfi-flash";
+		reg = <0 0x800000>;
+		bank-width = <2>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition at 0 {
+				label = "rootfs";
+				reg = <0x0 0x600000>;
+			};
+
+			partition at 600000 {
+				label = "nvram";
+				reg = <0x600000 0x20000>;
+			};
+
+			partition at 620000 {
+				label = "nvram_default";
+				reg = <0x620000 0x20000>;
+			};
+
+			partition at 640000 {
+				label = "POT";
+				reg = <0x640000 0x20000>;
+			};
+
+			partition at 660000 {
+				label = "traffic_meter";
+				reg = <0x660000 0x20000>;
+			};
+
+			partition at 760000 {
+				label = "uboot_env";
+				reg = <0x760000 0x20000>;
+			};
+
+			partition at 780000 {
+				label = "uboot";
+				reg = <0x780000 0x80000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	switch: switch at 0 {
+		compatible = "marvell,mv88e6085";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		dsa,member = <0 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port at 0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "wan";
+			};
+
+			port at 3 {
+				reg = <3>;
+				label = "cpu";
+			};
+
+			port at 5 {
+				reg = <5>;
+				label = "lan1";
+			};
+
+			port at 7 {
+				reg = <7>;
+				label = "lan2";
+			};
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+
+	ethernet-port at 0 {
+		/* Hardwired to DSA switch */
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_pci_gpios>;
+	pinctrl-names = "default";
+
+	pmx_power_led: pmx-power-led {
+		marvell,pins = "mpp0";
+		marvell,function = "gpio";
+	};
+
+	pmx_reset_button: pmx-reset-button {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_led_blink: pmx-power-led-blink {
+		marvell,pins = "mpp2";
+		marvell,function = "gpio";
+	};
+
+	pmx_wan_led: pmx-wan-led {
+		marvell,pins = "mpp3";
+		marvell,function = "gpio";
+	};
+
+	pmx_pci_gpios: pmx-pci-gpios {
+		marvell,pins = "mpp4";
+		marvell,function = "gpio";
+	};
+};
+
+&uart0 {
+	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
+	status = "okay";
+};
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 89bb0fc..9acb37b 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -151,6 +151,12 @@ config MACH_MSS2_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Maxtor Shared Storage II platform.
 
+config MACH_WNR854T_DT
+	bool "Netgear WNR854T (Flattened Device Tree)"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Netgear WNR854T platform.
+
 config MACH_WNR854T
 	bool "Netgear WNR854T"
 	help
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 4b2502b..9dff2d3 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
 obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
 obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
 obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
+obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o
diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c
new file mode 100644
index 0000000..c506e33
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-wnr854t.c
@@ -0,0 +1,78 @@
+/*
+ * Netgear WNR854T PCI setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <asm/mach/pci.h>
+#include "common.h"
+#include "orion5x.h"
+
+#define WNR854T_PCI_SLOT0_OFFS	7
+#define WNR854T_PCI_SLOT0_IRQ_PIN	4
+
+static void __init wnr854t_pci_preinit(void)
+{
+	int pin;
+
+	/*
+	 * Configure PCI GPIO IRQ pins
+	 */
+	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
+	if (gpio_request(pin, "PCI Int") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
+				pin);
+			gpio_free(pin);
+		}
+	} else {
+		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
+	}
+}
+
+static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
+	u8 pin)
+{
+	int irq;
+
+	/*
+	 * Check for devices with hard-wired IRQs.
+	 */
+	irq = orion5x_pci_map_irq(dev, slot, pin);
+	if (irq != -1)
+		return irq;
+
+	/*
+	 * PCI IRQs are connected via GPIOs
+	 */
+	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
+	case 0:
+		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
+	default:
+		return -1;
+	}
+}
+
+static struct hw_pci wnr854t_pci __initdata = {
+	.nr_controllers	= 2,
+	.preinit	= wnr854t_pci_preinit,
+	.setup		= orion5x_pci_sys_setup,
+	.scan		= orion5x_pci_sys_scan_bus,
+	.map_irq	= wnr854t_pci_map_irq,
+};
+
+static int __init wnr854t_pci_init(void)
+{
+	if (of_machine_is_compatible("netgear,wnr854t"))
+		pci_common_init(&wnr854t_pci);
+
+	return 0;
+}
+/* NB: Use late_initcall so we can gpio_request() without being deferred */
+late_initcall(wnr854t_pci_init);
-- 
2.8.1

Re: [PATCH 6/8] arm: orion5x: Add DT-based support for Netgear WNR854T

[Rob Herring]

On Fri, Aug 26, 2016 at 10:21:02AM +0100, Jamie Lentin wrote:
> This is a router based on the mv88f5181 chipset.
> 
> http://www.netgear.com/support/product/WNR854T.aspx
> http://wiki.openwrt.org/toh/netgear/wnr854t
> 
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 212 +++++++++++++++++++++

For the bindings,

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>  arch/arm/mach-orion5x/Makefile                     |   1 +
>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++

This is all PCI setup it appears. The PCI driver should be converted to 
a modern PCI host driver before it is supported with DT IMO.

Rob
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[PATCH 6/8] arm: orion5x: Add DT-based support for Netgear WNR854T

[Rob Herring]

On Fri, Aug 26, 2016 at 10:21:02AM +0100, Jamie Lentin wrote:
> This is a router based on the mv88f5181 chipset.
> 
> http://www.netgear.com/support/product/WNR854T.aspx
> http://wiki.openwrt.org/toh/netgear/wnr854t
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 212 +++++++++++++++++++++

For the bindings,

Acked-by: Rob Herring <robh@kernel.org>

>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>  arch/arm/mach-orion5x/Makefile                     |   1 +
>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++

This is all PCI setup it appears. The PCI driver should be converted to 
a modern PCI host driver before it is supported with DT IMO.

Rob

[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
---
This removes the contentious vendor partitioning scheme and goes back
to the original partitioning scheme used in non-DT ports to this board.
Using the same partitioning scheme should mean less surprises for
someone trying to upgrade their router.

The non-DT PCI setup is still here, as there are other orion5x DT boards
doing very similar things, and can all be converted at the same time.

The patchset in it's entirety is available at
https://github.com/lentinj/linux wnr854t-support-v2

Cheers,
---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 197 +++++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
 6 files changed, 284 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
index ff3c120..748a8f2 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -22,3 +22,4 @@ board. Currently known boards are:
 "lacie,d2-network"
 "marvell,rd-88f5182-nas"
 "maxtor,shared-storage-2"
+"netgear,wnr854t"
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index faacd52..4588b3c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-linkstation-lswtgl.dtb \
 	orion5x-lswsgl.dtb \
 	orion5x-maxtor-shared-storage-2.dtb \
+	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb
diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
new file mode 100644
index 0000000..cce5091
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2016 Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+	model = "Netgear WNR854-t";
+	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
+		     "marvell,orion5x";
+
+	memory {
+		reg = <0x00000000 0x2000000>; /* 32 MB */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_reset_button>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
+		pinctrl-names = "default";
+
+		led@0 {
+			label = "wnr854t:green:power";
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led@1 {
+			label = "wnr854t:blink:power";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led@2 {
+			label = "wnr854t:green:wan";
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&devbus_bootcs {
+	status = "okay";
+
+	devbus,keep-config;
+
+	flash@0 {
+		compatible = "cfi-flash";
+		reg = <0 0x800000>;
+		bank-width = <2>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "kernel";
+				reg = <0x0 0x100000>;
+			};
+
+			partition@100000 {
+				label = "rootfs";
+				reg = <0x100000 0x660000>;
+			};
+
+			partition@760000 {
+				label = "uboot_env";
+				reg = <0x760000 0x20000>;
+			};
+
+			partition@780000 {
+				label = "uboot";
+				reg = <0x780000 0x80000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	switch: switch@0 {
+		compatible = "marvell,mv88e6085";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		dsa,member = <0 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "wan";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "cpu";
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "lan1";
+			};
+
+			port@7 {
+				reg = <7>;
+				label = "lan2";
+			};
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+
+	ethernet-port@0 {
+		/* Hardwired to DSA switch */
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_pci_gpios>;
+	pinctrl-names = "default";
+
+	pmx_power_led: pmx-power-led {
+		marvell,pins = "mpp0";
+		marvell,function = "gpio";
+	};
+
+	pmx_reset_button: pmx-reset-button {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_led_blink: pmx-power-led-blink {
+		marvell,pins = "mpp2";
+		marvell,function = "gpio";
+	};
+
+	pmx_wan_led: pmx-wan-led {
+		marvell,pins = "mpp3";
+		marvell,function = "gpio";
+	};
+
+	pmx_pci_gpios: pmx-pci-gpios {
+		marvell,pins = "mpp4";
+		marvell,function = "gpio";
+	};
+};
+
+&uart0 {
+	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
+	status = "okay";
+};
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 89bb0fc..9acb37b 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -151,6 +151,12 @@ config MACH_MSS2_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Maxtor Shared Storage II platform.
 
+config MACH_WNR854T_DT
+	bool "Netgear WNR854T (Flattened Device Tree)"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Netgear WNR854T platform.
+
 config MACH_WNR854T
 	bool "Netgear WNR854T"
 	help
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 4b2502b..9dff2d3 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
 obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
 obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
 obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
+obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o
diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c
new file mode 100644
index 0000000..c506e33
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-wnr854t.c
@@ -0,0 +1,78 @@
+/*
+ * Netgear WNR854T PCI setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <asm/mach/pci.h>
+#include "common.h"
+#include "orion5x.h"
+
+#define WNR854T_PCI_SLOT0_OFFS	7
+#define WNR854T_PCI_SLOT0_IRQ_PIN	4
+
+static void __init wnr854t_pci_preinit(void)
+{
+	int pin;
+
+	/*
+	 * Configure PCI GPIO IRQ pins
+	 */
+	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
+	if (gpio_request(pin, "PCI Int") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
+				pin);
+			gpio_free(pin);
+		}
+	} else {
+		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
+	}
+}
+
+static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
+	u8 pin)
+{
+	int irq;
+
+	/*
+	 * Check for devices with hard-wired IRQs.
+	 */
+	irq = orion5x_pci_map_irq(dev, slot, pin);
+	if (irq != -1)
+		return irq;
+
+	/*
+	 * PCI IRQs are connected via GPIOs
+	 */
+	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
+	case 0:
+		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
+	default:
+		return -1;
+	}
+}
+
+static struct hw_pci wnr854t_pci __initdata = {
+	.nr_controllers	= 2,
+	.preinit	= wnr854t_pci_preinit,
+	.setup		= orion5x_pci_sys_setup,
+	.scan		= orion5x_pci_sys_scan_bus,
+	.map_irq	= wnr854t_pci_map_irq,
+};
+
+static int __init wnr854t_pci_init(void)
+{
+	if (of_machine_is_compatible("netgear,wnr854t"))
+		pci_common_init(&wnr854t_pci);
+
+	return 0;
+}
+/* NB: Use late_initcall so we can gpio_request() without being deferred */
+late_initcall(wnr854t_pci_init);
-- 
2.8.1

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[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

This is a router based on the mv88f5181 chipset.

http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
This removes the contentious vendor partitioning scheme and goes back
to the original partitioning scheme used in non-DT ports to this board.
Using the same partitioning scheme should mean less surprises for
someone trying to upgrade their router.

The non-DT PCI setup is still here, as there are other orion5x DT boards
doing very similar things, and can all be converted at the same time.

The patchset in it's entirety is available at
https://github.com/lentinj/linux wnr854t-support-v2

Cheers,
---
 .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 197 +++++++++++++++++++++
 arch/arm/mach-orion5x/Kconfig                      |   6 +
 arch/arm/mach-orion5x/Makefile                     |   1 +
 arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
 6 files changed, 284 insertions(+)
 create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
 create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
index ff3c120..748a8f2 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
@@ -22,3 +22,4 @@ board. Currently known boards are:
 "lacie,d2-network"
 "marvell,rd-88f5182-nas"
 "maxtor,shared-storage-2"
+"netgear,wnr854t"
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index faacd52..4588b3c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-linkstation-lswtgl.dtb \
 	orion5x-lswsgl.dtb \
 	orion5x-maxtor-shared-storage-2.dtb \
+	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb
diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
new file mode 100644
index 0000000..cce5091
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "orion5x-mv88f5181.dtsi"
+
+/ {
+	model = "Netgear WNR854-t";
+	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
+		     "marvell,orion5x";
+
+	memory {
+		reg = <0x00000000 0x2000000>; /* 32 MB */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pmx_reset_button>;
+		pinctrl-names = "default";
+
+		reset {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
+		pinctrl-names = "default";
+
+		led at 0 {
+			label = "wnr854t:green:power";
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 1 {
+			label = "wnr854t:blink:power";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led at 2 {
+			label = "wnr854t:green:wan";
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&devbus_bootcs {
+	status = "okay";
+
+	devbus,keep-config;
+
+	flash at 0 {
+		compatible = "cfi-flash";
+		reg = <0 0x800000>;
+		bank-width = <2>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition at 0 {
+				label = "kernel";
+				reg = <0x0 0x100000>;
+			};
+
+			partition at 100000 {
+				label = "rootfs";
+				reg = <0x100000 0x660000>;
+			};
+
+			partition at 760000 {
+				label = "uboot_env";
+				reg = <0x760000 0x20000>;
+			};
+
+			partition at 780000 {
+				label = "uboot";
+				reg = <0x780000 0x80000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	switch: switch at 0 {
+		compatible = "marvell,mv88e6085";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		dsa,member = <0 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port at 0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port at 1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port at 2 {
+				reg = <2>;
+				label = "wan";
+			};
+
+			port at 3 {
+				reg = <3>;
+				label = "cpu";
+			};
+
+			port at 5 {
+				reg = <5>;
+				label = "lan1";
+			};
+
+			port at 7 {
+				reg = <7>;
+				label = "lan2";
+			};
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+
+	ethernet-port at 0 {
+		/* Hardwired to DSA switch */
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_pci_gpios>;
+	pinctrl-names = "default";
+
+	pmx_power_led: pmx-power-led {
+		marvell,pins = "mpp0";
+		marvell,function = "gpio";
+	};
+
+	pmx_reset_button: pmx-reset-button {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_led_blink: pmx-power-led-blink {
+		marvell,pins = "mpp2";
+		marvell,function = "gpio";
+	};
+
+	pmx_wan_led: pmx-wan-led {
+		marvell,pins = "mpp3";
+		marvell,function = "gpio";
+	};
+
+	pmx_pci_gpios: pmx-pci-gpios {
+		marvell,pins = "mpp4";
+		marvell,function = "gpio";
+	};
+};
+
+&uart0 {
+	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
+	status = "okay";
+};
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 89bb0fc..9acb37b 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -151,6 +151,12 @@ config MACH_MSS2_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Maxtor Shared Storage II platform.
 
+config MACH_WNR854T_DT
+	bool "Netgear WNR854T (Flattened Device Tree)"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Netgear WNR854T platform.
+
 config MACH_WNR854T
 	bool "Netgear WNR854T"
 	help
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 4b2502b..9dff2d3 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
 obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
 obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
 obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
+obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o
diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c
new file mode 100644
index 0000000..c506e33
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-wnr854t.c
@@ -0,0 +1,78 @@
+/*
+ * Netgear WNR854T PCI setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <asm/mach/pci.h>
+#include "common.h"
+#include "orion5x.h"
+
+#define WNR854T_PCI_SLOT0_OFFS	7
+#define WNR854T_PCI_SLOT0_IRQ_PIN	4
+
+static void __init wnr854t_pci_preinit(void)
+{
+	int pin;
+
+	/*
+	 * Configure PCI GPIO IRQ pins
+	 */
+	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
+	if (gpio_request(pin, "PCI Int") == 0) {
+		if (gpio_direction_input(pin) == 0) {
+			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+		} else {
+			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
+				pin);
+			gpio_free(pin);
+		}
+	} else {
+		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
+	}
+}
+
+static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
+	u8 pin)
+{
+	int irq;
+
+	/*
+	 * Check for devices with hard-wired IRQs.
+	 */
+	irq = orion5x_pci_map_irq(dev, slot, pin);
+	if (irq != -1)
+		return irq;
+
+	/*
+	 * PCI IRQs are connected via GPIOs
+	 */
+	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
+	case 0:
+		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
+	default:
+		return -1;
+	}
+}
+
+static struct hw_pci wnr854t_pci __initdata = {
+	.nr_controllers	= 2,
+	.preinit	= wnr854t_pci_preinit,
+	.setup		= orion5x_pci_sys_setup,
+	.scan		= orion5x_pci_sys_scan_bus,
+	.map_irq	= wnr854t_pci_map_irq,
+};
+
+static int __init wnr854t_pci_init(void)
+{
+	if (of_machine_is_compatible("netgear,wnr854t"))
+		pci_common_init(&wnr854t_pci);
+
+	return 0;
+}
+/* NB: Use late_initcall so we can gpio_request() without being deferred */
+late_initcall(wnr854t_pci_init);
-- 
2.8.1

Re: [PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Gregory CLEMENT]

Hi Jamie,
 
 On lun., sept. 05 2016, Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org> wrote:

> This is a router based on the mv88f5181 chipset.
>
> http://www.netgear.com/support/product/WNR854T.aspx
> http://wiki.openwrt.org/toh/netgear/wnr854t
>
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
> ---
> This removes the contentious vendor partitioning scheme and goes back
> to the original partitioning scheme used in non-DT ports to this board.
> Using the same partitioning scheme should mean less surprises for
> someone trying to upgrade their router.
>
> The non-DT PCI setup is still here, as there are other orion5x DT boards
> doing very similar things, and can all be converted at the same time.

I only noticed today your v2. I expected a full series actually.  I am
now taking care of it. I mainly have to rename most of the commit titles
as they do not really match the subsystem where they will be applied.

I will apply all of them on the mvebu branches to avoid to more
dependency issue. However, we are very close to the end of the merge
window for arm-soc. I will do my best, but the merge of the series could
be delayed to 4.10.

Thanks,

Gregory


>
> The patchset in it's entirety is available at
> https://github.com/lentinj/linux wnr854t-support-v2
>
> Cheers,
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 197 +++++++++++++++++++++
>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>  arch/arm/mach-orion5x/Makefile                     |   1 +
>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
>  6 files changed, 284 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>  create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
>
> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> index ff3c120..748a8f2 100644
> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> @@ -22,3 +22,4 @@ board. Currently known boards are:
>  "lacie,d2-network"
>  "marvell,rd-88f5182-nas"
>  "maxtor,shared-storage-2"
> +"netgear,wnr854t"
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index faacd52..4588b3c 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
>  	orion5x-linkstation-lswtgl.dtb \
>  	orion5x-lswsgl.dtb \
>  	orion5x-maxtor-shared-storage-2.dtb \
> +	orion5x-netgear-wnr854t.dtb \
>  	orion5x-rd88f5182-nas.dtb
>  dtb-$(CONFIG_ARCH_PRIMA2) += \
>  	prima2-evb.dtb
> diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
> new file mode 100644
> index 0000000..cce5091
> --- /dev/null
> +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
> @@ -0,0 +1,197 @@
> +/*
> + * Copyright (C) 2016 Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "orion5x-mv88f5181.dtsi"
> +
> +/ {
> +	model = "Netgear WNR854-t";
> +	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
> +		     "marvell,orion5x";
> +
> +	memory {
> +		reg = <0x00000000 0x2000000>; /* 32 MB */
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	soc {
> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
> +			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
> +			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-0 = <&pmx_reset_button>;
> +		pinctrl-names = "default";
> +
> +		reset {
> +			label = "Reset Button";
> +			linux,code = <KEY_RESTART>;
> +			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
> +		pinctrl-names = "default";
> +
> +		led@0 {
> +			label = "wnr854t:green:power";
> +			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		led@1 {
> +			label = "wnr854t:blink:power";
> +			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		led@2 {
> +			label = "wnr854t:green:wan";
> +			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +};
> +
> +&devbus_bootcs {
> +	status = "okay";
> +
> +	devbus,keep-config;
> +
> +	flash@0 {
> +		compatible = "cfi-flash";
> +		reg = <0 0x800000>;
> +		bank-width = <2>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "kernel";
> +				reg = <0x0 0x100000>;
> +			};
> +
> +			partition@100000 {
> +				label = "rootfs";
> +				reg = <0x100000 0x660000>;
> +			};
> +
> +			partition@760000 {
> +				label = "uboot_env";
> +				reg = <0x760000 0x20000>;
> +			};
> +
> +			partition@780000 {
> +				label = "uboot";
> +				reg = <0x780000 0x80000>;
> +				read-only;
> +			};
> +		};
> +	};
> +};
> +
> +&mdio {
> +	status = "okay";
> +
> +	switch: switch@0 {
> +		compatible = "marvell,mv88e6085";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0>;
> +		dsa,member = <0 0>;
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@0 {
> +				reg = <0>;
> +				label = "lan3";
> +			};
> +
> +			port@1 {
> +				reg = <1>;
> +				label = "lan4";
> +			};
> +
> +			port@2 {
> +				reg = <2>;
> +				label = "wan";
> +			};
> +
> +			port@3 {
> +				reg = <3>;
> +				label = "cpu";
> +			};
> +
> +			port@5 {
> +				reg = <5>;
> +				label = "lan1";
> +			};
> +
> +			port@7 {
> +				reg = <7>;
> +				label = "lan2";
> +			};
> +		};
> +	};
> +};
> +
> +&eth {
> +	status = "okay";
> +
> +	ethernet-port@0 {
> +		/* Hardwired to DSA switch */
> +		speed = <1000>;
> +		duplex = <1>;
> +	};
> +};
> +
> +&pinctrl {
> +	pinctrl-0 = <&pmx_pci_gpios>;
> +	pinctrl-names = "default";
> +
> +	pmx_power_led: pmx-power-led {
> +		marvell,pins = "mpp0";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_reset_button: pmx-reset-button {
> +		marvell,pins = "mpp1";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_power_led_blink: pmx-power-led-blink {
> +		marvell,pins = "mpp2";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_wan_led: pmx-wan-led {
> +		marvell,pins = "mpp3";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_pci_gpios: pmx-pci-gpios {
> +		marvell,pins = "mpp4";
> +		marvell,function = "gpio";
> +	};
> +};
> +
> +&uart0 {
> +	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
> +	status = "okay";
> +};
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index 89bb0fc..9acb37b 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -151,6 +151,12 @@ config MACH_MSS2_DT
>  	  Say 'Y' here if you want your kernel to support the
>  	  Maxtor Shared Storage II platform.
>  
> +config MACH_WNR854T_DT
> +	bool "Netgear WNR854T (Flattened Device Tree)"
> +	help
> +	  Say 'Y' here if you want your kernel to support the
> +	  Netgear WNR854T platform.
> +
>  config MACH_WNR854T
>  	bool "Netgear WNR854T"
>  	help
> diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
> index 4b2502b..9dff2d3 100644
> --- a/arch/arm/mach-orion5x/Makefile
> +++ b/arch/arm/mach-orion5x/Makefile
> @@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
>  obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
>  obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
>  obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
> +obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o
> diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c
> new file mode 100644
> index 0000000..c506e33
> --- /dev/null
> +++ b/arch/arm/mach-orion5x/board-wnr854t.c
> @@ -0,0 +1,78 @@
> +/*
> + * Netgear WNR854T PCI setup
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <linux/gpio.h>
> +#include <linux/platform_device.h>
> +#include <linux/pci.h>
> +#include <asm/mach/pci.h>
> +#include "common.h"
> +#include "orion5x.h"
> +
> +#define WNR854T_PCI_SLOT0_OFFS	7
> +#define WNR854T_PCI_SLOT0_IRQ_PIN	4
> +
> +static void __init wnr854t_pci_preinit(void)
> +{
> +	int pin;
> +
> +	/*
> +	 * Configure PCI GPIO IRQ pins
> +	 */
> +	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
> +	if (gpio_request(pin, "PCI Int") == 0) {
> +		if (gpio_direction_input(pin) == 0) {
> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
> +		} else {
> +			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
> +				pin);
> +			gpio_free(pin);
> +		}
> +	} else {
> +		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
> +	}
> +}
> +
> +static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
> +	u8 pin)
> +{
> +	int irq;
> +
> +	/*
> +	 * Check for devices with hard-wired IRQs.
> +	 */
> +	irq = orion5x_pci_map_irq(dev, slot, pin);
> +	if (irq != -1)
> +		return irq;
> +
> +	/*
> +	 * PCI IRQs are connected via GPIOs
> +	 */
> +	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
> +	case 0:
> +		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
> +	default:
> +		return -1;
> +	}
> +}
> +
> +static struct hw_pci wnr854t_pci __initdata = {
> +	.nr_controllers	= 2,
> +	.preinit	= wnr854t_pci_preinit,
> +	.setup		= orion5x_pci_sys_setup,
> +	.scan		= orion5x_pci_sys_scan_bus,
> +	.map_irq	= wnr854t_pci_map_irq,
> +};
> +
> +static int __init wnr854t_pci_init(void)
> +{
> +	if (of_machine_is_compatible("netgear,wnr854t"))
> +		pci_common_init(&wnr854t_pci);
> +
> +	return 0;
> +}
> +/* NB: Use late_initcall so we can gpio_request() without being deferred */
> +late_initcall(wnr854t_pci_init);
> -- 
> 2.8.1
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Gregory CLEMENT]

Hi Jamie,
 
 On lun., sept. 05 2016, Jamie Lentin <jm@lentin.co.uk> wrote:

> This is a router based on the mv88f5181 chipset.
>
> http://www.netgear.com/support/product/WNR854T.aspx
> http://wiki.openwrt.org/toh/netgear/wnr854t
>
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
> This removes the contentious vendor partitioning scheme and goes back
> to the original partitioning scheme used in non-DT ports to this board.
> Using the same partitioning scheme should mean less surprises for
> someone trying to upgrade their router.
>
> The non-DT PCI setup is still here, as there are other orion5x DT boards
> doing very similar things, and can all be converted at the same time.

I only noticed today your v2. I expected a full series actually.  I am
now taking care of it. I mainly have to rename most of the commit titles
as they do not really match the subsystem where they will be applied.

I will apply all of them on the mvebu branches to avoid to more
dependency issue. However, we are very close to the end of the merge
window for arm-soc. I will do my best, but the merge of the series could
be delayed to 4.10.

Thanks,

Gregory


>
> The patchset in it's entirety is available at
> https://github.com/lentinj/linux wnr854t-support-v2
>
> Cheers,
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 197 +++++++++++++++++++++
>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>  arch/arm/mach-orion5x/Makefile                     |   1 +
>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
>  6 files changed, 284 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>  create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
>
> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> index ff3c120..748a8f2 100644
> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
> @@ -22,3 +22,4 @@ board. Currently known boards are:
>  "lacie,d2-network"
>  "marvell,rd-88f5182-nas"
>  "maxtor,shared-storage-2"
> +"netgear,wnr854t"
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index faacd52..4588b3c 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
>  	orion5x-linkstation-lswtgl.dtb \
>  	orion5x-lswsgl.dtb \
>  	orion5x-maxtor-shared-storage-2.dtb \
> +	orion5x-netgear-wnr854t.dtb \
>  	orion5x-rd88f5182-nas.dtb
>  dtb-$(CONFIG_ARCH_PRIMA2) += \
>  	prima2-evb.dtb
> diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
> new file mode 100644
> index 0000000..cce5091
> --- /dev/null
> +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
> @@ -0,0 +1,197 @@
> +/*
> + * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "orion5x-mv88f5181.dtsi"
> +
> +/ {
> +	model = "Netgear WNR854-t";
> +	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
> +		     "marvell,orion5x";
> +
> +	memory {
> +		reg = <0x00000000 0x2000000>; /* 32 MB */
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	soc {
> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
> +			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
> +			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-0 = <&pmx_reset_button>;
> +		pinctrl-names = "default";
> +
> +		reset {
> +			label = "Reset Button";
> +			linux,code = <KEY_RESTART>;
> +			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
> +		pinctrl-names = "default";
> +
> +		led at 0 {
> +			label = "wnr854t:green:power";
> +			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		led at 1 {
> +			label = "wnr854t:blink:power";
> +			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
> +		};
> +
> +		led at 2 {
> +			label = "wnr854t:green:wan";
> +			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +};
> +
> +&devbus_bootcs {
> +	status = "okay";
> +
> +	devbus,keep-config;
> +
> +	flash at 0 {
> +		compatible = "cfi-flash";
> +		reg = <0 0x800000>;
> +		bank-width = <2>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition at 0 {
> +				label = "kernel";
> +				reg = <0x0 0x100000>;
> +			};
> +
> +			partition at 100000 {
> +				label = "rootfs";
> +				reg = <0x100000 0x660000>;
> +			};
> +
> +			partition at 760000 {
> +				label = "uboot_env";
> +				reg = <0x760000 0x20000>;
> +			};
> +
> +			partition at 780000 {
> +				label = "uboot";
> +				reg = <0x780000 0x80000>;
> +				read-only;
> +			};
> +		};
> +	};
> +};
> +
> +&mdio {
> +	status = "okay";
> +
> +	switch: switch at 0 {
> +		compatible = "marvell,mv88e6085";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0>;
> +		dsa,member = <0 0>;
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port at 0 {
> +				reg = <0>;
> +				label = "lan3";
> +			};
> +
> +			port at 1 {
> +				reg = <1>;
> +				label = "lan4";
> +			};
> +
> +			port at 2 {
> +				reg = <2>;
> +				label = "wan";
> +			};
> +
> +			port at 3 {
> +				reg = <3>;
> +				label = "cpu";
> +			};
> +
> +			port at 5 {
> +				reg = <5>;
> +				label = "lan1";
> +			};
> +
> +			port at 7 {
> +				reg = <7>;
> +				label = "lan2";
> +			};
> +		};
> +	};
> +};
> +
> +&eth {
> +	status = "okay";
> +
> +	ethernet-port at 0 {
> +		/* Hardwired to DSA switch */
> +		speed = <1000>;
> +		duplex = <1>;
> +	};
> +};
> +
> +&pinctrl {
> +	pinctrl-0 = <&pmx_pci_gpios>;
> +	pinctrl-names = "default";
> +
> +	pmx_power_led: pmx-power-led {
> +		marvell,pins = "mpp0";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_reset_button: pmx-reset-button {
> +		marvell,pins = "mpp1";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_power_led_blink: pmx-power-led-blink {
> +		marvell,pins = "mpp2";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_wan_led: pmx-wan-led {
> +		marvell,pins = "mpp3";
> +		marvell,function = "gpio";
> +	};
> +
> +	pmx_pci_gpios: pmx-pci-gpios {
> +		marvell,pins = "mpp4";
> +		marvell,function = "gpio";
> +	};
> +};
> +
> +&uart0 {
> +	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
> +	status = "okay";
> +};
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index 89bb0fc..9acb37b 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -151,6 +151,12 @@ config MACH_MSS2_DT
>  	  Say 'Y' here if you want your kernel to support the
>  	  Maxtor Shared Storage II platform.
>  
> +config MACH_WNR854T_DT
> +	bool "Netgear WNR854T (Flattened Device Tree)"
> +	help
> +	  Say 'Y' here if you want your kernel to support the
> +	  Netgear WNR854T platform.
> +
>  config MACH_WNR854T
>  	bool "Netgear WNR854T"
>  	help
> diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
> index 4b2502b..9dff2d3 100644
> --- a/arch/arm/mach-orion5x/Makefile
> +++ b/arch/arm/mach-orion5x/Makefile
> @@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
>  obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
>  obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
>  obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
> +obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o
> diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c
> new file mode 100644
> index 0000000..c506e33
> --- /dev/null
> +++ b/arch/arm/mach-orion5x/board-wnr854t.c
> @@ -0,0 +1,78 @@
> +/*
> + * Netgear WNR854T PCI setup
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <linux/gpio.h>
> +#include <linux/platform_device.h>
> +#include <linux/pci.h>
> +#include <asm/mach/pci.h>
> +#include "common.h"
> +#include "orion5x.h"
> +
> +#define WNR854T_PCI_SLOT0_OFFS	7
> +#define WNR854T_PCI_SLOT0_IRQ_PIN	4
> +
> +static void __init wnr854t_pci_preinit(void)
> +{
> +	int pin;
> +
> +	/*
> +	 * Configure PCI GPIO IRQ pins
> +	 */
> +	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
> +	if (gpio_request(pin, "PCI Int") == 0) {
> +		if (gpio_direction_input(pin) == 0) {
> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
> +		} else {
> +			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
> +				pin);
> +			gpio_free(pin);
> +		}
> +	} else {
> +		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
> +	}
> +}
> +
> +static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
> +	u8 pin)
> +{
> +	int irq;
> +
> +	/*
> +	 * Check for devices with hard-wired IRQs.
> +	 */
> +	irq = orion5x_pci_map_irq(dev, slot, pin);
> +	if (irq != -1)
> +		return irq;
> +
> +	/*
> +	 * PCI IRQs are connected via GPIOs
> +	 */
> +	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
> +	case 0:
> +		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
> +	default:
> +		return -1;
> +	}
> +}
> +
> +static struct hw_pci wnr854t_pci __initdata = {
> +	.nr_controllers	= 2,
> +	.preinit	= wnr854t_pci_preinit,
> +	.setup		= orion5x_pci_sys_setup,
> +	.scan		= orion5x_pci_sys_scan_bus,
> +	.map_irq	= wnr854t_pci_map_irq,
> +};
> +
> +static int __init wnr854t_pci_init(void)
> +{
> +	if (of_machine_is_compatible("netgear,wnr854t"))
> +		pci_common_init(&wnr854t_pci);
> +
> +	return 0;
> +}
> +/* NB: Use late_initcall so we can gpio_request() without being deferred */
> +late_initcall(wnr854t_pci_init);
> -- 
> 2.8.1
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On Thu, 8 Sep 2016, Gregory CLEMENT wrote:

> Hi Jamie,
>
> On lun., sept. 05 2016, Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org> wrote:
>
>> This is a router based on the mv88f5181 chipset.
>>
>> http://www.netgear.com/support/product/WNR854T.aspx
>> http://wiki.openwrt.org/toh/netgear/wnr854t
>>
>> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
>> ---
>> This removes the contentious vendor partitioning scheme and goes back
>> to the original partitioning scheme used in non-DT ports to this board.
>> Using the same partitioning scheme should mean less surprises for
>> someone trying to upgrade their router.
>>
>> The non-DT PCI setup is still here, as there are other orion5x DT boards
>> doing very similar things, and can all be converted at the same time.
>
> I only noticed today your v2. I expected a full series actually.

It seemed excessive to spam the entire patchset out again, of course I can 
if it makes your life easier.

> I am
> now taking care of it. I mainly have to rename most of the commit titles
> as they do not really match the subsystem where they will be applied.

Thanks, let me know if I can make myself useful.

> I will apply all of them on the mvebu branches to avoid to more
> dependency issue. However, we are very close to the end of the merge
> window for arm-soc. I will do my best, but the merge of the series could
> be delayed to 4.10.
>
> Thanks,
>
> Gregory
>
>
>>
>> The patchset in it's entirety is available at
>> https://github.com/lentinj/linux wnr854t-support-v2
>>
>> Cheers,
>> ---
>>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>>  arch/arm/boot/dts/Makefile                         |   1 +
>>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 197 +++++++++++++++++++++
>>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>>  arch/arm/mach-orion5x/Makefile                     |   1 +
>>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
>>  6 files changed, 284 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>>  create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
>>
>> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> index ff3c120..748a8f2 100644
>> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> @@ -22,3 +22,4 @@ board. Currently known boards are:
>>  "lacie,d2-network"
>>  "marvell,rd-88f5182-nas"
>>  "maxtor,shared-storage-2"
>> +"netgear,wnr854t"
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index faacd52..4588b3c 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
>>  	orion5x-linkstation-lswtgl.dtb \
>>  	orion5x-lswsgl.dtb \
>>  	orion5x-maxtor-shared-storage-2.dtb \
>> +	orion5x-netgear-wnr854t.dtb \
>>  	orion5x-rd88f5182-nas.dtb
>>  dtb-$(CONFIG_ARCH_PRIMA2) += \
>>  	prima2-evb.dtb
>> diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>> new file mode 100644
>> index 0000000..cce5091
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>> @@ -0,0 +1,197 @@
>> +/*
>> + * Copyright (C) 2016 Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +#include "orion5x-mv88f5181.dtsi"
>> +
>> +/ {
>> +	model = "Netgear WNR854-t";
>> +	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
>> +		     "marvell,orion5x";
>> +
>> +	memory {
>> +		reg = <0x00000000 0x2000000>; /* 32 MB */
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +
>> +	soc {
>> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
>> +			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
>> +			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
>> +	};
>> +
>> +	gpio-keys {
>> +		compatible = "gpio-keys";
>> +		pinctrl-0 = <&pmx_reset_button>;
>> +		pinctrl-names = "default";
>> +
>> +		reset {
>> +			label = "Reset Button";
>> +			linux,code = <KEY_RESTART>;
>> +			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
>> +		};
>> +	};
>> +
>> +	gpio-leds {
>> +		compatible = "gpio-leds";
>> +		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
>> +		pinctrl-names = "default";
>> +
>> +		led@0 {
>> +			label = "wnr854t:green:power";
>> +			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
>> +		};
>> +
>> +		led@1 {
>> +			label = "wnr854t:blink:power";
>> +			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
>> +		};
>> +
>> +		led@2 {
>> +			label = "wnr854t:green:wan";
>> +			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
>> +		};
>> +	};
>> +};
>> +
>> +&devbus_bootcs {
>> +	status = "okay";
>> +
>> +	devbus,keep-config;
>> +
>> +	flash@0 {
>> +		compatible = "cfi-flash";
>> +		reg = <0 0x800000>;
>> +		bank-width = <2>;
>> +
>> +		partitions {
>> +			compatible = "fixed-partitions";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +
>> +			partition@0 {
>> +				label = "kernel";
>> +				reg = <0x0 0x100000>;
>> +			};
>> +
>> +			partition@100000 {
>> +				label = "rootfs";
>> +				reg = <0x100000 0x660000>;
>> +			};
>> +
>> +			partition@760000 {
>> +				label = "uboot_env";
>> +				reg = <0x760000 0x20000>;
>> +			};
>> +
>> +			partition@780000 {
>> +				label = "uboot";
>> +				reg = <0x780000 0x80000>;
>> +				read-only;
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&mdio {
>> +	status = "okay";
>> +
>> +	switch: switch@0 {
>> +		compatible = "marvell,mv88e6085";
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		reg = <0>;
>> +		dsa,member = <0 0>;
>> +
>> +		ports {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +
>> +			port@0 {
>> +				reg = <0>;
>> +				label = "lan3";
>> +			};
>> +
>> +			port@1 {
>> +				reg = <1>;
>> +				label = "lan4";
>> +			};
>> +
>> +			port@2 {
>> +				reg = <2>;
>> +				label = "wan";
>> +			};
>> +
>> +			port@3 {
>> +				reg = <3>;
>> +				label = "cpu";
>> +			};
>> +
>> +			port@5 {
>> +				reg = <5>;
>> +				label = "lan1";
>> +			};
>> +
>> +			port@7 {
>> +				reg = <7>;
>> +				label = "lan2";
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&eth {
>> +	status = "okay";
>> +
>> +	ethernet-port@0 {
>> +		/* Hardwired to DSA switch */
>> +		speed = <1000>;
>> +		duplex = <1>;
>> +	};
>> +};
>> +
>> +&pinctrl {
>> +	pinctrl-0 = <&pmx_pci_gpios>;
>> +	pinctrl-names = "default";
>> +
>> +	pmx_power_led: pmx-power-led {
>> +		marvell,pins = "mpp0";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_reset_button: pmx-reset-button {
>> +		marvell,pins = "mpp1";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_power_led_blink: pmx-power-led-blink {
>> +		marvell,pins = "mpp2";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_wan_led: pmx-wan-led {
>> +		marvell,pins = "mpp3";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_pci_gpios: pmx-pci-gpios {
>> +		marvell,pins = "mpp4";
>> +		marvell,function = "gpio";
>> +	};
>> +};
>> +
>> +&uart0 {
>> +	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
>> index 89bb0fc..9acb37b 100644
>> --- a/arch/arm/mach-orion5x/Kconfig
>> +++ b/arch/arm/mach-orion5x/Kconfig
>> @@ -151,6 +151,12 @@ config MACH_MSS2_DT
>>  	  Say 'Y' here if you want your kernel to support the
>>  	  Maxtor Shared Storage II platform.
>>
>> +config MACH_WNR854T_DT
>> +	bool "Netgear WNR854T (Flattened Device Tree)"
>> +	help
>> +	  Say 'Y' here if you want your kernel to support the
>> +	  Netgear WNR854T platform.
>> +
>>  config MACH_WNR854T
>>  	bool "Netgear WNR854T"
>>  	help
>> diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
>> index 4b2502b..9dff2d3 100644
>> --- a/arch/arm/mach-orion5x/Makefile
>> +++ b/arch/arm/mach-orion5x/Makefile
>> @@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
>>  obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
>>  obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
>>  obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
>> +obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o
>> diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c
>> new file mode 100644
>> index 0000000..c506e33
>> --- /dev/null
>> +++ b/arch/arm/mach-orion5x/board-wnr854t.c
>> @@ -0,0 +1,78 @@
>> +/*
>> + * Netgear WNR854T PCI setup
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +#include <linux/gpio.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pci.h>
>> +#include <asm/mach/pci.h>
>> +#include "common.h"
>> +#include "orion5x.h"
>> +
>> +#define WNR854T_PCI_SLOT0_OFFS	7
>> +#define WNR854T_PCI_SLOT0_IRQ_PIN	4
>> +
>> +static void __init wnr854t_pci_preinit(void)
>> +{
>> +	int pin;
>> +
>> +	/*
>> +	 * Configure PCI GPIO IRQ pins
>> +	 */
>> +	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
>> +	if (gpio_request(pin, "PCI Int") == 0) {
>> +		if (gpio_direction_input(pin) == 0) {
>> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
>> +		} else {
>> +			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
>> +				pin);
>> +			gpio_free(pin);
>> +		}
>> +	} else {
>> +		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
>> +	}
>> +}
>> +
>> +static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
>> +	u8 pin)
>> +{
>> +	int irq;
>> +
>> +	/*
>> +	 * Check for devices with hard-wired IRQs.
>> +	 */
>> +	irq = orion5x_pci_map_irq(dev, slot, pin);
>> +	if (irq != -1)
>> +		return irq;
>> +
>> +	/*
>> +	 * PCI IRQs are connected via GPIOs
>> +	 */
>> +	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
>> +	case 0:
>> +		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
>> +	default:
>> +		return -1;
>> +	}
>> +}
>> +
>> +static struct hw_pci wnr854t_pci __initdata = {
>> +	.nr_controllers	= 2,
>> +	.preinit	= wnr854t_pci_preinit,
>> +	.setup		= orion5x_pci_sys_setup,
>> +	.scan		= orion5x_pci_sys_scan_bus,
>> +	.map_irq	= wnr854t_pci_map_irq,
>> +};
>> +
>> +static int __init wnr854t_pci_init(void)
>> +{
>> +	if (of_machine_is_compatible("netgear,wnr854t"))
>> +		pci_common_init(&wnr854t_pci);
>> +
>> +	return 0;
>> +}
>> +/* NB: Use late_initcall so we can gpio_request() without being deferred */
>> +late_initcall(wnr854t_pci_init);
>> --
>> 2.8.1
>>
>
>

-- 
Jamie Lentin
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[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On Thu, 8 Sep 2016, Gregory CLEMENT wrote:

> Hi Jamie,
>
> On lun., sept. 05 2016, Jamie Lentin <jm@lentin.co.uk> wrote:
>
>> This is a router based on the mv88f5181 chipset.
>>
>> http://www.netgear.com/support/product/WNR854T.aspx
>> http://wiki.openwrt.org/toh/netgear/wnr854t
>>
>> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
>> ---
>> This removes the contentious vendor partitioning scheme and goes back
>> to the original partitioning scheme used in non-DT ports to this board.
>> Using the same partitioning scheme should mean less surprises for
>> someone trying to upgrade their router.
>>
>> The non-DT PCI setup is still here, as there are other orion5x DT boards
>> doing very similar things, and can all be converted at the same time.
>
> I only noticed today your v2. I expected a full series actually.

It seemed excessive to spam the entire patchset out again, of course I can 
if it makes your life easier.

> I am
> now taking care of it. I mainly have to rename most of the commit titles
> as they do not really match the subsystem where they will be applied.

Thanks, let me know if I can make myself useful.

> I will apply all of them on the mvebu branches to avoid to more
> dependency issue. However, we are very close to the end of the merge
> window for arm-soc. I will do my best, but the merge of the series could
> be delayed to 4.10.
>
> Thanks,
>
> Gregory
>
>
>>
>> The patchset in it's entirety is available at
>> https://github.com/lentinj/linux wnr854t-support-v2
>>
>> Cheers,
>> ---
>>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>>  arch/arm/boot/dts/Makefile                         |   1 +
>>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 197 +++++++++++++++++++++
>>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>>  arch/arm/mach-orion5x/Makefile                     |   1 +
>>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
>>  6 files changed, 284 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>>  create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c
>>
>> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> index ff3c120..748a8f2 100644
>> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
>> @@ -22,3 +22,4 @@ board. Currently known boards are:
>>  "lacie,d2-network"
>>  "marvell,rd-88f5182-nas"
>>  "maxtor,shared-storage-2"
>> +"netgear,wnr854t"
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index faacd52..4588b3c 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
>>  	orion5x-linkstation-lswtgl.dtb \
>>  	orion5x-lswsgl.dtb \
>>  	orion5x-maxtor-shared-storage-2.dtb \
>> +	orion5x-netgear-wnr854t.dtb \
>>  	orion5x-rd88f5182-nas.dtb
>>  dtb-$(CONFIG_ARCH_PRIMA2) += \
>>  	prima2-evb.dtb
>> diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>> new file mode 100644
>> index 0000000..cce5091
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>> @@ -0,0 +1,197 @@
>> +/*
>> + * Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +#include "orion5x-mv88f5181.dtsi"
>> +
>> +/ {
>> +	model = "Netgear WNR854-t";
>> +	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
>> +		     "marvell,orion5x";
>> +
>> +	memory {
>> +		reg = <0x00000000 0x2000000>; /* 32 MB */
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +
>> +	soc {
>> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
>> +			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
>> +			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
>> +	};
>> +
>> +	gpio-keys {
>> +		compatible = "gpio-keys";
>> +		pinctrl-0 = <&pmx_reset_button>;
>> +		pinctrl-names = "default";
>> +
>> +		reset {
>> +			label = "Reset Button";
>> +			linux,code = <KEY_RESTART>;
>> +			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
>> +		};
>> +	};
>> +
>> +	gpio-leds {
>> +		compatible = "gpio-leds";
>> +		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
>> +		pinctrl-names = "default";
>> +
>> +		led at 0 {
>> +			label = "wnr854t:green:power";
>> +			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
>> +		};
>> +
>> +		led at 1 {
>> +			label = "wnr854t:blink:power";
>> +			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
>> +		};
>> +
>> +		led at 2 {
>> +			label = "wnr854t:green:wan";
>> +			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
>> +		};
>> +	};
>> +};
>> +
>> +&devbus_bootcs {
>> +	status = "okay";
>> +
>> +	devbus,keep-config;
>> +
>> +	flash at 0 {
>> +		compatible = "cfi-flash";
>> +		reg = <0 0x800000>;
>> +		bank-width = <2>;
>> +
>> +		partitions {
>> +			compatible = "fixed-partitions";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +
>> +			partition at 0 {
>> +				label = "kernel";
>> +				reg = <0x0 0x100000>;
>> +			};
>> +
>> +			partition at 100000 {
>> +				label = "rootfs";
>> +				reg = <0x100000 0x660000>;
>> +			};
>> +
>> +			partition at 760000 {
>> +				label = "uboot_env";
>> +				reg = <0x760000 0x20000>;
>> +			};
>> +
>> +			partition at 780000 {
>> +				label = "uboot";
>> +				reg = <0x780000 0x80000>;
>> +				read-only;
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&mdio {
>> +	status = "okay";
>> +
>> +	switch: switch at 0 {
>> +		compatible = "marvell,mv88e6085";
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		reg = <0>;
>> +		dsa,member = <0 0>;
>> +
>> +		ports {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +
>> +			port at 0 {
>> +				reg = <0>;
>> +				label = "lan3";
>> +			};
>> +
>> +			port at 1 {
>> +				reg = <1>;
>> +				label = "lan4";
>> +			};
>> +
>> +			port at 2 {
>> +				reg = <2>;
>> +				label = "wan";
>> +			};
>> +
>> +			port at 3 {
>> +				reg = <3>;
>> +				label = "cpu";
>> +			};
>> +
>> +			port at 5 {
>> +				reg = <5>;
>> +				label = "lan1";
>> +			};
>> +
>> +			port at 7 {
>> +				reg = <7>;
>> +				label = "lan2";
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&eth {
>> +	status = "okay";
>> +
>> +	ethernet-port at 0 {
>> +		/* Hardwired to DSA switch */
>> +		speed = <1000>;
>> +		duplex = <1>;
>> +	};
>> +};
>> +
>> +&pinctrl {
>> +	pinctrl-0 = <&pmx_pci_gpios>;
>> +	pinctrl-names = "default";
>> +
>> +	pmx_power_led: pmx-power-led {
>> +		marvell,pins = "mpp0";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_reset_button: pmx-reset-button {
>> +		marvell,pins = "mpp1";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_power_led_blink: pmx-power-led-blink {
>> +		marvell,pins = "mpp2";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_wan_led: pmx-wan-led {
>> +		marvell,pins = "mpp3";
>> +		marvell,function = "gpio";
>> +	};
>> +
>> +	pmx_pci_gpios: pmx-pci-gpios {
>> +		marvell,pins = "mpp4";
>> +		marvell,function = "gpio";
>> +	};
>> +};
>> +
>> +&uart0 {
>> +	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
>> index 89bb0fc..9acb37b 100644
>> --- a/arch/arm/mach-orion5x/Kconfig
>> +++ b/arch/arm/mach-orion5x/Kconfig
>> @@ -151,6 +151,12 @@ config MACH_MSS2_DT
>>  	  Say 'Y' here if you want your kernel to support the
>>  	  Maxtor Shared Storage II platform.
>>
>> +config MACH_WNR854T_DT
>> +	bool "Netgear WNR854T (Flattened Device Tree)"
>> +	help
>> +	  Say 'Y' here if you want your kernel to support the
>> +	  Netgear WNR854T platform.
>> +
>>  config MACH_WNR854T
>>  	bool "Netgear WNR854T"
>>  	help
>> diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
>> index 4b2502b..9dff2d3 100644
>> --- a/arch/arm/mach-orion5x/Makefile
>> +++ b/arch/arm/mach-orion5x/Makefile
>> @@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_ORION5X_DT)		+= board-dt.o
>>  obj-$(CONFIG_MACH_D2NET_DT)	+= board-d2net.o
>>  obj-$(CONFIG_MACH_MSS2_DT)	+= board-mss2.o
>>  obj-$(CONFIG_MACH_RD88F5182_DT)	+= board-rd88f5182.o
>> +obj-$(CONFIG_MACH_WNR854T_DT)	+= board-wnr854t.o
>> diff --git a/arch/arm/mach-orion5x/board-wnr854t.c b/arch/arm/mach-orion5x/board-wnr854t.c
>> new file mode 100644
>> index 0000000..c506e33
>> --- /dev/null
>> +++ b/arch/arm/mach-orion5x/board-wnr854t.c
>> @@ -0,0 +1,78 @@
>> +/*
>> + * Netgear WNR854T PCI setup
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +#include <linux/gpio.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pci.h>
>> +#include <asm/mach/pci.h>
>> +#include "common.h"
>> +#include "orion5x.h"
>> +
>> +#define WNR854T_PCI_SLOT0_OFFS	7
>> +#define WNR854T_PCI_SLOT0_IRQ_PIN	4
>> +
>> +static void __init wnr854t_pci_preinit(void)
>> +{
>> +	int pin;
>> +
>> +	/*
>> +	 * Configure PCI GPIO IRQ pins
>> +	 */
>> +	pin = WNR854T_PCI_SLOT0_IRQ_PIN;
>> +	if (gpio_request(pin, "PCI Int") == 0) {
>> +		if (gpio_direction_input(pin) == 0) {
>> +			irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
>> +		} else {
>> +			pr_err("wnr854t_pci_preinit failed to set_irq_type pin %d\n",
>> +				pin);
>> +			gpio_free(pin);
>> +		}
>> +	} else {
>> +		pr_err("wnr854t_pci_preinit failed to request gpio %d\n", pin);
>> +	}
>> +}
>> +
>> +static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
>> +	u8 pin)
>> +{
>> +	int irq;
>> +
>> +	/*
>> +	 * Check for devices with hard-wired IRQs.
>> +	 */
>> +	irq = orion5x_pci_map_irq(dev, slot, pin);
>> +	if (irq != -1)
>> +		return irq;
>> +
>> +	/*
>> +	 * PCI IRQs are connected via GPIOs
>> +	 */
>> +	switch (slot - WNR854T_PCI_SLOT0_OFFS) {
>> +	case 0:
>> +		return gpio_to_irq(WNR854T_PCI_SLOT0_IRQ_PIN);
>> +	default:
>> +		return -1;
>> +	}
>> +}
>> +
>> +static struct hw_pci wnr854t_pci __initdata = {
>> +	.nr_controllers	= 2,
>> +	.preinit	= wnr854t_pci_preinit,
>> +	.setup		= orion5x_pci_sys_setup,
>> +	.scan		= orion5x_pci_sys_scan_bus,
>> +	.map_irq	= wnr854t_pci_map_irq,
>> +};
>> +
>> +static int __init wnr854t_pci_init(void)
>> +{
>> +	if (of_machine_is_compatible("netgear,wnr854t"))
>> +		pci_common_init(&wnr854t_pci);
>> +
>> +	return 0;
>> +}
>> +/* NB: Use late_initcall so we can gpio_request() without being deferred */
>> +late_initcall(wnr854t_pci_init);
>> --
>> 2.8.1
>>
>
>

-- 
Jamie Lentin

Re: [PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Rob Herring]

On Mon, Sep 05, 2016 at 10:07:26PM +0100, Jamie Lentin wrote:
> This is a router based on the mv88f5181 chipset.
> 
> http://www.netgear.com/support/product/WNR854T.aspx
> http://wiki.openwrt.org/toh/netgear/wnr854t
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
> This removes the contentious vendor partitioning scheme and goes back
> to the original partitioning scheme used in non-DT ports to this board.
> Using the same partitioning scheme should mean less surprises for
> someone trying to upgrade their router.
> 
> The non-DT PCI setup is still here, as there are other orion5x DT boards
> doing very similar things, and can all be converted at the same time.

If we keep accepting this duplicated, legacy PCI setup, who is going to 
be motivated to clean things up. But it's ultimately up to Arnd and 
Olof.

 
> The patchset in it's entirety is available at
> https://github.com/lentinj/linux wnr854t-support-v2
> 
> Cheers,
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 197 +++++++++++++++++++++

Acked-by: Rob Herring <robh@kernel.org>

>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>  arch/arm/mach-orion5x/Makefile                     |   1 +
>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
>  6 files changed, 284 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>  create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Rob Herring]

On Mon, Sep 05, 2016 at 10:07:26PM +0100, Jamie Lentin wrote:
> This is a router based on the mv88f5181 chipset.
> 
> http://www.netgear.com/support/product/WNR854T.aspx
> http://wiki.openwrt.org/toh/netgear/wnr854t
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
> This removes the contentious vendor partitioning scheme and goes back
> to the original partitioning scheme used in non-DT ports to this board.
> Using the same partitioning scheme should mean less surprises for
> someone trying to upgrade their router.
> 
> The non-DT PCI setup is still here, as there are other orion5x DT boards
> doing very similar things, and can all be converted at the same time.

If we keep accepting this duplicated, legacy PCI setup, who is going to 
be motivated to clean things up. But it's ultimately up to Arnd and 
Olof.

 
> The patchset in it's entirety is available at
> https://github.com/lentinj/linux wnr854t-support-v2
> 
> Cheers,
> ---
>  .../bindings/arm/marvell/marvell,orion5x.txt       |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/orion5x-netgear-wnr854t.dts      | 197 +++++++++++++++++++++

Acked-by: Rob Herring <robh@kernel.org>

>  arch/arm/mach-orion5x/Kconfig                      |   6 +
>  arch/arm/mach-orion5x/Makefile                     |   1 +
>  arch/arm/mach-orion5x/board-wnr854t.c              |  78 ++++++++
>  6 files changed, 284 insertions(+)
>  create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
>  create mode 100644 arch/arm/mach-orion5x/board-wnr854t.c

Re: [PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Monday, September 12, 2016 12:06:25 PM CEST Rob Herring wrote:
> On Mon, Sep 05, 2016 at 10:07:26PM +0100, Jamie Lentin wrote:
> > This is a router based on the mv88f5181 chipset.
> > 
> > http://www.netgear.com/support/product/WNR854T.aspx
> > http://wiki.openwrt.org/toh/netgear/wnr854t
> > 
> > Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
> > ---
> > This removes the contentious vendor partitioning scheme and goes back
> > to the original partitioning scheme used in non-DT ports to this board.
> > Using the same partitioning scheme should mean less surprises for
> > someone trying to upgrade their router.
> > 
> > The non-DT PCI setup is still here, as there are other orion5x DT boards
> > doing very similar things, and can all be converted at the same time.
> 
> If we keep accepting this duplicated, legacy PCI setup, who is going to 
> be motivated to clean things up. But it's ultimately up to Arnd and 
> Olof.
> 

I mentioned before that I'm feeling a bit uneasy about this too.

Maybe we can instead leave out the PCI support from the new
file for now and not delete the legacy board file?

	Arnd

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[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Monday, September 12, 2016 12:06:25 PM CEST Rob Herring wrote:
> On Mon, Sep 05, 2016 at 10:07:26PM +0100, Jamie Lentin wrote:
> > This is a router based on the mv88f5181 chipset.
> > 
> > http://www.netgear.com/support/product/WNR854T.aspx
> > http://wiki.openwrt.org/toh/netgear/wnr854t
> > 
> > Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> > ---
> > This removes the contentious vendor partitioning scheme and goes back
> > to the original partitioning scheme used in non-DT ports to this board.
> > Using the same partitioning scheme should mean less surprises for
> > someone trying to upgrade their router.
> > 
> > The non-DT PCI setup is still here, as there are other orion5x DT boards
> > doing very similar things, and can all be converted at the same time.
> 
> If we keep accepting this duplicated, legacy PCI setup, who is going to 
> be motivated to clean things up. But it's ultimately up to Arnd and 
> Olof.
> 

I mentioned before that I'm feeling a bit uneasy about this too.

Maybe we can instead leave out the PCI support from the new
file for now and not delete the legacy board file?

	Arnd

Re: [PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Monday, September 12, 2016 11:13:33 PM CEST Arnd Bergmann wrote:
> On Monday, September 12, 2016 12:06:25 PM CEST Rob Herring wrote:
> > On Mon, Sep 05, 2016 at 10:07:26PM +0100, Jamie Lentin wrote:
> > > This is a router based on the mv88f5181 chipset.
> > > 
> > > http://www.netgear.com/support/product/WNR854T.aspx
> > > http://wiki.openwrt.org/toh/netgear/wnr854t
> > > 
> > > Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
> > > ---
> > > This removes the contentious vendor partitioning scheme and goes back
> > > to the original partitioning scheme used in non-DT ports to this board.
> > > Using the same partitioning scheme should mean less surprises for
> > > someone trying to upgrade their router.
> > > 
> > > The non-DT PCI setup is still here, as there are other orion5x DT boards
> > > doing very similar things, and can all be converted at the same time.
> > 
> > If we keep accepting this duplicated, legacy PCI setup, who is going to 
> > be motivated to clean things up. But it's ultimately up to Arnd and 
> > Olof.
> > 
> 
> I mentioned before that I'm feeling a bit uneasy about this too.
> 
> Maybe we can instead leave out the PCI support from the new
> file for now and not delete the legacy board file?
> 

Another idea that has worked in the past is that we ask everyone
to do one piece of the puzzle. In this case that could be to
convert the existing PCI support to a proper host driver
in arch/arm/mach-orion5x/pci.c that is separate from the PCIe
support (for which we already have a driver IIRC) and have
it probed by calling pci_scan_root_bus() from a platform
driver init function. The next person who wants DT suppor for
an existing orion machine can then add DT support to that driver.

	Arnd

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[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Monday, September 12, 2016 11:13:33 PM CEST Arnd Bergmann wrote:
> On Monday, September 12, 2016 12:06:25 PM CEST Rob Herring wrote:
> > On Mon, Sep 05, 2016 at 10:07:26PM +0100, Jamie Lentin wrote:
> > > This is a router based on the mv88f5181 chipset.
> > > 
> > > http://www.netgear.com/support/product/WNR854T.aspx
> > > http://wiki.openwrt.org/toh/netgear/wnr854t
> > > 
> > > Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> > > ---
> > > This removes the contentious vendor partitioning scheme and goes back
> > > to the original partitioning scheme used in non-DT ports to this board.
> > > Using the same partitioning scheme should mean less surprises for
> > > someone trying to upgrade their router.
> > > 
> > > The non-DT PCI setup is still here, as there are other orion5x DT boards
> > > doing very similar things, and can all be converted at the same time.
> > 
> > If we keep accepting this duplicated, legacy PCI setup, who is going to 
> > be motivated to clean things up. But it's ultimately up to Arnd and 
> > Olof.
> > 
> 
> I mentioned before that I'm feeling a bit uneasy about this too.
> 
> Maybe we can instead leave out the PCI support from the new
> file for now and not delete the legacy board file?
> 

Another idea that has worked in the past is that we ask everyone
to do one piece of the puzzle. In this case that could be to
convert the existing PCI support to a proper host driver
in arch/arm/mach-orion5x/pci.c that is separate from the PCIe
support (for which we already have a driver IIRC) and have
it probed by calling pci_scan_root_bus() from a platform
driver init function. The next person who wants DT suppor for
an existing orion machine can then add DT support to that driver.

	Arnd

Re: [PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Andrew Lunn]

> Maybe we can instead leave out the PCI support from the new
> file for now and not delete the legacy board file?

Jamie, which interrupt do you see the WiFi card using?  If it is
IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with
than if it uses GPIO 4.

Thanks
     Andrew
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[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Andrew Lunn]

> Maybe we can instead leave out the PCI support from the new
> file for now and not delete the legacy board file?

Jamie, which interrupt do you see the WiFi card using?  If it is
IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with
than if it uses GPIO 4.

Thanks
     Andrew

Re: [PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On 2016-09-12 23:03, Andrew Lunn wrote:
>> Maybe we can instead leave out the PCI support from the new
>> file for now and not delete the legacy board file?

This seems a reasonable compromise. The PCI card the router comes with 
isn't supported by mwl8k mainline anyway (There's STA-only firmware that 
can be extracted from a windows driver and PCI IDs added, but stats 
reporting uses a different format), so it's not a huge loss, although 
many did replace the card with something Atheros-based.

Unfortunately the power regulator on my spare router has stopped 
regulating, which will make more development tricky. But will have a 
look at the PCI conversion if I can get hold of another.

> Jamie, which interrupt do you see the WiFi card using?  If it is
> IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with
> than if it uses GPIO 4.

Definitely uses GPIO 4.

# cat /proc/interrupts
            CPU0
  17:     165966  bridge-interrupt-ctrl   2 Edge      orion_event
  22:       5119  interrupt-controller   3 Edge      serial
  24:          0  bridge-interrupt-ctrl   3 Edge      orion_wdt
  25:      89504  interrupt-controller  22 Edge      f1072004.mdio-bus
  28:          1  f1010100.gpio   1 Edge      Reset Button
  31:        598  f1010100.gpio   4 Level     mwl8k
  59:        985  interrupt-controller  21 Edge      eth0
Err:          0
# iw dev wlan0 scan > /dev/null ; cat /proc/interrupts
            CPU0
  17:     166424  bridge-interrupt-ctrl   2 Edge      orion_event
  22:       5250  interrupt-controller   3 Edge      serial
  24:          0  bridge-interrupt-ctrl   3 Edge      orion_wdt
  25:      89748  interrupt-controller  22 Edge      f1072004.mdio-bus
  28:          1  f1010100.gpio   1 Edge      Reset Button
  31:        708  f1010100.gpio   4 Level     mwl8k
  59:        985  interrupt-controller  21 Edge      eth0
Err:          0
# sleep 10 ; cat /proc/interrupts
            CPU0
  17:     167985  bridge-interrupt-ctrl   2 Edge      orion_event
  22:       5349  interrupt-controller   3 Edge      serial
  24:          0  bridge-interrupt-ctrl   3 Edge      orion_wdt
  25:      90603  interrupt-controller  22 Edge      f1072004.mdio-bus
  28:          1  f1010100.gpio   1 Edge      Reset Button
  31:        708  f1010100.gpio   4 Level     mwl8k
  59:        995  interrupt-controller  21 Edge      eth0
Err:          0
# iw dev wlan0 scan > /dev/null ; cat /proc/interrupts
            CPU0
  17:     168270  bridge-interrupt-ctrl   2 Edge      orion_event
  22:       5480  interrupt-controller   3 Edge      serial
  24:          0  bridge-interrupt-ctrl   3 Edge      orion_wdt
  25:      90727  interrupt-controller  22 Edge      f1072004.mdio-bus
  28:          1  f1010100.gpio   1 Edge      Reset Button
  31:        818  f1010100.gpio   4 Level     mwl8k
  59:        996  interrupt-controller  21 Edge      eth0
Err:          0

> 
> Thanks
>      Andrew
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[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On 2016-09-12 23:03, Andrew Lunn wrote:
>> Maybe we can instead leave out the PCI support from the new
>> file for now and not delete the legacy board file?

This seems a reasonable compromise. The PCI card the router comes with 
isn't supported by mwl8k mainline anyway (There's STA-only firmware that 
can be extracted from a windows driver and PCI IDs added, but stats 
reporting uses a different format), so it's not a huge loss, although 
many did replace the card with something Atheros-based.

Unfortunately the power regulator on my spare router has stopped 
regulating, which will make more development tricky. But will have a 
look at the PCI conversion if I can get hold of another.

> Jamie, which interrupt do you see the WiFi card using?  If it is
> IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with
> than if it uses GPIO 4.

Definitely uses GPIO 4.

# cat /proc/interrupts
            CPU0
  17:     165966  bridge-interrupt-ctrl   2 Edge      orion_event
  22:       5119  interrupt-controller   3 Edge      serial
  24:          0  bridge-interrupt-ctrl   3 Edge      orion_wdt
  25:      89504  interrupt-controller  22 Edge      f1072004.mdio-bus
  28:          1  f1010100.gpio   1 Edge      Reset Button
  31:        598  f1010100.gpio   4 Level     mwl8k
  59:        985  interrupt-controller  21 Edge      eth0
Err:          0
# iw dev wlan0 scan > /dev/null ; cat /proc/interrupts
            CPU0
  17:     166424  bridge-interrupt-ctrl   2 Edge      orion_event
  22:       5250  interrupt-controller   3 Edge      serial
  24:          0  bridge-interrupt-ctrl   3 Edge      orion_wdt
  25:      89748  interrupt-controller  22 Edge      f1072004.mdio-bus
  28:          1  f1010100.gpio   1 Edge      Reset Button
  31:        708  f1010100.gpio   4 Level     mwl8k
  59:        985  interrupt-controller  21 Edge      eth0
Err:          0
# sleep 10 ; cat /proc/interrupts
            CPU0
  17:     167985  bridge-interrupt-ctrl   2 Edge      orion_event
  22:       5349  interrupt-controller   3 Edge      serial
  24:          0  bridge-interrupt-ctrl   3 Edge      orion_wdt
  25:      90603  interrupt-controller  22 Edge      f1072004.mdio-bus
  28:          1  f1010100.gpio   1 Edge      Reset Button
  31:        708  f1010100.gpio   4 Level     mwl8k
  59:        995  interrupt-controller  21 Edge      eth0
Err:          0
# iw dev wlan0 scan > /dev/null ; cat /proc/interrupts
            CPU0
  17:     168270  bridge-interrupt-ctrl   2 Edge      orion_event
  22:       5480  interrupt-controller   3 Edge      serial
  24:          0  bridge-interrupt-ctrl   3 Edge      orion_wdt
  25:      90727  interrupt-controller  22 Edge      f1072004.mdio-bus
  28:          1  f1010100.gpio   1 Edge      Reset Button
  31:        818  f1010100.gpio   4 Level     mwl8k
  59:        996  interrupt-controller  21 Edge      eth0
Err:          0

> 
> Thanks
>      Andrew

Re: [PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Andrew Lunn]

On Tue, Sep 13, 2016 at 10:10:41AM +0100, Jamie Lentin wrote:
> On 2016-09-12 23:03, Andrew Lunn wrote:
> >>Maybe we can instead leave out the PCI support from the new
> >>file for now and not delete the legacy board file?
> 
> This seems a reasonable compromise. The PCI card the router comes
> with isn't supported by mwl8k mainline anyway (There's STA-only
> firmware that can be extracted from a windows driver and PCI IDs
> added, but stats reporting uses a different format), so it's not a
> huge loss, although many did replace the card with something
> Atheros-based.

O.K. So dropping the PCI code gets us going forward.
Have we missed the merge window?

> Unfortunately the power regulator on my spare router has stopped
> regulating, which will make more development tricky.

The Green Light of death?

> >Jamie, which interrupt do you see the WiFi card using?  If it is
> >IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with
> >than if it uses GPIO 4.
> 
> Definitely uses GPIO 4.

O.K, that makes it more interesting. As far as i can see, no other
PCIe system uses a GPIO for its interrupt. There is no core support
for this, or any bus driver doing it. So there is no binding to
follow.

	Andrew
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[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Andrew Lunn]

On Tue, Sep 13, 2016 at 10:10:41AM +0100, Jamie Lentin wrote:
> On 2016-09-12 23:03, Andrew Lunn wrote:
> >>Maybe we can instead leave out the PCI support from the new
> >>file for now and not delete the legacy board file?
> 
> This seems a reasonable compromise. The PCI card the router comes
> with isn't supported by mwl8k mainline anyway (There's STA-only
> firmware that can be extracted from a windows driver and PCI IDs
> added, but stats reporting uses a different format), so it's not a
> huge loss, although many did replace the card with something
> Atheros-based.

O.K. So dropping the PCI code gets us going forward.
Have we missed the merge window?

> Unfortunately the power regulator on my spare router has stopped
> regulating, which will make more development tricky.

The Green Light of death?

> >Jamie, which interrupt do you see the WiFi card using?  If it is
> >IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with
> >than if it uses GPIO 4.
> 
> Definitely uses GPIO 4.

O.K, that makes it more interesting. As far as i can see, no other
PCIe system uses a GPIO for its interrupt. There is no core support
for this, or any bus driver doing it. So there is no binding to
follow.

	Andrew

Re: [PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On 2016-09-13 13:36, Andrew Lunn wrote:
> On Tue, Sep 13, 2016 at 10:10:41AM +0100, Jamie Lentin wrote:
>> On 2016-09-12 23:03, Andrew Lunn wrote:
>> >>Maybe we can instead leave out the PCI support from the new
>> >>file for now and not delete the legacy board file?
>> 
>> This seems a reasonable compromise. The PCI card the router comes
>> with isn't supported by mwl8k mainline anyway (There's STA-only
>> firmware that can be extracted from a windows driver and PCI IDs
>> added, but stats reporting uses a different format), so it's not a
>> huge loss, although many did replace the card with something
>> Atheros-based.
> 
> O.K. So dropping the PCI code gets us going forward.

Is an arch/arm/mach-mvebu/orion5x.c also required? Or is continuing to 
use arch/arm/mach-orion5x/board-dt.c until everything has been converted 
the favoured approach?

> Have we missed the merge window?

I got the impression Gregory Clement had merged them? If not a good 
portion of this patchset is uncontroversial generic orion5x stuff, it'd 
be nice to get those in even if none of the router-specific stuff 
doesn't make it.

>> Unfortunately the power regulator on my spare router has stopped
>> regulating, which will make more development tricky.
> 
> The Green Light of death?

Seems that way, the 3.3v line is only getting up to 2.8v. My routers 
have had their power supply sections hacked in comparison to photos I've 
seen on GLOD pages, so I presumed this was fixed. Apparently not. Maybe 
I can persuade it to be useful with 5v + 3.3v in the right places.

>> >Jamie, which interrupt do you see the WiFi card using?  If it is
>> >IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with
>> >than if it uses GPIO 4.
>> 
>> Definitely uses GPIO 4.
> 
> O.K, that makes it more interesting. As far as i can see, no other
> PCIe system uses a GPIO for its interrupt. There is no core support
> for this, or any bus driver doing it. So there is no binding to
> follow.

Not sure if the difference is relevant at this point but it's regular 
PCI, not PCIe.

> 
> 	Andrew
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[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Jamie Lentin]

On 2016-09-13 13:36, Andrew Lunn wrote:
> On Tue, Sep 13, 2016 at 10:10:41AM +0100, Jamie Lentin wrote:
>> On 2016-09-12 23:03, Andrew Lunn wrote:
>> >>Maybe we can instead leave out the PCI support from the new
>> >>file for now and not delete the legacy board file?
>> 
>> This seems a reasonable compromise. The PCI card the router comes
>> with isn't supported by mwl8k mainline anyway (There's STA-only
>> firmware that can be extracted from a windows driver and PCI IDs
>> added, but stats reporting uses a different format), so it's not a
>> huge loss, although many did replace the card with something
>> Atheros-based.
> 
> O.K. So dropping the PCI code gets us going forward.

Is an arch/arm/mach-mvebu/orion5x.c also required? Or is continuing to 
use arch/arm/mach-orion5x/board-dt.c until everything has been converted 
the favoured approach?

> Have we missed the merge window?

I got the impression Gregory Clement had merged them? If not a good 
portion of this patchset is uncontroversial generic orion5x stuff, it'd 
be nice to get those in even if none of the router-specific stuff 
doesn't make it.

>> Unfortunately the power regulator on my spare router has stopped
>> regulating, which will make more development tricky.
> 
> The Green Light of death?

Seems that way, the 3.3v line is only getting up to 2.8v. My routers 
have had their power supply sections hacked in comparison to photos I've 
seen on GLOD pages, so I presumed this was fixed. Apparently not. Maybe 
I can persuade it to be useful with 5v + 3.3v in the right places.

>> >Jamie, which interrupt do you see the WiFi card using?  If it is
>> >IRQ_ORION5X_PCIE0_INT, (1 + 11), that is probably easier to deal with
>> >than if it uses GPIO 4.
>> 
>> Definitely uses GPIO 4.
> 
> O.K, that makes it more interesting. As far as i can see, no other
> PCIe system uses a GPIO for its interrupt. There is no core support
> for this, or any bus driver doing it. So there is no binding to
> follow.

Not sure if the difference is relevant at this point but it's regular 
PCI, not PCIe.

> 
> 	Andrew

Re: [PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Gregory CLEMENT]

Hi Jamie,
 
 On mar., sept. 13 2016, Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org> wrote:

> On 2016-09-13 13:36, Andrew Lunn wrote:
>> On Tue, Sep 13, 2016 at 10:10:41AM +0100, Jamie Lentin wrote:
>>> On 2016-09-12 23:03, Andrew Lunn wrote:
>>> >>Maybe we can instead leave out the PCI support from the new
>>> >>file for now and not delete the legacy board file?
>>>
>>> This seems a reasonable compromise. The PCI card the router comes
>>> with isn't supported by mwl8k mainline anyway (There's STA-only
>>> firmware that can be extracted from a windows driver and PCI IDs
>>> added, but stats reporting uses a different format), so it's not a
>>> huge loss, although many did replace the card with something
>>> Atheros-based.
>>
>> O.K. So dropping the PCI code gets us going forward.
>
> Is an arch/arm/mach-mvebu/orion5x.c also required? Or is continuing to
> use arch/arm/mach-orion5x/board-dt.c until everything has been
> converted the favoured approach?
>
>> Have we missed the merge window?
>
> I got the impression Gregory Clement had merged them? If not a good
> portion of this patchset is uncontroversial generic orion5x stuff,
> it'd be nice to get those in even if none of the router-specific stuff
> doesn't make it.

I applied on mvebu/for-next in order to find any merge conflict. It
seems ok on this side. However, I didn't make the pull request to
arm-soc with these patches so I fear it is too late.

Arnd would you agree to accept a new pull request?

Gregory


-- 
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Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Gregory CLEMENT]

Hi Jamie,
 
 On mar., sept. 13 2016, Jamie Lentin <jm@lentin.co.uk> wrote:

> On 2016-09-13 13:36, Andrew Lunn wrote:
>> On Tue, Sep 13, 2016 at 10:10:41AM +0100, Jamie Lentin wrote:
>>> On 2016-09-12 23:03, Andrew Lunn wrote:
>>> >>Maybe we can instead leave out the PCI support from the new
>>> >>file for now and not delete the legacy board file?
>>>
>>> This seems a reasonable compromise. The PCI card the router comes
>>> with isn't supported by mwl8k mainline anyway (There's STA-only
>>> firmware that can be extracted from a windows driver and PCI IDs
>>> added, but stats reporting uses a different format), so it's not a
>>> huge loss, although many did replace the card with something
>>> Atheros-based.
>>
>> O.K. So dropping the PCI code gets us going forward.
>
> Is an arch/arm/mach-mvebu/orion5x.c also required? Or is continuing to
> use arch/arm/mach-orion5x/board-dt.c until everything has been
> converted the favoured approach?
>
>> Have we missed the merge window?
>
> I got the impression Gregory Clement had merged them? If not a good
> portion of this patchset is uncontroversial generic orion5x stuff,
> it'd be nice to get those in even if none of the router-specific stuff
> doesn't make it.

I applied on mvebu/for-next in order to find any merge conflict. It
seems ok on this side. However, I didn't make the pull request to
arm-soc with these patches so I fear it is too late.

Arnd would you agree to accept a new pull request?

Gregory


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Tuesday, September 13, 2016 9:16:28 PM CEST Gregory CLEMENT wrote:
> Hi Jamie,
>  
>  On mar., sept. 13 2016, Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org> wrote:
> 
> > On 2016-09-13 13:36, Andrew Lunn wrote:
> >> On Tue, Sep 13, 2016 at 10:10:41AM +0100, Jamie Lentin wrote:
> >>> On 2016-09-12 23:03, Andrew Lunn wrote:
> >>> >>Maybe we can instead leave out the PCI support from the new
> >>> >>file for now and not delete the legacy board file?
> >>>
> >>> This seems a reasonable compromise. The PCI card the router comes
> >>> with isn't supported by mwl8k mainline anyway (There's STA-only
> >>> firmware that can be extracted from a windows driver and PCI IDs
> >>> added, but stats reporting uses a different format), so it's not a
> >>> huge loss, although many did replace the card with something
> >>> Atheros-based.
> >>
> >> O.K. So dropping the PCI code gets us going forward.
> >
> > Is an arch/arm/mach-mvebu/orion5x.c also required? Or is continuing to
> > use arch/arm/mach-orion5x/board-dt.c until everything has been
> > converted the favoured approach?
> >
> >> Have we missed the merge window?
> >
> > I got the impression Gregory Clement had merged them? If not a good
> > portion of this patchset is uncontroversial generic orion5x stuff,
> > it'd be nice to get those in even if none of the router-specific stuff
> > doesn't make it.
> 
> I applied on mvebu/for-next in order to find any merge conflict. It
> seems ok on this side. However, I didn't make the pull request to
> arm-soc with these patches so I fear it is too late.
> 
> Arnd would you agree to accept a new pull request?

Yes, please just send it. We are a bit backlogged on pull requests,
but because you got all the other pull requests to us early, you can
always have a couple of late changes on top that we would normally
pull.

	Arnd

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[PATCH 6/8 v2] arm: orion5x: Add DT-based support for Netgear WNR854T

[Arnd Bergmann]

On Tuesday, September 13, 2016 9:16:28 PM CEST Gregory CLEMENT wrote:
> Hi Jamie,
>  
>  On mar., sept. 13 2016, Jamie Lentin <jm@lentin.co.uk> wrote:
> 
> > On 2016-09-13 13:36, Andrew Lunn wrote:
> >> On Tue, Sep 13, 2016 at 10:10:41AM +0100, Jamie Lentin wrote:
> >>> On 2016-09-12 23:03, Andrew Lunn wrote:
> >>> >>Maybe we can instead leave out the PCI support from the new
> >>> >>file for now and not delete the legacy board file?
> >>>
> >>> This seems a reasonable compromise. The PCI card the router comes
> >>> with isn't supported by mwl8k mainline anyway (There's STA-only
> >>> firmware that can be extracted from a windows driver and PCI IDs
> >>> added, but stats reporting uses a different format), so it's not a
> >>> huge loss, although many did replace the card with something
> >>> Atheros-based.
> >>
> >> O.K. So dropping the PCI code gets us going forward.
> >
> > Is an arch/arm/mach-mvebu/orion5x.c also required? Or is continuing to
> > use arch/arm/mach-orion5x/board-dt.c until everything has been
> > converted the favoured approach?
> >
> >> Have we missed the merge window?
> >
> > I got the impression Gregory Clement had merged them? If not a good
> > portion of this patchset is uncontroversial generic orion5x stuff,
> > it'd be nice to get those in even if none of the router-specific stuff
> > doesn't make it.
> 
> I applied on mvebu/for-next in order to find any merge conflict. It
> seems ok on this side. However, I didn't make the pull request to
> arm-soc with these patches so I fear it is too late.
> 
> Arnd would you agree to accept a new pull request?

Yes, please just send it. We are a bit backlogged on pull requests,
but because you got all the other pull requests to us early, you can
always have a couple of late changes on top that we would normally
pull.

	Arnd

[PATCH 7/8] arm: orion5x: Remove old non-DT-based WNR854T support

[Jamie Lentin]

The non-DT-based support is now redundant, remove it and replace it
with the DT-support in defconfigs.

Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
---
 arch/arm/configs/multi_v5_defconfig   |   2 +-
 arch/arm/configs/mvebu_v5_defconfig   |   2 +-
 arch/arm/configs/orion5x_defconfig    |   2 +-
 arch/arm/mach-orion5x/Kconfig         |   6 --
 arch/arm/mach-orion5x/Makefile        |   1 -
 arch/arm/mach-orion5x/wnr854t-setup.c | 185 ----------------------------------
 6 files changed, 3 insertions(+), 195 deletions(-)
 delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c

diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
index 2658b80..8b417b1 100644
--- a/arch/arm/configs/multi_v5_defconfig
+++ b/arch/arm/configs/multi_v5_defconfig
@@ -44,7 +44,7 @@ CONFIG_MACH_MV2120=y
 CONFIG_MACH_D2NET_DT=y
 CONFIG_MACH_NET2BIG=y
 CONFIG_MACH_MSS2_DT=y
-CONFIG_MACH_WNR854T=y
+CONFIG_MACH_WNR854T_DT=y
 CONFIG_MACH_RD88F5181L_GE=y
 CONFIG_MACH_RD88F5181L_FXO=y
 CONFIG_MACH_RD88F6183AP_GE=y
diff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig
index 6051c51..81dabae 100644
--- a/arch/arm/configs/mvebu_v5_defconfig
+++ b/arch/arm/configs/mvebu_v5_defconfig
@@ -31,7 +31,7 @@ CONFIG_MACH_MV2120=y
 CONFIG_MACH_D2NET_DT=y
 CONFIG_MACH_NET2BIG=y
 CONFIG_MACH_MSS2_DT=y
-CONFIG_MACH_WNR854T=y
+CONFIG_MACH_WNR854T_DT=y
 CONFIG_MACH_RD88F5181L_GE=y
 CONFIG_MACH_RD88F5181L_FXO=y
 CONFIG_MACH_RD88F6183AP_GE=y
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index 27a70a7..93b63aa 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -37,7 +37,7 @@ CONFIG_MACH_D2NET=y
 CONFIG_MACH_BIGDISK=y
 CONFIG_MACH_NET2BIG=y
 CONFIG_MACH_MSS2=y
-CONFIG_MACH_WNR854T=y
+CONFIG_MACH_WNR854T_DT=y
 CONFIG_MACH_RD88F5181L_GE=y
 CONFIG_MACH_RD88F5181L_FXO=y
 CONFIG_MACH_RD88F6183AP_GE=y
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 9acb37b..7dff2a5 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -157,12 +157,6 @@ config MACH_WNR854T_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Netgear WNR854T platform.
 
-config MACH_WNR854T
-	bool "Netgear WNR854T"
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Netgear WNR854T platform.
-
 config MACH_RD88F5181L_GE
 	bool "Marvell Orion-VoIP GE Reference Design"
 	help
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 9dff2d3..a2c9ebc 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_MACH_WRT350N_V2)	+= wrt350n-v2-setup.o
 obj-$(CONFIG_MACH_TS78XX)	+= ts78xx-setup.o
 obj-$(CONFIG_MACH_MV2120)	+= mv2120-setup.o
 obj-$(CONFIG_MACH_NET2BIG)	+= net2big-setup.o
-obj-$(CONFIG_MACH_WNR854T)	+= wnr854t-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_GE)	+= rd88f5181l-ge-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_FXO)	+= rd88f5181l-fxo-setup.o
 obj-$(CONFIG_MACH_RD88F6183AP_GE)	+= rd88f6183ap-ge-setup.o
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
deleted file mode 100644
index 4e1e5c8..0000000
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * arch/arm/mach-orion5x/wnr854t-setup.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <net/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "orion5x.h"
-#include "common.h"
-#include "mpp.h"
-
-static unsigned int wnr854t_mpp_modes[] __initdata = {
-	MPP0_GPIO,		/* Power LED green (0=on) */
-	MPP1_GPIO,		/* Reset Button (0=off) */
-	MPP2_GPIO,		/* Power LED blink (0=off) */
-	MPP3_GPIO,		/* WAN Status LED amber (0=off) */
-	MPP4_GPIO,		/* PCI int */
-	MPP5_GPIO,		/* ??? */
-	MPP6_GPIO,		/* ??? */
-	MPP7_GPIO,		/* ??? */
-	MPP8_UNUSED,		/* ??? */
-	MPP9_GIGE,		/* GE_RXERR */
-	MPP10_UNUSED,		/* ??? */
-	MPP11_UNUSED,		/* ??? */
-	MPP12_GIGE,		/* GE_TXD[4] */
-	MPP13_GIGE,		/* GE_TXD[5] */
-	MPP14_GIGE,		/* GE_TXD[6] */
-	MPP15_GIGE,		/* GE_TXD[7] */
-	MPP16_GIGE,		/* GE_RXD[4] */
-	MPP17_GIGE,		/* GE_RXD[5] */
-	MPP18_GIGE,		/* GE_RXD[6] */
-	MPP19_GIGE,		/* GE_RXD[7] */
-	0,
-};
-
-/*
- * 8M NOR flash Device bus boot chip select
- */
-#define WNR854T_NOR_BOOT_BASE	0xf4000000
-#define WNR854T_NOR_BOOT_SIZE	SZ_8M
-
-static struct mtd_partition wnr854t_nor_flash_partitions[] = {
-	{
-		.name		= "kernel",
-		.offset		= 0x00000000,
-		.size		= 0x00100000,
-	}, {
-		.name		= "rootfs",
-		.offset		= 0x00100000,
-		.size		= 0x00660000,
-	}, {
-		.name		= "uboot",
-		.offset		= 0x00760000,
-		.size		= 0x00040000,
-	},
-};
-
-static struct physmap_flash_data wnr854t_nor_flash_data = {
-	.width		= 2,
-	.parts		= wnr854t_nor_flash_partitions,
-	.nr_parts	= ARRAY_SIZE(wnr854t_nor_flash_partitions),
-};
-
-static struct resource wnr854t_nor_flash_resource = {
-	.flags		= IORESOURCE_MEM,
-	.start		= WNR854T_NOR_BOOT_BASE,
-	.end		= WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device wnr854t_nor_flash = {
-	.name			= "physmap-flash",
-	.id			= 0,
-	.dev		= {
-		.platform_data	= &wnr854t_nor_flash_data,
-	},
-	.num_resources		= 1,
-	.resource		= &wnr854t_nor_flash_resource,
-};
-
-static struct mv643xx_eth_platform_data wnr854t_eth_data = {
-	.phy_addr	= MV643XX_ETH_PHY_NONE,
-	.speed		= SPEED_1000,
-	.duplex		= DUPLEX_FULL,
-};
-
-static struct dsa_chip_data wnr854t_switch_chip_data = {
-	.port_names[0] = "lan3",
-	.port_names[1] = "lan4",
-	.port_names[2] = "wan",
-	.port_names[3] = "cpu",
-	.port_names[5] = "lan1",
-	.port_names[7] = "lan2",
-};
-
-static struct dsa_platform_data wnr854t_switch_plat_data = {
-	.nr_chips	= 1,
-	.chip		= &wnr854t_switch_chip_data,
-};
-
-static void __init wnr854t_init(void)
-{
-	/*
-	 * Setup basic Orion functions. Need to be called early.
-	 */
-	orion5x_init();
-
-	orion5x_mpp_conf(wnr854t_mpp_modes);
-
-	/*
-	 * Configure peripherals.
-	 */
-	orion5x_eth_init(&wnr854t_eth_data);
-	orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
-	orion5x_uart0_init();
-
-	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
-				    ORION_MBUS_DEVBUS_BOOT_ATTR,
-				    WNR854T_NOR_BOOT_BASE,
-				    WNR854T_NOR_BOOT_SIZE);
-	platform_device_register(&wnr854t_nor_flash);
-}
-
-static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
-	u8 pin)
-{
-	int irq;
-
-	/*
-	 * Check for devices with hard-wired IRQs.
-	 */
-	irq = orion5x_pci_map_irq(dev, slot, pin);
-	if (irq != -1)
-		return irq;
-
-	/*
-	 * Mini-PCI slot.
-	 */
-	if (slot == 7)
-		return gpio_to_irq(4);
-
-	return -1;
-}
-
-static struct hw_pci wnr854t_pci __initdata = {
-	.nr_controllers	= 2,
-	.setup		= orion5x_pci_sys_setup,
-	.scan		= orion5x_pci_sys_scan_bus,
-	.map_irq	= wnr854t_pci_map_irq,
-};
-
-static int __init wnr854t_pci_init(void)
-{
-	if (machine_is_wnr854t())
-		pci_common_init(&wnr854t_pci);
-
-	return 0;
-}
-subsys_initcall(wnr854t_pci_init);
-
-MACHINE_START(WNR854T, "Netgear WNR854T")
-	/* Maintainer: Imre Kaloz <kaloz-p3rKhJxN3npAfugRpC6u6w@public.gmane.org> */
-	.atag_offset	= 0x100,
-	.nr_irqs	= ORION5X_NR_IRQS,
-	.init_machine	= wnr854t_init,
-	.map_io		= orion5x_map_io,
-	.init_early	= orion5x_init_early,
-	.init_irq	= orion5x_init_irq,
-	.init_time	= orion5x_timer_init,
-	.fixup		= tag_fixup_mem32,
-	.restart	= orion5x_restart,
-MACHINE_END
-- 
2.8.1

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[PATCH 7/8] arm: orion5x: Remove old non-DT-based WNR854T support

[Jamie Lentin]

The non-DT-based support is now redundant, remove it and replace it
with the DT-support in defconfigs.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
 arch/arm/configs/multi_v5_defconfig   |   2 +-
 arch/arm/configs/mvebu_v5_defconfig   |   2 +-
 arch/arm/configs/orion5x_defconfig    |   2 +-
 arch/arm/mach-orion5x/Kconfig         |   6 --
 arch/arm/mach-orion5x/Makefile        |   1 -
 arch/arm/mach-orion5x/wnr854t-setup.c | 185 ----------------------------------
 6 files changed, 3 insertions(+), 195 deletions(-)
 delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c

diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
index 2658b80..8b417b1 100644
--- a/arch/arm/configs/multi_v5_defconfig
+++ b/arch/arm/configs/multi_v5_defconfig
@@ -44,7 +44,7 @@ CONFIG_MACH_MV2120=y
 CONFIG_MACH_D2NET_DT=y
 CONFIG_MACH_NET2BIG=y
 CONFIG_MACH_MSS2_DT=y
-CONFIG_MACH_WNR854T=y
+CONFIG_MACH_WNR854T_DT=y
 CONFIG_MACH_RD88F5181L_GE=y
 CONFIG_MACH_RD88F5181L_FXO=y
 CONFIG_MACH_RD88F6183AP_GE=y
diff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig
index 6051c51..81dabae 100644
--- a/arch/arm/configs/mvebu_v5_defconfig
+++ b/arch/arm/configs/mvebu_v5_defconfig
@@ -31,7 +31,7 @@ CONFIG_MACH_MV2120=y
 CONFIG_MACH_D2NET_DT=y
 CONFIG_MACH_NET2BIG=y
 CONFIG_MACH_MSS2_DT=y
-CONFIG_MACH_WNR854T=y
+CONFIG_MACH_WNR854T_DT=y
 CONFIG_MACH_RD88F5181L_GE=y
 CONFIG_MACH_RD88F5181L_FXO=y
 CONFIG_MACH_RD88F6183AP_GE=y
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index 27a70a7..93b63aa 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -37,7 +37,7 @@ CONFIG_MACH_D2NET=y
 CONFIG_MACH_BIGDISK=y
 CONFIG_MACH_NET2BIG=y
 CONFIG_MACH_MSS2=y
-CONFIG_MACH_WNR854T=y
+CONFIG_MACH_WNR854T_DT=y
 CONFIG_MACH_RD88F5181L_GE=y
 CONFIG_MACH_RD88F5181L_FXO=y
 CONFIG_MACH_RD88F6183AP_GE=y
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 9acb37b..7dff2a5 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -157,12 +157,6 @@ config MACH_WNR854T_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Netgear WNR854T platform.
 
-config MACH_WNR854T
-	bool "Netgear WNR854T"
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Netgear WNR854T platform.
-
 config MACH_RD88F5181L_GE
 	bool "Marvell Orion-VoIP GE Reference Design"
 	help
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 9dff2d3..a2c9ebc 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_MACH_WRT350N_V2)	+= wrt350n-v2-setup.o
 obj-$(CONFIG_MACH_TS78XX)	+= ts78xx-setup.o
 obj-$(CONFIG_MACH_MV2120)	+= mv2120-setup.o
 obj-$(CONFIG_MACH_NET2BIG)	+= net2big-setup.o
-obj-$(CONFIG_MACH_WNR854T)	+= wnr854t-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_GE)	+= rd88f5181l-ge-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_FXO)	+= rd88f5181l-fxo-setup.o
 obj-$(CONFIG_MACH_RD88F6183AP_GE)	+= rd88f6183ap-ge-setup.o
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
deleted file mode 100644
index 4e1e5c8..0000000
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * arch/arm/mach-orion5x/wnr854t-setup.c
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <net/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include "orion5x.h"
-#include "common.h"
-#include "mpp.h"
-
-static unsigned int wnr854t_mpp_modes[] __initdata = {
-	MPP0_GPIO,		/* Power LED green (0=on) */
-	MPP1_GPIO,		/* Reset Button (0=off) */
-	MPP2_GPIO,		/* Power LED blink (0=off) */
-	MPP3_GPIO,		/* WAN Status LED amber (0=off) */
-	MPP4_GPIO,		/* PCI int */
-	MPP5_GPIO,		/* ??? */
-	MPP6_GPIO,		/* ??? */
-	MPP7_GPIO,		/* ??? */
-	MPP8_UNUSED,		/* ??? */
-	MPP9_GIGE,		/* GE_RXERR */
-	MPP10_UNUSED,		/* ??? */
-	MPP11_UNUSED,		/* ??? */
-	MPP12_GIGE,		/* GE_TXD[4] */
-	MPP13_GIGE,		/* GE_TXD[5] */
-	MPP14_GIGE,		/* GE_TXD[6] */
-	MPP15_GIGE,		/* GE_TXD[7] */
-	MPP16_GIGE,		/* GE_RXD[4] */
-	MPP17_GIGE,		/* GE_RXD[5] */
-	MPP18_GIGE,		/* GE_RXD[6] */
-	MPP19_GIGE,		/* GE_RXD[7] */
-	0,
-};
-
-/*
- * 8M NOR flash Device bus boot chip select
- */
-#define WNR854T_NOR_BOOT_BASE	0xf4000000
-#define WNR854T_NOR_BOOT_SIZE	SZ_8M
-
-static struct mtd_partition wnr854t_nor_flash_partitions[] = {
-	{
-		.name		= "kernel",
-		.offset		= 0x00000000,
-		.size		= 0x00100000,
-	}, {
-		.name		= "rootfs",
-		.offset		= 0x00100000,
-		.size		= 0x00660000,
-	}, {
-		.name		= "uboot",
-		.offset		= 0x00760000,
-		.size		= 0x00040000,
-	},
-};
-
-static struct physmap_flash_data wnr854t_nor_flash_data = {
-	.width		= 2,
-	.parts		= wnr854t_nor_flash_partitions,
-	.nr_parts	= ARRAY_SIZE(wnr854t_nor_flash_partitions),
-};
-
-static struct resource wnr854t_nor_flash_resource = {
-	.flags		= IORESOURCE_MEM,
-	.start		= WNR854T_NOR_BOOT_BASE,
-	.end		= WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device wnr854t_nor_flash = {
-	.name			= "physmap-flash",
-	.id			= 0,
-	.dev		= {
-		.platform_data	= &wnr854t_nor_flash_data,
-	},
-	.num_resources		= 1,
-	.resource		= &wnr854t_nor_flash_resource,
-};
-
-static struct mv643xx_eth_platform_data wnr854t_eth_data = {
-	.phy_addr	= MV643XX_ETH_PHY_NONE,
-	.speed		= SPEED_1000,
-	.duplex		= DUPLEX_FULL,
-};
-
-static struct dsa_chip_data wnr854t_switch_chip_data = {
-	.port_names[0] = "lan3",
-	.port_names[1] = "lan4",
-	.port_names[2] = "wan",
-	.port_names[3] = "cpu",
-	.port_names[5] = "lan1",
-	.port_names[7] = "lan2",
-};
-
-static struct dsa_platform_data wnr854t_switch_plat_data = {
-	.nr_chips	= 1,
-	.chip		= &wnr854t_switch_chip_data,
-};
-
-static void __init wnr854t_init(void)
-{
-	/*
-	 * Setup basic Orion functions. Need to be called early.
-	 */
-	orion5x_init();
-
-	orion5x_mpp_conf(wnr854t_mpp_modes);
-
-	/*
-	 * Configure peripherals.
-	 */
-	orion5x_eth_init(&wnr854t_eth_data);
-	orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
-	orion5x_uart0_init();
-
-	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
-				    ORION_MBUS_DEVBUS_BOOT_ATTR,
-				    WNR854T_NOR_BOOT_BASE,
-				    WNR854T_NOR_BOOT_SIZE);
-	platform_device_register(&wnr854t_nor_flash);
-}
-
-static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
-	u8 pin)
-{
-	int irq;
-
-	/*
-	 * Check for devices with hard-wired IRQs.
-	 */
-	irq = orion5x_pci_map_irq(dev, slot, pin);
-	if (irq != -1)
-		return irq;
-
-	/*
-	 * Mini-PCI slot.
-	 */
-	if (slot == 7)
-		return gpio_to_irq(4);
-
-	return -1;
-}
-
-static struct hw_pci wnr854t_pci __initdata = {
-	.nr_controllers	= 2,
-	.setup		= orion5x_pci_sys_setup,
-	.scan		= orion5x_pci_sys_scan_bus,
-	.map_irq	= wnr854t_pci_map_irq,
-};
-
-static int __init wnr854t_pci_init(void)
-{
-	if (machine_is_wnr854t())
-		pci_common_init(&wnr854t_pci);
-
-	return 0;
-}
-subsys_initcall(wnr854t_pci_init);
-
-MACHINE_START(WNR854T, "Netgear WNR854T")
-	/* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
-	.atag_offset	= 0x100,
-	.nr_irqs	= ORION5X_NR_IRQS,
-	.init_machine	= wnr854t_init,
-	.map_io		= orion5x_map_io,
-	.init_early	= orion5x_init_early,
-	.init_irq	= orion5x_init_irq,
-	.init_time	= orion5x_timer_init,
-	.fixup		= tag_fixup_mem32,
-	.restart	= orion5x_restart,
-MACHINE_END
-- 
2.8.1

Re: [PATCH 7/8] arm: orion5x: Remove old non-DT-based WNR854T support

[Andrew Lunn]

On Fri, Aug 26, 2016 at 10:21:03AM +0100, Jamie Lentin wrote:
> The non-DT-based support is now redundant, remove it and replace it
> with the DT-support in defconfigs.
> 
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>

Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>

    Andrew
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[PATCH 7/8] arm: orion5x: Remove old non-DT-based WNR854T support

[Andrew Lunn]

On Fri, Aug 26, 2016 at 10:21:03AM +0100, Jamie Lentin wrote:
> The non-DT-based support is now redundant, remove it and replace it
> with the DT-support in defconfigs.
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

[PATCH 8/8] arm: orion5x: Configure WNR854T ethernet PHY LEDs

[Jamie Lentin]

The default PHY configuration disables most of the LEDs. The following
configures the ethernet activity LEDs as Netgear intended.

Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
---
Andrew, note that the slave mdio bus is called "mdio", however there is
an example in bindings/net/dsa/dsa.txt using "mdio-bus". Is this a
mismatch to fix?

That said there's no formal definition of either node, and there's at
least one DT (vf610-zii-dev-rev-b.dts) that uses "mdio" already merged.
---
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 51 +++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
index 402a364..2a35a04 100644
--- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -136,31 +136,82 @@
 			port@0 {
 				reg = <0>;
 				label = "lan3";
+				phy-handle = <&lan3phy>;
 			};
 
 			port@1 {
 				reg = <1>;
 				label = "lan4";
+				phy-handle = <&lan4phy>;
 			};
 
 			port@2 {
 				reg = <2>;
 				label = "wan";
+				phy-handle = <&wanphy>;
 			};
 
 			port@3 {
 				reg = <3>;
 				label = "cpu";
+				ethernet = <&ethport>;
 			};
 
 			port@5 {
 				reg = <5>;
 				label = "lan1";
+				phy-handle = <&lan1phy>;
 			};
 
 			port@7 {
 				reg = <7>;
 				label = "lan2";
+				phy-handle = <&lan2phy>;
+			};
+		};
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			lan3phy: ethernet-phy@0 {
+				/* Marvell 88E1121R (port 1) */
+				compatible = "ethernet-phy-id0141.0cb0",
+					     "ethernet-phy-ieee802.3-c22";
+				reg = <0>;
+				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+			};
+
+			lan4phy: ethernet-phy@1 {
+				/* Marvell 88E1121R (port 2) */
+				compatible = "ethernet-phy-id0141.0cb0",
+					     "ethernet-phy-ieee802.3-c22";
+				reg = <1>;
+				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+			};
+
+			wanphy: ethernet-phy@2 {
+				/* Marvell 88E1121R (port 1) */
+				compatible = "ethernet-phy-id0141.0cb0",
+					     "ethernet-phy-ieee802.3-c22";
+				reg = <2>;
+				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+			};
+
+			lan1phy: ethernet-phy@5 {
+				/* Marvell 88E1112 */
+				compatible = "ethernet-phy-id0141.0cb0",
+					     "ethernet-phy-ieee802.3-c22";
+				reg = <5>;
+				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+			};
+
+			lan2phy: ethernet-phy@7 {
+				/* Marvell 88E1112 */
+				compatible = "ethernet-phy-id0141.0cb0",
+					     "ethernet-phy-ieee802.3-c22";
+				reg = <7>;
+				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
 			};
 		};
 	};
-- 
2.8.1

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[PATCH 8/8] arm: orion5x: Configure WNR854T ethernet PHY LEDs

[Jamie Lentin]

The default PHY configuration disables most of the LEDs. The following
configures the ethernet activity LEDs as Netgear intended.

Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
---
Andrew, note that the slave mdio bus is called "mdio", however there is
an example in bindings/net/dsa/dsa.txt using "mdio-bus". Is this a
mismatch to fix?

That said there's no formal definition of either node, and there's at
least one DT (vf610-zii-dev-rev-b.dts) that uses "mdio" already merged.
---
 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 51 +++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
index 402a364..2a35a04 100644
--- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -136,31 +136,82 @@
 			port at 0 {
 				reg = <0>;
 				label = "lan3";
+				phy-handle = <&lan3phy>;
 			};
 
 			port at 1 {
 				reg = <1>;
 				label = "lan4";
+				phy-handle = <&lan4phy>;
 			};
 
 			port at 2 {
 				reg = <2>;
 				label = "wan";
+				phy-handle = <&wanphy>;
 			};
 
 			port at 3 {
 				reg = <3>;
 				label = "cpu";
+				ethernet = <&ethport>;
 			};
 
 			port at 5 {
 				reg = <5>;
 				label = "lan1";
+				phy-handle = <&lan1phy>;
 			};
 
 			port at 7 {
 				reg = <7>;
 				label = "lan2";
+				phy-handle = <&lan2phy>;
+			};
+		};
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			lan3phy: ethernet-phy at 0 {
+				/* Marvell 88E1121R (port 1) */
+				compatible = "ethernet-phy-id0141.0cb0",
+					     "ethernet-phy-ieee802.3-c22";
+				reg = <0>;
+				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+			};
+
+			lan4phy: ethernet-phy at 1 {
+				/* Marvell 88E1121R (port 2) */
+				compatible = "ethernet-phy-id0141.0cb0",
+					     "ethernet-phy-ieee802.3-c22";
+				reg = <1>;
+				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+			};
+
+			wanphy: ethernet-phy at 2 {
+				/* Marvell 88E1121R (port 1) */
+				compatible = "ethernet-phy-id0141.0cb0",
+					     "ethernet-phy-ieee802.3-c22";
+				reg = <2>;
+				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+			};
+
+			lan1phy: ethernet-phy at 5 {
+				/* Marvell 88E1112 */
+				compatible = "ethernet-phy-id0141.0cb0",
+					     "ethernet-phy-ieee802.3-c22";
+				reg = <5>;
+				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
+			};
+
+			lan2phy: ethernet-phy at 7 {
+				/* Marvell 88E1112 */
+				compatible = "ethernet-phy-id0141.0cb0",
+					     "ethernet-phy-ieee802.3-c22";
+				reg = <7>;
+				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
 			};
 		};
 	};
-- 
2.8.1

Re: [PATCH 8/8] arm: orion5x: Configure WNR854T ethernet PHY LEDs

[Andrew Lunn]

On Fri, Aug 26, 2016 at 10:21:04AM +0100, Jamie Lentin wrote:
> The default PHY configuration disables most of the LEDs. The following
> configures the ethernet activity LEDs as Netgear intended.
> 
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>
> ---
> Andrew, note that the slave mdio bus is called "mdio", however there is
> an example in bindings/net/dsa/dsa.txt using "mdio-bus". Is this a
> mismatch to fix?

Hi Jamie

Yes, the documentation should match reality.

Unfortunately, there is a bit of a mess here. Different drivers have
different names for this node in device tree. And since device tree is
supposed to be stable, we cannot change them all to be the same.

I did intend to write some documentation defining what best practices
are for mdio busses, but never got around to it.

    Andrew
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[PATCH 8/8] arm: orion5x: Configure WNR854T ethernet PHY LEDs

[Andrew Lunn]

On Fri, Aug 26, 2016 at 10:21:04AM +0100, Jamie Lentin wrote:
> The default PHY configuration disables most of the LEDs. The following
> configures the ethernet activity LEDs as Netgear intended.
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
> ---
> Andrew, note that the slave mdio bus is called "mdio", however there is
> an example in bindings/net/dsa/dsa.txt using "mdio-bus". Is this a
> mismatch to fix?

Hi Jamie

Yes, the documentation should match reality.

Unfortunately, there is a bit of a mess here. Different drivers have
different names for this node in device tree. And since device tree is
supposed to be stable, we cannot change them all to be the same.

I did intend to write some documentation defining what best practices
are for mdio busses, but never got around to it.

    Andrew

Re: [PATCH 8/8] arm: orion5x: Configure WNR854T ethernet PHY LEDs

[Andrew Lunn]

On Fri, Aug 26, 2016 at 10:21:04AM +0100, Jamie Lentin wrote:
> The default PHY configuration disables most of the LEDs. The following
> configures the ethernet activity LEDs as Netgear intended.
> 
> Signed-off-by: Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org>

Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>

    Andrew
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[PATCH 8/8] arm: orion5x: Configure WNR854T ethernet PHY LEDs

[Andrew Lunn]

On Fri, Aug 26, 2016 at 10:21:04AM +0100, Jamie Lentin wrote:
> The default PHY configuration disables most of the LEDs. The following
> configures the ethernet activity LEDs as Netgear intended.
> 
> Signed-off-by: Jamie Lentin <jm@lentin.co.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH 0/8] Convert Netgear WNR854T to devicetree

[Imre Kaloz]

Hi Jamie,

On Fri, 26 Aug 2016 11:20:56 +0200, Jamie Lentin <jm@lentin.co.uk> wrote:

<snip>

> * Use Flash partition scheme from original netgear Linux image (but
> keeping the uboot/uboot_env split) instead of the partition scheme from
> the old non-DT support, which didn't match either Netgear's layout,
> u-boot or openWRT. NB: I've no copy of the original flash contents
> (Netgear's firmware images only contain a squashfs image of the rootfs),
> so I can't confirm the other partitions are accurately named.

Both the factory layout and OpenWrt's changed a few times - the later just  
to accommodate bigger kernels. Some factory firmwares did include a kernel  
update, too.

I would suggest staying with the OpenWrt layour (maybe increase again the  
size of the kernel partition):
- the bootloader loads the kernel from JFFS2
- most of the partitions in the factory firmware are empty
- the factory layout gives you almost no space to play with

But this is up to you now :)


Best,

Imre

[PATCH 0/8] Convert Netgear WNR854T to devicetree

[Imre Kaloz]

Hi Jamie,

On Fri, 26 Aug 2016 11:20:56 +0200, Jamie Lentin <jm@lentin.co.uk> wrote:

<snip>

> * Use Flash partition scheme from original netgear Linux image (but
> keeping the uboot/uboot_env split) instead of the partition scheme from
> the old non-DT support, which didn't match either Netgear's layout,
> u-boot or openWRT. NB: I've no copy of the original flash contents
> (Netgear's firmware images only contain a squashfs image of the rootfs),
> so I can't confirm the other partitions are accurately named.

Both the factory layout and OpenWrt's changed a few times - the later just  
to accommodate bigger kernels. Some factory firmwares did include a kernel  
update, too.

I would suggest staying with the OpenWrt layour (maybe increase again the  
size of the kernel partition):
- the bootloader loads the kernel from JFFS2
- most of the partitions in the factory firmware are empty
- the factory layout gives you almost no space to play with

But this is up to you now :)


Best,

Imre

Re: [PATCH 0/8] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

On Fri, 26 Aug 2016, Imre Kaloz wrote:

> Hi Jamie,
>
> On Fri, 26 Aug 2016 11:20:56 +0200, Jamie Lentin <jm@lentin.co.uk> wrote:
>
> <snip>
>
>> * Use Flash partition scheme from original netgear Linux image (but
>> keeping the uboot/uboot_env split) instead of the partition scheme from
>> the old non-DT support, which didn't match either Netgear's layout,
>> u-boot or openWRT. NB: I've no copy of the original flash contents
>> (Netgear's firmware images only contain a squashfs image of the rootfs),
>> so I can't confirm the other partitions are accurately named.
>
> Both the factory layout and OpenWrt's changed a few times - the later just to 
> accommodate bigger kernels. Some factory firmwares did include a kernel 
> update, too.

The Netgear firwmare images (as far as I've seen) all contain a uImage, as 
the uImage lives in the same JFFS2 partition as the rootfs, which the 
firmware image is a dump of.

> I would suggest staying with the OpenWrt layour (maybe increase again the 
> size of the kernel partition):
> - the bootloader loads the kernel from JFFS2
> - most of the partitions in the factory firmware are empty

Phew, I'm not missing out on much then :)

> - the factory layout gives you almost no space to play with
>
> But this is up to you now :)

When making a patchset for the D-Link DNS-325 I remember being told that 
the kernel's default partition scheme should match the vendor's (even if 
it is fairly nonsensical). It's easy enough to override if you've replaced 
the default firmware, and I'll invariably be overriding it so the mainline 
kernel definition won't make much difference to me either way.

Of course, one could also argue I'm breaking backwards compatibility at 
this point by changing it, so maybe I should put it back.

> Best,
>
> Imre

-- 
Jamie Lentin

[PATCH 0/8] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

On Fri, 26 Aug 2016, Imre Kaloz wrote:

> Hi Jamie,
>
> On Fri, 26 Aug 2016 11:20:56 +0200, Jamie Lentin <jm@lentin.co.uk> wrote:
>
> <snip>
>
>> * Use Flash partition scheme from original netgear Linux image (but
>> keeping the uboot/uboot_env split) instead of the partition scheme from
>> the old non-DT support, which didn't match either Netgear's layout,
>> u-boot or openWRT. NB: I've no copy of the original flash contents
>> (Netgear's firmware images only contain a squashfs image of the rootfs),
>> so I can't confirm the other partitions are accurately named.
>
> Both the factory layout and OpenWrt's changed a few times - the later just to 
> accommodate bigger kernels. Some factory firmwares did include a kernel 
> update, too.

The Netgear firwmare images (as far as I've seen) all contain a uImage, as 
the uImage lives in the same JFFS2 partition as the rootfs, which the 
firmware image is a dump of.

> I would suggest staying with the OpenWrt layour (maybe increase again the 
> size of the kernel partition):
> - the bootloader loads the kernel from JFFS2
> - most of the partitions in the factory firmware are empty

Phew, I'm not missing out on much then :)

> - the factory layout gives you almost no space to play with
>
> But this is up to you now :)

When making a patchset for the D-Link DNS-325 I remember being told that 
the kernel's default partition scheme should match the vendor's (even if 
it is fairly nonsensical). It's easy enough to override if you've replaced 
the default firmware, and I'll invariably be overriding it so the mainline 
kernel definition won't make much difference to me either way.

Of course, one could also argue I'm breaking backwards compatibility at 
this point by changing it, so maybe I should put it back.

> Best,
>
> Imre

-- 
Jamie Lentin

Re: [PATCH 0/8] Convert Netgear WNR854T to devicetree

[Andrew Lunn]

> >- the factory layout gives you almost no space to play with

Given that the kernel has grown in size over the years, does the
mainline kernel fit in the factory layout?

> Of course, one could also argue I'm breaking backwards compatibility
> at this point by changing it, so maybe I should put it back.

I don't mind breaking backwards compatibility, if the factory defaults
no longer actually work.....

Also, lets think about the users here. This is a very old box. Anybody
playing with one are probably of the sort who tinker with a classic
car in the garage, taking the engine apart and putting it back
together again. I doubt there are users of this box who take their car
in for a service once they are out of windscreen washing water.

    Andrew
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[PATCH 0/8] Convert Netgear WNR854T to devicetree

[Andrew Lunn]

> >- the factory layout gives you almost no space to play with

Given that the kernel has grown in size over the years, does the
mainline kernel fit in the factory layout?

> Of course, one could also argue I'm breaking backwards compatibility
> at this point by changing it, so maybe I should put it back.

I don't mind breaking backwards compatibility, if the factory defaults
no longer actually work.....

Also, lets think about the users here. This is a very old box. Anybody
playing with one are probably of the sort who tinker with a classic
car in the garage, taking the engine apart and putting it back
together again. I doubt there are users of this box who take their car
in for a service once they are out of windscreen washing water.

    Andrew

Re: [PATCH 0/8] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

On Fri, 26 Aug 2016, Andrew Lunn wrote:

>>> - the factory layout gives you almost no space to play with
>
> Given that the kernel has grown in size over the years, does the
> mainline kernel fit in the factory layout?

The factory layout has a 6MB JFFS2 for root & uImage (uboot mounts it 
by default) + 1MB miscellany. So the main restriction on kernel size is 
the size of your userland.

The non-DT mainline layout is 1MB JFFS2 for uImage + 7MB rootfs. Which is 
a closer approximation to other devices with a uImage in it's own 
partition.

>> Of course, one could also argue I'm breaking backwards compatibility
>> at this point by changing it, so maybe I should put it back.
>
> I don't mind breaking backwards compatibility, if the factory defaults
> no longer actually work.....
>
> Also, lets think about the users here. This is a very old box. Anybody
> playing with one are probably of the sort who tinker with a classic
> car in the garage, taking the engine apart and putting it back
> together again. I doubt there are users of this box who take their car
> in for a service once they are out of windscreen washing water.

My line of thinking was that the only people that will see this default 
partition scheme are people that have just compiled a mainline kernel and 
booted it to see what happens. At which point you probably still have the 
Netgear image in Flash. If you had OpenWRT in Flash then in all likelihood 
you'd already be using an OpenWRT kernel too, with it's own flash layout. 
Finally, you could have rolled your own userland and put that on Flash, 
but by then you should know enough to do what you like :)

>
>    Andrew
>

-- 
Jamie Lentin

[PATCH 0/8] Convert Netgear WNR854T to devicetree

[Jamie Lentin]

On Fri, 26 Aug 2016, Andrew Lunn wrote:

>>> - the factory layout gives you almost no space to play with
>
> Given that the kernel has grown in size over the years, does the
> mainline kernel fit in the factory layout?

The factory layout has a 6MB JFFS2 for root & uImage (uboot mounts it 
by default) + 1MB miscellany. So the main restriction on kernel size is 
the size of your userland.

The non-DT mainline layout is 1MB JFFS2 for uImage + 7MB rootfs. Which is 
a closer approximation to other devices with a uImage in it's own 
partition.

>> Of course, one could also argue I'm breaking backwards compatibility
>> at this point by changing it, so maybe I should put it back.
>
> I don't mind breaking backwards compatibility, if the factory defaults
> no longer actually work.....
>
> Also, lets think about the users here. This is a very old box. Anybody
> playing with one are probably of the sort who tinker with a classic
> car in the garage, taking the engine apart and putting it back
> together again. I doubt there are users of this box who take their car
> in for a service once they are out of windscreen washing water.

My line of thinking was that the only people that will see this default 
partition scheme are people that have just compiled a mainline kernel and 
booted it to see what happens. At which point you probably still have the 
Netgear image in Flash. If you had OpenWRT in Flash then in all likelihood 
you'd already be using an OpenWRT kernel too, with it's own flash layout. 
Finally, you could have rolled your own userland and put that on Flash, 
but by then you should know enough to do what you like :)

>
>    Andrew
>

-- 
Jamie Lentin

Re: [PATCH 0/8] Convert Netgear WNR854T to devicetree

[Imre Kaloz]

On Fri, 26 Aug 2016 18:50:33 +0200, Jamie Lentin <jm-Pj/HzkgeCk7QXOPxS62xeg@public.gmane.org> wrote:

> On Fri, 26 Aug 2016, Andrew Lunn wrote:
>
>>>> - the factory layout gives you almost no space to play with
>>
>> Given that the kernel has grown in size over the years, does the
>> mainline kernel fit in the factory layout?
>
> The factory layout has a 6MB JFFS2 for root & uImage (uboot mounts it by  
> default) + 1MB miscellany. So the main restriction on kernel size is the  
> size of your userland.
>
> The non-DT mainline layout is 1MB JFFS2 for uImage + 7MB rootfs. Which  
> is a closer approximation to other devices with a uImage in it's own  
> partition.
>
>>> Of course, one could also argue I'm breaking backwards compatibility
>>> at this point by changing it, so maybe I should put it back.
>>
>> I don't mind breaking backwards compatibility, if the factory defaults
>> no longer actually work.....
>>
>> Also, lets think about the users here. This is a very old box. Anybody
>> playing with one are probably of the sort who tinker with a classic
>> car in the garage, taking the engine apart and putting it back
>> together again. I doubt there are users of this box who take their car
>> in for a service once they are out of windscreen washing water.
>
> My line of thinking was that the only people that will see this default  
> partition scheme are people that have just compiled a mainline kernel  
> and booted it to see what happens. At which point you probably still  
> have the Netgear image in Flash. If you had OpenWRT in Flash then in all  
> likelihood you'd already be using an OpenWRT kernel too, with it's own  
> flash layout. Finally, you could have rolled your own userland and put  
> that on Flash, but by then you should know enough to do what you like :)

Well, that means you have serial console - otherwise without userland it's  
pretty unusable ;) Anyways, I would stay with a modified version of the  
non-DT partitions, with the kernel size increased to ~1.4MB (didn't check  
how much overhead is DT support).


Imre
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[PATCH 0/8] Convert Netgear WNR854T to devicetree

[Imre Kaloz]

On Fri, 26 Aug 2016 18:50:33 +0200, Jamie Lentin <jm@lentin.co.uk> wrote:

> On Fri, 26 Aug 2016, Andrew Lunn wrote:
>
>>>> - the factory layout gives you almost no space to play with
>>
>> Given that the kernel has grown in size over the years, does the
>> mainline kernel fit in the factory layout?
>
> The factory layout has a 6MB JFFS2 for root & uImage (uboot mounts it by  
> default) + 1MB miscellany. So the main restriction on kernel size is the  
> size of your userland.
>
> The non-DT mainline layout is 1MB JFFS2 for uImage + 7MB rootfs. Which  
> is a closer approximation to other devices with a uImage in it's own  
> partition.
>
>>> Of course, one could also argue I'm breaking backwards compatibility
>>> at this point by changing it, so maybe I should put it back.
>>
>> I don't mind breaking backwards compatibility, if the factory defaults
>> no longer actually work.....
>>
>> Also, lets think about the users here. This is a very old box. Anybody
>> playing with one are probably of the sort who tinker with a classic
>> car in the garage, taking the engine apart and putting it back
>> together again. I doubt there are users of this box who take their car
>> in for a service once they are out of windscreen washing water.
>
> My line of thinking was that the only people that will see this default  
> partition scheme are people that have just compiled a mainline kernel  
> and booted it to see what happens. At which point you probably still  
> have the Netgear image in Flash. If you had OpenWRT in Flash then in all  
> likelihood you'd already be using an OpenWRT kernel too, with it's own  
> flash layout. Finally, you could have rolled your own userland and put  
> that on Flash, but by then you should know enough to do what you like :)

Well, that means you have serial console - otherwise without userland it's  
pretty unusable ;) Anyways, I would stay with a modified version of the  
non-DT partitions, with the kernel size increased to ~1.4MB (didn't check  
how much overhead is DT support).


Imre