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From: Meelis Roos <mroos@linux.ee>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Borislav Petkov <bp@alien8.de>,
	Linux Kernel list <linux-kernel@vger.kernel.org>,
	x86@kernel.org, linux-edac@vger.kernel.org,
	Tom Lendacky <thomas.lendacky@amd.com>
Subject: Re: 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64
Date: Wed, 3 Jan 2018 16:01:11 +0200 (EET)	[thread overview]
Message-ID: <alpine.LRH.2.21.1801031557370.4107@math.ut.ee> (raw)
In-Reply-To: <alpine.DEB.2.20.1801031407180.1957@nanos>

> That's the entry area, which is mapped into kernel _AND_ user space. Now
> that's special because we switch CR3 while we are executing there.
> 
> And this one is:
> 
> 0xffffffff81e00000-0xffffffff82000000           2M     ro         PSE     GLB x  pmd
> 
> and the one we switch to is:
> 
> 0xffffffff81000000-0xffffffff82000000          16M     ro         PSE         x  pmd
> 
> Meelis, does the patch below fix it for you?

Yes, the MCE-s are gone with this patch on top of 4.15-rc6.

> 
> Thanks,
> 
> 	tglx
> 
> 8<-------------------
> 
> --- a/arch/x86/mm/pti.c
> +++ b/arch/x86/mm/pti.c
> @@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(vo
>  static void __init pti_clone_entry_text(void)
>  {
>  	pti_clone_pmds((unsigned long) __entry_text_start,
> -			(unsigned long) __irqentry_text_end, _PAGE_RW);
> +			(unsigned long) __irqentry_text_end,
> +		       _PAGE_RW | _PAGE_GLOBAL);
>  }
>  
>  /*
> 

-- 
Meelis Roos (mroos@linux.ee)

WARNING: multiple messages have this Message-ID (diff)
From: mroos@linux.ee
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Borislav Petkov <bp@alien8.de>,
	Linux Kernel list <linux-kernel@vger.kernel.org>,
	x86@kernel.org, linux-edac@vger.kernel.org,
	Tom Lendacky <thomas.lendacky@amd.com>
Subject: 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64
Date: Wed, 3 Jan 2018 16:01:11 +0200 (EET)	[thread overview]
Message-ID: <alpine.LRH.2.21.1801031557370.4107@math.ut.ee> (raw)

> That's the entry area, which is mapped into kernel _AND_ user space. Now
> that's special because we switch CR3 while we are executing there.
> 
> And this one is:
> 
> 0xffffffff81e00000-0xffffffff82000000           2M     ro         PSE     GLB x  pmd
> 
> and the one we switch to is:
> 
> 0xffffffff81000000-0xffffffff82000000          16M     ro         PSE         x  pmd
> 
> Meelis, does the patch below fix it for you?

Yes, the MCE-s are gone with this patch on top of 4.15-rc6.

> 
> Thanks,
> 
> 	tglx
> 
> 8<-------------------
> 
> --- a/arch/x86/mm/pti.c
> +++ b/arch/x86/mm/pti.c
> @@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(vo
>  static void __init pti_clone_entry_text(void)
>  {
>  	pti_clone_pmds((unsigned long) __entry_text_start,
> -			(unsigned long) __irqentry_text_end, _PAGE_RW);
> +			(unsigned long) __irqentry_text_end,
> +		       _PAGE_RW | _PAGE_GLOBAL);
>  }
>  
>  /*
>

  reply	other threads:[~2018-01-03 14:01 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-02 20:49 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64 Meelis Roos
2018-01-02 21:27 ` Borislav Petkov
2018-01-02 23:07   ` Thomas Gleixner
2018-01-03  9:16     ` Meelis Roos
2018-01-03 12:42       ` Borislav Petkov
2018-01-03 13:17         ` Thomas Gleixner
2018-01-03 13:17           ` Thomas Gleixner
2018-01-03 14:01           ` Meelis Roos [this message]
2018-01-03 14:01             ` mroos
2018-01-03 16:22           ` [tip:x86/pti] x86/pti: Make sure the user/kernel PTEs match tip-bot for Thomas Gleixner
2018-02-09 23:30             ` Dave Hansen
2018-02-13 15:59               ` Thomas Gleixner
2018-01-03  7:07   ` 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64 Meelis Roos

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