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From: Harry Wentland <harry.wentland@amd.com>
To: Uma Shankar <uma.shankar@intel.com>,
	intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Shashank.Sharma@amd.com, sebastian@sebastianwick.net
Subject: Re: [RFC v2 02/22] drm: Add Enhanced Gamma and color lut range attributes
Date: Wed, 3 Nov 2021 11:08:13 -0400	[thread overview]
Message-ID: <d67a9761-91b4-3432-dd55-f85bb0657b68@amd.com> (raw)
In-Reply-To: <20210906213904.27918-3-uma.shankar@intel.com>



On 2021-09-06 17:38, Uma Shankar wrote:
> Existing LUT precision structure is having only 16 bit
> precision. This is not enough for upcoming enhanced hardwares
> and advance usecases like HDR processing. Hence added a new
> structure with 32 bit precision values.
> 
> This also defines a new structure to define color lut ranges,
> along with related macro definitions and enums. This will help
> describe multi segmented lut ranges in the hardware.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  include/uapi/drm/drm_mode.h | 58 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index 90c55383f1ee..1079794c86c3 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -903,6 +903,64 @@ struct hdr_output_metadata {
>  	};
>  };
>  
> +/*
> + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means the LUT
> + * can be used for either purpose, but not simultaneously. To expose
> + * modes that support gamma and degamma simultaneously the gamma mode
> + * must declare distinct DRM_MODE_LUT_GAMMA and DRM_MODE_LUT_DEGAMMA
> + * ranges.
> + */
> +/* LUT is for gamma (after CTM) */
> +#define DRM_MODE_LUT_GAMMA BIT(0)
> +/* LUT is for degamma (before CTM) */
> +#define DRM_MODE_LUT_DEGAMMA BIT(1)
> +/* linearly interpolate between the points */
> +#define DRM_MODE_LUT_INTERPOLATE BIT(2)
> +/*
> + * the last value of the previous range is the
> + * first value of the current range.
> + */
> +#define DRM_MODE_LUT_REUSE_LAST BIT(3)
> +/* the curve must be non-decreasing */
> +#define DRM_MODE_LUT_NON_DECREASING BIT(4)
> +/* the curve is reflected across origin for negative inputs */
> +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5)
> +/* the same curve (red) is used for blue and green channels as well */
> +#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6)
> +
> +struct drm_color_lut_range {
> +	/* DRM_MODE_LUT_* */
> +	__u32 flags;
> +	/* number of points on the curve */
> +	__u16 count;
> +	/* input/output bits per component */
> +	__u8 input_bpc, output_bpc;
> +	/* input start/end values */
> +	__s32 start, end;
> +	/* output min/max values */
> +	__s32 min, max;
> +};
> +
> +enum lut_type {
> +	LUT_TYPE_DEGAMMA = 0,
> +	LUT_TYPE_GAMMA = 1,
> +};
> +
> +/*
> + * Creating 64 bit palette entries for better data
> + * precision. This will be required for HDR and
> + * similar color processing usecases.
> + */
> +struct drm_color_lut_ext {
> +	/*
> +	 * Data is U32.32 fixed point format.
> +	 */
> +	__u64 red;
> +	__u64 green;
> +	__u64 blue;
> +	__u64 reserved;
> +};

I've been drawing out examples of drm_color_lut_range defined PWLs
and understand a bit better what you and Ville are trying to accomplish
with it. It actually makes a lot of sense and would allow for a generic
way to populate different PWL definitions with a generic function.

But I still have some key questions that either are not answered in these
patch sets or that I somehow overlooked.

Can you explain how the U32.32 fixed point format relates to the input_bpc
and output_bpc in drm_color_lut_range, as we as to the pixel coming in from
the framebuffer.

E.g. if we have ARGB2101010 what happens to a 0x3ff red value (assuming alpha
is non-multiplied)?

If the drm_color_lut_range segments are defined with input_bpc of 24 bpc will
0x3ff be zero-expanded to 24-bit? Is the 24 bpc an integer? I.e. would our 3xff
be interpreted as 0x3ff << (24-10)? 

Assuming the output_bpc is 16 bpc and the programmed LUT makes this 1-to-1 would
the output value be 0x3ff << (16-10)?

On AMD HW the pipe-internal format is a custom floating point format. We could
probably express that in terms of input/output_bpc and do the translation in our
driver between that and the internal floating point format, depending on the
framebuffer format, but there is the added complication of the magnitude of the
pixel data and correlating HDR with SDR planes.

E.g. any SDR data would map from 0.0 to 1.0 floating point, while HDR content would
map from 0.0 to some value larger than 1.0. I don't (yet) have a clear picture how
to represent that with the drm_color_lut_range definition.

If some of these questions should be obvious I apologize for being a bit dense,
though it helps to make this accessible to the lowest common denominator
to ensure not only the smartest devs can work with this.

Harry

> +
>  #define DRM_MODE_PAGE_FLIP_EVENT 0x01
>  #define DRM_MODE_PAGE_FLIP_ASYNC 0x02
>  #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
> 


WARNING: multiple messages have this Message-ID (diff)
From: Harry Wentland <harry.wentland@amd.com>
To: Uma Shankar <uma.shankar@intel.com>,
	intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: "Cyr, Aric" <Aric.Cyr@amd.com>,
	ppaalanen@gmail.com, sebastian@sebastianwick.net
Subject: Re: [Intel-gfx] [RFC v2 02/22] drm: Add Enhanced Gamma and color lut range attributes
Date: Wed, 3 Nov 2021 11:08:13 -0400	[thread overview]
Message-ID: <d67a9761-91b4-3432-dd55-f85bb0657b68@amd.com> (raw)
In-Reply-To: <20210906213904.27918-3-uma.shankar@intel.com>



On 2021-09-06 17:38, Uma Shankar wrote:
> Existing LUT precision structure is having only 16 bit
> precision. This is not enough for upcoming enhanced hardwares
> and advance usecases like HDR processing. Hence added a new
> structure with 32 bit precision values.
> 
> This also defines a new structure to define color lut ranges,
> along with related macro definitions and enums. This will help
> describe multi segmented lut ranges in the hardware.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  include/uapi/drm/drm_mode.h | 58 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index 90c55383f1ee..1079794c86c3 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -903,6 +903,64 @@ struct hdr_output_metadata {
>  	};
>  };
>  
> +/*
> + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means the LUT
> + * can be used for either purpose, but not simultaneously. To expose
> + * modes that support gamma and degamma simultaneously the gamma mode
> + * must declare distinct DRM_MODE_LUT_GAMMA and DRM_MODE_LUT_DEGAMMA
> + * ranges.
> + */
> +/* LUT is for gamma (after CTM) */
> +#define DRM_MODE_LUT_GAMMA BIT(0)
> +/* LUT is for degamma (before CTM) */
> +#define DRM_MODE_LUT_DEGAMMA BIT(1)
> +/* linearly interpolate between the points */
> +#define DRM_MODE_LUT_INTERPOLATE BIT(2)
> +/*
> + * the last value of the previous range is the
> + * first value of the current range.
> + */
> +#define DRM_MODE_LUT_REUSE_LAST BIT(3)
> +/* the curve must be non-decreasing */
> +#define DRM_MODE_LUT_NON_DECREASING BIT(4)
> +/* the curve is reflected across origin for negative inputs */
> +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5)
> +/* the same curve (red) is used for blue and green channels as well */
> +#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6)
> +
> +struct drm_color_lut_range {
> +	/* DRM_MODE_LUT_* */
> +	__u32 flags;
> +	/* number of points on the curve */
> +	__u16 count;
> +	/* input/output bits per component */
> +	__u8 input_bpc, output_bpc;
> +	/* input start/end values */
> +	__s32 start, end;
> +	/* output min/max values */
> +	__s32 min, max;
> +};
> +
> +enum lut_type {
> +	LUT_TYPE_DEGAMMA = 0,
> +	LUT_TYPE_GAMMA = 1,
> +};
> +
> +/*
> + * Creating 64 bit palette entries for better data
> + * precision. This will be required for HDR and
> + * similar color processing usecases.
> + */
> +struct drm_color_lut_ext {
> +	/*
> +	 * Data is U32.32 fixed point format.
> +	 */
> +	__u64 red;
> +	__u64 green;
> +	__u64 blue;
> +	__u64 reserved;
> +};

I've been drawing out examples of drm_color_lut_range defined PWLs
and understand a bit better what you and Ville are trying to accomplish
with it. It actually makes a lot of sense and would allow for a generic
way to populate different PWL definitions with a generic function.

But I still have some key questions that either are not answered in these
patch sets or that I somehow overlooked.

Can you explain how the U32.32 fixed point format relates to the input_bpc
and output_bpc in drm_color_lut_range, as we as to the pixel coming in from
the framebuffer.

E.g. if we have ARGB2101010 what happens to a 0x3ff red value (assuming alpha
is non-multiplied)?

If the drm_color_lut_range segments are defined with input_bpc of 24 bpc will
0x3ff be zero-expanded to 24-bit? Is the 24 bpc an integer? I.e. would our 3xff
be interpreted as 0x3ff << (24-10)? 

Assuming the output_bpc is 16 bpc and the programmed LUT makes this 1-to-1 would
the output value be 0x3ff << (16-10)?

On AMD HW the pipe-internal format is a custom floating point format. We could
probably express that in terms of input/output_bpc and do the translation in our
driver between that and the internal floating point format, depending on the
framebuffer format, but there is the added complication of the magnitude of the
pixel data and correlating HDR with SDR planes.

E.g. any SDR data would map from 0.0 to 1.0 floating point, while HDR content would
map from 0.0 to some value larger than 1.0. I don't (yet) have a clear picture how
to represent that with the drm_color_lut_range definition.

If some of these questions should be obvious I apologize for being a bit dense,
though it helps to make this accessible to the lowest common denominator
to ensure not only the smartest devs can work with this.

Harry

> +
>  #define DRM_MODE_PAGE_FLIP_EVENT 0x01
>  #define DRM_MODE_PAGE_FLIP_ASYNC 0x02
>  #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
> 


  reply	other threads:[~2021-11-03 15:08 UTC|newest]

Thread overview: 154+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-06 21:38 [Intel-gfx] [RFC v2 00/22] Add Support for Plane Color Lut and CSC features Uma Shankar
2021-09-06 21:38 ` Uma Shankar
2021-09-06 21:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add Support for Plane Color Lut and CSC features (rev2) Patchwork
2021-09-06 21:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 01/22] drm: RFC for Plane Color Hardware Pipeline Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-10-12 10:30   ` Pekka Paalanen
2021-10-12 10:30     ` [Intel-gfx] " Pekka Paalanen
2021-10-12 10:35     ` Simon Ser
2021-10-12 10:35       ` [Intel-gfx] " Simon Ser
2021-10-12 12:00       ` Pekka Paalanen
2021-10-12 12:00         ` [Intel-gfx] " Pekka Paalanen
2021-10-12 19:11         ` Shankar, Uma
2021-10-12 19:11           ` [Intel-gfx] " Shankar, Uma
2021-10-13  7:25           ` Pekka Paalanen
2021-10-13  7:25             ` [Intel-gfx] " Pekka Paalanen
2021-10-14 19:46             ` Shankar, Uma
2021-10-14 19:46               ` [Intel-gfx] " Shankar, Uma
2021-10-12 20:58     ` Shankar, Uma
2021-10-12 20:58       ` [Intel-gfx] " Shankar, Uma
2021-10-13  8:30       ` Pekka Paalanen
2021-10-13  8:30         ` [Intel-gfx] " Pekka Paalanen
2021-10-14 19:44         ` Shankar, Uma
2021-10-14 19:44           ` [Intel-gfx] " Shankar, Uma
2021-10-15  7:42           ` Pekka Paalanen
2021-10-15  7:42             ` [Intel-gfx] " Pekka Paalanen
2021-10-26 15:11             ` Harry Wentland
2021-10-26 15:11               ` [Intel-gfx] " Harry Wentland
2021-10-26 15:36           ` Harry Wentland
2021-10-26 15:36             ` [Intel-gfx] " Harry Wentland
2021-10-27  8:00             ` Pekka Paalanen
2021-10-27  8:00               ` [Intel-gfx] " Pekka Paalanen
2021-10-27 12:48               ` Harry Wentland
2021-10-27 12:48                 ` Harry Wentland
2021-10-26 15:40       ` Harry Wentland
2021-10-26 15:40         ` [Intel-gfx] " Harry Wentland
2021-11-23 15:05   ` Harry Wentland
2021-11-23 15:05     ` [Intel-gfx] " Harry Wentland
2021-11-25 20:43     ` Shankar, Uma
2021-11-25 20:43       ` [Intel-gfx] " Shankar, Uma
2021-11-26  8:21       ` Pekka Paalanen
2021-11-26  8:21         ` [Intel-gfx] " Pekka Paalanen
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 02/22] drm: Add Enhanced Gamma and color lut range attributes Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-11-03 15:08   ` Harry Wentland [this message]
2021-11-03 15:08     ` [Intel-gfx] " Harry Wentland
2021-11-04  8:38     ` Pekka Paalanen
2021-11-04  8:38       ` [Intel-gfx] " Pekka Paalanen
2021-11-04 16:27       ` Harry Wentland
2021-11-04 16:27         ` [Intel-gfx] " Harry Wentland
2021-11-05 11:49         ` Ville Syrjälä
2021-11-05 11:49           ` [Intel-gfx] " Ville Syrjälä
2021-11-09 20:22           ` Harry Wentland
2021-11-09 20:22             ` [Intel-gfx] " Harry Wentland
2021-11-08  9:54         ` Pekka Paalanen
2021-11-08  9:54           ` [Intel-gfx] " Pekka Paalanen
2021-11-09 20:47           ` Harry Wentland
2021-11-09 20:47             ` [Intel-gfx] " Harry Wentland
2021-11-09 22:02             ` Ville Syrjälä
2021-11-09 22:02               ` [Intel-gfx] " Ville Syrjälä
2021-11-10  8:49               ` Pekka Paalanen
2021-11-10  8:49                 ` [Intel-gfx] " Pekka Paalanen
2021-11-10 11:55                 ` Ville Syrjälä
2021-11-10 11:55                   ` [Intel-gfx] " Ville Syrjälä
2021-11-10 15:17                   ` Harry Wentland
2021-11-10 15:17                     ` [Intel-gfx] " Harry Wentland
2021-11-11  8:22                     ` Pekka Paalanen
2021-11-11  8:22                       ` [Intel-gfx] " Pekka Paalanen
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 03/22] drm: Add Plane Degamma Mode property Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-10-12 11:50   ` Pekka Paalanen
2021-10-12 11:50     ` [Intel-gfx] " Pekka Paalanen
2021-10-12 21:02     ` Shankar, Uma
2021-10-12 21:02       ` [Intel-gfx] " Shankar, Uma
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 04/22] drm: Add Plane Degamma Lut property Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 05/22] drm/i915/xelpd: Define Degamma Lut range struct for HDR planes Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-11-03 15:10   ` Harry Wentland
2021-11-03 15:10     ` [Intel-gfx] " Harry Wentland
2021-11-05 12:59     ` Ville Syrjälä
2021-11-05 12:59       ` [Intel-gfx] " Ville Syrjälä
2021-11-09 20:19       ` Harry Wentland
2021-11-09 20:19         ` [Intel-gfx] " Harry Wentland
2021-11-09 21:45         ` Ville Syrjälä
2021-11-09 21:45           ` [Intel-gfx] " Ville Syrjälä
2021-11-09 21:56           ` Harry Wentland
2021-11-09 21:56             ` [Intel-gfx] " Harry Wentland
2021-11-11 15:17   ` Harry Wentland
2021-11-11 15:17     ` [Intel-gfx] " Harry Wentland
2021-11-11 16:42     ` Ville Syrjälä
2021-11-11 16:42       ` [Intel-gfx] " Ville Syrjälä
2021-11-11 20:42       ` Shankar, Uma
2021-11-11 20:42         ` [Intel-gfx] " Shankar, Uma
2021-11-11 21:10         ` Harry Wentland
2021-11-11 21:10           ` [Intel-gfx] " Harry Wentland
2021-11-11 21:58           ` Shankar, Uma
2021-11-11 21:58             ` [Intel-gfx] " Shankar, Uma
2021-11-12  8:37             ` Pekka Paalanen
2021-11-12  8:37               ` [Intel-gfx] " Pekka Paalanen
2021-11-23 14:40               ` Harry Wentland
2021-11-23 14:40                 ` [Intel-gfx] " Harry Wentland
2021-11-12 14:54           ` Ville Syrjälä
2021-11-12 14:54             ` [Intel-gfx] " Ville Syrjälä
2021-11-16  8:15             ` Pekka Paalanen
2021-11-16  8:15               ` [Intel-gfx] " Pekka Paalanen
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 06/22] drm/i915/xelpd: Add register definitions for Plane Degamma Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 07/22] drm/i915/xelpd: Enable plane color features Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 08/22] drm/i915/xelpd: Add color capabilities of SDR planes Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 09/22] drm/i915/xelpd: Program Plane Degamma Registers Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 10/22] drm/i915/xelpd: Add plane color check to glk_plane_color_ctl Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 11/22] drm/i915/xelpd: Initialize plane color features Uma Shankar
2021-09-06 21:38   ` Uma Shankar
2021-09-06 21:38 ` [RFC v2 12/22] drm/i915/xelpd: Load plane color luts from atomic flip Uma Shankar
2021-09-06 21:38   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:38 ` [RFC v2 13/22] drm: Add Plane CTM property Uma Shankar
2021-09-06 21:38   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:38 ` [RFC v2 14/22] drm: Add helper to attach Plane ctm property Uma Shankar
2021-09-06 21:38   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:38 ` [RFC v2 15/22] drm/i915/xelpd: Define Plane CSC Registers Uma Shankar
2021-09-06 21:38   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:38 ` [RFC v2 16/22] drm/i915/xelpd: Enable Plane CSC Uma Shankar
2021-09-06 21:38   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:38 ` [RFC v2 17/22] drm: Add Plane Gamma Mode property Uma Shankar
2021-09-06 21:38   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:39 ` [RFC v2 18/22] drm: Add Plane Gamma Lut property Uma Shankar
2021-09-06 21:39   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:39 ` [RFC v2 19/22] drm/i915/xelpd: Define and Initialize Plane Gamma Lut range Uma Shankar
2021-09-06 21:39   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:39 ` [RFC v2 20/22] drm/i915/xelpd: Add register definitions for Plane Gamma Uma Shankar
2021-09-06 21:39   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:39 ` [RFC v2 21/22] drm/i915/xelpd: Program Plane Gamma Registers Uma Shankar
2021-09-06 21:39   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:39 ` [RFC v2 22/22] drm/i915/xelpd: Enable plane gamma Uma Shankar
2021-09-06 21:39   ` [Intel-gfx] " Uma Shankar
2021-09-06 21:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Add Support for Plane Color Lut and CSC features (rev2) Patchwork
2021-09-06 23:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-12 11:55 ` [RFC v2 00/22] Add Support for Plane Color Lut and CSC features Pekka Paalanen
2021-10-12 11:55   ` [Intel-gfx] " Pekka Paalanen
2021-10-12 21:01   ` Shankar, Uma
2021-10-12 21:01     ` [Intel-gfx] " Shankar, Uma
2021-10-26 15:02     ` Harry Wentland
2021-10-26 15:02       ` [Intel-gfx] " Harry Wentland
2021-10-27  8:18       ` Pekka Paalanen
2021-10-27  8:18         ` [Intel-gfx] " Pekka Paalanen
2022-02-02 16:11 ` Harry Wentland
2022-02-02 16:11   ` [Intel-gfx] " Harry Wentland
2022-02-03 17:22   ` Shankar, Uma
2022-02-03 17:22     ` [Intel-gfx] " Shankar, Uma

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