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* [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
@ 2022-12-06  0:45 Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR Andre Przywara
                   ` (17 more replies)
  0 siblings, 18 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

Hi,

this is some early attempt at supporting the new SoC series that covers
the Allwinner D1 siblings R528 and T113s. They all share the same die,
although the D1 and D1s use RISC-V cores, which requires more plumbing,
to use the sunxi code across two architectures. Getting the R528 support
in should help a bit in sorting out what's new peripheral code and what
is architecture dependent. IIUC, Samuel has that running, although with
some hacks, the number of which this series tries to reduce.

The most interesting part of this is the pincontroller rework, this
tackles two issues:
- For the first time in the history of mainline Allwinner support the
  pincontroller changed the register layout. The code here tries to
  abstract the differences away, so both variants can share the code
  peacefully.
- For the above mentioned reason, the pincontroller code is quite old,
  and is mostly spread out across arch/arm, in a pre-DM style, even
  though we have real DM support in U-Boot proper. We need the non-DM
  version for the (ARM-only?) legacy SPL, so can't get rid of that
  completely. This series also tries to modernise that code, and moves
  it into board/sunxi/, where it can be more easily shared with RISC-V.

The preliminary MangoPi MQ-R bits on top are mostly for illustration
purposes, and in case someone wants to give it a try. For some probably
stupid reason MMC doesn't work, although the driver loads fine. Also
this omits the DRAM code, although there is some GPLed code out there,
which can be lifted into here, with some extra work.

I would mostly appreciate to have some opinion on the pinctrl patches: I
understand that patch 03/17 isn't strictly necessary, but I always
disliked U-Boot's "use C structs to model MMIO register frames"
approach, so thought now is the time to get rid of that ;-)
Also I am unsure about patch 06/17, which seems like a step back
(spreading per-SoC data over several files), but I actually aim at
getting rid of cpu_sun[x]i.h altogether, since we should not really need
it, except for some exceptions.
The third patch I would like to hear feedback about is patch 08/17.
Finally patch 14/17 would deserve some extra pair of eyes.

Please let me know if you have any opinions!

Cheers,
Andre

P.S. I understand there is some code to support those SoCs out there,
apologies if I just re-implemented some of it. Please point me to
patches that seem upstream-worthy, and I will happily integrate them in
here, potentially replacing some of my patches.

Andre Przywara (15):
  sunxi: remove CONFIG_SATAPWR
  sunxi: remove CONFIG_MACPWR
  pinctrl: sunxi: remove struct sunxi_gpio
  pinctrl: sunxi: add GPIO in/out wrappers
  pinctrl: sunxi: move pinctrl code and remove GPIO_EXTRA_HEADER
  pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h
  pinctrl: sunxi: add new D1 pinctrl support
  sunxi: introduce NCAT2 generation model
  pinctrl: sunxi: add Allwinner D1 pinctrl description
  sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup
  sunxi: clock: support D1/R528 PLL6 clock
  sunxi: add early Allwinner R528/T113 SoC support
  sunxi: refactor serial base addresses to avoid asm/arch/cpu.h
  arm: sunxi: add Allwinner T113s devicetree stub
  sunxi: add preliminary MangoPi MQ-R board support

Samuel Holland (2):
  clk: sunxi: Add support for the D1 CCU
  riscv: dts: allwinner: Add the D1/D1s SoC devicetree

 arch/arm/Kconfig                              |   3 +-
 arch/arm/cpu/armv7/sunxi/sram.c               |   1 +
 arch/arm/cpu/armv8/fel_utils.S                |   1 +
 arch/arm/dts/Makefile                         |   2 +
 arch/arm/dts/sun8i-t113s-mangopi-mq-r.dts     |  54 ++
 arch/arm/dts/sun8i-t113s.dtsi                 |  59 ++
 arch/arm/include/asm/arch-sunxi/clock.h       |   3 +-
 .../include/asm/arch-sunxi/clock_sun50i_h6.h  |   8 +
 arch/arm/include/asm/arch-sunxi/cpu.h         |   2 +
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h   |  17 -
 .../include/asm/arch-sunxi/cpu_sun50i_h6.h    |   7 -
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |   9 -
 .../include/asm/arch-sunxi/cpu_sunxi_ncat2.h  |  49 +
 arch/arm/include/asm/arch-sunxi/mmc.h         |   2 +-
 arch/arm/include/asm/arch-sunxi/prcm.h        |   2 +-
 arch/arm/include/asm/arch-sunxi/serial.h      |  32 +
 arch/arm/include/asm/arch-sunxi/timer.h       |   2 +-
 arch/arm/mach-sunxi/Kconfig                   |  51 +-
 arch/arm/mach-sunxi/Makefile                  |   2 +-
 arch/arm/mach-sunxi/board.c                   |   9 +-
 arch/arm/mach-sunxi/clock_sun50i_h6.c         |  38 +-
 arch/arm/mach-sunxi/cpu_info.c                |   2 +
 arch/arm/mach-sunxi/dram_suniv.c              |   2 +-
 arch/arm/mach-sunxi/gtbus_sun9i.c             |   1 +
 arch/arm/mach-sunxi/pinmux.c                  |  78 --
 arch/arm/mach-sunxi/spl_spi_sunxi.c           |   1 +
 arch/arm/mach-sunxi/timer.c                   |   1 +
 arch/riscv/dts/sun20i-d1.dtsi                 |  66 ++
 arch/riscv/dts/sun20i-d1s.dtsi                |  76 ++
 arch/riscv/dts/sunxi-d1-t113.dtsi             |  15 +
 arch/riscv/dts/sunxi-d1s-t113.dtsi            | 844 ++++++++++++++++++
 board/sunxi/Makefile                          |   2 +
 board/sunxi/board.c                           |  25 +-
 board/sunxi/chip.c                            |   2 +-
 board/sunxi/dram_sun8i_r528.c                 |   9 +
 board/sunxi/pinctrl.c                         |  94 ++
 common/spl/Kconfig                            |   2 +-
 configs/A10-OLinuXino-Lime_defconfig          |   1 -
 configs/A20-OLinuXino-Lime2-eMMC_defconfig    |   1 -
 configs/A20-OLinuXino-Lime2_defconfig         |   1 -
 configs/A20-OLinuXino-Lime_defconfig          |   1 -
 configs/A20-OLinuXino_MICRO-eMMC_defconfig    |   1 -
 configs/A20-OLinuXino_MICRO_defconfig         |   1 -
 configs/A20-Olimex-SOM-EVB_defconfig          |   1 -
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig  |   1 -
 configs/A20-Olimex-SOM204-EVB_defconfig       |   1 -
 configs/Bananapi_M2_Ultra_defconfig           |   1 -
 configs/Bananapi_defconfig                    |   1 -
 configs/Bananapro_defconfig                   |   1 -
 configs/Cubieboard2_defconfig                 |   1 -
 configs/Cubieboard_defconfig                  |   1 -
 configs/Cubietruck_defconfig                  |   1 -
 configs/Itead_Ibox_A20_defconfig              |   1 -
 configs/Lamobo_R1_defconfig                   |   2 -
 configs/Linksprite_pcDuino3_Nano_defconfig    |   1 -
 configs/Linksprite_pcDuino3_defconfig         |   1 -
 configs/Mele_A1000_defconfig                  |   1 -
 configs/Orangepi_defconfig                    |   1 -
 configs/Orangepi_mini_defconfig               |   1 -
 configs/Sinovoip_BPI_M3_defconfig             |   1 -
 configs/bananapi_m1_plus_defconfig            |   1 -
 configs/bananapi_m2_plus_h3_defconfig         |   1 -
 configs/bananapi_m2_plus_h5_defconfig         |   1 -
 configs/i12-tvbox_defconfig                   |   1 -
 configs/jesurun_q5_defconfig                  |   1 -
 configs/mangopi_mq_r_defconfig                |  12 +
 configs/mixtile_loftq_defconfig               |   1 -
 configs/nanopi_m1_plus_defconfig              |   1 -
 configs/nanopi_neo_plus2_defconfig            |   1 -
 configs/nanopi_r1s_h5_defconfig               |   1 -
 configs/orangepi_pc2_defconfig                |   1 -
 configs/orangepi_plus2e_defconfig             |   1 -
 configs/orangepi_plus_defconfig               |   2 -
 configs/orangepi_win_defconfig                |   1 -
 configs/pine_h64_defconfig                    |   1 -
 configs/zeropi_defconfig                      |   1 -
 drivers/ata/ahci_sunxi.c                      |   9 +
 drivers/clk/sunxi/Kconfig                     |   6 +
 drivers/clk/sunxi/Makefile                    |   1 +
 drivers/clk/sunxi/clk_d1.c                    | 101 +++
 drivers/gpio/axp_gpio.c                       |   1 +
 drivers/gpio/sunxi_gpio.c                     |  30 +-
 drivers/i2c/sun6i_p2wi.c                      |   2 +-
 drivers/i2c/sun8i_rsb.c                       |   2 +-
 drivers/mmc/sunxi_mmc.c                       |  12 +-
 drivers/net/sun8i_emac.c                      |   9 +-
 drivers/net/sunxi_emac.c                      |  10 +-
 drivers/pinctrl/sunxi/Kconfig                 |   5 +
 drivers/pinctrl/sunxi/pinctrl-sunxi.c         |  43 +-
 drivers/video/hitachi_tx18d42vm_lcd.c         |   1 +
 drivers/video/ssd2828.c                       |   1 -
 drivers/video/sunxi/sunxi_display.c           |   1 +
 drivers/video/sunxi/sunxi_lcd.c               |   1 +
 include/configs/sunxi-common.h                |   2 +-
 include/dt-bindings/clock/sun20i-d1-ccu.h     | 156 ++++
 include/dt-bindings/clock/sun20i-d1-r-ccu.h   |  19 +
 include/dt-bindings/reset/sun20i-d1-ccu.h     |  77 ++
 include/dt-bindings/reset/sun20i-d1-r-ccu.h   |  16 +
 .../arch-sunxi/gpio.h => include/sunxi_gpio.h | 102 ++-
 99 files changed, 1936 insertions(+), 296 deletions(-)
 create mode 100644 arch/arm/dts/sun8i-t113s-mangopi-mq-r.dts
 create mode 100644 arch/arm/dts/sun8i-t113s.dtsi
 create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/serial.h
 delete mode 100644 arch/arm/mach-sunxi/pinmux.c
 create mode 100644 arch/riscv/dts/sun20i-d1.dtsi
 create mode 100644 arch/riscv/dts/sun20i-d1s.dtsi
 create mode 100644 arch/riscv/dts/sunxi-d1-t113.dtsi
 create mode 100644 arch/riscv/dts/sunxi-d1s-t113.dtsi
 create mode 100644 board/sunxi/dram_sun8i_r528.c
 create mode 100644 board/sunxi/pinctrl.c
 create mode 100644 configs/mangopi_mq_r_defconfig
 create mode 100644 drivers/clk/sunxi/clk_d1.c
 create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h
 create mode 100644 include/dt-bindings/clock/sun20i-d1-r-ccu.h
 create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h
 create mode 100644 include/dt-bindings/reset/sun20i-d1-r-ccu.h
 rename arch/arm/include/asm/arch-sunxi/gpio.h => include/sunxi_gpio.h (74%)

-- 
2.35.5


^ permalink raw reply	[flat|nested] 62+ messages in thread
* [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-14  8:37   ` Samuel Holland
  2022-12-06  0:45 ` [RFC PATCH 02/17] sunxi: remove CONFIG_MACPWR Andre Przywara
                   ` (16 subsequent siblings)
  17 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that
enables the power for a SATA harddisk.
In the DT this is described with the target-supply property in the AHCI
DT node, pointing to a (GPIO controlled) regulator. Since we need SATA
only in U-Boot proper, and use a DM driver for AHCI there, we should use
the DT instead of hardcoding this.

Add code to the sunxi AHCI driver to check the DT for that regulator and
enable it, at probe time. Then drop the current code from board.c, which
was doing that job before.
This allows us to remove the SATAPWR Kconfig definition and the
respective values from the defconfigs.
We also select the generic fixed regulator driver, which handles those
GPIO controlled regulators.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/Kconfig                             |  2 ++
 arch/arm/mach-sunxi/Kconfig                  |  8 --------
 board/sunxi/board.c                          | 14 --------------
 configs/A10-OLinuXino-Lime_defconfig         |  1 -
 configs/A20-OLinuXino-Lime2-eMMC_defconfig   |  1 -
 configs/A20-OLinuXino-Lime2_defconfig        |  1 -
 configs/A20-OLinuXino-Lime_defconfig         |  1 -
 configs/A20-OLinuXino_MICRO-eMMC_defconfig   |  1 -
 configs/A20-OLinuXino_MICRO_defconfig        |  1 -
 configs/A20-Olimex-SOM-EVB_defconfig         |  1 -
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig |  1 -
 configs/A20-Olimex-SOM204-EVB_defconfig      |  1 -
 configs/Cubieboard2_defconfig                |  1 -
 configs/Cubieboard_defconfig                 |  1 -
 configs/Cubietruck_defconfig                 |  1 -
 configs/Itead_Ibox_A20_defconfig             |  1 -
 configs/Lamobo_R1_defconfig                  |  1 -
 configs/Linksprite_pcDuino3_Nano_defconfig   |  1 -
 configs/Linksprite_pcDuino3_defconfig        |  1 -
 configs/Sinovoip_BPI_M3_defconfig            |  1 -
 configs/orangepi_plus_defconfig              |  1 -
 drivers/ata/ahci_sunxi.c                     |  9 +++++++++
 22 files changed, 11 insertions(+), 40 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f95ed71b246..3623520b353 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1148,6 +1148,8 @@ config ARCH_SUNXI
 	select DM_SPI_FLASH if SPI
 	select DM_KEYBOARD
 	select DM_MMC if MMC
+	select DM_REGULATOR
+	select DM_REGULATOR_FIXED
 	select DM_SCSI if SCSI
 	select DM_SERIAL
 	select GPIO_EXTRA_HEADER
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index dbe6005daab..5f95fe72d08 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -985,14 +985,6 @@ config VIDEO_LCD_TL059WV5C0
 
 endchoice
 
-config SATAPWR
-	string "SATA power pin"
-	default ""
-	help
-	  Set the pins used to power the SATA. This takes a string in the
-	  format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
-	  port H.
-
 config GMAC_TX_DELAY
 	int "GMAC Transmit Clock Delay Chain"
 	default 0
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 21a2407e062..ec35a7f06bd 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -229,20 +229,6 @@ int board_init(void)
 		return ret;
 
 	/* strcmp() would look better, but doesn't get optimised away. */
-	if (CONFIG_SATAPWR[0]) {
-		satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
-		if (satapwr_pin >= 0) {
-			gpio_request(satapwr_pin, "satapwr");
-			gpio_direction_output(satapwr_pin, 1);
-
-			/*
-			 * Give the attached SATA device time to power-up
-			 * to avoid link timeouts
-			 */
-			mdelay(500);
-		}
-	}
-
 	if (CONFIG_MACPWR[0]) {
 		macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
 		if (macpwr_pin >= 0) {
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index ee92ac45fbc..f5d98607003 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -8,7 +8,6 @@ CONFIG_DRAM_EMR1=4
 CONFIG_SYS_CLK_FREQ=912000000
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_I2C1_ENABLE=y
-CONFIG_SATAPWR="PC3"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index 8ce10d6f75b..a8e949a3971 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
-CONFIG_SATAPWR="PC3"
 CONFIG_SPL_SPI_SUNXI=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index e38110b030b..c143cc17314 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
-CONFIG_SATAPWR="PC3"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 4e4804748ef..b6546c26d04 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -6,7 +6,6 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_I2C1_ENABLE=y
-CONFIG_SATAPWR="PC3"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
index 113d54dc0b9..95860ef8fa1 100644
--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
-CONFIG_SATAPWR="PB8"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 1e1c30ef303..32ca51554b1 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -9,7 +9,6 @@ CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
-CONFIG_SATAPWR="PB8"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index e76e6dd0932..1364c42d865 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -9,7 +9,6 @@ CONFIG_MMC3_CD_PIN="PH0"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_SATAPWR="PC3"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
index 1d3cf311952..77abe5c27ea 100644
--- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
-CONFIG_SATAPWR="PC3"
 CONFIG_GMAC_TX_DELAY=4
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig
index 97d0b9cee75..19065fb18d0 100644
--- a/configs/A20-Olimex-SOM204-EVB_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB_defconfig
@@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
-CONFIG_SATAPWR="PC3"
 CONFIG_GMAC_TX_DELAY=4
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 2c1b3d27aa0..40608498f38 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=480
 CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_SATAPWR="PB8"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index 008167509d3..9de9ee07568 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=480
 CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_SATAPWR="PB8"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index a4246343706..86588cdd5e2 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -9,7 +9,6 @@ CONFIG_USB0_VBUS_PIN="PH17"
 CONFIG_USB0_VBUS_DET="PH22"
 CONFIG_USB0_ID_DET="PH19"
 CONFIG_VIDEO_VGA=y
-CONFIG_SATAPWR="PH12"
 CONFIG_GMAC_TX_DELAY=1
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index 6474c9e90a7..b52ce776251 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=480
 CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_SATAPWR="PB8"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index c943fd3c06e..d51601ff10f 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -6,7 +6,6 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
 CONFIG_MACPWR="PH23"
 CONFIG_MMC0_CD_PIN="PH10"
-CONFIG_SATAPWR="PB3"
 CONFIG_GMAC_TX_DELAY=4
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 469dcc11f12..773f4a9e318 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -6,7 +6,6 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_ZQ=122
 CONFIG_USB1_VBUS_PIN="PH11"
-CONFIG_SATAPWR="PH2"
 CONFIG_GMAC_TX_DELAY=3
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index c4a3f2db963..5b454b23864 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_ZQ=122
-CONFIG_SATAPWR="PH2"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index ab70eff68eb..bcc8b1fba98 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -13,7 +13,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH11"
 CONFIG_USB1_VBUS_PIN="PD24"
 CONFIG_AXP_GPIO=y
-CONFIG_SATAPWR="PD25"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_CONSOLE_MUX=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 5c7f0731d90..f4ce4851d7c 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672
 CONFIG_MACPWR="PD6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB1_VBUS_PIN="PG13"
-CONFIG_SATAPWR="PG11"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_I2C=y
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index 94a3379c532..9064774e661 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -7,6 +7,7 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <linux/delay.h>
+#include <power/regulator.h>
 
 #define AHCI_PHYCS0R 0x00c0
 #define AHCI_PHYCS1R 0x00c4
@@ -74,6 +75,7 @@ static int sunxi_ahci_phy_init(u8 *reg_base)
 
 static int sunxi_sata_probe(struct udevice *dev)
 {
+	struct udevice *reg_dev;
 	ulong base;
 	u8 *reg;
 	int ret;
@@ -89,6 +91,13 @@ static int sunxi_sata_probe(struct udevice *dev)
 		debug("%s: Failed to init phy (err=%d)\n", __func__, ret);
 		return ret;
 	}
+
+	ret = device_get_supply_regulator(dev, "target-supply", &reg_dev);
+	if (ret == 0) {
+		regulator_set_enable(reg_dev, true);
+		mdelay(500);
+	}
+
 	ret = ahci_probe_scsi(dev, base);
 	if (ret) {
 		debug("%s: Failed to probe (err=%d)\n", __func__, ret);
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 02/17] sunxi: remove CONFIG_MACPWR
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-14  9:09   ` Samuel Holland
  2022-12-06  0:45 ` [RFC PATCH 03/17] pinctrl: sunxi: remove struct sunxi_gpio Andre Przywara
                   ` (15 subsequent siblings)
  17 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
the power for the Ethernet "MAC" (mostly PHY, really).
In the DT this is described with the phy-supply property in the MAC DT
node, pointing to a (GPIO controlled) regulator. Since we need Ethernet
only in U-Boot proper, and use a DM driver there, we should use the DT
instead of hardcoding this.

Add code to the sun8i_emac and sunxi_emac drivers to check the DT for
that regulator and enable it, at probe time. Then drop the current code
from board.c, which was doing that job before.
This allows us to remove the MACPWR Kconfig definition and the respective
values from the defconfigs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/mach-sunxi/Kconfig           |  7 -------
 board/sunxi/board.c                   | 10 ----------
 configs/Bananapi_M2_Ultra_defconfig   |  1 -
 configs/Bananapi_defconfig            |  1 -
 configs/Bananapro_defconfig           |  1 -
 configs/Lamobo_R1_defconfig           |  1 -
 configs/Mele_A1000_defconfig          |  1 -
 configs/Orangepi_defconfig            |  1 -
 configs/Orangepi_mini_defconfig       |  1 -
 configs/bananapi_m1_plus_defconfig    |  1 -
 configs/bananapi_m2_plus_h3_defconfig |  1 -
 configs/bananapi_m2_plus_h5_defconfig |  1 -
 configs/i12-tvbox_defconfig           |  1 -
 configs/jesurun_q5_defconfig          |  1 -
 configs/mixtile_loftq_defconfig       |  1 -
 configs/nanopi_m1_plus_defconfig      |  1 -
 configs/nanopi_neo_plus2_defconfig    |  1 -
 configs/nanopi_r1s_h5_defconfig       |  1 -
 configs/orangepi_pc2_defconfig        |  1 -
 configs/orangepi_plus2e_defconfig     |  1 -
 configs/orangepi_plus_defconfig       |  1 -
 configs/orangepi_win_defconfig        |  1 -
 configs/pine_h64_defconfig            |  1 -
 configs/zeropi_defconfig              |  1 -
 drivers/net/sun8i_emac.c              |  9 +++++++--
 drivers/net/sunxi_emac.c              | 10 ++++++++--
 26 files changed, 15 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 5f95fe72d08..6220175d612 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -645,13 +645,6 @@ config OLD_SUNXI_KERNEL_COMPAT
 	Set this to enable various workarounds for old kernels, this results in
 	sub-optimal settings for newer kernels, only enable if needed.
 
-config MACPWR
-	string "MAC power pin"
-	default ""
-	help
-	  Set the pin used to power the MAC. This takes a string in the format
-	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
 config MMC0_CD_PIN
 	string "Card detect pin for mmc0"
 	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index ec35a7f06bd..3077cc71ebd 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -228,15 +228,6 @@ int board_init(void)
 	if (ret)
 		return ret;
 
-	/* strcmp() would look better, but doesn't get optimised away. */
-	if (CONFIG_MACPWR[0]) {
-		macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
-		if (macpwr_pin >= 0) {
-			gpio_request(macpwr_pin, "macpwr");
-			gpio_direction_output(macpwr_pin, 1);
-		}
-	}
-
 #if CONFIG_IS_ENABLED(DM_I2C)
 	/*
 	 * Temporary workaround for enabling I2C clocks until proper sunxi DM
@@ -244,7 +235,6 @@ int board_init(void)
 	 */
 	i2c_init_board();
 #endif
-
 	eth_init_board();
 
 	return 0;
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index 0bd163afdd7..1c4b90ab9d2 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
 CONFIG_SPL=y
 CONFIG_MACH_SUN8I_R40=y
 CONFIG_DRAM_CLK=576
-CONFIG_MACPWR="PA17"
 CONFIG_MMC0_CD_PIN="PH13"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB1_VBUS_PIN="PH23"
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index 2814d77c187..2a590e141d9 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
-CONFIG_MACPWR="PH23"
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_GMAC_TX_DELAY=3
 CONFIG_AHCI=y
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 11375991c81..4b56195d4f2 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
-CONFIG_MACPWR="PH23"
 CONFIG_USB1_VBUS_PIN="PH0"
 CONFIG_USB2_VBUS_PIN="PH1"
 CONFIG_VIDEO_COMPOSITE=y
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index d51601ff10f..fc63a7fbd46 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
-CONFIG_MACPWR="PH23"
 CONFIG_MMC0_CD_PIN="PH10"
 CONFIG_GMAC_TX_DELAY=4
 CONFIG_AHCI=y
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index 3424b976772..a407550f6bd 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
 CONFIG_SPL=y
 CONFIG_MACH_SUN4I=y
-CONFIG_MACPWR="PH15"
 CONFIG_VIDEO_VGA=y
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_AHCI=y
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index b4d5feff309..5c14e327e39 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
-CONFIG_MACPWR="PH23"
 CONFIG_USB1_VBUS_PIN="PH26"
 CONFIG_USB2_VBUS_PIN="PH22"
 CONFIG_VIDEO_VGA=y
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 43197381114..fdacf0cd123 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
-CONFIG_MACPWR="PH23"
 CONFIG_MMC0_CD_PIN="PH10"
 CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig
index 12ea6a3236a..f398c70ce1a 100644
--- a/configs/bananapi_m1_plus_defconfig
+++ b/configs/bananapi_m1_plus_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi-m1-plus"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
-CONFIG_MACPWR="PH23"
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_GMAC_TX_DELAY=3
 CONFIG_AHCI=y
diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig
index 2bd5a70a2d0..ab138a43060 100644
--- a/configs/bananapi_m2_plus_h3_defconfig
+++ b/configs/bananapi_m2_plus_h3_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
 CONFIG_SPL=y
 CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
-CONFIG_MACPWR="PD6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig
index 926cf6f5a4d..29200e53585 100644
--- a/configs/bananapi_m2_plus_h5_defconfig
+++ b/configs/bananapi_m2_plus_h5_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-bananapi-m2-plus"
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I_H5=y
 CONFIG_DRAM_CLK=672
-CONFIG_MACPWR="PD6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index d75a7992a82..11971a8a766 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
-CONFIG_MACPWR="PH21"
 CONFIG_VIDEO_COMPOSITE=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 2e6b045b549..701d8ecfaa8 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
 CONFIG_SPL=y
 CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=312
-CONFIG_MACPWR="PH19"
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_VIDEO_COMPOSITE=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 646594b6e07..cdee80b3566 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
 CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_ZQ=251
-CONFIG_MACPWR="PA21"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB1_VBUS_PIN="PH24"
 CONFIG_USB2_VBUS_PIN=""
diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig
index 89065f0411a..a3b82de4de6 100644
--- a/configs/nanopi_m1_plus_defconfig
+++ b/configs/nanopi_m1_plus_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus"
 CONFIG_SPL=y
 CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=408
-CONFIG_MACPWR="PD6"
 CONFIG_MMC0_CD_PIN="PH13"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig
index d462b63e944..f7e3efdfe5e 100644
--- a/configs/nanopi_neo_plus2_defconfig
+++ b/configs/nanopi_neo_plus2_defconfig
@@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_ZQ=3881977
 # CONFIG_DRAM_ODT_EN is not set
-CONFIG_MACPWR="PD6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig
index 5c332ca5261..760dfe37022 100644
--- a/configs/nanopi_r1s_h5_defconfig
+++ b/configs/nanopi_r1s_h5_defconfig
@@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881977
 # CONFIG_DRAM_ODT_EN is not set
-CONFIG_MACPWR="PD6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
index 356ae7ce476..cf75cf4b351 100644
--- a/configs/orangepi_pc2_defconfig
+++ b/configs/orangepi_pc2_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN50I_H5=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881977
-CONFIG_MACPWR="PD6"
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
index e27b329b0a9..c72adfb3e69 100644
--- a/configs/orangepi_plus2e_defconfig
+++ b/configs/orangepi_plus2e_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e"
 CONFIG_SPL=y
 CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
-CONFIG_MACPWR="PD6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index f4ce4851d7c..c407af38bcc 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
 CONFIG_SPL=y
 CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
-CONFIG_MACPWR="PD6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB1_VBUS_PIN="PG13"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig
index 1e26970230f..b803dcd01ef 100644
--- a/configs/orangepi_win_defconfig
+++ b/configs/orangepi_win_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I=y
 CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
-CONFIG_MACPWR="PD14"
 CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig
index 578bd92f6a3..0b482dcea24 100644
--- a/configs/pine_h64_defconfig
+++ b/configs/pine_h64_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64"
 CONFIG_SPL=y
 CONFIG_MACH_SUN50I_H6=y
 CONFIG_SUNXI_DRAM_H6_LPDDR3=y
-CONFIG_MACPWR="PC16"
 CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB3_VBUS_PIN="PL5"
diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig
index 8365da2c472..7ace1b5cbfd 100644
--- a/configs/zeropi_defconfig
+++ b/configs/zeropi_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi"
 CONFIG_SPL=y
 CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=408
-CONFIG_MACPWR="PD6"
 # CONFIG_VIDEO_DE2 is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SYS_MONITOR_LEN=786432
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 9cca8fa4e0a..c7087b7302d 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -29,6 +29,7 @@
 #include <net.h>
 #include <reset.h>
 #include <wait_bit.h>
+#include <power/regulator.h>
 
 #define MDIO_CMD_MII_BUSY		BIT(0)
 #define MDIO_CMD_MII_WRITE		BIT(1)
@@ -169,9 +170,8 @@ struct emac_eth_dev {
 	struct clk ephy_clk;
 	struct reset_ctl tx_rst;
 	struct reset_ctl ephy_rst;
-#if CONFIG_IS_ENABLED(DM_GPIO)
 	struct gpio_desc reset_gpio;
-#endif
+	struct udevice *phy_reg;
 };
 
 
@@ -738,6 +738,9 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
 
 	sun8i_emac_set_syscon(sun8i_pdata, priv);
 
+	if (priv->phy_reg)
+		regulator_set_enable(priv->phy_reg, true);
+
 	sun8i_mdio_init(dev->name, dev);
 	priv->bus = miiphy_get_dev_by_name(dev->name);
 
@@ -844,6 +847,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
 		return -EINVAL;
 	}
 
+	device_get_supply_regulator(dev, "phy-supply", &priv->phy_reg);
+
 	pdata->phy_interface = -1;
 	priv->phyaddr = -1;
 	priv->use_internal_phy = false;
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 8625e49dae4..ee8b8a1667d 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -17,6 +17,7 @@
 #include <net.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <power/regulator.h>
 
 /* EMAC register  */
 struct emac_regs {
@@ -164,9 +165,8 @@ struct emac_eth_dev {
 	struct mii_dev *bus;
 	struct phy_device *phydev;
 	int link_printed;
-#ifdef CONFIG_DM_ETH
 	uchar rx_buf[EMAC_RX_BUFSIZE];
-#endif
+	struct udevice *phy_reg;
 };
 
 struct emac_rxhdr {
@@ -575,6 +575,9 @@ static int sunxi_emac_eth_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
+	if (priv->phy_reg)
+		regulator_set_enable(priv->phy_reg, true);
+
 	return sunxi_emac_init_phy(priv, dev);
 }
 
@@ -588,9 +591,12 @@ static const struct eth_ops sunxi_emac_eth_ops = {
 static int sunxi_emac_eth_of_to_plat(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct emac_eth_dev *priv = dev_get_priv(dev);
 
 	pdata->iobase = dev_read_addr(dev);
 
+	device_get_supply_regulator(dev, "phy-supply", &priv->phy_reg);
+
 	return 0;
 }
 
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 03/17] pinctrl: sunxi: remove struct sunxi_gpio
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 02/17] sunxi: remove CONFIG_MACPWR Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 04/17] pinctrl: sunxi: add GPIO in/out wrappers Andre Przywara
                   ` (14 subsequent siblings)
  17 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

So far every Allwinner SoC used the same basic pincontroller/GPIO
register frame, and just differed by the number of implemented banks and
pins, plus some special functionality from time to time. However the D1
and successors use a slightly different pinctrl register layout.
Use that opportunity to drop "struct sunxi_gpio", that described that
MMIO frame in a C struct. That approach is somewhat frowned upon in the
Linux world and rarely used there, though still popular with U-Boot.

Switching from a C struct to a "base address plus offset" approach allows
to switch between the two models more dynamically, without reverting to
preprocessor macros and #ifdef's.

Model the pinctrl MMIO register frame in the usual "base address +
offset" way, and replace a hard-to-parse CPP macro with a more readable
static function.
All the users get converted over. There are no functional changes at
this point, it just prepares the stages for the D1 and friends.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/include/asm/arch-sunxi/gpio.h | 63 +++++++++++---------------
 arch/arm/mach-sunxi/pinmux.c           | 51 +++++++++++----------
 drivers/gpio/sunxi_gpio.c              | 15 +++---
 drivers/pinctrl/sunxi/pinctrl-sunxi.c  | 14 +++---
 4 files changed, 68 insertions(+), 75 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 437e86479ce..8333810a69f 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -28,13 +28,6 @@
 #define SUNXI_GPIO_H	7
 #define SUNXI_GPIO_I	8
 
-/*
- * This defines the number of GPIO banks for the _main_ GPIO controller.
- * You should fix up the padding in struct sunxi_gpio_reg below if you
- * change this.
- */
-#define SUNXI_GPIO_BANKS 9
-
 /*
  * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
  * at a different register offset.
@@ -52,46 +45,42 @@
 #define SUNXI_GPIO_M	12
 #define SUNXI_GPIO_N	13
 
-struct sunxi_gpio {
-	u32 cfg[4];
-	u32 dat;
-	u32 drv[2];
-	u32 pull[2];
-};
-
-/* gpio interrupt control */
-struct sunxi_gpio_int {
-	u32 cfg[3];
-	u32 ctl;
-	u32 sta;
-	u32 deb;		/* interrupt debounce */
-};
-
-struct sunxi_gpio_reg {
-	struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
-	u8 res[0xbc];
-	struct sunxi_gpio_int gpio_int;
-};
-
 #define SUN50I_H6_GPIO_POW_MOD_SEL	0x340
 #define SUN50I_H6_GPIO_POW_MOD_VAL	0x348
 
-#define BANK_TO_GPIO(bank)	(((bank) < SUNXI_GPIO_L) ? \
-	&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
-	&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
-
 #define GPIO_BANK(pin)		((pin) >> 5)
 #define GPIO_NUM(pin)		((pin) & 0x1f)
 
+#define GPIO_CFG_REG_OFFSET	0x00
 #define GPIO_CFG_INDEX(pin)	(((pin) & 0x1f) >> 3)
 #define GPIO_CFG_OFFSET(pin)	((((pin) & 0x1f) & 0x7) << 2)
 
+#define GPIO_DAT_REG_OFFSET	0x10
+
+#define GPIO_DRV_REG_OFFSET	0x14
 #define GPIO_DRV_INDEX(pin)	(((pin) & 0x1f) >> 4)
 #define GPIO_DRV_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
 
+#define GPIO_PULL_REG_OFFSET	0x1c
 #define GPIO_PULL_INDEX(pin)	(((pin) & 0x1f) >> 4)
 #define GPIO_PULL_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
 
+#define SUNXI_PINCTRL_BANK_SIZE 0x24
+
+static inline void* BANK_TO_GPIO(int bank)
+{
+	void *pio_base;
+
+	if (bank < SUNXI_GPIO_L) {
+		pio_base = (void *)(uintptr_t)SUNXI_PIO_BASE;
+	} else {
+		pio_base = (void *)(uintptr_t)SUNXI_R_PIO_BASE;
+		bank -= SUNXI_GPIO_L;
+	}
+
+	return pio_base + bank * SUNXI_PINCTRL_BANK_SIZE;
+}
+
 /* GPIO bank sizes */
 #define SUNXI_GPIOS_PER_BANK	32
 
@@ -214,18 +203,18 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_AXP0_GPIO_COUNT	6
 
 struct sunxi_gpio_plat {
-	struct sunxi_gpio	*regs;
+	void			*regs;
 	char			bank_name[3];
 };
 
-void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
+void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val);
 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
-int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
+int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset);
 int sunxi_gpio_get_cfgpin(u32 pin);
 void sunxi_gpio_set_drv(u32 pin, u32 val);
-void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val);
+void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val);
 void sunxi_gpio_set_pull(u32 pin, u32 val);
-void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val);
+void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val);
 int sunxi_name_to_gpio(const char *name);
 
 #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
index c95fcee9f6c..b650f6b1aea 100644
--- a/arch/arm/mach-sunxi/pinmux.c
+++ b/arch/arm/mach-sunxi/pinmux.c
@@ -9,29 +9,30 @@
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
 
-void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
+void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val)
 {
-	u32 index = GPIO_CFG_INDEX(bank_offset);
-	u32 offset = GPIO_CFG_OFFSET(bank_offset);
+	u32 index = GPIO_CFG_INDEX(pin_offset);
+	u32 offset = GPIO_CFG_OFFSET(pin_offset);
 
-	clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset);
+	clrsetbits_le32(bank_base + GPIO_CFG_REG_OFFSET + index * 4,
+			0xfU << offset, val << offset);
 }
 
 void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
 {
 	u32 bank = GPIO_BANK(pin);
-	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+	void *pio = BANK_TO_GPIO(bank);
 
-	sunxi_gpio_set_cfgbank(pio, pin, val);
+	sunxi_gpio_set_cfgbank(pio, pin % 32, val);
 }
 
-int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
+int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset)
 {
-	u32 index = GPIO_CFG_INDEX(bank_offset);
-	u32 offset = GPIO_CFG_OFFSET(bank_offset);
+	u32 index = GPIO_CFG_INDEX(pin_offset);
+	u32 offset = GPIO_CFG_OFFSET(pin_offset);
 	u32 cfg;
 
-	cfg = readl(&pio->cfg[index]);
+	cfg = readl(bank_base + GPIO_CFG_REG_OFFSET + index * 4);
 	cfg >>= offset;
 
 	return cfg & 0xf;
@@ -40,39 +41,41 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
 int sunxi_gpio_get_cfgpin(u32 pin)
 {
 	u32 bank = GPIO_BANK(pin);
-	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+	void *bank_base = BANK_TO_GPIO(bank);
 
-	return sunxi_gpio_get_cfgbank(pio, pin);
+	return sunxi_gpio_get_cfgbank(bank_base, pin % 32);
 }
 
 void sunxi_gpio_set_drv(u32 pin, u32 val)
 {
 	u32 bank = GPIO_BANK(pin);
-	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+	void *bank_base = BANK_TO_GPIO(bank);
 
-	sunxi_gpio_set_drv_bank(pio, pin, val);
+	sunxi_gpio_set_drv_bank(bank_base, pin % 32, val);
 }
 
-void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val)
+void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val)
 {
-	u32 index = GPIO_DRV_INDEX(bank_offset);
-	u32 offset = GPIO_DRV_OFFSET(bank_offset);
+	u32 index = GPIO_DRV_INDEX(pin_offset);
+	u32 offset = GPIO_DRV_OFFSET(pin_offset);
 
-	clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset);
+	clrsetbits_le32(bank_base + GPIO_DRV_REG_OFFSET + index * 4,
+			0x3U << offset, val << offset);
 }
 
 void sunxi_gpio_set_pull(u32 pin, u32 val)
 {
 	u32 bank = GPIO_BANK(pin);
-	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+	void *bank_base = BANK_TO_GPIO(bank);
 
-	sunxi_gpio_set_pull_bank(pio, pin, val);
+	sunxi_gpio_set_pull_bank(bank_base, pin % 32, val);
 }
 
-void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val)
+void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val)
 {
-	u32 index = GPIO_PULL_INDEX(bank_offset);
-	u32 offset = GPIO_PULL_OFFSET(bank_offset);
+	u32 index = GPIO_PULL_INDEX(pin_offset);
+	u32 offset = GPIO_PULL_OFFSET(pin_offset);
 
-	clrsetbits_le32(&pio->pull[index], 0x3 << offset, val << offset);
+	clrsetbits_le32(bank_base + GPIO_PULL_REG_OFFSET + index * 4,
+			0x3U << offset, val << offset);
 }
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 1e85db179a6..1bf691a204a 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -24,15 +24,15 @@ static int sunxi_gpio_output(u32 pin, u32 val)
 	u32 dat;
 	u32 bank = GPIO_BANK(pin);
 	u32 num = GPIO_NUM(pin);
-	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+	void *pio = BANK_TO_GPIO(bank);
 
-	dat = readl(&pio->dat);
+	dat = readl(pio + 0x10);
 	if (val)
 		dat |= 0x1 << num;
 	else
 		dat &= ~(0x1 << num);
 
-	writel(dat, &pio->dat);
+	writel(dat, pio + 0x10);
 
 	return 0;
 }
@@ -42,9 +42,9 @@ static int sunxi_gpio_input(u32 pin)
 	u32 dat;
 	u32 bank = GPIO_BANK(pin);
 	u32 num = GPIO_NUM(pin);
-	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+	void *pio = BANK_TO_GPIO(bank);
 
-	dat = readl(&pio->dat);
+	dat = readl(pio + 0x10);
 	dat >>= num;
 
 	return dat & 0x1;
@@ -138,7 +138,7 @@ static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
 	u32 num = GPIO_NUM(offset);
 	unsigned dat;
 
-	dat = readl(&plat->regs->dat);
+	dat = readl(plat->regs + GPIO_DAT_REG_OFFSET);
 	dat >>= num;
 
 	return dat & 0x1;
@@ -181,7 +181,8 @@ static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset,
 		u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE);
 		u32 num = GPIO_NUM(offset);
 
-		clrsetbits_le32(&plat->regs->dat, 1 << num, value << num);
+		clrsetbits_le32(plat->regs + GPIO_DAT_REG_OFFSET,
+				1 << num, value << num);
 		sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
 	} else if (flags & GPIOD_IS_IN) {
 		u32 pull = 0;
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 061104be056..5ab3951ab52 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -35,7 +35,7 @@ struct sunxi_pinctrl_desc {
 };
 
 struct sunxi_pinctrl_plat {
-	struct sunxi_gpio __iomem *base;
+	void __iomem *base;
 };
 
 static int sunxi_pinctrl_get_pins_count(struct udevice *dev)
@@ -86,8 +86,8 @@ static int sunxi_pinctrl_pinmux_set(struct udevice *dev, uint pin_selector,
 	      sunxi_pinctrl_get_function_name(dev, func_selector),
 	      desc->functions[func_selector].mux);
 
-	sunxi_gpio_set_cfgbank(plat->base + bank, pin,
-			       desc->functions[func_selector].mux);
+	sunxi_gpio_set_cfgbank(plat->base + bank * SUNXI_PINCTRL_BANK_SIZE,
+			       pin, desc->functions[func_selector].mux);
 
 	return 0;
 }
@@ -102,7 +102,7 @@ static const struct pinconf_param sunxi_pinctrl_pinconf_params[] = {
 static int sunxi_pinctrl_pinconf_set_pull(struct sunxi_pinctrl_plat *plat,
 					  uint bank, uint pin, uint bias)
 {
-	struct sunxi_gpio *regs = &plat->base[bank];
+	void *regs = plat->base + bank * SUNXI_PINCTRL_BANK_SIZE;
 
 	sunxi_gpio_set_pull_bank(regs, pin, bias);
 
@@ -112,7 +112,7 @@ static int sunxi_pinctrl_pinconf_set_pull(struct sunxi_pinctrl_plat *plat,
 static int sunxi_pinctrl_pinconf_set_drive(struct sunxi_pinctrl_plat *plat,
 					   uint bank, uint pin, uint drive)
 {
-	struct sunxi_gpio *regs = &plat->base[bank];
+	void *regs = plat->base + bank * SUNXI_PINCTRL_BANK_SIZE;
 
 	if (drive < 10 || drive > 40)
 		return -EINVAL;
@@ -148,7 +148,7 @@ static int sunxi_pinctrl_get_pin_muxing(struct udevice *dev, uint pin_selector,
 	struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
 	int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
 	int pin	 = pin_selector % SUNXI_GPIOS_PER_BANK;
-	int mux  = sunxi_gpio_get_cfgbank(plat->base + bank, pin);
+	int mux  = sunxi_gpio_get_cfgbank(plat->base + bank * SUNXI_PINCTRL_BANK_SIZE, pin);
 
 	switch (mux) {
 	case SUNXI_GPIO_INPUT:
@@ -206,7 +206,7 @@ static int sunxi_pinctrl_bind(struct udevice *dev)
 		if (!gpio_plat)
 			return -ENOMEM;
 
-		gpio_plat->regs = plat->base + i;
+		gpio_plat->regs = plat->base + i * SUNXI_PINCTRL_BANK_SIZE;
 		gpio_plat->bank_name[0] = 'P';
 		gpio_plat->bank_name[1] = 'A' + desc->first_bank + i;
 		gpio_plat->bank_name[2] = '\0';
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 04/17] pinctrl: sunxi: add GPIO in/out wrappers
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (2 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 03/17] pinctrl: sunxi: remove struct sunxi_gpio Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-15  5:59   ` Samuel Holland
  2022-12-06  0:45 ` [RFC PATCH 05/17] pinctrl: sunxi: move pinctrl code and remove GPIO_EXTRA_HEADER Andre Przywara
                   ` (13 subsequent siblings)
  17 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

So far we were open-coding the pincontroller's GPIO output/input access
in each function using that.

Provide two functions that wrap that nicely, so users don't need to know
about the internals, and we can abstract the new D1 pinctrl more easily.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/include/asm/arch-sunxi/gpio.h |  2 ++
 arch/arm/mach-sunxi/pinmux.c           | 10 ++++++++++
 drivers/gpio/sunxi_gpio.c              | 26 +++++---------------------
 3 files changed, 17 insertions(+), 21 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 8333810a69f..42ca03d8c18 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -211,6 +211,8 @@ void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val);
 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
 int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset);
 int sunxi_gpio_get_cfgpin(u32 pin);
+void sunxi_gpio_set_output_bank(void *bank_base, u32 clear_mask, u32 set_mask);
+u32 sunxi_gpio_get_output_bank(void *bank_base);
 void sunxi_gpio_set_drv(u32 pin, u32 val);
 void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val);
 void sunxi_gpio_set_pull(u32 pin, u32 val);
diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
index b650f6b1aea..91acbf9269f 100644
--- a/arch/arm/mach-sunxi/pinmux.c
+++ b/arch/arm/mach-sunxi/pinmux.c
@@ -46,6 +46,16 @@ int sunxi_gpio_get_cfgpin(u32 pin)
 	return sunxi_gpio_get_cfgbank(bank_base, pin % 32);
 }
 
+void sunxi_gpio_set_output_bank(void *bank_base, u32 clear_mask, u32 set_mask)
+{
+	clrsetbits_le32(bank_base + GPIO_DAT_REG_OFFSET, clear_mask, set_mask);
+}
+
+u32 sunxi_gpio_get_output_bank(void *bank_base)
+{
+	return readl(bank_base + GPIO_DAT_REG_OFFSET);
+}
+
 void sunxi_gpio_set_drv(u32 pin, u32 val)
 {
 	u32 bank = GPIO_BANK(pin);
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 1bf691a204a..767996c10fc 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -21,33 +21,22 @@
 #if !CONFIG_IS_ENABLED(DM_GPIO)
 static int sunxi_gpio_output(u32 pin, u32 val)
 {
-	u32 dat;
 	u32 bank = GPIO_BANK(pin);
 	u32 num = GPIO_NUM(pin);
 	void *pio = BANK_TO_GPIO(bank);
 
-	dat = readl(pio + 0x10);
-	if (val)
-		dat |= 0x1 << num;
-	else
-		dat &= ~(0x1 << num);
-
-	writel(dat, pio + 0x10);
-
+	sunxi_gpio_set_output_bank(pio, val ? 0 : 1U << num,
+					val ? 1U << num : 0);
 	return 0;
 }
 
 static int sunxi_gpio_input(u32 pin)
 {
-	u32 dat;
 	u32 bank = GPIO_BANK(pin);
 	u32 num = GPIO_NUM(pin);
 	void *pio = BANK_TO_GPIO(bank);
 
-	dat = readl(pio + 0x10);
-	dat >>= num;
-
-	return dat & 0x1;
+	return (sunxi_gpio_get_output_bank(pio) >> num) & 0x1;
 }
 
 int gpio_request(unsigned gpio, const char *label)
@@ -136,12 +125,8 @@ static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
 {
 	struct sunxi_gpio_plat *plat = dev_get_plat(dev);
 	u32 num = GPIO_NUM(offset);
-	unsigned dat;
-
-	dat = readl(plat->regs + GPIO_DAT_REG_OFFSET);
-	dat >>= num;
 
-	return dat & 0x1;
+	return (sunxi_gpio_get_output_bank(plat->regs) >> num) & 0x1;
 }
 
 static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
@@ -181,8 +166,7 @@ static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset,
 		u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE);
 		u32 num = GPIO_NUM(offset);
 
-		clrsetbits_le32(plat->regs + GPIO_DAT_REG_OFFSET,
-				1 << num, value << num);
+		sunxi_gpio_set_output_bank(plat->regs, 1U << num, value << num);
 		sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
 	} else if (flags & GPIOD_IS_IN) {
 		u32 pull = 0;
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 05/17] pinctrl: sunxi: move pinctrl code and remove GPIO_EXTRA_HEADER
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (3 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 04/17] pinctrl: sunxi: add GPIO in/out wrappers Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 06/17] pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h Andre Przywara
                   ` (12 subsequent siblings)
  17 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

U-Boot's generic GPIO_EXTRA_HEADER is a convenience symbol to allow code
to more easily include platform specific GPIO headers. This should not
be needed in a DM world anymore, since the generic GPIO framework
handles that nicely.
For Allwinner boards we still need to deal with non-DM GPIO in the SPL,
but this should become the exception, not the rule.

Make this more obvious by removing the definition of GPIO_EXTRA_HEADER,
and just force every legacy user of platform specific GPIO to include
the new sunxi_gpio.h header explicitly. Everyone doing so should feel
ashamed and should find a way to avoid it from now on.
This also moves and renames the existing sunxi-specific low level
pinctrl routines from arch/arm/mach-sunxi into board/sunxi, and the
gpio.h header to the generic include/ directory, so the common code can
be shared outside of arch/arm.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/Kconfig                                             | 1 -
 arch/arm/mach-sunxi/Makefile                                 | 1 -
 arch/arm/mach-sunxi/board.c                                  | 1 +
 arch/arm/mach-sunxi/dram_suniv.c                             | 2 +-
 arch/arm/mach-sunxi/spl_spi_sunxi.c                          | 1 +
 board/sunxi/Makefile                                         | 1 +
 board/sunxi/board.c                                          | 1 +
 board/sunxi/chip.c                                           | 2 +-
 arch/arm/mach-sunxi/pinmux.c => board/sunxi/pinctrl.c        | 5 ++++-
 drivers/gpio/axp_gpio.c                                      | 1 +
 drivers/gpio/sunxi_gpio.c                                    | 1 +
 drivers/i2c/sun6i_p2wi.c                                     | 2 +-
 drivers/i2c/sun8i_rsb.c                                      | 2 +-
 drivers/mmc/sunxi_mmc.c                                      | 1 +
 drivers/pinctrl/sunxi/pinctrl-sunxi.c                        | 1 +
 drivers/video/hitachi_tx18d42vm_lcd.c                        | 1 +
 drivers/video/ssd2828.c                                      | 1 -
 drivers/video/sunxi/sunxi_display.c                          | 1 +
 drivers/video/sunxi/sunxi_lcd.c                              | 1 +
 .../include/asm/arch-sunxi/gpio.h => include/sunxi_gpio.h    | 0
 20 files changed, 19 insertions(+), 8 deletions(-)
 rename arch/arm/mach-sunxi/pinmux.c => board/sunxi/pinctrl.c (93%)
 rename arch/arm/include/asm/arch-sunxi/gpio.h => include/sunxi_gpio.h (100%)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3623520b353..c19b2c49359 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1152,7 +1152,6 @@ config ARCH_SUNXI
 	select DM_REGULATOR_FIXED
 	select DM_SCSI if SCSI
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_SEPARATE
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 58f807cb82d..671211e9322 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -10,7 +10,6 @@ obj-y	+= board.o
 obj-y	+= clock.o
 obj-y	+= cpu_info.o
 obj-y	+= dram_helpers.o
-obj-y	+= pinmux.o
 obj-$(CONFIG_SUN6I_PRCM)	+= prcm.o
 obj-$(CONFIG_AXP_PMIC_BUS)	+= pmic_bus.o
 obj-$(CONFIG_MACH_SUNIV)	+= clock_sun6i.o
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 86233637bfc..b6ffbff883c 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -17,6 +17,7 @@
 #include <i2c.h>
 #include <serial.h>
 #include <spl.h>
+#include <sunxi_gpio.h>
 #include <asm/cache.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c
index 56c2d557ff1..fcc8dad2a2f 100644
--- a/arch/arm/mach-sunxi/dram_suniv.c
+++ b/arch/arm/mach-sunxi/dram_suniv.c
@@ -13,10 +13,10 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/dram.h>
-#include <asm/arch/gpio.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
 #include <hang.h>
+#include <sunxi_gpio.h>
 
 #define SDR_T_CAS			(0x2)
 #define SDR_T_RAS			(0x8)
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 81159cfee61..c2410dd7bb1 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -13,6 +13,7 @@
 #include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/libfdt.h>
+#include <sunxi_gpio.h>
 
 #ifdef CONFIG_SPL_OS_BOOT
 #error CONFIG_SPL_OS_BOOT is not supported yet
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index d96b7897b6c..7763b032c80 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -7,6 +7,7 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 obj-y	+= board.o
+obj-y	+= pinctrl.o
 obj-$(CONFIG_SUN7I_GMAC)	+= gmac.o
 obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i_auto.o
 obj-$(CONFIG_MACH_SUN5I)	+= dram_sun5i_auto.o
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 3077cc71ebd..ef24413de4c 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -38,6 +38,7 @@
 #include <asm/armv7.h>
 #endif
 #include <asm/gpio.h>
+#include <sunxi_gpio.h>
 #include <asm/io.h>
 #include <u-boot/crc.h>
 #include <env_internal.h>
diff --git a/board/sunxi/chip.c b/board/sunxi/chip.c
index cde04bebe96..eeee6319e79 100644
--- a/board/sunxi/chip.c
+++ b/board/sunxi/chip.c
@@ -12,7 +12,7 @@
 #include <w1-eeprom.h>
 #include <dm/device-internal.h>
 
-#include <asm/arch/gpio.h>
+#include <sunxi_gpio.h>
 
 #include <extension_board.h>
 
diff --git a/arch/arm/mach-sunxi/pinmux.c b/board/sunxi/pinctrl.c
similarity index 93%
rename from arch/arm/mach-sunxi/pinmux.c
rename to board/sunxi/pinctrl.c
index 91acbf9269f..aac37f639b8 100644
--- a/arch/arm/mach-sunxi/pinmux.c
+++ b/board/sunxi/pinctrl.c
@@ -3,11 +3,14 @@
  * (C) Copyright 2007-2011
  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Low level GPIO/pin controller access functions, to be shared by non-DM
+ * SPL code and the DM pinctrl/GPIO drivers.
  */
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/gpio.h>
+#include <sunxi_gpio.h>
 
 void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val)
 {
diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c
index 35585dc8ac9..14a99ce4c9c 100644
--- a/drivers/gpio/axp_gpio.c
+++ b/drivers/gpio/axp_gpio.c
@@ -14,6 +14,7 @@
 #include <dm/lists.h>
 #include <dm/root.h>
 #include <errno.h>
+#include <sunxi_gpio.h>
 
 static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);
 
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 767996c10fc..49a6be6fd03 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -17,6 +17,7 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <sunxi_gpio.h>
 
 #if !CONFIG_IS_ENABLED(DM_GPIO)
 static int sunxi_gpio_output(u32 pin, u32 val)
diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c
index d221323295d..b8e07a533ca 100644
--- a/drivers/i2c/sun6i_p2wi.c
+++ b/drivers/i2c/sun6i_p2wi.c
@@ -20,10 +20,10 @@
 #include <errno.h>
 #include <i2c.h>
 #include <reset.h>
+#include <sunxi_gpio.h>
 #include <time.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/p2wi.h>
 #include <asm/arch/prcm.h>
 #include <asm/arch/sys_proto.h>
diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c
index 47fa05b6d1c..f36f2c7afac 100644
--- a/drivers/i2c/sun8i_rsb.c
+++ b/drivers/i2c/sun8i_rsb.c
@@ -14,10 +14,10 @@
 #include <dm.h>
 #include <errno.h>
 #include <i2c.h>
+#include <sunxi_gpio.h>
 #include <reset.h>
 #include <time.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/prcm.h>
 #include <asm/arch/rsb.h>
 
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 1bb7b6d0e92..a9132af3f64 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -21,6 +21,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/mmc.h>
 #include <linux/delay.h>
+#include <sunxi_gpio.h>
 
 #ifndef CCM_MMC_CTRL_MODE_SEL_NEW
 #define CCM_MMC_CTRL_MODE_SEL_NEW	0
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 5ab3951ab52..8c12febcc0d 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -7,6 +7,7 @@
 #include <dm/pinctrl.h>
 #include <errno.h>
 #include <malloc.h>
+#include <sunxi_gpio.h>
 
 #include <asm/gpio.h>
 
diff --git a/drivers/video/hitachi_tx18d42vm_lcd.c b/drivers/video/hitachi_tx18d42vm_lcd.c
index 87c4d27438a..95984fe3d3d 100644
--- a/drivers/video/hitachi_tx18d42vm_lcd.c
+++ b/drivers/video/hitachi_tx18d42vm_lcd.c
@@ -10,6 +10,7 @@
 #include <linux/delay.h>
 
 #include <asm/gpio.h>
+#include <sunxi_gpio.h>
 #include <errno.h>
 
 /*
diff --git a/drivers/video/ssd2828.c b/drivers/video/ssd2828.c
index 4cdcbe7755a..948f5e74d0f 100644
--- a/drivers/video/ssd2828.c
+++ b/drivers/video/ssd2828.c
@@ -12,7 +12,6 @@
 #include <common.h>
 #include <malloc.h>
 #include <mipi_display.h>
-#include <asm/arch/gpio.h>
 #include <asm/gpio.h>
 #include <linux/delay.h>
 
diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c
index 2ee6212c58d..7cc2f5577f3 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -31,6 +31,7 @@
 #include <malloc.h>
 #include <video.h>
 #include <dm/uclass-internal.h>
+#include <sunxi_gpio.h>
 #include "../videomodes.h"
 #include "../anx9804.h"
 #include "../hitachi_tx18d42vm_lcd.h"
diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c
index 8b9c3b2bfa9..7a01cc343ca 100644
--- a/drivers/video/sunxi/sunxi_lcd.c
+++ b/drivers/video/sunxi/sunxi_lcd.c
@@ -17,6 +17,7 @@
 #include <asm/arch/lcdc.h>
 #include <asm/global_data.h>
 #include <asm/gpio.h>
+#include <sunxi_gpio.h>
 
 struct sunxi_lcd_priv {
 	struct display_timing timing;
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/include/sunxi_gpio.h
similarity index 100%
rename from arch/arm/include/asm/arch-sunxi/gpio.h
rename to include/sunxi_gpio.h
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 06/17] pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (4 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 05/17] pinctrl: sunxi: move pinctrl code and remove GPIO_EXTRA_HEADER Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 07/17] pinctrl: sunxi: add new D1 pinctrl support Andre Przywara
                   ` (11 subsequent siblings)
  17 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

On the Allwinner platform we were describing a quite comprehensive
memory map in a per-SoC header unser arch/arm.
In the old days that was used by every driver, but nowadays it should
only be needed by SPL drivers (not using the DT). Many addresses in
there were never used, and some are not needed anymore.

To avoid a dependency on CPU specific headers in an arch specific
directory, move the definition of the pinctroller MMIO base address into
the sunxi_gpio.h header, because the SPL routines for GPIO should be the
only one needing this address.
This is a first step towards getting rid of cpu_sun[x]i.h completely,
and allows to remove the inclusion of that file from the sunxi_gpio.h
header.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h     |  2 --
 arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h |  2 --
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h     |  2 --
 include/sunxi_gpio.h                            | 12 +++++++++++-
 4 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index f7ecc790dbf..d6fe51f24bc 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -91,7 +91,6 @@
 
 #define SUNXI_CCM_BASE			0x01c20000
 #define SUNXI_INTC_BASE			0x01c20400
-#define SUNXI_PIO_BASE			0x01c20800
 #define SUNXI_TIMER_BASE		0x01c20c00
 #ifndef CONFIG_SUNXI_GEN_SUN6I
 #define SUNXI_PWM_BASE			0x01c20e00
@@ -210,7 +209,6 @@ defined(CONFIG_MACH_SUN50I)
 
 #define SUNXI_R_TWI_BASE		0x01f02400
 #define SUNXI_R_UART_BASE		0x01f02800
-#define SUNXI_R_PIO_BASE		0x01f02c00
 #define SUN6I_P2WI_BASE			0x01f03400
 #define SUNXI_RSB_BASE			0x01f03400
 
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
index d9cf8ae0428..9b6bf843601 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
@@ -22,7 +22,6 @@
 #define SUNXI_SIDC_BASE			0x03006000
 #define SUNXI_SID_BASE			0x03006200
 #define SUNXI_TIMER_BASE		0x03009000
-#define SUNXI_PIO_BASE			0x0300B000
 #define SUNXI_PSI_BASE			0x0300C000
 
 #define SUNXI_GIC400_BASE		0x03020000
@@ -68,7 +67,6 @@
 #define SUNXI_R_CPUCFG_BASE		0x07000400
 #define SUNXI_PRCM_BASE			0x07010000
 #define SUNXI_R_WDOG_BASE		0x07020400
-#define SUNXI_R_PIO_BASE		0x07022000
 #define SUNXI_R_UART_BASE		0x07080000
 #define SUNXI_R_TWI_BASE		0x07081400
 
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index 9c2d11b5901..20025be2319 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -81,7 +81,6 @@
 /* APB0 Module */
 #define SUNXI_CCM_BASE			(REGS_APB0_BASE + 0x0000)
 #define SUNXI_CCMMODULE_BASE		(REGS_APB0_BASE + 0x0400)
-#define SUNXI_PIO_BASE			(REGS_APB0_BASE + 0x0800)
 #define SUNXI_TIMER_BASE		(REGS_APB0_BASE + 0x0C00)
 #define SUNXI_PWM_BASE			(REGS_APB0_BASE + 0x1400)
 #define SUNXI_LRADC_BASE		(REGS_APB0_BASE + 0x1800)
@@ -102,7 +101,6 @@
 /* RCPUS Module */
 #define SUNXI_PRCM_BASE			(REGS_RCPUS_BASE + 0x1400)
 #define SUNXI_R_UART_BASE		(REGS_RCPUS_BASE + 0x2800)
-#define SUNXI_R_PIO_BASE		(REGS_RCPUS_BASE + 0x2c00)
 #define SUNXI_RSB_BASE			(REGS_RCPUS_BASE + 0x3400)
 
 /* Misc. */
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index 42ca03d8c18..5ac476f960d 100644
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -9,7 +9,17 @@
 #define _SUNXI_GPIO_H
 
 #include <linux/types.h>
-#include <asm/arch/cpu.h>
+
+#if defined(CONFIG_MACH_SUN9I)
+#define SUNXI_PIO_BASE		0x06000800
+#define SUNXI_R_PIO_BASE	0x08002c00
+#elif defined(CONFIG_SUN50I_GEN_H6)
+#define SUNXI_PIO_BASE		0x0300b000
+#define SUNXI_R_PIO_BASE	0x07022000
+#else
+#define SUNXI_PIO_BASE		0x01c20800
+#define SUNXI_R_PIO_BASE	0x01f02c00
+#endif
 
 /*
  * sunxi has 9 banks of gpio, they are:
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 07/17] pinctrl: sunxi: add new D1 pinctrl support
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (5 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 06/17] pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model Andre Przywara
                   ` (10 subsequent siblings)
  17 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

For the first time since at least the Allwinner A10 SoCs, the D1 (and
related cores) use a new pincontroller MMIO register layout, so we
cannot use our hardcoded, fixed offsets anymore.
Ideally this would all be handled by devicetree and DM drivers, but for
the DT-less SPL we still need the legacy interfaces.

Add a new Kconfig symbol to differenciate between the two generations of
pincontrollers, and just use that to just switch some basic symbols.
The rest is already abstracted enough, so works out of the box.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/mach-sunxi/Kconfig |  6 ++++++
 include/sunxi_gpio.h        | 26 +++++++++++++++++++++-----
 2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 6220175d612..5e019948f85 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -113,6 +113,12 @@ config SUNXI_SRAM_ADDRESS
 config SUNXI_A64_TIMER_ERRATUM
 	bool
 
+config SUNXI_NEW_PINCTRL
+	bool
+	---help---
+	The Allwinner D1 and other new SoCs use a different register map
+	for the GPIO block, which we need to know about in the SPL.
+
 # Note only one of these may be selected at a time! But hidden choices are
 # not supported by Kconfig
 config SUNXI_GEN_SUN4I
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index 5ac476f960d..2f8b220f750 100644
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -68,15 +68,32 @@
 #define GPIO_DAT_REG_OFFSET	0x10
 
 #define GPIO_DRV_REG_OFFSET	0x14
-#define GPIO_DRV_INDEX(pin)	(((pin) & 0x1f) >> 4)
-#define GPIO_DRV_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
+
+/*		Newer SoCs use a slightly different register layout */
+#ifdef CONFIG_SUNXI_NEW_PINCTRL
+/* pin drive strength: 4 bits per pin */
+#define GPIO_DRV_INDEX(pin)	((pin) / 8)
+#define GPIO_DRV_OFFSET(pin)	(((pin) % 8) * 4)
+
+#define GPIO_PULL_REG_OFFSET	0x24
+
+#define SUNXI_PINCTRL_BANK_SIZE	0x30
+#define SUNXI_GPIO_DISABLE	0xf
+
+#else /* older generation pin controllers */
+/* pin drive strength: 2 bits per pin */
+#define GPIO_DRV_INDEX(pin)	((pin) / 16)
+#define GPIO_DRV_OFFSET(pin)	(((pin) % 16) * 2)
 
 #define GPIO_PULL_REG_OFFSET	0x1c
+
+#define SUNXI_PINCTRL_BANK_SIZE	0x24
+#define SUNXI_GPIO_DISABLE	0x7
+#endif
+
 #define GPIO_PULL_INDEX(pin)	(((pin) & 0x1f) >> 4)
 #define GPIO_PULL_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
 
-#define SUNXI_PINCTRL_BANK_SIZE 0x24
-
 static inline void* BANK_TO_GPIO(int bank)
 {
 	void *pio_base;
@@ -132,7 +149,6 @@ enum sunxi_gpio_number {
 /* GPIO pin function config */
 #define SUNXI_GPIO_INPUT	0
 #define SUNXI_GPIO_OUTPUT	1
-#define SUNXI_GPIO_DISABLE	7
 
 #define SUN8I_H3_GPA_UART0	2
 #define SUN8I_H3_GPA_UART2	2
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (6 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 07/17] pinctrl: sunxi: add new D1 pinctrl support Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-06  5:38   ` Icenowy Zheng
                     ` (2 more replies)
  2022-12-06  0:45 ` [RFC PATCH 09/17] pinctrl: sunxi: add Allwinner D1 pinctrl description Andre Przywara
                   ` (9 subsequent siblings)
  17 siblings, 3 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

Allwinner seems to typically stick to a common MMIO memory map for
several SoCs, but from time to time does some breaking changes, which
also introduce new generations of some peripherals. The last time this
happened with the H6, which apart from re-organising the base addresses
also changed the clock controller significantly. We added a
CONFIG_SUN50I_GEN_H6 symbol back then to mark SoCs sharing those traits.

Now the Allwinner D1 changes the memory map again, and also extends the
pincontroller, among other peripherals.
To mark this generation of SoCs, add a CONFIG_SUNXI_GEN_NCAT2 symbol,
this name is reportedly used in the Allwinner BSP code, and prevents us
from inventing our own name.

Add this new symbol to some guards that were already checking for the H6
generation, since many features are shared between the two (like the
renovated clock controller).

This paves the way to introduce a first user of this generation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/include/asm/arch-sunxi/clock.h       |  2 +-
 arch/arm/include/asm/arch-sunxi/cpu.h         |  2 +
 .../include/asm/arch-sunxi/cpu_sunxi_ncat2.h  | 54 +++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/mmc.h         |  2 +-
 arch/arm/include/asm/arch-sunxi/prcm.h        |  2 +-
 arch/arm/include/asm/arch-sunxi/timer.h       |  2 +-
 arch/arm/mach-sunxi/Kconfig                   | 14 ++++-
 arch/arm/mach-sunxi/Makefile                  |  1 +
 arch/arm/mach-sunxi/board.c                   |  4 +-
 common/spl/Kconfig                            |  2 +-
 drivers/mmc/sunxi_mmc.c                       | 10 ++--
 include/sunxi_gpio.h                          |  3 ++
 12 files changed, 86 insertions(+), 12 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h

diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 2cfd5407423..3d34261b0e5 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -16,7 +16,7 @@
 /* clock control module regs definition */
 #if defined(CONFIG_MACH_SUN8I_A83T)
 #include <asm/arch/clock_sun8i_a83t.h>
-#elif defined(CONFIG_SUN50I_GEN_H6)
+#elif defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
 #include <asm/arch/clock_sun50i_h6.h>
 #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
       defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index b08f2023748..768c6572d6b 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -10,6 +10,8 @@
 #include <asm/arch/cpu_sun9i.h>
 #elif defined(CONFIG_SUN50I_GEN_H6)
 #include <asm/arch/cpu_sun50i_h6.h>
+#elif defined(CONFIG_SUNXI_GEN_NCAT2)
+#include <asm/arch/cpu_sunxi_ncat2.h>
 #else
 #include <asm/arch/cpu_sun4i.h>
 #endif
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
new file mode 100644
index 00000000000..13093085a5e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2022 Arm Limited
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_SUNXI_NCAT2_H
+#define _SUNXI_CPU_SUNXI_NCAT2_H
+
+#define SUNXI_SRAM_A1_BASE		CONFIG_SUNXI_SRAM_ADDRESS
+#define SUNXI_SRAM_C_BASE		0x00028000
+#define SUNXI_SRAM_A2_BASE		0x00100000
+
+#define SUNXI_SRAMC_BASE		0x02800000
+#define SUNXI_CCM_BASE			0x02001000
+/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
+#define SUNXI_SIDC_BASE			0x03006000
+#define SUNXI_SID_BASE			0x03006200
+#define SUNXI_TIMER_BASE		0x02050000
+
+#ifdef CONFIG_MACH_SUN50I_H6
+#define SUNXI_DRAM_COM_BASE		0x04002000
+#define SUNXI_DRAM_CTL0_BASE		0x04003000
+#define SUNXI_DRAM_PHY0_BASE		0x04005000
+#endif
+#define SUNXI_MMC0_BASE			0x04020000
+#define SUNXI_MMC1_BASE			0x04021000
+#define SUNXI_MMC2_BASE			0x04022000
+
+#define SUNXI_UART0_BASE		0x02500000
+#define SUNXI_UART1_BASE		0x02500400
+#define SUNXI_UART2_BASE		0x02500800
+#define SUNXI_UART3_BASE		0x02500C00
+#define SUNXI_TWI0_BASE			0x02502000
+#define SUNXI_TWI1_BASE			0x02502400
+#define SUNXI_TWI2_BASE			0x02502800
+#define SUNXI_TWI3_BASE			0x02502C00
+#define SUNXI_SPI0_BASE			0x04025000
+#define SUNXI_SPI1_BASE			0x04026000
+
+#define SUNXI_RTC_BASE			0x07000000
+#define SUNXI_R_CPUCFG_BASE		0x07000400
+#define SUNXI_PRCM_BASE			0x07010000
+#define SUNXI_R_WDOG_BASE		0x07020400
+#define SUNXI_R_UART_BASE		0x07080000
+#define SUNXI_R_TWI_BASE		0x07081400
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif
+
+#endif /* _SUNXI_CPU_SUNXI_NCAT2_H */
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 5daacf10eb1..8ed3e0459c9 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -45,7 +45,7 @@ struct sunxi_mmc {
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
 	u32 res2[26];
-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
 	u32 res3[17];
 	u32 samp_dl;
 	u32 res4[46];
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 5106076f5e9..c5418cfd28d 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -9,7 +9,7 @@
 #define _SUNXI_PRCM_H
 
 /* prcm regs definition */
-#if defined(CONFIG_SUN50I_GEN_H6)
+#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
 #include <asm/arch/prcm_sun50i.h>
 #else
 #include <asm/arch/prcm_sun6i.h>
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
index bb5626d893b..e17db8588e2 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -76,7 +76,7 @@ struct sunxi_timer_reg {
 	struct sunxi_tgp tgp[4];
 	u8 res5[8];
 	u32 cpu_cfg;
-#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
 	u8 res3[16];
 	struct sunxi_wdog wdog[5];	/* We have 5 watchdogs */
 #endif
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 5e019948f85..b59db212fa8 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -102,7 +102,7 @@ config AXP_PMIC_BUS
 config SUNXI_SRAM_ADDRESS
 	hex
 	default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
-	default 0x20000 if SUN50I_GEN_H6
+	default 0x20000 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
 	default 0x0
 	---help---
 	Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
@@ -144,6 +144,16 @@ config SUN50I_GEN_H6
 	Select this for sunxi SoCs which have H6 like peripherals, clocks
 	and memory map.
 
+config SUNXI_GEN_NCAT2
+	bool
+	select FIT
+	select SPL_LOAD_FIT
+	select MMC_SUNXI_HAS_NEW_MODE
+	select SUPPORT_SPL
+	---help---
+	Select this for sunxi SoCs which have D1 like peripherals, clocks
+	and memory map.
+
 config SUNXI_DRAM_DW
 	bool
 	---help---
@@ -787,6 +797,7 @@ config VIDEO_SUNXI
 	depends on !MACH_SUN9I
 	depends on !MACH_SUN50I
 	depends on !SUN50I_GEN_H6
+	depends on !SUNXI_GEN_NCAT2
 	select VIDEO
 	select DISPLAY
 	imply VIDEO_DT_SIMPLEFB
@@ -1000,6 +1011,7 @@ config SPL_STACK_R_ADDR
 	default 0x2fe00000 if MACH_SUN9I
 	default 0x4fe00000 if MACH_SUN50I
 	default 0x4fe00000 if SUN50I_GEN_H6
+	default 0x4fe00000 if SUNXI_GEN_NCAT2
 
 config SPL_SPI_SUNXI
 	bool "Support for SPI Flash on Allwinner SoCs in SPL"
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 671211e9322..1d4c70ec352 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_MACH_SUN8I)	+= clock_sun6i.o
 endif
 obj-$(CONFIG_MACH_SUN9I)	+= clock_sun9i.o gtbus_sun9i.o
 obj-$(CONFIG_SUN50I_GEN_H6)	+= clock_sun50i_h6.o
+obj-$(CONFIG_SUNXI_GEN_NCAT2)	+= clock_sun50i_h6.o
 ifndef CONFIG_ARM64
 obj-y	+= timer.o
 endif
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index b6ffbff883c..3763ec3d2e4 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -177,7 +177,7 @@ static int gpio_init(void)
 #error Unsupported console port number. Please fix pin mux settings in board.c
 #endif
 
-#ifdef CONFIG_SUN50I_GEN_H6
+#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
 	/* Update PIO power bias configuration by copy hardware detected value */
 	val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
 	writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
@@ -475,7 +475,7 @@ void reset_cpu(void)
 		/* sun5i sometimes gets stuck without this */
 		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 	}
-#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
 #if defined(CONFIG_MACH_SUN50I_H6)
 	/* WDOG is broken for some H6 rev. use the R_WDOG instead */
 	static const struct sunxi_wdog *wdog =
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index fef01bdd7da..fdd64db498f 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -265,7 +265,7 @@ config SPL_TEXT_BASE
 	default 0x402F0400 if AM33XX
 	default 0x40301350 if OMAP54XX
 	default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
-	default 0x20060 if SUN50I_GEN_H6
+	default 0x20060 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
 	default 0x00060 if ARCH_SUNXI
 	default 0xfffc0000 if ARCH_ZYNQMP
 	default 0x0
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index a9132af3f64..6ce2729473c 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -114,6 +114,7 @@ static bool sunxi_mmc_can_calibrate(void)
 	return IS_ENABLED(CONFIG_MACH_SUN50I) ||
 	       IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
 	       IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
+	       IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) ||
 	       IS_ENABLED(CONFIG_MACH_SUN8I_R40);
 }
 
@@ -248,7 +249,7 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
 	rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 	writel(rval, &priv->reg->clkcr);
 
-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
 	/* A64 supports calibration of delays on MMC controller and we
 	 * have to set delay of zero before starting calibration.
 	 * Allwinner BSP driver sets a delay only in the case of
@@ -559,7 +560,8 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 	cfg->host_caps = MMC_MODE_4BIT;
 
 	if ((IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN8I) ||
-	    IS_ENABLED(CONFIG_SUN50I_GEN_H6)) && (sdc_no == 2))
+	    IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
+	    IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) && (sdc_no == 2))
 		cfg->host_caps = MMC_MODE_8BIT;
 
 	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
@@ -573,7 +575,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 
 	/* config ahb clock */
 	debug("init mmc %d clock and io\n", sdc_no);
-#if !defined(CONFIG_SUN50I_GEN_H6)
+#if !defined(CONFIG_SUN50I_GEN_H6) && !defined(CONFIG_SUNXI_GEN_NCAT2)
 	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 
 #ifdef CONFIG_SUNXI_GEN_SUN6I
@@ -647,7 +649,7 @@ static unsigned get_mclk_offset(void)
 	if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
 		return 0x410;
 
-	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
+	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
 		return 0x830;
 
 	return 0x88;
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index 2f8b220f750..04d7aa3d632 100644
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -16,6 +16,9 @@
 #elif defined(CONFIG_SUN50I_GEN_H6)
 #define SUNXI_PIO_BASE		0x0300b000
 #define SUNXI_R_PIO_BASE	0x07022000
+#elif defined(CONFIG_SUNXI_GEN_NCAT2)
+#define SUNXI_PIO_BASE		0x02000000
+#define SUNXI_R_PIO_BASE	0
 #else
 #define SUNXI_PIO_BASE		0x01c20800
 #define SUNXI_R_PIO_BASE	0x01f02c00
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 09/17] pinctrl: sunxi: add Allwinner D1 pinctrl description
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (7 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU Andre Przywara
                   ` (8 subsequent siblings)
  17 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

Apart from using the new pinctrl MMIO register layout, the Allwinner D1
and related SoCs still need to usual set of mux values hardcoded in
U-Boot's pinctrl driver.
Add the values we need so far to this list, so that DM based drivers
will just work without further ado.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/pinctrl/sunxi/Kconfig         |  4 ++++
 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 28 +++++++++++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 77da90836b6..c8f937d91e9 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -124,4 +124,8 @@ config PINCTRL_SUN50I_H616_R
 	default MACH_SUN50I_H616
 	select PINCTRL_SUNXI
 
+config PINCTRL_SUN20I_D1
+	bool "Support for the Allwinner D1/R528 PIO"
+	select PINCTRL_SUNXI
+
 endif
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 8c12febcc0d..83720cea747 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -728,6 +728,28 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc
 	.num_banks	= 1,
 };
 
+static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = {
+	{ "emac",	8 },	/* PE0-PE15 */
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc2",	3 },	/* PC1-PC7 */
+	{ "spi0",	2 },	/* PC2-PC7 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	6 },	/* PB2-PB3 */
+#endif
+	{ "uart3",	3 },	/* PB6-PB9 */
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = {
+	.functions	= sun20i_d1_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun20i_d1_pinctrl_functions),
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 7,
+};
+
 static const struct udevice_id sunxi_pinctrl_ids[] = {
 #ifdef CONFIG_PINCTRL_SUNIV_F1C100S
 	{
@@ -884,6 +906,12 @@ static const struct udevice_id sunxi_pinctrl_ids[] = {
 		.compatible = "allwinner,sun50i-h616-r-pinctrl",
 		.data = (ulong)&sun50i_h616_r_pinctrl_desc,
 	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN20I_D1
+	{
+		.compatible = "allwinner,sun20i-d1-pinctrl",
+		.data = (ulong)&sun20i_d1_pinctrl_desc,
+	},
 #endif
 	{}
 };
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (8 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 09/17] pinctrl: sunxi: add Allwinner D1 pinctrl description Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2023-05-22  3:57   ` Sam Edwards
  2023-05-26  0:34   ` Sam Edwards
  2022-12-06  0:45 ` [RFC PATCH 11/17] sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup Andre Przywara
                   ` (7 subsequent siblings)
  17 siblings, 2 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

From: Samuel Holland <samuel@sholland.org>

Since the D1 CCU binding is defined, we can add support for its
gates/resets, following the pattern of the existing drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
---
 drivers/clk/sunxi/Kconfig                 |   6 +
 drivers/clk/sunxi/Makefile                |   1 +
 drivers/clk/sunxi/clk_d1.c                | 101 ++++++++++++++
 include/dt-bindings/clock/sun20i-d1-ccu.h | 156 ++++++++++++++++++++++
 include/dt-bindings/reset/sun20i-d1-ccu.h |  77 +++++++++++
 5 files changed, 341 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_d1.c
 create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h
 create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index bf11fad6eef..f65e482ba4c 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -87,6 +87,12 @@ config CLK_SUN8I_H3
 	  This enables common clock driver support for platforms based
 	  on Allwinner H3/H5 SoC.
 
+config CLK_SUN20I_D1
+	bool "Clock driver for Allwinner D1"
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner D1 SoC.
+
 config CLK_SUN50I_H6
 	bool "Clock driver for Allwinner H6"
 	default MACH_SUN50I_H6
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 895da02ebea..90a277489dc 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
 obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
 obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
+obj-$(CONFIG_CLK_SUN20I_D1) += clk_d1.o
 obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
 obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
 obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
diff --git a/drivers/clk/sunxi/clk_d1.c b/drivers/clk/sunxi/clk_d1.c
new file mode 100644
index 00000000000..9412b77a542
--- /dev/null
+++ b/drivers/clk/sunxi/clk_d1.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun20i-d1-ccu.h>
+#include <dt-bindings/reset/sun20i-d1-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate d1_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
+	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
+	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
+	[CLK_BUS_UART0]		= GATE(0x90c, BIT(0)),
+	[CLK_BUS_UART1]		= GATE(0x90c, BIT(1)),
+	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
+	[CLK_BUS_UART3]		= GATE(0x90c, BIT(3)),
+	[CLK_BUS_UART4]		= GATE(0x90c, BIT(4)),
+	[CLK_BUS_UART5]		= GATE(0x90c, BIT(5)),
+	[CLK_BUS_I2C0]		= GATE(0x91c, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x91c, BIT(1)),
+	[CLK_BUS_I2C2]		= GATE(0x91c, BIT(2)),
+	[CLK_BUS_I2C3]		= GATE(0x91c, BIT(3)),
+	[CLK_SPI0]		= GATE(0x940, BIT(31)),
+	[CLK_SPI1]		= GATE(0x944, BIT(31)),
+	[CLK_BUS_SPI0]		= GATE(0x96c, BIT(0)),
+	[CLK_BUS_SPI1]		= GATE(0x96c, BIT(1)),
+
+	[CLK_BUS_EMAC]		= GATE(0x97c, BIT(0)),
+
+	[CLK_USB_OHCI0]		= GATE(0xa70, BIT(31)),
+	[CLK_USB_OHCI1]		= GATE(0xa74, BIT(31)),
+	[CLK_BUS_OHCI0]		= GATE(0xa8c, BIT(0)),
+	[CLK_BUS_OHCI1]		= GATE(0xa8c, BIT(1)),
+	[CLK_BUS_EHCI0]		= GATE(0xa8c, BIT(4)),
+	[CLK_BUS_EHCI1]		= GATE(0xa8c, BIT(5)),
+	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
+	[CLK_BUS_LRADC]		= GATE(0xa9c, BIT(0)),
+
+	[CLK_RISCV]		= GATE(0xd04, BIT(31)),
+};
+
+static struct ccu_reset d1_resets[] = {
+	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
+	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
+	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
+	[RST_BUS_UART0]		= RESET(0x90c, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x90c, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x90c, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x90c, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x90c, BIT(20)),
+	[RST_BUS_UART5]		= RESET(0x90c, BIT(21)),
+	[RST_BUS_I2C0]		= RESET(0x91c, BIT(16)),
+	[RST_BUS_I2C1]		= RESET(0x91c, BIT(17)),
+	[RST_BUS_I2C2]		= RESET(0x91c, BIT(18)),
+	[RST_BUS_I2C3]		= RESET(0x91c, BIT(19)),
+	[RST_BUS_SPI0]		= RESET(0x96c, BIT(16)),
+	[RST_BUS_SPI1]		= RESET(0x96c, BIT(17)),
+
+	[RST_BUS_EMAC]		= RESET(0x97c, BIT(16)),
+
+	[RST_USB_PHY0]		= RESET(0xa70, BIT(30)),
+	[RST_USB_PHY1]		= RESET(0xa74, BIT(30)),
+	[RST_BUS_OHCI0]		= RESET(0xa8c, BIT(16)),
+	[RST_BUS_OHCI1]		= RESET(0xa8c, BIT(17)),
+	[RST_BUS_EHCI0]		= RESET(0xa8c, BIT(20)),
+	[RST_BUS_EHCI1]		= RESET(0xa8c, BIT(21)),
+	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
+	[RST_BUS_LRADC]		= RESET(0xa9c, BIT(16)),
+};
+
+static const struct ccu_desc d1_ccu_desc = {
+	.gates	= d1_gates,
+	.resets	= d1_resets,
+};
+
+static int d1_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(d1_resets));
+}
+
+static const struct udevice_id d1_ccu_ids[] = {
+	{ .compatible = "allwinner,sun20i-d1-ccu",
+	  .data = (ulong)&d1_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun20i_d1) = {
+	.name		= "sun20i_d1_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= d1_ccu_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= d1_clk_bind,
+};
diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h
new file mode 100644
index 00000000000..e3ac53315e1
--- /dev/null
+++ b/include/dt-bindings/clock/sun20i-d1-ccu.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2020 huangzhenwei@allwinnertech.com
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
+#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
+
+#define CLK_PLL_CPUX		0
+#define CLK_PLL_DDR0		1
+#define CLK_PLL_PERIPH0_4X	2
+#define CLK_PLL_PERIPH0_2X	3
+#define CLK_PLL_PERIPH0_800M	4
+#define CLK_PLL_PERIPH0		5
+#define CLK_PLL_PERIPH0_DIV3	6
+#define CLK_PLL_VIDEO0_4X	7
+#define CLK_PLL_VIDEO0_2X	8
+#define CLK_PLL_VIDEO0		9
+#define CLK_PLL_VIDEO1_4X	10
+#define CLK_PLL_VIDEO1_2X	11
+#define CLK_PLL_VIDEO1		12
+#define CLK_PLL_VE		13
+#define CLK_PLL_AUDIO0_4X	14
+#define CLK_PLL_AUDIO0_2X	15
+#define CLK_PLL_AUDIO0		16
+#define CLK_PLL_AUDIO1		17
+#define CLK_PLL_AUDIO1_DIV2	18
+#define CLK_PLL_AUDIO1_DIV5	19
+#define CLK_CPUX		20
+#define CLK_CPUX_AXI		21
+#define CLK_CPUX_APB		22
+#define CLK_PSI_AHB		23
+#define CLK_APB0		24
+#define CLK_APB1		25
+#define CLK_MBUS		26
+#define CLK_DE			27
+#define CLK_BUS_DE		28
+#define CLK_DI			29
+#define CLK_BUS_DI		30
+#define CLK_G2D			31
+#define CLK_BUS_G2D		32
+#define CLK_CE			33
+#define CLK_BUS_CE		34
+#define CLK_VE			35
+#define CLK_BUS_VE		36
+#define CLK_BUS_DMA		37
+#define CLK_BUS_MSGBOX0		38
+#define CLK_BUS_MSGBOX1		39
+#define CLK_BUS_MSGBOX2		40
+#define CLK_BUS_SPINLOCK	41
+#define CLK_BUS_HSTIMER		42
+#define CLK_AVS			43
+#define CLK_BUS_DBG		44
+#define CLK_BUS_PWM		45
+#define CLK_BUS_IOMMU		46
+#define CLK_DRAM		47
+#define CLK_MBUS_DMA		48
+#define CLK_MBUS_VE		49
+#define CLK_MBUS_CE		50
+#define CLK_MBUS_TVIN		51
+#define CLK_MBUS_CSI		52
+#define CLK_MBUS_G2D		53
+#define CLK_MBUS_RISCV		54
+#define CLK_BUS_DRAM		55
+#define CLK_MMC0		56
+#define CLK_MMC1		57
+#define CLK_MMC2		58
+#define CLK_BUS_MMC0		59
+#define CLK_BUS_MMC1		60
+#define CLK_BUS_MMC2		61
+#define CLK_BUS_UART0		62
+#define CLK_BUS_UART1		63
+#define CLK_BUS_UART2		64
+#define CLK_BUS_UART3		65
+#define CLK_BUS_UART4		66
+#define CLK_BUS_UART5		67
+#define CLK_BUS_I2C0		68
+#define CLK_BUS_I2C1		69
+#define CLK_BUS_I2C2		70
+#define CLK_BUS_I2C3		71
+#define CLK_SPI0		72
+#define CLK_SPI1		73
+#define CLK_BUS_SPI0		74
+#define CLK_BUS_SPI1		75
+#define CLK_EMAC_25M		76
+#define CLK_BUS_EMAC		77
+#define CLK_IR_TX		78
+#define CLK_BUS_IR_TX		79
+#define CLK_BUS_GPADC		80
+#define CLK_BUS_THS		81
+#define CLK_I2S0		82
+#define CLK_I2S1		83
+#define CLK_I2S2		84
+#define CLK_I2S2_ASRC		85
+#define CLK_BUS_I2S0		86
+#define CLK_BUS_I2S1		87
+#define CLK_BUS_I2S2		88
+#define CLK_SPDIF_TX		89
+#define CLK_SPDIF_RX		90
+#define CLK_BUS_SPDIF		91
+#define CLK_DMIC		92
+#define CLK_BUS_DMIC		93
+#define CLK_AUDIO_DAC		94
+#define CLK_AUDIO_ADC		95
+#define CLK_BUS_AUDIO		96
+#define CLK_USB_OHCI0		97
+#define CLK_USB_OHCI1		98
+#define CLK_BUS_OHCI0		99
+#define CLK_BUS_OHCI1		100
+#define CLK_BUS_EHCI0		101
+#define CLK_BUS_EHCI1		102
+#define CLK_BUS_OTG		103
+#define CLK_BUS_LRADC		104
+#define CLK_BUS_DPSS_TOP	105
+#define CLK_HDMI_24M		106
+#define CLK_HDMI_CEC_32K	107
+#define CLK_HDMI_CEC		108
+#define CLK_BUS_HDMI		109
+#define CLK_MIPI_DSI		110
+#define CLK_BUS_MIPI_DSI	111
+#define CLK_TCON_LCD0		112
+#define CLK_BUS_TCON_LCD0	113
+#define CLK_TCON_TV		114
+#define CLK_BUS_TCON_TV		115
+#define CLK_TVE			116
+#define CLK_BUS_TVE_TOP		117
+#define CLK_BUS_TVE		118
+#define CLK_TVD			119
+#define CLK_BUS_TVD_TOP		120
+#define CLK_BUS_TVD		121
+#define CLK_LEDC		122
+#define CLK_BUS_LEDC		123
+#define CLK_CSI_TOP		124
+#define CLK_CSI_MCLK		125
+#define CLK_BUS_CSI		126
+#define CLK_TPADC		127
+#define CLK_BUS_TPADC		128
+#define CLK_BUS_TZMA		129
+#define CLK_DSP			130
+#define CLK_BUS_DSP_CFG		131
+#define CLK_RISCV		132
+#define CLK_RISCV_AXI		133
+#define CLK_BUS_RISCV_CFG	134
+#define CLK_FANOUT_24M		135
+#define CLK_FANOUT_12M		136
+#define CLK_FANOUT_16M		137
+#define CLK_FANOUT_25M		138
+#define CLK_FANOUT_32K		139
+#define CLK_FANOUT_27M		140
+#define CLK_FANOUT_PCLK		141
+#define CLK_FANOUT0		142
+#define CLK_FANOUT1		143
+#define CLK_FANOUT2		144
+
+#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun20i-d1-ccu.h b/include/dt-bindings/reset/sun20i-d1-ccu.h
new file mode 100644
index 00000000000..de9ff520323
--- /dev/null
+++ b/include/dt-bindings/reset/sun20i-d1-ccu.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2020 huangzhenwei@allwinnertech.com
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
+#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
+
+#define RST_MBUS		0
+#define RST_BUS_DE		1
+#define RST_BUS_DI		2
+#define RST_BUS_G2D		3
+#define RST_BUS_CE		4
+#define RST_BUS_VE		5
+#define RST_BUS_DMA		6
+#define RST_BUS_MSGBOX0		7
+#define RST_BUS_MSGBOX1		8
+#define RST_BUS_MSGBOX2		9
+#define RST_BUS_SPINLOCK	10
+#define RST_BUS_HSTIMER		11
+#define RST_BUS_DBG		12
+#define RST_BUS_PWM		13
+#define RST_BUS_DRAM		14
+#define RST_BUS_MMC0		15
+#define RST_BUS_MMC1		16
+#define RST_BUS_MMC2		17
+#define RST_BUS_UART0		18
+#define RST_BUS_UART1		19
+#define RST_BUS_UART2		20
+#define RST_BUS_UART3		21
+#define RST_BUS_UART4		22
+#define RST_BUS_UART5		23
+#define RST_BUS_I2C0		24
+#define RST_BUS_I2C1		25
+#define RST_BUS_I2C2		26
+#define RST_BUS_I2C3		27
+#define RST_BUS_SPI0		28
+#define RST_BUS_SPI1		29
+#define RST_BUS_EMAC		30
+#define RST_BUS_IR_TX		31
+#define RST_BUS_GPADC		32
+#define RST_BUS_THS		33
+#define RST_BUS_I2S0		34
+#define RST_BUS_I2S1		35
+#define RST_BUS_I2S2		36
+#define RST_BUS_SPDIF		37
+#define RST_BUS_DMIC		38
+#define RST_BUS_AUDIO		39
+#define RST_USB_PHY0		40
+#define RST_USB_PHY1		41
+#define RST_BUS_OHCI0		42
+#define RST_BUS_OHCI1		43
+#define RST_BUS_EHCI0		44
+#define RST_BUS_EHCI1		45
+#define RST_BUS_OTG		46
+#define RST_BUS_LRADC		47
+#define RST_BUS_DPSS_TOP	48
+#define RST_BUS_HDMI_SUB	49
+#define RST_BUS_HDMI_MAIN	50
+#define RST_BUS_MIPI_DSI	51
+#define RST_BUS_TCON_LCD0	52
+#define RST_BUS_TCON_TV		53
+#define RST_BUS_LVDS0		54
+#define RST_BUS_TVE		55
+#define RST_BUS_TVE_TOP		56
+#define RST_BUS_TVD		57
+#define RST_BUS_TVD_TOP		58
+#define RST_BUS_LEDC		59
+#define RST_BUS_CSI		60
+#define RST_BUS_TPADC		61
+#define RST_DSP			62
+#define RST_BUS_DSP_CFG		63
+#define RST_BUS_DSP_DBG		64
+#define RST_BUS_RISCV_CFG	65
+
+#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 11/17] sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (9 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 12/17] sunxi: clock: support D1/R528 PLL6 clock Andre Przywara
                   ` (6 subsequent siblings)
  17 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL.
Just enable that when we program that PLL.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h |  1 +
 arch/arm/mach-sunxi/clock_sun50i_h6.c             | 12 +++++++-----
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 37df4410eaa..9895c2c220e 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -228,6 +228,7 @@ struct sunxi_ccm_reg {
 
 /* pll1 bit field */
 #define CCM_PLL1_CTRL_EN		BIT(31)
+#define CCM_PLL1_LDO_EN			BIT(30)
 #define CCM_PLL1_LOCK_EN		BIT(29)
 #define CCM_PLL1_LOCK			BIT(28)
 #define CCM_PLL1_OUT_EN			BIT(27)
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 7926394cf76..90110eab101 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -86,11 +86,13 @@ void clock_set_pll1(unsigned int clk)
 	writel(val, &ccm->cpu_axi_cfg);
 
 	/* clk = 24*n/p, p is ignored if clock is >288MHz */
-	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 |
-#ifdef CONFIG_MACH_SUN50I_H616
-	       CCM_PLL1_OUT_EN |
-#endif
-	       CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg);
+	val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2;
+	val |= CCM_PLL1_CTRL_N(clk / 24000000);
+	if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
+	       val |= CCM_PLL1_OUT_EN;
+	if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
+	       val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN;
+	writel(val, &ccm->pll1_cfg);
 	while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
 
 	/* Switch CPU to PLL1 */
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 12/17] sunxi: clock: support D1/R528 PLL6 clock
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (10 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 11/17] sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support Andre Przywara
                   ` (5 subsequent siblings)
  17 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

The PLL_PERIPH0 clock changed a bit in the D1/R528/T113s SoCs: there is
new P0 divider at bits [18:16], and the M divider is 1.

Add code to support this version of "PLL6".

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../include/asm/arch-sunxi/clock_sun50i_h6.h  |  2 ++
 arch/arm/mach-sunxi/clock_sun50i_h6.c         | 24 +++++++++++++------
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 9895c2c220e..8471e11aa02 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -249,6 +249,8 @@ struct sunxi_ccm_reg {
 #define CCM_PLL6_CTRL_EN		BIT(31)
 #define CCM_PLL6_LOCK_EN		BIT(29)
 #define CCM_PLL6_LOCK			BIT(28)
+#define CCM_PLL6_CTRL_P0_SHIFT		16
+#define CCM_PLL6_CTRL_P0_MASK		(0x7 << CCM_PLL6_CTRL_P0_SHIFT)
 #define CCM_PLL6_CTRL_N_SHIFT		8
 #define CCM_PLL6_CTRL_N_MASK		(0xff << CCM_PLL6_CTRL_N_SHIFT)
 #define CCM_PLL6_CTRL_DIV1_SHIFT	0
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 90110eab101..607efe6a9c1 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -107,16 +107,26 @@ unsigned int clock_get_pll6(void)
 {
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2;
-
 	uint32_t rval = readl(&ccm->pll6_cfg);
 	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
-	int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
-			CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
 	int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
-			CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
-	/* The register defines PLL6-2X or PLL6-4X, not plain PLL6 */
-	return 24000000 / m * n / div1 / div2;
+		    CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
+	int div1, m;
+
+	if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
+		div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >>
+			CCM_PLL6_CTRL_P0_SHIFT) + 1;
+		m = 1;
+	} else {
+		div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
+			CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
+		if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+			m = 4;
+		else
+			m = 2;
+	}
+
+	return 24000000U * n / m / div1 / div2;
 }
 
 int clock_twi_onoff(int port, int state)
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (11 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 12/17] sunxi: clock: support D1/R528 PLL6 clock Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2023-05-16  2:52   ` Sam Edwards
  2022-12-06  0:45 ` [RFC PATCH 14/17] sunxi: refactor serial base addresses to avoid asm/arch/cpu.h Andre Przywara
                   ` (4 subsequent siblings)
  17 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).

This adds the new Kconfig stanza, using the two newly introduced symbols
for the new SoC generation and pincontroller. It also adds the new symbols
to the relavent code places, to set all the hardcoded bits directly.

We just chicken out the DRAM controller code for now with a stub to make
it compile. There is GPLed code out there that can be used, although that
still looks very much like the disassembly/decompile it came from.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../arm/include/asm/arch-sunxi/clock_sun50i_h6.h |  5 +++++
 arch/arm/mach-sunxi/Kconfig                      | 16 ++++++++++++++++
 arch/arm/mach-sunxi/board.c                      |  4 ++++
 arch/arm/mach-sunxi/clock_sun50i_h6.c            |  2 ++
 arch/arm/mach-sunxi/cpu_info.c                   |  2 ++
 board/sunxi/Makefile                             |  1 +
 board/sunxi/dram_sun8i_r528.c                    |  9 +++++++++
 drivers/mmc/sunxi_mmc.c                          |  1 +
 drivers/pinctrl/sunxi/Kconfig                    |  1 +
 9 files changed, 41 insertions(+)
 create mode 100644 board/sunxi/dram_sun8i_r528.c

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 8471e11aa02..d34a9baf5e1 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -288,6 +288,11 @@ struct sunxi_ccm_reg {
 
 /* apb1 bit field */
 #define CCM_APB1_DEFAULT		0x03000102
+#elif CONFIG_MACH_SUN8I_R528
+#define CCM_PLL6_DEFAULT		0xe8216300
+#define CCM_PSI_AHB1_AHB2_DEFAULT	0x03000002
+//#define CCM_AHB3_DEFAULT		0x03000002
+#define CCM_APB1_DEFAULT		0x03000102
 #endif
 
 /* apb2 bit field */
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index b59db212fa8..71799686a05 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -51,6 +51,12 @@ config DRAM_SUN50I_H616
 	  Select this dram controller driver for some sun50i platforms,
 	  like H616.
 
+config DRAM_SUN8I_R528
+	bool
+	help
+	  Select this DRAM controller driver for the R528, T113, D1
+	  and D1s/F133 SoC.
+
 if DRAM_SUN50I_H616
 config DRAM_SUN50I_H616_WRITE_LEVELING
 	bool "H616 DRAM write leveling"
@@ -318,6 +324,15 @@ config MACH_SUN8I_R40
 	select PHY_SUN4I_USB
 	imply SPL_SYS_I2C_LEGACY
 
+config MACH_SUN8I_R528
+	bool "sun8i (Allwinner R528)"
+	select CPU_V7A
+	select SUNXI_GEN_NCAT2
+	select SUNXI_NEW_PINCTRL
+	select MMC_SUNXI_HAS_NEW_MODE
+	select SUPPORT_SPL
+	select DRAM_SUN8I_R528
+
 config MACH_SUN8I_V3S
 	bool "sun8i (Allwinner V3/V3s/S3/S3L)"
 	select CPU_V7A
@@ -622,6 +637,7 @@ config SYS_CONFIG_NAME
 	default "sun6i" if MACH_SUN6I
 	default "sun7i" if MACH_SUN7I
 	default "sun8i" if MACH_SUN8I
+	default "sun8i" if MACH_SUN8I_R528
 	default "sun9i" if MACH_SUN9I
 	default "sun50i" if MACH_SUN50I
 	default "sun50i" if MACH_SUN50I_H6
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 3763ec3d2e4..33331cda5e2 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -148,6 +148,10 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528)
+	sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6);
+	sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6);
+	sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 607efe6a9c1..4d5e23a9af4 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -38,7 +38,9 @@ void clock_init_safe(void)
 			CCM_CPU_AXI_DEFAULT_FACTORS);
 
 	writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg);
+#ifdef CCM_AHB3_DEFAULT
 	writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg);
+#endif
 	writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);
 
 	/*
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index 7eef178859b..7fecc3b88dd 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -93,6 +93,8 @@ int print_cpuinfo(void)
 	printf("CPU:   Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN8I_V3S
 	printf("CPU:   Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_R528
+	puts("CPU:   Allwinner R528 (SUN8I)\n");
 #elif defined CONFIG_MACH_SUN9I
 	puts("CPU:   Allwinner A80 (SUN9I)\n");
 #elif defined CONFIG_MACH_SUN50I
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 7763b032c80..db16cf247c6 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_SUN7I_GMAC)	+= gmac.o
 obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i_auto.o
 obj-$(CONFIG_MACH_SUN5I)	+= dram_sun5i_auto.o
 obj-$(CONFIG_MACH_SUN7I)	+= dram_sun5i_auto.o
+obj-$(CONFIG_DRAM_SUN8I_R528)	+= dram_sun8i_r528.o
 obj-$(CONFIG_CHIP_DIP_SCAN)	+= chip.o
diff --git a/board/sunxi/dram_sun8i_r528.c b/board/sunxi/dram_sun8i_r528.c
new file mode 100644
index 00000000000..84261df1cd8
--- /dev/null
+++ b/board/sunxi/dram_sun8i_r528.c
@@ -0,0 +1,9 @@
+/*
+ * Quick hack to make it compile, we cannot use the SPL just yet.
+ * There is GPLed DRAM code in awboot, to be lifted here, after some
+ * massaging.
+ */
+unsigned long sunxi_dram_init(void)
+{
+	return 128 * 1024 * 1024;
+}
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 6ce2729473c..59b1bbd4a9c 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -736,6 +736,7 @@ static const struct udevice_id sunxi_mmc_ids[] = {
 	{ .compatible = "allwinner,sun50i-h6-emmc" },
 	{ .compatible = "allwinner,sun50i-a100-mmc" },
 	{ .compatible = "allwinner,sun50i-a100-emmc" },
+	{ .compatible = "allwinner,sun20i-d1-mmc" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index c8f937d91e9..cbd61795986 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -126,6 +126,7 @@ config PINCTRL_SUN50I_H616_R
 
 config PINCTRL_SUN20I_D1
 	bool "Support for the Allwinner D1/R528 PIO"
+	default MACH_SUN8I_R528
 	select PINCTRL_SUNXI
 
 endif
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 14/17] sunxi: refactor serial base addresses to avoid asm/arch/cpu.h
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (12 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 15/17] riscv: dts: allwinner: Add the D1/D1s SoC devicetree Andre Przywara
                   ` (3 subsequent siblings)
  17 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

At the moment we have each SoC's memory map defined in its own cpu.h,
which is included in include/configs/sunxi_common.h. This will be a
problem with the introduction of Allwinner RISC-V support.

Remove the inclusion of that header file from the common config header,
instead move the required serial base addresses (for the SPL) into a
separate header file. Then include the original cpu.h file only where
we really need it, which is only under arch/arm now.

This disentangles the architecture specific header files from the
generic code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/cpu/armv7/sunxi/sram.c               |  1 +
 arch/arm/cpu/armv8/fel_utils.S                |  1 +
 arch/arm/include/asm/arch-sunxi/clock.h       |  1 +
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h   | 15 ---------
 .../include/asm/arch-sunxi/cpu_sun50i_h6.h    |  5 ---
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |  7 ----
 .../include/asm/arch-sunxi/cpu_sunxi_ncat2.h  |  5 ---
 arch/arm/include/asm/arch-sunxi/serial.h      | 32 +++++++++++++++++++
 arch/arm/mach-sunxi/gtbus_sun9i.c             |  1 +
 arch/arm/mach-sunxi/timer.c                   |  1 +
 include/configs/sunxi-common.h                |  2 +-
 11 files changed, 38 insertions(+), 33 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/serial.h

diff --git a/arch/arm/cpu/armv7/sunxi/sram.c b/arch/arm/cpu/armv7/sunxi/sram.c
index 28564c2846a..28ff6a1b7c2 100644
--- a/arch/arm/cpu/armv7/sunxi/sram.c
+++ b/arch/arm/cpu/armv7/sunxi/sram.c
@@ -12,6 +12,7 @@
 #include <common.h>
 #include <init.h>
 #include <asm/io.h>
+#include <asm/arch/cpu.h>
 
 void sunxi_sram_init(void)
 {
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index 5266515f145..9b1d55bb31a 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -10,6 +10,7 @@
 #include <config.h>
 #include <asm/system.h>
 #include <linux/linkage.h>
+#include <asm/arch/cpu.h>
 
 /*
  * We don't overwrite save_boot_params() here, to save the FEL state upon
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 3d34261b0e5..fcc8966cb0b 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -9,6 +9,7 @@
 #define _SUNXI_CLOCK_H
 
 #include <linux/types.h>
+#include <asm/arch/cpu.h>
 
 #define CLK_GATE_OPEN			0x1
 #define CLK_GATE_CLOSE			0x0
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index d6fe51f24bc..3daee2f574a 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -128,20 +128,6 @@ defined(CONFIG_MACH_SUN50I)
 #define SUNXI_CPUCFG_BASE		0x01c25c00
 #endif
 
-#ifdef CONFIG_MACH_SUNIV
-#define SUNXI_UART0_BASE		0x01c25000
-#define SUNXI_UART1_BASE		0x01c25400
-#define SUNXI_UART2_BASE		0x01c25800
-#else
-#define SUNXI_UART0_BASE		0x01c28000
-#define SUNXI_UART1_BASE		0x01c28400
-#define SUNXI_UART2_BASE		0x01c28800
-#endif
-#define SUNXI_UART3_BASE		0x01c28c00
-#define SUNXI_UART4_BASE		0x01c29000
-#define SUNXI_UART5_BASE		0x01c29400
-#define SUNXI_UART6_BASE		0x01c29800
-#define SUNXI_UART7_BASE		0x01c29c00
 #define SUNXI_PS2_0_BASE		0x01c2a000
 #define SUNXI_PS2_1_BASE		0x01c2a400
 
@@ -208,7 +194,6 @@ defined(CONFIG_MACH_SUN50I)
 #endif
 
 #define SUNXI_R_TWI_BASE		0x01f02400
-#define SUNXI_R_UART_BASE		0x01f02800
 #define SUN6I_P2WI_BASE			0x01f03400
 #define SUNXI_RSB_BASE			0x01f03400
 
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
index 9b6bf843601..15ee092d358 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
@@ -42,10 +42,6 @@
 #define SUNXI_DRAM_PHY0_BASE		0x04800000
 #endif
 
-#define SUNXI_UART0_BASE		0x05000000
-#define SUNXI_UART1_BASE		0x05000400
-#define SUNXI_UART2_BASE		0x05000800
-#define SUNXI_UART3_BASE		0x05000C00
 #define SUNXI_TWI0_BASE			0x05002000
 #define SUNXI_TWI1_BASE			0x05002400
 #define SUNXI_TWI2_BASE			0x05002800
@@ -67,7 +63,6 @@
 #define SUNXI_R_CPUCFG_BASE		0x07000400
 #define SUNXI_PRCM_BASE			0x07010000
 #define SUNXI_R_WDOG_BASE		0x07020400
-#define SUNXI_R_UART_BASE		0x07080000
 #define SUNXI_R_TWI_BASE		0x07081400
 
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index 20025be2319..2bf2675d5c1 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -86,12 +86,6 @@
 #define SUNXI_LRADC_BASE		(REGS_APB0_BASE + 0x1800)
 
 /* APB1 Module */
-#define SUNXI_UART0_BASE		(REGS_APB1_BASE + 0x0000)
-#define SUNXI_UART1_BASE		(REGS_APB1_BASE + 0x0400)
-#define SUNXI_UART2_BASE		(REGS_APB1_BASE + 0x0800)
-#define SUNXI_UART3_BASE		(REGS_APB1_BASE + 0x0C00)
-#define SUNXI_UART4_BASE		(REGS_APB1_BASE + 0x1000)
-#define SUNXI_UART5_BASE		(REGS_APB1_BASE + 0x1400)
 #define SUNXI_TWI0_BASE			(REGS_APB1_BASE + 0x2800)
 #define SUNXI_TWI1_BASE			(REGS_APB1_BASE + 0x2C00)
 #define SUNXI_TWI2_BASE			(REGS_APB1_BASE + 0x3000)
@@ -100,7 +94,6 @@
 
 /* RCPUS Module */
 #define SUNXI_PRCM_BASE			(REGS_RCPUS_BASE + 0x1400)
-#define SUNXI_R_UART_BASE		(REGS_RCPUS_BASE + 0x2800)
 #define SUNXI_RSB_BASE			(REGS_RCPUS_BASE + 0x3400)
 
 /* Misc. */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
index 13093085a5e..d01508517c3 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
@@ -27,10 +27,6 @@
 #define SUNXI_MMC1_BASE			0x04021000
 #define SUNXI_MMC2_BASE			0x04022000
 
-#define SUNXI_UART0_BASE		0x02500000
-#define SUNXI_UART1_BASE		0x02500400
-#define SUNXI_UART2_BASE		0x02500800
-#define SUNXI_UART3_BASE		0x02500C00
 #define SUNXI_TWI0_BASE			0x02502000
 #define SUNXI_TWI1_BASE			0x02502400
 #define SUNXI_TWI2_BASE			0x02502800
@@ -42,7 +38,6 @@
 #define SUNXI_R_CPUCFG_BASE		0x07000400
 #define SUNXI_PRCM_BASE			0x07010000
 #define SUNXI_R_WDOG_BASE		0x07020400
-#define SUNXI_R_UART_BASE		0x07080000
 #define SUNXI_R_TWI_BASE		0x07081400
 
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/arch-sunxi/serial.h b/arch/arm/include/asm/arch-sunxi/serial.h
new file mode 100644
index 00000000000..9386287b65e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/serial.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  hardcoded UART base addresses for early SPL use
+ *
+ *  Copyright (c) 2022  Arm Ltd.
+ */
+
+#ifndef SUNXI_SERIAL_MEMMAP_H
+#define SUNXI_SERIAL_MEMMAP_H
+
+#if defined(CONFIG_MACH_SUN9I)
+#define SUNXI_UART0_BASE		0x07000000
+#define SUNXI_R_UART_BASE		0x08002800
+#elif defined(CONFIG_SUN50I_GEN_H6)
+#define SUNXI_UART0_BASE		0x05000000
+#define SUNXI_R_UART_BASE		0x07080000
+#elif defined(CONFIG_MACH_SUNIV)
+#define SUNXI_UART0_BASE		0x01c25000
+#define SUNXI_R_UART_BASE		0
+#elif defined(CONFIG_SUNXI_GEN_NCAT2)
+#define SUNXI_UART0_BASE		0x02500000
+#define SUNXI_R_UART_BASE		0		// 0x07080000 (?>
+#else
+#define SUNXI_UART0_BASE		0x01c28000
+#define SUNXI_R_UART_BASE		0x01f02800
+#endif
+
+#define SUNXI_UART1_BASE		(SUNXI_UART0_BASE + 0x400)
+#define SUNXI_UART2_BASE		(SUNXI_UART0_BASE + 0x800)
+#define SUNXI_UART3_BASE		(SUNXI_UART0_BASE + 0xc00)
+
+#endif /* SUNXI_SERIAL_MEMMAP_H */
diff --git a/arch/arm/mach-sunxi/gtbus_sun9i.c b/arch/arm/mach-sunxi/gtbus_sun9i.c
index cf011c4cfa7..5624621b500 100644
--- a/arch/arm/mach-sunxi/gtbus_sun9i.c
+++ b/arch/arm/mach-sunxi/gtbus_sun9i.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/gtbus_sun9i.h>
 #include <asm/arch/sys_proto.h>
 
diff --git a/arch/arm/mach-sunxi/timer.c b/arch/arm/mach-sunxi/timer.c
index fc9d419a25e..9a6f6c06d8c 100644
--- a/arch/arm/mach-sunxi/timer.c
+++ b/arch/arm/mach-sunxi/timer.c
@@ -10,6 +10,7 @@
 #include <time.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/timer.h>
 #include <linux/delay.h>
 
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 720768629d6..d594e9aaf88 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -12,7 +12,6 @@
 #ifndef _SUNXI_COMMON_CONFIG_H
 #define _SUNXI_COMMON_CONFIG_H
 
-#include <asm/arch/cpu.h>
 #include <linux/stringify.h>
 
 /* Serial & console */
@@ -25,6 +24,7 @@
 #define CONFIG_SYS_NS16550_CLK		24000000
 #endif
 #ifndef CONFIG_DM_SERIAL
+#include <asm/arch/serial.h>
 # define CONFIG_SYS_NS16550_REG_SIZE	-4
 # define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
 # define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 15/17] riscv: dts: allwinner: Add the D1/D1s SoC devicetree
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (13 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 14/17] sunxi: refactor serial base addresses to avoid asm/arch/cpu.h Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-06  0:45 ` [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub Andre Przywara
                   ` (2 subsequent siblings)
  17 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

From: Samuel Holland <samuel@sholland.org>

D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
on a single die, or at a pair of dies derived from the same design.

D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
variants.

Because the original design supported both ARM and RISC-V CPUs, some
peripherals are duplicated. In addition, all variants except D1s contain
a HiFi 4 DSP with its own set of peripherals.

The devicetrees are organized to minimize duplication:
 - Common perhiperals are described in sunxi-d1s-t113.dtsi
 - DSP-related peripherals are described in sunxi-d1-t113.dtsi
 - RISC-V specific hardware is described in sun20i-d1s.dtsi
 - Functionality unique to the D1 variant is described in sun20i-d1.dtsi

The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 arch/riscv/dts/sun20i-d1.dtsi               |  66 ++
 arch/riscv/dts/sun20i-d1s.dtsi              |  76 ++
 arch/riscv/dts/sunxi-d1-t113.dtsi           |  15 +
 arch/riscv/dts/sunxi-d1s-t113.dtsi          | 844 ++++++++++++++++++++
 include/dt-bindings/clock/sun20i-d1-r-ccu.h |  19 +
 include/dt-bindings/reset/sun20i-d1-r-ccu.h |  16 +
 6 files changed, 1036 insertions(+)
 create mode 100644 arch/riscv/dts/sun20i-d1.dtsi
 create mode 100644 arch/riscv/dts/sun20i-d1s.dtsi
 create mode 100644 arch/riscv/dts/sunxi-d1-t113.dtsi
 create mode 100644 arch/riscv/dts/sunxi-d1s-t113.dtsi
 create mode 100644 include/dt-bindings/clock/sun20i-d1-r-ccu.h
 create mode 100644 include/dt-bindings/reset/sun20i-d1-r-ccu.h

diff --git a/arch/riscv/dts/sun20i-d1.dtsi b/arch/riscv/dts/sun20i-d1.dtsi
new file mode 100644
index 00000000000..97e7cbb3259
--- /dev/null
+++ b/arch/riscv/dts/sun20i-d1.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
+
+#include "sun20i-d1s.dtsi"
+#include "sunxi-d1-t113.dtsi"
+
+/ {
+	soc {
+		lradc: keys@2009800 {
+			compatible = "allwinner,sun20i-d1-lradc",
+				     "allwinner,sun50i-r329-lradc";
+			reg = <0x2009800 0x400>;
+			interrupts = <SOC_PERIPHERAL_IRQ(61) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_LRADC>;
+			resets = <&ccu RST_BUS_LRADC>;
+			status = "disabled";
+		};
+
+		i2s0: i2s@2032000 {
+			compatible = "allwinner,sun20i-d1-i2s",
+				     "allwinner,sun50i-r329-i2s";
+			reg = <0x2032000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(26) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2S0>,
+				 <&ccu CLK_I2S0>;
+			clock-names = "apb", "mod";
+			resets = <&ccu RST_BUS_I2S0>;
+			dmas = <&dma 3>, <&dma 3>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#sound-dai-cells = <0>;
+		};
+	};
+};
+
+&pio {
+	/omit-if-no-ref/
+	dmic_pb11_d0_pin: dmic-pb11-d0-pin {
+		pins = "PB11";
+		function = "dmic";
+	};
+
+	/omit-if-no-ref/
+	dmic_pe17_clk_pin: dmic-pe17-clk-pin {
+		pins = "PE17";
+		function = "dmic";
+	};
+
+	/omit-if-no-ref/
+	i2c0_pb10_pins: i2c0-pb10-pins {
+		pins = "PB10", "PB11";
+		function = "i2c0";
+	};
+
+	/omit-if-no-ref/
+	i2c2_pb0_pins: i2c2-pb0-pins {
+		pins = "PB0", "PB1";
+		function = "i2c2";
+	};
+
+	/omit-if-no-ref/
+	uart0_pb8_pins: uart0-pb8-pins {
+		pins = "PB8", "PB9";
+		function = "uart0";
+	};
+};
diff --git a/arch/riscv/dts/sun20i-d1s.dtsi b/arch/riscv/dts/sun20i-d1s.dtsi
new file mode 100644
index 00000000000..859509832d5
--- /dev/null
+++ b/arch/riscv/dts/sun20i-d1s.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
+
+#define SOC_PERIPHERAL_IRQ(nr)	(nr + 16)
+
+#include "sunxi-d1s-t113.dtsi"
+
+/ {
+	cpus {
+		timebase-frequency = <24000000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "thead,c906", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			clocks = <&ccu CLK_RISCV>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <32768>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			mmu-type = "riscv,sv39";
+			operating-points-v2 = <&opp_table_cpu>;
+			riscv,isa = "rv64imafdc";
+			#cooling-cells = <2>;
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+	};
+
+	opp_table_cpu: opp-table-cpu {
+		compatible = "operating-points-v2";
+
+		opp-408000000 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <900000 900000 1100000>;
+		};
+
+		opp-1080000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <900000 900000 1100000>;
+		};
+	};
+
+	soc {
+		interrupt-parent = <&plic>;
+
+		riscv_wdt: watchdog@6011000 {
+			compatible = "allwinner,sun20i-d1-wdt";
+			reg = <0x6011000 0x20>;
+			interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dcxo>, <&rtc CLK_OSC32K>;
+			clock-names = "hosc", "losc";
+		};
+
+		plic: interrupt-controller@10000000 {
+			compatible = "allwinner,sun20i-d1-plic",
+				     "thead,c900-plic";
+			reg = <0x10000000 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>,
+					      <&cpu0_intc 9>;
+			interrupt-controller;
+			riscv,ndev = <176>;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/arch/riscv/dts/sunxi-d1-t113.dtsi b/arch/riscv/dts/sunxi-d1-t113.dtsi
new file mode 100644
index 00000000000..b7156123df5
--- /dev/null
+++ b/arch/riscv/dts/sunxi-d1-t113.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
+
+/ {
+	soc {
+		dsp_wdt: watchdog@1700400 {
+			compatible = "allwinner,sun20i-d1-wdt";
+			reg = <0x1700400 0x20>;
+			interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dcxo>, <&rtc CLK_OSC32K>;
+			clock-names = "hosc", "losc";
+			status = "reserved";
+		};
+	};
+};
diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi
new file mode 100644
index 00000000000..c8815cbf0b4
--- /dev/null
+++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi
@@ -0,0 +1,844 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
+
+#include <dt-bindings/clock/sun6i-rtc.h>
+#include <dt-bindings/clock/sun8i-de2.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
+#include <dt-bindings/clock/sun20i-d1-ccu.h>
+#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/reset/sun20i-d1-ccu.h>
+#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	dcxo: dcxo-clk {
+		compatible = "fixed-clock";
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+		clock-output-names = "dcxo";
+		#clock-cells = <0>;
+	};
+
+	de: display-engine {
+		compatible = "allwinner,sun20i-d1-display-engine";
+		allwinner,pipelines = <&mixer0>, <&mixer1>;
+		status = "disabled";
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		dma-noncoherent;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pio: pinctrl@2000000 {
+			compatible = "allwinner,sun20i-d1-pinctrl";
+			reg = <0x2000000 0x800>;
+			interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>,
+				     <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>,
+				     <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>,
+				     <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>,
+				     <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>,
+				     <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_APB0>,
+				 <&dcxo>,
+				 <&rtc CLK_OSC32K>;
+			clock-names = "apb", "hosc", "losc";
+			gpio-controller;
+			interrupt-controller;
+			#gpio-cells = <3>;
+			#interrupt-cells = <3>;
+
+			/omit-if-no-ref/
+			clk_pg11_pin: clk-pg11-pin {
+				pins = "PG11";
+				function = "clk";
+			};
+
+			/omit-if-no-ref/
+			dsi_4lane_pins: dsi-4lane-pins {
+				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+				       "PD6", "PD7", "PD8", "PD9";
+				drive-strength = <30>;
+				function = "dsi";
+			};
+
+			/omit-if-no-ref/
+			lcd_rgb666_pins: lcd-rgb666-pins {
+				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+				       "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
+				       "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
+				       "PD18", "PD19", "PD20", "PD21";
+				function = "lcd0";
+			};
+
+			/omit-if-no-ref/
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+				function = "mmc0";
+			};
+
+			/omit-if-no-ref/
+			mmc1_pins: mmc1-pins {
+				pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
+				function = "mmc1";
+			};
+
+			/omit-if-no-ref/
+			mmc2_pins: mmc2-pins {
+				pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
+				function = "mmc2";
+			};
+
+			/omit-if-no-ref/
+			rgmii_pe_pins: rgmii-pe-pins {
+				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+				       "PE5", "PE6", "PE7", "PE8", "PE9",
+				       "PE11", "PE12", "PE13", "PE14", "PE15";
+				function = "emac";
+			};
+
+			/omit-if-no-ref/
+			rmii_pe_pins: rmii-pe-pins {
+				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+				       "PE5", "PE6", "PE7", "PE8", "PE9";
+				function = "emac";
+			};
+
+			/omit-if-no-ref/
+			uart1_pg6_pins: uart1-pg6-pins {
+				pins = "PG6", "PG7";
+				function = "uart1";
+			};
+
+			/omit-if-no-ref/
+			uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
+				pins = "PG8", "PG9";
+				function = "uart1";
+			};
+
+			/omit-if-no-ref/
+			uart3_pb_pins: uart3-pb-pins {
+				pins = "PB6", "PB7";
+				function = "uart3";
+			};
+		};
+
+		ccu: clock-controller@2001000 {
+			compatible = "allwinner,sun20i-d1-ccu";
+			reg = <0x2001000 0x1000>;
+			clocks = <&dcxo>,
+				 <&rtc CLK_OSC32K>,
+				 <&rtc CLK_IOSC>;
+			clock-names = "hosc", "losc", "iosc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		dmic: dmic@2031000 {
+			compatible = "allwinner,sun20i-d1-dmic",
+				     "allwinner,sun50i-h6-dmic";
+			reg = <0x2031000 0x400>;
+			interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_DMIC>,
+				 <&ccu CLK_DMIC>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_DMIC>;
+			dmas = <&dma 8>;
+			dma-names = "rx";
+			status = "disabled";
+			#sound-dai-cells = <0>;
+		};
+
+		i2s1: i2s@2033000 {
+			compatible = "allwinner,sun20i-d1-i2s",
+				     "allwinner,sun50i-r329-i2s";
+			reg = <0x2033000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2S1>,
+				 <&ccu CLK_I2S1>;
+			clock-names = "apb", "mod";
+			resets = <&ccu RST_BUS_I2S1>;
+			dmas = <&dma 4>, <&dma 4>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#sound-dai-cells = <0>;
+		};
+
+		i2s2: i2s@2034000 {
+			compatible = "allwinner,sun20i-d1-i2s",
+				     "allwinner,sun50i-r329-i2s";
+			reg = <0x2034000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2S2>,
+				 <&ccu CLK_I2S2>;
+			clock-names = "apb", "mod";
+			resets = <&ccu RST_BUS_I2S2>;
+			dmas = <&dma 5>, <&dma 5>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#sound-dai-cells = <0>;
+		};
+
+		timer: timer@2050000 {
+			compatible = "allwinner,sun20i-d1-timer",
+				     "allwinner,sun8i-a23-timer";
+			reg = <0x2050000 0xa0>;
+			interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>,
+				     <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dcxo>;
+		};
+
+		wdt: watchdog@20500a0 {
+			compatible = "allwinner,sun20i-d1-wdt-reset",
+				     "allwinner,sun20i-d1-wdt";
+			reg = <0x20500a0 0x20>;
+			interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dcxo>, <&rtc CLK_OSC32K>;
+			clock-names = "hosc", "losc";
+			status = "reserved";
+		};
+
+		uart0: serial@2500000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x2500000 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_UART0>;
+			resets = <&ccu RST_BUS_UART0>;
+			dmas = <&dma 14>, <&dma 14>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		uart1: serial@2500400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x2500400 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_UART1>;
+			resets = <&ccu RST_BUS_UART1>;
+			dmas = <&dma 15>, <&dma 15>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		uart2: serial@2500800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x2500800 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_UART2>;
+			resets = <&ccu RST_BUS_UART2>;
+			dmas = <&dma 16>, <&dma 16>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		uart3: serial@2500c00 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x2500c00 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_UART3>;
+			resets = <&ccu RST_BUS_UART3>;
+			dmas = <&dma 17>, <&dma 17>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		uart4: serial@2501000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x2501000 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_UART4>;
+			resets = <&ccu RST_BUS_UART4>;
+			dmas = <&dma 18>, <&dma 18>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		uart5: serial@2501400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x2501400 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_UART5>;
+			resets = <&ccu RST_BUS_UART5>;
+			dmas = <&dma 19>, <&dma 19>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		i2c0: i2c@2502000 {
+			compatible = "allwinner,sun20i-d1-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x2502000 0x400>;
+			interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C0>;
+			resets = <&ccu RST_BUS_I2C0>;
+			dmas = <&dma 43>, <&dma 43>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@2502400 {
+			compatible = "allwinner,sun20i-d1-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x2502400 0x400>;
+			interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C1>;
+			resets = <&ccu RST_BUS_I2C1>;
+			dmas = <&dma 44>, <&dma 44>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@2502800 {
+			compatible = "allwinner,sun20i-d1-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x2502800 0x400>;
+			interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C2>;
+			resets = <&ccu RST_BUS_I2C2>;
+			dmas = <&dma 45>, <&dma 45>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@2502c00 {
+			compatible = "allwinner,sun20i-d1-i2c",
+				     "allwinner,sun8i-v536-i2c",
+				     "allwinner,sun6i-a31-i2c";
+			reg = <0x2502c00 0x400>;
+			interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C3>;
+			resets = <&ccu RST_BUS_I2C3>;
+			dmas = <&dma 46>, <&dma 46>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		syscon: syscon@3000000 {
+			compatible = "allwinner,sun20i-d1-system-control";
+			reg = <0x3000000 0x1000>;
+			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			regulators@3000150 {
+				compatible = "allwinner,sun20i-d1-system-ldos";
+				reg = <0x3000150 0x4>;
+
+				reg_ldoa: ldoa {
+				};
+
+				reg_ldob: ldob {
+				};
+			};
+		};
+
+		dma: dma-controller@3002000 {
+			compatible = "allwinner,sun20i-d1-dma";
+			reg = <0x3002000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
+			clock-names = "bus", "mbus";
+			resets = <&ccu RST_BUS_DMA>;
+			dma-channels = <16>;
+			dma-requests = <48>;
+			#dma-cells = <1>;
+		};
+
+		sid: efuse@3006000 {
+			compatible = "allwinner,sun20i-d1-sid";
+			reg = <0x3006000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		mbus: dram-controller@3102000 {
+			compatible = "allwinner,sun20i-d1-mbus";
+			reg = <0x3102000 0x1000>,
+			      <0x3103000 0x1000>;
+			reg-names = "mbus", "dram";
+			interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_MBUS>,
+				 <&ccu CLK_DRAM>,
+				 <&ccu CLK_BUS_DRAM>;
+			clock-names = "mbus", "dram", "bus";
+			dma-ranges = <0 0x40000000 0x80000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#interconnect-cells = <1>;
+		};
+
+		mmc0: mmc@4020000 {
+			compatible = "allwinner,sun20i-d1-mmc";
+			reg = <0x4020000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC0>;
+			reset-names = "ahb";
+			cap-sd-highspeed;
+			max-frequency = <150000000>;
+			no-mmc;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc@4021000 {
+			compatible = "allwinner,sun20i-d1-mmc";
+			reg = <0x4021000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC1>;
+			reset-names = "ahb";
+			cap-sd-highspeed;
+			max-frequency = <150000000>;
+			no-mmc;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc2: mmc@4022000 {
+			compatible = "allwinner,sun20i-d1-emmc",
+				     "allwinner,sun50i-a100-emmc";
+			reg = <0x4022000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC2>;
+			reset-names = "ahb";
+			cap-mmc-highspeed;
+			max-frequency = <150000000>;
+			mmc-ddr-1_8v;
+			mmc-ddr-3_3v;
+			no-sd;
+			no-sdio;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		usb_otg: usb@4100000 {
+			compatible = "allwinner,sun20i-d1-musb",
+				     "allwinner,sun8i-a33-musb";
+			reg = <0x4100000 0x400>;
+			interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			extcon = <&usbphy 0>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		usbphy: phy@4100400 {
+			compatible = "allwinner,sun20i-d1-usb-phy";
+			reg = <0x4100400 0x100>,
+			      <0x4101800 0x100>,
+			      <0x4200800 0x100>;
+			reg-names = "phy_ctrl",
+				    "pmu0",
+				    "pmu1";
+			clocks = <&dcxo>,
+				 <&dcxo>;
+			clock-names = "usb0_phy",
+				      "usb1_phy";
+			resets = <&ccu RST_USB_PHY0>,
+				 <&ccu RST_USB_PHY1>;
+			reset-names = "usb0_reset",
+				      "usb1_reset";
+			status = "disabled";
+			#phy-cells = <1>;
+		};
+
+		ehci0: usb@4101000 {
+			compatible = "allwinner,sun20i-d1-ehci",
+				     "generic-ehci";
+			reg = <0x4101000 0x100>;
+			interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_BUS_EHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>,
+				 <&ccu RST_BUS_EHCI0>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci0: usb@4101400 {
+			compatible = "allwinner,sun20i-d1-ohci",
+				     "generic-ohci";
+			reg = <0x4101400 0x100>;
+			interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ehci1: usb@4200000 {
+			compatible = "allwinner,sun20i-d1-ehci",
+				     "generic-ehci";
+			reg = <0x4200000 0x100>;
+			interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI1>,
+				 <&ccu CLK_BUS_EHCI1>,
+				 <&ccu CLK_USB_OHCI1>;
+			resets = <&ccu RST_BUS_OHCI1>,
+				 <&ccu RST_BUS_EHCI1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci1: usb@4200400 {
+			compatible = "allwinner,sun20i-d1-ohci",
+				     "generic-ohci";
+			reg = <0x4200400 0x100>;
+			interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI1>,
+				 <&ccu CLK_USB_OHCI1>;
+			resets = <&ccu RST_BUS_OHCI1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		emac: ethernet@4500000 {
+			compatible = "allwinner,sun20i-d1-emac",
+				     "allwinner,sun50i-a64-emac";
+			reg = <0x4500000 0x10000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks = <&ccu CLK_BUS_EMAC>;
+			clock-names = "stmmaceth";
+			resets = <&ccu RST_BUS_EMAC>;
+			reset-names = "stmmaceth";
+			syscon = <&syscon>;
+			status = "disabled";
+
+			mdio: mdio {
+				compatible = "snps,dwmac-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		display_clocks: clock-controller@5000000 {
+			compatible = "allwinner,sun20i-d1-de2-clk",
+				     "allwinner,sun50i-h5-de2-clk";
+			reg = <0x5000000 0x10000>;
+			clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_DE>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		mixer0: mixer@5100000 {
+			compatible = "allwinner,sun20i-d1-de2-mixer-0";
+			reg = <0x5100000 0x100000>;
+			clocks = <&display_clocks CLK_BUS_MIXER0>,
+				 <&display_clocks CLK_MIXER0>;
+			clock-names = "bus", "mod";
+			resets = <&display_clocks RST_MIXER0>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mixer0_out: port@1 {
+					reg = <1>;
+
+					mixer0_out_tcon_top_mixer0: endpoint {
+						remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+					};
+				};
+			};
+		};
+
+		mixer1: mixer@5200000 {
+			compatible = "allwinner,sun20i-d1-de2-mixer-1";
+			reg = <0x5200000 0x100000>;
+			clocks = <&display_clocks CLK_BUS_MIXER1>,
+				 <&display_clocks CLK_MIXER1>;
+			clock-names = "bus", "mod";
+			resets = <&display_clocks RST_MIXER1>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mixer1_out: port@1 {
+					reg = <1>;
+
+					mixer1_out_tcon_top_mixer1: endpoint {
+						remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
+					};
+				};
+			};
+		};
+
+		dsi: dsi@5450000 {
+			compatible = "allwinner,sun20i-d1-mipi-dsi",
+				     "allwinner,sun50i-a100-mipi-dsi";
+			reg = <0x5450000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MIPI_DSI>,
+				 <&tcon_top CLK_TCON_TOP_DSI>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_MIPI_DSI>;
+			phys = <&dphy>;
+			phy-names = "dphy";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port {
+				dsi_in_tcon_lcd0: endpoint {
+					remote-endpoint = <&tcon_lcd0_out_dsi>;
+				};
+			};
+		};
+
+		dphy: phy@5451000 {
+			compatible = "allwinner,sun20i-d1-mipi-dphy",
+				     "allwinner,sun50i-a100-mipi-dphy";
+			reg = <0x5451000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MIPI_DSI>,
+				 <&ccu CLK_MIPI_DSI>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_MIPI_DSI>;
+			#phy-cells = <0>;
+		};
+
+		tcon_top: tcon-top@5460000 {
+			compatible = "allwinner,sun20i-d1-tcon-top";
+			reg = <0x5460000 0x1000>;
+			clocks = <&ccu CLK_BUS_DPSS_TOP>,
+				 <&ccu CLK_TCON_TV>,
+				 <&ccu CLK_TVE>,
+				 <&ccu CLK_TCON_LCD0>;
+			clock-names = "bus", "tcon-tv0", "tve0", "dsi";
+			clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
+			resets = <&ccu RST_BUS_DPSS_TOP>;
+			#clock-cells = <1>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon_top_mixer0_in: port@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					tcon_top_mixer0_in_mixer0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+					};
+				};
+
+				tcon_top_mixer0_out: port@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
+					};
+
+					tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
+					};
+				};
+
+				tcon_top_mixer1_in: port@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					tcon_top_mixer1_in_mixer1: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
+					};
+				};
+
+				tcon_top_mixer1_out: port@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
+					};
+
+					tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
+						reg = <2>;
+						remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
+					};
+				};
+
+				tcon_top_hdmi_in: port@4 {
+					reg = <4>;
+
+					tcon_top_hdmi_in_tcon_tv0: endpoint {
+						remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
+					};
+				};
+
+				tcon_top_hdmi_out: port@5 {
+					reg = <5>;
+				};
+			};
+		};
+
+		tcon_lcd0: lcd-controller@5461000 {
+			compatible = "allwinner,sun20i-d1-tcon-lcd";
+			reg = <0x5461000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_TCON_LCD0>,
+				 <&ccu CLK_TCON_LCD0>;
+			clock-names = "ahb", "tcon-ch0";
+			clock-output-names = "tcon-pixel-clock";
+			resets = <&ccu RST_BUS_TCON_LCD0>,
+				 <&ccu RST_BUS_LVDS0>;
+			reset-names = "lcd", "lvds";
+			#clock-cells = <0>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon_lcd0_in: port@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
+					};
+
+					tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
+					};
+				};
+
+				tcon_lcd0_out: port@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					tcon_lcd0_out_dsi: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&dsi_in_tcon_lcd0>;
+					};
+				};
+			};
+		};
+
+		tcon_tv0: lcd-controller@5470000 {
+			compatible = "allwinner,sun20i-d1-tcon-tv";
+			reg = <0x5470000 0x1000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_TCON_TV>,
+				 <&tcon_top CLK_TCON_TOP_TV0>;
+			clock-names = "ahb", "tcon-ch1";
+			resets = <&ccu RST_BUS_TCON_TV>;
+			reset-names = "lcd";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon_tv0_in: port@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
+					};
+
+					tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
+					};
+				};
+
+				tcon_tv0_out: port@1 {
+					reg = <1>;
+
+					tcon_tv0_out_tcon_top_hdmi: endpoint {
+						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
+					};
+				};
+			};
+		};
+
+		r_ccu: clock-controller@7010000 {
+			compatible = "allwinner,sun20i-d1-r-ccu";
+			reg = <0x7010000 0x400>;
+			clocks = <&dcxo>,
+				 <&rtc CLK_OSC32K>,
+				 <&rtc CLK_IOSC>,
+				 <&ccu CLK_PLL_PERIPH0_DIV3>;
+			clock-names = "hosc", "losc", "iosc", "pll-periph";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		rtc: rtc@7090000 {
+			compatible = "allwinner,sun20i-d1-rtc",
+				     "allwinner,sun50i-r329-rtc";
+			reg = <0x7090000 0x400>;
+			interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_BUS_R_RTC>,
+				 <&dcxo>,
+				 <&r_ccu CLK_R_AHB>;
+			clock-names = "bus", "hosc", "ahb";
+			#clock-cells = <1>;
+		};
+	};
+};
diff --git a/include/dt-bindings/clock/sun20i-d1-r-ccu.h b/include/dt-bindings/clock/sun20i-d1-r-ccu.h
new file mode 100644
index 00000000000..4c2697fd32b
--- /dev/null
+++ b/include/dt-bindings/clock/sun20i-d1-r-ccu.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
+
+#define CLK_R_AHB		0
+
+#define CLK_BUS_R_TIMER		2
+#define CLK_BUS_R_TWD		3
+#define CLK_BUS_R_PPU		4
+#define CLK_R_IR_RX		5
+#define CLK_BUS_R_IR_RX		6
+#define CLK_BUS_R_RTC		7
+#define CLK_BUS_R_CPUCFG	8
+
+#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun20i-d1-r-ccu.h b/include/dt-bindings/reset/sun20i-d1-r-ccu.h
new file mode 100644
index 00000000000..d93d6423d28
--- /dev/null
+++ b/include/dt-bindings/reset/sun20i-d1-r-ccu.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
+
+#define RST_BUS_R_TIMER		0
+#define RST_BUS_R_TWD		1
+#define RST_BUS_R_PPU		2
+#define RST_BUS_R_IR_RX		3
+#define RST_BUS_R_RTC		4
+#define RST_BUS_R_CPUCFG	5
+
+#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (14 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 15/17] riscv: dts: allwinner: Add the D1/D1s SoC devicetree Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2022-12-06  5:55   ` Icenowy Zheng
  2022-12-06  0:45 ` [RFC PATCH 17/17] sunxi: add preliminary MangoPi MQ-R board support Andre Przywara
  2023-06-09 22:16 ` [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Sam Edwards
  17 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

This adds the basic SoC .dtsi devicetree stub for the Allwinner T113s
SoC. This shares a die with the Allwinner D1 SoC (with RISC-V cores),
but uses two Cortex-A7 cores instead of the T-HEAD C906 RISC-V core.

Include the existing D1 devicetree stub, but add the ARM specific nodes,
like for the CPU, the arch timer and the GIC.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/dts/sun8i-t113s.dtsi | 59 +++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 arch/arm/dts/sun8i-t113s.dtsi

diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-t113s.dtsi
new file mode 100644
index 00000000000..0919ce559f6
--- /dev/null
+++ b/arch/arm/dts/sun8i-t113s.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Arm Ltd.
+
+#define SOC_PERIPHERAL_IRQ(nr)	GIC_SPI nr
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <../../riscv/dts/sunxi-d1s-t113.dtsi>
+#include <../../riscv/dts/sunxi-d1-t113.dtsi>
+
+/ {
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+			clocks = <&ccu CLK_CPUX>;
+			clock-names = "cpu";
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <1>;
+			clocks = <&ccu CLK_CPUX>;
+			clock-names = "cpu";
+		};
+	};
+
+	gic: interrupt-controller@1c81000 {
+		compatible = "arm,gic-400";
+		reg = <0x03021000 0x1000>,
+		      <0x03022000 0x2000>,
+		      <0x03024000 0x2000>,
+		      <0x03026000 0x2000>;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>;
+	};
+};
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* [RFC PATCH 17/17] sunxi: add preliminary MangoPi MQ-R board support
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (15 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub Andre Przywara
@ 2022-12-06  0:45 ` Andre Przywara
  2023-06-09 22:16 ` [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Sam Edwards
  17 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-06  0:45 UTC (permalink / raw)
  To: Samuel Holland, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

This includes a preliminary basic DT and a defconfig to get the board
booted. Although there is some DRAM code based on some disassembly, it
is not ready yet, so the SPL doesn't really work, and needs some help
from awboot.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/dts/Makefile                     |  2 +
 arch/arm/dts/sun8i-t113s-mangopi-mq-r.dts | 54 +++++++++++++++++++++++
 configs/mangopi_mq_r_defconfig            | 12 +++++
 3 files changed, 68 insertions(+)
 create mode 100644 arch/arm/dts/sun8i-t113s-mangopi-mq-r.dts
 create mode 100644 configs/mangopi_mq_r_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 43951a7731e..602349b88ab 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -694,6 +694,8 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
 	sun8i-s3-pinecube.dtb \
 	sun8i-v3-sl631-imx179.dtb \
 	sun8i-v3s-licheepi-zero.dtb
+dtb-$(CONFIG_MACH_SUN8I_R528) += \
+	sun8i-t113s-mangopi-mq-r.dtb
 dtb-$(CONFIG_MACH_SUN50I_H5) += \
 	sun50i-h5-bananapi-m2-plus.dtb \
 	sun50i-h5-emlid-neutis-n5-devboard.dtb \
diff --git a/arch/arm/dts/sun8i-t113s-mangopi-mq-r.dts b/arch/arm/dts/sun8i-t113s-mangopi-mq-r.dts
new file mode 100644
index 00000000000..1fa0c46b7dc
--- /dev/null
+++ b/arch/arm/dts/sun8i-t113s-mangopi-mq-r.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Arm Ltd.
+
+/dts-v1/;
+
+#include "sun8i-t113s.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Mangopi MQ-R";
+	compatible = "mangopi,mq-r", "allwinner,sun8i-t113s";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reg_3v3: regulator-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&dcxo {
+	clock-frequency = <24000000>;
+};
+
+&mmc0 {
+	pinctrl-0 = <&mmc0_pins>;
+	pinctrl-names = "default";
+	vmmc-supply = <&reg_3v3>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pe_pins>;
+	status = "okay";
+};
+
+&pio {
+	uart0_pe_pins: uart0-pe-pins {
+		pins = "PE2", "PE3";
+		function = "uart0";
+	};
+};
diff --git a/configs/mangopi_mq_r_defconfig b/configs/mangopi_mq_r_defconfig
new file mode 100644
index 00000000000..32b1449dc92
--- /dev/null
+++ b/configs/mangopi_mq_r_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-mangopi-mq-r"
+CONFIG_SUNXI_MINIMUM_DRAM_MB=128
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_R528=y
+CONFIG_MMC0_CD_PIN="PF6"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
+# dummy values
+CONFIG_DRAM_CLK=600
+CONFIG_DRAM_ZQ=0
-- 
2.35.5


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model
  2022-12-06  0:45 ` [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model Andre Przywara
@ 2022-12-06  5:38   ` Icenowy Zheng
  2023-05-16  2:32   ` Sam Edwards
  2023-06-03 18:03   ` Sam Edwards
  2 siblings, 0 replies; 62+ messages in thread
From: Icenowy Zheng @ 2022-12-06  5:38 UTC (permalink / raw)
  To: Andre Przywara, Samuel Holland, Jagan Teki; +Cc: u-boot, Jernej Skrabec

在 2022-12-06星期二的 00:45 +0000，Andre Przywara写道：
> Allwinner seems to typically stick to a common MMIO memory map for
> several SoCs, but from time to time does some breaking changes, which
> also introduce new generations of some peripherals. The last time
> this
> happened with the H6, which apart from re-organising the base
> addresses
> also changed the clock controller significantly. We added a
> CONFIG_SUN50I_GEN_H6 symbol back then to mark SoCs sharing those
> traits.
> 
> Now the Allwinner D1 changes the memory map again, and also extends
> the
> pincontroller, among other peripherals.
> To mark this generation of SoCs, add a CONFIG_SUNXI_GEN_NCAT2 symbol,
> this name is reportedly used in the Allwinner BSP code, and prevents
> us
> from inventing our own name.

Should we also rename the misleading GEN_SUN50I_H6 to GEN_NCAT ?

> 
> Add this new symbol to some guards that were already checking for the
> H6
> generation, since many features are shared between the two (like the
> renovated clock controller).
> 
> This paves the way to introduce a first user of this generation.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/include/asm/arch-sunxi/clock.h       |  2 +-
>  arch/arm/include/asm/arch-sunxi/cpu.h         |  2 +
>  .../include/asm/arch-sunxi/cpu_sunxi_ncat2.h  | 54
> +++++++++++++++++++
>  arch/arm/include/asm/arch-sunxi/mmc.h         |  2 +-
>  arch/arm/include/asm/arch-sunxi/prcm.h        |  2 +-
>  arch/arm/include/asm/arch-sunxi/timer.h       |  2 +-
>  arch/arm/mach-sunxi/Kconfig                   | 14 ++++-
>  arch/arm/mach-sunxi/Makefile                  |  1 +
>  arch/arm/mach-sunxi/board.c                   |  4 +-
>  common/spl/Kconfig                            |  2 +-
>  drivers/mmc/sunxi_mmc.c                       | 10 ++--
>  include/sunxi_gpio.h                          |  3 ++
>  12 files changed, 86 insertions(+), 12 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
> b/arch/arm/include/asm/arch-sunxi/clock.h
> index 2cfd5407423..3d34261b0e5 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock.h
> @@ -16,7 +16,7 @@
>  /* clock control module regs definition */
>  #if defined(CONFIG_MACH_SUN8I_A83T)
>  #include <asm/arch/clock_sun8i_a83t.h>
> -#elif defined(CONFIG_SUN50I_GEN_H6)
> +#elif defined(CONFIG_SUN50I_GEN_H6) ||
> defined(CONFIG_SUNXI_GEN_NCAT2)
>  #include <asm/arch/clock_sun50i_h6.h>
>  #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
>        defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV)
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
> b/arch/arm/include/asm/arch-sunxi/cpu.h
> index b08f2023748..768c6572d6b 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> @@ -10,6 +10,8 @@
>  #include <asm/arch/cpu_sun9i.h>
>  #elif defined(CONFIG_SUN50I_GEN_H6)
>  #include <asm/arch/cpu_sun50i_h6.h>
> +#elif defined(CONFIG_SUNXI_GEN_NCAT2)
> +#include <asm/arch/cpu_sunxi_ncat2.h>
>  #else
>  #include <asm/arch/cpu_sun4i.h>
>  #endif
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
> b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
> new file mode 100644
> index 00000000000..13093085a5e
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
> @@ -0,0 +1,54 @@
> +/*
> + * (C) Copyright 2022 Arm Limited
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#ifndef _SUNXI_CPU_SUNXI_NCAT2_H
> +#define _SUNXI_CPU_SUNXI_NCAT2_H
> +
> +#define SUNXI_SRAM_A1_BASE             CONFIG_SUNXI_SRAM_ADDRESS
> +#define SUNXI_SRAM_C_BASE              0x00028000
> +#define SUNXI_SRAM_A2_BASE             0x00100000
> +
> +#define SUNXI_SRAMC_BASE               0x02800000
> +#define SUNXI_CCM_BASE                 0x02001000
> +/* SID address space starts at 0x03006000, but e-fuse is at offset
> 0x200 */
> +#define SUNXI_SIDC_BASE                        0x03006000
> +#define SUNXI_SID_BASE                 0x03006200
> +#define SUNXI_TIMER_BASE               0x02050000
> +
> +#ifdef CONFIG_MACH_SUN50I_H6
> +#define SUNXI_DRAM_COM_BASE            0x04002000
> +#define SUNXI_DRAM_CTL0_BASE           0x04003000
> +#define SUNXI_DRAM_PHY0_BASE           0x04005000
> +#endif
> +#define SUNXI_MMC0_BASE                        0x04020000
> +#define SUNXI_MMC1_BASE                        0x04021000
> +#define SUNXI_MMC2_BASE                        0x04022000
> +
> +#define SUNXI_UART0_BASE               0x02500000
> +#define SUNXI_UART1_BASE               0x02500400
> +#define SUNXI_UART2_BASE               0x02500800
> +#define SUNXI_UART3_BASE               0x02500C00
> +#define SUNXI_TWI0_BASE                        0x02502000
> +#define SUNXI_TWI1_BASE                        0x02502400
> +#define SUNXI_TWI2_BASE                        0x02502800
> +#define SUNXI_TWI3_BASE                        0x02502C00
> +#define SUNXI_SPI0_BASE                        0x04025000
> +#define SUNXI_SPI1_BASE                        0x04026000
> +
> +#define SUNXI_RTC_BASE                 0x07000000
> +#define SUNXI_R_CPUCFG_BASE            0x07000400
> +#define SUNXI_PRCM_BASE                        0x07010000
> +#define SUNXI_R_WDOG_BASE              0x07020400
> +#define SUNXI_R_UART_BASE              0x07080000
> +#define SUNXI_R_TWI_BASE               0x07081400
> +
> +#ifndef __ASSEMBLY__
> +void sunxi_board_init(void);
> +void sunxi_reset(void);
> +int sunxi_get_sid(unsigned int *sid);
> +#endif
> +
> +#endif /* _SUNXI_CPU_SUNXI_NCAT2_H */
> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h
> b/arch/arm/include/asm/arch-sunxi/mmc.h
> index 5daacf10eb1..8ed3e0459c9 100644
> --- a/arch/arm/include/asm/arch-sunxi/mmc.h
> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
> @@ -45,7 +45,7 @@ struct sunxi_mmc {
>         u32 chda;               /* 0x90 */
>         u32 cbda;               /* 0x94 */
>         u32 res2[26];
> -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
> +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
> || defined(CONFIG_SUNXI_GEN_NCAT2)
>         u32 res3[17];
>         u32 samp_dl;
>         u32 res4[46];
> diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h
> b/arch/arm/include/asm/arch-sunxi/prcm.h
> index 5106076f5e9..c5418cfd28d 100644
> --- a/arch/arm/include/asm/arch-sunxi/prcm.h
> +++ b/arch/arm/include/asm/arch-sunxi/prcm.h
> @@ -9,7 +9,7 @@
>  #define _SUNXI_PRCM_H
>  
>  /* prcm regs definition */
> -#if defined(CONFIG_SUN50I_GEN_H6)
> +#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
>  #include <asm/arch/prcm_sun50i.h>
>  #else
>  #include <asm/arch/prcm_sun6i.h>
> diff --git a/arch/arm/include/asm/arch-sunxi/timer.h
> b/arch/arm/include/asm/arch-sunxi/timer.h
> index bb5626d893b..e17db8588e2 100644
> --- a/arch/arm/include/asm/arch-sunxi/timer.h
> +++ b/arch/arm/include/asm/arch-sunxi/timer.h
> @@ -76,7 +76,7 @@ struct sunxi_timer_reg {
>         struct sunxi_tgp tgp[4];
>         u8 res5[8];
>         u32 cpu_cfg;
> -#elif defined(CONFIG_SUNXI_GEN_SUN6I) ||
> defined(CONFIG_SUN50I_GEN_H6)
> +#elif defined(CONFIG_SUNXI_GEN_SUN6I) ||
> defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
>         u8 res3[16];
>         struct sunxi_wdog wdog[5];      /* We have 5 watchdogs */
>  #endif
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-
> sunxi/Kconfig
> index 5e019948f85..b59db212fa8 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -102,7 +102,7 @@ config AXP_PMIC_BUS
>  config SUNXI_SRAM_ADDRESS
>         hex
>         default 0x10000 if MACH_SUN9I || MACH_SUN50I ||
> MACH_SUN50I_H5
> -       default 0x20000 if SUN50I_GEN_H6
> +       default 0x20000 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
>         default 0x0
>         ---help---
>         Older Allwinner SoCs have their mask boot ROM mapped just
> below 4GB,
> @@ -144,6 +144,16 @@ config SUN50I_GEN_H6
>         Select this for sunxi SoCs which have H6 like peripherals,
> clocks
>         and memory map.
>  
> +config SUNXI_GEN_NCAT2
> +       bool
> +       select FIT
> +       select SPL_LOAD_FIT
> +       select MMC_SUNXI_HAS_NEW_MODE
> +       select SUPPORT_SPL
> +       ---help---
> +       Select this for sunxi SoCs which have D1 like peripherals,
> clocks
> +       and memory map.
> +
>  config SUNXI_DRAM_DW
>         bool
>         ---help---
> @@ -787,6 +797,7 @@ config VIDEO_SUNXI
>         depends on !MACH_SUN9I
>         depends on !MACH_SUN50I
>         depends on !SUN50I_GEN_H6
> +       depends on !SUNXI_GEN_NCAT2
>         select VIDEO
>         select DISPLAY
>         imply VIDEO_DT_SIMPLEFB
> @@ -1000,6 +1011,7 @@ config SPL_STACK_R_ADDR
>         default 0x2fe00000 if MACH_SUN9I
>         default 0x4fe00000 if MACH_SUN50I
>         default 0x4fe00000 if SUN50I_GEN_H6
> +       default 0x4fe00000 if SUNXI_GEN_NCAT2
>  
>  config SPL_SPI_SUNXI
>         bool "Support for SPI Flash on Allwinner SoCs in SPL"
> diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-
> sunxi/Makefile
> index 671211e9322..1d4c70ec352 100644
> --- a/arch/arm/mach-sunxi/Makefile
> +++ b/arch/arm/mach-sunxi/Makefile
> @@ -25,6 +25,7 @@ obj-$(CONFIG_MACH_SUN8I)      += clock_sun6i.o
>  endif
>  obj-$(CONFIG_MACH_SUN9I)       += clock_sun9i.o gtbus_sun9i.o
>  obj-$(CONFIG_SUN50I_GEN_H6)    += clock_sun50i_h6.o
> +obj-$(CONFIG_SUNXI_GEN_NCAT2)  += clock_sun50i_h6.o
>  ifndef CONFIG_ARM64
>  obj-y  += timer.o
>  endif
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-
> sunxi/board.c
> index b6ffbff883c..3763ec3d2e4 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -177,7 +177,7 @@ static int gpio_init(void)
>  #error Unsupported console port number. Please fix pin mux settings
> in board.c
>  #endif
>  
> -#ifdef CONFIG_SUN50I_GEN_H6
> +#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
>         /* Update PIO power bias configuration by copy hardware
> detected value */
>         val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
>         writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> @@ -475,7 +475,7 @@ void reset_cpu(void)
>                 /* sun5i sometimes gets stuck without this */
>                 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
>         }
> -#elif defined(CONFIG_SUNXI_GEN_SUN6I) ||
> defined(CONFIG_SUN50I_GEN_H6)
> +#elif defined(CONFIG_SUNXI_GEN_SUN6I) ||
> defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
>  #if defined(CONFIG_MACH_SUN50I_H6)
>         /* WDOG is broken for some H6 rev. use the R_WDOG instead */
>         static const struct sunxi_wdog *wdog =
> diff --git a/common/spl/Kconfig b/common/spl/Kconfig
> index fef01bdd7da..fdd64db498f 100644
> --- a/common/spl/Kconfig
> +++ b/common/spl/Kconfig
> @@ -265,7 +265,7 @@ config SPL_TEXT_BASE
>         default 0x402F0400 if AM33XX
>         default 0x40301350 if OMAP54XX
>         default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 ||
> MACH_SUN9I
> -       default 0x20060 if SUN50I_GEN_H6
> +       default 0x20060 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
>         default 0x00060 if ARCH_SUNXI
>         default 0xfffc0000 if ARCH_ZYNQMP
>         default 0x0
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index a9132af3f64..6ce2729473c 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -114,6 +114,7 @@ static bool sunxi_mmc_can_calibrate(void)
>         return IS_ENABLED(CONFIG_MACH_SUN50I) ||
>                IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
>                IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
> +              IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) ||
>                IS_ENABLED(CONFIG_MACH_SUN8I_R40);
>  }
>  
> @@ -248,7 +249,7 @@ static int mmc_config_clock(struct sunxi_mmc_priv
> *priv, struct mmc *mmc)
>         rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
>         writel(rval, &priv->reg->clkcr);
>  
> -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
> +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
> || defined(CONFIG_SUNXI_GEN_NCAT2)
>         /* A64 supports calibration of delays on MMC controller and
> we
>          * have to set delay of zero before starting calibration.
>          * Allwinner BSP driver sets a delay only in the case of
> @@ -559,7 +560,8 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>         cfg->host_caps = MMC_MODE_4BIT;
>  
>         if ((IS_ENABLED(CONFIG_MACH_SUN50I) ||
> IS_ENABLED(CONFIG_MACH_SUN8I) ||
> -           IS_ENABLED(CONFIG_SUN50I_GEN_H6)) && (sdc_no == 2))
> +           IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
> +           IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) && (sdc_no == 2))
>                 cfg->host_caps = MMC_MODE_8BIT;
>  
>         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
> @@ -573,7 +575,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>  
>         /* config ahb clock */
>         debug("init mmc %d clock and io\n", sdc_no);
> -#if !defined(CONFIG_SUN50I_GEN_H6)
> +#if !defined(CONFIG_SUN50I_GEN_H6) &&
> !defined(CONFIG_SUNXI_GEN_NCAT2)
>         setbits_le32(&ccm->ahb_gate0, 1 <<
> AHB_GATE_OFFSET_MMC(sdc_no));
>  
>  #ifdef CONFIG_SUNXI_GEN_SUN6I
> @@ -647,7 +649,7 @@ static unsigned get_mclk_offset(void)
>         if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
>                 return 0x410;
>  
> -       if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
> +       if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
> IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
>                 return 0x830;
>  
>         return 0x88;
> diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
> index 2f8b220f750..04d7aa3d632 100644
> --- a/include/sunxi_gpio.h
> +++ b/include/sunxi_gpio.h
> @@ -16,6 +16,9 @@
>  #elif defined(CONFIG_SUN50I_GEN_H6)
>  #define SUNXI_PIO_BASE         0x0300b000
>  #define SUNXI_R_PIO_BASE       0x07022000
> +#elif defined(CONFIG_SUNXI_GEN_NCAT2)
> +#define SUNXI_PIO_BASE         0x02000000
> +#define SUNXI_R_PIO_BASE       0
>  #else
>  #define SUNXI_PIO_BASE         0x01c20800
>  #define SUNXI_R_PIO_BASE       0x01f02c00


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub
  2022-12-06  0:45 ` [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub Andre Przywara
@ 2022-12-06  5:55   ` Icenowy Zheng
  2023-01-03 17:38     ` Andre Przywara
  0 siblings, 1 reply; 62+ messages in thread
From: Icenowy Zheng @ 2022-12-06  5:55 UTC (permalink / raw)
  To: Andre Przywara, Samuel Holland, Jagan Teki; +Cc: u-boot, Jernej Skrabec

在 2022-12-06星期二的 00:45 +0000，Andre Przywara写道：
> This adds the basic SoC .dtsi devicetree stub for the Allwinner T113s
> SoC. This shares a die with the Allwinner D1 SoC (with RISC-V cores),
> but uses two Cortex-A7 cores instead of the T-HEAD C906 RISC-V core.
> 
> Include the existing D1 devicetree stub, but add the ARM specific
> nodes,
> like for the CPU, the arch timer and the GIC.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/dts/sun8i-t113s.dtsi | 59
> +++++++++++++++++++++++++++++++++++
>  1 file changed, 59 insertions(+)
>  create mode 100644 arch/arm/dts/sun8i-t113s.dtsi
> 
> diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-
> t113s.dtsi
> new file mode 100644
> index 00000000000..0919ce559f6
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-t113s.dtsi
> @@ -0,0 +1,59 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2022 Arm Ltd.
> +
> +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <../../riscv/dts/sunxi-d1s-t113.dtsi>

Should we make a R528 DTSI which includes d1-t113.dtsi, and then T113
DTSI which includes d1s-t113.dtsi ?

> +#include <../../riscv/dts/sunxi-d1-t113.dtsi>
> +
> +/ {
> +       interrupt-parent = <&gic>;
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu0: cpu@0 {
> +                       compatible = "arm,cortex-a7";
> +                       device_type = "cpu";
> +                       reg = <0>;
> +                       clocks = <&ccu CLK_CPUX>;
> +                       clock-names = "cpu";
> +               };
> +
> +               cpu1: cpu@1 {
> +                       compatible = "arm,cortex-a7";
> +                       device_type = "cpu";
> +                       reg = <1>;
> +                       clocks = <&ccu CLK_CPUX>;
> +                       clock-names = "cpu";
> +               };
> +       };
> +
> +       gic: interrupt-controller@1c81000 {
> +               compatible = "arm,gic-400";
> +               reg = <0x03021000 0x1000>,
> +                     <0x03022000 0x2000>,
> +                     <0x03024000 0x2000>,
> +                     <0x03026000 0x2000>;
> +               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>;
> +               interrupt-controller;
> +               #interrupt-cells = <3>;
> +       };
> +
> +       timer {
> +               compatible = "arm,armv7-timer";
> +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>,
> +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>,
> +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>,
> +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>;
> +       };
> +
> +       pmu {
> +               compatible = "arm,cortex-a7-pmu";
> +               interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> +               interrupt-affinity = <&cpu0>, <&cpu1>;
> +       };
> +};


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR
  2022-12-06  0:45 ` [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR Andre Przywara
@ 2022-12-14  8:37   ` Samuel Holland
  2022-12-14 14:25     ` Andre Przywara
  0 siblings, 1 reply; 62+ messages in thread
From: Samuel Holland @ 2022-12-14  8:37 UTC (permalink / raw)
  To: Andre Przywara, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

Hi Andre,

On 12/5/22 18:45, Andre Przywara wrote:
> The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that
> enables the power for a SATA harddisk.
> In the DT this is described with the target-supply property in the AHCI
> DT node, pointing to a (GPIO controlled) regulator. Since we need SATA
> only in U-Boot proper, and use a DM driver for AHCI there, we should use
> the DT instead of hardcoding this.
> 
> Add code to the sunxi AHCI driver to check the DT for that regulator and
> enable it, at probe time. Then drop the current code from board.c, which
> was doing that job before.
> This allows us to remove the SATAPWR Kconfig definition and the
> respective values from the defconfigs.
> We also select the generic fixed regulator driver, which handles those
> GPIO controlled regulators.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/Kconfig                             |  2 ++
>  arch/arm/mach-sunxi/Kconfig                  |  8 --------
>  board/sunxi/board.c                          | 14 --------------
>  configs/A10-OLinuXino-Lime_defconfig         |  1 -
>  configs/A20-OLinuXino-Lime2-eMMC_defconfig   |  1 -
>  configs/A20-OLinuXino-Lime2_defconfig        |  1 -
>  configs/A20-OLinuXino-Lime_defconfig         |  1 -
>  configs/A20-OLinuXino_MICRO-eMMC_defconfig   |  1 -
>  configs/A20-OLinuXino_MICRO_defconfig        |  1 -
>  configs/A20-Olimex-SOM-EVB_defconfig         |  1 -
>  configs/A20-Olimex-SOM204-EVB-eMMC_defconfig |  1 -
>  configs/A20-Olimex-SOM204-EVB_defconfig      |  1 -
>  configs/Cubieboard2_defconfig                |  1 -
>  configs/Cubieboard_defconfig                 |  1 -
>  configs/Cubietruck_defconfig                 |  1 -
>  configs/Itead_Ibox_A20_defconfig             |  1 -
>  configs/Lamobo_R1_defconfig                  |  1 -
>  configs/Linksprite_pcDuino3_Nano_defconfig   |  1 -
>  configs/Linksprite_pcDuino3_defconfig        |  1 -
>  configs/Sinovoip_BPI_M3_defconfig            |  1 -
>  configs/orangepi_plus_defconfig              |  1 -
>  drivers/ata/ahci_sunxi.c                     |  9 +++++++++
>  22 files changed, 11 insertions(+), 40 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index f95ed71b246..3623520b353 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1148,6 +1148,8 @@ config ARCH_SUNXI
>  	select DM_SPI_FLASH if SPI
>  	select DM_KEYBOARD
>  	select DM_MMC if MMC
> +	select DM_REGULATOR
> +	select DM_REGULATOR_FIXED

While not all boards have fixed regulators, so many do that I am happy
to have this driver enabled by default. However, I recommend "imply"
over "select" so the regulator uclass can be disabled if
USB/SATA/Ethernet/whatever are not being used. You also need to
select/imply POWER, as it is a dependency.

>  	select DM_SCSI if SCSI
>  	select DM_SERIAL
>  	select GPIO_EXTRA_HEADER
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index dbe6005daab..5f95fe72d08 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -985,14 +985,6 @@ config VIDEO_LCD_TL059WV5C0
>  
>  endchoice
>  
> -config SATAPWR
> -	string "SATA power pin"
> -	default ""
> -	help
> -	  Set the pins used to power the SATA. This takes a string in the
> -	  format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
> -	  port H.
> -
>  config GMAC_TX_DELAY
>  	int "GMAC Transmit Clock Delay Chain"
>  	default 0
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 21a2407e062..ec35a7f06bd 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -229,20 +229,6 @@ int board_init(void)
>  		return ret;
>  
>  	/* strcmp() would look better, but doesn't get optimised away. */
> -	if (CONFIG_SATAPWR[0]) {
> -		satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
> -		if (satapwr_pin >= 0) {
> -			gpio_request(satapwr_pin, "satapwr");
> -			gpio_direction_output(satapwr_pin, 1);
> -
> -			/*
> -			 * Give the attached SATA device time to power-up
> -			 * to avoid link timeouts
> -			 */
> -			mdelay(500);
> -		}
> -	}
> -
>  	if (CONFIG_MACPWR[0]) {
>  		macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
>  		if (macpwr_pin >= 0) {
> diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
> index ee92ac45fbc..f5d98607003 100644
> --- a/configs/A10-OLinuXino-Lime_defconfig
> +++ b/configs/A10-OLinuXino-Lime_defconfig
> @@ -8,7 +8,6 @@ CONFIG_DRAM_EMR1=4
>  CONFIG_SYS_CLK_FREQ=912000000
>  CONFIG_MMC0_CD_PIN="PH1"
>  CONFIG_I2C1_ENABLE=y
> -CONFIG_SATAPWR="PC3"
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> index 8ce10d6f75b..a8e949a3971 100644
> --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> @@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  CONFIG_USB0_VBUS_PIN="PC17"
>  CONFIG_USB0_VBUS_DET="PH5"
>  CONFIG_I2C1_ENABLE=y
> -CONFIG_SATAPWR="PC3"
>  CONFIG_SPL_SPI_SUNXI=y
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
> index e38110b030b..c143cc17314 100644
> --- a/configs/A20-OLinuXino-Lime2_defconfig
> +++ b/configs/A20-OLinuXino-Lime2_defconfig
> @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
>  CONFIG_USB0_VBUS_PIN="PC17"
>  CONFIG_USB0_VBUS_DET="PH5"
>  CONFIG_I2C1_ENABLE=y
> -CONFIG_SATAPWR="PC3"
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
> index 4e4804748ef..b6546c26d04 100644
> --- a/configs/A20-OLinuXino-Lime_defconfig
> +++ b/configs/A20-OLinuXino-Lime_defconfig
> @@ -6,7 +6,6 @@ CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=384
>  CONFIG_MMC0_CD_PIN="PH1"
>  CONFIG_I2C1_ENABLE=y
> -CONFIG_SATAPWR="PC3"
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
> index 113d54dc0b9..95860ef8fa1 100644
> --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
> +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
> @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  CONFIG_I2C1_ENABLE=y
>  CONFIG_VIDEO_VGA=y
> -CONFIG_SATAPWR="PB8"
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
> index 1e1c30ef303..32ca51554b1 100644
> --- a/configs/A20-OLinuXino_MICRO_defconfig
> +++ b/configs/A20-OLinuXino_MICRO_defconfig
> @@ -9,7 +9,6 @@ CONFIG_MMC3_CD_PIN="PH11"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=3
>  CONFIG_I2C1_ENABLE=y
>  CONFIG_VIDEO_VGA=y
> -CONFIG_SATAPWR="PB8"
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
> index e76e6dd0932..1364c42d865 100644
> --- a/configs/A20-Olimex-SOM-EVB_defconfig
> +++ b/configs/A20-Olimex-SOM-EVB_defconfig
> @@ -9,7 +9,6 @@ CONFIG_MMC3_CD_PIN="PH0"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=3
>  CONFIG_USB0_VBUS_PIN="PB9"
>  CONFIG_USB0_VBUS_DET="PH5"
> -CONFIG_SATAPWR="PC3"
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
> index 1d3cf311952..77abe5c27ea 100644
> --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
> +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
> @@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  CONFIG_USB0_VBUS_PIN="PC17"
>  CONFIG_USB0_VBUS_DET="PH5"
>  CONFIG_I2C1_ENABLE=y
> -CONFIG_SATAPWR="PC3"
>  CONFIG_GMAC_TX_DELAY=4
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig
> index 97d0b9cee75..19065fb18d0 100644
> --- a/configs/A20-Olimex-SOM204-EVB_defconfig
> +++ b/configs/A20-Olimex-SOM204-EVB_defconfig
> @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
>  CONFIG_USB0_VBUS_PIN="PC17"
>  CONFIG_USB0_VBUS_DET="PH5"
>  CONFIG_I2C1_ENABLE=y
> -CONFIG_SATAPWR="PC3"
>  CONFIG_GMAC_TX_DELAY=4
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
> index 2c1b3d27aa0..40608498f38 100644
> --- a/configs/Cubieboard2_defconfig
> +++ b/configs/Cubieboard2_defconfig
> @@ -5,7 +5,6 @@ CONFIG_SPL=y
>  CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=480
>  CONFIG_MMC0_CD_PIN="PH1"
> -CONFIG_SATAPWR="PB8"
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
> index 008167509d3..9de9ee07568 100644
> --- a/configs/Cubieboard_defconfig
> +++ b/configs/Cubieboard_defconfig
> @@ -5,7 +5,6 @@ CONFIG_SPL=y
>  CONFIG_MACH_SUN4I=y
>  CONFIG_DRAM_CLK=480
>  CONFIG_MMC0_CD_PIN="PH1"
> -CONFIG_SATAPWR="PB8"
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
> index a4246343706..86588cdd5e2 100644
> --- a/configs/Cubietruck_defconfig
> +++ b/configs/Cubietruck_defconfig
> @@ -9,7 +9,6 @@ CONFIG_USB0_VBUS_PIN="PH17"
>  CONFIG_USB0_VBUS_DET="PH22"
>  CONFIG_USB0_ID_DET="PH19"
>  CONFIG_VIDEO_VGA=y
> -CONFIG_SATAPWR="PH12"
>  CONFIG_GMAC_TX_DELAY=1
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
> index 6474c9e90a7..b52ce776251 100644
> --- a/configs/Itead_Ibox_A20_defconfig
> +++ b/configs/Itead_Ibox_A20_defconfig
> @@ -5,7 +5,6 @@ CONFIG_SPL=y
>  CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=480
>  CONFIG_MMC0_CD_PIN="PH1"
> -CONFIG_SATAPWR="PB8"
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
> index c943fd3c06e..d51601ff10f 100644
> --- a/configs/Lamobo_R1_defconfig
> +++ b/configs/Lamobo_R1_defconfig
> @@ -6,7 +6,6 @@ CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=432
>  CONFIG_MACPWR="PH23"
>  CONFIG_MMC0_CD_PIN="PH10"
> -CONFIG_SATAPWR="PB3"
>  CONFIG_GMAC_TX_DELAY=4
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
> index 469dcc11f12..773f4a9e318 100644
> --- a/configs/Linksprite_pcDuino3_Nano_defconfig
> +++ b/configs/Linksprite_pcDuino3_Nano_defconfig
> @@ -6,7 +6,6 @@ CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=408
>  CONFIG_DRAM_ZQ=122
>  CONFIG_USB1_VBUS_PIN="PH11"
> -CONFIG_SATAPWR="PH2"
>  CONFIG_GMAC_TX_DELAY=3
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
> index c4a3f2db963..5b454b23864 100644
> --- a/configs/Linksprite_pcDuino3_defconfig
> +++ b/configs/Linksprite_pcDuino3_defconfig
> @@ -5,7 +5,6 @@ CONFIG_SPL=y
>  CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=480
>  CONFIG_DRAM_ZQ=122
> -CONFIG_SATAPWR="PH2"
>  CONFIG_AHCI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
> index ab70eff68eb..bcc8b1fba98 100644
> --- a/configs/Sinovoip_BPI_M3_defconfig
> +++ b/configs/Sinovoip_BPI_M3_defconfig
> @@ -13,7 +13,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
>  CONFIG_USB0_ID_DET="PH11"
>  CONFIG_USB1_VBUS_PIN="PD24"
>  CONFIG_AXP_GPIO=y
> -CONFIG_SATAPWR="PD25"
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
>  CONFIG_CONSOLE_MUX=y
> diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
> index 5c7f0731d90..f4ce4851d7c 100644
> --- a/configs/orangepi_plus_defconfig
> +++ b/configs/orangepi_plus_defconfig
> @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672
>  CONFIG_MACPWR="PD6"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  CONFIG_USB1_VBUS_PIN="PG13"
> -CONFIG_SATAPWR="PG11"

BananaPi M3 and OrangePi Plus have USB-SATA adapters, not onboard AHCI,
so they would lose the ability to use SATA with this change.

OrangePi Plus has the SATA controller regulator as usb3_vbus-supply in
its devicetree. So we could replace this with CONFIG_USB3_VBUS_PIN for
now, and it will continue to work once we switch the PHY driver to use
the regulator uclass.

But the BananaPi M3 has its USB-SATA downstream from an external hub.
CONFIG_USB1_VBUS_PIN is used for the regulator powering the hub, so I do
not see an obvious solution here.

Regards,
Samuel

>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
>  CONFIG_SPL_I2C=y
> diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
> index 94a3379c532..9064774e661 100644
> --- a/drivers/ata/ahci_sunxi.c
> +++ b/drivers/ata/ahci_sunxi.c
> @@ -7,6 +7,7 @@
>  #include <asm/io.h>
>  #include <asm/gpio.h>
>  #include <linux/delay.h>
> +#include <power/regulator.h>
>  
>  #define AHCI_PHYCS0R 0x00c0
>  #define AHCI_PHYCS1R 0x00c4
> @@ -74,6 +75,7 @@ static int sunxi_ahci_phy_init(u8 *reg_base)
>  
>  static int sunxi_sata_probe(struct udevice *dev)
>  {
> +	struct udevice *reg_dev;
>  	ulong base;
>  	u8 *reg;
>  	int ret;
> @@ -89,6 +91,13 @@ static int sunxi_sata_probe(struct udevice *dev)
>  		debug("%s: Failed to init phy (err=%d)\n", __func__, ret);
>  		return ret;
>  	}
> +
> +	ret = device_get_supply_regulator(dev, "target-supply", &reg_dev);
> +	if (ret == 0) {
> +		regulator_set_enable(reg_dev, true);
> +		mdelay(500);
> +	}
> +
>  	ret = ahci_probe_scsi(dev, base);
>  	if (ret) {
>  		debug("%s: Failed to probe (err=%d)\n", __func__, ret);


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 02/17] sunxi: remove CONFIG_MACPWR
  2022-12-06  0:45 ` [RFC PATCH 02/17] sunxi: remove CONFIG_MACPWR Andre Przywara
@ 2022-12-14  9:09   ` Samuel Holland
  2022-12-14 14:23     ` Andre Przywara
  0 siblings, 1 reply; 62+ messages in thread
From: Samuel Holland @ 2022-12-14  9:09 UTC (permalink / raw)
  To: Andre Przywara, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

Hi Andre,

Thanks for this cleanup! With the two issues below addressed, it looks
good to me.

On 12/5/22 18:45, Andre Przywara wrote:
> The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
> the power for the Ethernet "MAC" (mostly PHY, really).
> In the DT this is described with the phy-supply property in the MAC DT
> node, pointing to a (GPIO controlled) regulator. Since we need Ethernet
> only in U-Boot proper, and use a DM driver there, we should use the DT
> instead of hardcoding this.
> 
> Add code to the sun8i_emac and sunxi_emac drivers to check the DT for
> that regulator and enable it, at probe time. Then drop the current code
> from board.c, which was doing that job before.
> This allows us to remove the MACPWR Kconfig definition and the respective
> values from the defconfigs.

... and we don't care about sun7i-gmac here because there's no U-Boot
driver for it, and the Linux driver already uses the devicetree.

> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/mach-sunxi/Kconfig           |  7 -------
>  board/sunxi/board.c                   | 10 ----------
>  configs/Bananapi_M2_Ultra_defconfig   |  1 -
>  configs/Bananapi_defconfig            |  1 -
>  configs/Bananapro_defconfig           |  1 -
>  configs/Lamobo_R1_defconfig           |  1 -
>  configs/Mele_A1000_defconfig          |  1 -
>  configs/Orangepi_defconfig            |  1 -
>  configs/Orangepi_mini_defconfig       |  1 -
>  configs/bananapi_m1_plus_defconfig    |  1 -
>  configs/bananapi_m2_plus_h3_defconfig |  1 -
>  configs/bananapi_m2_plus_h5_defconfig |  1 -
>  configs/i12-tvbox_defconfig           |  1 -
>  configs/jesurun_q5_defconfig          |  1 -
>  configs/mixtile_loftq_defconfig       |  1 -
>  configs/nanopi_m1_plus_defconfig      |  1 -
>  configs/nanopi_neo_plus2_defconfig    |  1 -
>  configs/nanopi_r1s_h5_defconfig       |  1 -
>  configs/orangepi_pc2_defconfig        |  1 -
>  configs/orangepi_plus2e_defconfig     |  1 -
>  configs/orangepi_plus_defconfig       |  1 -
>  configs/orangepi_win_defconfig        |  1 -
>  configs/pine_h64_defconfig            |  1 -
>  configs/zeropi_defconfig              |  1 -
>  drivers/net/sun8i_emac.c              |  9 +++++++--
>  drivers/net/sunxi_emac.c              | 10 ++++++++--
>  26 files changed, 15 insertions(+), 43 deletions(-)
> 
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 5f95fe72d08..6220175d612 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -645,13 +645,6 @@ config OLD_SUNXI_KERNEL_COMPAT
>  	Set this to enable various workarounds for old kernels, this results in
>  	sub-optimal settings for newer kernels, only enable if needed.
>  
> -config MACPWR
> -	string "MAC power pin"
> -	default ""
> -	help
> -	  Set the pin used to power the MAC. This takes a string in the format
> -	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
> -
>  config MMC0_CD_PIN
>  	string "Card detect pin for mmc0"
>  	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index ec35a7f06bd..3077cc71ebd 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -228,15 +228,6 @@ int board_init(void)
>  	if (ret)
>  		return ret;
>  
> -	/* strcmp() would look better, but doesn't get optimised away. */
> -	if (CONFIG_MACPWR[0]) {
> -		macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
> -		if (macpwr_pin >= 0) {
> -			gpio_request(macpwr_pin, "macpwr");
> -			gpio_direction_output(macpwr_pin, 1);
> -		}
> -	}
> -
>  #if CONFIG_IS_ENABLED(DM_I2C)
>  	/*
>  	 * Temporary workaround for enabling I2C clocks until proper sunxi DM
> @@ -244,7 +235,6 @@ int board_init(void)
>  	 */
>  	i2c_init_board();
>  #endif
> -
>  	eth_init_board();
>  
>  	return 0;
> diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
> index 0bd163afdd7..1c4b90ab9d2 100644
> --- a/configs/Bananapi_M2_Ultra_defconfig
> +++ b/configs/Bananapi_M2_Ultra_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN8I_R40=y
>  CONFIG_DRAM_CLK=576
> -CONFIG_MACPWR="PA17"

This GPIO is actually the PHY reset line, not its power supply. Since
that line has a pull up, I don't think this was necessary to begin with.

>  CONFIG_MMC0_CD_PIN="PH13"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  CONFIG_USB1_VBUS_PIN="PH23"
> diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
> index 2814d77c187..2a590e141d9 100644
> --- a/configs/Bananapi_defconfig
> +++ b/configs/Bananapi_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=432
> -CONFIG_MACPWR="PH23"
>  CONFIG_VIDEO_COMPOSITE=y
>  CONFIG_GMAC_TX_DELAY=3
>  CONFIG_AHCI=y
> diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
> index 11375991c81..4b56195d4f2 100644
> --- a/configs/Bananapro_defconfig
> +++ b/configs/Bananapro_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=432
> -CONFIG_MACPWR="PH23"
>  CONFIG_USB1_VBUS_PIN="PH0"
>  CONFIG_USB2_VBUS_PIN="PH1"
>  CONFIG_VIDEO_COMPOSITE=y
> diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
> index d51601ff10f..fc63a7fbd46 100644
> --- a/configs/Lamobo_R1_defconfig
> +++ b/configs/Lamobo_R1_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=432
> -CONFIG_MACPWR="PH23"
>  CONFIG_MMC0_CD_PIN="PH10"
>  CONFIG_GMAC_TX_DELAY=4
>  CONFIG_AHCI=y
> diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
> index 3424b976772..a407550f6bd 100644
> --- a/configs/Mele_A1000_defconfig
> +++ b/configs/Mele_A1000_defconfig
> @@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
>  CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN4I=y
> -CONFIG_MACPWR="PH15"
>  CONFIG_VIDEO_VGA=y
>  CONFIG_VIDEO_COMPOSITE=y
>  CONFIG_AHCI=y
> diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
> index b4d5feff309..5c14e327e39 100644
> --- a/configs/Orangepi_defconfig
> +++ b/configs/Orangepi_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=432
> -CONFIG_MACPWR="PH23"
>  CONFIG_USB1_VBUS_PIN="PH26"
>  CONFIG_USB2_VBUS_PIN="PH22"
>  CONFIG_VIDEO_VGA=y
> diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
> index 43197381114..fdacf0cd123 100644
> --- a/configs/Orangepi_mini_defconfig
> +++ b/configs/Orangepi_mini_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=432
> -CONFIG_MACPWR="PH23"
>  CONFIG_MMC0_CD_PIN="PH10"
>  CONFIG_MMC3_CD_PIN="PH11"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=3
> diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig
> index 12ea6a3236a..f398c70ce1a 100644
> --- a/configs/bananapi_m1_plus_defconfig
> +++ b/configs/bananapi_m1_plus_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi-m1-plus"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=432
> -CONFIG_MACPWR="PH23"
>  CONFIG_VIDEO_COMPOSITE=y
>  CONFIG_GMAC_TX_DELAY=3
>  CONFIG_AHCI=y
> diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig
> index 2bd5a70a2d0..ab138a43060 100644
> --- a/configs/bananapi_m2_plus_h3_defconfig
> +++ b/configs/bananapi_m2_plus_h3_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN8I_H3=y
>  CONFIG_DRAM_CLK=672
> -CONFIG_MACPWR="PD6"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig
> index 926cf6f5a4d..29200e53585 100644
> --- a/configs/bananapi_m2_plus_h5_defconfig
> +++ b/configs/bananapi_m2_plus_h5_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-bananapi-m2-plus"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN50I_H5=y
>  CONFIG_DRAM_CLK=672
> -CONFIG_MACPWR="PD6"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
> index d75a7992a82..11971a8a766 100644
> --- a/configs/i12-tvbox_defconfig
> +++ b/configs/i12-tvbox_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN7I=y
>  CONFIG_DRAM_CLK=384
> -CONFIG_MACPWR="PH21"
>  CONFIG_VIDEO_COMPOSITE=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
> index 2e6b045b549..701d8ecfaa8 100644
> --- a/configs/jesurun_q5_defconfig
> +++ b/configs/jesurun_q5_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN4I=y
>  CONFIG_DRAM_CLK=312
> -CONFIG_MACPWR="PH19"
>  CONFIG_USB0_VBUS_PIN="PB9"
>  CONFIG_VIDEO_COMPOSITE=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
> index 646594b6e07..cdee80b3566 100644
> --- a/configs/mixtile_loftq_defconfig
> +++ b/configs/mixtile_loftq_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN6I=y
>  CONFIG_DRAM_ZQ=251
> -CONFIG_MACPWR="PA21"

This board does not have a regulator in its devicetree.

I verified the rest of the boards have an equivalent GPIO-controlled
fixed regulator in their devicetrees.

>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  CONFIG_USB1_VBUS_PIN="PH24"
>  CONFIG_USB2_VBUS_PIN=""
> diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig
> index 89065f0411a..a3b82de4de6 100644
> --- a/configs/nanopi_m1_plus_defconfig
> +++ b/configs/nanopi_m1_plus_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN8I_H3=y
>  CONFIG_DRAM_CLK=408
> -CONFIG_MACPWR="PD6"
>  CONFIG_MMC0_CD_PIN="PH13"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig
> index d462b63e944..f7e3efdfe5e 100644
> --- a/configs/nanopi_neo_plus2_defconfig
> +++ b/configs/nanopi_neo_plus2_defconfig
> @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
>  CONFIG_DRAM_CLK=408
>  CONFIG_DRAM_ZQ=3881977
>  # CONFIG_DRAM_ODT_EN is not set
> -CONFIG_MACPWR="PD6"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig
> index 5c332ca5261..760dfe37022 100644
> --- a/configs/nanopi_r1s_h5_defconfig
> +++ b/configs/nanopi_r1s_h5_defconfig
> @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
>  CONFIG_DRAM_CLK=672
>  CONFIG_DRAM_ZQ=3881977
>  # CONFIG_DRAM_ODT_EN is not set
> -CONFIG_MACPWR="PD6"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
> index 356ae7ce476..cf75cf4b351 100644
> --- a/configs/orangepi_pc2_defconfig
> +++ b/configs/orangepi_pc2_defconfig
> @@ -5,7 +5,6 @@ CONFIG_SPL=y
>  CONFIG_MACH_SUN50I_H5=y
>  CONFIG_DRAM_CLK=672
>  CONFIG_DRAM_ZQ=3881977
> -CONFIG_MACPWR="PD6"
>  CONFIG_SPL_SPI_SUNXI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
> index e27b329b0a9..c72adfb3e69 100644
> --- a/configs/orangepi_plus2e_defconfig
> +++ b/configs/orangepi_plus2e_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN8I_H3=y
>  CONFIG_DRAM_CLK=672
> -CONFIG_MACPWR="PD6"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
> index f4ce4851d7c..c407af38bcc 100644
> --- a/configs/orangepi_plus_defconfig
> +++ b/configs/orangepi_plus_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN8I_H3=y
>  CONFIG_DRAM_CLK=672
> -CONFIG_MACPWR="PD6"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  CONFIG_USB1_VBUS_PIN="PG13"
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig
> index 1e26970230f..b803dcd01ef 100644
> --- a/configs/orangepi_win_defconfig
> +++ b/configs/orangepi_win_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN50I=y
>  CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
> -CONFIG_MACPWR="PD14"
>  CONFIG_SPL_SPI_SUNXI=y
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig
> index 578bd92f6a3..0b482dcea24 100644
> --- a/configs/pine_h64_defconfig
> +++ b/configs/pine_h64_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN50I_H6=y
>  CONFIG_SUNXI_DRAM_H6_LPDDR3=y
> -CONFIG_MACPWR="PC16"
>  CONFIG_MMC0_CD_PIN="PF6"
>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>  CONFIG_USB3_VBUS_PIN="PL5"
> diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig
> index 8365da2c472..7ace1b5cbfd 100644
> --- a/configs/zeropi_defconfig
> +++ b/configs/zeropi_defconfig
> @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi"
>  CONFIG_SPL=y
>  CONFIG_MACH_SUN8I_H3=y
>  CONFIG_DRAM_CLK=408
> -CONFIG_MACPWR="PD6"
>  # CONFIG_VIDEO_DE2 is not set
>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>  CONFIG_SYS_MONITOR_LEN=786432
> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> index 9cca8fa4e0a..c7087b7302d 100644
> --- a/drivers/net/sun8i_emac.c
> +++ b/drivers/net/sun8i_emac.c
> @@ -29,6 +29,7 @@
>  #include <net.h>
>  #include <reset.h>
>  #include <wait_bit.h>
> +#include <power/regulator.h>
>  
>  #define MDIO_CMD_MII_BUSY		BIT(0)
>  #define MDIO_CMD_MII_WRITE		BIT(1)
> @@ -169,9 +170,8 @@ struct emac_eth_dev {
>  	struct clk ephy_clk;
>  	struct reset_ctl tx_rst;
>  	struct reset_ctl ephy_rst;
> -#if CONFIG_IS_ENABLED(DM_GPIO)
>  	struct gpio_desc reset_gpio;
> -#endif
> +	struct udevice *phy_reg;
>  };
>  
>  
> @@ -738,6 +738,9 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
>  
>  	sun8i_emac_set_syscon(sun8i_pdata, priv);
>  
> +	if (priv->phy_reg)
> +		regulator_set_enable(priv->phy_reg, true);
> +
>  	sun8i_mdio_init(dev->name, dev);
>  	priv->bus = miiphy_get_dev_by_name(dev->name);
>  
> @@ -844,6 +847,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
>  		return -EINVAL;
>  	}
>  
> +	device_get_supply_regulator(dev, "phy-supply", &priv->phy_reg);
> +
>  	pdata->phy_interface = -1;
>  	priv->phyaddr = -1;
>  	priv->use_internal_phy = false;
> diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
> index 8625e49dae4..ee8b8a1667d 100644
> --- a/drivers/net/sunxi_emac.c
> +++ b/drivers/net/sunxi_emac.c
> @@ -17,6 +17,7 @@
>  #include <net.h>
>  #include <asm/io.h>
>  #include <asm/arch/clock.h>
> +#include <power/regulator.h>
>  
>  /* EMAC register  */
>  struct emac_regs {
> @@ -164,9 +165,8 @@ struct emac_eth_dev {
>  	struct mii_dev *bus;
>  	struct phy_device *phydev;
>  	int link_printed;
> -#ifdef CONFIG_DM_ETH
>  	uchar rx_buf[EMAC_RX_BUFSIZE];
> -#endif
> +	struct udevice *phy_reg;
>  };
>  
>  struct emac_rxhdr {
> @@ -575,6 +575,9 @@ static int sunxi_emac_eth_probe(struct udevice *dev)
>  	if (ret)
>  		return ret;
>  
> +	if (priv->phy_reg)
> +		regulator_set_enable(priv->phy_reg, true);
> +
>  	return sunxi_emac_init_phy(priv, dev);
>  }
>  
> @@ -588,9 +591,12 @@ static const struct eth_ops sunxi_emac_eth_ops = {
>  static int sunxi_emac_eth_of_to_plat(struct udevice *dev)
>  {
>  	struct eth_pdata *pdata = dev_get_plat(dev);
> +	struct emac_eth_dev *priv = dev_get_priv(dev);
>  
>  	pdata->iobase = dev_read_addr(dev);
>  
> +	device_get_supply_regulator(dev, "phy-supply", &priv->phy_reg);

For sun4i-emac, the phy-supply property is actually part of the mdio
node, not the emac node.

Regards,
Samuel

> +
>  	return 0;
>  }
>  


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 02/17] sunxi: remove CONFIG_MACPWR
  2022-12-14  9:09   ` Samuel Holland
@ 2022-12-14 14:23     ` Andre Przywara
  0 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2022-12-14 14:23 UTC (permalink / raw)
  To: Samuel Holland; +Cc: Jagan Teki, u-boot, Icenowy Zheng, Jernej Skrabec

On Wed, 14 Dec 2022 03:09:22 -0600
Samuel Holland <samuel@sholland.org> wrote:

Hi Samuel,

> Thanks for this cleanup! With the two issues below addressed, it looks
> good to me.

many thanks for having such a thorough look!

> On 12/5/22 18:45, Andre Przywara wrote:
> > The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
> > the power for the Ethernet "MAC" (mostly PHY, really).
> > In the DT this is described with the phy-supply property in the MAC DT
> > node, pointing to a (GPIO controlled) regulator. Since we need Ethernet
> > only in U-Boot proper, and use a DM driver there, we should use the DT
> > instead of hardcoding this.
> > 
> > Add code to the sun8i_emac and sunxi_emac drivers to check the DT for
> > that regulator and enable it, at probe time. Then drop the current code
> > from board.c, which was doing that job before.
> > This allows us to remove the MACPWR Kconfig definition and the respective
> > values from the defconfigs.  
> 
> ... and we don't care about sun7i-gmac here because there's no U-Boot
> driver for it, and the Linux driver already uses the devicetree.

If you mean the Gigabit MAC on the A20 (allwinner,sun7i-a20-gmac), that's
implemented in drivers/net/designware.c. And this code already parses
phy-supply. I think I tried it on my BananaPi, but can double check.

> 
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> >  arch/arm/mach-sunxi/Kconfig           |  7 -------
> >  board/sunxi/board.c                   | 10 ----------
> >  configs/Bananapi_M2_Ultra_defconfig   |  1 -
> >  configs/Bananapi_defconfig            |  1 -
> >  configs/Bananapro_defconfig           |  1 -
> >  configs/Lamobo_R1_defconfig           |  1 -
> >  configs/Mele_A1000_defconfig          |  1 -
> >  configs/Orangepi_defconfig            |  1 -
> >  configs/Orangepi_mini_defconfig       |  1 -
> >  configs/bananapi_m1_plus_defconfig    |  1 -
> >  configs/bananapi_m2_plus_h3_defconfig |  1 -
> >  configs/bananapi_m2_plus_h5_defconfig |  1 -
> >  configs/i12-tvbox_defconfig           |  1 -
> >  configs/jesurun_q5_defconfig          |  1 -
> >  configs/mixtile_loftq_defconfig       |  1 -
> >  configs/nanopi_m1_plus_defconfig      |  1 -
> >  configs/nanopi_neo_plus2_defconfig    |  1 -
> >  configs/nanopi_r1s_h5_defconfig       |  1 -
> >  configs/orangepi_pc2_defconfig        |  1 -
> >  configs/orangepi_plus2e_defconfig     |  1 -
> >  configs/orangepi_plus_defconfig       |  1 -
> >  configs/orangepi_win_defconfig        |  1 -
> >  configs/pine_h64_defconfig            |  1 -
> >  configs/zeropi_defconfig              |  1 -
> >  drivers/net/sun8i_emac.c              |  9 +++++++--
> >  drivers/net/sunxi_emac.c              | 10 ++++++++--
> >  26 files changed, 15 insertions(+), 43 deletions(-)
> > 
> > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > index 5f95fe72d08..6220175d612 100644
> > --- a/arch/arm/mach-sunxi/Kconfig
> > +++ b/arch/arm/mach-sunxi/Kconfig
> > @@ -645,13 +645,6 @@ config OLD_SUNXI_KERNEL_COMPAT
> >  	Set this to enable various workarounds for old kernels, this results in
> >  	sub-optimal settings for newer kernels, only enable if needed.
> >  
> > -config MACPWR
> > -	string "MAC power pin"
> > -	default ""
> > -	help
> > -	  Set the pin used to power the MAC. This takes a string in the format
> > -	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
> > -
> >  config MMC0_CD_PIN
> >  	string "Card detect pin for mmc0"
> >  	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
> > diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> > index ec35a7f06bd..3077cc71ebd 100644
> > --- a/board/sunxi/board.c
> > +++ b/board/sunxi/board.c
> > @@ -228,15 +228,6 @@ int board_init(void)
> >  	if (ret)
> >  		return ret;
> >  
> > -	/* strcmp() would look better, but doesn't get optimised away. */
> > -	if (CONFIG_MACPWR[0]) {
> > -		macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
> > -		if (macpwr_pin >= 0) {
> > -			gpio_request(macpwr_pin, "macpwr");
> > -			gpio_direction_output(macpwr_pin, 1);
> > -		}
> > -	}
> > -
> >  #if CONFIG_IS_ENABLED(DM_I2C)
> >  	/*
> >  	 * Temporary workaround for enabling I2C clocks until proper sunxi DM
> > @@ -244,7 +235,6 @@ int board_init(void)
> >  	 */
> >  	i2c_init_board();
> >  #endif
> > -
> >  	eth_init_board();
> >  
> >  	return 0;
> > diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
> > index 0bd163afdd7..1c4b90ab9d2 100644
> > --- a/configs/Bananapi_M2_Ultra_defconfig
> > +++ b/configs/Bananapi_M2_Ultra_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN8I_R40=y
> >  CONFIG_DRAM_CLK=576
> > -CONFIG_MACPWR="PA17"  
> 
> This GPIO is actually the PHY reset line, not its power supply. Since
> that line has a pull up, I don't think this was necessary to begin with.

Ha, good find. Indeed the schematic confirms that. And the BPi M2 Berry
uses the same connection, but doesn't mention PA17 at all (neither in the
defconfig nor in the DT). I don't have a M2U, but will play around with my
M2 Berry, to simulate that.

> >  CONFIG_MMC0_CD_PIN="PH13"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  CONFIG_USB1_VBUS_PIN="PH23"
> > diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
> > index 2814d77c187..2a590e141d9 100644
> > --- a/configs/Bananapi_defconfig
> > +++ b/configs/Bananapi_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=432
> > -CONFIG_MACPWR="PH23"
> >  CONFIG_VIDEO_COMPOSITE=y
> >  CONFIG_GMAC_TX_DELAY=3
> >  CONFIG_AHCI=y
> > diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
> > index 11375991c81..4b56195d4f2 100644
> > --- a/configs/Bananapro_defconfig
> > +++ b/configs/Bananapro_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=432
> > -CONFIG_MACPWR="PH23"
> >  CONFIG_USB1_VBUS_PIN="PH0"
> >  CONFIG_USB2_VBUS_PIN="PH1"
> >  CONFIG_VIDEO_COMPOSITE=y
> > diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
> > index d51601ff10f..fc63a7fbd46 100644
> > --- a/configs/Lamobo_R1_defconfig
> > +++ b/configs/Lamobo_R1_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=432
> > -CONFIG_MACPWR="PH23"
> >  CONFIG_MMC0_CD_PIN="PH10"
> >  CONFIG_GMAC_TX_DELAY=4
> >  CONFIG_AHCI=y
> > diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
> > index 3424b976772..a407550f6bd 100644
> > --- a/configs/Mele_A1000_defconfig
> > +++ b/configs/Mele_A1000_defconfig
> > @@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
> >  CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN4I=y
> > -CONFIG_MACPWR="PH15"
> >  CONFIG_VIDEO_VGA=y
> >  CONFIG_VIDEO_COMPOSITE=y
> >  CONFIG_AHCI=y
> > diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
> > index b4d5feff309..5c14e327e39 100644
> > --- a/configs/Orangepi_defconfig
> > +++ b/configs/Orangepi_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=432
> > -CONFIG_MACPWR="PH23"
> >  CONFIG_USB1_VBUS_PIN="PH26"
> >  CONFIG_USB2_VBUS_PIN="PH22"
> >  CONFIG_VIDEO_VGA=y
> > diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
> > index 43197381114..fdacf0cd123 100644
> > --- a/configs/Orangepi_mini_defconfig
> > +++ b/configs/Orangepi_mini_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=432
> > -CONFIG_MACPWR="PH23"
> >  CONFIG_MMC0_CD_PIN="PH10"
> >  CONFIG_MMC3_CD_PIN="PH11"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=3
> > diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig
> > index 12ea6a3236a..f398c70ce1a 100644
> > --- a/configs/bananapi_m1_plus_defconfig
> > +++ b/configs/bananapi_m1_plus_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi-m1-plus"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=432
> > -CONFIG_MACPWR="PH23"
> >  CONFIG_VIDEO_COMPOSITE=y
> >  CONFIG_GMAC_TX_DELAY=3
> >  CONFIG_AHCI=y
> > diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig
> > index 2bd5a70a2d0..ab138a43060 100644
> > --- a/configs/bananapi_m2_plus_h3_defconfig
> > +++ b/configs/bananapi_m2_plus_h3_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN8I_H3=y
> >  CONFIG_DRAM_CLK=672
> > -CONFIG_MACPWR="PD6"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig
> > index 926cf6f5a4d..29200e53585 100644
> > --- a/configs/bananapi_m2_plus_h5_defconfig
> > +++ b/configs/bananapi_m2_plus_h5_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-bananapi-m2-plus"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN50I_H5=y
> >  CONFIG_DRAM_CLK=672
> > -CONFIG_MACPWR="PD6"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
> > index d75a7992a82..11971a8a766 100644
> > --- a/configs/i12-tvbox_defconfig
> > +++ b/configs/i12-tvbox_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=384
> > -CONFIG_MACPWR="PH21"
> >  CONFIG_VIDEO_COMPOSITE=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
> > index 2e6b045b549..701d8ecfaa8 100644
> > --- a/configs/jesurun_q5_defconfig
> > +++ b/configs/jesurun_q5_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN4I=y
> >  CONFIG_DRAM_CLK=312
> > -CONFIG_MACPWR="PH19"
> >  CONFIG_USB0_VBUS_PIN="PB9"
> >  CONFIG_VIDEO_COMPOSITE=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
> > index 646594b6e07..cdee80b3566 100644
> > --- a/configs/mixtile_loftq_defconfig
> > +++ b/configs/mixtile_loftq_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN6I=y
> >  CONFIG_DRAM_ZQ=251
> > -CONFIG_MACPWR="PA21"  
> 
> This board does not have a regulator in its devicetree.

Yeah, that's an odd one, as the DT only exists in the U-Boot tree. So we
could just add it. I guess given the age and "support status" of this
board no one would care anyways ;-)

> I verified the rest of the boards have an equivalent GPIO-controlled
> fixed regulator in their devicetrees.

Oh, many thanks!

> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  CONFIG_USB1_VBUS_PIN="PH24"
> >  CONFIG_USB2_VBUS_PIN=""
> > diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig
> > index 89065f0411a..a3b82de4de6 100644
> > --- a/configs/nanopi_m1_plus_defconfig
> > +++ b/configs/nanopi_m1_plus_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN8I_H3=y
> >  CONFIG_DRAM_CLK=408
> > -CONFIG_MACPWR="PD6"
> >  CONFIG_MMC0_CD_PIN="PH13"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig
> > index d462b63e944..f7e3efdfe5e 100644
> > --- a/configs/nanopi_neo_plus2_defconfig
> > +++ b/configs/nanopi_neo_plus2_defconfig
> > @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
> >  CONFIG_DRAM_CLK=408
> >  CONFIG_DRAM_ZQ=3881977
> >  # CONFIG_DRAM_ODT_EN is not set
> > -CONFIG_MACPWR="PD6"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig
> > index 5c332ca5261..760dfe37022 100644
> > --- a/configs/nanopi_r1s_h5_defconfig
> > +++ b/configs/nanopi_r1s_h5_defconfig
> > @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
> >  CONFIG_DRAM_CLK=672
> >  CONFIG_DRAM_ZQ=3881977
> >  # CONFIG_DRAM_ODT_EN is not set
> > -CONFIG_MACPWR="PD6"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
> > index 356ae7ce476..cf75cf4b351 100644
> > --- a/configs/orangepi_pc2_defconfig
> > +++ b/configs/orangepi_pc2_defconfig
> > @@ -5,7 +5,6 @@ CONFIG_SPL=y
> >  CONFIG_MACH_SUN50I_H5=y
> >  CONFIG_DRAM_CLK=672
> >  CONFIG_DRAM_ZQ=3881977
> > -CONFIG_MACPWR="PD6"
> >  CONFIG_SPL_SPI_SUNXI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
> > index e27b329b0a9..c72adfb3e69 100644
> > --- a/configs/orangepi_plus2e_defconfig
> > +++ b/configs/orangepi_plus2e_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN8I_H3=y
> >  CONFIG_DRAM_CLK=672
> > -CONFIG_MACPWR="PD6"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
> > index f4ce4851d7c..c407af38bcc 100644
> > --- a/configs/orangepi_plus_defconfig
> > +++ b/configs/orangepi_plus_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN8I_H3=y
> >  CONFIG_DRAM_CLK=672
> > -CONFIG_MACPWR="PD6"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  CONFIG_USB1_VBUS_PIN="PG13"
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig
> > index 1e26970230f..b803dcd01ef 100644
> > --- a/configs/orangepi_win_defconfig
> > +++ b/configs/orangepi_win_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN50I=y
> >  CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
> > -CONFIG_MACPWR="PD14"
> >  CONFIG_SPL_SPI_SUNXI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig
> > index 578bd92f6a3..0b482dcea24 100644
> > --- a/configs/pine_h64_defconfig
> > +++ b/configs/pine_h64_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN50I_H6=y
> >  CONFIG_SUNXI_DRAM_H6_LPDDR3=y
> > -CONFIG_MACPWR="PC16"
> >  CONFIG_MMC0_CD_PIN="PF6"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  CONFIG_USB3_VBUS_PIN="PL5"
> > diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig
> > index 8365da2c472..7ace1b5cbfd 100644
> > --- a/configs/zeropi_defconfig
> > +++ b/configs/zeropi_defconfig
> > @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi"
> >  CONFIG_SPL=y
> >  CONFIG_MACH_SUN8I_H3=y
> >  CONFIG_DRAM_CLK=408
> > -CONFIG_MACPWR="PD6"
> >  # CONFIG_VIDEO_DE2 is not set
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> > index 9cca8fa4e0a..c7087b7302d 100644
> > --- a/drivers/net/sun8i_emac.c
> > +++ b/drivers/net/sun8i_emac.c
> > @@ -29,6 +29,7 @@
> >  #include <net.h>
> >  #include <reset.h>
> >  #include <wait_bit.h>
> > +#include <power/regulator.h>
> >  
> >  #define MDIO_CMD_MII_BUSY		BIT(0)
> >  #define MDIO_CMD_MII_WRITE		BIT(1)
> > @@ -169,9 +170,8 @@ struct emac_eth_dev {
> >  	struct clk ephy_clk;
> >  	struct reset_ctl tx_rst;
> >  	struct reset_ctl ephy_rst;
> > -#if CONFIG_IS_ENABLED(DM_GPIO)
> >  	struct gpio_desc reset_gpio;
> > -#endif
> > +	struct udevice *phy_reg;
> >  };
> >  
> >  
> > @@ -738,6 +738,9 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
> >  
> >  	sun8i_emac_set_syscon(sun8i_pdata, priv);
> >  
> > +	if (priv->phy_reg)
> > +		regulator_set_enable(priv->phy_reg, true);
> > +
> >  	sun8i_mdio_init(dev->name, dev);
> >  	priv->bus = miiphy_get_dev_by_name(dev->name);
> >  
> > @@ -844,6 +847,8 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
> >  		return -EINVAL;
> >  	}
> >  
> > +	device_get_supply_regulator(dev, "phy-supply", &priv->phy_reg);
> > +
> >  	pdata->phy_interface = -1;
> >  	priv->phyaddr = -1;
> >  	priv->use_internal_phy = false;
> > diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
> > index 8625e49dae4..ee8b8a1667d 100644
> > --- a/drivers/net/sunxi_emac.c
> > +++ b/drivers/net/sunxi_emac.c
> > @@ -17,6 +17,7 @@
> >  #include <net.h>
> >  #include <asm/io.h>
> >  #include <asm/arch/clock.h>
> > +#include <power/regulator.h>
> >  
> >  /* EMAC register  */
> >  struct emac_regs {
> > @@ -164,9 +165,8 @@ struct emac_eth_dev {
> >  	struct mii_dev *bus;
> >  	struct phy_device *phydev;
> >  	int link_printed;
> > -#ifdef CONFIG_DM_ETH
> >  	uchar rx_buf[EMAC_RX_BUFSIZE];
> > -#endif
> > +	struct udevice *phy_reg;
> >  };
> >  
> >  struct emac_rxhdr {
> > @@ -575,6 +575,9 @@ static int sunxi_emac_eth_probe(struct udevice *dev)
> >  	if (ret)
> >  		return ret;
> >  
> > +	if (priv->phy_reg)
> > +		regulator_set_enable(priv->phy_reg, true);
> > +
> >  	return sunxi_emac_init_phy(priv, dev);
> >  }
> >  
> > @@ -588,9 +591,12 @@ static const struct eth_ops sunxi_emac_eth_ops = {
> >  static int sunxi_emac_eth_of_to_plat(struct udevice *dev)
> >  {
> >  	struct eth_pdata *pdata = dev_get_plat(dev);
> > +	struct emac_eth_dev *priv = dev_get_priv(dev);
> >  
> >  	pdata->iobase = dev_read_addr(dev);
> >  
> > +	device_get_supply_regulator(dev, "phy-supply", &priv->phy_reg);  
> 
> For sun4i-emac, the phy-supply property is actually part of the mdio
> node, not the emac node.

Huh, right. As far as I can tell, this only affects two boards, Mele_A1000
and jesurun_q5, which I don't have.
So can we follow the link to the PHY node, then go to its parent, which
should be the MDIO node? And pick the regulator from there?

Cheers,
Andre

> Regards,
> Samuel
> 
> > +
> >  	return 0;
> >  }
> >    
> 


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR
  2022-12-14  8:37   ` Samuel Holland
@ 2022-12-14 14:25     ` Andre Przywara
  2022-12-14 23:40       ` Samuel Holland
  0 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2022-12-14 14:25 UTC (permalink / raw)
  To: Samuel Holland
  Cc: Jagan Teki, u-boot, Icenowy Zheng, Jernej Skrabec, linux-sunxi

On Wed, 14 Dec 2022 02:37:12 -0600
Samuel Holland <samuel@sholland.org> wrote:

Hi Samuel,

many thanks for having a look!

> On 12/5/22 18:45, Andre Przywara wrote:
> > The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that
> > enables the power for a SATA harddisk.
> > In the DT this is described with the target-supply property in the AHCI
> > DT node, pointing to a (GPIO controlled) regulator. Since we need SATA
> > only in U-Boot proper, and use a DM driver for AHCI there, we should use
> > the DT instead of hardcoding this.
> > 
> > Add code to the sunxi AHCI driver to check the DT for that regulator and
> > enable it, at probe time. Then drop the current code from board.c, which
> > was doing that job before.
> > This allows us to remove the SATAPWR Kconfig definition and the
> > respective values from the defconfigs.
> > We also select the generic fixed regulator driver, which handles those
> > GPIO controlled regulators.
> > 
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> >  arch/arm/Kconfig                             |  2 ++
> >  arch/arm/mach-sunxi/Kconfig                  |  8 --------
> >  board/sunxi/board.c                          | 14 --------------
> >  configs/A10-OLinuXino-Lime_defconfig         |  1 -
> >  configs/A20-OLinuXino-Lime2-eMMC_defconfig   |  1 -
> >  configs/A20-OLinuXino-Lime2_defconfig        |  1 -
> >  configs/A20-OLinuXino-Lime_defconfig         |  1 -
> >  configs/A20-OLinuXino_MICRO-eMMC_defconfig   |  1 -
> >  configs/A20-OLinuXino_MICRO_defconfig        |  1 -
> >  configs/A20-Olimex-SOM-EVB_defconfig         |  1 -
> >  configs/A20-Olimex-SOM204-EVB-eMMC_defconfig |  1 -
> >  configs/A20-Olimex-SOM204-EVB_defconfig      |  1 -
> >  configs/Cubieboard2_defconfig                |  1 -
> >  configs/Cubieboard_defconfig                 |  1 -
> >  configs/Cubietruck_defconfig                 |  1 -
> >  configs/Itead_Ibox_A20_defconfig             |  1 -
> >  configs/Lamobo_R1_defconfig                  |  1 -
> >  configs/Linksprite_pcDuino3_Nano_defconfig   |  1 -
> >  configs/Linksprite_pcDuino3_defconfig        |  1 -
> >  configs/Sinovoip_BPI_M3_defconfig            |  1 -
> >  configs/orangepi_plus_defconfig              |  1 -
> >  drivers/ata/ahci_sunxi.c                     |  9 +++++++++
> >  22 files changed, 11 insertions(+), 40 deletions(-)
> > 
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index f95ed71b246..3623520b353 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1148,6 +1148,8 @@ config ARCH_SUNXI
> >  	select DM_SPI_FLASH if SPI
> >  	select DM_KEYBOARD
> >  	select DM_MMC if MMC
> > +	select DM_REGULATOR
> > +	select DM_REGULATOR_FIXED  
> 
> While not all boards have fixed regulators, so many do that I am happy
> to have this driver enabled by default. However, I recommend "imply"
> over "select" so the regulator uclass can be disabled if
> USB/SATA/Ethernet/whatever are not being used. You also need to
> select/imply POWER, as it is a dependency.

Yes, that's indeed better.

> >  	select DM_SCSI if SCSI
> >  	select DM_SERIAL
> >  	select GPIO_EXTRA_HEADER
> > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > index dbe6005daab..5f95fe72d08 100644
> > --- a/arch/arm/mach-sunxi/Kconfig
> > +++ b/arch/arm/mach-sunxi/Kconfig
> > @@ -985,14 +985,6 @@ config VIDEO_LCD_TL059WV5C0
> >  
> >  endchoice
> >  
> > -config SATAPWR
> > -	string "SATA power pin"
> > -	default ""
> > -	help
> > -	  Set the pins used to power the SATA. This takes a string in the
> > -	  format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
> > -	  port H.
> > -
> >  config GMAC_TX_DELAY
> >  	int "GMAC Transmit Clock Delay Chain"
> >  	default 0
> > diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> > index 21a2407e062..ec35a7f06bd 100644
> > --- a/board/sunxi/board.c
> > +++ b/board/sunxi/board.c
> > @@ -229,20 +229,6 @@ int board_init(void)
> >  		return ret;
> >  
> >  	/* strcmp() would look better, but doesn't get optimised away. */
> > -	if (CONFIG_SATAPWR[0]) {
> > -		satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
> > -		if (satapwr_pin >= 0) {
> > -			gpio_request(satapwr_pin, "satapwr");
> > -			gpio_direction_output(satapwr_pin, 1);
> > -
> > -			/*
> > -			 * Give the attached SATA device time to power-up
> > -			 * to avoid link timeouts
> > -			 */
> > -			mdelay(500);
> > -		}
> > -	}
> > -
> >  	if (CONFIG_MACPWR[0]) {
> >  		macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
> >  		if (macpwr_pin >= 0) {
> > diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
> > index ee92ac45fbc..f5d98607003 100644
> > --- a/configs/A10-OLinuXino-Lime_defconfig
> > +++ b/configs/A10-OLinuXino-Lime_defconfig
> > @@ -8,7 +8,6 @@ CONFIG_DRAM_EMR1=4
> >  CONFIG_SYS_CLK_FREQ=912000000
> >  CONFIG_MMC0_CD_PIN="PH1"
> >  CONFIG_I2C1_ENABLE=y
> > -CONFIG_SATAPWR="PC3"
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > index 8ce10d6f75b..a8e949a3971 100644
> > --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
> > @@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  CONFIG_USB0_VBUS_PIN="PC17"
> >  CONFIG_USB0_VBUS_DET="PH5"
> >  CONFIG_I2C1_ENABLE=y
> > -CONFIG_SATAPWR="PC3"
> >  CONFIG_SPL_SPI_SUNXI=y
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
> > index e38110b030b..c143cc17314 100644
> > --- a/configs/A20-OLinuXino-Lime2_defconfig
> > +++ b/configs/A20-OLinuXino-Lime2_defconfig
> > @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
> >  CONFIG_USB0_VBUS_PIN="PC17"
> >  CONFIG_USB0_VBUS_DET="PH5"
> >  CONFIG_I2C1_ENABLE=y
> > -CONFIG_SATAPWR="PC3"
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
> > index 4e4804748ef..b6546c26d04 100644
> > --- a/configs/A20-OLinuXino-Lime_defconfig
> > +++ b/configs/A20-OLinuXino-Lime_defconfig
> > @@ -6,7 +6,6 @@ CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=384
> >  CONFIG_MMC0_CD_PIN="PH1"
> >  CONFIG_I2C1_ENABLE=y
> > -CONFIG_SATAPWR="PC3"
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
> > index 113d54dc0b9..95860ef8fa1 100644
> > --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
> > +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
> > @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  CONFIG_I2C1_ENABLE=y
> >  CONFIG_VIDEO_VGA=y
> > -CONFIG_SATAPWR="PB8"
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
> > index 1e1c30ef303..32ca51554b1 100644
> > --- a/configs/A20-OLinuXino_MICRO_defconfig
> > +++ b/configs/A20-OLinuXino_MICRO_defconfig
> > @@ -9,7 +9,6 @@ CONFIG_MMC3_CD_PIN="PH11"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=3
> >  CONFIG_I2C1_ENABLE=y
> >  CONFIG_VIDEO_VGA=y
> > -CONFIG_SATAPWR="PB8"
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
> > index e76e6dd0932..1364c42d865 100644
> > --- a/configs/A20-Olimex-SOM-EVB_defconfig
> > +++ b/configs/A20-Olimex-SOM-EVB_defconfig
> > @@ -9,7 +9,6 @@ CONFIG_MMC3_CD_PIN="PH0"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=3
> >  CONFIG_USB0_VBUS_PIN="PB9"
> >  CONFIG_USB0_VBUS_DET="PH5"
> > -CONFIG_SATAPWR="PC3"
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
> > index 1d3cf311952..77abe5c27ea 100644
> > --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
> > +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
> > @@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  CONFIG_USB0_VBUS_PIN="PC17"
> >  CONFIG_USB0_VBUS_DET="PH5"
> >  CONFIG_I2C1_ENABLE=y
> > -CONFIG_SATAPWR="PC3"
> >  CONFIG_GMAC_TX_DELAY=4
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig
> > index 97d0b9cee75..19065fb18d0 100644
> > --- a/configs/A20-Olimex-SOM204-EVB_defconfig
> > +++ b/configs/A20-Olimex-SOM204-EVB_defconfig
> > @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
> >  CONFIG_USB0_VBUS_PIN="PC17"
> >  CONFIG_USB0_VBUS_DET="PH5"
> >  CONFIG_I2C1_ENABLE=y
> > -CONFIG_SATAPWR="PC3"
> >  CONFIG_GMAC_TX_DELAY=4
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
> > index 2c1b3d27aa0..40608498f38 100644
> > --- a/configs/Cubieboard2_defconfig
> > +++ b/configs/Cubieboard2_defconfig
> > @@ -5,7 +5,6 @@ CONFIG_SPL=y
> >  CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=480
> >  CONFIG_MMC0_CD_PIN="PH1"
> > -CONFIG_SATAPWR="PB8"
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
> > index 008167509d3..9de9ee07568 100644
> > --- a/configs/Cubieboard_defconfig
> > +++ b/configs/Cubieboard_defconfig
> > @@ -5,7 +5,6 @@ CONFIG_SPL=y
> >  CONFIG_MACH_SUN4I=y
> >  CONFIG_DRAM_CLK=480
> >  CONFIG_MMC0_CD_PIN="PH1"
> > -CONFIG_SATAPWR="PB8"
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
> > index a4246343706..86588cdd5e2 100644
> > --- a/configs/Cubietruck_defconfig
> > +++ b/configs/Cubietruck_defconfig
> > @@ -9,7 +9,6 @@ CONFIG_USB0_VBUS_PIN="PH17"
> >  CONFIG_USB0_VBUS_DET="PH22"
> >  CONFIG_USB0_ID_DET="PH19"
> >  CONFIG_VIDEO_VGA=y
> > -CONFIG_SATAPWR="PH12"
> >  CONFIG_GMAC_TX_DELAY=1
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
> > index 6474c9e90a7..b52ce776251 100644
> > --- a/configs/Itead_Ibox_A20_defconfig
> > +++ b/configs/Itead_Ibox_A20_defconfig
> > @@ -5,7 +5,6 @@ CONFIG_SPL=y
> >  CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=480
> >  CONFIG_MMC0_CD_PIN="PH1"
> > -CONFIG_SATAPWR="PB8"
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
> > index c943fd3c06e..d51601ff10f 100644
> > --- a/configs/Lamobo_R1_defconfig
> > +++ b/configs/Lamobo_R1_defconfig
> > @@ -6,7 +6,6 @@ CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=432
> >  CONFIG_MACPWR="PH23"
> >  CONFIG_MMC0_CD_PIN="PH10"
> > -CONFIG_SATAPWR="PB3"
> >  CONFIG_GMAC_TX_DELAY=4
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
> > index 469dcc11f12..773f4a9e318 100644
> > --- a/configs/Linksprite_pcDuino3_Nano_defconfig
> > +++ b/configs/Linksprite_pcDuino3_Nano_defconfig
> > @@ -6,7 +6,6 @@ CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=408
> >  CONFIG_DRAM_ZQ=122
> >  CONFIG_USB1_VBUS_PIN="PH11"
> > -CONFIG_SATAPWR="PH2"
> >  CONFIG_GMAC_TX_DELAY=3
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> > diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
> > index c4a3f2db963..5b454b23864 100644
> > --- a/configs/Linksprite_pcDuino3_defconfig
> > +++ b/configs/Linksprite_pcDuino3_defconfig
> > @@ -5,7 +5,6 @@ CONFIG_SPL=y
> >  CONFIG_MACH_SUN7I=y
> >  CONFIG_DRAM_CLK=480
> >  CONFIG_DRAM_ZQ=122
> > -CONFIG_SATAPWR="PH2"
> >  CONFIG_AHCI=y
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> > diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
> > index ab70eff68eb..bcc8b1fba98 100644
> > --- a/configs/Sinovoip_BPI_M3_defconfig
> > +++ b/configs/Sinovoip_BPI_M3_defconfig
> > @@ -13,7 +13,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
> >  CONFIG_USB0_ID_DET="PH11"
> >  CONFIG_USB1_VBUS_PIN="PD24"
> >  CONFIG_AXP_GPIO=y
> > -CONFIG_SATAPWR="PD25"
> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> >  CONFIG_CONSOLE_MUX=y
> > diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
> > index 5c7f0731d90..f4ce4851d7c 100644
> > --- a/configs/orangepi_plus_defconfig
> > +++ b/configs/orangepi_plus_defconfig
> > @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672
> >  CONFIG_MACPWR="PD6"
> >  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> >  CONFIG_USB1_VBUS_PIN="PG13"
> > -CONFIG_SATAPWR="PG11"  
> 
> BananaPi M3 and OrangePi Plus have USB-SATA adapters, not onboard AHCI,
> so they would lose the ability to use SATA with this change.

Many thanks for having a thorough look, I much appreciate that.
Of course you are right. I actually found this myself, and thought I
mentioned it somewhere, but apparently this got lost in between cover
letter versions and commit messages on different branches. Apologies for
that.
So yeah, my research figured that this isn't described properly in the DT,
so SATA disks just work in Linux because U-Boot flipped the bit here.
I heard about USB child DT nodes, which IIUC are possible to describe
errata and such, but I don't think it's a good solution here. Would
probably need driver changes, so wouldn't be backwards compatible.

> OrangePi Plus has the SATA controller regulator as usb3_vbus-supply in
> its devicetree. So we could replace this with CONFIG_USB3_VBUS_PIN for
> now, and it will continue to work once we switch the PHY driver to use
> the regulator uclass.
> 
> But the BananaPi M3 has its USB-SATA downstream from an external hub.
> CONFIG_USB1_VBUS_PIN is used for the regulator powering the hub, so I do
> not see an obvious solution here.

Yeah, I didn't find a neat automatic solution for that either.
Can we add a regulator-fixed, and make this regulator-boot-on? Without
actually referencing this regulator anywhere? I need to check this
actually works in U-Boot, but what do you say with your Linux/DT maintainer
hat on?

Cheers,
Andre

> >  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> >  CONFIG_SYS_MONITOR_LEN=786432
> >  CONFIG_SPL_I2C=y
> > diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
> > index 94a3379c532..9064774e661 100644
> > --- a/drivers/ata/ahci_sunxi.c
> > +++ b/drivers/ata/ahci_sunxi.c
> > @@ -7,6 +7,7 @@
> >  #include <asm/io.h>
> >  #include <asm/gpio.h>
> >  #include <linux/delay.h>
> > +#include <power/regulator.h>
> >  
> >  #define AHCI_PHYCS0R 0x00c0
> >  #define AHCI_PHYCS1R 0x00c4
> > @@ -74,6 +75,7 @@ static int sunxi_ahci_phy_init(u8 *reg_base)
> >  
> >  static int sunxi_sata_probe(struct udevice *dev)
> >  {
> > +	struct udevice *reg_dev;
> >  	ulong base;
> >  	u8 *reg;
> >  	int ret;
> > @@ -89,6 +91,13 @@ static int sunxi_sata_probe(struct udevice *dev)
> >  		debug("%s: Failed to init phy (err=%d)\n", __func__, ret);
> >  		return ret;
> >  	}
> > +
> > +	ret = device_get_supply_regulator(dev, "target-supply", &reg_dev);
> > +	if (ret == 0) {
> > +		regulator_set_enable(reg_dev, true);
> > +		mdelay(500);
> > +	}
> > +
> >  	ret = ahci_probe_scsi(dev, base);
> >  	if (ret) {
> >  		debug("%s: Failed to probe (err=%d)\n", __func__, ret);  
> 


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR
  2022-12-14 14:25     ` Andre Przywara
@ 2022-12-14 23:40       ` Samuel Holland
  0 siblings, 0 replies; 62+ messages in thread
From: Samuel Holland @ 2022-12-14 23:40 UTC (permalink / raw)
  To: Andre Przywara
  Cc: Jagan Teki, u-boot, Icenowy Zheng, Jernej Skrabec, linux-sunxi

Andre,

On 12/14/22 08:25, Andre Przywara wrote:
> On Wed, 14 Dec 2022 02:37:12 -0600 Samuel Holland <samuel@sholland.org> wrote:
>> On 12/5/22 18:45, Andre Przywara wrote:
>>> diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
>>> index ab70eff68eb..bcc8b1fba98 100644
>>> --- a/configs/Sinovoip_BPI_M3_defconfig
>>> +++ b/configs/Sinovoip_BPI_M3_defconfig
>>> @@ -13,7 +13,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
>>>  CONFIG_USB0_ID_DET="PH11"
>>>  CONFIG_USB1_VBUS_PIN="PD24"
>>>  CONFIG_AXP_GPIO=y
>>> -CONFIG_SATAPWR="PD25"
>>>  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>>>  CONFIG_SYS_MONITOR_LEN=786432
>>>  CONFIG_CONSOLE_MUX=y
>>> diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
>>> index 5c7f0731d90..f4ce4851d7c 100644
>>> --- a/configs/orangepi_plus_defconfig
>>> +++ b/configs/orangepi_plus_defconfig
>>> @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672
>>>  CONFIG_MACPWR="PD6"
>>>  CONFIG_MMC_SUNXI_SLOT_EXTRA=2
>>>  CONFIG_USB1_VBUS_PIN="PG13"
>>> -CONFIG_SATAPWR="PG11"  
>>
>> BananaPi M3 and OrangePi Plus have USB-SATA adapters, not onboard AHCI,
>> so they would lose the ability to use SATA with this change.
> 
> Many thanks for having a thorough look, I much appreciate that.
> Of course you are right. I actually found this myself, and thought I
> mentioned it somewhere, but apparently this got lost in between cover
> letter versions and commit messages on different branches. Apologies for
> that.
> So yeah, my research figured that this isn't described properly in the DT,
> so SATA disks just work in Linux because U-Boot flipped the bit here.
> I heard about USB child DT nodes, which IIUC are possible to describe
> errata and such, but I don't think it's a good solution here. Would
> probably need driver changes, so wouldn't be backwards compatible.
> 
>> OrangePi Plus has the SATA controller regulator as usb3_vbus-supply in
>> its devicetree. So we could replace this with CONFIG_USB3_VBUS_PIN for
>> now, and it will continue to work once we switch the PHY driver to use
>> the regulator uclass.
>>
>> But the BananaPi M3 has its USB-SATA downstream from an external hub.
>> CONFIG_USB1_VBUS_PIN is used for the regulator powering the hub, so I do
>> not see an obvious solution here.
> 
> Yeah, I didn't find a neat automatic solution for that either.
> Can we add a regulator-fixed, and make this regulator-boot-on? Without
> actually referencing this regulator anywhere? I need to check this
> actually works in U-Boot, but what do you say with your Linux/DT maintainer
> hat on?

I can think of a few solutions, though none is perfect:

1) As you suggest, add a new fixed regulator with regulator-boot-on. It
also needs regulator-always-on to keep the OS from disabling it later,
since it would have no consumer. We would also need to call
regulators_enable_boot_on() from our board code to enable in in U-Boot.

2) Add a new fixed regulator, and point usb1_vbus-supply to it. Then
have the new regulator reference the hub regulator as its vin-supply.
This would require updating the U-Boot fixed regulator driver to control
its vin-supply. And it is also a misleading use of usb1_vbus-supply.

3) Add a gpio-hog to the devicetree, to unconditionally enable the
regulator. This would be the closest equivalent to what we are doing
now, and the quickest path to getting the legacy board code removed. We
could do this entirely within U-Boot, so I lean toward this solution.

Regards,
Samuel


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 04/17] pinctrl: sunxi: add GPIO in/out wrappers
  2022-12-06  0:45 ` [RFC PATCH 04/17] pinctrl: sunxi: add GPIO in/out wrappers Andre Przywara
@ 2022-12-15  5:59   ` Samuel Holland
  0 siblings, 0 replies; 62+ messages in thread
From: Samuel Holland @ 2022-12-15  5:59 UTC (permalink / raw)
  To: Andre Przywara, Jagan Teki; +Cc: u-boot, Icenowy Zheng, Jernej Skrabec

On 12/5/22 18:45, Andre Przywara wrote:
> So far we were open-coding the pincontroller's GPIO output/input access
> in each function using that.
> 
> Provide two functions that wrap that nicely, so users don't need to know
> about the internals, and we can abstract the new D1 pinctrl more easily.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/include/asm/arch-sunxi/gpio.h |  2 ++
>  arch/arm/mach-sunxi/pinmux.c           | 10 ++++++++++
>  drivers/gpio/sunxi_gpio.c              | 26 +++++---------------------
>  3 files changed, 17 insertions(+), 21 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
> index 8333810a69f..42ca03d8c18 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -211,6 +211,8 @@ void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val);
>  void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
>  int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset);
>  int sunxi_gpio_get_cfgpin(u32 pin);
> +void sunxi_gpio_set_output_bank(void *bank_base, u32 clear_mask, u32 set_mask);
> +u32 sunxi_gpio_get_output_bank(void *bank_base);
>  void sunxi_gpio_set_drv(u32 pin, u32 val);
>  void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val);
>  void sunxi_gpio_set_pull(u32 pin, u32 val);
> diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
> index b650f6b1aea..91acbf9269f 100644
> --- a/arch/arm/mach-sunxi/pinmux.c
> +++ b/arch/arm/mach-sunxi/pinmux.c
> @@ -46,6 +46,16 @@ int sunxi_gpio_get_cfgpin(u32 pin)
>  	return sunxi_gpio_get_cfgbank(bank_base, pin % 32);
>  }
>  
> +void sunxi_gpio_set_output_bank(void *bank_base, u32 clear_mask, u32 set_mask)
> +{
> +	clrsetbits_le32(bank_base + GPIO_DAT_REG_OFFSET, clear_mask, set_mask);
> +}
> +
> +u32 sunxi_gpio_get_output_bank(void *bank_base)
> +{
> +	return readl(bank_base + GPIO_DAT_REG_OFFSET);
> +}
> +
>  void sunxi_gpio_set_drv(u32 pin, u32 val)
>  {
>  	u32 bank = GPIO_BANK(pin);
> diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
> index 1bf691a204a..767996c10fc 100644
> --- a/drivers/gpio/sunxi_gpio.c
> +++ b/drivers/gpio/sunxi_gpio.c
> @@ -21,33 +21,22 @@
>  #if !CONFIG_IS_ENABLED(DM_GPIO)
>  static int sunxi_gpio_output(u32 pin, u32 val)
>  {
> -	u32 dat;
>  	u32 bank = GPIO_BANK(pin);
>  	u32 num = GPIO_NUM(pin);
>  	void *pio = BANK_TO_GPIO(bank);
>  
> -	dat = readl(pio + 0x10);
> -	if (val)
> -		dat |= 0x1 << num;
> -	else
> -		dat &= ~(0x1 << num);
> -
> -	writel(dat, pio + 0x10);
> -
> +	sunxi_gpio_set_output_bank(pio, val ? 0 : 1U << num,
> +					val ? 1U << num : 0);
>  	return 0;
>  }
>  
>  static int sunxi_gpio_input(u32 pin)
>  {
> -	u32 dat;
>  	u32 bank = GPIO_BANK(pin);
>  	u32 num = GPIO_NUM(pin);
>  	void *pio = BANK_TO_GPIO(bank);
>  
> -	dat = readl(pio + 0x10);
> -	dat >>= num;
> -
> -	return dat & 0x1;
> +	return (sunxi_gpio_get_output_bank(pio) >> num) & 0x1;
>  }

I would suggest putting this change before patch 3. And I would suggest
following the existing pattern of functions, with an inner one taking
(bank pointer, pin offset, value), and a wrapper calling BANK_TO_GPIO.
This would consolidate the shifting/masking as well.

If you move these two functions to pinmux.c, then all of the
BANK_TO_GPIO callers are in that file, and you can move BANK_TO_GPIO to
pinmux.c as well when you remove the struct and touch all of the call
sites anyway.

Regards,
Samuel

>  
>  int gpio_request(unsigned gpio, const char *label)
> @@ -136,12 +125,8 @@ static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
>  {
>  	struct sunxi_gpio_plat *plat = dev_get_plat(dev);
>  	u32 num = GPIO_NUM(offset);
> -	unsigned dat;
> -
> -	dat = readl(plat->regs + GPIO_DAT_REG_OFFSET);
> -	dat >>= num;
>  
> -	return dat & 0x1;
> +	return (sunxi_gpio_get_output_bank(plat->regs) >> num) & 0x1;
>  }
>  
>  static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
> @@ -181,8 +166,7 @@ static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset,
>  		u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE);
>  		u32 num = GPIO_NUM(offset);
>  
> -		clrsetbits_le32(plat->regs + GPIO_DAT_REG_OFFSET,
> -				1 << num, value << num);
> +		sunxi_gpio_set_output_bank(plat->regs, 1U << num, value << num);
>  		sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
>  	} else if (flags & GPIOD_IS_IN) {
>  		u32 pull = 0;


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub
  2022-12-06  5:55   ` Icenowy Zheng
@ 2023-01-03 17:38     ` Andre Przywara
  2023-01-04  5:49       ` Icenowy Zheng
  0 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2023-01-03 17:38 UTC (permalink / raw)
  To: Icenowy Zheng; +Cc: Samuel Holland, Jagan Teki, u-boot, Jernej Skrabec

On Tue, 06 Dec 2022 13:55:02 +0800
Icenowy Zheng <uwu@icenowy.me> wrote:

Hi Icenowy,

> 在 2022-12-06星期二的 00:45 +0000，Andre Przywara写道：
> > This adds the basic SoC .dtsi devicetree stub for the Allwinner T113s
> > SoC. This shares a die with the Allwinner D1 SoC (with RISC-V cores),
> > but uses two Cortex-A7 cores instead of the T-HEAD C906 RISC-V core.
> > 
> > Include the existing D1 devicetree stub, but add the ARM specific
> > nodes,
> > like for the CPU, the arch timer and the GIC.
> > 
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> >  arch/arm/dts/sun8i-t113s.dtsi | 59
> > +++++++++++++++++++++++++++++++++++
> >  1 file changed, 59 insertions(+)
> >  create mode 100644 arch/arm/dts/sun8i-t113s.dtsi
> > 
> > diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-
> > t113s.dtsi
> > new file mode 100644
> > index 00000000000..0919ce559f6
> > --- /dev/null
> > +++ b/arch/arm/dts/sun8i-t113s.dtsi
> > @@ -0,0 +1,59 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +// Copyright (C) 2022 Arm Ltd.
> > +
> > +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <../../riscv/dts/sunxi-d1s-t113.dtsi>  
> 
> Should we make a R528 DTSI which includes d1-t113.dtsi, and then T113
> DTSI which includes d1s-t113.dtsi ?

If I understand Samuel correctly, the T113-s includes the DSP, in contrast
to the D1s, which has fused that off.
That would make including both sunxi-d1*-t113.dtsi files the right choice,
wouldn't it? According to Samuel's list, sunxi-d1-t113.dtsi contains DSP
related peripherals.

I don't know if there is anything DT relevant that the R528 has over the
T113-s, but I don't claim to provide an R528 DT anyway, at least not yet,
so we can leave this for the future, should a board or manual emerge.

So this file here should to be the equivalent of sun20i-d1s.dtsi,
providing the ARM specific bits.

Does that make sense? If you agree, I would post this to Linux ASAP.

Cheers,
Andre


> > +#include <../../riscv/dts/sunxi-d1-t113.dtsi>
> > +
> > +/ {
> > +       interrupt-parent = <&gic>;
> > +
> > +       cpus {
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu0: cpu@0 {
> > +                       compatible = "arm,cortex-a7";
> > +                       device_type = "cpu";
> > +                       reg = <0>;
> > +                       clocks = <&ccu CLK_CPUX>;
> > +                       clock-names = "cpu";
> > +               };
> > +
> > +               cpu1: cpu@1 {
> > +                       compatible = "arm,cortex-a7";
> > +                       device_type = "cpu";
> > +                       reg = <1>;
> > +                       clocks = <&ccu CLK_CPUX>;
> > +                       clock-names = "cpu";
> > +               };
> > +       };
> > +
> > +       gic: interrupt-controller@1c81000 {
> > +               compatible = "arm,gic-400";
> > +               reg = <0x03021000 0x1000>,
> > +                     <0x03022000 0x2000>,
> > +                     <0x03024000 0x2000>,
> > +                     <0x03026000 0x2000>;
> > +               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |  
> > IRQ_TYPE_LEVEL_HIGH)>;  
> > +               interrupt-controller;
> > +               #interrupt-cells = <3>;
> > +       };
> > +
> > +       timer {
> > +               compatible = "arm,armv7-timer";
> > +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |  
> > IRQ_TYPE_LEVEL_LOW)>,  
> > +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |  
> > IRQ_TYPE_LEVEL_LOW)>,  
> > +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |  
> > IRQ_TYPE_LEVEL_LOW)>,  
> > +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |  
> > IRQ_TYPE_LEVEL_LOW)>;  
> > +       };
> > +
> > +       pmu {
> > +               compatible = "arm,cortex-a7-pmu";
> > +               interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> > +               interrupt-affinity = <&cpu0>, <&cpu1>;
> > +       };
> > +};  
> 


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub
  2023-01-03 17:38     ` Andre Przywara
@ 2023-01-04  5:49       ` Icenowy Zheng
  0 siblings, 0 replies; 62+ messages in thread
From: Icenowy Zheng @ 2023-01-04  5:49 UTC (permalink / raw)
  To: Andre Przywara; +Cc: Samuel Holland, Jagan Teki, u-boot, Jernej Skrabec

在 2023-01-03星期二的 17:38 +0000，Andre Przywara写道：
> On Tue, 06 Dec 2022 13:55:02 +0800
> Icenowy Zheng <uwu@icenowy.me> wrote:
> 
> Hi Icenowy,
> 
> > 在 2022-12-06星期二的 00:45 +0000，Andre Przywara写道：
> > > This adds the basic SoC .dtsi devicetree stub for the Allwinner
> > > T113s
> > > SoC. This shares a die with the Allwinner D1 SoC (with RISC-V
> > > cores),
> > > but uses two Cortex-A7 cores instead of the T-HEAD C906 RISC-V
> > > core.
> > > 
> > > Include the existing D1 devicetree stub, but add the ARM specific
> > > nodes,
> > > like for the CPU, the arch timer and the GIC.
> > > 
> > > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > > ---
> > >  arch/arm/dts/sun8i-t113s.dtsi | 59
> > > +++++++++++++++++++++++++++++++++++
> > >  1 file changed, 59 insertions(+)
> > >  create mode 100644 arch/arm/dts/sun8i-t113s.dtsi
> > > 
> > > diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-
> > > t113s.dtsi
> > > new file mode 100644
> > > index 00000000000..0919ce559f6
> > > --- /dev/null
> > > +++ b/arch/arm/dts/sun8i-t113s.dtsi
> > > @@ -0,0 +1,59 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > > +// Copyright (C) 2022 Arm Ltd.
> > > +
> > > +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
> > > +
> > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +#include <../../riscv/dts/sunxi-d1s-t113.dtsi>  
> > 
> > Should we make a R528 DTSI which includes d1-t113.dtsi, and then
> > T113
> > DTSI which includes d1s-t113.dtsi ?
> 
> If I understand Samuel correctly, the T113-s includes the DSP, in
> contrast
> to the D1s, which has fused that off.
> That would make including both sunxi-d1*-t113.dtsi files the right
> choice,
> wouldn't it? According to Samuel's list, sunxi-d1-t113.dtsi contains
> DSP
> related peripherals.

Okay, although I heard that the DSP is not fused off (because DSP RAM
is used by BROM).

> 
> I don't know if there is anything DT relevant that the R528 has over
> the
> T113-s, but I don't claim to provide an R528 DT anyway, at least not
> yet,
> so we can leave this for the future, should a board or manual emerge.
> 
> So this file here should to be the equivalent of sun20i-d1s.dtsi,
> providing the ARM specific bits.
> 
> Does that make sense? If you agree, I would post this to Linux ASAP.

It sounds good.

> 
> Cheers,
> Andre
> 
> 
> > > +#include <../../riscv/dts/sunxi-d1-t113.dtsi>
> > > +
> > > +/ {
> > > +       interrupt-parent = <&gic>;
> > > +
> > > +       cpus {
> > > +               #address-cells = <1>;
> > > +               #size-cells = <0>;
> > > +
> > > +               cpu0: cpu@0 {
> > > +                       compatible = "arm,cortex-a7";
> > > +                       device_type = "cpu";
> > > +                       reg = <0>;
> > > +                       clocks = <&ccu CLK_CPUX>;
> > > +                       clock-names = "cpu";
> > > +               };
> > > +
> > > +               cpu1: cpu@1 {
> > > +                       compatible = "arm,cortex-a7";
> > > +                       device_type = "cpu";
> > > +                       reg = <1>;
> > > +                       clocks = <&ccu CLK_CPUX>;
> > > +                       clock-names = "cpu";
> > > +               };
> > > +       };
> > > +
> > > +       gic: interrupt-controller@1c81000 {
> > > +               compatible = "arm,gic-400";
> > > +               reg = <0x03021000 0x1000>,
> > > +                     <0x03022000 0x2000>,
> > > +                     <0x03024000 0x2000>,
> > > +                     <0x03026000 0x2000>;
> > > +               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4)
> > > |  
> > > IRQ_TYPE_LEVEL_HIGH)>;  
> > > +               interrupt-controller;
> > > +               #interrupt-cells = <3>;
> > > +       };
> > > +
> > > +       timer {
> > > +               compatible = "arm,armv7-timer";
> > > +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4)
> > > |  
> > > IRQ_TYPE_LEVEL_LOW)>,  
> > > +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4)
> > > |  
> > > IRQ_TYPE_LEVEL_LOW)>,  
> > > +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4)
> > > |  
> > > IRQ_TYPE_LEVEL_LOW)>,  
> > > +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4)
> > > |  
> > > IRQ_TYPE_LEVEL_LOW)>;  
> > > +       };
> > > +
> > > +       pmu {
> > > +               compatible = "arm,cortex-a7-pmu";
> > > +               interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
> > > +                            <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> > > +               interrupt-affinity = <&cpu0>, <&cpu1>;
> > > +       };
> > > +};  
> > 
> 


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model
  2022-12-06  0:45 ` [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model Andre Przywara
  2022-12-06  5:38   ` Icenowy Zheng
@ 2023-05-16  2:32   ` Sam Edwards
  2023-05-16 21:08     ` Andre Przywara
  2023-06-03 18:03   ` Sam Edwards
  2 siblings, 1 reply; 62+ messages in thread
From: Sam Edwards @ 2023-05-16  2:32 UTC (permalink / raw)
  To: Andre Przywara, Samuel Holland, Jagan Teki
  Cc: u-boot, Icenowy Zheng, Jernej Skrabec

Hi Andre! Thank you for your efforts on this patchset; I've been 
test-driving it a bit myself this week.

On 12/5/22 17:45, Andre Przywara wrote:

> +#define SUNXI_RTC_BASE			0x07000000
> +#define SUNXI_R_CPUCFG_BASE		0x07000400
> +#define SUNXI_PRCM_BASE			0x07010000
> +#define SUNXI_R_WDOG_BASE		0x07020400
> +#define SUNXI_R_UART_BASE		0x07080000
> +#define SUNXI_R_TWI_BASE		0x07081400

How sure are we that this memory map is consistent across the whole 
NCAT2 family? The documentation for my target (T113-S3) puts the RTC 
base at 0x07090000, for example. I find no mention of there being a PRCM 
peripheral in this particular chip either.

> diff --git a/common/spl/Kconfig b/common/spl/Kconfig
> index fef01bdd7da..fdd64db498f 100644
> --- a/common/spl/Kconfig
> +++ b/common/spl/Kconfig
> @@ -265,7 +265,7 @@ config SPL_TEXT_BASE
>   	default 0x402F0400 if AM33XX
>   	default 0x40301350 if OMAP54XX
>   	default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
> -	default 0x20060 if SUN50I_GEN_H6
> +	default 0x20060 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
>   	default 0x00060 if ARCH_SUNXI
>   	default 0xfffc0000 if ARCH_ZYNQMP
>   	default 0x0

Would it also be good to change the default for CONFIG_SPL_STACK? As-is 
it defaults to 0x8000, which would put it in the BROM region. 
Allwinner's boot0 starts its stack at 0x48000, which I've been using.

> diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
> index 2f8b220f750..04d7aa3d632 100644
> --- a/include/sunxi_gpio.h
> +++ b/include/sunxi_gpio.h
> @@ -16,6 +16,9 @@
>   #elif defined(CONFIG_SUN50I_GEN_H6)
>   #define SUNXI_PIO_BASE		0x0300b000
>   #define SUNXI_R_PIO_BASE	0x07022000
> +#elif defined(CONFIG_SUNXI_GEN_NCAT2)
> +#define SUNXI_PIO_BASE		0x02000000
> +#define SUNXI_R_PIO_BASE	0
>   #else
>   #define SUNXI_PIO_BASE		0x01c20800
>   #define SUNXI_R_PIO_BASE	0x01f02c00

Code elsewhere assumes that SUNXI_R_PIO_BASE is nonzero; on my local 
branch in particular I had to update 
arch/arm/mach-sunxi/board.c:gpio_init. Perhaps it would be better to 
leave SUNXI_R_PIO_BASE undefined in the chips where this gadget is missing?

Much gratitude,
Sam

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support
  2022-12-06  0:45 ` [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support Andre Przywara
@ 2023-05-16  2:52   ` Sam Edwards
  2023-05-16 22:01     ` Andre Przywara
  0 siblings, 1 reply; 62+ messages in thread
From: Sam Edwards @ 2023-05-16  2:52 UTC (permalink / raw)
  To: Andre Przywara, Samuel Holland, Jagan Teki
  Cc: u-boot, Icenowy Zheng, Jernej Skrabec

On 12/5/22 17:45, Andre Przywara wrote:
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index 3763ec3d2e4..33331cda5e2 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -148,6 +148,10 @@ static int gpio_init(void)
>   	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
>   	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
>   	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528)
> +	sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6);
> +	sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6);
> +	sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
>   #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
>   	sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
>   	sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);

I'm a relative outsider to sunxi, but it does look like the NCAT2 
generation's MUX is a lot more flexible in its UART assignments: e.g. 
while H3's UART1-3 only had one set of pins each UART could use, the 
T113 (my target) supports anywhere from 2-6 (typically 4) different 
options for each of its UARTs. It is not as simple as configuring which 
UART is the serial console anymore, because different boards might wire 
the console header to different pins. My particular target uses UART3 on 
pins PB6/PB7, for example.

Since this patchset is updating the PIO driver anyway, maybe it's worth 
updating the (preprocessor, not runtime) logic in gpio_init to support 
getting the UART TX/RX pins from Kconfig, validating that the 
CONFIG_CONS_INDEX and pin selection are compatible, and setting the 
correct MUX function for those pins with a value pulled from a table?

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model
  2023-05-16  2:32   ` Sam Edwards
@ 2023-05-16 21:08     ` Andre Przywara
  2023-05-16 23:53       ` Sam Edwards
  0 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2023-05-16 21:08 UTC (permalink / raw)
  To: Sam Edwards
  Cc: Samuel Holland, Jagan Teki, u-boot, Icenowy Zheng, Jernej Skrabec

On Mon, 15 May 2023 20:32:52 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

> Hi Andre! Thank you for your efforts on this patchset; I've been 
> test-driving it a bit myself this week.

many thanks for having a look, that's much appreciated!

> On 12/5/22 17:45, Andre Przywara wrote:
> 
> > +#define SUNXI_RTC_BASE			0x07000000
> > +#define SUNXI_R_CPUCFG_BASE		0x07000400
> > +#define SUNXI_PRCM_BASE			0x07010000
> > +#define SUNXI_R_WDOG_BASE		0x07020400
> > +#define SUNXI_R_UART_BASE		0x07080000
> > +#define SUNXI_R_TWI_BASE		0x07081400  
> 
> How sure are we that this memory map is consistent across the whole 
> NCAT2 family? The documentation for my target (T113-S3) puts the RTC 
> base at 0x07090000, for example. I find no mention of there being a PRCM 
> peripheral in this particular chip either.

This whole memory map is somewhat of a legacy. Apart from a few
addresses for the SPL needs we shouldn't have those defines at all.
Some symbols are needed because there are other macros using them,
although these then are eventually unused.
I have some patches to remove most of the symbols, and patch 14/17
demonstrates some idea how to pin this down to what's really needed.

For this particular case: this was copied from the H6 memory map, some
addresses are just plain wrong for the D1 family. I will try to remove
them as much as possible, leaving only the ones needed in.

> > diff --git a/common/spl/Kconfig b/common/spl/Kconfig
> > index fef01bdd7da..fdd64db498f 100644
> > --- a/common/spl/Kconfig
> > +++ b/common/spl/Kconfig
> > @@ -265,7 +265,7 @@ config SPL_TEXT_BASE
> >   	default 0x402F0400 if AM33XX
> >   	default 0x40301350 if OMAP54XX
> >   	default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
> > -	default 0x20060 if SUN50I_GEN_H6
> > +	default 0x20060 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
> >   	default 0x00060 if ARCH_SUNXI
> >   	default 0xfffc0000 if ARCH_ZYNQMP
> >   	default 0x0  
> 
> Would it also be good to change the default for CONFIG_SPL_STACK? As-is 
> it defaults to 0x8000, which would put it in the BROM region. 
> Allwinner's boot0 starts its stack at 0x48000, which I've been using.

Yeah, well spotted, this was a bug in this early RTC post. I never ran
the SPL, because the DRAM code was missing still. I fixed the stack
pointer meanwhile in an updated (and working) version on Github:
https://github.com/apritzel/u-boot/commit/d5fa559abdf2#diff-19adb575625e29e7a996e0ffb1a266e24239d9b004f17154616220a3f17a24ed

> > diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
> > index 2f8b220f750..04d7aa3d632 100644
> > --- a/include/sunxi_gpio.h
> > +++ b/include/sunxi_gpio.h
> > @@ -16,6 +16,9 @@
> >   #elif defined(CONFIG_SUN50I_GEN_H6)
> >   #define SUNXI_PIO_BASE		0x0300b000
> >   #define SUNXI_R_PIO_BASE	0x07022000
> > +#elif defined(CONFIG_SUNXI_GEN_NCAT2)
> > +#define SUNXI_PIO_BASE		0x02000000
> > +#define SUNXI_R_PIO_BASE	0
> >   #else
> >   #define SUNXI_PIO_BASE		0x01c20800
> >   #define SUNXI_R_PIO_BASE	0x01f02c00  
> 
> Code elsewhere assumes that SUNXI_R_PIO_BASE is nonzero; on my local 
> branch in particular I had to update 
> arch/arm/mach-sunxi/board.c:gpio_init. Perhaps it would be better to 
> leave SUNXI_R_PIO_BASE undefined in the chips where this gadget is missing?

I think leaving it undefined causes more problems, doesn't it? Looking
at #define BANK_TO_GPIO(bank) in
arch/arm/include/asm/arch-sunxi/gpio.h, specifically. I am saying that
because that's what I tried first ;-)

So where did you see problems? If you would (wrongly) reference
PortL somewhere in SPL GPIO code, it would use a wrong pointer, but at
least the code would still compile fine, wouldn't it?

Cheers,
Andre

P.S. Could you try the github post? Then compiled and booted fine for
me, and includes the DRAM code as well now:
https://github.com/apritzel/u-boot/commits/t113s-mq-r-WIP

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support
  2023-05-16  2:52   ` Sam Edwards
@ 2023-05-16 22:01     ` Andre Przywara
  0 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2023-05-16 22:01 UTC (permalink / raw)
  To: Sam Edwards
  Cc: Samuel Holland, Jagan Teki, u-boot, Icenowy Zheng, Jernej Skrabec

On Mon, 15 May 2023 20:52:23 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

> On 12/5/22 17:45, Andre Przywara wrote:
> > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> > index 3763ec3d2e4..33331cda5e2 100644
> > --- a/arch/arm/mach-sunxi/board.c
> > +++ b/arch/arm/mach-sunxi/board.c
> > @@ -148,6 +148,10 @@ static int gpio_init(void)
> >   	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
> >   	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
> >   	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
> > +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528)
> > +	sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6);
> > +	sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6);
> > +	sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
> >   #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
> >   	sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
> >   	sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);  
> 
> I'm a relative outsider to sunxi, but it does look like the NCAT2 
> generation's MUX is a lot more flexible in its UART assignments: e.g. 
> while H3's UART1-3 only had one set of pins each UART could use, the 
> T113 (my target) supports anywhere from 2-6 (typically 4) different 
> options for each of its UARTs. It is not as simple as configuring which 
> UART is the serial console anymore, because different boards might wire 
> the console header to different pins. My particular target uses UART3 on 
> pins PB6/PB7, for example.

Well, theoretically there are indeed quite some options, but in reality
we find that most boards follow some reference design, and the *debug*
UART is only ever using a very few of the possible settings. For the
later (ARMv8) SoCs this is mostly UART0, but for the T113 it's
apparently indeed UART3. I also changed that in the Github version, to
use the very same PB6/7 UART3 mux as you.

> Since this patchset is updating the PIO driver anyway, maybe it's worth 
> updating the (preprocessor, not runtime) logic in gpio_init to support 
> getting the UART TX/RX pins from Kconfig, validating that the 
> CONFIG_CONS_INDEX and pin selection are compatible, and setting the 
> correct MUX function for those pins with a value pulled from a table?

Mmmh, that's an idea one could follow, as this function is indeed
insane. I actually rewrote gpio_init() already, to replace the hard to
read #ifdef's with actual C if statements, though that's still
following the same idea as the current code.
Let me have a look how this would look like.

Cheers,
Andre

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model
  2023-05-16 21:08     ` Andre Przywara
@ 2023-05-16 23:53       ` Sam Edwards
  2023-05-17  0:43         ` Andre Przywara
  0 siblings, 1 reply; 62+ messages in thread
From: Sam Edwards @ 2023-05-16 23:53 UTC (permalink / raw)
  To: Andre Przywara
  Cc: Samuel Holland, Jagan Teki, u-boot, Icenowy Zheng, Jernej Skrabec

On 5/16/23 15:08, Andre Przywara wrote:
> This whole memory map is somewhat of a legacy. Apart from a few
> addresses for the SPL needs we shouldn't have those defines at all.
> Some symbols are needed because there are other macros using them,
> although these then are eventually unused.
> I have some patches to remove most of the symbols, and patch 14/17
> demonstrates some idea how to pin this down to what's really needed.
> 
> For this particular case: this was copied from the H6 memory map, some
> addresses are just plain wrong for the D1 family. I will try to remove
> them as much as possible, leaving only the ones needed in.

I see - the only "tangible" concern I had was the access to 
prcm->res_cal_ctrl done in
arch/arm/mach-sunxi/clock_sun50i_h6.c:clock_init_safe

This doesn't appear to upset the silicon but also doesn't seem necessary 
either -- and with how tight of a memory footprint SPL has to fit into, 
I wanted to check whether this was just something undocumented or dead 
code that needed to be removed. It sounds like it's mostly the latter.

> So where did you see problems? If you would (wrongly) reference
> PortL somewhere in SPL GPIO code, it would use a wrong pointer, but at
> least the code would still compile fine, wouldn't it?

The specific patch I had to apply (to arch/arm/mach-sunxi/board.c) was:
         /* Update PIO power bias configuration by copy hardware 
detected value */
         val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
         writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
-       val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
-       writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+       if (SUNXI_R_PIO_BASE) {
+               val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+               writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+       }

With SUNXI_R_PIO_BASE being 0, this was actually attempting to write to 
BROM. This might also be something that doesn't really upset the 
silicon, though: my debug environment is a concolic emulator I quickly 
hacked up to trace MMIO accesses, and it flagged the write to BROM as an 
error. It was easier to patch the SPL than to have the emulator ignore 
the error (and verify that the T113 was cool with it).

Since this kind of extraneous/erroneous init code tends to remain 
undetected when the symbols they need are dummied-out like this, I 
figured I'd give a nudge in the direction of instead *removing* the 
symbols where appropriate and fixing whatever breaks -- especially since 
we really need to be thrifty about SPL size. But that might also be 
something that happens in a later cleanup pass when the patchset is 
being prepared for upstream inclusion. :)

> P.S. Could you try the github post? Then compiled and booted fine for
> me, and includes the DRAM code as well now:
> https://github.com/apritzel/u-boot/commits/t113s-mq-r-WIP

Ooh, more up-to-date code, thanks for the link! I'll switch to using 
this instead going forward. My pulls from that branch might be 
relatively infrequent since I'm also working on some patches for better 
Clang compatibility concurrent with the efforts here. Is this email 
thread a good venue for feedback against that branch or would you prefer 
that I use GitHub issues instead?

Warm regards,
Sam

P.S. My target is the BMC on the Turing Pi 2 board. They have the same 
SoC and (apparently) UART console configuration, but the differences end 
there: in particular, my target supports boot from either/both 
microSD+SPI-NAND. I might have to start pushing for room for SPI drivers 
in the SPL soon. :)

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model
  2023-05-16 23:53       ` Sam Edwards
@ 2023-05-17  0:43         ` Andre Przywara
  2023-05-17  8:56           ` Andre Przywara
  0 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2023-05-17  0:43 UTC (permalink / raw)
  To: Sam Edwards
  Cc: Samuel Holland, Jagan Teki, u-boot, Icenowy Zheng, Jernej Skrabec

On Tue, 16 May 2023 17:53:38 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

> On 5/16/23 15:08, Andre Przywara wrote:
> > This whole memory map is somewhat of a legacy. Apart from a few
> > addresses for the SPL needs we shouldn't have those defines at all.
> > Some symbols are needed because there are other macros using them,
> > although these then are eventually unused.
> > I have some patches to remove most of the symbols, and patch 14/17
> > demonstrates some idea how to pin this down to what's really needed.
> > 
> > For this particular case: this was copied from the H6 memory map, some
> > addresses are just plain wrong for the D1 family. I will try to remove
> > them as much as possible, leaving only the ones needed in.  
> 
> I see - the only "tangible" concern I had was the access to 
> prcm->res_cal_ctrl done in
> arch/arm/mach-sunxi/clock_sun50i_h6.c:clock_init_safe
> 
> This doesn't appear to upset the silicon but also doesn't seem necessary 
> either -- and with how tight of a memory footprint SPL has to fit into,

What's the particular concern here? Compared to the A64 we are pretty
cool: it's Thumb2 code and we are at around 27KB, at least with my
toolchain. And I haven't tried, but I am pretty sure the BROM
loads more than 32K, as it does on the H6 and H616 already. The U-Boot
build system and the code already supports this - we rely on this for
the H616 - so we can lift the limit anytime, if really needed.

> I wanted to check whether this was just something undocumented or dead 
> code that needed to be removed. It sounds like it's mostly the latter.

I haven't checked if the vendor boot0 does this. I am pretty sure there
is a PRCM block, it's just regularly not mentioned in the manuals.

> > So where did you see problems? If you would (wrongly) reference
> > PortL somewhere in SPL GPIO code, it would use a wrong pointer, but at
> > least the code would still compile fine, wouldn't it?  
> 
> The specific patch I had to apply (to arch/arm/mach-sunxi/board.c) was:
>          /* Update PIO power bias configuration by copy hardware 
> detected value */
>          val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
>          writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> -       val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> -       writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> +       if (SUNXI_R_PIO_BASE) {
> +               val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> +               writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> +       }

Ah, I see, I indeed missed that. We seem to define all symbols anyway,
so we can even lose the #ifdef and use proper if's here.
Will incorporate that in the next drop.

> With SUNXI_R_PIO_BASE being 0, this was actually attempting to write to 
> BROM. This might also be something that doesn't really upset the 
> silicon, though: my debug environment is a concolic emulator I quickly 
> hacked up to trace MMIO accesses, and it flagged the write to BROM as an 
> error. It was easier to patch the SPL than to have the emulator ignore 
> the error (and verify that the T113 was cool with it).

Ah yeah, the Allwinner interconnect is pretty relaxed about those
things: accesses to addresses with no device behind them are usually
ignored (RAZ/WI), where other platform might throw an external abort.
Writes to ROM areas are ignored as well.

> Since this kind of extraneous/erroneous init code tends to remain 
> undetected when the symbols they need are dummied-out like this, I 
> figured I'd give a nudge in the direction of instead *removing* the 
> symbols where appropriate and fixing whatever breaks -- especially since 
> we really need to be thrifty about SPL size. But that might also be 
> something that happens in a later cleanup pass when the patchset is 
> being prepared for upstream inclusion. :)
> 
> > P.S. Could you try the github post? Then compiled and booted fine for
> > me, and includes the DRAM code as well now:
> > https://github.com/apritzel/u-boot/commits/t113s-mq-r-WIP  
> 
> Ooh, more up-to-date code, thanks for the link! I'll switch to using 
> this instead going forward. My pulls from that branch might be 
> relatively infrequent

Don't worry, I won't push to this anymore.

> since I'm also working on some patches for better 
> Clang compatibility concurrent with the efforts here. Is this email 
> thread a good venue for feedback against that branch or would you prefer 
> that I use GitHub issues instead?

Please use this thread here, if you find something still wrong in the
branch. I just pushed it to github since someone asked for a fixed
and complete version, and I didn't have time to prepare a proper post
again.

I will hopefully post a proper version for upstreaming in the next days.


> Warm regards,
> Sam
> 
> P.S. My target is the BMC on the Turing Pi 2 board.

Ah, interesting, didn't know that this is now a BMC - for a
SoC from Allwinner's arch nemesis Rockchip ;-)

> They have the same 
> SoC and (apparently) UART console configuration, but the differences end 
> there: in particular, my target supports boot from either/both 
> microSD+SPI-NAND. I might have to start pushing for room for SPI drivers 
> in the SPL soon. :)

We already have SPI(-NOR) booting support, check
arch/arm/mach-sunxi/spl_spi_sunxi.c. This code is very small, and just
needs to be updated to cover the D1/T113 SPI controller, which is
slightly different. See
https://lore.kernel.org/linux-arm-kernel/20230507150345.1971083-1-bigunclemax@gmail.com/
for the Linux SPI bits.
Regarding SPI-*NAND*: there is
https://patchwork.ozlabs.org/user/todo/uboot/?series=322733
which is supposed to allow loading U-Boot proper from SPI-NAND. I
haven't tested it yet, and wasn't overly happy with the refactoring, but
would appreciate any kind of review or test.

Cheers,
Andre

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model
  2023-05-17  0:43         ` Andre Przywara
@ 2023-05-17  8:56           ` Andre Przywara
  2023-05-17 14:04             ` Maxim Kiselev
  0 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2023-05-17  8:56 UTC (permalink / raw)
  To: Sam Edwards
  Cc: Samuel Holland, Jagan Teki, u-boot, Icenowy Zheng,
	Jernej Skrabec, Maksim Kiselev

On Wed, 17 May 2023 01:43:12 +0100
Andre Przywara <andre.przywara@arm.com> wrote:

+Maksim, as he was interested in the U-Boot series as well and had some
plans for SPI-NOR booting, IIUC.

Cheers,
Andre

> On Tue, 16 May 2023 17:53:38 -0600
> Sam Edwards <cfsworks@gmail.com> wrote:
> 
> Hi Sam,
> 
> > On 5/16/23 15:08, Andre Przywara wrote:  
> > > This whole memory map is somewhat of a legacy. Apart from a few
> > > addresses for the SPL needs we shouldn't have those defines at all.
> > > Some symbols are needed because there are other macros using them,
> > > although these then are eventually unused.
> > > I have some patches to remove most of the symbols, and patch 14/17
> > > demonstrates some idea how to pin this down to what's really needed.
> > > 
> > > For this particular case: this was copied from the H6 memory map, some
> > > addresses are just plain wrong for the D1 family. I will try to remove
> > > them as much as possible, leaving only the ones needed in.    
> > 
> > I see - the only "tangible" concern I had was the access to 
> > prcm->res_cal_ctrl done in
> > arch/arm/mach-sunxi/clock_sun50i_h6.c:clock_init_safe
> > 
> > This doesn't appear to upset the silicon but also doesn't seem necessary 
> > either -- and with how tight of a memory footprint SPL has to fit into,  
> 
> What's the particular concern here? Compared to the A64 we are pretty
> cool: it's Thumb2 code and we are at around 27KB, at least with my
> toolchain. And I haven't tried, but I am pretty sure the BROM
> loads more than 32K, as it does on the H6 and H616 already. The U-Boot
> build system and the code already supports this - we rely on this for
> the H616 - so we can lift the limit anytime, if really needed.
> 
> > I wanted to check whether this was just something undocumented or dead 
> > code that needed to be removed. It sounds like it's mostly the latter.  
> 
> I haven't checked if the vendor boot0 does this. I am pretty sure there
> is a PRCM block, it's just regularly not mentioned in the manuals.
> 
> > > So where did you see problems? If you would (wrongly) reference
> > > PortL somewhere in SPL GPIO code, it would use a wrong pointer, but at
> > > least the code would still compile fine, wouldn't it?    
> > 
> > The specific patch I had to apply (to arch/arm/mach-sunxi/board.c) was:
> >          /* Update PIO power bias configuration by copy hardware 
> > detected value */
> >          val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> >          writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> > -       val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> > -       writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> > +       if (SUNXI_R_PIO_BASE) {
> > +               val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> > +               writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> > +       }  
> 
> Ah, I see, I indeed missed that. We seem to define all symbols anyway,
> so we can even lose the #ifdef and use proper if's here.
> Will incorporate that in the next drop.
> 
> > With SUNXI_R_PIO_BASE being 0, this was actually attempting to write to 
> > BROM. This might also be something that doesn't really upset the 
> > silicon, though: my debug environment is a concolic emulator I quickly 
> > hacked up to trace MMIO accesses, and it flagged the write to BROM as an 
> > error. It was easier to patch the SPL than to have the emulator ignore 
> > the error (and verify that the T113 was cool with it).  
> 
> Ah yeah, the Allwinner interconnect is pretty relaxed about those
> things: accesses to addresses with no device behind them are usually
> ignored (RAZ/WI), where other platform might throw an external abort.
> Writes to ROM areas are ignored as well.
> 
> > Since this kind of extraneous/erroneous init code tends to remain 
> > undetected when the symbols they need are dummied-out like this, I 
> > figured I'd give a nudge in the direction of instead *removing* the 
> > symbols where appropriate and fixing whatever breaks -- especially since 
> > we really need to be thrifty about SPL size. But that might also be 
> > something that happens in a later cleanup pass when the patchset is 
> > being prepared for upstream inclusion. :)
> >   
> > > P.S. Could you try the github post? Then compiled and booted fine for
> > > me, and includes the DRAM code as well now:
> > > https://github.com/apritzel/u-boot/commits/t113s-mq-r-WIP    
> > 
> > Ooh, more up-to-date code, thanks for the link! I'll switch to using 
> > this instead going forward. My pulls from that branch might be 
> > relatively infrequent  
> 
> Don't worry, I won't push to this anymore.
> 
> > since I'm also working on some patches for better 
> > Clang compatibility concurrent with the efforts here. Is this email 
> > thread a good venue for feedback against that branch or would you prefer 
> > that I use GitHub issues instead?  
> 
> Please use this thread here, if you find something still wrong in the
> branch. I just pushed it to github since someone asked for a fixed
> and complete version, and I didn't have time to prepare a proper post
> again.
> 
> I will hopefully post a proper version for upstreaming in the next days.
> 
> 
> > Warm regards,
> > Sam
> > 
> > P.S. My target is the BMC on the Turing Pi 2 board.  
> 
> Ah, interesting, didn't know that this is now a BMC - for a
> SoC from Allwinner's arch nemesis Rockchip ;-)
> 
> > They have the same 
> > SoC and (apparently) UART console configuration, but the differences end 
> > there: in particular, my target supports boot from either/both 
> > microSD+SPI-NAND. I might have to start pushing for room for SPI drivers 
> > in the SPL soon. :)  
> 
> We already have SPI(-NOR) booting support, check
> arch/arm/mach-sunxi/spl_spi_sunxi.c. This code is very small, and just
> needs to be updated to cover the D1/T113 SPI controller, which is
> slightly different. See
> https://lore.kernel.org/linux-arm-kernel/20230507150345.1971083-1-bigunclemax@gmail.com/
> for the Linux SPI bits.
> Regarding SPI-*NAND*: there is
> https://patchwork.ozlabs.org/user/todo/uboot/?series=322733
> which is supposed to allow loading U-Boot proper from SPI-NAND. I
> haven't tested it yet, and wasn't overly happy with the refactoring, but
> would appreciate any kind of review or test.
> 
> Cheers,
> Andre


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model
  2023-05-17  8:56           ` Andre Przywara
@ 2023-05-17 14:04             ` Maxim Kiselev
  2023-05-25 18:25               ` Maksim Kiselev
  0 siblings, 1 reply; 62+ messages in thread
From: Maxim Kiselev @ 2023-05-17 14:04 UTC (permalink / raw)
  To: Andre Przywara
  Cc: Sam Edwards, Samuel Holland, Jagan Teki, u-boot, Icenowy Zheng,
	Jernej Skrabec

Hi Sam,

> I might have to start pushing for room for SPI drivers
> in the SPL soon. :)

As Andre already pointed out, I have a patch which adds boot support
from SPI-NOR for D1/T113 SoCs.
Maybe I can share it somewhere to avoid double work?

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU
  2022-12-06  0:45 ` [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU Andre Przywara
@ 2023-05-22  3:57   ` Sam Edwards
  2023-05-24  0:58     ` Andre Przywara
  2023-05-26  0:34   ` Sam Edwards
  1 sibling, 1 reply; 62+ messages in thread
From: Sam Edwards @ 2023-05-22  3:57 UTC (permalink / raw)
  To: Andre Przywara, Samuel Holland, Jagan Teki
  Cc: u-boot, Icenowy Zheng, Jernej Skrabec

On 12/5/22 17:45, Andre Przywara wrote:
> From: Samuel Holland <samuel@sholland.org>
> 
> Since the D1 CCU binding is defined, we can add support for its
> gates/resets, following the pattern of the existing drivers.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> Acked-by: Sean Anderson <seanga2@gmail.com>

Hi Andre,

So far so good! This patchset seems pretty functional. I'm still trying 
to get various peripherals on my board up and running; there are a 
couple of rough edges I'm encountering. I'll report back when I have a 
build I like.

In particular, I had to update this patch in your series to be 
consistent with 46fa23f9ee. My own patch follows.

I'd also suggest adding to `mangopi_mq_r_defconfig`:
CONFIG_CLK_SUN20I_D1=y
...or, better yet, an appropriate `select` in Kconfig?

Cheers,
Sam

--

diff --git a/drivers/clk/sunxi/clk_d1.c b/drivers/clk/sunxi/clk_d1.c
index 9412b77a54..f4ff682566 100644
--- a/drivers/clk/sunxi/clk_d1.c
+++ b/drivers/clk/sunxi/clk_d1.c
@@ -74,28 +74,9 @@ static struct ccu_reset d1_resets[] = {
  	[RST_BUS_LRADC]		= RESET(0xa9c, BIT(16)),
  };

-static const struct ccu_desc d1_ccu_desc = {
+const struct ccu_desc d1_ccu_desc = {
  	.gates	= d1_gates,
  	.resets	= d1_resets,
-};
-
-static int d1_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(d1_resets));
-}
-
-static const struct udevice_id d1_ccu_ids[] = {
-	{ .compatible = "allwinner,sun20i-d1-ccu",
-	  .data = (ulong)&d1_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun20i_d1) = {
-	.name		= "sun20i_d1_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= d1_ccu_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= d1_clk_bind,
+	.num_gates  = ARRAY_SIZE(d1_gates),
+	.num_resets = ARRAY_SIZE(d1_resets),
  };
diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index ec02a2d037..176d3cbc28 100644
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -125,6 +125,7 @@ extern const struct ccu_desc h616_ccu_desc;
  extern const struct ccu_desc h6_r_ccu_desc;
  extern const struct ccu_desc r40_ccu_desc;
  extern const struct ccu_desc v3s_ccu_desc;
+extern const struct ccu_desc d1_ccu_desc;

  static const struct udevice_id sunxi_clk_ids[] = {
  #ifdef CONFIG_CLK_SUN4I_A10
@@ -214,6 +215,10 @@ static const struct udevice_id sunxi_clk_ids[] = {
  #ifdef CONFIG_CLK_SUNIV_F1C100S
  	{ .compatible = "allwinner,suniv-f1c100s-ccu",
  	  .data = (ulong)&f1c100s_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN20I_D1
+	{ .compatible = "allwinner,sun20i-d1-ccu",
+	  .data = (ulong)&d1_ccu_desc },
  #endif
  	{ }
  };

^ permalink raw reply related	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU
  2023-05-22  3:57   ` Sam Edwards
@ 2023-05-24  0:58     ` Andre Przywara
  0 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2023-05-24  0:58 UTC (permalink / raw)
  To: Sam Edwards
  Cc: Samuel Holland, Jagan Teki, u-boot, Icenowy Zheng, Jernej Skrabec

On Sun, 21 May 2023 21:57:57 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

> On 12/5/22 17:45, Andre Przywara wrote:
> > From: Samuel Holland <samuel@sholland.org>
> > 
> > Since the D1 CCU binding is defined, we can add support for its
> > gates/resets, following the pattern of the existing drivers.
> > 
> > Signed-off-by: Samuel Holland <samuel@sholland.org>
> > Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> > Acked-by: Sean Anderson <seanga2@gmail.com>  
> 
> Hi Andre,
> 
> So far so good! This patchset seems pretty functional. I'm still trying 
> to get various peripherals on my board up and running; there are a 
> couple of rough edges I'm encountering. I'll report back when I have a 
> build I like.
> 
> In particular, I had to update this patch in your series to be 
> consistent with 46fa23f9ee. My own patch follows.

Ah, yeah, Samuel's rework. Thanks for the heads up, I somehow missed
that when updating the series!

> I'd also suggest adding to `mangopi_mq_r_defconfig`:
> CONFIG_CLK_SUN20I_D1=y
> ...or, better yet, an appropriate `select` in Kconfig?

I think this is related to the rework, I just added a "default
MACH_SUN8I_R528" line to the clock's Kconfig, similar to what we
already do for the pinctrl driver.

I merged the changes into the respective patch.

Please note that I also found a build bug for 64-bit SoCs, and that the
new DRAM driver's Kconfig symbols conflict with the already used
symbols for other DRAM drivers (like the A64 one). This broke the A64
DRAM init routine, for instance.

If the tests work well, I will try to post some proper version ASAP. If
not, I will probably just push some updated WIP version to my Github.

Thanks,
Andre


> --
> 
> diff --git a/drivers/clk/sunxi/clk_d1.c b/drivers/clk/sunxi/clk_d1.c
> index 9412b77a54..f4ff682566 100644
> --- a/drivers/clk/sunxi/clk_d1.c
> +++ b/drivers/clk/sunxi/clk_d1.c
> @@ -74,28 +74,9 @@ static struct ccu_reset d1_resets[] = {
>   	[RST_BUS_LRADC]		= RESET(0xa9c, BIT(16)),
>   };
> 
> -static const struct ccu_desc d1_ccu_desc = {
> +const struct ccu_desc d1_ccu_desc = {
>   	.gates	= d1_gates,
>   	.resets	= d1_resets,
> -};
> -
> -static int d1_clk_bind(struct udevice *dev)
> -{
> -	return sunxi_reset_bind(dev, ARRAY_SIZE(d1_resets));
> -}
> -
> -static const struct udevice_id d1_ccu_ids[] = {
> -	{ .compatible = "allwinner,sun20i-d1-ccu",
> -	  .data = (ulong)&d1_ccu_desc },
> -	{ }
> -};
> -
> -U_BOOT_DRIVER(clk_sun20i_d1) = {
> -	.name		= "sun20i_d1_ccu",
> -	.id		= UCLASS_CLK,
> -	.of_match	= d1_ccu_ids,
> -	.priv_auto	= sizeof(struct ccu_priv),
> -	.ops		= &sunxi_clk_ops,
> -	.probe		= sunxi_clk_probe,
> -	.bind		= d1_clk_bind,
> +	.num_gates  = ARRAY_SIZE(d1_gates),
> +	.num_resets = ARRAY_SIZE(d1_resets),
>   };
> diff --git a/drivers/clk/sunxi/clk_sunxi.c
> b/drivers/clk/sunxi/clk_sunxi.c index ec02a2d037..176d3cbc28 100644
> --- a/drivers/clk/sunxi/clk_sunxi.c
> +++ b/drivers/clk/sunxi/clk_sunxi.c
> @@ -125,6 +125,7 @@ extern const struct ccu_desc h616_ccu_desc;
>   extern const struct ccu_desc h6_r_ccu_desc;
>   extern const struct ccu_desc r40_ccu_desc;
>   extern const struct ccu_desc v3s_ccu_desc;
> +extern const struct ccu_desc d1_ccu_desc;
> 
>   static const struct udevice_id sunxi_clk_ids[] = {
>   #ifdef CONFIG_CLK_SUN4I_A10
> @@ -214,6 +215,10 @@ static const struct udevice_id sunxi_clk_ids[] =
> { #ifdef CONFIG_CLK_SUNIV_F1C100S
>   	{ .compatible = "allwinner,suniv-f1c100s-ccu",
>   	  .data = (ulong)&f1c100s_ccu_desc },
> +#endif
> +#ifdef CONFIG_CLK_SUN20I_D1
> +	{ .compatible = "allwinner,sun20i-d1-ccu",
> +	  .data = (ulong)&d1_ccu_desc },
>   #endif
>   	{ }
>   };


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model
  2023-05-17 14:04             ` Maxim Kiselev
@ 2023-05-25 18:25               ` Maksim Kiselev
  2023-05-26 11:05                 ` Andre Przywara
  0 siblings, 1 reply; 62+ messages in thread
From: Maksim Kiselev @ 2023-05-25 18:25 UTC (permalink / raw)
  To: Andre Przywara
  Cc: Sam Edwards, Samuel Holland, Jagan Teki, u-boot, Icenowy Zheng,
	Jernej Skrabec

Hi, Andre

Could you please include this fix for i2c in the next version of this 
series.

diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 93bbc6916e..d088ea75b9 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -124,7 +124,7 @@ enum mvtwsi_ctrl_register_fields {
   * on other platforms, it is a normal r/w bit, which is cleared by 
writing 0.
   */

-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || 
defined(CONFIG_SUNXI_GEN_NCAT2)
  #define        MVTWSI_CONTROL_CLEAR_IFLG       0x00000008
  #else
  #define        MVTWSI_CONTROL_CLEAR_IFLG       0x00000000


^ permalink raw reply related	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU
  2022-12-06  0:45 ` [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU Andre Przywara
  2023-05-22  3:57   ` Sam Edwards
@ 2023-05-26  0:34   ` Sam Edwards
  2023-05-26 10:50     ` Andre Przywara
  1 sibling, 1 reply; 62+ messages in thread
From: Sam Edwards @ 2023-05-26  0:34 UTC (permalink / raw)
  To: u-boot, Andre Przywara

Hi again Andre,

On 12/5/22 17:45, Andre Przywara wrote:
> +static struct ccu_clk_gate d1_gates[] = {
> +	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
> +	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
> +	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
> +	[CLK_BUS_UART0]		= GATE(0x90c, BIT(0)),
> +	[CLK_BUS_UART1]		= GATE(0x90c, BIT(1)),
> +	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
> +	[CLK_BUS_UART3]		= GATE(0x90c, BIT(3)),
> +	[CLK_BUS_UART4]		= GATE(0x90c, BIT(4)),
> +	[CLK_BUS_UART5]		= GATE(0x90c, BIT(5)),
> +	[CLK_BUS_I2C0]		= GATE(0x91c, BIT(0)),
> +	[CLK_BUS_I2C1]		= GATE(0x91c, BIT(1)),
> +	[CLK_BUS_I2C2]		= GATE(0x91c, BIT(2)),
> +	[CLK_BUS_I2C3]		= GATE(0x91c, BIT(3)),
> +	[CLK_SPI0]		= GATE(0x940, BIT(31)),
> +	[CLK_SPI1]		= GATE(0x944, BIT(31)),
> +	[CLK_BUS_SPI0]		= GATE(0x96c, BIT(0)),
> +	[CLK_BUS_SPI1]		= GATE(0x96c, BIT(1)),
> +
> +	[CLK_BUS_EMAC]		= GATE(0x97c, BIT(0)),
> +
> +	[CLK_USB_OHCI0]		= GATE(0xa70, BIT(31)),
> +	[CLK_USB_OHCI1]		= GATE(0xa74, BIT(31)),
> +	[CLK_BUS_OHCI0]		= GATE(0xa8c, BIT(0)),
> +	[CLK_BUS_OHCI1]		= GATE(0xa8c, BIT(1)),
> +	[CLK_BUS_EHCI0]		= GATE(0xa8c, BIT(4)),
> +	[CLK_BUS_EHCI1]		= GATE(0xa8c, BIT(5)),
> +	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
> +	[CLK_BUS_LRADC]		= GATE(0xa9c, BIT(0)),
> +
> +	[CLK_RISCV]		= GATE(0xd04, BIT(31)),
> +};

Would it be reasonable to add (possibly one for APB1 also):
[CLK_APB0] = GATE_DUMMY,

...in order to suppress this warning at init:
sunxi_set_gate: (CLK#24) unhandled

As I understand it, CLK_APB0 is only for speed control and doesn't have 
a gate, but since the FDT references it, other drivers are asking the 
clock driver to ungate it, resulting in that (safe-to-ignore) warning.

Warm regards,
Sam

PS: Do you have any plans for PSCI support, so we can get the second 
core up too? I'd like to patch that in and include it in your series 
once my available time permits. Just thought I'd check that you/someone 
wasn't working on it already. :)

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU
  2023-05-26  0:34   ` Sam Edwards
@ 2023-05-26 10:50     ` Andre Przywara
  2023-05-26 19:27       ` Maksim Kiselev
  0 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2023-05-26 10:50 UTC (permalink / raw)
  To: Sam Edwards; +Cc: u-boot

On Thu, 25 May 2023 18:34:45 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

thanks for staying on this!

> On 12/5/22 17:45, Andre Przywara wrote:
> > +static struct ccu_clk_gate d1_gates[] = {
> > +	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
> > +	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
> > +	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
> > +	[CLK_BUS_UART0]		= GATE(0x90c, BIT(0)),
> > +	[CLK_BUS_UART1]		= GATE(0x90c, BIT(1)),
> > +	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
> > +	[CLK_BUS_UART3]		= GATE(0x90c, BIT(3)),
> > +	[CLK_BUS_UART4]		= GATE(0x90c, BIT(4)),
> > +	[CLK_BUS_UART5]		= GATE(0x90c, BIT(5)),
> > +	[CLK_BUS_I2C0]		= GATE(0x91c, BIT(0)),
> > +	[CLK_BUS_I2C1]		= GATE(0x91c, BIT(1)),
> > +	[CLK_BUS_I2C2]		= GATE(0x91c, BIT(2)),
> > +	[CLK_BUS_I2C3]		= GATE(0x91c, BIT(3)),
> > +	[CLK_SPI0]		= GATE(0x940, BIT(31)),
> > +	[CLK_SPI1]		= GATE(0x944, BIT(31)),
> > +	[CLK_BUS_SPI0]		= GATE(0x96c, BIT(0)),
> > +	[CLK_BUS_SPI1]		= GATE(0x96c, BIT(1)),
> > +
> > +	[CLK_BUS_EMAC]		= GATE(0x97c, BIT(0)),
> > +
> > +	[CLK_USB_OHCI0]		= GATE(0xa70, BIT(31)),
> > +	[CLK_USB_OHCI1]		= GATE(0xa74, BIT(31)),
> > +	[CLK_BUS_OHCI0]		= GATE(0xa8c, BIT(0)),
> > +	[CLK_BUS_OHCI1]		= GATE(0xa8c, BIT(1)),
> > +	[CLK_BUS_EHCI0]		= GATE(0xa8c, BIT(4)),
> > +	[CLK_BUS_EHCI1]		= GATE(0xa8c, BIT(5)),
> > +	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
> > +	[CLK_BUS_LRADC]		= GATE(0xa9c, BIT(0)),
> > +
> > +	[CLK_RISCV]		= GATE(0xd04, BIT(31)),
> > +};  
> 
> Would it be reasonable to add (possibly one for APB1 also):
> [CLK_APB0] = GATE_DUMMY,
> 
> ...in order to suppress this warning at init:
> sunxi_set_gate: (CLK#24) unhandled

Yeah, seems like we are working in lockstep, as I found and fixed the
very same issue in the very same way on Wednesday ;-)

> As I understand it, CLK_APB0 is only for speed control and doesn't have 
> a gate, but since the FDT references it, other drivers are asking the 
> clock driver to ungate it, resulting in that (safe-to-ignore) warning.

The APB0 bus transports register accesses to a certain subset of "low
speed" peripherals, Those peripherals include the clock control unit
(CCU) itself, and the GPIO registers, so it's quite essential for
normal operation. CLK_APB0 is the clock driving that bus, and as it's
controlled via the CCU, you just cannot turn that off. Check "Figure
3-3 System bus tree" in the manual.

Linux never really touches that clock (for said reasons), and Allwinner
recommends a certain frequency, which we set up in the SPL.

So to not boil the ocean here for something that doesn't need control
anyway, we just introduced those "dummy gates", to appease U-Boot's
clock framework and avoid that warning.

Long story short: you did everything right ;-)

> PS: Do you have any plans for PSCI support, so we can get the second 
> core up too? I'd like to patch that in and include it in your series 
> once my available time permits. Just thought I'd check that you/someone 
> wasn't working on it already. :)

I checked the manuals, and it seems the required bits are documented,
but IIRC they differ from the other (much older) 32-bit parts. So it
would require some refactoring of the existing sunxi PSCI code to
accommodate the T113.
That's not really a problem, but I didn't find time yet to tackle this,
so if you want to beat me on it: be my guest.
For the basic operation SMP is not essential, so I don't want to let
that hold back the T113 U-Boot support in general. The plan is to have
an extra patch on top for PSCI, and merge that when it's ready - which
could be together with the basic support, if we get it done on time.

Cheers,
Andre


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model
  2023-05-25 18:25               ` Maksim Kiselev
@ 2023-05-26 11:05                 ` Andre Przywara
  0 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2023-05-26 11:05 UTC (permalink / raw)
  To: Maksim Kiselev
  Cc: Sam Edwards, Samuel Holland, Jagan Teki, u-boot, Icenowy Zheng,
	Jernej Skrabec

On Thu, 25 May 2023 21:25:57 +0300
Maksim Kiselev <bigunclemax@gmail.com> wrote:

Hi Maksim,

> Could you please include this fix for i2c in the next version of this 
> series.
> 
> diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
> index 93bbc6916e..d088ea75b9 100644
> --- a/drivers/i2c/mvtwsi.c
> +++ b/drivers/i2c/mvtwsi.c
> @@ -124,7 +124,7 @@ enum mvtwsi_ctrl_register_fields {
>    * on other platforms, it is a normal r/w bit, which is cleared by 
> writing 0.
>    */
> 
> -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
> +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || 
> defined(CONFIG_SUNXI_GEN_NCAT2)

Ah, thanks for pointing this out, I never really tried I2C, I think.
So those code lines are of course hideous to begin with, but it's a
nightmare to fix this properly (by looking at the DT compatible
string), and we might need it for the SPL anyway, so would need
something like this anyway.
So I will just go ahead and add this to this patch.

Thanks for the report!

Cheers,
Andre

>   #define        MVTWSI_CONTROL_CLEAR_IFLG       0x00000008
>   #else
>   #define        MVTWSI_CONTROL_CLEAR_IFLG       0x00000000
> 


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU
  2023-05-26 10:50     ` Andre Przywara
@ 2023-05-26 19:27       ` Maksim Kiselev
  2023-05-26 20:22         ` Sam Edwards
  0 siblings, 1 reply; 62+ messages in thread
From: Maksim Kiselev @ 2023-05-26 19:27 UTC (permalink / raw)
  To: Andre Przywara, Sam Edwards; +Cc: u-boot

Hi Sam, Andre,

On Thu, 25 May 2023 18:34:45 -0600 Sam Edwards <cfsworks@gmail.com> wrote:

> PS: Do you have any plans for PSCI support, so we can get the second
> core up too? I'd like to patch that in and include it in your series
> once my available time permits. Just thought I'd check that you/someone
> wasn't working on it already. :)
Let me join the PSCI discussion. This is not news, but maybe someone 
else didn't know it :)

There is a Linux patch that allows to bring up the second core.
https://github.com/szemzoa/awboot/blob/6ea4ae4ad7a558ad952fefee1942e260aea1a69f/linux/second_core_support_in_platsmp.patch#L10

I think this could be useful for adding PSCI support for T113.

On 26.05.2023 13:50, Andre Przywara wrote:
> I checked the manuals, and it seems the required bits are documented,
> but IIRC they differ from the other (much older) 32-bit parts. So it
> would require some refactoring of the existing sunxi PSCI code to
> accommodate the T113.
For some reason, these registers 0x070005C0, 0x070005C4, 0x070005C8 do 
not have a detailed description in the user manual.
Only there are some notes in the paragraph '3.4.2.3 NON_CPU0 Boot Process' .

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU
  2023-05-26 19:27       ` Maksim Kiselev
@ 2023-05-26 20:22         ` Sam Edwards
  2023-05-26 22:07           ` Andre Przywara
  0 siblings, 1 reply; 62+ messages in thread
From: Sam Edwards @ 2023-05-26 20:22 UTC (permalink / raw)
  To: Maksim Kiselev, Andre Przywara; +Cc: u-boot

Hi folks,

On 5/26/23 13:27, Maksim Kiselev wrote:
> 
> There is a Linux patch that allows to bring up the second core.
> https://github.com/szemzoa/awboot/blob/6ea4ae4ad7a558ad952fefee1942e260aea1a69f/linux/second_core_support_in_platsmp.patch#L10
> 
> I think this could be useful for adding PSCI support for T113.

I'm a little surprised that apparently all that is necessary is to set 
the entry point and deassert reset. I've been trying essentially that so 
far with no success (entirely possible I made a mistake somewhere). 
Perhaps this patch assumes that power to the core is enabled before 
kernel boot? I haven't yet figured out what in the PRCM I need to poke 
to get power to the core, and the PRCM for this chip is not well-documented.

On 5/26/23 04:50, Andre Przywara wrote:
 > I checked the manuals, and it seems the required bits are documented,
 > but IIRC they differ from the other (much older) 32-bit parts. So it
 > would require some refactoring of the existing sunxi PSCI code to
 > accommodate the T113.

Yeah, I decided to factor out the register-manipulating bits to a 
handful of sunxi_cpu_set_* functions, which can be switched out to suit 
the specific SoC in use. psci.c is growing way too many #ifdef branches, 
so I might refactor this yet again to the "weak symbols with strong 
overrides in e.g. psci-r528.c" pattern, unless you find that pattern 
particularly distasteful.

I have my WIP diff below. Before inclusion, I'll split it into multiple 
patches (refactoring -> adding R528 support) but it's definitely not 
ready for that yet. However if you could, it would help if you checked 
my changes to cpu_sunxi_ncat2.h and squashed them into your own series 
if they look good to you.

Cheers,
Sam

---
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c 
b/arch/arm/cpu/armv7/sunxi/psci.c
index e1d3638b5c..02c5c56c86 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -38,6 +38,8 @@
  #define SUN8I_R40_PWR_CLAMP(cpu)		(0x120 + (cpu) * 0x4)
  #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0		(0xbc)

+#define SUN8I_R528_SOFT_ENTRY			(0x1c8)
+
  static void __secure cp15_write_cntp_tval(u32 tval)
  {
  	asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@@ -125,6 +127,13 @@ static void __secure sunxi_set_entry_address(void 
*entry)
  	writel((u32)entry,
  	       SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
  }
+#elif defined CONFIG_MACH_SUN8I_R528
+/* secondary core entry address is programmed differently on R528 */
+static void __secure sunxi_set_entry_address(void *entry)
+{
+	writel((u32)entry,
+	       SUNXI_R_CPUCFG_BASE + SUN8I_R528_SOFT_ENTRY);
+}
  #else
  static void __secure sunxi_set_entry_address(void *entry)
  {
@@ -155,6 +164,10 @@ static void __secure sunxi_cpu_set_power(int cpu, 
bool on)
  			   (void *)cpucfg + SUN8I_R40_PWROFF,
  			   on, cpu);
  }
+#elif defined CONFIG_MACH_SUN8I_R528
+static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool 
__always_unused on)
+{
+}
  #else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
  static void __secure sunxi_cpu_set_power(int cpu, bool on)
  {
@@ -166,30 +179,91 @@ static void __secure sunxi_cpu_set_power(int cpu, 
bool on)
  }
  #endif /* CONFIG_MACH_SUN7I */

-void __secure sunxi_cpu_power_off(u32 cpuid)
+#ifdef CONFIG_MACH_SUN8I_R528
+#define C0_RST_CTRL	0x0000
+#define C0_CTRL_REG0	0x0010
+#define C0_CPU_STATUS	0x0080
+
+#define C0_BIT_WFI	16
+
+static void __secure sunxi_cpu_set_reset(int cpu, bool active)
+{
+	if (active)
+		clrbits_le32(SUNXI_CPUX_BASE + C0_RST_CTRL, BIT(cpu));
+	else
+		setbits_le32(SUNXI_CPUX_BASE + C0_RST_CTRL, BIT(cpu));
+}
+
+static void __secure sunxi_cpu_set_locking(int cpu, bool lock)
+{
+	/* TODO: I don't know what this is or how to do it */
+}
+
+static bool __secure sunxi_cpu_poll_wfi(int cpu)
+{
+	return !!(readl(SUNXI_CPUX_BASE + C0_CPU_STATUS) & BIT(C0_BIT_WFI + cpu));
+}
+
+static void __secure sunxi_cpu_invalidate_cache(int cpu)
+{
+	clrbits_le32(SUNXI_CPUX_BASE + C0_CTRL_REG0, BIT(cpu));
+}
+#else /* ! CONFIG_MACH_SUN8I_R528 */
+static void __secure sunxi_cpu_set_reset(int cpu, bool active)
+{
+	struct sunxi_cpucfg_reg *cpucfg =
+		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+	writel(active ? 0b00 : 0b11, &cpucfg->cpu[cpu].rst);
+}
+
+static void __secure sunxi_cpu_set_locking(int cpu, bool lock)
  {
  	struct sunxi_cpucfg_reg *cpucfg =
  		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+	if (lock)
+		clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+	else
+		setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+}
+
+static bool __secure sunxi_cpu_poll_wfi(int cpu)
+{
+	struct sunxi_cpucfg_reg *cpucfg =
+		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+	return !!(readl(&cpucfg->cpu[cpu].status) & BIT(2));
+}
+
+static void __secure sunxi_cpu_invalidate_cache(int cpu)
+{
+	struct sunxi_cpucfg_reg *cpucfg =
+		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+	clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
+}
+#endif
+
+void __secure sunxi_cpu_power_off(u32 cpuid)
+{
  	u32 cpu = cpuid & 0x3;

  	/* Wait for the core to enter WFI */
-	while (1) {
-		if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
-			break;
+	while (!sunxi_cpu_poll_wfi(cpu))
  		__mdelay(1);
-	}

  	/* Assert reset on target CPU */
-	writel(0, &cpucfg->cpu[cpu].rst);
+	sunxi_cpu_set_reset(cpu, true);

  	/* Lock CPU (Disable external debug access) */
-	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+	sunxi_cpu_set_locking(cpu, true);

  	/* Power down CPU */
  	sunxi_cpu_set_power(cpuid, false);

-	/* Unlock CPU (Disable external debug access) */
-	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+	/* Unlock CPU (Reenable external debug access) */
+	sunxi_cpu_set_locking(cpu, false);
  }

  static u32 __secure cp15_read_scr(void)
@@ -246,8 +320,6 @@ out:
  int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
  			 u32 context_id)
  {
-	struct sunxi_cpucfg_reg *cpucfg =
-		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
  	u32 cpu = (mpidr & 0x3);

  	/* store target PC and context id */
@@ -257,22 +329,22 @@ int __secure psci_cpu_on(u32 __always_unused 
unused, u32 mpidr, u32 pc,
  	sunxi_set_entry_address(&psci_cpu_entry);

  	/* Assert reset on target CPU */
-	writel(0, &cpucfg->cpu[cpu].rst);
+	sunxi_cpu_set_reset(cpu, true);

  	/* Invalidate L1 cache */
-	clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
+	sunxi_cpu_invalidate_cache(cpu);

  	/* Lock CPU (Disable external debug access) */
-	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+	sunxi_cpu_set_locking(cpu, true);

  	/* Power up target CPU */
  	sunxi_cpu_set_power(cpu, true);

  	/* De-assert reset on target CPU */
-	writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
+	sunxi_cpu_set_reset(cpu, false);

-	/* Unlock CPU (Disable external debug access) */
-	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+	/* Unlock CPU (Reenable external debug access) */
+	sunxi_cpu_set_locking(cpu, false);

  	return ARM_PSCI_RET_SUCCESS;
  }
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
index d01508517c..629d761aa6 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
@@ -17,6 +17,8 @@
  #define SUNXI_SIDC_BASE			0x03006000
  #define SUNXI_SID_BASE			0x03006200
  #define SUNXI_TIMER_BASE		0x02050000
+#define SUNXI_GIC400_BASE		0x03020000
+#define SUNXI_CPUX_BASE			0x09010000

  #ifdef CONFIG_MACH_SUN50I_H6
  #define SUNXI_DRAM_COM_BASE		0x04002000
@@ -34,11 +36,11 @@
  #define SUNXI_SPI0_BASE			0x04025000
  #define SUNXI_SPI1_BASE			0x04026000

-#define SUNXI_RTC_BASE			0x07000000
  #define SUNXI_R_CPUCFG_BASE		0x07000400
  #define SUNXI_PRCM_BASE			0x07010000
  #define SUNXI_R_WDOG_BASE		0x07020400
-#define SUNXI_R_TWI_BASE		0x07081400
+#define SUNXI_R_TWI_BASE		0x07020800
+#define SUNXI_RTC_BASE			0x07090000

  #ifndef __ASSEMBLY__
  void sunxi_board_init(void);
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index bb9b863d2c..a5d312d377 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -366,6 +366,8 @@ config MACH_SUN8I_R40
  config MACH_SUN8I_R528
  	bool "sun8i (Allwinner R528)"
  	select CPU_V7A
+	select CPU_V7_HAS_NONSEC
+	select ARCH_SUPPORT_PSCI
  	select SUNXI_GEN_NCAT2
  	select SUNXI_NEW_PINCTRL
  	select MMC_SUNXI_HAS_NEW_MODE

^ permalink raw reply related	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU
  2023-05-26 20:22         ` Sam Edwards
@ 2023-05-26 22:07           ` Andre Przywara
  2023-05-27  2:15             ` Sam Edwards
  0 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2023-05-26 22:07 UTC (permalink / raw)
  To: Sam Edwards; +Cc: Maksim Kiselev, u-boot

On Fri, 26 May 2023 14:22:29 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

> On 5/26/23 13:27, Maksim Kiselev wrote:
> > 
> > There is a Linux patch that allows to bring up the second core.
> > https://github.com/szemzoa/awboot/blob/6ea4ae4ad7a558ad952fefee1942e260aea1a69f/linux/second_core_support_in_platsmp.patch#L10
> > 
> > I think this could be useful for adding PSCI support for T113.  
> 
> I'm a little surprised that apparently all that is necessary is to set 
> the entry point and deassert reset. I've been trying essentially that so 
> far with no success (entirely possible I made a mistake somewhere). 

So with "no success" you are referring to the patch below? Which is the
Linux patch ported to U-Boot? And does that mean that the Linux patch
works, but the U-Boot version doesn't?

> Perhaps this patch assumes that power to the core is enabled before 
> kernel boot? I haven't yet figured out what in the PRCM I need to poke 
> to get power to the core, and the PRCM for this chip is not well-documented.

The PRCM is routinely not documented in the user manuals, IIUC
Allwinner provides separate documents for that (but not to us).
So far this was all reverse engineered from either BSP code or
some disassembly. Is there any indication in the BSP source code as to
how this is supposed to work? And maybe there is no separate power
control for the second core?

And have you checked that the PSCI runtime code is correctly hooked up
in U-Boot? I have to check what's really needed, but the whole code
needs to be linked to secure SRAM, IIRC.

> On 5/26/23 04:50, Andre Przywara wrote:
>  > I checked the manuals, and it seems the required bits are documented,
>  > but IIRC they differ from the other (much older) 32-bit parts. So it
>  > would require some refactoring of the existing sunxi PSCI code to
>  > accommodate the T113.  
> 
> Yeah, I decided to factor out the register-manipulating bits to a 
> handful of sunxi_cpu_set_* functions, which can be switched out to suit 
> the specific SoC in use. psci.c is growing way too many #ifdef branches, 
> so I might refactor this yet again to the "weak symbols with strong 
> overrides in e.g. psci-r528.c" pattern, unless you find that pattern 
> particularly distasteful.

We don't need #ifdef's, you can use normal C "if" statements:

static void __secure sunxi_set_entry_address(void *entry)
{
	if (IS_ENABLED(CONFIG_MACH_SUN8I_R528))
		writel((u32)entry,
			SUNXI_R_CPUCFG_BASE + SUN8I_R528_SOFT_ENTRY);
	else 
		writel((u32)entry,
			SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
}

"Dead code elimination" in modern compilers will remove everything
that's not needed, if this can be figured out at compile time (try it!).

This just requires to have all symbols defined all the time, but there
is no reason to protect #define's with #ifdef's either, as it doesn't
hurt to have unused preprocessor symbols. Or you define shared names
(SUNXI_ENTRY_ADDRESS_BASE), depending on Kconfig symbols.
arch/arm/mach-sunxi/spl_spi_sunxi.c makes use of those techniques
extensively, have a look there for inspiration (like static functions
to return base addresses: spi0_base_address(), this will be optimised
away completely).

> I have my WIP diff below. Before inclusion, I'll split it into multiple 
> patches (refactoring -> adding R528 support) but it's definitely not 
> ready for that yet. However if you could, it would help if you checked 
> my changes to cpu_sunxi_ncat2.h and squashed them into your own series 
> if they look good to you.

Sure. I actually removed most of the symbols there, as we don't need
them, but can surely add the ones you found for PSCI. Do you need
I2C in the SPL (looking at SUNXI_R_TWI_BASE)?

Thanks,
Andre

> ---
> diff --git a/arch/arm/cpu/armv7/sunxi/psci.c 
> b/arch/arm/cpu/armv7/sunxi/psci.c
> index e1d3638b5c..02c5c56c86 100644
> --- a/arch/arm/cpu/armv7/sunxi/psci.c
> +++ b/arch/arm/cpu/armv7/sunxi/psci.c
> @@ -38,6 +38,8 @@
>   #define SUN8I_R40_PWR_CLAMP(cpu)		(0x120 + (cpu) * 0x4)
>   #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0		(0xbc)
> 
> +#define SUN8I_R528_SOFT_ENTRY			(0x1c8)
> +
>   static void __secure cp15_write_cntp_tval(u32 tval)
>   {
>   	asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
> @@ -125,6 +127,13 @@ static void __secure sunxi_set_entry_address(void 
> *entry)
>   	writel((u32)entry,
>   	       SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
>   }
> +#elif defined CONFIG_MACH_SUN8I_R528
> +/* secondary core entry address is programmed differently on R528 */
> +static void __secure sunxi_set_entry_address(void *entry)
> +{
> +	writel((u32)entry,
> +	       SUNXI_R_CPUCFG_BASE + SUN8I_R528_SOFT_ENTRY);
> +}
>   #else
>   static void __secure sunxi_set_entry_address(void *entry)
>   {
> @@ -155,6 +164,10 @@ static void __secure sunxi_cpu_set_power(int cpu, 
> bool on)
>   			   (void *)cpucfg + SUN8I_R40_PWROFF,
>   			   on, cpu);
>   }
> +#elif defined CONFIG_MACH_SUN8I_R528
> +static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool 
> __always_unused on)
> +{
> +}
>   #else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
>   static void __secure sunxi_cpu_set_power(int cpu, bool on)
>   {
> @@ -166,30 +179,91 @@ static void __secure sunxi_cpu_set_power(int cpu, 
> bool on)
>   }
>   #endif /* CONFIG_MACH_SUN7I */
> 
> -void __secure sunxi_cpu_power_off(u32 cpuid)
> +#ifdef CONFIG_MACH_SUN8I_R528
> +#define C0_RST_CTRL	0x0000
> +#define C0_CTRL_REG0	0x0010
> +#define C0_CPU_STATUS	0x0080
> +
> +#define C0_BIT_WFI	16
> +
> +static void __secure sunxi_cpu_set_reset(int cpu, bool active)
> +{
> +	if (active)
> +		clrbits_le32(SUNXI_CPUX_BASE + C0_RST_CTRL, BIT(cpu));
> +	else
> +		setbits_le32(SUNXI_CPUX_BASE + C0_RST_CTRL, BIT(cpu));
> +}
> +
> +static void __secure sunxi_cpu_set_locking(int cpu, bool lock)
> +{
> +	/* TODO: I don't know what this is or how to do it */
> +}
> +
> +static bool __secure sunxi_cpu_poll_wfi(int cpu)
> +{
> +	return !!(readl(SUNXI_CPUX_BASE + C0_CPU_STATUS) & BIT(C0_BIT_WFI + cpu));
> +}
> +
> +static void __secure sunxi_cpu_invalidate_cache(int cpu)
> +{
> +	clrbits_le32(SUNXI_CPUX_BASE + C0_CTRL_REG0, BIT(cpu));
> +}
> +#else /* ! CONFIG_MACH_SUN8I_R528 */
> +static void __secure sunxi_cpu_set_reset(int cpu, bool active)
> +{
> +	struct sunxi_cpucfg_reg *cpucfg =
> +		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
> +
> +	writel(active ? 0b00 : 0b11, &cpucfg->cpu[cpu].rst);
> +}
> +
> +static void __secure sunxi_cpu_set_locking(int cpu, bool lock)
>   {
>   	struct sunxi_cpucfg_reg *cpucfg =
>   		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
> +
> +	if (lock)
> +		clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
> +	else
> +		setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
> +}
> +
> +static bool __secure sunxi_cpu_poll_wfi(int cpu)
> +{
> +	struct sunxi_cpucfg_reg *cpucfg =
> +		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
> +
> +	return !!(readl(&cpucfg->cpu[cpu].status) & BIT(2));
> +}
> +
> +static void __secure sunxi_cpu_invalidate_cache(int cpu)
> +{
> +	struct sunxi_cpucfg_reg *cpucfg =
> +		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
> +
> +	clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
> +}
> +#endif
> +
> +void __secure sunxi_cpu_power_off(u32 cpuid)
> +{
>   	u32 cpu = cpuid & 0x3;
> 
>   	/* Wait for the core to enter WFI */
> -	while (1) {
> -		if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
> -			break;
> +	while (!sunxi_cpu_poll_wfi(cpu))
>   		__mdelay(1);
> -	}
> 
>   	/* Assert reset on target CPU */
> -	writel(0, &cpucfg->cpu[cpu].rst);
> +	sunxi_cpu_set_reset(cpu, true);
> 
>   	/* Lock CPU (Disable external debug access) */
> -	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
> +	sunxi_cpu_set_locking(cpu, true);
> 
>   	/* Power down CPU */
>   	sunxi_cpu_set_power(cpuid, false);
> 
> -	/* Unlock CPU (Disable external debug access) */
> -	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
> +	/* Unlock CPU (Reenable external debug access) */
> +	sunxi_cpu_set_locking(cpu, false);
>   }
> 
>   static u32 __secure cp15_read_scr(void)
> @@ -246,8 +320,6 @@ out:
>   int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
>   			 u32 context_id)
>   {
> -	struct sunxi_cpucfg_reg *cpucfg =
> -		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
>   	u32 cpu = (mpidr & 0x3);
> 
>   	/* store target PC and context id */
> @@ -257,22 +329,22 @@ int __secure psci_cpu_on(u32 __always_unused 
> unused, u32 mpidr, u32 pc,
>   	sunxi_set_entry_address(&psci_cpu_entry);
> 
>   	/* Assert reset on target CPU */
> -	writel(0, &cpucfg->cpu[cpu].rst);
> +	sunxi_cpu_set_reset(cpu, true);
> 
>   	/* Invalidate L1 cache */
> -	clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
> +	sunxi_cpu_invalidate_cache(cpu);
> 
>   	/* Lock CPU (Disable external debug access) */
> -	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
> +	sunxi_cpu_set_locking(cpu, true);
> 
>   	/* Power up target CPU */
>   	sunxi_cpu_set_power(cpu, true);
> 
>   	/* De-assert reset on target CPU */
> -	writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
> +	sunxi_cpu_set_reset(cpu, false);
> 
> -	/* Unlock CPU (Disable external debug access) */
> -	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
> +	/* Unlock CPU (Reenable external debug access) */
> +	sunxi_cpu_set_locking(cpu, false);
> 
>   	return ARM_PSCI_RET_SUCCESS;
>   }
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h 
> b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
> index d01508517c..629d761aa6 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
> @@ -17,6 +17,8 @@
>   #define SUNXI_SIDC_BASE			0x03006000
>   #define SUNXI_SID_BASE			0x03006200
>   #define SUNXI_TIMER_BASE		0x02050000
> +#define SUNXI_GIC400_BASE		0x03020000
> +#define SUNXI_CPUX_BASE			0x09010000
> 
>   #ifdef CONFIG_MACH_SUN50I_H6
>   #define SUNXI_DRAM_COM_BASE		0x04002000
> @@ -34,11 +36,11 @@
>   #define SUNXI_SPI0_BASE			0x04025000
>   #define SUNXI_SPI1_BASE			0x04026000
> 
> -#define SUNXI_RTC_BASE			0x07000000
>   #define SUNXI_R_CPUCFG_BASE		0x07000400
>   #define SUNXI_PRCM_BASE			0x07010000
>   #define SUNXI_R_WDOG_BASE		0x07020400
> -#define SUNXI_R_TWI_BASE		0x07081400
> +#define SUNXI_R_TWI_BASE		0x07020800
> +#define SUNXI_RTC_BASE			0x07090000
> 
>   #ifndef __ASSEMBLY__
>   void sunxi_board_init(void);
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index bb9b863d2c..a5d312d377 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -366,6 +366,8 @@ config MACH_SUN8I_R40
>   config MACH_SUN8I_R528
>   	bool "sun8i (Allwinner R528)"
>   	select CPU_V7A
> +	select CPU_V7_HAS_NONSEC
> +	select ARCH_SUPPORT_PSCI
>   	select SUNXI_GEN_NCAT2
>   	select SUNXI_NEW_PINCTRL
>   	select MMC_SUNXI_HAS_NEW_MODE


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU
  2023-05-26 22:07           ` Andre Przywara
@ 2023-05-27  2:15             ` Sam Edwards
  2023-05-30  0:58               ` Sam Edwards
  0 siblings, 1 reply; 62+ messages in thread
From: Sam Edwards @ 2023-05-27  2:15 UTC (permalink / raw)
  To: Andre Przywara; +Cc: Maksim Kiselev, u-boot

Hey Andre,

On 5/26/23 16:07, Andre Przywara wrote:
> So with "no success" you are referring to the patch below? Which is the
> Linux patch ported to U-Boot? And does that mean that the Linux patch
> works, but the U-Boot version doesn't?

Yes, the diff below is what I've been trying to use. It's not the Linux 
patch ported to U-Boot; I was trying to get it to work (wondering if 
there was something I was missing, like power control) when Maksim 
pointed out the Linux patch. I haven't tried the latter at all.

My "no success" is Linux stalling indefinitely at:
[    0.123090] smp: Bringing up secondary CPUs ...

> The PRCM is routinely not documented in the user manuals, IIUC
> Allwinner provides separate documents for that (but not to us).
> So far this was all reverse engineered from either BSP code or
> some disassembly. Is there any indication in the BSP source code as to
> how this is supposed to work? And maybe there is no separate power
> control for the second core?

The user manual strongly suggests that power is enabled by default, so I 
may not need to touch PRCM after all. I also checked (and 
double-checked) the raw disassembly of my resulting `psci_cpu_on` and it 
does look like all of the correct registers are being hit.

I don't have any BSP source code suggesting anything otherwise. I do 
have an OP-TEE binary, which doesn't appear to try anything more than 
the kernel patch (and my current PSCI implementation) does.

> And have you checked that the PSCI runtime code is correctly hooked up
> in U-Boot? I have to check what's really needed, but the whole code
> needs to be linked to secure SRAM, IIRC.

I'm about 80% sure the PSCI code is properly callable. I've toyed with 
the kernel a little bit to test this. I get a "bad mode" panic if U-Boot 
doesn't register the SMC vector, and PSCI_RET_NOT_SUPPORTED if I call 
unused function IDs, so I think U-Boot is able to get called and return 
just fine.

The OP-TEE binary also doesn't appear to try to relocate itself into any 
kind of particular RAM location. It just runs where it loads from DRAM. 
I take this to mean U-Boot's "in-situ" secure segment case is 
appropriate here, and no specific linking is needed.

The one thing I'm not very sure about at the moment is whether 
`psci_cpu_entry` is properly handling the newly-awakened second core. 
I'll keep debugging.

> We don't need #ifdef's, you can use normal C "if" statements:

I'll try to follow that approach then.

> This just requires to have all symbols defined all the time

Egh, gross, this means some code that shouldn't be used for a particular 
target can slip by the compiler's diagnostics unnoticed (such as when 
this happened with SUNXI_R_PIO_BASE). I wish there was a better way.

> Sure. I actually removed most of the symbols there, as we don't need
> them, but can surely add the ones you found for PSCI. Do you need
> I2C in the SPL (looking at SUNXI_R_TWI_BASE)?

I'm not sure yet: my target does have an EEPROM on TWI2, which might 
eventually be used to store a board revision (and therefore which 
determines the FDT that the SPL should load), but I'm also considering 
overlays for other versions that are applied within main U-Boot.

But I can't fit much more in SPL anyway. The text section there is 
already up to 0x6ec0 (without SPI or NAND yet), and with third-party 
tooling assuming U-Boot at offset 0x8000, I can't very easily allocate 
more room to it. I might have to figure out what more to clear out here.

But anyway I only filled in that address because I came across the 
correct value in Allwinner's fork of U-Boot and noted it down before I 
forgot.

Cheers,
Sam

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU
  2023-05-27  2:15             ` Sam Edwards
@ 2023-05-30  0:58               ` Sam Edwards
  2023-05-31 15:19                 ` Andre Przywara
  0 siblings, 1 reply; 62+ messages in thread
From: Sam Edwards @ 2023-05-30  0:58 UTC (permalink / raw)
  To: Andre Przywara; +Cc: Maksim Kiselev, u-boot

Hey again Andre,

On 5/26/23 20:15, Sam Edwards wrote:
> My "no success" is Linux stalling indefinitely at:
> [    0.123090] smp: Bringing up secondary CPUs ...

OK, correction: my "no success" was Linux being unable to access the 
GIC, so boot was getting stuck. This was because it was running in 
nonsec mode and the GIC wasn't getting the interrupts moved over into 
group1.

The root cause of THAT was that the T113's CBAR's PERIPHBASE is still 
0x01C80000, where the GIC used to be on the older ARM sunxis. Allwinner 
never updated their ARM cores when they moved the GIC to 0x03020000!

Guess we need a `#define CFG_ARM_GIC_BASE_ADDRESS 0x03020000`. Where do 
you recommend I put that? :)

I also think sunxi/psci.c:psci_arch_init needs some cleanup:
- It sets GICC_PMR to 0xFF, which should probably be removed because 
that was already done by `_nonsec_init`
- It tries to clear the NS bit of SCR to enter secure mode, but the NS 
bit is just enabled later in `_secure_monitor`. So that should also be 
removed because it has no effect.

So, I'll have a few PSCI patches for you soon -- once I rest up from all 
of that GIC debugging, that is!

Cheers,
Sam

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU
  2023-05-30  0:58               ` Sam Edwards
@ 2023-05-31 15:19                 ` Andre Przywara
  0 siblings, 0 replies; 62+ messages in thread
From: Andre Przywara @ 2023-05-31 15:19 UTC (permalink / raw)
  To: Sam Edwards; +Cc: Maksim Kiselev, u-boot

On Mon, 29 May 2023 18:58:54 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

> On 5/26/23 20:15, Sam Edwards wrote:
> > My "no success" is Linux stalling indefinitely at:
> > [    0.123090] smp: Bringing up secondary CPUs ...  
> 
> OK, correction: my "no success" was Linux being unable to access the 
> GIC, so boot was getting stuck. This was because it was running in 
> nonsec mode and the GIC wasn't getting the interrupts moved over into 
> group1.
> 
> The root cause of THAT was that the T113's CBAR's PERIPHBASE is still 
> 0x01C80000, where the GIC used to be on the older ARM sunxis. Allwinner 
> never updated their ARM cores when they moved the GIC to 0x03020000!

Ah, good find! And yeah, I already noticed that on the H6 a few years
back, but nobody really cares, and other SoCs get CBAR wrong as well
(hence the existing workaround).

> Guess we need a `#define CFG_ARM_GIC_BASE_ADDRESS 0x03020000`. Where do 
> you recommend I put that? :)

Meh, the reflex would be to put it in include/configs/sunxi-common.h.
Although I wonder if it really belongs into Kconfig, but that may be for
another time.

> I also think sunxi/psci.c:psci_arch_init needs some cleanup:
> - It sets GICC_PMR to 0xFF, which should probably be removed because 
> that was already done by `_nonsec_init`
> - It tries to clear the NS bit of SCR to enter secure mode, but the NS 
> bit is just enabled later in `_secure_monitor`. So that should also be 
> removed because it has no effect.
> 
> So, I'll have a few PSCI patches for you soon -- once I rest up from all 
> of that GIC debugging, that is!

Ah, sorry to hear that, the GIC can really be a beast ;-)

Cheers,
Andre

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model
  2022-12-06  0:45 ` [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model Andre Przywara
  2022-12-06  5:38   ` Icenowy Zheng
  2023-05-16  2:32   ` Sam Edwards
@ 2023-06-03 18:03   ` Sam Edwards
  2 siblings, 0 replies; 62+ messages in thread
From: Sam Edwards @ 2023-06-03 18:03 UTC (permalink / raw)
  To: u-boot, Andre Przywara

Hi again Andre,

On 12/5/22 17:45, Andre Przywara wrote:
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index b6ffbff883c..3763ec3d2e4 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -177,7 +177,7 @@ static int gpio_init(void)
>   #error Unsupported console port number. Please fix pin mux settings in board.c
>   #endif
>   
> -#ifdef CONFIG_SUN50I_GEN_H6
> +#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
>   	/* Update PIO power bias configuration by copy hardware detected value */
>   	val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
>   	writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> @@ -475,7 +475,7 @@ void reset_cpu(void)
>   		/* sun5i sometimes gets stuck without this */
>   		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
>   	}
> -#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
> +#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
>   #if defined(CONFIG_MACH_SUN50I_H6)
>   	/* WDOG is broken for some H6 rev. use the R_WDOG instead */
>   	static const struct sunxi_wdog *wdog =

It appears that the R528/T113s updated the watchdog slightly from H6 in 
that it now requires a key (0x16AA << 16) OR'd in all writes to 
WDOG_SOFT_RST_REG, WDOG_CFG_REG, and WDOG_MODE_REG, or it will ignore 
those writes. This reset code busywaits indefinitely unless I add that 
key. It looks like sunxi_wdt.c needs to be updated as well, but I don't 
know if that's in-scope for this patchset.

Cheers,
Sam

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
                   ` (16 preceding siblings ...)
  2022-12-06  0:45 ` [RFC PATCH 17/17] sunxi: add preliminary MangoPi MQ-R board support Andre Przywara
@ 2023-06-09 22:16 ` Sam Edwards
  2023-06-12  0:20   ` Andre Przywara
  17 siblings, 1 reply; 62+ messages in thread
From: Sam Edwards @ 2023-06-09 22:16 UTC (permalink / raw)
  To: u-boot, Andre Przywara

Hi Andre,

On 12/5/22 17:45, Andre Przywara wrote:
> Please let me know if you have any opinions!

I believe I promised you last month I'd let you know once I had a build 
I'm happy with, and I'm pleased to say that I think I've reached that 
point. I'm running quite rapidly out of sharp edges to sand down, too.

I have a build of U-Boot for my target, complete with:
- UART3 initialized correctly
- DRAM coming up correctly
- SPL sets configured boot clock correctly
- SPI-NAND support (SPL and U-Boot proper)
- MMC support (SPL and U-Boot proper)
- SPL boot from FEL
- USB gadget support
- Ethernet MAC+PHY support
- I²C support *
- GPIO support (LEDs, buttons, misc. board management)
- `reset` working (requries CONFIG_SYSRESET unset, WDT key)
- PSCI, nonsec
- Able to boot Linux ;)

* Requires nonzero `MVTWSI_CONTROL_CLEAR_IFLG` for NCAT2, and a patch to 
the pinctrl driver to configure the proper mux function for my necessary 
pins.

I figured I'd share this list as a sort of checklist for your own work, 
too. The remainder of my efforts now will probably be focused on 
mainlining this stuff (let me know how else I can be of help), and then 
I'm afraid I'll have to disappear back downstream to the Turing Pi 2 
development effort, but maybe our paths will cross again in the kernel 
lists. :)

Thank you greatly,
Sam

P.S. I figure the reason there aren't I²C function defs in the d1 
pinctrl table already is because Allwinner tends to kick around the I²C 
mux values a lot and we would need a per-pin lookup table that would eat 
up too much valuable image space?

In an entirely JUST FOR FUN exercise to give myself a break from staring 
at datasheets/patches and do a "pure CS" coding challenge for a change, 
I came up with a terse encoding scheme for this table. Here is the size 
(in bits) for a selection of D1's functions (pin assignments harvested 
from Linux):

  'emac': 50,
  'i2c0': 101,
  'i2c1': 64,
  'i2c2': 109,
  'i2c3': 91,
  'mmc0': 23,
  'mmc1': 23,
  'mmc2': 20,
  'spi0': 41,
  'spi1': 48,
  'uart0': 78,
  'uart1': 87,
  'uart2': 88,
  'uart3': 102,
  'uart4': 68,
  'uart5': 66,

...and yes, it also identifies invalid pin assignments! I'd be willing 
to contribute something like this if there's big interest, but I figure 
needing to compress this at build-time might be a bit too complicated 
for the U-Boot project's liking.

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2023-06-09 22:16 ` [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Sam Edwards
@ 2023-06-12  0:20   ` Andre Przywara
  2023-06-12 21:18     ` Sam Edwards
  0 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2023-06-12  0:20 UTC (permalink / raw)
  To: Sam Edwards; +Cc: u-boot

On Fri, 9 Jun 2023 16:16:43 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

> On 12/5/22 17:45, Andre Przywara wrote:
> > Please let me know if you have any opinions!  
> 
> I believe I promised you last month I'd let you know once I had a build 
> I'm happy with, and I'm pleased to say that I think I've reached that 
> point. I'm running quite rapidly out of sharp edges to sand down, too.

Thanks for the update and the list! Can you confirm where you
still needed code changes compared to say my github branch plus the
changes we already discussed? Trying some guesses below, please confirm
or deny:

> I have a build of U-Boot for my target, complete with:
> - UART3 initialized correctly

this is problematic because of the other pinmux used on your board,
which cannot easily be encoded alongside the existing UART3 pinmux?

> - DRAM coming up correctly
> - SPL sets configured boot clock correctly

This should work as per github?

> - SPI-NAND support (SPL and U-Boot proper)

This is with Icenow's series? Any D1 specific changes needed there?

> - MMC support (SPL and U-Boot proper)
> - SPL boot from FEL

again worked already in github?

> - USB gadget support

So with the fixed SUNXI_SRAMC_BASE you said it worked? What about the
USB PHY? That needs at least wiring in the compatible string? If you
have such a patch, can you please rebase it on top of my v2 USB PHY
series and post that?

> - Ethernet MAC+PHY support

Anything surprising here? Is that using an already supported external
PHY?

> - I²C support *
> - GPIO support (LEDs, buttons, misc. board management)

again should work out of the box, minus your board specific
configuration?

> - `reset` working (requries CONFIG_SYSRESET unset, WDT key)

Isn't "CONFIG_SYSRESET unset" a hack? I dimly remember we had this for
some other SoC initially, but later got rid of it?
For the WDT key: it seems like Linux got a nice patch to integrate this
neatly into the driver without quirking this too much, do you have
something ready for U-Boot as well? Would love to see it on the list
then ;-)

> - PSCI, nonsec

ah yeah, owe you some reviews on this one ...

> - Able to boot Linux ;)
> 
> * Requires nonzero `MVTWSI_CONTROL_CLEAR_IFLG` for NCAT2, and a patch to 
> the pinctrl driver to configure the proper mux function for my necessary 
> pins.

Are those pinmuxes straight forward to add to the pinctrl driver? Or
are there conflicts similar to UART3?
 
> I figured I'd share this list as a sort of checklist for your own work, 
> too. The remainder of my efforts now will probably be focused on 
> mainlining this stuff (let me know how else I can be of help), and then 
> I'm afraid I'll have to disappear back downstream to the Turing Pi 2 
> development effort, but maybe our paths will cross again in the kernel 
> lists. :)

Yeah, as you may know, the DT has to go through the kernel list. DT
patches can be tedious to upstream, there is now much attention to
every detail. Running checkpatch and dtbs_check should reveal most
issues beforehand, though.

Cheers,
Andre


> 
> Thank you greatly,
> Sam
> 
> P.S. I figure the reason there aren't I²C function defs in the d1 
> pinctrl table already is because Allwinner tends to kick around the I²C 
> mux values a lot and we would need a per-pin lookup table that would eat 
> up too much valuable image space?
> 
> In an entirely JUST FOR FUN exercise to give myself a break from staring 
> at datasheets/patches and do a "pure CS" coding challenge for a change, 
> I came up with a terse encoding scheme for this table. Here is the size 
> (in bits) for a selection of D1's functions (pin assignments harvested 
> from Linux):
> 
>   'emac': 50,
>   'i2c0': 101,
>   'i2c1': 64,
>   'i2c2': 109,
>   'i2c3': 91,
>   'mmc0': 23,
>   'mmc1': 23,
>   'mmc2': 20,
>   'spi0': 41,
>   'spi1': 48,
>   'uart0': 78,
>   'uart1': 87,
>   'uart2': 88,
>   'uart3': 102,
>   'uart4': 68,
>   'uart5': 66,
> 
> ...and yes, it also identifies invalid pin assignments! I'd be willing 
> to contribute something like this if there's big interest, but I figure 
> needing to compress this at build-time might be a bit too complicated 
> for the U-Boot project's liking.


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2023-06-12  0:20   ` Andre Przywara
@ 2023-06-12 21:18     ` Sam Edwards
  2023-06-15  0:07       ` Andre Przywara
  2023-06-16 15:59       ` Andre Przywara
  0 siblings, 2 replies; 62+ messages in thread
From: Sam Edwards @ 2023-06-12 21:18 UTC (permalink / raw)
  To: Andre Przywara; +Cc: u-boot

Hey Andre,

On 6/11/23 18:20, Andre Przywara wrote:
> Thanks for the update and the list! Can you confirm where you
> still needed code changes compared to say my github branch plus the
> changes we already discussed? Trying some guesses below, please confirm
> or deny:

Preeeeetttttyyy much everything I've changed locally has been submitted 
to the list or discussed in the relevant patchset. Have you updated your 
GitHub branch recently (past couple of weeks)? I haven't been watching 
it but I can pull it again and see which of my local changes are still 
required.

>> I have a build of U-Boot for my target, complete with:
>> - UART3 initialized correctly
> 
> this is problematic because of the other pinmux used on your board,
> which cannot easily be encoded alongside the existing UART3 pinmux?

Actually no, my board's UART3 is on PB6/PB7, nice and standard.

>> - DRAM coming up correctly
>> - SPL sets configured boot clock correctly
> 
> This should work as per github?

Yep, everything was working satisfactorily once I figured out I needed 
to set CONFIG_SYS_CLK_FREQ to get acceptable boot speeds.

>> - SPI-NAND support (SPL and U-Boot proper)
> 
> This is with Icenow's series? Any D1 specific changes needed there?

Yes, with Icenowy's series (322733).

I learned that the BROM sets the boot medium code to 0x04 when it's an 
SPI-*NAND* (while older chips used 0x03 for "it's either SPI-NOR or 
SPI-NAND, good luck figuring out which"). Since `env_get_location` 
assumes BOOT_DEVICE_SPI is NOR (and my target needs to load env from UBI 
iff booting from NAND), I'm hoping I can convince Icenowy to separate 
out the SPI-NAND and SPI-NOR load methods entirely (vs. her current 
try-NAND-then-NOR approach) with the aid of some disambiguation logic to 
probe for an SPI-NAND on the older chips known to report these as 0x03.

I also needed Maksim's patch series (355747) to support the D1 SPI master.

>> - MMC support (SPL and U-Boot proper)
>> - SPL boot from FEL
> 
> again worked already in github?

Yes and yes. I was just confirming they're good; no local work needed 
from me here.

>> - USB gadget support
> 
> So with the fixed SUNXI_SRAMC_BASE you said it worked? What about the
> USB PHY? That needs at least wiring in the compatible string? If you
> have such a patch, can you please rebase it on top of my v2 USB PHY
> series and post that?

Yes, with corrected SUNXI_SRAMC_BASE -- though I also needed my patches 
to make musb-new/sunxi.c use the UDC gadget model in DM (series 358842), 
as I don't think there's another way to init the controller at runtime.

I can't say whether the endpoint limit is correct or that mUSB *host* 
operation works.

The USB PHY only required that CONFIG_PHY_SUN4I_USB be enabled. The 
correct compatible is already wired up. It does look like your PHY 
series drops the explicit requirement to set PHY_SUN4I_USB so that's 
better than what I was doing (adding a `select` directive under R528).

I can test your series if you want but I doubt it intersects my work 
here in any significant way.

>> - Ethernet MAC+PHY support
> 
> Anything surprising here? Is that using an already supported external
> PHY?

The only surprise was this was how I noticed that CONFIG_CLK_SUN20I_D1 
was not being implicitly enabled. Enabling that was then how I found 
that the clock driver wasn't compatible with current upstream (which I 
already mentioned).

The PHY is external and already supported, adding it to my DT required 
very little work.

>> - I²C support *
>> - GPIO support (LEDs, buttons, misc. board management)
> 
> again should work out of the box, minus your board specific
> configuration?

GPIO is completely OotB, yes. I²C is OotB once MVTWSI_CONTROL_CLEAR_IFLG 
is set correctly. (The pinctrl requirements for it are a little harder, 
more on that below.)

>> - `reset` working (requries CONFIG_SYSRESET unset, WDT key)
> 
> Isn't "CONFIG_SYSRESET unset" a hack? I dimly remember we had this for
> some other SoC initially, but later got rid of it?

Unsetting it is required for reset_cpu() to be defined. Your patchset 
updates that function (albeit without adding the WDT key, so the current 
patch is broken) to support NCAT2 already. U-Boot has no driver for 
"allwinner,sun20i-d1-wdt-reset", so this is the only way for `reset` to 
work.

> For the WDT key: it seems like Linux got a nice patch to integrate this
> neatly into the driver without quirking this too much, do you have
> something ready for U-Boot as well? Would love to see it on the list
> then ;-)

I just hacked the correct value into the function; nothing really 
suitable for the list, sorry.

>> - PSCI, nonsec
> 
> ah yeah, owe you some reviews on this one ...

It occurs to me that my work *might* support H6 as well (they both use 
CPUX blocks, right?) so perhaps it would be better if I de-RFC'd my 
series and instead worked to upstream it chasing H6, for you to come 
along later and tack on NCAT2 support with your R528 patchset?

>> - Able to boot Linux ;)
>>
>> * Requires nonzero `MVTWSI_CONTROL_CLEAR_IFLG` for NCAT2, and a patch to
>> the pinctrl driver to configure the proper mux function for my necessary
>> pins.
> 
> Are those pinmuxes straight forward to add to the pinctrl driver? Or
> are there conflicts similar to UART3?

The conflict is that I'm on i2c2 + muxval 2. I suspect this one's going 
to be a downstream patch to add the necessary line:
{ "i2c2",	2 },	/* PE12-PE13 */

...and since no other assignment for i2c2 uses muxval 2, the only hope 
for this to be supported upstream would be for the pinctrl driver to 
include the full pin->muxval LUT.

>> I figured I'd share this list as a sort of checklist for your own work,
>> too. The remainder of my efforts now will probably be focused on
>> mainlining this stuff (let me know how else I can be of help), and then
>> I'm afraid I'll have to disappear back downstream to the Turing Pi 2
>> development effort, but maybe our paths will cross again in the kernel
>> lists. :)
> 
> Yeah, as you may know, the DT has to go through the kernel list. DT
> patches can be tedious to upstream, there is now much attention to
> every detail. Running checkpatch and dtbs_check should reveal most
> issues beforehand, though.

At this time I have no interest in upstreaming the DT. That might change 
in the future, but for now it's very much meant to be out-of-tree.

> Cheers,
> Andre

Likewise,
Sam

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2023-06-12 21:18     ` Sam Edwards
@ 2023-06-15  0:07       ` Andre Przywara
  2023-06-18 19:01         ` Sam Edwards
  2023-06-16 15:59       ` Andre Przywara
  1 sibling, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2023-06-15  0:07 UTC (permalink / raw)
  To: Sam Edwards; +Cc: u-boot

On Mon, 12 Jun 2023 15:18:17 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

> On 6/11/23 18:20, Andre Przywara wrote:
> > Thanks for the update and the list! Can you confirm where you
> > still needed code changes compared to say my github branch plus the
> > changes we already discussed? Trying some guesses below, please confirm
> > or deny:  
> 
> Preeeeetttttyyy much everything I've changed locally has been submitted 
> to the list or discussed in the relevant patchset. Have you updated your 
> GitHub branch recently (past couple of weeks)? I haven't been watching 
> it but I can pull it again and see which of my local changes are still 
> required.

So I finally found some time to address some issues in the series,
especially in the first patches (pinctrl rework and preparation).
I pushed a branch to https://github.com/apritzel/u-boot/commits/r528-rc
I need to do more testing, most importantly regression testing on other
SoCs, and will only be able to post something next week, I guess.

If you could briefly list the things that are still missing, I could
try to pick some low hanging fruits.

> >> I have a build of U-Boot for my target, complete with:
> >> - UART3 initialized correctly  
> > 
> > this is problematic because of the other pinmux used on your board,
> > which cannot easily be encoded alongside the existing UART3 pinmux?  
> 
> Actually no, my board's UART3 is on PB6/PB7, nice and standard.
> 
> >> - DRAM coming up correctly
> >> - SPL sets configured boot clock correctly  
> > 
> > This should work as per github?  
> 
> Yep, everything was working satisfactorily once I figured out I needed 
> to set CONFIG_SYS_CLK_FREQ to get acceptable boot speeds.

Interesting, indeed this is left at 0, which I think will result in 288
MHz. What is that frequency in your case? Do you know what the BSP
programs? Traditionally we used something conservative that works
without cooling and with the default voltage, but I don't know that
value for the T113s.

> >> - SPI-NAND support (SPL and U-Boot proper)  
> > 
> > This is with Icenow's series? Any D1 specific changes needed there?  
> 
> Yes, with Icenowy's series (322733).
> 
> I learned that the BROM sets the boot medium code to 0x04 when it's an 
> SPI-*NAND* (while older chips used 0x03 for "it's either SPI-NOR or 
> SPI-NAND, good luck figuring out which"). Since `env_get_location` 
> assumes BOOT_DEVICE_SPI is NOR (and my target needs to load env from UBI 
> iff booting from NAND), I'm hoping I can convince Icenowy to separate 
> out the SPI-NAND and SPI-NOR load methods entirely (vs. her current 
> try-NAND-then-NOR approach) with the aid of some disambiguation logic to 
> probe for an SPI-NAND on the older chips known to report these as 0x03.
> 
> I also needed Maksim's patch series (355747) to support the D1 SPI master.
> 
> >> - MMC support (SPL and U-Boot proper)
> >> - SPL boot from FEL  
> > 
> > again worked already in github?  
> 
> Yes and yes. I was just confirming they're good; no local work needed 
> from me here.
> 
> >> - USB gadget support  
> > 
> > So with the fixed SUNXI_SRAMC_BASE you said it worked? What about the
> > USB PHY? That needs at least wiring in the compatible string? If you
> > have such a patch, can you please rebase it on top of my v2 USB PHY
> > series and post that?  
> 
> Yes, with corrected SUNXI_SRAMC_BASE -- though I also needed my patches 
> to make musb-new/sunxi.c use the UDC gadget model in DM (series 358842), 
> as I don't think there's another way to init the controller at runtime.
> 
> I can't say whether the endpoint limit is correct or that mUSB *host* 
> operation works.
> 
> The USB PHY only required that CONFIG_PHY_SUN4I_USB be enabled. The 
> correct compatible is already wired up. It does look like your PHY 
> series drops the explicit requirement to set PHY_SUN4I_USB so that's 
> better than what I was doing (adding a `select` directive under R528).

Ah, right, we already merged the "allwinner,sun20i-d1-usb-phy" patch.

> I can test your series if you want but I doubt it intersects my work 
> here in any significant way.
> 
> >> - Ethernet MAC+PHY support  
> > 
> > Anything surprising here? Is that using an already supported external
> > PHY?  
> 
> The only surprise was this was how I noticed that CONFIG_CLK_SUN20I_D1 
> was not being implicitly enabled. Enabling that was then how I found 
> that the clock driver wasn't compatible with current upstream (which I 
> already mentioned).

I think CLK_SUN20I_D1 should be set by default now, so can you check
that this is fixed?

> The PHY is external and already supported, adding it to my DT required 
> very little work.
> 
> >> - I²C support *
> >> - GPIO support (LEDs, buttons, misc. board management)  
> > 
> > again should work out of the box, minus your board specific
> > configuration?  
> 
> GPIO is completely OotB, yes. I²C is OotB once MVTWSI_CONTROL_CLEAR_IFLG 
> is set correctly. (The pinctrl requirements for it are a little harder, 
> more on that below.)
> 
> >> - `reset` working (requries CONFIG_SYSRESET unset, WDT key)  
> > 
> > Isn't "CONFIG_SYSRESET unset" a hack? I dimly remember we had this for
> > some other SoC initially, but later got rid of it?  
> 
> Unsetting it is required for reset_cpu() to be defined. Your patchset 
> updates that function (albeit without adding the WDT key, so the current 
> patch is broken) to support NCAT2 already. U-Boot has no driver for 
> "allwinner,sun20i-d1-wdt-reset", so this is the only way for `reset` to 
> work.

OK, thanks, need to dig into this again.

> > For the WDT key: it seems like Linux got a nice patch to integrate this
> > neatly into the driver without quirking this too much, do you have
> > something ready for U-Boot as well? Would love to see it on the list
> > then ;-)  
> 
> I just hacked the correct value into the function; nothing really 
> suitable for the list, sorry.
> 
> >> - PSCI, nonsec  
> > 
> > ah yeah, owe you some reviews on this one ...  
> 
> It occurs to me that my work *might* support H6 as well (they both use 
> CPUX blocks, right?) so perhaps it would be better if I de-RFC'd my 
> series and instead worked to upstream it chasing H6, for you to come 
> along later and tack on NCAT2 support with your R528 patchset?

Why would we need H6 PSCI support? On the ARMv8 parts we use Trusted
Firmware-A (TF-A) to provide PSCI services, which has a much more mature
implementation.

> >> - Able to boot Linux ;)
> >>
> >> * Requires nonzero `MVTWSI_CONTROL_CLEAR_IFLG` for NCAT2, and a patch to
> >> the pinctrl driver to configure the proper mux function for my necessary
> >> pins.  
> > 
> > Are those pinmuxes straight forward to add to the pinctrl driver? Or
> > are there conflicts similar to UART3?  
> 
> The conflict is that I'm on i2c2 + muxval 2. I suspect this one's going 
> to be a downstream patch to add the necessary line:
> { "i2c2",	2 },	/* PE12-PE13 */

How would this conflict, exactly? I don't see any other I2C2
definition? And what do you need I2C2 for, exactly?

> ...and since no other assignment for i2c2 uses muxval 2, the only hope 
> for this to be supported upstream would be for the pinctrl driver to 
> include the full pin->muxval LUT.

Well, there are shortcuts. I sketched some simpler idea in the comment
at the top of pinctrl-sunxi.c.

> >> I figured I'd share this list as a sort of checklist for your own work,
> >> too. The remainder of my efforts now will probably be focused on
> >> mainlining this stuff (let me know how else I can be of help), and then
> >> I'm afraid I'll have to disappear back downstream to the Turing Pi 2
> >> development effort, but maybe our paths will cross again in the kernel
> >> lists. :)  
> > 
> > Yeah, as you may know, the DT has to go through the kernel list. DT
> > patches can be tedious to upstream, there is now much attention to
> > every detail. Running checkpatch and dtbs_check should reveal most
> > issues beforehand, though.  
> 
> At this time I have no interest in upstreaming the DT.

Why not?

> That might change 
> in the future, but for now it's very much meant to be out-of-tree.

Why is this? This only increases your update burden, and we might break
something and not realise that, if your DT is not in the tree.
The question to ask should be rather: why *not* to upstream the DT?
Please keep in mind that this would block U-Boot support, since we need
the DT approved in the kernel before we could merge it into U-Boot.

Cheers,
Andre

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2023-06-12 21:18     ` Sam Edwards
  2023-06-15  0:07       ` Andre Przywara
@ 2023-06-16 15:59       ` Andre Przywara
  2023-06-16 16:27         ` Maxim Kiselev
  1 sibling, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2023-06-16 15:59 UTC (permalink / raw)
  To: Sam Edwards; +Cc: u-boot

On Mon, 12 Jun 2023 15:18:17 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

something regarding "reset" below ...

> On 6/11/23 18:20, Andre Przywara wrote:
> > Thanks for the update and the list! Can you confirm where you
> > still needed code changes compared to say my github branch plus the
> > changes we already discussed? Trying some guesses below, please confirm
> > or deny:  
> 
> Preeeeetttttyyy much everything I've changed locally has been submitted 
> to the list or discussed in the relevant patchset. Have you updated your 
> GitHub branch recently (past couple of weeks)? I haven't been watching 
> it but I can pull it again and see which of my local changes are still 
> required.
> 
> >> I have a build of U-Boot for my target, complete with:
> >> - UART3 initialized correctly  
> > 
> > this is problematic because of the other pinmux used on your board,
> > which cannot easily be encoded alongside the existing UART3 pinmux?  
> 
> Actually no, my board's UART3 is on PB6/PB7, nice and standard.
> 
> >> - DRAM coming up correctly
> >> - SPL sets configured boot clock correctly  
> > 
> > This should work as per github?  
> 
> Yep, everything was working satisfactorily once I figured out I needed 
> to set CONFIG_SYS_CLK_FREQ to get acceptable boot speeds.
> 
> >> - SPI-NAND support (SPL and U-Boot proper)  
> > 
> > This is with Icenow's series? Any D1 specific changes needed there?  
> 
> Yes, with Icenowy's series (322733).
> 
> I learned that the BROM sets the boot medium code to 0x04 when it's an 
> SPI-*NAND* (while older chips used 0x03 for "it's either SPI-NOR or 
> SPI-NAND, good luck figuring out which"). Since `env_get_location` 
> assumes BOOT_DEVICE_SPI is NOR (and my target needs to load env from UBI 
> iff booting from NAND), I'm hoping I can convince Icenowy to separate 
> out the SPI-NAND and SPI-NOR load methods entirely (vs. her current 
> try-NAND-then-NOR approach) with the aid of some disambiguation logic to 
> probe for an SPI-NAND on the older chips known to report these as 0x03.
> 
> I also needed Maksim's patch series (355747) to support the D1 SPI master.
> 
> >> - MMC support (SPL and U-Boot proper)
> >> - SPL boot from FEL  
> > 
> > again worked already in github?  
> 
> Yes and yes. I was just confirming they're good; no local work needed 
> from me here.
> 
> >> - USB gadget support  
> > 
> > So with the fixed SUNXI_SRAMC_BASE you said it worked? What about the
> > USB PHY? That needs at least wiring in the compatible string? If you
> > have such a patch, can you please rebase it on top of my v2 USB PHY
> > series and post that?  
> 
> Yes, with corrected SUNXI_SRAMC_BASE -- though I also needed my patches 
> to make musb-new/sunxi.c use the UDC gadget model in DM (series 358842), 
> as I don't think there's another way to init the controller at runtime.
> 
> I can't say whether the endpoint limit is correct or that mUSB *host* 
> operation works.
> 
> The USB PHY only required that CONFIG_PHY_SUN4I_USB be enabled. The 
> correct compatible is already wired up. It does look like your PHY 
> series drops the explicit requirement to set PHY_SUN4I_USB so that's 
> better than what I was doing (adding a `select` directive under R528).
> 
> I can test your series if you want but I doubt it intersects my work 
> here in any significant way.
> 
> >> - Ethernet MAC+PHY support  
> > 
> > Anything surprising here? Is that using an already supported external
> > PHY?  
> 
> The only surprise was this was how I noticed that CONFIG_CLK_SUN20I_D1 
> was not being implicitly enabled. Enabling that was then how I found 
> that the clock driver wasn't compatible with current upstream (which I 
> already mentioned).
> 
> The PHY is external and already supported, adding it to my DT required 
> very little work.
> 
> >> - I²C support *
> >> - GPIO support (LEDs, buttons, misc. board management)  
> > 
> > again should work out of the box, minus your board specific
> > configuration?  
> 
> GPIO is completely OotB, yes. I²C is OotB once MVTWSI_CONTROL_CLEAR_IFLG 
> is set correctly. (The pinctrl requirements for it are a little harder, 
> more on that below.)
> 
> >> - `reset` working (requries CONFIG_SYSRESET unset, WDT key)  
> > 
> > Isn't "CONFIG_SYSRESET unset" a hack? I dimly remember we had this for
> > some other SoC initially, but later got rid of it?  
> 
> Unsetting it is required for reset_cpu() to be defined. Your patchset 
> updates that function (albeit without adding the WDT key, so the current 
> patch is broken) to support NCAT2 already. U-Boot has no driver for 
> "allwinner,sun20i-d1-wdt-reset", so this is the only way for `reset` to 
> work.

So I had a look at this, and it's a bit surprising:
The watchdog driver already supports "allwinner,sun20i-d1-wdt" for a
while. We don't need to list the "-reset" version, because the normal
compatible name acts as a fallback string. However the DT node in the base
.dtsi sets: status = "reserved"; for this (and the other) watchdog, so
U-Boot's DM (correctly!) ignores those devices. Trying to figure out why.
Adding:
&wdt {
	status = "okay";
};
to sun8i-t113s.dtsi fixes that for me, now the reset command works.

> > For the WDT key: it seems like Linux got a nice patch to integrate this
> > neatly into the driver without quirking this too much, do you have
> > something ready for U-Boot as well? Would love to see it on the list
> > then ;-)  
> 
> I just hacked the correct value into the function; nothing really 
> suitable for the list, sorry.

CONFIG_SYSRESET is only applicable for U-Boot proper, so we need
reset_cpu for the SPL still. That is not as critical, since the SPL resets
the board only in case of an error, but should be fixed nevertheless. I
will have a stab at this.

Cheers,
Andre

> >> - PSCI, nonsec  
> > 
> > ah yeah, owe you some reviews on this one ...  
> 
> It occurs to me that my work *might* support H6 as well (they both use 
> CPUX blocks, right?) so perhaps it would be better if I de-RFC'd my 
> series and instead worked to upstream it chasing H6, for you to come 
> along later and tack on NCAT2 support with your R528 patchset?
> 
> >> - Able to boot Linux ;)
> >>
> >> * Requires nonzero `MVTWSI_CONTROL_CLEAR_IFLG` for NCAT2, and a patch to
> >> the pinctrl driver to configure the proper mux function for my necessary
> >> pins.  
> > 
> > Are those pinmuxes straight forward to add to the pinctrl driver? Or
> > are there conflicts similar to UART3?  
> 
> The conflict is that I'm on i2c2 + muxval 2. I suspect this one's going 
> to be a downstream patch to add the necessary line:
> { "i2c2",	2 },	/* PE12-PE13 */
> 
> ...and since no other assignment for i2c2 uses muxval 2, the only hope 
> for this to be supported upstream would be for the pinctrl driver to 
> include the full pin->muxval LUT.
> 
> >> I figured I'd share this list as a sort of checklist for your own work,
> >> too. The remainder of my efforts now will probably be focused on
> >> mainlining this stuff (let me know how else I can be of help), and then
> >> I'm afraid I'll have to disappear back downstream to the Turing Pi 2
> >> development effort, but maybe our paths will cross again in the kernel
> >> lists. :)  
> > 
> > Yeah, as you may know, the DT has to go through the kernel list. DT
> > patches can be tedious to upstream, there is now much attention to
> > every detail. Running checkpatch and dtbs_check should reveal most
> > issues beforehand, though.  
> 
> At this time I have no interest in upstreaming the DT. That might change 
> in the future, but for now it's very much meant to be out-of-tree.
> 
> > Cheers,
> > Andre  
> 
> Likewise,
> Sam


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2023-06-16 15:59       ` Andre Przywara
@ 2023-06-16 16:27         ` Maxim Kiselev
  2023-06-16 16:36           ` Andre Przywara
  0 siblings, 1 reply; 62+ messages in thread
From: Maxim Kiselev @ 2023-06-16 16:27 UTC (permalink / raw)
  To: Andre Przywara; +Cc: Sam Edwards, u-boot

Hi Andre, Sam,

пт, 16 июн. 2023 г. в 18:59, Andre Przywara <andre.przywara@arm.com>:
>
> On Mon, 12 Jun 2023 15:18:17 -0600
> Sam Edwards <cfsworks@gmail.com> wrote:
>
> Hi Sam,
>
> something regarding "reset" below ...
>
> > On 6/11/23 18:20, Andre Przywara wrote:
> > > Thanks for the update and the list! Can you confirm where you
> > > still needed code changes compared to say my github branch plus the
> > > changes we already discussed? Trying some guesses below, please confirm
> > > or deny:
> >
> > Preeeeetttttyyy much everything I've changed locally has been submitted
> > to the list or discussed in the relevant patchset. Have you updated your
> > GitHub branch recently (past couple of weeks)? I haven't been watching
> > it but I can pull it again and see which of my local changes are still
> > required.
> >
> > >> I have a build of U-Boot for my target, complete with:
> > >> - UART3 initialized correctly
> > >
> > > this is problematic because of the other pinmux used on your board,
> > > which cannot easily be encoded alongside the existing UART3 pinmux?
> >
> > Actually no, my board's UART3 is on PB6/PB7, nice and standard.
> >
> > >> - DRAM coming up correctly
> > >> - SPL sets configured boot clock correctly
> > >
> > > This should work as per github?
> >
> > Yep, everything was working satisfactorily once I figured out I needed
> > to set CONFIG_SYS_CLK_FREQ to get acceptable boot speeds.
> >
> > >> - SPI-NAND support (SPL and U-Boot proper)
> > >
> > > This is with Icenow's series? Any D1 specific changes needed there?
> >
> > Yes, with Icenowy's series (322733).
> >
> > I learned that the BROM sets the boot medium code to 0x04 when it's an
> > SPI-*NAND* (while older chips used 0x03 for "it's either SPI-NOR or
> > SPI-NAND, good luck figuring out which"). Since `env_get_location`
> > assumes BOOT_DEVICE_SPI is NOR (and my target needs to load env from UBI
> > iff booting from NAND), I'm hoping I can convince Icenowy to separate
> > out the SPI-NAND and SPI-NOR load methods entirely (vs. her current
> > try-NAND-then-NOR approach) with the aid of some disambiguation logic to
> > probe for an SPI-NAND on the older chips known to report these as 0x03.
> >
> > I also needed Maksim's patch series (355747) to support the D1 SPI master.
> >
> > >> - MMC support (SPL and U-Boot proper)
> > >> - SPL boot from FEL
> > >
> > > again worked already in github?
> >
> > Yes and yes. I was just confirming they're good; no local work needed
> > from me here.
> >
> > >> - USB gadget support
> > >
> > > So with the fixed SUNXI_SRAMC_BASE you said it worked? What about the
> > > USB PHY? That needs at least wiring in the compatible string? If you
> > > have such a patch, can you please rebase it on top of my v2 USB PHY
> > > series and post that?
> >
> > Yes, with corrected SUNXI_SRAMC_BASE -- though I also needed my patches
> > to make musb-new/sunxi.c use the UDC gadget model in DM (series 358842),
> > as I don't think there's another way to init the controller at runtime.
> >
> > I can't say whether the endpoint limit is correct or that mUSB *host*
> > operation works.
> >
> > The USB PHY only required that CONFIG_PHY_SUN4I_USB be enabled. The
> > correct compatible is already wired up. It does look like your PHY
> > series drops the explicit requirement to set PHY_SUN4I_USB so that's
> > better than what I was doing (adding a `select` directive under R528).
> >
> > I can test your series if you want but I doubt it intersects my work
> > here in any significant way.
> >
> > >> - Ethernet MAC+PHY support
> > >
> > > Anything surprising here? Is that using an already supported external
> > > PHY?
> >
> > The only surprise was this was how I noticed that CONFIG_CLK_SUN20I_D1
> > was not being implicitly enabled. Enabling that was then how I found
> > that the clock driver wasn't compatible with current upstream (which I
> > already mentioned).
> >
> > The PHY is external and already supported, adding it to my DT required
> > very little work.
> >
> > >> - I²C support *
> > >> - GPIO support (LEDs, buttons, misc. board management)
> > >
> > > again should work out of the box, minus your board specific
> > > configuration?
> >
> > GPIO is completely OotB, yes. I²C is OotB once MVTWSI_CONTROL_CLEAR_IFLG
> > is set correctly. (The pinctrl requirements for it are a little harder,
> > more on that below.)
> >
> > >> - `reset` working (requries CONFIG_SYSRESET unset, WDT key)
> > >
> > > Isn't "CONFIG_SYSRESET unset" a hack? I dimly remember we had this for
> > > some other SoC initially, but later got rid of it?
> >
> > Unsetting it is required for reset_cpu() to be defined. Your patchset
> > updates that function (albeit without adding the WDT key, so the current
> > patch is broken) to support NCAT2 already. U-Boot has no driver for
> > "allwinner,sun20i-d1-wdt-reset", so this is the only way for `reset` to
> > work.
>
> So I had a look at this, and it's a bit surprising:
> The watchdog driver already supports "allwinner,sun20i-d1-wdt" for a
> while. We don't need to list the "-reset" version, because the normal
> compatible name acts as a fallback string. However the DT node in the base
> .dtsi sets: status = "reserved"; for this (and the other) watchdog, so
> U-Boot's DM (correctly!) ignores those devices. Trying to figure out why.
> Adding:
> &wdt {
>         status = "okay";
> };
> to sun8i-t113s.dtsi fixes that for me, now the reset command works.

I did it the same way for myself. 🙂 But I thought this was the wrong way and
the watchdog should be managed by a trusted OS  or something like that.
(which we don't have in the mainline yet)

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2023-06-16 16:27         ` Maxim Kiselev
@ 2023-06-16 16:36           ` Andre Przywara
  2023-06-17  8:26             ` Maxim Kiselev
  0 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2023-06-16 16:36 UTC (permalink / raw)
  To: Maxim Kiselev; +Cc: Sam Edwards, u-boot, Samuel Holland

On Fri, 16 Jun 2023 19:27:16 +0300
Maxim Kiselev <bigunclemax@gmail.com> wrote:

Hi Maxim,

thanks for the reply! If you have anything that is missing or broken in
the new version of the patchset I put on github, please let me know.

> пт, 16 июн. 2023 г. в 18:59, Andre Przywara <andre.przywara@arm.com>:
> >
> > On Mon, 12 Jun 2023 15:18:17 -0600
> > Sam Edwards <cfsworks@gmail.com> wrote:
> >
> > Hi Sam,
> >
> > something regarding "reset" below ...
> >  
> > > On 6/11/23 18:20, Andre Przywara wrote:  
> > > > Thanks for the update and the list! Can you confirm where you
> > > > still needed code changes compared to say my github branch plus the
> > > > changes we already discussed? Trying some guesses below, please confirm
> > > > or deny:  
> > >
> > > Preeeeetttttyyy much everything I've changed locally has been submitted
> > > to the list or discussed in the relevant patchset. Have you updated your
> > > GitHub branch recently (past couple of weeks)? I haven't been watching
> > > it but I can pull it again and see which of my local changes are still
> > > required.
> > >  
> > > >> I have a build of U-Boot for my target, complete with:
> > > >> - UART3 initialized correctly  
> > > >
> > > > this is problematic because of the other pinmux used on your board,
> > > > which cannot easily be encoded alongside the existing UART3 pinmux?  
> > >
> > > Actually no, my board's UART3 is on PB6/PB7, nice and standard.
> > >  
> > > >> - DRAM coming up correctly
> > > >> - SPL sets configured boot clock correctly  
> > > >
> > > > This should work as per github?  
> > >
> > > Yep, everything was working satisfactorily once I figured out I needed
> > > to set CONFIG_SYS_CLK_FREQ to get acceptable boot speeds.
> > >  
> > > >> - SPI-NAND support (SPL and U-Boot proper)  
> > > >
> > > > This is with Icenow's series? Any D1 specific changes needed there?  
> > >
> > > Yes, with Icenowy's series (322733).
> > >
> > > I learned that the BROM sets the boot medium code to 0x04 when it's an
> > > SPI-*NAND* (while older chips used 0x03 for "it's either SPI-NOR or
> > > SPI-NAND, good luck figuring out which"). Since `env_get_location`
> > > assumes BOOT_DEVICE_SPI is NOR (and my target needs to load env from UBI
> > > iff booting from NAND), I'm hoping I can convince Icenowy to separate
> > > out the SPI-NAND and SPI-NOR load methods entirely (vs. her current
> > > try-NAND-then-NOR approach) with the aid of some disambiguation logic to
> > > probe for an SPI-NAND on the older chips known to report these as 0x03.
> > >
> > > I also needed Maksim's patch series (355747) to support the D1 SPI master.
> > >  
> > > >> - MMC support (SPL and U-Boot proper)
> > > >> - SPL boot from FEL  
> > > >
> > > > again worked already in github?  
> > >
> > > Yes and yes. I was just confirming they're good; no local work needed
> > > from me here.
> > >  
> > > >> - USB gadget support  
> > > >
> > > > So with the fixed SUNXI_SRAMC_BASE you said it worked? What about the
> > > > USB PHY? That needs at least wiring in the compatible string? If you
> > > > have such a patch, can you please rebase it on top of my v2 USB PHY
> > > > series and post that?  
> > >
> > > Yes, with corrected SUNXI_SRAMC_BASE -- though I also needed my patches
> > > to make musb-new/sunxi.c use the UDC gadget model in DM (series 358842),
> > > as I don't think there's another way to init the controller at runtime.
> > >
> > > I can't say whether the endpoint limit is correct or that mUSB *host*
> > > operation works.
> > >
> > > The USB PHY only required that CONFIG_PHY_SUN4I_USB be enabled. The
> > > correct compatible is already wired up. It does look like your PHY
> > > series drops the explicit requirement to set PHY_SUN4I_USB so that's
> > > better than what I was doing (adding a `select` directive under R528).
> > >
> > > I can test your series if you want but I doubt it intersects my work
> > > here in any significant way.
> > >  
> > > >> - Ethernet MAC+PHY support  
> > > >
> > > > Anything surprising here? Is that using an already supported external
> > > > PHY?  
> > >
> > > The only surprise was this was how I noticed that CONFIG_CLK_SUN20I_D1
> > > was not being implicitly enabled. Enabling that was then how I found
> > > that the clock driver wasn't compatible with current upstream (which I
> > > already mentioned).
> > >
> > > The PHY is external and already supported, adding it to my DT required
> > > very little work.
> > >  
> > > >> - I²C support *
> > > >> - GPIO support (LEDs, buttons, misc. board management)  
> > > >
> > > > again should work out of the box, minus your board specific
> > > > configuration?  
> > >
> > > GPIO is completely OotB, yes. I²C is OotB once MVTWSI_CONTROL_CLEAR_IFLG
> > > is set correctly. (The pinctrl requirements for it are a little harder,
> > > more on that below.)
> > >  
> > > >> - `reset` working (requries CONFIG_SYSRESET unset, WDT key)  
> > > >
> > > > Isn't "CONFIG_SYSRESET unset" a hack? I dimly remember we had this for
> > > > some other SoC initially, but later got rid of it?  
> > >
> > > Unsetting it is required for reset_cpu() to be defined. Your patchset
> > > updates that function (albeit without adding the WDT key, so the current
> > > patch is broken) to support NCAT2 already. U-Boot has no driver for
> > > "allwinner,sun20i-d1-wdt-reset", so this is the only way for `reset` to
> > > work.  
> >
> > So I had a look at this, and it's a bit surprising:
> > The watchdog driver already supports "allwinner,sun20i-d1-wdt" for a
> > while. We don't need to list the "-reset" version, because the normal
> > compatible name acts as a fallback string. However the DT node in the base
> > .dtsi sets: status = "reserved"; for this (and the other) watchdog, so
> > U-Boot's DM (correctly!) ignores those devices. Trying to figure out why.
> > Adding:
> > &wdt {
> >         status = "okay";
> > };
> > to sun8i-t113s.dtsi fixes that for me, now the reset command works.  
> 
> I did it the same way for myself. 🙂 But I thought this was the wrong way and
> the watchdog should be managed by a trusted OS  or something like that.
> (which we don't have in the mainline yet)

Well, the name "reserved" suggests so, but I think it's really that those
watchdogs don't seem to affect the RISC-V core, that's why there is a
separate one (riscv_wdt). To avoid those watchdogs being picked up the any
(RISC-V) OS, they are marked as reserved in the *shared* .dtsi.
So I think marking the one as "okay" in the ARM specific .dtsi is the way
to go, but I will wait for someone confirming the reason behind it.

Cheers,
Andre

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2023-06-16 16:36           ` Andre Przywara
@ 2023-06-17  8:26             ` Maxim Kiselev
  0 siblings, 0 replies; 62+ messages in thread
From: Maxim Kiselev @ 2023-06-17  8:26 UTC (permalink / raw)
  To: Andre Przywara; +Cc: Sam Edwards, u-boot, Samuel Holland

Hi Andre,

пт, 16 июн. 2023 г. в 19:36, Andre Przywara <andre.przywara@arm.com>:
[..]
>
> thanks for the reply! If you have anything that is missing or broken in
> the new version of the patchset I put on github, please let me know.

I tried the new version and everything looks pretty good for me. Great job!
Just one note. Could you please add SUNXI_R_CPUCFG_BASE 0x07000400
to cpu_sunxi_ncat2.h file. This register is required for Sam's PCSI patches.
Otherwise it leads to undeclared error:
      In file included from ./arch/arm/include/asm/armv7.h:60,
                  from arch/arm/cpu/armv7/sunxi/psci.c:16:
      arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_entry’:
      arch/arm/cpu/armv7/sunxi/psci.c:138:24: error:
‘SUNXI_R_CPUCFG_BASE’ undeclared (first use in this function); did you
mean ‘SUNXI_CPUCFG_BASE’?
      138 |                        SUNXI_R_CPUCFG_BASE + SUN8I_R528_SOFT_ENTRY);
            |                        ^~~~~~~~~~~~~~~~~~~

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2023-06-15  0:07       ` Andre Przywara
@ 2023-06-18 19:01         ` Sam Edwards
  2023-06-20 12:42           ` Andre Przywara
  0 siblings, 1 reply; 62+ messages in thread
From: Sam Edwards @ 2023-06-18 19:01 UTC (permalink / raw)
  To: Andre Przywara; +Cc: u-boot

Hi Andre,

On 6/14/23 18:07, Andre Przywara wrote:
> So I finally found some time to address some issues in the series,
> especially in the first patches (pinctrl rework and preparation).
> I pushed a branch to https://github.com/apritzel/u-boot/commits/r528-rc
> I need to do more testing, most importantly regression testing on other
> SoCs, and will only be able to post something next week, I guess.
> 
> If you could briefly list the things that are still missing, I could
> try to pick some low hanging fruits.

Rebasing onto this branch ended up eliminating a good chunk of my local 
hack commits. I've verified that everything is still working (but have 
not yet retested NAND SPL).

The remaining local changes I have are two additions to cpu_sunxi_ncat2.h:
+#define SUNXI_R_CPUCFG_BASE		0x07000400 /* for PSCI */
+#define SUNXI_RTC_BASE			0x07090000 /* for FEL */

The former can probably be brought into my PSCI series somehow (unless 
we expect more chips with CPUX blocks which might move those soft entry 
registers around, then it should be defined in cpu_sunxi_*.h). The 
latter is to support a reimplementation of Allwinner's `efex` command 
that I'm using for development (it pokes the magic number 0x5AA5A55A 
into RTC's GP_DATA_REG[2] and then resets; SPL clears that magic number 
and then does an early branch to BROM+0x0020 -- exactly what Allwinner's 
fork does).

I've also noticed exactly(!) one formatting difference in our clk_d1.c:
-	.num_gates = ARRAY_SIZE(d1_gates),
+	.num_gates  = ARRAY_SIZE(d1_gates),

Up to you if you prefer to align the = or not, but it does look 
inconsistent when .gates and .resets are aligned and .num_* aren't - 
might be a nitpick that comes up in patch review.

> Interesting, indeed this is left at 0, which I think will result in 288
> MHz.

Correct, at least that's what I was seeing.

> What is that frequency in your case? Do you know what the BSP
> programs?

1008 MHz, both.

> Traditionally we used something conservative that works
> without cooling and with the default voltage, but I don't know that
> value for the T113s.

For what it's worth, this board has a bare T113-s3 and the current OS 
does not reclock from 1008 MHz at all, and I don't know of any users of 
the board having stability issues.

In my own case, it idles at that clock at around ~35°C.

> I think CLK_SUN20I_D1 should be set by default now, so can you check
> that this is fixed?

It is now gone from my defconfig and still working, so indeed this is fixed.

> Why would we need H6 PSCI support? On the ARMv8 parts we use Trusted
> Firmware-A (TF-A) to provide PSCI services, which has a much more mature
> implementation.

It's not about the H6 and more about me being unsure whether R528/T113 
is the first ARMv7-based SoC to use the new CPU management registers. If 
it's not, and there's another such chip supported in U-Boot that just 
lacks PSCI, it would make more sense for me to land my PSCI series 
independently of our work here, and then you can add the R528 case 
later. It sounds like R528/T113 may be the first such chip needing this 
new code, though, so this may have to wait until the R528 series lands.

> How would this conflict, exactly? I don't see any other I2C2
> definition?

Well, no, the other definitions haven't landed in U-Boot yet. But they 
do exist in the kernel, datasheets, and physical chips themselves:

PB0/PB1/PB8/PB9/PE4/PE5: i2c2 defined as muxval 4
PC0/PC1/PD20/PD21/PG6/PG7/PG14/PG15: i2c2 defined as muxval 3
PE12/PE13: i2c2 defined as muxval 2

Defining i2c2=2 universally would mean that the pins for i2c2 cannot be 
changed, since it would conflict with every other definition.

> And what do you need I2C2 for, exactly?

Pins PE12/PE13 host an I²C bus with the board ID EEPROM and an Ethernet 
switch that should be reset (and have a few registers set to configure 
proper port isolation) very shortly after power-on.

> Well, there are shortcuts. I sketched some simpler idea in the comment
> at the top of pinctrl-sunxi.c.

My shortcut for the time being will probably be, "downstream patch."

>> At this time I have no interest in upstreaming the DT.
> 
> Why not?
> 
>> That might change
>> in the future, but for now it's very much meant to be out-of-tree.
> 
> Why is this? This only increases your update burden, and we might break
> something and not realise that, if your DT is not in the tree.
> The question to ask should be rather: why *not* to upstream the DT?
> Please keep in mind that this would block U-Boot support, since we need
> the DT approved in the kernel before we could merge it into U-Boot.

Currently, downstream is still fairly dependent on the Tina Linux 
kernel, not mainline. This is a situation I'd like to change, but it's a 
push for another day -- my focus right now is only on improving the 
bootloader situation.

This means that there are actually two DTs: one for the kernel, using 
the Tina Linux binding values, and one for U-Boot's control FDT, which 
can only support U-Boot right now (and cannot yet be tested on a real 
kernel). So neither DT is acceptable upstream: the former uses 
incompatible values/includes, and the latter isn't meant for Linux.

Even after(/if) this situation is resolved, the unified DT will probably 
remain in a state of flux for a while, until some drivers can be updated 
upstream (there's a slight mess with the I²C driver that needs to be 
cleaned up and we have to use GPIO-bitbanged I²C until then, for 
example) so it'll take more work before we have a "final" DT. At *that* 
time, upstreaming would be a good idea...

...but for now it's very much meant to be out-of-tree. :)

(I also do not work for the company that produced this board -- I'm just 
a contributor to the firmware project. Whether the project would even 
use the mainline version of its DT in the first place is, though likely, 
ultimately not my call.)

> Cheers,
> Andre

Likewise,
Sam

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2023-06-18 19:01         ` Sam Edwards
@ 2023-06-20 12:42           ` Andre Przywara
  2023-06-20 22:11             ` Sam Edwards
  0 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2023-06-20 12:42 UTC (permalink / raw)
  To: Sam Edwards; +Cc: u-boot

On Sun, 18 Jun 2023 13:01:33 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

thanks for the reply, that's very helpful.

> On 6/14/23 18:07, Andre Przywara wrote:
> > So I finally found some time to address some issues in the series,
> > especially in the first patches (pinctrl rework and preparation).
> > I pushed a branch to https://github.com/apritzel/u-boot/commits/r528-rc
> > I need to do more testing, most importantly regression testing on other
> > SoCs, and will only be able to post something next week, I guess.
> > 
> > If you could briefly list the things that are still missing, I could
> > try to pick some low hanging fruits.  
> 
> Rebasing onto this branch ended up eliminating a good chunk of my local 
> hack commits. I've verified that everything is still working (but have 
> not yet retested NAND SPL).

Great, thanks!

> The remaining local changes I have are two additions to cpu_sunxi_ncat2.h:
> +#define SUNXI_R_CPUCFG_BASE		0x07000400 /* for PSCI */
> +#define SUNXI_RTC_BASE			0x07090000 /* for FEL */

Right, I will definitely take the PSCI bit, but not so sure about FEL yet.

> The former can probably be brought into my PSCI series somehow (unless 
> we expect more chips with CPUX blocks which might move those soft entry 
> registers around, then it should be defined in cpu_sunxi_*.h). The 
> latter is to support a reimplementation of Allwinner's `efex` command 
> that I'm using for development (it pokes the magic number 0x5AA5A55A 
> into RTC's GP_DATA_REG[2] and then resets; SPL clears that magic number 
> and then does an early branch to BROM+0x0020 -- exactly what Allwinner's 
> fork does).

So yeah, the request of a "Enter FEL" command came up multiple times, but
so far no one could be bothered to implement this properly. The idea would
be to have a generic command (more like "fel-reset" than efex), and
allow each SoC (family) to implement this differently, as every
SoC requires something a bit different here (32-bit vs. 64-bit, having an
RTC vs not, etc).

If you could post your solution somewhere, we could start this effort.
There was some patch for the H3 already, and it's relatively
straight-forward on the newer SoCs (H616, IIRC), so if at least two
popular, but different SoCs would be supported, we could make sure to have
the right abstractions in place.

> I've also noticed exactly(!) one formatting difference in our clk_d1.c:
> -	.num_gates = ARRAY_SIZE(d1_gates),
> +	.num_gates  = ARRAY_SIZE(d1_gates),
> 
> Up to you if you prefer to align the = or not, but it does look 
> inconsistent when .gates and .resets are aligned and .num_* aren't - 
> might be a nitpick that comes up in patch review.

Well, this is how it is in all the other clock drivers, so I chose to stay
consistent with them ;-)

> > Interesting, indeed this is left at 0, which I think will result in 288
> > MHz.  
> 
> Correct, at least that's what I was seeing.
> 
> > What is that frequency in your case? Do you know what the BSP
> > programs?  
> 
> 1008 MHz, both.
> 
> > Traditionally we used something conservative that works
> > without cooling and with the default voltage, but I don't know that
> > value for the T113s.  
> 
> For what it's worth, this board has a bare T113-s3 and the current OS 
> does not reclock from 1008 MHz at all, and I don't know of any users of 
> the board having stability issues.
> 
> In my own case, it idles at that clock at around ~35°C.

OK, many thanks, it looks like 1008 MHz it is, then.

> > I think CLK_SUN20I_D1 should be set by default now, so can you check
> > that this is fixed?  
> 
> It is now gone from my defconfig and still working, so indeed this is fixed.
> 
> > Why would we need H6 PSCI support? On the ARMv8 parts we use Trusted
> > Firmware-A (TF-A) to provide PSCI services, which has a much more mature
> > implementation.  
> 
> It's not about the H6 and more about me being unsure whether R528/T113 
> is the first ARMv7-based SoC to use the new CPU management registers. If 
> it's not, and there's another such chip supported in U-Boot that just 
> lacks PSCI, it would make more sense for me to land my PSCI series 
> independently of our work here, and then you can add the R528 case 
> later. It sounds like R528/T113 may be the first such chip needing this 
> new code, though, so this may have to wait until the R528 series lands.
> 
> > How would this conflict, exactly? I don't see any other I2C2
> > definition?  
> 
> Well, no, the other definitions haven't landed in U-Boot yet. But they 
> do exist in the kernel, datasheets, and physical chips themselves:
> 
> PB0/PB1/PB8/PB9/PE4/PE5: i2c2 defined as muxval 4
> PC0/PC1/PD20/PD21/PG6/PG7/PG14/PG15: i2c2 defined as muxval 3
> PE12/PE13: i2c2 defined as muxval 2
> 
> Defining i2c2=2 universally would mean that the pins for i2c2 cannot be 
> changed, since it would conflict with every other definition.

Well, we are well aware that the current pinmux code is limited, but
we figured it does work for all practical purposes, and U-Boot has a far
tighter scope than Linux, so we don't need to support every theoretically
possible use case.
So if the TuringPi 2 board would be upstream, and you need I2C2, you would
just set the precedence for muxval 2. It's then the next board's problem
to live with that. Either by adding the port number (PB/PC/PD/PG) to the
definitions, or by reverting to a DT solution:
https://lore.kernel.org/linux-sunxi/20221110014255.20711-1-andre.przywara@arm.com/

> > And what do you need I2C2 for, exactly?  
> 
> Pins PE12/PE13 host an I²C bus with the board ID EEPROM and an Ethernet 
> switch that should be reset (and have a few registers set to configure 
> proper port isolation) very shortly after power-on.
> 
> > Well, there are shortcuts. I sketched some simpler idea in the comment
> > at the top of pinctrl-sunxi.c.  
> 
> My shortcut for the time being will probably be, "downstream patch."

see below ;-)

> >> At this time I have no interest in upstreaming the DT.  
> > 
> > Why not?
> >   
> >> That might change
> >> in the future, but for now it's very much meant to be out-of-tree.  
> > 
> > Why is this? This only increases your update burden, and we might break
> > something and not realise that, if your DT is not in the tree.
> > The question to ask should be rather: why *not* to upstream the DT?
> > Please keep in mind that this would block U-Boot support, since we need
> > the DT approved in the kernel before we could merge it into U-Boot.  
> 
> Currently, downstream is still fairly dependent on the Tina Linux 
> kernel, not mainline. This is a situation I'd like to change, but it's a 
> push for another day -- my focus right now is only on improving the 
> bootloader situation.

Ah, depending on the BSP kernel is indeed quite bad. I wonder what
features of the kernel you rely on that upstream does not have? Or is it
more about the BMC userland parts that are married to the Allwinner kernel
and its own interfaces?

> This means that there are actually two DTs: one for the kernel, using 
> the Tina Linux binding values, and one for U-Boot's control FDT, which 
> can only support U-Boot right now (and cannot yet be tested on a real 
> kernel). So neither DT is acceptable upstream: the former uses 
> incompatible values/includes, and the latter isn't meant for Linux.

So as you probably know, conceptually there is only one DT per machine, as
the DT describes the hardware. That's why try hard to align U-Boot and
Linux at least, and IIUC the BSDs copied the version in the Linux kernel
tree as well. Allwinner seems to have little clue or interest here, and we
gave up on their (quite misguided) interpretation of the DT a long time
ago.

> Even after(/if) this situation is resolved, the unified DT will probably 
> remain in a state of flux for a while, until some drivers can be updated 
> upstream (there's a slight mess with the I²C driver that needs to be 
> cleaned up and we have to use GPIO-bitbanged I²C until then, for 
> example) so it'll take more work before we have a "final" DT. At *that* 
> time, upstreaming would be a good idea...

Final DT is a noble goal, but in reality there will always be room for
improvement and additions. So what we typically do is to start with a
simple .dts for the kernel tree, describing the basic peripherals, and
everything that already works and is not subject to debate. If in doubt,
include a node, and we will comment. Could you prepare such a patch? This
should not contradict any DT nodes that U-Boot uses, so it's not a double
effort.
This would mean we have a *second* board DT for the T113s SoC in the
kernel, which always helps to improve quality and prevents hacks that just
work on the MangoPi. Besides, the TuringPi board is an actually useful
application of the SoC, deployed and available, in contrast to just some
development board from Chinese websites.
And once this is merged, we could just copy this over to U-Boot and add
the defconfig and any other support patches there.

> ...but for now it's very much meant to be out-of-tree. :)
> 
> (I also do not work for the company that produced this board -- I'm just 

Ah, that would have been a first anyway ;-)

> a contributor to the firmware project. Whether the project would even 
> use the mainline version of its DT in the first place is, though likely, 
> ultimately not my call.)

Yeah, I understand it's not the most grateful job to chase up on doing
things properly and stay on with the upstreaming process. Ultimately it's
the right thing to do, though, and will save you hassle over time. Plus we
(the community) will help you with that, and you'd get a second commit in
the kernel ;-)

Cheers,
Andre

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2023-06-20 12:42           ` Andre Przywara
@ 2023-06-20 22:11             ` Sam Edwards
  2023-06-21 10:55               ` Andre Przywara
  0 siblings, 1 reply; 62+ messages in thread
From: Sam Edwards @ 2023-06-20 22:11 UTC (permalink / raw)
  To: Andre Przywara; +Cc: u-boot

Hi Andre,

On 6/20/23 06:42, Andre Przywara wrote:
> So yeah, the request of a "Enter FEL" command came up multiple times, but
> so far no one could be bothered to implement this properly. The idea would
> be to have a generic command (more like "fel-reset" than efex), and
> allow each SoC (family) to implement this differently, as every
> SoC requires something a bit different here (32-bit vs. 64-bit, having an
> RTC vs not, etc).
> 
> If you could post your solution somewhere, we could start this effort.
> There was some patch for the H3 already, and it's relatively
> straight-forward on the newer SoCs (H616, IIRC), so if at least two
> popular, but different SoCs would be supported, we could make sure to have
> the right abstractions in place.

I already have a "go_to_fel()" that does the right thing to enter FEL 
from the SPL; I would pretty much just need to introduce the following 
per-SoC(-family) functions:
- bool sunxi_fel_flag_test(void)
- void sunxi_fel_flag_clear(void)
- void sunxi_fel_flag_set(void)

The "fel-reset" command (which is easier to type than what I have, "run 
fel_do_enter") would then call sunxi_fel_flag_set() and initiate a 
reset, and the SPL's early init just has to do sunxi_fel_flag_test() -> 
sunxi_fel_flag_clear() -> go_to_fel(). Seems easy enough.

Could you recommend to me a sufficiently different chip to test my 
abstractions against? Something ARMv8 and *without* RTC? I can then send 
in a series adding FEL support for that. (Also, did that H3 patch 
actually land? I didn't see anything but want to know if I should be 
refactoring my approach to extend what that H3 patch does or not.)

> Ah, depending on the BSP kernel is indeed quite bad. I wonder what
> features of the kernel you rely on that upstream does not have? Or is it
> more about the BMC userland parts that are married to the Allwinner kernel
> and its own interfaces?

I don't fully know; getting the kernel back on mainline is, as I said, a 
push for another day. I'm very much making a point of not looking into 
it before the bootloader can be upgraded to something that isn't a 
crashy, hard-to-update, failure-prone mess. (I'm working in "biggest 
fire, first out" order.)

That said, the first such dependent feature that leaps to mind is the 
AWNAND driver's CONFIG_AW_SPINAND_SIMULATE_MULTIPLANE, which logically 
interleaves pages of the NAND in a different ordering vs. what the 
physical NAND (and mainline's spi-nand driver) does. Alas this is a 
feature we're dependent on not because it provides benefits to our users 
(it does not, and in downstream discussions I've been soapboxing about 
how it's likely wearing down people's NANDs) but because the boards are 
flashed at the factory with this flag enabled so we need it set for the 
NAND to be accessible. We've experimented with reflashing the board with 
that flag disabled, but that has so far only resulted in corrupted flash.

Hope is not lost, though, for I have a half-written tool which shows 
some promise in being able to "unscramble the egg" and migrate existing 
NANDs over to the correct layout. That should be sufficient to get 
mainline U-Boot (and Tina Linux with the flag disabled) working, but I 
have no idea about mainline Linux still: this would only peel back one 
layer of the onion, and I don't know whether the next obstacle will be 
easier, harder, or about the same difficulty.

But it does mean that, for now, we're stuck with Tina Linux.

> Final DT is a noble goal, but in reality there will always be room for
> improvement and additions. So what we typically do is to start with a
> simple .dts for the kernel tree, describing the basic peripherals, and
> everything that already works and is not subject to debate. If in doubt,
> include a node, and we will comment. Could you prepare such a patch?

The peripheral-describing .dts that I have is for Tina Linux, and uses 
incompatible compatibles (ha), includes, dt-bindings, temporary hacks 
while better driver support can be developed, and would otherwise not 
fly upstream. I can send it in *anyway* if for some reason you think 
that's a good idea, but I really don't see that as being anything other 
than a waste of time.

As well, I can't write a fresh .dts for mainline (one more likely to be 
accepted on the list). A mainline kernel has never been booted on this 
board, so I would do no better at this than a kernel contributor 
selected at random. The best I can do now is write something that 
*looks* like the correct .dts.

As I keep saying, that may change in the future. But the answer today is 
still "no, I cannot."

> This
> should not contradict any DT nodes that U-Boot uses, so it's not a double
> effort.

True, in theory it *shouldn't* but in practice, I've found it does.

One way I've been bitten is that the sunxi SPI driver in U-Boot doesn't 
support Quad-SPI, so if the DT says the SPI-NAND is connected with a bus 
width of 4, the SPI-NAND driver requests Quad-SPI transfers, but the SPI 
master driver has no idea that it needs to handle the transfer any 
differently, and we're left with corrupt NAND reads/writes. Without 
Quad-SPI support in U-Boot's master driver (and/or, better yet, a U-Boot 
equivalent to Linux commit 83596fbeb5) -- also a push for another day -- 
I have no choice but to give U-Boot a specially edited version of the DT 
that omits this property.

> This would mean we have a *second* board DT for the T113s SoC in the
> kernel, which always helps to improve quality and prevents hacks that just
> work on the MangoPi. Besides, the TuringPi board is an actually useful
> application of the SoC, deployed and available, in contrast to just some
> development board from Chinese websites.
> And once this is merged, we could just copy this over to U-Boot and add
> the defconfig and any other support patches there.

See below.

>> ...but for now it's very much meant to be out-of-tree. :)
>>
>> (I also do not work for the company that produced this board -- I'm just
> 
> Ah, that would have been a first anyway ;-)

Oh? What would have been a first? I could pass it along to my contact at 
this company and encourage him to get involved in some way. I'm sure 
they'd appreciate the opportunity for the good press associated with 
being the first at something in the F/OSS world, and it might help to 
get them in the habit of cooperating closely with upstream (to make it 
less likely that they just fork things the moment upstream doesn't solve 
some problem they're having).

> Yeah, I understand it's not the most grateful job to chase up on doing
> things properly and stay on with the upstreaming process. Ultimately it's
> the right thing to do, though, and will save you hassle over time. Plus we
> (the community) will help you with that, and you'd get a second commit in
> the kernel ;-)

Ideologically-speaking, this is music to my ears, and I think we would 
even be having this same discussion were our roles reversed: we do both 
agree fully on the (mutual) benefits of upstream contribution.

But even more ultimately: the available time on any given day is 
limited, and I have to choose my battles. There are often things that 
either require less effort, save an even greater hassle over time, or 
provide more urgently-needed benefits, which (pragmatically speaking) 
ought to take priority. That doesn't mean the other lower-priority items 
have no benefit, it just means they should not be done *now.*

> Cheers,
> Andre

Likewise,
Sam

^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2023-06-20 22:11             ` Sam Edwards
@ 2023-06-21 10:55               ` Andre Przywara
  2023-06-21 20:22                 ` Sam Edwards
  0 siblings, 1 reply; 62+ messages in thread
From: Andre Przywara @ 2023-06-21 10:55 UTC (permalink / raw)
  To: Sam Edwards; +Cc: u-boot

On Tue, 20 Jun 2023 16:11:48 -0600
Sam Edwards <cfsworks@gmail.com> wrote:

Hi Sam,

pleasure to write with you ;-)

> On 6/20/23 06:42, Andre Przywara wrote:
> > So yeah, the request of a "Enter FEL" command came up multiple times, but
> > so far no one could be bothered to implement this properly. The idea would
> > be to have a generic command (more like "fel-reset" than efex), and
> > allow each SoC (family) to implement this differently, as every
> > SoC requires something a bit different here (32-bit vs. 64-bit, having an
> > RTC vs not, etc).
> > 
> > If you could post your solution somewhere, we could start this effort.
> > There was some patch for the H3 already, and it's relatively
> > straight-forward on the newer SoCs (H616, IIRC), so if at least two
> > popular, but different SoCs would be supported, we could make sure to have
> > the right abstractions in place.  
> 
> I already have a "go_to_fel()" that does the right thing to enter FEL 
> from the SPL; I would pretty much just need to introduce the following 
> per-SoC(-family) functions:
> - bool sunxi_fel_flag_test(void)
> - void sunxi_fel_flag_clear(void)
> - void sunxi_fel_flag_set(void)

Well, so this is actually the fallback implementation which should
somewhat work on most SoCs: set a flag, reset, and catch the flag in
the SPL. For modern SoCs with CPU hotplug support (the H616 is one one
of those, and it looks like the T113s is as well), there is actually a more
direct route:
We put some magic and the FEL entry address into some special memory
locations, then just reset. Now the *BootROM* will do the check already,
and branch to the provided entry point, which would be the FEL routine.
This doesn't rely on a prepared SPL to be loaded, so works without a
boot device with mainline U-Boot around.
Refer to section 3.4.2.3 and 3.4.2.4 of the T113-S3 user manual (v1.1).
According to this, the magic would be 0xfa50392f, the magic's address is
0x070005C0, and CPU0's entry point address would be in 0x070005C4. I had a
proof of concept implementation for the H616 using this method. The only
problem left would be that someone needs to clean the magic afterwards,
otherwise any follow-up reset would trigger FEL mode again.

> The "fel-reset" command (which is easier to type than what I have, "run 
> fel_do_enter") would then call sunxi_fel_flag_set() and initiate a 
> reset, and the SPL's early init just has to do sunxi_fel_flag_test() -> 
> sunxi_fel_flag_clear() -> go_to_fel(). Seems easy enough.
> 
> Could you recommend to me a sufficiently different chip to test my 
> abstractions against? Something ARMv8 and *without* RTC?

I think all ARMv8 parts have an RTC, so your generic approach might work
there as well. The complication is that the SPL switches to AArch64 very
early, in hand-stitched AArch32 assembly, check out
arch/arm/include/asm/arch-sunxi/boot0.h.
The check would need to be coded like this, then.

> I can then send 
> in a series adding FEL support for that. (Also, did that H3 patch 
> actually land? I didn't see anything but want to know if I should be 
> refactoring my approach to extend what that H3 patch does or not.)

https://patchwork.ozlabs.org/project/uboot/patch/c211aa414c59e7275fef82bf6f0035276d6e29f3.1656875482.git.msuchanek@suse.de/

Another generic approach for ARMv7 parts would be to reset the peripherals
as much as possible, then configure the core in a BROM compatible way
(MMU off, etc) and just branch to the BROM FEL entry address. This idea is
already somewhat used in our return-to-FEL code in the SPL, although we
don't change too much of the core setup in the SPL.

> > Ah, depending on the BSP kernel is indeed quite bad. I wonder what
> > features of the kernel you rely on that upstream does not have? Or is it
> > more about the BMC userland parts that are married to the Allwinner kernel
> > and its own interfaces?  
> 
> I don't fully know; getting the kernel back on mainline is, as I said, a 
> push for another day. I'm very much making a point of not looking into 
> it before the bootloader can be upgraded to something that isn't a 
> crashy, hard-to-update, failure-prone mess. (I'm working in "biggest 
> fire, first out" order.)

Fair enough, from a mainlining point of view you need to funnel the
board .dts through the Linux tree first, though.
Also, with the right DT, a mainline kernel would run on the board
already, maybe just not with the full functionality you'd expect from
it.

What I mean to say: you can surely continue using Tina Linux for the
BMC functionality on the board right now, but still upstream the board
.dts. As mentioned, the DT just describes the hardware, so it doesn't
dictate what to do with it. One might abuse the board as a T113s dev
board, maybe ;-) Does it work without any of the modules populated?

> That said, the first such dependent feature that leaps to mind is the 
> AWNAND driver's CONFIG_AW_SPINAND_SIMULATE_MULTIPLANE, which logically 
> interleaves pages of the NAND in a different ordering vs. what the 
> physical NAND (and mainline's spi-nand driver) does. Alas this is a 
> feature we're dependent on not because it provides benefits to our users 
> (it does not, and in downstream discussions I've been soapboxing about 
> how it's likely wearing down people's NANDs) but because the boards are 
> flashed at the factory with this flag enabled so we need it set for the 
> NAND to be accessible. We've experimented with reflashing the board with 
> that flag disabled, but that has so far only resulted in corrupted flash.
> 
> Hope is not lost, though, for I have a half-written tool which shows 
> some promise in being able to "unscramble the egg" and migrate existing 
> NANDs over to the correct layout. That should be sufficient to get 
> mainline U-Boot (and Tina Linux with the flag disabled) working, but I 
> have no idea about mainline Linux still: this would only peel back one 
> layer of the onion, and I don't know whether the next obstacle will be 
> easier, harder, or about the same difficulty.
> 
> But it does mean that, for now, we're stuck with Tina Linux.
> 
> > Final DT is a noble goal, but in reality there will always be room for
> > improvement and additions. So what we typically do is to start with a
> > simple .dts for the kernel tree, describing the basic peripherals, and
> > everything that already works and is not subject to debate. If in doubt,
> > include a node, and we will comment. Could you prepare such a patch?  
> 
> The peripheral-describing .dts that I have is for Tina Linux, and uses 
> incompatible compatibles (ha), includes, dt-bindings, temporary hacks 
> while better driver support can be developed, and would otherwise not 
> fly upstream.

Sure, you keep that nasty piece downstream, and load it in U-Boot into
$fdt_addr_r, then take it from there.
That doesn't affect the mainline Linux and U-Boot DT, though, which
could be upstreamed independently.
Then you can use the mainline DT (as used by U-Boot), using
$fdtcontroladdr, or any loaded DT, via $fdt_addr_r.

> I can send it in *anyway* if for some reason you think 
> that's a good idea, but I really don't see that as being anything other 
> than a waste of time.

There is indeed no point in sending a DT which only works with the
Allwinner BSP kernel.

> As well, I can't write a fresh .dts for mainline (one more likely to be 
> accepted on the list).

Yes, please!

> A mainline kernel has never been booted on this 
> board, so I would do no better at this than a kernel contributor 
> selected at random.

... having a board. So far you are the one contributor with access to
the hardware, so: thanks for volunteering! ;-)

> The best I can do now is write something that *looks* like the correct .dts.

Yes, and that would be the right .dts, if it passes the kernel review.

> As I keep saying, that may change in the future. But the answer today is 
> still "no, I cannot."

So to summarise what I am trying to say: You create a simple .dts file,
basically #include "sun8i-t113s.dtsi" and declaring the UART. Then add the
devices that already work (Ethernet?, USB-OTG) and see how far you get.
You could just load a kernel and initrd via FEL, and use the mainline
kernel just via serial like this. Granted, this is not really useful in
the BMC context, but would be a start.

This is actually similar to what Chris just did [1] for the RG Nano: this
initial DT for this mini handheld gaming console has no display support, so
is pretty useless in its original context, but starting mainline support
is the important thing here.

Plus: this exposes the problems you face (PHY config?) to a wider range of
people, who can help with the solution.

[1]
https://lore.kernel.org/linux-sunxi/20230620200022.295674-1-macroalpha82@gmail.com/T
> 
> > This
> > should not contradict any DT nodes that U-Boot uses, so it's not a double
> > effort.  
> 
> True, in theory it *shouldn't* but in practice, I've found it does.
> 
> One way I've been bitten is that the sunxi SPI driver in U-Boot doesn't 
> support Quad-SPI, so if the DT says the SPI-NAND is connected with a bus 
> width of 4, the SPI-NAND driver requests Quad-SPI transfers, but the SPI 
> master driver has no idea that it needs to handle the transfer any 
> differently, and we're left with corrupt NAND reads/writes. Without 
> Quad-SPI support in U-Boot's master driver (and/or, better yet, a U-Boot 
> equivalent to Linux commit 83596fbeb5) -- also a push for another day -- 
> I have no choice but to give U-Boot a specially edited version of the DT 
> that omits this property.

The U-Boot build system support some kind of build time DT "overlay"
feature: You put a file with the same name, but ending in
"-u-boot.dtsi" in the arch/arm/dts directory, and it will be included
into the DT which gets embedded into the U-Boot image. See
arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dts for an
example, and doc/develop/devicetree/control.rst for the proper
documentation.
So we upstream a minimal, non-controversial and non-contradicting base
.dts into the kernel tree, and can fix things up for the time being
using this method. This hack can then go away if either the mainline
kernel DT gets fixed and/or U-Boot learns the quad-SPI trick.

> > This would mean we have a *second* board DT for the T113s SoC in the
> > kernel, which always helps to improve quality and prevents hacks that just
> > work on the MangoPi. Besides, the TuringPi board is an actually useful
> > application of the SoC, deployed and available, in contrast to just some
> > development board from Chinese websites.
> > And once this is merged, we could just copy this over to U-Boot and add
> > the defconfig and any other support patches there.  
> 
> See below.
> 
> >> ...but for now it's very much meant to be out-of-tree. :)
> >>
> >> (I also do not work for the company that produced this board -- I'm just  
> > 
> > Ah, that would have been a first anyway ;-)  
> 
> Oh? What would have been a first? I could pass it along to my contact at

Someone from the board vendor company actually actively adding upstream
support for their device early. There were some examples in the past
where employees participated in upstreaming, but I cannot remember
seeing this too often when it comes to the initial DT support.

> this company and encourage him to get involved in some way. I'm sure 
> they'd appreciate the opportunity for the good press associated with 
> being the first at something in the F/OSS world, and it might help to 
> get them in the habit of cooperating closely with upstream (to make it 
> less likely that they just fork things the moment upstream doesn't solve 
> some problem they're having).

Yes, I understand the pressure in a product-centric world with release
dates and timelines, but the advantage of vendor-backed contributions
are early access to hardware and documentation, plus access to the
hardware engineers.

> > Yeah, I understand it's not the most grateful job to chase up on doing
> > things properly and stay on with the upstreaming process. Ultimately it's
> > the right thing to do, though, and will save you hassle over time. Plus we
> > (the community) will help you with that, and you'd get a second commit in
> > the kernel ;-)  
> 
> Ideologically-speaking, this is music to my ears, and I think we would 
> even be having this same discussion were our roles reversed: we do both 
> agree fully on the (mutual) benefits of upstream contribution.
> 
> But even more ultimately: the available time on any given day is 
> limited, and I have to choose my battles. There are often things that 

Fair enough, and there is no real pressure in getting the mainline DT
fully functional and merged today. But we should start the process *now*,
as this helps to detect problems early, and allows other people to jump on
this and continue the work or help out.

Cheers,
Andre


> either require less effort, save an even greater hassle over time, or 
> provide more urgently-needed benefits, which (pragmatically speaking) 
> ought to take priority. That doesn't mean the other lower-priority items 
> have no benefit, it just means they should not be done *now.*
> 
> > Cheers,
> > Andre  
> 
> Likewise,
> Sam


^ permalink raw reply	[flat|nested] 62+ messages in thread
* Re: [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
  2023-06-21 10:55               ` Andre Przywara
@ 2023-06-21 20:22                 ` Sam Edwards
  0 siblings, 0 replies; 62+ messages in thread
From: Sam Edwards @ 2023-06-21 20:22 UTC (permalink / raw)
  To: Andre Przywara; +Cc: u-boot

On 6/21/23 04:55, Andre Przywara wrote:
> On Tue, 20 Jun 2023 16:11:48 -0600
> Sam Edwards <cfsworks@gmail.com> wrote:
> 
> Hi Sam,
> 
> pleasure to write with you ;-)

Hi Andre,

Likewise!

> Well, so this is actually the fallback implementation which should
> somewhat work on most SoCs: set a flag, reset, and catch the flag in
> the SPL. For modern SoCs with CPU hotplug support (the H616 is one one
> of those, and it looks like the T113s is as well), there is actually a more
> direct route:

Oh man, I would definitely prefer a direct route that doesn't require 
the SPL coming up a second time, but...

> We put some magic and the FEL entry address into some special memory
> locations, then just reset. Now the *BootROM* will do the check already,
> and branch to the provided entry point, which would be the FEL routine.
> This doesn't rely on a prepared SPL to be loaded, so works without a
> boot device with mainline U-Boot around.
> Refer to section 3.4.2.3 and 3.4.2.4 of the T113-S3 user manual (v1.1).
> According to this, the magic would be 0xfa50392f, the magic's address is
> 0x070005C0, and CPU0's entry point address would be in 0x070005C4. I had a
> proof of concept implementation for the H616 using this method.

...I tried this and it seems that the 070005C* block hardware-resets to 
zero before BROM runs. Is there a softer reset method you had in mind 
that would avoid this?

> The only
> problem left would be that someone needs to clean the magic afterwards,
> otherwise any follow-up reset would trigger FEL mode again.
That's at least pretty fixable though: instead of setting the entry 
address to the FEL entry point, set it to a thunk placed in SRAM that 
clears the flag before continuing onward to FEL.

>> The "fel-reset" command (which is easier to type than what I have, "run
>> fel_do_enter") would then call sunxi_fel_flag_set() and initiate a
>> reset, and the SPL's early init just has to do sunxi_fel_flag_test() ->
>> sunxi_fel_flag_clear() -> go_to_fel(). Seems easy enough.
>>
>> Could you recommend to me a sufficiently different chip to test my
>> abstractions against? Something ARMv8 and *without* RTC?
> 
> I think all ARMv8 parts have an RTC, so your generic approach might work
> there as well. The complication is that the SPL switches to AArch64 very
> early, in hand-stitched AArch32 assembly, check out
> arch/arm/include/asm/arch-sunxi/boot0.h.
> The check would need to be coded like this, then.
> 
>> I can then send
>> in a series adding FEL support for that. (Also, did that H3 patch
>> actually land? I didn't see anything but want to know if I should be
>> refactoring my approach to extend what that H3 patch does or not.)
> 
> https://patchwork.ozlabs.org/project/uboot/patch/c211aa414c59e7275fef82bf6f0035276d6e29f3.1656875482.git.msuchanek@suse.de/

This approach seems close to mine, only my go_to_fel() enters by way of 
return_to_fel() after first modifying fel_stash.lr, since the 
return_to_fel() mechanism already takes care of restoring the core to a 
BROM-friendly state.
> One might abuse the board as a T113s dev
> board, maybe ;-) Does it work without any of the modules populated?

Sure, if you're thinking about getting one. You just need an ATX-pinout 
PSU to power the BMC (it runs off of the 5V standby rail).

> ... having a board. So far you are the one contributor with access to
> the hardware, so: thanks for volunteering! ;-)

Andre, please, I know you're being tongue-in-cheek here, but I said 
"no." We should have reached the agree-to-disagree point 2 emails ago: 
you've made your (very compelling) case for why downstream would benefit 
from the early expertise of the upstream DT reviewers, and how upstream 
would benefit from having the DT for a second "real" T113-using board, 
but at some point you need to trust that I understand that and that I 
must therefore have very good reasons not to be distracting myself with 
trying to (dual-)boot a mainline kernel yet. One thing at a time, y'know? :)

> The U-Boot build system support some kind of build time DT "overlay"
> feature: You put a file with the same name, but ending in
> "-u-boot.dtsi" in the arch/arm/dts directory, and it will be included
> into the DT which gets embedded into the U-Boot image. See
> arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dts for an
> example, and doc/develop/devicetree/control.rst for the proper
> documentation.
> So we upstream a minimal, non-controversial and non-contradicting base
> .dts into the kernel tree, and can fix things up for the time being
> using this method. This hack can then go away if either the mainline
> kernel DT gets fixed and/or U-Boot learns the quad-SPI trick.

Oh, good to know! I'll try to remember that this option exists when the 
time comes to use it.

> Someone from the board vendor company actually actively adding upstream
> support for their device early. There were some examples in the past
> where employees participated in upstreaming, but I cannot remember
> seeing this too often when it comes to the initial DT support.

I brought this email thread to the attention of the firmware development 
team at this company, then. No promises (they seem to have their hands 
sufficiently full with userspace work) but FWIW my opinion of them is 
that they do have a community-centric and F/OSS-oriented mindset, so 
with a bit of luck they may make themselves known on the upstream 
mailing lists at some point.

Thank you for your ongoing efforts,
Sam

^ permalink raw reply	[flat|nested] 62+ messages in thread
end of thread, other threads:[~2023-06-21 20:22 UTC | newest]

Thread overview: 62+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-06  0:45 [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 01/17] sunxi: remove CONFIG_SATAPWR Andre Przywara
2022-12-14  8:37   ` Samuel Holland
2022-12-14 14:25     ` Andre Przywara
2022-12-14 23:40       ` Samuel Holland
2022-12-06  0:45 ` [RFC PATCH 02/17] sunxi: remove CONFIG_MACPWR Andre Przywara
2022-12-14  9:09   ` Samuel Holland
2022-12-14 14:23     ` Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 03/17] pinctrl: sunxi: remove struct sunxi_gpio Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 04/17] pinctrl: sunxi: add GPIO in/out wrappers Andre Przywara
2022-12-15  5:59   ` Samuel Holland
2022-12-06  0:45 ` [RFC PATCH 05/17] pinctrl: sunxi: move pinctrl code and remove GPIO_EXTRA_HEADER Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 06/17] pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 07/17] pinctrl: sunxi: add new D1 pinctrl support Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model Andre Przywara
2022-12-06  5:38   ` Icenowy Zheng
2023-05-16  2:32   ` Sam Edwards
2023-05-16 21:08     ` Andre Przywara
2023-05-16 23:53       ` Sam Edwards
2023-05-17  0:43         ` Andre Przywara
2023-05-17  8:56           ` Andre Przywara
2023-05-17 14:04             ` Maxim Kiselev
2023-05-25 18:25               ` Maksim Kiselev
2023-05-26 11:05                 ` Andre Przywara
2023-06-03 18:03   ` Sam Edwards
2022-12-06  0:45 ` [RFC PATCH 09/17] pinctrl: sunxi: add Allwinner D1 pinctrl description Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 10/17] clk: sunxi: Add support for the D1 CCU Andre Przywara
2023-05-22  3:57   ` Sam Edwards
2023-05-24  0:58     ` Andre Przywara
2023-05-26  0:34   ` Sam Edwards
2023-05-26 10:50     ` Andre Przywara
2023-05-26 19:27       ` Maksim Kiselev
2023-05-26 20:22         ` Sam Edwards
2023-05-26 22:07           ` Andre Przywara
2023-05-27  2:15             ` Sam Edwards
2023-05-30  0:58               ` Sam Edwards
2023-05-31 15:19                 ` Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 11/17] sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 12/17] sunxi: clock: support D1/R528 PLL6 clock Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 13/17] sunxi: add early Allwinner R528/T113 SoC support Andre Przywara
2023-05-16  2:52   ` Sam Edwards
2023-05-16 22:01     ` Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 14/17] sunxi: refactor serial base addresses to avoid asm/arch/cpu.h Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 15/17] riscv: dts: allwinner: Add the D1/D1s SoC devicetree Andre Przywara
2022-12-06  0:45 ` [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub Andre Przywara
2022-12-06  5:55   ` Icenowy Zheng
2023-01-03 17:38     ` Andre Przywara
2023-01-04  5:49       ` Icenowy Zheng
2022-12-06  0:45 ` [RFC PATCH 17/17] sunxi: add preliminary MangoPi MQ-R board support Andre Przywara
2023-06-09 22:16 ` [RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support Sam Edwards
2023-06-12  0:20   ` Andre Przywara
2023-06-12 21:18     ` Sam Edwards
2023-06-15  0:07       ` Andre Przywara
2023-06-18 19:01         ` Sam Edwards
2023-06-20 12:42           ` Andre Przywara
2023-06-20 22:11             ` Sam Edwards
2023-06-21 10:55               ` Andre Przywara
2023-06-21 20:22                 ` Sam Edwards
2023-06-16 15:59       ` Andre Przywara
2023-06-16 16:27         ` Maxim Kiselev
2023-06-16 16:36           ` Andre Przywara
2023-06-17  8:26             ` Maxim Kiselev

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