[PATCH v5 0/3] rockchip: sdhci: Add HS400 Enhanced Strobe support

[PATCH v5 0/3] rockchip: sdhci: Add HS400 Enhanced Strobe support

[Alper Nebi Yasak]

This series implements support for the HS400 Enhanced Strobe mode on the
Rockchip SDHCI driver, for both RK3399 and RK3568. To test, I'm building
for chromebook_kevin with the following configs enabled:

    +CONFIG_MMC_SPEED_MODE_SET=y
     [...]
     CONFIG_MMC_PWRSEQ=y
    +CONFIG_MMC_IO_VOLTAGE=y
    +CONFIG_MMC_UHS_SUPPORT=y
    +CONFIG_MMC_HS400_ES_SUPPORT=y
    +CONFIG_MMC_HS400_SUPPORT=y
     CONFIG_MMC_DW=y
     CONFIG_MMC_DW_ROCKCHIP=y
     CONFIG_MMC_SDHCI=y
    +CONFIG_MMC_SDHCI_SDMA=y
     CONFIG_MMC_SDHCI_ROCKCHIP=y

and running roughly:

    $ mmc rescan [0|1|3|10|11|12]
    $ mmc info
    $ mmc part
    $ load mmc 0:1 0xd0000000 256MiB.bin
    $ load mmc 0:1 0xd0000000 16MiB.bin
    $ load mmc 0:1 0xd0000000 8MiB.bin

Here's the differences in info and speeds I get with this:

    Mode                   | Bus Speed    | Bus Width
    -----------------------+--------------+--------------
    MMC Legacy             | 25000000     | 8-bit
    MMC High Speed (26MHz) | 26000000     | 8-bit
    MMC High Speed (52MHz) | 52000000     | 8-bit
    HS200 (200MHz)         | 200000000    | 8-bit
    HS400 (200MHz)         | 200000000    | 8-bit DDR
    HS400ES (200MHz)       | 200000000    | 8-bit DDR

    Mode                   | 256 MiB Load | 16 MiB Load  | 8 MiB Load
    -----------------------+--------------+--------------+--------------
    MMC Legacy             | ~22.1  MiB/s | ~21.9  MiB/s | ~21.6  MiB/s
    MMC High Speed (26MHz) | ~22.1  MiB/s | ~21.9  MiB/s | ~21.6  MiB/s
    MMC High Speed (52MHz) | ~43.7  MiB/s | ~42.8  MiB/s | ~41.7  MiB/s
    HS200 (200MHz)         | ~161.2 MiB/s | ~149.5 MiB/s | ~137.9 MiB/s
    HS400 (200MHz)         | ~254.5 MiB/s | ~235.3 MiB/s | ~216.2 MiB/s
    HS400ES (200MHz)       | ~254.7 MiB/s | ~238.8 MiB/s | ~216.2 MiB/s

Hope I haven't missed anything. Enabling the configs above for each
board is left to board maintainers as I can't test on those boards.

Changes in v5:
- Incorporate RK3568 HS400ES fixes from Yifeng Zhao:
  - Use DWCMSHC_CTRL_HS400 = 0x7, instead of SDHCI_CTRL_HS400 = 0x5
  - Configure DWCMSHC_CARD_IS_EMMC in rk3568_sdhci_set_ios_post()
  - Configure DLL_STRBIN and DLL_TXCLK for HS400.
- Drop re-init fix already merged to master

v4: https://patchwork.ozlabs.org/project/uboot/list/?series=283482&state=*

Changes in v4:
- Add comment for SDHCI set_enhanced_strobe() operation
- Add comment for Rockchip SDHCI set_enhanced_strobe() driver data op

v3: https://patchwork.ozlabs.org/project/uboot/list/?series=281327&state=*

Changes in v3:
- Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init()

v2: https://patchwork.ozlabs.org/project/uboot/list/?series=280494&state=*

Changes in v2:
- Unset ES bit in rk3399 set_control_reg() to fix a reinit issue
- Don't use unnecessary & for function pointer in ops struct
- Rename rk3399_set_enhanced_strobe -> rk3399_sdhci_set_enhanced_strobe
- Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe
- Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES
- Rewrote cover letter

v1: https://patchwork.ozlabs.org/project/uboot/list/?series=269768&state=*

Alper Nebi Yasak (3):
  mmc: sdhci: Add HS400 Enhanced Strobe support
  rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3399
  rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568

 drivers/mmc/rockchip_sdhci.c | 117 +++++++++++++++++++++++++++++++++--
 drivers/mmc/sdhci.c          |  18 ++++++
 include/sdhci.h              |  12 ++++
 3 files changed, 141 insertions(+), 6 deletions(-)

-- 
2.35.1

[PATCH v5 1/3] mmc: sdhci: Add HS400 Enhanced Strobe support

[Alper Nebi Yasak]

Delegate setting the Enhanced Strobe configuration to individual drivers
if they set a function for it. Return -ENOTSUPP if they do not, like
what the MMC uclass does.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
---

(no changes since v4)

Changes in v4:
- Add comment for SDHCI set_enhanced_strobe() operation

Changes in v2:
- Add tag: "Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>"

 drivers/mmc/sdhci.c | 18 ++++++++++++++++++
 include/sdhci.h     | 12 ++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 766e4a6b0c5e..bf989a594f7e 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -513,6 +513,7 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
 		reg |= SDHCI_CTRL_UHS_SDR104;
 		break;
 	case MMC_HS_400:
+	case MMC_HS_400_ES:
 		reg |= SDHCI_CTRL_HS400;
 		break;
 	default:
@@ -666,6 +667,7 @@ static int sdhci_set_ios(struct mmc *mmc)
 		    mmc->selected_mode == MMC_DDR_52 ||
 		    mmc->selected_mode == MMC_HS_200 ||
 		    mmc->selected_mode == MMC_HS_400 ||
+		    mmc->selected_mode == MMC_HS_400_ES ||
 		    mmc->selected_mode == UHS_SDR25 ||
 		    mmc->selected_mode == UHS_SDR50 ||
 		    mmc->selected_mode == UHS_SDR104 ||
@@ -799,6 +801,19 @@ static int sdhci_wait_dat0(struct udevice *dev, int state,
 	return -ETIMEDOUT;
 }
 
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+static int sdhci_set_enhanced_strobe(struct udevice *dev)
+{
+	struct mmc *mmc = mmc_get_mmc_dev(dev);
+	struct sdhci_host *host = mmc->priv;
+
+	if (host->ops && host->ops->set_enhanced_strobe)
+		return host->ops->set_enhanced_strobe(host);
+
+	return -ENOTSUPP;
+}
+#endif
+
 const struct dm_mmc_ops sdhci_ops = {
 	.send_cmd	= sdhci_send_command,
 	.set_ios	= sdhci_set_ios,
@@ -808,6 +823,9 @@ const struct dm_mmc_ops sdhci_ops = {
 	.execute_tuning	= sdhci_execute_tuning,
 #endif
 	.wait_dat0	= sdhci_wait_dat0,
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+	.set_enhanced_strobe = sdhci_set_enhanced_strobe,
+#endif
 };
 #else
 static const struct mmc_ops sdhci_ops = {
diff --git a/include/sdhci.h b/include/sdhci.h
index c8d69f5a63f7..88f1917480b6 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -272,6 +272,18 @@ struct sdhci_ops {
 	int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
 	int (*set_delay)(struct sdhci_host *host);
 	int	(*deferred_probe)(struct sdhci_host *host);
+
+	/**
+	 * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
+	 *
+	 * This is called after setting the card speed and mode to
+	 * HS400 ES, and should set any host-specific configuration
+	 * necessary for it.
+	 *
+	 * @host: SDHCI host structure
+	 * Return: 0 if successful, -ve on error
+	 */
+	int	(*set_enhanced_strobe)(struct sdhci_host *host);
 };
 
 #define ADMA_MAX_LEN	65532
-- 
2.35.1

[PATCH v5 2/3] rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3399

[Alper Nebi Yasak]

On RK3399, a register bit must be set to enable Enhanced Strobe.
Let the Rockchip SDHCI driver set it when Enhanced Strobe configuration
is requested. However, having it set makes the lower-speed modes stop
working and makes reinitialization fail, so let it be unset as needed in
set_control_reg().

This is mostly ported from Linux's Arasan SDHCI driver which happens
to be the underlying IP. (drivers/mmc/host/sdhci-of-arasan.c in Linux
tree).

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
---

Changes in v5:
- Add tag: "Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>"

Changes in v4:
- Add comment for Rockchip SDHCI set_enhanced_strobe() driver data op

Changes in v2:
- Unset ES bit in rk3399 set_control_reg() to fix a reinit issue
- Don't use unnecessary & for function pointer in ops struct
- Rename rk3399_set_enhanced_strobe -> rk3399_sdhci_set_enhanced_strobe
- Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES

 drivers/mmc/rockchip_sdhci.c | 53 ++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index b91df05de4ff..f4d5a59036a2 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -42,6 +42,9 @@
 	((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
 	PHYCTRL_DLLRDY_DONE)
 
+#define ARASAN_VENDOR_REGISTER		0x78
+#define ARASAN_VENDOR_ENHANCED_STROBE	BIT(0)
+
 /* Rockchip specific Registers */
 #define DWCMSHC_EMMC_DLL_CTRL		0x800
 #define DWCMSHC_EMMC_DLL_CTRL_RESET	BIT(1)
@@ -117,6 +120,19 @@ struct sdhci_data {
 	 * Return: 0 if successful, -ve on error
 	 */
 	int (*set_ios_post)(struct sdhci_host *host);
+
+	/**
+	 * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
+	 *
+	 * This is the set_enhanced_strobe() SDHCI operation that should
+	 * be used for the hardware this driver data is associated with.
+	 * Normally, this is used to set any host-specific configuration
+	 * necessary for HS400 ES.
+	 *
+	 * @host: SDHCI host structure
+	 * Return: 0 if successful, -ve on error
+	 */
+	int (*set_enhanced_strobe)(struct sdhci_host *host);
 };
 
 static int rk3399_emmc_phy_init(struct udevice *dev)
@@ -206,6 +222,21 @@ static int rk3399_emmc_get_phy(struct udevice *dev)
 	return 0;
 }
 
+static int rk3399_sdhci_set_enhanced_strobe(struct sdhci_host *host)
+{
+	struct mmc *mmc = host->mmc;
+	u32 vendor;
+
+	vendor = sdhci_readl(host, ARASAN_VENDOR_REGISTER);
+	if (mmc->selected_mode == MMC_HS_400_ES)
+		vendor |= ARASAN_VENDOR_ENHANCED_STROBE;
+	else
+		vendor &= ~ARASAN_VENDOR_ENHANCED_STROBE;
+	sdhci_writel(host, vendor, ARASAN_VENDOR_REGISTER);
+
+	return 0;
+}
+
 static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
 {
 	struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
@@ -217,6 +248,15 @@ static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
 		rk3399_emmc_phy_power_off(priv->phy);
 
 	sdhci_set_control_reg(host);
+
+	/*
+	 * Reinitializing the device tries to set it to lower-speed modes
+	 * first, which fails if the Enhanced Strobe bit is set, making
+	 * the device impossible to use. Set the correct value here to
+	 * let reinitialization attempts succeed.
+	 */
+	if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT))
+		rk3399_sdhci_set_enhanced_strobe(host);
 };
 
 static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
@@ -409,10 +449,22 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 	return ret;
 }
 
+static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
+{
+	struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+	struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
+
+	if (data->set_enhanced_strobe)
+		return data->set_enhanced_strobe(host);
+
+	return -ENOTSUPP;
+}
+
 static struct sdhci_ops rockchip_sdhci_ops = {
 	.set_ios_post	= rockchip_sdhci_set_ios_post,
 	.platform_execute_tuning = &rockchip_sdhci_execute_tuning,
 	.set_control_reg = rockchip_sdhci_set_control_reg,
+	.set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
 };
 
 static int rockchip_sdhci_probe(struct udevice *dev)
@@ -495,6 +547,7 @@ static const struct sdhci_data rk3399_data = {
 	.emmc_phy_init = rk3399_emmc_phy_init,
 	.set_control_reg = rk3399_sdhci_set_control_reg,
 	.set_ios_post = rk3399_sdhci_set_ios_post,
+	.set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
 };
 
 static const struct sdhci_data rk3568_data = {
-- 
2.35.1

[PATCH v5 3/3] rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568

[Alper Nebi Yasak]

On RK3568, a register bit must be set to enable Enhanced Strobe.
However, it appears that the address of this register may differ from
vendor to vendor and should be read from the underlying MMC IP. Let the
Rockchip SDHCI driver read this address and set the relevant bit when
Enhanced Strobe configuration is requested.

The IP uses a custom mode select value (0x7) for HS400, use that instead
of the common but non-standard SDHCI_CTRL_HS400 value (0x5). Also add
some necessary DLL_STRBIN and DLL_TXCLK configuration for HS400.

Additionally, a bit signifying that the connected hardware is an eMMC
chip must be set to enable Data Strobe for HS400 and HS400ES modes. Also
make the driver set this bit as appropriate.

This is partly ported from Linux's Synopsys DWC MSHC driver which
happens to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in
Linux tree).

Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
---
This is a fixed version I received off-list from Yifeng. I didn't modify
the diff, but added a paragraph in the commit message mentioning their
changes and adjusted the signoffs in the end.

Didn't add the Reviewed-by tag due to changes.

Changes in v5:
- Incorporate RK3568 HS400ES fixes from Yifeng Zhao:
  - Use DWCMSHC_CTRL_HS400 = 0x7, instead of SDHCI_CTRL_HS400 = 0x5
  - Configure DWCMSHC_CARD_IS_EMMC in rk3568_sdhci_set_ios_post()
  - Configure DLL_STRBIN and DLL_TXCLK for HS400.

Changes in v3:
- Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init()

Changes in v2:
- Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe
- Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES

 drivers/mmc/rockchip_sdhci.c | 64 ++++++++++++++++++++++++++++++++----
 1 file changed, 58 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index f4d5a59036a2..f3f9d83ba36f 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -22,6 +22,8 @@
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/hardware.h>
 
+/* DWCMSHC specific Mode Select value */
+#define DWCMSHC_CTRL_HS400		0x7
 /* 400KHz is max freq for card ID etc. Use that as min */
 #define EMMC_MIN_FREQ	400000
 #define KHz	(1000)
@@ -45,6 +47,14 @@
 #define ARASAN_VENDOR_REGISTER		0x78
 #define ARASAN_VENDOR_ENHANCED_STROBE	BIT(0)
 
+/* DWC IP vendor area 1 pointer */
+#define DWCMSHC_P_VENDOR_AREA1		0xe8
+#define DWCMSHC_AREA1_MASK		GENMASK(11, 0)
+/* Offset inside the vendor area 1 */
+#define DWCMSHC_EMMC_CONTROL		0x2c
+#define DWCMSHC_CARD_IS_EMMC		BIT(0)
+#define DWCMSHC_ENHANCED_STROBE		BIT(8)
+
 /* Rockchip specific Registers */
 #define DWCMSHC_EMMC_DLL_CTRL		0x800
 #define DWCMSHC_EMMC_DLL_CTRL_RESET	BIT(1)
@@ -60,8 +70,14 @@
 #define DWCMSHC_EMMC_DLL_INC_VALUE	2
 #define DWCMSHC_EMMC_DLL_INC		8
 #define DWCMSHC_EMMC_DLL_DLYENA		BIT(27)
-#define DLL_TXCLK_TAPNUM_DEFAULT	0x10
-#define DLL_STRBIN_TAPNUM_DEFAULT	0x3
+#define DLL_TXCLK_TAPNUM_DEFAULT	0xA
+
+#define DLL_STRBIN_TAPNUM_DEFAULT	0x8
+#define DLL_STRBIN_TAPNUM_FROM_SW	BIT(24)
+#define DLL_STRBIN_DELAY_NUM_SEL	BIT(26)
+#define DLL_STRBIN_DELAY_NUM_OFFSET	16
+#define DLL_STRBIN_DELAY_NUM_DEFAULT	0x16
+
 #define DLL_TXCLK_TAPNUM_FROM_SW	BIT(24)
 #define DWCMSHC_EMMC_DLL_LOCKED		BIT(8)
 #define DWCMSHC_EMMC_DLL_TIMEOUT	BIT(9)
@@ -327,7 +343,8 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
 		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
 
 		extra = DWCMSHC_EMMC_DLL_DLYENA |
-			DLL_STRBIN_TAPNUM_DEFAULT;
+			DLL_STRBIN_TAPNUM_DEFAULT |
+			DLL_STRBIN_TAPNUM_FROM_SW;
 		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 	} else {
 		/* reset the clock phase when the frequency is lower than 100MHz */
@@ -335,7 +352,15 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
 		extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
 		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
-		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
+		/*
+		 * Before switching to hs400es mode, the driver will enable
+		 * enhanced strobe first. PHY needs to configure the parameters
+		 * of enhanced strobe first.
+		 */
+		extra = DWCMSHC_EMMC_DLL_DLYENA |
+			DLL_STRBIN_DELAY_NUM_SEL |
+			DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
+		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 	}
 
 	return 0;
@@ -346,11 +371,30 @@ static int rk3568_emmc_get_phy(struct udevice *dev)
 	return 0;
 }
 
+static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
+{
+	struct mmc *mmc = host->mmc;
+	u32 vendor;
+	int reg;
+
+	reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
+	      + DWCMSHC_EMMC_CONTROL;
+
+	vendor = sdhci_readl(host, reg);
+	if (mmc->selected_mode == MMC_HS_400_ES)
+		vendor |= DWCMSHC_ENHANCED_STROBE;
+	else
+		vendor &= ~DWCMSHC_ENHANCED_STROBE;
+	sdhci_writel(host, vendor, reg);
+
+	return 0;
+}
+
 static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
 {
 	struct mmc *mmc = host->mmc;
 	uint clock = mmc->tran_speed;
-	u32 reg;
+	u32 reg, vendor_reg;
 
 	if (!clock)
 		clock = mmc->clock;
@@ -360,8 +404,15 @@ static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
 	if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
 		reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 		reg &= ~SDHCI_CTRL_UHS_MASK;
-		reg |= SDHCI_CTRL_HS400;
+		reg |= DWCMSHC_CTRL_HS400;
 		sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+
+		vendor_reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
+			     + DWCMSHC_EMMC_CONTROL;
+		/* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
+		reg = sdhci_readw(host, vendor_reg);
+		reg |= DWCMSHC_CARD_IS_EMMC;
+		sdhci_writew(host, reg, vendor_reg);
 	} else {
 		sdhci_set_uhs_timing(host);
 	}
@@ -554,6 +605,7 @@ static const struct sdhci_data rk3568_data = {
 	.get_phy = rk3568_emmc_get_phy,
 	.emmc_phy_init = rk3568_emmc_phy_init,
 	.set_ios_post = rk3568_sdhci_set_ios_post,
+	.set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe,
 };
 
 static const struct udevice_id sdhci_ids[] = {
-- 
2.35.1

Re: [PATCH v5 3/3] rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568

[zyf]

Hi all,

This series have been tested successfully on the RK3568 EVB1.

Test info：
=> mmc list 
mmc@fe2b0000: 1
mmc@fe310000: 0 (eMMC)
mmc info 
Device: mmc@fe310000
Manufacturer ID: 45
OEM: 100
Name: DA601 
Bus Speed: 200000000
Mode: HS400ES (200MHz)
Rd Block Len: 512
MMC version 5.1
High Capacity: Yes
Capacity: 14.7 GiB
Bus Width: 8-bit DDR
Erase Group Size: 512 KiB
HC WP Group Size: 8 MiB
User Capacity: 14.7 GiB WRREL
Boot Capacity: 4 MiB ENH
RPMB Capacity: 4 MiB ENH
Boot area 0 is not write protected
Boot area 1 is not write protected
=> mmc read 0x30000000 0 100000
MMC read: dev # 0, block # 0, count 1048576 ... 1048576 blocks read: OK
=> mmc write 0x30000000 0 100000
MMC write: dev # 0, block # 0, count 1048576 ... 1048576 blocks written: OK

Test config:
diff --git a/arch/arm/dts/rk3568-u-boot.dtsi b/arch/arm/dts/rk3568-u-boot.dtsi
index 5a80dda275..bd98bd6191 100644
--- a/arch/arm/dts/rk3568-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-u-boot.dtsi
@@ -49,6 +49,8 @@
        bus-width = <8>;
        u-boot,dm-spl;
        mmc-hs200-1_8v;
+       mmc-hs400-1_8v;
+       mmc-hs400-enhanced-strobe;
        status = "okay";
 };
 
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index 435be99edf..313f618723 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -41,6 +41,10 @@ CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_VERBOSE=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y

Best regards,
Yifeng

>On RK3568, a register bit must be set to enable Enhanced Strobe.
>However, it appears that the address of this register may differ from
>vendor to vendor and should be read from the underlying MMC IP. Let the
>Rockchip SDHCI driver read this address and set the relevant bit when
>Enhanced Strobe configuration is requested.
>
>The IP uses a custom mode select value (0x7) for HS400, use that instead
>of the common but non-standard SDHCI_CTRL_HS400 value (0x5). Also add
>some necessary DLL_STRBIN and DLL_TXCLK configuration for HS400.
>
>Additionally, a bit signifying that the connected hardware is an eMMC
>chip must be set to enable Data Strobe for HS400 and HS400ES modes. Also
>make the driver set this bit as appropriate.
>
>This is partly ported from Linux's Synopsys DWC MSHC driver which
>happens to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in
>Linux tree).
>
>Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
>Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
>Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
>---
>This is a fixed version I received off-list from Yifeng. I didn't modify
>the diff, but added a paragraph in the commit message mentioning their
>changes and adjusted the signoffs in the end.
>
>Didn't add the Reviewed-by tag due to changes.
>
>Changes in v5:
>- Incorporate RK3568 HS400ES fixes from Yifeng Zhao:
>  - Use DWCMSHC_CTRL_HS400 = 0x7, instead of SDHCI_CTRL_HS400 = 0x5
>  - Configure DWCMSHC_CARD_IS_EMMC in rk3568_sdhci_set_ios_post()
>  - Configure DLL_STRBIN and DLL_TXCLK for HS400.
>
>Changes in v3:
>- Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init()
>
>Changes in v2:
>- Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe
>- Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES
>
>drivers/mmc/rockchip_sdhci.c | 64 ++++++++++++++++++++++++++++++++----
>1 file changed, 58 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
>index f4d5a59036a2..f3f9d83ba36f 100644
>--- a/drivers/mmc/rockchip_sdhci.c
>+++ b/drivers/mmc/rockchip_sdhci.c
>@@ -22,6 +22,8 @@
>#include <asm/arch-rockchip/clock.h>
>#include <asm/arch-rockchip/hardware.h>
>+/* DWCMSHC specific Mode Select value */
>+#define DWCMSHC_CTRL_HS400	0x7
>/* 400KHz is max freq for card ID etc. Use that as min */
>#define EMMC_MIN_FREQ	400000
>#define KHz	(1000)
>@@ -45,6 +47,14 @@
>#define ARASAN_VENDOR_REGISTER	0x78
>#define ARASAN_VENDOR_ENHANCED_STROBE	BIT(0)
>+/* DWC IP vendor area 1 pointer */
>+#define DWCMSHC_P_VENDOR_AREA1	0xe8
>+#define DWCMSHC_AREA1_MASK	GENMASK(11, 0)
>+/* Offset inside the vendor area 1 */
>+#define DWCMSHC_EMMC_CONTROL	0x2c
>+#define DWCMSHC_CARD_IS_EMMC	BIT(0)
>+#define DWCMSHC_ENHANCED_STROBE	BIT(8)
>+
>/* Rockchip specific Registers */
>#define DWCMSHC_EMMC_DLL_CTRL	0x800
>#define DWCMSHC_EMMC_DLL_CTRL_RESET	BIT(1)
>@@ -60,8 +70,14 @@
>#define DWCMSHC_EMMC_DLL_INC_VALUE	2
>#define DWCMSHC_EMMC_DLL_INC	8
>#define DWCMSHC_EMMC_DLL_DLYENA	BIT(27)
>-#define DLL_TXCLK_TAPNUM_DEFAULT	0x10
>-#define DLL_STRBIN_TAPNUM_DEFAULT	0x3
>+#define DLL_TXCLK_TAPNUM_DEFAULT	0xA
>+
>+#define DLL_STRBIN_TAPNUM_DEFAULT	0x8
>+#define DLL_STRBIN_TAPNUM_FROM_SW	BIT(24)
>+#define DLL_STRBIN_DELAY_NUM_SEL	BIT(26)
>+#define DLL_STRBIN_DELAY_NUM_OFFSET	16
>+#define DLL_STRBIN_DELAY_NUM_DEFAULT	0x16
>+
>#define DLL_TXCLK_TAPNUM_FROM_SW	BIT(24)
>#define DWCMSHC_EMMC_DLL_LOCKED	BIT(8)
>#define DWCMSHC_EMMC_DLL_TIMEOUT	BIT(9)
>@@ -327,7 +343,8 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
>sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
>extra = DWCMSHC_EMMC_DLL_DLYENA |
>-	DLL_STRBIN_TAPNUM_DEFAULT;
>+	DLL_STRBIN_TAPNUM_DEFAULT |
>+	DLL_STRBIN_TAPNUM_FROM_SW;
>sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
>} else {
>/* reset the clock phase when the frequency is lower than 100MHz */
>@@ -335,7 +352,15 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
>extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
>sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
>sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
>-	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
>+	/*
>+	* Before switching to hs400es mode, the driver will enable
>+	* enhanced strobe first. PHY needs to configure the parameters
>+	* of enhanced strobe first.
>+	*/
>+	extra = DWCMSHC_EMMC_DLL_DLYENA |
>+	DLL_STRBIN_DELAY_NUM_SEL |
>+	DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
>+	sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
>}
>return 0;
>@@ -346,11 +371,30 @@ static int rk3568_emmc_get_phy(struct udevice *dev)
>return 0;
>}
>+static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
>+{
>+	struct mmc *mmc = host->mmc;
>+	u32 vendor;
>+	int reg;
>+
>+	reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
>+	      + DWCMSHC_EMMC_CONTROL;
>+
>+	vendor = sdhci_readl(host, reg);
>+	if (mmc->selected_mode == MMC_HS_400_ES)
>+	vendor |= DWCMSHC_ENHANCED_STROBE;
>+	else
>+	vendor &= ~DWCMSHC_ENHANCED_STROBE;
>+	sdhci_writel(host, vendor, reg);
>+
>+	return 0;
>+}
>+
>static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
>{
>struct mmc *mmc = host->mmc;
>uint clock = mmc->tran_speed;
>-	u32 reg;
>+	u32 reg, vendor_reg;
>if (!clock)
>clock = mmc->clock;
>@@ -360,8 +404,15 @@ static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
>if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
>reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
>reg &= ~SDHCI_CTRL_UHS_MASK;
>-	reg |= SDHCI_CTRL_HS400;
>+	reg |= DWCMSHC_CTRL_HS400;
>sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
>+
>+	vendor_reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
>+	     + DWCMSHC_EMMC_CONTROL;
>+	/* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
>+	reg = sdhci_readw(host, vendor_reg);
>+	reg |= DWCMSHC_CARD_IS_EMMC;
>+	sdhci_writew(host, reg, vendor_reg);
>} else {
>sdhci_set_uhs_timing(host);
>}
>@@ -554,6 +605,7 @@ static const struct sdhci_data rk3568_data = {
>.get_phy = rk3568_emmc_get_phy,
>.emmc_phy_init = rk3568_emmc_phy_init,
>.set_ios_post = rk3568_sdhci_set_ios_post,
>+	.set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe,
>};
>static const struct udevice_id sdhci_ids[] = {
>--
>2.35.1

Re: [PATCH v5 1/3] mmc: sdhci: Add HS400 Enhanced Strobe support

[Kever Yang]

HI Alper,

On 2022/3/16 01:46, Alper Nebi Yasak wrote:
> Delegate setting the Enhanced Strobe configuration to individual drivers
> if they set a function for it. Return -ENOTSUPP if they do not, like
> what the MMC uclass does.
>
> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever

> ---
>
> (no changes since v4)
>
> Changes in v4:
> - Add comment for SDHCI set_enhanced_strobe() operation
>
> Changes in v2:
> - Add tag: "Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>"
>
>   drivers/mmc/sdhci.c | 18 ++++++++++++++++++
>   include/sdhci.h     | 12 ++++++++++++
>   2 files changed, 30 insertions(+)
>
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> index 766e4a6b0c5e..bf989a594f7e 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -513,6 +513,7 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
>   		reg |= SDHCI_CTRL_UHS_SDR104;
>   		break;
>   	case MMC_HS_400:
> +	case MMC_HS_400_ES:
>   		reg |= SDHCI_CTRL_HS400;
>   		break;
>   	default:
> @@ -666,6 +667,7 @@ static int sdhci_set_ios(struct mmc *mmc)
>   		    mmc->selected_mode == MMC_DDR_52 ||
>   		    mmc->selected_mode == MMC_HS_200 ||
>   		    mmc->selected_mode == MMC_HS_400 ||
> +		    mmc->selected_mode == MMC_HS_400_ES ||
>   		    mmc->selected_mode == UHS_SDR25 ||
>   		    mmc->selected_mode == UHS_SDR50 ||
>   		    mmc->selected_mode == UHS_SDR104 ||
> @@ -799,6 +801,19 @@ static int sdhci_wait_dat0(struct udevice *dev, int state,
>   	return -ETIMEDOUT;
>   }
>   
> +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
> +static int sdhci_set_enhanced_strobe(struct udevice *dev)
> +{
> +	struct mmc *mmc = mmc_get_mmc_dev(dev);
> +	struct sdhci_host *host = mmc->priv;
> +
> +	if (host->ops && host->ops->set_enhanced_strobe)
> +		return host->ops->set_enhanced_strobe(host);
> +
> +	return -ENOTSUPP;
> +}
> +#endif
> +
>   const struct dm_mmc_ops sdhci_ops = {
>   	.send_cmd	= sdhci_send_command,
>   	.set_ios	= sdhci_set_ios,
> @@ -808,6 +823,9 @@ const struct dm_mmc_ops sdhci_ops = {
>   	.execute_tuning	= sdhci_execute_tuning,
>   #endif
>   	.wait_dat0	= sdhci_wait_dat0,
> +#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
> +	.set_enhanced_strobe = sdhci_set_enhanced_strobe,
> +#endif
>   };
>   #else
>   static const struct mmc_ops sdhci_ops = {
> diff --git a/include/sdhci.h b/include/sdhci.h
> index c8d69f5a63f7..88f1917480b6 100644
> --- a/include/sdhci.h
> +++ b/include/sdhci.h
> @@ -272,6 +272,18 @@ struct sdhci_ops {
>   	int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
>   	int (*set_delay)(struct sdhci_host *host);
>   	int	(*deferred_probe)(struct sdhci_host *host);
> +
> +	/**
> +	 * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
> +	 *
> +	 * This is called after setting the card speed and mode to
> +	 * HS400 ES, and should set any host-specific configuration
> +	 * necessary for it.
> +	 *
> +	 * @host: SDHCI host structure
> +	 * Return: 0 if successful, -ve on error
> +	 */
> +	int	(*set_enhanced_strobe)(struct sdhci_host *host);
>   };
>   
>   #define ADMA_MAX_LEN	65532

Re: [PATCH v5 2/3] rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3399

[Kever Yang]

On 2022/3/16 01:46, Alper Nebi Yasak wrote:
> On RK3399, a register bit must be set to enable Enhanced Strobe.
> Let the Rockchip SDHCI driver set it when Enhanced Strobe configuration
> is requested. However, having it set makes the lower-speed modes stop
> working and makes reinitialization fail, so let it be unset as needed in
> set_control_reg().
>
> This is mostly ported from Linux's Arasan SDHCI driver which happens
> to be the underlying IP. (drivers/mmc/host/sdhci-of-arasan.c in Linux
> tree).
>
> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>


Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever

> ---
>
> Changes in v5:
> - Add tag: "Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>"
>
> Changes in v4:
> - Add comment for Rockchip SDHCI set_enhanced_strobe() driver data op
>
> Changes in v2:
> - Unset ES bit in rk3399 set_control_reg() to fix a reinit issue
> - Don't use unnecessary & for function pointer in ops struct
> - Rename rk3399_set_enhanced_strobe -> rk3399_sdhci_set_enhanced_strobe
> - Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES
>
>   drivers/mmc/rockchip_sdhci.c | 53 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 53 insertions(+)
>
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index b91df05de4ff..f4d5a59036a2 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -42,6 +42,9 @@
>   	((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
>   	PHYCTRL_DLLRDY_DONE)
>   
> +#define ARASAN_VENDOR_REGISTER		0x78
> +#define ARASAN_VENDOR_ENHANCED_STROBE	BIT(0)
> +
>   /* Rockchip specific Registers */
>   #define DWCMSHC_EMMC_DLL_CTRL		0x800
>   #define DWCMSHC_EMMC_DLL_CTRL_RESET	BIT(1)
> @@ -117,6 +120,19 @@ struct sdhci_data {
>   	 * Return: 0 if successful, -ve on error
>   	 */
>   	int (*set_ios_post)(struct sdhci_host *host);
> +
> +	/**
> +	 * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
> +	 *
> +	 * This is the set_enhanced_strobe() SDHCI operation that should
> +	 * be used for the hardware this driver data is associated with.
> +	 * Normally, this is used to set any host-specific configuration
> +	 * necessary for HS400 ES.
> +	 *
> +	 * @host: SDHCI host structure
> +	 * Return: 0 if successful, -ve on error
> +	 */
> +	int (*set_enhanced_strobe)(struct sdhci_host *host);
>   };
>   
>   static int rk3399_emmc_phy_init(struct udevice *dev)
> @@ -206,6 +222,21 @@ static int rk3399_emmc_get_phy(struct udevice *dev)
>   	return 0;
>   }
>   
> +static int rk3399_sdhci_set_enhanced_strobe(struct sdhci_host *host)
> +{
> +	struct mmc *mmc = host->mmc;
> +	u32 vendor;
> +
> +	vendor = sdhci_readl(host, ARASAN_VENDOR_REGISTER);
> +	if (mmc->selected_mode == MMC_HS_400_ES)
> +		vendor |= ARASAN_VENDOR_ENHANCED_STROBE;
> +	else
> +		vendor &= ~ARASAN_VENDOR_ENHANCED_STROBE;
> +	sdhci_writel(host, vendor, ARASAN_VENDOR_REGISTER);
> +
> +	return 0;
> +}
> +
>   static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
>   {
>   	struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
> @@ -217,6 +248,15 @@ static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
>   		rk3399_emmc_phy_power_off(priv->phy);
>   
>   	sdhci_set_control_reg(host);
> +
> +	/*
> +	 * Reinitializing the device tries to set it to lower-speed modes
> +	 * first, which fails if the Enhanced Strobe bit is set, making
> +	 * the device impossible to use. Set the correct value here to
> +	 * let reinitialization attempts succeed.
> +	 */
> +	if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT))
> +		rk3399_sdhci_set_enhanced_strobe(host);
>   };
>   
>   static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
> @@ -409,10 +449,22 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
>   	return ret;
>   }
>   
> +static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
> +{
> +	struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
> +	struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
> +
> +	if (data->set_enhanced_strobe)
> +		return data->set_enhanced_strobe(host);
> +
> +	return -ENOTSUPP;
> +}
> +
>   static struct sdhci_ops rockchip_sdhci_ops = {
>   	.set_ios_post	= rockchip_sdhci_set_ios_post,
>   	.platform_execute_tuning = &rockchip_sdhci_execute_tuning,
>   	.set_control_reg = rockchip_sdhci_set_control_reg,
> +	.set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
>   };
>   
>   static int rockchip_sdhci_probe(struct udevice *dev)
> @@ -495,6 +547,7 @@ static const struct sdhci_data rk3399_data = {
>   	.emmc_phy_init = rk3399_emmc_phy_init,
>   	.set_control_reg = rk3399_sdhci_set_control_reg,
>   	.set_ios_post = rk3399_sdhci_set_ios_post,
> +	.set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
>   };
>   
>   static const struct sdhci_data rk3568_data = {

Re: [PATCH v5 3/3] rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568

[Kever Yang]

On 2022/3/16 01:46, Alper Nebi Yasak wrote:
> On RK3568, a register bit must be set to enable Enhanced Strobe.
> However, it appears that the address of this register may differ from
> vendor to vendor and should be read from the underlying MMC IP. Let the
> Rockchip SDHCI driver read this address and set the relevant bit when
> Enhanced Strobe configuration is requested.
>
> The IP uses a custom mode select value (0x7) for HS400, use that instead
> of the common but non-standard SDHCI_CTRL_HS400 value (0x5). Also add
> some necessary DLL_STRBIN and DLL_TXCLK configuration for HS400.
>
> Additionally, a bit signifying that the connected hardware is an eMMC
> chip must be set to enable Data Strobe for HS400 and HS400ES modes. Also
> make the driver set this bit as appropriate.
>
> This is partly ported from Linux's Synopsys DWC MSHC driver which
> happens to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in
> Linux tree).
>
> Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>


Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever

> ---
> This is a fixed version I received off-list from Yifeng. I didn't modify
> the diff, but added a paragraph in the commit message mentioning their
> changes and adjusted the signoffs in the end.
>
> Didn't add the Reviewed-by tag due to changes.
>
> Changes in v5:
> - Incorporate RK3568 HS400ES fixes from Yifeng Zhao:
>    - Use DWCMSHC_CTRL_HS400 = 0x7, instead of SDHCI_CTRL_HS400 = 0x5
>    - Configure DWCMSHC_CARD_IS_EMMC in rk3568_sdhci_set_ios_post()
>    - Configure DLL_STRBIN and DLL_TXCLK for HS400.
>
> Changes in v3:
> - Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init()
>
> Changes in v2:
> - Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe
> - Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES
>
>   drivers/mmc/rockchip_sdhci.c | 64 ++++++++++++++++++++++++++++++++----
>   1 file changed, 58 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index f4d5a59036a2..f3f9d83ba36f 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -22,6 +22,8 @@
>   #include <asm/arch-rockchip/clock.h>
>   #include <asm/arch-rockchip/hardware.h>
>   
> +/* DWCMSHC specific Mode Select value */
> +#define DWCMSHC_CTRL_HS400		0x7
>   /* 400KHz is max freq for card ID etc. Use that as min */
>   #define EMMC_MIN_FREQ	400000
>   #define KHz	(1000)
> @@ -45,6 +47,14 @@
>   #define ARASAN_VENDOR_REGISTER		0x78
>   #define ARASAN_VENDOR_ENHANCED_STROBE	BIT(0)
>   
> +/* DWC IP vendor area 1 pointer */
> +#define DWCMSHC_P_VENDOR_AREA1		0xe8
> +#define DWCMSHC_AREA1_MASK		GENMASK(11, 0)
> +/* Offset inside the vendor area 1 */
> +#define DWCMSHC_EMMC_CONTROL		0x2c
> +#define DWCMSHC_CARD_IS_EMMC		BIT(0)
> +#define DWCMSHC_ENHANCED_STROBE		BIT(8)
> +
>   /* Rockchip specific Registers */
>   #define DWCMSHC_EMMC_DLL_CTRL		0x800
>   #define DWCMSHC_EMMC_DLL_CTRL_RESET	BIT(1)
> @@ -60,8 +70,14 @@
>   #define DWCMSHC_EMMC_DLL_INC_VALUE	2
>   #define DWCMSHC_EMMC_DLL_INC		8
>   #define DWCMSHC_EMMC_DLL_DLYENA		BIT(27)
> -#define DLL_TXCLK_TAPNUM_DEFAULT	0x10
> -#define DLL_STRBIN_TAPNUM_DEFAULT	0x3
> +#define DLL_TXCLK_TAPNUM_DEFAULT	0xA
> +
> +#define DLL_STRBIN_TAPNUM_DEFAULT	0x8
> +#define DLL_STRBIN_TAPNUM_FROM_SW	BIT(24)
> +#define DLL_STRBIN_DELAY_NUM_SEL	BIT(26)
> +#define DLL_STRBIN_DELAY_NUM_OFFSET	16
> +#define DLL_STRBIN_DELAY_NUM_DEFAULT	0x16
> +
>   #define DLL_TXCLK_TAPNUM_FROM_SW	BIT(24)
>   #define DWCMSHC_EMMC_DLL_LOCKED		BIT(8)
>   #define DWCMSHC_EMMC_DLL_TIMEOUT	BIT(9)
> @@ -327,7 +343,8 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
>   		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
>   
>   		extra = DWCMSHC_EMMC_DLL_DLYENA |
> -			DLL_STRBIN_TAPNUM_DEFAULT;
> +			DLL_STRBIN_TAPNUM_DEFAULT |
> +			DLL_STRBIN_TAPNUM_FROM_SW;
>   		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
>   	} else {
>   		/* reset the clock phase when the frequency is lower than 100MHz */
> @@ -335,7 +352,15 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
>   		extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
>   		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
>   		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
> -		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
> +		/*
> +		 * Before switching to hs400es mode, the driver will enable
> +		 * enhanced strobe first. PHY needs to configure the parameters
> +		 * of enhanced strobe first.
> +		 */
> +		extra = DWCMSHC_EMMC_DLL_DLYENA |
> +			DLL_STRBIN_DELAY_NUM_SEL |
> +			DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
> +		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
>   	}
>   
>   	return 0;
> @@ -346,11 +371,30 @@ static int rk3568_emmc_get_phy(struct udevice *dev)
>   	return 0;
>   }
>   
> +static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
> +{
> +	struct mmc *mmc = host->mmc;
> +	u32 vendor;
> +	int reg;
> +
> +	reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
> +	      + DWCMSHC_EMMC_CONTROL;
> +
> +	vendor = sdhci_readl(host, reg);
> +	if (mmc->selected_mode == MMC_HS_400_ES)
> +		vendor |= DWCMSHC_ENHANCED_STROBE;
> +	else
> +		vendor &= ~DWCMSHC_ENHANCED_STROBE;
> +	sdhci_writel(host, vendor, reg);
> +
> +	return 0;
> +}
> +
>   static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
>   {
>   	struct mmc *mmc = host->mmc;
>   	uint clock = mmc->tran_speed;
> -	u32 reg;
> +	u32 reg, vendor_reg;
>   
>   	if (!clock)
>   		clock = mmc->clock;
> @@ -360,8 +404,15 @@ static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
>   	if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
>   		reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
>   		reg &= ~SDHCI_CTRL_UHS_MASK;
> -		reg |= SDHCI_CTRL_HS400;
> +		reg |= DWCMSHC_CTRL_HS400;
>   		sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
> +
> +		vendor_reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
> +			     + DWCMSHC_EMMC_CONTROL;
> +		/* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
> +		reg = sdhci_readw(host, vendor_reg);
> +		reg |= DWCMSHC_CARD_IS_EMMC;
> +		sdhci_writew(host, reg, vendor_reg);
>   	} else {
>   		sdhci_set_uhs_timing(host);
>   	}
> @@ -554,6 +605,7 @@ static const struct sdhci_data rk3568_data = {
>   	.get_phy = rk3568_emmc_get_phy,
>   	.emmc_phy_init = rk3568_emmc_phy_init,
>   	.set_ios_post = rk3568_sdhci_set_ios_post,
> +	.set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe,
>   };
>   
>   static const struct udevice_id sdhci_ids[] = {

Re: [PATCH v5 0/3] rockchip: sdhci: Add HS400 Enhanced Strobe support

[Jaehoon Chung]

Hi,

On 3/16/22 02:46, Alper Nebi Yasak wrote:
> This series implements support for the HS400 Enhanced Strobe mode on the
> Rockchip SDHCI driver, for both RK3399 and RK3568. To test, I'm building
> for chromebook_kevin with the following configs enabled:
> 
>     +CONFIG_MMC_SPEED_MODE_SET=y
>      [...]
>      CONFIG_MMC_PWRSEQ=y
>     +CONFIG_MMC_IO_VOLTAGE=y
>     +CONFIG_MMC_UHS_SUPPORT=y
>     +CONFIG_MMC_HS400_ES_SUPPORT=y
>     +CONFIG_MMC_HS400_SUPPORT=y
>      CONFIG_MMC_DW=y
>      CONFIG_MMC_DW_ROCKCHIP=y
>      CONFIG_MMC_SDHCI=y
>     +CONFIG_MMC_SDHCI_SDMA=y
>      CONFIG_MMC_SDHCI_ROCKCHIP=y
> 
> and running roughly:
> 
>     $ mmc rescan [0|1|3|10|11|12]
>     $ mmc info
>     $ mmc part
>     $ load mmc 0:1 0xd0000000 256MiB.bin
>     $ load mmc 0:1 0xd0000000 16MiB.bin
>     $ load mmc 0:1 0xd0000000 8MiB.bin
> 
> Here's the differences in info and speeds I get with this:
> 
>     Mode                   | Bus Speed    | Bus Width
>     -----------------------+--------------+--------------
>     MMC Legacy             | 25000000     | 8-bit
>     MMC High Speed (26MHz) | 26000000     | 8-bit
>     MMC High Speed (52MHz) | 52000000     | 8-bit
>     HS200 (200MHz)         | 200000000    | 8-bit
>     HS400 (200MHz)         | 200000000    | 8-bit DDR
>     HS400ES (200MHz)       | 200000000    | 8-bit DDR
> 
>     Mode                   | 256 MiB Load | 16 MiB Load  | 8 MiB Load
>     -----------------------+--------------+--------------+--------------
>     MMC Legacy             | ~22.1  MiB/s | ~21.9  MiB/s | ~21.6  MiB/s
>     MMC High Speed (26MHz) | ~22.1  MiB/s | ~21.9  MiB/s | ~21.6  MiB/s
>     MMC High Speed (52MHz) | ~43.7  MiB/s | ~42.8  MiB/s | ~41.7  MiB/s
>     HS200 (200MHz)         | ~161.2 MiB/s | ~149.5 MiB/s | ~137.9 MiB/s
>     HS400 (200MHz)         | ~254.5 MiB/s | ~235.3 MiB/s | ~216.2 MiB/s
>     HS400ES (200MHz)       | ~254.7 MiB/s | ~238.8 MiB/s | ~216.2 MiB/s
> 
> Hope I haven't missed anything. Enabling the configs above for each
> board is left to board maintainers as I can't test on those boards.
> 
> Changes in v5:
> - Incorporate RK3568 HS400ES fixes from Yifeng Zhao:
>   - Use DWCMSHC_CTRL_HS400 = 0x7, instead of SDHCI_CTRL_HS400 = 0x5
>   - Configure DWCMSHC_CARD_IS_EMMC in rk3568_sdhci_set_ios_post()
>   - Configure DLL_STRBIN and DLL_TXCLK for HS400.
> - Drop re-init fix already merged to master
> 
> v4: https://protect2.fireeye.com/v1/url?k=1188e6ba-7003f38c-11896df5-74fe485cbff1-62638f65a0b40d18&q=1&e=1d5ef967-0e2c-4678-89d3-9c866ce2121b&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D283482%26state%3D%2A
> 
> Changes in v4:
> - Add comment for SDHCI set_enhanced_strobe() operation
> - Add comment for Rockchip SDHCI set_enhanced_strobe() driver data op
> 
> v3: https://protect2.fireeye.com/v1/url?k=e0d60bb1-815d1e87-e0d780fe-74fe485cbff1-ae754d5cb8424c27&q=1&e=1d5ef967-0e2c-4678-89d3-9c866ce2121b&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D281327%26state%3D%2A
> 
> Changes in v3:
> - Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init()
> 
> v2: https://protect2.fireeye.com/v1/url?k=418d7235-20066703-418cf97a-74fe485cbff1-5208c5c7e2a5cf22&q=1&e=1d5ef967-0e2c-4678-89d3-9c866ce2121b&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D280494%26state%3D%2A
> 
> Changes in v2:
> - Unset ES bit in rk3399 set_control_reg() to fix a reinit issue
> - Don't use unnecessary & for function pointer in ops struct
> - Rename rk3399_set_enhanced_strobe -> rk3399_sdhci_set_enhanced_strobe
> - Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe
> - Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES
> - Rewrote cover letter
> 
> v1: https://protect2.fireeye.com/v1/url?k=7057862b-11dc931d-70560d64-74fe485cbff1-6d7b0ff32c53c391&q=1&e=1d5ef967-0e2c-4678-89d3-9c866ce2121b&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D269768%26state%3D%2A
> 
> Alper Nebi Yasak (3):
>   mmc: sdhci: Add HS400 Enhanced Strobe support
>   rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3399
>   rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568
> 
>  drivers/mmc/rockchip_sdhci.c | 117 +++++++++++++++++++++++++++++++++--
>  drivers/mmc/sdhci.c          |  18 ++++++
>  include/sdhci.h              |  12 ++++
>  3 files changed, 141 insertions(+), 6 deletions(-)

Applied to u-boot-mmc. 

Best Regards,
Jaehoon Chung

>