* [PATCH v2 0/5] drm/rockchip: add rk3399 display controller support
@ 2016-04-20 6:18 ` Mark Yao
0 siblings, 0 replies; 71+ messages in thread
From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw)
To: David Airlie, Heiko Stuebner, dri-devel, linux-arm-kernel,
linux-rockchip, linux-kernel
Cc: Mark Yao
This series of patches add support for rk3399 display crontroller(vop),
there are two VOP in rk3399 chip, respectively VOP_BIG and VOP_LIT.
most registers layout of this two vop is same, their framework are both
VOP_FULL, the differences of this two is VOP_LIT cut off some features.
Those patches tested on rk3399 evb board.
Changes in v2:
- sort the registers and vop compatible name
- spilt VOP_REG_MASK into a single patch
- make rk3399 vop documentation more readable(Heiko Stübner)
Mark Yao (5):
drm/rockchip: sort registers define by chip's number
dt-bindings: sort Rockchip vop compatible by chip's number
drm/rockchip: vop: introduce VOP_REG_MASK
drm/rockchip: vop: add rk3399 vop support
dt-bindings: add documentation for Rockchip rk3399 display
controllers
.../bindings/display/rockchip/rockchip-vop.txt | 7 +-
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 60 +++--
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 5 +
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 236 ++++++++++++-----
drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 279 +++++++++++++++++---
5 files changed, 447 insertions(+), 140 deletions(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 71+ messages in thread* [PATCH v2 0/5] drm/rockchip: add rk3399 display controller support @ 2016-04-20 6:18 ` Mark Yao 0 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: linux-arm-kernel This series of patches add support for rk3399 display crontroller(vop), there are two VOP in rk3399 chip, respectively VOP_BIG and VOP_LIT. most registers layout of this two vop is same, their framework are both VOP_FULL, the differences of this two is VOP_LIT cut off some features. Those patches tested on rk3399 evb board. Changes in v2: - sort the registers and vop compatible name - spilt VOP_REG_MASK into a single patch - make rk3399 vop documentation more readable(Heiko St?bner) Mark Yao (5): drm/rockchip: sort registers define by chip's number dt-bindings: sort Rockchip vop compatible by chip's number drm/rockchip: vop: introduce VOP_REG_MASK drm/rockchip: vop: add rk3399 vop support dt-bindings: add documentation for Rockchip rk3399 display controllers .../bindings/display/rockchip/rockchip-vop.txt | 7 +- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 60 +++-- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 5 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 236 ++++++++++++----- drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 279 +++++++++++++++++--- 5 files changed, 447 insertions(+), 140 deletions(-) -- 1.7.9.5 ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v2 0/5] drm/rockchip: add rk3399 display controller support @ 2016-04-20 6:18 ` Mark Yao 0 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: David Airlie, Heiko Stuebner, dri-devel, linux-arm-kernel, linux-rockchip, linux-kernel This series of patches add support for rk3399 display crontroller(vop), there are two VOP in rk3399 chip, respectively VOP_BIG and VOP_LIT. most registers layout of this two vop is same, their framework are both VOP_FULL, the differences of this two is VOP_LIT cut off some features. Those patches tested on rk3399 evb board. Changes in v2: - sort the registers and vop compatible name - spilt VOP_REG_MASK into a single patch - make rk3399 vop documentation more readable(Heiko Stübner) Mark Yao (5): drm/rockchip: sort registers define by chip's number dt-bindings: sort Rockchip vop compatible by chip's number drm/rockchip: vop: introduce VOP_REG_MASK drm/rockchip: vop: add rk3399 vop support dt-bindings: add documentation for Rockchip rk3399 display controllers .../bindings/display/rockchip/rockchip-vop.txt | 7 +- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 60 +++-- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 5 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 236 ++++++++++++----- drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 279 +++++++++++++++++--- 5 files changed, 447 insertions(+), 140 deletions(-) -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v2 1/5] drm/rockchip: sort registers define by chip's number 2016-04-20 6:18 ` Mark Yao (?) @ 2016-04-20 6:18 ` Mark Yao -1 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: David Airlie, Heiko Stuebner, dri-devel, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Mark Yao No functional changes, sort the vop registers to make code more readable. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 166 +++++++++++++-------------- drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 88 +++++++------- 2 files changed, 127 insertions(+), 127 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 3166b46..e75b2b8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -50,6 +50,87 @@ static const uint32_t formats_win_lite[] = { DRM_FORMAT_BGR565, }; +static const struct vop_scl_regs rk3066_win_scl = { + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), +}; + +static const struct vop_win_phy rk3036_win0_data = { + .scl = &rk3066_win_scl, + .data_formats = formats_win_full, + .nformats = ARRAY_SIZE(formats_win_full), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), +}; + +static const struct vop_win_phy rk3036_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), +}; + +static const struct vop_win_data rk3036_vop_win_data[] = { + { .base = 0x00, .phy = &rk3036_win0_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x00, .phy = &rk3036_win1_data, + .type = DRM_PLANE_TYPE_CURSOR }, +}; + +static const int rk3036_vop_intrs[] = { + DSP_HOLD_VALID_INTR, + FS_INTR, + LINE_FLAG_INTR, + BUS_ERROR_INTR, +}; + +static const struct vop_intr rk3036_intr = { + .intrs = rk3036_vop_intrs, + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), +}; + +static const struct vop_ctrl rk3036_ctrl_data = { + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { + {RK3036_DSP_CTRL1, 0x00000000}, +}; + +static const struct vop_data rk3036_vop = { + .init_table = rk3036_vop_init_reg_table, + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), + .ctrl = &rk3036_ctrl_data, + .intr = &rk3036_intr, + .win = rk3036_vop_win_data, + .win_size = ARRAY_SIZE(rk3036_vop_win_data), +}; + static const struct vop_scl_extension rk3288_win_full_scl_ext = { .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), @@ -190,92 +271,11 @@ static const struct vop_data rk3288_vop = { .win_size = ARRAY_SIZE(rk3288_vop_win_data), }; -static const struct vop_scl_regs rk3066_win_scl = { - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), -}; - -static const struct vop_win_phy rk3036_win0_data = { - .scl = &rk3066_win_scl, - .data_formats = formats_win_full, - .nformats = ARRAY_SIZE(formats_win_full), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), -}; - -static const struct vop_win_phy rk3036_win1_data = { - .data_formats = formats_win_lite, - .nformats = ARRAY_SIZE(formats_win_lite), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), -}; - -static const struct vop_win_data rk3036_vop_win_data[] = { - { .base = 0x00, .phy = &rk3036_win0_data, - .type = DRM_PLANE_TYPE_PRIMARY }, - { .base = 0x00, .phy = &rk3036_win1_data, - .type = DRM_PLANE_TYPE_CURSOR }, -}; - -static const int rk3036_vop_intrs[] = { - DSP_HOLD_VALID_INTR, - FS_INTR, - LINE_FLAG_INTR, - BUS_ERROR_INTR, -}; - -static const struct vop_intr rk3036_intr = { - .intrs = rk3036_vop_intrs, - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), -}; - -static const struct vop_ctrl rk3036_ctrl_data = { - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), -}; - -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { - {RK3036_DSP_CTRL1, 0x00000000}, -}; - -static const struct vop_data rk3036_vop = { - .init_table = rk3036_vop_init_reg_table, - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), - .ctrl = &rk3036_ctrl_data, - .intr = &rk3036_intr, - .win = rk3036_vop_win_data, - .win_size = ARRAY_SIZE(rk3036_vop_win_data), -}; - static const struct of_device_id vop_driver_dt_match[] = { - { .compatible = "rockchip,rk3288-vop", - .data = &rk3288_vop }, { .compatible = "rockchip,rk3036-vop", .data = &rk3036_vop }, + { .compatible = "rockchip,rk3288-vop", + .data = &rk3288_vop }, {}, }; MODULE_DEVICE_TABLE(of, vop_driver_dt_match); diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index d4b46cb..43903e0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -15,6 +15,50 @@ #ifndef _ROCKCHIP_VOP_REG_H #define _ROCKCHIP_VOP_REG_H +/* rk3036 register definition */ +#define RK3036_SYS_CTRL 0x00 +#define RK3036_DSP_CTRL0 0x04 +#define RK3036_DSP_CTRL1 0x08 +#define RK3036_INT_STATUS 0x10 +#define RK3036_ALPHA_CTRL 0x14 +#define RK3036_WIN0_COLOR_KEY 0x18 +#define RK3036_WIN1_COLOR_KEY 0x1c +#define RK3036_WIN0_YRGB_MST 0x20 +#define RK3036_WIN0_CBR_MST 0x24 +#define RK3036_WIN1_VIR 0x28 +#define RK3036_AXI_BUS_CTRL 0x2c +#define RK3036_WIN0_VIR 0x30 +#define RK3036_WIN0_ACT_INFO 0x34 +#define RK3036_WIN0_DSP_INFO 0x38 +#define RK3036_WIN0_DSP_ST 0x3c +#define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 +#define RK3036_WIN0_SCL_FACTOR_CBR 0x44 +#define RK3036_WIN0_SCL_OFFSET 0x48 +#define RK3036_HWC_MST 0x58 +#define RK3036_HWC_DSP_ST 0x5c +#define RK3036_DSP_HTOTAL_HS_END 0x6c +#define RK3036_DSP_HACT_ST_END 0x70 +#define RK3036_DSP_VTOTAL_VS_END 0x74 +#define RK3036_DSP_VACT_ST_END 0x78 +#define RK3036_DSP_VS_ST_END_F1 0x7c +#define RK3036_DSP_VACT_ST_END_F1 0x80 +#define RK3036_GATHER_TRANSFER 0x84 +#define RK3036_VERSION_INFO 0x94 +#define RK3036_REG_CFG_DONE 0x90 +#define RK3036_WIN1_MST 0xa0 +#define RK3036_WIN1_ACT_INFO 0xb4 +#define RK3036_WIN1_DSP_INFO 0xb8 +#define RK3036_WIN1_DSP_ST 0xbc +#define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 +#define RK3036_WIN1_SCL_OFFSET 0xc8 +#define RK3036_BCSH_CTRL 0xd0 +#define RK3036_BCSH_COLOR_BAR 0xd4 +#define RK3036_BCSH_BCS 0xd8 +#define RK3036_BCSH_H 0xdc +#define RK3036_WIN1_LUT_ADDR 0x400 +#define RK3036_HWC_LUT_ADDR 0x800 +/* rk3036 register definition end */ + /* rk3288 register definition */ #define RK3288_REG_CFG_DONE 0x0000 #define RK3288_VERSION_INFO 0x0004 @@ -122,48 +166,4 @@ #define RK3288_DSP_VACT_ST_END_F1 0x019c /* register definition end */ -/* rk3036 register definition */ -#define RK3036_SYS_CTRL 0x00 -#define RK3036_DSP_CTRL0 0x04 -#define RK3036_DSP_CTRL1 0x08 -#define RK3036_INT_STATUS 0x10 -#define RK3036_ALPHA_CTRL 0x14 -#define RK3036_WIN0_COLOR_KEY 0x18 -#define RK3036_WIN1_COLOR_KEY 0x1c -#define RK3036_WIN0_YRGB_MST 0x20 -#define RK3036_WIN0_CBR_MST 0x24 -#define RK3036_WIN1_VIR 0x28 -#define RK3036_AXI_BUS_CTRL 0x2c -#define RK3036_WIN0_VIR 0x30 -#define RK3036_WIN0_ACT_INFO 0x34 -#define RK3036_WIN0_DSP_INFO 0x38 -#define RK3036_WIN0_DSP_ST 0x3c -#define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 -#define RK3036_WIN0_SCL_FACTOR_CBR 0x44 -#define RK3036_WIN0_SCL_OFFSET 0x48 -#define RK3036_HWC_MST 0x58 -#define RK3036_HWC_DSP_ST 0x5c -#define RK3036_DSP_HTOTAL_HS_END 0x6c -#define RK3036_DSP_HACT_ST_END 0x70 -#define RK3036_DSP_VTOTAL_VS_END 0x74 -#define RK3036_DSP_VACT_ST_END 0x78 -#define RK3036_DSP_VS_ST_END_F1 0x7c -#define RK3036_DSP_VACT_ST_END_F1 0x80 -#define RK3036_GATHER_TRANSFER 0x84 -#define RK3036_VERSION_INFO 0x94 -#define RK3036_REG_CFG_DONE 0x90 -#define RK3036_WIN1_MST 0xa0 -#define RK3036_WIN1_ACT_INFO 0xb4 -#define RK3036_WIN1_DSP_INFO 0xb8 -#define RK3036_WIN1_DSP_ST 0xbc -#define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 -#define RK3036_WIN1_SCL_OFFSET 0xc8 -#define RK3036_BCSH_CTRL 0xd0 -#define RK3036_BCSH_COLOR_BAR 0xd4 -#define RK3036_BCSH_BCS 0xd8 -#define RK3036_BCSH_H 0xdc -#define RK3036_WIN1_LUT_ADDR 0x400 -#define RK3036_HWC_LUT_ADDR 0x800 -/* rk3036 register definition end */ - #endif /* _ROCKCHIP_VOP_REG_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 1/5] drm/rockchip: sort registers define by chip's number @ 2016-04-20 6:18 ` Mark Yao 0 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: linux-arm-kernel No functional changes, sort the vop registers to make code more readable. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 166 +++++++++++++-------------- drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 88 +++++++------- 2 files changed, 127 insertions(+), 127 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 3166b46..e75b2b8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -50,6 +50,87 @@ static const uint32_t formats_win_lite[] = { DRM_FORMAT_BGR565, }; +static const struct vop_scl_regs rk3066_win_scl = { + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), +}; + +static const struct vop_win_phy rk3036_win0_data = { + .scl = &rk3066_win_scl, + .data_formats = formats_win_full, + .nformats = ARRAY_SIZE(formats_win_full), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), +}; + +static const struct vop_win_phy rk3036_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), +}; + +static const struct vop_win_data rk3036_vop_win_data[] = { + { .base = 0x00, .phy = &rk3036_win0_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x00, .phy = &rk3036_win1_data, + .type = DRM_PLANE_TYPE_CURSOR }, +}; + +static const int rk3036_vop_intrs[] = { + DSP_HOLD_VALID_INTR, + FS_INTR, + LINE_FLAG_INTR, + BUS_ERROR_INTR, +}; + +static const struct vop_intr rk3036_intr = { + .intrs = rk3036_vop_intrs, + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), +}; + +static const struct vop_ctrl rk3036_ctrl_data = { + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { + {RK3036_DSP_CTRL1, 0x00000000}, +}; + +static const struct vop_data rk3036_vop = { + .init_table = rk3036_vop_init_reg_table, + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), + .ctrl = &rk3036_ctrl_data, + .intr = &rk3036_intr, + .win = rk3036_vop_win_data, + .win_size = ARRAY_SIZE(rk3036_vop_win_data), +}; + static const struct vop_scl_extension rk3288_win_full_scl_ext = { .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), @@ -190,92 +271,11 @@ static const struct vop_data rk3288_vop = { .win_size = ARRAY_SIZE(rk3288_vop_win_data), }; -static const struct vop_scl_regs rk3066_win_scl = { - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), -}; - -static const struct vop_win_phy rk3036_win0_data = { - .scl = &rk3066_win_scl, - .data_formats = formats_win_full, - .nformats = ARRAY_SIZE(formats_win_full), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), -}; - -static const struct vop_win_phy rk3036_win1_data = { - .data_formats = formats_win_lite, - .nformats = ARRAY_SIZE(formats_win_lite), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), -}; - -static const struct vop_win_data rk3036_vop_win_data[] = { - { .base = 0x00, .phy = &rk3036_win0_data, - .type = DRM_PLANE_TYPE_PRIMARY }, - { .base = 0x00, .phy = &rk3036_win1_data, - .type = DRM_PLANE_TYPE_CURSOR }, -}; - -static const int rk3036_vop_intrs[] = { - DSP_HOLD_VALID_INTR, - FS_INTR, - LINE_FLAG_INTR, - BUS_ERROR_INTR, -}; - -static const struct vop_intr rk3036_intr = { - .intrs = rk3036_vop_intrs, - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), -}; - -static const struct vop_ctrl rk3036_ctrl_data = { - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), -}; - -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { - {RK3036_DSP_CTRL1, 0x00000000}, -}; - -static const struct vop_data rk3036_vop = { - .init_table = rk3036_vop_init_reg_table, - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), - .ctrl = &rk3036_ctrl_data, - .intr = &rk3036_intr, - .win = rk3036_vop_win_data, - .win_size = ARRAY_SIZE(rk3036_vop_win_data), -}; - static const struct of_device_id vop_driver_dt_match[] = { - { .compatible = "rockchip,rk3288-vop", - .data = &rk3288_vop }, { .compatible = "rockchip,rk3036-vop", .data = &rk3036_vop }, + { .compatible = "rockchip,rk3288-vop", + .data = &rk3288_vop }, {}, }; MODULE_DEVICE_TABLE(of, vop_driver_dt_match); diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index d4b46cb..43903e0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -15,6 +15,50 @@ #ifndef _ROCKCHIP_VOP_REG_H #define _ROCKCHIP_VOP_REG_H +/* rk3036 register definition */ +#define RK3036_SYS_CTRL 0x00 +#define RK3036_DSP_CTRL0 0x04 +#define RK3036_DSP_CTRL1 0x08 +#define RK3036_INT_STATUS 0x10 +#define RK3036_ALPHA_CTRL 0x14 +#define RK3036_WIN0_COLOR_KEY 0x18 +#define RK3036_WIN1_COLOR_KEY 0x1c +#define RK3036_WIN0_YRGB_MST 0x20 +#define RK3036_WIN0_CBR_MST 0x24 +#define RK3036_WIN1_VIR 0x28 +#define RK3036_AXI_BUS_CTRL 0x2c +#define RK3036_WIN0_VIR 0x30 +#define RK3036_WIN0_ACT_INFO 0x34 +#define RK3036_WIN0_DSP_INFO 0x38 +#define RK3036_WIN0_DSP_ST 0x3c +#define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 +#define RK3036_WIN0_SCL_FACTOR_CBR 0x44 +#define RK3036_WIN0_SCL_OFFSET 0x48 +#define RK3036_HWC_MST 0x58 +#define RK3036_HWC_DSP_ST 0x5c +#define RK3036_DSP_HTOTAL_HS_END 0x6c +#define RK3036_DSP_HACT_ST_END 0x70 +#define RK3036_DSP_VTOTAL_VS_END 0x74 +#define RK3036_DSP_VACT_ST_END 0x78 +#define RK3036_DSP_VS_ST_END_F1 0x7c +#define RK3036_DSP_VACT_ST_END_F1 0x80 +#define RK3036_GATHER_TRANSFER 0x84 +#define RK3036_VERSION_INFO 0x94 +#define RK3036_REG_CFG_DONE 0x90 +#define RK3036_WIN1_MST 0xa0 +#define RK3036_WIN1_ACT_INFO 0xb4 +#define RK3036_WIN1_DSP_INFO 0xb8 +#define RK3036_WIN1_DSP_ST 0xbc +#define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 +#define RK3036_WIN1_SCL_OFFSET 0xc8 +#define RK3036_BCSH_CTRL 0xd0 +#define RK3036_BCSH_COLOR_BAR 0xd4 +#define RK3036_BCSH_BCS 0xd8 +#define RK3036_BCSH_H 0xdc +#define RK3036_WIN1_LUT_ADDR 0x400 +#define RK3036_HWC_LUT_ADDR 0x800 +/* rk3036 register definition end */ + /* rk3288 register definition */ #define RK3288_REG_CFG_DONE 0x0000 #define RK3288_VERSION_INFO 0x0004 @@ -122,48 +166,4 @@ #define RK3288_DSP_VACT_ST_END_F1 0x019c /* register definition end */ -/* rk3036 register definition */ -#define RK3036_SYS_CTRL 0x00 -#define RK3036_DSP_CTRL0 0x04 -#define RK3036_DSP_CTRL1 0x08 -#define RK3036_INT_STATUS 0x10 -#define RK3036_ALPHA_CTRL 0x14 -#define RK3036_WIN0_COLOR_KEY 0x18 -#define RK3036_WIN1_COLOR_KEY 0x1c -#define RK3036_WIN0_YRGB_MST 0x20 -#define RK3036_WIN0_CBR_MST 0x24 -#define RK3036_WIN1_VIR 0x28 -#define RK3036_AXI_BUS_CTRL 0x2c -#define RK3036_WIN0_VIR 0x30 -#define RK3036_WIN0_ACT_INFO 0x34 -#define RK3036_WIN0_DSP_INFO 0x38 -#define RK3036_WIN0_DSP_ST 0x3c -#define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 -#define RK3036_WIN0_SCL_FACTOR_CBR 0x44 -#define RK3036_WIN0_SCL_OFFSET 0x48 -#define RK3036_HWC_MST 0x58 -#define RK3036_HWC_DSP_ST 0x5c -#define RK3036_DSP_HTOTAL_HS_END 0x6c -#define RK3036_DSP_HACT_ST_END 0x70 -#define RK3036_DSP_VTOTAL_VS_END 0x74 -#define RK3036_DSP_VACT_ST_END 0x78 -#define RK3036_DSP_VS_ST_END_F1 0x7c -#define RK3036_DSP_VACT_ST_END_F1 0x80 -#define RK3036_GATHER_TRANSFER 0x84 -#define RK3036_VERSION_INFO 0x94 -#define RK3036_REG_CFG_DONE 0x90 -#define RK3036_WIN1_MST 0xa0 -#define RK3036_WIN1_ACT_INFO 0xb4 -#define RK3036_WIN1_DSP_INFO 0xb8 -#define RK3036_WIN1_DSP_ST 0xbc -#define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 -#define RK3036_WIN1_SCL_OFFSET 0xc8 -#define RK3036_BCSH_CTRL 0xd0 -#define RK3036_BCSH_COLOR_BAR 0xd4 -#define RK3036_BCSH_BCS 0xd8 -#define RK3036_BCSH_H 0xdc -#define RK3036_WIN1_LUT_ADDR 0x400 -#define RK3036_HWC_LUT_ADDR 0x800 -/* rk3036 register definition end */ - #endif /* _ROCKCHIP_VOP_REG_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 1/5] drm/rockchip: sort registers define by chip's number @ 2016-04-20 6:18 ` Mark Yao 0 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: David Airlie, Heiko Stuebner, dri-devel, linux-arm-kernel, linux-rockchip, linux-kernel No functional changes, sort the vop registers to make code more readable. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 166 +++++++++++++-------------- drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 88 +++++++------- 2 files changed, 127 insertions(+), 127 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 3166b46..e75b2b8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -50,6 +50,87 @@ static const uint32_t formats_win_lite[] = { DRM_FORMAT_BGR565, }; +static const struct vop_scl_regs rk3066_win_scl = { + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), +}; + +static const struct vop_win_phy rk3036_win0_data = { + .scl = &rk3066_win_scl, + .data_formats = formats_win_full, + .nformats = ARRAY_SIZE(formats_win_full), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), +}; + +static const struct vop_win_phy rk3036_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), +}; + +static const struct vop_win_data rk3036_vop_win_data[] = { + { .base = 0x00, .phy = &rk3036_win0_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x00, .phy = &rk3036_win1_data, + .type = DRM_PLANE_TYPE_CURSOR }, +}; + +static const int rk3036_vop_intrs[] = { + DSP_HOLD_VALID_INTR, + FS_INTR, + LINE_FLAG_INTR, + BUS_ERROR_INTR, +}; + +static const struct vop_intr rk3036_intr = { + .intrs = rk3036_vop_intrs, + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), +}; + +static const struct vop_ctrl rk3036_ctrl_data = { + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { + {RK3036_DSP_CTRL1, 0x00000000}, +}; + +static const struct vop_data rk3036_vop = { + .init_table = rk3036_vop_init_reg_table, + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), + .ctrl = &rk3036_ctrl_data, + .intr = &rk3036_intr, + .win = rk3036_vop_win_data, + .win_size = ARRAY_SIZE(rk3036_vop_win_data), +}; + static const struct vop_scl_extension rk3288_win_full_scl_ext = { .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), @@ -190,92 +271,11 @@ static const struct vop_data rk3288_vop = { .win_size = ARRAY_SIZE(rk3288_vop_win_data), }; -static const struct vop_scl_regs rk3066_win_scl = { - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), -}; - -static const struct vop_win_phy rk3036_win0_data = { - .scl = &rk3066_win_scl, - .data_formats = formats_win_full, - .nformats = ARRAY_SIZE(formats_win_full), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), -}; - -static const struct vop_win_phy rk3036_win1_data = { - .data_formats = formats_win_lite, - .nformats = ARRAY_SIZE(formats_win_lite), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), -}; - -static const struct vop_win_data rk3036_vop_win_data[] = { - { .base = 0x00, .phy = &rk3036_win0_data, - .type = DRM_PLANE_TYPE_PRIMARY }, - { .base = 0x00, .phy = &rk3036_win1_data, - .type = DRM_PLANE_TYPE_CURSOR }, -}; - -static const int rk3036_vop_intrs[] = { - DSP_HOLD_VALID_INTR, - FS_INTR, - LINE_FLAG_INTR, - BUS_ERROR_INTR, -}; - -static const struct vop_intr rk3036_intr = { - .intrs = rk3036_vop_intrs, - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), -}; - -static const struct vop_ctrl rk3036_ctrl_data = { - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), -}; - -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { - {RK3036_DSP_CTRL1, 0x00000000}, -}; - -static const struct vop_data rk3036_vop = { - .init_table = rk3036_vop_init_reg_table, - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), - .ctrl = &rk3036_ctrl_data, - .intr = &rk3036_intr, - .win = rk3036_vop_win_data, - .win_size = ARRAY_SIZE(rk3036_vop_win_data), -}; - static const struct of_device_id vop_driver_dt_match[] = { - { .compatible = "rockchip,rk3288-vop", - .data = &rk3288_vop }, { .compatible = "rockchip,rk3036-vop", .data = &rk3036_vop }, + { .compatible = "rockchip,rk3288-vop", + .data = &rk3288_vop }, {}, }; MODULE_DEVICE_TABLE(of, vop_driver_dt_match); diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index d4b46cb..43903e0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -15,6 +15,50 @@ #ifndef _ROCKCHIP_VOP_REG_H #define _ROCKCHIP_VOP_REG_H +/* rk3036 register definition */ +#define RK3036_SYS_CTRL 0x00 +#define RK3036_DSP_CTRL0 0x04 +#define RK3036_DSP_CTRL1 0x08 +#define RK3036_INT_STATUS 0x10 +#define RK3036_ALPHA_CTRL 0x14 +#define RK3036_WIN0_COLOR_KEY 0x18 +#define RK3036_WIN1_COLOR_KEY 0x1c +#define RK3036_WIN0_YRGB_MST 0x20 +#define RK3036_WIN0_CBR_MST 0x24 +#define RK3036_WIN1_VIR 0x28 +#define RK3036_AXI_BUS_CTRL 0x2c +#define RK3036_WIN0_VIR 0x30 +#define RK3036_WIN0_ACT_INFO 0x34 +#define RK3036_WIN0_DSP_INFO 0x38 +#define RK3036_WIN0_DSP_ST 0x3c +#define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 +#define RK3036_WIN0_SCL_FACTOR_CBR 0x44 +#define RK3036_WIN0_SCL_OFFSET 0x48 +#define RK3036_HWC_MST 0x58 +#define RK3036_HWC_DSP_ST 0x5c +#define RK3036_DSP_HTOTAL_HS_END 0x6c +#define RK3036_DSP_HACT_ST_END 0x70 +#define RK3036_DSP_VTOTAL_VS_END 0x74 +#define RK3036_DSP_VACT_ST_END 0x78 +#define RK3036_DSP_VS_ST_END_F1 0x7c +#define RK3036_DSP_VACT_ST_END_F1 0x80 +#define RK3036_GATHER_TRANSFER 0x84 +#define RK3036_VERSION_INFO 0x94 +#define RK3036_REG_CFG_DONE 0x90 +#define RK3036_WIN1_MST 0xa0 +#define RK3036_WIN1_ACT_INFO 0xb4 +#define RK3036_WIN1_DSP_INFO 0xb8 +#define RK3036_WIN1_DSP_ST 0xbc +#define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 +#define RK3036_WIN1_SCL_OFFSET 0xc8 +#define RK3036_BCSH_CTRL 0xd0 +#define RK3036_BCSH_COLOR_BAR 0xd4 +#define RK3036_BCSH_BCS 0xd8 +#define RK3036_BCSH_H 0xdc +#define RK3036_WIN1_LUT_ADDR 0x400 +#define RK3036_HWC_LUT_ADDR 0x800 +/* rk3036 register definition end */ + /* rk3288 register definition */ #define RK3288_REG_CFG_DONE 0x0000 #define RK3288_VERSION_INFO 0x0004 @@ -122,48 +166,4 @@ #define RK3288_DSP_VACT_ST_END_F1 0x019c /* register definition end */ -/* rk3036 register definition */ -#define RK3036_SYS_CTRL 0x00 -#define RK3036_DSP_CTRL0 0x04 -#define RK3036_DSP_CTRL1 0x08 -#define RK3036_INT_STATUS 0x10 -#define RK3036_ALPHA_CTRL 0x14 -#define RK3036_WIN0_COLOR_KEY 0x18 -#define RK3036_WIN1_COLOR_KEY 0x1c -#define RK3036_WIN0_YRGB_MST 0x20 -#define RK3036_WIN0_CBR_MST 0x24 -#define RK3036_WIN1_VIR 0x28 -#define RK3036_AXI_BUS_CTRL 0x2c -#define RK3036_WIN0_VIR 0x30 -#define RK3036_WIN0_ACT_INFO 0x34 -#define RK3036_WIN0_DSP_INFO 0x38 -#define RK3036_WIN0_DSP_ST 0x3c -#define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 -#define RK3036_WIN0_SCL_FACTOR_CBR 0x44 -#define RK3036_WIN0_SCL_OFFSET 0x48 -#define RK3036_HWC_MST 0x58 -#define RK3036_HWC_DSP_ST 0x5c -#define RK3036_DSP_HTOTAL_HS_END 0x6c -#define RK3036_DSP_HACT_ST_END 0x70 -#define RK3036_DSP_VTOTAL_VS_END 0x74 -#define RK3036_DSP_VACT_ST_END 0x78 -#define RK3036_DSP_VS_ST_END_F1 0x7c -#define RK3036_DSP_VACT_ST_END_F1 0x80 -#define RK3036_GATHER_TRANSFER 0x84 -#define RK3036_VERSION_INFO 0x94 -#define RK3036_REG_CFG_DONE 0x90 -#define RK3036_WIN1_MST 0xa0 -#define RK3036_WIN1_ACT_INFO 0xb4 -#define RK3036_WIN1_DSP_INFO 0xb8 -#define RK3036_WIN1_DSP_ST 0xbc -#define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 -#define RK3036_WIN1_SCL_OFFSET 0xc8 -#define RK3036_BCSH_CTRL 0xd0 -#define RK3036_BCSH_COLOR_BAR 0xd4 -#define RK3036_BCSH_BCS 0xd8 -#define RK3036_BCSH_H 0xdc -#define RK3036_WIN1_LUT_ADDR 0x400 -#define RK3036_HWC_LUT_ADDR 0x800 -/* rk3036 register definition end */ - #endif /* _ROCKCHIP_VOP_REG_H */ -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v2 1/5] drm/rockchip: sort registers define by chip's number 2016-04-20 6:18 ` Mark Yao (?) (?) @ 2016-06-02 6:51 ` Tomasz Figa 2016-06-02 7:05 ` Mark yao 2016-08-17 17:20 ` Sean Paul -1 siblings, 2 replies; 71+ messages in thread From: Tomasz Figa @ 2016-06-02 6:51 UTC (permalink / raw) To: dri-devel Hi Mark, Mark Yao <mark.yao <at> rock-chips.com> writes: > > No functional changes, sort the vop registers to make > code more readable. I might have found a typo. I guess it could be just fixed in this patch, if it's already moving the code around. Please see the comments inline. > > Signed-off-by: Mark Yao <mark.yao <at> rock-chips.com> > --- > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 166 +++++++++++++-------- ------ > drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 88 +++++++------- > 2 files changed, 127 insertions(+), 127 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > index 3166b46..e75b2b8 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > <at> <at> -50,6 +50,87 <at> <at> static const uint32_t formats_win_lite[] = { > DRM_FORMAT_BGR565, > }; > > +static const struct vop_scl_regs rk3066_win_scl = { Why is this rk3066 and not rk3036? It doesn't match the sorting order introduced by this patch, by the way. Typo? > + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win0_data = { > + .scl = &rk3066_win_scl, Ditto. Best regards, Tomasz _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v2 1/5] drm/rockchip: sort registers define by chip's number 2016-06-02 6:51 ` Tomasz Figa @ 2016-06-02 7:05 ` Mark yao 2016-08-17 17:20 ` Sean Paul 1 sibling, 0 replies; 71+ messages in thread From: Mark yao @ 2016-06-02 7:05 UTC (permalink / raw) To: Tomasz Figa, dri-devel On 2016年06月02日 14:51, Tomasz Figa wrote: > Hi Mark, > > Mark Yao <mark.yao <at> rock-chips.com> writes: >> No functional changes, sort the vop registers to make >> code more readable. > I might have found a typo. I guess it could be just fixed in this patch, > if it's already moving the code around. Please see the comments inline. > >> Signed-off-by: Mark Yao <mark.yao <at> rock-chips.com> >> --- >> drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 166 +++++++++++++-------- > ------ >> drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 88 +++++++------- >> 2 files changed, 127 insertions(+), 127 deletions(-) >> >> diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c >> index 3166b46..e75b2b8 100644 >> --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c >> +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c >> <at> <at> -50,6 +50,87 <at> <at> static const uint32_t > formats_win_lite[] = { >> DRM_FORMAT_BGR565, >> }; >> >> +static const struct vop_scl_regs rk3066_win_scl = { > Why is this rk3066 and not rk3036? It doesn't match the sorting order > introduced by this patch, by the way. Typo? Right, That is my mistake, It's rk3036_win_scl, Typo problem. Thanks. > >> + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), >> + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), >> + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), >> + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), >> +}; >> + >> +static const struct vop_win_phy rk3036_win0_data = { >> + .scl = &rk3066_win_scl, > Ditto. > > Best regards, > Tomasz > > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Ｍark Yao _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-06-02 6:51 ` Tomasz Figa 2016-06-02 7:05 ` Mark yao @ 2016-08-17 17:20 ` Sean Paul 1 sibling, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-17 17:20 UTC (permalink / raw) To: tfiga, dri-devel, mark.yao Cc: linux-arm-kernel, linux-rockchip, linux-kernel, heiko, Sean Paul From: Mark Yao <mark.yao@rock-chips.com> No functional changes, sort the vop registers to make code more readable. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul resolved conflict with name change from _3066 to _3036] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Fix typo from _3066 _3036 (Tomasz Figa) drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- 1 file changed, 84 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 919992c..44caf14 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { DRM_FORMAT_BGR565, }; +static const struct vop_scl_regs rk3036_win_scl = { + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), +}; + +static const struct vop_win_phy rk3036_win0_data = { + .scl = &rk3036_win_scl, + .data_formats = formats_win_full, + .nformats = ARRAY_SIZE(formats_win_full), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), +}; + +static const struct vop_win_phy rk3036_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), +}; + +static const struct vop_win_data rk3036_vop_win_data[] = { + { .base = 0x00, .phy = &rk3036_win0_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x00, .phy = &rk3036_win1_data, + .type = DRM_PLANE_TYPE_CURSOR }, +}; + +static const int rk3036_vop_intrs[] = { + DSP_HOLD_VALID_INTR, + FS_INTR, + LINE_FLAG_INTR, + BUS_ERROR_INTR, +}; + +static const struct vop_intr rk3036_intr = { + .intrs = rk3036_vop_intrs, + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), +}; + +static const struct vop_ctrl rk3036_ctrl_data = { + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { + {RK3036_DSP_CTRL1, 0x00000000}, +}; + +static const struct vop_data rk3036_vop = { + .init_table = rk3036_vop_init_reg_table, + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), + .ctrl = &rk3036_ctrl_data, + .intr = &rk3036_intr, + .win = rk3036_vop_win_data, + .win_size = ARRAY_SIZE(rk3036_vop_win_data), +}; + static const struct vop_scl_extension rk3288_win_full_scl_ext = { .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { .win_size = ARRAY_SIZE(rk3288_vop_win_data), }; -static const struct vop_scl_regs rk3036_win_scl = { - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), -}; - -static const struct vop_win_phy rk3036_win0_data = { - .scl = &rk3036_win_scl, - .data_formats = formats_win_full, - .nformats = ARRAY_SIZE(formats_win_full), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), -}; - -static const struct vop_win_phy rk3036_win1_data = { - .data_formats = formats_win_lite, - .nformats = ARRAY_SIZE(formats_win_lite), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), -}; - -static const struct vop_win_data rk3036_vop_win_data[] = { - { .base = 0x00, .phy = &rk3036_win0_data, - .type = DRM_PLANE_TYPE_PRIMARY }, - { .base = 0x00, .phy = &rk3036_win1_data, - .type = DRM_PLANE_TYPE_CURSOR }, -}; - -static const int rk3036_vop_intrs[] = { - DSP_HOLD_VALID_INTR, - FS_INTR, - LINE_FLAG_INTR, - BUS_ERROR_INTR, -}; - -static const struct vop_intr rk3036_intr = { - .intrs = rk3036_vop_intrs, - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), -}; - -static const struct vop_ctrl rk3036_ctrl_data = { - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), -}; - -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { - {RK3036_DSP_CTRL1, 0x00000000}, -}; - -static const struct vop_data rk3036_vop = { - .init_table = rk3036_vop_init_reg_table, - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), - .ctrl = &rk3036_ctrl_data, - .intr = &rk3036_intr, - .win = rk3036_vop_win_data, - .win_size = ARRAY_SIZE(rk3036_vop_win_data), -}; - static const struct of_device_id vop_driver_dt_match[] = { - { .compatible = "rockchip,rk3288-vop", - .data = &rk3288_vop }, { .compatible = "rockchip,rk3036-vop", .data = &rk3036_vop }, + { .compatible = "rockchip,rk3288-vop", + .data = &rk3288_vop }, {}, }; MODULE_DEVICE_TABLE(of, vop_driver_dt_match); -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-17 17:20 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-17 17:20 UTC (permalink / raw) To: linux-arm-kernel From: Mark Yao <mark.yao@rock-chips.com> No functional changes, sort the vop registers to make code more readable. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul resolved conflict with name change from _3066 to _3036] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Fix typo from _3066 _3036 (Tomasz Figa) drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- 1 file changed, 84 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 919992c..44caf14 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { DRM_FORMAT_BGR565, }; +static const struct vop_scl_regs rk3036_win_scl = { + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), +}; + +static const struct vop_win_phy rk3036_win0_data = { + .scl = &rk3036_win_scl, + .data_formats = formats_win_full, + .nformats = ARRAY_SIZE(formats_win_full), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), +}; + +static const struct vop_win_phy rk3036_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), +}; + +static const struct vop_win_data rk3036_vop_win_data[] = { + { .base = 0x00, .phy = &rk3036_win0_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x00, .phy = &rk3036_win1_data, + .type = DRM_PLANE_TYPE_CURSOR }, +}; + +static const int rk3036_vop_intrs[] = { + DSP_HOLD_VALID_INTR, + FS_INTR, + LINE_FLAG_INTR, + BUS_ERROR_INTR, +}; + +static const struct vop_intr rk3036_intr = { + .intrs = rk3036_vop_intrs, + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), +}; + +static const struct vop_ctrl rk3036_ctrl_data = { + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { + {RK3036_DSP_CTRL1, 0x00000000}, +}; + +static const struct vop_data rk3036_vop = { + .init_table = rk3036_vop_init_reg_table, + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), + .ctrl = &rk3036_ctrl_data, + .intr = &rk3036_intr, + .win = rk3036_vop_win_data, + .win_size = ARRAY_SIZE(rk3036_vop_win_data), +}; + static const struct vop_scl_extension rk3288_win_full_scl_ext = { .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { .win_size = ARRAY_SIZE(rk3288_vop_win_data), }; -static const struct vop_scl_regs rk3036_win_scl = { - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), -}; - -static const struct vop_win_phy rk3036_win0_data = { - .scl = &rk3036_win_scl, - .data_formats = formats_win_full, - .nformats = ARRAY_SIZE(formats_win_full), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), -}; - -static const struct vop_win_phy rk3036_win1_data = { - .data_formats = formats_win_lite, - .nformats = ARRAY_SIZE(formats_win_lite), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), -}; - -static const struct vop_win_data rk3036_vop_win_data[] = { - { .base = 0x00, .phy = &rk3036_win0_data, - .type = DRM_PLANE_TYPE_PRIMARY }, - { .base = 0x00, .phy = &rk3036_win1_data, - .type = DRM_PLANE_TYPE_CURSOR }, -}; - -static const int rk3036_vop_intrs[] = { - DSP_HOLD_VALID_INTR, - FS_INTR, - LINE_FLAG_INTR, - BUS_ERROR_INTR, -}; - -static const struct vop_intr rk3036_intr = { - .intrs = rk3036_vop_intrs, - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), -}; - -static const struct vop_ctrl rk3036_ctrl_data = { - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), -}; - -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { - {RK3036_DSP_CTRL1, 0x00000000}, -}; - -static const struct vop_data rk3036_vop = { - .init_table = rk3036_vop_init_reg_table, - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), - .ctrl = &rk3036_ctrl_data, - .intr = &rk3036_intr, - .win = rk3036_vop_win_data, - .win_size = ARRAY_SIZE(rk3036_vop_win_data), -}; - static const struct of_device_id vop_driver_dt_match[] = { - { .compatible = "rockchip,rk3288-vop", - .data = &rk3288_vop }, { .compatible = "rockchip,rk3036-vop", .data = &rk3036_vop }, + { .compatible = "rockchip,rk3288-vop", + .data = &rk3288_vop }, {}, }; MODULE_DEVICE_TABLE(of, vop_driver_dt_match); -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-17 17:20 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-17 17:20 UTC (permalink / raw) To: tfiga, dri-devel, mark.yao; +Cc: linux-rockchip, linux-kernel, linux-arm-kernel From: Mark Yao <mark.yao@rock-chips.com> No functional changes, sort the vop registers to make code more readable. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul resolved conflict with name change from _3066 to _3036] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Fix typo from _3066 _3036 (Tomasz Figa) drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- 1 file changed, 84 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 919992c..44caf14 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { DRM_FORMAT_BGR565, }; +static const struct vop_scl_regs rk3036_win_scl = { + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), +}; + +static const struct vop_win_phy rk3036_win0_data = { + .scl = &rk3036_win_scl, + .data_formats = formats_win_full, + .nformats = ARRAY_SIZE(formats_win_full), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), +}; + +static const struct vop_win_phy rk3036_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), +}; + +static const struct vop_win_data rk3036_vop_win_data[] = { + { .base = 0x00, .phy = &rk3036_win0_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x00, .phy = &rk3036_win1_data, + .type = DRM_PLANE_TYPE_CURSOR }, +}; + +static const int rk3036_vop_intrs[] = { + DSP_HOLD_VALID_INTR, + FS_INTR, + LINE_FLAG_INTR, + BUS_ERROR_INTR, +}; + +static const struct vop_intr rk3036_intr = { + .intrs = rk3036_vop_intrs, + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), +}; + +static const struct vop_ctrl rk3036_ctrl_data = { + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { + {RK3036_DSP_CTRL1, 0x00000000}, +}; + +static const struct vop_data rk3036_vop = { + .init_table = rk3036_vop_init_reg_table, + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), + .ctrl = &rk3036_ctrl_data, + .intr = &rk3036_intr, + .win = rk3036_vop_win_data, + .win_size = ARRAY_SIZE(rk3036_vop_win_data), +}; + static const struct vop_scl_extension rk3288_win_full_scl_ext = { .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { .win_size = ARRAY_SIZE(rk3288_vop_win_data), }; -static const struct vop_scl_regs rk3036_win_scl = { - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), -}; - -static const struct vop_win_phy rk3036_win0_data = { - .scl = &rk3036_win_scl, - .data_formats = formats_win_full, - .nformats = ARRAY_SIZE(formats_win_full), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), -}; - -static const struct vop_win_phy rk3036_win1_data = { - .data_formats = formats_win_lite, - .nformats = ARRAY_SIZE(formats_win_lite), - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), -}; - -static const struct vop_win_data rk3036_vop_win_data[] = { - { .base = 0x00, .phy = &rk3036_win0_data, - .type = DRM_PLANE_TYPE_PRIMARY }, - { .base = 0x00, .phy = &rk3036_win1_data, - .type = DRM_PLANE_TYPE_CURSOR }, -}; - -static const int rk3036_vop_intrs[] = { - DSP_HOLD_VALID_INTR, - FS_INTR, - LINE_FLAG_INTR, - BUS_ERROR_INTR, -}; - -static const struct vop_intr rk3036_intr = { - .intrs = rk3036_vop_intrs, - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), -}; - -static const struct vop_ctrl rk3036_ctrl_data = { - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), -}; - -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { - {RK3036_DSP_CTRL1, 0x00000000}, -}; - -static const struct vop_data rk3036_vop = { - .init_table = rk3036_vop_init_reg_table, - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), - .ctrl = &rk3036_ctrl_data, - .intr = &rk3036_intr, - .win = rk3036_vop_win_data, - .win_size = ARRAY_SIZE(rk3036_vop_win_data), -}; - static const struct of_device_id vop_driver_dt_match[] = { - { .compatible = "rockchip,rk3288-vop", - .data = &rk3288_vop }, { .compatible = "rockchip,rk3036-vop", .data = &rk3036_vop }, + { .compatible = "rockchip,rk3288-vop", + .data = &rk3288_vop }, {}, }; MODULE_DEVICE_TABLE(of, vop_driver_dt_match); -- 2.8.0.rc3.226.g39d4020 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-17 17:20 ` Sean Paul (?) @ 2016-08-18 9:08 ` Mark yao -1 siblings, 0 replies; 71+ messages in thread From: Mark yao @ 2016-08-18 9:08 UTC (permalink / raw) To: Sean Paul, tfiga, dri-devel Cc: linux-arm-kernel, linux-rockchip, linux-kernel, heiko Hi Sean Thanks for send v3 patch for rk3399 vop support. But sorry for that, I had changed my mind, those patches are deprecated, I have new rk3399 patch on my downstream kernel, I will upstream soon. Thanks. On 2016年08月18日 01:20, Sean Paul wrote: > From: Mark Yao <mark.yao@rock-chips.com> > > No functional changes, sort the vop registers to make > code more readable. > > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > [seanpaul resolved conflict with name change from _3066 to _3036] > Signed-off-by: Sean Paul <seanpaul@chromium.org> > --- > > Changes in v3: > - Fix typo from _3066 _3036 (Tomasz Figa) > > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- > 1 file changed, 84 insertions(+), 84 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > index 919992c..44caf14 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { > DRM_FORMAT_BGR565, > }; > > +static const struct vop_scl_regs rk3036_win_scl = { > + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win0_data = { > + .scl = &rk3036_win_scl, > + .data_formats = formats_win_full, > + .nformats = ARRAY_SIZE(formats_win_full), > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win1_data = { > + .data_formats = formats_win_lite, > + .nformats = ARRAY_SIZE(formats_win_lite), > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > +}; > + > +static const struct vop_win_data rk3036_vop_win_data[] = { > + { .base = 0x00, .phy = &rk3036_win0_data, > + .type = DRM_PLANE_TYPE_PRIMARY }, > + { .base = 0x00, .phy = &rk3036_win1_data, > + .type = DRM_PLANE_TYPE_CURSOR }, > +}; > + > +static const int rk3036_vop_intrs[] = { > + DSP_HOLD_VALID_INTR, > + FS_INTR, > + LINE_FLAG_INTR, > + BUS_ERROR_INTR, > +}; > + > +static const struct vop_intr rk3036_intr = { > + .intrs = rk3036_vop_intrs, > + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > +}; > + > +static const struct vop_ctrl rk3036_ctrl_data = { > + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > +}; > + > +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > + {RK3036_DSP_CTRL1, 0x00000000}, > +}; > + > +static const struct vop_data rk3036_vop = { > + .init_table = rk3036_vop_init_reg_table, > + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > + .ctrl = &rk3036_ctrl_data, > + .intr = &rk3036_intr, > + .win = rk3036_vop_win_data, > + .win_size = ARRAY_SIZE(rk3036_vop_win_data), > +}; > + > static const struct vop_scl_extension rk3288_win_full_scl_ext = { > .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), > .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), > @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { > .win_size = ARRAY_SIZE(rk3288_vop_win_data), > }; > > -static const struct vop_scl_regs rk3036_win_scl = { > - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > -}; > - > -static const struct vop_win_phy rk3036_win0_data = { > - .scl = &rk3036_win_scl, > - .data_formats = formats_win_full, > - .nformats = ARRAY_SIZE(formats_win_full), > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > -}; > - > -static const struct vop_win_phy rk3036_win1_data = { > - .data_formats = formats_win_lite, > - .nformats = ARRAY_SIZE(formats_win_lite), > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > -}; > - > -static const struct vop_win_data rk3036_vop_win_data[] = { > - { .base = 0x00, .phy = &rk3036_win0_data, > - .type = DRM_PLANE_TYPE_PRIMARY }, > - { .base = 0x00, .phy = &rk3036_win1_data, > - .type = DRM_PLANE_TYPE_CURSOR }, > -}; > - > -static const int rk3036_vop_intrs[] = { > - DSP_HOLD_VALID_INTR, > - FS_INTR, > - LINE_FLAG_INTR, > - BUS_ERROR_INTR, > -}; > - > -static const struct vop_intr rk3036_intr = { > - .intrs = rk3036_vop_intrs, > - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > -}; > - > -static const struct vop_ctrl rk3036_ctrl_data = { > - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > -}; > - > -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > - {RK3036_DSP_CTRL1, 0x00000000}, > -}; > - > -static const struct vop_data rk3036_vop = { > - .init_table = rk3036_vop_init_reg_table, > - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > - .ctrl = &rk3036_ctrl_data, > - .intr = &rk3036_intr, > - .win = rk3036_vop_win_data, > - .win_size = ARRAY_SIZE(rk3036_vop_win_data), > -}; > - > static const struct of_device_id vop_driver_dt_match[] = { > - { .compatible = "rockchip,rk3288-vop", > - .data = &rk3288_vop }, > { .compatible = "rockchip,rk3036-vop", > .data = &rk3036_vop }, > + { .compatible = "rockchip,rk3288-vop", > + .data = &rk3288_vop }, > {}, > }; > MODULE_DEVICE_TABLE(of, vop_driver_dt_match); -- Ｍark Yao ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-18 9:08 ` Mark yao 0 siblings, 0 replies; 71+ messages in thread From: Mark yao @ 2016-08-18 9:08 UTC (permalink / raw) To: linux-arm-kernel Hi Sean Thanks for send v3 patch for rk3399 vop support. But sorry for that, I had changed my mind, those patches are deprecated, I have new rk3399 patch on my downstream kernel, I will upstream soon. Thanks. On 2016?08?18? 01:20, Sean Paul wrote: > From: Mark Yao <mark.yao@rock-chips.com> > > No functional changes, sort the vop registers to make > code more readable. > > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > [seanpaul resolved conflict with name change from _3066 to _3036] > Signed-off-by: Sean Paul <seanpaul@chromium.org> > --- > > Changes in v3: > - Fix typo from _3066 _3036 (Tomasz Figa) > > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- > 1 file changed, 84 insertions(+), 84 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > index 919992c..44caf14 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { > DRM_FORMAT_BGR565, > }; > > +static const struct vop_scl_regs rk3036_win_scl = { > + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win0_data = { > + .scl = &rk3036_win_scl, > + .data_formats = formats_win_full, > + .nformats = ARRAY_SIZE(formats_win_full), > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win1_data = { > + .data_formats = formats_win_lite, > + .nformats = ARRAY_SIZE(formats_win_lite), > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > +}; > + > +static const struct vop_win_data rk3036_vop_win_data[] = { > + { .base = 0x00, .phy = &rk3036_win0_data, > + .type = DRM_PLANE_TYPE_PRIMARY }, > + { .base = 0x00, .phy = &rk3036_win1_data, > + .type = DRM_PLANE_TYPE_CURSOR }, > +}; > + > +static const int rk3036_vop_intrs[] = { > + DSP_HOLD_VALID_INTR, > + FS_INTR, > + LINE_FLAG_INTR, > + BUS_ERROR_INTR, > +}; > + > +static const struct vop_intr rk3036_intr = { > + .intrs = rk3036_vop_intrs, > + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > +}; > + > +static const struct vop_ctrl rk3036_ctrl_data = { > + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > +}; > + > +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > + {RK3036_DSP_CTRL1, 0x00000000}, > +}; > + > +static const struct vop_data rk3036_vop = { > + .init_table = rk3036_vop_init_reg_table, > + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > + .ctrl = &rk3036_ctrl_data, > + .intr = &rk3036_intr, > + .win = rk3036_vop_win_data, > + .win_size = ARRAY_SIZE(rk3036_vop_win_data), > +}; > + > static const struct vop_scl_extension rk3288_win_full_scl_ext = { > .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), > .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), > @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { > .win_size = ARRAY_SIZE(rk3288_vop_win_data), > }; > > -static const struct vop_scl_regs rk3036_win_scl = { > - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > -}; > - > -static const struct vop_win_phy rk3036_win0_data = { > - .scl = &rk3036_win_scl, > - .data_formats = formats_win_full, > - .nformats = ARRAY_SIZE(formats_win_full), > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > -}; > - > -static const struct vop_win_phy rk3036_win1_data = { > - .data_formats = formats_win_lite, > - .nformats = ARRAY_SIZE(formats_win_lite), > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > -}; > - > -static const struct vop_win_data rk3036_vop_win_data[] = { > - { .base = 0x00, .phy = &rk3036_win0_data, > - .type = DRM_PLANE_TYPE_PRIMARY }, > - { .base = 0x00, .phy = &rk3036_win1_data, > - .type = DRM_PLANE_TYPE_CURSOR }, > -}; > - > -static const int rk3036_vop_intrs[] = { > - DSP_HOLD_VALID_INTR, > - FS_INTR, > - LINE_FLAG_INTR, > - BUS_ERROR_INTR, > -}; > - > -static const struct vop_intr rk3036_intr = { > - .intrs = rk3036_vop_intrs, > - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > -}; > - > -static const struct vop_ctrl rk3036_ctrl_data = { > - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > -}; > - > -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > - {RK3036_DSP_CTRL1, 0x00000000}, > -}; > - > -static const struct vop_data rk3036_vop = { > - .init_table = rk3036_vop_init_reg_table, > - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > - .ctrl = &rk3036_ctrl_data, > - .intr = &rk3036_intr, > - .win = rk3036_vop_win_data, > - .win_size = ARRAY_SIZE(rk3036_vop_win_data), > -}; > - > static const struct of_device_id vop_driver_dt_match[] = { > - { .compatible = "rockchip,rk3288-vop", > - .data = &rk3288_vop }, > { .compatible = "rockchip,rk3036-vop", > .data = &rk3036_vop }, > + { .compatible = "rockchip,rk3288-vop", > + .data = &rk3288_vop }, > {}, > }; > MODULE_DEVICE_TABLE(of, vop_driver_dt_match); -- ?ark Yao ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-18 9:08 ` Mark yao 0 siblings, 0 replies; 71+ messages in thread From: Mark yao @ 2016-08-18 9:08 UTC (permalink / raw) To: Sean Paul, tfiga, dri-devel Cc: linux-rockchip, linux-kernel, linux-arm-kernel Hi Sean Thanks for send v3 patch for rk3399 vop support. But sorry for that, I had changed my mind, those patches are deprecated, I have new rk3399 patch on my downstream kernel, I will upstream soon. Thanks. On 2016年08月18日 01:20, Sean Paul wrote: > From: Mark Yao <mark.yao@rock-chips.com> > > No functional changes, sort the vop registers to make > code more readable. > > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > [seanpaul resolved conflict with name change from _3066 to _3036] > Signed-off-by: Sean Paul <seanpaul@chromium.org> > --- > > Changes in v3: > - Fix typo from _3066 _3036 (Tomasz Figa) > > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- > 1 file changed, 84 insertions(+), 84 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > index 919992c..44caf14 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { > DRM_FORMAT_BGR565, > }; > > +static const struct vop_scl_regs rk3036_win_scl = { > + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win0_data = { > + .scl = &rk3036_win_scl, > + .data_formats = formats_win_full, > + .nformats = ARRAY_SIZE(formats_win_full), > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win1_data = { > + .data_formats = formats_win_lite, > + .nformats = ARRAY_SIZE(formats_win_lite), > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > +}; > + > +static const struct vop_win_data rk3036_vop_win_data[] = { > + { .base = 0x00, .phy = &rk3036_win0_data, > + .type = DRM_PLANE_TYPE_PRIMARY }, > + { .base = 0x00, .phy = &rk3036_win1_data, > + .type = DRM_PLANE_TYPE_CURSOR }, > +}; > + > +static const int rk3036_vop_intrs[] = { > + DSP_HOLD_VALID_INTR, > + FS_INTR, > + LINE_FLAG_INTR, > + BUS_ERROR_INTR, > +}; > + > +static const struct vop_intr rk3036_intr = { > + .intrs = rk3036_vop_intrs, > + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > +}; > + > +static const struct vop_ctrl rk3036_ctrl_data = { > + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > +}; > + > +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > + {RK3036_DSP_CTRL1, 0x00000000}, > +}; > + > +static const struct vop_data rk3036_vop = { > + .init_table = rk3036_vop_init_reg_table, > + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > + .ctrl = &rk3036_ctrl_data, > + .intr = &rk3036_intr, > + .win = rk3036_vop_win_data, > + .win_size = ARRAY_SIZE(rk3036_vop_win_data), > +}; > + > static const struct vop_scl_extension rk3288_win_full_scl_ext = { > .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), > .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), > @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { > .win_size = ARRAY_SIZE(rk3288_vop_win_data), > }; > > -static const struct vop_scl_regs rk3036_win_scl = { > - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > -}; > - > -static const struct vop_win_phy rk3036_win0_data = { > - .scl = &rk3036_win_scl, > - .data_formats = formats_win_full, > - .nformats = ARRAY_SIZE(formats_win_full), > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > -}; > - > -static const struct vop_win_phy rk3036_win1_data = { > - .data_formats = formats_win_lite, > - .nformats = ARRAY_SIZE(formats_win_lite), > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > -}; > - > -static const struct vop_win_data rk3036_vop_win_data[] = { > - { .base = 0x00, .phy = &rk3036_win0_data, > - .type = DRM_PLANE_TYPE_PRIMARY }, > - { .base = 0x00, .phy = &rk3036_win1_data, > - .type = DRM_PLANE_TYPE_CURSOR }, > -}; > - > -static const int rk3036_vop_intrs[] = { > - DSP_HOLD_VALID_INTR, > - FS_INTR, > - LINE_FLAG_INTR, > - BUS_ERROR_INTR, > -}; > - > -static const struct vop_intr rk3036_intr = { > - .intrs = rk3036_vop_intrs, > - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > -}; > - > -static const struct vop_ctrl rk3036_ctrl_data = { > - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > -}; > - > -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > - {RK3036_DSP_CTRL1, 0x00000000}, > -}; > - > -static const struct vop_data rk3036_vop = { > - .init_table = rk3036_vop_init_reg_table, > - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > - .ctrl = &rk3036_ctrl_data, > - .intr = &rk3036_intr, > - .win = rk3036_vop_win_data, > - .win_size = ARRAY_SIZE(rk3036_vop_win_data), > -}; > - > static const struct of_device_id vop_driver_dt_match[] = { > - { .compatible = "rockchip,rk3288-vop", > - .data = &rk3288_vop }, > { .compatible = "rockchip,rk3036-vop", > .data = &rk3036_vop }, > + { .compatible = "rockchip,rk3288-vop", > + .data = &rk3288_vop }, > {}, > }; > MODULE_DEVICE_TABLE(of, vop_driver_dt_match); -- Ｍark Yao _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-18 9:08 ` Mark yao (?) @ 2016-08-18 9:11 ` Daniel Vetter -1 siblings, 0 replies; 71+ messages in thread From: Daniel Vetter @ 2016-08-18 9:11 UTC (permalink / raw) To: Mark yao Cc: Sean Paul, tfiga, dri-devel, linux-rockchip, linux-kernel, linux-arm-kernel On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: > Hi Sean > > Thanks for send v3 patch for rk3399 vop support. > > But sorry for that, I had changed my mind, those patches are deprecated, > I have new rk3399 patch on my downstream kernel, I will upstream soon. Wut? Imo merge Sean's patch here, and then rebase your downstream patches on top of it. That you have a downstream tree which is out of sync with upstream shouldn't be a reason to stall upstream development. -Daniel > > Thanks. > > On 2016年08月18日 01:20, Sean Paul wrote: > > From: Mark Yao <mark.yao@rock-chips.com> > > > > No functional changes, sort the vop registers to make > > code more readable. > > > > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > > [seanpaul resolved conflict with name change from _3066 to _3036] > > Signed-off-by: Sean Paul <seanpaul@chromium.org> > > --- > > > > Changes in v3: > > - Fix typo from _3066 _3036 (Tomasz Figa) > > > > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- > > 1 file changed, 84 insertions(+), 84 deletions(-) > > > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > > index 919992c..44caf14 100644 > > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > > @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { > > DRM_FORMAT_BGR565, > > }; > > +static const struct vop_scl_regs rk3036_win_scl = { > > + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > > + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > > + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > > + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > > +}; > > + > > +static const struct vop_win_phy rk3036_win0_data = { > > + .scl = &rk3036_win_scl, > > + .data_formats = formats_win_full, > > + .nformats = ARRAY_SIZE(formats_win_full), > > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > > + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > > + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > > + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > > + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > > + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > > + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > > + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > > +}; > > + > > +static const struct vop_win_phy rk3036_win1_data = { > > + .data_formats = formats_win_lite, > > + .nformats = ARRAY_SIZE(formats_win_lite), > > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > > + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > > + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > > + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > > + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > > + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > > +}; > > + > > +static const struct vop_win_data rk3036_vop_win_data[] = { > > + { .base = 0x00, .phy = &rk3036_win0_data, > > + .type = DRM_PLANE_TYPE_PRIMARY }, > > + { .base = 0x00, .phy = &rk3036_win1_data, > > + .type = DRM_PLANE_TYPE_CURSOR }, > > +}; > > + > > +static const int rk3036_vop_intrs[] = { > > + DSP_HOLD_VALID_INTR, > > + FS_INTR, > > + LINE_FLAG_INTR, > > + BUS_ERROR_INTR, > > +}; > > + > > +static const struct vop_intr rk3036_intr = { > > + .intrs = rk3036_vop_intrs, > > + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > > + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > > + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > > + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > > +}; > > + > > +static const struct vop_ctrl rk3036_ctrl_data = { > > + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > > + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > > + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > > + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > > + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > > + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > > + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > > + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > > +}; > > + > > +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > > + {RK3036_DSP_CTRL1, 0x00000000}, > > +}; > > + > > +static const struct vop_data rk3036_vop = { > > + .init_table = rk3036_vop_init_reg_table, > > + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > > + .ctrl = &rk3036_ctrl_data, > > + .intr = &rk3036_intr, > > + .win = rk3036_vop_win_data, > > + .win_size = ARRAY_SIZE(rk3036_vop_win_data), > > +}; > > + > > static const struct vop_scl_extension rk3288_win_full_scl_ext = { > > .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), > > .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), > > @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { > > .win_size = ARRAY_SIZE(rk3288_vop_win_data), > > }; > > -static const struct vop_scl_regs rk3036_win_scl = { > > - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > > - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > > - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > > - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > > -}; > > - > > -static const struct vop_win_phy rk3036_win0_data = { > > - .scl = &rk3036_win_scl, > > - .data_formats = formats_win_full, > > - .nformats = ARRAY_SIZE(formats_win_full), > > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > > - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > > - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > > - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > > - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > > - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > > - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > > - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > > -}; > > - > > -static const struct vop_win_phy rk3036_win1_data = { > > - .data_formats = formats_win_lite, > > - .nformats = ARRAY_SIZE(formats_win_lite), > > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > > - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > > - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > > - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > > - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > > - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > > -}; > > - > > -static const struct vop_win_data rk3036_vop_win_data[] = { > > - { .base = 0x00, .phy = &rk3036_win0_data, > > - .type = DRM_PLANE_TYPE_PRIMARY }, > > - { .base = 0x00, .phy = &rk3036_win1_data, > > - .type = DRM_PLANE_TYPE_CURSOR }, > > -}; > > - > > -static const int rk3036_vop_intrs[] = { > > - DSP_HOLD_VALID_INTR, > > - FS_INTR, > > - LINE_FLAG_INTR, > > - BUS_ERROR_INTR, > > -}; > > - > > -static const struct vop_intr rk3036_intr = { > > - .intrs = rk3036_vop_intrs, > > - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > > - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > > - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > > - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > > -}; > > - > > -static const struct vop_ctrl rk3036_ctrl_data = { > > - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > > - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > > - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > > - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > > - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > > - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > > - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > > - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > > -}; > > - > > -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > > - {RK3036_DSP_CTRL1, 0x00000000}, > > -}; > > - > > -static const struct vop_data rk3036_vop = { > > - .init_table = rk3036_vop_init_reg_table, > > - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > > - .ctrl = &rk3036_ctrl_data, > > - .intr = &rk3036_intr, > > - .win = rk3036_vop_win_data, > > - .win_size = ARRAY_SIZE(rk3036_vop_win_data), > > -}; > > - > > static const struct of_device_id vop_driver_dt_match[] = { > > - { .compatible = "rockchip,rk3288-vop", > > - .data = &rk3288_vop }, > > { .compatible = "rockchip,rk3036-vop", > > .data = &rk3036_vop }, > > + { .compatible = "rockchip,rk3288-vop", > > + .data = &rk3288_vop }, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, vop_driver_dt_match); > > > -- > Ｍark Yao > > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-18 9:11 ` Daniel Vetter 0 siblings, 0 replies; 71+ messages in thread From: Daniel Vetter @ 2016-08-18 9:11 UTC (permalink / raw) To: linux-arm-kernel On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: > Hi Sean > > Thanks for send v3 patch for rk3399 vop support. > > But sorry for that, I had changed my mind, those patches are deprecated, > I have new rk3399 patch on my downstream kernel, I will upstream soon. Wut? Imo merge Sean's patch here, and then rebase your downstream patches on top of it. That you have a downstream tree which is out of sync with upstream shouldn't be a reason to stall upstream development. -Daniel > > Thanks. > > On 2016?08?18? 01:20, Sean Paul wrote: > > From: Mark Yao <mark.yao@rock-chips.com> > > > > No functional changes, sort the vop registers to make > > code more readable. > > > > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > > [seanpaul resolved conflict with name change from _3066 to _3036] > > Signed-off-by: Sean Paul <seanpaul@chromium.org> > > --- > > > > Changes in v3: > > - Fix typo from _3066 _3036 (Tomasz Figa) > > > > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- > > 1 file changed, 84 insertions(+), 84 deletions(-) > > > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > > index 919992c..44caf14 100644 > > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > > @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { > > DRM_FORMAT_BGR565, > > }; > > +static const struct vop_scl_regs rk3036_win_scl = { > > + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > > + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > > + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > > + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > > +}; > > + > > +static const struct vop_win_phy rk3036_win0_data = { > > + .scl = &rk3036_win_scl, > > + .data_formats = formats_win_full, > > + .nformats = ARRAY_SIZE(formats_win_full), > > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > > + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > > + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > > + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > > + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > > + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > > + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > > + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > > +}; > > + > > +static const struct vop_win_phy rk3036_win1_data = { > > + .data_formats = formats_win_lite, > > + .nformats = ARRAY_SIZE(formats_win_lite), > > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > > + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > > + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > > + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > > + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > > + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > > +}; > > + > > +static const struct vop_win_data rk3036_vop_win_data[] = { > > + { .base = 0x00, .phy = &rk3036_win0_data, > > + .type = DRM_PLANE_TYPE_PRIMARY }, > > + { .base = 0x00, .phy = &rk3036_win1_data, > > + .type = DRM_PLANE_TYPE_CURSOR }, > > +}; > > + > > +static const int rk3036_vop_intrs[] = { > > + DSP_HOLD_VALID_INTR, > > + FS_INTR, > > + LINE_FLAG_INTR, > > + BUS_ERROR_INTR, > > +}; > > + > > +static const struct vop_intr rk3036_intr = { > > + .intrs = rk3036_vop_intrs, > > + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > > + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > > + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > > + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > > +}; > > + > > +static const struct vop_ctrl rk3036_ctrl_data = { > > + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > > + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > > + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > > + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > > + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > > + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > > + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > > + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > > +}; > > + > > +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > > + {RK3036_DSP_CTRL1, 0x00000000}, > > +}; > > + > > +static const struct vop_data rk3036_vop = { > > + .init_table = rk3036_vop_init_reg_table, > > + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > > + .ctrl = &rk3036_ctrl_data, > > + .intr = &rk3036_intr, > > + .win = rk3036_vop_win_data, > > + .win_size = ARRAY_SIZE(rk3036_vop_win_data), > > +}; > > + > > static const struct vop_scl_extension rk3288_win_full_scl_ext = { > > .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), > > .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), > > @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { > > .win_size = ARRAY_SIZE(rk3288_vop_win_data), > > }; > > -static const struct vop_scl_regs rk3036_win_scl = { > > - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > > - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > > - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > > - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > > -}; > > - > > -static const struct vop_win_phy rk3036_win0_data = { > > - .scl = &rk3036_win_scl, > > - .data_formats = formats_win_full, > > - .nformats = ARRAY_SIZE(formats_win_full), > > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > > - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > > - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > > - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > > - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > > - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > > - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > > - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > > -}; > > - > > -static const struct vop_win_phy rk3036_win1_data = { > > - .data_formats = formats_win_lite, > > - .nformats = ARRAY_SIZE(formats_win_lite), > > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > > - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > > - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > > - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > > - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > > - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > > -}; > > - > > -static const struct vop_win_data rk3036_vop_win_data[] = { > > - { .base = 0x00, .phy = &rk3036_win0_data, > > - .type = DRM_PLANE_TYPE_PRIMARY }, > > - { .base = 0x00, .phy = &rk3036_win1_data, > > - .type = DRM_PLANE_TYPE_CURSOR }, > > -}; > > - > > -static const int rk3036_vop_intrs[] = { > > - DSP_HOLD_VALID_INTR, > > - FS_INTR, > > - LINE_FLAG_INTR, > > - BUS_ERROR_INTR, > > -}; > > - > > -static const struct vop_intr rk3036_intr = { > > - .intrs = rk3036_vop_intrs, > > - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > > - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > > - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > > - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > > -}; > > - > > -static const struct vop_ctrl rk3036_ctrl_data = { > > - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > > - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > > - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > > - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > > - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > > - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > > - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > > - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > > -}; > > - > > -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > > - {RK3036_DSP_CTRL1, 0x00000000}, > > -}; > > - > > -static const struct vop_data rk3036_vop = { > > - .init_table = rk3036_vop_init_reg_table, > > - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > > - .ctrl = &rk3036_ctrl_data, > > - .intr = &rk3036_intr, > > - .win = rk3036_vop_win_data, > > - .win_size = ARRAY_SIZE(rk3036_vop_win_data), > > -}; > > - > > static const struct of_device_id vop_driver_dt_match[] = { > > - { .compatible = "rockchip,rk3288-vop", > > - .data = &rk3288_vop }, > > { .compatible = "rockchip,rk3036-vop", > > .data = &rk3036_vop }, > > + { .compatible = "rockchip,rk3288-vop", > > + .data = &rk3288_vop }, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, vop_driver_dt_match); > > > -- > ?ark Yao > > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-18 9:11 ` Daniel Vetter 0 siblings, 0 replies; 71+ messages in thread From: Daniel Vetter @ 2016-08-18 9:11 UTC (permalink / raw) To: Mark yao; +Cc: linux-kernel, dri-devel, tfiga, linux-rockchip, linux-arm-kernel On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: > Hi Sean > > Thanks for send v3 patch for rk3399 vop support. > > But sorry for that, I had changed my mind, those patches are deprecated, > I have new rk3399 patch on my downstream kernel, I will upstream soon. Wut? Imo merge Sean's patch here, and then rebase your downstream patches on top of it. That you have a downstream tree which is out of sync with upstream shouldn't be a reason to stall upstream development. -Daniel > > Thanks. > > On 2016年08月18日 01:20, Sean Paul wrote: > > From: Mark Yao <mark.yao@rock-chips.com> > > > > No functional changes, sort the vop registers to make > > code more readable. > > > > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > > [seanpaul resolved conflict with name change from _3066 to _3036] > > Signed-off-by: Sean Paul <seanpaul@chromium.org> > > --- > > > > Changes in v3: > > - Fix typo from _3066 _3036 (Tomasz Figa) > > > > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- > > 1 file changed, 84 insertions(+), 84 deletions(-) > > > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > > index 919992c..44caf14 100644 > > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > > @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { > > DRM_FORMAT_BGR565, > > }; > > +static const struct vop_scl_regs rk3036_win_scl = { > > + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > > + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > > + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > > + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > > +}; > > + > > +static const struct vop_win_phy rk3036_win0_data = { > > + .scl = &rk3036_win_scl, > > + .data_formats = formats_win_full, > > + .nformats = ARRAY_SIZE(formats_win_full), > > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > > + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > > + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > > + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > > + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > > + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > > + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > > + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > > +}; > > + > > +static const struct vop_win_phy rk3036_win1_data = { > > + .data_formats = formats_win_lite, > > + .nformats = ARRAY_SIZE(formats_win_lite), > > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > > + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > > + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > > + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > > + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > > + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > > +}; > > + > > +static const struct vop_win_data rk3036_vop_win_data[] = { > > + { .base = 0x00, .phy = &rk3036_win0_data, > > + .type = DRM_PLANE_TYPE_PRIMARY }, > > + { .base = 0x00, .phy = &rk3036_win1_data, > > + .type = DRM_PLANE_TYPE_CURSOR }, > > +}; > > + > > +static const int rk3036_vop_intrs[] = { > > + DSP_HOLD_VALID_INTR, > > + FS_INTR, > > + LINE_FLAG_INTR, > > + BUS_ERROR_INTR, > > +}; > > + > > +static const struct vop_intr rk3036_intr = { > > + .intrs = rk3036_vop_intrs, > > + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > > + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > > + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > > + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > > +}; > > + > > +static const struct vop_ctrl rk3036_ctrl_data = { > > + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > > + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > > + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > > + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > > + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > > + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > > + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > > + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > > +}; > > + > > +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > > + {RK3036_DSP_CTRL1, 0x00000000}, > > +}; > > + > > +static const struct vop_data rk3036_vop = { > > + .init_table = rk3036_vop_init_reg_table, > > + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > > + .ctrl = &rk3036_ctrl_data, > > + .intr = &rk3036_intr, > > + .win = rk3036_vop_win_data, > > + .win_size = ARRAY_SIZE(rk3036_vop_win_data), > > +}; > > + > > static const struct vop_scl_extension rk3288_win_full_scl_ext = { > > .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), > > .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), > > @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { > > .win_size = ARRAY_SIZE(rk3288_vop_win_data), > > }; > > -static const struct vop_scl_regs rk3036_win_scl = { > > - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > > - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > > - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > > - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > > -}; > > - > > -static const struct vop_win_phy rk3036_win0_data = { > > - .scl = &rk3036_win_scl, > > - .data_formats = formats_win_full, > > - .nformats = ARRAY_SIZE(formats_win_full), > > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > > - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > > - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > > - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > > - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > > - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > > - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > > - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > > -}; > > - > > -static const struct vop_win_phy rk3036_win1_data = { > > - .data_formats = formats_win_lite, > > - .nformats = ARRAY_SIZE(formats_win_lite), > > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > > - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > > - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > > - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > > - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > > - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > > -}; > > - > > -static const struct vop_win_data rk3036_vop_win_data[] = { > > - { .base = 0x00, .phy = &rk3036_win0_data, > > - .type = DRM_PLANE_TYPE_PRIMARY }, > > - { .base = 0x00, .phy = &rk3036_win1_data, > > - .type = DRM_PLANE_TYPE_CURSOR }, > > -}; > > - > > -static const int rk3036_vop_intrs[] = { > > - DSP_HOLD_VALID_INTR, > > - FS_INTR, > > - LINE_FLAG_INTR, > > - BUS_ERROR_INTR, > > -}; > > - > > -static const struct vop_intr rk3036_intr = { > > - .intrs = rk3036_vop_intrs, > > - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > > - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > > - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > > - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > > -}; > > - > > -static const struct vop_ctrl rk3036_ctrl_data = { > > - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > > - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > > - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > > - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > > - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > > - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > > - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > > - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > > -}; > > - > > -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > > - {RK3036_DSP_CTRL1, 0x00000000}, > > -}; > > - > > -static const struct vop_data rk3036_vop = { > > - .init_table = rk3036_vop_init_reg_table, > > - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > > - .ctrl = &rk3036_ctrl_data, > > - .intr = &rk3036_intr, > > - .win = rk3036_vop_win_data, > > - .win_size = ARRAY_SIZE(rk3036_vop_win_data), > > -}; > > - > > static const struct of_device_id vop_driver_dt_match[] = { > > - { .compatible = "rockchip,rk3288-vop", > > - .data = &rk3288_vop }, > > { .compatible = "rockchip,rk3036-vop", > > .data = &rk3036_vop }, > > + { .compatible = "rockchip,rk3288-vop", > > + .data = &rk3288_vop }, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, vop_driver_dt_match); > > > -- > Ｍark Yao > > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-18 9:11 ` Daniel Vetter (?) @ 2016-08-18 10:02 ` Mark yao -1 siblings, 0 replies; 71+ messages in thread From: Mark yao @ 2016-08-18 10:02 UTC (permalink / raw) To: Sean Paul, tfiga, dri-devel, linux-rockchip, linux-kernel, linux-arm-kernel On 2016年08月18日 17:11, Daniel Vetter wrote: > On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >> >Hi Sean >> > >> >Thanks for send v3 patch for rk3399 vop support. >> > >> >But sorry for that, I had changed my mind, those patches are deprecated, >> >I have new rk3399 patch on my downstream kernel, I will upstream soon. > Wut? Imo merge Sean's patch here, and then rebase your downstream patches > on top of it. That you have a downstream tree which is out of sync with > upstream shouldn't be a reason to stall upstream development. > -Daniel > Yeah, Sorry for that. In fact, on my downstream kernel, also have those patches, my new rk3399 patches are based on them, but the new rk3399 patches will cover the those patches, Sean's patches is old version. I just want to fast forward, don't want to send two version drivers to upstream. but if you and Dave feel ok for that, I have no problem:-) . merged Sean's patches and then apply new version patches. Thanks. -- Ｍark Yao ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-18 10:02 ` Mark yao 0 siblings, 0 replies; 71+ messages in thread From: Mark yao @ 2016-08-18 10:02 UTC (permalink / raw) To: linux-arm-kernel On 2016?08?18? 17:11, Daniel Vetter wrote: > On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >> >Hi Sean >> > >> >Thanks for send v3 patch for rk3399 vop support. >> > >> >But sorry for that, I had changed my mind, those patches are deprecated, >> >I have new rk3399 patch on my downstream kernel, I will upstream soon. > Wut? Imo merge Sean's patch here, and then rebase your downstream patches > on top of it. That you have a downstream tree which is out of sync with > upstream shouldn't be a reason to stall upstream development. > -Daniel > Yeah, Sorry for that. In fact, on my downstream kernel, also have those patches, my new rk3399 patches are based on them, but the new rk3399 patches will cover the those patches, Sean's patches is old version. I just want to fast forward, don't want to send two version drivers to upstream. but if you and Dave feel ok for that, I have no problem:-) . merged Sean's patches and then apply new version patches. Thanks. -- ?ark Yao ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-18 10:02 ` Mark yao 0 siblings, 0 replies; 71+ messages in thread From: Mark yao @ 2016-08-18 10:02 UTC (permalink / raw) To: Sean Paul, tfiga, dri-devel, linux-rockchip, linux-kernel, linux-arm-kernel On 2016年08月18日 17:11, Daniel Vetter wrote: > On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >> >Hi Sean >> > >> >Thanks for send v3 patch for rk3399 vop support. >> > >> >But sorry for that, I had changed my mind, those patches are deprecated, >> >I have new rk3399 patch on my downstream kernel, I will upstream soon. > Wut? Imo merge Sean's patch here, and then rebase your downstream patches > on top of it. That you have a downstream tree which is out of sync with > upstream shouldn't be a reason to stall upstream development. > -Daniel > Yeah, Sorry for that. In fact, on my downstream kernel, also have those patches, my new rk3399 patches are based on them, but the new rk3399 patches will cover the those patches, Sean's patches is old version. I just want to fast forward, don't want to send two version drivers to upstream. but if you and Dave feel ok for that, I have no problem:-) . merged Sean's patches and then apply new version patches. Thanks. -- Ｍark Yao _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-18 10:02 ` Mark yao (?) @ 2016-08-22 20:30 ` Sean Paul -1 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-22 20:30 UTC (permalink / raw) To: Mark yao Cc: Tomasz Figa, dri-devel, linux-rockchip, Linux Kernel Mailing List, Linux ARM Kernel On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: > On 2016年08月18日 17:11, Daniel Vetter wrote: >> >> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>> >>> >Hi Sean >>> > >>> >Thanks for send v3 patch for rk3399 vop support. >>> > >>> >But sorry for that, I had changed my mind, those patches are deprecated, >>> >I have new rk3399 patch on my downstream kernel, I will upstream soon. >> >> Wut? Imo merge Sean's patch here, and then rebase your downstream patches >> on top of it. That you have a downstream tree which is out of sync with >> upstream shouldn't be a reason to stall upstream development. >> -Daniel >> > Yeah, Sorry for that. > > In fact, on my downstream kernel, also have those patches, my new rk3399 > patches are based on them, > but the new rk3399 patches will cover the those patches, Sean's patches is > old version. > > I just want to fast forward, don't want to send two version drivers to > upstream. > but if you and Dave feel ok for that, I have no problem:-) . > > merged Sean's patches and then apply new version patches. > Ok, so can I get a review/ack for these revised patches then? Something is better than nothing, and there's a bunch of stuff that depends on these changes. Sean > Thanks. > > -- > Ｍark Yao > > ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-22 20:30 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-22 20:30 UTC (permalink / raw) To: linux-arm-kernel On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: > On 2016?08?18? 17:11, Daniel Vetter wrote: >> >> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>> >>> >Hi Sean >>> > >>> >Thanks for send v3 patch for rk3399 vop support. >>> > >>> >But sorry for that, I had changed my mind, those patches are deprecated, >>> >I have new rk3399 patch on my downstream kernel, I will upstream soon. >> >> Wut? Imo merge Sean's patch here, and then rebase your downstream patches >> on top of it. That you have a downstream tree which is out of sync with >> upstream shouldn't be a reason to stall upstream development. >> -Daniel >> > Yeah, Sorry for that. > > In fact, on my downstream kernel, also have those patches, my new rk3399 > patches are based on them, > but the new rk3399 patches will cover the those patches, Sean's patches is > old version. > > I just want to fast forward, don't want to send two version drivers to > upstream. > but if you and Dave feel ok for that, I have no problem:-) . > > merged Sean's patches and then apply new version patches. > Ok, so can I get a review/ack for these revised patches then? Something is better than nothing, and there's a bunch of stuff that depends on these changes. Sean > Thanks. > > -- > ?ark Yao > > ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-22 20:30 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-22 20:30 UTC (permalink / raw) To: Mark yao Cc: Linux ARM Kernel, linux-rockchip, Linux Kernel Mailing List, dri-devel, Tomasz Figa On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: > On 2016年08月18日 17:11, Daniel Vetter wrote: >> >> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>> >>> >Hi Sean >>> > >>> >Thanks for send v3 patch for rk3399 vop support. >>> > >>> >But sorry for that, I had changed my mind, those patches are deprecated, >>> >I have new rk3399 patch on my downstream kernel, I will upstream soon. >> >> Wut? Imo merge Sean's patch here, and then rebase your downstream patches >> on top of it. That you have a downstream tree which is out of sync with >> upstream shouldn't be a reason to stall upstream development. >> -Daniel >> > Yeah, Sorry for that. > > In fact, on my downstream kernel, also have those patches, my new rk3399 > patches are based on them, > but the new rk3399 patches will cover the those patches, Sean's patches is > old version. > > I just want to fast forward, don't want to send two version drivers to > upstream. > but if you and Dave feel ok for that, I have no problem:-) . > > merged Sean's patches and then apply new version patches. > Ok, so can I get a review/ack for these revised patches then? Something is better than nothing, and there's a bunch of stuff that depends on these changes. Sean > Thanks. > > -- > Ｍark Yao > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-22 20:30 ` Sean Paul @ 2016-08-23 0:40 ` Mark yao -1 siblings, 0 replies; 71+ messages in thread From: Mark yao @ 2016-08-23 0:40 UTC (permalink / raw) To: Sean Paul Cc: Tomasz Figa, dri-devel, linux-rockchip, Linux Kernel Mailing List, Linux ARM Kernel On 2016年08月23日 04:30, Sean Paul wrote: > On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: >> On 2016年08月18日 17:11, Daniel Vetter wrote: >>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>> Hi Sean >>>>> >>>>> Thanks for send v3 patch for rk3399 vop support. >>>>> >>>>> But sorry for that, I had changed my mind, those patches are deprecated, >>>>> I have new rk3399 patch on my downstream kernel, I will upstream soon. >>> Wut? Imo merge Sean's patch here, and then rebase your downstream patches >>> on top of it. That you have a downstream tree which is out of sync with >>> upstream shouldn't be a reason to stall upstream development. >>> -Daniel >>> >> Yeah, Sorry for that. >> >> In fact, on my downstream kernel, also have those patches, my new rk3399 >> patches are based on them, >> but the new rk3399 patches will cover the those patches, Sean's patches is >> old version. >> >> I just want to fast forward, don't want to send two version drivers to >> upstream. >> but if you and Dave feel ok for that, I have no problem:-) . >> >> merged Sean's patches and then apply new version patches. >> > Ok, so can I get a review/ack for these revised patches then? > Something is better than nothing, and there's a bunch of stuff that > depends on these changes. > > Sean Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the lost patches use v2 version? > > >> Thanks. >> >> -- >> Ｍark Yao >> >> > > -- Ｍark Yao ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-23 0:40 ` Mark yao 0 siblings, 0 replies; 71+ messages in thread From: Mark yao @ 2016-08-23 0:40 UTC (permalink / raw) To: linux-arm-kernel On 2016?08?23? 04:30, Sean Paul wrote: > On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: >> On 2016?08?18? 17:11, Daniel Vetter wrote: >>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>> Hi Sean >>>>> >>>>> Thanks for send v3 patch for rk3399 vop support. >>>>> >>>>> But sorry for that, I had changed my mind, those patches are deprecated, >>>>> I have new rk3399 patch on my downstream kernel, I will upstream soon. >>> Wut? Imo merge Sean's patch here, and then rebase your downstream patches >>> on top of it. That you have a downstream tree which is out of sync with >>> upstream shouldn't be a reason to stall upstream development. >>> -Daniel >>> >> Yeah, Sorry for that. >> >> In fact, on my downstream kernel, also have those patches, my new rk3399 >> patches are based on them, >> but the new rk3399 patches will cover the those patches, Sean's patches is >> old version. >> >> I just want to fast forward, don't want to send two version drivers to >> upstream. >> but if you and Dave feel ok for that, I have no problem:-) . >> >> merged Sean's patches and then apply new version patches. >> > Ok, so can I get a review/ack for these revised patches then? > Something is better than nothing, and there's a bunch of stuff that > depends on these changes. > > Sean Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the lost patches use v2 version? > > >> Thanks. >> >> -- >> ?ark Yao >> >> > > -- ?ark Yao ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-23 0:40 ` Mark yao (?) @ 2016-08-23 13:13 ` Sean Paul -1 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-23 13:13 UTC (permalink / raw) To: Mark yao Cc: Tomasz Figa, dri-devel, linux-rockchip, Linux Kernel Mailing List, Linux ARM Kernel On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> wrote: > On 2016年08月23日 04:30, Sean Paul wrote: >> >> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: >>> >>> On 2016年08月18日 17:11, Daniel Vetter wrote: >>>> >>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>> >>>>>> Hi Sean >>>>>> >>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>> >>>>>> But sorry for that, I had changed my mind, those patches are >>>>>> deprecated, >>>>>> I have new rk3399 patch on my downstream kernel, I will upstream soon. >>>> >>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>> patches >>>> on top of it. That you have a downstream tree which is out of sync with >>>> upstream shouldn't be a reason to stall upstream development. >>>> -Daniel >>>> >>> Yeah, Sorry for that. >>> >>> In fact, on my downstream kernel, also have those patches, my new rk3399 >>> patches are based on them, >>> but the new rk3399 patches will cover the those patches, Sean's patches >>> is >>> old version. >>> >>> I just want to fast forward, don't want to send two version drivers to >>> upstream. >>> but if you and Dave feel ok for that, I have no problem:-) . >>> >>> merged Sean's patches and then apply new version patches. >>> >> Ok, so can I get a review/ack for these revised patches then? >> Something is better than nothing, and there's a bunch of stuff that >> depends on these changes. >> >> Sean > > Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the lost > patches use v2 version? > Yes, v2 4/5 was reviewed as-is, so I just applied it. Sean > >> >> >>> Thanks. >>> >>> -- >>> Ｍark Yao >>> >>> >> >> > > > -- > Ｍark Yao > > ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-23 13:13 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-23 13:13 UTC (permalink / raw) To: linux-arm-kernel On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> wrote: > On 2016?08?23? 04:30, Sean Paul wrote: >> >> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: >>> >>> On 2016?08?18? 17:11, Daniel Vetter wrote: >>>> >>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>> >>>>>> Hi Sean >>>>>> >>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>> >>>>>> But sorry for that, I had changed my mind, those patches are >>>>>> deprecated, >>>>>> I have new rk3399 patch on my downstream kernel, I will upstream soon. >>>> >>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>> patches >>>> on top of it. That you have a downstream tree which is out of sync with >>>> upstream shouldn't be a reason to stall upstream development. >>>> -Daniel >>>> >>> Yeah, Sorry for that. >>> >>> In fact, on my downstream kernel, also have those patches, my new rk3399 >>> patches are based on them, >>> but the new rk3399 patches will cover the those patches, Sean's patches >>> is >>> old version. >>> >>> I just want to fast forward, don't want to send two version drivers to >>> upstream. >>> but if you and Dave feel ok for that, I have no problem:-) . >>> >>> merged Sean's patches and then apply new version patches. >>> >> Ok, so can I get a review/ack for these revised patches then? >> Something is better than nothing, and there's a bunch of stuff that >> depends on these changes. >> >> Sean > > Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the lost > patches use v2 version? > Yes, v2 4/5 was reviewed as-is, so I just applied it. Sean > >> >> >>> Thanks. >>> >>> -- >>> ?ark Yao >>> >>> >> >> > > > -- > ?ark Yao > > ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-23 13:13 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-23 13:13 UTC (permalink / raw) To: Mark yao Cc: Linux ARM Kernel, linux-rockchip, Linux Kernel Mailing List, dri-devel, Tomasz Figa On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> wrote: > On 2016年08月23日 04:30, Sean Paul wrote: >> >> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: >>> >>> On 2016年08月18日 17:11, Daniel Vetter wrote: >>>> >>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>> >>>>>> Hi Sean >>>>>> >>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>> >>>>>> But sorry for that, I had changed my mind, those patches are >>>>>> deprecated, >>>>>> I have new rk3399 patch on my downstream kernel, I will upstream soon. >>>> >>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>> patches >>>> on top of it. That you have a downstream tree which is out of sync with >>>> upstream shouldn't be a reason to stall upstream development. >>>> -Daniel >>>> >>> Yeah, Sorry for that. >>> >>> In fact, on my downstream kernel, also have those patches, my new rk3399 >>> patches are based on them, >>> but the new rk3399 patches will cover the those patches, Sean's patches >>> is >>> old version. >>> >>> I just want to fast forward, don't want to send two version drivers to >>> upstream. >>> but if you and Dave feel ok for that, I have no problem:-) . >>> >>> merged Sean's patches and then apply new version patches. >>> >> Ok, so can I get a review/ack for these revised patches then? >> Something is better than nothing, and there's a bunch of stuff that >> depends on these changes. >> >> Sean > > Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the lost > patches use v2 version? > Yes, v2 4/5 was reviewed as-is, so I just applied it. Sean > >> >> >>> Thanks. >>> >>> -- >>> Ｍark Yao >>> >>> >> >> > > > -- > Ｍark Yao > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-23 13:13 ` Sean Paul (?) @ 2016-08-25 2:25 ` Mark yao -1 siblings, 0 replies; 71+ messages in thread From: Mark yao @ 2016-08-25 2:25 UTC (permalink / raw) To: Sean Paul Cc: Tomasz Figa, dri-devel, linux-rockchip, Linux Kernel Mailing List, Linux ARM Kernel On 2016年08月23日 21:13, Sean Paul wrote: > On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> wrote: >> On 2016年08月23日 04:30, Sean Paul wrote: >>> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: >>>> On 2016年08月18日 17:11, Daniel Vetter wrote: >>>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>>> Hi Sean >>>>>>> >>>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>>> >>>>>>> But sorry for that, I had changed my mind, those patches are >>>>>>> deprecated, >>>>>>> I have new rk3399 patch on my downstream kernel, I will upstream soon. >>>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>>> patches >>>>> on top of it. That you have a downstream tree which is out of sync with >>>>> upstream shouldn't be a reason to stall upstream development. >>>>> -Daniel >>>>> >>>> Yeah, Sorry for that. >>>> >>>> In fact, on my downstream kernel, also have those patches, my new rk3399 >>>> patches are based on them, >>>> but the new rk3399 patches will cover the those patches, Sean's patches >>>> is >>>> old version. >>>> >>>> I just want to fast forward, don't want to send two version drivers to >>>> upstream. >>>> but if you and Dave feel ok for that, I have no problem:-) . >>>> >>>> merged Sean's patches and then apply new version patches. >>>> >>> Ok, so can I get a review/ack for these revised patches then? >>> Something is better than nothing, and there's a bunch of stuff that >>> depends on these changes. >>> >>> Sean >> Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the lost >> patches use v2 version? >> > Yes, v2 4/5 was reviewed as-is, so I just applied it. > > Sean Applied this series to my drm-next. Thanks. >>> >>>> Thanks. >>>> >>>> -- >>>> Ｍark Yao >>>> >>>> >>> >> >> -- >> Ｍark Yao >> >> > > -- Ｍark Yao ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-25 2:25 ` Mark yao 0 siblings, 0 replies; 71+ messages in thread From: Mark yao @ 2016-08-25 2:25 UTC (permalink / raw) To: linux-arm-kernel On 2016?08?23? 21:13, Sean Paul wrote: > On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> wrote: >> On 2016?08?23? 04:30, Sean Paul wrote: >>> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: >>>> On 2016?08?18? 17:11, Daniel Vetter wrote: >>>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>>> Hi Sean >>>>>>> >>>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>>> >>>>>>> But sorry for that, I had changed my mind, those patches are >>>>>>> deprecated, >>>>>>> I have new rk3399 patch on my downstream kernel, I will upstream soon. >>>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>>> patches >>>>> on top of it. That you have a downstream tree which is out of sync with >>>>> upstream shouldn't be a reason to stall upstream development. >>>>> -Daniel >>>>> >>>> Yeah, Sorry for that. >>>> >>>> In fact, on my downstream kernel, also have those patches, my new rk3399 >>>> patches are based on them, >>>> but the new rk3399 patches will cover the those patches, Sean's patches >>>> is >>>> old version. >>>> >>>> I just want to fast forward, don't want to send two version drivers to >>>> upstream. >>>> but if you and Dave feel ok for that, I have no problem:-) . >>>> >>>> merged Sean's patches and then apply new version patches. >>>> >>> Ok, so can I get a review/ack for these revised patches then? >>> Something is better than nothing, and there's a bunch of stuff that >>> depends on these changes. >>> >>> Sean >> Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the lost >> patches use v2 version? >> > Yes, v2 4/5 was reviewed as-is, so I just applied it. > > Sean Applied this series to my drm-next. Thanks. >>> >>>> Thanks. >>>> >>>> -- >>>> ?ark Yao >>>> >>>> >>> >> >> -- >> ?ark Yao >> >> > > -- ?ark Yao ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-25 2:25 ` Mark yao 0 siblings, 0 replies; 71+ messages in thread From: Mark yao @ 2016-08-25 2:25 UTC (permalink / raw) To: Sean Paul Cc: Linux ARM Kernel, linux-rockchip, Linux Kernel Mailing List, dri-devel, Tomasz Figa On 2016年08月23日 21:13, Sean Paul wrote: > On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> wrote: >> On 2016年08月23日 04:30, Sean Paul wrote: >>> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> wrote: >>>> On 2016年08月18日 17:11, Daniel Vetter wrote: >>>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>>> Hi Sean >>>>>>> >>>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>>> >>>>>>> But sorry for that, I had changed my mind, those patches are >>>>>>> deprecated, >>>>>>> I have new rk3399 patch on my downstream kernel, I will upstream soon. >>>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>>> patches >>>>> on top of it. That you have a downstream tree which is out of sync with >>>>> upstream shouldn't be a reason to stall upstream development. >>>>> -Daniel >>>>> >>>> Yeah, Sorry for that. >>>> >>>> In fact, on my downstream kernel, also have those patches, my new rk3399 >>>> patches are based on them, >>>> but the new rk3399 patches will cover the those patches, Sean's patches >>>> is >>>> old version. >>>> >>>> I just want to fast forward, don't want to send two version drivers to >>>> upstream. >>>> but if you and Dave feel ok for that, I have no problem:-) . >>>> >>>> merged Sean's patches and then apply new version patches. >>>> >>> Ok, so can I get a review/ack for these revised patches then? >>> Something is better than nothing, and there's a bunch of stuff that >>> depends on these changes. >>> >>> Sean >> Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the lost >> patches use v2 version? >> > Yes, v2 4/5 was reviewed as-is, so I just applied it. > > Sean Applied this series to my drm-next. Thanks. >>> >>>> Thanks. >>>> >>>> -- >>>> Ｍark Yao >>>> >>>> >>> >> >> -- >> Ｍark Yao >> >> > > -- Ｍark Yao _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-25 2:25 ` Mark yao (?) (?) @ 2016-08-25 17:15 ` Sean Paul 2016-08-25 17:17 ` Sean Paul -1 siblings, 1 reply; 71+ messages in thread From: Sean Paul @ 2016-08-25 17:15 UTC (permalink / raw) To: Mark yao Cc: Linux ARM Kernel, linux-rockchip, Linux Kernel Mailing List, dri-devel, Tomasz Figa [-- Attachment #1.1: Type: text/plain, Size: 2360 bytes --] On Wed, Aug 24, 2016 at 10:25 PM, Mark yao <mark.yao@rock-chips.com> wrote: > On 2016年08月23日 21:13, Sean Paul wrote: > >> On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> >> wrote: >> >>> On 2016年08月23日 04:30, Sean Paul wrote: >>> >>>> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> >>>> wrote: >>>> >>>>> On 2016年08月18日 17:11, Daniel Vetter wrote: >>>>> >>>>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>> >>>>>>> Hi Sean >>>>>>>> >>>>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>>>> >>>>>>>> But sorry for that, I had changed my mind, those patches are >>>>>>>> deprecated, >>>>>>>> I have new rk3399 patch on my downstream kernel, I will upstream >>>>>>>> soon. >>>>>>>> >>>>>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>>>> patches >>>>>> on top of it. That you have a downstream tree which is out of sync >>>>>> with >>>>>> upstream shouldn't be a reason to stall upstream development. >>>>>> -Daniel >>>>>> >>>>>> Yeah, Sorry for that. >>>>> >>>>> In fact, on my downstream kernel, also have those patches, my new >>>>> rk3399 >>>>> patches are based on them, >>>>> but the new rk3399 patches will cover the those patches, Sean's >>>>> patches >>>>> is >>>>> old version. >>>>> >>>>> I just want to fast forward, don't want to send two version drivers to >>>>> upstream. >>>>> but if you and Dave feel ok for that, I have no problem:-) . >>>>> >>>>> merged Sean's patches and then apply new version patches. >>>>> >>>>> Ok, so can I get a review/ack for these revised patches then? >>>> Something is better than nothing, and there's a bunch of stuff that >>>> depends on these changes. >>>> >>>> Sean >>>> >>> Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the >>> lost >>> patches use v2 version? >>> >>> Yes, v2 4/5 was reviewed as-is, so I just applied it. >> >> Sean >> > Applied this series to my drm-next. > > You should probably just rebase your downstream kernel on top of my branch here: https://cgit.freedesktop.org/~seanpaul/dogwood/log/?h=for-next Sean Thanks. > > > >>>> Thanks. >>>>> >>>>> -- >>>>> Ｍark Yao >>>>> >>>>> >>>>> >>>> >>> -- >>> Ｍark Yao >>> >>> >>> >> >> > > -- > Ｍark Yao > > > [-- Attachment #1.2: Type: text/html, Size: 4738 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number 2016-08-25 17:15 ` Sean Paul 2016-08-25 17:17 ` Sean Paul @ 2016-08-25 17:17 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-25 17:17 UTC (permalink / raw) To: Mark yao Cc: Tomasz Figa, dri-devel, linux-rockchip, Linux Kernel Mailing List, Linux ARM Kernel On Thu, Aug 25, 2016 at 1:15 PM, Sean Paul <seanpaul@chromium.org> wrote: > > > On Wed, Aug 24, 2016 at 10:25 PM, Mark yao <mark.yao@rock-chips.com> wrote: >> >> On 2016年08月23日 21:13, Sean Paul wrote: >>> >>> On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> >>> wrote: >>>> >>>> On 2016年08月23日 04:30, Sean Paul wrote: >>>>> >>>>> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> >>>>> wrote: >>>>>> >>>>>> On 2016年08月18日 17:11, Daniel Vetter wrote: >>>>>>> >>>>>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>>>>> >>>>>>>>> Hi Sean >>>>>>>>> >>>>>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>>>>> >>>>>>>>> But sorry for that, I had changed my mind, those patches are >>>>>>>>> deprecated, >>>>>>>>> I have new rk3399 patch on my downstream kernel, I will upstream >>>>>>>>> soon. >>>>>>> >>>>>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>>>>> patches >>>>>>> on top of it. That you have a downstream tree which is out of sync >>>>>>> with >>>>>>> upstream shouldn't be a reason to stall upstream development. >>>>>>> -Daniel >>>>>>> >>>>>> Yeah, Sorry for that. >>>>>> >>>>>> In fact, on my downstream kernel, also have those patches, my new >>>>>> rk3399 >>>>>> patches are based on them, >>>>>> but the new rk3399 patches will cover the those patches, Sean's >>>>>> patches >>>>>> is >>>>>> old version. >>>>>> >>>>>> I just want to fast forward, don't want to send two version drivers to >>>>>> upstream. >>>>>> but if you and Dave feel ok for that, I have no problem:-) . >>>>>> >>>>>> merged Sean's patches and then apply new version patches. >>>>>> >>>>> Ok, so can I get a review/ack for these revised patches then? >>>>> Something is better than nothing, and there's a bunch of stuff that >>>>> depends on these changes. >>>>> >>>>> Sean >>>> >>>> Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the >>>> lost >>>> patches use v2 version? >>>> >>> Yes, v2 4/5 was reviewed as-is, so I just applied it. >>> >>> Sean >> >> Applied this series to my drm-next. >> > > You should probably just rebase your downstream kernel on top of my branch > here: https://cgit.freedesktop.org/~seanpaul/dogwood/log/?h=for-next > Resending in plain text. Sean > Sean > > >> Thanks. >> >> >>>>> >>>>>> Thanks. >>>>>> >>>>>> -- >>>>>> Ｍark Yao >>>>>> >>>>>> >>>>> >>>> >>>> -- >>>> Ｍark Yao >>>> >>>> >>> >>> >> >> >> -- >> Ｍark Yao >> >> > ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-25 17:17 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-25 17:17 UTC (permalink / raw) To: linux-arm-kernel On Thu, Aug 25, 2016 at 1:15 PM, Sean Paul <seanpaul@chromium.org> wrote: > > > On Wed, Aug 24, 2016 at 10:25 PM, Mark yao <mark.yao@rock-chips.com> wrote: >> >> On 2016?08?23? 21:13, Sean Paul wrote: >>> >>> On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> >>> wrote: >>>> >>>> On 2016?08?23? 04:30, Sean Paul wrote: >>>>> >>>>> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> >>>>> wrote: >>>>>> >>>>>> On 2016?08?18? 17:11, Daniel Vetter wrote: >>>>>>> >>>>>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>>>>> >>>>>>>>> Hi Sean >>>>>>>>> >>>>>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>>>>> >>>>>>>>> But sorry for that, I had changed my mind, those patches are >>>>>>>>> deprecated, >>>>>>>>> I have new rk3399 patch on my downstream kernel, I will upstream >>>>>>>>> soon. >>>>>>> >>>>>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>>>>> patches >>>>>>> on top of it. That you have a downstream tree which is out of sync >>>>>>> with >>>>>>> upstream shouldn't be a reason to stall upstream development. >>>>>>> -Daniel >>>>>>> >>>>>> Yeah, Sorry for that. >>>>>> >>>>>> In fact, on my downstream kernel, also have those patches, my new >>>>>> rk3399 >>>>>> patches are based on them, >>>>>> but the new rk3399 patches will cover the those patches, Sean's >>>>>> patches >>>>>> is >>>>>> old version. >>>>>> >>>>>> I just want to fast forward, don't want to send two version drivers to >>>>>> upstream. >>>>>> but if you and Dave feel ok for that, I have no problem:-) . >>>>>> >>>>>> merged Sean's patches and then apply new version patches. >>>>>> >>>>> Ok, so can I get a review/ack for these revised patches then? >>>>> Something is better than nothing, and there's a bunch of stuff that >>>>> depends on these changes. >>>>> >>>>> Sean >>>> >>>> Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the >>>> lost >>>> patches use v2 version? >>>> >>> Yes, v2 4/5 was reviewed as-is, so I just applied it. >>> >>> Sean >> >> Applied this series to my drm-next. >> > > You should probably just rebase your downstream kernel on top of my branch > here: https://cgit.freedesktop.org/~seanpaul/dogwood/log/?h=for-next > Resending in plain text. Sean > Sean > > >> Thanks. >> >> >>>>> >>>>>> Thanks. >>>>>> >>>>>> -- >>>>>> ?ark Yao >>>>>> >>>>>> >>>>> >>>> >>>> -- >>>> ?ark Yao >>>> >>>> >>> >>> >> >> >> -- >> ?ark Yao >> >> > ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number @ 2016-08-25 17:17 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-25 17:17 UTC (permalink / raw) To: Mark yao Cc: Linux ARM Kernel, linux-rockchip, Linux Kernel Mailing List, dri-devel, Tomasz Figa On Thu, Aug 25, 2016 at 1:15 PM, Sean Paul <seanpaul@chromium.org> wrote: > > > On Wed, Aug 24, 2016 at 10:25 PM, Mark yao <mark.yao@rock-chips.com> wrote: >> >> On 2016年08月23日 21:13, Sean Paul wrote: >>> >>> On Mon, Aug 22, 2016 at 8:40 PM, Mark yao <mark.yao@rock-chips.com> >>> wrote: >>>> >>>> On 2016年08月23日 04:30, Sean Paul wrote: >>>>> >>>>> On Thu, Aug 18, 2016 at 6:02 AM, Mark yao <mark.yao@rock-chips.com> >>>>> wrote: >>>>>> >>>>>> On 2016年08月18日 17:11, Daniel Vetter wrote: >>>>>>> >>>>>>> On Thu, Aug 18, 2016 at 05:08:14PM +0800, Mark yao wrote: >>>>>>>>> >>>>>>>>> Hi Sean >>>>>>>>> >>>>>>>>> Thanks for send v3 patch for rk3399 vop support. >>>>>>>>> >>>>>>>>> But sorry for that, I had changed my mind, those patches are >>>>>>>>> deprecated, >>>>>>>>> I have new rk3399 patch on my downstream kernel, I will upstream >>>>>>>>> soon. >>>>>>> >>>>>>> Wut? Imo merge Sean's patch here, and then rebase your downstream >>>>>>> patches >>>>>>> on top of it. That you have a downstream tree which is out of sync >>>>>>> with >>>>>>> upstream shouldn't be a reason to stall upstream development. >>>>>>> -Daniel >>>>>>> >>>>>> Yeah, Sorry for that. >>>>>> >>>>>> In fact, on my downstream kernel, also have those patches, my new >>>>>> rk3399 >>>>>> patches are based on them, >>>>>> but the new rk3399 patches will cover the those patches, Sean's >>>>>> patches >>>>>> is >>>>>> old version. >>>>>> >>>>>> I just want to fast forward, don't want to send two version drivers to >>>>>> upstream. >>>>>> but if you and Dave feel ok for that, I have no problem:-) . >>>>>> >>>>>> merged Sean's patches and then apply new version patches. >>>>>> >>>>> Ok, so can I get a review/ack for these revised patches then? >>>>> Something is better than nothing, and there's a bunch of stuff that >>>>> depends on these changes. >>>>> >>>>> Sean >>>> >>>> Yes, But I miss your [PATCH v3 0/5] and [PATCH v3 4/5]. do you mean the >>>> lost >>>> patches use v2 version? >>>> >>> Yes, v2 4/5 was reviewed as-is, so I just applied it. >>> >>> Sean >> >> Applied this series to my drm-next. >> > > You should probably just rebase your downstream kernel on top of my branch > here: https://cgit.freedesktop.org/~seanpaul/dogwood/log/?h=for-next > Resending in plain text. Sean > Sean > > >> Thanks. >> >> >>>>> >>>>>> Thanks. >>>>>> >>>>>> -- >>>>>> Ｍark Yao >>>>>> >>>>>> >>>>> >>>> >>>> -- >>>> Ｍark Yao >>>> >>>> >>> >>> >> >> >> -- >> Ｍark Yao >> >> > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v2 2/5] dt-bindings: sort Rockchip vop compatible by chip's number 2016-04-20 6:18 ` Mark Yao @ 2016-04-20 6:18 ` Mark Yao -1 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: David Airlie, Heiko Stuebner, dri-devel, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Mark Yao Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- .../bindings/display/rockchip/rockchip-vop.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 5489b59..196121f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -6,8 +6,8 @@ buffer to an external LCD interface. Required properties: - compatible: value should be one of the following - "rockchip,rk3288-vop"; "rockchip,rk3036-vop"; + "rockchip,rk3288-vop"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 2/5] dt-bindings: sort Rockchip vop compatible by chip's number @ 2016-04-20 6:18 ` Mark Yao 0 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- .../bindings/display/rockchip/rockchip-vop.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 5489b59..196121f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -6,8 +6,8 @@ buffer to an external LCD interface. Required properties: - compatible: value should be one of the following - "rockchip,rk3288-vop"; "rockchip,rk3036-vop"; + "rockchip,rk3288-vop"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v2 2/5] dt-bindings: sort Rockchip vop compatible by chip's number 2016-04-20 6:18 ` Mark Yao (?) @ 2016-06-02 6:56 ` Tomasz Figa 2016-08-17 17:11 ` Sean Paul 2016-08-18 21:15 ` Sean Paul -1 siblings, 2 replies; 71+ messages in thread From: Tomasz Figa @ 2016-06-02 6:56 UTC (permalink / raw) To: linux-kernel Mark Yao <mark.yao <at> rock-chips.com> writes: > Would be good to say something about purpose of the change. Even just one sentence, e.g. "A trivial cleanup to make things better organized." Other than that: Reviewed-by: Tomasz Figa <tfiga@chromium.org> Best regards, Tomasz ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 2/5] dt-bindings: sort Rockchip vop compatible by chip's number 2016-06-02 6:56 ` Tomasz Figa 2016-08-17 17:11 ` Sean Paul @ 2016-08-17 17:11 ` Sean Paul 1 sibling, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-17 17:11 UTC (permalink / raw) To: tfiga, dri-devel, mark.yao, robh Cc: linux-arm-kernel, linux-rockchip, linux-kernel, heiko, Sean Paul From: Mark Yao <mark.yao@rock-chips.com> Reorder the compatible vop devices to be sorted by chip number in ascending order. Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul added commit description per tfiga's review] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Updated commit message (Tomasz Figa) Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 5489b59..196121f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -6,8 +6,8 @@ buffer to an external LCD interface. Required properties: - compatible: value should be one of the following - "rockchip,rk3288-vop"; "rockchip,rk3036-vop"; + "rockchip,rk3288-vop"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 2/5] dt-bindings: sort Rockchip vop compatible by chip's number @ 2016-08-17 17:11 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-17 17:11 UTC (permalink / raw) To: linux-arm-kernel From: Mark Yao <mark.yao@rock-chips.com> Reorder the compatible vop devices to be sorted by chip number in ascending order. Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul added commit description per tfiga's review] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Updated commit message (Tomasz Figa) Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 5489b59..196121f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -6,8 +6,8 @@ buffer to an external LCD interface. Required properties: - compatible: value should be one of the following - "rockchip,rk3288-vop"; "rockchip,rk3036-vop"; + "rockchip,rk3288-vop"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 2/5] dt-bindings: sort Rockchip vop compatible by chip's number @ 2016-08-17 17:11 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-17 17:11 UTC (permalink / raw) To: tfiga, dri-devel, mark.yao, robh Cc: linux-rockchip, linux-kernel, linux-arm-kernel From: Mark Yao <mark.yao@rock-chips.com> Reorder the compatible vop devices to be sorted by chip number in ascending order. Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul added commit description per tfiga's review] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Updated commit message (Tomasz Figa) Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 5489b59..196121f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -6,8 +6,8 @@ buffer to an external LCD interface. Required properties: - compatible: value should be one of the following - "rockchip,rk3288-vop"; "rockchip,rk3036-vop"; + "rockchip,rk3288-vop"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 2.8.0.rc3.226.g39d4020 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 2/5] dt-bindings: sort Rockchip vop compatible by chip's number 2016-06-02 6:56 ` Tomasz Figa 2016-08-17 17:11 ` Sean Paul @ 2016-08-18 21:15 ` Sean Paul 1 sibling, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-18 21:15 UTC (permalink / raw) To: tfiga, dri-devel, mark.yao, robh, devicetree Cc: linux-arm-kernel, linux-rockchip, linux-kernel, heiko, Sean Paul From: Mark Yao <mark.yao@rock-chips.com> Reorder the compatible vop devices to be sorted by chip number in ascending order. Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul added commit description per tfiga's review] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Resending to add devicetree list Changes in v3: - Updated commit message (Tomasz Figa) Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 5489b59..196121f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -6,8 +6,8 @@ buffer to an external LCD interface. Required properties: - compatible: value should be one of the following - "rockchip,rk3288-vop"; "rockchip,rk3036-vop"; + "rockchip,rk3288-vop"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 2/5] dt-bindings: sort Rockchip vop compatible by chip's number @ 2016-08-18 21:15 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-18 21:15 UTC (permalink / raw) To: linux-arm-kernel From: Mark Yao <mark.yao@rock-chips.com> Reorder the compatible vop devices to be sorted by chip number in ascending order. Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul added commit description per tfiga's review] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Resending to add devicetree list Changes in v3: - Updated commit message (Tomasz Figa) Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 5489b59..196121f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -6,8 +6,8 @@ buffer to an external LCD interface. Required properties: - compatible: value should be one of the following - "rockchip,rk3288-vop"; "rockchip,rk3036-vop"; + "rockchip,rk3288-vop"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 2/5] dt-bindings: sort Rockchip vop compatible by chip's number @ 2016-08-18 21:15 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-18 21:15 UTC (permalink / raw) To: tfiga, dri-devel, mark.yao, robh, devicetree Cc: linux-rockchip, linux-kernel, linux-arm-kernel From: Mark Yao <mark.yao@rock-chips.com> Reorder the compatible vop devices to be sorted by chip number in ascending order. Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul added commit description per tfiga's review] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Resending to add devicetree list Changes in v3: - Updated commit message (Tomasz Figa) Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 5489b59..196121f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -6,8 +6,8 @@ buffer to an external LCD interface. Required properties: - compatible: value should be one of the following - "rockchip,rk3288-vop"; "rockchip,rk3036-vop"; + "rockchip,rk3288-vop"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 2.8.0.rc3.226.g39d4020 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: sort Rockchip vop compatible by chip's number @ 2016-08-19 13:51 ` Rob Herring 0 siblings, 0 replies; 71+ messages in thread From: Rob Herring @ 2016-08-19 13:51 UTC (permalink / raw) To: Sean Paul Cc: tfiga, dri-devel, mark.yao, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, heiko On Thu, Aug 18, 2016 at 02:15:18PM -0700, Sean Paul wrote: > From: Mark Yao <mark.yao@rock-chips.com> > > Reorder the compatible vop devices to be sorted by chip number > in ascending order. > > Reviewed-by: Tomasz Figa <tfiga@chromium.org> > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > [seanpaul added commit description per tfiga's review] > Signed-off-by: Sean Paul <seanpaul@chromium.org> > --- > > Resending to add devicetree list > > Changes in v3: > - Updated commit message (Tomasz Figa) > > Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 2/5] dt-bindings: sort Rockchip vop compatible by chip's number @ 2016-08-19 13:51 ` Rob Herring 0 siblings, 0 replies; 71+ messages in thread From: Rob Herring @ 2016-08-19 13:51 UTC (permalink / raw) To: linux-arm-kernel On Thu, Aug 18, 2016 at 02:15:18PM -0700, Sean Paul wrote: > From: Mark Yao <mark.yao@rock-chips.com> > > Reorder the compatible vop devices to be sorted by chip number > in ascending order. > > Reviewed-by: Tomasz Figa <tfiga@chromium.org> > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > [seanpaul added commit description per tfiga's review] > Signed-off-by: Sean Paul <seanpaul@chromium.org> > --- > > Resending to add devicetree list > > Changes in v3: > - Updated commit message (Tomasz Figa) > > Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: sort Rockchip vop compatible by chip's number @ 2016-08-19 13:51 ` Rob Herring 0 siblings, 0 replies; 71+ messages in thread From: Rob Herring @ 2016-08-19 13:51 UTC (permalink / raw) To: Sean Paul Cc: tfiga-F7+t8E8rja9g9hUCZPvPmw, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, mark.yao-TNX95d0MmH7DzftRWevZcw, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, heiko-4mtYJXux2i+zQB+pC5nmwQ On Thu, Aug 18, 2016 at 02:15:18PM -0700, Sean Paul wrote: > From: Mark Yao <mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > > Reorder the compatible vop devices to be sorted by chip number > in ascending order. > > Reviewed-by: Tomasz Figa <tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> > Signed-off-by: Mark Yao <mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > [seanpaul added commit description per tfiga's review] > Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> > --- > > Resending to add devicetree list > > Changes in v3: > - Updated commit message (Tomasz Figa) > > Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v2 3/5] drm/rockchip: vop: introduce VOP_REG_MASK 2016-04-20 6:18 ` Mark Yao (?) @ 2016-04-20 6:18 ` Mark Yao -1 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: David Airlie, Heiko Stuebner, dri-devel, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Mark Yao Some new vop register support mask, bit[16-31] is mask, bit[0-15] is value, the mask is correspond to the value. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 45 ++++++++++++++------------- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 9 +++++- 3 files changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 28596e7..59f24cd 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -36,15 +36,18 @@ #include "rockchip_drm_fb.h" #include "rockchip_drm_vop.h" -#define __REG_SET_RELAXED(x, off, mask, shift, v) \ - vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) -#define __REG_SET_NORMAL(x, off, mask, shift, v) \ - vop_mask_write(x, off, (mask) << shift, (v) << shift) +#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ + vop_mask_write(x, off, mask, shift, v, write_mask, true) + +#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ + vop_mask_write(x, off, mask, shift, v, write_mask, false) #define REG_SET(x, base, reg, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) + __REG_SET_##mode(x, base + reg.offset, \ + reg.mask, reg.shift, v, reg.write_mask) #define REG_SET_MASK(x, base, reg, mask, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v) + __REG_SET_##mode(x, base + reg.offset, \ + mask, reg.shift, v, reg.write_mask) #define VOP_WIN_SET(x, win, name, v) \ REG_SET(x, win->base, win->phy->name, v, RELAXED) @@ -160,27 +163,25 @@ static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, } static inline void vop_mask_write(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t v) + uint32_t mask, uint32_t shift, uint32_t v, + bool write_mask, bool relaxed) { - if (mask) { - uint32_t cached_val = vop->regsbak[offset >> 2]; - - cached_val = (cached_val & ~mask) | v; - writel(cached_val, vop->regs + offset); - vop->regsbak[offset >> 2] = cached_val; - } -} + if (!mask) + return; -static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t v) -{ - if (mask) { + if (write_mask) { + v = (v << shift) | (mask << (shift + 16)); + } else { uint32_t cached_val = vop->regsbak[offset >> 2]; - cached_val = (cached_val & ~mask) | v; - writel_relaxed(cached_val, vop->regs + offset); - vop->regsbak[offset >> 2] = cached_val; + v = (cached_val & ~(mask << shift)) | (v << shift); + vop->regsbak[offset >> 2] = v; } + + if (relaxed) + writel_relaxed(v, vop->regs + offset); + else + writel(v, vop->regs + offset); } static inline uint32_t vop_get_intr_type(struct vop *vop, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 071ff0b..28dafb6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -33,6 +33,7 @@ struct vop_reg { uint32_t offset; uint32_t shift; uint32_t mask; + bool write_mask; }; struct vop_ctrl { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index e75b2b8..6846868 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -23,7 +23,14 @@ #define VOP_REG(off, _mask, s) \ {.offset = off, \ .mask = _mask, \ - .shift = s,} + .shift = s, \ + .write_mask = false,} + +#define VOP_REG_MASK(off, _mask, s) \ + {.offset = off, \ + .mask = _mask, \ + .shift = s, \ + .write_mask = true,} static const uint32_t formats_win_full[] = { DRM_FORMAT_XRGB8888, -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 3/5] drm/rockchip: vop: introduce VOP_REG_MASK @ 2016-04-20 6:18 ` Mark Yao 0 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: linux-arm-kernel Some new vop register support mask, bit[16-31] is mask, bit[0-15] is value, the mask is correspond to the value. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 45 ++++++++++++++------------- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 9 +++++- 3 files changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 28596e7..59f24cd 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -36,15 +36,18 @@ #include "rockchip_drm_fb.h" #include "rockchip_drm_vop.h" -#define __REG_SET_RELAXED(x, off, mask, shift, v) \ - vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) -#define __REG_SET_NORMAL(x, off, mask, shift, v) \ - vop_mask_write(x, off, (mask) << shift, (v) << shift) +#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ + vop_mask_write(x, off, mask, shift, v, write_mask, true) + +#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ + vop_mask_write(x, off, mask, shift, v, write_mask, false) #define REG_SET(x, base, reg, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) + __REG_SET_##mode(x, base + reg.offset, \ + reg.mask, reg.shift, v, reg.write_mask) #define REG_SET_MASK(x, base, reg, mask, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v) + __REG_SET_##mode(x, base + reg.offset, \ + mask, reg.shift, v, reg.write_mask) #define VOP_WIN_SET(x, win, name, v) \ REG_SET(x, win->base, win->phy->name, v, RELAXED) @@ -160,27 +163,25 @@ static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, } static inline void vop_mask_write(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t v) + uint32_t mask, uint32_t shift, uint32_t v, + bool write_mask, bool relaxed) { - if (mask) { - uint32_t cached_val = vop->regsbak[offset >> 2]; - - cached_val = (cached_val & ~mask) | v; - writel(cached_val, vop->regs + offset); - vop->regsbak[offset >> 2] = cached_val; - } -} + if (!mask) + return; -static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t v) -{ - if (mask) { + if (write_mask) { + v = (v << shift) | (mask << (shift + 16)); + } else { uint32_t cached_val = vop->regsbak[offset >> 2]; - cached_val = (cached_val & ~mask) | v; - writel_relaxed(cached_val, vop->regs + offset); - vop->regsbak[offset >> 2] = cached_val; + v = (cached_val & ~(mask << shift)) | (v << shift); + vop->regsbak[offset >> 2] = v; } + + if (relaxed) + writel_relaxed(v, vop->regs + offset); + else + writel(v, vop->regs + offset); } static inline uint32_t vop_get_intr_type(struct vop *vop, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 071ff0b..28dafb6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -33,6 +33,7 @@ struct vop_reg { uint32_t offset; uint32_t shift; uint32_t mask; + bool write_mask; }; struct vop_ctrl { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index e75b2b8..6846868 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -23,7 +23,14 @@ #define VOP_REG(off, _mask, s) \ {.offset = off, \ .mask = _mask, \ - .shift = s,} + .shift = s, \ + .write_mask = false,} + +#define VOP_REG_MASK(off, _mask, s) \ + {.offset = off, \ + .mask = _mask, \ + .shift = s, \ + .write_mask = true,} static const uint32_t formats_win_full[] = { DRM_FORMAT_XRGB8888, -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 3/5] drm/rockchip: vop: introduce VOP_REG_MASK @ 2016-04-20 6:18 ` Mark Yao 0 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: David Airlie, Heiko Stuebner, dri-devel, linux-arm-kernel, linux-rockchip, linux-kernel Some new vop register support mask, bit[16-31] is mask, bit[0-15] is value, the mask is correspond to the value. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 45 ++++++++++++++------------- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 9 +++++- 3 files changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 28596e7..59f24cd 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -36,15 +36,18 @@ #include "rockchip_drm_fb.h" #include "rockchip_drm_vop.h" -#define __REG_SET_RELAXED(x, off, mask, shift, v) \ - vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) -#define __REG_SET_NORMAL(x, off, mask, shift, v) \ - vop_mask_write(x, off, (mask) << shift, (v) << shift) +#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ + vop_mask_write(x, off, mask, shift, v, write_mask, true) + +#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ + vop_mask_write(x, off, mask, shift, v, write_mask, false) #define REG_SET(x, base, reg, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) + __REG_SET_##mode(x, base + reg.offset, \ + reg.mask, reg.shift, v, reg.write_mask) #define REG_SET_MASK(x, base, reg, mask, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v) + __REG_SET_##mode(x, base + reg.offset, \ + mask, reg.shift, v, reg.write_mask) #define VOP_WIN_SET(x, win, name, v) \ REG_SET(x, win->base, win->phy->name, v, RELAXED) @@ -160,27 +163,25 @@ static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, } static inline void vop_mask_write(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t v) + uint32_t mask, uint32_t shift, uint32_t v, + bool write_mask, bool relaxed) { - if (mask) { - uint32_t cached_val = vop->regsbak[offset >> 2]; - - cached_val = (cached_val & ~mask) | v; - writel(cached_val, vop->regs + offset); - vop->regsbak[offset >> 2] = cached_val; - } -} + if (!mask) + return; -static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t v) -{ - if (mask) { + if (write_mask) { + v = (v << shift) | (mask << (shift + 16)); + } else { uint32_t cached_val = vop->regsbak[offset >> 2]; - cached_val = (cached_val & ~mask) | v; - writel_relaxed(cached_val, vop->regs + offset); - vop->regsbak[offset >> 2] = cached_val; + v = (cached_val & ~(mask << shift)) | (v << shift); + vop->regsbak[offset >> 2] = v; } + + if (relaxed) + writel_relaxed(v, vop->regs + offset); + else + writel(v, vop->regs + offset); } static inline uint32_t vop_get_intr_type(struct vop *vop, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 071ff0b..28dafb6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -33,6 +33,7 @@ struct vop_reg { uint32_t offset; uint32_t shift; uint32_t mask; + bool write_mask; }; struct vop_ctrl { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index e75b2b8..6846868 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -23,7 +23,14 @@ #define VOP_REG(off, _mask, s) \ {.offset = off, \ .mask = _mask, \ - .shift = s,} + .shift = s, \ + .write_mask = false,} + +#define VOP_REG_MASK(off, _mask, s) \ + {.offset = off, \ + .mask = _mask, \ + .shift = s, \ + .write_mask = true,} static const uint32_t formats_win_full[] = { DRM_FORMAT_XRGB8888, -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v2 3/5] drm/rockchip: vop: introduce VOP_REG_MASK 2016-04-20 6:18 ` Mark Yao (?) (?) @ 2016-06-02 7:19 ` Tomasz Figa 2016-08-17 17:23 ` Sean Paul -1 siblings, 1 reply; 71+ messages in thread From: Tomasz Figa @ 2016-06-02 7:19 UTC (permalink / raw) To: dri-devel Hi Mark, Mark Yao <mark.yao <at> rock-chips.com> writes: > > Some new vop register support mask, bit[16-31] is mask, > bit[0-15] is value, the mask is correspond to the value. Please see my comments inline. > > Signed-off-by: Mark Yao <mark.yao <at> rock-chips.com> > --- > drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 45 ++++++++++++++------- ------ > drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 9 +++++- > 3 files changed, 32 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > index 28596e7..59f24cd 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c [snip] > -static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, > - uint32_t mask, uint32_t v) > -{ > - if (mask) { > + if (write_mask) { > + v = (v << shift) | (mask << (shift + 16)); If the caller gives "v" too big, it might get over the bit 16 and affect the mask. IMHO it would be much safer to mask (v << shift) with 0xffff just in case. > + } else { > uint32_t cached_val = vop->regsbak[offset >> 2]; > > - cached_val = (cached_val & ~mask) | v; > - writel_relaxed(cached_val, vop->regs + offset); > - vop->regsbak[offset >> 2] = cached_val; > + v = (cached_val & ~(mask << shift)) | (v << shift); Should we also mask "v" with "mask" for better safety? Best regards, Tomasz _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 3/5] drm/rockchip: vop: introduce VOP_REG_MASK 2016-06-02 7:19 ` Tomasz Figa 2016-08-17 17:23 ` Sean Paul @ 2016-08-17 17:23 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-17 17:23 UTC (permalink / raw) To: tfiga, dri-devel, mark.yao Cc: linux-arm-kernel, linux-rockchip, linux-kernel, heiko, Sean Paul From: Mark Yao <mark.yao@rock-chips.com> Some new vop register support mask, bit[16-31] is mask, bit[0-15] is value, the mask is correspond to the value. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul masked 'v' per tfiga's review comments] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Masked v in vop_mask_write to avoid stomping other bits (Tomasz) drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 45 +++++++++++++++-------------- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 9 +++++- 3 files changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 91305eb..5047507 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -36,15 +36,18 @@ #include "rockchip_drm_fb.h" #include "rockchip_drm_vop.h" -#define __REG_SET_RELAXED(x, off, mask, shift, v) \ - vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) -#define __REG_SET_NORMAL(x, off, mask, shift, v) \ - vop_mask_write(x, off, (mask) << shift, (v) << shift) +#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ + vop_mask_write(x, off, mask, shift, v, write_mask, true) + +#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ + vop_mask_write(x, off, mask, shift, v, write_mask, false) #define REG_SET(x, base, reg, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) + __REG_SET_##mode(x, base + reg.offset, \ + reg.mask, reg.shift, v, reg.write_mask) #define REG_SET_MASK(x, base, reg, mask, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v) + __REG_SET_##mode(x, base + reg.offset, \ + mask, reg.shift, v, reg.write_mask) #define VOP_WIN_SET(x, win, name, v) \ REG_SET(x, win->base, win->phy->name, v, RELAXED) @@ -164,27 +167,25 @@ static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, } static inline void vop_mask_write(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t v) + uint32_t mask, uint32_t shift, uint32_t v, + bool write_mask, bool relaxed) { - if (mask) { - uint32_t cached_val = vop->regsbak[offset >> 2]; - - cached_val = (cached_val & ~mask) | v; - writel(cached_val, vop->regs + offset); - vop->regsbak[offset >> 2] = cached_val; - } -} + if (!mask) + return; -static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t v) -{ - if (mask) { + if (write_mask) { + v = ((v << shift) & 0xffff) | (mask << (shift + 16)); + } else { uint32_t cached_val = vop->regsbak[offset >> 2]; - cached_val = (cached_val & ~mask) | v; - writel_relaxed(cached_val, vop->regs + offset); - vop->regsbak[offset >> 2] = cached_val; + v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); + vop->regsbak[offset >> 2] = v; } + + if (relaxed) + writel_relaxed(v, vop->regs + offset); + else + writel(v, vop->regs + offset); } static inline uint32_t vop_get_intr_type(struct vop *vop, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 071ff0b..28dafb6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -33,6 +33,7 @@ struct vop_reg { uint32_t offset; uint32_t shift; uint32_t mask; + bool write_mask; }; struct vop_ctrl { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 44caf14..e3f72ba 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -23,7 +23,14 @@ #define VOP_REG(off, _mask, s) \ {.offset = off, \ .mask = _mask, \ - .shift = s,} + .shift = s, \ + .write_mask = false,} + +#define VOP_REG_MASK(off, _mask, s) \ + {.offset = off, \ + .mask = _mask, \ + .shift = s, \ + .write_mask = true,} static const uint32_t formats_win_full[] = { DRM_FORMAT_XRGB8888, -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 3/5] drm/rockchip: vop: introduce VOP_REG_MASK @ 2016-08-17 17:23 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-17 17:23 UTC (permalink / raw) To: linux-arm-kernel From: Mark Yao <mark.yao@rock-chips.com> Some new vop register support mask, bit[16-31] is mask, bit[0-15] is value, the mask is correspond to the value. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul masked 'v' per tfiga's review comments] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Masked v in vop_mask_write to avoid stomping other bits (Tomasz) drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 45 +++++++++++++++-------------- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 9 +++++- 3 files changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 91305eb..5047507 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -36,15 +36,18 @@ #include "rockchip_drm_fb.h" #include "rockchip_drm_vop.h" -#define __REG_SET_RELAXED(x, off, mask, shift, v) \ - vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) -#define __REG_SET_NORMAL(x, off, mask, shift, v) \ - vop_mask_write(x, off, (mask) << shift, (v) << shift) +#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ + vop_mask_write(x, off, mask, shift, v, write_mask, true) + +#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ + vop_mask_write(x, off, mask, shift, v, write_mask, false) #define REG_SET(x, base, reg, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) + __REG_SET_##mode(x, base + reg.offset, \ + reg.mask, reg.shift, v, reg.write_mask) #define REG_SET_MASK(x, base, reg, mask, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v) + __REG_SET_##mode(x, base + reg.offset, \ + mask, reg.shift, v, reg.write_mask) #define VOP_WIN_SET(x, win, name, v) \ REG_SET(x, win->base, win->phy->name, v, RELAXED) @@ -164,27 +167,25 @@ static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, } static inline void vop_mask_write(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t v) + uint32_t mask, uint32_t shift, uint32_t v, + bool write_mask, bool relaxed) { - if (mask) { - uint32_t cached_val = vop->regsbak[offset >> 2]; - - cached_val = (cached_val & ~mask) | v; - writel(cached_val, vop->regs + offset); - vop->regsbak[offset >> 2] = cached_val; - } -} + if (!mask) + return; -static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t v) -{ - if (mask) { + if (write_mask) { + v = ((v << shift) & 0xffff) | (mask << (shift + 16)); + } else { uint32_t cached_val = vop->regsbak[offset >> 2]; - cached_val = (cached_val & ~mask) | v; - writel_relaxed(cached_val, vop->regs + offset); - vop->regsbak[offset >> 2] = cached_val; + v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); + vop->regsbak[offset >> 2] = v; } + + if (relaxed) + writel_relaxed(v, vop->regs + offset); + else + writel(v, vop->regs + offset); } static inline uint32_t vop_get_intr_type(struct vop *vop, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 071ff0b..28dafb6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -33,6 +33,7 @@ struct vop_reg { uint32_t offset; uint32_t shift; uint32_t mask; + bool write_mask; }; struct vop_ctrl { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 44caf14..e3f72ba 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -23,7 +23,14 @@ #define VOP_REG(off, _mask, s) \ {.offset = off, \ .mask = _mask, \ - .shift = s,} + .shift = s, \ + .write_mask = false,} + +#define VOP_REG_MASK(off, _mask, s) \ + {.offset = off, \ + .mask = _mask, \ + .shift = s, \ + .write_mask = true,} static const uint32_t formats_win_full[] = { DRM_FORMAT_XRGB8888, -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 3/5] drm/rockchip: vop: introduce VOP_REG_MASK @ 2016-08-17 17:23 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-17 17:23 UTC (permalink / raw) To: tfiga, dri-devel, mark.yao; +Cc: linux-rockchip, linux-kernel, linux-arm-kernel From: Mark Yao <mark.yao@rock-chips.com> Some new vop register support mask, bit[16-31] is mask, bit[0-15] is value, the mask is correspond to the value. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul masked 'v' per tfiga's review comments] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Masked v in vop_mask_write to avoid stomping other bits (Tomasz) drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 45 +++++++++++++++-------------- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 9 +++++- 3 files changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 91305eb..5047507 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -36,15 +36,18 @@ #include "rockchip_drm_fb.h" #include "rockchip_drm_vop.h" -#define __REG_SET_RELAXED(x, off, mask, shift, v) \ - vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) -#define __REG_SET_NORMAL(x, off, mask, shift, v) \ - vop_mask_write(x, off, (mask) << shift, (v) << shift) +#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ + vop_mask_write(x, off, mask, shift, v, write_mask, true) + +#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ + vop_mask_write(x, off, mask, shift, v, write_mask, false) #define REG_SET(x, base, reg, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) + __REG_SET_##mode(x, base + reg.offset, \ + reg.mask, reg.shift, v, reg.write_mask) #define REG_SET_MASK(x, base, reg, mask, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v) + __REG_SET_##mode(x, base + reg.offset, \ + mask, reg.shift, v, reg.write_mask) #define VOP_WIN_SET(x, win, name, v) \ REG_SET(x, win->base, win->phy->name, v, RELAXED) @@ -164,27 +167,25 @@ static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, } static inline void vop_mask_write(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t v) + uint32_t mask, uint32_t shift, uint32_t v, + bool write_mask, bool relaxed) { - if (mask) { - uint32_t cached_val = vop->regsbak[offset >> 2]; - - cached_val = (cached_val & ~mask) | v; - writel(cached_val, vop->regs + offset); - vop->regsbak[offset >> 2] = cached_val; - } -} + if (!mask) + return; -static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t v) -{ - if (mask) { + if (write_mask) { + v = ((v << shift) & 0xffff) | (mask << (shift + 16)); + } else { uint32_t cached_val = vop->regsbak[offset >> 2]; - cached_val = (cached_val & ~mask) | v; - writel_relaxed(cached_val, vop->regs + offset); - vop->regsbak[offset >> 2] = cached_val; + v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); + vop->regsbak[offset >> 2] = v; } + + if (relaxed) + writel_relaxed(v, vop->regs + offset); + else + writel(v, vop->regs + offset); } static inline uint32_t vop_get_intr_type(struct vop *vop, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 071ff0b..28dafb6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -33,6 +33,7 @@ struct vop_reg { uint32_t offset; uint32_t shift; uint32_t mask; + bool write_mask; }; struct vop_ctrl { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 44caf14..e3f72ba 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -23,7 +23,14 @@ #define VOP_REG(off, _mask, s) \ {.offset = off, \ .mask = _mask, \ - .shift = s,} + .shift = s, \ + .write_mask = false,} + +#define VOP_REG_MASK(off, _mask, s) \ + {.offset = off, \ + .mask = _mask, \ + .shift = s, \ + .write_mask = true,} static const uint32_t formats_win_full[] = { DRM_FORMAT_XRGB8888, -- 2.8.0.rc3.226.g39d4020 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 4/5] drm/rockchip: vop: add rk3399 vop support 2016-04-20 6:18 ` Mark Yao (?) @ 2016-04-20 6:18 ` Mark Yao -1 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: David Airlie, Heiko Stuebner, dri-devel, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Mark Yao There are two VOP in rk3399 chip, respectively VOP_BIG and VOP_LIT. most registers layout of this two vop is same, their framework are both VOP_FULL, the Major differences of this two is that: VOP_BIG max output resolution is 4096x2160. VOP_LIT max output resolution is 2560x1600 VOP_BIG support four windows. VOP_LIT only support two windows. RK3399 vop register layout is similar with rk3288, so some feature can reuse with rk3288. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 15 ++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 4 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 91 +++++++++++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 193 +++++++++++++++++++++++++++ 4 files changed, 298 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 59f24cd..5c9ff8e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -912,7 +912,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc) u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; u16 vact_end = vact_st + vdisplay; - uint32_t val; + uint32_t pin_pol, val; vop_enable(crtc); /* @@ -951,21 +951,26 @@ static void vop_crtc_enable(struct drm_crtc *crtc) vop_dsp_hold_valid_irq_disable(vop); } - val = 0x8; - val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; - val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); - VOP_CTRL_SET(vop, pin_pol, val); + pin_pol = 0x8; + pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; + pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); + VOP_CTRL_SET(vop, pin_pol, pin_pol); + switch (s->output_type) { case DRM_MODE_CONNECTOR_LVDS: VOP_CTRL_SET(vop, rgb_en, 1); + VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol); break; case DRM_MODE_CONNECTOR_eDP: + VOP_CTRL_SET(vop, edp_pin_pol, pin_pol); VOP_CTRL_SET(vop, edp_en, 1); break; case DRM_MODE_CONNECTOR_HDMIA: + VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol); VOP_CTRL_SET(vop, hdmi_en, 1); break; case DRM_MODE_CONNECTOR_DSI: + VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol); VOP_CTRL_SET(vop, mipi_en, 1); break; default: diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 28dafb6..ff4f52e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -49,6 +49,10 @@ struct vop_ctrl { struct vop_reg dither_down; struct vop_reg dither_up; struct vop_reg pin_pol; + struct vop_reg rgb_pin_pol; + struct vop_reg hdmi_pin_pol; + struct vop_reg edp_pin_pol; + struct vop_reg mipi_pin_pol; struct vop_reg htotal_pw; struct vop_reg hact_st_end; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 6846868..6f42e56 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -278,11 +278,102 @@ static const struct vop_data rk3288_vop = { .win_size = ARRAY_SIZE(rk3288_vop_win_data), }; +static const struct vop_ctrl rk3399_ctrl_data = { + .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22), + .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), + .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12), + .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13), + .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14), + .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15), + .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1), + .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), + .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), + .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), + .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), + .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20), + .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24), + .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28), + .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0), + .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0), + .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0), + .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0), +}; + +static const int rk3399_vop_intrs[] = { + FS_INTR, + 0, 0, + LINE_FLAG_INTR, + 0, + BUS_ERROR_INTR, + 0, 0, 0, 0, 0, 0, 0, + DSP_HOLD_VALID_INTR, +}; + +static const struct vop_intr rk3399_vop_intr = { + .intrs = rk3399_vop_intrs, + .nintrs = ARRAY_SIZE(rk3399_vop_intrs), + .status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0), + .enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0), + .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0), +}; + +static const struct vop_reg_data rk3399_init_reg_table[] = { + {RK3399_SYS_CTRL, 0x2000f800}, + {RK3399_DSP_CTRL0, 0x00000000}, + {RK3399_WIN0_CTRL0, 0x00000080}, + {RK3399_WIN1_CTRL0, 0x00000080}, + /* TODO: Win2/3 support multiple area function, but we haven't found + * a suitable way to use it yet, so let's just use them as other windows + * with only area 0 enabled. + */ + {RK3399_WIN2_CTRL0, 0x00000010}, + {RK3399_WIN3_CTRL0, 0x00000010}, +}; + +static const struct vop_data rk3399_vop_big = { + .init_table = rk3399_init_reg_table, + .table_size = ARRAY_SIZE(rk3399_init_reg_table), + .intr = &rk3399_vop_intr, + .ctrl = &rk3399_ctrl_data, + /* + * rk3399 vop big windows register layout is same as rk3288. + */ + .win = rk3288_vop_win_data, + .win_size = ARRAY_SIZE(rk3288_vop_win_data), +}; + +static const struct vop_win_data rk3399_vop_lit_win_data[] = { + { .base = 0x00, .phy = &rk3288_win01_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x00, .phy = &rk3288_win23_data, + .type = DRM_PLANE_TYPE_CURSOR}, +}; + +static const struct vop_data rk3399_vop_lit = { + .init_table = rk3399_init_reg_table, + .table_size = ARRAY_SIZE(rk3399_init_reg_table), + .intr = &rk3399_vop_intr, + .ctrl = &rk3399_ctrl_data, + /* + * rk3399 vop lit windows register layout is same as rk3288, + * but cut off the win1 and win3 windows. + */ + .win = rk3399_vop_lit_win_data, + .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), +}; + static const struct of_device_id vop_driver_dt_match[] = { { .compatible = "rockchip,rk3036-vop", .data = &rk3036_vop }, { .compatible = "rockchip,rk3288-vop", .data = &rk3288_vop }, + { .compatible = "rockchip,rk3399-vop-big", + .data = &rk3399_vop_big }, + { .compatible = "rockchip,rk3399-vop-lit", + .data = &rk3399_vop_lit }, {}, }; MODULE_DEVICE_TABLE(of, vop_driver_dt_match); diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 43903e0..2cae529 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -166,4 +166,197 @@ #define RK3288_DSP_VACT_ST_END_F1 0x019c /* register definition end */ +/* rk3399 register definition */ +#define RK3399_REG_CFG_DONE 0x00000 +#define RK3399_VERSION_INFO 0x00004 +#define RK3399_SYS_CTRL 0x00008 +#define RK3399_SYS_CTRL1 0x0000c +#define RK3399_DSP_CTRL0 0x00010 +#define RK3399_DSP_CTRL1 0x00014 +#define RK3399_DSP_BG 0x00018 +#define RK3399_MCU_CTRL 0x0001c +#define RK3399_WB_CTRL0 0x00020 +#define RK3399_WB_CTRL1 0x00024 +#define RK3399_WB_YRGB_MST 0x00028 +#define RK3399_WB_CBR_MST 0x0002c +#define RK3399_WIN0_CTRL0 0x00030 +#define RK3399_WIN0_CTRL1 0x00034 +#define RK3399_WIN0_COLOR_KEY 0x00038 +#define RK3399_WIN0_VIR 0x0003c +#define RK3399_WIN0_YRGB_MST 0x00040 +#define RK3399_WIN0_CBR_MST 0x00044 +#define RK3399_WIN0_ACT_INFO 0x00048 +#define RK3399_WIN0_DSP_INFO 0x0004c +#define RK3399_WIN0_DSP_ST 0x00050 +#define RK3399_WIN0_SCL_FACTOR_YRGB 0x00054 +#define RK3399_WIN0_SCL_FACTOR_CBR 0x00058 +#define RK3399_WIN0_SCL_OFFSET 0x0005c +#define RK3399_WIN0_SRC_ALPHA_CTRL 0x00060 +#define RK3399_WIN0_DST_ALPHA_CTRL 0x00064 +#define RK3399_WIN0_FADING_CTRL 0x00068 +#define RK3399_WIN0_CTRL2 0x0006c +#define RK3399_WIN1_CTRL0 0x00070 +#define RK3399_WIN1_CTRL1 0x00074 +#define RK3399_WIN1_COLOR_KEY 0x00078 +#define RK3399_WIN1_VIR 0x0007c +#define RK3399_WIN1_YRGB_MST 0x00080 +#define RK3399_WIN1_CBR_MST 0x00084 +#define RK3399_WIN1_ACT_INFO 0x00088 +#define RK3399_WIN1_DSP_INFO 0x0008c +#define RK3399_WIN1_DSP_ST 0x00090 +#define RK3399_WIN1_SCL_FACTOR_YRGB 0x00094 +#define RK3399_WIN1_SCL_FACTOR_CBR 0x00098 +#define RK3399_WIN1_SCL_OFFSET 0x0009c +#define RK3399_WIN1_SRC_ALPHA_CTRL 0x000a0 +#define RK3399_WIN1_DST_ALPHA_CTRL 0x000a4 +#define RK3399_WIN1_FADING_CTRL 0x000a8 +#define RK3399_WIN1_CTRL2 0x000ac +#define RK3399_WIN2_CTRL0 0x000b0 +#define RK3399_WIN2_CTRL1 0x000b4 +#define RK3399_WIN2_VIR0_1 0x000b8 +#define RK3399_WIN2_VIR2_3 0x000bc +#define RK3399_WIN2_MST0 0x000c0 +#define RK3399_WIN2_DSP_INFO0 0x000c4 +#define RK3399_WIN2_DSP_ST0 0x000c8 +#define RK3399_WIN2_COLOR_KEY 0x000cc +#define RK3399_WIN2_MST1 0x000d0 +#define RK3399_WIN2_DSP_INFO1 0x000d4 +#define RK3399_WIN2_DSP_ST1 0x000d8 +#define RK3399_WIN2_SRC_ALPHA_CTRL 0x000dc +#define RK3399_WIN2_MST2 0x000e0 +#define RK3399_WIN2_DSP_INFO2 0x000e4 +#define RK3399_WIN2_DSP_ST2 0x000e8 +#define RK3399_WIN2_DST_ALPHA_CTRL 0x000ec +#define RK3399_WIN2_MST3 0x000f0 +#define RK3399_WIN2_DSP_INFO3 0x000f4 +#define RK3399_WIN2_DSP_ST3 0x000f8 +#define RK3399_WIN2_FADING_CTRL 0x000fc +#define RK3399_WIN3_CTRL0 0x00100 +#define RK3399_WIN3_CTRL1 0x00104 +#define RK3399_WIN3_VIR0_1 0x00108 +#define RK3399_WIN3_VIR2_3 0x0010c +#define RK3399_WIN3_MST0 0x00110 +#define RK3399_WIN3_DSP_INFO0 0x00114 +#define RK3399_WIN3_DSP_ST0 0x00118 +#define RK3399_WIN3_COLOR_KEY 0x0011c +#define RK3399_WIN3_MST1 0x00120 +#define RK3399_WIN3_DSP_INFO1 0x00124 +#define RK3399_WIN3_DSP_ST1 0x00128 +#define RK3399_WIN3_SRC_ALPHA_CTRL 0x0012c +#define RK3399_WIN3_MST2 0x00130 +#define RK3399_WIN3_DSP_INFO2 0x00134 +#define RK3399_WIN3_DSP_ST2 0x00138 +#define RK3399_WIN3_DST_ALPHA_CTRL 0x0013c +#define RK3399_WIN3_MST3 0x00140 +#define RK3399_WIN3_DSP_INFO3 0x00144 +#define RK3399_WIN3_DSP_ST3 0x00148 +#define RK3399_WIN3_FADING_CTRL 0x0014c +#define RK3399_HWC_CTRL0 0x00150 +#define RK3399_HWC_CTRL1 0x00154 +#define RK3399_HWC_MST 0x00158 +#define RK3399_HWC_DSP_ST 0x0015c +#define RK3399_HWC_SRC_ALPHA_CTRL 0x00160 +#define RK3399_HWC_DST_ALPHA_CTRL 0x00164 +#define RK3399_HWC_FADING_CTRL 0x00168 +#define RK3399_HWC_RESERVED1 0x0016c +#define RK3399_POST_DSP_HACT_INFO 0x00170 +#define RK3399_POST_DSP_VACT_INFO 0x00174 +#define RK3399_POST_SCL_FACTOR_YRGB 0x00178 +#define RK3399_POST_RESERVED 0x0017c +#define RK3399_POST_SCL_CTRL 0x00180 +#define RK3399_POST_DSP_VACT_INFO_F1 0x00184 +#define RK3399_DSP_HTOTAL_HS_END 0x00188 +#define RK3399_DSP_HACT_ST_END 0x0018c +#define RK3399_DSP_VTOTAL_VS_END 0x00190 +#define RK3399_DSP_VACT_ST_END 0x00194 +#define RK3399_DSP_VS_ST_END_F1 0x00198 +#define RK3399_DSP_VACT_ST_END_F1 0x0019c +#define RK3399_PWM_CTRL 0x001a0 +#define RK3399_PWM_PERIOD_HPR 0x001a4 +#define RK3399_PWM_DUTY_LPR 0x001a8 +#define RK3399_PWM_CNT 0x001ac +#define RK3399_BCSH_COLOR_BAR 0x001b0 +#define RK3399_BCSH_BCS 0x001b4 +#define RK3399_BCSH_H 0x001b8 +#define RK3399_BCSH_CTRL 0x001bc +#define RK3399_CABC_CTRL0 0x001c0 +#define RK3399_CABC_CTRL1 0x001c4 +#define RK3399_CABC_CTRL2 0x001c8 +#define RK3399_CABC_CTRL3 0x001cc +#define RK3399_CABC_GAUSS_LINE0_0 0x001d0 +#define RK3399_CABC_GAUSS_LINE0_1 0x001d4 +#define RK3399_CABC_GAUSS_LINE1_0 0x001d8 +#define RK3399_CABC_GAUSS_LINE1_1 0x001dc +#define RK3399_CABC_GAUSS_LINE2_0 0x001e0 +#define RK3399_CABC_GAUSS_LINE2_1 0x001e4 +#define RK3399_FRC_LOWER01_0 0x001e8 +#define RK3399_FRC_LOWER01_1 0x001ec +#define RK3399_FRC_LOWER10_0 0x001f0 +#define RK3399_FRC_LOWER10_1 0x001f4 +#define RK3399_FRC_LOWER11_0 0x001f8 +#define RK3399_FRC_LOWER11_1 0x001fc +#define RK3399_AFBCD0_CTRL 0x00200 +#define RK3399_AFBCD0_HDR_PTR 0x00204 +#define RK3399_AFBCD0_PIC_SIZE 0x00208 +#define RK3399_AFBCD0_STATUS 0x0020c +#define RK3399_AFBCD1_CTRL 0x00220 +#define RK3399_AFBCD1_HDR_PTR 0x00224 +#define RK3399_AFBCD1_PIC_SIZE 0x00228 +#define RK3399_AFBCD1_STATUS 0x0022c +#define RK3399_AFBCD2_CTRL 0x00240 +#define RK3399_AFBCD2_HDR_PTR 0x00244 +#define RK3399_AFBCD2_PIC_SIZE 0x00248 +#define RK3399_AFBCD2_STATUS 0x0024c +#define RK3399_AFBCD3_CTRL 0x00260 +#define RK3399_AFBCD3_HDR_PTR 0x00264 +#define RK3399_AFBCD3_PIC_SIZE 0x00268 +#define RK3399_AFBCD3_STATUS 0x0026c +#define RK3399_INTR_EN0 0x00280 +#define RK3399_INTR_CLEAR0 0x00284 +#define RK3399_INTR_STATUS0 0x00288 +#define RK3399_INTR_RAW_STATUS0 0x0028c +#define RK3399_INTR_EN1 0x00290 +#define RK3399_INTR_CLEAR1 0x00294 +#define RK3399_INTR_STATUS1 0x00298 +#define RK3399_INTR_RAW_STATUS1 0x0029c +#define RK3399_LINE_FLAG 0x002a0 +#define RK3399_VOP_STATUS 0x002a4 +#define RK3399_BLANKING_VALUE 0x002a8 +#define RK3399_MCU_BYPASS_PORT 0x002ac +#define RK3399_WIN0_DSP_BG 0x002b0 +#define RK3399_WIN1_DSP_BG 0x002b4 +#define RK3399_WIN2_DSP_BG 0x002b8 +#define RK3399_WIN3_DSP_BG 0x002bc +#define RK3399_YUV2YUV_WIN 0x002c0 +#define RK3399_YUV2YUV_POST 0x002c4 +#define RK3399_AUTO_GATING_EN 0x002cc +#define RK3399_WIN0_CSC_COE 0x003a0 +#define RK3399_WIN1_CSC_COE 0x003c0 +#define RK3399_WIN2_CSC_COE 0x003e0 +#define RK3399_WIN3_CSC_COE 0x00400 +#define RK3399_HWC_CSC_COE 0x00420 +#define RK3399_BCSH_R2Y_CSC_COE 0x00440 +#define RK3399_BCSH_Y2R_CSC_COE 0x00460 +#define RK3399_POST_YUV2YUV_Y2R_COE 0x00480 +#define RK3399_POST_YUV2YUV_3X3_COE 0x004a0 +#define RK3399_POST_YUV2YUV_R2Y_COE 0x004c0 +#define RK3399_WIN0_YUV2YUV_Y2R 0x004e0 +#define RK3399_WIN0_YUV2YUV_3X3 0x00500 +#define RK3399_WIN0_YUV2YUV_R2Y 0x00520 +#define RK3399_WIN1_YUV2YUV_Y2R 0x00540 +#define RK3399_WIN1_YUV2YUV_3X3 0x00560 +#define RK3399_WIN1_YUV2YUV_R2Y 0x00580 +#define RK3399_WIN2_YUV2YUV_Y2R 0x005a0 +#define RK3399_WIN2_YUV2YUV_3X3 0x005c0 +#define RK3399_WIN2_YUV2YUV_R2Y 0x005e0 +#define RK3399_WIN3_YUV2YUV_Y2R 0x00600 +#define RK3399_WIN3_YUV2YUV_3X3 0x00620 +#define RK3399_WIN3_YUV2YUV_R2Y 0x00640 +#define RK3399_WIN2_LUT_ADDR 0x01000 +#define RK3399_WIN3_LUT_ADDR 0x01400 +#define RK3399_HWC_LUT_ADDR 0x01800 +#define RK3399_CABC_GAMMA_LUT_ADDR 0x01c00 +#define RK3399_GAMMA_LUT_ADDR 0x02000 +/* rk3399 register definition end */ + #endif /* _ROCKCHIP_VOP_REG_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 4/5] drm/rockchip: vop: add rk3399 vop support @ 2016-04-20 6:18 ` Mark Yao 0 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: linux-arm-kernel There are two VOP in rk3399 chip, respectively VOP_BIG and VOP_LIT. most registers layout of this two vop is same, their framework are both VOP_FULL, the Major differences of this two is that: VOP_BIG max output resolution is 4096x2160. VOP_LIT max output resolution is 2560x1600 VOP_BIG support four windows. VOP_LIT only support two windows. RK3399 vop register layout is similar with rk3288, so some feature can reuse with rk3288. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 15 ++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 4 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 91 +++++++++++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 193 +++++++++++++++++++++++++++ 4 files changed, 298 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 59f24cd..5c9ff8e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -912,7 +912,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc) u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; u16 vact_end = vact_st + vdisplay; - uint32_t val; + uint32_t pin_pol, val; vop_enable(crtc); /* @@ -951,21 +951,26 @@ static void vop_crtc_enable(struct drm_crtc *crtc) vop_dsp_hold_valid_irq_disable(vop); } - val = 0x8; - val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; - val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); - VOP_CTRL_SET(vop, pin_pol, val); + pin_pol = 0x8; + pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; + pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); + VOP_CTRL_SET(vop, pin_pol, pin_pol); + switch (s->output_type) { case DRM_MODE_CONNECTOR_LVDS: VOP_CTRL_SET(vop, rgb_en, 1); + VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol); break; case DRM_MODE_CONNECTOR_eDP: + VOP_CTRL_SET(vop, edp_pin_pol, pin_pol); VOP_CTRL_SET(vop, edp_en, 1); break; case DRM_MODE_CONNECTOR_HDMIA: + VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol); VOP_CTRL_SET(vop, hdmi_en, 1); break; case DRM_MODE_CONNECTOR_DSI: + VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol); VOP_CTRL_SET(vop, mipi_en, 1); break; default: diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 28dafb6..ff4f52e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -49,6 +49,10 @@ struct vop_ctrl { struct vop_reg dither_down; struct vop_reg dither_up; struct vop_reg pin_pol; + struct vop_reg rgb_pin_pol; + struct vop_reg hdmi_pin_pol; + struct vop_reg edp_pin_pol; + struct vop_reg mipi_pin_pol; struct vop_reg htotal_pw; struct vop_reg hact_st_end; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 6846868..6f42e56 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -278,11 +278,102 @@ static const struct vop_data rk3288_vop = { .win_size = ARRAY_SIZE(rk3288_vop_win_data), }; +static const struct vop_ctrl rk3399_ctrl_data = { + .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22), + .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), + .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12), + .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13), + .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14), + .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15), + .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1), + .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), + .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), + .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), + .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), + .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20), + .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24), + .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28), + .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0), + .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0), + .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0), + .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0), +}; + +static const int rk3399_vop_intrs[] = { + FS_INTR, + 0, 0, + LINE_FLAG_INTR, + 0, + BUS_ERROR_INTR, + 0, 0, 0, 0, 0, 0, 0, + DSP_HOLD_VALID_INTR, +}; + +static const struct vop_intr rk3399_vop_intr = { + .intrs = rk3399_vop_intrs, + .nintrs = ARRAY_SIZE(rk3399_vop_intrs), + .status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0), + .enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0), + .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0), +}; + +static const struct vop_reg_data rk3399_init_reg_table[] = { + {RK3399_SYS_CTRL, 0x2000f800}, + {RK3399_DSP_CTRL0, 0x00000000}, + {RK3399_WIN0_CTRL0, 0x00000080}, + {RK3399_WIN1_CTRL0, 0x00000080}, + /* TODO: Win2/3 support multiple area function, but we haven't found + * a suitable way to use it yet, so let's just use them as other windows + * with only area 0 enabled. + */ + {RK3399_WIN2_CTRL0, 0x00000010}, + {RK3399_WIN3_CTRL0, 0x00000010}, +}; + +static const struct vop_data rk3399_vop_big = { + .init_table = rk3399_init_reg_table, + .table_size = ARRAY_SIZE(rk3399_init_reg_table), + .intr = &rk3399_vop_intr, + .ctrl = &rk3399_ctrl_data, + /* + * rk3399 vop big windows register layout is same as rk3288. + */ + .win = rk3288_vop_win_data, + .win_size = ARRAY_SIZE(rk3288_vop_win_data), +}; + +static const struct vop_win_data rk3399_vop_lit_win_data[] = { + { .base = 0x00, .phy = &rk3288_win01_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x00, .phy = &rk3288_win23_data, + .type = DRM_PLANE_TYPE_CURSOR}, +}; + +static const struct vop_data rk3399_vop_lit = { + .init_table = rk3399_init_reg_table, + .table_size = ARRAY_SIZE(rk3399_init_reg_table), + .intr = &rk3399_vop_intr, + .ctrl = &rk3399_ctrl_data, + /* + * rk3399 vop lit windows register layout is same as rk3288, + * but cut off the win1 and win3 windows. + */ + .win = rk3399_vop_lit_win_data, + .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), +}; + static const struct of_device_id vop_driver_dt_match[] = { { .compatible = "rockchip,rk3036-vop", .data = &rk3036_vop }, { .compatible = "rockchip,rk3288-vop", .data = &rk3288_vop }, + { .compatible = "rockchip,rk3399-vop-big", + .data = &rk3399_vop_big }, + { .compatible = "rockchip,rk3399-vop-lit", + .data = &rk3399_vop_lit }, {}, }; MODULE_DEVICE_TABLE(of, vop_driver_dt_match); diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 43903e0..2cae529 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -166,4 +166,197 @@ #define RK3288_DSP_VACT_ST_END_F1 0x019c /* register definition end */ +/* rk3399 register definition */ +#define RK3399_REG_CFG_DONE 0x00000 +#define RK3399_VERSION_INFO 0x00004 +#define RK3399_SYS_CTRL 0x00008 +#define RK3399_SYS_CTRL1 0x0000c +#define RK3399_DSP_CTRL0 0x00010 +#define RK3399_DSP_CTRL1 0x00014 +#define RK3399_DSP_BG 0x00018 +#define RK3399_MCU_CTRL 0x0001c +#define RK3399_WB_CTRL0 0x00020 +#define RK3399_WB_CTRL1 0x00024 +#define RK3399_WB_YRGB_MST 0x00028 +#define RK3399_WB_CBR_MST 0x0002c +#define RK3399_WIN0_CTRL0 0x00030 +#define RK3399_WIN0_CTRL1 0x00034 +#define RK3399_WIN0_COLOR_KEY 0x00038 +#define RK3399_WIN0_VIR 0x0003c +#define RK3399_WIN0_YRGB_MST 0x00040 +#define RK3399_WIN0_CBR_MST 0x00044 +#define RK3399_WIN0_ACT_INFO 0x00048 +#define RK3399_WIN0_DSP_INFO 0x0004c +#define RK3399_WIN0_DSP_ST 0x00050 +#define RK3399_WIN0_SCL_FACTOR_YRGB 0x00054 +#define RK3399_WIN0_SCL_FACTOR_CBR 0x00058 +#define RK3399_WIN0_SCL_OFFSET 0x0005c +#define RK3399_WIN0_SRC_ALPHA_CTRL 0x00060 +#define RK3399_WIN0_DST_ALPHA_CTRL 0x00064 +#define RK3399_WIN0_FADING_CTRL 0x00068 +#define RK3399_WIN0_CTRL2 0x0006c +#define RK3399_WIN1_CTRL0 0x00070 +#define RK3399_WIN1_CTRL1 0x00074 +#define RK3399_WIN1_COLOR_KEY 0x00078 +#define RK3399_WIN1_VIR 0x0007c +#define RK3399_WIN1_YRGB_MST 0x00080 +#define RK3399_WIN1_CBR_MST 0x00084 +#define RK3399_WIN1_ACT_INFO 0x00088 +#define RK3399_WIN1_DSP_INFO 0x0008c +#define RK3399_WIN1_DSP_ST 0x00090 +#define RK3399_WIN1_SCL_FACTOR_YRGB 0x00094 +#define RK3399_WIN1_SCL_FACTOR_CBR 0x00098 +#define RK3399_WIN1_SCL_OFFSET 0x0009c +#define RK3399_WIN1_SRC_ALPHA_CTRL 0x000a0 +#define RK3399_WIN1_DST_ALPHA_CTRL 0x000a4 +#define RK3399_WIN1_FADING_CTRL 0x000a8 +#define RK3399_WIN1_CTRL2 0x000ac +#define RK3399_WIN2_CTRL0 0x000b0 +#define RK3399_WIN2_CTRL1 0x000b4 +#define RK3399_WIN2_VIR0_1 0x000b8 +#define RK3399_WIN2_VIR2_3 0x000bc +#define RK3399_WIN2_MST0 0x000c0 +#define RK3399_WIN2_DSP_INFO0 0x000c4 +#define RK3399_WIN2_DSP_ST0 0x000c8 +#define RK3399_WIN2_COLOR_KEY 0x000cc +#define RK3399_WIN2_MST1 0x000d0 +#define RK3399_WIN2_DSP_INFO1 0x000d4 +#define RK3399_WIN2_DSP_ST1 0x000d8 +#define RK3399_WIN2_SRC_ALPHA_CTRL 0x000dc +#define RK3399_WIN2_MST2 0x000e0 +#define RK3399_WIN2_DSP_INFO2 0x000e4 +#define RK3399_WIN2_DSP_ST2 0x000e8 +#define RK3399_WIN2_DST_ALPHA_CTRL 0x000ec +#define RK3399_WIN2_MST3 0x000f0 +#define RK3399_WIN2_DSP_INFO3 0x000f4 +#define RK3399_WIN2_DSP_ST3 0x000f8 +#define RK3399_WIN2_FADING_CTRL 0x000fc +#define RK3399_WIN3_CTRL0 0x00100 +#define RK3399_WIN3_CTRL1 0x00104 +#define RK3399_WIN3_VIR0_1 0x00108 +#define RK3399_WIN3_VIR2_3 0x0010c +#define RK3399_WIN3_MST0 0x00110 +#define RK3399_WIN3_DSP_INFO0 0x00114 +#define RK3399_WIN3_DSP_ST0 0x00118 +#define RK3399_WIN3_COLOR_KEY 0x0011c +#define RK3399_WIN3_MST1 0x00120 +#define RK3399_WIN3_DSP_INFO1 0x00124 +#define RK3399_WIN3_DSP_ST1 0x00128 +#define RK3399_WIN3_SRC_ALPHA_CTRL 0x0012c +#define RK3399_WIN3_MST2 0x00130 +#define RK3399_WIN3_DSP_INFO2 0x00134 +#define RK3399_WIN3_DSP_ST2 0x00138 +#define RK3399_WIN3_DST_ALPHA_CTRL 0x0013c +#define RK3399_WIN3_MST3 0x00140 +#define RK3399_WIN3_DSP_INFO3 0x00144 +#define RK3399_WIN3_DSP_ST3 0x00148 +#define RK3399_WIN3_FADING_CTRL 0x0014c +#define RK3399_HWC_CTRL0 0x00150 +#define RK3399_HWC_CTRL1 0x00154 +#define RK3399_HWC_MST 0x00158 +#define RK3399_HWC_DSP_ST 0x0015c +#define RK3399_HWC_SRC_ALPHA_CTRL 0x00160 +#define RK3399_HWC_DST_ALPHA_CTRL 0x00164 +#define RK3399_HWC_FADING_CTRL 0x00168 +#define RK3399_HWC_RESERVED1 0x0016c +#define RK3399_POST_DSP_HACT_INFO 0x00170 +#define RK3399_POST_DSP_VACT_INFO 0x00174 +#define RK3399_POST_SCL_FACTOR_YRGB 0x00178 +#define RK3399_POST_RESERVED 0x0017c +#define RK3399_POST_SCL_CTRL 0x00180 +#define RK3399_POST_DSP_VACT_INFO_F1 0x00184 +#define RK3399_DSP_HTOTAL_HS_END 0x00188 +#define RK3399_DSP_HACT_ST_END 0x0018c +#define RK3399_DSP_VTOTAL_VS_END 0x00190 +#define RK3399_DSP_VACT_ST_END 0x00194 +#define RK3399_DSP_VS_ST_END_F1 0x00198 +#define RK3399_DSP_VACT_ST_END_F1 0x0019c +#define RK3399_PWM_CTRL 0x001a0 +#define RK3399_PWM_PERIOD_HPR 0x001a4 +#define RK3399_PWM_DUTY_LPR 0x001a8 +#define RK3399_PWM_CNT 0x001ac +#define RK3399_BCSH_COLOR_BAR 0x001b0 +#define RK3399_BCSH_BCS 0x001b4 +#define RK3399_BCSH_H 0x001b8 +#define RK3399_BCSH_CTRL 0x001bc +#define RK3399_CABC_CTRL0 0x001c0 +#define RK3399_CABC_CTRL1 0x001c4 +#define RK3399_CABC_CTRL2 0x001c8 +#define RK3399_CABC_CTRL3 0x001cc +#define RK3399_CABC_GAUSS_LINE0_0 0x001d0 +#define RK3399_CABC_GAUSS_LINE0_1 0x001d4 +#define RK3399_CABC_GAUSS_LINE1_0 0x001d8 +#define RK3399_CABC_GAUSS_LINE1_1 0x001dc +#define RK3399_CABC_GAUSS_LINE2_0 0x001e0 +#define RK3399_CABC_GAUSS_LINE2_1 0x001e4 +#define RK3399_FRC_LOWER01_0 0x001e8 +#define RK3399_FRC_LOWER01_1 0x001ec +#define RK3399_FRC_LOWER10_0 0x001f0 +#define RK3399_FRC_LOWER10_1 0x001f4 +#define RK3399_FRC_LOWER11_0 0x001f8 +#define RK3399_FRC_LOWER11_1 0x001fc +#define RK3399_AFBCD0_CTRL 0x00200 +#define RK3399_AFBCD0_HDR_PTR 0x00204 +#define RK3399_AFBCD0_PIC_SIZE 0x00208 +#define RK3399_AFBCD0_STATUS 0x0020c +#define RK3399_AFBCD1_CTRL 0x00220 +#define RK3399_AFBCD1_HDR_PTR 0x00224 +#define RK3399_AFBCD1_PIC_SIZE 0x00228 +#define RK3399_AFBCD1_STATUS 0x0022c +#define RK3399_AFBCD2_CTRL 0x00240 +#define RK3399_AFBCD2_HDR_PTR 0x00244 +#define RK3399_AFBCD2_PIC_SIZE 0x00248 +#define RK3399_AFBCD2_STATUS 0x0024c +#define RK3399_AFBCD3_CTRL 0x00260 +#define RK3399_AFBCD3_HDR_PTR 0x00264 +#define RK3399_AFBCD3_PIC_SIZE 0x00268 +#define RK3399_AFBCD3_STATUS 0x0026c +#define RK3399_INTR_EN0 0x00280 +#define RK3399_INTR_CLEAR0 0x00284 +#define RK3399_INTR_STATUS0 0x00288 +#define RK3399_INTR_RAW_STATUS0 0x0028c +#define RK3399_INTR_EN1 0x00290 +#define RK3399_INTR_CLEAR1 0x00294 +#define RK3399_INTR_STATUS1 0x00298 +#define RK3399_INTR_RAW_STATUS1 0x0029c +#define RK3399_LINE_FLAG 0x002a0 +#define RK3399_VOP_STATUS 0x002a4 +#define RK3399_BLANKING_VALUE 0x002a8 +#define RK3399_MCU_BYPASS_PORT 0x002ac +#define RK3399_WIN0_DSP_BG 0x002b0 +#define RK3399_WIN1_DSP_BG 0x002b4 +#define RK3399_WIN2_DSP_BG 0x002b8 +#define RK3399_WIN3_DSP_BG 0x002bc +#define RK3399_YUV2YUV_WIN 0x002c0 +#define RK3399_YUV2YUV_POST 0x002c4 +#define RK3399_AUTO_GATING_EN 0x002cc +#define RK3399_WIN0_CSC_COE 0x003a0 +#define RK3399_WIN1_CSC_COE 0x003c0 +#define RK3399_WIN2_CSC_COE 0x003e0 +#define RK3399_WIN3_CSC_COE 0x00400 +#define RK3399_HWC_CSC_COE 0x00420 +#define RK3399_BCSH_R2Y_CSC_COE 0x00440 +#define RK3399_BCSH_Y2R_CSC_COE 0x00460 +#define RK3399_POST_YUV2YUV_Y2R_COE 0x00480 +#define RK3399_POST_YUV2YUV_3X3_COE 0x004a0 +#define RK3399_POST_YUV2YUV_R2Y_COE 0x004c0 +#define RK3399_WIN0_YUV2YUV_Y2R 0x004e0 +#define RK3399_WIN0_YUV2YUV_3X3 0x00500 +#define RK3399_WIN0_YUV2YUV_R2Y 0x00520 +#define RK3399_WIN1_YUV2YUV_Y2R 0x00540 +#define RK3399_WIN1_YUV2YUV_3X3 0x00560 +#define RK3399_WIN1_YUV2YUV_R2Y 0x00580 +#define RK3399_WIN2_YUV2YUV_Y2R 0x005a0 +#define RK3399_WIN2_YUV2YUV_3X3 0x005c0 +#define RK3399_WIN2_YUV2YUV_R2Y 0x005e0 +#define RK3399_WIN3_YUV2YUV_Y2R 0x00600 +#define RK3399_WIN3_YUV2YUV_3X3 0x00620 +#define RK3399_WIN3_YUV2YUV_R2Y 0x00640 +#define RK3399_WIN2_LUT_ADDR 0x01000 +#define RK3399_WIN3_LUT_ADDR 0x01400 +#define RK3399_HWC_LUT_ADDR 0x01800 +#define RK3399_CABC_GAMMA_LUT_ADDR 0x01c00 +#define RK3399_GAMMA_LUT_ADDR 0x02000 +/* rk3399 register definition end */ + #endif /* _ROCKCHIP_VOP_REG_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 4/5] drm/rockchip: vop: add rk3399 vop support @ 2016-04-20 6:18 ` Mark Yao 0 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:18 UTC (permalink / raw) To: David Airlie, Heiko Stuebner, dri-devel, linux-arm-kernel, linux-rockchip, linux-kernel There are two VOP in rk3399 chip, respectively VOP_BIG and VOP_LIT. most registers layout of this two vop is same, their framework are both VOP_FULL, the Major differences of this two is that: VOP_BIG max output resolution is 4096x2160. VOP_LIT max output resolution is 2560x1600 VOP_BIG support four windows. VOP_LIT only support two windows. RK3399 vop register layout is similar with rk3288, so some feature can reuse with rk3288. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 15 ++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 4 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 91 +++++++++++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 193 +++++++++++++++++++++++++++ 4 files changed, 298 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 59f24cd..5c9ff8e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -912,7 +912,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc) u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; u16 vact_end = vact_st + vdisplay; - uint32_t val; + uint32_t pin_pol, val; vop_enable(crtc); /* @@ -951,21 +951,26 @@ static void vop_crtc_enable(struct drm_crtc *crtc) vop_dsp_hold_valid_irq_disable(vop); } - val = 0x8; - val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; - val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); - VOP_CTRL_SET(vop, pin_pol, val); + pin_pol = 0x8; + pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; + pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); + VOP_CTRL_SET(vop, pin_pol, pin_pol); + switch (s->output_type) { case DRM_MODE_CONNECTOR_LVDS: VOP_CTRL_SET(vop, rgb_en, 1); + VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol); break; case DRM_MODE_CONNECTOR_eDP: + VOP_CTRL_SET(vop, edp_pin_pol, pin_pol); VOP_CTRL_SET(vop, edp_en, 1); break; case DRM_MODE_CONNECTOR_HDMIA: + VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol); VOP_CTRL_SET(vop, hdmi_en, 1); break; case DRM_MODE_CONNECTOR_DSI: + VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol); VOP_CTRL_SET(vop, mipi_en, 1); break; default: diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 28dafb6..ff4f52e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -49,6 +49,10 @@ struct vop_ctrl { struct vop_reg dither_down; struct vop_reg dither_up; struct vop_reg pin_pol; + struct vop_reg rgb_pin_pol; + struct vop_reg hdmi_pin_pol; + struct vop_reg edp_pin_pol; + struct vop_reg mipi_pin_pol; struct vop_reg htotal_pw; struct vop_reg hact_st_end; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 6846868..6f42e56 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -278,11 +278,102 @@ static const struct vop_data rk3288_vop = { .win_size = ARRAY_SIZE(rk3288_vop_win_data), }; +static const struct vop_ctrl rk3399_ctrl_data = { + .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22), + .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), + .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12), + .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13), + .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14), + .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15), + .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1), + .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), + .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), + .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), + .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), + .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20), + .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24), + .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28), + .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0), + .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0), + .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0), + .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0), +}; + +static const int rk3399_vop_intrs[] = { + FS_INTR, + 0, 0, + LINE_FLAG_INTR, + 0, + BUS_ERROR_INTR, + 0, 0, 0, 0, 0, 0, 0, + DSP_HOLD_VALID_INTR, +}; + +static const struct vop_intr rk3399_vop_intr = { + .intrs = rk3399_vop_intrs, + .nintrs = ARRAY_SIZE(rk3399_vop_intrs), + .status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0), + .enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0), + .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0), +}; + +static const struct vop_reg_data rk3399_init_reg_table[] = { + {RK3399_SYS_CTRL, 0x2000f800}, + {RK3399_DSP_CTRL0, 0x00000000}, + {RK3399_WIN0_CTRL0, 0x00000080}, + {RK3399_WIN1_CTRL0, 0x00000080}, + /* TODO: Win2/3 support multiple area function, but we haven't found + * a suitable way to use it yet, so let's just use them as other windows + * with only area 0 enabled. + */ + {RK3399_WIN2_CTRL0, 0x00000010}, + {RK3399_WIN3_CTRL0, 0x00000010}, +}; + +static const struct vop_data rk3399_vop_big = { + .init_table = rk3399_init_reg_table, + .table_size = ARRAY_SIZE(rk3399_init_reg_table), + .intr = &rk3399_vop_intr, + .ctrl = &rk3399_ctrl_data, + /* + * rk3399 vop big windows register layout is same as rk3288. + */ + .win = rk3288_vop_win_data, + .win_size = ARRAY_SIZE(rk3288_vop_win_data), +}; + +static const struct vop_win_data rk3399_vop_lit_win_data[] = { + { .base = 0x00, .phy = &rk3288_win01_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x00, .phy = &rk3288_win23_data, + .type = DRM_PLANE_TYPE_CURSOR}, +}; + +static const struct vop_data rk3399_vop_lit = { + .init_table = rk3399_init_reg_table, + .table_size = ARRAY_SIZE(rk3399_init_reg_table), + .intr = &rk3399_vop_intr, + .ctrl = &rk3399_ctrl_data, + /* + * rk3399 vop lit windows register layout is same as rk3288, + * but cut off the win1 and win3 windows. + */ + .win = rk3399_vop_lit_win_data, + .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), +}; + static const struct of_device_id vop_driver_dt_match[] = { { .compatible = "rockchip,rk3036-vop", .data = &rk3036_vop }, { .compatible = "rockchip,rk3288-vop", .data = &rk3288_vop }, + { .compatible = "rockchip,rk3399-vop-big", + .data = &rk3399_vop_big }, + { .compatible = "rockchip,rk3399-vop-lit", + .data = &rk3399_vop_lit }, {}, }; MODULE_DEVICE_TABLE(of, vop_driver_dt_match); diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 43903e0..2cae529 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -166,4 +166,197 @@ #define RK3288_DSP_VACT_ST_END_F1 0x019c /* register definition end */ +/* rk3399 register definition */ +#define RK3399_REG_CFG_DONE 0x00000 +#define RK3399_VERSION_INFO 0x00004 +#define RK3399_SYS_CTRL 0x00008 +#define RK3399_SYS_CTRL1 0x0000c +#define RK3399_DSP_CTRL0 0x00010 +#define RK3399_DSP_CTRL1 0x00014 +#define RK3399_DSP_BG 0x00018 +#define RK3399_MCU_CTRL 0x0001c +#define RK3399_WB_CTRL0 0x00020 +#define RK3399_WB_CTRL1 0x00024 +#define RK3399_WB_YRGB_MST 0x00028 +#define RK3399_WB_CBR_MST 0x0002c +#define RK3399_WIN0_CTRL0 0x00030 +#define RK3399_WIN0_CTRL1 0x00034 +#define RK3399_WIN0_COLOR_KEY 0x00038 +#define RK3399_WIN0_VIR 0x0003c +#define RK3399_WIN0_YRGB_MST 0x00040 +#define RK3399_WIN0_CBR_MST 0x00044 +#define RK3399_WIN0_ACT_INFO 0x00048 +#define RK3399_WIN0_DSP_INFO 0x0004c +#define RK3399_WIN0_DSP_ST 0x00050 +#define RK3399_WIN0_SCL_FACTOR_YRGB 0x00054 +#define RK3399_WIN0_SCL_FACTOR_CBR 0x00058 +#define RK3399_WIN0_SCL_OFFSET 0x0005c +#define RK3399_WIN0_SRC_ALPHA_CTRL 0x00060 +#define RK3399_WIN0_DST_ALPHA_CTRL 0x00064 +#define RK3399_WIN0_FADING_CTRL 0x00068 +#define RK3399_WIN0_CTRL2 0x0006c +#define RK3399_WIN1_CTRL0 0x00070 +#define RK3399_WIN1_CTRL1 0x00074 +#define RK3399_WIN1_COLOR_KEY 0x00078 +#define RK3399_WIN1_VIR 0x0007c +#define RK3399_WIN1_YRGB_MST 0x00080 +#define RK3399_WIN1_CBR_MST 0x00084 +#define RK3399_WIN1_ACT_INFO 0x00088 +#define RK3399_WIN1_DSP_INFO 0x0008c +#define RK3399_WIN1_DSP_ST 0x00090 +#define RK3399_WIN1_SCL_FACTOR_YRGB 0x00094 +#define RK3399_WIN1_SCL_FACTOR_CBR 0x00098 +#define RK3399_WIN1_SCL_OFFSET 0x0009c +#define RK3399_WIN1_SRC_ALPHA_CTRL 0x000a0 +#define RK3399_WIN1_DST_ALPHA_CTRL 0x000a4 +#define RK3399_WIN1_FADING_CTRL 0x000a8 +#define RK3399_WIN1_CTRL2 0x000ac +#define RK3399_WIN2_CTRL0 0x000b0 +#define RK3399_WIN2_CTRL1 0x000b4 +#define RK3399_WIN2_VIR0_1 0x000b8 +#define RK3399_WIN2_VIR2_3 0x000bc +#define RK3399_WIN2_MST0 0x000c0 +#define RK3399_WIN2_DSP_INFO0 0x000c4 +#define RK3399_WIN2_DSP_ST0 0x000c8 +#define RK3399_WIN2_COLOR_KEY 0x000cc +#define RK3399_WIN2_MST1 0x000d0 +#define RK3399_WIN2_DSP_INFO1 0x000d4 +#define RK3399_WIN2_DSP_ST1 0x000d8 +#define RK3399_WIN2_SRC_ALPHA_CTRL 0x000dc +#define RK3399_WIN2_MST2 0x000e0 +#define RK3399_WIN2_DSP_INFO2 0x000e4 +#define RK3399_WIN2_DSP_ST2 0x000e8 +#define RK3399_WIN2_DST_ALPHA_CTRL 0x000ec +#define RK3399_WIN2_MST3 0x000f0 +#define RK3399_WIN2_DSP_INFO3 0x000f4 +#define RK3399_WIN2_DSP_ST3 0x000f8 +#define RK3399_WIN2_FADING_CTRL 0x000fc +#define RK3399_WIN3_CTRL0 0x00100 +#define RK3399_WIN3_CTRL1 0x00104 +#define RK3399_WIN3_VIR0_1 0x00108 +#define RK3399_WIN3_VIR2_3 0x0010c +#define RK3399_WIN3_MST0 0x00110 +#define RK3399_WIN3_DSP_INFO0 0x00114 +#define RK3399_WIN3_DSP_ST0 0x00118 +#define RK3399_WIN3_COLOR_KEY 0x0011c +#define RK3399_WIN3_MST1 0x00120 +#define RK3399_WIN3_DSP_INFO1 0x00124 +#define RK3399_WIN3_DSP_ST1 0x00128 +#define RK3399_WIN3_SRC_ALPHA_CTRL 0x0012c +#define RK3399_WIN3_MST2 0x00130 +#define RK3399_WIN3_DSP_INFO2 0x00134 +#define RK3399_WIN3_DSP_ST2 0x00138 +#define RK3399_WIN3_DST_ALPHA_CTRL 0x0013c +#define RK3399_WIN3_MST3 0x00140 +#define RK3399_WIN3_DSP_INFO3 0x00144 +#define RK3399_WIN3_DSP_ST3 0x00148 +#define RK3399_WIN3_FADING_CTRL 0x0014c +#define RK3399_HWC_CTRL0 0x00150 +#define RK3399_HWC_CTRL1 0x00154 +#define RK3399_HWC_MST 0x00158 +#define RK3399_HWC_DSP_ST 0x0015c +#define RK3399_HWC_SRC_ALPHA_CTRL 0x00160 +#define RK3399_HWC_DST_ALPHA_CTRL 0x00164 +#define RK3399_HWC_FADING_CTRL 0x00168 +#define RK3399_HWC_RESERVED1 0x0016c +#define RK3399_POST_DSP_HACT_INFO 0x00170 +#define RK3399_POST_DSP_VACT_INFO 0x00174 +#define RK3399_POST_SCL_FACTOR_YRGB 0x00178 +#define RK3399_POST_RESERVED 0x0017c +#define RK3399_POST_SCL_CTRL 0x00180 +#define RK3399_POST_DSP_VACT_INFO_F1 0x00184 +#define RK3399_DSP_HTOTAL_HS_END 0x00188 +#define RK3399_DSP_HACT_ST_END 0x0018c +#define RK3399_DSP_VTOTAL_VS_END 0x00190 +#define RK3399_DSP_VACT_ST_END 0x00194 +#define RK3399_DSP_VS_ST_END_F1 0x00198 +#define RK3399_DSP_VACT_ST_END_F1 0x0019c +#define RK3399_PWM_CTRL 0x001a0 +#define RK3399_PWM_PERIOD_HPR 0x001a4 +#define RK3399_PWM_DUTY_LPR 0x001a8 +#define RK3399_PWM_CNT 0x001ac +#define RK3399_BCSH_COLOR_BAR 0x001b0 +#define RK3399_BCSH_BCS 0x001b4 +#define RK3399_BCSH_H 0x001b8 +#define RK3399_BCSH_CTRL 0x001bc +#define RK3399_CABC_CTRL0 0x001c0 +#define RK3399_CABC_CTRL1 0x001c4 +#define RK3399_CABC_CTRL2 0x001c8 +#define RK3399_CABC_CTRL3 0x001cc +#define RK3399_CABC_GAUSS_LINE0_0 0x001d0 +#define RK3399_CABC_GAUSS_LINE0_1 0x001d4 +#define RK3399_CABC_GAUSS_LINE1_0 0x001d8 +#define RK3399_CABC_GAUSS_LINE1_1 0x001dc +#define RK3399_CABC_GAUSS_LINE2_0 0x001e0 +#define RK3399_CABC_GAUSS_LINE2_1 0x001e4 +#define RK3399_FRC_LOWER01_0 0x001e8 +#define RK3399_FRC_LOWER01_1 0x001ec +#define RK3399_FRC_LOWER10_0 0x001f0 +#define RK3399_FRC_LOWER10_1 0x001f4 +#define RK3399_FRC_LOWER11_0 0x001f8 +#define RK3399_FRC_LOWER11_1 0x001fc +#define RK3399_AFBCD0_CTRL 0x00200 +#define RK3399_AFBCD0_HDR_PTR 0x00204 +#define RK3399_AFBCD0_PIC_SIZE 0x00208 +#define RK3399_AFBCD0_STATUS 0x0020c +#define RK3399_AFBCD1_CTRL 0x00220 +#define RK3399_AFBCD1_HDR_PTR 0x00224 +#define RK3399_AFBCD1_PIC_SIZE 0x00228 +#define RK3399_AFBCD1_STATUS 0x0022c +#define RK3399_AFBCD2_CTRL 0x00240 +#define RK3399_AFBCD2_HDR_PTR 0x00244 +#define RK3399_AFBCD2_PIC_SIZE 0x00248 +#define RK3399_AFBCD2_STATUS 0x0024c +#define RK3399_AFBCD3_CTRL 0x00260 +#define RK3399_AFBCD3_HDR_PTR 0x00264 +#define RK3399_AFBCD3_PIC_SIZE 0x00268 +#define RK3399_AFBCD3_STATUS 0x0026c +#define RK3399_INTR_EN0 0x00280 +#define RK3399_INTR_CLEAR0 0x00284 +#define RK3399_INTR_STATUS0 0x00288 +#define RK3399_INTR_RAW_STATUS0 0x0028c +#define RK3399_INTR_EN1 0x00290 +#define RK3399_INTR_CLEAR1 0x00294 +#define RK3399_INTR_STATUS1 0x00298 +#define RK3399_INTR_RAW_STATUS1 0x0029c +#define RK3399_LINE_FLAG 0x002a0 +#define RK3399_VOP_STATUS 0x002a4 +#define RK3399_BLANKING_VALUE 0x002a8 +#define RK3399_MCU_BYPASS_PORT 0x002ac +#define RK3399_WIN0_DSP_BG 0x002b0 +#define RK3399_WIN1_DSP_BG 0x002b4 +#define RK3399_WIN2_DSP_BG 0x002b8 +#define RK3399_WIN3_DSP_BG 0x002bc +#define RK3399_YUV2YUV_WIN 0x002c0 +#define RK3399_YUV2YUV_POST 0x002c4 +#define RK3399_AUTO_GATING_EN 0x002cc +#define RK3399_WIN0_CSC_COE 0x003a0 +#define RK3399_WIN1_CSC_COE 0x003c0 +#define RK3399_WIN2_CSC_COE 0x003e0 +#define RK3399_WIN3_CSC_COE 0x00400 +#define RK3399_HWC_CSC_COE 0x00420 +#define RK3399_BCSH_R2Y_CSC_COE 0x00440 +#define RK3399_BCSH_Y2R_CSC_COE 0x00460 +#define RK3399_POST_YUV2YUV_Y2R_COE 0x00480 +#define RK3399_POST_YUV2YUV_3X3_COE 0x004a0 +#define RK3399_POST_YUV2YUV_R2Y_COE 0x004c0 +#define RK3399_WIN0_YUV2YUV_Y2R 0x004e0 +#define RK3399_WIN0_YUV2YUV_3X3 0x00500 +#define RK3399_WIN0_YUV2YUV_R2Y 0x00520 +#define RK3399_WIN1_YUV2YUV_Y2R 0x00540 +#define RK3399_WIN1_YUV2YUV_3X3 0x00560 +#define RK3399_WIN1_YUV2YUV_R2Y 0x00580 +#define RK3399_WIN2_YUV2YUV_Y2R 0x005a0 +#define RK3399_WIN2_YUV2YUV_3X3 0x005c0 +#define RK3399_WIN2_YUV2YUV_R2Y 0x005e0 +#define RK3399_WIN3_YUV2YUV_Y2R 0x00600 +#define RK3399_WIN3_YUV2YUV_3X3 0x00620 +#define RK3399_WIN3_YUV2YUV_R2Y 0x00640 +#define RK3399_WIN2_LUT_ADDR 0x01000 +#define RK3399_WIN3_LUT_ADDR 0x01400 +#define RK3399_HWC_LUT_ADDR 0x01800 +#define RK3399_CABC_GAMMA_LUT_ADDR 0x01c00 +#define RK3399_GAMMA_LUT_ADDR 0x02000 +/* rk3399 register definition end */ + #endif /* _ROCKCHIP_VOP_REG_H */ -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v2 4/5] drm/rockchip: vop: add rk3399 vop support 2016-04-20 6:18 ` Mark Yao (?) (?) @ 2016-06-02 7:27 ` Tomasz Figa -1 siblings, 0 replies; 71+ messages in thread From: Tomasz Figa @ 2016-06-02 7:27 UTC (permalink / raw) To: dri-devel Hi Mark, Mark Yao <mark.yao <at> rock-chips.com> writes: > > There are two VOP in rk3399 chip, respectively VOP_BIG and VOP_LIT. > most registers layout of this two vop is same, their framework are both > VOP_FULL, the Major differences of this two is that: Reviewed-by: Tomasz Figa <tfiga@chromium.org> Best regards, Tomasz _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v2 5/5] dt-bindings: add documentation for Rockchip rk3399 display controllers 2016-04-20 6:18 ` Mark Yao (?) @ 2016-04-20 6:20 ` Mark Yao -1 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:20 UTC (permalink / raw) To: David Airlie, Heiko Stuebner, dri-devel, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Mark Yao, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- .../bindings/display/rockchip/rockchip-vop.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 196121f..6bf8473 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -8,6 +8,11 @@ Required properties: - compatible: value should be one of the following "rockchip,rk3036-vop"; "rockchip,rk3288-vop"; + "rockchip,rk3399-vop-big"; + "rockchip,rk3399-vop-lit"; +Document compatible values for rk3399 display controllers. +Big and little display controllers are not identical and have differing +feature sets on the rk3399. - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 5/5] dt-bindings: add documentation for Rockchip rk3399 display controllers @ 2016-04-20 6:20 ` Mark Yao 0 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:20 UTC (permalink / raw) To: linux-arm-kernel Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- .../bindings/display/rockchip/rockchip-vop.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 196121f..6bf8473 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -8,6 +8,11 @@ Required properties: - compatible: value should be one of the following "rockchip,rk3036-vop"; "rockchip,rk3288-vop"; + "rockchip,rk3399-vop-big"; + "rockchip,rk3399-vop-lit"; +Document compatible values for rk3399 display controllers. +Big and little display controllers are not identical and have differing +feature sets on the rk3399. - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v2 5/5] dt-bindings: add documentation for Rockchip rk3399 display controllers @ 2016-04-20 6:20 ` Mark Yao 0 siblings, 0 replies; 71+ messages in thread From: Mark Yao @ 2016-04-20 6:20 UTC (permalink / raw) To: David Airlie, Heiko Stuebner, dri-devel, linux-arm-kernel, linux-rockchip, linux-kernel Cc: Mark Rutland, Pawel Moll, Ian Campbell, Rob Herring, Kumar Gala Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> --- .../bindings/display/rockchip/rockchip-vop.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 196121f..6bf8473 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -8,6 +8,11 @@ Required properties: - compatible: value should be one of the following "rockchip,rk3036-vop"; "rockchip,rk3288-vop"; + "rockchip,rk3399-vop-big"; + "rockchip,rk3399-vop-lit"; +Document compatible values for rk3399 display controllers. +Big and little display controllers are not identical and have differing +feature sets on the rk3399. - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 1.7.9.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v2 5/5] dt-bindings: add documentation for Rockchip rk3399 display controllers 2016-04-20 6:20 ` Mark Yao (?) (?) @ 2016-06-02 7:33 ` Tomasz Figa 2016-08-17 17:16 ` Sean Paul -1 siblings, 1 reply; 71+ messages in thread From: Tomasz Figa @ 2016-06-02 7:33 UTC (permalink / raw) To: dri-devel Hi Mark, Mark Yao <mark.yao <at> rock-chips.com> writes: > > Cc: Rob Herring <robh+dt <at> kernel.org> > Cc: Pawel Moll <pawel.moll <at> arm.com> > Cc: Mark Rutland <mark.rutland <at> arm.com> > Cc: Ian Campbell <ijc+devicetree <at> hellion.org.uk> > Cc: Kumar Gala <galak <at> codeaurora.org> > > Signed-off-by: Mark Yao <mark.yao <at> rock-chips.com> > --- > .../bindings/display/rockchip/rockchip-vop.txt | 5 +++++ > 1 file changed, 5 insertions(+) Please see my comment inline. > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip- vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip- vop.txt > index 196121f..6bf8473 100644 > --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt > <at> <at> -8,6 +8,11 <at> <at> Required properties: > - compatible: value should be one of the following > "rockchip,rk3036-vop"; > "rockchip,rk3288-vop"; > + "rockchip,rk3399-vop-big"; > + "rockchip,rk3399-vop-lit"; > +Document compatible values for rk3399 display controllers. > +Big and little display controllers are not identical and have differing > +feature sets on the rk3399. I think this doesn't really need any explanation. If two separate compatible strings are given, it means that the hardware is different. :) Other than that, Reviewed-by: Tomasz Figa <tfiga@chromium.org> Best regards, Tomasz _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 5/5] dt-bindings: add compatible strings for big/little rockchip vops 2016-06-02 7:33 ` Tomasz Figa 2016-08-17 17:16 ` Sean Paul @ 2016-08-17 17:16 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-17 17:16 UTC (permalink / raw) To: tfiga, dri-devel, mark.yao, robh Cc: linux-arm-kernel, linux-rockchip, linux-kernel, heiko, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Sean Paul From: Mark Yao <mark.yao@rock-chips.com> This patch documents the compatible strings for the big and little vop in rockchip's drm driver. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul removed superfluous description per tfiga's review] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Updated subject (Sean Paul) - Removed unnecessary description (Tomasz) Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 196121f..9eb3f0a 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -8,6 +8,8 @@ Required properties: - compatible: value should be one of the following "rockchip,rk3036-vop"; "rockchip,rk3288-vop"; + "rockchip,rk3399-vop-big"; + "rockchip,rk3399-vop-lit"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 5/5] dt-bindings: add compatible strings for big/little rockchip vops @ 2016-08-17 17:16 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-17 17:16 UTC (permalink / raw) To: linux-arm-kernel From: Mark Yao <mark.yao@rock-chips.com> This patch documents the compatible strings for the big and little vop in rockchip's drm driver. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul removed superfluous description per tfiga's review] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Updated subject (Sean Paul) - Removed unnecessary description (Tomasz) Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 196121f..9eb3f0a 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -8,6 +8,8 @@ Required properties: - compatible: value should be one of the following "rockchip,rk3036-vop"; "rockchip,rk3288-vop"; + "rockchip,rk3399-vop-big"; + "rockchip,rk3399-vop-lit"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 5/5] dt-bindings: add compatible strings for big/little rockchip vops @ 2016-08-17 17:16 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-17 17:16 UTC (permalink / raw) To: tfiga, dri-devel, mark.yao, robh Cc: Mark Rutland, Pawel Moll, Ian Campbell, linux-kernel, linux-rockchip, Rob Herring, Kumar Gala, linux-arm-kernel From: Mark Yao <mark.yao@rock-chips.com> This patch documents the compatible strings for the big and little vop in rockchip's drm driver. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul removed superfluous description per tfiga's review] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Changes in v3: - Updated subject (Sean Paul) - Removed unnecessary description (Tomasz) Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 196121f..9eb3f0a 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -8,6 +8,8 @@ Required properties: - compatible: value should be one of the following "rockchip,rk3036-vop"; "rockchip,rk3288-vop"; + "rockchip,rk3399-vop-big"; + "rockchip,rk3399-vop-lit"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 2.8.0.rc3.226.g39d4020 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 71+ messages in thread
[parent not found: <0001-<1471454202-1631-1-git-send-email-seanpaul@chromium.org>]
* [PATCH v3 5/5] dt-bindings: add compatible strings for big/little rockchip vops [not found] <0001-<1471454202-1631-1-git-send-email-seanpaul@chromium.org> 2016-08-18 21:12 ` Sean Paul @ 2016-08-18 21:12 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-18 21:12 UTC (permalink / raw) To: devicetree, tfiga, dri-devel, mark.yao, robh Cc: linux-arm-kernel, linux-rockchip, linux-kernel, heiko, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, Sean Paul From: Mark Yao <mark.yao@rock-chips.com> This patch documents the compatible strings for the big and little vop in rockchip's drm driver. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul removed superfluous description per tfiga's review] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Resending to add devicetree list Changes in v3: - Updated subject (Sean Paul) - Removed unnecessary description (Tomasz) Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 196121f..9eb3f0a 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -8,6 +8,8 @@ Required properties: - compatible: value should be one of the following "rockchip,rk3036-vop"; "rockchip,rk3288-vop"; + "rockchip,rk3399-vop-big"; + "rockchip,rk3399-vop-lit"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 5/5] dt-bindings: add compatible strings for big/little rockchip vops @ 2016-08-18 21:12 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-18 21:12 UTC (permalink / raw) To: linux-arm-kernel From: Mark Yao <mark.yao@rock-chips.com> This patch documents the compatible strings for the big and little vop in rockchip's drm driver. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul removed superfluous description per tfiga's review] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Resending to add devicetree list Changes in v3: - Updated subject (Sean Paul) - Removed unnecessary description (Tomasz) Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 196121f..9eb3f0a 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -8,6 +8,8 @@ Required properties: - compatible: value should be one of the following "rockchip,rk3036-vop"; "rockchip,rk3288-vop"; + "rockchip,rk3399-vop-big"; + "rockchip,rk3399-vop-lit"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v3 5/5] dt-bindings: add compatible strings for big/little rockchip vops @ 2016-08-18 21:12 ` Sean Paul 0 siblings, 0 replies; 71+ messages in thread From: Sean Paul @ 2016-08-18 21:12 UTC (permalink / raw) To: devicetree, tfiga, dri-devel, mark.yao, robh Cc: Mark Rutland, Pawel Moll, Ian Campbell, linux-kernel, linux-rockchip, Rob Herring, Kumar Gala, linux-arm-kernel From: Mark Yao <mark.yao@rock-chips.com> This patch documents the compatible strings for the big and little vop in rockchip's drm driver. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> [seanpaul removed superfluous description per tfiga's review] Signed-off-by: Sean Paul <seanpaul@chromium.org> --- Resending to add devicetree list Changes in v3: - Updated subject (Sean Paul) - Removed unnecessary description (Tomasz) Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 196121f..9eb3f0a 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -8,6 +8,8 @@ Required properties: - compatible: value should be one of the following "rockchip,rk3036-vop"; "rockchip,rk3288-vop"; + "rockchip,rk3399-vop-big"; + "rockchip,rk3399-vop-lit"; - interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier -- 2.8.0.rc3.226.g39d4020 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v3 5/5] dt-bindings: add compatible strings for big/little rockchip vops @ 2016-08-19 13:50 ` Rob Herring 0 siblings, 0 replies; 71+ messages in thread From: Rob Herring @ 2016-08-19 13:50 UTC (permalink / raw) To: Sean Paul Cc: devicetree, tfiga, dri-devel, mark.yao, linux-arm-kernel, linux-rockchip, linux-kernel, heiko, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala On Thu, Aug 18, 2016 at 02:12:43PM -0700, Sean Paul wrote: > From: Mark Yao <mark.yao@rock-chips.com> > > This patch documents the compatible strings for the big and little vop > in rockchip's drm driver. > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Pawel Moll <pawel.moll@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> > Cc: Kumar Gala <galak@codeaurora.org> > > Reviewed-by: Tomasz Figa <tfiga@chromium.org> > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > [seanpaul removed superfluous description per tfiga's review] > Signed-off-by: Sean Paul <seanpaul@chromium.org> > --- > > Resending to add devicetree list > > Changes in v3: > - Updated subject (Sean Paul) > - Removed unnecessary description (Tomasz) > > Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 ++ > 1 file changed, 2 insertions(+) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v3 5/5] dt-bindings: add compatible strings for big/little rockchip vops @ 2016-08-19 13:50 ` Rob Herring 0 siblings, 0 replies; 71+ messages in thread From: Rob Herring @ 2016-08-19 13:50 UTC (permalink / raw) To: linux-arm-kernel On Thu, Aug 18, 2016 at 02:12:43PM -0700, Sean Paul wrote: > From: Mark Yao <mark.yao@rock-chips.com> > > This patch documents the compatible strings for the big and little vop > in rockchip's drm driver. > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Pawel Moll <pawel.moll@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> > Cc: Kumar Gala <galak@codeaurora.org> > > Reviewed-by: Tomasz Figa <tfiga@chromium.org> > Signed-off-by: Mark Yao <mark.yao@rock-chips.com> > [seanpaul removed superfluous description per tfiga's review] > Signed-off-by: Sean Paul <seanpaul@chromium.org> > --- > > Resending to add devicetree list > > Changes in v3: > - Updated subject (Sean Paul) > - Removed unnecessary description (Tomasz) > > Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 ++ > 1 file changed, 2 insertions(+) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v3 5/5] dt-bindings: add compatible strings for big/little rockchip vops @ 2016-08-19 13:50 ` Rob Herring 0 siblings, 0 replies; 71+ messages in thread From: Rob Herring @ 2016-08-19 13:50 UTC (permalink / raw) To: Sean Paul Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, tfiga-F7+t8E8rja9g9hUCZPvPmw, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, mark.yao-TNX95d0MmH7DzftRWevZcw, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, heiko-4mtYJXux2i+zQB+pC5nmwQ, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala On Thu, Aug 18, 2016 at 02:12:43PM -0700, Sean Paul wrote: > From: Mark Yao <mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > > This patch documents the compatible strings for the big and little vop > in rockchip's drm driver. > > Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> > Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> > Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> > Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> > Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> > > Reviewed-by: Tomasz Figa <tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> > Signed-off-by: Mark Yao <mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > [seanpaul removed superfluous description per tfiga's review] > Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> > --- > > Resending to add devicetree list > > Changes in v3: > - Updated subject (Sean Paul) > - Removed unnecessary description (Tomasz) > > Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 2 ++ > 1 file changed, 2 insertions(+) Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 71+ messages in thread
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Thread overview: 71+ messages (download: mbox.gz / follow: Atom feed)
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2016-04-20 6:18 [PATCH v2 0/5] drm/rockchip: add rk3399 display controller support Mark Yao
2016-04-20 6:18 ` Mark Yao
2016-04-20 6:18 ` Mark Yao
2016-04-20 6:18 ` [PATCH v2 1/5] drm/rockchip: sort registers define by chip's number Mark Yao
2016-04-20 6:18 ` Mark Yao
2016-04-20 6:18 ` Mark Yao
2016-06-02 6:51 ` Tomasz Figa
2016-06-02 7:05 ` Mark yao
2016-08-17 17:20 ` [PATCH v3 " Sean Paul
2016-08-17 17:20 ` Sean Paul
2016-08-17 17:20 ` Sean Paul
2016-08-18 9:08 ` Mark yao
2016-08-18 9:08 ` Mark yao
2016-08-18 9:08 ` Mark yao
2016-08-18 9:11 ` Daniel Vetter
2016-08-18 9:11 ` Daniel Vetter
2016-08-18 9:11 ` Daniel Vetter
2016-08-18 10:02 ` Mark yao
2016-08-18 10:02 ` Mark yao
2016-08-18 10:02 ` Mark yao
2016-08-22 20:30 ` Sean Paul
2016-08-22 20:30 ` Sean Paul
2016-08-22 20:30 ` Sean Paul
2016-08-23 0:40 ` Mark yao
2016-08-23 0:40 ` Mark yao
2016-08-23 13:13 ` Sean Paul
2016-08-23 13:13 ` Sean Paul
2016-08-23 13:13 ` Sean Paul
2016-08-25 2:25 ` Mark yao
2016-08-25 2:25 ` Mark yao
2016-08-25 2:25 ` Mark yao
2016-08-25 17:15 ` Sean Paul
2016-08-25 17:17 ` Sean Paul
2016-08-25 17:17 ` Sean Paul
2016-08-25 17:17 ` Sean Paul
2016-04-20 6:18 ` [PATCH v2 2/5] dt-bindings: sort Rockchip vop compatible " Mark Yao
2016-04-20 6:18 ` Mark Yao
2016-06-02 6:56 ` Tomasz Figa
2016-08-17 17:11 ` [PATCH v3 " Sean Paul
2016-08-17 17:11 ` Sean Paul
2016-08-17 17:11 ` Sean Paul
2016-08-18 21:15 ` Sean Paul
2016-08-18 21:15 ` Sean Paul
2016-08-18 21:15 ` Sean Paul
2016-08-19 13:51 ` Rob Herring
2016-08-19 13:51 ` Rob Herring
2016-08-19 13:51 ` Rob Herring
2016-04-20 6:18 ` [PATCH v2 3/5] drm/rockchip: vop: introduce VOP_REG_MASK Mark Yao
2016-04-20 6:18 ` Mark Yao
2016-04-20 6:18 ` Mark Yao
2016-06-02 7:19 ` Tomasz Figa
2016-08-17 17:23 ` [PATCH v3 " Sean Paul
2016-08-17 17:23 ` Sean Paul
2016-08-17 17:23 ` Sean Paul
2016-04-20 6:18 ` [PATCH v2 4/5] drm/rockchip: vop: add rk3399 vop support Mark Yao
2016-04-20 6:18 ` Mark Yao
2016-04-20 6:18 ` Mark Yao
2016-06-02 7:27 ` Tomasz Figa
2016-04-20 6:20 ` [PATCH v2 5/5] dt-bindings: add documentation for Rockchip rk3399 display controllers Mark Yao
2016-04-20 6:20 ` Mark Yao
2016-04-20 6:20 ` Mark Yao
2016-06-02 7:33 ` Tomasz Figa
2016-08-17 17:16 ` [PATCH v3 5/5] dt-bindings: add compatible strings for big/little rockchip vops Sean Paul
2016-08-17 17:16 ` Sean Paul
2016-08-17 17:16 ` Sean Paul
[not found] <0001-<1471454202-1631-1-git-send-email-seanpaul@chromium.org>
2016-08-18 21:12 ` Sean Paul
2016-08-18 21:12 ` Sean Paul
2016-08-18 21:12 ` Sean Paul
2016-08-19 13:50 ` Rob Herring
2016-08-19 13:50 ` Rob Herring
2016-08-19 13:50 ` Rob Herring
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