Re: [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago board

[Takashi Iwai <tiwai@suse.de>]

On Fri, 31 Jul 2020 14:26:05 +0200,
Brent Lu wrote:
> 
> From: Yu-Hsuan Hsu <yuhsuan@chromium.org>
> 
> The CRAS server does not set the period size in hw_param so ALSA will
> calculate a value for period size which is based on the buffer size
> and other parameters. The value may not always be aligned with Atom's
> dsp design so a constraint is added to make sure the board always has
> a good value.
> 
> Cyan uses chtmax98090 and others(banon, celes, edgar, kefka...) use
> rt5650.
> 
> Signed-off-by: Yu-Hsuan Hsu <yuhsuan@chromium.org>
> Signed-off-by: Brent Lu <brent.lu@intel.com>
> ---
>  sound/soc/intel/boards/cht_bsw_max98090_ti.c | 14 +++++++++++++-
>  sound/soc/intel/boards/cht_bsw_rt5645.c      | 14 +++++++++++++-
>  2 files changed, 26 insertions(+), 2 deletions(-)
> 
> diff --git a/sound/soc/intel/boards/cht_bsw_max98090_ti.c b/sound/soc/intel/boards/cht_bsw_max98090_ti.c
> index 835e9bd..bf67254 100644
> --- a/sound/soc/intel/boards/cht_bsw_max98090_ti.c
> +++ b/sound/soc/intel/boards/cht_bsw_max98090_ti.c
> @@ -283,8 +283,20 @@ static int cht_codec_fixup(struct snd_soc_pcm_runtime *rtd,
>  
>  static int cht_aif1_startup(struct snd_pcm_substream *substream)
>  {
> -	return snd_pcm_hw_constraint_single(substream->runtime,
> +	int err;
> +
> +	/* Set period size to 240 to align with Atom design */
> +	err = snd_pcm_hw_constraint_minmax(substream->runtime,
> +			SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 240, 240);
> +	if (err < 0)
> +		return err;

Again, is this fixed 240 is a must?  Or is this also an alignment
issue?


thanks,

Takashi