From: Takashi Iwai <tiwai@suse.de> To: Yu-Hsuan Hsu <yuhsuan@chromium.org> Cc: Mark Brown <broonie@kernel.org>, Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>, Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>, "alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>, Kai Vehmanen <kai.vehmanen@linux.intel.com>, Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>, "Rojewski, Cezary" <cezary.rojewski@intel.com>, Takashi Iwai <tiwai@suse.com>, Jie Yang <yang.jie@linux.intel.com>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Liam Girdwood <liam.r.girdwood@linux.intel.com>, Sam McNally <sammc@chromium.org>, "yuhsuan@google.com" <yuhsuan@google.com>, Ranjani Sridharan <ranjani.sridharan@linux.intel.com>, Daniel Stuart <daniel.stuart14@gmail.com>, Andy Shevchenko <andriy.shevchenko@linux.intel.com>, "Lu, Brent" <brent.lu@intel.com>, Damian van Soelen <dj.vsoelen@gmail.com> Subject: Re: [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago board Date: Wed, 12 Aug 2020 08:13:59 +0200 [thread overview] Message-ID: <s5hr1scz908.wl-tiwai@suse.de> (raw) In-Reply-To: <CAGvk5PqGi7cXthLHFi4NyypxFiGnoHvD9vp+5nJdH-_VkVvcKw@mail.gmail.com> On Wed, 12 Aug 2020 05:09:58 +0200, Yu-Hsuan Hsu wrote: > > Mark Brown <broonie@kernel.org> 於 2020年8月12日 週三 上午1:22寫道: > > > > On Tue, Aug 11, 2020 at 11:54:38AM -0500, Pierre-Louis Bossart wrote: > > > > > > constraint logic needs to know about this DSP limitation - it seems like > > > > none of this is going to change without something new going into the > > > > mix? We at least need a new question to ask about the DSP firmware I > > > > think. > > > > > I just tested aplay -Dhw: on a Cyan Chromebook with the Ubuntu kernel 5.4, > > > and I see no issues with the 240 sample period. Same with 432, 960, 9600, > > > etc. > > > > > I also tried just for fun what happens with 256 samples, and I don't see any > > > underflows thrown either, so I am wondering what exactly the problem is? > > > Something's not adding up. I would definitively favor multiple of 1ms > > > periods, since it's the only case that was productized, but there's got to > > > me something a side effect of how CRAS programs the hw_params. > > > > Is it something that goes wrong with longer playbacks possibly (eg, > > someone watching a feature film or something)? > > Thanks for testing! > > After doing some experiments, I think I can identify the problem more precisely. > 1. aplay can not reproduce this issue because it writes samples > immediately when there are some space in the buffer. However, you can > add --test-position to see how the delay grows with period size 256. > > aplay -Dhw:1,0 --period-size=256 --buffer-size=480 /dev/zero -d 1 -f dat --test-position > Playing raw data '/dev/zero' : Signed 16 bit Little Endian, Rate 48000 > Hz, Stereo > Suspicious buffer position (1 total): avail = 0, delay = 2064, buffer = 512 > Suspicious buffer position (2 total): avail = 0, delay = 2064, buffer = 512 > Suspicious buffer position (3 total): avail = 0, delay = 2096, buffer = 512 > ... Isn't this about the alignment of the buffer size against the period size, not the period size itself? i.e. in the example above, the buffer size isn't a multiple of period size, and DSP can't handle if the position overlaps the buffer size in a half way. If that's the problem (and it's an oft-seen restriction), the right constraint is snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); Takashi > 2. Since many samples are moved to DSP(delay), the measured rate of > the ring-buffer is high. (I measured it by alsa_conformance_test, > which only test the sampling rate in the ring buffer of kernel not > DSP) > > 3. Since CRAS writes samples with a fixed frequency, this behavior > will take all samples from the ring buffer, which is seen as underrun > by CRAS. (It seems that it is not a real underrun because that avail > does not larger than buffer size. Maybe CRAS should also take dalay > into account.) > > 4. In spite of it is not a real underrun, the large delay is still a > big problem. Can we apply the constraint to fix it? Or any better > idea? > > Thanks, > Yu-Hsuan >
WARNING: multiple messages have this Message-ID (diff)
From: Takashi Iwai <tiwai@suse.de> To: Yu-Hsuan Hsu <yuhsuan@chromium.org> Cc: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>, "alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>, Andy Shevchenko <andriy.shevchenko@linux.intel.com>, Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>, Kai Vehmanen <kai.vehmanen@linux.intel.com>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "Rojewski, Cezary" <cezary.rojewski@intel.com>, Jie Yang <yang.jie@linux.intel.com>, Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>, Takashi Iwai <tiwai@suse.com>, Liam Girdwood <liam.r.girdwood@linux.intel.com>, Sam McNally <sammc@chromium.org>, Mark Brown <broonie@kernel.org>, Ranjani Sridharan <ranjani.sridharan@linux.intel.com>, Daniel Stuart <daniel.stuart14@gmail.com>, "yuhsuan@google.com" <yuhsuan@google.com>, "Lu, Brent" <brent.lu@intel.com>, Damian van Soelen <dj.vsoelen@gmail.com> Subject: Re: [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago board Date: Wed, 12 Aug 2020 08:13:59 +0200 [thread overview] Message-ID: <s5hr1scz908.wl-tiwai@suse.de> (raw) In-Reply-To: <CAGvk5PqGi7cXthLHFi4NyypxFiGnoHvD9vp+5nJdH-_VkVvcKw@mail.gmail.com> On Wed, 12 Aug 2020 05:09:58 +0200, Yu-Hsuan Hsu wrote: > > Mark Brown <broonie@kernel.org> 於 2020年8月12日 週三 上午1:22寫道: > > > > On Tue, Aug 11, 2020 at 11:54:38AM -0500, Pierre-Louis Bossart wrote: > > > > > > constraint logic needs to know about this DSP limitation - it seems like > > > > none of this is going to change without something new going into the > > > > mix? We at least need a new question to ask about the DSP firmware I > > > > think. > > > > > I just tested aplay -Dhw: on a Cyan Chromebook with the Ubuntu kernel 5.4, > > > and I see no issues with the 240 sample period. Same with 432, 960, 9600, > > > etc. > > > > > I also tried just for fun what happens with 256 samples, and I don't see any > > > underflows thrown either, so I am wondering what exactly the problem is? > > > Something's not adding up. I would definitively favor multiple of 1ms > > > periods, since it's the only case that was productized, but there's got to > > > me something a side effect of how CRAS programs the hw_params. > > > > Is it something that goes wrong with longer playbacks possibly (eg, > > someone watching a feature film or something)? > > Thanks for testing! > > After doing some experiments, I think I can identify the problem more precisely. > 1. aplay can not reproduce this issue because it writes samples > immediately when there are some space in the buffer. However, you can > add --test-position to see how the delay grows with period size 256. > > aplay -Dhw:1,0 --period-size=256 --buffer-size=480 /dev/zero -d 1 -f dat --test-position > Playing raw data '/dev/zero' : Signed 16 bit Little Endian, Rate 48000 > Hz, Stereo > Suspicious buffer position (1 total): avail = 0, delay = 2064, buffer = 512 > Suspicious buffer position (2 total): avail = 0, delay = 2064, buffer = 512 > Suspicious buffer position (3 total): avail = 0, delay = 2096, buffer = 512 > ... Isn't this about the alignment of the buffer size against the period size, not the period size itself? i.e. in the example above, the buffer size isn't a multiple of period size, and DSP can't handle if the position overlaps the buffer size in a half way. If that's the problem (and it's an oft-seen restriction), the right constraint is snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); Takashi > 2. Since many samples are moved to DSP(delay), the measured rate of > the ring-buffer is high. (I measured it by alsa_conformance_test, > which only test the sampling rate in the ring buffer of kernel not > DSP) > > 3. Since CRAS writes samples with a fixed frequency, this behavior > will take all samples from the ring buffer, which is seen as underrun > by CRAS. (It seems that it is not a real underrun because that avail > does not larger than buffer size. Maybe CRAS should also take dalay > into account.) > > 4. In spite of it is not a real underrun, the large delay is still a > big problem. Can we apply the constraint to fix it? Or any better > idea? > > Thanks, > Yu-Hsuan >
next prev parent reply other threads:[~2020-08-12 6:14 UTC|newest] Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-29 11:03 [PATCH 0/2] Add period size constraint for Atom Chromebook Brent Lu 2020-07-29 11:03 ` Brent Lu 2020-07-29 11:03 ` [PATCH 1/2] ASoC: intel: atom: Add period size constraint Brent Lu 2020-07-29 11:03 ` Brent Lu 2020-07-29 11:19 ` Andy Shevchenko 2020-07-29 11:19 ` Andy Shevchenko 2020-07-29 11:03 ` [PATCH 2/2] ASoC: Intel: Add period size constraint on strago board Brent Lu 2020-07-29 11:03 ` Brent Lu 2020-07-29 14:08 ` Pierre-Louis Bossart 2020-07-29 14:08 ` Pierre-Louis Bossart 2020-07-30 8:02 ` Lu, Brent 2020-07-30 8:02 ` Lu, Brent 2020-07-30 15:27 ` Pierre-Louis Bossart 2020-07-30 15:44 ` Pierre-Louis Bossart 2020-07-30 16:17 ` Lu, Brent 2020-07-30 16:17 ` Lu, Brent 2020-07-30 16:56 ` Takashi Iwai 2020-07-30 16:56 ` Takashi Iwai 2020-07-31 12:28 ` Lu, Brent 2020-07-31 12:28 ` Lu, Brent 2020-07-29 11:20 ` [PATCH 0/2] Add period size constraint for Atom Chromebook Andy Shevchenko 2020-07-29 11:20 ` Andy Shevchenko 2020-07-31 12:26 ` [PATCH v3 " Brent Lu 2020-07-31 12:26 ` Brent Lu 2020-07-31 12:26 ` [PATCH v3 1/2] ASoC: intel: atom: Add period size constraint Brent Lu 2020-07-31 12:26 ` Brent Lu 2020-07-31 12:26 ` [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago board Brent Lu 2020-07-31 12:26 ` Brent Lu 2020-07-31 13:34 ` Takashi Iwai 2020-07-31 13:34 ` Takashi Iwai 2020-08-01 8:58 ` Lu, Brent 2020-08-01 8:58 ` Lu, Brent 2020-08-01 9:26 ` Takashi Iwai 2020-08-01 9:26 ` Takashi Iwai 2020-08-03 13:00 ` Lu, Brent 2020-08-03 13:00 ` Lu, Brent 2020-08-03 15:13 ` Pierre-Louis Bossart 2020-08-03 15:13 ` Pierre-Louis Bossart 2020-08-03 16:45 ` Lu, Brent 2020-08-03 16:45 ` Lu, Brent 2020-08-03 16:56 ` Takashi Iwai 2020-08-03 16:56 ` Takashi Iwai 2020-08-04 4:33 ` Lu, Brent 2020-08-04 4:33 ` Lu, Brent 2020-08-04 14:24 ` Pierre-Louis Bossart 2020-08-04 14:24 ` Pierre-Louis Bossart 2020-08-06 16:41 ` Lu, Brent 2020-08-06 16:41 ` Lu, Brent 2020-08-10 15:03 ` Pierre-Louis Bossart 2020-08-10 15:03 ` Pierre-Louis Bossart 2020-08-10 17:38 ` Yu-Hsuan Hsu 2020-08-10 17:38 ` Yu-Hsuan Hsu 2020-08-11 2:16 ` Lu, Brent 2020-08-11 2:16 ` Lu, Brent 2020-08-11 2:29 ` Yu-Hsuan Hsu 2020-08-11 2:29 ` Yu-Hsuan Hsu 2020-08-11 7:43 ` Takashi Iwai 2020-08-11 7:43 ` Takashi Iwai 2020-08-11 8:25 ` Yu-Hsuan Hsu 2020-08-11 8:25 ` Yu-Hsuan Hsu 2020-08-11 8:39 ` Takashi Iwai 2020-08-11 8:39 ` Takashi Iwai 2020-08-11 9:35 ` Yu-Hsuan Hsu 2020-08-11 9:35 ` Yu-Hsuan Hsu 2020-08-11 14:53 ` Mark Brown 2020-08-11 14:53 ` Mark Brown 2020-08-11 16:54 ` Pierre-Louis Bossart 2020-08-11 16:54 ` Pierre-Louis Bossart 2020-08-11 17:22 ` Mark Brown 2020-08-11 17:22 ` Mark Brown 2020-08-12 3:09 ` Yu-Hsuan Hsu 2020-08-12 3:09 ` Yu-Hsuan Hsu 2020-08-12 6:13 ` Takashi Iwai [this message] 2020-08-12 6:13 ` Takashi Iwai 2020-08-12 6:53 ` Yu-Hsuan Hsu 2020-08-12 6:53 ` Yu-Hsuan Hsu 2020-08-12 6:58 ` Takashi Iwai 2020-08-12 6:58 ` Takashi Iwai 2020-08-12 7:43 ` Yu-Hsuan Hsu 2020-08-12 7:43 ` Yu-Hsuan Hsu 2020-08-12 7:47 ` Takashi Iwai 2020-08-12 7:47 ` Takashi Iwai 2020-08-12 14:46 ` Pierre-Louis Bossart 2020-08-12 14:46 ` Pierre-Louis Bossart 2020-08-12 14:55 ` Takashi Iwai 2020-08-12 14:55 ` Takashi Iwai 2020-08-12 15:54 ` Pierre-Louis Bossart 2020-08-12 15:54 ` Pierre-Louis Bossart 2020-08-12 16:08 ` Lu, Brent 2020-08-12 16:08 ` Lu, Brent 2020-08-12 16:38 ` Pierre-Louis Bossart 2020-08-12 16:38 ` Pierre-Louis Bossart 2020-08-13 6:24 ` Yu-Hsuan Hsu 2020-08-13 6:24 ` Yu-Hsuan Hsu 2020-08-13 7:55 ` Lu, Brent 2020-08-13 7:55 ` Lu, Brent 2020-08-13 8:36 ` Yu-Hsuan Hsu 2020-08-13 8:36 ` Yu-Hsuan Hsu 2020-08-13 8:45 ` Takashi Iwai 2020-08-13 8:45 ` Takashi Iwai 2020-08-13 12:57 ` Pierre-Louis Bossart 2020-08-13 12:57 ` Pierre-Louis Bossart 2020-08-13 17:15 ` Yu-Hsuan Hsu 2020-08-13 17:15 ` Yu-Hsuan Hsu 2020-08-21 16:40 ` [PATCH v3 0/2] Add period size constraint for Atom Chromebook Mark Brown 2020-08-21 16:40 ` Mark Brown
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