From: Hal Feng <hal.feng@starfivetech.com> To: Conor Dooley <conor@kernel.org> Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, Rob Herring <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, "Thomas Gleixner" <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, "Philipp Zabel" <p.zabel@pengutronix.de>, Linus Walleij <linus.walleij@linaro.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree Date: Wed, 1 Feb 2023 15:21:48 +0800 [thread overview] Message-ID: <c507e0b2-5ca3-cffe-55d2-873ed8c24e3d@starfivetech.com> (raw) In-Reply-To: <Y6zHy9oL4xzl+6Rd@spud> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote: > Hey, > > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote: >> From: Emil Renner Berthing <kernel@esmil.dk> >> >> Add initial device tree for the JH7110 RISC-V SoC by StarFive >> Technology Ltd. >> >> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> >> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> >> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> >> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> >> --- >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++ >> 1 file changed, 411 insertions(+) >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> new file mode 100644 >> index 000000000000..64d260ea1f29 >> --- /dev/null >> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> @@ -0,0 +1,411 @@ >> +// SPDX-License-Identifier: GPL-2.0 OR MIT >> +/* >> + * Copyright (C) 2022 StarFive Technology Co., Ltd. >> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> >> + */ >> + >> +/dts-v1/; >> +#include <dt-bindings/clock/starfive,jh7110-crg.h> >> +#include <dt-bindings/reset/starfive,jh7110-crg.h> >> + >> +/ { >> + compatible = "starfive,jh7110"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + S76_0: cpu@0 { >> + compatible = "sifive,u74-mc", "riscv"; > > The label here says S76 but the compatible says u74-mc. U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores. > Which is correct? Your docs say S7 and S76, so I would imagine that it > is actually an S76? I found SiFive website [1] call it S76, but call it S7 in other places. So I misunderstood this. Considering the ISA difference you described as below, I think it's proper to change the label to "S7_0". [1] https://www.sifive.com/cores/essential > >> + reg = <0>; >> + d-cache-block-size = <64>; >> + d-cache-sets = <64>; >> + d-cache-size = <8192>; >> + d-tlb-sets = <1>; >> + d-tlb-size = <40>; >> + device_type = "cpu"; >> + i-cache-block-size = <64>; >> + i-cache-sets = <64>; >> + i-cache-size = <16384>; >> + i-tlb-sets = <1>; >> + i-tlb-size = <40>; >> + mmu-type = "riscv,sv39"; >> + next-level-cache = <&ccache>; >> + riscv,isa = "rv64imac"; > > While I was poking around trying to see if there was some logic behind > that compatible, I noticed that SiFive's docs for the S76 say it is > RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC". > I assume that rv64imac is the correct one here? Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a S7-series core, not S76. > >> + tlb-split; >> + status = "disabled"; >> + >> + cpu0_intc: interrupt-controller { >> + compatible = "riscv,cpu-intc"; >> + interrupt-controller; >> + #interrupt-cells = <1>; >> + }; >> + }; >> + >> + U74_1: cpu@1 { >> + compatible = "sifive,u74-mc", "riscv"; >> + reg = <1>; >> + d-cache-block-size = <64>; >> + d-cache-sets = <64>; >> + d-cache-size = <32768>; >> + d-tlb-sets = <1>; >> + d-tlb-size = <40>; >> + device_type = "cpu"; >> + i-cache-block-size = <64>; >> + i-cache-sets = <64>; >> + i-cache-size = <32768>; >> + i-tlb-sets = <1>; >> + i-tlb-size = <40>; >> + mmu-type = "riscv,sv39"; >> + next-level-cache = <&ccache>; >> + riscv,isa = "rv64imafdc"; > > That also begs the question: > Do your u74s support RV64GBC, as the (current) SiFive documentation > suggests? Actually, U74 doesn't support the full B extension, and the SiFive doc [1] describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes "IMAFD". "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here. [1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf Best regards, Hal
WARNING: multiple messages have this Message-ID (diff)
From: Hal Feng <hal.feng@starfivetech.com> To: Conor Dooley <conor@kernel.org> Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, Rob Herring <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, "Thomas Gleixner" <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, "Philipp Zabel" <p.zabel@pengutronix.de>, Linus Walleij <linus.walleij@linaro.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree Date: Wed, 1 Feb 2023 15:21:48 +0800 [thread overview] Message-ID: <c507e0b2-5ca3-cffe-55d2-873ed8c24e3d@starfivetech.com> (raw) In-Reply-To: <Y6zHy9oL4xzl+6Rd@spud> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote: > Hey, > > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote: >> From: Emil Renner Berthing <kernel@esmil.dk> >> >> Add initial device tree for the JH7110 RISC-V SoC by StarFive >> Technology Ltd. >> >> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> >> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> >> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> >> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> >> --- >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++ >> 1 file changed, 411 insertions(+) >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> new file mode 100644 >> index 000000000000..64d260ea1f29 >> --- /dev/null >> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> @@ -0,0 +1,411 @@ >> +// SPDX-License-Identifier: GPL-2.0 OR MIT >> +/* >> + * Copyright (C) 2022 StarFive Technology Co., Ltd. >> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> >> + */ >> + >> +/dts-v1/; >> +#include <dt-bindings/clock/starfive,jh7110-crg.h> >> +#include <dt-bindings/reset/starfive,jh7110-crg.h> >> + >> +/ { >> + compatible = "starfive,jh7110"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + S76_0: cpu@0 { >> + compatible = "sifive,u74-mc", "riscv"; > > The label here says S76 but the compatible says u74-mc. U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores. > Which is correct? Your docs say S7 and S76, so I would imagine that it > is actually an S76? I found SiFive website [1] call it S76, but call it S7 in other places. So I misunderstood this. Considering the ISA difference you described as below, I think it's proper to change the label to "S7_0". [1] https://www.sifive.com/cores/essential > >> + reg = <0>; >> + d-cache-block-size = <64>; >> + d-cache-sets = <64>; >> + d-cache-size = <8192>; >> + d-tlb-sets = <1>; >> + d-tlb-size = <40>; >> + device_type = "cpu"; >> + i-cache-block-size = <64>; >> + i-cache-sets = <64>; >> + i-cache-size = <16384>; >> + i-tlb-sets = <1>; >> + i-tlb-size = <40>; >> + mmu-type = "riscv,sv39"; >> + next-level-cache = <&ccache>; >> + riscv,isa = "rv64imac"; > > While I was poking around trying to see if there was some logic behind > that compatible, I noticed that SiFive's docs for the S76 say it is > RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC". > I assume that rv64imac is the correct one here? Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a S7-series core, not S76. > >> + tlb-split; >> + status = "disabled"; >> + >> + cpu0_intc: interrupt-controller { >> + compatible = "riscv,cpu-intc"; >> + interrupt-controller; >> + #interrupt-cells = <1>; >> + }; >> + }; >> + >> + U74_1: cpu@1 { >> + compatible = "sifive,u74-mc", "riscv"; >> + reg = <1>; >> + d-cache-block-size = <64>; >> + d-cache-sets = <64>; >> + d-cache-size = <32768>; >> + d-tlb-sets = <1>; >> + d-tlb-size = <40>; >> + device_type = "cpu"; >> + i-cache-block-size = <64>; >> + i-cache-sets = <64>; >> + i-cache-size = <32768>; >> + i-tlb-sets = <1>; >> + i-tlb-size = <40>; >> + mmu-type = "riscv,sv39"; >> + next-level-cache = <&ccache>; >> + riscv,isa = "rv64imafdc"; > > That also begs the question: > Do your u74s support RV64GBC, as the (current) SiFive documentation > suggests? Actually, U74 doesn't support the full B extension, and the SiFive doc [1] describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes "IMAFD". "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here. [1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf Best regards, Hal _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-02-01 7:22 UTC|newest] Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-20 1:12 [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 1:12 ` [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 10:05 ` Krzysztof Kozlowski 2022-12-20 10:05 ` Krzysztof Kozlowski 2022-12-23 2:05 ` Hal Feng 2022-12-23 2:05 ` Hal Feng 2022-12-20 20:58 ` Conor Dooley 2022-12-20 20:58 ` Conor Dooley 2022-12-23 2:15 ` Hal Feng 2022-12-23 2:15 ` Hal Feng 2022-12-20 1:12 ` [PATCH v3 2/7] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 1:12 ` [PATCH v3 3/7] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 1:12 ` [PATCH v3 4/7] dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 20:21 ` Rob Herring 2022-12-20 20:21 ` Rob Herring 2022-12-20 1:12 ` [PATCH v3 5/7] soc: sifive: ccache: Add StarFive JH7110 support Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 21:14 ` Conor Dooley 2022-12-20 21:14 ` Conor Dooley 2022-12-20 1:12 ` [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 10:10 ` Krzysztof Kozlowski 2022-12-20 10:10 ` Krzysztof Kozlowski 2022-12-25 10:31 ` Hal Feng 2022-12-25 10:31 ` Hal Feng 2022-12-25 11:56 ` Krzysztof Kozlowski 2022-12-25 11:56 ` Krzysztof Kozlowski 2022-12-20 21:31 ` Conor Dooley 2022-12-20 21:31 ` Conor Dooley 2022-12-25 14:31 ` Hal Feng 2022-12-25 14:31 ` Hal Feng 2022-12-27 20:58 ` Conor Dooley 2022-12-27 20:58 ` Conor Dooley 2022-12-28 22:48 ` Conor Dooley 2022-12-28 22:48 ` Conor Dooley 2022-12-29 5:25 ` Icenowy Zheng 2022-12-29 5:25 ` Icenowy Zheng 2022-12-29 9:02 ` Conor Dooley 2022-12-29 9:02 ` Conor Dooley 2023-02-01 7:53 ` Hal Feng 2023-02-01 7:53 ` Hal Feng 2023-02-01 7:31 ` Hal Feng 2023-02-01 7:31 ` Hal Feng 2023-02-01 7:21 ` Hal Feng [this message] 2023-02-01 7:21 ` Hal Feng 2023-02-01 8:21 ` Conor Dooley 2023-02-01 8:21 ` Conor Dooley 2023-02-02 18:56 ` Hal Feng 2023-02-02 18:56 ` Hal Feng 2023-02-02 19:41 ` Conor Dooley 2023-02-02 19:41 ` Conor Dooley 2023-02-09 11:11 ` Conor Dooley 2023-02-09 11:11 ` Conor Dooley 2023-02-13 9:41 ` Hal Feng 2023-02-13 9:41 ` Hal Feng 2023-02-13 10:07 ` Conor Dooley 2023-02-13 10:07 ` Conor Dooley 2023-02-14 2:37 ` Hal Feng 2023-02-14 2:37 ` Hal Feng 2023-02-15 3:07 ` Hal Feng 2023-02-15 3:07 ` Hal Feng 2023-02-15 7:42 ` Conor Dooley 2023-02-15 7:42 ` Conor Dooley 2023-02-15 7:59 ` Conor Dooley 2023-02-15 7:59 ` Conor Dooley 2023-01-31 2:00 ` Hal Feng 2023-01-31 2:00 ` Hal Feng 2023-01-31 6:17 ` Conor Dooley 2023-01-31 6:17 ` Conor Dooley 2023-02-02 2:42 ` Hal Feng 2023-02-02 2:42 ` Hal Feng 2023-02-02 6:19 ` Conor Dooley 2023-02-02 6:19 ` Conor Dooley 2022-12-20 1:12 ` [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board " Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 21:26 ` Conor Dooley 2022-12-20 21:26 ` Conor Dooley 2022-12-23 3:12 ` Hal Feng 2022-12-23 3:12 ` Hal Feng 2022-12-28 22:49 ` Conor Dooley 2022-12-28 22:49 ` Conor Dooley 2023-01-10 17:59 ` Conor Dooley 2023-01-10 17:59 ` Conor Dooley 2023-01-18 23:43 ` Conor Dooley 2023-01-18 23:43 ` Conor Dooley 2023-02-14 9:53 ` Emil Renner Berthing 2023-02-14 9:53 ` Emil Renner Berthing 2023-02-15 14:03 ` Hal Feng 2023-02-15 14:03 ` Hal Feng 2023-02-16 9:27 ` Emil Renner Berthing 2023-02-16 9:27 ` Emil Renner Berthing 2023-02-16 9:50 ` Conor Dooley 2023-02-16 9:50 ` Conor Dooley 2023-02-16 10:09 ` Conor Dooley 2023-02-16 10:09 ` Conor Dooley 2023-02-16 10:32 ` Emil Renner Berthing 2023-02-16 10:32 ` Emil Renner Berthing 2023-02-16 12:27 ` Hal Feng 2023-02-16 12:27 ` Hal Feng 2023-02-16 13:02 ` Conor Dooley 2023-02-16 13:02 ` Conor Dooley 2022-12-26 23:01 ` [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC Conor Dooley 2022-12-26 23:01 ` Conor Dooley 2022-12-27 7:58 ` Krzysztof Kozlowski 2022-12-27 7:58 ` Krzysztof Kozlowski 2022-12-27 14:20 ` Conor Dooley 2022-12-27 14:20 ` Conor Dooley
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