From: Hal Feng <hal.feng@starfivetech.com> To: Conor Dooley <conor@kernel.org> Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, Rob Herring <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, "Thomas Gleixner" <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, "Philipp Zabel" <p.zabel@pengutronix.de>, Linus Walleij <linus.walleij@linaro.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree Date: Sun, 25 Dec 2022 22:31:41 +0800 [thread overview] Message-ID: <e23460e8-0ca4-b20b-e48e-faeca4f30e88@starfivetech.com> (raw) In-Reply-To: <Y6Ipv0BUummgqNaw@spud> On Tue, 20 Dec 2022 21:31:43 +0000, Conor Dooley wrote: > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote: > > From: Emil Renner Berthing <kernel@esmil.dk> > > > > Add initial device tree for the JH7110 RISC-V SoC by StarFive > > Technology Ltd. > > > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> > > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> > > Co-developed-by: Hal Feng <hal.feng@starfivetech.com> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > > --- > > FWIW, this cpu-map is now the default in linux, so you no longer *need* > to add it for that purpose - but there's obviously no harm in being > explicit for other operating systems etc. (IOW, don't remove it!) > > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&S76_0>; > > + }; > > + > > + core1 { > > + cpu = <&U74_1>; > > + }; > > + > > + core2 { > > + cpu = <&U74_2>; > > + }; > > + > > + core3 { > > + cpu = <&U74_3>; > > + }; > > + > > + core4 { > > + cpu = <&U74_4>; > > + }; > > + }; > > + }; > > + }; > > > + syscrg: clock-controller@13020000 { > > For obvious reasons, I cannot apply this until both the clock & pinctrl > bindings are in my tree - but you know that already. > > > + compatible = "starfive,jh7110-syscrg"; > > + reg = <0x0 0x13020000 0x0 0x10000>; > > + clocks = <&osc>, <&gmac1_rmii_refin>, > > + <&gmac1_rgmii_rxin>, > > + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, > > + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, > > + <&tdm_ext>, <&mclk_ext>; > > As Krzk asked - are these clocks really all inputs to the SoC? Yes, they are all external clock sources inputted to the SoC. They are used as root clocks or optional parent clocks in clock tree. > > > + clock-names = "osc", "gmac1_rmii_refin", > > + "gmac1_rgmii_rxin", > > + "i2stx_bclk_ext", "i2stx_lrck_ext", > > + "i2srx_bclk_ext", "i2srx_lrck_ext", > > + "tdm_ext", "mclk_ext"; > > + #clock-cells = <1>; > > + #reset-cells = <1>; > > + }; > > + > > + gpio: gpio@13040000 { > > > + gpioa: gpio@17020000 { > > Out of curiousity, why gpio & gpioa? Oh, is it easier to read if I change "gpio" and "gpioa" to "sysgpio" and "aongpio"? Thanks. Best regards, Hal
WARNING: multiple messages have this Message-ID (diff)
From: Hal Feng <hal.feng@starfivetech.com> To: Conor Dooley <conor@kernel.org> Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, Rob Herring <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, "Thomas Gleixner" <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, "Philipp Zabel" <p.zabel@pengutronix.de>, Linus Walleij <linus.walleij@linaro.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree Date: Sun, 25 Dec 2022 22:31:41 +0800 [thread overview] Message-ID: <e23460e8-0ca4-b20b-e48e-faeca4f30e88@starfivetech.com> (raw) In-Reply-To: <Y6Ipv0BUummgqNaw@spud> On Tue, 20 Dec 2022 21:31:43 +0000, Conor Dooley wrote: > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote: > > From: Emil Renner Berthing <kernel@esmil.dk> > > > > Add initial device tree for the JH7110 RISC-V SoC by StarFive > > Technology Ltd. > > > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> > > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> > > Co-developed-by: Hal Feng <hal.feng@starfivetech.com> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > > --- > > FWIW, this cpu-map is now the default in linux, so you no longer *need* > to add it for that purpose - but there's obviously no harm in being > explicit for other operating systems etc. (IOW, don't remove it!) > > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&S76_0>; > > + }; > > + > > + core1 { > > + cpu = <&U74_1>; > > + }; > > + > > + core2 { > > + cpu = <&U74_2>; > > + }; > > + > > + core3 { > > + cpu = <&U74_3>; > > + }; > > + > > + core4 { > > + cpu = <&U74_4>; > > + }; > > + }; > > + }; > > + }; > > > + syscrg: clock-controller@13020000 { > > For obvious reasons, I cannot apply this until both the clock & pinctrl > bindings are in my tree - but you know that already. > > > + compatible = "starfive,jh7110-syscrg"; > > + reg = <0x0 0x13020000 0x0 0x10000>; > > + clocks = <&osc>, <&gmac1_rmii_refin>, > > + <&gmac1_rgmii_rxin>, > > + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, > > + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, > > + <&tdm_ext>, <&mclk_ext>; > > As Krzk asked - are these clocks really all inputs to the SoC? Yes, they are all external clock sources inputted to the SoC. They are used as root clocks or optional parent clocks in clock tree. > > > + clock-names = "osc", "gmac1_rmii_refin", > > + "gmac1_rgmii_rxin", > > + "i2stx_bclk_ext", "i2stx_lrck_ext", > > + "i2srx_bclk_ext", "i2srx_lrck_ext", > > + "tdm_ext", "mclk_ext"; > > + #clock-cells = <1>; > > + #reset-cells = <1>; > > + }; > > + > > + gpio: gpio@13040000 { > > > + gpioa: gpio@17020000 { > > Out of curiousity, why gpio & gpioa? Oh, is it easier to read if I change "gpio" and "gpioa" to "sysgpio" and "aongpio"? Thanks. Best regards, Hal _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-12-25 14:32 UTC|newest] Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-20 1:12 [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 1:12 ` [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 10:05 ` Krzysztof Kozlowski 2022-12-20 10:05 ` Krzysztof Kozlowski 2022-12-23 2:05 ` Hal Feng 2022-12-23 2:05 ` Hal Feng 2022-12-20 20:58 ` Conor Dooley 2022-12-20 20:58 ` Conor Dooley 2022-12-23 2:15 ` Hal Feng 2022-12-23 2:15 ` Hal Feng 2022-12-20 1:12 ` [PATCH v3 2/7] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 1:12 ` [PATCH v3 3/7] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 1:12 ` [PATCH v3 4/7] dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 20:21 ` Rob Herring 2022-12-20 20:21 ` Rob Herring 2022-12-20 1:12 ` [PATCH v3 5/7] soc: sifive: ccache: Add StarFive JH7110 support Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 21:14 ` Conor Dooley 2022-12-20 21:14 ` Conor Dooley 2022-12-20 1:12 ` [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 10:10 ` Krzysztof Kozlowski 2022-12-20 10:10 ` Krzysztof Kozlowski 2022-12-25 10:31 ` Hal Feng 2022-12-25 10:31 ` Hal Feng 2022-12-25 11:56 ` Krzysztof Kozlowski 2022-12-25 11:56 ` Krzysztof Kozlowski 2022-12-20 21:31 ` Conor Dooley 2022-12-20 21:31 ` Conor Dooley 2022-12-25 14:31 ` Hal Feng [this message] 2022-12-25 14:31 ` Hal Feng 2022-12-27 20:58 ` Conor Dooley 2022-12-27 20:58 ` Conor Dooley 2022-12-28 22:48 ` Conor Dooley 2022-12-28 22:48 ` Conor Dooley 2022-12-29 5:25 ` Icenowy Zheng 2022-12-29 5:25 ` Icenowy Zheng 2022-12-29 9:02 ` Conor Dooley 2022-12-29 9:02 ` Conor Dooley 2023-02-01 7:53 ` Hal Feng 2023-02-01 7:53 ` Hal Feng 2023-02-01 7:31 ` Hal Feng 2023-02-01 7:31 ` Hal Feng 2023-02-01 7:21 ` Hal Feng 2023-02-01 7:21 ` Hal Feng 2023-02-01 8:21 ` Conor Dooley 2023-02-01 8:21 ` Conor Dooley 2023-02-02 18:56 ` Hal Feng 2023-02-02 18:56 ` Hal Feng 2023-02-02 19:41 ` Conor Dooley 2023-02-02 19:41 ` Conor Dooley 2023-02-09 11:11 ` Conor Dooley 2023-02-09 11:11 ` Conor Dooley 2023-02-13 9:41 ` Hal Feng 2023-02-13 9:41 ` Hal Feng 2023-02-13 10:07 ` Conor Dooley 2023-02-13 10:07 ` Conor Dooley 2023-02-14 2:37 ` Hal Feng 2023-02-14 2:37 ` Hal Feng 2023-02-15 3:07 ` Hal Feng 2023-02-15 3:07 ` Hal Feng 2023-02-15 7:42 ` Conor Dooley 2023-02-15 7:42 ` Conor Dooley 2023-02-15 7:59 ` Conor Dooley 2023-02-15 7:59 ` Conor Dooley 2023-01-31 2:00 ` Hal Feng 2023-01-31 2:00 ` Hal Feng 2023-01-31 6:17 ` Conor Dooley 2023-01-31 6:17 ` Conor Dooley 2023-02-02 2:42 ` Hal Feng 2023-02-02 2:42 ` Hal Feng 2023-02-02 6:19 ` Conor Dooley 2023-02-02 6:19 ` Conor Dooley 2022-12-20 1:12 ` [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board " Hal Feng 2022-12-20 1:12 ` Hal Feng 2022-12-20 21:26 ` Conor Dooley 2022-12-20 21:26 ` Conor Dooley 2022-12-23 3:12 ` Hal Feng 2022-12-23 3:12 ` Hal Feng 2022-12-28 22:49 ` Conor Dooley 2022-12-28 22:49 ` Conor Dooley 2023-01-10 17:59 ` Conor Dooley 2023-01-10 17:59 ` Conor Dooley 2023-01-18 23:43 ` Conor Dooley 2023-01-18 23:43 ` Conor Dooley 2023-02-14 9:53 ` Emil Renner Berthing 2023-02-14 9:53 ` Emil Renner Berthing 2023-02-15 14:03 ` Hal Feng 2023-02-15 14:03 ` Hal Feng 2023-02-16 9:27 ` Emil Renner Berthing 2023-02-16 9:27 ` Emil Renner Berthing 2023-02-16 9:50 ` Conor Dooley 2023-02-16 9:50 ` Conor Dooley 2023-02-16 10:09 ` Conor Dooley 2023-02-16 10:09 ` Conor Dooley 2023-02-16 10:32 ` Emil Renner Berthing 2023-02-16 10:32 ` Emil Renner Berthing 2023-02-16 12:27 ` Hal Feng 2023-02-16 12:27 ` Hal Feng 2023-02-16 13:02 ` Conor Dooley 2023-02-16 13:02 ` Conor Dooley 2022-12-26 23:01 ` [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC Conor Dooley 2022-12-26 23:01 ` Conor Dooley 2022-12-27 7:58 ` Krzysztof Kozlowski 2022-12-27 7:58 ` Krzysztof Kozlowski 2022-12-27 14:20 ` Conor Dooley 2022-12-27 14:20 ` Conor Dooley
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