From: "Rafael J. Wysocki" <rafael@kernel.org> To: Karol Herbst <kherbst@redhat.com> Cc: "Rafael J. Wysocki" <rafael@kernel.org>, Mika Westerberg <mika.westerberg@intel.com>, Bjorn Helgaas <helgaas@kernel.org>, LKML <linux-kernel@vger.kernel.org>, Lyude Paul <lyude@redhat.com>, "Rafael J . Wysocki" <rjw@rjwysocki.net>, Linux PCI <linux-pci@vger.kernel.org>, Linux PM <linux-pm@vger.kernel.org>, dri-devel <dri-devel@lists.freedesktop.org>, nouveau <nouveau@lists.freedesktop.org>, Dave Airlie <airlied@gmail.com>, Mario Limonciello <Mario.Limonciello@dell.com> Subject: Re: [PATCH v4] pci: prevent putting nvidia GPUs into lower device states on certain intel bridges Date: Thu, 21 Nov 2019 17:39:21 +0100 [thread overview] Message-ID: <CAJZ5v0jbh7jz+YQcw-gC5ztmMOc4E9+KFBCy4VGRsRFxBw-gnw@mail.gmail.com> (raw) In-Reply-To: <CACO55ttBkZD9dm0Y_jT931NnzHHtDFyLz28aoo+ZG0pnLzPgbA@mail.gmail.com> On Thu, Nov 21, 2019 at 5:06 PM Karol Herbst <kherbst@redhat.com> wrote: > > On Thu, Nov 21, 2019 at 4:47 PM Rafael J. Wysocki <rafael@kernel.org> wrote: > > > > On Thu, Nov 21, 2019 at 1:53 PM Karol Herbst <kherbst@redhat.com> wrote: > > > > > > On Thu, Nov 21, 2019 at 12:46 PM Mika Westerberg > > > <mika.westerberg@intel.com> wrote: > > > > > > > > On Thu, Nov 21, 2019 at 12:34:22PM +0100, Rafael J. Wysocki wrote: > > > > > On Thu, Nov 21, 2019 at 12:28 PM Mika Westerberg > > > > > <mika.westerberg@intel.com> wrote: > > > > > > > > > > > > On Wed, Nov 20, 2019 at 11:29:33PM +0100, Rafael J. Wysocki wrote: > > > > > > > > last week or so I found systems where the GPU was under the "PCI > > > > > > > > Express Root Port" (name from lspci) and on those systems all of that > > > > > > > > seems to work. So I am wondering if it's indeed just the 0x1901 one, > > > > > > > > which also explains Mikas case that Thunderbolt stuff works as devices > > > > > > > > never get populated under this particular bridge controller, but under > > > > > > > > those "Root Port"s > > > > > > > > > > > > > > It always is a PCIe port, but its location within the SoC may matter. > > > > > > > > > > > > Exactly. Intel hardware has PCIe ports on CPU side (these are called > > > > > > PEG, PCI Express Graphics, ports), and the PCH side. I think the IP is > > > > > > still the same. > > > > > > > > > > > > yeah, I meant the bridge controller with the ID 0x1901 is on the CPU > > > side. And if the Nvidia GPU is on a port on the PCH side it all seems > > > to work just fine. > > > > But that may involve different AML too, may it not? > > > > > > > > > Also some custom AML-based power management is involved and that may > > > > > > > be making specific assumptions on the configuration of the SoC and the > > > > > > > GPU at the time of its invocation which unfortunately are not known to > > > > > > > us. > > > > > > > > > > > > > > However, it looks like the AML invoked to power down the GPU from > > > > > > > acpi_pci_set_power_state() gets confused if it is not in PCI D0 at > > > > > > > that point, so it looks like that AML tries to access device memory on > > > > > > > the GPU (beyond the PCI config space) or similar which is not > > > > > > > accessible in PCI power states below D0. > > > > > > > > > > > > Or the PCI config space of the GPU when the parent root port is in D3hot > > > > > > (as it is the case here). Also then the GPU config space is not > > > > > > accessible. > > > > > > > > > > Why would the parent port be in D3hot at that point? Wouldn't that be > > > > > a suspend ordering violation? > > > > > > > > No. We put the GPU into D3hot first, then the root port and then turn > > > > off the power resource (which is attached to the root port) resulting > > > > the topology entering D3cold. > > > > > > > > > > If the kernel does a D0 -> D3hot -> D0 cycle this works as well, but > > > the power savings are way lower, so I kind of prefer skipping D3hot > > > instead of D3cold. Skipping D3hot doesn't seem to make any difference > > > in power savings in my testing. > > > > OK > > > > What exactly did you do to skip D3cold in your testing? > > > > For that I poked into the PCI registers directly and skipped doing the > ACPI calls and simply checked for the idle power consumption on my > laptop. That doesn't involve the PCIe port PM, however. > But I guess I should retest with calling pci_d3cold_disable > from nouveau instead? Or is there a different preferable way of > testing this? There is a sysfs attribute called "d3cold_allowed" which can be used for "blocking" D3cold, so can you please retest using that?
WARNING: multiple messages have this Message-ID (diff)
From: "Rafael J. Wysocki" <rafael@kernel.org> To: Karol Herbst <kherbst@redhat.com> Cc: "Rafael J. Wysocki" <rafael@kernel.org>, Linux PCI <linux-pci@vger.kernel.org>, Mika Westerberg <mika.westerberg@intel.com>, Linux PM <linux-pm@vger.kernel.org>, "Rafael J . Wysocki" <rjw@rjwysocki.net>, LKML <linux-kernel@vger.kernel.org>, dri-devel <dri-devel@lists.freedesktop.org>, Mario Limonciello <Mario.Limonciello@dell.com>, Bjorn Helgaas <helgaas@kernel.org>, nouveau <nouveau@lists.freedesktop.org> Subject: Re: [PATCH v4] pci: prevent putting nvidia GPUs into lower device states on certain intel bridges Date: Thu, 21 Nov 2019 17:39:21 +0100 [thread overview] Message-ID: <CAJZ5v0jbh7jz+YQcw-gC5ztmMOc4E9+KFBCy4VGRsRFxBw-gnw@mail.gmail.com> (raw) Message-ID: <20191121163921.wjQ8LL3LwR1A4zwq7LmlDbtRYdl1RBTqHzYln58GFIs@z> (raw) In-Reply-To: <CACO55ttBkZD9dm0Y_jT931NnzHHtDFyLz28aoo+ZG0pnLzPgbA@mail.gmail.com> On Thu, Nov 21, 2019 at 5:06 PM Karol Herbst <kherbst@redhat.com> wrote: > > On Thu, Nov 21, 2019 at 4:47 PM Rafael J. Wysocki <rafael@kernel.org> wrote: > > > > On Thu, Nov 21, 2019 at 1:53 PM Karol Herbst <kherbst@redhat.com> wrote: > > > > > > On Thu, Nov 21, 2019 at 12:46 PM Mika Westerberg > > > <mika.westerberg@intel.com> wrote: > > > > > > > > On Thu, Nov 21, 2019 at 12:34:22PM +0100, Rafael J. Wysocki wrote: > > > > > On Thu, Nov 21, 2019 at 12:28 PM Mika Westerberg > > > > > <mika.westerberg@intel.com> wrote: > > > > > > > > > > > > On Wed, Nov 20, 2019 at 11:29:33PM +0100, Rafael J. Wysocki wrote: > > > > > > > > last week or so I found systems where the GPU was under the "PCI > > > > > > > > Express Root Port" (name from lspci) and on those systems all of that > > > > > > > > seems to work. So I am wondering if it's indeed just the 0x1901 one, > > > > > > > > which also explains Mikas case that Thunderbolt stuff works as devices > > > > > > > > never get populated under this particular bridge controller, but under > > > > > > > > those "Root Port"s > > > > > > > > > > > > > > It always is a PCIe port, but its location within the SoC may matter. > > > > > > > > > > > > Exactly. Intel hardware has PCIe ports on CPU side (these are called > > > > > > PEG, PCI Express Graphics, ports), and the PCH side. I think the IP is > > > > > > still the same. > > > > > > > > > > > > yeah, I meant the bridge controller with the ID 0x1901 is on the CPU > > > side. And if the Nvidia GPU is on a port on the PCH side it all seems > > > to work just fine. > > > > But that may involve different AML too, may it not? > > > > > > > > > Also some custom AML-based power management is involved and that may > > > > > > > be making specific assumptions on the configuration of the SoC and the > > > > > > > GPU at the time of its invocation which unfortunately are not known to > > > > > > > us. > > > > > > > > > > > > > > However, it looks like the AML invoked to power down the GPU from > > > > > > > acpi_pci_set_power_state() gets confused if it is not in PCI D0 at > > > > > > > that point, so it looks like that AML tries to access device memory on > > > > > > > the GPU (beyond the PCI config space) or similar which is not > > > > > > > accessible in PCI power states below D0. > > > > > > > > > > > > Or the PCI config space of the GPU when the parent root port is in D3hot > > > > > > (as it is the case here). Also then the GPU config space is not > > > > > > accessible. > > > > > > > > > > Why would the parent port be in D3hot at that point? Wouldn't that be > > > > > a suspend ordering violation? > > > > > > > > No. We put the GPU into D3hot first, then the root port and then turn > > > > off the power resource (which is attached to the root port) resulting > > > > the topology entering D3cold. > > > > > > > > > > If the kernel does a D0 -> D3hot -> D0 cycle this works as well, but > > > the power savings are way lower, so I kind of prefer skipping D3hot > > > instead of D3cold. Skipping D3hot doesn't seem to make any difference > > > in power savings in my testing. > > > > OK > > > > What exactly did you do to skip D3cold in your testing? > > > > For that I poked into the PCI registers directly and skipped doing the > ACPI calls and simply checked for the idle power consumption on my > laptop. That doesn't involve the PCIe port PM, however. > But I guess I should retest with calling pci_d3cold_disable > from nouveau instead? Or is there a different preferable way of > testing this? There is a sysfs attribute called "d3cold_allowed" which can be used for "blocking" D3cold, so can you please retest using that? _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2019-11-21 16:39 UTC|newest] Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-17 12:19 [PATCH v4] pci: prevent putting nvidia GPUs into lower device states on certain intel bridges Karol Herbst 2019-11-14 19:17 ` Karol Herbst 2019-11-14 19:17 ` Karol Herbst [not found] ` <20191017121901.13699-1-kherbst-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> 2019-11-19 20:06 ` Dave Airlie 2019-11-19 20:06 ` Dave Airlie 2019-11-19 21:49 ` Bjorn Helgaas 2019-11-19 21:49 ` Bjorn Helgaas [not found] ` <20191119214955.GA223696-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org> 2019-11-19 22:26 ` Karol Herbst 2019-11-19 22:26 ` Karol Herbst 2019-11-19 22:57 ` Bjorn Helgaas 2019-11-19 22:57 ` Bjorn Helgaas 2019-11-20 10:18 ` Mika Westerberg 2019-11-20 10:18 ` Mika Westerberg [not found] ` <20191120101816.GX11621-3PARRvDOhMZrdx17CPfAsdBPR1lH4CV8@public.gmane.org> 2019-11-20 10:52 ` Rafael J. Wysocki 2019-11-20 10:52 ` Rafael J. Wysocki 2019-11-20 11:22 ` Mika Westerberg 2019-11-20 11:22 ` Mika Westerberg 2019-11-20 11:48 ` Rafael J. Wysocki 2019-11-20 11:51 ` Karol Herbst 2019-11-20 11:51 ` Karol Herbst [not found] ` <CACO55tsjj+xkDjubz1J=fsPecW4H_J8AaBTeaMm+NYjp8Kiq8g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2019-11-20 12:06 ` Rafael J. Wysocki 2019-11-20 12:06 ` Rafael J. Wysocki [not found] ` <CAJZ5v0ithxMPK2YxfTUx_Ygpze2FMDJ6LwKwJb2vx89dfgHX_A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2019-11-20 12:09 ` Karol Herbst 2019-11-20 12:09 ` Karol Herbst 2019-11-20 12:14 ` Rafael J. Wysocki 2019-11-20 12:14 ` Rafael J. Wysocki 2019-11-20 12:19 ` Karol Herbst 2019-11-20 12:19 ` Karol Herbst 2019-11-20 12:11 ` Rafael J. Wysocki 2019-11-20 12:11 ` Rafael J. Wysocki 2019-11-20 11:51 ` Mika Westerberg 2019-11-20 11:51 ` Mika Westerberg [not found] ` <20191120115127.GD11621-3PARRvDOhMZrdx17CPfAsdBPR1lH4CV8@public.gmane.org> 2019-11-20 11:54 ` Karol Herbst 2019-11-20 11:54 ` Karol Herbst [not found] ` <CACO55tsfNOdtu5SZ-4HzO4Ji6gQtafvZ7Rm19nkPcJAgwUBFMw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2019-11-20 11:58 ` Karol Herbst 2019-11-20 11:58 ` Karol Herbst 2019-11-20 12:09 ` Mika Westerberg 2019-11-20 12:09 ` Mika Westerberg [not found] ` <20191120120913.GE11621-3PARRvDOhMZrdx17CPfAsdBPR1lH4CV8@public.gmane.org> 2019-11-20 12:11 ` Karol Herbst 2019-11-20 12:11 ` Karol Herbst 2019-11-20 15:15 ` Mika Westerberg 2019-11-20 15:15 ` Mika Westerberg 2019-11-20 15:37 ` Karol Herbst 2019-11-20 15:53 ` Mika Westerberg 2019-11-20 15:53 ` Mika Westerberg 2019-11-20 16:23 ` Mika Westerberg 2019-11-20 16:23 ` Mika Westerberg [not found] ` <20191120162306.GM11621-3PARRvDOhMZrdx17CPfAsdBPR1lH4CV8@public.gmane.org> 2019-11-20 21:36 ` Karol Herbst 2019-11-20 21:36 ` Karol Herbst 2019-11-21 10:14 ` Mika Westerberg 2019-11-21 10:14 ` Mika Westerberg 2019-11-21 11:03 ` Rafael J. Wysocki [not found] ` <CAJZ5v0hAgz4Fu=83AJE2PYUsi+Jk=Lrr4MNp5ySA9yY=3wr5rg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2019-11-21 11:08 ` Rafael J. Wysocki 2019-11-21 11:08 ` Rafael J. Wysocki 2019-11-21 11:15 ` Rafael J. Wysocki 2019-11-21 11:15 ` Rafael J. Wysocki 2019-11-21 11:17 ` Mika Westerberg 2019-11-21 11:17 ` Mika Westerberg 2019-11-21 11:31 ` Rafael J. Wysocki 2019-11-21 11:31 ` Rafael J. Wysocki 2019-11-20 21:37 ` Rafael J. Wysocki 2019-11-20 21:37 ` Rafael J. Wysocki 2019-11-20 21:40 ` Karol Herbst 2019-11-20 21:40 ` Karol Herbst 2019-11-20 22:29 ` Rafael J. Wysocki 2019-11-20 22:29 ` Rafael J. Wysocki 2019-11-21 11:28 ` Mika Westerberg [not found] ` <20191121112821.GU11621-3PARRvDOhMZrdx17CPfAsdBPR1lH4CV8@public.gmane.org> 2019-11-21 11:34 ` Rafael J. Wysocki 2019-11-21 11:34 ` Rafael J. Wysocki 2019-11-21 11:46 ` Mika Westerberg 2019-11-21 11:46 ` Mika Westerberg 2019-11-21 12:52 ` Mika Westerberg 2019-11-21 12:56 ` Karol Herbst 2019-11-21 12:56 ` Karol Herbst [not found] ` <20191121125236.GX11621-3PARRvDOhMZrdx17CPfAsdBPR1lH4CV8@public.gmane.org> 2019-11-21 15:43 ` Rafael J. Wysocki 2019-11-21 15:43 ` Rafael J. Wysocki 2019-11-21 19:49 ` Mika Westerberg 2019-11-21 19:49 ` Mika Westerberg [not found] ` <20191121194942.GY11621-3PARRvDOhMZrdx17CPfAsdBPR1lH4CV8@public.gmane.org> 2019-11-21 22:39 ` Rafael J. Wysocki 2019-11-21 22:39 ` Rafael J. Wysocki 2019-11-21 22:50 ` Karol Herbst 2019-11-22 0:13 ` Karol Herbst 2019-11-22 0:13 ` Karol Herbst 2019-11-22 9:07 ` Rafael J. Wysocki 2019-11-22 9:07 ` Rafael J. Wysocki [not found] ` <CAJZ5v0jNq77xPXxeYeq_JJBCfekVPVPOye1mZwpQi=+=MKSS7w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2019-11-22 11:30 ` Karol Herbst 2019-11-22 11:30 ` Karol Herbst 2019-11-22 10:36 ` Mika Westerberg 2019-11-22 11:30 ` Rafael J. Wysocki 2019-11-22 11:30 ` Rafael J. Wysocki [not found] ` <CAJZ5v0gifnGZcKr6mgc6C2EfqX13OyJnOac0uDxYNKN=A0cgMg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2019-11-22 11:34 ` Karol Herbst 2019-11-22 11:34 ` Karol Herbst 2019-11-22 11:54 ` Rafael J. Wysocki 2019-11-22 11:54 ` Rafael J. Wysocki 2019-11-22 11:52 ` Mika Westerberg 2019-11-22 12:15 ` Rafael J. Wysocki 2019-11-21 12:52 ` Karol Herbst 2019-11-21 12:52 ` Karol Herbst 2019-11-21 15:47 ` Rafael J. Wysocki 2019-11-21 15:47 ` Rafael J. Wysocki 2019-11-21 16:06 ` Karol Herbst 2019-11-21 16:06 ` Karol Herbst 2019-11-21 16:39 ` Rafael J. Wysocki [this message] 2019-11-21 16:39 ` Rafael J. Wysocki 2019-11-26 23:10 ` Lyude Paul 2019-11-27 11:48 ` Mika Westerberg 2019-11-27 11:48 ` Mika Westerberg 2019-11-27 11:51 ` Karol Herbst 2019-11-27 11:51 ` Karol Herbst 2019-11-27 19:51 ` Lyude Paul 2019-11-27 19:51 ` Lyude Paul 2019-12-09 11:17 ` Karol Herbst 2019-12-09 11:38 ` Rafael J. Wysocki 2019-12-09 12:24 ` Karol Herbst 2019-12-10 19:58 ` Dave Airlie 2019-12-10 20:49 ` Karol Herbst 2020-01-13 15:31 ` Karol Herbst
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