From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Matthew Brost <matthew.brost@intel.com>
Cc: jason.ekstrand@intel.com, daniel.vetter@intel.com,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC PATCH 55/97] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC
Date: Thu, 27 May 2021 10:02:55 +0100 [thread overview]
Message-ID: <c757430f-9e00-0533-7d76-fe88d4a784d4@linux.intel.com> (raw)
In-Reply-To: <20210526181844.GB4268@sdutt-i7>
On 26/05/2021 19:18, Matthew Brost wrote:
> On Wed, May 26, 2021 at 10:21:05AM +0100, Tvrtko Ursulin wrote:
>>
>> On 25/05/2021 18:07, Matthew Brost wrote:
>>> On Tue, May 25, 2021 at 11:06:00AM +0100, Tvrtko Ursulin wrote:
>>>>
>>>> On 06/05/2021 20:14, Matthew Brost wrote:
>>>>> When running the GuC the GPU can't be considered idle if the GuC still
>>>>> has contexts pinned. As such, a call has been added in
>>>>> intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for
>>>>> the number of unpinned contexts to go to zero.
>>>>>
>>>>> Cc: John Harrison <john.c.harrison@intel.com>
>>>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 3 +-
>>>>> drivers/gpu/drm/i915/gt/intel_gt.c | 18 ++++
>>>>> drivers/gpu/drm/i915/gt/intel_gt.h | 2 +
>>>>> drivers/gpu/drm/i915/gt/intel_gt_requests.c | 22 ++---
>>>>> drivers/gpu/drm/i915/gt/intel_gt_requests.h | 7 +-
>>>>> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 4 +
>>>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 1 +
>>>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 4 +
>>>>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 91 ++++++++++++++++++-
>>>>> drivers/gpu/drm/i915/gt/uc/intel_uc.h | 5 +
>>>>> drivers/gpu/drm/i915/i915_debugfs.c | 1 +
>>>>> drivers/gpu/drm/i915/i915_gem_evict.c | 1 +
>>>>> .../gpu/drm/i915/selftests/igt_live_test.c | 2 +-
>>>>> .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +-
>>>>> 14 files changed, 137 insertions(+), 27 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>>>>> index 8598a1c78a4c..2f5295c9408d 100644
>>>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>>>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>>>>> @@ -634,7 +634,8 @@ mmap_offset_attach(struct drm_i915_gem_object *obj,
>>>>> goto insert;
>>>>> /* Attempt to reap some mmap space from dead objects */
>>>>> - err = intel_gt_retire_requests_timeout(&i915->gt, MAX_SCHEDULE_TIMEOUT);
>>>>> + err = intel_gt_retire_requests_timeout(&i915->gt, MAX_SCHEDULE_TIMEOUT,
>>>>> + NULL);
>>>>> if (err)
>>>>> goto err;
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>>>>> index 8d77dcbad059..1742a8561f69 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>>>>> @@ -574,6 +574,24 @@ static void __intel_gt_disable(struct intel_gt *gt)
>>>>> GEM_BUG_ON(intel_gt_pm_is_awake(gt));
>>>>> }
>>>>> +int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
>>>>> +{
>>>>> + long rtimeout;
>>>>> +
>>>>> + /* If the device is asleep, we have no requests outstanding */
>>>>> + if (!intel_gt_pm_is_awake(gt))
>>>>> + return 0;
>>>>> +
>>>>> + while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
>>>>> + &rtimeout)) > 0) {
>>>>> + cond_resched();
>>>>> + if (signal_pending(current))
>>>>> + return -EINTR;
>>>>> + }
>>>>> +
>>>>> + return timeout ? timeout : intel_uc_wait_for_idle(>->uc, rtimeout);
>>>>> +}
>>>>> +
>>>>> int intel_gt_init(struct intel_gt *gt)
>>>>> {
>>>>> int err;
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
>>>>> index 7ec395cace69..c775043334bf 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
>>>>> @@ -48,6 +48,8 @@ void intel_gt_driver_release(struct intel_gt *gt);
>>>>> void intel_gt_driver_late_release(struct intel_gt *gt);
>>>>> +int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
>>>>> +
>>>>> void intel_gt_check_and_clear_faults(struct intel_gt *gt);
>>>>> void intel_gt_clear_error_registers(struct intel_gt *gt,
>>>>> intel_engine_mask_t engine_mask);
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
>>>>> index 647eca9d867a..c6c702f236fa 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
>>>>> @@ -13,6 +13,7 @@
>>>>> #include "intel_gt_pm.h"
>>>>> #include "intel_gt_requests.h"
>>>>> #include "intel_timeline.h"
>>>>> +#include "uc/intel_uc.h"
>>>>> static bool retire_requests(struct intel_timeline *tl)
>>>>> {
>>>>> @@ -130,7 +131,8 @@ void intel_engine_fini_retire(struct intel_engine_cs *engine)
>>>>> GEM_BUG_ON(engine->retire);
>>>>> }
>>>>> -long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
>>>>> +long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout,
>>>>> + long *rtimeout)
>>>>
>>>> What is 'rtimeout', I know remaining, but it can be more self-descriptive to
>>>> start with.
>>>>
>>>
>>> 'remaining_timeout' it is.
>>>
>>>> It feels a bit churny for what it is. How plausible would be alternatives to
>>>> either change existing timeout to in/out, or measure sleep internally in
>>>> this function, or just risk sleeping twice as long by passing the original
>>>> timeout to uc idle as well?
>>>>
>>>
>>> Originally had it just passing in the same value, got review feedback
>>> saying I should pass in the adjusted value. Hard to make everyone happy.
>>
>> Ok.
>>
>>>>> {
>>>>> struct intel_gt_timelines *timelines = >->timelines;
>>>>> struct intel_timeline *tl, *tn;
>>>>> @@ -195,22 +197,10 @@ out_active: spin_lock(&timelines->lock);
>>>>> if (flush_submission(gt, timeout)) /* Wait, there's more! */
>>>>> active_count++;
>>>>> - return active_count ? timeout : 0;
>>>>> -}
>>>>> -
>>>>> -int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
>>>>> -{
>>>>> - /* If the device is asleep, we have no requests outstanding */
>>>>> - if (!intel_gt_pm_is_awake(gt))
>>>>> - return 0;
>>>>> -
>>>>> - while ((timeout = intel_gt_retire_requests_timeout(gt, timeout)) > 0) {
>>>>> - cond_resched();
>>>>> - if (signal_pending(current))
>>>>> - return -EINTR;
>>>>> - }
>>>>> + if (rtimeout)
>>>>> + *rtimeout = timeout;
>>>>> - return timeout;
>>>>> + return active_count ? timeout : 0;
>>>>> }
>>>>> static void retire_work_handler(struct work_struct *work)
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.h b/drivers/gpu/drm/i915/gt/intel_gt_requests.h
>>>>> index fcc30a6e4fe9..4419787124e2 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.h
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.h
>>>>> @@ -10,10 +10,11 @@ struct intel_engine_cs;
>>>>> struct intel_gt;
>>>>> struct intel_timeline;
>>>>> -long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout);
>>>>> +long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout,
>>>>> + long *rtimeout);
>>>>> static inline void intel_gt_retire_requests(struct intel_gt *gt)
>>>>> {
>>>>> - intel_gt_retire_requests_timeout(gt, 0);
>>>>> + intel_gt_retire_requests_timeout(gt, 0, NULL);
>>>>> }
>>>>> void intel_engine_init_retire(struct intel_engine_cs *engine);
>>>>> @@ -21,8 +22,6 @@ void intel_engine_add_retire(struct intel_engine_cs *engine,
>>>>> struct intel_timeline *tl);
>>>>> void intel_engine_fini_retire(struct intel_engine_cs *engine);
>>>>> -int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
>>>>> -
>>>>> void intel_gt_init_requests(struct intel_gt *gt);
>>>>> void intel_gt_park_requests(struct intel_gt *gt);
>>>>> void intel_gt_unpark_requests(struct intel_gt *gt);
>>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>>>>> index 485e98f3f304..47eaa69809e8 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>>>>> @@ -38,6 +38,8 @@ struct intel_guc {
>>>>> spinlock_t irq_lock;
>>>>> unsigned int msg_enabled_mask;
>>>>> + atomic_t outstanding_submission_g2h;
>>>>> +
>>>>> struct {
>>>>> bool enabled;
>>>>> void (*reset)(struct intel_guc *guc);
>>>>> @@ -239,6 +241,8 @@ static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
>>>>> spin_unlock_irq(&guc->irq_lock);
>>>>> }
>>>>> +int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout);
>>>>> +
>>>>> int intel_guc_reset_engine(struct intel_guc *guc,
>>>>> struct intel_engine_cs *engine);
>>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>> index f1893030ca88..cf701056fa14 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>>>> @@ -111,6 +111,7 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
>>>>> INIT_LIST_HEAD(&ct->requests.incoming);
>>>>> INIT_WORK(&ct->requests.worker, ct_incoming_request_worker_func);
>>>>> tasklet_init(&ct->receive_tasklet, ct_receive_tasklet_func, (unsigned long)ct);
>>>>> + init_waitqueue_head(&ct->wq);
>>>>> }
>>>>> static inline const char *guc_ct_buffer_type_to_str(u32 type)
>>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>>>>> index 660bf37238e2..ab1b79ab960b 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>>>>> @@ -10,6 +10,7 @@
>>>>> #include <linux/spinlock.h>
>>>>> #include <linux/workqueue.h>
>>>>> #include <linux/ktime.h>
>>>>> +#include <linux/wait.h>
>>>>> #include "intel_guc_fwif.h"
>>>>> @@ -68,6 +69,9 @@ struct intel_guc_ct {
>>>>> struct tasklet_struct receive_tasklet;
>>>>> + /** @wq: wait queue for g2h chanenl */
>>>>> + wait_queue_head_t wq;
>>>>> +
>>>>> struct {
>>>>> u16 last_fence; /* last fence used to send request */
>>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>>> index ae0b386467e3..0ff7dd6d337d 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>>> @@ -253,6 +253,74 @@ static inline void set_lrc_desc_registered(struct intel_guc *guc, u32 id,
>>>>> xa_store_irq(&guc->context_lookup, id, ce, GFP_ATOMIC);
>>>>> }
>>>>> +static int guc_submission_busy_loop(struct intel_guc* guc,
>>>>> + const u32 *action,
>>>>> + u32 len,
>>>>> + u32 g2h_len_dw,
>>>>> + bool loop)
>>>>> +{
>>>>> + int err;
>>>>> +
>>>>> + err = intel_guc_send_busy_loop(guc, action, len, g2h_len_dw, loop);
>>>>> +
>>>>> + if (!err && g2h_len_dw)
>>>>> + atomic_inc(&guc->outstanding_submission_g2h);
>>>>> +
>>>>> + return err;
>>>>> +}
>>>>> +
>>>>> +static int guc_wait_for_pending_msg(struct intel_guc *guc,
>>>>> + atomic_t *wait_var,
>>>>> + bool interruptible,
>>>>> + long timeout)
>>>>> +{
>>>>> + const int state = interruptible ?
>>>>> + TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
>>>>> + DEFINE_WAIT(wait);
>>>>> +
>>>>> + might_sleep();
>>>>> + GEM_BUG_ON(timeout < 0);
>>>>> +
>>>>> + if (!atomic_read(wait_var))
>>>>> + return 0;
>>>>> +
>>>>> + if (!timeout)
>>>>> + return -ETIME;
>>>>> +
>>>>> + for (;;) {
>>>>> + prepare_to_wait(&guc->ct.wq, &wait, state);
>>>>> +
>>>>> + if (!atomic_read(wait_var))
>>>>> + break;
>>>>> +
>>>>> + if (signal_pending_state(state, current)) {
>>>>> + timeout = -ERESTARTSYS;
>>>>> + break;
>>>>> + }
>>>>> +
>>>>> + if (!timeout) {
>>>>> + timeout = -ETIME;
>>>>> + break;
>>>>> + }
>>>>> +
>>>>> + timeout = io_schedule_timeout(timeout);
>>>>> + }
>>>>> + finish_wait(&guc->ct.wq, &wait);
>>>>> +
>>>>> + return (timeout < 0) ? timeout : 0;
>>>>> +}
>>>>
>>>> See if it is possible to simplify all this with wait_var_event and
>>>> wake_up_var.
>>>>
>>>
>>> Let me check on that.
>>>>> +
>>>>> +int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout)
>>>>> +{
>>>>> + bool interruptible = true;
>>>>> +
>>>>> + if (unlikely(timeout < 0))
>>>>> + timeout = -timeout, interruptible = false;
>>>>> +
>>>>> + return guc_wait_for_pending_msg(guc, &guc->outstanding_submission_g2h,
>>>>> + interruptible, timeout);
>>>>> +}
>>>>> +
>>>>> static int guc_add_request(struct intel_guc *guc, struct i915_request *rq)
>>>>> {
>>>>> int err;
>>>>> @@ -279,6 +347,7 @@ static int guc_add_request(struct intel_guc *guc, struct i915_request *rq)
>>>>> err = intel_guc_send_nb(guc, action, len, g2h_len_dw);
>>>>> if (!enabled && !err) {
>>>>> + atomic_inc(&guc->outstanding_submission_g2h);
>>>>> set_context_enabled(ce);
>>>>> } else if (!enabled) {
>>>>> clr_context_pending_enable(ce);
>>>>> @@ -734,7 +803,7 @@ static int __guc_action_register_context(struct intel_guc *guc,
>>>>> offset,
>>>>> };
>>>>> - return intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
>>>>> + return guc_submission_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
>>>>> }
>>>>> static int register_context(struct intel_context *ce)
>>>>> @@ -754,7 +823,7 @@ static int __guc_action_deregister_context(struct intel_guc *guc,
>>>>> guc_id,
>>>>> };
>>>>> - return intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action),
>>>>> + return guc_submission_busy_loop(guc, action, ARRAY_SIZE(action),
>>>>> G2H_LEN_DW_DEREGISTER_CONTEXT, true);
>>>>> }
>>>>> @@ -871,7 +940,9 @@ static int guc_context_pin(struct intel_context *ce, void *vaddr)
>>>>> static void guc_context_unpin(struct intel_context *ce)
>>>>> {
>>>>> - unpin_guc_id(ce_to_guc(ce), ce);
>>>>> + struct intel_guc *guc = ce_to_guc(ce);
>>>>> +
>>>>> + unpin_guc_id(guc, ce);
>>>>> lrc_unpin(ce);
>>>>> }
>>>>> @@ -894,7 +965,7 @@ static void __guc_context_sched_disable(struct intel_guc *guc,
>>>>> intel_context_get(ce);
>>>>> - intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action),
>>>>> + guc_submission_busy_loop(guc, action, ARRAY_SIZE(action),
>>>>> G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, true);
>>>>> }
>>>>> @@ -1437,6 +1508,15 @@ g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
>>>>> return ce;
>>>>> }
>>>>> +static void decr_outstanding_submission_g2h(struct intel_guc *guc)
>>>>> +{
>>>>> + if (atomic_dec_and_test(&guc->outstanding_submission_g2h)) {
>>>>> + smp_mb();
>>>>> + if (waitqueue_active(&guc->ct.wq))
>>>>> + wake_up_all(&guc->ct.wq);
>>>>
>>>> I keep pointing out this pattern is racy and at least needs comment why it
>>>> is safe.
>>>>
>>>
>>> There is a comment in wake queue code header saying why this is safe. I
>>> don't think we need to repeat this here.
>>
>> Yeah, _describing how to make it safe_, after it starts with:
>>
>> * NOTE: this function is lockless and requires care, incorrect usage _will_
>> * lead to sporadic and non-obvious failure.
>>
>> Then it also says:
>>
>> * Also note that this 'optimization' trades a spin_lock() for an smp_mb(),
>> * which (when the lock is uncontended) are of roughly equal cost.
>>
>> I question the need to optimize this path since it means reader has to figure out if it is safe while a simple wake_up_all after atomic_dec_and_test would have done it.
>>
>> Is the case of no waiters a predominant one? It at least deserves a comment explaining why the optimisation is important.
>>
>
> I just didn't want to add a spin_lock if there is known working code
> path without one and our code fits into that path. I can add a comment
> but I don't really think it necessary.
Lock already exists in the wake_up_all, it is not about adding your own.
As premature optimisations are usually best avoided it is simply about
how do you justify a):
+static void decr_outstanding_submission_g2h(struct intel_guc *guc)
+{
+ if (atomic_dec_and_test(&guc->outstanding_submission_g2h)) {
+ smp_mb();
+ if (waitqueue_active(&guc->ct.wq))
+ wake_up_all(&guc->ct.wq);
When the easy alternative (easy to read, easy to review, easy to
maintain) is b):
+static void decr_outstanding_submission_g2h(struct intel_guc *guc)
+{
+ if (atomic_dec_and_test(&guc->outstanding_submission_g2h))
+ wake_up_all(&guc->ct.wq);
For me as external reader the question seems to be, I will say it again,
is the case of no waiters a common one and is this a hot path to justify
avoiding a function call by adding the mental complexity explained in
the waitqueue_active comment? Here and in the other places in the GuC
backend waitqueue_active is used.
Regards,
Tvrtko
next prev parent reply other threads:[~2021-05-27 9:03 UTC|newest]
Thread overview: 249+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-06 19:13 [RFC PATCH 00/97] Basic GuC submission support in the i915 Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 01/97] drm/i915/gt: Move engine setup out of set_default_submission Matthew Brost
2021-05-19 0:25 ` Matthew Brost
2021-05-25 8:44 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-06 19:13 ` [RFC PATCH 02/97] drm/i915/gt: Move submission_method into intel_gt Matthew Brost
2021-05-19 3:10 ` Matthew Brost
2021-05-25 8:44 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-06 19:13 ` [RFC PATCH 03/97] drm/i915/gt: Move CS interrupt handler to the backend Matthew Brost
2021-05-19 3:31 ` Matthew Brost
2021-05-25 8:45 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-06 19:13 ` [RFC PATCH 04/97] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost
2021-05-20 16:47 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 05/97] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost
2021-05-24 10:30 ` Michal Wajdeczko
2021-05-06 19:13 ` [RFC PATCH 06/97] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost
2021-05-25 0:31 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 07/97] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost
2021-05-24 10:48 ` Michal Wajdeczko
2021-05-25 0:36 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 08/97] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost
2021-05-24 23:52 ` Michał Winiarski
2021-05-06 19:13 ` [RFC PATCH 09/97] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost
2021-05-25 2:38 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 10/97] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost
2021-05-25 0:42 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 11/97] drm/i915/guc: Only rely on own CTB size Matthew Brost
2021-05-25 2:47 ` Matthew Brost
2021-05-25 12:48 ` [Intel-gfx] " Michal Wajdeczko
2021-05-06 19:13 ` [RFC PATCH 12/97] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost
2021-05-25 2:53 ` Matthew Brost
2021-05-25 13:07 ` Michal Wajdeczko
2021-05-25 16:56 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 13/97] drm/i915/guc: Replace CTB array with explicit members Matthew Brost
2021-05-25 3:15 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 14/97] drm/i915/guc: Update sizes of CTB buffers Matthew Brost
2021-05-25 2:56 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 15/97] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-05-25 18:08 ` Matthew Brost
2021-05-25 19:37 ` [Intel-gfx] " Michal Wajdeczko
2021-05-06 19:13 ` [RFC PATCH 16/97] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost
2021-05-25 3:21 ` Matthew Brost
2021-05-25 3:21 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 17/97] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost
2021-05-25 16:14 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 18/97] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost
2021-05-25 18:15 ` Matthew Brost
2021-05-25 19:43 ` [Intel-gfx] " Michal Wajdeczko
2021-05-06 19:13 ` [RFC PATCH 19/97] drm/i915/guc: Always copy CT message to new allocation Matthew Brost
2021-05-25 18:25 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 20/97] drm/i915/guc: Introduce unified HXG messages Matthew Brost
2021-05-11 15:16 ` Daniel Vetter
2021-05-11 17:59 ` Matthew Brost
2021-05-11 22:11 ` Michal Wajdeczko
2021-05-12 8:40 ` Daniel Vetter
2021-05-06 19:13 ` [RFC PATCH 21/97] drm/i915/guc: Update MMIO based communication Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 22/97] drm/i915/guc: Update CTB response status Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 23/97] drm/i915/guc: Support per context scheduling policies Matthew Brost
2021-05-25 1:15 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 24/97] drm/i915/guc: Add flag for mark broken CTB Matthew Brost
2021-05-27 19:44 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 25/97] drm/i915/guc: New definition of the CTB descriptor Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 26/97] drm/i915/guc: New definition of the CTB registration action Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 27/97] drm/i915/guc: New CTB based communication Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 28/97] drm/i915/guc: Kill guc_clients.ct_pool Matthew Brost
2021-05-25 1:01 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 29/97] drm/i915/guc: Update firmware to v60.1.2 Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 30/97] drm/i915/uc: turn on GuC/HuC auto mode by default Matthew Brost
2021-05-24 11:00 ` Michal Wajdeczko
2021-05-06 19:13 ` [RFC PATCH 31/97] drm/i915/guc: Early initialization of GuC send registers Matthew Brost
2021-05-26 20:28 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 32/97] drm/i915: Introduce i915_sched_engine object Matthew Brost
2021-05-11 15:18 ` Daniel Vetter
2021-05-11 17:56 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 33/97] drm/i915: Engine relative MMIO Matthew Brost
2021-05-25 9:05 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-06 19:13 ` [RFC PATCH 34/97] drm/i915/guc: Use guc_class instead of engine_class in fw interface Matthew Brost
2021-05-26 20:41 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 35/97] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost
2021-05-24 11:59 ` Michal Wajdeczko
2021-05-25 17:32 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 36/97] drm/i915/guc: Add non blocking CTB send function Matthew Brost
2021-05-24 12:21 ` Michal Wajdeczko
2021-05-25 17:30 ` Matthew Brost
2021-05-25 9:21 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-25 17:21 ` Matthew Brost
2021-05-26 8:57 ` Tvrtko Ursulin
2021-05-26 18:10 ` Matthew Brost
2021-05-27 10:02 ` Tvrtko Ursulin
2021-05-27 14:35 ` Matthew Brost
2021-05-27 15:11 ` Tvrtko Ursulin
2021-06-07 17:31 ` Matthew Brost
2021-06-08 8:39 ` Tvrtko Ursulin
2021-06-08 8:46 ` Daniel Vetter
2021-06-09 23:10 ` Matthew Brost
2021-06-10 15:27 ` Daniel Vetter
2021-06-24 16:38 ` Matthew Brost
2021-06-24 17:25 ` Daniel Vetter
2021-06-09 13:58 ` Michal Wajdeczko
2021-06-09 23:05 ` Matthew Brost
2021-06-09 14:14 ` Michal Wajdeczko
2021-06-09 23:13 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 37/97] drm/i915/guc: Add stall timer to " Matthew Brost
2021-05-24 12:58 ` Michal Wajdeczko
2021-05-24 18:35 ` Matthew Brost
2021-05-25 14:15 ` Michal Wajdeczko
2021-05-25 16:54 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 38/97] drm/i915/guc: Optimize CTB writes and reads Matthew Brost
2021-05-24 13:31 ` Michal Wajdeczko
2021-05-25 17:39 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 39/97] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-05-24 13:43 ` [Intel-gfx] " Michal Wajdeczko
2021-05-24 18:40 ` Matthew Brost
2021-05-25 9:24 ` Tvrtko Ursulin
2021-05-25 17:15 ` Matthew Brost
2021-05-26 9:30 ` Tvrtko Ursulin
2021-05-26 18:20 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 40/97] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost
2021-05-24 13:45 ` Michal Wajdeczko
2021-05-06 19:13 ` [RFC PATCH 41/97] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 42/97] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 43/97] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost
2021-05-11 15:26 ` Daniel Vetter
2021-05-11 17:01 ` Matthew Brost
2021-05-11 17:43 ` Daniel Vetter
2021-05-11 19:34 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 44/97] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-05-25 9:43 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-25 17:10 ` Matthew Brost
2021-05-06 19:13 ` [RFC PATCH 45/97] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 46/97] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-05-29 20:32 ` Michal Wajdeczko
2021-05-06 19:14 ` [RFC PATCH 47/97] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 48/97] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 49/97] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-05-11 15:37 ` Daniel Vetter
2021-05-11 16:31 ` Matthew Brost
2021-05-26 10:26 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-06 19:14 ` [RFC PATCH 50/97] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 51/97] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 52/97] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 53/97] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-05-25 9:52 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-25 17:01 ` Matthew Brost
2021-05-26 9:25 ` Tvrtko Ursulin
2021-05-26 18:15 ` Matthew Brost
2021-05-27 8:41 ` Tvrtko Ursulin
2021-05-27 14:38 ` Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 54/97] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 55/97] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-05-25 10:06 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-25 17:07 ` Matthew Brost
2021-05-26 9:21 ` Tvrtko Ursulin
2021-05-26 18:18 ` Matthew Brost
2021-05-27 9:02 ` Tvrtko Ursulin [this message]
2021-05-27 14:37 ` Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 56/97] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 57/97] drm/i915/guc: Add several request trace points Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 58/97] drm/i915: Add intel_context tracing Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 59/97] drm/i915/guc: GuC virtual engines Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 60/97] drm/i915: Track 'serial' counts for " Matthew Brost
2021-05-25 10:16 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-25 17:52 ` Matthew Brost
2021-05-26 8:40 ` Tvrtko Ursulin
2021-05-26 18:45 ` John Harrison
2021-05-27 8:53 ` Tvrtko Ursulin
2021-05-27 17:01 ` John Harrison
2021-06-01 9:31 ` Tvrtko Ursulin
2021-06-02 1:20 ` John Harrison
2021-06-02 12:04 ` Tvrtko Ursulin
2021-06-02 12:09 ` Tvrtko Ursulin
2021-05-06 19:14 ` [RFC PATCH 61/97] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-06-02 12:18 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-06 19:14 ` [RFC PATCH 62/97] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 63/97] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-06-02 13:31 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-06 19:14 ` [RFC PATCH 64/97] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-06-02 14:33 ` [Intel-gfx] " Tvrtko Ursulin
2021-06-04 3:17 ` Matthew Brost
2021-06-04 8:16 ` Daniel Vetter
2021-06-04 18:02 ` Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 65/97] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-06-02 14:36 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-06 19:14 ` [RFC PATCH 66/97] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-05-11 8:16 ` [drm/i915/guc] 07336fb545: WARNING:at_drivers/gpu/drm/i915/gt/uc/intel_uc.c:#__uc_sanitize[i915] kernel test robot
2021-05-06 19:14 ` [RFC PATCH 67/97] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 68/97] drm/i915/guc: Handle context reset notification Matthew Brost
2021-05-11 16:25 ` [Intel-gfx] " Daniel Vetter
2021-05-06 19:14 ` [RFC PATCH 69/97] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 70/97] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 71/97] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 72/97] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 73/97] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 74/97] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-05-11 16:28 ` [Intel-gfx] " Daniel Vetter
2021-05-11 17:12 ` Matthew Brost
2021-05-11 17:45 ` Daniel Vetter
2021-05-06 19:14 ` [RFC PATCH 75/97] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 76/97] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 77/97] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 78/97] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 79/97] drm/i915/guc: Don't call ring_is_idle in GuC submission Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 80/97] drm/i915/guc: Implement banned contexts for " Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 81/97] drm/i915/guc: Allow flexible number of context ids Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 82/97] drm/i915/guc: Connect the number of guc_ids to debugfs Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 83/97] drm/i915/guc: Don't return -EAGAIN to user when guc_ids exhausted Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 84/97] drm/i915/guc: Don't allow requests not ready to consume all guc_ids Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 85/97] drm/i915/guc: Introduce guc_submit_engine object Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 86/97] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 87/97] drm/i915/guc: Implement GuC priority management Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 88/97] drm/i915/guc: Support request cancellation Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 89/97] drm/i915/guc: Check return of __xa_store when registering a context Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 90/97] drm/i915/guc: Non-static lrc descriptor registration buffer Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 91/97] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 92/97] drm/i915: Add GT PM delayed worker Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 93/97] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 94/97] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 95/97] drm/i915/guc: Selftest for GuC flow control Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 96/97] drm/i915/guc: Update GuC documentation Matthew Brost
2021-05-06 19:14 ` [RFC PATCH 97/97] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-05-09 17:12 ` [RFC PATCH 00/97] Basic GuC submission support in the i915 Martin Peres
2021-05-09 23:11 ` Jason Ekstrand
2021-05-10 13:55 ` Martin Peres
2021-05-10 16:25 ` Jason Ekstrand
2021-05-11 8:01 ` Martin Peres
2021-05-10 16:33 ` Daniel Vetter
2021-05-10 18:30 ` [Intel-gfx] " Francisco Jerez
2021-05-11 8:06 ` Martin Peres
2021-05-11 15:26 ` Bloomfield, Jon
2021-05-11 16:39 ` Matthew Brost
2021-05-12 6:26 ` Martin Peres
2021-05-14 16:31 ` Jason Ekstrand
2021-05-25 15:37 ` Alex Deucher
2021-05-11 2:58 ` Dixit, Ashutosh
2021-05-11 7:47 ` Martin Peres
2021-05-14 11:11 ` [Intel-gfx] " Tvrtko Ursulin
2021-05-14 16:36 ` Jason Ekstrand
2021-05-14 16:46 ` Matthew Brost
2021-05-14 16:41 ` Matthew Brost
2021-05-25 10:32 ` Tvrtko Ursulin
2021-05-25 16:45 ` Matthew Brost
2021-06-02 15:27 ` Tvrtko Ursulin
2021-06-02 18:57 ` Daniel Vetter
2021-06-03 3:41 ` Matthew Brost
2021-06-03 4:47 ` Daniel Vetter
2021-06-03 9:49 ` Tvrtko Ursulin
2021-06-03 10:52 ` Tvrtko Ursulin
2021-06-03 4:10 ` Matthew Brost
2021-06-03 8:51 ` Tvrtko Ursulin
2021-06-03 16:34 ` Matthew Brost
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