* [Intel-gfx] [RFC-v23 01/13] drm/i915/pxp: Introduce Intel PXP component
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-21 16:08 ` Chris Wilson
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
` (14 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (a.k.a default session or
arbitrary session). So Mesa can allocate the protected buffer,
which is encrypted with the leverage of the arbitrary hardware
session.
rev21:
- Remove the term "Mesa" from the help description of Kconfig
- Remove unnecessary "select INTEL_MEI_TXE" from DRM_I915_PXP
in Kconfig
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Kconfig | 21 ++++++++++++++
drivers/gpu/drm/i915/Makefile | 5 ++++
drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 ++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 25 +++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 25 +++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 23 ++++++++++++++++
9 files changed, 151 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..f0a8c46126d8 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,27 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ select INTEL_MEI
+ select INTEL_MEI_ME
+ select INTEL_MEI_PXP
+ default y
+ help
+ This option selects INTEL_MEI_ME if it isn't already selected to
+ enabled full PXP Services on Intel platforms.
+
+ PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
+ that helps to establish the hardware protected session and manage
+ the status of the alive software session, as well as its life cycle.
+
+ This patch series is to allow the kernel space to create and
+ manage a single hardware session (a.k.a default session or
+ arbitrary session). So user space can allocate the protected buffer,
+ which is encrypted with the leverage of the arbitrary hardware
+ session.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 006dec54408d..9d27e2d8decc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -265,6 +265,11 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index d8e1ab412634..336ad7deae06 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -18,6 +18,7 @@
#include "intel_uncore.h"
#include "intel_pm.h"
#include "shmem_utils.h"
+#include "pxp/intel_pxp.h"
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
@@ -584,6 +585,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ intel_pxp_init(>->pxp);
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -607,6 +610,8 @@ void intel_gt_driver_remove(struct intel_gt *gt)
{
__intel_gt_disable(gt);
+ intel_pxp_fini(>->pxp);
+
intel_uc_driver_remove(>->uc);
intel_engines_release(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index a83d3e18254d..c4760e2722fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_types.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -145,6 +146,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index 000000000000..9bc3c7e30654
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+
+void intel_pxp_init(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ if (INTEL_GEN(gt->i915) < 12)
+ return;
+
+ intel_pxp_ctx_init(&pxp->ctx);
+
+ drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
+}
+
+void intel_pxp_fini(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ if (INTEL_GEN(gt->i915) < 12)
+ return;
+
+ intel_pxp_ctx_fini(&pxp->ctx);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
new file mode 100644
index 000000000000..f47bc6bea34f
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_H__
+#define __INTEL_PXP_H__
+
+#include "intel_pxp_types.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_init(struct intel_pxp *pxp);
+void intel_pxp_fini(struct intel_pxp *pxp);
+#else
+static inline void intel_pxp_init(struct intel_pxp *pxp)
+{
+ return 0;
+}
+
+static inline void intel_pxp_fini(struct intel_pxp *pxp)
+{
+}
+#endif
+
+#endif /* __INTEL_PXP_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
new file mode 100644
index 000000000000..2be6bf2f0d0f
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_context.h"
+
+/**
+ * intel_pxp_ctx_init - To init a pxp context.
+ * @ctx: pointer to ctx structure.
+ */
+void intel_pxp_ctx_init(struct pxp_context *ctx)
+{
+ mutex_init(&ctx->mutex);
+ ctx->inited = true;
+}
+
+/**
+ * intel_pxp_ctx_fini - To finish the pxp context.
+ * @ctx: pointer to ctx structure.
+ */
+void intel_pxp_ctx_fini(struct pxp_context *ctx)
+{
+ ctx->inited = false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
new file mode 100644
index 000000000000..f51021c33d45
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_CONTEXT_H__
+#define __INTEL_PXP_CONTEXT_H__
+
+#include <linux/mutex.h>
+#include "intel_pxp_types.h"
+
+void intel_pxp_ctx_init(struct pxp_context *ctx);
+void intel_pxp_ctx_fini(struct pxp_context *ctx);
+
+#endif /* __INTEL_PXP_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
new file mode 100644
index 000000000000..f9b40ea98b1b
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TYPES_H__
+#define __INTEL_PXP_TYPES_H__
+
+#include <linux/mutex.h>
+
+/* struct pxp_context - Represents combined view of driver and logical HW states. */
+struct pxp_context {
+ /** @mutex: mutex to protect the pxp context */
+ struct mutex mutex;
+
+ bool inited;
+};
+
+struct intel_pxp {
+ struct pxp_context ctx;
+};
+
+#endif /* __INTEL_PXP_TYPES_H__ */
--
2.17.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [RFC-v23 01/13] drm/i915/pxp: Introduce Intel PXP component
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
@ 2021-01-21 16:08 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2021-01-21 16:08 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx; +Cc: kumar.gaurav
Quoting Huang, Sean Z (2021-01-19 07:43:08)
> PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> that helps to establish the hardware protected session and manage
> the status of the alive software session, as well as its life cycle.
>
> This patch series is to allow the kernel space to create and
> manage a single hardware session (a.k.a default session or
> arbitrary session). So Mesa can allocate the protected buffer,
> which is encrypted with the leverage of the arbitrary hardware
> session.
>
> rev21:
> - Remove the term "Mesa" from the help description of Kconfig
> - Remove unnecessary "select INTEL_MEI_TXE" from DRM_I915_PXP
> in Kconfig
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Kconfig | 21 ++++++++++++++
> drivers/gpu/drm/i915/Makefile | 5 ++++
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 ++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 25 +++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 25 +++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 23 ++++++++++++++++
> 9 files changed, 151 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>
> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> index 1e1cb245fca7..f0a8c46126d8 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -130,6 +130,27 @@ config DRM_I915_GVT_KVMGT
> Choose this option if you want to enable KVMGT support for
> Intel GVT-g.
>
> +config DRM_I915_PXP
> + bool "Enable Intel PXP support for Intel Gen12+ platform"
> + depends on DRM_I915
> + select INTEL_MEI
> + select INTEL_MEI_ME
> + select INTEL_MEI_PXP
> + default y
That's a bitter pill to swallow. Note that
INTEL_MEI depends on x86 && PCI
so we really should only be
depends on INTEL_MEI if X86 && PCI
> + help
> + This option selects INTEL_MEI_ME if it isn't already selected to
> + enabled full PXP Services on Intel platforms.
> +
> + PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
GEN12+ GPUs
We have to be careful to distinguish GPU generation from processor
generation. Too easy for the reader to confuse.
> + that helps to establish the hardware protected session and manage
> + the status of the alive software session, as well as its life cycle.
> +
> + This patch series is to allow the kernel space to create and
> + manage a single hardware session (a.k.a default session or
> + arbitrary session). So user space can allocate the protected buffer,
> + which is encrypted with the leverage of the arbitrary hardware
> + session.
Patch series in a user help message? This paragraph looks like it
doesn't belong here.
> +
> menu "drm/i915 Debugging"
> depends on DRM_I915
> depends on EXPERT
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 006dec54408d..9d27e2d8decc 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -265,6 +265,11 @@ i915-y += \
>
> i915-y += i915_perf.o
>
> +# Protected execution platform (PXP) support
> +i915-$(CONFIG_DRM_I915_PXP) += \
> + pxp/intel_pxp.o \
> + pxp/intel_pxp_context.o
> +
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> i915-$(CONFIG_DRM_I915_SELFTEST) += \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index d8e1ab412634..336ad7deae06 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -18,6 +18,7 @@
> #include "intel_uncore.h"
> #include "intel_pm.h"
> #include "shmem_utils.h"
> +#include "pxp/intel_pxp.h"
>
> void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> {
> @@ -584,6 +585,8 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + intel_pxp_init(>->pxp);
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -607,6 +610,8 @@ void intel_gt_driver_remove(struct intel_gt *gt)
> {
> __intel_gt_disable(gt);
>
> + intel_pxp_fini(>->pxp);
> +
> intel_uc_driver_remove(>->uc);
>
> intel_engines_release(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index a83d3e18254d..c4760e2722fd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp_types.h"
>
> struct drm_i915_private;
> struct i915_ggtt;
> @@ -145,6 +146,8 @@ struct intel_gt {
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> } info;
> +
> + struct intel_pxp pxp;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> new file mode 100644
> index 000000000000..9bc3c7e30654
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_context.h"
> +
> +void intel_pxp_init(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> +
> + if (INTEL_GEN(gt->i915) < 12)
> + return;
> +
> + intel_pxp_ctx_init(&pxp->ctx);
> +
> + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
> +}
> +
> +void intel_pxp_fini(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> +
> + if (INTEL_GEN(gt->i915) < 12)
> + return;
> +
> + intel_pxp_ctx_fini(&pxp->ctx);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> new file mode 100644
> index 000000000000..f47bc6bea34f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_H__
> +#define __INTEL_PXP_H__
> +
> +#include "intel_pxp_types.h"
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +void intel_pxp_init(struct intel_pxp *pxp);
> +void intel_pxp_fini(struct intel_pxp *pxp);
> +#else
> +static inline void intel_pxp_init(struct intel_pxp *pxp)
> +{
> + return 0;
> +}
> +
> +static inline void intel_pxp_fini(struct intel_pxp *pxp)
> +{
> +}
> +#endif
> +
> +#endif /* __INTEL_PXP_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> new file mode 100644
> index 000000000000..2be6bf2f0d0f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_context.h"
> +
> +/**
> + * intel_pxp_ctx_init - To init a pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_init(struct pxp_context *ctx)
> +{
> + mutex_init(&ctx->mutex);
> + ctx->inited = true;
> +}
> +
> +/**
> + * intel_pxp_ctx_fini - To finish the pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_fini(struct pxp_context *ctx)
> +{
> + ctx->inited = false;
Is something wrong with the setup code? What has access to PXP beyond
your control?
-Chris
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] [RFC-v23 02/13] drm/i915/pxp: set KCR reg init during the boot time
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-21 17:04 ` Chris Wilson
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
` (13 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
rev21:
- Remove "#define KCR_INIT_MASK_SHIFT (16)", but still keep the
macro in this .c file
- Write KCR_INIT reg inly for gen12 during boot, not required
for gen13+
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 9bc3c7e30654..4e9cee7df4f2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,12 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+/* KCR register definitions */
+#define KCR_INIT _MMIO(0x320f0)
+
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << 16))
+
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -15,6 +21,9 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_ctx_init(&pxp->ctx);
+ if (INTEL_GEN(gt->i915) == 12)
+ intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
}
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [RFC-v23 02/13] drm/i915/pxp: set KCR reg init during the boot time
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
@ 2021-01-21 17:04 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2021-01-21 17:04 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx; +Cc: kumar.gaurav
Quoting Huang, Sean Z (2021-01-19 07:43:09)
> Set the KCR init during the boot time, which is
> required by hardware, to allow us doing further
> protection operation such as sending commands to
> GPU or TEE.
>
> rev21:
> - Remove "#define KCR_INIT_MASK_SHIFT (16)", but still keep the
> macro in this .c file
> - Write KCR_INIT reg inly for gen12 during boot, not required
> for gen13+
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 9bc3c7e30654..4e9cee7df4f2 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,12 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
>
> +/* KCR register definitions */
> +#define KCR_INIT _MMIO(0x320f0)
> +
> +/* Setting KCR Init bit is required after system boot */
> +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << 16))
What Rodrigo was saying is that this is a classic masked register, so we
should be doing:
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
intel_uncore_write(gt->uncore, KCR_INIT,
_MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
-Chris
_______________________________________________
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] [RFC-v23 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
` (12 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(default) session.
rev21:
- Remove debug print_hex_dump() from intel_pxp_tee_io_message()
- In struct i915_pxp_component_ops, change "receive" to "recv"
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 129 +++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45 ++++++++
8 files changed, 203 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9d27e2d8decc..07bb0400e016 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -268,7 +268,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
- pxp/intel_pxp_context.o
+ pxp/intel_pxp_context.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f5666b44ea9d..e9cb8e9ca172 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
+ mutex_init(&dev_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8376cff5ba86..d2ae5874c516 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1209,6 +1209,12 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 4e9cee7df4f2..81cf845d1b94 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
/* KCR register definitions */
#define KCR_INIT _MMIO(0x320f0)
@@ -24,6 +25,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (INTEL_GEN(gt->i915) == 12)
intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ intel_pxp_tee_component_init(pxp);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
}
@@ -34,5 +37,7 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (INTEL_GEN(gt->i915) < 12)
return;
+ intel_pxp_tee_component_fini(pxp);
+
intel_pxp_ctx_fini(&pxp->ctx);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index 000000000000..e7edd4e1d5b4
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include <linux/component.h>
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
+ return -EINVAL;
+
+ lockdep_assert_held(&i915->pxp_tee_comp_mutex);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in, msg_in_size);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to send TEE message\n");
+ return -EFAULT;
+ }
+
+ ret = pxp_tee_master->ops->recv(pxp_tee_master->tee_dev, msg_out, msg_out_buf_size);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed to receive TEE message\n");
+ return -EFAULT;
+ }
+
+ if (ret > msg_out_buf_size) {
+ drm_err(&i915->drm, "Failed to receive TEE message due to unexpected output size\n");
+ return -EFAULT;
+ }
+
+ *msg_out_size_ptr = ret;
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * i915_pxp_tee_component_bind - bind funciton to pass the function pointers to pxp_tee
+ * @i915_kdev: pointer to i915 kernel device
+ * @tee_kdev: pointer to tee kernel device
+ * @data: pointer to pxp_tee_master containing the function pointers
+ *
+ * This bind function is called during the system boot or resume from system sleep.
+ *
+ * Return: return 0 if successful.
+ */
+static int i915_pxp_tee_component_bind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ if (!i915 || !tee_kdev || !data)
+ return -EPERM;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_master = (struct i915_pxp_comp_master *)data;
+ i915->pxp_tee_master->tee_dev = tee_kdev;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ return 0;
+}
+
+static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ if (!i915 || !tee_kdev || !data)
+ return;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_master = NULL;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+}
+
+static const struct component_ops i915_pxp_tee_component_ops = {
+ .bind = i915_pxp_tee_component_bind,
+ .unbind = i915_pxp_tee_component_unbind,
+};
+
+void intel_pxp_tee_component_init(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops,
+ I915_COMPONENT_PXP);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed at component add(%d)\n", ret);
+ return;
+ }
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_comp_added = true;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+}
+
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ if (!i915->pxp_tee_comp_added) {
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+ return;
+ }
+
+ i915->pxp_tee_comp_added = false;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
new file mode 100644
index 000000000000..4b5e3edb1d9b
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TEE_H__
+#define __INTEL_PXP_TEE_H__
+
+#include "intel_pxp.h"
+
+void intel_pxp_tee_component_init(struct intel_pxp *pxp);
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_TEE_H__ */
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 55c3b123581b..c1e2a43d2d1e 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -29,6 +29,7 @@
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
+ I915_COMPONENT_PXP
};
/* MAX_PORT is the number of port
diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h
new file mode 100644
index 000000000000..0efd14702b4b
--- /dev/null
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef _I915_PXP_TEE_INTERFACE_H_
+#define _I915_PXP_TEE_INTERFACE_H_
+
+#include <linux/mutex.h>
+#include <linux/device.h>
+
+/**
+ * struct i915_pxp_component_ops - ops for PXP services.
+ * @owner: Module providing the ops
+ * @send: sends data to PXP
+ * @receive: receives data from PXP
+ */
+struct i915_pxp_component_ops {
+ /**
+ * @owner: owner of the module provding the ops
+ */
+ struct module *owner;
+
+ int (*send)(struct device *dev, const void *message, size_t size);
+ int (*recv)(struct device *dev, void *buffer, size_t size);
+};
+
+/**
+ * struct i915_pxp_component_master - Used for communication between i915
+ * and TEE drivers for the PXP services
+ * @tee_dev: device that provide the PXP service from TEE Bus.
+ * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
+ */
+struct i915_pxp_comp_master {
+ struct device *tee_dev;
+ const struct i915_pxp_component_ops *ops;
+
+ /* To protect the above members. */
+ struct mutex mutex;
+};
+
+#endif /* _I915_TEE_PXP_INTERFACE_H_ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [RFC-v23 04/13] drm/i915/pxp: Create the arbitrary session after boot
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (2 preceding siblings ...)
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 05/13] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
` (11 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
rev21:
- Rename SESSION_TYPE_TYPE0, SESSION_TYPE_TYPE1 as SESSION_TYPE_HWDRM,
SESSION_TYPE_NONHWDRM to have better meaning.
- Remove enum pxp_session_types and enum pxp_protection_modes from
single session patch series.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 122 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 16 +++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 73 +++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 4 +
8 files changed, 221 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 07bb0400e016..e3b7f6b5dadb 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -268,6 +268,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_arb.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 81cf845d1b94..4f033907564a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
/* KCR register definitions */
#define KCR_INIT _MMIO(0x320f0)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
new file mode 100644
index 000000000000..dd98ca407e78
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp_types.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
+
+/* Arbitrary session */
+#define ARB_SESSION_INDEX 0xf
+
+bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp)
+{
+ u32 regval_sip = 0;
+ intel_wakeref_t wakeref;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
+ regval_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+ }
+
+ return regval_sip & BIT(ARB_SESSION_INDEX);
+}
+
+/* wait hw session_in_play reg to match the current sw state */
+static int wait_arb_hw_sw_state(struct intel_pxp *pxp)
+{
+ const int max_retry = 10;
+ const int ms_delay = 10;
+ int retry = 0;
+ int ret;
+
+ ret = -EINVAL;
+ for (retry = 0; retry < max_retry; retry++) {
+ if (intel_pxp_arb_session_is_in_play(pxp) ==
+ pxp->ctx.arb_is_in_play) {
+ ret = 0;
+ break;
+ }
+
+ msleep(ms_delay);
+ }
+
+ return ret;
+}
+
+static void arb_session_entry_init(struct intel_pxp *pxp)
+{
+ pxp->ctx.arb_is_in_play = false;
+}
+
+static int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
+{
+ int ret;
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ arb_session_entry_init(pxp);
+ ret = wait_arb_hw_sw_state(pxp);
+
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_mark_session_in_play - To put an reserved protected session to "in_play" state
+ * @pxp: pointer to pxp struct.
+ *
+ * Return: status. 0 means update is successful.
+ */
+static int intel_pxp_arb_mark_session_in_play(struct intel_pxp *pxp)
+{
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ if (pxp->ctx.arb_is_in_play)
+ return -EINVAL;
+
+ pxp->ctx.arb_is_in_play = true;
+ return 0;
+}
+
+int intel_pxp_arb_create_session(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ if (pxp->ctx.flag_display_hm_surface_keys) {
+ drm_err(>->i915->drm, "%s: arb session is alive so skipping the creation\n",
+ __func__);
+ return 0;
+ }
+
+ ret = intel_pxp_arb_reserve_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to reserve arb session\n");
+ return ret;
+ }
+
+ ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION_INDEX);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to send tee cmd for arb session creation\n");
+ return ret;
+ }
+
+ ret = intel_pxp_arb_mark_session_in_play(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to mark arb session status in play\n");
+ return ret;
+ }
+
+ pxp->ctx.flag_display_hm_surface_keys = true;
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
new file mode 100644
index 000000000000..2196153dd879
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_ARB_H__
+#define __INTEL_PXP_ARB_H__
+
+#include <linux/types.h>
+
+struct intel_pxp;
+
+int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_ARB_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index f51021c33d45..bf2feb4aaf6d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -8,6 +8,7 @@
#include <linux/mutex.h>
#include "intel_pxp_types.h"
+#include "intel_pxp_arb.h"
void intel_pxp_ctx_init(struct pxp_context *ctx);
void intel_pxp_ctx_fini(struct pxp_context *ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index e7edd4e1d5b4..4dd33ffb8373 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -10,6 +10,32 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
+
+#define PXP_TEE_APIVER 0x40002
+#define PXP_TEE_ARB_CMDID 0x1e
+#define PXP_TEE_ARB_PROTECTION_MODE 0x2
+
+/* PXP TEE message header */
+struct pxp_tee_cmd_header {
+ u32 api_version;
+ u32 command_id;
+ u32 status;
+ /* Length of the message (excluding the header) */
+ u32 buffer_len;
+} __packed;
+
+/* PXP TEE message input to create a arbitrary session */
+struct pxp_tee_create_arb_in {
+ struct pxp_tee_cmd_header header;
+ u32 protection_mode;
+ u32 session_id;
+} __packed;
+
+/* PXP TEE message output to create a arbitrary session */
+struct pxp_tee_create_arb_out {
+ struct pxp_tee_cmd_header header;
+} __packed;
static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
void *msg_in, u32 msg_in_size,
@@ -62,7 +88,9 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
static int i915_pxp_tee_component_bind(struct device *i915_kdev,
struct device *tee_kdev, void *data)
{
+ int ret = 0;
struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+ struct intel_pxp *pxp = &i915->gt.pxp;
if (!i915 || !tee_kdev || !data)
return -EPERM;
@@ -72,6 +100,19 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
i915->pxp_tee_master->tee_dev = tee_kdev;
mutex_unlock(&i915->pxp_tee_comp_mutex);
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Create arb session only if tee is ready, during system boot or sleep/resume */
+ if (!intel_pxp_arb_session_is_in_play(pxp))
+ ret = intel_pxp_arb_create_session(pxp);
+
+ mutex_unlock(&pxp->ctx.mutex);
+
+ if (ret) {
+ drm_err(&i915->drm, "Failed to create arb session ret=[%d]\n", ret);
+ return ret;
+ }
+
return 0;
}
@@ -127,3 +168,35 @@ void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
}
+
+int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
+ int arb_session_id)
+{
+ int ret;
+ u32 msg_out_size_received = 0;
+ struct pxp_tee_create_arb_in msg_in = {0};
+ struct pxp_tee_create_arb_out msg_out = {0};
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ msg_in.header.api_version = PXP_TEE_APIVER;
+ msg_in.header.command_id = PXP_TEE_ARB_CMDID;
+ msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header);
+ msg_in.protection_mode = PXP_TEE_ARB_PROTECTION_MODE;
+ msg_in.session_id = arb_session_id;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+
+ ret = intel_pxp_tee_io_message(pxp,
+ &msg_in,
+ sizeof(msg_in),
+ &msg_out, &msg_out_size_received,
+ sizeof(msg_out));
+
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ if (ret)
+ drm_err(&i915->drm, "Failed to send tee msg ret=[%d]\n", ret);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
index 4b5e3edb1d9b..c46f9033f709 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -11,4 +11,7 @@
void intel_pxp_tee_component_init(struct intel_pxp *pxp);
void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
+int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
+ int arb_session_id);
+
#endif /* __INTEL_PXP_TEE_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index f9b40ea98b1b..e2bd320302c2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -14,6 +14,10 @@ struct pxp_context {
struct mutex mutex;
bool inited;
+
+ bool arb_is_in_play;
+
+ bool flag_display_hm_surface_keys;
};
struct intel_pxp {
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [RFC-v23 05/13] drm/i915/pxp: Func to send hardware session termination
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (3 preceding siblings ...)
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
` (10 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
rev21:
In intel_pxp_cmd.c:
- Remove the debug print as well as print_hex_dump()
- Should call i915_gem_object_flush_map() before unpin map
- Using "goto label" instead of bool such as is_engine_pm_get
- We should always return the error if any, instead of skip
with i915_request_set_error_once()
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 13 +++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 124 +++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 4 +
5 files changed, 160 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e3b7f6b5dadb..c931ef5e8a85 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -269,6 +269,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_arb.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 4f033907564a..f71677a84405 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -17,10 +17,23 @@
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ int i;
if (INTEL_GEN(gt->i915) < 12)
return;
+ /* Find the first VCS engine present */
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (HAS_ENGINE(gt, _VCS(i))) {
+ pxp->vcs_engine = gt->engine[_VCS(i)];
+ break;
+ }
+ }
+ if (!pxp->vcs_engine) {
+ drm_err(>->i915->drm, "Could not find a VCS engine\n");
+ return;
+ }
+
intel_pxp_ctx_init(&pxp->ctx);
if (INTEL_GEN(gt->i915) == 12)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index 000000000000..6898b8826302
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_cmd.h"
+#include "i915_drv.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(>->i915->drm, "Failed to %s, invalid cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(>->i915->drm, "Failed to i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ i915_gem_object_flush_map(pool->obj);
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(>->i915->drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ int size = cmd_size_in_dw * 4;
+
+ ce = pxp->vcs_engine->kernel_context;
+ if (!ce)
+ return -EINVAL;
+
+ if (!cmd || cmd_size_in_dw == 0)
+ return -EINVAL;
+
+ intel_engine_pm_get(ce->engine);
+
+ size = round_up(size, PAGE_SIZE);
+ pool = intel_gt_get_buffer_pool(gt, size);
+ if (IS_ERR(pool)) {
+ err = PTR_ERR(pool);
+ goto out_engine_pm_put;
+ }
+
+ batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_engine_pool_put;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err)
+ goto out_engine_pool_put;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_vma_unpin;
+ }
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err)
+ goto out_vma_unpin;
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (!err)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err)
+ goto out_vma_unpin;
+
+ if (ce->engine->emit_init_breadcrumb) {
+ err = ce->engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_vma_unpin;
+ }
+
+ err = ce->engine->emit_bb_start(rq, batch->node.start,
+ batch->node.size, 0);
+ if (err)
+ goto out_vma_unpin;
+
+ i915_request_add(rq);
+
+out_vma_unpin:
+ i915_vma_unpin(batch);
+out_engine_pool_put:
+ intel_gt_buffer_pool_put(pool);
+out_engine_pm_put:
+ intel_engine_pm_put(ce->engine);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
new file mode 100644
index 000000000000..d04463962421
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_CMD_H__
+#define __INTEL_PXP_CMD_H__
+
+#include "gt/intel_gt_buffer_pool.h"
+#include "intel_pxp.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw);
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw);
+#endif /* __INTEL_PXP_SM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index e2bd320302c2..19d43b43e483 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -8,6 +8,8 @@
#include <linux/mutex.h>
+struct intel_engine_cs;
+
/* struct pxp_context - Represents combined view of driver and logical HW states. */
struct pxp_context {
/** @mutex: mutex to protect the pxp context */
@@ -22,6 +24,8 @@ struct pxp_context {
struct intel_pxp {
struct pxp_context ctx;
+
+ struct intel_engine_cs *vcs_engine;
};
#endif /* __INTEL_PXP_TYPES_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [RFC-v23 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (4 preceding siblings ...)
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 05/13] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 07/13] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
` (9 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
rev21:
- Fix bug, access i915 pointer before assigning the value at
intel_pxp_irq_handler()
- Writing register GEN11_CRYPTO_RSVD_INTR_ENABLE to enable the PXP irq
- Remove the unnecessary comment for GEN11_CRYPTO_RSVD_INTR_MASK
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 14 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 99 ++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 23 ++++-
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 -
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++
7 files changed, 145 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 9830342aa6f4..2241e9abfa3a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -14,6 +14,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -107,6 +108,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>->pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
@@ -233,6 +237,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
}
void gen11_gt_irq_postinstall(struct intel_gt *gt)
@@ -245,6 +252,10 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
const u32 dmask = irqs << 16 | irqs;
const u32 smask = irqs << 16;
+ const u32 smask_pxp =
+ (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+ PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
+ PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE) << 16;
BUILD_BUG_ON(irqs & 0xffff0000);
@@ -271,6 +282,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
/* Same thing for GuC interrupts */
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, smask_pxp);
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~smask_pxp);
}
void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 249a81575b9d..97bcecada87f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7943,6 +7943,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE 1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index f71677a84405..99cd93e12455 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -2,6 +2,7 @@
/*
* Copyright(c) 2020 Intel Corporation.
*/
+#include <linux/workqueue.h>
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
@@ -14,6 +15,70 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << 16))
+static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>->irq_lock);
+
+ intel_uncore_write(gt->uncore, GEN11_CRYPTO_RSVD_INTR_MASK, mask << 16);
+}
+
+static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ int ret;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ pxp->ctx.global_state_attacked = true;
+
+ mutex_unlock(&pxp->ctx.mutex);
+
+ return ret;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ if (pxp->ctx.global_state_attacked) {
+ pxp->ctx.global_state_attacked = false;
+
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_arb_create_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to create arb session\n");
+ goto end;
+ }
+ }
+end:
+ mutex_unlock(&pxp->ctx.mutex);
+ return ret;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work);
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>->irq_lock);
+ events = fetch_and_zero(&pxp->current_events);
+ spin_unlock_irq(>->irq_lock);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(pxp);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(pxp);
+
+ spin_lock_irq(>->irq_lock);
+ intel_pxp_write_irq_mask_reg(gt, ~pxp->handled_irr);
+ spin_unlock_irq(>->irq_lock);
+}
+
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -41,6 +106,12 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_tee_component_init(pxp);
+ INIT_WORK(&pxp->irq_work, intel_pxp_irq_work);
+
+ pxp->handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+ PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
+ PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
}
@@ -55,3 +126,31 @@ void intel_pxp_fini(struct intel_pxp *pxp)
intel_pxp_ctx_fini(&pxp->ctx);
}
+
+/**
+ * intel_pxp_irq_handler - Proxies KCR interrupts to PXP.
+ * @pxp: pointer to pxp struct
+ * @iir: GT interrupt vector associated with the interrupt
+ *
+ * Dispatches each vector element into an IRQ to PXP.
+ */
+void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
+{
+ const u32 events = iir & pxp->handled_irr;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!gt || !gt->i915 || INTEL_GEN(gt->i915) < 12)
+ return;
+
+ lockdep_assert_held(>->irq_lock);
+
+ if (!events) {
+ drm_err(>->i915->drm, "pxp irq handler called with zero irr\n");
+ return;
+ }
+
+ intel_pxp_write_irq_mask_reg(gt, ~0);
+
+ pxp->current_events |= events;
+ schedule_work(&pxp->irq_work);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index f47bc6bea34f..420da2790624 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -8,15 +8,36 @@
#include "intel_pxp_types.h"
+#define PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED BIT(1)
+#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
+#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+
#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
+int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
+int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp);
+
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
#else
-static inline void intel_pxp_init(struct intel_pxp *pxp)
+static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
+{
+}
+
+static inline int i915_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ return 0;
+}
+
+static inline int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
{
return 0;
}
+static inline void intel_pxp_init(struct intel_pxp *pxp)
+{
+}
+
static inline void intel_pxp_fini(struct intel_pxp *pxp)
{
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
index 2be6bf2f0d0f..4e820258b7ae 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -11,7 +11,10 @@
*/
void intel_pxp_ctx_init(struct pxp_context *ctx)
{
+ ctx->global_state_attacked = false;
+
mutex_init(&ctx->mutex);
+
ctx->inited = true;
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index bf2feb4aaf6d..f51021c33d45 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -8,7 +8,6 @@
#include <linux/mutex.h>
#include "intel_pxp_types.h"
-#include "intel_pxp_arb.h"
void intel_pxp_ctx_init(struct pxp_context *ctx);
void intel_pxp_ctx_fini(struct pxp_context *ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index 19d43b43e483..dd7445ff2cb8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -7,6 +7,7 @@
#define __INTEL_PXP_TYPES_H__
#include <linux/mutex.h>
+#include <linux/workqueue.h>
struct intel_engine_cs;
@@ -20,9 +21,14 @@ struct pxp_context {
bool arb_is_in_play;
bool flag_display_hm_surface_keys;
+ bool global_state_attacked;
};
struct intel_pxp {
+ struct work_struct irq_work;
+ u32 handled_irr;
+ u32 current_events;
+
struct pxp_context ctx;
struct intel_engine_cs *vcs_engine;
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [RFC-v23 07/13] drm/i915/pxp: Destroy arb session upon teardown
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (5 preceding siblings ...)
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 08/13] drm/i915/pxp: Enable PXP power management Huang, Sean Z
` (8 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
rev21:
- Bug fixing, we need to set the PXP_GLOBAL_TERMINATE 0x320f8
register after arb session termination
- Remove enum pxp_session_types and enum pxp_protection_modes from
single session patch series.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 86 ++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 109 +++++++++++++++++++++--
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 11 +--
5 files changed, 200 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 99cd93e12455..e6dd57ec73f5 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -29,6 +29,9 @@ static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
mutex_lock(&pxp->ctx.mutex);
pxp->ctx.global_state_attacked = true;
+ pxp->ctx.flag_display_hm_surface_keys = false;
+
+ ret = intel_pxp_arb_terminate_session_with_global_terminate(pxp);
mutex_unlock(&pxp->ctx.mutex);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
index dd98ca407e78..cde5ddd73da9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -10,9 +10,13 @@
#include "intel_pxp_arb.h"
#include "intel_pxp.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_cmd.h"
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
+/* PXP global terminate register for session termination */
+#define PXP_GLOBAL_TERMINATE _MMIO(0x320f8)
+
/* Arbitrary session */
#define ARB_SESSION_INDEX 0xf
@@ -120,3 +124,85 @@ int intel_pxp_arb_create_session(struct intel_pxp *pxp)
return ret;
}
+
+static int intel_pxp_arb_session_terminate(struct intel_pxp *pxp)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ /* Calculate how many bytes need to be alloc */
+ cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL, ARB_SESSION_INDEX);
+ cmd_size_in_dw += intel_pxp_cmd_add_inline_termination(NULL);
+ cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr, ARB_SESSION_INDEX);
+ cmd_ptr += intel_pxp_cmd_add_inline_termination(cmd_ptr);
+ cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_err(>->i915->drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
+ }
+
+ ret = intel_pxp_cmd_submit(pxp, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to intel_pxp_cmd_submit()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_terminate_session_with_global_terminate - Terminate the arb hw session.
+ * @pxp: pointer to pxp struct.
+ *
+ * This function is NOT intended to be called from the ioctl, and need to be protected by
+ * ctx.mutex to ensure no SIP change during the call.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+int intel_pxp_arb_terminate_session_with_global_terminate(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ /* terminate the hw sessions */
+ ret = intel_pxp_arb_session_terminate(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to intel_pxp_arb_session_terminate\n");
+ return ret;
+ }
+
+ pxp->ctx.arb_is_in_play = false;
+
+ ret = wait_arb_hw_sw_state(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to wait_arb_hw_sw_state\n");
+ return ret;
+ }
+
+ intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
index 2196153dd879..6b0622e8ba93 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -11,6 +11,7 @@
struct intel_pxp;
int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+int intel_pxp_arb_terminate_session_with_global_terminate(struct intel_pxp *pxp);
bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp);
#endif /* __INTEL_PXP_ARB_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
index 6898b8826302..6a0fe50c1aeb 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -5,13 +5,29 @@
#include "intel_pxp_cmd.h"
#include "i915_drv.h"
+#include "gt/intel_gpu_commands.h"
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
-struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
- struct intel_context *ce,
- struct intel_gt_buffer_pool_node *pool,
- u32 *cmd_buf, int cmd_size_in_dw)
+/* PXP GPU command definitions */
+
+/* MI_SET_APPID */
+#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
+
+/* MI_FLUSH_DW */
+#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22)
+
+/* MI_WAIT */
+#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9)
+#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8)
+
+/* CRYPTO_KEY_EXCHANGE */
+#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16))
+
+static struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
{
struct i915_vma *batch = ERR_PTR(-EINVAL);
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -46,7 +62,8 @@ struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
return batch;
}
-int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd,
+ int cmd_size_in_dw)
{
int err = -EINVAL;
struct i915_vma *batch;
@@ -122,3 +139,85 @@ int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
return err;
}
+
+int intel_pxp_cmd_add_prolog(struct intel_pxp *pxp, u32 *cmd,
+ int session_index)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_prolog = cmd;
+ const int cmd_prolog_size_in_dw = 10;
+
+ if (!cmd)
+ return cmd_prolog_size_in_dw;
+
+ /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_FLUSH_DW - pxp off */
+ *cmd_prolog++ = MI_FLUSH_DW; /* DW0 */
+ *cmd_prolog++ = 0; /* DW1 */
+ *cmd_prolog++ = 0; /* DW2 */
+
+ /* MI_SET_APPID */
+ *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_SESSION_ID(session_index));
+
+ /* MFX_WAIT */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_FLUSH_DW - pxp on */
+ *cmd_prolog++ = (MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE); /* DW0 */
+ *cmd_prolog++ = 0; /* DW1 */
+ *cmd_prolog++ = 0; /* DW2 */
+
+ /* MFX_WAIT */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ increased_size_in_dw = (cmd_prolog - cmd);
+
+ return increased_size_in_dw;
+}
+
+int intel_pxp_cmd_add_epilog(u32 *cmd)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_epilog = cmd;
+ const int cmd_epilog_size_in_dw = 5;
+
+ if (!cmd)
+ return cmd_epilog_size_in_dw;
+
+ /* MI_FLUSH_DW - pxp off */
+ *cmd_epilog++ = MI_FLUSH_DW; /* DW0 */
+ *cmd_epilog++ = 0; /* DW1 */
+ *cmd_epilog++ = 0; /* DW2 */
+
+ /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+ *cmd_epilog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_BATCH_BUFFER_END */
+ *cmd_epilog++ = MI_BATCH_BUFFER_END;
+
+ increased_size_in_dw = (cmd_epilog - cmd);
+ return increased_size_in_dw;
+}
+
+int intel_pxp_cmd_add_inline_termination(u32 *cmd)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_termin = cmd;
+ const int cmd_termin_size_in_dw = 2;
+
+ if (!cmd)
+ return cmd_termin_size_in_dw;
+
+ /* CRYPTO_KEY_EXCHANGE - session inline termination */
+ *cmd_termin++ = CRYPTO_KEY_EXCHANGE; /* DW0 */
+ *cmd_termin++ = 0; /* DW1 */
+
+ increased_size_in_dw = (cmd_termin - cmd);
+ return increased_size_in_dw;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
index d04463962421..efd26e4987a4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
@@ -9,10 +9,11 @@
#include "gt/intel_gt_buffer_pool.h"
#include "intel_pxp.h"
-struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
- struct intel_context *ce,
- struct intel_gt_buffer_pool_node *pool,
- u32 *cmd_buf, int cmd_size_in_dw);
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd,
+ int cmd_size_in_dw);
+int intel_pxp_cmd_add_prolog(struct intel_pxp *pxp, u32 *cmd,
+ int session_index);
+int intel_pxp_cmd_add_epilog(u32 *cmd);
+int intel_pxp_cmd_add_inline_termination(u32 *cmd);
-int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [RFC-v23 08/13] drm/i915/pxp: Enable PXP power management
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (6 preceding siblings ...)
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 07/13] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 09/13] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
` (7 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++
drivers/gpu/drm/i915/i915_drv.c | 4 ++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 ++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 +
6 files changed, 106 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c931ef5e8a85..eba360ed84d8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -271,6 +271,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_arb.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index c94e8ac884eb..ae0387e419a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -20,6 +20,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -266,6 +267,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>->uc);
+ intel_pxp_pm_resume(>->pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -300,6 +303,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_pm_prepare_suspend(>->pxp);
intel_uc_suspend(>->uc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e9cb8e9ca172..19db49206e0c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1342,6 +1344,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(&dev_priv->gt.pxp);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index 000000000000..5a1b5ad4f997
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp_context.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+ if (!pxp->ctx.inited)
+ return;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Disable PXP-IOCTLs */
+ pxp->ctx.global_state_in_suspend = true;
+
+ mutex_unlock(&pxp->ctx.mutex);
+}
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+ if (!pxp->ctx.inited)
+ return;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ if (pxp->ctx.global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ pxp->ctx.global_state_attacked = false;
+
+ pxp->ctx.flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(&pxp->ctx.mutex);
+}
+
+int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!pxp->ctx.inited)
+ return 0;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (pxp->ctx.global_state_in_suspend) {
+ ret = intel_pxp_arb_terminate_session_with_global_terminate(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to terminate the arb session\n");
+ goto end;
+ }
+
+ pxp->ctx.global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(&pxp->ctx.mutex);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
new file mode 100644
index 000000000000..135bfb59aaf7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_PM_H__
+#define __INTEL_PXP_PM_H__
+
+#include "i915_drv.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp);
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp);
+int intel_pxp_pm_resume(struct intel_pxp *pxp);
+#else
+static inline void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+}
+
+static inline void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+}
+
+static inline int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ return 0;
+}
+#endif
+
+#endif /* __INTEL_PXP_PM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index dd7445ff2cb8..e825553db46e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -22,6 +22,7 @@ struct pxp_context {
bool flag_display_hm_surface_keys;
bool global_state_attacked;
+ bool global_state_in_suspend;
};
struct intel_pxp {
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [RFC-v23 09/13] drm/i915/pxp: Expose session state for display protection flip
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (7 preceding siblings ...)
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 08/13] drm/i915/pxp: Enable PXP power management Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-21 19:47 ` Rodrigo Vivi
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 10/13] mei: pxp: export pavp client to me client bus Huang, Sean Z
` (6 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive. And Implement the funciton to set
the protected flag for gem context.
rev23:
- Require user space to explicitly set recoverable flag to
false for protected context creation.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 34 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 24 +++++++++++++
include/uapi/drm/i915_drm.h | 9 +++++
4 files changed, 69 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 1449f54924e0..7a9872d35fbb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -134,6 +134,8 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
+#define UCONTEXT_PROTECTED 5
+#define UCONTEXT_UNRECOVERABLE 6
/**
* @flags: small set of booleans
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index e6dd57ec73f5..f2ac5996700d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -157,3 +157,37 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
pxp->current_events |= events;
schedule_work(&pxp->irq_work);
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ if (i915->gt.pxp.ctx.inited &&
+ i915->gt.pxp.ctx.flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
+
+int intel_pxp_gem_context_create_param(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ if (!ctx || !args)
+ return -EINVAL;
+
+ if (args->param == I915_CONTEXT_PARAM_PROTECTED_CONTENT) {
+ if (!intel_pxp_arb_session_is_in_play(&ctx->i915->gt.pxp))
+ return -EINVAL;
+
+ if (args->value)
+ set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+ } else if (args->param == I915_CONTEXT_PARAM_RECOVERABLE)
+ if (!args->value)
+ set_bit(UCONTEXT_UNRECOVERABLE, &ctx->user_flags);
+
+ return 0;
+}
+
+bool intel_pxp_gem_context_protected_param_valid(struct i915_gem_context *ctx)
+{
+ return (test_bit(UCONTEXT_PROTECTED, &ctx->user_flags) &&
+ test_bit(UCONTEXT_UNRECOVERABLE, &ctx->user_flags));
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 420da2790624..ab461cc1839a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,6 +12,10 @@
#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+struct drm_i915_private;
+struct i915_gem_context;
+struct drm_i915_gem_context_param;
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
@@ -19,6 +23,10 @@ int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp);
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
+int intel_pxp_gem_context_create_param(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args);
+bool intel_pxp_gem_context_protected_param_valid(struct i915_gem_context *ctx);
#else
static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
{
@@ -41,6 +49,22 @@ static inline void intel_pxp_init(struct intel_pxp *pxp)
static inline void intel_pxp_fini(struct intel_pxp *pxp)
{
}
+
+static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ return false;
+}
+
+static inline int intel_pxp_gem_context_create_param(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ return 0;
+}
+
+static inline bool intel_pxp_gem_context_protected_param_valid(struct i915_gem_context *ctx)
+{
+ return false;
+}
#endif
#endif /* __INTEL_PXP_H__ */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 1987e2ea79a3..00fd1c2bcbb3 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1694,6 +1694,15 @@ struct drm_i915_gem_context_param {
* Default is 16 KiB.
*/
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
+
+/*
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true (1) PAVP content protection is enabled.
+ * When enabled, the context is marked unrecoverable and may
+ * become invalid due to PAVP teardown event or other error.
+ */
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
/* Must be kept compact -- no holes and well documented */
__u64 value;
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [RFC-v23 09/13] drm/i915/pxp: Expose session state for display protection flip
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 09/13] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
@ 2021-01-21 19:47 ` Rodrigo Vivi
0 siblings, 0 replies; 30+ messages in thread
From: Rodrigo Vivi @ 2021-01-21 19:47 UTC (permalink / raw)
To: Huang, Sean Z, Joonas Lahtinen; +Cc: kumar.gaurav, Intel-gfx
On Mon, Jan 18, 2021 at 11:43:16PM -0800, Huang, Sean Z wrote:
> Implement the intel_pxp_gem_object_status() to allow i915 display
> querying the current PXP session state. In the design, display
> should not perform protection flip on the protected buffers if
> there is no PXP session alive. And Implement the funciton to set
> the protected flag for gem context.
>
> rev23:
> - Require user space to explicitly set recoverable flag to
> false for protected context creation.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 34 +++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 24 +++++++++++++
> include/uapi/drm/i915_drm.h | 9 +++++
> 4 files changed, 69 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index 1449f54924e0..7a9872d35fbb 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -134,6 +134,8 @@ struct i915_gem_context {
> #define UCONTEXT_BANNABLE 2
> #define UCONTEXT_RECOVERABLE 3
> #define UCONTEXT_PERSISTENCE 4
> +#define UCONTEXT_PROTECTED 5
> +#define UCONTEXT_UNRECOVERABLE 6
I don't believe we want to extend this.
if I understood corectly, the request was to make sure that
UCONTEXT_RECOVERABLE is not set, not to create the negative one...
Joonas?
>
> /**
> * @flags: small set of booleans
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index e6dd57ec73f5..f2ac5996700d 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -157,3 +157,37 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
> pxp->current_events |= events;
> schedule_work(&pxp->irq_work);
> }
> +
> +bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
> +{
> + if (i915->gt.pxp.ctx.inited &&
> + i915->gt.pxp.ctx.flag_display_hm_surface_keys)
> + return true;
> + else
> + return false;
> +}
> +
> +int intel_pxp_gem_context_create_param(struct i915_gem_context *ctx,
> + struct drm_i915_gem_context_param *args)
> +{
> + if (!ctx || !args)
> + return -EINVAL;
> +
> + if (args->param == I915_CONTEXT_PARAM_PROTECTED_CONTENT) {
> + if (!intel_pxp_arb_session_is_in_play(&ctx->i915->gt.pxp))
> + return -EINVAL;
> +
> + if (args->value)
> + set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> + } else if (args->param == I915_CONTEXT_PARAM_RECOVERABLE)
> + if (!args->value)
> + set_bit(UCONTEXT_UNRECOVERABLE, &ctx->user_flags);
> +
> + return 0;
> +}
> +
> +bool intel_pxp_gem_context_protected_param_valid(struct i915_gem_context *ctx)
> +{
> + return (test_bit(UCONTEXT_PROTECTED, &ctx->user_flags) &&
> + test_bit(UCONTEXT_UNRECOVERABLE, &ctx->user_flags));
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 420da2790624..ab461cc1839a 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -12,6 +12,10 @@
> #define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
> #define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
>
> +struct drm_i915_private;
> +struct i915_gem_context;
> +struct drm_i915_gem_context_param;
> +
> #ifdef CONFIG_DRM_I915_PXP
> void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
> int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
> @@ -19,6 +23,10 @@ int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp);
>
> void intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_fini(struct intel_pxp *pxp);
> +bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
> +int intel_pxp_gem_context_create_param(struct i915_gem_context *ctx,
> + struct drm_i915_gem_context_param *args);
> +bool intel_pxp_gem_context_protected_param_valid(struct i915_gem_context *ctx);
> #else
> static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
> {
> @@ -41,6 +49,22 @@ static inline void intel_pxp_init(struct intel_pxp *pxp)
> static inline void intel_pxp_fini(struct intel_pxp *pxp)
> {
> }
> +
> +static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
> +{
> + return false;
> +}
> +
> +static inline int intel_pxp_gem_context_create_param(struct i915_gem_context *ctx,
> + struct drm_i915_gem_context_param *args)
> +{
> + return 0;
> +}
> +
> +static inline bool intel_pxp_gem_context_protected_param_valid(struct i915_gem_context *ctx)
> +{
> + return false;
> +}
> #endif
>
> #endif /* __INTEL_PXP_H__ */
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 1987e2ea79a3..00fd1c2bcbb3 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1694,6 +1694,15 @@ struct drm_i915_gem_context_param {
> * Default is 16 KiB.
> */
> #define I915_CONTEXT_PARAM_RINGSIZE 0xc
> +
> +/*
> + * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + *
> + * If set to true (1) PAVP content protection is enabled.
> + * When enabled, the context is marked unrecoverable and may
> + * become invalid due to PAVP teardown event or other error.
> + */
> +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
> /* Must be kept compact -- no holes and well documented */
>
> __u64 value;
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] [RFC-v23 10/13] mei: pxp: export pavp client to me client bus
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (8 preceding siblings ...)
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 09/13] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
` (5 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav, Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +++++++++++++++++++++++++++++++++
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index 000000000000..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index 000000000000..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index 000000000000..bd31fce1e6ba
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/uuid.h>
+#include <linux/mei_cl_bus.h>
+#include <linux/component.h>
+#include <drm/drm_connector.h>
+#include <drm/i915_component.h>
+#include <drm/i915_pxp_tee_interface.h>
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .recv = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = &mei_pxp_ops;
+ comp_master->tee_dev = dev;
+ ret = component_bind_all(dev, comp_master);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static void mei_component_master_unbind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+
+ dev_dbg(dev, "%s\n", __func__);
+ component_unbind_all(dev, comp_master);
+}
+
+static const struct component_master_ops mei_component_master_ops = {
+ .bind = mei_component_master_bind,
+ .unbind = mei_component_master_unbind,
+};
+
+/**
+ * mei_pxp_component_match - compare function for matching mei pxp.
+ *
+ * The function checks if the driver is i915, the subcomponent is PXP
+ * and the grand parent of pxp and the parent of i915 are the same
+ * PCH device.
+ *
+ * @dev: master device
+ * @subcomponent: subcomponent to match (I915_COMPONENT_PXP)
+ * @data: compare data (mei pxp device)
+ *
+ * Return:
+ * * 1 - if components match
+ * * 0 - otherwise
+ */
+static int mei_pxp_component_match(struct device *dev, int subcomponent,
+ void *data)
+{
+ struct device *base = data;
+
+ if (subcomponent != I915_COMPONENT_PXP)
+ return 0;
+
+ if (strcmp(dev->driver->name, "i915") == 0) {
+ base = base->parent;
+ if (!base)
+ return 0;
+
+ base = base->parent;
+ dev = dev->parent;
+ return (base && dev && dev == base);
+ }
+
+ return 0;
+}
+
+static int mei_pxp_probe(struct mei_cl_device *cldev,
+ const struct mei_cl_device_id *id)
+{
+ struct i915_pxp_comp_master *comp_master;
+ struct component_match *master_match;
+ int ret;
+
+ ret = mei_cldev_enable(cldev);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret);
+ goto enable_err_exit;
+ }
+
+ comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL);
+ if (!comp_master) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ master_match = NULL;
+ component_match_add_typed(&cldev->dev, &master_match,
+ mei_pxp_component_match, &cldev->dev);
+ if (IS_ERR_OR_NULL(master_match)) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ mei_cldev_set_drvdata(cldev, comp_master);
+ ret = component_master_add_with_match(&cldev->dev,
+ &mei_component_master_ops,
+ master_match);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "Master comp add failed %d\n", ret);
+ goto err_exit;
+ }
+
+ return 0;
+
+err_exit:
+ mei_cldev_set_drvdata(cldev, NULL);
+ kfree(comp_master);
+ mei_cldev_disable(cldev);
+enable_err_exit:
+ return ret;
+}
+
+static int mei_pxp_remove(struct mei_cl_device *cldev)
+{
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+
+ component_master_del(&cldev->dev, &mei_component_master_ops);
+ kfree(comp_master);
+ mei_cldev_set_drvdata(cldev, NULL);
+
+ return mei_cldev_disable(cldev);
+}
+
+/* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/
+#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
+ 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
+
+static struct mei_cl_device_id mei_pxp_tbl[] = {
+ { .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY },
+ { }
+};
+MODULE_DEVICE_TABLE(mei, mei_pxp_tbl);
+
+static struct mei_cl_driver mei_pxp_driver = {
+ .id_table = mei_pxp_tbl,
+ .name = KBUILD_MODNAME,
+ .probe = mei_pxp_probe,
+ .remove = mei_pxp_remove,
+};
+
+module_mei_cl_driver(mei_pxp_driver);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MEI PXP");
diff --git a/drivers/misc/mei/pxp/mei_pxp.h b/drivers/misc/mei/pxp/mei_pxp.h
new file mode 100644
index 000000000000..e7b15373fefd
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef __MEI_PXP_H__
+#define __MEI_PXP_H__
+
+/* me_pxp_status: Enumeration of all PXP Status Codes */
+enum me_pxp_status {
+ ME_PXP_STATUS_SUCCESS = 0x0000,
+
+};
+
+#endif /* __MEI_PXP_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [RFC-v23 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (9 preceding siblings ...)
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 10/13] mei: pxp: export pavp client to me client bus Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 12/13] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
` (4 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav, Matthew Auld, Bommu Krishnaiah
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
rev21:
- Fix "Fi.CI.CHECKPATCH" warnings
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 41 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
include/uapi/drm/i915_drm.h | 47 ++++++++++++++++++++++
3 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 45d60e3d98e3..3ad3413c459f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -7,6 +7,7 @@
#include "gem/i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_user_extensions.h"
static int
i915_gem_create(struct drm_file *file,
@@ -91,6 +92,35 @@ i915_gem_dumb_create(struct drm_file *file,
&args->size, &args->handle);
}
+struct create_ext {
+ struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -102,10 +132,19 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ return ret;
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 19db49206e0c..0e3d04c50f53 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1731,7 +1731,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 00fd1c2bcbb3..aa232ded9951 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -729,6 +730,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+ * Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ */
+ __u64 size;
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ __u32 pad;
+#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
+#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
+ (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
+ __u64 extensions;
+
+};
+
struct drm_i915_gem_pread {
/** Handle for the object being read. */
__u32 handle;
@@ -1708,6 +1730,31 @@ struct drm_i915_gem_context_param {
__u64 value;
};
+struct drm_i915_gem_object_param {
+ /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
+ __u32 handle;
+
+ /* Data pointer size */
+ __u32 size;
+
+/*
+ * I915_OBJECT_PARAM:
+ *
+ * Select object namespace for the param.
+ */
+#define I915_OBJECT_PARAM (1ull << 32)
+
+ __u64 param;
+
+ /* Data value or pointer */
+ __u64 data;
+};
+
+struct drm_i915_gem_create_ext_setparam {
+ struct i915_user_extension base;
+ struct drm_i915_gem_object_param param;
+};
+
/**
* Context SSEU programming
*
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [RFC-v23 12/13] drm/i915/pxp: User interface for Protected buffer
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (10 preceding siblings ...)
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support Huang, Sean Z
` (3 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: kumar.gaurav, Huang Sean Z, Bommu Krishnaiah, Kondapally Kalyan
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
This api allow user mode to create Protected buffer and context creation.
rev21:
- Only allow set I915_CONTEXT_PARAM_PROTECTED_CONTENT during context
creation (i915_gem_context_create_ioctl), but not allow during
context set param (i915_gem_context_setparam_ioctl)
rev23:
- Require user space to explicitly set recoverable flag to
false for protected context creation.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
Cc: Huang Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 13 +++++++++
drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 ++++
drivers/gpu/drm/i915/gem/i915_gem_create.c | 27 ++++++++++++++++---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5 ++++
include/uapi/drm/i915_drm.h | 10 +++++++
5 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 4d2f40cf237b..2af1da45ce63 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -81,6 +81,8 @@
#include "i915_trace.h"
#include "i915_user_extensions.h"
+#include "pxp/intel_pxp.h"
+
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
static struct i915_global_gem_context {
@@ -2052,6 +2054,7 @@ static int create_setparam(struct i915_user_extension __user *ext, void *data)
{
struct drm_i915_gem_context_create_ext_setparam local;
const struct create_ext *arg = data;
+ int ret;
if (copy_from_user(&local, ext, sizeof(local)))
return -EFAULT;
@@ -2059,6 +2062,10 @@ static int create_setparam(struct i915_user_extension __user *ext, void *data)
if (local.param.ctx_id)
return -EINVAL;
+ ret = intel_pxp_gem_context_create_param(arg->ctx, &local.param);
+ if (ret)
+ return ret;
+
return ctx_setparam(arg->fpriv, arg->ctx, &local.param);
}
@@ -2328,6 +2335,12 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
goto err_ctx;
}
+ if (i915_gem_context_is_protected(ext_data.ctx))
+ if (!intel_pxp_gem_context_protected_param_valid(ext_data.ctx)) {
+ ret = -EINVAL;
+ goto err_ctx;
+ }
+
ret = gem_context_register(ext_data.ctx, ext_data.fpriv, &id);
if (ret < 0)
goto err_ctx;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index b5c908f3f4f2..173154fdc311 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,11 @@ static inline void i915_gem_context_set_recoverable(struct i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
}
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context *ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 3ad3413c459f..c9b83217a6da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -5,6 +5,7 @@
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_region.h"
+#include "pxp/intel_pxp.h"
#include "i915_drv.h"
#include "i915_user_extensions.h"
@@ -13,7 +14,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -35,6 +37,8 @@ i915_gem_create(struct drm_file *file,
GEM_BUG_ON(size != obj->base.size);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -89,11 +93,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
mem_type),
- &args->size, &args->handle);
+ &args->size, &args->handle, 0);
}
struct create_ext {
struct drm_i915_private *i915;
+ unsigned long user_flags;
};
static int __create_setparam(struct drm_i915_gem_object_param *args,
@@ -104,6 +109,17 @@ static int __create_setparam(struct drm_i915_gem_object_param *args,
return -EINVAL;
}
+ switch (lower_32_bits(args->param)) {
+ case I915_PARAM_PROTECTED_CONTENT:
+ if (args->size) {
+ return -EINVAL;
+ } else if (args->data) {
+ ext_data->user_flags = args->data;
+ return 0;
+ }
+ break;
+ }
+
return -EINVAL;
}
@@ -145,8 +161,13 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
if (ret)
return ret;
+ if (ext_data.user_flags & I915_BO_PROTECTED) {
+ if (!intel_pxp_gem_object_status(i915))
+ return -EINVAL;
+ }
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
- &args->size, &args->handle);
+ &args->size, &args->handle, ext_data.user_flags);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+ * @user_flags: small set of booleans set by the user
+ */
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index aa232ded9951..17a6e3545570 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1744,6 +1744,16 @@ struct drm_i915_gem_object_param {
*/
#define I915_OBJECT_PARAM (1ull << 32)
+/*
+ * I915_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true (1) buffer contents is expected to be protected by
+ * PAVP encryption and requires decryption for scan out and processing.
+ * Protected buffers can only be used in PAVP protected contexts.
+ * A protected buffer may become invalid as a result of PAVP teardown.
+ */
+#define I915_PARAM_PROTECTED_CONTENT 0x1
+
__u64 param;
/* Data value or pointer */
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (11 preceding siblings ...)
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 12/13] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
@ 2021-01-19 7:43 ` Huang, Sean Z
2021-01-19 9:35 ` Gupta, Anshuman
2021-01-19 12:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev23) Patchwork
` (2 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Huang, Sean Z @ 2021-01-19 7:43 UTC (permalink / raw)
To: Intel-gfx; +Cc: Bommu Krishnaiah, kumar.gaurav, Huang Sean Z
From: Anshuman Gupta <anshuman.gupta@intel.com>
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PXP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
v3:
- intel_pxp_gem_object_status() API changes.
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Huang Sean Z <sean.z.huang@intel.com>
Cc: Gaurav Kumar <kumar.gaurav@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index cf3589fd0ddb..39f8c922ce66 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include <drm/drm_plane_helper.h>
#include <drm/drm_rect.h>
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -768,6 +770,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -804,6 +811,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -814,7 +822,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -890,8 +898,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 97bcecada87f..7a4817054bc8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7208,6 +7208,7 @@ enum {
#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
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^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support Huang, Sean Z
@ 2021-01-19 9:35 ` Gupta, Anshuman
2021-01-21 20:30 ` Ville Syrjälä
0 siblings, 1 reply; 30+ messages in thread
From: Gupta, Anshuman @ 2021-01-19 9:35 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx, Nikula, Jani, Ville Syrjälä
Cc: Vetter, Daniel, Gaurav, Kumar, Bommu, Krishnaiah
Jani/Ville
I had received an offline comment form Gaurav on this patch,
See below,
> -----Original Message-----
> From: Huang, Sean Z <sean.z.huang@intel.com>
> Sent: Tuesday, January 19, 2021 1:13 PM
> To: Intel-gfx@lists.freedesktop.org
> Cc: Gaurav, Kumar <kumar.gaurav@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>; Bommu, Krishnaiah
> <krishnaiah.bommu@intel.com>; Huang, Sean Z <sean.z.huang@intel.com>
> Subject: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
>
> From: Anshuman Gupta <anshuman.gupta@intel.com>
>
> Add support to enable/disable PLANE_SURF Decryption Request bit.
> It requires only to enable plane decryption support when following
> condition met.
> 1. PXP session is enabled.
> 2. Buffer object is protected.
>
> v2:
> - Rebased to libva_cp-drm-tip_tgl_cp tree.
> - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
>
> v3:
> - intel_pxp_gem_object_status() API changes.
>
> Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Huang Sean Z <sean.z.huang@intel.com>
> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index cf3589fd0ddb..39f8c922ce66 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -39,6 +39,8 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_rect.h>
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_drv.h"
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> @@ -768,6 +770,11 @@ icl_program_input_csc(struct intel_plane *plane,
> PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2),
> 0x0); }
>
> +static bool intel_fb_obj_protected(const struct drm_i915_gem_object
> +*obj) {
> + return obj->user_flags & I915_BO_PROTECTED ? true : false; }
> +
> static void
> skl_plane_async_flip(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state, @@ -804,6
> +811,7 @@ skl_program_plane(struct intel_plane *plane,
> u32 surf_addr = plane_state->color_plane[color_plane].offset;
> u32 stride = skl_plane_stride(plane_state, color_plane);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> + const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> int aux_plane = intel_main_to_aux_plane(fb, color_plane);
> int crtc_x = plane_state->uapi.dst.x1;
> int crtc_y = plane_state->uapi.dst.y1; @@ -814,7 +822,7 @@
> skl_program_plane(struct intel_plane *plane,
> u8 alpha = plane_state->hw.alpha >> 8;
> u32 plane_color_ctl = 0, aux_dist = 0;
> unsigned long irqflags;
> - u32 keymsk, keymax;
> + u32 keymsk, keymax, plane_surf;
> u32 plane_ctl = plane_state->ctl;
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -890,8 +898,15
> @@ skl_program_plane(struct intel_plane *plane,
> * the control register just before the surface register.
> */
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> - intel_plane_ggtt_offset(plane_state) + surf_addr);
> + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> +
> + if (intel_pxp_gem_object_status(dev_priv) &&
> + intel_fb_obj_protected(obj))
> + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
Here in case of if fb obj is protected but pxp session is not enabled i.e intel_pxp_gem_object_status() returns false, request to show the black frame buffer on display instead of corrupted data.
plane_surf = 0xXXX; //Pointer to black framebuffer
But above approach would be a hack.
@Jani and @Ville could you please guide with the general way of handling this as pxp session keys can be invalidated at any time.
Thanks,
Anshuman Gupta.
> + else
> + plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
> +
> + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> plane_surf);
>
> if (plane_state->scaler_id >= 0)
> skl_program_scaler(plane, crtc_state, plane_state); diff --git
> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 97bcecada87f..7a4817054bc8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7208,6 +7208,7 @@ enum {
> #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A,
> _PLANE_SURF_3_B)
> #define PLANE_SURF(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_SURF_1(pipe),
> _PLANE_SURF_2(pipe))
> +#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
>
> #define _PLANE_OFFSET_1_B 0x711a4
> #define _PLANE_OFFSET_2_B 0x712a4
> --
> 2.17.1
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^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
2021-01-19 9:35 ` Gupta, Anshuman
@ 2021-01-21 20:30 ` Ville Syrjälä
2021-01-21 20:50 ` Gaurav, Kumar
0 siblings, 1 reply; 30+ messages in thread
From: Ville Syrjälä @ 2021-01-21 20:30 UTC (permalink / raw)
To: Gupta, Anshuman
Cc: Nikula, Jani, Gaurav, Kumar, Intel-gfx, Huang, Sean Z, Bommu,
Krishnaiah, Vetter, Daniel
On Tue, Jan 19, 2021 at 09:35:18AM +0000, Gupta, Anshuman wrote:
> Jani/Ville
> I had received an offline comment form Gaurav on this patch,
> See below,
> > -----Original Message-----
> > From: Huang, Sean Z <sean.z.huang@intel.com>
> > Sent: Tuesday, January 19, 2021 1:13 PM
> > To: Intel-gfx@lists.freedesktop.org
> > Cc: Gaurav, Kumar <kumar.gaurav@intel.com>; Gupta, Anshuman
> > <anshuman.gupta@intel.com>; Bommu, Krishnaiah
> > <krishnaiah.bommu@intel.com>; Huang, Sean Z <sean.z.huang@intel.com>
> > Subject: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
> >
> > From: Anshuman Gupta <anshuman.gupta@intel.com>
> >
> > Add support to enable/disable PLANE_SURF Decryption Request bit.
> > It requires only to enable plane decryption support when following
> > condition met.
> > 1. PXP session is enabled.
> > 2. Buffer object is protected.
> >
> > v2:
> > - Rebased to libva_cp-drm-tip_tgl_cp tree.
> > - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
> >
> > v3:
> > - intel_pxp_gem_object_status() API changes.
> >
> > Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > Cc: Huang Sean Z <sean.z.huang@intel.com>
> > Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 19 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index cf3589fd0ddb..39f8c922ce66 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -39,6 +39,8 @@
> > #include <drm/drm_plane_helper.h>
> > #include <drm/drm_rect.h>
> >
> > +#include "pxp/intel_pxp.h"
> > +
> > #include "i915_drv.h"
> > #include "i915_trace.h"
> > #include "i915_vgpu.h"
> > @@ -768,6 +770,11 @@ icl_program_input_csc(struct intel_plane *plane,
> > PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2),
> > 0x0); }
> >
> > +static bool intel_fb_obj_protected(const struct drm_i915_gem_object
> > +*obj) {
> > + return obj->user_flags & I915_BO_PROTECTED ? true : false; }
> > +
> > static void
> > skl_plane_async_flip(struct intel_plane *plane,
> > const struct intel_crtc_state *crtc_state, @@ -804,6
> > +811,7 @@ skl_program_plane(struct intel_plane *plane,
> > u32 surf_addr = plane_state->color_plane[color_plane].offset;
> > u32 stride = skl_plane_stride(plane_state, color_plane);
> > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > + const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> > int aux_plane = intel_main_to_aux_plane(fb, color_plane);
> > int crtc_x = plane_state->uapi.dst.x1;
> > int crtc_y = plane_state->uapi.dst.y1; @@ -814,7 +822,7 @@
> > skl_program_plane(struct intel_plane *plane,
> > u8 alpha = plane_state->hw.alpha >> 8;
> > u32 plane_color_ctl = 0, aux_dist = 0;
> > unsigned long irqflags;
> > - u32 keymsk, keymax;
> > + u32 keymsk, keymax, plane_surf;
> > u32 plane_ctl = plane_state->ctl;
> >
> > plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -890,8 +898,15
> > @@ skl_program_plane(struct intel_plane *plane,
> > * the control register just before the surface register.
> > */
> > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > - intel_plane_ggtt_offset(plane_state) + surf_addr);
> > + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > +
> > + if (intel_pxp_gem_object_status(dev_priv) &&
> > + intel_fb_obj_protected(obj))
> > + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> Here in case of if fb obj is protected but pxp session is not enabled i.e intel_pxp_gem_object_status() returns false, request to show the black frame buffer on display instead of corrupted data.
> plane_surf = 0xXXX; //Pointer to black framebuffer
> But above approach would be a hack.
> @Jani and @Ville could you please guide with the general way of handling this as pxp session keys can be invalidated at any time.
Would need such a black buffer to be always pinned into the gtt, which
is seems a bit wasteful. We could perhaps just force the plane to output
black eg. by using the plane gamma. I think we should always have the
per-plane gamma available on skl+ universal planes. Cursor may be a
different story.
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
2021-01-21 20:30 ` Ville Syrjälä
@ 2021-01-21 20:50 ` Gaurav, Kumar
2021-01-21 21:00 ` Ville Syrjälä
0 siblings, 1 reply; 30+ messages in thread
From: Gaurav, Kumar @ 2021-01-21 20:50 UTC (permalink / raw)
To: Ville Syrjälä, Gupta, Anshuman
Cc: Nikula, Jani, Bommu, Krishnaiah, Intel-gfx, Huang, Sean Z,
Vetter, Daniel
Thanks Anshuman for adding me for review.
Actually, using plane Gamma is good idea to show black frame. Another option could be alpha value since we know for ChromeOS protected buffer will always be flipped on overlays.
Below explanation captures need for black frame in i915 Display for HWDRM protected surfaces -
Problem Statement -
There is race condition between Ring3 and Ring0 where encrypted frame could be flipped by i915 Display despite Ring3 checking if HWDRM session keys are valid for encrypted frame.
Google Bug -
BUG1 -[Intel] i915 framebuffer tracking (protected surfaces that can't be decrypted are being rendered as encrypted) -b/155511255
Background -
There are 4 high level pipelines working together in HWDRM playback.
1. CDM Pipeline -
App CDM SW Stack -> LibVA/iHD -> i915 -> MEI -> CSME-FW
2. Media(Audio/Video) Pipeline
App Media SW Stack -> LibVA/iHD -> i915 -> GPU
3. 3D Pipeline in Compositor
App Composition SW Stack -> OpenGL/MESA/MiniGBM -> i915 -> GPU/Display
4. Display Pipeline in Compositor
App Composition SW Stack -> Ozone/MiniGBM -> i915 -> Display
Discussion Point -
Even after Pipeline #4 is context robustness compliant there is a corner case/race condition for corruption as following - BUG1
App's Composition SW Stack -> Creates Protected Context and Protected Buffer(MiniGBM)
App's Composition SW Stack -> Supplies Protected Buffer to LibVA/iHD -> i915 -> GPU -> Encrypted decoded output
App's Composition SW Stack -> Gets back decode output -> Checks for context robustness -> Submits frame for flip -> i915 Display(by the time i915 Display gets flip PAVP session is invalid despite being atomic since invalidation of PAVP is HW async event) -> Display HW -> Shows corruption
-----Original Message-----
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Sent: Thursday, January 21, 2021 12:31 PM
To: Gupta, Anshuman <anshuman.gupta@intel.com>
Cc: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>; Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Vetter, Daniel <daniel.vetter@intel.com>
Subject: Re: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
On Tue, Jan 19, 2021 at 09:35:18AM +0000, Gupta, Anshuman wrote:
> Jani/Ville
> I had received an offline comment form Gaurav on this patch, See
> below,
> > -----Original Message-----
> > From: Huang, Sean Z <sean.z.huang@intel.com>
> > Sent: Tuesday, January 19, 2021 1:13 PM
> > To: Intel-gfx@lists.freedesktop.org
> > Cc: Gaurav, Kumar <kumar.gaurav@intel.com>; Gupta, Anshuman
> > <anshuman.gupta@intel.com>; Bommu, Krishnaiah
> > <krishnaiah.bommu@intel.com>; Huang, Sean Z <sean.z.huang@intel.com>
> > Subject: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
> >
> > From: Anshuman Gupta <anshuman.gupta@intel.com>
> >
> > Add support to enable/disable PLANE_SURF Decryption Request bit.
> > It requires only to enable plane decryption support when following
> > condition met.
> > 1. PXP session is enabled.
> > 2. Buffer object is protected.
> >
> > v2:
> > - Rebased to libva_cp-drm-tip_tgl_cp tree.
> > - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
> >
> > v3:
> > - intel_pxp_gem_object_status() API changes.
> >
> > Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > Cc: Huang Sean Z <sean.z.huang@intel.com>
> > Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 19 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index cf3589fd0ddb..39f8c922ce66 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -39,6 +39,8 @@
> > #include <drm/drm_plane_helper.h>
> > #include <drm/drm_rect.h>
> >
> > +#include "pxp/intel_pxp.h"
> > +
> > #include "i915_drv.h"
> > #include "i915_trace.h"
> > #include "i915_vgpu.h"
> > @@ -768,6 +770,11 @@ icl_program_input_csc(struct intel_plane *plane,
> > PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); }
> >
> > +static bool intel_fb_obj_protected(const struct drm_i915_gem_object
> > +*obj) {
> > + return obj->user_flags & I915_BO_PROTECTED ? true : false; }
> > +
> > static void
> > skl_plane_async_flip(struct intel_plane *plane,
> > const struct intel_crtc_state *crtc_state, @@ -804,6
> > +811,7 @@ skl_program_plane(struct intel_plane *plane,
> > u32 surf_addr = plane_state->color_plane[color_plane].offset;
> > u32 stride = skl_plane_stride(plane_state, color_plane);
> > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > + const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> > int aux_plane = intel_main_to_aux_plane(fb, color_plane);
> > int crtc_x = plane_state->uapi.dst.x1;
> > int crtc_y = plane_state->uapi.dst.y1; @@ -814,7 +822,7 @@
> > skl_program_plane(struct intel_plane *plane,
> > u8 alpha = plane_state->hw.alpha >> 8;
> > u32 plane_color_ctl = 0, aux_dist = 0;
> > unsigned long irqflags;
> > - u32 keymsk, keymax;
> > + u32 keymsk, keymax, plane_surf;
> > u32 plane_ctl = plane_state->ctl;
> >
> > plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -890,8 +898,15 @@
> > skl_program_plane(struct intel_plane *plane,
> > * the control register just before the surface register.
> > */
> > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > - intel_plane_ggtt_offset(plane_state) + surf_addr);
> > + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > +
> > + if (intel_pxp_gem_object_status(dev_priv) &&
> > + intel_fb_obj_protected(obj))
> > + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> Here in case of if fb obj is protected but pxp session is not enabled i.e intel_pxp_gem_object_status() returns false, request to show the black frame buffer on display instead of corrupted data.
> plane_surf = 0xXXX; //Pointer to black
> framebuffer But above approach would be a hack.
> @Jani and @Ville could you please guide with the general way of handling this as pxp session keys can be invalidated at any time.
Would need such a black buffer to be always pinned into the gtt, which is seems a bit wasteful. We could perhaps just force the plane to output black eg. by using the plane gamma. I think we should always have the per-plane gamma available on skl+ universal planes. Cursor may be a different story.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
2021-01-21 20:50 ` Gaurav, Kumar
@ 2021-01-21 21:00 ` Ville Syrjälä
2021-01-21 21:34 ` Gaurav, Kumar
0 siblings, 1 reply; 30+ messages in thread
From: Ville Syrjälä @ 2021-01-21 21:00 UTC (permalink / raw)
To: Gaurav, Kumar
Cc: Nikula, Jani, Intel-gfx, Huang, Sean Z, Bommu, Krishnaiah,
Vetter, Daniel
On Thu, Jan 21, 2021 at 08:50:18PM +0000, Gaurav, Kumar wrote:
> Thanks Anshuman for adding me for review.
>
> Actually, using plane Gamma is good idea to show black frame. Another option could be alpha value since we know for ChromeOS protected buffer will always be flipped on overlays.
>
> Below explanation captures need for black frame in i915 Display for HWDRM protected surfaces -
> Problem Statement -
> There is race condition between Ring3 and Ring0 where encrypted frame could be flipped by i915 Display despite Ring3 checking if HWDRM session keys are valid for encrypted frame.
>
> Google Bug -
> BUG1 -[Intel] i915 framebuffer tracking (protected surfaces that can't be decrypted are being rendered as encrypted) -b/155511255
>
> Background -
> There are 4 high level pipelines working together in HWDRM playback.
> 1. CDM Pipeline -
> App CDM SW Stack -> LibVA/iHD -> i915 -> MEI -> CSME-FW
>
> 2. Media(Audio/Video) Pipeline
> App Media SW Stack -> LibVA/iHD -> i915 -> GPU
>
> 3. 3D Pipeline in Compositor
> App Composition SW Stack -> OpenGL/MESA/MiniGBM -> i915 -> GPU/Display
>
> 4. Display Pipeline in Compositor
> App Composition SW Stack -> Ozone/MiniGBM -> i915 -> Display
>
> Discussion Point -
> Even after Pipeline #4 is context robustness compliant there is a corner case/race condition for corruption as following - BUG1
> App's Composition SW Stack -> Creates Protected Context and Protected Buffer(MiniGBM)
> App's Composition SW Stack -> Supplies Protected Buffer to LibVA/iHD -> i915 -> GPU -> Encrypted decoded output
> App's Composition SW Stack -> Gets back decode output -> Checks for context robustness -> Submits frame for flip -> i915 Display(by the time i915 Display gets flip PAVP session is invalid despite being atomic since invalidation of PAVP is HW async event) -> Display HW -> Shows corruption
It'll always be racy unless the invalidation becomes a two stage process
that first tells display to stop scanning out the thing and then waits
for the display to finish scanning out the current frame.
>
>
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Thursday, January 21, 2021 12:31 PM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> Cc: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>; Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Vetter, Daniel <daniel.vetter@intel.com>
> Subject: Re: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
>
> On Tue, Jan 19, 2021 at 09:35:18AM +0000, Gupta, Anshuman wrote:
> > Jani/Ville
> > I had received an offline comment form Gaurav on this patch, See
> > below,
> > > -----Original Message-----
> > > From: Huang, Sean Z <sean.z.huang@intel.com>
> > > Sent: Tuesday, January 19, 2021 1:13 PM
> > > To: Intel-gfx@lists.freedesktop.org
> > > Cc: Gaurav, Kumar <kumar.gaurav@intel.com>; Gupta, Anshuman
> > > <anshuman.gupta@intel.com>; Bommu, Krishnaiah
> > > <krishnaiah.bommu@intel.com>; Huang, Sean Z <sean.z.huang@intel.com>
> > > Subject: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
> > >
> > > From: Anshuman Gupta <anshuman.gupta@intel.com>
> > >
> > > Add support to enable/disable PLANE_SURF Decryption Request bit.
> > > It requires only to enable plane decryption support when following
> > > condition met.
> > > 1. PXP session is enabled.
> > > 2. Buffer object is protected.
> > >
> > > v2:
> > > - Rebased to libva_cp-drm-tip_tgl_cp tree.
> > > - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
> > >
> > > v3:
> > > - intel_pxp_gem_object_status() API changes.
> > >
> > > Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > > Cc: Huang Sean Z <sean.z.huang@intel.com>
> > > Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > 2 files changed, 19 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > index cf3589fd0ddb..39f8c922ce66 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > @@ -39,6 +39,8 @@
> > > #include <drm/drm_plane_helper.h>
> > > #include <drm/drm_rect.h>
> > >
> > > +#include "pxp/intel_pxp.h"
> > > +
> > > #include "i915_drv.h"
> > > #include "i915_trace.h"
> > > #include "i915_vgpu.h"
> > > @@ -768,6 +770,11 @@ icl_program_input_csc(struct intel_plane *plane,
> > > PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); }
> > >
> > > +static bool intel_fb_obj_protected(const struct drm_i915_gem_object
> > > +*obj) {
> > > + return obj->user_flags & I915_BO_PROTECTED ? true : false; }
> > > +
> > > static void
> > > skl_plane_async_flip(struct intel_plane *plane,
> > > const struct intel_crtc_state *crtc_state, @@ -804,6
> > > +811,7 @@ skl_program_plane(struct intel_plane *plane,
> > > u32 surf_addr = plane_state->color_plane[color_plane].offset;
> > > u32 stride = skl_plane_stride(plane_state, color_plane);
> > > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > + const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> > > int aux_plane = intel_main_to_aux_plane(fb, color_plane);
> > > int crtc_x = plane_state->uapi.dst.x1;
> > > int crtc_y = plane_state->uapi.dst.y1; @@ -814,7 +822,7 @@
> > > skl_program_plane(struct intel_plane *plane,
> > > u8 alpha = plane_state->hw.alpha >> 8;
> > > u32 plane_color_ctl = 0, aux_dist = 0;
> > > unsigned long irqflags;
> > > - u32 keymsk, keymax;
> > > + u32 keymsk, keymax, plane_surf;
> > > u32 plane_ctl = plane_state->ctl;
> > >
> > > plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -890,8 +898,15 @@
> > > skl_program_plane(struct intel_plane *plane,
> > > * the control register just before the surface register.
> > > */
> > > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > > - intel_plane_ggtt_offset(plane_state) + surf_addr);
> > > + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > > +
> > > + if (intel_pxp_gem_object_status(dev_priv) &&
> > > + intel_fb_obj_protected(obj))
> > > + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> > Here in case of if fb obj is protected but pxp session is not enabled i.e intel_pxp_gem_object_status() returns false, request to show the black frame buffer on display instead of corrupted data.
> > plane_surf = 0xXXX; //Pointer to black
> > framebuffer But above approach would be a hack.
> > @Jani and @Ville could you please guide with the general way of handling this as pxp session keys can be invalidated at any time.
>
> Would need such a black buffer to be always pinned into the gtt, which is seems a bit wasteful. We could perhaps just force the plane to output black eg. by using the plane gamma. I think we should always have the per-plane gamma available on skl+ universal planes. Cursor may be a different story.
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
2021-01-21 21:00 ` Ville Syrjälä
@ 2021-01-21 21:34 ` Gaurav, Kumar
2021-01-22 11:58 ` Ville Syrjälä
0 siblings, 1 reply; 30+ messages in thread
From: Gaurav, Kumar @ 2021-01-21 21:34 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Nikula, Jani, Intel-gfx, Huang, Sean Z, Bommu, Krishnaiah,
Vetter, Daniel
So the idea is to perform HWDRM session check in flip IRQL and i915 PXP will guarantee that IRQL is not blocked.
We have done similar check in Windows flip IRQL.
-----Original Message-----
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Sent: Thursday, January 21, 2021 1:00 PM
To: Gaurav, Kumar <kumar.gaurav@intel.com>
Cc: Gupta, Anshuman <anshuman.gupta@intel.com>; Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>; Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Vetter, Daniel <daniel.vetter@intel.com>
Subject: Re: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
On Thu, Jan 21, 2021 at 08:50:18PM +0000, Gaurav, Kumar wrote:
> Thanks Anshuman for adding me for review.
>
> Actually, using plane Gamma is good idea to show black frame. Another option could be alpha value since we know for ChromeOS protected buffer will always be flipped on overlays.
>
> Below explanation captures need for black frame in i915 Display for
> HWDRM protected surfaces - Problem Statement - There is race condition
> between Ring3 and Ring0 where encrypted frame could be flipped by i915 Display despite Ring3 checking if HWDRM session keys are valid for encrypted frame.
>
> Google Bug -
> BUG1 -[Intel] i915 framebuffer tracking (protected surfaces that can't
> be decrypted are being rendered as encrypted) -b/155511255
>
> Background -
> There are 4 high level pipelines working together in HWDRM playback.
> 1. CDM Pipeline -
> App CDM SW Stack -> LibVA/iHD -> i915 -> MEI -> CSME-FW
>
> 2. Media(Audio/Video) Pipeline
> App Media SW Stack -> LibVA/iHD -> i915 -> GPU
>
> 3. 3D Pipeline in Compositor
> App Composition SW Stack -> OpenGL/MESA/MiniGBM -> i915 -> GPU/Display
>
> 4. Display Pipeline in Compositor
> App Composition SW Stack -> Ozone/MiniGBM -> i915 -> Display
>
> Discussion Point -
> Even after Pipeline #4 is context robustness compliant there is a
> corner case/race condition for corruption as following - BUG1 App's
> Composition SW Stack -> Creates Protected Context and Protected
> Buffer(MiniGBM) App's Composition SW Stack -> Supplies Protected
> Buffer to LibVA/iHD -> i915 -> GPU -> Encrypted decoded output App's
> Composition SW Stack -> Gets back decode output -> Checks for context
> robustness -> Submits frame for flip -> i915 Display(by the time i915
> Display gets flip PAVP session is invalid despite being atomic since
> invalidation of PAVP is HW async event) -> Display HW -> Shows
> corruption
It'll always be racy unless the invalidation becomes a two stage process that first tells display to stop scanning out the thing and then waits for the display to finish scanning out the current frame.
>
>
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Thursday, January 21, 2021 12:31 PM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> Cc: Huang, Sean Z <sean.z.huang@intel.com>;
> Intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> Gaurav, Kumar <kumar.gaurav@intel.com>; Bommu, Krishnaiah
> <krishnaiah.bommu@intel.com>; Vetter, Daniel <daniel.vetter@intel.com>
> Subject: Re: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption
> support
>
> On Tue, Jan 19, 2021 at 09:35:18AM +0000, Gupta, Anshuman wrote:
> > Jani/Ville
> > I had received an offline comment form Gaurav on this patch, See
> > below,
> > > -----Original Message-----
> > > From: Huang, Sean Z <sean.z.huang@intel.com>
> > > Sent: Tuesday, January 19, 2021 1:13 PM
> > > To: Intel-gfx@lists.freedesktop.org
> > > Cc: Gaurav, Kumar <kumar.gaurav@intel.com>; Gupta, Anshuman
> > > <anshuman.gupta@intel.com>; Bommu, Krishnaiah
> > > <krishnaiah.bommu@intel.com>; Huang, Sean Z
> > > <sean.z.huang@intel.com>
> > > Subject: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption
> > > support
> > >
> > > From: Anshuman Gupta <anshuman.gupta@intel.com>
> > >
> > > Add support to enable/disable PLANE_SURF Decryption Request bit.
> > > It requires only to enable plane decryption support when following
> > > condition met.
> > > 1. PXP session is enabled.
> > > 2. Buffer object is protected.
> > >
> > > v2:
> > > - Rebased to libva_cp-drm-tip_tgl_cp tree.
> > > - Used gen fb obj user_flags instead gem_object_metadata.
> > > [Krishna]
> > >
> > > v3:
> > > - intel_pxp_gem_object_status() API changes.
> > >
> > > Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > > Cc: Huang Sean Z <sean.z.huang@intel.com>
> > > Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > 2 files changed, 19 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > index cf3589fd0ddb..39f8c922ce66 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > @@ -39,6 +39,8 @@
> > > #include <drm/drm_plane_helper.h> #include <drm/drm_rect.h>
> > >
> > > +#include "pxp/intel_pxp.h"
> > > +
> > > #include "i915_drv.h"
> > > #include "i915_trace.h"
> > > #include "i915_vgpu.h"
> > > @@ -768,6 +770,11 @@ icl_program_input_csc(struct intel_plane *plane,
> > > PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); }
> > >
> > > +static bool intel_fb_obj_protected(const struct
> > > +drm_i915_gem_object
> > > +*obj) {
> > > + return obj->user_flags & I915_BO_PROTECTED ? true : false; }
> > > +
> > > static void
> > > skl_plane_async_flip(struct intel_plane *plane,
> > > const struct intel_crtc_state *crtc_state, @@ -804,6
> > > +811,7 @@ skl_program_plane(struct intel_plane *plane,
> > > u32 surf_addr = plane_state->color_plane[color_plane].offset;
> > > u32 stride = skl_plane_stride(plane_state, color_plane);
> > > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > + const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> > > int aux_plane = intel_main_to_aux_plane(fb, color_plane);
> > > int crtc_x = plane_state->uapi.dst.x1;
> > > int crtc_y = plane_state->uapi.dst.y1; @@ -814,7 +822,7 @@
> > > skl_program_plane(struct intel_plane *plane,
> > > u8 alpha = plane_state->hw.alpha >> 8;
> > > u32 plane_color_ctl = 0, aux_dist = 0;
> > > unsigned long irqflags;
> > > - u32 keymsk, keymax;
> > > + u32 keymsk, keymax, plane_surf;
> > > u32 plane_ctl = plane_state->ctl;
> > >
> > > plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -890,8 +898,15
> > > @@ skl_program_plane(struct intel_plane *plane,
> > > * the control register just before the surface register.
> > > */
> > > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > > - intel_plane_ggtt_offset(plane_state) + surf_addr);
> > > + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > > +
> > > + if (intel_pxp_gem_object_status(dev_priv) &&
> > > + intel_fb_obj_protected(obj))
> > > + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> > Here in case of if fb obj is protected but pxp session is not enabled i.e intel_pxp_gem_object_status() returns false, request to show the black frame buffer on display instead of corrupted data.
> > plane_surf = 0xXXX; //Pointer to black
> > framebuffer But above approach would be a hack.
> > @Jani and @Ville could you please guide with the general way of handling this as pxp session keys can be invalidated at any time.
>
> Would need such a black buffer to be always pinned into the gtt, which is seems a bit wasteful. We could perhaps just force the plane to output black eg. by using the plane gamma. I think we should always have the per-plane gamma available on skl+ universal planes. Cursor may be a different story.
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
2021-01-21 21:34 ` Gaurav, Kumar
@ 2021-01-22 11:58 ` Ville Syrjälä
2021-01-22 17:25 ` Gaurav, Kumar
0 siblings, 1 reply; 30+ messages in thread
From: Ville Syrjälä @ 2021-01-22 11:58 UTC (permalink / raw)
To: Gaurav, Kumar
Cc: Nikula, Jani, Intel-gfx, Huang, Sean Z, Bommu, Krishnaiah,
Vetter, Daniel
On Thu, Jan 21, 2021 at 09:34:53PM +0000, Gaurav, Kumar wrote:
> So the idea is to perform HWDRM session check in flip IRQL and i915 PXP will guarantee that IRQL is not blocked.
> We have done similar check in Windows flip IRQL.
>
What's an flip IRQL? Some sort of flip related irq handler?
a) we don't use the flip done interrupt (except for async flips), if
that's what you're referring to
b) how would doing anything there help against the race?
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Thursday, January 21, 2021 1:00 PM
> To: Gaurav, Kumar <kumar.gaurav@intel.com>
> Cc: Gupta, Anshuman <anshuman.gupta@intel.com>; Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>; Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Vetter, Daniel <daniel.vetter@intel.com>
> Subject: Re: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
>
> On Thu, Jan 21, 2021 at 08:50:18PM +0000, Gaurav, Kumar wrote:
> > Thanks Anshuman for adding me for review.
> >
> > Actually, using plane Gamma is good idea to show black frame. Another option could be alpha value since we know for ChromeOS protected buffer will always be flipped on overlays.
> >
> > Below explanation captures need for black frame in i915 Display for
> > HWDRM protected surfaces - Problem Statement - There is race condition
> > between Ring3 and Ring0 where encrypted frame could be flipped by i915 Display despite Ring3 checking if HWDRM session keys are valid for encrypted frame.
> >
> > Google Bug -
> > BUG1 -[Intel] i915 framebuffer tracking (protected surfaces that can't
> > be decrypted are being rendered as encrypted) -b/155511255
> >
> > Background -
> > There are 4 high level pipelines working together in HWDRM playback.
> > 1. CDM Pipeline -
> > App CDM SW Stack -> LibVA/iHD -> i915 -> MEI -> CSME-FW
> >
> > 2. Media(Audio/Video) Pipeline
> > App Media SW Stack -> LibVA/iHD -> i915 -> GPU
> >
> > 3. 3D Pipeline in Compositor
> > App Composition SW Stack -> OpenGL/MESA/MiniGBM -> i915 -> GPU/Display
> >
> > 4. Display Pipeline in Compositor
> > App Composition SW Stack -> Ozone/MiniGBM -> i915 -> Display
> >
> > Discussion Point -
> > Even after Pipeline #4 is context robustness compliant there is a
> > corner case/race condition for corruption as following - BUG1 App's
> > Composition SW Stack -> Creates Protected Context and Protected
> > Buffer(MiniGBM) App's Composition SW Stack -> Supplies Protected
> > Buffer to LibVA/iHD -> i915 -> GPU -> Encrypted decoded output App's
> > Composition SW Stack -> Gets back decode output -> Checks for context
> > robustness -> Submits frame for flip -> i915 Display(by the time i915
> > Display gets flip PAVP session is invalid despite being atomic since
> > invalidation of PAVP is HW async event) -> Display HW -> Shows
> > corruption
>
> It'll always be racy unless the invalidation becomes a two stage process that first tells display to stop scanning out the thing and then waits for the display to finish scanning out the current frame.
>
> >
> >
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: Thursday, January 21, 2021 12:31 PM
> > To: Gupta, Anshuman <anshuman.gupta@intel.com>
> > Cc: Huang, Sean Z <sean.z.huang@intel.com>;
> > Intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> > Gaurav, Kumar <kumar.gaurav@intel.com>; Bommu, Krishnaiah
> > <krishnaiah.bommu@intel.com>; Vetter, Daniel <daniel.vetter@intel.com>
> > Subject: Re: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption
> > support
> >
> > On Tue, Jan 19, 2021 at 09:35:18AM +0000, Gupta, Anshuman wrote:
> > > Jani/Ville
> > > I had received an offline comment form Gaurav on this patch, See
> > > below,
> > > > -----Original Message-----
> > > > From: Huang, Sean Z <sean.z.huang@intel.com>
> > > > Sent: Tuesday, January 19, 2021 1:13 PM
> > > > To: Intel-gfx@lists.freedesktop.org
> > > > Cc: Gaurav, Kumar <kumar.gaurav@intel.com>; Gupta, Anshuman
> > > > <anshuman.gupta@intel.com>; Bommu, Krishnaiah
> > > > <krishnaiah.bommu@intel.com>; Huang, Sean Z
> > > > <sean.z.huang@intel.com>
> > > > Subject: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption
> > > > support
> > > >
> > > > From: Anshuman Gupta <anshuman.gupta@intel.com>
> > > >
> > > > Add support to enable/disable PLANE_SURF Decryption Request bit.
> > > > It requires only to enable plane decryption support when following
> > > > condition met.
> > > > 1. PXP session is enabled.
> > > > 2. Buffer object is protected.
> > > >
> > > > v2:
> > > > - Rebased to libva_cp-drm-tip_tgl_cp tree.
> > > > - Used gen fb obj user_flags instead gem_object_metadata.
> > > > [Krishna]
> > > >
> > > > v3:
> > > > - intel_pxp_gem_object_status() API changes.
> > > >
> > > > Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > > > Cc: Huang Sean Z <sean.z.huang@intel.com>
> > > > Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
> > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > 2 files changed, 19 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > index cf3589fd0ddb..39f8c922ce66 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > @@ -39,6 +39,8 @@
> > > > #include <drm/drm_plane_helper.h> #include <drm/drm_rect.h>
> > > >
> > > > +#include "pxp/intel_pxp.h"
> > > > +
> > > > #include "i915_drv.h"
> > > > #include "i915_trace.h"
> > > > #include "i915_vgpu.h"
> > > > @@ -768,6 +770,11 @@ icl_program_input_csc(struct intel_plane *plane,
> > > > PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); }
> > > >
> > > > +static bool intel_fb_obj_protected(const struct
> > > > +drm_i915_gem_object
> > > > +*obj) {
> > > > + return obj->user_flags & I915_BO_PROTECTED ? true : false; }
> > > > +
> > > > static void
> > > > skl_plane_async_flip(struct intel_plane *plane,
> > > > const struct intel_crtc_state *crtc_state, @@ -804,6
> > > > +811,7 @@ skl_program_plane(struct intel_plane *plane,
> > > > u32 surf_addr = plane_state->color_plane[color_plane].offset;
> > > > u32 stride = skl_plane_stride(plane_state, color_plane);
> > > > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > > + const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> > > > int aux_plane = intel_main_to_aux_plane(fb, color_plane);
> > > > int crtc_x = plane_state->uapi.dst.x1;
> > > > int crtc_y = plane_state->uapi.dst.y1; @@ -814,7 +822,7 @@
> > > > skl_program_plane(struct intel_plane *plane,
> > > > u8 alpha = plane_state->hw.alpha >> 8;
> > > > u32 plane_color_ctl = 0, aux_dist = 0;
> > > > unsigned long irqflags;
> > > > - u32 keymsk, keymax;
> > > > + u32 keymsk, keymax, plane_surf;
> > > > u32 plane_ctl = plane_state->ctl;
> > > >
> > > > plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -890,8 +898,15
> > > > @@ skl_program_plane(struct intel_plane *plane,
> > > > * the control register just before the surface register.
> > > > */
> > > > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > > > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > > > - intel_plane_ggtt_offset(plane_state) + surf_addr);
> > > > + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > > > +
> > > > + if (intel_pxp_gem_object_status(dev_priv) &&
> > > > + intel_fb_obj_protected(obj))
> > > > + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> > > Here in case of if fb obj is protected but pxp session is not enabled i.e intel_pxp_gem_object_status() returns false, request to show the black frame buffer on display instead of corrupted data.
> > > plane_surf = 0xXXX; //Pointer to black
> > > framebuffer But above approach would be a hack.
> > > @Jani and @Ville could you please guide with the general way of handling this as pxp session keys can be invalidated at any time.
> >
> > Would need such a black buffer to be always pinned into the gtt, which is seems a bit wasteful. We could perhaps just force the plane to output black eg. by using the plane gamma. I think we should always have the per-plane gamma available on skl+ universal planes. Cursor may be a different story.
> >
> > --
> > Ville Syrjälä
> > Intel
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
2021-01-22 11:58 ` Ville Syrjälä
@ 2021-01-22 17:25 ` Gaurav, Kumar
0 siblings, 0 replies; 30+ messages in thread
From: Gaurav, Kumar @ 2021-01-22 17:25 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Nikula, Jani, Intel-gfx, Huang, Sean Z, Bommu, Krishnaiah,
Vetter, Daniel
a) How are you scheduling flips for ChromeOS HWDRM overlays(not primary planes)?
b) For this you need to understand race. The race is between - Display HW detecting that there is HDCP display config change and deciding to destroy crypto context vs. Display HW flipping HWDRM protected surface.
If Display HW decided to destroy crypto context then display HW does flip user will corruption but the check before flip makes sure that order is reversed i.e. no invalid crypto context flips are scheduled in Display HW.
-----Original Message-----
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Sent: Friday, January 22, 2021 3:59 AM
To: Gaurav, Kumar <kumar.gaurav@intel.com>
Cc: Gupta, Anshuman <anshuman.gupta@intel.com>; Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>; Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Vetter, Daniel <daniel.vetter@intel.com>
Subject: Re: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support
On Thu, Jan 21, 2021 at 09:34:53PM +0000, Gaurav, Kumar wrote:
> So the idea is to perform HWDRM session check in flip IRQL and i915 PXP will guarantee that IRQL is not blocked.
> We have done similar check in Windows flip IRQL.
>
What's an flip IRQL? Some sort of flip related irq handler?
a) we don't use the flip done interrupt (except for async flips), if
that's what you're referring to
b) how would doing anything there help against the race?
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Thursday, January 21, 2021 1:00 PM
> To: Gaurav, Kumar <kumar.gaurav@intel.com>
> Cc: Gupta, Anshuman <anshuman.gupta@intel.com>; Huang, Sean Z
> <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org; Nikula,
> Jani <jani.nikula@intel.com>; Bommu, Krishnaiah
> <krishnaiah.bommu@intel.com>; Vetter, Daniel <daniel.vetter@intel.com>
> Subject: Re: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption
> support
>
> On Thu, Jan 21, 2021 at 08:50:18PM +0000, Gaurav, Kumar wrote:
> > Thanks Anshuman for adding me for review.
> >
> > Actually, using plane Gamma is good idea to show black frame. Another option could be alpha value since we know for ChromeOS protected buffer will always be flipped on overlays.
> >
> > Below explanation captures need for black frame in i915 Display for
> > HWDRM protected surfaces - Problem Statement - There is race
> > condition between Ring3 and Ring0 where encrypted frame could be flipped by i915 Display despite Ring3 checking if HWDRM session keys are valid for encrypted frame.
> >
> > Google Bug -
> > BUG1 -[Intel] i915 framebuffer tracking (protected surfaces that
> > can't be decrypted are being rendered as encrypted) -b/155511255
> >
> > Background -
> > There are 4 high level pipelines working together in HWDRM playback.
> > 1. CDM Pipeline -
> > App CDM SW Stack -> LibVA/iHD -> i915 -> MEI -> CSME-FW
> >
> > 2. Media(Audio/Video) Pipeline
> > App Media SW Stack -> LibVA/iHD -> i915 -> GPU
> >
> > 3. 3D Pipeline in Compositor
> > App Composition SW Stack -> OpenGL/MESA/MiniGBM -> i915 ->
> > GPU/Display
> >
> > 4. Display Pipeline in Compositor
> > App Composition SW Stack -> Ozone/MiniGBM -> i915 -> Display
> >
> > Discussion Point -
> > Even after Pipeline #4 is context robustness compliant there is a
> > corner case/race condition for corruption as following - BUG1 App's
> > Composition SW Stack -> Creates Protected Context and Protected
> > Buffer(MiniGBM) App's Composition SW Stack -> Supplies Protected
> > Buffer to LibVA/iHD -> i915 -> GPU -> Encrypted decoded output App's
> > Composition SW Stack -> Gets back decode output -> Checks for
> > context robustness -> Submits frame for flip -> i915 Display(by the
> > time i915 Display gets flip PAVP session is invalid despite being
> > atomic since invalidation of PAVP is HW async event) -> Display HW
> > -> Shows corruption
>
> It'll always be racy unless the invalidation becomes a two stage process that first tells display to stop scanning out the thing and then waits for the display to finish scanning out the current frame.
>
> >
> >
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: Thursday, January 21, 2021 12:31 PM
> > To: Gupta, Anshuman <anshuman.gupta@intel.com>
> > Cc: Huang, Sean Z <sean.z.huang@intel.com>;
> > Intel-gfx@lists.freedesktop.org; Nikula, Jani
> > <jani.nikula@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>;
> > Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Vetter, Daniel
> > <daniel.vetter@intel.com>
> > Subject: Re: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption
> > support
> >
> > On Tue, Jan 19, 2021 at 09:35:18AM +0000, Gupta, Anshuman wrote:
> > > Jani/Ville
> > > I had received an offline comment form Gaurav on this patch, See
> > > below,
> > > > -----Original Message-----
> > > > From: Huang, Sean Z <sean.z.huang@intel.com>
> > > > Sent: Tuesday, January 19, 2021 1:13 PM
> > > > To: Intel-gfx@lists.freedesktop.org
> > > > Cc: Gaurav, Kumar <kumar.gaurav@intel.com>; Gupta, Anshuman
> > > > <anshuman.gupta@intel.com>; Bommu, Krishnaiah
> > > > <krishnaiah.bommu@intel.com>; Huang, Sean Z
> > > > <sean.z.huang@intel.com>
> > > > Subject: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption
> > > > support
> > > >
> > > > From: Anshuman Gupta <anshuman.gupta@intel.com>
> > > >
> > > > Add support to enable/disable PLANE_SURF Decryption Request bit.
> > > > It requires only to enable plane decryption support when
> > > > following condition met.
> > > > 1. PXP session is enabled.
> > > > 2. Buffer object is protected.
> > > >
> > > > v2:
> > > > - Rebased to libva_cp-drm-tip_tgl_cp tree.
> > > > - Used gen fb obj user_flags instead gem_object_metadata.
> > > > [Krishna]
> > > >
> > > > v3:
> > > > - intel_pxp_gem_object_status() API changes.
> > > >
> > > > Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > > > Cc: Huang Sean Z <sean.z.huang@intel.com>
> > > > Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
> > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > 2 files changed, 19 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > index cf3589fd0ddb..39f8c922ce66 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > @@ -39,6 +39,8 @@
> > > > #include <drm/drm_plane_helper.h> #include <drm/drm_rect.h>
> > > >
> > > > +#include "pxp/intel_pxp.h"
> > > > +
> > > > #include "i915_drv.h"
> > > > #include "i915_trace.h"
> > > > #include "i915_vgpu.h"
> > > > @@ -768,6 +770,11 @@ icl_program_input_csc(struct intel_plane *plane,
> > > > PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); }
> > > >
> > > > +static bool intel_fb_obj_protected(const struct
> > > > +drm_i915_gem_object
> > > > +*obj) {
> > > > + return obj->user_flags & I915_BO_PROTECTED ? true : false; }
> > > > +
> > > > static void
> > > > skl_plane_async_flip(struct intel_plane *plane,
> > > > const struct intel_crtc_state *crtc_state, @@ -804,6
> > > > +811,7 @@ skl_program_plane(struct intel_plane *plane,
> > > > u32 surf_addr = plane_state->color_plane[color_plane].offset;
> > > > u32 stride = skl_plane_stride(plane_state, color_plane);
> > > > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > > + const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> > > > int aux_plane = intel_main_to_aux_plane(fb, color_plane);
> > > > int crtc_x = plane_state->uapi.dst.x1;
> > > > int crtc_y = plane_state->uapi.dst.y1; @@ -814,7 +822,7 @@
> > > > skl_program_plane(struct intel_plane *plane,
> > > > u8 alpha = plane_state->hw.alpha >> 8;
> > > > u32 plane_color_ctl = 0, aux_dist = 0;
> > > > unsigned long irqflags;
> > > > - u32 keymsk, keymax;
> > > > + u32 keymsk, keymax, plane_surf;
> > > > u32 plane_ctl = plane_state->ctl;
> > > >
> > > > plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -890,8 +898,15
> > > > @@ skl_program_plane(struct intel_plane *plane,
> > > > * the control register just before the surface register.
> > > > */
> > > > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > > > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > > > - intel_plane_ggtt_offset(plane_state) + surf_addr);
> > > > + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > > > +
> > > > + if (intel_pxp_gem_object_status(dev_priv) &&
> > > > + intel_fb_obj_protected(obj))
> > > > + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> > > Here in case of if fb obj is protected but pxp session is not enabled i.e intel_pxp_gem_object_status() returns false, request to show the black frame buffer on display instead of corrupted data.
> > > plane_surf = 0xXXX; //Pointer to black
> > > framebuffer But above approach would be a hack.
> > > @Jani and @Ville could you please guide with the general way of handling this as pxp session keys can be invalidated at any time.
> >
> > Would need such a black buffer to be always pinned into the gtt, which is seems a bit wasteful. We could perhaps just force the plane to output black eg. by using the plane gamma. I think we should always have the per-plane gamma available on skl+ universal planes. Cursor may be a different story.
> >
> > --
> > Ville Syrjälä
> > Intel
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev23)
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (12 preceding siblings ...)
2021-01-19 7:43 ` [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support Huang, Sean Z
@ 2021-01-19 12:33 ` Patchwork
2021-01-19 13:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-01-23 14:18 ` [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Lionel Landwerlin
15 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2021-01-19 12:33 UTC (permalink / raw)
To: Gupta, Anshuman; +Cc: intel-gfx
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev23)
URL : https://patchwork.freedesktop.org/series/84620/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ca9c47130ec2 drm/i915/pxp: Introduce Intel PXP component
-:123: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#123:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 193 lines checked
187fcb952b02 drm/i915/pxp: set KCR reg init during the boot time
bdb7c62200bd drm/i915/pxp: Implement funcs to create the TEE channel
-:89: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#89:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 245 lines checked
ad259427e624 drm/i915/pxp: Create the arbitrary session after boot
-:47: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#47:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 271 lines checked
59fdff6af707 drm/i915/pxp: Func to send hardware session termination
-:61: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#61:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 188 lines checked
fa19c26fe841 drm/i915/pxp: Enable PXP irq worker and callback stub
b3ff2db1b43a drm/i915/pxp: Destroy arb session upon teardown
34248533ecd5 drm/i915/pxp: Enable PXP power management
-:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 148 lines checked
e9e96872b7b3 drm/i915/pxp: Expose session state for display protection flip
339c726f3313 mei: pxp: export pavp client to me client bus
-:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#32:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 277 lines checked
bce23b9235c4 drm/i915/uapi: introduce drm_i915_gem_create_ext
-:109: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#109: FILE: include/uapi/drm/i915_drm.h:395:
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
total: 0 errors, 1 warnings, 0 checks, 135 lines checked
35f7c19a2c16 drm/i915/pxp: User interface for Protected buffer
9df9f88c8a7b drm/i915/pxp: Add plane decryption support
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce Intel PXP component - Mesa single session (rev23)
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (13 preceding siblings ...)
2021-01-19 12:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev23) Patchwork
@ 2021-01-19 13:03 ` Patchwork
2021-01-23 14:18 ` [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Lionel Landwerlin
15 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2021-01-19 13:03 UTC (permalink / raw)
To: Gupta, Anshuman; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4980 bytes --]
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev23)
URL : https://patchwork.freedesktop.org/series/84620/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9640 -> Patchwork_19403
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19403 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19403, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19403/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19403:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gem_contexts:
- fi-byt-j1900: NOTRUN -> [DMESG-FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19403/fi-byt-j1900/igt@i915_selftest@live@gem_contexts.html
Known issues
------------
Here are the changes found in Patchwork_19403 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][2] ([fdo#109271]) +22 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19403/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][3] ([i915#2283])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19403/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-byt-j1900: NOTRUN -> [SKIP][4] ([fdo#109271]) +27 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19403/fi-byt-j1900/igt@gem_huc_copy@huc-copy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19403/fi-byt-j1900/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-j1900: NOTRUN -> [FAIL][6] ([i915#49])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19403/fi-byt-j1900/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_vgem@basic-read:
- fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9640/fi-tgl-y/igt@prime_vgem@basic-read.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19403/fi-tgl-y/igt@prime_vgem@basic-read.html
#### Possible fixes ####
* igt@prime_vgem@basic-fence-flip:
- fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9640/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19403/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
Participating hosts (42 -> 38)
------------------------------
Additional (1): fi-byt-j1900
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9640 -> Patchwork_19403
CI-20190529: 20190529
CI_DRM_9640: e4a7b069614eee3e01353d8529d5cf8b924feeec @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19403: 9df9f88c8a7b3c4034060b41bae3dfef19d7e9a3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9df9f88c8a7b drm/i915/pxp: Add plane decryption support
35f7c19a2c16 drm/i915/pxp: User interface for Protected buffer
bce23b9235c4 drm/i915/uapi: introduce drm_i915_gem_create_ext
339c726f3313 mei: pxp: export pavp client to me client bus
e9e96872b7b3 drm/i915/pxp: Expose session state for display protection flip
34248533ecd5 drm/i915/pxp: Enable PXP power management
b3ff2db1b43a drm/i915/pxp: Destroy arb session upon teardown
fa19c26fe841 drm/i915/pxp: Enable PXP irq worker and callback stub
59fdff6af707 drm/i915/pxp: Func to send hardware session termination
ad259427e624 drm/i915/pxp: Create the arbitrary session after boot
bdb7c62200bd drm/i915/pxp: Implement funcs to create the TEE channel
187fcb952b02 drm/i915/pxp: set KCR reg init during the boot time
ca9c47130ec2 drm/i915/pxp: Introduce Intel PXP component
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19403/index.html
[-- Attachment #1.2: Type: text/html, Size: 6062 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session
2021-01-19 7:43 [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (14 preceding siblings ...)
2021-01-19 13:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2021-01-23 14:18 ` Lionel Landwerlin
2021-01-23 21:47 ` Gaurav, Kumar
15 siblings, 1 reply; 30+ messages in thread
From: Lionel Landwerlin @ 2021-01-23 14:18 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx; +Cc: Jason Ekstrand, kumar.gaurav, Lahtinen, Joonas
Hi,
One of the thing that came up during UMD review is that the default
session ID is actually uAPI :
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8064#note_776201
Could we expose it through a get_param on the context?
Thanks,
-Lionel
On 19/01/2021 09:43, Huang, Sean Z wrote:
> PXP (Protected Xe Path) is an i915 component, available on
> GEN12+ that helps to establish the hardware protected session
> and manage the status of the alive software session, as well
> as its life cycle.
>
> This patch series is to allow the kernel space to create and
> manage a single hardware session (a.k.a. default session or
> arbitrary session). So user can allocate the protected buffer,
> which is encrypted with the leverage of the arbitrary hardware
> session.
>
>
> rev23:
> #09, #12
> - Require user space to explicitly set recoverable flag to
> false for protected context creation.
>
> #13
> - Add Cc of reviewers in commit message.
>
>
> Anshuman Gupta (1):
> drm/i915/pxp: Add plane decryption support
>
> Bommu Krishnaiah (2):
> drm/i915/uapi: introduce drm_i915_gem_create_ext
> drm/i915/pxp: User interface for Protected buffer
>
> Huang, Sean Z (9):
> drm/i915/pxp: Introduce Intel PXP component
> drm/i915/pxp: set KCR reg init during the boot time
> drm/i915/pxp: Implement funcs to create the TEE channel
> drm/i915/pxp: Create the arbitrary session after boot
> drm/i915/pxp: Func to send hardware session termination
> drm/i915/pxp: Enable PXP irq worker and callback stub
> drm/i915/pxp: Destroy arb session upon teardown
> drm/i915/pxp: Enable PXP power management
> drm/i915/pxp: Expose session state for display protection flip
>
> Vitaly Lubart (1):
> mei: pxp: export pavp client to me client bus
>
> drivers/gpu/drm/i915/Kconfig | 21 ++
> drivers/gpu/drm/i915/Makefile | 9 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 13 +
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 +
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 68 +++++-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 14 ++
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> drivers/gpu/drm/i915/i915_drv.c | 7 +-
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 193 +++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 70 ++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 208 ++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 17 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 223 +++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 19 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 28 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 +++++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 202 +++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 38 +++
> drivers/misc/mei/Kconfig | 2 +
> drivers/misc/mei/Makefile | 1 +
> drivers/misc/mei/pxp/Kconfig | 13 +
> drivers/misc/mei/pxp/Makefile | 7 +
> drivers/misc/mei/pxp/mei_pxp.c | 230 ++++++++++++++++++
> drivers/misc/mei/pxp/mei_pxp.h | 18 ++
> include/drm/i915_component.h | 1 +
> include/drm/i915_pxp_tee_interface.h | 45 ++++
> include/uapi/drm/i915_drm.h | 66 +++++
> 37 files changed, 1686 insertions(+), 8 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> create mode 100644 drivers/misc/mei/pxp/Kconfig
> create mode 100644 drivers/misc/mei/pxp/Makefile
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
> create mode 100644 include/drm/i915_pxp_tee_interface.h
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session
2021-01-23 14:18 ` [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session Lionel Landwerlin
@ 2021-01-23 21:47 ` Gaurav, Kumar
2021-01-25 15:38 ` Lionel Landwerlin
0 siblings, 1 reply; 30+ messages in thread
From: Gaurav, Kumar @ 2021-01-23 21:47 UTC (permalink / raw)
To: Landwerlin, Lionel G, Huang, Sean Z, Intel-gfx
Cc: Ekstrand, Jason, Lahtinen, Joonas
Yes, this should not be problem since MESA is already using MI_SET_APPID with app_id 0xf.
I proposed this earlier but I was told that MESA team will not be comfortable in querying app_id or session_states.
Although check for proper session_state should be part of context robustness check.
-----Original Message-----
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Sent: Saturday, January 23, 2021 6:19 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Cc: Gaurav, Kumar <kumar.gaurav@intel.com>; Lahtinen, Joonas <joonas.lahtinen@intel.com>; Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Ekstrand, Jason <jason.ekstrand@intel.com>
Subject: Re: [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session
Hi,
One of the thing that came up during UMD review is that the default session ID is actually uAPI :
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8064#note_776201
Could we expose it through a get_param on the context?
Thanks,
-Lionel
On 19/01/2021 09:43, Huang, Sean Z wrote:
> PXP (Protected Xe Path) is an i915 component, available on
> GEN12+ that helps to establish the hardware protected session
> and manage the status of the alive software session, as well as its
> life cycle.
>
> This patch series is to allow the kernel space to create and manage a
> single hardware session (a.k.a. default session or arbitrary session).
> So user can allocate the protected buffer, which is encrypted with the
> leverage of the arbitrary hardware session.
>
>
> rev23:
> #09, #12
> - Require user space to explicitly set recoverable flag to
> false for protected context creation.
>
> #13
> - Add Cc of reviewers in commit message.
>
>
> Anshuman Gupta (1):
> drm/i915/pxp: Add plane decryption support
>
> Bommu Krishnaiah (2):
> drm/i915/uapi: introduce drm_i915_gem_create_ext
> drm/i915/pxp: User interface for Protected buffer
>
> Huang, Sean Z (9):
> drm/i915/pxp: Introduce Intel PXP component
> drm/i915/pxp: set KCR reg init during the boot time
> drm/i915/pxp: Implement funcs to create the TEE channel
> drm/i915/pxp: Create the arbitrary session after boot
> drm/i915/pxp: Func to send hardware session termination
> drm/i915/pxp: Enable PXP irq worker and callback stub
> drm/i915/pxp: Destroy arb session upon teardown
> drm/i915/pxp: Enable PXP power management
> drm/i915/pxp: Expose session state for display protection flip
>
> Vitaly Lubart (1):
> mei: pxp: export pavp client to me client bus
>
> drivers/gpu/drm/i915/Kconfig | 21 ++
> drivers/gpu/drm/i915/Makefile | 9 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 13 +
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 +
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 68 +++++-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 14 ++
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> drivers/gpu/drm/i915/i915_drv.c | 7 +-
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 193 +++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 70 ++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 208 ++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 17 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 223 +++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 19 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 28 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 +++++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 202 +++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 38 +++
> drivers/misc/mei/Kconfig | 2 +
> drivers/misc/mei/Makefile | 1 +
> drivers/misc/mei/pxp/Kconfig | 13 +
> drivers/misc/mei/pxp/Makefile | 7 +
> drivers/misc/mei/pxp/mei_pxp.c | 230 ++++++++++++++++++
> drivers/misc/mei/pxp/mei_pxp.h | 18 ++
> include/drm/i915_component.h | 1 +
> include/drm/i915_pxp_tee_interface.h | 45 ++++
> include/uapi/drm/i915_drm.h | 66 +++++
> 37 files changed, 1686 insertions(+), 8 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> create mode 100644 drivers/misc/mei/pxp/Kconfig
> create mode 100644 drivers/misc/mei/pxp/Makefile
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
> create mode 100644 include/drm/i915_pxp_tee_interface.h
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session
2021-01-23 21:47 ` Gaurav, Kumar
@ 2021-01-25 15:38 ` Lionel Landwerlin
2021-01-25 16:22 ` Gaurav, Kumar
0 siblings, 1 reply; 30+ messages in thread
From: Lionel Landwerlin @ 2021-01-25 15:38 UTC (permalink / raw)
To: Gaurav, Kumar, Huang, Sean Z, Intel-gfx; +Cc: Ekstrand, Jason, Lahtinen, Joonas
Okay, if the get_param is too much at the point, can we at least have a
define to reflect that this is a special number from the kernel?
Thanks,
-Lionel
On 23/01/2021 23:47, Gaurav, Kumar wrote:
> Yes, this should not be problem since MESA is already using MI_SET_APPID with app_id 0xf.
>
> I proposed this earlier but I was told that MESA team will not be comfortable in querying app_id or session_states.
> Although check for proper session_state should be part of context robustness check.
>
> -----Original Message-----
> From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Sent: Saturday, January 23, 2021 6:19 AM
> To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
> Cc: Gaurav, Kumar <kumar.gaurav@intel.com>; Lahtinen, Joonas <joonas.lahtinen@intel.com>; Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Ekstrand, Jason <jason.ekstrand@intel.com>
> Subject: Re: [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session
>
> Hi,
>
> One of the thing that came up during UMD review is that the default session ID is actually uAPI :
> https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8064#note_776201
> Could we expose it through a get_param on the context?
>
> Thanks,
>
> -Lionel
>
> On 19/01/2021 09:43, Huang, Sean Z wrote:
>> PXP (Protected Xe Path) is an i915 component, available on
>> GEN12+ that helps to establish the hardware protected session
>> and manage the status of the alive software session, as well as its
>> life cycle.
>>
>> This patch series is to allow the kernel space to create and manage a
>> single hardware session (a.k.a. default session or arbitrary session).
>> So user can allocate the protected buffer, which is encrypted with the
>> leverage of the arbitrary hardware session.
>>
>>
>> rev23:
>> #09, #12
>> - Require user space to explicitly set recoverable flag to
>> false for protected context creation.
>>
>> #13
>> - Add Cc of reviewers in commit message.
>>
>>
>> Anshuman Gupta (1):
>> drm/i915/pxp: Add plane decryption support
>>
>> Bommu Krishnaiah (2):
>> drm/i915/uapi: introduce drm_i915_gem_create_ext
>> drm/i915/pxp: User interface for Protected buffer
>>
>> Huang, Sean Z (9):
>> drm/i915/pxp: Introduce Intel PXP component
>> drm/i915/pxp: set KCR reg init during the boot time
>> drm/i915/pxp: Implement funcs to create the TEE channel
>> drm/i915/pxp: Create the arbitrary session after boot
>> drm/i915/pxp: Func to send hardware session termination
>> drm/i915/pxp: Enable PXP irq worker and callback stub
>> drm/i915/pxp: Destroy arb session upon teardown
>> drm/i915/pxp: Enable PXP power management
>> drm/i915/pxp: Expose session state for display protection flip
>>
>> Vitaly Lubart (1):
>> mei: pxp: export pavp client to me client bus
>>
>> drivers/gpu/drm/i915/Kconfig | 21 ++
>> drivers/gpu/drm/i915/Makefile | 9 +
>> drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
>> drivers/gpu/drm/i915/gem/i915_gem_context.c | 13 +
>> drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 +
>> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
>> drivers/gpu/drm/i915/gem/i915_gem_create.c | 68 +++++-
>> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +
>> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
>> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 14 ++
>> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
>> drivers/gpu/drm/i915/i915_drv.c | 7 +-
>> drivers/gpu/drm/i915/i915_drv.h | 6 +
>> drivers/gpu/drm/i915/i915_reg.h | 2 +
>> drivers/gpu/drm/i915/pxp/intel_pxp.c | 193 +++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp.h | 70 ++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 208 ++++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 17 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 223 +++++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 19 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 28 +++
>> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 +++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++
>> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 202 +++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 38 +++
>> drivers/misc/mei/Kconfig | 2 +
>> drivers/misc/mei/Makefile | 1 +
>> drivers/misc/mei/pxp/Kconfig | 13 +
>> drivers/misc/mei/pxp/Makefile | 7 +
>> drivers/misc/mei/pxp/mei_pxp.c | 230 ++++++++++++++++++
>> drivers/misc/mei/pxp/mei_pxp.h | 18 ++
>> include/drm/i915_component.h | 1 +
>> include/drm/i915_pxp_tee_interface.h | 45 ++++
>> include/uapi/drm/i915_drm.h | 66 +++++
>> 37 files changed, 1686 insertions(+), 8 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>> create mode 100644 drivers/misc/mei/pxp/Kconfig
>> create mode 100644 drivers/misc/mei/pxp/Makefile
>> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
>> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
>> create mode 100644 include/drm/i915_pxp_tee_interface.h
>>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session
2021-01-25 15:38 ` Lionel Landwerlin
@ 2021-01-25 16:22 ` Gaurav, Kumar
0 siblings, 0 replies; 30+ messages in thread
From: Gaurav, Kumar @ 2021-01-25 16:22 UTC (permalink / raw)
To: Landwerlin, Lionel G, Huang, Sean Z, Intel-gfx, Bommu, Krishnaiah
Cc: Ekstrand, Jason, Lahtinen, Joonas
+Krishnaish
Actually, Rodrigo requested GET_PARAM for this API(due to IGT tests) so I believe GET_PARAM is getting implemented. Krishnaiah?
-----Original Message-----
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Sent: Monday, January 25, 2021 7:38 AM
To: Gaurav, Kumar <kumar.gaurav@intel.com>; Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Cc: Lahtinen, Joonas <joonas.lahtinen@intel.com>; Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Ekstrand, Jason <jason.ekstrand@intel.com>
Subject: Re: [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component - Mesa single session
Okay, if the get_param is too much at the point, can we at least have a define to reflect that this is a special number from the kernel?
Thanks,
-Lionel
On 23/01/2021 23:47, Gaurav, Kumar wrote:
> Yes, this should not be problem since MESA is already using MI_SET_APPID with app_id 0xf.
>
> I proposed this earlier but I was told that MESA team will not be comfortable in querying app_id or session_states.
> Although check for proper session_state should be part of context robustness check.
>
> -----Original Message-----
> From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Sent: Saturday, January 23, 2021 6:19 AM
> To: Huang, Sean Z <sean.z.huang@intel.com>;
> Intel-gfx@lists.freedesktop.org
> Cc: Gaurav, Kumar <kumar.gaurav@intel.com>; Lahtinen, Joonas
> <joonas.lahtinen@intel.com>; Joonas Lahtinen
> <joonas.lahtinen@linux.intel.com>; Ekstrand, Jason
> <jason.ekstrand@intel.com>
> Subject: Re: [Intel-gfx] [RFC-v23 00/13] Introduce Intel PXP component
> - Mesa single session
>
> Hi,
>
> One of the thing that came up during UMD review is that the default session ID is actually uAPI :
> https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8064#note_77
> 6201 Could we expose it through a get_param on the context?
>
> Thanks,
>
> -Lionel
>
> On 19/01/2021 09:43, Huang, Sean Z wrote:
>> PXP (Protected Xe Path) is an i915 component, available on
>> GEN12+ that helps to establish the hardware protected session
>> and manage the status of the alive software session, as well as its
>> life cycle.
>>
>> This patch series is to allow the kernel space to create and manage a
>> single hardware session (a.k.a. default session or arbitrary session).
>> So user can allocate the protected buffer, which is encrypted with
>> the leverage of the arbitrary hardware session.
>>
>>
>> rev23:
>> #09, #12
>> - Require user space to explicitly set recoverable flag to
>> false for protected context creation.
>>
>> #13
>> - Add Cc of reviewers in commit message.
>>
>>
>> Anshuman Gupta (1):
>> drm/i915/pxp: Add plane decryption support
>>
>> Bommu Krishnaiah (2):
>> drm/i915/uapi: introduce drm_i915_gem_create_ext
>> drm/i915/pxp: User interface for Protected buffer
>>
>> Huang, Sean Z (9):
>> drm/i915/pxp: Introduce Intel PXP component
>> drm/i915/pxp: set KCR reg init during the boot time
>> drm/i915/pxp: Implement funcs to create the TEE channel
>> drm/i915/pxp: Create the arbitrary session after boot
>> drm/i915/pxp: Func to send hardware session termination
>> drm/i915/pxp: Enable PXP irq worker and callback stub
>> drm/i915/pxp: Destroy arb session upon teardown
>> drm/i915/pxp: Enable PXP power management
>> drm/i915/pxp: Expose session state for display protection flip
>>
>> Vitaly Lubart (1):
>> mei: pxp: export pavp client to me client bus
>>
>> drivers/gpu/drm/i915/Kconfig | 21 ++
>> drivers/gpu/drm/i915/Makefile | 9 +
>> drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
>> drivers/gpu/drm/i915/gem/i915_gem_context.c | 13 +
>> drivers/gpu/drm/i915/gem/i915_gem_context.h | 5 +
>> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
>> drivers/gpu/drm/i915/gem/i915_gem_create.c | 68 +++++-
>> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +
>> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
>> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 14 ++
>> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
>> drivers/gpu/drm/i915/i915_drv.c | 7 +-
>> drivers/gpu/drm/i915/i915_drv.h | 6 +
>> drivers/gpu/drm/i915/i915_reg.h | 2 +
>> drivers/gpu/drm/i915/pxp/intel_pxp.c | 193 +++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp.h | 70 ++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 208 ++++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 17 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 223 +++++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 19 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 28 +++
>> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 +++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++
>> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 202 +++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 38 +++
>> drivers/misc/mei/Kconfig | 2 +
>> drivers/misc/mei/Makefile | 1 +
>> drivers/misc/mei/pxp/Kconfig | 13 +
>> drivers/misc/mei/pxp/Makefile | 7 +
>> drivers/misc/mei/pxp/mei_pxp.c | 230 ++++++++++++++++++
>> drivers/misc/mei/pxp/mei_pxp.h | 18 ++
>> include/drm/i915_component.h | 1 +
>> include/drm/i915_pxp_tee_interface.h | 45 ++++
>> include/uapi/drm/i915_drm.h | 66 +++++
>> 37 files changed, 1686 insertions(+), 8 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>> create mode 100644 drivers/misc/mei/pxp/Kconfig
>> create mode 100644 drivers/misc/mei/pxp/Makefile
>> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
>> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
>> create mode 100644 include/drm/i915_pxp_tee_interface.h
>>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread