From: John Harrison <john.c.harrison@intel.com>
To: Matthew Brost <matthew.brost@intel.com>,
intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 27/47] drm/i915: Track 'serial' counts for virtual engines
Date: Mon, 12 Jul 2021 11:11:48 -0700 [thread overview]
Message-ID: <1f82fc27-d857-228a-99fb-038295be77d0@intel.com> (raw)
In-Reply-To: <20210624070516.21893-28-matthew.brost@intel.com>
On 6/24/2021 00:04, Matthew Brost wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> The serial number tracking of engines happens at the backend of
> request submission and was expecting to only be given physical
> engines. However, in GuC submission mode, the decomposition of virtual
> to physical engines does not happen in i915. Instead, requests are
> submitted to their virtual engine mask all the way through to the
> hardware (i.e. to GuC). This would mean that the heart beat code
> thinks the physical engines are idle due to the serial number not
> incrementing.
>
> This patch updates the tracking to decompose virtual engines into
> their physical constituents and tracks the request against each. This
> is not entirely accurate as the GuC will only be issuing the request
> to one physical engine. However, it is the best that i915 can do given
> that it has no knowledge of the GuC's scheduling decisions.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Need to pull in the updated subject line and commit description from
Tvrtko in the RFC patch set review.
John.
> ---
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 ++
> .../gpu/drm/i915/gt/intel_execlists_submission.c | 6 ++++++
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 6 ++++++
> drivers/gpu/drm/i915/gt/mock_engine.c | 6 ++++++
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 16 ++++++++++++++++
> drivers/gpu/drm/i915/i915_request.c | 4 +++-
> 6 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 5b91068ab277..1dc59e6c9a92 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -388,6 +388,8 @@ struct intel_engine_cs {
> void (*park)(struct intel_engine_cs *engine);
> void (*unpark)(struct intel_engine_cs *engine);
>
> + void (*bump_serial)(struct intel_engine_cs *engine);
> +
> void (*set_default_submission)(struct intel_engine_cs *engine);
>
> const struct intel_context_ops *cops;
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index bd4ced794ff9..9cfb8800a0e6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3203,6 +3203,11 @@ static void execlists_release(struct intel_engine_cs *engine)
> lrc_fini_wa_ctx(engine);
> }
>
> +static void execlist_bump_serial(struct intel_engine_cs *engine)
> +{
> + engine->serial++;
> +}
> +
> static void
> logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> {
> @@ -3212,6 +3217,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>
> engine->cops = &execlists_context_ops;
> engine->request_alloc = execlists_request_alloc;
> + engine->bump_serial = execlist_bump_serial;
>
> engine->reset.prepare = execlists_reset_prepare;
> engine->reset.rewind = execlists_reset_rewind;
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 5d42a12ef3d6..e1506b280df1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -1044,6 +1044,11 @@ static void setup_irq(struct intel_engine_cs *engine)
> }
> }
>
> +static void ring_bump_serial(struct intel_engine_cs *engine)
> +{
> + engine->serial++;
> +}
> +
> static void setup_common(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *i915 = engine->i915;
> @@ -1063,6 +1068,7 @@ static void setup_common(struct intel_engine_cs *engine)
>
> engine->cops = &ring_context_ops;
> engine->request_alloc = ring_request_alloc;
> + engine->bump_serial = ring_bump_serial;
>
> /*
> * Using a global execution timeline; the previous final breadcrumb is
> diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
> index 68970398e4ef..9203c766db80 100644
> --- a/drivers/gpu/drm/i915/gt/mock_engine.c
> +++ b/drivers/gpu/drm/i915/gt/mock_engine.c
> @@ -292,6 +292,11 @@ static void mock_engine_release(struct intel_engine_cs *engine)
> intel_engine_fini_retire(engine);
> }
>
> +static void mock_bump_serial(struct intel_engine_cs *engine)
> +{
> + engine->serial++;
> +}
> +
> struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
> const char *name,
> int id)
> @@ -318,6 +323,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
>
> engine->base.cops = &mock_context_ops;
> engine->base.request_alloc = mock_request_alloc;
> + engine->base.bump_serial = mock_bump_serial;
> engine->base.emit_flush = mock_emit_flush;
> engine->base.emit_fini_breadcrumb = mock_emit_breadcrumb;
> engine->base.submit_request = mock_submit_request;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index ccbcf024b31b..d1badd7137b7 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1496,6 +1496,20 @@ static void guc_release(struct intel_engine_cs *engine)
> lrc_fini_wa_ctx(engine);
> }
>
> +static void guc_bump_serial(struct intel_engine_cs *engine)
> +{
> + engine->serial++;
> +}
> +
> +static void virtual_guc_bump_serial(struct intel_engine_cs *engine)
> +{
> + struct intel_engine_cs *e;
> + intel_engine_mask_t tmp, mask = engine->mask;
> +
> + for_each_engine_masked(e, engine->gt, mask, tmp)
> + e->serial++;
> +}
> +
> static void guc_default_vfuncs(struct intel_engine_cs *engine)
> {
> /* Default vfuncs which can be overridden by each engine. */
> @@ -1504,6 +1518,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>
> engine->cops = &guc_context_ops;
> engine->request_alloc = guc_request_alloc;
> + engine->bump_serial = guc_bump_serial;
>
> engine->sched_engine->schedule = i915_schedule;
>
> @@ -1836,6 +1851,7 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count)
>
> ve->base.cops = &virtual_guc_context_ops;
> ve->base.request_alloc = guc_request_alloc;
> + ve->base.bump_serial = virtual_guc_bump_serial;
>
> ve->base.submit_request = guc_submit_request;
>
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index 7f7aa096e873..de9deb95b8b1 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -692,7 +692,9 @@ bool __i915_request_submit(struct i915_request *request)
> request->ring->vaddr + request->postfix);
>
> trace_i915_request_execute(request);
> - engine->serial++;
> + if (engine->bump_serial)
> + engine->bump_serial(engine);
> +
> result = true;
>
> GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
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next prev parent reply other threads:[~2021-07-12 18:11 UTC|newest]
Thread overview: 170+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-24 7:04 [Intel-gfx] [PATCH 00/47] GuC submission support Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 01/47] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-06-24 17:23 ` Michal Wajdeczko
2021-06-24 7:04 ` [Intel-gfx] [PATCH 02/47] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost
2021-06-25 11:58 ` Michal Wajdeczko
2021-06-24 7:04 ` [Intel-gfx] [PATCH 03/47] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-06-24 13:49 ` Michal Wajdeczko
2021-06-24 15:41 ` Matthew Brost
2021-06-25 12:03 ` Michal Wajdeczko
2021-06-24 7:04 ` [Intel-gfx] [PATCH 04/47] drm/i915/guc: Add non blocking CTB send function Matthew Brost
2021-06-24 14:48 ` Michal Wajdeczko
2021-06-24 15:49 ` Matthew Brost
2021-06-24 17:02 ` Michal Wajdeczko
2021-06-24 22:41 ` Matthew Brost
2021-06-25 11:50 ` Michal Wajdeczko
2021-06-25 17:53 ` Matthew Brost
2021-06-24 22:47 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 05/47] drm/i915/guc: Add stall timer to " Matthew Brost
2021-06-24 17:37 ` Michal Wajdeczko
2021-06-24 23:01 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 06/47] drm/i915/guc: Optimize CTB writes and reads Matthew Brost
2021-06-25 13:09 ` Michal Wajdeczko
2021-06-25 18:26 ` Matthew Brost
2021-06-25 20:28 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 07/47] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 08/47] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-06-29 21:11 ` John Harrison
2021-06-30 0:30 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 09/47] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost
2021-06-25 19:44 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 10/47] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost
2021-06-25 13:17 ` Michal Wajdeczko
2021-06-25 17:26 ` Matthew Brost
2021-06-29 21:20 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 11/47] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-06-29 22:04 ` John Harrison
2021-06-30 0:41 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 12/47] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-06-29 22:09 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 13/47] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-06-25 13:25 ` Michal Wajdeczko
2021-06-25 17:46 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 14/47] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-07-09 22:39 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 15/47] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-07-09 22:48 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 16/47] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-07-09 22:53 ` John Harrison
2021-07-10 3:00 ` Matthew Brost
2021-07-12 17:57 ` John Harrison
2021-07-12 18:11 ` Daniel Vetter
2021-06-24 7:04 ` [Intel-gfx] [PATCH 17/47] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-07-09 22:59 ` John Harrison
2021-07-10 3:36 ` Matthew Brost
2021-07-12 17:54 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 18/47] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-07-09 23:03 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 19/47] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-07-15 1:51 ` Daniele Ceraolo Spurio
2021-06-24 7:04 ` [Intel-gfx] [PATCH 20/47] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-07-09 23:53 ` John Harrison
2021-07-15 0:07 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 21/47] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-07-13 18:36 ` John Harrison
2021-07-15 0:06 ` Matthew Brost
2021-07-15 0:12 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 22/47] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-07-10 0:16 ` John Harrison
2021-07-10 3:55 ` Matthew Brost
2021-07-17 4:09 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 23/47] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-07-12 18:05 ` John Harrison
2021-07-12 20:59 ` Matthew Brost
2021-07-12 21:37 ` John Harrison
2021-07-13 8:51 ` Michal Wajdeczko
2021-07-14 23:56 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 24/47] drm/i915/guc: Add several request trace points Matthew Brost
2021-07-12 18:08 ` John Harrison
2021-07-13 9:06 ` Tvrtko Ursulin
2021-07-20 1:59 ` Matthew Brost
2021-07-22 13:55 ` Tvrtko Ursulin
2021-06-24 7:04 ` [Intel-gfx] [PATCH 25/47] drm/i915: Add intel_context tracing Matthew Brost
2021-07-12 18:10 ` John Harrison
2021-07-12 21:47 ` Matthew Brost
2021-07-12 21:51 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 26/47] drm/i915/guc: GuC virtual engines Matthew Brost
2021-07-15 1:21 ` Daniele Ceraolo Spurio
2021-06-24 7:04 ` [Intel-gfx] [PATCH 27/47] drm/i915: Track 'serial' counts for " Matthew Brost
2021-07-12 18:11 ` John Harrison [this message]
2021-07-12 20:06 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 28/47] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-07-12 18:23 ` John Harrison
2021-07-12 20:05 ` Matthew Brost
2021-07-12 21:36 ` Matthew Brost
2021-07-12 21:48 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 29/47] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-07-12 18:23 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 30/47] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-07-12 19:19 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 31/47] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-07-12 19:58 ` John Harrison
2021-07-15 0:53 ` Matthew Brost
2021-07-15 9:36 ` Tvrtko Ursulin
2021-07-26 22:48 ` Matthew Brost
2021-07-27 8:56 ` Tvrtko Ursulin
2021-07-27 18:30 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 32/47] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-07-12 20:01 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 33/47] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-07-12 20:11 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 34/47] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-07-12 22:56 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 35/47] drm/i915/guc: Handle context reset notification Matthew Brost
2021-07-12 22:58 ` John Harrison
2021-07-15 0:32 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 36/47] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-07-12 22:59 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 37/47] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-07-12 23:00 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 38/47] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 39/47] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-06-24 15:55 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 40/47] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-06-24 16:19 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 41/47] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-07-12 23:05 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 42/47] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-07-15 0:43 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 43/47] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-06-25 0:59 ` Matthew Brost
2021-06-25 19:10 ` John Harrison
2021-07-10 18:56 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 44/47] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-06-25 1:10 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 45/47] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-06-24 16:34 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 46/47] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 47/47] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-06-30 8:22 ` Martin Peres
2021-06-30 18:00 ` Matthew Brost
2021-07-01 18:24 ` Martin Peres
2021-07-02 8:13 ` Martin Peres
2021-07-02 13:06 ` Michal Wajdeczko
2021-07-02 13:12 ` Martin Peres
2021-07-02 14:08 ` Michal Wajdeczko
2021-06-30 18:58 ` John Harrison
2021-07-01 8:14 ` Pekka Paalanen
2021-07-01 18:27 ` Martin Peres
2021-07-01 19:28 ` Daniel Vetter
2021-07-02 7:29 ` Pekka Paalanen
2021-07-02 8:09 ` Martin Peres
2021-07-02 15:07 ` Michal Wajdeczko
2021-07-03 8:21 ` Martin Peres
2021-07-07 0:57 ` John Harrison
2021-07-07 7:47 ` Pekka Paalanen
2021-07-07 10:11 ` Michal Wajdeczko
2021-07-15 0:49 ` Matthew Brost
2021-06-24 7:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission support Patchwork
2021-06-24 7:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-24 7:47 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-07-12 19:23 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev2) Patchwork
2021-10-22 9:35 ` [Intel-gfx] [PATCH 00/47] GuC submission support Joonas Lahtinen
2021-10-22 16:42 ` Matthew Brost
2021-10-25 9:37 ` Joonas Lahtinen
2021-10-25 15:15 ` Matthew Brost
2021-10-26 8:59 ` Joonas Lahtinen
2021-10-26 15:43 ` Matthew Brost
2021-10-26 15:51 ` Matthew Brost
2021-10-27 9:21 ` Joonas Lahtinen
2021-10-25 17:06 ` John Harrison
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