From: John Harrison <john.c.harrison@intel.com>
To: Matthew Brost <matthew.brost@intel.com>,
intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 30/47] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs
Date: Mon, 12 Jul 2021 12:19:58 -0700 [thread overview]
Message-ID: <7b74afc3-58a9-54cd-9966-48f1d1e0998d@intel.com> (raw)
In-Reply-To: <20210624070516.21893-31-matthew.brost@intel.com>
On 6/24/2021 00:04, Matthew Brost wrote:
> With GuC virtual engines the physical engine which a request executes
> and completes on isn't known to the i915. Therefore we can't attach a
> request to a physical engines breadcrumbs. To work around this we create
> a single breadcrumbs per engine class when using GuC submission and
> direct all physical engine interrupts to this breadcrumbs.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> CC: John Harrison <John.C.Harrison@Intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 41 +++++-------
> drivers/gpu/drm/i915/gt/intel_breadcrumbs.h | 14 +++-
> .../gpu/drm/i915/gt/intel_breadcrumbs_types.h | 7 ++
> drivers/gpu/drm/i915/gt/intel_engine.h | 3 +
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 +++++++-
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
> .../drm/i915/gt/intel_execlists_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/mock_engine.c | 4 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 67 +++++++++++++++++--
> 9 files changed, 131 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
> index 38cc42783dfb..2007dc6f6b99 100644
> --- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
> @@ -15,28 +15,14 @@
> #include "intel_gt_pm.h"
> #include "intel_gt_requests.h"
>
> -static bool irq_enable(struct intel_engine_cs *engine)
> +static bool irq_enable(struct intel_breadcrumbs *b)
> {
> - if (!engine->irq_enable)
> - return false;
> -
> - /* Caller disables interrupts */
> - spin_lock(&engine->gt->irq_lock);
> - engine->irq_enable(engine);
> - spin_unlock(&engine->gt->irq_lock);
> -
> - return true;
> + return intel_engine_irq_enable(b->irq_engine);
> }
>
> -static void irq_disable(struct intel_engine_cs *engine)
> +static void irq_disable(struct intel_breadcrumbs *b)
> {
> - if (!engine->irq_disable)
> - return;
> -
> - /* Caller disables interrupts */
> - spin_lock(&engine->gt->irq_lock);
> - engine->irq_disable(engine);
> - spin_unlock(&engine->gt->irq_lock);
> + intel_engine_irq_disable(b->irq_engine);
> }
>
> static void __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b)
> @@ -57,7 +43,7 @@ static void __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b)
> WRITE_ONCE(b->irq_armed, true);
>
> /* Requests may have completed before we could enable the interrupt. */
> - if (!b->irq_enabled++ && irq_enable(b->irq_engine))
> + if (!b->irq_enabled++ && b->irq_enable(b))
> irq_work_queue(&b->irq_work);
> }
>
> @@ -76,7 +62,7 @@ static void __intel_breadcrumbs_disarm_irq(struct intel_breadcrumbs *b)
> {
> GEM_BUG_ON(!b->irq_enabled);
> if (!--b->irq_enabled)
> - irq_disable(b->irq_engine);
> + b->irq_disable(b);
>
> WRITE_ONCE(b->irq_armed, false);
> intel_gt_pm_put_async(b->irq_engine->gt);
> @@ -281,7 +267,7 @@ intel_breadcrumbs_create(struct intel_engine_cs *irq_engine)
> if (!b)
> return NULL;
>
> - b->irq_engine = irq_engine;
> + kref_init(&b->ref);
>
> spin_lock_init(&b->signalers_lock);
> INIT_LIST_HEAD(&b->signalers);
> @@ -290,6 +276,10 @@ intel_breadcrumbs_create(struct intel_engine_cs *irq_engine)
> spin_lock_init(&b->irq_lock);
> init_irq_work(&b->irq_work, signal_irq_work);
>
> + b->irq_engine = irq_engine;
> + b->irq_enable = irq_enable;
> + b->irq_disable = irq_disable;
> +
> return b;
> }
>
> @@ -303,9 +293,9 @@ void intel_breadcrumbs_reset(struct intel_breadcrumbs *b)
> spin_lock_irqsave(&b->irq_lock, flags);
>
> if (b->irq_enabled)
> - irq_enable(b->irq_engine);
> + b->irq_enable(b);
> else
> - irq_disable(b->irq_engine);
> + b->irq_disable(b);
>
> spin_unlock_irqrestore(&b->irq_lock, flags);
> }
> @@ -325,11 +315,14 @@ void __intel_breadcrumbs_park(struct intel_breadcrumbs *b)
> }
> }
>
> -void intel_breadcrumbs_free(struct intel_breadcrumbs *b)
> +void intel_breadcrumbs_free(struct kref *kref)
> {
> + struct intel_breadcrumbs *b = container_of(kref, typeof(*b), ref);
> +
> irq_work_sync(&b->irq_work);
> GEM_BUG_ON(!list_empty(&b->signalers));
> GEM_BUG_ON(b->irq_armed);
> +
> kfree(b);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.h b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
> index 3ce5ce270b04..72105b74663d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
> @@ -17,7 +17,7 @@ struct intel_breadcrumbs;
>
> struct intel_breadcrumbs *
> intel_breadcrumbs_create(struct intel_engine_cs *irq_engine);
> -void intel_breadcrumbs_free(struct intel_breadcrumbs *b);
> +void intel_breadcrumbs_free(struct kref *kref);
>
> void intel_breadcrumbs_reset(struct intel_breadcrumbs *b);
> void __intel_breadcrumbs_park(struct intel_breadcrumbs *b);
> @@ -48,4 +48,16 @@ void i915_request_cancel_breadcrumb(struct i915_request *request);
> void intel_context_remove_breadcrumbs(struct intel_context *ce,
> struct intel_breadcrumbs *b);
>
> +static inline struct intel_breadcrumbs *
> +intel_breadcrumbs_get(struct intel_breadcrumbs *b)
> +{
> + kref_get(&b->ref);
> + return b;
> +}
> +
> +static inline void intel_breadcrumbs_put(struct intel_breadcrumbs *b)
> +{
> + kref_put(&b->ref, intel_breadcrumbs_free);
> +}
> +
> #endif /* __INTEL_BREADCRUMBS__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h b/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
> index 3a084ce8ff5e..a4e146684be8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
> @@ -7,10 +7,13 @@
> #define __INTEL_BREADCRUMBS_TYPES__
>
> #include <linux/irq_work.h>
> +#include <linux/kref.h>
> #include <linux/list.h>
> #include <linux/spinlock.h>
> #include <linux/types.h>
>
> +typedef u8 intel_engine_mask_t;
Seems like the wrong place for this. Can it be moved to
gt/intel_engine_types.h instead?
> +
> /*
> * Rather than have every client wait upon all user interrupts,
> * with the herd waking after every interrupt and each doing the
> @@ -29,6 +32,7 @@
> * the overhead of waking that client is much preferred.
> */
> struct intel_breadcrumbs {
> + struct kref ref;
> atomic_t active;
>
> spinlock_t signalers_lock; /* protects the list of signalers */
> @@ -42,7 +46,10 @@ struct intel_breadcrumbs {
> bool irq_armed;
>
> /* Not all breadcrumbs are attached to physical HW */
> + intel_engine_mask_t engine_mask;
> struct intel_engine_cs *irq_engine;
> + bool (*irq_enable)(struct intel_breadcrumbs *b);
> + void (*irq_disable)(struct intel_breadcrumbs *b);
> };
>
> #endif /* __INTEL_BREADCRUMBS_TYPES__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 923eaee627b3..e9e0657f847a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -212,6 +212,9 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
>
> void intel_engine_init_execlists(struct intel_engine_cs *engine);
>
> +bool intel_engine_irq_enable(struct intel_engine_cs *engine);
> +void intel_engine_irq_disable(struct intel_engine_cs *engine);
> +
> static inline void __intel_engine_reset(struct intel_engine_cs *engine,
> bool stalled)
> {
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index d13b1716c29e..69245670b8b0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -739,7 +739,7 @@ static int engine_setup_common(struct intel_engine_cs *engine)
> err_cmd_parser:
> i915_sched_engine_put(engine->sched_engine);
> err_sched_engine:
> - intel_breadcrumbs_free(engine->breadcrumbs);
> + intel_breadcrumbs_put(engine->breadcrumbs);
> err_status:
> cleanup_status_page(engine);
> return err;
> @@ -947,7 +947,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
> GEM_BUG_ON(!list_empty(&engine->sched_engine->requests));
>
> i915_sched_engine_put(engine->sched_engine);
> - intel_breadcrumbs_free(engine->breadcrumbs);
> + intel_breadcrumbs_put(engine->breadcrumbs);
>
> intel_engine_fini_retire(engine);
> intel_engine_cleanup_cmd_parser(engine);
> @@ -1264,6 +1264,30 @@ bool intel_engines_are_idle(struct intel_gt *gt)
> return true;
> }
>
> +bool intel_engine_irq_enable(struct intel_engine_cs *engine)
> +{
> + if (!engine->irq_enable)
> + return false;
> +
> + /* Caller disables interrupts */
> + spin_lock(&engine->gt->irq_lock);
> + engine->irq_enable(engine);
> + spin_unlock(&engine->gt->irq_lock);
> +
> + return true;
> +}
> +
> +void intel_engine_irq_disable(struct intel_engine_cs *engine)
> +{
> + if (!engine->irq_disable)
> + return;
> +
> + /* Caller disables interrupts */
> + spin_lock(&engine->gt->irq_lock);
> + engine->irq_disable(engine);
> + spin_unlock(&engine->gt->irq_lock);
> +}
> +
> void intel_engines_reset_default_submission(struct intel_gt *gt)
> {
> struct intel_engine_cs *engine;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 1dc59e6c9a92..e7cb6a06db9d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -64,7 +64,6 @@ struct intel_gt;
> struct intel_ring;
> struct intel_uncore;
>
> -typedef u8 intel_engine_mask_t;
Oh.
The following fixes this for me:
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
index 3ce5ce270b04..ac5cdd6ff3f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
@@ -10,6 +10,7 @@
#include <linux/irq_work.h>
#include "intel_engine_types.h"
+#include "gt/intel_breadcrumbs_types.h"
struct drm_printer;
struct i915_request;
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
index 3a084ce8ff5e..260ccd5c1573 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
@@ -11,6 +11,8 @@
#include <linux/spinlock.h>
#include <linux/types.h>
+#include "gt/intel_engine_types.h"
+
/*
* Rather than have every client wait upon all user interrupts,
* with the herd waking after every interrupt and each doing the
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 1cb9c3b70b29..da15b8b3c1f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -21,7 +21,6 @@
#include "i915_pmu.h"
#include "i915_priolist_types.h"
#include "i915_selftest.h"
-#include "intel_breadcrumbs_types.h"
#include "intel_sseu.h"
#include "intel_timeline_types.h"
#include "intel_uncore.h"
John.
> #define ALL_ENGINES ((intel_engine_mask_t)~0ul)
>
> struct intel_hw_status_page {
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 9cfb8800a0e6..c10ea6080752 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3419,7 +3419,7 @@ static void rcu_virtual_context_destroy(struct work_struct *wrk)
> intel_context_fini(&ve->context);
>
> if (ve->base.breadcrumbs)
> - intel_breadcrumbs_free(ve->base.breadcrumbs);
> + intel_breadcrumbs_put(ve->base.breadcrumbs);
> if (ve->base.sched_engine)
> i915_sched_engine_put(ve->base.sched_engine);
> intel_engine_free_request_pool(&ve->base);
> diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
> index 9203c766db80..fc5a65ab1937 100644
> --- a/drivers/gpu/drm/i915/gt/mock_engine.c
> +++ b/drivers/gpu/drm/i915/gt/mock_engine.c
> @@ -284,7 +284,7 @@ static void mock_engine_release(struct intel_engine_cs *engine)
> GEM_BUG_ON(timer_pending(&mock->hw_delay));
>
> i915_sched_engine_put(engine->sched_engine);
> - intel_breadcrumbs_free(engine->breadcrumbs);
> + intel_breadcrumbs_put(engine->breadcrumbs);
>
> intel_context_unpin(engine->kernel_context);
> intel_context_put(engine->kernel_context);
> @@ -376,7 +376,7 @@ int mock_engine_init(struct intel_engine_cs *engine)
> return 0;
>
> err_breadcrumbs:
> - intel_breadcrumbs_free(engine->breadcrumbs);
> + intel_breadcrumbs_put(engine->breadcrumbs);
> err_schedule:
> i915_sched_engine_put(engine->sched_engine);
> return -ENOMEM;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index d1badd7137b7..83058df5ba01 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1074,6 +1074,9 @@ static void __guc_context_destroy(struct intel_context *ce)
> struct guc_virtual_engine *ve =
> container_of(ce, typeof(*ve), context);
>
> + if (ve->base.breadcrumbs)
> + intel_breadcrumbs_put(ve->base.breadcrumbs);
> +
> kfree(ve);
> } else {
> intel_context_free(ce);
> @@ -1377,6 +1380,62 @@ static const struct intel_context_ops virtual_guc_context_ops = {
> .get_sibling = guc_virtual_get_sibling,
> };
>
> +static bool
> +guc_irq_enable_breadcrumbs(struct intel_breadcrumbs *b)
> +{
> + struct intel_engine_cs *sibling;
> + intel_engine_mask_t tmp, mask = b->engine_mask;
> + bool result = false;
> +
> + for_each_engine_masked(sibling, b->irq_engine->gt, mask, tmp)
> + result |= intel_engine_irq_enable(sibling);
> +
> + return result;
> +}
> +
> +static void
> +guc_irq_disable_breadcrumbs(struct intel_breadcrumbs *b)
> +{
> + struct intel_engine_cs *sibling;
> + intel_engine_mask_t tmp, mask = b->engine_mask;
> +
> + for_each_engine_masked(sibling, b->irq_engine->gt, mask, tmp)
> + intel_engine_irq_disable(sibling);
> +}
> +
> +static void guc_init_breadcrumbs(struct intel_engine_cs *engine)
> +{
> + int i;
> +
> + /*
> + * In GuC submission mode we do not know which physical engine a request
> + * will be scheduled on, this creates a problem because the breadcrumb
> + * interrupt is per physical engine. To work around this we attach
> + * requests and direct all breadcrumb interrupts to the first instance
> + * of an engine per class. In addition all breadcrumb interrupts are
> + * enabled / disabled across an engine class in unison.
> + */
> + for (i = 0; i < MAX_ENGINE_INSTANCE; ++i) {
> + struct intel_engine_cs *sibling =
> + engine->gt->engine_class[engine->class][i];
> +
> + if (sibling) {
> + if (engine->breadcrumbs != sibling->breadcrumbs) {
> + intel_breadcrumbs_put(engine->breadcrumbs);
> + engine->breadcrumbs =
> + intel_breadcrumbs_get(sibling->breadcrumbs);
> + }
> + break;
> + }
> + }
> +
> + if (engine->breadcrumbs) {
> + engine->breadcrumbs->engine_mask |= engine->mask;
> + engine->breadcrumbs->irq_enable = guc_irq_enable_breadcrumbs;
> + engine->breadcrumbs->irq_disable = guc_irq_disable_breadcrumbs;
> + }
> +}
> +
> static void sanitize_hwsp(struct intel_engine_cs *engine)
> {
> struct intel_timeline *tl;
> @@ -1600,6 +1659,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
>
> guc_default_vfuncs(engine);
> guc_default_irqs(engine);
> + guc_init_breadcrumbs(engine);
>
> if (engine->class == RENDER_CLASS)
> rcs_submission_override(engine);
> @@ -1839,11 +1899,6 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count)
> ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
> ve->base.uabi_instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
> ve->base.saturated = ALL_ENGINES;
> - ve->base.breadcrumbs = intel_breadcrumbs_create(&ve->base);
> - if (!ve->base.breadcrumbs) {
> - kfree(ve);
> - return ERR_PTR(-ENOMEM);
> - }
>
> snprintf(ve->base.name, sizeof(ve->base.name), "virtual");
>
> @@ -1892,6 +1947,8 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count)
> sibling->emit_fini_breadcrumb;
> ve->base.emit_fini_breadcrumb_dw =
> sibling->emit_fini_breadcrumb_dw;
> + ve->base.breadcrumbs =
> + intel_breadcrumbs_get(sibling->breadcrumbs);
>
> ve->base.flags |= sibling->flags;
>
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next prev parent reply other threads:[~2021-07-12 19:20 UTC|newest]
Thread overview: 170+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-24 7:04 [Intel-gfx] [PATCH 00/47] GuC submission support Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 01/47] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-06-24 17:23 ` Michal Wajdeczko
2021-06-24 7:04 ` [Intel-gfx] [PATCH 02/47] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost
2021-06-25 11:58 ` Michal Wajdeczko
2021-06-24 7:04 ` [Intel-gfx] [PATCH 03/47] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-06-24 13:49 ` Michal Wajdeczko
2021-06-24 15:41 ` Matthew Brost
2021-06-25 12:03 ` Michal Wajdeczko
2021-06-24 7:04 ` [Intel-gfx] [PATCH 04/47] drm/i915/guc: Add non blocking CTB send function Matthew Brost
2021-06-24 14:48 ` Michal Wajdeczko
2021-06-24 15:49 ` Matthew Brost
2021-06-24 17:02 ` Michal Wajdeczko
2021-06-24 22:41 ` Matthew Brost
2021-06-25 11:50 ` Michal Wajdeczko
2021-06-25 17:53 ` Matthew Brost
2021-06-24 22:47 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 05/47] drm/i915/guc: Add stall timer to " Matthew Brost
2021-06-24 17:37 ` Michal Wajdeczko
2021-06-24 23:01 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 06/47] drm/i915/guc: Optimize CTB writes and reads Matthew Brost
2021-06-25 13:09 ` Michal Wajdeczko
2021-06-25 18:26 ` Matthew Brost
2021-06-25 20:28 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 07/47] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 08/47] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-06-29 21:11 ` John Harrison
2021-06-30 0:30 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 09/47] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost
2021-06-25 19:44 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 10/47] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost
2021-06-25 13:17 ` Michal Wajdeczko
2021-06-25 17:26 ` Matthew Brost
2021-06-29 21:20 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 11/47] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-06-29 22:04 ` John Harrison
2021-06-30 0:41 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 12/47] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-06-29 22:09 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 13/47] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-06-25 13:25 ` Michal Wajdeczko
2021-06-25 17:46 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 14/47] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-07-09 22:39 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 15/47] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-07-09 22:48 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 16/47] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-07-09 22:53 ` John Harrison
2021-07-10 3:00 ` Matthew Brost
2021-07-12 17:57 ` John Harrison
2021-07-12 18:11 ` Daniel Vetter
2021-06-24 7:04 ` [Intel-gfx] [PATCH 17/47] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-07-09 22:59 ` John Harrison
2021-07-10 3:36 ` Matthew Brost
2021-07-12 17:54 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 18/47] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-07-09 23:03 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 19/47] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-07-15 1:51 ` Daniele Ceraolo Spurio
2021-06-24 7:04 ` [Intel-gfx] [PATCH 20/47] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-07-09 23:53 ` John Harrison
2021-07-15 0:07 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 21/47] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-07-13 18:36 ` John Harrison
2021-07-15 0:06 ` Matthew Brost
2021-07-15 0:12 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 22/47] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-07-10 0:16 ` John Harrison
2021-07-10 3:55 ` Matthew Brost
2021-07-17 4:09 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 23/47] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-07-12 18:05 ` John Harrison
2021-07-12 20:59 ` Matthew Brost
2021-07-12 21:37 ` John Harrison
2021-07-13 8:51 ` Michal Wajdeczko
2021-07-14 23:56 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 24/47] drm/i915/guc: Add several request trace points Matthew Brost
2021-07-12 18:08 ` John Harrison
2021-07-13 9:06 ` Tvrtko Ursulin
2021-07-20 1:59 ` Matthew Brost
2021-07-22 13:55 ` Tvrtko Ursulin
2021-06-24 7:04 ` [Intel-gfx] [PATCH 25/47] drm/i915: Add intel_context tracing Matthew Brost
2021-07-12 18:10 ` John Harrison
2021-07-12 21:47 ` Matthew Brost
2021-07-12 21:51 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 26/47] drm/i915/guc: GuC virtual engines Matthew Brost
2021-07-15 1:21 ` Daniele Ceraolo Spurio
2021-06-24 7:04 ` [Intel-gfx] [PATCH 27/47] drm/i915: Track 'serial' counts for " Matthew Brost
2021-07-12 18:11 ` John Harrison
2021-07-12 20:06 ` Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] [PATCH 28/47] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-07-12 18:23 ` John Harrison
2021-07-12 20:05 ` Matthew Brost
2021-07-12 21:36 ` Matthew Brost
2021-07-12 21:48 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 29/47] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-07-12 18:23 ` John Harrison
2021-06-24 7:04 ` [Intel-gfx] [PATCH 30/47] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-07-12 19:19 ` John Harrison [this message]
2021-06-24 7:05 ` [Intel-gfx] [PATCH 31/47] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-07-12 19:58 ` John Harrison
2021-07-15 0:53 ` Matthew Brost
2021-07-15 9:36 ` Tvrtko Ursulin
2021-07-26 22:48 ` Matthew Brost
2021-07-27 8:56 ` Tvrtko Ursulin
2021-07-27 18:30 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 32/47] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-07-12 20:01 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 33/47] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-07-12 20:11 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 34/47] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-07-12 22:56 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 35/47] drm/i915/guc: Handle context reset notification Matthew Brost
2021-07-12 22:58 ` John Harrison
2021-07-15 0:32 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 36/47] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-07-12 22:59 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 37/47] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-07-12 23:00 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 38/47] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 39/47] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-06-24 15:55 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 40/47] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-06-24 16:19 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 41/47] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-07-12 23:05 ` John Harrison
2021-06-24 7:05 ` [Intel-gfx] [PATCH 42/47] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-07-15 0:43 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 43/47] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-06-25 0:59 ` Matthew Brost
2021-06-25 19:10 ` John Harrison
2021-07-10 18:56 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 44/47] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-06-25 1:10 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 45/47] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-06-24 16:34 ` Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 46/47] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] [PATCH 47/47] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-06-30 8:22 ` Martin Peres
2021-06-30 18:00 ` Matthew Brost
2021-07-01 18:24 ` Martin Peres
2021-07-02 8:13 ` Martin Peres
2021-07-02 13:06 ` Michal Wajdeczko
2021-07-02 13:12 ` Martin Peres
2021-07-02 14:08 ` Michal Wajdeczko
2021-06-30 18:58 ` John Harrison
2021-07-01 8:14 ` Pekka Paalanen
2021-07-01 18:27 ` Martin Peres
2021-07-01 19:28 ` Daniel Vetter
2021-07-02 7:29 ` Pekka Paalanen
2021-07-02 8:09 ` Martin Peres
2021-07-02 15:07 ` Michal Wajdeczko
2021-07-03 8:21 ` Martin Peres
2021-07-07 0:57 ` John Harrison
2021-07-07 7:47 ` Pekka Paalanen
2021-07-07 10:11 ` Michal Wajdeczko
2021-07-15 0:49 ` Matthew Brost
2021-06-24 7:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission support Patchwork
2021-06-24 7:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-24 7:47 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-07-12 19:23 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev2) Patchwork
2021-10-22 9:35 ` [Intel-gfx] [PATCH 00/47] GuC submission support Joonas Lahtinen
2021-10-22 16:42 ` Matthew Brost
2021-10-25 9:37 ` Joonas Lahtinen
2021-10-25 15:15 ` Matthew Brost
2021-10-26 8:59 ` Joonas Lahtinen
2021-10-26 15:43 ` Matthew Brost
2021-10-26 15:51 ` Matthew Brost
2021-10-27 9:21 ` Joonas Lahtinen
2021-10-25 17:06 ` John Harrison
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