* [PATCH RFC v5 01/12] linux-header: Update linux/kvm.h
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
@ 2021-04-12 6:52 ` Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
` (10 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Yifei Jiang @ 2021-04-12 6:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: kvm-riscv, kvm, libvir-list, anup.patel, palmer,
Alistair.Francis, sagark, kbastian, bin.meng, fanliang, wu.wubin,
zhang.zhanghailiang, yinyipeng1, Yifei Jiang
Update linux-headers/linux/kvm.h from
https://github.com/avpatel/linux/tree/riscv_kvm_v17.
Only use this header file, so here do not update all linux headers by
update-linux-headers.sh until above KVM series is accepted.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
| 97 +++++++++++++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 020b62a619..1e92fd2a76 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -216,6 +216,20 @@ struct kvm_hyperv_exit {
} u;
};
+struct kvm_xen_exit {
+#define KVM_EXIT_XEN_HCALL 1
+ __u32 type;
+ union {
+ struct {
+ __u32 longmode;
+ __u32 cpl;
+ __u64 input;
+ __u64 result;
+ __u64 params[6];
+ } hcall;
+ } u;
+};
+
#define KVM_S390_GET_SKEYS_NONE 1
#define KVM_S390_SKEYS_MAX 1048576
@@ -251,6 +265,10 @@ struct kvm_hyperv_exit {
#define KVM_EXIT_X86_RDMSR 29
#define KVM_EXIT_X86_WRMSR 30
#define KVM_EXIT_DIRTY_RING_FULL 31
+#define KVM_EXIT_AP_RESET_HOLD 32
+#define KVM_EXIT_X86_BUS_LOCK 33
+#define KVM_EXIT_XEN 34
+#define KVM_EXIT_RISCV_SBI 35
/* For KVM_EXIT_INTERNAL_ERROR */
/* Emulate instruction failed. */
@@ -427,6 +445,15 @@ struct kvm_run {
__u32 index; /* kernel -> user */
__u64 data; /* kernel <-> user */
} msr;
+ /* KVM_EXIT_XEN */
+ struct kvm_xen_exit xen;
+ /* KVM_EXIT_RISCV_SBI */
+ struct {
+ unsigned long extension_id;
+ unsigned long function_id;
+ unsigned long args[6];
+ unsigned long ret[2];
+ } riscv_sbi;
/* Fix the size of the union. */
char padding[256];
};
@@ -573,6 +600,7 @@ struct kvm_vapic_addr {
#define KVM_MP_STATE_CHECK_STOP 6
#define KVM_MP_STATE_OPERATING 7
#define KVM_MP_STATE_LOAD 8
+#define KVM_MP_STATE_AP_RESET_HOLD 9
struct kvm_mp_state {
__u32 mp_state;
@@ -1056,6 +1084,8 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_ENFORCE_PV_FEATURE_CPUID 190
#define KVM_CAP_SYS_HYPERV_CPUID 191
#define KVM_CAP_DIRTY_LOG_RING 192
+#define KVM_CAP_X86_BUS_LOCK_EXIT 193
+#define KVM_CAP_PPC_DAWR1 194
#ifdef KVM_CAP_IRQ_ROUTING
@@ -1129,6 +1159,11 @@ struct kvm_x86_mce {
#endif
#ifdef KVM_CAP_XEN_HVM
+#define KVM_XEN_HVM_CONFIG_HYPERCALL_MSR (1 << 0)
+#define KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL (1 << 1)
+#define KVM_XEN_HVM_CONFIG_SHARED_INFO (1 << 2)
+#define KVM_XEN_HVM_CONFIG_RUNSTATE (1 << 3)
+
struct kvm_xen_hvm_config {
__u32 flags;
__u32 msr;
@@ -1563,6 +1598,57 @@ struct kvm_pv_cmd {
/* Available with KVM_CAP_DIRTY_LOG_RING */
#define KVM_RESET_DIRTY_RINGS _IO(KVMIO, 0xc7)
+/* Per-VM Xen attributes */
+#define KVM_XEN_HVM_GET_ATTR _IOWR(KVMIO, 0xc8, struct kvm_xen_hvm_attr)
+#define KVM_XEN_HVM_SET_ATTR _IOW(KVMIO, 0xc9, struct kvm_xen_hvm_attr)
+
+struct kvm_xen_hvm_attr {
+ __u16 type;
+ __u16 pad[3];
+ union {
+ __u8 long_mode;
+ __u8 vector;
+ struct {
+ __u64 gfn;
+ } shared_info;
+ __u64 pad[8];
+ } u;
+};
+
+/* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_SHARED_INFO */
+#define KVM_XEN_ATTR_TYPE_LONG_MODE 0x0
+#define KVM_XEN_ATTR_TYPE_SHARED_INFO 0x1
+#define KVM_XEN_ATTR_TYPE_UPCALL_VECTOR 0x2
+
+/* Per-vCPU Xen attributes */
+#define KVM_XEN_VCPU_GET_ATTR _IOWR(KVMIO, 0xca, struct kvm_xen_vcpu_attr)
+#define KVM_XEN_VCPU_SET_ATTR _IOW(KVMIO, 0xcb, struct kvm_xen_vcpu_attr)
+
+struct kvm_xen_vcpu_attr {
+ __u16 type;
+ __u16 pad[3];
+ union {
+ __u64 gpa;
+ __u64 pad[8];
+ struct {
+ __u64 state;
+ __u64 state_entry_time;
+ __u64 time_running;
+ __u64 time_runnable;
+ __u64 time_blocked;
+ __u64 time_offline;
+ } runstate;
+ } u;
+};
+
+/* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_SHARED_INFO */
+#define KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO 0x0
+#define KVM_XEN_VCPU_ATTR_TYPE_VCPU_TIME_INFO 0x1
+#define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADDR 0x2
+#define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_CURRENT 0x3
+#define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_DATA 0x4
+#define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADJUST 0x5
+
/* Secure Encrypted Virtualization command */
enum sev_cmd_id {
/* Guest initialization commands */
@@ -1591,6 +1677,8 @@ enum sev_cmd_id {
KVM_SEV_DBG_ENCRYPT,
/* Guest certificates commands */
KVM_SEV_CERT_EXPORT,
+ /* Attestation report */
+ KVM_SEV_GET_ATTESTATION_REPORT,
KVM_SEV_NR_MAX,
};
@@ -1643,6 +1731,12 @@ struct kvm_sev_dbg {
__u32 len;
};
+struct kvm_sev_attestation_report {
+ __u8 mnonce[16];
+ __u64 uaddr;
+ __u32 len;
+};
+
#define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0)
#define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1)
#define KVM_DEV_ASSIGN_MASK_INTX (1 << 2)
@@ -1764,4 +1858,7 @@ struct kvm_dirty_gfn {
__u64 offset;
};
+#define KVM_BUS_LOCK_DETECTION_OFF (1 << 0)
+#define KVM_BUS_LOCK_DETECTION_EXIT (1 << 1)
+
#endif /* __LINUX_KVM_H */
--
2.19.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH RFC v5 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 01/12] linux-header: Update linux/kvm.h Yifei Jiang
@ 2021-04-12 6:52 ` Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
` (9 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Yifei Jiang @ 2021-04-12 6:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: kvm-riscv, kvm, libvir-list, anup.patel, palmer,
Alistair.Francis, sagark, kbastian, bin.meng, fanliang, wu.wubin,
zhang.zhanghailiang, yinyipeng1, Yifei Jiang, Alistair Francis
Add target/riscv/kvm.c to place kvm_arch_* function needed by
kvm/kvm-all.c. Meanwhile, add kvm support in meson.build file.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
meson.build | 2 +
target/riscv/kvm.c | 133 +++++++++++++++++++++++++++++++++++++++
target/riscv/meson.build | 1 +
3 files changed, 136 insertions(+)
create mode 100644 target/riscv/kvm.c
diff --git a/meson.build b/meson.build
index c6f4b0cf5e..1eab53f03e 100644
--- a/meson.build
+++ b/meson.build
@@ -72,6 +72,8 @@ elif cpu in ['ppc', 'ppc64']
kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
elif cpu in ['mips', 'mips64']
kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
+elif cpu in ['riscv32', 'riscv64']
+ kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
else
kvm_targets = []
endif
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
new file mode 100644
index 0000000000..687dd4b621
--- /dev/null
+++ b/target/riscv/kvm.c
@@ -0,0 +1,133 @@
+/*
+ * RISC-V implementation of KVM hooks
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include <sys/ioctl.h>
+
+#include <linux/kvm.h>
+
+#include "qemu-common.h"
+#include "qemu/timer.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "sysemu/kvm_int.h"
+#include "cpu.h"
+#include "trace.h"
+#include "hw/pci/pci.h"
+#include "exec/memattrs.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "qemu/log.h"
+#include "hw/loader.h"
+
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+ KVM_CAP_LAST_INFO
+};
+
+int kvm_arch_get_registers(CPUState *cs)
+{
+ return 0;
+}
+
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+ return 0;
+}
+
+int kvm_arch_release_virq_post(int virq)
+{
+ return 0;
+}
+
+int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
+ uint64_t address, uint32_t data, PCIDevice *dev)
+{
+ return 0;
+}
+
+int kvm_arch_destroy_vcpu(CPUState *cs)
+{
+ return 0;
+}
+
+unsigned long kvm_arch_vcpu_id(CPUState *cpu)
+{
+ return cpu->cpu_index;
+}
+
+void kvm_arch_init_irq_routing(KVMState *s)
+{
+}
+
+int kvm_arch_init_vcpu(CPUState *cs)
+{
+ return 0;
+}
+
+int kvm_arch_msi_data_to_gsi(uint32_t data)
+{
+ abort();
+}
+
+int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
+ int vector, PCIDevice *dev)
+{
+ return 0;
+}
+
+int kvm_arch_init(MachineState *ms, KVMState *s)
+{
+ return 0;
+}
+
+int kvm_arch_irqchip_create(KVMState *s)
+{
+ return 0;
+}
+
+int kvm_arch_process_async_events(CPUState *cs)
+{
+ return 0;
+}
+
+void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
+{
+}
+
+MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
+{
+ return MEMTXATTRS_UNSPECIFIED;
+}
+
+bool kvm_arch_stop_on_emulation_error(CPUState *cs)
+{
+ return true;
+}
+
+int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+{
+ return 0;
+}
+
+bool kvm_arch_cpu_check_are_resettable(void)
+{
+ return true;
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 88ab850682..32afd6e882 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -23,6 +23,7 @@ riscv_ss.add(files(
'vector_helper.c',
'translate.c',
))
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
riscv_softmmu_ss = ss.source_set()
riscv_softmmu_ss.add(files(
--
2.19.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 01/12] linux-header: Update linux/kvm.h Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
@ 2021-04-12 6:52 ` Yifei Jiang
2021-04-14 22:32 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
` (8 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Yifei Jiang @ 2021-04-12 6:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: kvm-riscv, kvm, libvir-list, anup.patel, palmer,
Alistair.Francis, sagark, kbastian, bin.meng, fanliang, wu.wubin,
zhang.zhanghailiang, yinyipeng1, Yifei Jiang
Get isa info from kvm while kvm init.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/kvm.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 687dd4b621..0d924be33f 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -38,6 +38,18 @@
#include "qemu/log.h"
#include "hw/loader.h"
+static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
+{
+ __u64 id = KVM_REG_RISCV | type | idx;
+
+ if (riscv_cpu_is_32bit(env)) {
+ id |= KVM_REG_SIZE_U32;
+ } else {
+ id |= KVM_REG_SIZE_U64;
+ }
+ return id;
+}
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
@@ -79,7 +91,20 @@ void kvm_arch_init_irq_routing(KVMState *s)
int kvm_arch_init_vcpu(CPUState *cs)
{
- return 0;
+ int ret = 0;
+ target_ulong isa;
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ __u64 id;
+
+ id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa));
+ ret = kvm_get_one_reg(cs, id, &isa);
+ if (ret) {
+ return ret;
+ }
+ env->misa = isa | RVXLEN;
+
+ return ret;
}
int kvm_arch_msi_data_to_gsi(uint32_t data)
--
2.19.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu
2021-04-12 6:52 ` [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
@ 2021-04-14 22:32 ` Alistair Francis
0 siblings, 0 replies; 21+ messages in thread
From: Alistair Francis @ 2021-04-14 22:32 UTC (permalink / raw)
To: Yifei Jiang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Sagar Karandikar, open list:Overall, libvir-list,
Bastian Koppelmann, Anup Patel, yinyipeng, Alistair Francis,
kvm-riscv, Palmer Dabbelt, fanliang, Wubin (H),
Zhanghailiang
On Mon, Apr 12, 2021 at 4:53 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Get isa info from kvm while kvm init.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
> target/riscv/kvm.c | 27 ++++++++++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 687dd4b621..0d924be33f 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -38,6 +38,18 @@
> #include "qemu/log.h"
> #include "hw/loader.h"
>
> +static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
> +{
> + __u64 id = KVM_REG_RISCV | type | idx;
Can you use uint64_t instead of __u64?
Once that is fixed:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> +
> + if (riscv_cpu_is_32bit(env)) {
> + id |= KVM_REG_SIZE_U32;
> + } else {
> + id |= KVM_REG_SIZE_U64;
> + }
> + return id;
> +}
> +
> const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
> KVM_CAP_LAST_INFO
> };
> @@ -79,7 +91,20 @@ void kvm_arch_init_irq_routing(KVMState *s)
>
> int kvm_arch_init_vcpu(CPUState *cs)
> {
> - return 0;
> + int ret = 0;
> + target_ulong isa;
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> + __u64 id;
> +
> + id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa));
> + ret = kvm_get_one_reg(cs, id, &isa);
> + if (ret) {
> + return ret;
> + }
> + env->misa = isa | RVXLEN;
> +
> + return ret;
> }
>
> int kvm_arch_msi_data_to_gsi(uint32_t data)
> --
> 2.19.1
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
` (2 preceding siblings ...)
2021-04-12 6:52 ` [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
@ 2021-04-12 6:52 ` Yifei Jiang
2021-04-14 22:39 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
` (7 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Yifei Jiang @ 2021-04-12 6:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: kvm-riscv, kvm, libvir-list, anup.patel, palmer,
Alistair.Francis, sagark, kbastian, bin.meng, fanliang, wu.wubin,
zhang.zhanghailiang, yinyipeng1, Yifei Jiang
Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/kvm.c | 150 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 149 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 0d924be33f..63485d7b65 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -50,13 +50,161 @@ static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
return id;
}
+#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
+ KVM_REG_RISCV_CORE_REG(name))
+
+#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
+ KVM_REG_RISCV_CSR_REG(name))
+
+#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
+
+#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
+
+static int kvm_riscv_get_regs_core(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ target_ulong reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®);
+ if (ret) {
+ return ret;
+ }
+ env->pc = reg;
+
+ for (i = 1; i < 32; i++) {
+ __u64 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
+ ret = kvm_get_one_reg(cs, id, ®);
+ if (ret) {
+ return ret;
+ }
+ env->gpr[i] = reg;
+ }
+
+ return ret;
+}
+
+static int kvm_riscv_get_regs_csr(CPUState *cs)
+{
+ int ret = 0;
+ target_ulong reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sstatus), ®);
+ if (ret) {
+ return ret;
+ }
+ env->mstatus = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sie), ®);
+ if (ret) {
+ return ret;
+ }
+ env->mie = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stvec), ®);
+ if (ret) {
+ return ret;
+ }
+ env->stvec = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sscratch), ®);
+ if (ret) {
+ return ret;
+ }
+ env->sscratch = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sepc), ®);
+ if (ret) {
+ return ret;
+ }
+ env->sepc = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, scause), ®);
+ if (ret) {
+ return ret;
+ }
+ env->scause = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stval), ®);
+ if (ret) {
+ return ret;
+ }
+ env->sbadaddr = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sip), ®);
+ if (ret) {
+ return ret;
+ }
+ env->mip = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, satp), ®);
+ if (ret) {
+ return ret;
+ }
+ env->satp = reg;
+
+ return ret;
+}
+
+static int kvm_riscv_get_regs_fp(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (riscv_has_ext(env, RVD)) {
+ uint64_t reg;
+ for (i = 0; i < 32; i++) {
+ ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®);
+ if (ret) {
+ return ret;
+ }
+ env->fpr[i] = reg;
+ }
+ return ret;
+ }
+
+ if (riscv_has_ext(env, RVF)) {
+ uint32_t reg;
+ for (i = 0; i < 32; i++) {
+ ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®);
+ if (ret) {
+ return ret;
+ }
+ env->fpr[i] = reg;
+ }
+ return ret;
+ }
+
+ return ret;
+}
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
int kvm_arch_get_registers(CPUState *cs)
{
- return 0;
+ int ret = 0;
+
+ ret = kvm_riscv_get_regs_core(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_get_regs_csr(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_get_regs_fp(cs);
+ if (ret) {
+ return ret;
+ }
+
+ return ret;
}
int kvm_arch_put_registers(CPUState *cs, int level)
--
2.19.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers
2021-04-12 6:52 ` [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
@ 2021-04-14 22:39 ` Alistair Francis
0 siblings, 0 replies; 21+ messages in thread
From: Alistair Francis @ 2021-04-14 22:39 UTC (permalink / raw)
To: Yifei Jiang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Sagar Karandikar, open list:Overall, libvir-list,
Bastian Koppelmann, Anup Patel, yinyipeng, Alistair Francis,
kvm-riscv, Palmer Dabbelt, fanliang, Wubin (H),
Zhanghailiang
On Mon, Apr 12, 2021 at 4:58 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/kvm.c | 150 ++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 149 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 0d924be33f..63485d7b65 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -50,13 +50,161 @@ static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
> return id;
> }
>
> +#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
> + KVM_REG_RISCV_CORE_REG(name))
> +
> +#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
> + KVM_REG_RISCV_CSR_REG(name))
> +
> +#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
> +
> +#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
> +
> +static int kvm_riscv_get_regs_core(CPUState *cs)
> +{
> + int ret = 0;
> + int i;
> + target_ulong reg;
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®);
> + if (ret) {
> + return ret;
> + }
> + env->pc = reg;
> +
> + for (i = 1; i < 32; i++) {
> + __u64 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
> + ret = kvm_get_one_reg(cs, id, ®);
> + if (ret) {
> + return ret;
> + }
> + env->gpr[i] = reg;
> + }
> +
> + return ret;
> +}
> +
> +static int kvm_riscv_get_regs_csr(CPUState *cs)
> +{
> + int ret = 0;
> + target_ulong reg;
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sstatus), ®);
> + if (ret) {
> + return ret;
> + }
> + env->mstatus = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sie), ®);
> + if (ret) {
> + return ret;
> + }
> + env->mie = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stvec), ®);
> + if (ret) {
> + return ret;
> + }
> + env->stvec = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sscratch), ®);
> + if (ret) {
> + return ret;
> + }
> + env->sscratch = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sepc), ®);
> + if (ret) {
> + return ret;
> + }
> + env->sepc = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, scause), ®);
> + if (ret) {
> + return ret;
> + }
> + env->scause = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stval), ®);
> + if (ret) {
> + return ret;
> + }
> + env->sbadaddr = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sip), ®);
> + if (ret) {
> + return ret;
> + }
> + env->mip = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, satp), ®);
> + if (ret) {
> + return ret;
> + }
> + env->satp = reg;
> +
> + return ret;
> +}
> +
> +static int kvm_riscv_get_regs_fp(CPUState *cs)
> +{
> + int ret = 0;
> + int i;
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + if (riscv_has_ext(env, RVD)) {
> + uint64_t reg;
> + for (i = 0; i < 32; i++) {
> + ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®);
> + if (ret) {
> + return ret;
> + }
> + env->fpr[i] = reg;
> + }
> + return ret;
> + }
> +
> + if (riscv_has_ext(env, RVF)) {
> + uint32_t reg;
> + for (i = 0; i < 32; i++) {
> + ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®);
> + if (ret) {
> + return ret;
> + }
> + env->fpr[i] = reg;
> + }
> + return ret;
> + }
> +
> + return ret;
> +}
> +
> const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
> KVM_CAP_LAST_INFO
> };
>
> int kvm_arch_get_registers(CPUState *cs)
> {
> - return 0;
> + int ret = 0;
> +
> + ret = kvm_riscv_get_regs_core(cs);
> + if (ret) {
> + return ret;
> + }
> +
> + ret = kvm_riscv_get_regs_csr(cs);
> + if (ret) {
> + return ret;
> + }
> +
> + ret = kvm_riscv_get_regs_fp(cs);
> + if (ret) {
> + return ret;
> + }
> +
> + return ret;
> }
>
> int kvm_arch_put_registers(CPUState *cs, int level)
> --
> 2.19.1
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
` (3 preceding siblings ...)
2021-04-12 6:52 ` [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
@ 2021-04-12 6:52 ` Yifei Jiang
2021-04-14 22:46 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang
` (6 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Yifei Jiang @ 2021-04-12 6:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: kvm-riscv, kvm, libvir-list, anup.patel, palmer,
Alistair.Francis, sagark, kbastian, bin.meng, fanliang, wu.wubin,
zhang.zhanghailiang, yinyipeng1, Yifei Jiang
Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/kvm.c | 142 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 141 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 63485d7b65..9d1441952a 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -85,6 +85,31 @@ static int kvm_riscv_get_regs_core(CPUState *cs)
return ret;
}
+static int kvm_riscv_put_regs_core(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ target_ulong reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ reg = env->pc;
+ ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®);
+ if (ret) {
+ return ret;
+ }
+
+ for (i = 1; i < 32; i++) {
+ __u64 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
+ reg = env->gpr[i];
+ ret = kvm_set_one_reg(cs, id, ®);
+ if (ret) {
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
static int kvm_riscv_get_regs_csr(CPUState *cs)
{
int ret = 0;
@@ -148,6 +173,70 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
return ret;
}
+static int kvm_riscv_put_regs_csr(CPUState *cs)
+{
+ int ret = 0;
+ target_ulong reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ reg = env->mstatus;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sstatus), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->mie;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sie), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->stvec;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, stvec), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->sscratch;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sscratch), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->sepc;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sepc), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->scause;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, scause), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->sbadaddr;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, stval), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->mip;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sip), ®);
+ if (ret) {
+ return ret;
+ }
+
+ reg = env->satp;
+ ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, satp), ®);
+ if (ret) {
+ return ret;
+ }
+
+ return ret;
+}
+
+
static int kvm_riscv_get_regs_fp(CPUState *cs)
{
int ret = 0;
@@ -181,6 +270,40 @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
return ret;
}
+static int kvm_riscv_put_regs_fp(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (riscv_has_ext(env, RVD)) {
+ uint64_t reg;
+ for (i = 0; i < 32; i++) {
+ reg = env->fpr[i];
+ ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®);
+ if (ret) {
+ return ret;
+ }
+ }
+ return ret;
+ }
+
+ if (riscv_has_ext(env, RVF)) {
+ uint32_t reg;
+ for (i = 0; i < 32; i++) {
+ reg = env->fpr[i];
+ ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®);
+ if (ret) {
+ return ret;
+ }
+ }
+ return ret;
+ }
+
+ return ret;
+}
+
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
@@ -209,7 +332,24 @@ int kvm_arch_get_registers(CPUState *cs)
int kvm_arch_put_registers(CPUState *cs, int level)
{
- return 0;
+ int ret = 0;
+
+ ret = kvm_riscv_put_regs_core(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_put_regs_csr(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_put_regs_fp(cs);
+ if (ret) {
+ return ret;
+ }
+
+ return ret;
}
int kvm_arch_release_virq_post(int virq)
--
2.19.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers
2021-04-12 6:52 ` [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
@ 2021-04-14 22:46 ` Alistair Francis
0 siblings, 0 replies; 21+ messages in thread
From: Alistair Francis @ 2021-04-14 22:46 UTC (permalink / raw)
To: Yifei Jiang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Sagar Karandikar, open list:Overall, libvir-list,
Bastian Koppelmann, Anup Patel, yinyipeng, Alistair Francis,
kvm-riscv, Palmer Dabbelt, fanliang, Wubin (H),
Zhanghailiang
On Mon, Apr 12, 2021 at 4:56 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
> target/riscv/kvm.c | 142 ++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 141 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 63485d7b65..9d1441952a 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -85,6 +85,31 @@ static int kvm_riscv_get_regs_core(CPUState *cs)
> return ret;
> }
>
> +static int kvm_riscv_put_regs_core(CPUState *cs)
> +{
> + int ret = 0;
> + int i;
> + target_ulong reg;
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + reg = env->pc;
> + ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®);
> + if (ret) {
> + return ret;
> + }
> +
> + for (i = 1; i < 32; i++) {
> + __u64 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
Can you use uint64_t for the entire series instead?
> + reg = env->gpr[i];
> + ret = kvm_set_one_reg(cs, id, ®);
> + if (ret) {
> + return ret;
> + }
> + }
> +
> + return ret;
> +}
> +
> static int kvm_riscv_get_regs_csr(CPUState *cs)
> {
> int ret = 0;
> @@ -148,6 +173,70 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
> return ret;
> }
>
> +static int kvm_riscv_put_regs_csr(CPUState *cs)
> +{
> + int ret = 0;
> + target_ulong reg;
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + reg = env->mstatus;
> + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sstatus), ®);
> + if (ret) {
> + return ret;
> + }
> +
> + reg = env->mie;
> + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sie), ®);
> + if (ret) {
> + return ret;
> + }
> +
> + reg = env->stvec;
> + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, stvec), ®);
> + if (ret) {
> + return ret;
> + }
> +
> + reg = env->sscratch;
> + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sscratch), ®);
> + if (ret) {
> + return ret;
> + }
> +
> + reg = env->sepc;
> + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sepc), ®);
> + if (ret) {
> + return ret;
> + }
> +
> + reg = env->scause;
> + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, scause), ®);
> + if (ret) {
> + return ret;
> + }
> +
> + reg = env->sbadaddr;
This will change soon-ish as my next PR converts this to stval.
> + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, stval), ®);
> + if (ret) {
> + return ret;
> + }
> +
> + reg = env->mip;
> + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, sip), ®);
> + if (ret) {
> + return ret;
> + }
> +
> + reg = env->satp;
> + ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, satp), ®);
> + if (ret) {
> + return ret;
> + }
> +
> + return ret;
> +}
> +
> +
Double line here.
Otherwise:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> static int kvm_riscv_get_regs_fp(CPUState *cs)
> {
> int ret = 0;
> @@ -181,6 +270,40 @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
> return ret;
> }
>
> +static int kvm_riscv_put_regs_fp(CPUState *cs)
> +{
> + int ret = 0;
> + int i;
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + if (riscv_has_ext(env, RVD)) {
> + uint64_t reg;
> + for (i = 0; i < 32; i++) {
> + reg = env->fpr[i];
> + ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®);
> + if (ret) {
> + return ret;
> + }
> + }
> + return ret;
> + }
> +
> + if (riscv_has_ext(env, RVF)) {
> + uint32_t reg;
> + for (i = 0; i < 32; i++) {
> + reg = env->fpr[i];
> + ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®);
> + if (ret) {
> + return ret;
> + }
> + }
> + return ret;
> + }
> +
> + return ret;
> +}
> +
> +
> const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
> KVM_CAP_LAST_INFO
> };
> @@ -209,7 +332,24 @@ int kvm_arch_get_registers(CPUState *cs)
>
> int kvm_arch_put_registers(CPUState *cs, int level)
> {
> - return 0;
> + int ret = 0;
> +
> + ret = kvm_riscv_put_regs_core(cs);
> + if (ret) {
> + return ret;
> + }
> +
> + ret = kvm_riscv_put_regs_csr(cs);
> + if (ret) {
> + return ret;
> + }
> +
> + ret = kvm_riscv_put_regs_fp(cs);
> + if (ret) {
> + return ret;
> + }
> +
> + return ret;
> }
>
> int kvm_arch_release_virq_post(int virq)
> --
> 2.19.1
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
` (4 preceding siblings ...)
2021-04-12 6:52 ` [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
@ 2021-04-12 6:52 ` Yifei Jiang
2021-04-14 22:48 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang
` (5 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Yifei Jiang @ 2021-04-12 6:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: kvm-riscv, kvm, libvir-list, anup.patel, palmer,
Alistair.Francis, sagark, kbastian, bin.meng, fanliang, wu.wubin,
zhang.zhanghailiang, yinyipeng1, Yifei Jiang
Get kernel and fdt start address in virt.c, and pass them to KVM
when cpu reset. In addition, add kvm_riscv.h to place riscv specific
interface.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
hw/riscv/boot.c | 11 +++++++++++
hw/riscv/virt.c | 7 +++++++
include/hw/riscv/boot.h | 1 +
target/riscv/cpu.c | 8 ++++++++
target/riscv/cpu.h | 3 +++
target/riscv/kvm-stub.c | 25 +++++++++++++++++++++++++
target/riscv/kvm.c | 13 +++++++++++++
target/riscv/kvm_riscv.h | 24 ++++++++++++++++++++++++
target/riscv/meson.build | 2 +-
9 files changed, 93 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/kvm-stub.c
create mode 100644 target/riscv/kvm_riscv.h
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0d38bb7426..b9741a647d 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -290,3 +290,14 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
return;
}
+
+void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
+{
+ CPUState *cs;
+
+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+ RISCVCPU *riscv_cpu = RISCV_CPU(cs);
+ riscv_cpu->env.kernel_addr = kernel_addr;
+ riscv_cpu->env.fdt_addr = fdt_addr;
+ }
+}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index c0dc69ff33..4a1fca139c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -728,6 +728,13 @@ static void virt_machine_init(MachineState *machine)
virt_memmap[VIRT_MROM].size, kernel_entry,
fdt_load_addr, machine->fdt);
+ /*
+ * Only direct boot kernel is currently supported for KVM VM,
+ * So here setup kernel start address and fdt address.
+ * TODO:Support firmware loading and integrate to TCG start
+ */
+ riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
+
/* SiFive Test MMIO device */
sifive_test_create(memmap[VIRT_TEST].base);
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 11a21dd584..28d838cc29 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -51,5 +51,6 @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
hwaddr rom_size,
uint32_t reset_vec_size,
uint64_t kernel_entry);
+void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr);
#endif /* RISCV_BOOT_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b..dd34ab4978 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -29,6 +29,8 @@
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "fpu/softfloat-helpers.h"
+#include "sysemu/kvm.h"
+#include "kvm_riscv.h"
/* RISC-V CPU definitions */
@@ -361,6 +363,12 @@ static void riscv_cpu_reset(DeviceState *dev)
cs->exception_index = EXCP_NONE;
env->load_res = -1;
set_default_nan_mode(1, &env->fp_status);
+
+#ifndef CONFIG_USER_ONLY
+ if (kvm_enabled()) {
+ kvm_riscv_reset_vcpu(cpu);
+ }
+#endif
}
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0a33d387ba..a489d94187 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -243,6 +243,9 @@ struct CPURISCVState {
/* Fields from here on are preserved across CPU reset. */
QEMUTimer *timer; /* Internal timer */
+
+ hwaddr kernel_addr;
+ hwaddr fdt_addr;
};
OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
new file mode 100644
index 0000000000..39b96fe3f4
--- /dev/null
+++ b/target/riscv/kvm-stub.c
@@ -0,0 +1,25 @@
+/*
+ * QEMU KVM RISC-V specific function stubs
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "kvm_riscv.h"
+
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
+{
+ abort();
+}
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 9d1441952a..79c931acb4 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -37,6 +37,7 @@
#include "hw/irq.h"
#include "qemu/log.h"
#include "hw/loader.h"
+#include "kvm_riscv.h"
static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
{
@@ -440,6 +441,18 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
return 0;
}
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
+{
+ CPURISCVState *env = &cpu->env;
+
+ if (!kvm_enabled()) {
+ return;
+ }
+ env->pc = cpu->env.kernel_addr;
+ env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
+ env->gpr[11] = cpu->env.fdt_addr; /* a1 */
+}
+
bool kvm_arch_cpu_check_are_resettable(void)
{
return true;
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
new file mode 100644
index 0000000000..f38c82bf59
--- /dev/null
+++ b/target/riscv/kvm_riscv.h
@@ -0,0 +1,24 @@
+/*
+ * QEMU KVM support -- RISC-V specific functions.
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_KVM_RISCV_H
+#define QEMU_KVM_RISCV_H
+
+void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+
+#endif
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 32afd6e882..0f63e3824d 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -23,7 +23,7 @@ riscv_ss.add(files(
'vector_helper.c',
'translate.c',
))
-riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
riscv_softmmu_ss = ss.source_set()
riscv_softmmu_ss.add(files(
--
2.19.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM
2021-04-12 6:52 ` [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang
@ 2021-04-14 22:48 ` Alistair Francis
0 siblings, 0 replies; 21+ messages in thread
From: Alistair Francis @ 2021-04-14 22:48 UTC (permalink / raw)
To: Yifei Jiang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Sagar Karandikar, open list:Overall, libvir-list,
Bastian Koppelmann, Anup Patel, yinyipeng, Alistair Francis,
kvm-riscv, Palmer Dabbelt, fanliang, Wubin (H),
Zhanghailiang
On Mon, Apr 12, 2021 at 4:56 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Get kernel and fdt start address in virt.c, and pass them to KVM
> when cpu reset. In addition, add kvm_riscv.h to place riscv specific
> interface.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/boot.c | 11 +++++++++++
> hw/riscv/virt.c | 7 +++++++
> include/hw/riscv/boot.h | 1 +
> target/riscv/cpu.c | 8 ++++++++
> target/riscv/cpu.h | 3 +++
> target/riscv/kvm-stub.c | 25 +++++++++++++++++++++++++
> target/riscv/kvm.c | 13 +++++++++++++
> target/riscv/kvm_riscv.h | 24 ++++++++++++++++++++++++
> target/riscv/meson.build | 2 +-
> 9 files changed, 93 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/kvm-stub.c
> create mode 100644 target/riscv/kvm_riscv.h
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 0d38bb7426..b9741a647d 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -290,3 +290,14 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
>
> return;
> }
> +
> +void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
> +{
> + CPUState *cs;
> +
> + for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
> + RISCVCPU *riscv_cpu = RISCV_CPU(cs);
> + riscv_cpu->env.kernel_addr = kernel_addr;
> + riscv_cpu->env.fdt_addr = fdt_addr;
> + }
> +}
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index c0dc69ff33..4a1fca139c 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -728,6 +728,13 @@ static void virt_machine_init(MachineState *machine)
> virt_memmap[VIRT_MROM].size, kernel_entry,
> fdt_load_addr, machine->fdt);
>
> + /*
> + * Only direct boot kernel is currently supported for KVM VM,
> + * So here setup kernel start address and fdt address.
> + * TODO:Support firmware loading and integrate to TCG start
> + */
> + riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
> +
> /* SiFive Test MMIO device */
> sifive_test_create(memmap[VIRT_TEST].base);
>
> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
> index 11a21dd584..28d838cc29 100644
> --- a/include/hw/riscv/boot.h
> +++ b/include/hw/riscv/boot.h
> @@ -51,5 +51,6 @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
> hwaddr rom_size,
> uint32_t reset_vec_size,
> uint64_t kernel_entry);
> +void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr);
>
> #endif /* RISCV_BOOT_H */
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 7d6ed80f6b..dd34ab4978 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -29,6 +29,8 @@
> #include "hw/qdev-properties.h"
> #include "migration/vmstate.h"
> #include "fpu/softfloat-helpers.h"
> +#include "sysemu/kvm.h"
> +#include "kvm_riscv.h"
>
> /* RISC-V CPU definitions */
>
> @@ -361,6 +363,12 @@ static void riscv_cpu_reset(DeviceState *dev)
> cs->exception_index = EXCP_NONE;
> env->load_res = -1;
> set_default_nan_mode(1, &env->fp_status);
> +
> +#ifndef CONFIG_USER_ONLY
> + if (kvm_enabled()) {
> + kvm_riscv_reset_vcpu(cpu);
> + }
> +#endif
> }
>
> static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0a33d387ba..a489d94187 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -243,6 +243,9 @@ struct CPURISCVState {
>
> /* Fields from here on are preserved across CPU reset. */
> QEMUTimer *timer; /* Internal timer */
> +
> + hwaddr kernel_addr;
> + hwaddr fdt_addr;
> };
>
> OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
> diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
> new file mode 100644
> index 0000000000..39b96fe3f4
> --- /dev/null
> +++ b/target/riscv/kvm-stub.c
> @@ -0,0 +1,25 @@
> +/*
> + * QEMU KVM RISC-V specific function stubs
> + *
> + * Copyright (c) 2020 Huawei Technologies Co., Ltd
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +#include "kvm_riscv.h"
> +
> +void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> +{
> + abort();
> +}
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 9d1441952a..79c931acb4 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -37,6 +37,7 @@
> #include "hw/irq.h"
> #include "qemu/log.h"
> #include "hw/loader.h"
> +#include "kvm_riscv.h"
>
> static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
> {
> @@ -440,6 +441,18 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
> return 0;
> }
>
> +void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> +{
> + CPURISCVState *env = &cpu->env;
> +
> + if (!kvm_enabled()) {
> + return;
> + }
> + env->pc = cpu->env.kernel_addr;
> + env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
> + env->gpr[11] = cpu->env.fdt_addr; /* a1 */
> +}
> +
> bool kvm_arch_cpu_check_are_resettable(void)
> {
> return true;
> diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
> new file mode 100644
> index 0000000000..f38c82bf59
> --- /dev/null
> +++ b/target/riscv/kvm_riscv.h
> @@ -0,0 +1,24 @@
> +/*
> + * QEMU KVM support -- RISC-V specific functions.
> + *
> + * Copyright (c) 2020 Huawei Technologies Co., Ltd
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef QEMU_KVM_RISCV_H
> +#define QEMU_KVM_RISCV_H
> +
> +void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
> +
> +#endif
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index 32afd6e882..0f63e3824d 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -23,7 +23,7 @@ riscv_ss.add(files(
> 'vector_helper.c',
> 'translate.c',
> ))
> -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
> +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
>
> riscv_softmmu_ss = ss.source_set()
> riscv_softmmu_ss.add(files(
> --
> 2.19.1
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
` (5 preceding siblings ...)
2021-04-12 6:52 ` [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang
@ 2021-04-12 6:52 ` Yifei Jiang
2021-04-14 22:50 ` Alistair Francis
2021-04-30 4:53 ` Anup Patel
2021-04-12 6:52 ` [PATCH RFC v5 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
` (4 subsequent siblings)
11 siblings, 2 replies; 21+ messages in thread
From: Yifei Jiang @ 2021-04-12 6:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: kvm-riscv, kvm, libvir-list, anup.patel, palmer,
Alistair.Francis, sagark, kbastian, bin.meng, fanliang, wu.wubin,
zhang.zhanghailiang, yinyipeng1, Yifei Jiang
Only support supervisor external interrupt currently.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
hw/intc/sifive_plic.c | 29 ++++++++++++++++++++---------
target/riscv/kvm-stub.c | 5 +++++
target/riscv/kvm.c | 20 ++++++++++++++++++++
target/riscv/kvm_riscv.h | 1 +
4 files changed, 46 insertions(+), 9 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 97a1a27a9a..2746eb7a05 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -31,6 +31,8 @@
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
#include "migration/vmstate.h"
+#include "sysemu/kvm.h"
+#include "kvm_riscv.h"
#define RISCV_DEBUG_PLIC 0
@@ -147,15 +149,24 @@ static void sifive_plic_update(SiFivePLICState *plic)
continue;
}
int level = sifive_plic_irqs_pending(plic, addrid);
- switch (mode) {
- case PLICMode_M:
- riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
- break;
- case PLICMode_S:
- riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
- break;
- default:
- break;
+ if (kvm_enabled()) {
+ if (mode == PLICMode_M) {
+ continue;
+ }
+ kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level);
+ } else {
+ switch (mode) {
+ case PLICMode_M:
+ riscv_cpu_update_mip(RISCV_CPU(cpu),
+ MIP_MEIP, BOOL_TO_MASK(level));
+ break;
+ case PLICMode_S:
+ riscv_cpu_update_mip(RISCV_CPU(cpu),
+ MIP_SEIP, BOOL_TO_MASK(level));
+ break;
+ default:
+ break;
+ }
}
}
diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
index 39b96fe3f4..4e8fc31a21 100644
--- a/target/riscv/kvm-stub.c
+++ b/target/riscv/kvm-stub.c
@@ -23,3 +23,8 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
{
abort();
}
+
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+ abort();
+}
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 79c931acb4..da63535812 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -453,6 +453,26 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
env->gpr[11] = cpu->env.fdt_addr; /* a1 */
}
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+ int ret;
+ unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
+
+ if (irq != IRQ_S_EXT) {
+ return;
+ }
+
+ if (!kvm_enabled()) {
+ return;
+ }
+
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
+ if (ret < 0) {
+ perror("Set irq failed");
+ abort();
+ }
+}
+
bool kvm_arch_cpu_check_are_resettable(void)
{
return true;
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index f38c82bf59..ed281bdce0 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -20,5 +20,6 @@
#define QEMU_KVM_RISCV_H
void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
#endif
--
2.19.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
2021-04-12 6:52 ` [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang
@ 2021-04-14 22:50 ` Alistair Francis
2021-04-30 4:53 ` Anup Patel
1 sibling, 0 replies; 21+ messages in thread
From: Alistair Francis @ 2021-04-14 22:50 UTC (permalink / raw)
To: Yifei Jiang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Sagar Karandikar, open list:Overall, libvir-list,
Bastian Koppelmann, Anup Patel, yinyipeng, Alistair Francis,
kvm-riscv, Palmer Dabbelt, fanliang, Wubin (H),
Zhanghailiang
On Mon, Apr 12, 2021 at 4:57 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Only support supervisor external interrupt currently.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/intc/sifive_plic.c | 29 ++++++++++++++++++++---------
> target/riscv/kvm-stub.c | 5 +++++
> target/riscv/kvm.c | 20 ++++++++++++++++++++
> target/riscv/kvm_riscv.h | 1 +
> 4 files changed, 46 insertions(+), 9 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index 97a1a27a9a..2746eb7a05 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -31,6 +31,8 @@
> #include "target/riscv/cpu.h"
> #include "sysemu/sysemu.h"
> #include "migration/vmstate.h"
> +#include "sysemu/kvm.h"
> +#include "kvm_riscv.h"
>
> #define RISCV_DEBUG_PLIC 0
>
> @@ -147,15 +149,24 @@ static void sifive_plic_update(SiFivePLICState *plic)
> continue;
> }
> int level = sifive_plic_irqs_pending(plic, addrid);
> - switch (mode) {
> - case PLICMode_M:
> - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
> - break;
> - case PLICMode_S:
> - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
> - break;
> - default:
> - break;
> + if (kvm_enabled()) {
> + if (mode == PLICMode_M) {
> + continue;
> + }
> + kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level);
> + } else {
> + switch (mode) {
> + case PLICMode_M:
> + riscv_cpu_update_mip(RISCV_CPU(cpu),
> + MIP_MEIP, BOOL_TO_MASK(level));
> + break;
> + case PLICMode_S:
> + riscv_cpu_update_mip(RISCV_CPU(cpu),
> + MIP_SEIP, BOOL_TO_MASK(level));
> + break;
> + default:
> + break;
> + }
> }
> }
>
> diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
> index 39b96fe3f4..4e8fc31a21 100644
> --- a/target/riscv/kvm-stub.c
> +++ b/target/riscv/kvm-stub.c
> @@ -23,3 +23,8 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> {
> abort();
> }
> +
> +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
> +{
> + abort();
> +}
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 79c931acb4..da63535812 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -453,6 +453,26 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> env->gpr[11] = cpu->env.fdt_addr; /* a1 */
> }
>
> +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
> +{
> + int ret;
> + unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
> +
> + if (irq != IRQ_S_EXT) {
> + return;
> + }
> +
> + if (!kvm_enabled()) {
> + return;
> + }
> +
> + ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
> + if (ret < 0) {
> + perror("Set irq failed");
> + abort();
> + }
> +}
> +
> bool kvm_arch_cpu_check_are_resettable(void)
> {
> return true;
> diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
> index f38c82bf59..ed281bdce0 100644
> --- a/target/riscv/kvm_riscv.h
> +++ b/target/riscv/kvm_riscv.h
> @@ -20,5 +20,6 @@
> #define QEMU_KVM_RISCV_H
>
> void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
> +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
>
> #endif
> --
> 2.19.1
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
2021-04-12 6:52 ` [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang
2021-04-14 22:50 ` Alistair Francis
@ 2021-04-30 4:53 ` Anup Patel
2021-05-06 7:59 ` Jiangyifei
1 sibling, 1 reply; 21+ messages in thread
From: Anup Patel @ 2021-04-30 4:53 UTC (permalink / raw)
To: Yifei Jiang
Cc: QEMU Developers, open list:RISC-V, kvm-riscv, KVM General,
libvir-list, Anup Patel, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann, Bin Meng, fanliang,
Wubin (H),
Zhanghailiang, yinyipeng
On Mon, Apr 12, 2021 at 12:24 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Only support supervisor external interrupt currently.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
> hw/intc/sifive_plic.c | 29 ++++++++++++++++++++---------
> target/riscv/kvm-stub.c | 5 +++++
> target/riscv/kvm.c | 20 ++++++++++++++++++++
> target/riscv/kvm_riscv.h | 1 +
> 4 files changed, 46 insertions(+), 9 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index 97a1a27a9a..2746eb7a05 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -31,6 +31,8 @@
> #include "target/riscv/cpu.h"
> #include "sysemu/sysemu.h"
> #include "migration/vmstate.h"
> +#include "sysemu/kvm.h"
> +#include "kvm_riscv.h"
>
> #define RISCV_DEBUG_PLIC 0
>
> @@ -147,15 +149,24 @@ static void sifive_plic_update(SiFivePLICState *plic)
> continue;
> }
> int level = sifive_plic_irqs_pending(plic, addrid);
> - switch (mode) {
> - case PLICMode_M:
> - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
> - break;
> - case PLICMode_S:
> - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
> - break;
> - default:
> - break;
> + if (kvm_enabled()) {
> + if (mode == PLICMode_M) {
> + continue;
> + }
> + kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level);
> + } else {
> + switch (mode) {
> + case PLICMode_M:
> + riscv_cpu_update_mip(RISCV_CPU(cpu),
> + MIP_MEIP, BOOL_TO_MASK(level));
> + break;
> + case PLICMode_S:
> + riscv_cpu_update_mip(RISCV_CPU(cpu),
> + MIP_SEIP, BOOL_TO_MASK(level));
> + break;
> + default:
> + break;
> + }
I am not comfortable with this patch.
This way we will endup calling kvm_riscv_set_irq() from various
places in hw/intc and hw/riscv.
I suggest to extend riscv_cpu_update_mip() such that when kvm is
enabled riscv_cpu_update_mip() will:
1) Consider only MIP_SEIP bit in "mask" parameter and all other
bits in "mask" parameter will be ignored probably with warning
2) When the MIP_SEIP bit is set in "mask" call kvm_riscv_set_irq()
to change the IRQ state in the KVM module.
Regards,
Anup
> }
> }
>
> diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
> index 39b96fe3f4..4e8fc31a21 100644
> --- a/target/riscv/kvm-stub.c
> +++ b/target/riscv/kvm-stub.c
> @@ -23,3 +23,8 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> {
> abort();
> }
> +
> +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
> +{
> + abort();
> +}
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 79c931acb4..da63535812 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -453,6 +453,26 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> env->gpr[11] = cpu->env.fdt_addr; /* a1 */
> }
>
> +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
> +{
> + int ret;
> + unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
> +
> + if (irq != IRQ_S_EXT) {
> + return;
> + }
> +
> + if (!kvm_enabled()) {
> + return;
> + }
> +
> + ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
> + if (ret < 0) {
> + perror("Set irq failed");
> + abort();
> + }
> +}
> +
> bool kvm_arch_cpu_check_are_resettable(void)
> {
> return true;
> diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
> index f38c82bf59..ed281bdce0 100644
> --- a/target/riscv/kvm_riscv.h
> +++ b/target/riscv/kvm_riscv.h
> @@ -20,5 +20,6 @@
> #define QEMU_KVM_RISCV_H
>
> void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
> +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
>
> #endif
> --
> 2.19.1
>
>
> --
> kvm-riscv mailing list
> kvm-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kvm-riscv
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
2021-04-30 4:53 ` Anup Patel
@ 2021-05-06 7:59 ` Jiangyifei
0 siblings, 0 replies; 21+ messages in thread
From: Jiangyifei @ 2021-05-06 7:59 UTC (permalink / raw)
To: Anup Patel
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, KVM General,
libvir-list, Bastian Koppelmann, Anup Patel, QEMU Developers,
yinyipeng, Palmer Dabbelt, kvm-riscv, Alistair Francis,
Fanliang (EulerOS), Wubin (H),
Zhanghailiang
> -----Original Message-----
> From: Qemu-riscv
> [mailto:qemu-riscv-bounces+jiangyifei=huawei.com@nongnu.org] On Behalf Of
> Anup Patel
> Sent: Friday, April 30, 2021 12:54 PM
> To: Jiangyifei <jiangyifei@huawei.com>
> Cc: Bin Meng <bin.meng@windriver.com>; open list:RISC-V
> <qemu-riscv@nongnu.org>; Sagar Karandikar <sagark@eecs.berkeley.edu>;
> KVM General <kvm@vger.kernel.org>; libvir-list@redhat.com; Bastian
> Koppelmann <kbastian@mail.uni-paderborn.de>; Anup Patel
> <anup.patel@wdc.com>; QEMU Developers <qemu-devel@nongnu.org>;
> yinyipeng <yinyipeng1@huawei.com>; Palmer Dabbelt <palmer@dabbelt.com>;
> kvm-riscv@lists.infradead.org; Alistair Francis <Alistair.Francis@wdc.com>;
> Fanliang (EulerOS) <fanliang@huawei.com>; Wubin (H)
> <wu.wubin@huawei.com>; Zhanghailiang <zhang.zhanghailiang@huawei.com>
> Subject: Re: [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by
> KVM when kvm enabled
>
> On Mon, Apr 12, 2021 at 12:24 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
> >
> > Only support supervisor external interrupt currently.
> >
> > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> > Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> > ---
> > hw/intc/sifive_plic.c | 29 ++++++++++++++++++++---------
> > target/riscv/kvm-stub.c | 5 +++++
> > target/riscv/kvm.c | 20 ++++++++++++++++++++
> > target/riscv/kvm_riscv.h | 1 +
> > 4 files changed, 46 insertions(+), 9 deletions(-)
> >
> > diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index
> > 97a1a27a9a..2746eb7a05 100644
> > --- a/hw/intc/sifive_plic.c
> > +++ b/hw/intc/sifive_plic.c
> > @@ -31,6 +31,8 @@
> > #include "target/riscv/cpu.h"
> > #include "sysemu/sysemu.h"
> > #include "migration/vmstate.h"
> > +#include "sysemu/kvm.h"
> > +#include "kvm_riscv.h"
> >
> > #define RISCV_DEBUG_PLIC 0
> >
> > @@ -147,15 +149,24 @@ static void sifive_plic_update(SiFivePLICState *plic)
> > continue;
> > }
> > int level = sifive_plic_irqs_pending(plic, addrid);
> > - switch (mode) {
> > - case PLICMode_M:
> > - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP,
> BOOL_TO_MASK(level));
> > - break;
> > - case PLICMode_S:
> > - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP,
> BOOL_TO_MASK(level));
> > - break;
> > - default:
> > - break;
> > + if (kvm_enabled()) {
> > + if (mode == PLICMode_M) {
> > + continue;
> > + }
> > + kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level);
> > + } else {
> > + switch (mode) {
> > + case PLICMode_M:
> > + riscv_cpu_update_mip(RISCV_CPU(cpu),
> > + MIP_MEIP,
> BOOL_TO_MASK(level));
> > + break;
> > + case PLICMode_S:
> > + riscv_cpu_update_mip(RISCV_CPU(cpu),
> > + MIP_SEIP,
> BOOL_TO_MASK(level));
> > + break;
> > + default:
> > + break;
> > + }
>
> I am not comfortable with this patch.
>
> This way we will endup calling kvm_riscv_set_irq() from various places in
> hw/intc and hw/riscv.
>
> I suggest to extend riscv_cpu_update_mip() such that when kvm is enabled
> riscv_cpu_update_mip() will:
> 1) Consider only MIP_SEIP bit in "mask" parameter and all other
> bits in "mask" parameter will be ignored probably with warning
> 2) When the MIP_SEIP bit is set in "mask" call kvm_riscv_set_irq() to change
> the IRQ state in the KVM module.
>
> Regards,
> Anup
>
Yes, but riscv_cpu_update_mip() in target/riscv/cpu_helper.c is used to TCG. So it is not
appropriate to adapt for KVM.
We will move riscv_cpu_update_mip() to target/riscv/cpu.c and modify it according your
advice.
Regards,
Yifei
> > }
> > }
> >
> > diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c index
> > 39b96fe3f4..4e8fc31a21 100644
> > --- a/target/riscv/kvm-stub.c
> > +++ b/target/riscv/kvm-stub.c
> > @@ -23,3 +23,8 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) {
> > abort();
> > }
> > +
> > +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) {
> > + abort();
> > +}
> > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index
> > 79c931acb4..da63535812 100644
> > --- a/target/riscv/kvm.c
> > +++ b/target/riscv/kvm.c
> > @@ -453,6 +453,26 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> > env->gpr[11] = cpu->env.fdt_addr; /* a1 */
> > }
> >
> > +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) {
> > + int ret;
> > + unsigned virq = level ? KVM_INTERRUPT_SET :
> KVM_INTERRUPT_UNSET;
> > +
> > + if (irq != IRQ_S_EXT) {
> > + return;
> > + }
> > +
> > + if (!kvm_enabled()) {
> > + return;
> > + }
> > +
> > + ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
> > + if (ret < 0) {
> > + perror("Set irq failed");
> > + abort();
> > + }
> > +}
> > +
> > bool kvm_arch_cpu_check_are_resettable(void)
> > {
> > return true;
> > diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index
> > f38c82bf59..ed281bdce0 100644
> > --- a/target/riscv/kvm_riscv.h
> > +++ b/target/riscv/kvm_riscv.h
> > @@ -20,5 +20,6 @@
> > #define QEMU_KVM_RISCV_H
> >
> > void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
> > +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
> >
> > #endif
> > --
> > 2.19.1
> >
> >
> > --
> > kvm-riscv mailing list
> > kvm-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/kvm-riscv
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH RFC v5 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
` (6 preceding siblings ...)
2021-04-12 6:52 ` [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang
@ 2021-04-12 6:52 ` Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 09/12] target/riscv: Add host cpu type Yifei Jiang
` (3 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Yifei Jiang @ 2021-04-12 6:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: kvm-riscv, kvm, libvir-list, anup.patel, palmer,
Alistair.Francis, sagark, kbastian, bin.meng, fanliang, wu.wubin,
zhang.zhanghailiang, yinyipeng1, Yifei Jiang
Use char-fe to handle console sbi call, which implement early
console io while apply 'earlycon=sbi' into kernel parameters.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/kvm.c | 42 ++++++++++++++++-
target/riscv/sbi_ecall_interface.h | 72 ++++++++++++++++++++++++++++++
2 files changed, 113 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/sbi_ecall_interface.h
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index da63535812..f9707157e7 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -38,6 +38,8 @@
#include "qemu/log.h"
#include "hw/loader.h"
#include "kvm_riscv.h"
+#include "sbi_ecall_interface.h"
+#include "chardev/char-fe.h"
static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
{
@@ -436,9 +438,47 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
return true;
}
+static int kvm_riscv_handle_sbi(struct kvm_run *run)
+{
+ int ret = 0;
+ unsigned char ch;
+ switch (run->riscv_sbi.extension_id) {
+ case SBI_EXT_0_1_CONSOLE_PUTCHAR:
+ ch = run->riscv_sbi.args[0];
+ qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+ break;
+ case SBI_EXT_0_1_CONSOLE_GETCHAR:
+ ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
+ if (ret == sizeof(ch)) {
+ run->riscv_sbi.args[0] = ch;
+ } else {
+ run->riscv_sbi.args[0] = -1;
+ }
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: un-handled SBI EXIT, specific reasons is %lu\n",
+ __func__, run->riscv_sbi.extension_id);
+ ret = -1;
+ break;
+ }
+ return ret;
+}
+
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
{
- return 0;
+ int ret = 0;
+ switch (run->exit_reason) {
+ case KVM_EXIT_RISCV_SBI:
+ ret = kvm_riscv_handle_sbi(run);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
+ __func__, run->exit_reason);
+ ret = -1;
+ break;
+ }
+ return ret;
}
void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
new file mode 100644
index 0000000000..fb1a3fa8f2
--- /dev/null
+++ b/target/riscv/sbi_ecall_interface.h
@@ -0,0 +1,72 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __SBI_ECALL_INTERFACE_H__
+#define __SBI_ECALL_INTERFACE_H__
+
+/* clang-format off */
+
+/* SBI Extension IDs */
+#define SBI_EXT_0_1_SET_TIMER 0x0
+#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
+#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
+#define SBI_EXT_0_1_CLEAR_IPI 0x3
+#define SBI_EXT_0_1_SEND_IPI 0x4
+#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
+#define SBI_EXT_0_1_SHUTDOWN 0x8
+#define SBI_EXT_BASE 0x10
+#define SBI_EXT_TIME 0x54494D45
+#define SBI_EXT_IPI 0x735049
+#define SBI_EXT_RFENCE 0x52464E43
+#define SBI_EXT_HSM 0x48534D
+
+/* SBI function IDs for BASE extension*/
+#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
+#define SBI_EXT_BASE_GET_IMP_ID 0x1
+#define SBI_EXT_BASE_GET_IMP_VERSION 0x2
+#define SBI_EXT_BASE_PROBE_EXT 0x3
+#define SBI_EXT_BASE_GET_MVENDORID 0x4
+#define SBI_EXT_BASE_GET_MARCHID 0x5
+#define SBI_EXT_BASE_GET_MIMPID 0x6
+
+/* SBI function IDs for TIME extension*/
+#define SBI_EXT_TIME_SET_TIMER 0x0
+
+/* SBI function IDs for IPI extension*/
+#define SBI_EXT_IPI_SEND_IPI 0x0
+
+/* SBI function IDs for RFENCE extension*/
+#define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0
+#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1
+#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA 0x3
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x4
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x5
+#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6
+
+/* SBI function IDs for HSM extension */
+#define SBI_EXT_HSM_HART_START 0x0
+#define SBI_EXT_HSM_HART_STOP 0x1
+#define SBI_EXT_HSM_HART_GET_STATUS 0x2
+
+#define SBI_HSM_HART_STATUS_STARTED 0x0
+#define SBI_HSM_HART_STATUS_STOPPED 0x1
+#define SBI_HSM_HART_STATUS_START_PENDING 0x2
+#define SBI_HSM_HART_STATUS_STOP_PENDING 0x3
+
+#define SBI_SPEC_VERSION_MAJOR_OFFSET 24
+#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
+#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
+#define SBI_EXT_VENDOR_START 0x09000000
+#define SBI_EXT_VENDOR_END 0x09FFFFFF
+/* clang-format on */
+
+#endif
--
2.19.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH RFC v5 09/12] target/riscv: Add host cpu type
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
` (7 preceding siblings ...)
2021-04-12 6:52 ` [PATCH RFC v5 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
@ 2021-04-12 6:52 ` Yifei Jiang
2021-04-14 22:33 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
` (2 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Yifei Jiang @ 2021-04-12 6:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: kvm-riscv, kvm, libvir-list, anup.patel, palmer,
Alistair.Francis, sagark, kbastian, bin.meng, fanliang, wu.wubin,
zhang.zhanghailiang, yinyipeng1, Yifei Jiang
'host' type cpu is set isa to RVXLEN simply, more isa info
will obtain from KVM in kvm_arch_init_vcpu()
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/cpu.c | 9 +++++++++
target/riscv/cpu.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index dd34ab4978..8132d35a92 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -216,6 +216,12 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
}
#endif
+static void riscv_host_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_misa(env, RVXLEN);
+}
+
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
@@ -706,6 +712,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.class_init = riscv_cpu_class_init,
},
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
+#if defined(CONFIG_KVM)
+ DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
+#endif
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a489d94187..3ca3dad341 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -43,6 +43,7 @@
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
#if defined(TARGET_RISCV32)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
--
2.19.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH RFC v5 09/12] target/riscv: Add host cpu type
2021-04-12 6:52 ` [PATCH RFC v5 09/12] target/riscv: Add host cpu type Yifei Jiang
@ 2021-04-14 22:33 ` Alistair Francis
0 siblings, 0 replies; 21+ messages in thread
From: Alistair Francis @ 2021-04-14 22:33 UTC (permalink / raw)
To: Yifei Jiang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Sagar Karandikar, open list:Overall, libvir-list,
Bastian Koppelmann, Anup Patel, yinyipeng, Alistair Francis,
kvm-riscv, Palmer Dabbelt, fanliang, Wubin (H),
Zhanghailiang
On Mon, Apr 12, 2021 at 4:54 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> 'host' type cpu is set isa to RVXLEN simply, more isa info
> will obtain from KVM in kvm_arch_init_vcpu()
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 9 +++++++++
> target/riscv/cpu.h | 1 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index dd34ab4978..8132d35a92 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -216,6 +216,12 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
> }
> #endif
>
> +static void riscv_host_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + set_misa(env, RVXLEN);
> +}
> +
> static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
> {
> ObjectClass *oc;
> @@ -706,6 +712,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .class_init = riscv_cpu_class_init,
> },
> DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
> +#if defined(CONFIG_KVM)
> + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
> +#endif
> #if defined(TARGET_RISCV32)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index a489d94187..3ca3dad341 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -43,6 +43,7 @@
> #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
> #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
> +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
>
> #if defined(TARGET_RISCV32)
> # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
> --
> 2.19.1
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH RFC v5 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
` (8 preceding siblings ...)
2021-04-12 6:52 ` [PATCH RFC v5 09/12] target/riscv: Add host cpu type Yifei Jiang
@ 2021-04-12 6:52 ` Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang
11 siblings, 0 replies; 21+ messages in thread
From: Yifei Jiang @ 2021-04-12 6:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: kvm-riscv, kvm, libvir-list, anup.patel, palmer,
Alistair.Francis, sagark, kbastian, bin.meng, fanliang, wu.wubin,
zhang.zhanghailiang, yinyipeng1, Yifei Jiang
Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
from KVM.
To set register of RISCV_TIMER_REG(state) will occur a error from KVM
on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
that adaping in QEMU.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/cpu.h | 6 ++++
target/riscv/kvm.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 78 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3ca3dad341..b043881bb1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -247,6 +247,12 @@ struct CPURISCVState {
hwaddr kernel_addr;
hwaddr fdt_addr;
+
+ /* kvm timer */
+ bool kvm_timer_dirty;
+ uint64_t kvm_timer_time;
+ uint64_t kvm_timer_compare;
+ uint64_t kvm_timer_state;
};
OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass,
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index f9707157e7..ec693795ce 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -59,6 +59,9 @@ static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
KVM_REG_RISCV_CSR_REG(name))
+#define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \
+ KVM_REG_RISCV_TIMER_REG(name))
+
#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
@@ -306,6 +309,75 @@ static int kvm_riscv_put_regs_fp(CPUState *cs)
return ret;
}
+static void kvm_riscv_get_regs_timer(CPUState *cs)
+{
+ int ret;
+ uint64_t reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (env->kvm_timer_dirty) {
+ return;
+ }
+
+ ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, time), ®);
+ if (ret) {
+ abort();
+ }
+ env->kvm_timer_time = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, compare), ®);
+ if (ret) {
+ abort();
+ }
+ env->kvm_timer_compare = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, state), ®);
+ if (ret) {
+ abort();
+ }
+ env->kvm_timer_state = reg;
+
+ env->kvm_timer_dirty = true;
+}
+
+static void kvm_riscv_put_regs_timer(CPUState *cs)
+{
+ int ret;
+ uint64_t reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (!env->kvm_timer_dirty) {
+ return;
+ }
+
+ reg = env->kvm_timer_time;
+ ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), ®);
+ if (ret) {
+ abort();
+ }
+
+ reg = env->kvm_timer_compare;
+ ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, compare), ®);
+ if (ret) {
+ abort();
+ }
+
+ /*
+ * To set register of RISCV_TIMER_REG(state) will occur a error from KVM
+ * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it
+ * doesn't matter that adaping in QEMU now.
+ * TODO If KVM changes, adapt here.
+ */
+ if (env->kvm_timer_state) {
+ reg = env->kvm_timer_state;
+ ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, state), ®);
+ if (ret) {
+ abort();
+ }
+ }
+
+ env->kvm_timer_dirty = false;
+}
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
--
2.19.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH RFC v5 11/12] target/riscv: Implement virtual time adjusting with vm state changing
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
` (9 preceding siblings ...)
2021-04-12 6:52 ` [PATCH RFC v5 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
@ 2021-04-12 6:52 ` Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang
11 siblings, 0 replies; 21+ messages in thread
From: Yifei Jiang @ 2021-04-12 6:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: kvm-riscv, kvm, libvir-list, anup.patel, palmer,
Alistair.Francis, sagark, kbastian, bin.meng, fanliang, wu.wubin,
zhang.zhanghailiang, yinyipeng1, Yifei Jiang
We hope that virtual time adjusts with vm state changing. When a vm
is stopped, guest virtual time should stop counting and kvm_timer
should be stopped. When the vm is resumed, guest virtual time should
continue to count and kvm_timer should be restored.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/kvm.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index ec693795ce..50328c537e 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -40,6 +40,7 @@
#include "kvm_riscv.h"
#include "sbi_ecall_interface.h"
#include "chardev/char-fe.h"
+#include "sysemu/runstate.h"
static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
{
@@ -448,6 +449,17 @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu)
return cpu->cpu_index;
}
+static void kvm_riscv_vm_state_change(void *opaque, int running, RunState state)
+{
+ CPUState *cs = opaque;
+
+ if (running) {
+ kvm_riscv_put_regs_timer(cs);
+ } else {
+ kvm_riscv_get_regs_timer(cs);
+ }
+}
+
void kvm_arch_init_irq_routing(KVMState *s)
{
}
@@ -460,6 +472,8 @@ int kvm_arch_init_vcpu(CPUState *cs)
CPURISCVState *env = &cpu->env;
__u64 id;
+ qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs);
+
id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa));
ret = kvm_get_one_reg(cs, id, &isa);
if (ret) {
--
2.19.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
` (10 preceding siblings ...)
2021-04-12 6:52 ` [PATCH RFC v5 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
@ 2021-04-12 6:52 ` Yifei Jiang
11 siblings, 0 replies; 21+ messages in thread
From: Yifei Jiang @ 2021-04-12 6:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: kvm-riscv, kvm, libvir-list, anup.patel, palmer,
Alistair.Francis, sagark, kbastian, bin.meng, fanliang, wu.wubin,
zhang.zhanghailiang, yinyipeng1, Yifei Jiang
Add virtual time context description to vmstate_riscv_cpu. After cpu being
loaded, virtual time context is updated to KVM.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/machine.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 44d4015bd6..ef2d5395a8 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -138,10 +138,20 @@ static const VMStateDescription vmstate_hyper = {
}
};
+static int cpu_post_load(void *opaque, int version_id)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ env->kvm_timer_dirty = true;
+ return 0;
+}
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 1,
.minimum_version_id = 1,
+ .post_load = cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -185,6 +195,10 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINT64(env.mtohost, RISCVCPU),
VMSTATE_UINT64(env.timecmp, RISCVCPU),
+ VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
+ VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
+ VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription * []) {
--
2.19.1
^ permalink raw reply related [flat|nested] 21+ messages in thread