[PATCH 0/8] coresight: etm4x: Fixes and updates for sysfs API

[PATCH 0/8] coresight: etm4x: Fixes and updates for sysfs API

[Mike Leach]

Review of ETMV4 sysfs code resulted in a number of minor issues being
discovered.

Patch set fixes these issues:-
1) Update for ETM v4.4 archtecture.
2) Add missing single shot comparator API.
3) Misc fixes and improvements to sysfs API
4) Updated programmers documentation and reference.

Mike Leach (8):
  coresight: etm4x: Fixes for ETM v4.4 architecture updates.
  coresight: etm4x: Fix input validation for sysfs.
  coresight: etm4x: Add missing API to set EL match on address filters
  coresight: etm4x: Fix issues with start-stop logic.
  coresight: etm4x: Improve usability of sysfs API.
  coresight: etm4x: Add view comparator settings API to sysfs.
  coresight: etm4x: Add missing single-shot control API to sysfs
  coresight: etm4x: docs: Additional documentation for ETM4x.

 .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++---
 .../{ => coresight}/coresight-cpu-debug.txt   |   0
 .../coresight/coresight-etm4x-reference.txt   | 459 ++++++++++++++++++
 .../trace/{ => coresight}/coresight.txt       |   0
 MAINTAINERS                                   |   3 +-
 .../coresight/coresight-etm4x-sysfs.c         | 308 +++++++++++-
 drivers/hwtracing/coresight/coresight-etm4x.c |  32 +-
 drivers/hwtracing/coresight/coresight-etm4x.h |  18 +-
 8 files changed, 902 insertions(+), 101 deletions(-)
 rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%)
 create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt
 rename Documentation/trace/{ => coresight}/coresight.txt (100%)

-- 
2.17.1


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[PATCH 1/8] coresight: etm4x: Fixes for ETM v4.4 architecture updates.

[Mike Leach]

ETMv4.4 adds in support for tracing secure EL2 (per arch 8.x updates).
Patch accounts for this new capability.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
---
 .../hwtracing/coresight/coresight-etm4x-sysfs.c   | 12 ++++++------
 drivers/hwtracing/coresight/coresight-etm4x.c     |  5 ++++-
 drivers/hwtracing/coresight/coresight-etm4x.h     | 15 +++++++++++----
 3 files changed, 21 insertions(+), 11 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 219c10eb752c..b6984be0c515 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -738,7 +738,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev,
 	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 	struct etmv4_config *config = &drvdata->config;
 
-	val = BMVAL(config->vinst_ctrl, 16, 19);
+	val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16;
 	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 }
 
@@ -754,8 +754,8 @@ static ssize_t s_exlevel_vinst_store(struct device *dev,
 		return -EINVAL;
 
 	spin_lock(&drvdata->spinlock);
-	/* clear all EXLEVEL_S bits (bit[18] is never implemented) */
-	config->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19));
+	/* clear all EXLEVEL_S bits  */
+	config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK);
 	/* enable instruction tracing for corresponding exception level */
 	val &= drvdata->s_ex_level;
 	config->vinst_ctrl |= (val << 16);
@@ -773,7 +773,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev,
 	struct etmv4_config *config = &drvdata->config;
 
 	/* EXLEVEL_NS, bits[23:20] */
-	val = BMVAL(config->vinst_ctrl, 20, 23);
+	val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20;
 	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 }
 
@@ -789,8 +789,8 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev,
 		return -EINVAL;
 
 	spin_lock(&drvdata->spinlock);
-	/* clear EXLEVEL_NS bits (bit[23] is never implemented */
-	config->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22));
+	/* clear EXLEVEL_NS bits  */
+	config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK);
 	/* enable instruction tracing for corresponding exception level */
 	val &= drvdata->ns_ex_level;
 	config->vinst_ctrl |= (val << 20);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index a128b5063f46..52b8876de157 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -629,6 +629,7 @@ static void etm4_init_arch_data(void *info)
 	 * TRCARCHMAJ, bits[11:8] architecture major versin number
 	 */
 	drvdata->arch = BMVAL(etmidr1, 4, 11);
+	drvdata->config.arch = drvdata->arch;
 
 	/* maximum size of resources */
 	etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
@@ -780,6 +781,7 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config)
 static u64 etm4_get_access_type(struct etmv4_config *config)
 {
 	u64 access_type = etm4_get_ns_access_type(config);
+	u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
 
 	/*
 	 * EXLEVEL_S, bits[11:8], don't trace anything happening
@@ -787,7 +789,8 @@ static u64 etm4_get_access_type(struct etmv4_config *config)
 	 */
 	access_type |= (ETM_EXLEVEL_S_APP	|
 			ETM_EXLEVEL_S_OS	|
-			ETM_EXLEVEL_S_HYP);
+			s_hyp			|
+			ETM_EXLEVEL_S_MON);
 
 	return access_type;
 }
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 4523f10ddd0f..60bc2fb5159b 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -180,17 +180,22 @@
 /* PowerDown Control Register bits */
 #define TRCPDCR_PU			BIT(3)
 
-/* secure state access levels */
+/* secure state access levels - TRCACATRn */
 #define ETM_EXLEVEL_S_APP		BIT(8)
 #define ETM_EXLEVEL_S_OS		BIT(9)
-#define ETM_EXLEVEL_S_NA		BIT(10)
-#define ETM_EXLEVEL_S_HYP		BIT(11)
-/* non-secure state access levels */
+#define ETM_EXLEVEL_S_HYP		BIT(10)
+#define ETM_EXLEVEL_S_MON		BIT(11)
+/* non-secure state access levels - TRCACATRn */
 #define ETM_EXLEVEL_NS_APP		BIT(12)
 #define ETM_EXLEVEL_NS_OS		BIT(13)
 #define ETM_EXLEVEL_NS_HYP		BIT(14)
 #define ETM_EXLEVEL_NS_NA		BIT(15)
 
+/* secure / non secure masks - TRCVICTLR, IDR3 */
+#define ETM_EXLEVEL_S_VICTLR_MASK	GENMASK(19, 16)
+/* NS MON (EL3) mode never implemented */
+#define ETM_EXLEVEL_NS_VICTLR_MASK	GENMASK(22, 20)
+
 /**
  * struct etmv4_config - configuration information related to an ETMv4
  * @mode:	Controls various modes supported by this ETM.
@@ -237,6 +242,7 @@
  * @vmid_mask0:	VM ID comparator mask for comparator 0-3.
  * @vmid_mask1:	VM ID comparator mask for comparator 4-7.
  * @ext_inp:	External input selection.
+ * @arch:	ETM architecture version (for arch dependent config).
  */
 struct etmv4_config {
 	u32				mode;
@@ -279,6 +285,7 @@ struct etmv4_config {
 	u32				vmid_mask0;
 	u32				vmid_mask1;
 	u32				ext_inp;
+	u8				arch;
 };
 
 /**
-- 
2.17.1


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Re: [PATCH 1/8] coresight: etm4x: Fixes for ETM v4.4 architecture updates.

[Mathieu Poirier]

Hi Mike,


On Mon, Aug 19, 2019 at 09:57:13PM +0100, Mike Leach wrote:
> ETMv4.4 adds in support for tracing secure EL2 (per arch 8.x updates).

What is the name of the ETMv4.4 document?  I can only find up to 4.2 on line.

> Patch accounts for this new capability.
> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../hwtracing/coresight/coresight-etm4x-sysfs.c   | 12 ++++++------
>  drivers/hwtracing/coresight/coresight-etm4x.c     |  5 ++++-
>  drivers/hwtracing/coresight/coresight-etm4x.h     | 15 +++++++++++----
>  3 files changed, 21 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 219c10eb752c..b6984be0c515 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -738,7 +738,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev,
>  	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
>  	struct etmv4_config *config = &drvdata->config;
>  
> -	val = BMVAL(config->vinst_ctrl, 16, 19);
> +	val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16;
>  	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
>  }
>  
> @@ -754,8 +754,8 @@ static ssize_t s_exlevel_vinst_store(struct device *dev,
>  		return -EINVAL;
>  
>  	spin_lock(&drvdata->spinlock);
> -	/* clear all EXLEVEL_S bits (bit[18] is never implemented) */
> -	config->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19));
> +	/* clear all EXLEVEL_S bits  */
> +	config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK);
>  	/* enable instruction tracing for corresponding exception level */
>  	val &= drvdata->s_ex_level;
>  	config->vinst_ctrl |= (val << 16);
> @@ -773,7 +773,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev,
>  	struct etmv4_config *config = &drvdata->config;
>  
>  	/* EXLEVEL_NS, bits[23:20] */
> -	val = BMVAL(config->vinst_ctrl, 20, 23);
> +	val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20;
>  	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
>  }
>  
> @@ -789,8 +789,8 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev,
>  		return -EINVAL;
>  
>  	spin_lock(&drvdata->spinlock);
> -	/* clear EXLEVEL_NS bits (bit[23] is never implemented */
> -	config->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22));
> +	/* clear EXLEVEL_NS bits  */
> +	config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK);
>  	/* enable instruction tracing for corresponding exception level */
>  	val &= drvdata->ns_ex_level;
>  	config->vinst_ctrl |= (val << 20);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index a128b5063f46..52b8876de157 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -629,6 +629,7 @@ static void etm4_init_arch_data(void *info)
>  	 * TRCARCHMAJ, bits[11:8] architecture major versin number
>  	 */
>  	drvdata->arch = BMVAL(etmidr1, 4, 11);
> +	drvdata->config.arch = drvdata->arch;
>  
>  	/* maximum size of resources */
>  	etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
> @@ -780,6 +781,7 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config)
>  static u64 etm4_get_access_type(struct etmv4_config *config)
>  {
>  	u64 access_type = etm4_get_ns_access_type(config);
> +	u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
>  
>  	/*
>  	 * EXLEVEL_S, bits[11:8], don't trace anything happening
> @@ -787,7 +789,8 @@ static u64 etm4_get_access_type(struct etmv4_config *config)
>  	 */
>  	access_type |= (ETM_EXLEVEL_S_APP	|
>  			ETM_EXLEVEL_S_OS	|
> -			ETM_EXLEVEL_S_HYP);
> +			s_hyp			|
> +			ETM_EXLEVEL_S_MON);
>  
>  	return access_type;
>  }
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 4523f10ddd0f..60bc2fb5159b 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -180,17 +180,22 @@
>  /* PowerDown Control Register bits */
>  #define TRCPDCR_PU			BIT(3)
>  
> -/* secure state access levels */
> +/* secure state access levels - TRCACATRn */
>  #define ETM_EXLEVEL_S_APP		BIT(8)
>  #define ETM_EXLEVEL_S_OS		BIT(9)
> -#define ETM_EXLEVEL_S_NA		BIT(10)
> -#define ETM_EXLEVEL_S_HYP		BIT(11)
> -/* non-secure state access levels */
> +#define ETM_EXLEVEL_S_HYP		BIT(10)
> +#define ETM_EXLEVEL_S_MON		BIT(11)
> +/* non-secure state access levels - TRCACATRn */
>  #define ETM_EXLEVEL_NS_APP		BIT(12)
>  #define ETM_EXLEVEL_NS_OS		BIT(13)
>  #define ETM_EXLEVEL_NS_HYP		BIT(14)
>  #define ETM_EXLEVEL_NS_NA		BIT(15)
>  
> +/* secure / non secure masks - TRCVICTLR, IDR3 */
> +#define ETM_EXLEVEL_S_VICTLR_MASK	GENMASK(19, 16)
> +/* NS MON (EL3) mode never implemented */
> +#define ETM_EXLEVEL_NS_VICTLR_MASK	GENMASK(22, 20)

It is hard to say without documentation but shouldn't this be GENMASK(23, 20)?  

> +
>  /**
>   * struct etmv4_config - configuration information related to an ETMv4
>   * @mode:	Controls various modes supported by this ETM.
> @@ -237,6 +242,7 @@
>   * @vmid_mask0:	VM ID comparator mask for comparator 0-3.
>   * @vmid_mask1:	VM ID comparator mask for comparator 4-7.
>   * @ext_inp:	External input selection.
> + * @arch:	ETM architecture version (for arch dependent config).
>   */
>  struct etmv4_config {
>  	u32				mode;
> @@ -279,6 +285,7 @@ struct etmv4_config {
>  	u32				vmid_mask0;
>  	u32				vmid_mask1;
>  	u32				ext_inp;
> +	u8				arch;
>  };
>  
>  /**
> -- 
> 2.17.1
> 

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Re: [PATCH 1/8] coresight: etm4x: Fixes for ETM v4.4 architecture updates.

[Mike Leach]

Hi Mathieu,

On Mon, 26 Aug 2019 at 22:47, Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> Hi Mike,
>
>
> On Mon, Aug 19, 2019 at 09:57:13PM +0100, Mike Leach wrote:
> > ETMv4.4 adds in support for tracing secure EL2 (per arch 8.x updates).
>
> What is the name of the ETMv4.4 document?  I can only find up to 4.2 on line.
>

Arm® Embedded Trace Macrocell
Architecture Specification
ETMv4.0 to ETMv4.4

ARM IHI0064F

Published 2018 - non-confidential.

So should be available.

> > Patch accounts for this new capability.
> >
> > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > ---
> >  .../hwtracing/coresight/coresight-etm4x-sysfs.c   | 12 ++++++------
> >  drivers/hwtracing/coresight/coresight-etm4x.c     |  5 ++++-
> >  drivers/hwtracing/coresight/coresight-etm4x.h     | 15 +++++++++++----
> >  3 files changed, 21 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index 219c10eb752c..b6984be0c515 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -738,7 +738,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev,
> >       struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> >       struct etmv4_config *config = &drvdata->config;
> >
> > -     val = BMVAL(config->vinst_ctrl, 16, 19);
> > +     val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16;
> >       return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> >  }
> >
> > @@ -754,8 +754,8 @@ static ssize_t s_exlevel_vinst_store(struct device *dev,
> >               return -EINVAL;
> >
> >       spin_lock(&drvdata->spinlock);
> > -     /* clear all EXLEVEL_S bits (bit[18] is never implemented) */
> > -     config->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19));
> > +     /* clear all EXLEVEL_S bits  */
> > +     config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK);
> >       /* enable instruction tracing for corresponding exception level */
> >       val &= drvdata->s_ex_level;
> >       config->vinst_ctrl |= (val << 16);
> > @@ -773,7 +773,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev,
> >       struct etmv4_config *config = &drvdata->config;
> >
> >       /* EXLEVEL_NS, bits[23:20] */
> > -     val = BMVAL(config->vinst_ctrl, 20, 23);
> > +     val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20;
> >       return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> >  }
> >
> > @@ -789,8 +789,8 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev,
> >               return -EINVAL;
> >
> >       spin_lock(&drvdata->spinlock);
> > -     /* clear EXLEVEL_NS bits (bit[23] is never implemented */
> > -     config->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22));
> > +     /* clear EXLEVEL_NS bits  */
> > +     config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK);
> >       /* enable instruction tracing for corresponding exception level */
> >       val &= drvdata->ns_ex_level;
> >       config->vinst_ctrl |= (val << 20);
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> > index a128b5063f46..52b8876de157 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> > @@ -629,6 +629,7 @@ static void etm4_init_arch_data(void *info)
> >        * TRCARCHMAJ, bits[11:8] architecture major versin number
> >        */
> >       drvdata->arch = BMVAL(etmidr1, 4, 11);
> > +     drvdata->config.arch = drvdata->arch;
> >
> >       /* maximum size of resources */
> >       etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
> > @@ -780,6 +781,7 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config)
> >  static u64 etm4_get_access_type(struct etmv4_config *config)
> >  {
> >       u64 access_type = etm4_get_ns_access_type(config);
> > +     u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
> >
> >       /*
> >        * EXLEVEL_S, bits[11:8], don't trace anything happening
> > @@ -787,7 +789,8 @@ static u64 etm4_get_access_type(struct etmv4_config *config)
> >        */
> >       access_type |= (ETM_EXLEVEL_S_APP       |
> >                       ETM_EXLEVEL_S_OS        |
> > -                     ETM_EXLEVEL_S_HYP);
> > +                     s_hyp                   |
> > +                     ETM_EXLEVEL_S_MON);
> >
> >       return access_type;
> >  }
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > index 4523f10ddd0f..60bc2fb5159b 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > @@ -180,17 +180,22 @@
> >  /* PowerDown Control Register bits */
> >  #define TRCPDCR_PU                   BIT(3)
> >
> > -/* secure state access levels */
> > +/* secure state access levels - TRCACATRn */
> >  #define ETM_EXLEVEL_S_APP            BIT(8)
> >  #define ETM_EXLEVEL_S_OS             BIT(9)
> > -#define ETM_EXLEVEL_S_NA             BIT(10)
> > -#define ETM_EXLEVEL_S_HYP            BIT(11)
> > -/* non-secure state access levels */
> > +#define ETM_EXLEVEL_S_HYP            BIT(10)
> > +#define ETM_EXLEVEL_S_MON            BIT(11)
> > +/* non-secure state access levels - TRCACATRn */
> >  #define ETM_EXLEVEL_NS_APP           BIT(12)
> >  #define ETM_EXLEVEL_NS_OS            BIT(13)
> >  #define ETM_EXLEVEL_NS_HYP           BIT(14)
> >  #define ETM_EXLEVEL_NS_NA            BIT(15)
> >
> > +/* secure / non secure masks - TRCVICTLR, IDR3 */
> > +#define ETM_EXLEVEL_S_VICTLR_MASK    GENMASK(19, 16)
> > +/* NS MON (EL3) mode never implemented */
> > +#define ETM_EXLEVEL_NS_VICTLR_MASK   GENMASK(22, 20)
>
> It is hard to say without documentation but shouldn't this be GENMASK(23, 20)?
>
Per the comment above, EL3_NS is prohibited so the mask refers to only
the 3 allow bits (NS EL0 - EL2).

> > +
> >  /**
> >   * struct etmv4_config - configuration information related to an ETMv4
> >   * @mode:    Controls various modes supported by this ETM.
> > @@ -237,6 +242,7 @@
> >   * @vmid_mask0:      VM ID comparator mask for comparator 0-3.
> >   * @vmid_mask1:      VM ID comparator mask for comparator 4-7.
> >   * @ext_inp: External input selection.
> > + * @arch:    ETM architecture version (for arch dependent config).
> >   */
> >  struct etmv4_config {
> >       u32                             mode;
> > @@ -279,6 +285,7 @@ struct etmv4_config {
> >       u32                             vmid_mask0;
> >       u32                             vmid_mask1;
> >       u32                             ext_inp;
> > +     u8                              arch;
> >  };
> >
> >  /**
> > --
> > 2.17.1
> >



-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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Re: [PATCH 1/8] coresight: etm4x: Fixes for ETM v4.4 architecture updates.

[Mathieu Poirier]

On Tue, 27 Aug 2019 at 04:13, Mike Leach <mike.leach@linaro.org> wrote:
>
> Hi Mathieu,
>
> On Mon, 26 Aug 2019 at 22:47, Mathieu Poirier
> <mathieu.poirier@linaro.org> wrote:
> >
> > Hi Mike,
> >
> >
> > On Mon, Aug 19, 2019 at 09:57:13PM +0100, Mike Leach wrote:
> > > ETMv4.4 adds in support for tracing secure EL2 (per arch 8.x updates).
> >
> > What is the name of the ETMv4.4 document?  I can only find up to 4.2 on line.
> >
>
> Arm® Embedded Trace Macrocell
> Architecture Specification
> ETMv4.0 to ETMv4.4
>
> ARM IHI0064F
>
> Published 2018 - non-confidential.
>
> So should be available.

With the name above I quickly found the document on line:
https://static.docs.arm.com/ihi0064/f/etm_v4_4_architecture_specification_IHI0064F.pdf

On the flip side the inforcenter site still has the old 4.0 to 4.2 version.

>
> > > Patch accounts for this new capability.
> > >
> > > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > > ---
> > >  .../hwtracing/coresight/coresight-etm4x-sysfs.c   | 12 ++++++------
> > >  drivers/hwtracing/coresight/coresight-etm4x.c     |  5 ++++-
> > >  drivers/hwtracing/coresight/coresight-etm4x.h     | 15 +++++++++++----
> > >  3 files changed, 21 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > index 219c10eb752c..b6984be0c515 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > @@ -738,7 +738,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev,
> > >       struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > >       struct etmv4_config *config = &drvdata->config;
> > >
> > > -     val = BMVAL(config->vinst_ctrl, 16, 19);
> > > +     val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16;
> > >       return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > >  }
> > >
> > > @@ -754,8 +754,8 @@ static ssize_t s_exlevel_vinst_store(struct device *dev,
> > >               return -EINVAL;
> > >
> > >       spin_lock(&drvdata->spinlock);
> > > -     /* clear all EXLEVEL_S bits (bit[18] is never implemented) */
> > > -     config->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19));
> > > +     /* clear all EXLEVEL_S bits  */
> > > +     config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK);
> > >       /* enable instruction tracing for corresponding exception level */
> > >       val &= drvdata->s_ex_level;
> > >       config->vinst_ctrl |= (val << 16);
> > > @@ -773,7 +773,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev,
> > >       struct etmv4_config *config = &drvdata->config;
> > >
> > >       /* EXLEVEL_NS, bits[23:20] */
> > > -     val = BMVAL(config->vinst_ctrl, 20, 23);
> > > +     val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20;
> > >       return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > >  }
> > >
> > > @@ -789,8 +789,8 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev,
> > >               return -EINVAL;
> > >
> > >       spin_lock(&drvdata->spinlock);
> > > -     /* clear EXLEVEL_NS bits (bit[23] is never implemented */
> > > -     config->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22));
> > > +     /* clear EXLEVEL_NS bits  */
> > > +     config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK);
> > >       /* enable instruction tracing for corresponding exception level */
> > >       val &= drvdata->ns_ex_level;
> > >       config->vinst_ctrl |= (val << 20);
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> > > index a128b5063f46..52b8876de157 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> > > @@ -629,6 +629,7 @@ static void etm4_init_arch_data(void *info)
> > >        * TRCARCHMAJ, bits[11:8] architecture major versin number
> > >        */
> > >       drvdata->arch = BMVAL(etmidr1, 4, 11);
> > > +     drvdata->config.arch = drvdata->arch;
> > >
> > >       /* maximum size of resources */
> > >       etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
> > > @@ -780,6 +781,7 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config)
> > >  static u64 etm4_get_access_type(struct etmv4_config *config)
> > >  {
> > >       u64 access_type = etm4_get_ns_access_type(config);
> > > +     u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
> > >
> > >       /*
> > >        * EXLEVEL_S, bits[11:8], don't trace anything happening
> > > @@ -787,7 +789,8 @@ static u64 etm4_get_access_type(struct etmv4_config *config)
> > >        */
> > >       access_type |= (ETM_EXLEVEL_S_APP       |
> > >                       ETM_EXLEVEL_S_OS        |
> > > -                     ETM_EXLEVEL_S_HYP);
> > > +                     s_hyp                   |
> > > +                     ETM_EXLEVEL_S_MON);
> > >
> > >       return access_type;
> > >  }
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > > index 4523f10ddd0f..60bc2fb5159b 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > > @@ -180,17 +180,22 @@
> > >  /* PowerDown Control Register bits */
> > >  #define TRCPDCR_PU                   BIT(3)
> > >
> > > -/* secure state access levels */
> > > +/* secure state access levels - TRCACATRn */
> > >  #define ETM_EXLEVEL_S_APP            BIT(8)
> > >  #define ETM_EXLEVEL_S_OS             BIT(9)
> > > -#define ETM_EXLEVEL_S_NA             BIT(10)
> > > -#define ETM_EXLEVEL_S_HYP            BIT(11)
> > > -/* non-secure state access levels */
> > > +#define ETM_EXLEVEL_S_HYP            BIT(10)
> > > +#define ETM_EXLEVEL_S_MON            BIT(11)
> > > +/* non-secure state access levels - TRCACATRn */
> > >  #define ETM_EXLEVEL_NS_APP           BIT(12)
> > >  #define ETM_EXLEVEL_NS_OS            BIT(13)
> > >  #define ETM_EXLEVEL_NS_HYP           BIT(14)
> > >  #define ETM_EXLEVEL_NS_NA            BIT(15)
> > >
> > > +/* secure / non secure masks - TRCVICTLR, IDR3 */
> > > +#define ETM_EXLEVEL_S_VICTLR_MASK    GENMASK(19, 16)
> > > +/* NS MON (EL3) mode never implemented */
> > > +#define ETM_EXLEVEL_NS_VICTLR_MASK   GENMASK(22, 20)
> >
> > It is hard to say without documentation but shouldn't this be GENMASK(23, 20)?
> >
> Per the comment above, EL3_NS is prohibited so the mask refers to only
> the 3 allow bits (NS EL0 - EL2).
>

Yes, the 4.4 documentation makes it obvious.

> > > +
> > >  /**
> > >   * struct etmv4_config - configuration information related to an ETMv4
> > >   * @mode:    Controls various modes supported by this ETM.
> > > @@ -237,6 +242,7 @@
> > >   * @vmid_mask0:      VM ID comparator mask for comparator 0-3.
> > >   * @vmid_mask1:      VM ID comparator mask for comparator 4-7.
> > >   * @ext_inp: External input selection.
> > > + * @arch:    ETM architecture version (for arch dependent config).
> > >   */
> > >  struct etmv4_config {
> > >       u32                             mode;
> > > @@ -279,6 +285,7 @@ struct etmv4_config {
> > >       u32                             vmid_mask0;
> > >       u32                             vmid_mask1;
> > >       u32                             ext_inp;
> > > +     u8                              arch;
> > >  };
> > >
> > >  /**
> > > --
> > > 2.17.1
> > >
>
>
>
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK

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Re: [PATCH 1/8] coresight: etm4x: Fixes for ETM v4.4 architecture updates.

[Leo Yan]

Hi Mike,

On Mon, Aug 19, 2019 at 09:57:13PM +0100, Mike Leach wrote:
> ETMv4.4 adds in support for tracing secure EL2 (per arch 8.x updates).
> Patch accounts for this new capability.
> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>

I reviewed this patch with connecting ETMv4.4 specification (which you
shared pointer in another email), I don't find any issue for registers
operations:

Reviewed-by: Leo Yan <leo.yan@linaro.org>

> ---
>  .../hwtracing/coresight/coresight-etm4x-sysfs.c   | 12 ++++++------
>  drivers/hwtracing/coresight/coresight-etm4x.c     |  5 ++++-
>  drivers/hwtracing/coresight/coresight-etm4x.h     | 15 +++++++++++----
>  3 files changed, 21 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 219c10eb752c..b6984be0c515 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -738,7 +738,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev,
>  	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
>  	struct etmv4_config *config = &drvdata->config;
>  
> -	val = BMVAL(config->vinst_ctrl, 16, 19);
> +	val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16;
>  	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
>  }
>  
> @@ -754,8 +754,8 @@ static ssize_t s_exlevel_vinst_store(struct device *dev,
>  		return -EINVAL;
>  
>  	spin_lock(&drvdata->spinlock);
> -	/* clear all EXLEVEL_S bits (bit[18] is never implemented) */
> -	config->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19));
> +	/* clear all EXLEVEL_S bits  */
> +	config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK);
>  	/* enable instruction tracing for corresponding exception level */
>  	val &= drvdata->s_ex_level;
>  	config->vinst_ctrl |= (val << 16);
> @@ -773,7 +773,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev,
>  	struct etmv4_config *config = &drvdata->config;
>  
>  	/* EXLEVEL_NS, bits[23:20] */
> -	val = BMVAL(config->vinst_ctrl, 20, 23);
> +	val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20;
>  	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
>  }
>  
> @@ -789,8 +789,8 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev,
>  		return -EINVAL;
>  
>  	spin_lock(&drvdata->spinlock);
> -	/* clear EXLEVEL_NS bits (bit[23] is never implemented */
> -	config->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22));
> +	/* clear EXLEVEL_NS bits  */
> +	config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK);
>  	/* enable instruction tracing for corresponding exception level */
>  	val &= drvdata->ns_ex_level;
>  	config->vinst_ctrl |= (val << 20);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index a128b5063f46..52b8876de157 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -629,6 +629,7 @@ static void etm4_init_arch_data(void *info)
>  	 * TRCARCHMAJ, bits[11:8] architecture major versin number
>  	 */
>  	drvdata->arch = BMVAL(etmidr1, 4, 11);
> +	drvdata->config.arch = drvdata->arch;
>  
>  	/* maximum size of resources */
>  	etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
> @@ -780,6 +781,7 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config)
>  static u64 etm4_get_access_type(struct etmv4_config *config)
>  {
>  	u64 access_type = etm4_get_ns_access_type(config);
> +	u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
>  
>  	/*
>  	 * EXLEVEL_S, bits[11:8], don't trace anything happening
> @@ -787,7 +789,8 @@ static u64 etm4_get_access_type(struct etmv4_config *config)
>  	 */
>  	access_type |= (ETM_EXLEVEL_S_APP	|
>  			ETM_EXLEVEL_S_OS	|
> -			ETM_EXLEVEL_S_HYP);
> +			s_hyp			|
> +			ETM_EXLEVEL_S_MON);
>  
>  	return access_type;
>  }
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 4523f10ddd0f..60bc2fb5159b 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -180,17 +180,22 @@
>  /* PowerDown Control Register bits */
>  #define TRCPDCR_PU			BIT(3)
>  
> -/* secure state access levels */
> +/* secure state access levels - TRCACATRn */
>  #define ETM_EXLEVEL_S_APP		BIT(8)
>  #define ETM_EXLEVEL_S_OS		BIT(9)
> -#define ETM_EXLEVEL_S_NA		BIT(10)
> -#define ETM_EXLEVEL_S_HYP		BIT(11)
> -/* non-secure state access levels */
> +#define ETM_EXLEVEL_S_HYP		BIT(10)
> +#define ETM_EXLEVEL_S_MON		BIT(11)
> +/* non-secure state access levels - TRCACATRn */
>  #define ETM_EXLEVEL_NS_APP		BIT(12)
>  #define ETM_EXLEVEL_NS_OS		BIT(13)
>  #define ETM_EXLEVEL_NS_HYP		BIT(14)
>  #define ETM_EXLEVEL_NS_NA		BIT(15)
>  
> +/* secure / non secure masks - TRCVICTLR, IDR3 */
> +#define ETM_EXLEVEL_S_VICTLR_MASK	GENMASK(19, 16)
> +/* NS MON (EL3) mode never implemented */
> +#define ETM_EXLEVEL_NS_VICTLR_MASK	GENMASK(22, 20)
> +
>  /**
>   * struct etmv4_config - configuration information related to an ETMv4
>   * @mode:	Controls various modes supported by this ETM.
> @@ -237,6 +242,7 @@
>   * @vmid_mask0:	VM ID comparator mask for comparator 0-3.
>   * @vmid_mask1:	VM ID comparator mask for comparator 4-7.
>   * @ext_inp:	External input selection.
> + * @arch:	ETM architecture version (for arch dependent config).
>   */
>  struct etmv4_config {
>  	u32				mode;
> @@ -279,6 +285,7 @@ struct etmv4_config {
>  	u32				vmid_mask0;
>  	u32				vmid_mask1;
>  	u32				ext_inp;
> +	u8				arch;
>  };
>  
>  /**
> -- 
> 2.17.1
> 
> _______________________________________________
> CoreSight mailing list
> CoreSight@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/coresight

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[PATCH 2/8] coresight: etm4x: Fix input validation for sysfs.

[Mike Leach]

A number of issues are fixed relating to sysfs input validation:-

1) bb_ctrl_store() - incorrect compare of bit select field to absolute
value. Reworked per ETMv4 specification.
2) seq_event_store() - incorrect mask value - register has two
event values.
3) cyc_threshold_store() - must mask with max before checking min
otherwise wrapped values can set illegal value below min.
4) res_ctrl_store() - update to mask off all res0 bits.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
---
 .../coresight/coresight-etm4x-sysfs.c         | 21 ++++++++++++-------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index b6984be0c515..fa1d6a938f6c 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -652,10 +652,13 @@ static ssize_t cyc_threshold_store(struct device *dev,
 
 	if (kstrtoul(buf, 16, &val))
 		return -EINVAL;
+
+	/* mask off max threshold before checking min value */
+	val &= ETM_CYC_THRESHOLD_MASK;
 	if (val < drvdata->ccitmin)
 		return -EINVAL;
 
-	config->ccctlr = val & ETM_CYC_THRESHOLD_MASK;
+	config->ccctlr = val;
 	return size;
 }
 static DEVICE_ATTR_RW(cyc_threshold);
@@ -686,14 +689,16 @@ static ssize_t bb_ctrl_store(struct device *dev,
 		return -EINVAL;
 	if (!drvdata->nr_addr_cmp)
 		return -EINVAL;
+
 	/*
-	 * Bit[7:0] selects which address range comparator is used for
-	 * branch broadcast control.
+	 * Bit[8] controls include(1) / exclude(0), bits[0-7] select
+	 * individual range comparators. If include then at least 1
+	 * range must be  selected.
 	 */
-	if (BMVAL(val, 0, 7) > drvdata->nr_addr_cmp)
+	if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0))
 		return -EINVAL;
 
-	config->bb_ctrl = val;
+	config->bb_ctrl = val & GENMASK(8, 0);
 	return size;
 }
 static DEVICE_ATTR_RW(bb_ctrl);
@@ -1324,8 +1329,8 @@ static ssize_t seq_event_store(struct device *dev,
 
 	spin_lock(&drvdata->spinlock);
 	idx = config->seq_idx;
-	/* RST, bits[7:0] */
-	config->seq_ctrl[idx] = val & 0xFF;
+	/* Seq control has two masks B[15:5] F[7:0] */
+	config->seq_ctrl[idx] = val & 0xFFFF;
 	spin_unlock(&drvdata->spinlock);
 	return size;
 }
@@ -1580,7 +1585,7 @@ static ssize_t res_ctrl_store(struct device *dev,
 	if (idx % 2 != 0)
 		/* PAIRINV, bit[21] */
 		val &= ~BIT(21);
-	config->res_ctrl[idx] = val;
+	config->res_ctrl[idx] = val & GENMASK(21, 0);
 	spin_unlock(&drvdata->spinlock);
 	return size;
 }
-- 
2.17.1


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Re: [PATCH 2/8] coresight: etm4x: Fix input validation for sysfs.

[Mathieu Poirier]

On Mon, Aug 19, 2019 at 09:57:14PM +0100, Mike Leach wrote:
> A number of issues are fixed relating to sysfs input validation:-
> 
> 1) bb_ctrl_store() - incorrect compare of bit select field to absolute
> value. Reworked per ETMv4 specification.
> 2) seq_event_store() - incorrect mask value - register has two
> event values.
> 3) cyc_threshold_store() - must mask with max before checking min
> otherwise wrapped values can set illegal value below min.
> 4) res_ctrl_store() - update to mask off all res0 bits.
> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../coresight/coresight-etm4x-sysfs.c         | 21 ++++++++++++-------
>  1 file changed, 13 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index b6984be0c515..fa1d6a938f6c 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -652,10 +652,13 @@ static ssize_t cyc_threshold_store(struct device *dev,
>  
>  	if (kstrtoul(buf, 16, &val))
>  		return -EINVAL;
> +
> +	/* mask off max threshold before checking min value */
> +	val &= ETM_CYC_THRESHOLD_MASK;
>  	if (val < drvdata->ccitmin)
>  		return -EINVAL;
>  
> -	config->ccctlr = val & ETM_CYC_THRESHOLD_MASK;
> +	config->ccctlr = val;
>  	return size;
>  }
>  static DEVICE_ATTR_RW(cyc_threshold);
> @@ -686,14 +689,16 @@ static ssize_t bb_ctrl_store(struct device *dev,
>  		return -EINVAL;
>  	if (!drvdata->nr_addr_cmp)
>  		return -EINVAL;
> +
>  	/*
> -	 * Bit[7:0] selects which address range comparator is used for
> -	 * branch broadcast control.
> +	 * Bit[8] controls include(1) / exclude(0), bits[0-7] select
> +	 * individual range comparators. If include then at least 1
> +	 * range must be  selected.

s/"must be  selected"/"must be selected"

>  	 */
> -	if (BMVAL(val, 0, 7) > drvdata->nr_addr_cmp)
> +	if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0))
>  		return -EINVAL;
>  
> -	config->bb_ctrl = val;
> +	config->bb_ctrl = val & GENMASK(8, 0);
>  	return size;
>  }
>  static DEVICE_ATTR_RW(bb_ctrl);
> @@ -1324,8 +1329,8 @@ static ssize_t seq_event_store(struct device *dev,
>  
>  	spin_lock(&drvdata->spinlock);
>  	idx = config->seq_idx;
> -	/* RST, bits[7:0] */
> -	config->seq_ctrl[idx] = val & 0xFF;
> +	/* Seq control has two masks B[15:5] F[7:0] */
> +	config->seq_ctrl[idx] = val & 0xFFFF;
>  	spin_unlock(&drvdata->spinlock);
>  	return size;
>  }
> @@ -1580,7 +1585,7 @@ static ssize_t res_ctrl_store(struct device *dev,
>  	if (idx % 2 != 0)
>  		/* PAIRINV, bit[21] */
>  		val &= ~BIT(21);
> -	config->res_ctrl[idx] = val;
> +	config->res_ctrl[idx] = val & GENMASK(21, 0);
>  	spin_unlock(&drvdata->spinlock);
>  	return size;
>  }

With the above:

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

> -- 
> 2.17.1
> 

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Re: [PATCH 2/8] coresight: etm4x: Fix input validation for sysfs.

[Leo Yan]

On Mon, Aug 19, 2019 at 09:57:14PM +0100, Mike Leach wrote:
> A number of issues are fixed relating to sysfs input validation:-
> 
> 1) bb_ctrl_store() - incorrect compare of bit select field to absolute
> value. Reworked per ETMv4 specification.
> 2) seq_event_store() - incorrect mask value - register has two
> event values.
> 3) cyc_threshold_store() - must mask with max before checking min
> otherwise wrapped values can set illegal value below min.
> 4) res_ctrl_store() - update to mask off all res0 bits.
> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../coresight/coresight-etm4x-sysfs.c         | 21 ++++++++++++-------
>  1 file changed, 13 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index b6984be0c515..fa1d6a938f6c 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -652,10 +652,13 @@ static ssize_t cyc_threshold_store(struct device *dev,
>  
>  	if (kstrtoul(buf, 16, &val))
>  		return -EINVAL;
> +
> +	/* mask off max threshold before checking min value */
> +	val &= ETM_CYC_THRESHOLD_MASK;
>  	if (val < drvdata->ccitmin)
>  		return -EINVAL;
>  
> -	config->ccctlr = val & ETM_CYC_THRESHOLD_MASK;
> +	config->ccctlr = val;
>  	return size;
>  }
>  static DEVICE_ATTR_RW(cyc_threshold);
> @@ -686,14 +689,16 @@ static ssize_t bb_ctrl_store(struct device *dev,
>  		return -EINVAL;
>  	if (!drvdata->nr_addr_cmp)
>  		return -EINVAL;
> +
>  	/*
> -	 * Bit[7:0] selects which address range comparator is used for
> -	 * branch broadcast control.
> +	 * Bit[8] controls include(1) / exclude(0), bits[0-7] select
> +	 * individual range comparators. If include then at least 1
> +	 * range must be  selected.
>  	 */
> -	if (BMVAL(val, 0, 7) > drvdata->nr_addr_cmp)
> +	if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0))
>  		return -EINVAL;
>  
> -	config->bb_ctrl = val;
> +	config->bb_ctrl = val & GENMASK(8, 0);
>  	return size;
>  }
>  static DEVICE_ATTR_RW(bb_ctrl);
> @@ -1324,8 +1329,8 @@ static ssize_t seq_event_store(struct device *dev,
>  
>  	spin_lock(&drvdata->spinlock);
>  	idx = config->seq_idx;
> -	/* RST, bits[7:0] */
> -	config->seq_ctrl[idx] = val & 0xFF;
> +	/* Seq control has two masks B[15:5] F[7:0] */

s/B[15:5]/B[15:8]

With this change and Mathieu mentioned redundant space:

Reviewed-by: Leo Yan <leo.yan@linaro.org>

> +	config->seq_ctrl[idx] = val & 0xFFFF;
>  	spin_unlock(&drvdata->spinlock);
>  	return size;
>  }
> @@ -1580,7 +1585,7 @@ static ssize_t res_ctrl_store(struct device *dev,
>  	if (idx % 2 != 0)
>  		/* PAIRINV, bit[21] */
>  		val &= ~BIT(21);
> -	config->res_ctrl[idx] = val;
> +	config->res_ctrl[idx] = val & GENMASK(21, 0);
>  	spin_unlock(&drvdata->spinlock);
>  	return size;
>  }
> -- 
> 2.17.1
> 
> _______________________________________________
> CoreSight mailing list
> CoreSight@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/coresight

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[PATCH 3/8] coresight: etm4x: Add missing API to set EL match on address filters

[Mike Leach]

TRCACATRn registers have match bits for secure and non-secure exception
levels which are not accessible by the sysfs API.
This adds a new sysfs parameter to enable this - addr_exlevel_s_ns.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
---
 .../coresight/coresight-etm4x-sysfs.c         | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index fa1d6a938f6c..7eab5d7d0b62 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -1233,6 +1233,44 @@ static ssize_t addr_context_store(struct device *dev,
 }
 static DEVICE_ATTR_RW(addr_context);
 
+static ssize_t addr_exlevel_s_ns_show(struct device *dev,
+				      struct device_attribute *attr,
+				      char *buf)
+{
+	u8 idx;
+	unsigned long val;
+	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	struct etmv4_config *config = &drvdata->config;
+
+	spin_lock(&drvdata->spinlock);
+	idx = config->addr_idx;
+	val = BMVAL(config->addr_acc[idx], 14, 8);
+	spin_unlock(&drvdata->spinlock);
+	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
+}
+
+static ssize_t addr_exlevel_s_ns_store(struct device *dev,
+				       struct device_attribute *attr,
+				       const char *buf, size_t size)
+{
+	u8 idx;
+	unsigned long val;
+	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	struct etmv4_config *config = &drvdata->config;
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	spin_lock(&drvdata->spinlock);
+	idx = config->addr_idx;
+	/* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */
+	config->addr_acc[idx] &= ~(GENMASK(14, 8));
+	config->addr_acc[idx] |= (val << 8);
+	spin_unlock(&drvdata->spinlock);
+	return size;
+}
+static DEVICE_ATTR_RW(addr_exlevel_s_ns);
+
 static ssize_t seq_idx_show(struct device *dev,
 			    struct device_attribute *attr,
 			    char *buf)
@@ -2038,6 +2076,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
 	&dev_attr_addr_stop.attr,
 	&dev_attr_addr_ctxtype.attr,
 	&dev_attr_addr_context.attr,
+	&dev_attr_addr_exlevel_s_ns.attr,
 	&dev_attr_seq_idx.attr,
 	&dev_attr_seq_state.attr,
 	&dev_attr_seq_event.attr,
-- 
2.17.1


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Re: [PATCH 3/8] coresight: etm4x: Add missing API to set EL match on address filters

[Mathieu Poirier]

On Mon, Aug 19, 2019 at 09:57:15PM +0100, Mike Leach wrote:
> TRCACATRn registers have match bits for secure and non-secure exception
> levels which are not accessible by the sysfs API.
> This adds a new sysfs parameter to enable this - addr_exlevel_s_ns.
> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../coresight/coresight-etm4x-sysfs.c         | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index fa1d6a938f6c..7eab5d7d0b62 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -1233,6 +1233,44 @@ static ssize_t addr_context_store(struct device *dev,
>  }
>  static DEVICE_ATTR_RW(addr_context);
>  
> +static ssize_t addr_exlevel_s_ns_show(struct device *dev,
> +				      struct device_attribute *attr,
> +				      char *buf)
> +{
> +	u8 idx;
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	spin_lock(&drvdata->spinlock);
> +	idx = config->addr_idx;
> +	val = BMVAL(config->addr_acc[idx], 14, 8);
> +	spin_unlock(&drvdata->spinlock);
> +	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +
> +static ssize_t addr_exlevel_s_ns_store(struct device *dev,
> +				       struct device_attribute *attr,
> +				       const char *buf, size_t size)
> +{
> +	u8 idx;
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	if (kstrtoul(buf, 16, &val))
> +		return -EINVAL;
> +
> +	spin_lock(&drvdata->spinlock);
> +	idx = config->addr_idx;
> +	/* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */
> +	config->addr_acc[idx] &= ~(GENMASK(14, 8));
> +	config->addr_acc[idx] |= (val << 8);
> +	spin_unlock(&drvdata->spinlock);
> +	return size;
> +}
> +static DEVICE_ATTR_RW(addr_exlevel_s_ns);
> +
>  static ssize_t seq_idx_show(struct device *dev,
>  			    struct device_attribute *attr,
>  			    char *buf)
> @@ -2038,6 +2076,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
>  	&dev_attr_addr_stop.attr,
>  	&dev_attr_addr_ctxtype.attr,
>  	&dev_attr_addr_context.attr,
> +	&dev_attr_addr_exlevel_s_ns.attr,
>  	&dev_attr_seq_idx.attr,
>  	&dev_attr_seq_state.attr,
>  	&dev_attr_seq_event.attr,

I'm ok with this patch but the new entry needs to be documented in [1].  But
before moving forward with that I'm wondering if this is the way to go.  Would
it be better to consolidate type, ctxtype, context and exlevel_s_ns in a single
entry, say addr_acc_type?  We'd shed a fair amount of code and make it more
simple for users to configure.


[1]. Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x

> -- 
> 2.17.1
> 

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Re: [PATCH 3/8] coresight: etm4x: Add missing API to set EL match on address filters

[Mike Leach]

Hi Mathieu,

On Mon, 26 Aug 2019 at 23:59, Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> On Mon, Aug 19, 2019 at 09:57:15PM +0100, Mike Leach wrote:
> > TRCACATRn registers have match bits for secure and non-secure exception
> > levels which are not accessible by the sysfs API.
> > This adds a new sysfs parameter to enable this - addr_exlevel_s_ns.
> >
> > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > ---
> >  .../coresight/coresight-etm4x-sysfs.c         | 39 +++++++++++++++++++
> >  1 file changed, 39 insertions(+)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index fa1d6a938f6c..7eab5d7d0b62 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -1233,6 +1233,44 @@ static ssize_t addr_context_store(struct device *dev,
> >  }
> >  static DEVICE_ATTR_RW(addr_context);
> >
> > +static ssize_t addr_exlevel_s_ns_show(struct device *dev,
> > +                                   struct device_attribute *attr,
> > +                                   char *buf)
> > +{
> > +     u8 idx;
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     idx = config->addr_idx;
> > +     val = BMVAL(config->addr_acc[idx], 14, 8);
> > +     spin_unlock(&drvdata->spinlock);
> > +     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t addr_exlevel_s_ns_store(struct device *dev,
> > +                                    struct device_attribute *attr,
> > +                                    const char *buf, size_t size)
> > +{
> > +     u8 idx;
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     if (kstrtoul(buf, 16, &val))
> > +             return -EINVAL;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     idx = config->addr_idx;
> > +     /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */
> > +     config->addr_acc[idx] &= ~(GENMASK(14, 8));
> > +     config->addr_acc[idx] |= (val << 8);
> > +     spin_unlock(&drvdata->spinlock);
> > +     return size;
> > +}
> > +static DEVICE_ATTR_RW(addr_exlevel_s_ns);
> > +
> >  static ssize_t seq_idx_show(struct device *dev,
> >                           struct device_attribute *attr,
> >                           char *buf)
> > @@ -2038,6 +2076,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
> >       &dev_attr_addr_stop.attr,
> >       &dev_attr_addr_ctxtype.attr,
> >       &dev_attr_addr_context.attr,
> > +     &dev_attr_addr_exlevel_s_ns.attr,
> >       &dev_attr_seq_idx.attr,
> >       &dev_attr_seq_state.attr,
> >       &dev_attr_seq_event.attr,
>
> I'm ok with this patch but the new entry needs to be documented in [1].

It is in a later patch.

>   But
> before moving forward with that I'm wondering if this is the way to go.  Would
> it be better to consolidate type, ctxtype, context and exlevel_s_ns in a single
> entry, say addr_acc_type?  We'd shed a fair amount of code and make it more
> simple for users to configure.
>

It will mean the user has less writes to do - but is it really simpler
to understand?

At present each feature takes the input value and interprets / shifts
it to set the relevant bits in the address comparator control
registers (context type being a string input rather than bit values).

The alternative is to require the user to understand the bit values -
which they may well do if they are referring to the ETM docs to
program in this detail, and provide a correct input value for their
requirements.

My addition adds to the API, rather than changes it, but if you prefer
we could go with an update to a single feature to control this value
in the comparator control registers.

Mike

>
> [1]. Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
>
> > --
> > 2.17.1
> >



-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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Re: [PATCH 3/8] coresight: etm4x: Add missing API to set EL match on address filters

[Mathieu Poirier]

On Tue, 27 Aug 2019 at 04:55, Mike Leach <mike.leach@linaro.org> wrote:
>
> Hi Mathieu,
>
> On Mon, 26 Aug 2019 at 23:59, Mathieu Poirier
> <mathieu.poirier@linaro.org> wrote:
> >
> > On Mon, Aug 19, 2019 at 09:57:15PM +0100, Mike Leach wrote:
> > > TRCACATRn registers have match bits for secure and non-secure exception
> > > levels which are not accessible by the sysfs API.
> > > This adds a new sysfs parameter to enable this - addr_exlevel_s_ns.
> > >
> > > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > > ---
> > >  .../coresight/coresight-etm4x-sysfs.c         | 39 +++++++++++++++++++
> > >  1 file changed, 39 insertions(+)
> > >
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > index fa1d6a938f6c..7eab5d7d0b62 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > @@ -1233,6 +1233,44 @@ static ssize_t addr_context_store(struct device *dev,
> > >  }
> > >  static DEVICE_ATTR_RW(addr_context);
> > >
> > > +static ssize_t addr_exlevel_s_ns_show(struct device *dev,
> > > +                                   struct device_attribute *attr,
> > > +                                   char *buf)
> > > +{
> > > +     u8 idx;
> > > +     unsigned long val;
> > > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > > +     struct etmv4_config *config = &drvdata->config;
> > > +
> > > +     spin_lock(&drvdata->spinlock);
> > > +     idx = config->addr_idx;
> > > +     val = BMVAL(config->addr_acc[idx], 14, 8);
> > > +     spin_unlock(&drvdata->spinlock);
> > > +     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > > +}
> > > +
> > > +static ssize_t addr_exlevel_s_ns_store(struct device *dev,
> > > +                                    struct device_attribute *attr,
> > > +                                    const char *buf, size_t size)
> > > +{
> > > +     u8 idx;
> > > +     unsigned long val;
> > > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > > +     struct etmv4_config *config = &drvdata->config;
> > > +
> > > +     if (kstrtoul(buf, 16, &val))
> > > +             return -EINVAL;
> > > +
> > > +     spin_lock(&drvdata->spinlock);
> > > +     idx = config->addr_idx;
> > > +     /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */
> > > +     config->addr_acc[idx] &= ~(GENMASK(14, 8));
> > > +     config->addr_acc[idx] |= (val << 8);
> > > +     spin_unlock(&drvdata->spinlock);
> > > +     return size;
> > > +}
> > > +static DEVICE_ATTR_RW(addr_exlevel_s_ns);
> > > +
> > >  static ssize_t seq_idx_show(struct device *dev,
> > >                           struct device_attribute *attr,
> > >                           char *buf)
> > > @@ -2038,6 +2076,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
> > >       &dev_attr_addr_stop.attr,
> > >       &dev_attr_addr_ctxtype.attr,
> > >       &dev_attr_addr_context.attr,
> > > +     &dev_attr_addr_exlevel_s_ns.attr,
> > >       &dev_attr_seq_idx.attr,
> > >       &dev_attr_seq_state.attr,
> > >       &dev_attr_seq_event.attr,
> >
> > I'm ok with this patch but the new entry needs to be documented in [1].
>
> It is in a later patch.

Very well

>
> >   But
> > before moving forward with that I'm wondering if this is the way to go.  Would
> > it be better to consolidate type, ctxtype, context and exlevel_s_ns in a single
> > entry, say addr_acc_type?  We'd shed a fair amount of code and make it more
> > simple for users to configure.
> >
>
> It will mean the user has less writes to do - but is it really simpler
> to understand?
>
> At present each feature takes the input value and interprets / shifts
> it to set the relevant bits in the address comparator control
> registers (context type being a string input rather than bit values).
>
> The alternative is to require the user to understand the bit values -
> which they may well do if they are referring to the ETM docs to
> program in this detail, and provide a correct input value for their
> requirements.
>
> My addition adds to the API, rather than changes it, but if you prefer
> we could go with an update to a single feature to control this value
> in the comparator control registers.

I am definitely not strongly opinionated on this - it is an idea I
wanted to float by you.  Since you don't seem to have a strong
position either we can just carry on with this patch and revisit in
the future if need be.

>
> Mike
>
> >
> > [1]. Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> >
> > > --
> > > 2.17.1
> > >
>
>
>
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK

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Re: [PATCH 3/8] coresight: etm4x: Add missing API to set EL match on address filters

[Leo Yan]

On Mon, Aug 19, 2019 at 09:57:15PM +0100, Mike Leach wrote:
> TRCACATRn registers have match bits for secure and non-secure exception
> levels which are not accessible by the sysfs API.
> This adds a new sysfs parameter to enable this - addr_exlevel_s_ns.
> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../coresight/coresight-etm4x-sysfs.c         | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index fa1d6a938f6c..7eab5d7d0b62 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -1233,6 +1233,44 @@ static ssize_t addr_context_store(struct device *dev,
>  }
>  static DEVICE_ATTR_RW(addr_context);
>  
> +static ssize_t addr_exlevel_s_ns_show(struct device *dev,
> +				      struct device_attribute *attr,
> +				      char *buf)
> +{
> +	u8 idx;
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	spin_lock(&drvdata->spinlock);
> +	idx = config->addr_idx;
> +	val = BMVAL(config->addr_acc[idx], 14, 8);
> +	spin_unlock(&drvdata->spinlock);
> +	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +
> +static ssize_t addr_exlevel_s_ns_store(struct device *dev,
> +				       struct device_attribute *attr,
> +				       const char *buf, size_t size)
> +{
> +	u8 idx;
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	if (kstrtoul(buf, 16, &val))
> +		return -EINVAL;
> +
> +	spin_lock(&drvdata->spinlock);
> +	idx = config->addr_idx;
> +	/* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */
> +	config->addr_acc[idx] &= ~(GENMASK(14, 8));
> +	config->addr_acc[idx] |= (val << 8);

I think it needs to check if 'val' is out of bound, which only can have
value which is less than 7 bits (finally set for bit 8 to bit 14).

Just curious, if the CPU runs in non-secure mode (e.g. NS-EL1 in
kernel mode), does it have permission to access EXLEVEL_S field?  I
don't see the spec give info for this.

Thanks,
Leo Yan

> +	spin_unlock(&drvdata->spinlock);
> +	return size;
> +}
> +static DEVICE_ATTR_RW(addr_exlevel_s_ns);
> +
>  static ssize_t seq_idx_show(struct device *dev,
>  			    struct device_attribute *attr,
>  			    char *buf)
> @@ -2038,6 +2076,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
>  	&dev_attr_addr_stop.attr,
>  	&dev_attr_addr_ctxtype.attr,
>  	&dev_attr_addr_context.attr,
> +	&dev_attr_addr_exlevel_s_ns.attr,
>  	&dev_attr_seq_idx.attr,
>  	&dev_attr_seq_state.attr,
>  	&dev_attr_seq_event.attr,
> -- 
> 2.17.1
> 
> _______________________________________________
> CoreSight mailing list
> CoreSight@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/coresight

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Re: [PATCH 3/8] coresight: etm4x: Add missing API to set EL match on address filters

[Mike Leach]

Hi Leo,

On Wed, 28 Aug 2019 at 03:53, Leo Yan <leo.yan@linaro.org> wrote:
>
> On Mon, Aug 19, 2019 at 09:57:15PM +0100, Mike Leach wrote:
> > TRCACATRn registers have match bits for secure and non-secure exception
> > levels which are not accessible by the sysfs API.
> > This adds a new sysfs parameter to enable this - addr_exlevel_s_ns.
> >
> > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > ---
> >  .../coresight/coresight-etm4x-sysfs.c         | 39 +++++++++++++++++++
> >  1 file changed, 39 insertions(+)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index fa1d6a938f6c..7eab5d7d0b62 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -1233,6 +1233,44 @@ static ssize_t addr_context_store(struct device *dev,
> >  }
> >  static DEVICE_ATTR_RW(addr_context);
> >
> > +static ssize_t addr_exlevel_s_ns_show(struct device *dev,
> > +                                   struct device_attribute *attr,
> > +                                   char *buf)
> > +{
> > +     u8 idx;
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     idx = config->addr_idx;
> > +     val = BMVAL(config->addr_acc[idx], 14, 8);
> > +     spin_unlock(&drvdata->spinlock);
> > +     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t addr_exlevel_s_ns_store(struct device *dev,
> > +                                    struct device_attribute *attr,
> > +                                    const char *buf, size_t size)
> > +{
> > +     u8 idx;
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     if (kstrtoul(buf, 16, &val))
> > +             return -EINVAL;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     idx = config->addr_idx;
> > +     /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */
> > +     config->addr_acc[idx] &= ~(GENMASK(14, 8));
> > +     config->addr_acc[idx] |= (val << 8);
>
> I think it needs to check if 'val' is out of bound, which only can have
> value which is less than 7 bits (finally set for bit 8 to bit 14).
>

Agreed.

> Just curious, if the CPU runs in non-secure mode (e.g. NS-EL1 in
> kernel mode), does it have permission to access EXLEVEL_S field?  I
> don't see the spec give info for this.
>

This field can be accessed in NS mode - the permissions for tracing
secure state are given in the authentication signals - this register
only controls matching in particular states.
If there is no permission to trace secure state, then the EXLEVEL_S
field will have no effect as trace will automatically be disabled
should the PE transit to secure state.

Thanks

Mike

> Thanks,
> Leo Yan
>
> > +     spin_unlock(&drvdata->spinlock);
> > +     return size;
> > +}
> > +static DEVICE_ATTR_RW(addr_exlevel_s_ns);
> > +
> >  static ssize_t seq_idx_show(struct device *dev,
> >                           struct device_attribute *attr,
> >                           char *buf)
> > @@ -2038,6 +2076,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
> >       &dev_attr_addr_stop.attr,
> >       &dev_attr_addr_ctxtype.attr,
> >       &dev_attr_addr_context.attr,
> > +     &dev_attr_addr_exlevel_s_ns.attr,
> >       &dev_attr_seq_idx.attr,
> >       &dev_attr_seq_state.attr,
> >       &dev_attr_seq_event.attr,
> > --
> > 2.17.1
> >
> > _______________________________________________
> > CoreSight mailing list
> > CoreSight@lists.linaro.org
> > https://lists.linaro.org/mailman/listinfo/coresight



-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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[PATCH 4/8] coresight: etm4x: Fix issues with start-stop logic.

[Mike Leach]

Fixes the following issues when using the ETMv4 start-stop logic.

1) Setting a start or a stop address should not automatically set the
start-stop status to 'on'. The value set by the user in 'mode' must
be respected or start instances could be missed.
2) Missing API for controlling TRCVIPCSSCTLR - start stop control by
PE comparators.
3) Default ETM configuration sets a trace all range, and correctly sets
the start-stop status bit. This was not being correctly reflected in
the 'mode' parameter.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
---
 .../coresight/coresight-etm4x-sysfs.c         | 39 +++++++++++++++++--
 drivers/hwtracing/coresight/coresight-etm4x.c |  1 +
 2 files changed, 36 insertions(+), 4 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 7eab5d7d0b62..3bcc260c9e55 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -217,6 +217,7 @@ static ssize_t reset_store(struct device *dev,
 
 	/* No start-stop filtering for ViewInst */
 	config->vissctlr = 0x0;
+	config->vipcssctlr = 0x0;
 
 	/* Disable seq events */
 	for (i = 0; i < drvdata->nrseqstate-1; i++)
@@ -1059,8 +1060,6 @@ static ssize_t addr_start_store(struct device *dev,
 	config->addr_val[idx] = (u64)val;
 	config->addr_type[idx] = ETM_ADDR_TYPE_START;
 	config->vissctlr |= BIT(idx);
-	/* SSSTATUS, bit[9] - turn on start/stop logic */
-	config->vinst_ctrl |= BIT(9);
 	spin_unlock(&drvdata->spinlock);
 	return size;
 }
@@ -1116,8 +1115,6 @@ static ssize_t addr_stop_store(struct device *dev,
 	config->addr_val[idx] = (u64)val;
 	config->addr_type[idx] = ETM_ADDR_TYPE_STOP;
 	config->vissctlr |= BIT(idx + 16);
-	/* SSSTATUS, bit[9] - turn on start/stop logic */
-	config->vinst_ctrl |= BIT(9);
 	spin_unlock(&drvdata->spinlock);
 	return size;
 }
@@ -1271,6 +1268,39 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev,
 }
 static DEVICE_ATTR_RW(addr_exlevel_s_ns);
 
+static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev,
+					    struct device_attribute *attr,
+					    char *buf)
+{
+	unsigned long val;
+	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	struct etmv4_config *config = &drvdata->config;
+
+	if (!drvdata->nr_pe_cmp)
+		return -EINVAL;
+	val = config->vipcssctlr;
+	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
+}
+static ssize_t vinst_pe_cmp_start_stop_store(struct device *dev,
+					     struct device_attribute *attr,
+					     const char *buf, size_t size)
+{
+	unsigned long val;
+	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	struct etmv4_config *config = &drvdata->config;
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+	if (!drvdata->nr_pe_cmp)
+		return -EINVAL;
+
+	spin_lock(&drvdata->spinlock);
+	config->vipcssctlr = val;
+	spin_unlock(&drvdata->spinlock);
+	return size;
+}
+static DEVICE_ATTR_RW(vinst_pe_cmp_start_stop);
+
 static ssize_t seq_idx_show(struct device *dev,
 			    struct device_attribute *attr,
 			    char *buf)
@@ -2077,6 +2107,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
 	&dev_attr_addr_ctxtype.attr,
 	&dev_attr_addr_context.attr,
 	&dev_attr_addr_exlevel_s_ns.attr,
+	&dev_attr_vinst_pe_cmp_start_stop.attr,
 	&dev_attr_seq_idx.attr,
 	&dev_attr_seq_state.attr,
 	&dev_attr_seq_event.attr,
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 52b8876de157..d8b078d0cc7f 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -868,6 +868,7 @@ static void etm4_set_default_filter(struct etmv4_config *config)
 	 * in the started state
 	 */
 	config->vinst_ctrl |= BIT(9);
+	config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
 
 	/* No start-stop filtering for ViewInst */
 	config->vissctlr = 0x0;
-- 
2.17.1


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Re: [PATCH 4/8] coresight: etm4x: Fix issues with start-stop logic.

[Leo Yan]

Hi Mike,

On Mon, Aug 19, 2019 at 09:57:16PM +0100, Mike Leach wrote:
> Fixes the following issues when using the ETMv4 start-stop logic.
> 
> 1) Setting a start or a stop address should not automatically set the
> start-stop status to 'on'. The value set by the user in 'mode' must
> be respected or start instances could be missed.
> 2) Missing API for controlling TRCVIPCSSCTLR - start stop control by
> PE comparators.
> 3) Default ETM configuration sets a trace all range, and correctly sets
> the start-stop status bit. This was not being correctly reflected in
> the 'mode' parameter.
> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../coresight/coresight-etm4x-sysfs.c         | 39 +++++++++++++++++--
>  drivers/hwtracing/coresight/coresight-etm4x.c |  1 +
>  2 files changed, 36 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 7eab5d7d0b62..3bcc260c9e55 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -217,6 +217,7 @@ static ssize_t reset_store(struct device *dev,
>  
>  	/* No start-stop filtering for ViewInst */
>  	config->vissctlr = 0x0;
> +	config->vipcssctlr = 0x0;
>  
>  	/* Disable seq events */
>  	for (i = 0; i < drvdata->nrseqstate-1; i++)
> @@ -1059,8 +1060,6 @@ static ssize_t addr_start_store(struct device *dev,
>  	config->addr_val[idx] = (u64)val;
>  	config->addr_type[idx] = ETM_ADDR_TYPE_START;
>  	config->vissctlr |= BIT(idx);
> -	/* SSSTATUS, bit[9] - turn on start/stop logic */
> -	config->vinst_ctrl |= BIT(9);
>  	spin_unlock(&drvdata->spinlock);
>  	return size;
>  }
> @@ -1116,8 +1115,6 @@ static ssize_t addr_stop_store(struct device *dev,
>  	config->addr_val[idx] = (u64)val;
>  	config->addr_type[idx] = ETM_ADDR_TYPE_STOP;
>  	config->vissctlr |= BIT(idx + 16);
> -	/* SSSTATUS, bit[9] - turn on start/stop logic */
> -	config->vinst_ctrl |= BIT(9);
>  	spin_unlock(&drvdata->spinlock);
>  	return size;
>  }
> @@ -1271,6 +1268,39 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev,
>  }
>  static DEVICE_ATTR_RW(addr_exlevel_s_ns);
>  
> +static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev,
> +					    struct device_attribute *attr,
> +					    char *buf)
> +{
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	if (!drvdata->nr_pe_cmp)
> +		return -EINVAL;
> +	val = config->vipcssctlr;
> +	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +static ssize_t vinst_pe_cmp_start_stop_store(struct device *dev,
> +					     struct device_attribute *attr,
> +					     const char *buf, size_t size)
> +{
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	if (kstrtoul(buf, 16, &val))
> +		return -EINVAL;
> +	if (!drvdata->nr_pe_cmp)
> +		return -EINVAL;
> +
> +	spin_lock(&drvdata->spinlock);
> +	config->vipcssctlr = val;
> +	spin_unlock(&drvdata->spinlock);

I don't find the code to set 'config->vipcssctlr' into hardware register
TRCVIPCSSCTLR.

And based on the register definition, here we also should clamp the
value for START/STOP?

Thanks,
Leo Yan

> +	return size;
> +}
> +static DEVICE_ATTR_RW(vinst_pe_cmp_start_stop);
> +
>  static ssize_t seq_idx_show(struct device *dev,
>  			    struct device_attribute *attr,
>  			    char *buf)
> @@ -2077,6 +2107,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
>  	&dev_attr_addr_ctxtype.attr,
>  	&dev_attr_addr_context.attr,
>  	&dev_attr_addr_exlevel_s_ns.attr,
> +	&dev_attr_vinst_pe_cmp_start_stop.attr,
>  	&dev_attr_seq_idx.attr,
>  	&dev_attr_seq_state.attr,
>  	&dev_attr_seq_event.attr,
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 52b8876de157..d8b078d0cc7f 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -868,6 +868,7 @@ static void etm4_set_default_filter(struct etmv4_config *config)
>  	 * in the started state
>  	 */
>  	config->vinst_ctrl |= BIT(9);
> +	config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
>  
>  	/* No start-stop filtering for ViewInst */
>  	config->vissctlr = 0x0;
> -- 
> 2.17.1
> 
> _______________________________________________
> CoreSight mailing list
> CoreSight@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/coresight

_______________________________________________
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Re: [PATCH 4/8] coresight: etm4x: Fix issues with start-stop logic.

[Mike Leach]

Hi Leo,

On Wed, 28 Aug 2019 at 04:18, Leo Yan <leo.yan@linaro.org> wrote:
>
> Hi Mike,
>
> On Mon, Aug 19, 2019 at 09:57:16PM +0100, Mike Leach wrote:
> > Fixes the following issues when using the ETMv4 start-stop logic.
> >
> > 1) Setting a start or a stop address should not automatically set the
> > start-stop status to 'on'. The value set by the user in 'mode' must
> > be respected or start instances could be missed.
> > 2) Missing API for controlling TRCVIPCSSCTLR - start stop control by
> > PE comparators.
> > 3) Default ETM configuration sets a trace all range, and correctly sets
> > the start-stop status bit. This was not being correctly reflected in
> > the 'mode' parameter.
> >
> > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > ---
> >  .../coresight/coresight-etm4x-sysfs.c         | 39 +++++++++++++++++--
> >  drivers/hwtracing/coresight/coresight-etm4x.c |  1 +
> >  2 files changed, 36 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index 7eab5d7d0b62..3bcc260c9e55 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -217,6 +217,7 @@ static ssize_t reset_store(struct device *dev,
> >
> >       /* No start-stop filtering for ViewInst */
> >       config->vissctlr = 0x0;
> > +     config->vipcssctlr = 0x0;
> >
> >       /* Disable seq events */
> >       for (i = 0; i < drvdata->nrseqstate-1; i++)
> > @@ -1059,8 +1060,6 @@ static ssize_t addr_start_store(struct device *dev,
> >       config->addr_val[idx] = (u64)val;
> >       config->addr_type[idx] = ETM_ADDR_TYPE_START;
> >       config->vissctlr |= BIT(idx);
> > -     /* SSSTATUS, bit[9] - turn on start/stop logic */
> > -     config->vinst_ctrl |= BIT(9);
> >       spin_unlock(&drvdata->spinlock);
> >       return size;
> >  }
> > @@ -1116,8 +1115,6 @@ static ssize_t addr_stop_store(struct device *dev,
> >       config->addr_val[idx] = (u64)val;
> >       config->addr_type[idx] = ETM_ADDR_TYPE_STOP;
> >       config->vissctlr |= BIT(idx + 16);
> > -     /* SSSTATUS, bit[9] - turn on start/stop logic */
> > -     config->vinst_ctrl |= BIT(9);
> >       spin_unlock(&drvdata->spinlock);
> >       return size;
> >  }
> > @@ -1271,6 +1268,39 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev,
> >  }
> >  static DEVICE_ATTR_RW(addr_exlevel_s_ns);
> >
> > +static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev,
> > +                                         struct device_attribute *attr,
> > +                                         char *buf)
> > +{
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     if (!drvdata->nr_pe_cmp)
> > +             return -EINVAL;
> > +     val = config->vipcssctlr;
> > +     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +static ssize_t vinst_pe_cmp_start_stop_store(struct device *dev,
> > +                                          struct device_attribute *attr,
> > +                                          const char *buf, size_t size)
> > +{
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     if (kstrtoul(buf, 16, &val))
> > +             return -EINVAL;
> > +     if (!drvdata->nr_pe_cmp)
> > +             return -EINVAL;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     config->vipcssctlr = val;
> > +     spin_unlock(&drvdata->spinlock);
>
> I don't find the code to set 'config->vipcssctlr' into hardware register
> TRCVIPCSSCTLR.
>

This is in coresight-etm4x.c, etm4_enable_hw(), ll 126-127

> And based on the register definition, here we also should clamp the
> value for START/STOP?
>

Unimplemented fields are RES0 - there is no issue with writing these -
they will remain RES0.  (ETM arch spec, section 7.2.1)

Thanks

Mike

> Thanks,
> Leo Yan
>
> > +     return size;
> > +}
> > +static DEVICE_ATTR_RW(vinst_pe_cmp_start_stop);
> > +
> >  static ssize_t seq_idx_show(struct device *dev,
> >                           struct device_attribute *attr,
> >                           char *buf)
> > @@ -2077,6 +2107,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
> >       &dev_attr_addr_ctxtype.attr,
> >       &dev_attr_addr_context.attr,
> >       &dev_attr_addr_exlevel_s_ns.attr,
> > +     &dev_attr_vinst_pe_cmp_start_stop.attr,
> >       &dev_attr_seq_idx.attr,
> >       &dev_attr_seq_state.attr,
> >       &dev_attr_seq_event.attr,
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> > index 52b8876de157..d8b078d0cc7f 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> > @@ -868,6 +868,7 @@ static void etm4_set_default_filter(struct etmv4_config *config)
> >        * in the started state
> >        */
> >       config->vinst_ctrl |= BIT(9);
> > +     config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
> >
> >       /* No start-stop filtering for ViewInst */
> >       config->vissctlr = 0x0;
> > --
> > 2.17.1
> >
> > _______________________________________________
> > CoreSight mailing list
> > CoreSight@lists.linaro.org
> > https://lists.linaro.org/mailman/listinfo/coresight



-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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[PATCH 5/8] coresight: etm4x: Improve usability of sysfs API.

[Mike Leach]

Some changes to make the sysfs programming more intuitive.

1) Setting include / exclude on a range had to be done by setting
the bit in 'mode' before setting the range. However, setting this
bit also had the effect of altering the current range as well.

Changed to only set include / exclude setting of a range at the point of
setting that range. Either use a 3rd input parameter as the include exclude
value, or if not present use the current value of 'mode'. Do not change
current range when 'mode' changes.

2) Context ID and VM ID masks required 2 value inputs, even when the
second value is ignored as insufficient CID / VMID comparators are
implemented.
Permit a single value to be used if that is sufficient to cover all
implemented comparators.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
---
 .../coresight/coresight-etm4x-sysfs.c         | 24 +++++++++++++------
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 3bcc260c9e55..baac5b48b7ac 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -297,8 +297,6 @@ static ssize_t mode_store(struct device *dev,
 
 	spin_lock(&drvdata->spinlock);
 	config->mode = val & ETMv4_MODE_ALL;
-	etm4_set_mode_exclude(drvdata,
-			      config->mode & ETM_MODE_EXCLUDE ? true : false);
 
 	if (drvdata->instrp0 == true) {
 		/* start by clearing instruction P0 field */
@@ -972,8 +970,12 @@ static ssize_t addr_range_store(struct device *dev,
 	unsigned long val1, val2;
 	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 	struct etmv4_config *config = &drvdata->config;
+	int elements, exclude;
 
-	if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
+	elements = sscanf(buf, "%lx %lx %x", &val1, &val2, &exclude);
+
+	/*  exclude is optional, but need at least two parameter */
+	if (elements < 2)
 		return -EINVAL;
 	/* lower address comparator cannot have a higher address value */
 	if (val1 > val2)
@@ -1001,9 +1003,11 @@ static ssize_t addr_range_store(struct device *dev,
 	/*
 	 * Program include or exclude control bits for vinst or vdata
 	 * whenever we change addr comparators to ETM_ADDR_TYPE_RANGE
+	 * use supplied value, or default to bit set in 'mode'
 	 */
-	etm4_set_mode_exclude(drvdata,
-			      config->mode & ETM_MODE_EXCLUDE ? true : false);
+	if (elements != 3)
+		exclude = config->mode & ETM_MODE_EXCLUDE;
+	etm4_set_mode_exclude(drvdata, exclude ? true : false);
 
 	spin_unlock(&drvdata->spinlock);
 	return size;
@@ -1787,6 +1791,7 @@ static ssize_t ctxid_masks_store(struct device *dev,
 	unsigned long val1, val2, mask;
 	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 	struct etmv4_config *config = &drvdata->config;
+	int nr_inputs;
 
 	/*
 	 * Don't use contextID tracing if coming from a PID namespace.  See
@@ -1802,7 +1807,9 @@ static ssize_t ctxid_masks_store(struct device *dev,
 	 */
 	if (!drvdata->ctxid_size || !drvdata->numcidc)
 		return -EINVAL;
-	if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
+	/* one mask if < 4 comparators, two for up to 8 */
+	nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
+	if ((drvdata->numcidc > 4) && (nr_inputs != 2))
 		return -EINVAL;
 
 	spin_lock(&drvdata->spinlock);
@@ -1976,6 +1983,7 @@ static ssize_t vmid_masks_store(struct device *dev,
 	unsigned long val1, val2, mask;
 	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 	struct etmv4_config *config = &drvdata->config;
+	int nr_inputs;
 
 	/*
 	 * only implemented when vmid tracing is enabled, i.e. at least one
@@ -1983,7 +1991,9 @@ static ssize_t vmid_masks_store(struct device *dev,
 	 */
 	if (!drvdata->vmid_size || !drvdata->numvmidc)
 		return -EINVAL;
-	if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
+	/* one mask if < 4 comparators, two for up to 8 */
+	nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
+	if ((drvdata->numvmidc > 4) && (nr_inputs != 2))
 		return -EINVAL;
 
 	spin_lock(&drvdata->spinlock);
-- 
2.17.1


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Re: [PATCH 5/8] coresight: etm4x: Improve usability of sysfs API.

[Mathieu Poirier]

On Mon, Aug 19, 2019 at 09:57:17PM +0100, Mike Leach wrote:
> Some changes to make the sysfs programming more intuitive.
> 
> 1) Setting include / exclude on a range had to be done by setting
> the bit in 'mode' before setting the range. However, setting this
> bit also had the effect of altering the current range as well.
> 
> Changed to only set include / exclude setting of a range at the point of
> setting that range. Either use a 3rd input parameter as the include exclude
> value, or if not present use the current value of 'mode'. Do not change
> current range when 'mode' changes.
> 
> 2) Context ID and VM ID masks required 2 value inputs, even when the
> second value is ignored as insufficient CID / VMID comparators are
> implemented.
> Permit a single value to be used if that is sufficient to cover all
> implemented comparators.

Please split in two patches.  With that:

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../coresight/coresight-etm4x-sysfs.c         | 24 +++++++++++++------
>  1 file changed, 17 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 3bcc260c9e55..baac5b48b7ac 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -297,8 +297,6 @@ static ssize_t mode_store(struct device *dev,
>  
>  	spin_lock(&drvdata->spinlock);
>  	config->mode = val & ETMv4_MODE_ALL;
> -	etm4_set_mode_exclude(drvdata,
> -			      config->mode & ETM_MODE_EXCLUDE ? true : false);
>  
>  	if (drvdata->instrp0 == true) {
>  		/* start by clearing instruction P0 field */
> @@ -972,8 +970,12 @@ static ssize_t addr_range_store(struct device *dev,
>  	unsigned long val1, val2;
>  	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
>  	struct etmv4_config *config = &drvdata->config;
> +	int elements, exclude;
>  
> -	if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
> +	elements = sscanf(buf, "%lx %lx %x", &val1, &val2, &exclude);
> +
> +	/*  exclude is optional, but need at least two parameter */
> +	if (elements < 2)
>  		return -EINVAL;
>  	/* lower address comparator cannot have a higher address value */
>  	if (val1 > val2)
> @@ -1001,9 +1003,11 @@ static ssize_t addr_range_store(struct device *dev,
>  	/*
>  	 * Program include or exclude control bits for vinst or vdata
>  	 * whenever we change addr comparators to ETM_ADDR_TYPE_RANGE
> +	 * use supplied value, or default to bit set in 'mode'
>  	 */
> -	etm4_set_mode_exclude(drvdata,
> -			      config->mode & ETM_MODE_EXCLUDE ? true : false);
> +	if (elements != 3)
> +		exclude = config->mode & ETM_MODE_EXCLUDE;
> +	etm4_set_mode_exclude(drvdata, exclude ? true : false);
>  
>  	spin_unlock(&drvdata->spinlock);
>  	return size;
> @@ -1787,6 +1791,7 @@ static ssize_t ctxid_masks_store(struct device *dev,
>  	unsigned long val1, val2, mask;
>  	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
>  	struct etmv4_config *config = &drvdata->config;
> +	int nr_inputs;
>  
>  	/*
>  	 * Don't use contextID tracing if coming from a PID namespace.  See
> @@ -1802,7 +1807,9 @@ static ssize_t ctxid_masks_store(struct device *dev,
>  	 */
>  	if (!drvdata->ctxid_size || !drvdata->numcidc)
>  		return -EINVAL;
> -	if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
> +	/* one mask if < 4 comparators, two for up to 8 */
> +	nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
> +	if ((drvdata->numcidc > 4) && (nr_inputs != 2))
>  		return -EINVAL;
>  
>  	spin_lock(&drvdata->spinlock);
> @@ -1976,6 +1983,7 @@ static ssize_t vmid_masks_store(struct device *dev,
>  	unsigned long val1, val2, mask;
>  	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
>  	struct etmv4_config *config = &drvdata->config;
> +	int nr_inputs;
>  
>  	/*
>  	 * only implemented when vmid tracing is enabled, i.e. at least one
> @@ -1983,7 +1991,9 @@ static ssize_t vmid_masks_store(struct device *dev,
>  	 */
>  	if (!drvdata->vmid_size || !drvdata->numvmidc)
>  		return -EINVAL;
> -	if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
> +	/* one mask if < 4 comparators, two for up to 8 */
> +	nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
> +	if ((drvdata->numvmidc > 4) && (nr_inputs != 2))
>  		return -EINVAL;
>  
>  	spin_lock(&drvdata->spinlock);
> -- 
> 2.17.1
> 

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Re: [PATCH 5/8] coresight: etm4x: Improve usability of sysfs API.

[Leo Yan]

On Mon, Aug 19, 2019 at 09:57:17PM +0100, Mike Leach wrote:
> Some changes to make the sysfs programming more intuitive.
> 
> 1) Setting include / exclude on a range had to be done by setting
> the bit in 'mode' before setting the range. However, setting this
> bit also had the effect of altering the current range as well.
> 
> Changed to only set include / exclude setting of a range at the point of
> setting that range. Either use a 3rd input parameter as the include exclude
> value, or if not present use the current value of 'mode'. Do not change
> current range when 'mode' changes.
> 
> 2) Context ID and VM ID masks required 2 value inputs, even when the
> second value is ignored as insufficient CID / VMID comparators are
> implemented.
> Permit a single value to be used if that is sufficient to cover all
> implemented comparators.
> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../coresight/coresight-etm4x-sysfs.c         | 24 +++++++++++++------
>  1 file changed, 17 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 3bcc260c9e55..baac5b48b7ac 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -297,8 +297,6 @@ static ssize_t mode_store(struct device *dev,
>  
>  	spin_lock(&drvdata->spinlock);
>  	config->mode = val & ETMv4_MODE_ALL;
> -	etm4_set_mode_exclude(drvdata,
> -			      config->mode & ETM_MODE_EXCLUDE ? true : false);
>  
>  	if (drvdata->instrp0 == true) {
>  		/* start by clearing instruction P0 field */
> @@ -972,8 +970,12 @@ static ssize_t addr_range_store(struct device *dev,
>  	unsigned long val1, val2;
>  	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
>  	struct etmv4_config *config = &drvdata->config;
> +	int elements, exclude;
>  
> -	if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
> +	elements = sscanf(buf, "%lx %lx %x", &val1, &val2, &exclude);
> +
> +	/*  exclude is optional, but need at least two parameter */
> +	if (elements < 2)
>  		return -EINVAL;
>  	/* lower address comparator cannot have a higher address value */
>  	if (val1 > val2)
> @@ -1001,9 +1003,11 @@ static ssize_t addr_range_store(struct device *dev,
>  	/*
>  	 * Program include or exclude control bits for vinst or vdata
>  	 * whenever we change addr comparators to ETM_ADDR_TYPE_RANGE
> +	 * use supplied value, or default to bit set in 'mode'
>  	 */
> -	etm4_set_mode_exclude(drvdata,
> -			      config->mode & ETM_MODE_EXCLUDE ? true : false);
> +	if (elements != 3)
> +		exclude = config->mode & ETM_MODE_EXCLUDE;
> +	etm4_set_mode_exclude(drvdata, exclude ? true : false);
>  
>  	spin_unlock(&drvdata->spinlock);
>  	return size;
> @@ -1787,6 +1791,7 @@ static ssize_t ctxid_masks_store(struct device *dev,
>  	unsigned long val1, val2, mask;
>  	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
>  	struct etmv4_config *config = &drvdata->config;
> +	int nr_inputs;
>  
>  	/*
>  	 * Don't use contextID tracing if coming from a PID namespace.  See
> @@ -1802,7 +1807,9 @@ static ssize_t ctxid_masks_store(struct device *dev,
>  	 */
>  	if (!drvdata->ctxid_size || !drvdata->numcidc)
>  		return -EINVAL;
> -	if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
> +	/* one mask if < 4 comparators, two for up to 8 */

One maks is <= 4 comparators.

> +	nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
> +	if ((drvdata->numcidc > 4) && (nr_inputs != 2))
>  		return -EINVAL;
>  
>  	spin_lock(&drvdata->spinlock);
> @@ -1976,6 +1983,7 @@ static ssize_t vmid_masks_store(struct device *dev,
>  	unsigned long val1, val2, mask;
>  	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
>  	struct etmv4_config *config = &drvdata->config;
> +	int nr_inputs;
>  
>  	/*
>  	 * only implemented when vmid tracing is enabled, i.e. at least one
> @@ -1983,7 +1991,9 @@ static ssize_t vmid_masks_store(struct device *dev,
>  	 */
>  	if (!drvdata->vmid_size || !drvdata->numvmidc)
>  		return -EINVAL;
> -	if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
> +	/* one mask if < 4 comparators, two for up to 8 */

One maks is <= 4 comparators.

> +	nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
> +	if ((drvdata->numvmidc > 4) && (nr_inputs != 2))
>  		return -EINVAL;
>  
>  	spin_lock(&drvdata->spinlock);
> -- 
> 2.17.1
> 
> _______________________________________________
> CoreSight mailing list
> CoreSight@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/coresight

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Re: [PATCH 5/8] coresight: etm4x: Improve usability of sysfs API.

[Mike Leach]

Hi Mathieu, Leo,

Will split & fix comments.

Thanks

Mike

On Wed, 28 Aug 2019 at 04:37, Leo Yan <leo.yan@linaro.org> wrote:
>
> On Mon, Aug 19, 2019 at 09:57:17PM +0100, Mike Leach wrote:
> > Some changes to make the sysfs programming more intuitive.
> >
> > 1) Setting include / exclude on a range had to be done by setting
> > the bit in 'mode' before setting the range. However, setting this
> > bit also had the effect of altering the current range as well.
> >
> > Changed to only set include / exclude setting of a range at the point of
> > setting that range. Either use a 3rd input parameter as the include exclude
> > value, or if not present use the current value of 'mode'. Do not change
> > current range when 'mode' changes.
> >
> > 2) Context ID and VM ID masks required 2 value inputs, even when the
> > second value is ignored as insufficient CID / VMID comparators are
> > implemented.
> > Permit a single value to be used if that is sufficient to cover all
> > implemented comparators.
> >
> > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > ---
> >  .../coresight/coresight-etm4x-sysfs.c         | 24 +++++++++++++------
> >  1 file changed, 17 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index 3bcc260c9e55..baac5b48b7ac 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -297,8 +297,6 @@ static ssize_t mode_store(struct device *dev,
> >
> >       spin_lock(&drvdata->spinlock);
> >       config->mode = val & ETMv4_MODE_ALL;
> > -     etm4_set_mode_exclude(drvdata,
> > -                           config->mode & ETM_MODE_EXCLUDE ? true : false);
> >
> >       if (drvdata->instrp0 == true) {
> >               /* start by clearing instruction P0 field */
> > @@ -972,8 +970,12 @@ static ssize_t addr_range_store(struct device *dev,
> >       unsigned long val1, val2;
> >       struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> >       struct etmv4_config *config = &drvdata->config;
> > +     int elements, exclude;
> >
> > -     if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
> > +     elements = sscanf(buf, "%lx %lx %x", &val1, &val2, &exclude);
> > +
> > +     /*  exclude is optional, but need at least two parameter */
> > +     if (elements < 2)
> >               return -EINVAL;
> >       /* lower address comparator cannot have a higher address value */
> >       if (val1 > val2)
> > @@ -1001,9 +1003,11 @@ static ssize_t addr_range_store(struct device *dev,
> >       /*
> >        * Program include or exclude control bits for vinst or vdata
> >        * whenever we change addr comparators to ETM_ADDR_TYPE_RANGE
> > +      * use supplied value, or default to bit set in 'mode'
> >        */
> > -     etm4_set_mode_exclude(drvdata,
> > -                           config->mode & ETM_MODE_EXCLUDE ? true : false);
> > +     if (elements != 3)
> > +             exclude = config->mode & ETM_MODE_EXCLUDE;
> > +     etm4_set_mode_exclude(drvdata, exclude ? true : false);
> >
> >       spin_unlock(&drvdata->spinlock);
> >       return size;
> > @@ -1787,6 +1791,7 @@ static ssize_t ctxid_masks_store(struct device *dev,
> >       unsigned long val1, val2, mask;
> >       struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> >       struct etmv4_config *config = &drvdata->config;
> > +     int nr_inputs;
> >
> >       /*
> >        * Don't use contextID tracing if coming from a PID namespace.  See
> > @@ -1802,7 +1807,9 @@ static ssize_t ctxid_masks_store(struct device *dev,
> >        */
> >       if (!drvdata->ctxid_size || !drvdata->numcidc)
> >               return -EINVAL;
> > -     if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
> > +     /* one mask if < 4 comparators, two for up to 8 */
>
> One maks is <= 4 comparators.
>
> > +     nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
> > +     if ((drvdata->numcidc > 4) && (nr_inputs != 2))
> >               return -EINVAL;
> >
> >       spin_lock(&drvdata->spinlock);
> > @@ -1976,6 +1983,7 @@ static ssize_t vmid_masks_store(struct device *dev,
> >       unsigned long val1, val2, mask;
> >       struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> >       struct etmv4_config *config = &drvdata->config;
> > +     int nr_inputs;
> >
> >       /*
> >        * only implemented when vmid tracing is enabled, i.e. at least one
> > @@ -1983,7 +1991,9 @@ static ssize_t vmid_masks_store(struct device *dev,
> >        */
> >       if (!drvdata->vmid_size || !drvdata->numvmidc)
> >               return -EINVAL;
> > -     if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
> > +     /* one mask if < 4 comparators, two for up to 8 */
>
> One maks is <= 4 comparators.
>
> > +     nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
> > +     if ((drvdata->numvmidc > 4) && (nr_inputs != 2))
> >               return -EINVAL;
> >
> >       spin_lock(&drvdata->spinlock);
> > --
> > 2.17.1
> >
> > _______________________________________________
> > CoreSight mailing list
> > CoreSight@lists.linaro.org
> > https://lists.linaro.org/mailman/listinfo/coresight



-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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[PATCH 6/8] coresight: etm4x: Add view comparator settings API to sysfs.

[Mike Leach]

Currently it is not possible to view the current settings of a given
address comparator without knowing what type it is set to. For example, if
a comparator is set as an addr_start comparator, attempting to read
addr_stop for the same index will result in an error.

addr_cmp_view is added to allow the user to see the current settings of
the indexed address comparator without resorting to trail and error when
the set type is not known.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
---
 .../coresight/coresight-etm4x-sysfs.c         | 51 +++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index baac5b48b7ac..483976074779 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -1272,6 +1272,56 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev,
 }
 static DEVICE_ATTR_RW(addr_exlevel_s_ns);
 
+static const char * const addr_type_names[] = {
+	"unused",
+	"single",
+	"range",
+	"start",
+	"stop"
+};
+
+static ssize_t addr_cmp_view_show(struct device *dev,
+				  struct device_attribute *attr, char *buf)
+{
+	u8 idx, addr_type;
+	unsigned long addr_v, addr_v2, addr_ctrl;
+	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	struct etmv4_config *config = &drvdata->config;
+	int size = 0;
+	bool exclude = false;
+
+	spin_lock(&drvdata->spinlock);
+	idx = config->addr_idx;
+	addr_v = config->addr_val[idx];
+	addr_ctrl = config->addr_acc[idx];
+	addr_type = config->addr_type[idx];
+	if (addr_type == ETM_ADDR_TYPE_RANGE) {
+		if (idx%2) {
+			idx -= 1;
+			addr_v2 = addr_v;
+			addr_v = config->addr_val[idx];
+		} else
+			addr_v2 = config->addr_val[idx+1];
+		exclude = config->viiectlr & BIT(idx / 2 + 16);
+	}
+	spin_unlock(&drvdata->spinlock);
+	if (addr_type) {
+		size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] %s %#lx", idx,
+				 addr_type_names[addr_type], addr_v);
+		if (addr_type == ETM_ADDR_TYPE_RANGE) {
+			size += scnprintf(buf+size, PAGE_SIZE-size,
+					  " %#lx %s", addr_v2,
+					  exclude ? "exclude" : "include");
+		}
+		size += scnprintf(buf+size, PAGE_SIZE-size,
+				  " ctrl(%#lx)\n", addr_ctrl);
+	} else {
+		size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] unused\n", idx);
+	}
+	return size;
+}
+static DEVICE_ATTR_RO(addr_cmp_view);
+
 static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev,
 					    struct device_attribute *attr,
 					    char *buf)
@@ -2117,6 +2167,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
 	&dev_attr_addr_ctxtype.attr,
 	&dev_attr_addr_context.attr,
 	&dev_attr_addr_exlevel_s_ns.attr,
+	&dev_attr_addr_cmp_view.attr,
 	&dev_attr_vinst_pe_cmp_start_stop.attr,
 	&dev_attr_seq_idx.attr,
 	&dev_attr_seq_state.attr,
-- 
2.17.1


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Re: [PATCH 6/8] coresight: etm4x: Add view comparator settings API to sysfs.

[Mathieu Poirier]

On Mon, Aug 19, 2019 at 09:57:18PM +0100, Mike Leach wrote:
> Currently it is not possible to view the current settings of a given
> address comparator without knowing what type it is set to. For example, if
> a comparator is set as an addr_start comparator, attempting to read
> addr_stop for the same index will result in an error.
> 
> addr_cmp_view is added to allow the user to see the current settings of
> the indexed address comparator without resorting to trail and error when
> the set type is not known.
> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../coresight/coresight-etm4x-sysfs.c         | 51 +++++++++++++++++++
>  1 file changed, 51 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index baac5b48b7ac..483976074779 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -1272,6 +1272,56 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev,
>  }
>  static DEVICE_ATTR_RW(addr_exlevel_s_ns);
>  
> +static const char * const addr_type_names[] = {
> +	"unused",
> +	"single",
> +	"range",
> +	"start",
> +	"stop"
> +};
> +
> +static ssize_t addr_cmp_view_show(struct device *dev,
> +				  struct device_attribute *attr, char *buf)
> +{
> +	u8 idx, addr_type;
> +	unsigned long addr_v, addr_v2, addr_ctrl;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +	int size = 0;
> +	bool exclude = false;
> +
> +	spin_lock(&drvdata->spinlock);
> +	idx = config->addr_idx;
> +	addr_v = config->addr_val[idx];
> +	addr_ctrl = config->addr_acc[idx];
> +	addr_type = config->addr_type[idx];
> +	if (addr_type == ETM_ADDR_TYPE_RANGE) {
> +		if (idx%2) {
> +			idx -= 1;
> +			addr_v2 = addr_v;
> +			addr_v = config->addr_val[idx];
> +		} else
> +			addr_v2 = config->addr_val[idx+1];

s/"idx+1"/"idx + 1"/

With that:

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

> +		exclude = config->viiectlr & BIT(idx / 2 + 16);
> +	}
> +	spin_unlock(&drvdata->spinlock);
> +	if (addr_type) {
> +		size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] %s %#lx", idx,
> +				 addr_type_names[addr_type], addr_v);
> +		if (addr_type == ETM_ADDR_TYPE_RANGE) {
> +			size += scnprintf(buf+size, PAGE_SIZE-size,
> +					  " %#lx %s", addr_v2,
> +					  exclude ? "exclude" : "include");
> +		}
> +		size += scnprintf(buf+size, PAGE_SIZE-size,
> +				  " ctrl(%#lx)\n", addr_ctrl);
> +	} else {
> +		size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] unused\n", idx);
> +	}
> +	return size;
> +}
> +static DEVICE_ATTR_RO(addr_cmp_view);
> +
>  static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev,
>  					    struct device_attribute *attr,
>  					    char *buf)
> @@ -2117,6 +2167,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
>  	&dev_attr_addr_ctxtype.attr,
>  	&dev_attr_addr_context.attr,
>  	&dev_attr_addr_exlevel_s_ns.attr,
> +	&dev_attr_addr_cmp_view.attr,
>  	&dev_attr_vinst_pe_cmp_start_stop.attr,
>  	&dev_attr_seq_idx.attr,
>  	&dev_attr_seq_state.attr,
> -- 
> 2.17.1
> 

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Re: [PATCH 6/8] coresight: etm4x: Add view comparator settings API to sysfs.

[Leo Yan]

Hi Mike,

On Mon, Aug 19, 2019 at 09:57:18PM +0100, Mike Leach wrote:
> Currently it is not possible to view the current settings of a given
> address comparator without knowing what type it is set to. For example, if
> a comparator is set as an addr_start comparator, attempting to read
> addr_stop for the same index will result in an error.
> 
> addr_cmp_view is added to allow the user to see the current settings of
> the indexed address comparator without resorting to trail and error when
> the set type is not known.
> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../coresight/coresight-etm4x-sysfs.c         | 51 +++++++++++++++++++
>  1 file changed, 51 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index baac5b48b7ac..483976074779 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -1272,6 +1272,56 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev,
>  }
>  static DEVICE_ATTR_RW(addr_exlevel_s_ns);
>  
> +static const char * const addr_type_names[] = {
> +	"unused",
> +	"single",
> +	"range",
> +	"start",
> +	"stop"
> +};
> +
> +static ssize_t addr_cmp_view_show(struct device *dev,
> +				  struct device_attribute *attr, char *buf)
> +{
> +	u8 idx, addr_type;
> +	unsigned long addr_v, addr_v2, addr_ctrl;

Some nitpicks, if you disagree, just ignore them :)

nitpicks: maybe we can use 'addr_v1' and 'addr_v2', we even can use
'addr_l' and 'addr_h'.

> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +	int size = 0;
> +	bool exclude = false;
> +
> +	spin_lock(&drvdata->spinlock);
> +	idx = config->addr_idx;
> +	addr_v = config->addr_val[idx];
> +	addr_ctrl = config->addr_acc[idx];
> +	addr_type = config->addr_type[idx];
> +	if (addr_type == ETM_ADDR_TYPE_RANGE) {
> +		if (idx%2) {

if (idx & 0x1)

> +			idx -= 1;
> +			addr_v2 = addr_v;
> +			addr_v = config->addr_val[idx];
> +		} else
> +			addr_v2 = config->addr_val[idx+1];

The code style doc [1] suggests to use braces for 'else' as well.

> +		exclude = config->viiectlr & BIT(idx / 2 + 16);
> +	}
> +	spin_unlock(&drvdata->spinlock);
> +	if (addr_type) {
> +		size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] %s %#lx", idx,
> +				 addr_type_names[addr_type], addr_v);
> +		if (addr_type == ETM_ADDR_TYPE_RANGE) {
> +			size += scnprintf(buf+size, PAGE_SIZE-size,

s/buf+size/buf + size
s/PAGE_SIZE-size/PAGE_SIZE - size

> +					  " %#lx %s", addr_v2,
> +					  exclude ? "exclude" : "include");
> +		}
> +		size += scnprintf(buf+size, PAGE_SIZE-size,

s/buf+size/buf + size

This patch logic is clear for me, so you could add my review tag:

Reviewed-by: Leo Yan <leo.yan@linaro.org>

Thanks,
Leo Yan

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/coding-style.rst#n194


> +				  " ctrl(%#lx)\n", addr_ctrl);
> +	} else {
> +		size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] unused\n", idx);
> +	}
> +	return size;
> +}
> +static DEVICE_ATTR_RO(addr_cmp_view);
> +
>  static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev,
>  					    struct device_attribute *attr,
>  					    char *buf)
> @@ -2117,6 +2167,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
>  	&dev_attr_addr_ctxtype.attr,
>  	&dev_attr_addr_context.attr,
>  	&dev_attr_addr_exlevel_s_ns.attr,
> +	&dev_attr_addr_cmp_view.attr,
>  	&dev_attr_vinst_pe_cmp_start_stop.attr,
>  	&dev_attr_seq_idx.attr,
>  	&dev_attr_seq_state.attr,
> -- 
> 2.17.1
> 
> _______________________________________________
> CoreSight mailing list
> CoreSight@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/coresight

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[PATCH 7/8] coresight: etm4x: Add missing single-shot control API to sysfs

[Mike Leach]

An API to control single-shot comparator operation was missing from sysfs.
This adds the parameters to sysfs to allow programming of this feature.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
---
 .../coresight/coresight-etm4x-sysfs.c         | 122 ++++++++++++++++++
 drivers/hwtracing/coresight/coresight-etm4x.c |  26 +++-
 drivers/hwtracing/coresight/coresight-etm4x.h |   3 +
 3 files changed, 150 insertions(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 483976074779..7c019dda1236 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -239,6 +239,7 @@ static ssize_t reset_store(struct device *dev,
 	for (i = 0; i < drvdata->nr_resource; i++)
 		config->res_ctrl[i] = 0x0;
 
+	config->ss_idx = 0x0;
 	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 		config->ss_ctrl[i] = 0x0;
 		config->ss_pe_cmp[i] = 0x0;
@@ -1713,6 +1714,123 @@ static ssize_t res_ctrl_store(struct device *dev,
 }
 static DEVICE_ATTR_RW(res_ctrl);
 
+static ssize_t sshot_idx_show(struct device *dev,
+			      struct device_attribute *attr, char *buf)
+{
+	unsigned long val;
+	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	struct etmv4_config *config = &drvdata->config;
+
+	val = config->ss_idx;
+	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
+}
+
+static ssize_t sshot_idx_store(struct device *dev,
+			       struct device_attribute *attr,
+			       const char *buf, size_t size)
+{
+	unsigned long val;
+	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	struct etmv4_config *config = &drvdata->config;
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+	if (val >= drvdata->nr_ss_cmp)
+		return -EINVAL;
+
+	spin_lock(&drvdata->spinlock);
+	config->ss_idx = val;
+	spin_unlock(&drvdata->spinlock);
+	return size;
+}
+static DEVICE_ATTR_RW(sshot_idx);
+
+static ssize_t sshot_ctrl_show(struct device *dev,
+			       struct device_attribute *attr,
+			       char *buf)
+{
+	unsigned long val;
+	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	struct etmv4_config *config = &drvdata->config;
+
+	spin_lock(&drvdata->spinlock);
+	val = config->ss_ctrl[config->ss_idx];
+	spin_unlock(&drvdata->spinlock);
+	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
+}
+
+static ssize_t sshot_ctrl_store(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t size)
+{
+	u8 idx;
+	unsigned long val;
+	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	struct etmv4_config *config = &drvdata->config;
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	spin_lock(&drvdata->spinlock);
+	idx = config->ss_idx;
+	config->ss_ctrl[idx] = val & GENMASK(24, 0);
+	/* must clear bit 31 in related status register on programming */
+	config->ss_status[idx] &= ~BIT(31);
+	spin_unlock(&drvdata->spinlock);
+	return size;
+}
+static DEVICE_ATTR_RW(sshot_ctrl);
+
+static ssize_t sshot_status_show(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	unsigned long val;
+	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	struct etmv4_config *config = &drvdata->config;
+
+	spin_lock(&drvdata->spinlock);
+	val = config->ss_status[config->ss_idx];
+	spin_unlock(&drvdata->spinlock);
+	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
+}
+static DEVICE_ATTR_RO(sshot_status);
+
+static ssize_t sshot_pe_ctrl_show(struct device *dev,
+				  struct device_attribute *attr,
+				  char *buf)
+{
+	unsigned long val;
+	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	struct etmv4_config *config = &drvdata->config;
+
+	spin_lock(&drvdata->spinlock);
+	val = config->ss_pe_cmp[config->ss_idx];
+	spin_unlock(&drvdata->spinlock);
+	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
+}
+
+static ssize_t sshot_pe_ctrl_store(struct device *dev,
+				   struct device_attribute *attr,
+				   const char *buf, size_t size)
+{
+	u8 idx;
+	unsigned long val;
+	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	struct etmv4_config *config = &drvdata->config;
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	spin_lock(&drvdata->spinlock);
+	idx = config->ss_idx;
+	config->ss_ctrl[idx] = val & GENMASK(7, 0);
+	/* must clear bit 31 in related status register on programming */
+	config->ss_status[idx] &= ~BIT(31);
+	spin_unlock(&drvdata->spinlock);
+	return size;
+}
+static DEVICE_ATTR_RW(sshot_pe_ctrl);
+
 static ssize_t ctxid_idx_show(struct device *dev,
 			      struct device_attribute *attr,
 			      char *buf)
@@ -2169,6 +2287,10 @@ static struct attribute *coresight_etmv4_attrs[] = {
 	&dev_attr_addr_exlevel_s_ns.attr,
 	&dev_attr_addr_cmp_view.attr,
 	&dev_attr_vinst_pe_cmp_start_stop.attr,
+	&dev_attr_sshot_idx.attr,
+	&dev_attr_sshot_ctrl.attr,
+	&dev_attr_sshot_pe_ctrl.attr,
+	&dev_attr_sshot_status.attr,
 	&dev_attr_seq_idx.attr,
 	&dev_attr_seq_state.attr,
 	&dev_attr_seq_event.attr,
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index d8b078d0cc7f..fb7083218410 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -149,6 +149,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 			       drvdata->base + TRCRSCTLRn(i));
 
 	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
+		/* always clear status bit on restart if using single-shot */
+		if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
+			config->ss_status[i] &= ~BIT(31);
 		writel_relaxed(config->ss_ctrl[i],
 			       drvdata->base + TRCSSCCRn(i));
 		writel_relaxed(config->ss_status[i],
@@ -448,6 +451,9 @@ static void etm4_disable_hw(void *info)
 {
 	u32 control;
 	struct etmv4_drvdata *drvdata = info;
+	struct etmv4_config *config = &drvdata->config;
+	struct device *etm_dev = &drvdata->csdev->dev;
+	int i;
 
 	CS_UNLOCK(drvdata->base);
 
@@ -470,6 +476,18 @@ static void etm4_disable_hw(void *info)
 	isb();
 	writel_relaxed(control, drvdata->base + TRCPRGCTLR);
 
+	/* wait for TRCSTATR.PMSTABLE to go to '1' */
+	if (coresight_timeout(drvdata->base, TRCSTATR,
+			      TRCSTATR_PMSTABLE_BIT, 1))
+		dev_err(etm_dev,
+			"timeout while waiting for PM stable Trace Status\n");
+
+	/* read the status of the single shot comparators */
+	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
+		config->ss_status[i] =
+			readl_relaxed(drvdata->base + TRCSSCSRn(i));
+	}
+
 	coresight_disclaim_device_unlocked(drvdata->base);
 
 	CS_LOCK(drvdata->base);
@@ -576,6 +594,7 @@ static void etm4_init_arch_data(void *info)
 	u32 etmidr4;
 	u32 etmidr5;
 	struct etmv4_drvdata *drvdata = info;
+	int i;
 
 	/* Make sure all registers are accessible */
 	etm4_os_unlock(drvdata);
@@ -699,9 +718,14 @@ static void etm4_init_arch_data(void *info)
 	drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
 	/*
 	 * NUMSSCC, bits[23:20] the number of single-shot
-	 * comparator control for tracing
+	 * comparator control for tracing. Read any status regs as these
+	 * also contain RO capability data.
 	 */
 	drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
+	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
+		drvdata->config.ss_status[i] =
+			readl_relaxed(drvdata->base + TRCSSCSRn(i));
+	}
 	/* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 	drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 	/* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 60bc2fb5159b..be8b32ea1654 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -175,6 +175,7 @@
 					 ETM_MODE_EXCL_USER)
 
 #define TRCSTATR_IDLE_BIT		0
+#define TRCSTATR_PMSTABLE_BIT		1
 #define ETM_DEFAULT_ADDR_COMP		0
 
 /* PowerDown Control Register bits */
@@ -226,6 +227,7 @@
  * @cntr_val:	Sets or returns the value for a counter.
  * @res_idx:	Resource index selector.
  * @res_ctrl:	Controls the selection of the resources in the trace unit.
+ * @ss_idx:	Single-shot index selector.
  * @ss_ctrl:	Controls the corresponding single-shot comparator resource.
  * @ss_status:	The status of the corresponding single-shot comparator.
  * @ss_pe_cmp:	Selects the PE comparator inputs for Single-shot control.
@@ -269,6 +271,7 @@ struct etmv4_config {
 	u32				cntr_val[ETMv4_MAX_CNTR];
 	u8				res_idx;
 	u32				res_ctrl[ETM_MAX_RES_SEL];
+	u8				ss_idx;
 	u32				ss_ctrl[ETM_MAX_SS_CMP];
 	u32				ss_status[ETM_MAX_SS_CMP];
 	u32				ss_pe_cmp[ETM_MAX_SS_CMP];
-- 
2.17.1


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Re: [PATCH 7/8] coresight: etm4x: Add missing single-shot control API to sysfs

[Mathieu Poirier]

On Mon, Aug 19, 2019 at 09:57:19PM +0100, Mike Leach wrote:
> An API to control single-shot comparator operation was missing from sysfs.
> This adds the parameters to sysfs to allow programming of this feature.
> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../coresight/coresight-etm4x-sysfs.c         | 122 ++++++++++++++++++
>  drivers/hwtracing/coresight/coresight-etm4x.c |  26 +++-
>  drivers/hwtracing/coresight/coresight-etm4x.h |   3 +
>  3 files changed, 150 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 483976074779..7c019dda1236 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -239,6 +239,7 @@ static ssize_t reset_store(struct device *dev,
>  	for (i = 0; i < drvdata->nr_resource; i++)
>  		config->res_ctrl[i] = 0x0;
>  
> +	config->ss_idx = 0x0;
>  	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
>  		config->ss_ctrl[i] = 0x0;
>  		config->ss_pe_cmp[i] = 0x0;
> @@ -1713,6 +1714,123 @@ static ssize_t res_ctrl_store(struct device *dev,
>  }
>  static DEVICE_ATTR_RW(res_ctrl);
>  
> +static ssize_t sshot_idx_show(struct device *dev,
> +			      struct device_attribute *attr, char *buf)
> +{
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	val = config->ss_idx;
> +	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +
> +static ssize_t sshot_idx_store(struct device *dev,
> +			       struct device_attribute *attr,
> +			       const char *buf, size_t size)
> +{
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	if (kstrtoul(buf, 16, &val))
> +		return -EINVAL;
> +	if (val >= drvdata->nr_ss_cmp)
> +		return -EINVAL;
> +
> +	spin_lock(&drvdata->spinlock);
> +	config->ss_idx = val;
> +	spin_unlock(&drvdata->spinlock);
> +	return size;
> +}
> +static DEVICE_ATTR_RW(sshot_idx);
> +
> +static ssize_t sshot_ctrl_show(struct device *dev,
> +			       struct device_attribute *attr,
> +			       char *buf)
> +{
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	spin_lock(&drvdata->spinlock);
> +	val = config->ss_ctrl[config->ss_idx];
> +	spin_unlock(&drvdata->spinlock);
> +	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +
> +static ssize_t sshot_ctrl_store(struct device *dev,
> +				struct device_attribute *attr,
> +				const char *buf, size_t size)
> +{
> +	u8 idx;
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	if (kstrtoul(buf, 16, &val))
> +		return -EINVAL;
> +
> +	spin_lock(&drvdata->spinlock);
> +	idx = config->ss_idx;
> +	config->ss_ctrl[idx] = val & GENMASK(24, 0);
> +	/* must clear bit 31 in related status register on programming */
> +	config->ss_status[idx] &= ~BIT(31);
> +	spin_unlock(&drvdata->spinlock);
> +	return size;
> +}
> +static DEVICE_ATTR_RW(sshot_ctrl);
> +
> +static ssize_t sshot_status_show(struct device *dev,
> +				 struct device_attribute *attr, char *buf)
> +{
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	spin_lock(&drvdata->spinlock);
> +	val = config->ss_status[config->ss_idx];
> +	spin_unlock(&drvdata->spinlock);
> +	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +static DEVICE_ATTR_RO(sshot_status);
> +
> +static ssize_t sshot_pe_ctrl_show(struct device *dev,
> +				  struct device_attribute *attr,
> +				  char *buf)
> +{
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	spin_lock(&drvdata->spinlock);
> +	val = config->ss_pe_cmp[config->ss_idx];
> +	spin_unlock(&drvdata->spinlock);
> +	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +
> +static ssize_t sshot_pe_ctrl_store(struct device *dev,
> +				   struct device_attribute *attr,
> +				   const char *buf, size_t size)
> +{
> +	u8 idx;
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	if (kstrtoul(buf, 16, &val))
> +		return -EINVAL;
> +
> +	spin_lock(&drvdata->spinlock);
> +	idx = config->ss_idx;
> +	config->ss_ctrl[idx] = val & GENMASK(7, 0);

        config->ss_pe_cmp[idx] = val & GENMASK(7, 0);

> +	/* must clear bit 31 in related status register on programming */
> +	config->ss_status[idx] &= ~BIT(31);
> +	spin_unlock(&drvdata->spinlock);
> +	return size;
> +}
> +static DEVICE_ATTR_RW(sshot_pe_ctrl);
> +
>  static ssize_t ctxid_idx_show(struct device *dev,
>  			      struct device_attribute *attr,
>  			      char *buf)
> @@ -2169,6 +2287,10 @@ static struct attribute *coresight_etmv4_attrs[] = {
>  	&dev_attr_addr_exlevel_s_ns.attr,
>  	&dev_attr_addr_cmp_view.attr,
>  	&dev_attr_vinst_pe_cmp_start_stop.attr,
> +	&dev_attr_sshot_idx.attr,
> +	&dev_attr_sshot_ctrl.attr,
> +	&dev_attr_sshot_pe_ctrl.attr,
> +	&dev_attr_sshot_status.attr,
>  	&dev_attr_seq_idx.attr,
>  	&dev_attr_seq_state.attr,
>  	&dev_attr_seq_event.attr,
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index d8b078d0cc7f..fb7083218410 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -149,6 +149,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
>  			       drvdata->base + TRCRSCTLRn(i));
>  
>  	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> +		/* always clear status bit on restart if using single-shot */
> +		if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> +			config->ss_status[i] &= ~BIT(31);
>  		writel_relaxed(config->ss_ctrl[i],
>  			       drvdata->base + TRCSSCCRn(i));
>  		writel_relaxed(config->ss_status[i],
> @@ -448,6 +451,9 @@ static void etm4_disable_hw(void *info)
>  {
>  	u32 control;
>  	struct etmv4_drvdata *drvdata = info;
> +	struct etmv4_config *config = &drvdata->config;
> +	struct device *etm_dev = &drvdata->csdev->dev;
> +	int i;
>  
>  	CS_UNLOCK(drvdata->base);
>  
> @@ -470,6 +476,18 @@ static void etm4_disable_hw(void *info)
>  	isb();
>  	writel_relaxed(control, drvdata->base + TRCPRGCTLR);
>  
> +	/* wait for TRCSTATR.PMSTABLE to go to '1' */
> +	if (coresight_timeout(drvdata->base, TRCSTATR,
> +			      TRCSTATR_PMSTABLE_BIT, 1))
> +		dev_err(etm_dev,
> +			"timeout while waiting for PM stable Trace Status\n");
> +
> +	/* read the status of the single shot comparators */
> +	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> +		config->ss_status[i] =
> +			readl_relaxed(drvdata->base + TRCSSCSRn(i));
> +	}
> +
>  	coresight_disclaim_device_unlocked(drvdata->base);
>  
>  	CS_LOCK(drvdata->base);
> @@ -576,6 +594,7 @@ static void etm4_init_arch_data(void *info)
>  	u32 etmidr4;
>  	u32 etmidr5;
>  	struct etmv4_drvdata *drvdata = info;
> +	int i;
>  
>  	/* Make sure all registers are accessible */
>  	etm4_os_unlock(drvdata);
> @@ -699,9 +718,14 @@ static void etm4_init_arch_data(void *info)
>  	drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
>  	/*
>  	 * NUMSSCC, bits[23:20] the number of single-shot
> -	 * comparator control for tracing
> +	 * comparator control for tracing. Read any status regs as these
> +	 * also contain RO capability data.
>  	 */
>  	drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
> +	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> +		drvdata->config.ss_status[i] =
> +			readl_relaxed(drvdata->base + TRCSSCSRn(i));
> +	}
>  	/* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
>  	drvdata->numcidc = BMVAL(etmidr4, 24, 27);
>  	/* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 60bc2fb5159b..be8b32ea1654 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -175,6 +175,7 @@
>  					 ETM_MODE_EXCL_USER)
>  
>  #define TRCSTATR_IDLE_BIT		0
> +#define TRCSTATR_PMSTABLE_BIT		1
>  #define ETM_DEFAULT_ADDR_COMP		0
>  
>  /* PowerDown Control Register bits */
> @@ -226,6 +227,7 @@
>   * @cntr_val:	Sets or returns the value for a counter.
>   * @res_idx:	Resource index selector.
>   * @res_ctrl:	Controls the selection of the resources in the trace unit.
> + * @ss_idx:	Single-shot index selector.
>   * @ss_ctrl:	Controls the corresponding single-shot comparator resource.
>   * @ss_status:	The status of the corresponding single-shot comparator.
>   * @ss_pe_cmp:	Selects the PE comparator inputs for Single-shot control.
> @@ -269,6 +271,7 @@ struct etmv4_config {
>  	u32				cntr_val[ETMv4_MAX_CNTR];
>  	u8				res_idx;
>  	u32				res_ctrl[ETM_MAX_RES_SEL];
> +	u8				ss_idx;
>  	u32				ss_ctrl[ETM_MAX_SS_CMP];
>  	u32				ss_status[ETM_MAX_SS_CMP];
>  	u32				ss_pe_cmp[ETM_MAX_SS_CMP];
> -- 
> 2.17.1
> 

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Re: [PATCH 7/8] coresight: etm4x: Add missing single-shot control API to sysfs

[Mike Leach]

Hi,

On Tue, 27 Aug 2019 at 23:27, Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> On Mon, Aug 19, 2019 at 09:57:19PM +0100, Mike Leach wrote:
> > An API to control single-shot comparator operation was missing from sysfs.
> > This adds the parameters to sysfs to allow programming of this feature.
> >
> > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > ---
> >  .../coresight/coresight-etm4x-sysfs.c         | 122 ++++++++++++++++++
> >  drivers/hwtracing/coresight/coresight-etm4x.c |  26 +++-
> >  drivers/hwtracing/coresight/coresight-etm4x.h |   3 +
> >  3 files changed, 150 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index 483976074779..7c019dda1236 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -239,6 +239,7 @@ static ssize_t reset_store(struct device *dev,
> >       for (i = 0; i < drvdata->nr_resource; i++)
> >               config->res_ctrl[i] = 0x0;
> >
> > +     config->ss_idx = 0x0;
> >       for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> >               config->ss_ctrl[i] = 0x0;
> >               config->ss_pe_cmp[i] = 0x0;
> > @@ -1713,6 +1714,123 @@ static ssize_t res_ctrl_store(struct device *dev,
> >  }
> >  static DEVICE_ATTR_RW(res_ctrl);
> >
> > +static ssize_t sshot_idx_show(struct device *dev,
> > +                           struct device_attribute *attr, char *buf)
> > +{
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     val = config->ss_idx;
> > +     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t sshot_idx_store(struct device *dev,
> > +                            struct device_attribute *attr,
> > +                            const char *buf, size_t size)
> > +{
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     if (kstrtoul(buf, 16, &val))
> > +             return -EINVAL;
> > +     if (val >= drvdata->nr_ss_cmp)
> > +             return -EINVAL;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     config->ss_idx = val;
> > +     spin_unlock(&drvdata->spinlock);
> > +     return size;
> > +}
> > +static DEVICE_ATTR_RW(sshot_idx);
> > +
> > +static ssize_t sshot_ctrl_show(struct device *dev,
> > +                            struct device_attribute *attr,
> > +                            char *buf)
> > +{
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     val = config->ss_ctrl[config->ss_idx];
> > +     spin_unlock(&drvdata->spinlock);
> > +     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t sshot_ctrl_store(struct device *dev,
> > +                             struct device_attribute *attr,
> > +                             const char *buf, size_t size)
> > +{
> > +     u8 idx;
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     if (kstrtoul(buf, 16, &val))
> > +             return -EINVAL;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     idx = config->ss_idx;
> > +     config->ss_ctrl[idx] = val & GENMASK(24, 0);
> > +     /* must clear bit 31 in related status register on programming */
> > +     config->ss_status[idx] &= ~BIT(31);
> > +     spin_unlock(&drvdata->spinlock);
> > +     return size;
> > +}
> > +static DEVICE_ATTR_RW(sshot_ctrl);
> > +
> > +static ssize_t sshot_status_show(struct device *dev,
> > +                              struct device_attribute *attr, char *buf)
> > +{
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     val = config->ss_status[config->ss_idx];
> > +     spin_unlock(&drvdata->spinlock);
> > +     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +static DEVICE_ATTR_RO(sshot_status);
> > +
> > +static ssize_t sshot_pe_ctrl_show(struct device *dev,
> > +                               struct device_attribute *attr,
> > +                               char *buf)
> > +{
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     val = config->ss_pe_cmp[config->ss_idx];
> > +     spin_unlock(&drvdata->spinlock);
> > +     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t sshot_pe_ctrl_store(struct device *dev,
> > +                                struct device_attribute *attr,
> > +                                const char *buf, size_t size)
> > +{
> > +     u8 idx;
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     if (kstrtoul(buf, 16, &val))
> > +             return -EINVAL;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     idx = config->ss_idx;
> > +     config->ss_ctrl[idx] = val & GENMASK(7, 0);
>
>         config->ss_pe_cmp[idx] = val & GENMASK(7, 0);
>

Good spot, Thanks

Mike


> > +     /* must clear bit 31 in related status register on programming */
> > +     config->ss_status[idx] &= ~BIT(31);
> > +     spin_unlock(&drvdata->spinlock);
> > +     return size;
> > +}
> > +static DEVICE_ATTR_RW(sshot_pe_ctrl);
> > +
> >  static ssize_t ctxid_idx_show(struct device *dev,
> >                             struct device_attribute *attr,
> >                             char *buf)
> > @@ -2169,6 +2287,10 @@ static struct attribute *coresight_etmv4_attrs[] = {
> >       &dev_attr_addr_exlevel_s_ns.attr,
> >       &dev_attr_addr_cmp_view.attr,
> >       &dev_attr_vinst_pe_cmp_start_stop.attr,
> > +     &dev_attr_sshot_idx.attr,
> > +     &dev_attr_sshot_ctrl.attr,
> > +     &dev_attr_sshot_pe_ctrl.attr,
> > +     &dev_attr_sshot_status.attr,
> >       &dev_attr_seq_idx.attr,
> >       &dev_attr_seq_state.attr,
> >       &dev_attr_seq_event.attr,
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> > index d8b078d0cc7f..fb7083218410 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> > @@ -149,6 +149,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> >                              drvdata->base + TRCRSCTLRn(i));
> >
> >       for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > +             /* always clear status bit on restart if using single-shot */
> > +             if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> > +                     config->ss_status[i] &= ~BIT(31);
> >               writel_relaxed(config->ss_ctrl[i],
> >                              drvdata->base + TRCSSCCRn(i));
> >               writel_relaxed(config->ss_status[i],
> > @@ -448,6 +451,9 @@ static void etm4_disable_hw(void *info)
> >  {
> >       u32 control;
> >       struct etmv4_drvdata *drvdata = info;
> > +     struct etmv4_config *config = &drvdata->config;
> > +     struct device *etm_dev = &drvdata->csdev->dev;
> > +     int i;
> >
> >       CS_UNLOCK(drvdata->base);
> >
> > @@ -470,6 +476,18 @@ static void etm4_disable_hw(void *info)
> >       isb();
> >       writel_relaxed(control, drvdata->base + TRCPRGCTLR);
> >
> > +     /* wait for TRCSTATR.PMSTABLE to go to '1' */
> > +     if (coresight_timeout(drvdata->base, TRCSTATR,
> > +                           TRCSTATR_PMSTABLE_BIT, 1))
> > +             dev_err(etm_dev,
> > +                     "timeout while waiting for PM stable Trace Status\n");
> > +
> > +     /* read the status of the single shot comparators */
> > +     for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > +             config->ss_status[i] =
> > +                     readl_relaxed(drvdata->base + TRCSSCSRn(i));
> > +     }
> > +
> >       coresight_disclaim_device_unlocked(drvdata->base);
> >
> >       CS_LOCK(drvdata->base);
> > @@ -576,6 +594,7 @@ static void etm4_init_arch_data(void *info)
> >       u32 etmidr4;
> >       u32 etmidr5;
> >       struct etmv4_drvdata *drvdata = info;
> > +     int i;
> >
> >       /* Make sure all registers are accessible */
> >       etm4_os_unlock(drvdata);
> > @@ -699,9 +718,14 @@ static void etm4_init_arch_data(void *info)
> >       drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
> >       /*
> >        * NUMSSCC, bits[23:20] the number of single-shot
> > -      * comparator control for tracing
> > +      * comparator control for tracing. Read any status regs as these
> > +      * also contain RO capability data.
> >        */
> >       drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
> > +     for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > +             drvdata->config.ss_status[i] =
> > +                     readl_relaxed(drvdata->base + TRCSSCSRn(i));
> > +     }
> >       /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
> >       drvdata->numcidc = BMVAL(etmidr4, 24, 27);
> >       /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > index 60bc2fb5159b..be8b32ea1654 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > @@ -175,6 +175,7 @@
> >                                        ETM_MODE_EXCL_USER)
> >
> >  #define TRCSTATR_IDLE_BIT            0
> > +#define TRCSTATR_PMSTABLE_BIT                1
> >  #define ETM_DEFAULT_ADDR_COMP                0
> >
> >  /* PowerDown Control Register bits */
> > @@ -226,6 +227,7 @@
> >   * @cntr_val:        Sets or returns the value for a counter.
> >   * @res_idx: Resource index selector.
> >   * @res_ctrl:        Controls the selection of the resources in the trace unit.
> > + * @ss_idx:  Single-shot index selector.
> >   * @ss_ctrl: Controls the corresponding single-shot comparator resource.
> >   * @ss_status:       The status of the corresponding single-shot comparator.
> >   * @ss_pe_cmp:       Selects the PE comparator inputs for Single-shot control.
> > @@ -269,6 +271,7 @@ struct etmv4_config {
> >       u32                             cntr_val[ETMv4_MAX_CNTR];
> >       u8                              res_idx;
> >       u32                             res_ctrl[ETM_MAX_RES_SEL];
> > +     u8                              ss_idx;
> >       u32                             ss_ctrl[ETM_MAX_SS_CMP];
> >       u32                             ss_status[ETM_MAX_SS_CMP];
> >       u32                             ss_pe_cmp[ETM_MAX_SS_CMP];
> > --
> > 2.17.1
> >



--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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Re: [PATCH 7/8] coresight: etm4x: Add missing single-shot control API to sysfs

[Leo Yan]

On Mon, Aug 19, 2019 at 09:57:19PM +0100, Mike Leach wrote:
> An API to control single-shot comparator operation was missing from sysfs.
> This adds the parameters to sysfs to allow programming of this feature.
> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../coresight/coresight-etm4x-sysfs.c         | 122 ++++++++++++++++++
>  drivers/hwtracing/coresight/coresight-etm4x.c |  26 +++-
>  drivers/hwtracing/coresight/coresight-etm4x.h |   3 +
>  3 files changed, 150 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 483976074779..7c019dda1236 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -239,6 +239,7 @@ static ssize_t reset_store(struct device *dev,
>  	for (i = 0; i < drvdata->nr_resource; i++)
>  		config->res_ctrl[i] = 0x0;
>  
> +	config->ss_idx = 0x0;
>  	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
>  		config->ss_ctrl[i] = 0x0;
>  		config->ss_pe_cmp[i] = 0x0;
> @@ -1713,6 +1714,123 @@ static ssize_t res_ctrl_store(struct device *dev,
>  }
>  static DEVICE_ATTR_RW(res_ctrl);
>  
> +static ssize_t sshot_idx_show(struct device *dev,
> +			      struct device_attribute *attr, char *buf)
> +{
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	val = config->ss_idx;
> +	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +
> +static ssize_t sshot_idx_store(struct device *dev,
> +			       struct device_attribute *attr,
> +			       const char *buf, size_t size)
> +{
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	if (kstrtoul(buf, 16, &val))
> +		return -EINVAL;
> +	if (val >= drvdata->nr_ss_cmp)
> +		return -EINVAL;
> +
> +	spin_lock(&drvdata->spinlock);
> +	config->ss_idx = val;
> +	spin_unlock(&drvdata->spinlock);
> +	return size;
> +}
> +static DEVICE_ATTR_RW(sshot_idx);
> +
> +static ssize_t sshot_ctrl_show(struct device *dev,
> +			       struct device_attribute *attr,
> +			       char *buf)
> +{
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	spin_lock(&drvdata->spinlock);
> +	val = config->ss_ctrl[config->ss_idx];
> +	spin_unlock(&drvdata->spinlock);
> +	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +
> +static ssize_t sshot_ctrl_store(struct device *dev,
> +				struct device_attribute *attr,
> +				const char *buf, size_t size)
> +{
> +	u8 idx;
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	if (kstrtoul(buf, 16, &val))
> +		return -EINVAL;
> +
> +	spin_lock(&drvdata->spinlock);
> +	idx = config->ss_idx;
> +	config->ss_ctrl[idx] = val & GENMASK(24, 0);
> +	/* must clear bit 31 in related status register on programming */
> +	config->ss_status[idx] &= ~BIT(31);

Since function etm4_enable_hw() will clear ss_status's bit 31 when
program TRCSSCSRn, so is here redundant to clear bit 31?

> +	spin_unlock(&drvdata->spinlock);
> +	return size;
> +}
> +static DEVICE_ATTR_RW(sshot_ctrl);
> +
> +static ssize_t sshot_status_show(struct device *dev,
> +				 struct device_attribute *attr, char *buf)
> +{
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	spin_lock(&drvdata->spinlock);
> +	val = config->ss_status[config->ss_idx];
> +	spin_unlock(&drvdata->spinlock);
> +	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +static DEVICE_ATTR_RO(sshot_status);
> +
> +static ssize_t sshot_pe_ctrl_show(struct device *dev,
> +				  struct device_attribute *attr,
> +				  char *buf)
> +{
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	spin_lock(&drvdata->spinlock);
> +	val = config->ss_pe_cmp[config->ss_idx];
> +	spin_unlock(&drvdata->spinlock);
> +	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +
> +static ssize_t sshot_pe_ctrl_store(struct device *dev,
> +				   struct device_attribute *attr,
> +				   const char *buf, size_t size)
> +{
> +	u8 idx;
> +	unsigned long val;
> +	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	struct etmv4_config *config = &drvdata->config;
> +
> +	if (kstrtoul(buf, 16, &val))
> +		return -EINVAL;
> +
> +	spin_lock(&drvdata->spinlock);
> +	idx = config->ss_idx;
> +	config->ss_ctrl[idx] = val & GENMASK(7, 0);
> +	/* must clear bit 31 in related status register on programming */
> +	config->ss_status[idx] &= ~BIT(31);

Same question for if it's redundant to clear bit 31?

Thanks,
Leo Yan

> +	spin_unlock(&drvdata->spinlock);
> +	return size;
> +}
> +static DEVICE_ATTR_RW(sshot_pe_ctrl);
> +
>  static ssize_t ctxid_idx_show(struct device *dev,
>  			      struct device_attribute *attr,
>  			      char *buf)
> @@ -2169,6 +2287,10 @@ static struct attribute *coresight_etmv4_attrs[] = {
>  	&dev_attr_addr_exlevel_s_ns.attr,
>  	&dev_attr_addr_cmp_view.attr,
>  	&dev_attr_vinst_pe_cmp_start_stop.attr,
> +	&dev_attr_sshot_idx.attr,
> +	&dev_attr_sshot_ctrl.attr,
> +	&dev_attr_sshot_pe_ctrl.attr,
> +	&dev_attr_sshot_status.attr,
>  	&dev_attr_seq_idx.attr,
>  	&dev_attr_seq_state.attr,
>  	&dev_attr_seq_event.attr,
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index d8b078d0cc7f..fb7083218410 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -149,6 +149,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
>  			       drvdata->base + TRCRSCTLRn(i));
>  
>  	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> +		/* always clear status bit on restart if using single-shot */
> +		if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> +			config->ss_status[i] &= ~BIT(31);
>  		writel_relaxed(config->ss_ctrl[i],
>  			       drvdata->base + TRCSSCCRn(i));
>  		writel_relaxed(config->ss_status[i],
> @@ -448,6 +451,9 @@ static void etm4_disable_hw(void *info)
>  {
>  	u32 control;
>  	struct etmv4_drvdata *drvdata = info;
> +	struct etmv4_config *config = &drvdata->config;
> +	struct device *etm_dev = &drvdata->csdev->dev;
> +	int i;
>  
>  	CS_UNLOCK(drvdata->base);
>  
> @@ -470,6 +476,18 @@ static void etm4_disable_hw(void *info)
>  	isb();
>  	writel_relaxed(control, drvdata->base + TRCPRGCTLR);
>  
> +	/* wait for TRCSTATR.PMSTABLE to go to '1' */
> +	if (coresight_timeout(drvdata->base, TRCSTATR,
> +			      TRCSTATR_PMSTABLE_BIT, 1))
> +		dev_err(etm_dev,
> +			"timeout while waiting for PM stable Trace Status\n");
> +
> +	/* read the status of the single shot comparators */
> +	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> +		config->ss_status[i] =
> +			readl_relaxed(drvdata->base + TRCSSCSRn(i));
> +	}
> +
>  	coresight_disclaim_device_unlocked(drvdata->base);
>  
>  	CS_LOCK(drvdata->base);
> @@ -576,6 +594,7 @@ static void etm4_init_arch_data(void *info)
>  	u32 etmidr4;
>  	u32 etmidr5;
>  	struct etmv4_drvdata *drvdata = info;
> +	int i;
>  
>  	/* Make sure all registers are accessible */
>  	etm4_os_unlock(drvdata);
> @@ -699,9 +718,14 @@ static void etm4_init_arch_data(void *info)
>  	drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
>  	/*
>  	 * NUMSSCC, bits[23:20] the number of single-shot
> -	 * comparator control for tracing
> +	 * comparator control for tracing. Read any status regs as these
> +	 * also contain RO capability data.
>  	 */
>  	drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
> +	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> +		drvdata->config.ss_status[i] =
> +			readl_relaxed(drvdata->base + TRCSSCSRn(i));
> +	}
>  	/* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
>  	drvdata->numcidc = BMVAL(etmidr4, 24, 27);
>  	/* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 60bc2fb5159b..be8b32ea1654 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -175,6 +175,7 @@
>  					 ETM_MODE_EXCL_USER)
>  
>  #define TRCSTATR_IDLE_BIT		0
> +#define TRCSTATR_PMSTABLE_BIT		1
>  #define ETM_DEFAULT_ADDR_COMP		0
>  
>  /* PowerDown Control Register bits */
> @@ -226,6 +227,7 @@
>   * @cntr_val:	Sets or returns the value for a counter.
>   * @res_idx:	Resource index selector.
>   * @res_ctrl:	Controls the selection of the resources in the trace unit.
> + * @ss_idx:	Single-shot index selector.
>   * @ss_ctrl:	Controls the corresponding single-shot comparator resource.
>   * @ss_status:	The status of the corresponding single-shot comparator.
>   * @ss_pe_cmp:	Selects the PE comparator inputs for Single-shot control.
> @@ -269,6 +271,7 @@ struct etmv4_config {
>  	u32				cntr_val[ETMv4_MAX_CNTR];
>  	u8				res_idx;
>  	u32				res_ctrl[ETM_MAX_RES_SEL];
> +	u8				ss_idx;
>  	u32				ss_ctrl[ETM_MAX_SS_CMP];
>  	u32				ss_status[ETM_MAX_SS_CMP];
>  	u32				ss_pe_cmp[ETM_MAX_SS_CMP];
> -- 
> 2.17.1
> 
> _______________________________________________
> CoreSight mailing list
> CoreSight@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/coresight

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Re: [PATCH 7/8] coresight: etm4x: Add missing single-shot control API to sysfs

[Mike Leach]

HI Leo,

On Wed, 28 Aug 2019 at 06:18, Leo Yan <leo.yan@linaro.org> wrote:
>
> On Mon, Aug 19, 2019 at 09:57:19PM +0100, Mike Leach wrote:
> > An API to control single-shot comparator operation was missing from sysfs.
> > This adds the parameters to sysfs to allow programming of this feature.
> >
> > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > ---
> >  .../coresight/coresight-etm4x-sysfs.c         | 122 ++++++++++++++++++
> >  drivers/hwtracing/coresight/coresight-etm4x.c |  26 +++-
> >  drivers/hwtracing/coresight/coresight-etm4x.h |   3 +
> >  3 files changed, 150 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index 483976074779..7c019dda1236 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -239,6 +239,7 @@ static ssize_t reset_store(struct device *dev,
> >       for (i = 0; i < drvdata->nr_resource; i++)
> >               config->res_ctrl[i] = 0x0;
> >
> > +     config->ss_idx = 0x0;
> >       for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> >               config->ss_ctrl[i] = 0x0;
> >               config->ss_pe_cmp[i] = 0x0;
> > @@ -1713,6 +1714,123 @@ static ssize_t res_ctrl_store(struct device *dev,
> >  }
> >  static DEVICE_ATTR_RW(res_ctrl);
> >
> > +static ssize_t sshot_idx_show(struct device *dev,
> > +                           struct device_attribute *attr, char *buf)
> > +{
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     val = config->ss_idx;
> > +     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t sshot_idx_store(struct device *dev,
> > +                            struct device_attribute *attr,
> > +                            const char *buf, size_t size)
> > +{
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     if (kstrtoul(buf, 16, &val))
> > +             return -EINVAL;
> > +     if (val >= drvdata->nr_ss_cmp)
> > +             return -EINVAL;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     config->ss_idx = val;
> > +     spin_unlock(&drvdata->spinlock);
> > +     return size;
> > +}
> > +static DEVICE_ATTR_RW(sshot_idx);
> > +
> > +static ssize_t sshot_ctrl_show(struct device *dev,
> > +                            struct device_attribute *attr,
> > +                            char *buf)
> > +{
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     val = config->ss_ctrl[config->ss_idx];
> > +     spin_unlock(&drvdata->spinlock);
> > +     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t sshot_ctrl_store(struct device *dev,
> > +                             struct device_attribute *attr,
> > +                             const char *buf, size_t size)
> > +{
> > +     u8 idx;
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     if (kstrtoul(buf, 16, &val))
> > +             return -EINVAL;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     idx = config->ss_idx;
> > +     config->ss_ctrl[idx] = val & GENMASK(24, 0);
> > +     /* must clear bit 31 in related status register on programming */
> > +     config->ss_status[idx] &= ~BIT(31);
>
> Since function etm4_enable_hw() will clear ss_status's bit 31 when
> program TRCSSCSRn, so is here redundant to clear bit 31?
>
> > +     spin_unlock(&drvdata->spinlock);
> > +     return size;
> > +}
> > +static DEVICE_ATTR_RW(sshot_ctrl);
> > +
> > +static ssize_t sshot_status_show(struct device *dev,
> > +                              struct device_attribute *attr, char *buf)
> > +{
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     val = config->ss_status[config->ss_idx];
> > +     spin_unlock(&drvdata->spinlock);
> > +     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +static DEVICE_ATTR_RO(sshot_status);
> > +
> > +static ssize_t sshot_pe_ctrl_show(struct device *dev,
> > +                               struct device_attribute *attr,
> > +                               char *buf)
> > +{
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     val = config->ss_pe_cmp[config->ss_idx];
> > +     spin_unlock(&drvdata->spinlock);
> > +     return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t sshot_pe_ctrl_store(struct device *dev,
> > +                                struct device_attribute *attr,
> > +                                const char *buf, size_t size)
> > +{
> > +     u8 idx;
> > +     unsigned long val;
> > +     struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +     struct etmv4_config *config = &drvdata->config;
> > +
> > +     if (kstrtoul(buf, 16, &val))
> > +             return -EINVAL;
> > +
> > +     spin_lock(&drvdata->spinlock);
> > +     idx = config->ss_idx;
> > +     config->ss_ctrl[idx] = val & GENMASK(7, 0);
> > +     /* must clear bit 31 in related status register on programming */
> > +     config->ss_status[idx] &= ~BIT(31);
>
> Same question for if it's redundant to clear bit 31?
>
> Thanks,
> Leo Yan
>

The sysfs representation is not the current state of these registers,
but the values that will be programmed on enabling the hardware. We do
not write anything to hardware immediately.
So from a sysfs perspective, the bit clear is reflected in the status
register here to recognise that it will be programmed as cleared.

Should the same registers be set from a different path - e.g. perf,
then the status will automatically be cleared each time the hw is
enabled.

Regards

Mike




> > +     spin_unlock(&drvdata->spinlock);
> > +     return size;
> > +}
> > +static DEVICE_ATTR_RW(sshot_pe_ctrl);
> > +
> >  static ssize_t ctxid_idx_show(struct device *dev,
> >                             struct device_attribute *attr,
> >                             char *buf)
> > @@ -2169,6 +2287,10 @@ static struct attribute *coresight_etmv4_attrs[] = {
> >       &dev_attr_addr_exlevel_s_ns.attr,
> >       &dev_attr_addr_cmp_view.attr,
> >       &dev_attr_vinst_pe_cmp_start_stop.attr,
> > +     &dev_attr_sshot_idx.attr,
> > +     &dev_attr_sshot_ctrl.attr,
> > +     &dev_attr_sshot_pe_ctrl.attr,
> > +     &dev_attr_sshot_status.attr,
> >       &dev_attr_seq_idx.attr,
> >       &dev_attr_seq_state.attr,
> >       &dev_attr_seq_event.attr,
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> > index d8b078d0cc7f..fb7083218410 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> > @@ -149,6 +149,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> >                              drvdata->base + TRCRSCTLRn(i));
> >
> >       for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > +             /* always clear status bit on restart if using single-shot */
> > +             if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> > +                     config->ss_status[i] &= ~BIT(31);
> >               writel_relaxed(config->ss_ctrl[i],
> >                              drvdata->base + TRCSSCCRn(i));
> >               writel_relaxed(config->ss_status[i],
> > @@ -448,6 +451,9 @@ static void etm4_disable_hw(void *info)
> >  {
> >       u32 control;
> >       struct etmv4_drvdata *drvdata = info;
> > +     struct etmv4_config *config = &drvdata->config;
> > +     struct device *etm_dev = &drvdata->csdev->dev;
> > +     int i;
> >
> >       CS_UNLOCK(drvdata->base);
> >
> > @@ -470,6 +476,18 @@ static void etm4_disable_hw(void *info)
> >       isb();
> >       writel_relaxed(control, drvdata->base + TRCPRGCTLR);
> >
> > +     /* wait for TRCSTATR.PMSTABLE to go to '1' */
> > +     if (coresight_timeout(drvdata->base, TRCSTATR,
> > +                           TRCSTATR_PMSTABLE_BIT, 1))
> > +             dev_err(etm_dev,
> > +                     "timeout while waiting for PM stable Trace Status\n");
> > +
> > +     /* read the status of the single shot comparators */
> > +     for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > +             config->ss_status[i] =
> > +                     readl_relaxed(drvdata->base + TRCSSCSRn(i));
> > +     }
> > +
> >       coresight_disclaim_device_unlocked(drvdata->base);
> >
> >       CS_LOCK(drvdata->base);
> > @@ -576,6 +594,7 @@ static void etm4_init_arch_data(void *info)
> >       u32 etmidr4;
> >       u32 etmidr5;
> >       struct etmv4_drvdata *drvdata = info;
> > +     int i;
> >
> >       /* Make sure all registers are accessible */
> >       etm4_os_unlock(drvdata);
> > @@ -699,9 +718,14 @@ static void etm4_init_arch_data(void *info)
> >       drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
> >       /*
> >        * NUMSSCC, bits[23:20] the number of single-shot
> > -      * comparator control for tracing
> > +      * comparator control for tracing. Read any status regs as these
> > +      * also contain RO capability data.
> >        */
> >       drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
> > +     for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > +             drvdata->config.ss_status[i] =
> > +                     readl_relaxed(drvdata->base + TRCSSCSRn(i));
> > +     }
> >       /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
> >       drvdata->numcidc = BMVAL(etmidr4, 24, 27);
> >       /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > index 60bc2fb5159b..be8b32ea1654 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > @@ -175,6 +175,7 @@
> >                                        ETM_MODE_EXCL_USER)
> >
> >  #define TRCSTATR_IDLE_BIT            0
> > +#define TRCSTATR_PMSTABLE_BIT                1
> >  #define ETM_DEFAULT_ADDR_COMP                0
> >
> >  /* PowerDown Control Register bits */
> > @@ -226,6 +227,7 @@
> >   * @cntr_val:        Sets or returns the value for a counter.
> >   * @res_idx: Resource index selector.
> >   * @res_ctrl:        Controls the selection of the resources in the trace unit.
> > + * @ss_idx:  Single-shot index selector.
> >   * @ss_ctrl: Controls the corresponding single-shot comparator resource.
> >   * @ss_status:       The status of the corresponding single-shot comparator.
> >   * @ss_pe_cmp:       Selects the PE comparator inputs for Single-shot control.
> > @@ -269,6 +271,7 @@ struct etmv4_config {
> >       u32                             cntr_val[ETMv4_MAX_CNTR];
> >       u8                              res_idx;
> >       u32                             res_ctrl[ETM_MAX_RES_SEL];
> > +     u8                              ss_idx;
> >       u32                             ss_ctrl[ETM_MAX_SS_CMP];
> >       u32                             ss_status[ETM_MAX_SS_CMP];
> >       u32                             ss_pe_cmp[ETM_MAX_SS_CMP];
> > --
> > 2.17.1
> >
> > _______________________________________________
> > CoreSight mailing list
> > CoreSight@lists.linaro.org
> > https://lists.linaro.org/mailman/listinfo/coresight



-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 8/8] coresight: etm4x: docs: Additional documentation for ETM4x.

[Mike Leach]

Update existing docs for new sysfs API features.
Add new ETMv4 reference document for sysfs programming.
Move coresight documentation to common directory.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
---
 .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++---
 .../{ => coresight}/coresight-cpu-debug.txt   |   0
 .../coresight/coresight-etm4x-reference.txt   | 459 ++++++++++++++++++
 .../trace/{ => coresight}/coresight.txt       |   0
 MAINTAINERS                                   |   3 +-
 5 files changed, 575 insertions(+), 70 deletions(-)
 rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%)
 create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt
 rename Documentation/trace/{ => coresight}/coresight.txt (100%)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
index 36258bc1b473..112c50ae9986 100644
--- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
@@ -1,4 +1,4 @@
-What:		/sys/bus/coresight/devices/<memory_map>.etm/enable_source
+What:		/sys/bus/coresight/devices/etm<N>/enable_source
 Date:		April 2015
 KernelVersion:  4.01
 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
@@ -8,82 +8,82 @@ Description:	(RW) Enable/disable tracing on this specific trace entiry.
 		of coresight components linking the source to the sink is
 		configured and managed automatically by the coresight framework.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/cpu
+What:		/sys/bus/coresight/devices/etm<N>/cpu
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) The CPU this tracing entity is associated with.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
+What:		/sys/bus/coresight/devices/etm<N>/nr_pe_cmp
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Indicates the number of PE comparator inputs that are
 		available for tracing.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
+What:		/sys/bus/coresight/devices/etm<N>/nr_addr_cmp
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Indicates the number of address comparator pairs that are
 		available for tracing.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
+What:		/sys/bus/coresight/devices/etm<N>/nr_cntr
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Indicates the number of counters that are available for
 		tracing.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
+What:		/sys/bus/coresight/devices/etm<N>/nr_ext_inp
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Indicates how many external inputs are implemented.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/numcidc
+What:		/sys/bus/coresight/devices/etm<N>/numcidc
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Indicates the number of Context ID comparators that are
 		available for tracing.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/numvmidc
+What:		/sys/bus/coresight/devices/etm<N>/numvmidc
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Indicates the number of VMID comparators that are available
 		for tracing.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
+What:		/sys/bus/coresight/devices/etm<N>/nrseqstate
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Indicates the number of sequencer states that are
 		implemented.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_resource
+What:		/sys/bus/coresight/devices/etm<N>/nr_resource
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Indicates the number of resource selection pairs that are
 		available for tracing.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
+What:		/sys/bus/coresight/devices/etm<N>/nr_ss_cmp
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Indicates the number of single-shot comparator controls that
 		are available for tracing.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/reset
+What:		/sys/bus/coresight/devices/etm<N>/reset
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(W) Cancels all configuration on a trace unit and set it back
 		to its boot configuration.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mode
+What:		/sys/bus/coresight/devices/etm<N>/mode
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
@@ -91,302 +91,349 @@ Description: 	(RW) Controls various modes supported by this ETM, for example
 		P0 instruction tracing, branch broadcast, cycle counting and
 		context ID tracing.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/pe
+What:		/sys/bus/coresight/devices/etm<N>/pe
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Controls which PE to trace.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/event
+What:		/sys/bus/coresight/devices/etm<N>/event
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Controls the tracing of arbitrary events from bank 0 to 3.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/event_instren
+What:		/sys/bus/coresight/devices/etm<N>/event_instren
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Controls the behavior of the events in bank 0 to 3.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/event_ts
+What:		/sys/bus/coresight/devices/etm<N>/event_ts
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Controls the insertion of global timestamps in the trace
 		streams.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/syncfreq
+What:		/sys/bus/coresight/devices/etm<N>/syncfreq
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Controls how often trace synchronization requests occur.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
+What:		/sys/bus/coresight/devices/etm<N>/cyc_threshold
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Sets the threshold value for cycle counting.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
+What:		/sys/bus/coresight/devices/etm<N>/bb_ctrl
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Controls which regions in the memory map are enabled to
 		use branch broadcasting.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/event_vinst
+What:		/sys/bus/coresight/devices/etm<N>/event_vinst
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Controls instruction trace filtering.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst
+What:		/sys/bus/coresight/devices/etm<N>/s_exlevel_vinst
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) In Secure state, each bit controls whether instruction
 		tracing is enabled for the corresponding exception level.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst
+What:		/sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) In non-secure state, each bit controls whether instruction
 		tracing is enabled for the corresponding exception level.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_idx
+What:		/sys/bus/coresight/devices/etm<N>/addr_idx
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Select which address comparator or pair (of comparators) to
 		work with.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype
+What:		/sys/bus/coresight/devices/etm<N>/addr_instdatatype
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Controls what type of comparison the trace unit performs.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_single
+What:		/sys/bus/coresight/devices/etm<N>/addr_single
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Used to setup single address comparator values.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_range
+What:		/sys/bus/coresight/devices/etm<N>/addr_range
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Used to setup address range comparator values.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_idx
+What:		/sys/bus/coresight/devices/etm<N>/seq_idx
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Select which sequensor.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_state
+What:		/sys/bus/coresight/devices/etm<N>/seq_state
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Use this to set, or read, the sequencer state.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_event
+What:		/sys/bus/coresight/devices/etm<N>/seq_event
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Moves the sequencer state to a specific state.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event
+What:		/sys/bus/coresight/devices/etm<N>/seq_reset_event
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Moves the sequencer to state 0 when a programmed event
 		occurs.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_idx
+What:		/sys/bus/coresight/devices/etm<N>/cntr_idx
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Select which counter unit to work with.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/cntrldvr
+What:		/sys/bus/coresight/devices/etm<N>/cntrldvr
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) This sets or returns the reload count value of the
 		specific counter.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_val
+What:		/sys/bus/coresight/devices/etm<N>/cntr_val
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) This sets or returns the current count value of the
                 specific counter.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl
+What:		/sys/bus/coresight/devices/etm<N>/cntr_ctrl
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Controls the operation of the selected counter.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/res_idx
+What:		/sys/bus/coresight/devices/etm<N>/res_idx
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Select which resource selection unit to work with.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/res_ctrl
+What:		/sys/bus/coresight/devices/etm<N>/res_ctrl
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description: 	(RW) Controls the selection of the resources in the trace unit.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx
+What:		/sys/bus/coresight/devices/etm<N>/ctxid_idx
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(RW) Select which context ID comparator to work with.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid
+What:		/sys/bus/coresight/devices/etm<N>/ctxid_pid
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(RW) Get/Set the context ID comparator value to trigger on.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks
+What:		/sys/bus/coresight/devices/etm<N>/ctxid_masks
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(RW) Mask for all 8 context ID comparator value
 		registers (if implemented).
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_idx
+What:		/sys/bus/coresight/devices/etm<N>/vmid_idx
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(RW) Select which virtual machine ID comparator to work with.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_val
+What:		/sys/bus/coresight/devices/etm<N>/vmid_val
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(RW) Get/Set the virtual machine ID comparator value to
 		trigger on.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_masks
+What:		/sys/bus/coresight/devices/etm<N>/vmid_masks
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(RW) Mask for all 8 virtual machine ID comparator value
 		registers (if implemented).
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr
+What:		/sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns
+Date:		August 2019
+KernelVersion:	5.4
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:	(RW) Set the Exception Level matching bits for secure and
+		non-secure exception levels.
+
+What:		/sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop
+Date:		August 2019
+KernelVersion:	5.4
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:	(RW) Access the start stop control register for PE input
+		comparators.
+
+What:		/sys/bus/coresight/devices/etm<N>/addr_cmp_view
+Date:		August 2019
+KernelVersion:	5.4
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:	(R) Print the current settings for the selected address
+		comparator.
+
+What:		/sys/bus/coresight/devices/etm<N>/sshot_idx
+Date:		August 2019
+KernelVersion:	5.4
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:	(RW) Select the single shot control register to access.
+
+What:		/sys/bus/coresight/devices/etm<N>/sshot_ctrl
+Date:		August 2019
+KernelVersion:	5.4
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:	(RW) Access the selected single shot control register.
+
+What:		/sys/bus/coresight/devices/etm<N>/sshot_status
+Date:		August 2019
+KernelVersion:	5.4
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:	(R) Print the current value of the selected single shot
+		status register.
+
+What:		/sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl
+Date:		August 2019
+KernelVersion:	5.4
+Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:	(RW) Access the selected single show PE comparator control
+		register.
+
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the OS Lock Status Register (0x304).
 		The value it taken directly  from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the Power Down Control Register
 		(0x310).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the Power Down Status Register
 		(0x314).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trclsr
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the SW Lock Status Register
 		(0xFB4).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the Authentication Status Register
 		(0xFB8).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevid
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the Device ID Register
 		(0xFC8).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the Device Type Register
 		(0xFCC).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the Peripheral ID0 Register
 		(0xFE0).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the Peripheral ID1 Register
 		(0xFE4).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the Peripheral ID2 Register
 		(0xFE8).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the Peripheral ID3 Register
 		(0xFEC).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcconfig
 Date:		February 2016
 KernelVersion:	4.07
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the trace configuration register
 		(0x010) as currently set by SW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid
+What:		/sys/bus/coresight/devices/etm<N>/mgmt/trctraceid
 Date:		February 2016
 KernelVersion:	4.07
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Print the content of the trace ID register (0x040).
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr0
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Returns the tracing capabilities of the trace unit (0x1E0).
 		The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr1
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Returns the tracing capabilities of the trace unit (0x1E4).
 		The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr2
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
@@ -394,7 +441,7 @@ Description:	(R) Returns the maximum size of the data value, data address,
 		VMID, context ID and instuction address in the trace unit
 		(0x1E8).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr3
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
@@ -403,42 +450,42 @@ Description:	(R) Returns the value associated with various resources
 		architecture specification for more details (0x1E8).
 		The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr4
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Returns how many resources the trace unit supports (0x1F0).
 		The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr5
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Returns how many resources the trace unit supports (0x1F4).
 		The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr8
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Returns the maximum speculation depth of the instruction
 		trace stream. (0x180).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr9
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Returns the number of P0 right-hand keys that the trace unit
 		can use (0x184).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr10
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:	(R) Returns the number of P1 right-hand keys that the trace unit
 		can use (0x188).  The value is taken directly from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr11
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
@@ -446,7 +493,7 @@ Description:	(R) Returns the number of special P1 right-hand keys that the
 		trace unit can use (0x18C).  The value is taken directly from
 		the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr12
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
@@ -454,7 +501,7 @@ Description:	(R) Returns the number of conditional P1 right-hand keys that
 		the trace unit can use (0x190).  The value is taken directly
 		from the HW.
 
-What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13
+What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr13
 Date:		April 2015
 KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight/coresight-cpu-debug.txt
similarity index 100%
rename from Documentation/trace/coresight-cpu-debug.txt
rename to Documentation/trace/coresight/coresight-cpu-debug.txt
diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.txt b/Documentation/trace/coresight/coresight-etm4x-reference.txt
new file mode 100644
index 000000000000..72e81bbbef43
--- /dev/null
+++ b/Documentation/trace/coresight/coresight-etm4x-reference.txt
@@ -0,0 +1,459 @@
+ETMv4 sysfs linux driver programming reference - v2.
+====================================================
+
+Supplement to existing ETMv4 driver documentation.
+
+Sysfs files and directories
+---------------------------
+
+Root: /sys/bus/coresight/devices/etm<N>
+
+
+The following paragraphs explain the association between sysfs files and the
+ETMv4 registers that they effect. Note the register names are given without
+the ‘TRC’ prefix.
+
+File		: mode (rw)
+Trace Registers	: {CONFIGR + others}
+Notes 		: Bit select trace features. See ‘mode’ section below. Bits
+		in this will cause equivalent programming of trace config and
+		other registers to enable the features requested.
+Syntax & eg	: 'echo bitfield > mode'
+       	 	bitfield up to 32 bits setting trace features.
+Example		: $> echo 0x > mode
+
+File		: reset (wo)
+Trace Registers	: All
+Notes 		: Reset all programming to trace nothing / no logic programmed.
+Syntax		: 'echo 1 > reset'
+
+File		: enable_source (wo)
+Trace Registers	: PRGCTLR, All hardware regs.
+Notes 		:  >0: Programs up the hardware with the current values held in
+		the driver and enables trace.
+		0: disable trace hardware.
+Syntax		: 'echo 1 > enable_source'
+
+File		: cpu (ro)
+Trace Registers	: None.
+Notes 		: CPU ID that this ETM is attached to.
+Example		:$> cat cpu
+		$> 0
+
+File		: addr_idx (rw)
+Trace Registers	: None.
+Notes 		: Virtual register to index address comparator and range
+		features. Set index for first of the pair in a range.
+Syntax		: 'echo idx > addr_idx'
+		Where idx <  nr_addr_cmp x 2
+
+File		: addr_range (rw)
+Trace Registers	: ACVR[idx, idx+1], VIIECTLR
+Notes 		: Pair of addresses for a range selected by addr_idx. Include
+		/ exclude according to the optional parameter, or if omitted
+		uses the current ‘mode’ setting. Select comparator range in
+		control register. Error if index is odd value.
+Depends		: mode, addr_idx
+Syntax		: 'echo addr1 addr2 [exclude] > addr_range'
+		Where addr1 and addr2 define the range and addr1 < addr2.
+		Optional exclude value - 0 for include, 1 for exclude.
+Example		: $> echo 0x0000 0x2000 0 > addr_range
+
+File		: addr_single (rw)
+Trace Registers	: ACVR[idx]
+Notes 		: Set a single address comparator according to addr_idx. This
+		is used if the address comparator is used as part of event
+		generation logic etc.
+Depends		: addr_idx
+Syntax		: 'echo addr1 > addr_single'
+
+File		: addr_start (rw)
+Trace Registers	: ACVR[idx], VISSCTLR
+Notes 		: Set a trace start address comparator according to addr_idx.
+		Select comparator in control register.
+Depends		: addr_idx
+Syntax		: 'echo addr1 > addr_start'
+
+File		: addr_stop (rw)
+Trace Registers	: ACVR[idx], VISSCTLR
+Notes 		: Set a trace stop address comparator according to addr_idx.
+		Select comparator in control register.
+Depends		: addr_idx
+Syntax		: 'echo addr1 > addr_stop'
+
+File		: addr_context (rw)
+Trace Registers	: ACATR[idx,{6:4}]
+Notes 		: Link context ID comparator to address comparator addr_idx
+Depends		: addr_idx.
+Syntax		: 'echo ctxt_idx > addr_context'
+		Where ctxt_idx is the index of the linked context id / vmid
+		comparator.
+
+File		: addr_ctxtype (rw)
+Trace Registers	: ACATR[idx,{3:2}]
+Notes 		: Input value string. Set type for linked context ID comparator
+Depends		: addr_idx
+Syntax		: 'echo type > addr_ctxtype'
+		Type one of {all, vmid, ctxid, none}
+Example		: $> echo ctxid > addr_ctxtype
+
+File		: addr_exlevel_s_ns (rw)
+Trace Registers	: ACATR[idx,{14:8}]
+Notes 		: Set the ELx secure and non-secure  matching bits for the
+		selected address comparator
+Depends		: addr_idx
+Syntax		: 'echo val > addr_exlevel_s_ns'
+		val is a 7 bit value for exception levels to exclude. Input
+		value shifted to correct bits in register.
+Example		: $> echo 0x4F > addr_exlevel_s_ns
+
+File		: addr_instdatatype (rw)
+Trace Registers	: ACATR[idx,{1:0}]
+Notes 		: Set the comparator address type for matching. Driver only
+		supports setting instruction address type.
+Depends		: addr_idx
+
+File		: addr_cmp_view (ro)
+Trace Registers	: ACVR[idx, idx+1], ACATR[idx], VIIECTLR
+Notes 		: Read the currently selected address comparator. If part of
+		address range then display both addresses.
+Depends		: addr_idx
+Syntax		: 'cat addr_cmp_view'
+Example		: $> cat addr_cmp_view
+		addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)
+
+File		: nr_addr_cmp (ro)
+Trace Registers	: From IDR4
+Notes 		: Number of address comparator pairs
+
+File		: sshot_idx (rw)
+Trace Registers	: None
+Notes 		: Select  single shot register set.
+
+File		: sshot_ctrl (rw)
+Trace Registers	: SSCCR[idx]
+Notes 		: Access a single shot comparator control register.
+Depends		: sshot_idx
+Syntax		: 'echo val > sshot_ctrl'
+		Writes val into the selected control register.
+
+File		: sshot_status (ro)
+Trace Registers	: SSCSR[idx]
+Notes 		: Read a single shot comparator status register
+Depends		: sshot_idx
+Syntax		: 'cat sshot_status'
+		Read status.
+Example		: $> cat sshot_status
+		0x1
+
+File		: sshot_pe_ctrl (rw)
+Trace Registers	: SSPCICR[idx]
+Notes 		: Access a single shot PE comparator input control register.
+Depends		: sshot_idx
+Syntax		: echo val > sshot_pe_ctrl
+		Writes val into the selected control register.
+
+File		: ns_exlevel_vinst (rw)
+Trace Registers	: VICTLR{23:20}
+Notes 		: Program non-secure exception level filters. Set / clear NS
+		exception filter bits. Setting ‘1’ excludes trace from the
+		exception level.
+Syntax		: 'echo bitfield > ns_exlevel_viinst'
+		Where bitfield contains bits to set clear for EL0 to EL2
+Example		: %> echo 0x4 > ns_exlevel_viinst
+		; Exclude EL2 NS trace.
+
+File		: vinst_pe_cmp_start_stop (rw)
+Trace Registers	: VIPCSSCTLR
+Notes 		: Access PE start stop comparator input control registers
+
+File		: bb_ctrl (rw)
+Trace Registers	: BBCTLR
+Notes 		: Define ranges that Branch Broadcast will operate in.
+		Default (0x0) is all addresses.
+Depends		: BB enabled.
+
+File		: cyc_threshold (rw)
+Trace Registers	: CCCTLR
+Notes 		: Set the threshold for which cycle counts will be emitted.
+		Error if attempt to set below minimum defined in IDR3, masked
+		to width of valid bits.
+Depends		: CC enabled.
+
+File		: syncfreq (rw)
+Trace Registers	: SYNCPR
+Notes 		: Set trace synchronisation period. Power of 2 value, 0 (off)
+		or 8-20. Driver defaults to 12 (every 4096 bytes).
+
+File		: cntr_idx (rw)
+Trace Registers	: none
+Notes 		: Select the counter to access
+Syntax		: 'echo idx > cntr_idx'
+		Where idx <  nr_cntr
+
+File		: cntr_ctrl (rw)
+Trace Registers	: CNTCTLR[idx]
+Notes 		: Set counter control value
+Depends		: cntr_idx
+Syntax		: 'echo val > cntr_ctrl'
+		Where val is per ETMv4 spec.
+
+File		: cntrldvr (rw)
+Trace Registers	: CNTRLDVR[idx]
+Notes 		: Set counter reload value
+Depends		: cntr_idx
+Syntax		: 'echo val > cntrldvr'
+		Where val is per ETMv4 spec.
+
+File		: nr_cntr (ro)
+Trace Registers	: From IDR5
+Notes 		: Number of counters implemented.
+
+File		: ctxid_idx (rw)
+Trace Registers	: None
+Notes 		: Select the context ID comparator to access
+Syntax		: 'echo idx > ctxid_idx'
+		Where idx <  numcidc
+
+File		: ctxid_pid (rw)
+Trace Registers	: CIDCVR[idx]
+Notes 		: Set the context ID comparator value
+Depends		: ctxid_idx
+
+File		: ctxid_masks (rw)
+Trace Registers	: CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7>
+Notes 		: Pair of values to set the byte masks for 1-8 context ID
+		comparators. Automatically clears masked bytes to 0 in CID
+		value registers.
+Syntax		: 'echo m3m2m1m0 [m7m6m5m4] > ctxid_masks'
+		32 bit values made up of mask bytes, where mN represents a
+		byte mask value for Ctxt ID comparator N.
+		Second value not required on systems that have fewer than 4
+		context ID comparators
+
+File		: numcidc (ro)
+Trace Registers	: From IDR4
+Notes 		: Number of Context ID comparators
+
+File		: vmid_idx (rw)
+Trace Registers	: None
+Notes 		: Select the VM ID comparator to access.
+Syntax		: 'echo idx > vmid_idx'
+		Where idx <  numvmidc
+
+File		: vmid_val (rw)
+Trace Registers	: VMIDCVR[idx]
+Notes 		: Set the VM ID comparator value
+Depends		: vmid_idx
+
+File		: vmid_masks (rw)
+Trace Registers	: VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7>
+Notes 		: Pair of values to set the byte masks for 1-8 VM ID
+		comparators. Automatically clears masked bytes to 0 in VMID
+		value registers.
+Syntax		: 'echo m3m2m1m0 [m7m6m5m4] > vmid_masks'
+		Where mN represents a byte mask value for VMID comparator N.
+		Second value not required on systems that have fewer than
+		4 VMID comparators.
+
+File		: numvmidc (ro)
+Trace Registers	: From IDR4
+Notes 		: Number of VMID comparators
+
+File		: res_idx (rw)
+Trace Registers	: None.
+Notes 		: Select the resource selector control to access. Must be 2 or
+		higher as selectors 0 and 1 are hardwired.
+Syntax		: 'echo idx > res_idx'
+		Where 2 <= idx <  nr_resource x 2
+
+File		: res_ctrl (rw)
+Trace Registers	: RSCTLR[idx]
+Notes 		: Set resource selector control value. Value per ETMv4 spec.
+Depends		: res_idx
+Syntax		: 'echo val > res_cntr'
+		Where val is per ETMv4 spec.
+
+File		: nr_resource (ro)
+Trace Registers	: From IDR4
+Notes 		: Number of resource selector pairs
+
+File		: event (rw)
+Trace Registers	: EVENTCTRL0R
+Notes 		: Set up to 4 implemented event fields.
+Syntax		: 'echo ev3ev2ev1ev0 > event'
+		Where evN is an 8 bit event field. Up to 4 event fields make up
+		the 32bit input value. Number of valid fields implementation
+		dependent defined in IDR0.
+
+File		: event_instren (rw)
+Trace Registers	: EVENTCTRL1R
+Notes 		: Choose events which insert event packets into trace stream.
+Depends		: EVENTCTRL0R
+Syntax		: 'echo bitfield > event_instren'
+		Where bitfield is up to 4 bits according to number of event
+		fields.
+
+File		: event_ts (rw)
+Trace Registers	: TSCTLR
+Notes 		: Set the event that will generate timestamp requests.
+Depends		: TS activated
+Syntax		: 'echo evfield > event_ts'
+		Where evfield is an 8 bit event selector.
+
+File		: seq_idx (rw)
+Trace Registers	: None
+Notes 		: Sequencer event register select - 0 to 2
+
+
+File		: seq_state (rw)
+Trace Registers	: SEQSTR
+Notes 		: Sequencer current state - 0 to 3.
+
+File		: seq_event (rw)
+Trace Registers	: SEQEVR[idx]
+Notes 		: State transition event registers
+Depends		: seq_idx
+Syntax		: 'echo evBevF > seq_event'
+		Where evBevF is a 16 bit value made up of two event selectors,
+		evB - back, evF - forwards.
+
+File		: seq_reset_event (rw)
+Trace Registers	: SEQRSTEVR
+Notes 		: Sequencer reset event
+Syntax		: 'echo evfield > seq_reset_event'
+		Where evfield is an 8 bit event selector.
+
+File		: nrseqstate (ro)
+Trace Registers	: From IDR5
+Notes 		: Number of sequencer states (0 or 4)
+
+File		: nr_pe_cmp (ro)
+Trace Registers	: From IDR4
+Notes 		: Number of PE comparator inputs
+
+File		: nr_ext_inp (ro)
+Trace Registers	: From IDR5
+Notes 		: Number of external inputs
+
+File		: nr_ss_cmp (ro)
+Trace Registers	: From IDR4
+Notes 		: Number of Single Shot control registers
+
+Note: When programming any address comparator the driver will tag the
+comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag
+is set, then only the values can be changed using the same sysfs file / type
+used to program it.
+
+Thus:-
+% echo 0 > addr_idx		    ; select address comparator 0
+% echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0 and 1.
+% echo 0x2000 > addr_start	    ; this will error as comparator 0 is a
+       	      			    ; range comparator
+% echo 2 > addr_idx 		    ; select address comparator 2
+% echo 0x2000 > addr_start	    ; this is OK as comparator 2 is unused,
+% echo 0x3000 > addr_stop	    ; this will error as comparator 2 a start
+       	      			    ; address comparator
+% echo 2 > addr_idx 		    ; select address comparator 3
+% echo 0x3000 > addr_stop	    ; this is OK
+
+To remove programming on all the comparators (and all the other hardware) use
+the reset parameter:
+
+% echo 1 > reset
+
+The ‘mode’ sysfs parameter.
+---------------------------
+
+This is a bitfield selection parameter that sets the overall trace mode for the
+ETM. The table below describes the bits, using the defines from the driver
+source file, along with a description of the feature these represent. Many
+features are optional and therefore dependent on implementation in the
+hardware.
+
+Bit assignements shown below:-
+
+bit (0)	    : #define ETM_MODE_EXCLUDE
+description : This is the default value for the include / exclude function when
+	      setting address ranges. Set 1 for exclude range. When the mode
+	      parameter is set this value is applied to the currently indexed
+	      address range.
+
+bit (4)	    : #define ETM_MODE_BB
+description : Set to enable branch broadcast if supported in hardware [IDR0].
+
+bit (5)	    : #define ETMv4_MODE_CYCACC
+description : Set to enable cycle accurate trace if supported [IDR0].
+
+bit (6)	    : ETMv4_MODE_CTXID
+description : Set to enable context ID tracing if supported in hardware [IDR2].
+
+bit (7)	    : ETM_MODE_VMID
+description : Set to enable virtual machine ID tracing if supported [IDR2].
+
+bit (11)    : ETMv4_MODE_TIMESTAMP
+description : Set to enable timestamp generation if supported [IDR0].
+
+bit (12)    : ETM_MODE_RETURNSTACK
+description : Set to enable trace return stack use if supported [IDR0].
+
+bit (13-14) : ETM_MODE_QELEM(val)
+description : ‘val’ determines level of Q element support enabled if
+	    implemented by the ETM [IDR0]
+
+bit (19)    : ETM_MODE_ATB_TRIGGER
+description : Set to enable the ATBTRIGGER bit in the event control register
+	    [EVENTCTLR1] if supported [IDR5].
+
+bit (20)    : ETM_MODE_LPOVERRIDE
+description : Set to enable the LPOVERRIDE bit in the event control register
+	    [EVENTCTLR1], if supported [IDR5].
+
+bit (21)    : ETM_MODE_ISTALL_EN
+description : Set to enable the ISTALL bit in the stall control register
+	    [STALLCTLR]
+
+bit (23)    : ETM_MODE_INSTPRIO
+description : Set to enable the INSTPRIORITY bit in the stall control register
+	    [STALLCTLR] , if supported [IDR0].
+
+bit (24)    : ETM_MODE_NOOVERFLOW
+description : Set to enable the NOOVERFLOW bit in the stall control register
+	    [STALLCTLR], if supported [IDR3].
+
+bit (25)    : ETM_MODE_TRACE_RESET
+description : Set to enable the TRCRESET bit in the viewinst control register
+	    [VICTLR] , if supported [IDR3].
+
+bit (26)    : ETM_MODE_TRACE_ERR
+description : Set to enable the TRCCTRL bit in the viewinst control register
+	    [VICTLR].
+
+bit (27)    : ETM_MODE_VIEWINST_STARTSTOP
+description : Set the initial state value of the ViewInst start / stop logic
+	    in the viewinst control register [VICTLR]
+
+bit (30)    : ETM_MODE_EXCL_KERN
+description : Set default trace setup to exclude kernel mode trace (see note a)
+
+bit (31)    : ETM_MODE_EXCL_USER
+description : Set default trace setup to exclude user space trace (see note a)
+
+Note a) On startup the ETM is programmed to trace the complete address space
+using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to
+set EL exclude bits for NS state in either user space (EL0) or kernel space
+(EL1) in the address range comparator. (the default setting excludes all
+secure EL, and NS EL2)
+
+Once the reset parameter has been used, and/or custom programming has been
+implemented - using these bits will result in the EL bits for address
+comparator 0 being set in the same way.
+
+Note b) Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with
+data trace. As A profile data trace is architecturally prohibited in ETMv4,
+these have been omitted here. Possible uses could be where a kernel has
+support for control of R or M profile infrastructure as part of a heterogeneous
+system.
+
+Bits 17, 28-29 are unused.
+
diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight/coresight.txt
similarity index 100%
rename from Documentation/trace/coresight.txt
rename to Documentation/trace/coresight/coresight.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index 783569e3c4b4..777b77fde29b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1582,8 +1582,7 @@ R:	Suzuki K Poulose <suzuki.poulose@arm.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	drivers/hwtracing/coresight/*
-F:	Documentation/trace/coresight.txt
-F:	Documentation/trace/coresight-cpu-debug.txt
+F:	Documentation/trace/coresight/*
 F:	Documentation/devicetree/bindings/arm/coresight.txt
 F:	Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
 F:	Documentation/ABI/testing/sysfs-bus-coresight-devices-*
-- 
2.17.1


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Re: [PATCH 8/8] coresight: etm4x: docs: Additional documentation for ETM4x.

[Mathieu Poirier]

On Mon, Aug 19, 2019 at 09:57:20PM +0100, Mike Leach wrote:
> Update existing docs for new sysfs API features.
> Add new ETMv4 reference document for sysfs programming.
> Move coresight documentation to common directory.

Please split in 3 different patches.  When sending again make sure to add
Jonathan Corbet, Greg KH and the linux-doc mailing as recipients.

Thanks,
Mathieu

> 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++---
>  .../{ => coresight}/coresight-cpu-debug.txt   |   0
>  .../coresight/coresight-etm4x-reference.txt   | 459 ++++++++++++++++++
>  .../trace/{ => coresight}/coresight.txt       |   0
>  MAINTAINERS                                   |   3 +-
>  5 files changed, 575 insertions(+), 70 deletions(-)
>  rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%)
>  create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt
>  rename Documentation/trace/{ => coresight}/coresight.txt (100%)
> 
> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> index 36258bc1b473..112c50ae9986 100644
> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> @@ -1,4 +1,4 @@
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/enable_source
> +What:		/sys/bus/coresight/devices/etm<N>/enable_source
>  Date:		April 2015
>  KernelVersion:  4.01
>  Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
> @@ -8,82 +8,82 @@ Description:	(RW) Enable/disable tracing on this specific trace entiry.
>  		of coresight components linking the source to the sink is
>  		configured and managed automatically by the coresight framework.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/cpu
> +What:		/sys/bus/coresight/devices/etm<N>/cpu
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) The CPU this tracing entity is associated with.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
> +What:		/sys/bus/coresight/devices/etm<N>/nr_pe_cmp
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of PE comparator inputs that are
>  		available for tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
> +What:		/sys/bus/coresight/devices/etm<N>/nr_addr_cmp
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of address comparator pairs that are
>  		available for tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
> +What:		/sys/bus/coresight/devices/etm<N>/nr_cntr
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of counters that are available for
>  		tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
> +What:		/sys/bus/coresight/devices/etm<N>/nr_ext_inp
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates how many external inputs are implemented.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/numcidc
> +What:		/sys/bus/coresight/devices/etm<N>/numcidc
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of Context ID comparators that are
>  		available for tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/numvmidc
> +What:		/sys/bus/coresight/devices/etm<N>/numvmidc
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of VMID comparators that are available
>  		for tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
> +What:		/sys/bus/coresight/devices/etm<N>/nrseqstate
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of sequencer states that are
>  		implemented.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_resource
> +What:		/sys/bus/coresight/devices/etm<N>/nr_resource
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of resource selection pairs that are
>  		available for tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
> +What:		/sys/bus/coresight/devices/etm<N>/nr_ss_cmp
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of single-shot comparator controls that
>  		are available for tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/reset
> +What:		/sys/bus/coresight/devices/etm<N>/reset
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(W) Cancels all configuration on a trace unit and set it back
>  		to its boot configuration.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mode
> +What:		/sys/bus/coresight/devices/etm<N>/mode
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> @@ -91,302 +91,349 @@ Description: 	(RW) Controls various modes supported by this ETM, for example
>  		P0 instruction tracing, branch broadcast, cycle counting and
>  		context ID tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/pe
> +What:		/sys/bus/coresight/devices/etm<N>/pe
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls which PE to trace.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/event
> +What:		/sys/bus/coresight/devices/etm<N>/event
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls the tracing of arbitrary events from bank 0 to 3.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/event_instren
> +What:		/sys/bus/coresight/devices/etm<N>/event_instren
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls the behavior of the events in bank 0 to 3.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/event_ts
> +What:		/sys/bus/coresight/devices/etm<N>/event_ts
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls the insertion of global timestamps in the trace
>  		streams.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/syncfreq
> +What:		/sys/bus/coresight/devices/etm<N>/syncfreq
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls how often trace synchronization requests occur.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
> +What:		/sys/bus/coresight/devices/etm<N>/cyc_threshold
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Sets the threshold value for cycle counting.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
> +What:		/sys/bus/coresight/devices/etm<N>/bb_ctrl
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls which regions in the memory map are enabled to
>  		use branch broadcasting.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/event_vinst
> +What:		/sys/bus/coresight/devices/etm<N>/event_vinst
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls instruction trace filtering.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst
> +What:		/sys/bus/coresight/devices/etm<N>/s_exlevel_vinst
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) In Secure state, each bit controls whether instruction
>  		tracing is enabled for the corresponding exception level.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst
> +What:		/sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) In non-secure state, each bit controls whether instruction
>  		tracing is enabled for the corresponding exception level.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_idx
> +What:		/sys/bus/coresight/devices/etm<N>/addr_idx
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Select which address comparator or pair (of comparators) to
>  		work with.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype
> +What:		/sys/bus/coresight/devices/etm<N>/addr_instdatatype
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls what type of comparison the trace unit performs.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_single
> +What:		/sys/bus/coresight/devices/etm<N>/addr_single
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Used to setup single address comparator values.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_range
> +What:		/sys/bus/coresight/devices/etm<N>/addr_range
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Used to setup address range comparator values.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_idx
> +What:		/sys/bus/coresight/devices/etm<N>/seq_idx
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Select which sequensor.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_state
> +What:		/sys/bus/coresight/devices/etm<N>/seq_state
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Use this to set, or read, the sequencer state.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_event
> +What:		/sys/bus/coresight/devices/etm<N>/seq_event
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Moves the sequencer state to a specific state.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event
> +What:		/sys/bus/coresight/devices/etm<N>/seq_reset_event
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Moves the sequencer to state 0 when a programmed event
>  		occurs.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_idx
> +What:		/sys/bus/coresight/devices/etm<N>/cntr_idx
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Select which counter unit to work with.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/cntrldvr
> +What:		/sys/bus/coresight/devices/etm<N>/cntrldvr
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) This sets or returns the reload count value of the
>  		specific counter.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_val
> +What:		/sys/bus/coresight/devices/etm<N>/cntr_val
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) This sets or returns the current count value of the
>                  specific counter.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl
> +What:		/sys/bus/coresight/devices/etm<N>/cntr_ctrl
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls the operation of the selected counter.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/res_idx
> +What:		/sys/bus/coresight/devices/etm<N>/res_idx
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Select which resource selection unit to work with.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/res_ctrl
> +What:		/sys/bus/coresight/devices/etm<N>/res_ctrl
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls the selection of the resources in the trace unit.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx
> +What:		/sys/bus/coresight/devices/etm<N>/ctxid_idx
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Select which context ID comparator to work with.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid
> +What:		/sys/bus/coresight/devices/etm<N>/ctxid_pid
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Get/Set the context ID comparator value to trigger on.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks
> +What:		/sys/bus/coresight/devices/etm<N>/ctxid_masks
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Mask for all 8 context ID comparator value
>  		registers (if implemented).
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_idx
> +What:		/sys/bus/coresight/devices/etm<N>/vmid_idx
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Select which virtual machine ID comparator to work with.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_val
> +What:		/sys/bus/coresight/devices/etm<N>/vmid_val
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Get/Set the virtual machine ID comparator value to
>  		trigger on.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_masks
> +What:		/sys/bus/coresight/devices/etm<N>/vmid_masks
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Mask for all 8 virtual machine ID comparator value
>  		registers (if implemented).
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr
> +What:		/sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(RW) Set the Exception Level matching bits for secure and
> +		non-secure exception levels.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(RW) Access the start stop control register for PE input
> +		comparators.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/addr_cmp_view
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(R) Print the current settings for the selected address
> +		comparator.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/sshot_idx
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(RW) Select the single shot control register to access.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/sshot_ctrl
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(RW) Access the selected single shot control register.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/sshot_status
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(R) Print the current value of the selected single shot
> +		status register.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(RW) Access the selected single show PE comparator control
> +		register.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the OS Lock Status Register (0x304).
>  		The value it taken directly  from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Power Down Control Register
>  		(0x310).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Power Down Status Register
>  		(0x314).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trclsr
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the SW Lock Status Register
>  		(0xFB4).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Authentication Status Register
>  		(0xFB8).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevid
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Device ID Register
>  		(0xFC8).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Device Type Register
>  		(0xFCC).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Peripheral ID0 Register
>  		(0xFE0).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Peripheral ID1 Register
>  		(0xFE4).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Peripheral ID2 Register
>  		(0xFE8).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Peripheral ID3 Register
>  		(0xFEC).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcconfig
>  Date:		February 2016
>  KernelVersion:	4.07
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the trace configuration register
>  		(0x010) as currently set by SW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trctraceid
>  Date:		February 2016
>  KernelVersion:	4.07
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the trace ID register (0x040).
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr0
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns the tracing capabilities of the trace unit (0x1E0).
>  		The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr1
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns the tracing capabilities of the trace unit (0x1E4).
>  		The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr2
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> @@ -394,7 +441,7 @@ Description:	(R) Returns the maximum size of the data value, data address,
>  		VMID, context ID and instuction address in the trace unit
>  		(0x1E8).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr3
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> @@ -403,42 +450,42 @@ Description:	(R) Returns the value associated with various resources
>  		architecture specification for more details (0x1E8).
>  		The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr4
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns how many resources the trace unit supports (0x1F0).
>  		The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr5
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns how many resources the trace unit supports (0x1F4).
>  		The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr8
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns the maximum speculation depth of the instruction
>  		trace stream. (0x180).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr9
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns the number of P0 right-hand keys that the trace unit
>  		can use (0x184).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr10
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns the number of P1 right-hand keys that the trace unit
>  		can use (0x188).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr11
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> @@ -446,7 +493,7 @@ Description:	(R) Returns the number of special P1 right-hand keys that the
>  		trace unit can use (0x18C).  The value is taken directly from
>  		the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr12
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> @@ -454,7 +501,7 @@ Description:	(R) Returns the number of conditional P1 right-hand keys that
>  		the trace unit can use (0x190).  The value is taken directly
>  		from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr13
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight/coresight-cpu-debug.txt
> similarity index 100%
> rename from Documentation/trace/coresight-cpu-debug.txt
> rename to Documentation/trace/coresight/coresight-cpu-debug.txt
> diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.txt b/Documentation/trace/coresight/coresight-etm4x-reference.txt
> new file mode 100644
> index 000000000000..72e81bbbef43
> --- /dev/null
> +++ b/Documentation/trace/coresight/coresight-etm4x-reference.txt
> @@ -0,0 +1,459 @@
> +ETMv4 sysfs linux driver programming reference - v2.
> +====================================================
> +
> +Supplement to existing ETMv4 driver documentation.
> +
> +Sysfs files and directories
> +---------------------------
> +
> +Root: /sys/bus/coresight/devices/etm<N>
> +
> +
> +The following paragraphs explain the association between sysfs files and the
> +ETMv4 registers that they effect. Note the register names are given without
> +the ‘TRC’ prefix.
> +
> +File		: mode (rw)
> +Trace Registers	: {CONFIGR + others}
> +Notes 		: Bit select trace features. See ‘mode’ section below. Bits
> +		in this will cause equivalent programming of trace config and
> +		other registers to enable the features requested.
> +Syntax & eg	: 'echo bitfield > mode'
> +       	 	bitfield up to 32 bits setting trace features.
> +Example		: $> echo 0x > mode
> +
> +File		: reset (wo)
> +Trace Registers	: All
> +Notes 		: Reset all programming to trace nothing / no logic programmed.
> +Syntax		: 'echo 1 > reset'
> +
> +File		: enable_source (wo)
> +Trace Registers	: PRGCTLR, All hardware regs.
> +Notes 		:  >0: Programs up the hardware with the current values held in
> +		the driver and enables trace.
> +		0: disable trace hardware.
> +Syntax		: 'echo 1 > enable_source'
> +
> +File		: cpu (ro)
> +Trace Registers	: None.
> +Notes 		: CPU ID that this ETM is attached to.
> +Example		:$> cat cpu
> +		$> 0
> +
> +File		: addr_idx (rw)
> +Trace Registers	: None.
> +Notes 		: Virtual register to index address comparator and range
> +		features. Set index for first of the pair in a range.
> +Syntax		: 'echo idx > addr_idx'
> +		Where idx <  nr_addr_cmp x 2
> +
> +File		: addr_range (rw)
> +Trace Registers	: ACVR[idx, idx+1], VIIECTLR
> +Notes 		: Pair of addresses for a range selected by addr_idx. Include
> +		/ exclude according to the optional parameter, or if omitted
> +		uses the current ‘mode’ setting. Select comparator range in
> +		control register. Error if index is odd value.
> +Depends		: mode, addr_idx
> +Syntax		: 'echo addr1 addr2 [exclude] > addr_range'
> +		Where addr1 and addr2 define the range and addr1 < addr2.
> +		Optional exclude value - 0 for include, 1 for exclude.
> +Example		: $> echo 0x0000 0x2000 0 > addr_range
> +
> +File		: addr_single (rw)
> +Trace Registers	: ACVR[idx]
> +Notes 		: Set a single address comparator according to addr_idx. This
> +		is used if the address comparator is used as part of event
> +		generation logic etc.
> +Depends		: addr_idx
> +Syntax		: 'echo addr1 > addr_single'
> +
> +File		: addr_start (rw)
> +Trace Registers	: ACVR[idx], VISSCTLR
> +Notes 		: Set a trace start address comparator according to addr_idx.
> +		Select comparator in control register.
> +Depends		: addr_idx
> +Syntax		: 'echo addr1 > addr_start'
> +
> +File		: addr_stop (rw)
> +Trace Registers	: ACVR[idx], VISSCTLR
> +Notes 		: Set a trace stop address comparator according to addr_idx.
> +		Select comparator in control register.
> +Depends		: addr_idx
> +Syntax		: 'echo addr1 > addr_stop'
> +
> +File		: addr_context (rw)
> +Trace Registers	: ACATR[idx,{6:4}]
> +Notes 		: Link context ID comparator to address comparator addr_idx
> +Depends		: addr_idx.
> +Syntax		: 'echo ctxt_idx > addr_context'
> +		Where ctxt_idx is the index of the linked context id / vmid
> +		comparator.
> +
> +File		: addr_ctxtype (rw)
> +Trace Registers	: ACATR[idx,{3:2}]
> +Notes 		: Input value string. Set type for linked context ID comparator
> +Depends		: addr_idx
> +Syntax		: 'echo type > addr_ctxtype'
> +		Type one of {all, vmid, ctxid, none}
> +Example		: $> echo ctxid > addr_ctxtype
> +
> +File		: addr_exlevel_s_ns (rw)
> +Trace Registers	: ACATR[idx,{14:8}]
> +Notes 		: Set the ELx secure and non-secure  matching bits for the
> +		selected address comparator
> +Depends		: addr_idx
> +Syntax		: 'echo val > addr_exlevel_s_ns'
> +		val is a 7 bit value for exception levels to exclude. Input
> +		value shifted to correct bits in register.
> +Example		: $> echo 0x4F > addr_exlevel_s_ns
> +
> +File		: addr_instdatatype (rw)
> +Trace Registers	: ACATR[idx,{1:0}]
> +Notes 		: Set the comparator address type for matching. Driver only
> +		supports setting instruction address type.
> +Depends		: addr_idx
> +
> +File		: addr_cmp_view (ro)
> +Trace Registers	: ACVR[idx, idx+1], ACATR[idx], VIIECTLR
> +Notes 		: Read the currently selected address comparator. If part of
> +		address range then display both addresses.
> +Depends		: addr_idx
> +Syntax		: 'cat addr_cmp_view'
> +Example		: $> cat addr_cmp_view
> +		addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)
> +
> +File		: nr_addr_cmp (ro)
> +Trace Registers	: From IDR4
> +Notes 		: Number of address comparator pairs
> +
> +File		: sshot_idx (rw)
> +Trace Registers	: None
> +Notes 		: Select  single shot register set.
> +
> +File		: sshot_ctrl (rw)
> +Trace Registers	: SSCCR[idx]
> +Notes 		: Access a single shot comparator control register.
> +Depends		: sshot_idx
> +Syntax		: 'echo val > sshot_ctrl'
> +		Writes val into the selected control register.
> +
> +File		: sshot_status (ro)
> +Trace Registers	: SSCSR[idx]
> +Notes 		: Read a single shot comparator status register
> +Depends		: sshot_idx
> +Syntax		: 'cat sshot_status'
> +		Read status.
> +Example		: $> cat sshot_status
> +		0x1
> +
> +File		: sshot_pe_ctrl (rw)
> +Trace Registers	: SSPCICR[idx]
> +Notes 		: Access a single shot PE comparator input control register.
> +Depends		: sshot_idx
> +Syntax		: echo val > sshot_pe_ctrl
> +		Writes val into the selected control register.
> +
> +File		: ns_exlevel_vinst (rw)
> +Trace Registers	: VICTLR{23:20}
> +Notes 		: Program non-secure exception level filters. Set / clear NS
> +		exception filter bits. Setting ‘1’ excludes trace from the
> +		exception level.
> +Syntax		: 'echo bitfield > ns_exlevel_viinst'
> +		Where bitfield contains bits to set clear for EL0 to EL2
> +Example		: %> echo 0x4 > ns_exlevel_viinst
> +		; Exclude EL2 NS trace.
> +
> +File		: vinst_pe_cmp_start_stop (rw)
> +Trace Registers	: VIPCSSCTLR
> +Notes 		: Access PE start stop comparator input control registers
> +
> +File		: bb_ctrl (rw)
> +Trace Registers	: BBCTLR
> +Notes 		: Define ranges that Branch Broadcast will operate in.
> +		Default (0x0) is all addresses.
> +Depends		: BB enabled.
> +
> +File		: cyc_threshold (rw)
> +Trace Registers	: CCCTLR
> +Notes 		: Set the threshold for which cycle counts will be emitted.
> +		Error if attempt to set below minimum defined in IDR3, masked
> +		to width of valid bits.
> +Depends		: CC enabled.
> +
> +File		: syncfreq (rw)
> +Trace Registers	: SYNCPR
> +Notes 		: Set trace synchronisation period. Power of 2 value, 0 (off)
> +		or 8-20. Driver defaults to 12 (every 4096 bytes).
> +
> +File		: cntr_idx (rw)
> +Trace Registers	: none
> +Notes 		: Select the counter to access
> +Syntax		: 'echo idx > cntr_idx'
> +		Where idx <  nr_cntr
> +
> +File		: cntr_ctrl (rw)
> +Trace Registers	: CNTCTLR[idx]
> +Notes 		: Set counter control value
> +Depends		: cntr_idx
> +Syntax		: 'echo val > cntr_ctrl'
> +		Where val is per ETMv4 spec.
> +
> +File		: cntrldvr (rw)
> +Trace Registers	: CNTRLDVR[idx]
> +Notes 		: Set counter reload value
> +Depends		: cntr_idx
> +Syntax		: 'echo val > cntrldvr'
> +		Where val is per ETMv4 spec.
> +
> +File		: nr_cntr (ro)
> +Trace Registers	: From IDR5
> +Notes 		: Number of counters implemented.
> +
> +File		: ctxid_idx (rw)
> +Trace Registers	: None
> +Notes 		: Select the context ID comparator to access
> +Syntax		: 'echo idx > ctxid_idx'
> +		Where idx <  numcidc
> +
> +File		: ctxid_pid (rw)
> +Trace Registers	: CIDCVR[idx]
> +Notes 		: Set the context ID comparator value
> +Depends		: ctxid_idx
> +
> +File		: ctxid_masks (rw)
> +Trace Registers	: CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7>
> +Notes 		: Pair of values to set the byte masks for 1-8 context ID
> +		comparators. Automatically clears masked bytes to 0 in CID
> +		value registers.
> +Syntax		: 'echo m3m2m1m0 [m7m6m5m4] > ctxid_masks'
> +		32 bit values made up of mask bytes, where mN represents a
> +		byte mask value for Ctxt ID comparator N.
> +		Second value not required on systems that have fewer than 4
> +		context ID comparators
> +
> +File		: numcidc (ro)
> +Trace Registers	: From IDR4
> +Notes 		: Number of Context ID comparators
> +
> +File		: vmid_idx (rw)
> +Trace Registers	: None
> +Notes 		: Select the VM ID comparator to access.
> +Syntax		: 'echo idx > vmid_idx'
> +		Where idx <  numvmidc
> +
> +File		: vmid_val (rw)
> +Trace Registers	: VMIDCVR[idx]
> +Notes 		: Set the VM ID comparator value
> +Depends		: vmid_idx
> +
> +File		: vmid_masks (rw)
> +Trace Registers	: VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7>
> +Notes 		: Pair of values to set the byte masks for 1-8 VM ID
> +		comparators. Automatically clears masked bytes to 0 in VMID
> +		value registers.
> +Syntax		: 'echo m3m2m1m0 [m7m6m5m4] > vmid_masks'
> +		Where mN represents a byte mask value for VMID comparator N.
> +		Second value not required on systems that have fewer than
> +		4 VMID comparators.
> +
> +File		: numvmidc (ro)
> +Trace Registers	: From IDR4
> +Notes 		: Number of VMID comparators
> +
> +File		: res_idx (rw)
> +Trace Registers	: None.
> +Notes 		: Select the resource selector control to access. Must be 2 or
> +		higher as selectors 0 and 1 are hardwired.
> +Syntax		: 'echo idx > res_idx'
> +		Where 2 <= idx <  nr_resource x 2
> +
> +File		: res_ctrl (rw)
> +Trace Registers	: RSCTLR[idx]
> +Notes 		: Set resource selector control value. Value per ETMv4 spec.
> +Depends		: res_idx
> +Syntax		: 'echo val > res_cntr'
> +		Where val is per ETMv4 spec.
> +
> +File		: nr_resource (ro)
> +Trace Registers	: From IDR4
> +Notes 		: Number of resource selector pairs
> +
> +File		: event (rw)
> +Trace Registers	: EVENTCTRL0R
> +Notes 		: Set up to 4 implemented event fields.
> +Syntax		: 'echo ev3ev2ev1ev0 > event'
> +		Where evN is an 8 bit event field. Up to 4 event fields make up
> +		the 32bit input value. Number of valid fields implementation
> +		dependent defined in IDR0.
> +
> +File		: event_instren (rw)
> +Trace Registers	: EVENTCTRL1R
> +Notes 		: Choose events which insert event packets into trace stream.
> +Depends		: EVENTCTRL0R
> +Syntax		: 'echo bitfield > event_instren'
> +		Where bitfield is up to 4 bits according to number of event
> +		fields.
> +
> +File		: event_ts (rw)
> +Trace Registers	: TSCTLR
> +Notes 		: Set the event that will generate timestamp requests.
> +Depends		: TS activated
> +Syntax		: 'echo evfield > event_ts'
> +		Where evfield is an 8 bit event selector.
> +
> +File		: seq_idx (rw)
> +Trace Registers	: None
> +Notes 		: Sequencer event register select - 0 to 2
> +
> +
> +File		: seq_state (rw)
> +Trace Registers	: SEQSTR
> +Notes 		: Sequencer current state - 0 to 3.
> +
> +File		: seq_event (rw)
> +Trace Registers	: SEQEVR[idx]
> +Notes 		: State transition event registers
> +Depends		: seq_idx
> +Syntax		: 'echo evBevF > seq_event'
> +		Where evBevF is a 16 bit value made up of two event selectors,
> +		evB - back, evF - forwards.
> +
> +File		: seq_reset_event (rw)
> +Trace Registers	: SEQRSTEVR
> +Notes 		: Sequencer reset event
> +Syntax		: 'echo evfield > seq_reset_event'
> +		Where evfield is an 8 bit event selector.
> +
> +File		: nrseqstate (ro)
> +Trace Registers	: From IDR5
> +Notes 		: Number of sequencer states (0 or 4)
> +
> +File		: nr_pe_cmp (ro)
> +Trace Registers	: From IDR4
> +Notes 		: Number of PE comparator inputs
> +
> +File		: nr_ext_inp (ro)
> +Trace Registers	: From IDR5
> +Notes 		: Number of external inputs
> +
> +File		: nr_ss_cmp (ro)
> +Trace Registers	: From IDR4
> +Notes 		: Number of Single Shot control registers
> +
> +Note: When programming any address comparator the driver will tag the
> +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag
> +is set, then only the values can be changed using the same sysfs file / type
> +used to program it.
> +
> +Thus:-
> +% echo 0 > addr_idx		    ; select address comparator 0
> +% echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0 and 1.
> +% echo 0x2000 > addr_start	    ; this will error as comparator 0 is a
> +       	      			    ; range comparator
> +% echo 2 > addr_idx 		    ; select address comparator 2
> +% echo 0x2000 > addr_start	    ; this is OK as comparator 2 is unused,
> +% echo 0x3000 > addr_stop	    ; this will error as comparator 2 a start
> +       	      			    ; address comparator
> +% echo 2 > addr_idx 		    ; select address comparator 3
> +% echo 0x3000 > addr_stop	    ; this is OK
> +
> +To remove programming on all the comparators (and all the other hardware) use
> +the reset parameter:
> +
> +% echo 1 > reset
> +
> +The ‘mode’ sysfs parameter.
> +---------------------------
> +
> +This is a bitfield selection parameter that sets the overall trace mode for the
> +ETM. The table below describes the bits, using the defines from the driver
> +source file, along with a description of the feature these represent. Many
> +features are optional and therefore dependent on implementation in the
> +hardware.
> +
> +Bit assignements shown below:-
> +
> +bit (0)	    : #define ETM_MODE_EXCLUDE
> +description : This is the default value for the include / exclude function when
> +	      setting address ranges. Set 1 for exclude range. When the mode
> +	      parameter is set this value is applied to the currently indexed
> +	      address range.
> +
> +bit (4)	    : #define ETM_MODE_BB
> +description : Set to enable branch broadcast if supported in hardware [IDR0].
> +
> +bit (5)	    : #define ETMv4_MODE_CYCACC
> +description : Set to enable cycle accurate trace if supported [IDR0].
> +
> +bit (6)	    : ETMv4_MODE_CTXID
> +description : Set to enable context ID tracing if supported in hardware [IDR2].
> +
> +bit (7)	    : ETM_MODE_VMID
> +description : Set to enable virtual machine ID tracing if supported [IDR2].
> +
> +bit (11)    : ETMv4_MODE_TIMESTAMP
> +description : Set to enable timestamp generation if supported [IDR0].
> +
> +bit (12)    : ETM_MODE_RETURNSTACK
> +description : Set to enable trace return stack use if supported [IDR0].
> +
> +bit (13-14) : ETM_MODE_QELEM(val)
> +description : ‘val’ determines level of Q element support enabled if
> +	    implemented by the ETM [IDR0]
> +
> +bit (19)    : ETM_MODE_ATB_TRIGGER
> +description : Set to enable the ATBTRIGGER bit in the event control register
> +	    [EVENTCTLR1] if supported [IDR5].
> +
> +bit (20)    : ETM_MODE_LPOVERRIDE
> +description : Set to enable the LPOVERRIDE bit in the event control register
> +	    [EVENTCTLR1], if supported [IDR5].
> +
> +bit (21)    : ETM_MODE_ISTALL_EN
> +description : Set to enable the ISTALL bit in the stall control register
> +	    [STALLCTLR]
> +
> +bit (23)    : ETM_MODE_INSTPRIO
> +description : Set to enable the INSTPRIORITY bit in the stall control register
> +	    [STALLCTLR] , if supported [IDR0].
> +
> +bit (24)    : ETM_MODE_NOOVERFLOW
> +description : Set to enable the NOOVERFLOW bit in the stall control register
> +	    [STALLCTLR], if supported [IDR3].
> +
> +bit (25)    : ETM_MODE_TRACE_RESET
> +description : Set to enable the TRCRESET bit in the viewinst control register
> +	    [VICTLR] , if supported [IDR3].
> +
> +bit (26)    : ETM_MODE_TRACE_ERR
> +description : Set to enable the TRCCTRL bit in the viewinst control register
> +	    [VICTLR].
> +
> +bit (27)    : ETM_MODE_VIEWINST_STARTSTOP
> +description : Set the initial state value of the ViewInst start / stop logic
> +	    in the viewinst control register [VICTLR]
> +
> +bit (30)    : ETM_MODE_EXCL_KERN
> +description : Set default trace setup to exclude kernel mode trace (see note a)
> +
> +bit (31)    : ETM_MODE_EXCL_USER
> +description : Set default trace setup to exclude user space trace (see note a)
> +
> +Note a) On startup the ETM is programmed to trace the complete address space
> +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to
> +set EL exclude bits for NS state in either user space (EL0) or kernel space
> +(EL1) in the address range comparator. (the default setting excludes all
> +secure EL, and NS EL2)
> +
> +Once the reset parameter has been used, and/or custom programming has been
> +implemented - using these bits will result in the EL bits for address
> +comparator 0 being set in the same way.
> +
> +Note b) Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with
> +data trace. As A profile data trace is architecturally prohibited in ETMv4,
> +these have been omitted here. Possible uses could be where a kernel has
> +support for control of R or M profile infrastructure as part of a heterogeneous
> +system.
> +
> +Bits 17, 28-29 are unused.
> +
> diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight/coresight.txt
> similarity index 100%
> rename from Documentation/trace/coresight.txt
> rename to Documentation/trace/coresight/coresight.txt
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 783569e3c4b4..777b77fde29b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1582,8 +1582,7 @@ R:	Suzuki K Poulose <suzuki.poulose@arm.com>
>  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>  S:	Maintained
>  F:	drivers/hwtracing/coresight/*
> -F:	Documentation/trace/coresight.txt
> -F:	Documentation/trace/coresight-cpu-debug.txt
> +F:	Documentation/trace/coresight/*
>  F:	Documentation/devicetree/bindings/arm/coresight.txt
>  F:	Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
>  F:	Documentation/ABI/testing/sysfs-bus-coresight-devices-*
> -- 
> 2.17.1
> 

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Re: [PATCH 8/8] coresight: etm4x: docs: Additional documentation for ETM4x.

[Mathieu Poirier]

On Mon, Aug 19, 2019 at 09:57:20PM +0100, Mike Leach wrote:
> Update existing docs for new sysfs API features.
> Add new ETMv4 reference document for sysfs programming.
> Move coresight documentation to common directory.
>

I also get the following warnings when adding the patch:

$ git am 0008-coresight-etm4x-docs-Additional-documentation-for-ET.patch
Applying: coresight: etm4x: docs: Additional documentation for ETM4x.
.git/rebase-apply/patch:620: space before tab in indent.
       	 	bitfield up to 32 bits setting trace features.
.git/rebase-apply/patch:950: space before tab in indent.
       	      			    ; range comparator
.git/rebase-apply/patch:954: space before tab in indent.
       	      			    ; address comparator
.git/rebase-apply/patch:1057: new blank line at EOF.
+
warning: 4 lines add whitespace errors.
 
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
>  .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++---
>  .../{ => coresight}/coresight-cpu-debug.txt   |   0
>  .../coresight/coresight-etm4x-reference.txt   | 459 ++++++++++++++++++
>  .../trace/{ => coresight}/coresight.txt       |   0
>  MAINTAINERS                                   |   3 +-
>  5 files changed, 575 insertions(+), 70 deletions(-)
>  rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%)
>  create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt
>  rename Documentation/trace/{ => coresight}/coresight.txt (100%)
> 
> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> index 36258bc1b473..112c50ae9986 100644
> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> @@ -1,4 +1,4 @@
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/enable_source
> +What:		/sys/bus/coresight/devices/etm<N>/enable_source
>  Date:		April 2015
>  KernelVersion:  4.01
>  Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
> @@ -8,82 +8,82 @@ Description:	(RW) Enable/disable tracing on this specific trace entiry.
>  		of coresight components linking the source to the sink is
>  		configured and managed automatically by the coresight framework.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/cpu
> +What:		/sys/bus/coresight/devices/etm<N>/cpu
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) The CPU this tracing entity is associated with.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
> +What:		/sys/bus/coresight/devices/etm<N>/nr_pe_cmp
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of PE comparator inputs that are
>  		available for tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
> +What:		/sys/bus/coresight/devices/etm<N>/nr_addr_cmp
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of address comparator pairs that are
>  		available for tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
> +What:		/sys/bus/coresight/devices/etm<N>/nr_cntr
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of counters that are available for
>  		tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
> +What:		/sys/bus/coresight/devices/etm<N>/nr_ext_inp
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates how many external inputs are implemented.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/numcidc
> +What:		/sys/bus/coresight/devices/etm<N>/numcidc
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of Context ID comparators that are
>  		available for tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/numvmidc
> +What:		/sys/bus/coresight/devices/etm<N>/numvmidc
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of VMID comparators that are available
>  		for tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
> +What:		/sys/bus/coresight/devices/etm<N>/nrseqstate
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of sequencer states that are
>  		implemented.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_resource
> +What:		/sys/bus/coresight/devices/etm<N>/nr_resource
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of resource selection pairs that are
>  		available for tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
> +What:		/sys/bus/coresight/devices/etm<N>/nr_ss_cmp
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Indicates the number of single-shot comparator controls that
>  		are available for tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/reset
> +What:		/sys/bus/coresight/devices/etm<N>/reset
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(W) Cancels all configuration on a trace unit and set it back
>  		to its boot configuration.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mode
> +What:		/sys/bus/coresight/devices/etm<N>/mode
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> @@ -91,302 +91,349 @@ Description: 	(RW) Controls various modes supported by this ETM, for example
>  		P0 instruction tracing, branch broadcast, cycle counting and
>  		context ID tracing.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/pe
> +What:		/sys/bus/coresight/devices/etm<N>/pe
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls which PE to trace.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/event
> +What:		/sys/bus/coresight/devices/etm<N>/event
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls the tracing of arbitrary events from bank 0 to 3.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/event_instren
> +What:		/sys/bus/coresight/devices/etm<N>/event_instren
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls the behavior of the events in bank 0 to 3.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/event_ts
> +What:		/sys/bus/coresight/devices/etm<N>/event_ts
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls the insertion of global timestamps in the trace
>  		streams.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/syncfreq
> +What:		/sys/bus/coresight/devices/etm<N>/syncfreq
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls how often trace synchronization requests occur.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
> +What:		/sys/bus/coresight/devices/etm<N>/cyc_threshold
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Sets the threshold value for cycle counting.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
> +What:		/sys/bus/coresight/devices/etm<N>/bb_ctrl
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls which regions in the memory map are enabled to
>  		use branch broadcasting.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/event_vinst
> +What:		/sys/bus/coresight/devices/etm<N>/event_vinst
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls instruction trace filtering.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst
> +What:		/sys/bus/coresight/devices/etm<N>/s_exlevel_vinst
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) In Secure state, each bit controls whether instruction
>  		tracing is enabled for the corresponding exception level.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst
> +What:		/sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) In non-secure state, each bit controls whether instruction
>  		tracing is enabled for the corresponding exception level.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_idx
> +What:		/sys/bus/coresight/devices/etm<N>/addr_idx
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Select which address comparator or pair (of comparators) to
>  		work with.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype
> +What:		/sys/bus/coresight/devices/etm<N>/addr_instdatatype
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls what type of comparison the trace unit performs.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_single
> +What:		/sys/bus/coresight/devices/etm<N>/addr_single
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Used to setup single address comparator values.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/addr_range
> +What:		/sys/bus/coresight/devices/etm<N>/addr_range
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Used to setup address range comparator values.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_idx
> +What:		/sys/bus/coresight/devices/etm<N>/seq_idx
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Select which sequensor.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_state
> +What:		/sys/bus/coresight/devices/etm<N>/seq_state
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Use this to set, or read, the sequencer state.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_event
> +What:		/sys/bus/coresight/devices/etm<N>/seq_event
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Moves the sequencer state to a specific state.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event
> +What:		/sys/bus/coresight/devices/etm<N>/seq_reset_event
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Moves the sequencer to state 0 when a programmed event
>  		occurs.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_idx
> +What:		/sys/bus/coresight/devices/etm<N>/cntr_idx
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Select which counter unit to work with.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/cntrldvr
> +What:		/sys/bus/coresight/devices/etm<N>/cntrldvr
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) This sets or returns the reload count value of the
>  		specific counter.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_val
> +What:		/sys/bus/coresight/devices/etm<N>/cntr_val
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) This sets or returns the current count value of the
>                  specific counter.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl
> +What:		/sys/bus/coresight/devices/etm<N>/cntr_ctrl
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls the operation of the selected counter.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/res_idx
> +What:		/sys/bus/coresight/devices/etm<N>/res_idx
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Select which resource selection unit to work with.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/res_ctrl
> +What:		/sys/bus/coresight/devices/etm<N>/res_ctrl
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description: 	(RW) Controls the selection of the resources in the trace unit.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx
> +What:		/sys/bus/coresight/devices/etm<N>/ctxid_idx
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Select which context ID comparator to work with.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid
> +What:		/sys/bus/coresight/devices/etm<N>/ctxid_pid
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Get/Set the context ID comparator value to trigger on.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks
> +What:		/sys/bus/coresight/devices/etm<N>/ctxid_masks
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Mask for all 8 context ID comparator value
>  		registers (if implemented).
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_idx
> +What:		/sys/bus/coresight/devices/etm<N>/vmid_idx
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Select which virtual machine ID comparator to work with.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_val
> +What:		/sys/bus/coresight/devices/etm<N>/vmid_val
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Get/Set the virtual machine ID comparator value to
>  		trigger on.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/vmid_masks
> +What:		/sys/bus/coresight/devices/etm<N>/vmid_masks
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(RW) Mask for all 8 virtual machine ID comparator value
>  		registers (if implemented).
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr
> +What:		/sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(RW) Set the Exception Level matching bits for secure and
> +		non-secure exception levels.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(RW) Access the start stop control register for PE input
> +		comparators.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/addr_cmp_view
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(R) Print the current settings for the selected address
> +		comparator.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/sshot_idx
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(RW) Select the single shot control register to access.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/sshot_ctrl
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(RW) Access the selected single shot control register.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/sshot_status
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(R) Print the current value of the selected single shot
> +		status register.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl
> +Date:		August 2019
> +KernelVersion:	5.4
> +Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> +Description:	(RW) Access the selected single show PE comparator control
> +		register.
> +
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the OS Lock Status Register (0x304).
>  		The value it taken directly  from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Power Down Control Register
>  		(0x310).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Power Down Status Register
>  		(0x314).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trclsr
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the SW Lock Status Register
>  		(0xFB4).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Authentication Status Register
>  		(0xFB8).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevid
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Device ID Register
>  		(0xFC8).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Device Type Register
>  		(0xFCC).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Peripheral ID0 Register
>  		(0xFE0).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Peripheral ID1 Register
>  		(0xFE4).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Peripheral ID2 Register
>  		(0xFE8).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the Peripheral ID3 Register
>  		(0xFEC).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcconfig
>  Date:		February 2016
>  KernelVersion:	4.07
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the trace configuration register
>  		(0x010) as currently set by SW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid
> +What:		/sys/bus/coresight/devices/etm<N>/mgmt/trctraceid
>  Date:		February 2016
>  KernelVersion:	4.07
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Print the content of the trace ID register (0x040).
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr0
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns the tracing capabilities of the trace unit (0x1E0).
>  		The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr1
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns the tracing capabilities of the trace unit (0x1E4).
>  		The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr2
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> @@ -394,7 +441,7 @@ Description:	(R) Returns the maximum size of the data value, data address,
>  		VMID, context ID and instuction address in the trace unit
>  		(0x1E8).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr3
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> @@ -403,42 +450,42 @@ Description:	(R) Returns the value associated with various resources
>  		architecture specification for more details (0x1E8).
>  		The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr4
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns how many resources the trace unit supports (0x1F0).
>  		The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr5
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns how many resources the trace unit supports (0x1F4).
>  		The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr8
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns the maximum speculation depth of the instruction
>  		trace stream. (0x180).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr9
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns the number of P0 right-hand keys that the trace unit
>  		can use (0x184).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr10
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
>  Description:	(R) Returns the number of P1 right-hand keys that the trace unit
>  		can use (0x188).  The value is taken directly from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr11
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> @@ -446,7 +493,7 @@ Description:	(R) Returns the number of special P1 right-hand keys that the
>  		trace unit can use (0x18C).  The value is taken directly from
>  		the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr12
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> @@ -454,7 +501,7 @@ Description:	(R) Returns the number of conditional P1 right-hand keys that
>  		the trace unit can use (0x190).  The value is taken directly
>  		from the HW.
>  
> -What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13
> +What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr13
>  Date:		April 2015
>  KernelVersion:	4.01
>  Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
> diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight/coresight-cpu-debug.txt
> similarity index 100%
> rename from Documentation/trace/coresight-cpu-debug.txt
> rename to Documentation/trace/coresight/coresight-cpu-debug.txt
> diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.txt b/Documentation/trace/coresight/coresight-etm4x-reference.txt
> new file mode 100644
> index 000000000000..72e81bbbef43
> --- /dev/null
> +++ b/Documentation/trace/coresight/coresight-etm4x-reference.txt
> @@ -0,0 +1,459 @@
> +ETMv4 sysfs linux driver programming reference - v2.
> +====================================================
> +
> +Supplement to existing ETMv4 driver documentation.
> +
> +Sysfs files and directories
> +---------------------------
> +
> +Root: /sys/bus/coresight/devices/etm<N>
> +
> +
> +The following paragraphs explain the association between sysfs files and the
> +ETMv4 registers that they effect. Note the register names are given without
> +the ‘TRC’ prefix.
> +
> +File		: mode (rw)
> +Trace Registers	: {CONFIGR + others}
> +Notes 		: Bit select trace features. See ‘mode’ section below. Bits
> +		in this will cause equivalent programming of trace config and
> +		other registers to enable the features requested.
> +Syntax & eg	: 'echo bitfield > mode'
> +       	 	bitfield up to 32 bits setting trace features.
> +Example		: $> echo 0x > mode
> +
> +File		: reset (wo)
> +Trace Registers	: All
> +Notes 		: Reset all programming to trace nothing / no logic programmed.
> +Syntax		: 'echo 1 > reset'
> +
> +File		: enable_source (wo)
> +Trace Registers	: PRGCTLR, All hardware regs.
> +Notes 		:  >0: Programs up the hardware with the current values held in
> +		the driver and enables trace.
> +		0: disable trace hardware.
> +Syntax		: 'echo 1 > enable_source'
> +
> +File		: cpu (ro)
> +Trace Registers	: None.
> +Notes 		: CPU ID that this ETM is attached to.
> +Example		:$> cat cpu
> +		$> 0
> +
> +File		: addr_idx (rw)
> +Trace Registers	: None.
> +Notes 		: Virtual register to index address comparator and range
> +		features. Set index for first of the pair in a range.
> +Syntax		: 'echo idx > addr_idx'
> +		Where idx <  nr_addr_cmp x 2
> +
> +File		: addr_range (rw)
> +Trace Registers	: ACVR[idx, idx+1], VIIECTLR
> +Notes 		: Pair of addresses for a range selected by addr_idx. Include
> +		/ exclude according to the optional parameter, or if omitted
> +		uses the current ‘mode’ setting. Select comparator range in
> +		control register. Error if index is odd value.
> +Depends		: mode, addr_idx
> +Syntax		: 'echo addr1 addr2 [exclude] > addr_range'
> +		Where addr1 and addr2 define the range and addr1 < addr2.
> +		Optional exclude value - 0 for include, 1 for exclude.
> +Example		: $> echo 0x0000 0x2000 0 > addr_range
> +
> +File		: addr_single (rw)
> +Trace Registers	: ACVR[idx]
> +Notes 		: Set a single address comparator according to addr_idx. This
> +		is used if the address comparator is used as part of event
> +		generation logic etc.
> +Depends		: addr_idx
> +Syntax		: 'echo addr1 > addr_single'
> +
> +File		: addr_start (rw)
> +Trace Registers	: ACVR[idx], VISSCTLR
> +Notes 		: Set a trace start address comparator according to addr_idx.
> +		Select comparator in control register.
> +Depends		: addr_idx
> +Syntax		: 'echo addr1 > addr_start'
> +
> +File		: addr_stop (rw)
> +Trace Registers	: ACVR[idx], VISSCTLR
> +Notes 		: Set a trace stop address comparator according to addr_idx.
> +		Select comparator in control register.
> +Depends		: addr_idx
> +Syntax		: 'echo addr1 > addr_stop'
> +
> +File		: addr_context (rw)
> +Trace Registers	: ACATR[idx,{6:4}]
> +Notes 		: Link context ID comparator to address comparator addr_idx
> +Depends		: addr_idx.
> +Syntax		: 'echo ctxt_idx > addr_context'
> +		Where ctxt_idx is the index of the linked context id / vmid
> +		comparator.
> +
> +File		: addr_ctxtype (rw)
> +Trace Registers	: ACATR[idx,{3:2}]
> +Notes 		: Input value string. Set type for linked context ID comparator
> +Depends		: addr_idx
> +Syntax		: 'echo type > addr_ctxtype'
> +		Type one of {all, vmid, ctxid, none}
> +Example		: $> echo ctxid > addr_ctxtype
> +
> +File		: addr_exlevel_s_ns (rw)
> +Trace Registers	: ACATR[idx,{14:8}]
> +Notes 		: Set the ELx secure and non-secure  matching bits for the
> +		selected address comparator
> +Depends		: addr_idx
> +Syntax		: 'echo val > addr_exlevel_s_ns'
> +		val is a 7 bit value for exception levels to exclude. Input
> +		value shifted to correct bits in register.
> +Example		: $> echo 0x4F > addr_exlevel_s_ns
> +
> +File		: addr_instdatatype (rw)
> +Trace Registers	: ACATR[idx,{1:0}]
> +Notes 		: Set the comparator address type for matching. Driver only
> +		supports setting instruction address type.
> +Depends		: addr_idx
> +
> +File		: addr_cmp_view (ro)
> +Trace Registers	: ACVR[idx, idx+1], ACATR[idx], VIIECTLR
> +Notes 		: Read the currently selected address comparator. If part of
> +		address range then display both addresses.
> +Depends		: addr_idx
> +Syntax		: 'cat addr_cmp_view'
> +Example		: $> cat addr_cmp_view
> +		addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)
> +
> +File		: nr_addr_cmp (ro)
> +Trace Registers	: From IDR4
> +Notes 		: Number of address comparator pairs
> +
> +File		: sshot_idx (rw)
> +Trace Registers	: None
> +Notes 		: Select  single shot register set.
> +
> +File		: sshot_ctrl (rw)
> +Trace Registers	: SSCCR[idx]
> +Notes 		: Access a single shot comparator control register.
> +Depends		: sshot_idx
> +Syntax		: 'echo val > sshot_ctrl'
> +		Writes val into the selected control register.
> +
> +File		: sshot_status (ro)
> +Trace Registers	: SSCSR[idx]
> +Notes 		: Read a single shot comparator status register
> +Depends		: sshot_idx
> +Syntax		: 'cat sshot_status'
> +		Read status.
> +Example		: $> cat sshot_status
> +		0x1
> +
> +File		: sshot_pe_ctrl (rw)
> +Trace Registers	: SSPCICR[idx]
> +Notes 		: Access a single shot PE comparator input control register.
> +Depends		: sshot_idx
> +Syntax		: echo val > sshot_pe_ctrl
> +		Writes val into the selected control register.
> +
> +File		: ns_exlevel_vinst (rw)
> +Trace Registers	: VICTLR{23:20}
> +Notes 		: Program non-secure exception level filters. Set / clear NS
> +		exception filter bits. Setting ‘1’ excludes trace from the
> +		exception level.
> +Syntax		: 'echo bitfield > ns_exlevel_viinst'
> +		Where bitfield contains bits to set clear for EL0 to EL2
> +Example		: %> echo 0x4 > ns_exlevel_viinst
> +		; Exclude EL2 NS trace.
> +
> +File		: vinst_pe_cmp_start_stop (rw)
> +Trace Registers	: VIPCSSCTLR
> +Notes 		: Access PE start stop comparator input control registers
> +
> +File		: bb_ctrl (rw)
> +Trace Registers	: BBCTLR
> +Notes 		: Define ranges that Branch Broadcast will operate in.
> +		Default (0x0) is all addresses.
> +Depends		: BB enabled.
> +
> +File		: cyc_threshold (rw)
> +Trace Registers	: CCCTLR
> +Notes 		: Set the threshold for which cycle counts will be emitted.
> +		Error if attempt to set below minimum defined in IDR3, masked
> +		to width of valid bits.
> +Depends		: CC enabled.
> +
> +File		: syncfreq (rw)
> +Trace Registers	: SYNCPR
> +Notes 		: Set trace synchronisation period. Power of 2 value, 0 (off)
> +		or 8-20. Driver defaults to 12 (every 4096 bytes).
> +
> +File		: cntr_idx (rw)
> +Trace Registers	: none
> +Notes 		: Select the counter to access
> +Syntax		: 'echo idx > cntr_idx'
> +		Where idx <  nr_cntr
> +
> +File		: cntr_ctrl (rw)
> +Trace Registers	: CNTCTLR[idx]
> +Notes 		: Set counter control value
> +Depends		: cntr_idx
> +Syntax		: 'echo val > cntr_ctrl'
> +		Where val is per ETMv4 spec.
> +
> +File		: cntrldvr (rw)
> +Trace Registers	: CNTRLDVR[idx]
> +Notes 		: Set counter reload value
> +Depends		: cntr_idx
> +Syntax		: 'echo val > cntrldvr'
> +		Where val is per ETMv4 spec.
> +
> +File		: nr_cntr (ro)
> +Trace Registers	: From IDR5
> +Notes 		: Number of counters implemented.
> +
> +File		: ctxid_idx (rw)
> +Trace Registers	: None
> +Notes 		: Select the context ID comparator to access
> +Syntax		: 'echo idx > ctxid_idx'
> +		Where idx <  numcidc
> +
> +File		: ctxid_pid (rw)
> +Trace Registers	: CIDCVR[idx]
> +Notes 		: Set the context ID comparator value
> +Depends		: ctxid_idx
> +
> +File		: ctxid_masks (rw)
> +Trace Registers	: CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7>
> +Notes 		: Pair of values to set the byte masks for 1-8 context ID
> +		comparators. Automatically clears masked bytes to 0 in CID
> +		value registers.
> +Syntax		: 'echo m3m2m1m0 [m7m6m5m4] > ctxid_masks'
> +		32 bit values made up of mask bytes, where mN represents a
> +		byte mask value for Ctxt ID comparator N.
> +		Second value not required on systems that have fewer than 4
> +		context ID comparators
> +
> +File		: numcidc (ro)
> +Trace Registers	: From IDR4
> +Notes 		: Number of Context ID comparators
> +
> +File		: vmid_idx (rw)
> +Trace Registers	: None
> +Notes 		: Select the VM ID comparator to access.
> +Syntax		: 'echo idx > vmid_idx'
> +		Where idx <  numvmidc
> +
> +File		: vmid_val (rw)
> +Trace Registers	: VMIDCVR[idx]
> +Notes 		: Set the VM ID comparator value
> +Depends		: vmid_idx
> +
> +File		: vmid_masks (rw)
> +Trace Registers	: VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7>
> +Notes 		: Pair of values to set the byte masks for 1-8 VM ID
> +		comparators. Automatically clears masked bytes to 0 in VMID
> +		value registers.
> +Syntax		: 'echo m3m2m1m0 [m7m6m5m4] > vmid_masks'
> +		Where mN represents a byte mask value for VMID comparator N.
> +		Second value not required on systems that have fewer than
> +		4 VMID comparators.
> +
> +File		: numvmidc (ro)
> +Trace Registers	: From IDR4
> +Notes 		: Number of VMID comparators
> +
> +File		: res_idx (rw)
> +Trace Registers	: None.
> +Notes 		: Select the resource selector control to access. Must be 2 or
> +		higher as selectors 0 and 1 are hardwired.
> +Syntax		: 'echo idx > res_idx'
> +		Where 2 <= idx <  nr_resource x 2
> +
> +File		: res_ctrl (rw)
> +Trace Registers	: RSCTLR[idx]
> +Notes 		: Set resource selector control value. Value per ETMv4 spec.
> +Depends		: res_idx
> +Syntax		: 'echo val > res_cntr'
> +		Where val is per ETMv4 spec.
> +
> +File		: nr_resource (ro)
> +Trace Registers	: From IDR4
> +Notes 		: Number of resource selector pairs
> +
> +File		: event (rw)
> +Trace Registers	: EVENTCTRL0R
> +Notes 		: Set up to 4 implemented event fields.
> +Syntax		: 'echo ev3ev2ev1ev0 > event'
> +		Where evN is an 8 bit event field. Up to 4 event fields make up
> +		the 32bit input value. Number of valid fields implementation
> +		dependent defined in IDR0.
> +
> +File		: event_instren (rw)
> +Trace Registers	: EVENTCTRL1R
> +Notes 		: Choose events which insert event packets into trace stream.
> +Depends		: EVENTCTRL0R
> +Syntax		: 'echo bitfield > event_instren'
> +		Where bitfield is up to 4 bits according to number of event
> +		fields.
> +
> +File		: event_ts (rw)
> +Trace Registers	: TSCTLR
> +Notes 		: Set the event that will generate timestamp requests.
> +Depends		: TS activated
> +Syntax		: 'echo evfield > event_ts'
> +		Where evfield is an 8 bit event selector.
> +
> +File		: seq_idx (rw)
> +Trace Registers	: None
> +Notes 		: Sequencer event register select - 0 to 2
> +
> +
> +File		: seq_state (rw)
> +Trace Registers	: SEQSTR
> +Notes 		: Sequencer current state - 0 to 3.
> +
> +File		: seq_event (rw)
> +Trace Registers	: SEQEVR[idx]
> +Notes 		: State transition event registers
> +Depends		: seq_idx
> +Syntax		: 'echo evBevF > seq_event'
> +		Where evBevF is a 16 bit value made up of two event selectors,
> +		evB - back, evF - forwards.
> +
> +File		: seq_reset_event (rw)
> +Trace Registers	: SEQRSTEVR
> +Notes 		: Sequencer reset event
> +Syntax		: 'echo evfield > seq_reset_event'
> +		Where evfield is an 8 bit event selector.
> +
> +File		: nrseqstate (ro)
> +Trace Registers	: From IDR5
> +Notes 		: Number of sequencer states (0 or 4)
> +
> +File		: nr_pe_cmp (ro)
> +Trace Registers	: From IDR4
> +Notes 		: Number of PE comparator inputs
> +
> +File		: nr_ext_inp (ro)
> +Trace Registers	: From IDR5
> +Notes 		: Number of external inputs
> +
> +File		: nr_ss_cmp (ro)
> +Trace Registers	: From IDR4
> +Notes 		: Number of Single Shot control registers
> +
> +Note: When programming any address comparator the driver will tag the
> +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag
> +is set, then only the values can be changed using the same sysfs file / type
> +used to program it.
> +
> +Thus:-
> +% echo 0 > addr_idx		    ; select address comparator 0
> +% echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0 and 1.
> +% echo 0x2000 > addr_start	    ; this will error as comparator 0 is a
> +       	      			    ; range comparator
> +% echo 2 > addr_idx 		    ; select address comparator 2
> +% echo 0x2000 > addr_start	    ; this is OK as comparator 2 is unused,
> +% echo 0x3000 > addr_stop	    ; this will error as comparator 2 a start
> +       	      			    ; address comparator
> +% echo 2 > addr_idx 		    ; select address comparator 3
> +% echo 0x3000 > addr_stop	    ; this is OK
> +
> +To remove programming on all the comparators (and all the other hardware) use
> +the reset parameter:
> +
> +% echo 1 > reset
> +
> +The ‘mode’ sysfs parameter.
> +---------------------------
> +
> +This is a bitfield selection parameter that sets the overall trace mode for the
> +ETM. The table below describes the bits, using the defines from the driver
> +source file, along with a description of the feature these represent. Many
> +features are optional and therefore dependent on implementation in the
> +hardware.
> +
> +Bit assignements shown below:-
> +
> +bit (0)	    : #define ETM_MODE_EXCLUDE
> +description : This is the default value for the include / exclude function when
> +	      setting address ranges. Set 1 for exclude range. When the mode
> +	      parameter is set this value is applied to the currently indexed
> +	      address range.
> +
> +bit (4)	    : #define ETM_MODE_BB
> +description : Set to enable branch broadcast if supported in hardware [IDR0].
> +
> +bit (5)	    : #define ETMv4_MODE_CYCACC
> +description : Set to enable cycle accurate trace if supported [IDR0].
> +
> +bit (6)	    : ETMv4_MODE_CTXID
> +description : Set to enable context ID tracing if supported in hardware [IDR2].
> +
> +bit (7)	    : ETM_MODE_VMID
> +description : Set to enable virtual machine ID tracing if supported [IDR2].
> +
> +bit (11)    : ETMv4_MODE_TIMESTAMP
> +description : Set to enable timestamp generation if supported [IDR0].
> +
> +bit (12)    : ETM_MODE_RETURNSTACK
> +description : Set to enable trace return stack use if supported [IDR0].
> +
> +bit (13-14) : ETM_MODE_QELEM(val)
> +description : ‘val’ determines level of Q element support enabled if
> +	    implemented by the ETM [IDR0]
> +
> +bit (19)    : ETM_MODE_ATB_TRIGGER
> +description : Set to enable the ATBTRIGGER bit in the event control register
> +	    [EVENTCTLR1] if supported [IDR5].
> +
> +bit (20)    : ETM_MODE_LPOVERRIDE
> +description : Set to enable the LPOVERRIDE bit in the event control register
> +	    [EVENTCTLR1], if supported [IDR5].
> +
> +bit (21)    : ETM_MODE_ISTALL_EN
> +description : Set to enable the ISTALL bit in the stall control register
> +	    [STALLCTLR]
> +
> +bit (23)    : ETM_MODE_INSTPRIO
> +description : Set to enable the INSTPRIORITY bit in the stall control register
> +	    [STALLCTLR] , if supported [IDR0].
> +
> +bit (24)    : ETM_MODE_NOOVERFLOW
> +description : Set to enable the NOOVERFLOW bit in the stall control register
> +	    [STALLCTLR], if supported [IDR3].
> +
> +bit (25)    : ETM_MODE_TRACE_RESET
> +description : Set to enable the TRCRESET bit in the viewinst control register
> +	    [VICTLR] , if supported [IDR3].
> +
> +bit (26)    : ETM_MODE_TRACE_ERR
> +description : Set to enable the TRCCTRL bit in the viewinst control register
> +	    [VICTLR].
> +
> +bit (27)    : ETM_MODE_VIEWINST_STARTSTOP
> +description : Set the initial state value of the ViewInst start / stop logic
> +	    in the viewinst control register [VICTLR]
> +
> +bit (30)    : ETM_MODE_EXCL_KERN
> +description : Set default trace setup to exclude kernel mode trace (see note a)
> +
> +bit (31)    : ETM_MODE_EXCL_USER
> +description : Set default trace setup to exclude user space trace (see note a)
> +
> +Note a) On startup the ETM is programmed to trace the complete address space
> +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to
> +set EL exclude bits for NS state in either user space (EL0) or kernel space
> +(EL1) in the address range comparator. (the default setting excludes all
> +secure EL, and NS EL2)
> +
> +Once the reset parameter has been used, and/or custom programming has been
> +implemented - using these bits will result in the EL bits for address
> +comparator 0 being set in the same way.
> +
> +Note b) Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with
> +data trace. As A profile data trace is architecturally prohibited in ETMv4,
> +these have been omitted here. Possible uses could be where a kernel has
> +support for control of R or M profile infrastructure as part of a heterogeneous
> +system.
> +
> +Bits 17, 28-29 are unused.
> +
> diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight/coresight.txt
> similarity index 100%
> rename from Documentation/trace/coresight.txt
> rename to Documentation/trace/coresight/coresight.txt
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 783569e3c4b4..777b77fde29b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1582,8 +1582,7 @@ R:	Suzuki K Poulose <suzuki.poulose@arm.com>
>  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>  S:	Maintained
>  F:	drivers/hwtracing/coresight/*
> -F:	Documentation/trace/coresight.txt
> -F:	Documentation/trace/coresight-cpu-debug.txt
> +F:	Documentation/trace/coresight/*
>  F:	Documentation/devicetree/bindings/arm/coresight.txt
>  F:	Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
>  F:	Documentation/ABI/testing/sysfs-bus-coresight-devices-*
> -- 
> 2.17.1
> 

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Re: [PATCH 8/8] coresight: etm4x: docs: Additional documentation for ETM4x.

[Mike Leach]

Hi Mathieu,

I assume you want the split to be ? :-
1. the update in Documentation/ARM/testing/sysfs-bus-coresight-devices-etm4x
2. the moving of coresight docs to their new common directory.
3. the addition of the new etm4x doc

On Tue, 27 Aug 2019 at 23:34, Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> On Mon, Aug 19, 2019 at 09:57:20PM +0100, Mike Leach wrote:
> > Update existing docs for new sysfs API features.
> > Add new ETMv4 reference document for sysfs programming.
> > Move coresight documentation to common directory.
> >
>
> I also get the following warnings when adding the patch:
>
> $ git am 0008-coresight-etm4x-docs-Additional-documentation-for-ET.patch
> Applying: coresight: etm4x: docs: Additional documentation for ETM4x.
> .git/rebase-apply/patch:620: space before tab in indent.
>                 bitfield up to 32 bits setting trace features.
> .git/rebase-apply/patch:950: space before tab in indent.
>                                     ; range comparator
> .git/rebase-apply/patch:954: space before tab in indent.
>                                     ; address comparator
> .git/rebase-apply/patch:1057: new blank line at EOF.
> +
> warning: 4 lines add whitespace errors.
>

OK - I'll re-look at this, but don't recall seeing any errors myself
& al cleared by checkpatch.

Regards

Mike


> > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > ---
> >  .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++---
> >  .../{ => coresight}/coresight-cpu-debug.txt   |   0
> >  .../coresight/coresight-etm4x-reference.txt   | 459 ++++++++++++++++++
> >  .../trace/{ => coresight}/coresight.txt       |   0
> >  MAINTAINERS                                   |   3 +-
> >  5 files changed, 575 insertions(+), 70 deletions(-)
> >  rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%)
> >  create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt
> >  rename Documentation/trace/{ => coresight}/coresight.txt (100%)
> >
> > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> > index 36258bc1b473..112c50ae9986 100644
> > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> > @@ -1,4 +1,4 @@
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/enable_source
> > +What:                /sys/bus/coresight/devices/etm<N>/enable_source
> >  Date:                April 2015
> >  KernelVersion:  4.01
> >  Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
> > @@ -8,82 +8,82 @@ Description:        (RW) Enable/disable tracing on this specific trace entiry.
> >               of coresight components linking the source to the sink is
> >               configured and managed automatically by the coresight framework.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/cpu
> > +What:                /sys/bus/coresight/devices/etm<N>/cpu
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) The CPU this tracing entity is associated with.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
> > +What:                /sys/bus/coresight/devices/etm<N>/nr_pe_cmp
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Indicates the number of PE comparator inputs that are
> >               available for tracing.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
> > +What:                /sys/bus/coresight/devices/etm<N>/nr_addr_cmp
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Indicates the number of address comparator pairs that are
> >               available for tracing.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
> > +What:                /sys/bus/coresight/devices/etm<N>/nr_cntr
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Indicates the number of counters that are available for
> >               tracing.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
> > +What:                /sys/bus/coresight/devices/etm<N>/nr_ext_inp
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Indicates how many external inputs are implemented.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/numcidc
> > +What:                /sys/bus/coresight/devices/etm<N>/numcidc
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Indicates the number of Context ID comparators that are
> >               available for tracing.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/numvmidc
> > +What:                /sys/bus/coresight/devices/etm<N>/numvmidc
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Indicates the number of VMID comparators that are available
> >               for tracing.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
> > +What:                /sys/bus/coresight/devices/etm<N>/nrseqstate
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Indicates the number of sequencer states that are
> >               implemented.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nr_resource
> > +What:                /sys/bus/coresight/devices/etm<N>/nr_resource
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Indicates the number of resource selection pairs that are
> >               available for tracing.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
> > +What:                /sys/bus/coresight/devices/etm<N>/nr_ss_cmp
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Indicates the number of single-shot comparator controls that
> >               are available for tracing.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/reset
> > +What:                /sys/bus/coresight/devices/etm<N>/reset
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (W) Cancels all configuration on a trace unit and set it back
> >               to its boot configuration.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mode
> > +What:                /sys/bus/coresight/devices/etm<N>/mode
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > @@ -91,302 +91,349 @@ Description:    (RW) Controls various modes supported by this ETM, for example
> >               P0 instruction tracing, branch broadcast, cycle counting and
> >               context ID tracing.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/pe
> > +What:                /sys/bus/coresight/devices/etm<N>/pe
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Controls which PE to trace.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/event
> > +What:                /sys/bus/coresight/devices/etm<N>/event
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Controls the tracing of arbitrary events from bank 0 to 3.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/event_instren
> > +What:                /sys/bus/coresight/devices/etm<N>/event_instren
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Controls the behavior of the events in bank 0 to 3.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/event_ts
> > +What:                /sys/bus/coresight/devices/etm<N>/event_ts
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Controls the insertion of global timestamps in the trace
> >               streams.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/syncfreq
> > +What:                /sys/bus/coresight/devices/etm<N>/syncfreq
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Controls how often trace synchronization requests occur.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
> > +What:                /sys/bus/coresight/devices/etm<N>/cyc_threshold
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Sets the threshold value for cycle counting.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
> > +What:                /sys/bus/coresight/devices/etm<N>/bb_ctrl
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Controls which regions in the memory map are enabled to
> >               use branch broadcasting.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/event_vinst
> > +What:                /sys/bus/coresight/devices/etm<N>/event_vinst
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Controls instruction trace filtering.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst
> > +What:                /sys/bus/coresight/devices/etm<N>/s_exlevel_vinst
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) In Secure state, each bit controls whether instruction
> >               tracing is enabled for the corresponding exception level.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst
> > +What:                /sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) In non-secure state, each bit controls whether instruction
> >               tracing is enabled for the corresponding exception level.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/addr_idx
> > +What:                /sys/bus/coresight/devices/etm<N>/addr_idx
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Select which address comparator or pair (of comparators) to
> >               work with.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype
> > +What:                /sys/bus/coresight/devices/etm<N>/addr_instdatatype
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Controls what type of comparison the trace unit performs.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/addr_single
> > +What:                /sys/bus/coresight/devices/etm<N>/addr_single
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Used to setup single address comparator values.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/addr_range
> > +What:                /sys/bus/coresight/devices/etm<N>/addr_range
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Used to setup address range comparator values.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/seq_idx
> > +What:                /sys/bus/coresight/devices/etm<N>/seq_idx
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Select which sequensor.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/seq_state
> > +What:                /sys/bus/coresight/devices/etm<N>/seq_state
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Use this to set, or read, the sequencer state.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/seq_event
> > +What:                /sys/bus/coresight/devices/etm<N>/seq_event
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Moves the sequencer state to a specific state.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event
> > +What:                /sys/bus/coresight/devices/etm<N>/seq_reset_event
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Moves the sequencer to state 0 when a programmed event
> >               occurs.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx
> > +What:                /sys/bus/coresight/devices/etm<N>/cntr_idx
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Select which counter unit to work with.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr
> > +What:                /sys/bus/coresight/devices/etm<N>/cntrldvr
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) This sets or returns the reload count value of the
> >               specific counter.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/cntr_val
> > +What:                /sys/bus/coresight/devices/etm<N>/cntr_val
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) This sets or returns the current count value of the
> >                  specific counter.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl
> > +What:                /sys/bus/coresight/devices/etm<N>/cntr_ctrl
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Controls the operation of the selected counter.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/res_idx
> > +What:                /sys/bus/coresight/devices/etm<N>/res_idx
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Select which resource selection unit to work with.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl
> > +What:                /sys/bus/coresight/devices/etm<N>/res_ctrl
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description:         (RW) Controls the selection of the resources in the trace unit.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx
> > +What:                /sys/bus/coresight/devices/etm<N>/ctxid_idx
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (RW) Select which context ID comparator to work with.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid
> > +What:                /sys/bus/coresight/devices/etm<N>/ctxid_pid
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (RW) Get/Set the context ID comparator value to trigger on.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks
> > +What:                /sys/bus/coresight/devices/etm<N>/ctxid_masks
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (RW) Mask for all 8 context ID comparator value
> >               registers (if implemented).
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx
> > +What:                /sys/bus/coresight/devices/etm<N>/vmid_idx
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (RW) Select which virtual machine ID comparator to work with.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/vmid_val
> > +What:                /sys/bus/coresight/devices/etm<N>/vmid_val
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (RW) Get/Set the virtual machine ID comparator value to
> >               trigger on.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks
> > +What:                /sys/bus/coresight/devices/etm<N>/vmid_masks
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (RW) Mask for all 8 virtual machine ID comparator value
> >               registers (if implemented).
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr
> > +What:                /sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns
> > +Date:                August 2019
> > +KernelVersion:       5.4
> > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (RW) Set the Exception Level matching bits for secure and
> > +             non-secure exception levels.
> > +
> > +What:                /sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop
> > +Date:                August 2019
> > +KernelVersion:       5.4
> > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (RW) Access the start stop control register for PE input
> > +             comparators.
> > +
> > +What:                /sys/bus/coresight/devices/etm<N>/addr_cmp_view
> > +Date:                August 2019
> > +KernelVersion:       5.4
> > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (R) Print the current settings for the selected address
> > +             comparator.
> > +
> > +What:                /sys/bus/coresight/devices/etm<N>/sshot_idx
> > +Date:                August 2019
> > +KernelVersion:       5.4
> > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (RW) Select the single shot control register to access.
> > +
> > +What:                /sys/bus/coresight/devices/etm<N>/sshot_ctrl
> > +Date:                August 2019
> > +KernelVersion:       5.4
> > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (RW) Access the selected single shot control register.
> > +
> > +What:                /sys/bus/coresight/devices/etm<N>/sshot_status
> > +Date:                August 2019
> > +KernelVersion:       5.4
> > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (R) Print the current value of the selected single shot
> > +             status register.
> > +
> > +What:                /sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl
> > +Date:                August 2019
> > +KernelVersion:       5.4
> > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (RW) Access the selected single show PE comparator control
> > +             register.
> > +
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the OS Lock Status Register (0x304).
> >               The value it taken directly  from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the Power Down Control Register
> >               (0x310).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the Power Down Status Register
> >               (0x314).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trclsr
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the SW Lock Status Register
> >               (0xFB4).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the Authentication Status Register
> >               (0xFB8).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcdevid
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the Device ID Register
> >               (0xFC8).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the Device Type Register
> >               (0xFCC).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the Peripheral ID0 Register
> >               (0xFE0).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the Peripheral ID1 Register
> >               (0xFE4).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the Peripheral ID2 Register
> >               (0xFE8).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the Peripheral ID3 Register
> >               (0xFEC).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcconfig
> >  Date:                February 2016
> >  KernelVersion:       4.07
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the trace configuration register
> >               (0x010) as currently set by SW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid
> > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trctraceid
> >  Date:                February 2016
> >  KernelVersion:       4.07
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Print the content of the trace ID register (0x040).
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0
> > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr0
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Returns the tracing capabilities of the trace unit (0x1E0).
> >               The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1
> > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr1
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Returns the tracing capabilities of the trace unit (0x1E4).
> >               The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2
> > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr2
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > @@ -394,7 +441,7 @@ Description:      (R) Returns the maximum size of the data value, data address,
> >               VMID, context ID and instuction address in the trace unit
> >               (0x1E8).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3
> > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr3
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > @@ -403,42 +450,42 @@ Description:    (R) Returns the value associated with various resources
> >               architecture specification for more details (0x1E8).
> >               The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4
> > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr4
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Returns how many resources the trace unit supports (0x1F0).
> >               The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5
> > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr5
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Returns how many resources the trace unit supports (0x1F4).
> >               The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8
> > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr8
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Returns the maximum speculation depth of the instruction
> >               trace stream. (0x180).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9
> > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr9
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Returns the number of P0 right-hand keys that the trace unit
> >               can use (0x184).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10
> > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr10
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> >  Description: (R) Returns the number of P1 right-hand keys that the trace unit
> >               can use (0x188).  The value is taken directly from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11
> > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr11
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > @@ -446,7 +493,7 @@ Description:      (R) Returns the number of special P1 right-hand keys that the
> >               trace unit can use (0x18C).  The value is taken directly from
> >               the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12
> > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr12
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > @@ -454,7 +501,7 @@ Description:      (R) Returns the number of conditional P1 right-hand keys that
> >               the trace unit can use (0x190).  The value is taken directly
> >               from the HW.
> >
> > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13
> > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr13
> >  Date:                April 2015
> >  KernelVersion:       4.01
> >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight/coresight-cpu-debug.txt
> > similarity index 100%
> > rename from Documentation/trace/coresight-cpu-debug.txt
> > rename to Documentation/trace/coresight/coresight-cpu-debug.txt
> > diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.txt b/Documentation/trace/coresight/coresight-etm4x-reference.txt
> > new file mode 100644
> > index 000000000000..72e81bbbef43
> > --- /dev/null
> > +++ b/Documentation/trace/coresight/coresight-etm4x-reference.txt
> > @@ -0,0 +1,459 @@
> > +ETMv4 sysfs linux driver programming reference - v2.
> > +====================================================
> > +
> > +Supplement to existing ETMv4 driver documentation.
> > +
> > +Sysfs files and directories
> > +---------------------------
> > +
> > +Root: /sys/bus/coresight/devices/etm<N>
> > +
> > +
> > +The following paragraphs explain the association between sysfs files and the
> > +ETMv4 registers that they effect. Note the register names are given without
> > +the ‘TRC’ prefix.
> > +
> > +File         : mode (rw)
> > +Trace Registers      : {CONFIGR + others}
> > +Notes                : Bit select trace features. See ‘mode’ section below. Bits
> > +             in this will cause equivalent programming of trace config and
> > +             other registers to enable the features requested.
> > +Syntax & eg  : 'echo bitfield > mode'
> > +                     bitfield up to 32 bits setting trace features.
> > +Example              : $> echo 0x > mode
> > +
> > +File         : reset (wo)
> > +Trace Registers      : All
> > +Notes                : Reset all programming to trace nothing / no logic programmed.
> > +Syntax               : 'echo 1 > reset'
> > +
> > +File         : enable_source (wo)
> > +Trace Registers      : PRGCTLR, All hardware regs.
> > +Notes                :  >0: Programs up the hardware with the current values held in
> > +             the driver and enables trace.
> > +             0: disable trace hardware.
> > +Syntax               : 'echo 1 > enable_source'
> > +
> > +File         : cpu (ro)
> > +Trace Registers      : None.
> > +Notes                : CPU ID that this ETM is attached to.
> > +Example              :$> cat cpu
> > +             $> 0
> > +
> > +File         : addr_idx (rw)
> > +Trace Registers      : None.
> > +Notes                : Virtual register to index address comparator and range
> > +             features. Set index for first of the pair in a range.
> > +Syntax               : 'echo idx > addr_idx'
> > +             Where idx <  nr_addr_cmp x 2
> > +
> > +File         : addr_range (rw)
> > +Trace Registers      : ACVR[idx, idx+1], VIIECTLR
> > +Notes                : Pair of addresses for a range selected by addr_idx. Include
> > +             / exclude according to the optional parameter, or if omitted
> > +             uses the current ‘mode’ setting. Select comparator range in
> > +             control register. Error if index is odd value.
> > +Depends              : mode, addr_idx
> > +Syntax               : 'echo addr1 addr2 [exclude] > addr_range'
> > +             Where addr1 and addr2 define the range and addr1 < addr2.
> > +             Optional exclude value - 0 for include, 1 for exclude.
> > +Example              : $> echo 0x0000 0x2000 0 > addr_range
> > +
> > +File         : addr_single (rw)
> > +Trace Registers      : ACVR[idx]
> > +Notes                : Set a single address comparator according to addr_idx. This
> > +             is used if the address comparator is used as part of event
> > +             generation logic etc.
> > +Depends              : addr_idx
> > +Syntax               : 'echo addr1 > addr_single'
> > +
> > +File         : addr_start (rw)
> > +Trace Registers      : ACVR[idx], VISSCTLR
> > +Notes                : Set a trace start address comparator according to addr_idx.
> > +             Select comparator in control register.
> > +Depends              : addr_idx
> > +Syntax               : 'echo addr1 > addr_start'
> > +
> > +File         : addr_stop (rw)
> > +Trace Registers      : ACVR[idx], VISSCTLR
> > +Notes                : Set a trace stop address comparator according to addr_idx.
> > +             Select comparator in control register.
> > +Depends              : addr_idx
> > +Syntax               : 'echo addr1 > addr_stop'
> > +
> > +File         : addr_context (rw)
> > +Trace Registers      : ACATR[idx,{6:4}]
> > +Notes                : Link context ID comparator to address comparator addr_idx
> > +Depends              : addr_idx.
> > +Syntax               : 'echo ctxt_idx > addr_context'
> > +             Where ctxt_idx is the index of the linked context id / vmid
> > +             comparator.
> > +
> > +File         : addr_ctxtype (rw)
> > +Trace Registers      : ACATR[idx,{3:2}]
> > +Notes                : Input value string. Set type for linked context ID comparator
> > +Depends              : addr_idx
> > +Syntax               : 'echo type > addr_ctxtype'
> > +             Type one of {all, vmid, ctxid, none}
> > +Example              : $> echo ctxid > addr_ctxtype
> > +
> > +File         : addr_exlevel_s_ns (rw)
> > +Trace Registers      : ACATR[idx,{14:8}]
> > +Notes                : Set the ELx secure and non-secure  matching bits for the
> > +             selected address comparator
> > +Depends              : addr_idx
> > +Syntax               : 'echo val > addr_exlevel_s_ns'
> > +             val is a 7 bit value for exception levels to exclude. Input
> > +             value shifted to correct bits in register.
> > +Example              : $> echo 0x4F > addr_exlevel_s_ns
> > +
> > +File         : addr_instdatatype (rw)
> > +Trace Registers      : ACATR[idx,{1:0}]
> > +Notes                : Set the comparator address type for matching. Driver only
> > +             supports setting instruction address type.
> > +Depends              : addr_idx
> > +
> > +File         : addr_cmp_view (ro)
> > +Trace Registers      : ACVR[idx, idx+1], ACATR[idx], VIIECTLR
> > +Notes                : Read the currently selected address comparator. If part of
> > +             address range then display both addresses.
> > +Depends              : addr_idx
> > +Syntax               : 'cat addr_cmp_view'
> > +Example              : $> cat addr_cmp_view
> > +             addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)
> > +
> > +File         : nr_addr_cmp (ro)
> > +Trace Registers      : From IDR4
> > +Notes                : Number of address comparator pairs
> > +
> > +File         : sshot_idx (rw)
> > +Trace Registers      : None
> > +Notes                : Select  single shot register set.
> > +
> > +File         : sshot_ctrl (rw)
> > +Trace Registers      : SSCCR[idx]
> > +Notes                : Access a single shot comparator control register.
> > +Depends              : sshot_idx
> > +Syntax               : 'echo val > sshot_ctrl'
> > +             Writes val into the selected control register.
> > +
> > +File         : sshot_status (ro)
> > +Trace Registers      : SSCSR[idx]
> > +Notes                : Read a single shot comparator status register
> > +Depends              : sshot_idx
> > +Syntax               : 'cat sshot_status'
> > +             Read status.
> > +Example              : $> cat sshot_status
> > +             0x1
> > +
> > +File         : sshot_pe_ctrl (rw)
> > +Trace Registers      : SSPCICR[idx]
> > +Notes                : Access a single shot PE comparator input control register.
> > +Depends              : sshot_idx
> > +Syntax               : echo val > sshot_pe_ctrl
> > +             Writes val into the selected control register.
> > +
> > +File         : ns_exlevel_vinst (rw)
> > +Trace Registers      : VICTLR{23:20}
> > +Notes                : Program non-secure exception level filters. Set / clear NS
> > +             exception filter bits. Setting ‘1’ excludes trace from the
> > +             exception level.
> > +Syntax               : 'echo bitfield > ns_exlevel_viinst'
> > +             Where bitfield contains bits to set clear for EL0 to EL2
> > +Example              : %> echo 0x4 > ns_exlevel_viinst
> > +             ; Exclude EL2 NS trace.
> > +
> > +File         : vinst_pe_cmp_start_stop (rw)
> > +Trace Registers      : VIPCSSCTLR
> > +Notes                : Access PE start stop comparator input control registers
> > +
> > +File         : bb_ctrl (rw)
> > +Trace Registers      : BBCTLR
> > +Notes                : Define ranges that Branch Broadcast will operate in.
> > +             Default (0x0) is all addresses.
> > +Depends              : BB enabled.
> > +
> > +File         : cyc_threshold (rw)
> > +Trace Registers      : CCCTLR
> > +Notes                : Set the threshold for which cycle counts will be emitted.
> > +             Error if attempt to set below minimum defined in IDR3, masked
> > +             to width of valid bits.
> > +Depends              : CC enabled.
> > +
> > +File         : syncfreq (rw)
> > +Trace Registers      : SYNCPR
> > +Notes                : Set trace synchronisation period. Power of 2 value, 0 (off)
> > +             or 8-20. Driver defaults to 12 (every 4096 bytes).
> > +
> > +File         : cntr_idx (rw)
> > +Trace Registers      : none
> > +Notes                : Select the counter to access
> > +Syntax               : 'echo idx > cntr_idx'
> > +             Where idx <  nr_cntr
> > +
> > +File         : cntr_ctrl (rw)
> > +Trace Registers      : CNTCTLR[idx]
> > +Notes                : Set counter control value
> > +Depends              : cntr_idx
> > +Syntax               : 'echo val > cntr_ctrl'
> > +             Where val is per ETMv4 spec.
> > +
> > +File         : cntrldvr (rw)
> > +Trace Registers      : CNTRLDVR[idx]
> > +Notes                : Set counter reload value
> > +Depends              : cntr_idx
> > +Syntax               : 'echo val > cntrldvr'
> > +             Where val is per ETMv4 spec.
> > +
> > +File         : nr_cntr (ro)
> > +Trace Registers      : From IDR5
> > +Notes                : Number of counters implemented.
> > +
> > +File         : ctxid_idx (rw)
> > +Trace Registers      : None
> > +Notes                : Select the context ID comparator to access
> > +Syntax               : 'echo idx > ctxid_idx'
> > +             Where idx <  numcidc
> > +
> > +File         : ctxid_pid (rw)
> > +Trace Registers      : CIDCVR[idx]
> > +Notes                : Set the context ID comparator value
> > +Depends              : ctxid_idx
> > +
> > +File         : ctxid_masks (rw)
> > +Trace Registers      : CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7>
> > +Notes                : Pair of values to set the byte masks for 1-8 context ID
> > +             comparators. Automatically clears masked bytes to 0 in CID
> > +             value registers.
> > +Syntax               : 'echo m3m2m1m0 [m7m6m5m4] > ctxid_masks'
> > +             32 bit values made up of mask bytes, where mN represents a
> > +             byte mask value for Ctxt ID comparator N.
> > +             Second value not required on systems that have fewer than 4
> > +             context ID comparators
> > +
> > +File         : numcidc (ro)
> > +Trace Registers      : From IDR4
> > +Notes                : Number of Context ID comparators
> > +
> > +File         : vmid_idx (rw)
> > +Trace Registers      : None
> > +Notes                : Select the VM ID comparator to access.
> > +Syntax               : 'echo idx > vmid_idx'
> > +             Where idx <  numvmidc
> > +
> > +File         : vmid_val (rw)
> > +Trace Registers      : VMIDCVR[idx]
> > +Notes                : Set the VM ID comparator value
> > +Depends              : vmid_idx
> > +
> > +File         : vmid_masks (rw)
> > +Trace Registers      : VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7>
> > +Notes                : Pair of values to set the byte masks for 1-8 VM ID
> > +             comparators. Automatically clears masked bytes to 0 in VMID
> > +             value registers.
> > +Syntax               : 'echo m3m2m1m0 [m7m6m5m4] > vmid_masks'
> > +             Where mN represents a byte mask value for VMID comparator N.
> > +             Second value not required on systems that have fewer than
> > +             4 VMID comparators.
> > +
> > +File         : numvmidc (ro)
> > +Trace Registers      : From IDR4
> > +Notes                : Number of VMID comparators
> > +
> > +File         : res_idx (rw)
> > +Trace Registers      : None.
> > +Notes                : Select the resource selector control to access. Must be 2 or
> > +             higher as selectors 0 and 1 are hardwired.
> > +Syntax               : 'echo idx > res_idx'
> > +             Where 2 <= idx <  nr_resource x 2
> > +
> > +File         : res_ctrl (rw)
> > +Trace Registers      : RSCTLR[idx]
> > +Notes                : Set resource selector control value. Value per ETMv4 spec.
> > +Depends              : res_idx
> > +Syntax               : 'echo val > res_cntr'
> > +             Where val is per ETMv4 spec.
> > +
> > +File         : nr_resource (ro)
> > +Trace Registers      : From IDR4
> > +Notes                : Number of resource selector pairs
> > +
> > +File         : event (rw)
> > +Trace Registers      : EVENTCTRL0R
> > +Notes                : Set up to 4 implemented event fields.
> > +Syntax               : 'echo ev3ev2ev1ev0 > event'
> > +             Where evN is an 8 bit event field. Up to 4 event fields make up
> > +             the 32bit input value. Number of valid fields implementation
> > +             dependent defined in IDR0.
> > +
> > +File         : event_instren (rw)
> > +Trace Registers      : EVENTCTRL1R
> > +Notes                : Choose events which insert event packets into trace stream.
> > +Depends              : EVENTCTRL0R
> > +Syntax               : 'echo bitfield > event_instren'
> > +             Where bitfield is up to 4 bits according to number of event
> > +             fields.
> > +
> > +File         : event_ts (rw)
> > +Trace Registers      : TSCTLR
> > +Notes                : Set the event that will generate timestamp requests.
> > +Depends              : TS activated
> > +Syntax               : 'echo evfield > event_ts'
> > +             Where evfield is an 8 bit event selector.
> > +
> > +File         : seq_idx (rw)
> > +Trace Registers      : None
> > +Notes                : Sequencer event register select - 0 to 2
> > +
> > +
> > +File         : seq_state (rw)
> > +Trace Registers      : SEQSTR
> > +Notes                : Sequencer current state - 0 to 3.
> > +
> > +File         : seq_event (rw)
> > +Trace Registers      : SEQEVR[idx]
> > +Notes                : State transition event registers
> > +Depends              : seq_idx
> > +Syntax               : 'echo evBevF > seq_event'
> > +             Where evBevF is a 16 bit value made up of two event selectors,
> > +             evB - back, evF - forwards.
> > +
> > +File         : seq_reset_event (rw)
> > +Trace Registers      : SEQRSTEVR
> > +Notes                : Sequencer reset event
> > +Syntax               : 'echo evfield > seq_reset_event'
> > +             Where evfield is an 8 bit event selector.
> > +
> > +File         : nrseqstate (ro)
> > +Trace Registers      : From IDR5
> > +Notes                : Number of sequencer states (0 or 4)
> > +
> > +File         : nr_pe_cmp (ro)
> > +Trace Registers      : From IDR4
> > +Notes                : Number of PE comparator inputs
> > +
> > +File         : nr_ext_inp (ro)
> > +Trace Registers      : From IDR5
> > +Notes                : Number of external inputs
> > +
> > +File         : nr_ss_cmp (ro)
> > +Trace Registers      : From IDR4
> > +Notes                : Number of Single Shot control registers
> > +
> > +Note: When programming any address comparator the driver will tag the
> > +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag
> > +is set, then only the values can be changed using the same sysfs file / type
> > +used to program it.
> > +
> > +Thus:-
> > +% echo 0 > addr_idx              ; select address comparator 0
> > +% echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0 and 1.
> > +% echo 0x2000 > addr_start       ; this will error as comparator 0 is a
> > +                                         ; range comparator
> > +% echo 2 > addr_idx              ; select address comparator 2
> > +% echo 0x2000 > addr_start       ; this is OK as comparator 2 is unused,
> > +% echo 0x3000 > addr_stop        ; this will error as comparator 2 a start
> > +                                         ; address comparator
> > +% echo 2 > addr_idx              ; select address comparator 3
> > +% echo 0x3000 > addr_stop        ; this is OK
> > +
> > +To remove programming on all the comparators (and all the other hardware) use
> > +the reset parameter:
> > +
> > +% echo 1 > reset
> > +
> > +The ‘mode’ sysfs parameter.
> > +---------------------------
> > +
> > +This is a bitfield selection parameter that sets the overall trace mode for the
> > +ETM. The table below describes the bits, using the defines from the driver
> > +source file, along with a description of the feature these represent. Many
> > +features are optional and therefore dependent on implementation in the
> > +hardware.
> > +
> > +Bit assignements shown below:-
> > +
> > +bit (0)          : #define ETM_MODE_EXCLUDE
> > +description : This is the default value for the include / exclude function when
> > +           setting address ranges. Set 1 for exclude range. When the mode
> > +           parameter is set this value is applied to the currently indexed
> > +           address range.
> > +
> > +bit (4)          : #define ETM_MODE_BB
> > +description : Set to enable branch broadcast if supported in hardware [IDR0].
> > +
> > +bit (5)          : #define ETMv4_MODE_CYCACC
> > +description : Set to enable cycle accurate trace if supported [IDR0].
> > +
> > +bit (6)          : ETMv4_MODE_CTXID
> > +description : Set to enable context ID tracing if supported in hardware [IDR2].
> > +
> > +bit (7)          : ETM_MODE_VMID
> > +description : Set to enable virtual machine ID tracing if supported [IDR2].
> > +
> > +bit (11)    : ETMv4_MODE_TIMESTAMP
> > +description : Set to enable timestamp generation if supported [IDR0].
> > +
> > +bit (12)    : ETM_MODE_RETURNSTACK
> > +description : Set to enable trace return stack use if supported [IDR0].
> > +
> > +bit (13-14) : ETM_MODE_QELEM(val)
> > +description : ‘val’ determines level of Q element support enabled if
> > +         implemented by the ETM [IDR0]
> > +
> > +bit (19)    : ETM_MODE_ATB_TRIGGER
> > +description : Set to enable the ATBTRIGGER bit in the event control register
> > +         [EVENTCTLR1] if supported [IDR5].
> > +
> > +bit (20)    : ETM_MODE_LPOVERRIDE
> > +description : Set to enable the LPOVERRIDE bit in the event control register
> > +         [EVENTCTLR1], if supported [IDR5].
> > +
> > +bit (21)    : ETM_MODE_ISTALL_EN
> > +description : Set to enable the ISTALL bit in the stall control register
> > +         [STALLCTLR]
> > +
> > +bit (23)    : ETM_MODE_INSTPRIO
> > +description : Set to enable the INSTPRIORITY bit in the stall control register
> > +         [STALLCTLR] , if supported [IDR0].
> > +
> > +bit (24)    : ETM_MODE_NOOVERFLOW
> > +description : Set to enable the NOOVERFLOW bit in the stall control register
> > +         [STALLCTLR], if supported [IDR3].
> > +
> > +bit (25)    : ETM_MODE_TRACE_RESET
> > +description : Set to enable the TRCRESET bit in the viewinst control register
> > +         [VICTLR] , if supported [IDR3].
> > +
> > +bit (26)    : ETM_MODE_TRACE_ERR
> > +description : Set to enable the TRCCTRL bit in the viewinst control register
> > +         [VICTLR].
> > +
> > +bit (27)    : ETM_MODE_VIEWINST_STARTSTOP
> > +description : Set the initial state value of the ViewInst start / stop logic
> > +         in the viewinst control register [VICTLR]
> > +
> > +bit (30)    : ETM_MODE_EXCL_KERN
> > +description : Set default trace setup to exclude kernel mode trace (see note a)
> > +
> > +bit (31)    : ETM_MODE_EXCL_USER
> > +description : Set default trace setup to exclude user space trace (see note a)
> > +
> > +Note a) On startup the ETM is programmed to trace the complete address space
> > +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to
> > +set EL exclude bits for NS state in either user space (EL0) or kernel space
> > +(EL1) in the address range comparator. (the default setting excludes all
> > +secure EL, and NS EL2)
> > +
> > +Once the reset parameter has been used, and/or custom programming has been
> > +implemented - using these bits will result in the EL bits for address
> > +comparator 0 being set in the same way.
> > +
> > +Note b) Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with
> > +data trace. As A profile data trace is architecturally prohibited in ETMv4,
> > +these have been omitted here. Possible uses could be where a kernel has
> > +support for control of R or M profile infrastructure as part of a heterogeneous
> > +system.
> > +
> > +Bits 17, 28-29 are unused.
> > +
> > diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight/coresight.txt
> > similarity index 100%
> > rename from Documentation/trace/coresight.txt
> > rename to Documentation/trace/coresight/coresight.txt
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 783569e3c4b4..777b77fde29b 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1582,8 +1582,7 @@ R:      Suzuki K Poulose <suzuki.poulose@arm.com>
> >  L:   linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> >  S:   Maintained
> >  F:   drivers/hwtracing/coresight/*
> > -F:   Documentation/trace/coresight.txt
> > -F:   Documentation/trace/coresight-cpu-debug.txt
> > +F:   Documentation/trace/coresight/*
> >  F:   Documentation/devicetree/bindings/arm/coresight.txt
> >  F:   Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> >  F:   Documentation/ABI/testing/sysfs-bus-coresight-devices-*
> > --
> > 2.17.1
> >



-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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Re: [PATCH 8/8] coresight: etm4x: docs: Additional documentation for ETM4x.

[Mathieu Poirier]

On Wed, 28 Aug 2019 at 08:20, Mike Leach <mike.leach@linaro.org> wrote:
>
> Hi Mathieu,
>
> I assume you want the split to be ? :-
> 1. the update in Documentation/ARM/testing/sysfs-bus-coresight-devices-etm4x
> 2. the moving of coresight docs to their new common directory.
> 3. the addition of the new etm4x doc

Yes, that would be great.

>
> On Tue, 27 Aug 2019 at 23:34, Mathieu Poirier
> <mathieu.poirier@linaro.org> wrote:
> >
> > On Mon, Aug 19, 2019 at 09:57:20PM +0100, Mike Leach wrote:
> > > Update existing docs for new sysfs API features.
> > > Add new ETMv4 reference document for sysfs programming.
> > > Move coresight documentation to common directory.
> > >
> >
> > I also get the following warnings when adding the patch:
> >
> > $ git am 0008-coresight-etm4x-docs-Additional-documentation-for-ET.patch
> > Applying: coresight: etm4x: docs: Additional documentation for ETM4x.
> > .git/rebase-apply/patch:620: space before tab in indent.
> >                 bitfield up to 32 bits setting trace features.
> > .git/rebase-apply/patch:950: space before tab in indent.
> >                                     ; range comparator
> > .git/rebase-apply/patch:954: space before tab in indent.
> >                                     ; address comparator
> > .git/rebase-apply/patch:1057: new blank line at EOF.
> > +
> > warning: 4 lines add whitespace errors.
> >
>
> OK - I'll re-look at this, but don't recall seeing any errors myself
> & al cleared by checkpatch.

I didn't get any errors from checkpatch either.  I got these while
applying the patch.

>
> Regards
>
> Mike
>
>
> > > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > > ---
> > >  .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++---
> > >  .../{ => coresight}/coresight-cpu-debug.txt   |   0
> > >  .../coresight/coresight-etm4x-reference.txt   | 459 ++++++++++++++++++
> > >  .../trace/{ => coresight}/coresight.txt       |   0
> > >  MAINTAINERS                                   |   3 +-
> > >  5 files changed, 575 insertions(+), 70 deletions(-)
> > >  rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%)
> > >  create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt
> > >  rename Documentation/trace/{ => coresight}/coresight.txt (100%)
> > >
> > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> > > index 36258bc1b473..112c50ae9986 100644
> > > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> > > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> > > @@ -1,4 +1,4 @@
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/enable_source
> > > +What:                /sys/bus/coresight/devices/etm<N>/enable_source
> > >  Date:                April 2015
> > >  KernelVersion:  4.01
> > >  Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
> > > @@ -8,82 +8,82 @@ Description:        (RW) Enable/disable tracing on this specific trace entiry.
> > >               of coresight components linking the source to the sink is
> > >               configured and managed automatically by the coresight framework.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/cpu
> > > +What:                /sys/bus/coresight/devices/etm<N>/cpu
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) The CPU this tracing entity is associated with.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
> > > +What:                /sys/bus/coresight/devices/etm<N>/nr_pe_cmp
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Indicates the number of PE comparator inputs that are
> > >               available for tracing.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
> > > +What:                /sys/bus/coresight/devices/etm<N>/nr_addr_cmp
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Indicates the number of address comparator pairs that are
> > >               available for tracing.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
> > > +What:                /sys/bus/coresight/devices/etm<N>/nr_cntr
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Indicates the number of counters that are available for
> > >               tracing.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
> > > +What:                /sys/bus/coresight/devices/etm<N>/nr_ext_inp
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Indicates how many external inputs are implemented.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/numcidc
> > > +What:                /sys/bus/coresight/devices/etm<N>/numcidc
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Indicates the number of Context ID comparators that are
> > >               available for tracing.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/numvmidc
> > > +What:                /sys/bus/coresight/devices/etm<N>/numvmidc
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Indicates the number of VMID comparators that are available
> > >               for tracing.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
> > > +What:                /sys/bus/coresight/devices/etm<N>/nrseqstate
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Indicates the number of sequencer states that are
> > >               implemented.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nr_resource
> > > +What:                /sys/bus/coresight/devices/etm<N>/nr_resource
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Indicates the number of resource selection pairs that are
> > >               available for tracing.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
> > > +What:                /sys/bus/coresight/devices/etm<N>/nr_ss_cmp
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Indicates the number of single-shot comparator controls that
> > >               are available for tracing.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/reset
> > > +What:                /sys/bus/coresight/devices/etm<N>/reset
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (W) Cancels all configuration on a trace unit and set it back
> > >               to its boot configuration.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mode
> > > +What:                /sys/bus/coresight/devices/etm<N>/mode
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > @@ -91,302 +91,349 @@ Description:    (RW) Controls various modes supported by this ETM, for example
> > >               P0 instruction tracing, branch broadcast, cycle counting and
> > >               context ID tracing.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/pe
> > > +What:                /sys/bus/coresight/devices/etm<N>/pe
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Controls which PE to trace.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/event
> > > +What:                /sys/bus/coresight/devices/etm<N>/event
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Controls the tracing of arbitrary events from bank 0 to 3.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/event_instren
> > > +What:                /sys/bus/coresight/devices/etm<N>/event_instren
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Controls the behavior of the events in bank 0 to 3.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/event_ts
> > > +What:                /sys/bus/coresight/devices/etm<N>/event_ts
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Controls the insertion of global timestamps in the trace
> > >               streams.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/syncfreq
> > > +What:                /sys/bus/coresight/devices/etm<N>/syncfreq
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Controls how often trace synchronization requests occur.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
> > > +What:                /sys/bus/coresight/devices/etm<N>/cyc_threshold
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Sets the threshold value for cycle counting.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
> > > +What:                /sys/bus/coresight/devices/etm<N>/bb_ctrl
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Controls which regions in the memory map are enabled to
> > >               use branch broadcasting.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/event_vinst
> > > +What:                /sys/bus/coresight/devices/etm<N>/event_vinst
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Controls instruction trace filtering.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst
> > > +What:                /sys/bus/coresight/devices/etm<N>/s_exlevel_vinst
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) In Secure state, each bit controls whether instruction
> > >               tracing is enabled for the corresponding exception level.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst
> > > +What:                /sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) In non-secure state, each bit controls whether instruction
> > >               tracing is enabled for the corresponding exception level.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/addr_idx
> > > +What:                /sys/bus/coresight/devices/etm<N>/addr_idx
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Select which address comparator or pair (of comparators) to
> > >               work with.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype
> > > +What:                /sys/bus/coresight/devices/etm<N>/addr_instdatatype
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Controls what type of comparison the trace unit performs.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/addr_single
> > > +What:                /sys/bus/coresight/devices/etm<N>/addr_single
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Used to setup single address comparator values.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/addr_range
> > > +What:                /sys/bus/coresight/devices/etm<N>/addr_range
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Used to setup address range comparator values.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/seq_idx
> > > +What:                /sys/bus/coresight/devices/etm<N>/seq_idx
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Select which sequensor.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/seq_state
> > > +What:                /sys/bus/coresight/devices/etm<N>/seq_state
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Use this to set, or read, the sequencer state.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/seq_event
> > > +What:                /sys/bus/coresight/devices/etm<N>/seq_event
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Moves the sequencer state to a specific state.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event
> > > +What:                /sys/bus/coresight/devices/etm<N>/seq_reset_event
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Moves the sequencer to state 0 when a programmed event
> > >               occurs.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx
> > > +What:                /sys/bus/coresight/devices/etm<N>/cntr_idx
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Select which counter unit to work with.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr
> > > +What:                /sys/bus/coresight/devices/etm<N>/cntrldvr
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) This sets or returns the reload count value of the
> > >               specific counter.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/cntr_val
> > > +What:                /sys/bus/coresight/devices/etm<N>/cntr_val
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) This sets or returns the current count value of the
> > >                  specific counter.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl
> > > +What:                /sys/bus/coresight/devices/etm<N>/cntr_ctrl
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Controls the operation of the selected counter.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/res_idx
> > > +What:                /sys/bus/coresight/devices/etm<N>/res_idx
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Select which resource selection unit to work with.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl
> > > +What:                /sys/bus/coresight/devices/etm<N>/res_ctrl
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description:         (RW) Controls the selection of the resources in the trace unit.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx
> > > +What:                /sys/bus/coresight/devices/etm<N>/ctxid_idx
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (RW) Select which context ID comparator to work with.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid
> > > +What:                /sys/bus/coresight/devices/etm<N>/ctxid_pid
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (RW) Get/Set the context ID comparator value to trigger on.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks
> > > +What:                /sys/bus/coresight/devices/etm<N>/ctxid_masks
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (RW) Mask for all 8 context ID comparator value
> > >               registers (if implemented).
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx
> > > +What:                /sys/bus/coresight/devices/etm<N>/vmid_idx
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (RW) Select which virtual machine ID comparator to work with.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/vmid_val
> > > +What:                /sys/bus/coresight/devices/etm<N>/vmid_val
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (RW) Get/Set the virtual machine ID comparator value to
> > >               trigger on.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks
> > > +What:                /sys/bus/coresight/devices/etm<N>/vmid_masks
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (RW) Mask for all 8 virtual machine ID comparator value
> > >               registers (if implemented).
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr
> > > +What:                /sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns
> > > +Date:                August 2019
> > > +KernelVersion:       5.4
> > > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > +Description: (RW) Set the Exception Level matching bits for secure and
> > > +             non-secure exception levels.
> > > +
> > > +What:                /sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop
> > > +Date:                August 2019
> > > +KernelVersion:       5.4
> > > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > +Description: (RW) Access the start stop control register for PE input
> > > +             comparators.
> > > +
> > > +What:                /sys/bus/coresight/devices/etm<N>/addr_cmp_view
> > > +Date:                August 2019
> > > +KernelVersion:       5.4
> > > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > +Description: (R) Print the current settings for the selected address
> > > +             comparator.
> > > +
> > > +What:                /sys/bus/coresight/devices/etm<N>/sshot_idx
> > > +Date:                August 2019
> > > +KernelVersion:       5.4
> > > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > +Description: (RW) Select the single shot control register to access.
> > > +
> > > +What:                /sys/bus/coresight/devices/etm<N>/sshot_ctrl
> > > +Date:                August 2019
> > > +KernelVersion:       5.4
> > > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > +Description: (RW) Access the selected single shot control register.
> > > +
> > > +What:                /sys/bus/coresight/devices/etm<N>/sshot_status
> > > +Date:                August 2019
> > > +KernelVersion:       5.4
> > > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > +Description: (R) Print the current value of the selected single shot
> > > +             status register.
> > > +
> > > +What:                /sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl
> > > +Date:                August 2019
> > > +KernelVersion:       5.4
> > > +Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > +Description: (RW) Access the selected single show PE comparator control
> > > +             register.
> > > +
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the OS Lock Status Register (0x304).
> > >               The value it taken directly  from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the Power Down Control Register
> > >               (0x310).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the Power Down Status Register
> > >               (0x314).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trclsr
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the SW Lock Status Register
> > >               (0xFB4).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the Authentication Status Register
> > >               (0xFB8).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcdevid
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the Device ID Register
> > >               (0xFC8).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the Device Type Register
> > >               (0xFCC).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the Peripheral ID0 Register
> > >               (0xFE0).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the Peripheral ID1 Register
> > >               (0xFE4).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the Peripheral ID2 Register
> > >               (0xFE8).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the Peripheral ID3 Register
> > >               (0xFEC).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trcconfig
> > >  Date:                February 2016
> > >  KernelVersion:       4.07
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the trace configuration register
> > >               (0x010) as currently set by SW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid
> > > +What:                /sys/bus/coresight/devices/etm<N>/mgmt/trctraceid
> > >  Date:                February 2016
> > >  KernelVersion:       4.07
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Print the content of the trace ID register (0x040).
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0
> > > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr0
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Returns the tracing capabilities of the trace unit (0x1E0).
> > >               The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1
> > > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr1
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Returns the tracing capabilities of the trace unit (0x1E4).
> > >               The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2
> > > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr2
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > @@ -394,7 +441,7 @@ Description:      (R) Returns the maximum size of the data value, data address,
> > >               VMID, context ID and instuction address in the trace unit
> > >               (0x1E8).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3
> > > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr3
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > @@ -403,42 +450,42 @@ Description:    (R) Returns the value associated with various resources
> > >               architecture specification for more details (0x1E8).
> > >               The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4
> > > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr4
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Returns how many resources the trace unit supports (0x1F0).
> > >               The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5
> > > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr5
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Returns how many resources the trace unit supports (0x1F4).
> > >               The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8
> > > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr8
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Returns the maximum speculation depth of the instruction
> > >               trace stream. (0x180).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9
> > > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr9
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Returns the number of P0 right-hand keys that the trace unit
> > >               can use (0x184).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10
> > > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr10
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > >  Description: (R) Returns the number of P1 right-hand keys that the trace unit
> > >               can use (0x188).  The value is taken directly from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11
> > > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr11
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > @@ -446,7 +493,7 @@ Description:      (R) Returns the number of special P1 right-hand keys that the
> > >               trace unit can use (0x18C).  The value is taken directly from
> > >               the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12
> > > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr12
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > @@ -454,7 +501,7 @@ Description:      (R) Returns the number of conditional P1 right-hand keys that
> > >               the trace unit can use (0x190).  The value is taken directly
> > >               from the HW.
> > >
> > > -What:                /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13
> > > +What:                /sys/bus/coresight/devices/etm<N>/trcidr/trcidr13
> > >  Date:                April 2015
> > >  KernelVersion:       4.01
> > >  Contact:     Mathieu Poirier <mathieu.poirier@linaro.org>
> > > diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight/coresight-cpu-debug.txt
> > > similarity index 100%
> > > rename from Documentation/trace/coresight-cpu-debug.txt
> > > rename to Documentation/trace/coresight/coresight-cpu-debug.txt
> > > diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.txt b/Documentation/trace/coresight/coresight-etm4x-reference.txt
> > > new file mode 100644
> > > index 000000000000..72e81bbbef43
> > > --- /dev/null
> > > +++ b/Documentation/trace/coresight/coresight-etm4x-reference.txt
> > > @@ -0,0 +1,459 @@
> > > +ETMv4 sysfs linux driver programming reference - v2.
> > > +====================================================
> > > +
> > > +Supplement to existing ETMv4 driver documentation.
> > > +
> > > +Sysfs files and directories
> > > +---------------------------
> > > +
> > > +Root: /sys/bus/coresight/devices/etm<N>
> > > +
> > > +
> > > +The following paragraphs explain the association between sysfs files and the
> > > +ETMv4 registers that they effect. Note the register names are given without
> > > +the ‘TRC’ prefix.
> > > +
> > > +File         : mode (rw)
> > > +Trace Registers      : {CONFIGR + others}
> > > +Notes                : Bit select trace features. See ‘mode’ section below. Bits
> > > +             in this will cause equivalent programming of trace config and
> > > +             other registers to enable the features requested.
> > > +Syntax & eg  : 'echo bitfield > mode'
> > > +                     bitfield up to 32 bits setting trace features.
> > > +Example              : $> echo 0x > mode
> > > +
> > > +File         : reset (wo)
> > > +Trace Registers      : All
> > > +Notes                : Reset all programming to trace nothing / no logic programmed.
> > > +Syntax               : 'echo 1 > reset'
> > > +
> > > +File         : enable_source (wo)
> > > +Trace Registers      : PRGCTLR, All hardware regs.
> > > +Notes                :  >0: Programs up the hardware with the current values held in
> > > +             the driver and enables trace.
> > > +             0: disable trace hardware.
> > > +Syntax               : 'echo 1 > enable_source'
> > > +
> > > +File         : cpu (ro)
> > > +Trace Registers      : None.
> > > +Notes                : CPU ID that this ETM is attached to.
> > > +Example              :$> cat cpu
> > > +             $> 0
> > > +
> > > +File         : addr_idx (rw)
> > > +Trace Registers      : None.
> > > +Notes                : Virtual register to index address comparator and range
> > > +             features. Set index for first of the pair in a range.
> > > +Syntax               : 'echo idx > addr_idx'
> > > +             Where idx <  nr_addr_cmp x 2
> > > +
> > > +File         : addr_range (rw)
> > > +Trace Registers      : ACVR[idx, idx+1], VIIECTLR
> > > +Notes                : Pair of addresses for a range selected by addr_idx. Include
> > > +             / exclude according to the optional parameter, or if omitted
> > > +             uses the current ‘mode’ setting. Select comparator range in
> > > +             control register. Error if index is odd value.
> > > +Depends              : mode, addr_idx
> > > +Syntax               : 'echo addr1 addr2 [exclude] > addr_range'
> > > +             Where addr1 and addr2 define the range and addr1 < addr2.
> > > +             Optional exclude value - 0 for include, 1 for exclude.
> > > +Example              : $> echo 0x0000 0x2000 0 > addr_range
> > > +
> > > +File         : addr_single (rw)
> > > +Trace Registers      : ACVR[idx]
> > > +Notes                : Set a single address comparator according to addr_idx. This
> > > +             is used if the address comparator is used as part of event
> > > +             generation logic etc.
> > > +Depends              : addr_idx
> > > +Syntax               : 'echo addr1 > addr_single'
> > > +
> > > +File         : addr_start (rw)
> > > +Trace Registers      : ACVR[idx], VISSCTLR
> > > +Notes                : Set a trace start address comparator according to addr_idx.
> > > +             Select comparator in control register.
> > > +Depends              : addr_idx
> > > +Syntax               : 'echo addr1 > addr_start'
> > > +
> > > +File         : addr_stop (rw)
> > > +Trace Registers      : ACVR[idx], VISSCTLR
> > > +Notes                : Set a trace stop address comparator according to addr_idx.
> > > +             Select comparator in control register.
> > > +Depends              : addr_idx
> > > +Syntax               : 'echo addr1 > addr_stop'
> > > +
> > > +File         : addr_context (rw)
> > > +Trace Registers      : ACATR[idx,{6:4}]
> > > +Notes                : Link context ID comparator to address comparator addr_idx
> > > +Depends              : addr_idx.
> > > +Syntax               : 'echo ctxt_idx > addr_context'
> > > +             Where ctxt_idx is the index of the linked context id / vmid
> > > +             comparator.
> > > +
> > > +File         : addr_ctxtype (rw)
> > > +Trace Registers      : ACATR[idx,{3:2}]
> > > +Notes                : Input value string. Set type for linked context ID comparator
> > > +Depends              : addr_idx
> > > +Syntax               : 'echo type > addr_ctxtype'
> > > +             Type one of {all, vmid, ctxid, none}
> > > +Example              : $> echo ctxid > addr_ctxtype
> > > +
> > > +File         : addr_exlevel_s_ns (rw)
> > > +Trace Registers      : ACATR[idx,{14:8}]
> > > +Notes                : Set the ELx secure and non-secure  matching bits for the
> > > +             selected address comparator
> > > +Depends              : addr_idx
> > > +Syntax               : 'echo val > addr_exlevel_s_ns'
> > > +             val is a 7 bit value for exception levels to exclude. Input
> > > +             value shifted to correct bits in register.
> > > +Example              : $> echo 0x4F > addr_exlevel_s_ns
> > > +
> > > +File         : addr_instdatatype (rw)
> > > +Trace Registers      : ACATR[idx,{1:0}]
> > > +Notes                : Set the comparator address type for matching. Driver only
> > > +             supports setting instruction address type.
> > > +Depends              : addr_idx
> > > +
> > > +File         : addr_cmp_view (ro)
> > > +Trace Registers      : ACVR[idx, idx+1], ACATR[idx], VIIECTLR
> > > +Notes                : Read the currently selected address comparator. If part of
> > > +             address range then display both addresses.
> > > +Depends              : addr_idx
> > > +Syntax               : 'cat addr_cmp_view'
> > > +Example              : $> cat addr_cmp_view
> > > +             addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)
> > > +
> > > +File         : nr_addr_cmp (ro)
> > > +Trace Registers      : From IDR4
> > > +Notes                : Number of address comparator pairs
> > > +
> > > +File         : sshot_idx (rw)
> > > +Trace Registers      : None
> > > +Notes                : Select  single shot register set.
> > > +
> > > +File         : sshot_ctrl (rw)
> > > +Trace Registers      : SSCCR[idx]
> > > +Notes                : Access a single shot comparator control register.
> > > +Depends              : sshot_idx
> > > +Syntax               : 'echo val > sshot_ctrl'
> > > +             Writes val into the selected control register.
> > > +
> > > +File         : sshot_status (ro)
> > > +Trace Registers      : SSCSR[idx]
> > > +Notes                : Read a single shot comparator status register
> > > +Depends              : sshot_idx
> > > +Syntax               : 'cat sshot_status'
> > > +             Read status.
> > > +Example              : $> cat sshot_status
> > > +             0x1
> > > +
> > > +File         : sshot_pe_ctrl (rw)
> > > +Trace Registers      : SSPCICR[idx]
> > > +Notes                : Access a single shot PE comparator input control register.
> > > +Depends              : sshot_idx
> > > +Syntax               : echo val > sshot_pe_ctrl
> > > +             Writes val into the selected control register.
> > > +
> > > +File         : ns_exlevel_vinst (rw)
> > > +Trace Registers      : VICTLR{23:20}
> > > +Notes                : Program non-secure exception level filters. Set / clear NS
> > > +             exception filter bits. Setting ‘1’ excludes trace from the
> > > +             exception level.
> > > +Syntax               : 'echo bitfield > ns_exlevel_viinst'
> > > +             Where bitfield contains bits to set clear for EL0 to EL2
> > > +Example              : %> echo 0x4 > ns_exlevel_viinst
> > > +             ; Exclude EL2 NS trace.
> > > +
> > > +File         : vinst_pe_cmp_start_stop (rw)
> > > +Trace Registers      : VIPCSSCTLR
> > > +Notes                : Access PE start stop comparator input control registers
> > > +
> > > +File         : bb_ctrl (rw)
> > > +Trace Registers      : BBCTLR
> > > +Notes                : Define ranges that Branch Broadcast will operate in.
> > > +             Default (0x0) is all addresses.
> > > +Depends              : BB enabled.
> > > +
> > > +File         : cyc_threshold (rw)
> > > +Trace Registers      : CCCTLR
> > > +Notes                : Set the threshold for which cycle counts will be emitted.
> > > +             Error if attempt to set below minimum defined in IDR3, masked
> > > +             to width of valid bits.
> > > +Depends              : CC enabled.
> > > +
> > > +File         : syncfreq (rw)
> > > +Trace Registers      : SYNCPR
> > > +Notes                : Set trace synchronisation period. Power of 2 value, 0 (off)
> > > +             or 8-20. Driver defaults to 12 (every 4096 bytes).
> > > +
> > > +File         : cntr_idx (rw)
> > > +Trace Registers      : none
> > > +Notes                : Select the counter to access
> > > +Syntax               : 'echo idx > cntr_idx'
> > > +             Where idx <  nr_cntr
> > > +
> > > +File         : cntr_ctrl (rw)
> > > +Trace Registers      : CNTCTLR[idx]
> > > +Notes                : Set counter control value
> > > +Depends              : cntr_idx
> > > +Syntax               : 'echo val > cntr_ctrl'
> > > +             Where val is per ETMv4 spec.
> > > +
> > > +File         : cntrldvr (rw)
> > > +Trace Registers      : CNTRLDVR[idx]
> > > +Notes                : Set counter reload value
> > > +Depends              : cntr_idx
> > > +Syntax               : 'echo val > cntrldvr'
> > > +             Where val is per ETMv4 spec.
> > > +
> > > +File         : nr_cntr (ro)
> > > +Trace Registers      : From IDR5
> > > +Notes                : Number of counters implemented.
> > > +
> > > +File         : ctxid_idx (rw)
> > > +Trace Registers      : None
> > > +Notes                : Select the context ID comparator to access
> > > +Syntax               : 'echo idx > ctxid_idx'
> > > +             Where idx <  numcidc
> > > +
> > > +File         : ctxid_pid (rw)
> > > +Trace Registers      : CIDCVR[idx]
> > > +Notes                : Set the context ID comparator value
> > > +Depends              : ctxid_idx
> > > +
> > > +File         : ctxid_masks (rw)
> > > +Trace Registers      : CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7>
> > > +Notes                : Pair of values to set the byte masks for 1-8 context ID
> > > +             comparators. Automatically clears masked bytes to 0 in CID
> > > +             value registers.
> > > +Syntax               : 'echo m3m2m1m0 [m7m6m5m4] > ctxid_masks'
> > > +             32 bit values made up of mask bytes, where mN represents a
> > > +             byte mask value for Ctxt ID comparator N.
> > > +             Second value not required on systems that have fewer than 4
> > > +             context ID comparators
> > > +
> > > +File         : numcidc (ro)
> > > +Trace Registers      : From IDR4
> > > +Notes                : Number of Context ID comparators
> > > +
> > > +File         : vmid_idx (rw)
> > > +Trace Registers      : None
> > > +Notes                : Select the VM ID comparator to access.
> > > +Syntax               : 'echo idx > vmid_idx'
> > > +             Where idx <  numvmidc
> > > +
> > > +File         : vmid_val (rw)
> > > +Trace Registers      : VMIDCVR[idx]
> > > +Notes                : Set the VM ID comparator value
> > > +Depends              : vmid_idx
> > > +
> > > +File         : vmid_masks (rw)
> > > +Trace Registers      : VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7>
> > > +Notes                : Pair of values to set the byte masks for 1-8 VM ID
> > > +             comparators. Automatically clears masked bytes to 0 in VMID
> > > +             value registers.
> > > +Syntax               : 'echo m3m2m1m0 [m7m6m5m4] > vmid_masks'
> > > +             Where mN represents a byte mask value for VMID comparator N.
> > > +             Second value not required on systems that have fewer than
> > > +             4 VMID comparators.
> > > +
> > > +File         : numvmidc (ro)
> > > +Trace Registers      : From IDR4
> > > +Notes                : Number of VMID comparators
> > > +
> > > +File         : res_idx (rw)
> > > +Trace Registers      : None.
> > > +Notes                : Select the resource selector control to access. Must be 2 or
> > > +             higher as selectors 0 and 1 are hardwired.
> > > +Syntax               : 'echo idx > res_idx'
> > > +             Where 2 <= idx <  nr_resource x 2
> > > +
> > > +File         : res_ctrl (rw)
> > > +Trace Registers      : RSCTLR[idx]
> > > +Notes                : Set resource selector control value. Value per ETMv4 spec.
> > > +Depends              : res_idx
> > > +Syntax               : 'echo val > res_cntr'
> > > +             Where val is per ETMv4 spec.
> > > +
> > > +File         : nr_resource (ro)
> > > +Trace Registers      : From IDR4
> > > +Notes                : Number of resource selector pairs
> > > +
> > > +File         : event (rw)
> > > +Trace Registers      : EVENTCTRL0R
> > > +Notes                : Set up to 4 implemented event fields.
> > > +Syntax               : 'echo ev3ev2ev1ev0 > event'
> > > +             Where evN is an 8 bit event field. Up to 4 event fields make up
> > > +             the 32bit input value. Number of valid fields implementation
> > > +             dependent defined in IDR0.
> > > +
> > > +File         : event_instren (rw)
> > > +Trace Registers      : EVENTCTRL1R
> > > +Notes                : Choose events which insert event packets into trace stream.
> > > +Depends              : EVENTCTRL0R
> > > +Syntax               : 'echo bitfield > event_instren'
> > > +             Where bitfield is up to 4 bits according to number of event
> > > +             fields.
> > > +
> > > +File         : event_ts (rw)
> > > +Trace Registers      : TSCTLR
> > > +Notes                : Set the event that will generate timestamp requests.
> > > +Depends              : TS activated
> > > +Syntax               : 'echo evfield > event_ts'
> > > +             Where evfield is an 8 bit event selector.
> > > +
> > > +File         : seq_idx (rw)
> > > +Trace Registers      : None
> > > +Notes                : Sequencer event register select - 0 to 2
> > > +
> > > +
> > > +File         : seq_state (rw)
> > > +Trace Registers      : SEQSTR
> > > +Notes                : Sequencer current state - 0 to 3.
> > > +
> > > +File         : seq_event (rw)
> > > +Trace Registers      : SEQEVR[idx]
> > > +Notes                : State transition event registers
> > > +Depends              : seq_idx
> > > +Syntax               : 'echo evBevF > seq_event'
> > > +             Where evBevF is a 16 bit value made up of two event selectors,
> > > +             evB - back, evF - forwards.
> > > +
> > > +File         : seq_reset_event (rw)
> > > +Trace Registers      : SEQRSTEVR
> > > +Notes                : Sequencer reset event
> > > +Syntax               : 'echo evfield > seq_reset_event'
> > > +             Where evfield is an 8 bit event selector.
> > > +
> > > +File         : nrseqstate (ro)
> > > +Trace Registers      : From IDR5
> > > +Notes                : Number of sequencer states (0 or 4)
> > > +
> > > +File         : nr_pe_cmp (ro)
> > > +Trace Registers      : From IDR4
> > > +Notes                : Number of PE comparator inputs
> > > +
> > > +File         : nr_ext_inp (ro)
> > > +Trace Registers      : From IDR5
> > > +Notes                : Number of external inputs
> > > +
> > > +File         : nr_ss_cmp (ro)
> > > +Trace Registers      : From IDR4
> > > +Notes                : Number of Single Shot control registers
> > > +
> > > +Note: When programming any address comparator the driver will tag the
> > > +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag
> > > +is set, then only the values can be changed using the same sysfs file / type
> > > +used to program it.
> > > +
> > > +Thus:-
> > > +% echo 0 > addr_idx              ; select address comparator 0
> > > +% echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0 and 1.
> > > +% echo 0x2000 > addr_start       ; this will error as comparator 0 is a
> > > +                                         ; range comparator
> > > +% echo 2 > addr_idx              ; select address comparator 2
> > > +% echo 0x2000 > addr_start       ; this is OK as comparator 2 is unused,
> > > +% echo 0x3000 > addr_stop        ; this will error as comparator 2 a start
> > > +                                         ; address comparator
> > > +% echo 2 > addr_idx              ; select address comparator 3
> > > +% echo 0x3000 > addr_stop        ; this is OK
> > > +
> > > +To remove programming on all the comparators (and all the other hardware) use
> > > +the reset parameter:
> > > +
> > > +% echo 1 > reset
> > > +
> > > +The ‘mode’ sysfs parameter.
> > > +---------------------------
> > > +
> > > +This is a bitfield selection parameter that sets the overall trace mode for the
> > > +ETM. The table below describes the bits, using the defines from the driver
> > > +source file, along with a description of the feature these represent. Many
> > > +features are optional and therefore dependent on implementation in the
> > > +hardware.
> > > +
> > > +Bit assignements shown below:-
> > > +
> > > +bit (0)          : #define ETM_MODE_EXCLUDE
> > > +description : This is the default value for the include / exclude function when
> > > +           setting address ranges. Set 1 for exclude range. When the mode
> > > +           parameter is set this value is applied to the currently indexed
> > > +           address range.
> > > +
> > > +bit (4)          : #define ETM_MODE_BB
> > > +description : Set to enable branch broadcast if supported in hardware [IDR0].
> > > +
> > > +bit (5)          : #define ETMv4_MODE_CYCACC
> > > +description : Set to enable cycle accurate trace if supported [IDR0].
> > > +
> > > +bit (6)          : ETMv4_MODE_CTXID
> > > +description : Set to enable context ID tracing if supported in hardware [IDR2].
> > > +
> > > +bit (7)          : ETM_MODE_VMID
> > > +description : Set to enable virtual machine ID tracing if supported [IDR2].
> > > +
> > > +bit (11)    : ETMv4_MODE_TIMESTAMP
> > > +description : Set to enable timestamp generation if supported [IDR0].
> > > +
> > > +bit (12)    : ETM_MODE_RETURNSTACK
> > > +description : Set to enable trace return stack use if supported [IDR0].
> > > +
> > > +bit (13-14) : ETM_MODE_QELEM(val)
> > > +description : ‘val’ determines level of Q element support enabled if
> > > +         implemented by the ETM [IDR0]
> > > +
> > > +bit (19)    : ETM_MODE_ATB_TRIGGER
> > > +description : Set to enable the ATBTRIGGER bit in the event control register
> > > +         [EVENTCTLR1] if supported [IDR5].
> > > +
> > > +bit (20)    : ETM_MODE_LPOVERRIDE
> > > +description : Set to enable the LPOVERRIDE bit in the event control register
> > > +         [EVENTCTLR1], if supported [IDR5].
> > > +
> > > +bit (21)    : ETM_MODE_ISTALL_EN
> > > +description : Set to enable the ISTALL bit in the stall control register
> > > +         [STALLCTLR]
> > > +
> > > +bit (23)    : ETM_MODE_INSTPRIO
> > > +description : Set to enable the INSTPRIORITY bit in the stall control register
> > > +         [STALLCTLR] , if supported [IDR0].
> > > +
> > > +bit (24)    : ETM_MODE_NOOVERFLOW
> > > +description : Set to enable the NOOVERFLOW bit in the stall control register
> > > +         [STALLCTLR], if supported [IDR3].
> > > +
> > > +bit (25)    : ETM_MODE_TRACE_RESET
> > > +description : Set to enable the TRCRESET bit in the viewinst control register
> > > +         [VICTLR] , if supported [IDR3].
> > > +
> > > +bit (26)    : ETM_MODE_TRACE_ERR
> > > +description : Set to enable the TRCCTRL bit in the viewinst control register
> > > +         [VICTLR].
> > > +
> > > +bit (27)    : ETM_MODE_VIEWINST_STARTSTOP
> > > +description : Set the initial state value of the ViewInst start / stop logic
> > > +         in the viewinst control register [VICTLR]
> > > +
> > > +bit (30)    : ETM_MODE_EXCL_KERN
> > > +description : Set default trace setup to exclude kernel mode trace (see note a)
> > > +
> > > +bit (31)    : ETM_MODE_EXCL_USER
> > > +description : Set default trace setup to exclude user space trace (see note a)
> > > +
> > > +Note a) On startup the ETM is programmed to trace the complete address space
> > > +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to
> > > +set EL exclude bits for NS state in either user space (EL0) or kernel space
> > > +(EL1) in the address range comparator. (the default setting excludes all
> > > +secure EL, and NS EL2)
> > > +
> > > +Once the reset parameter has been used, and/or custom programming has been
> > > +implemented - using these bits will result in the EL bits for address
> > > +comparator 0 being set in the same way.
> > > +
> > > +Note b) Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with
> > > +data trace. As A profile data trace is architecturally prohibited in ETMv4,
> > > +these have been omitted here. Possible uses could be where a kernel has
> > > +support for control of R or M profile infrastructure as part of a heterogeneous
> > > +system.
> > > +
> > > +Bits 17, 28-29 are unused.
> > > +
> > > diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight/coresight.txt
> > > similarity index 100%
> > > rename from Documentation/trace/coresight.txt
> > > rename to Documentation/trace/coresight/coresight.txt
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 783569e3c4b4..777b77fde29b 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -1582,8 +1582,7 @@ R:      Suzuki K Poulose <suzuki.poulose@arm.com>
> > >  L:   linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> > >  S:   Maintained
> > >  F:   drivers/hwtracing/coresight/*
> > > -F:   Documentation/trace/coresight.txt
> > > -F:   Documentation/trace/coresight-cpu-debug.txt
> > > +F:   Documentation/trace/coresight/*
> > >  F:   Documentation/devicetree/bindings/arm/coresight.txt
> > >  F:   Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> > >  F:   Documentation/ABI/testing/sysfs-bus-coresight-devices-*
> > > --
> > > 2.17.1
> > >
>
>
>
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK

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