* Re: [PATCH v14 01/18] irqchip/sifive-plic: Convert PLIC driver into a platform driver
2024-05-29 22:04 0% ` Samuel Holland
@ 2024-05-30 7:06 0% ` Geert Uytterhoeven
0 siblings, 0 replies; 200+ results
From: Geert Uytterhoeven @ 2024-05-30 7:06 UTC (permalink / raw)
To: Samuel Holland
Cc: Anup Patel, devicetree, Conor Dooley, Emil Renner Berthing,
Saravana Kannan, Marc Zyngier, Anup Patel, Atish Patra,
linux-kernel, Björn Töpel, Rob Herring, Palmer Dabbelt,
Krzysztof Kozlowski, Paul Walmsley, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel, Andrew Jones
Hi Samuel,
On Thu, May 30, 2024 at 12:04 AM Samuel Holland
<samuel.holland@sifive.com> wrote:
> On 2024-05-29 9:22 AM, Geert Uytterhoeven wrote:
> > On Thu, Feb 22, 2024 at 10:41 AM Anup Patel <apatel@ventanamicro.com> wrote:
> >> The PLIC driver does not require very early initialization so convert
> >> it into a platform driver.
> >>
> >> After conversion, the PLIC driver is probed after CPUs are brought-up
> >> so setup cpuhp state after context handler of all online CPUs are
> >> initialized otherwise PLIC driver crashes for platforms with multiple
> >> PLIC instances.
> >>
> >> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> >
> > Thanks for your patch, which is now commit 8ec99b033147ef3b
> > ("irqchip/sifive-plic: Convert PLIC driver into a platform
> > driver") in v6.9.
> >
> > It looks like this conversion is causing issues on BeagleV Starlight
> > Beta. After updating esmil/visionfive to v6.10-rc1, the kernel usually
> > fails to boot. Adding "earlycon keep_bootcon" reveals these differences:
> >
> > -riscv-plic c000000.interrupt-controller: mapped 133 interrupts with 2
> > handlers for 4 contexts.
> > +------------[ cut here ]------------
> > +WARNING: CPU: 0 PID: 1 at drivers/irqchip/irq-sifive-plic.c:373
> > +Unable to handle kernel NULL pointer dereference at virtual address
> The fact that you hit the warning indicates that plic_handle_irq() was called
> before handler->present was set. Previously the PLIC driver was probed very
> early, so it is unlikely that some peripheral already had a pending interrupt.
> Now, while platform device drivers would not yet be able to request interrupts
> (because the irqdomain is not registered yet), they could have programmed the
> hardware in a way that generates an interrupt. If that interrupt was enabled at
> the PLIC (e.g. by the bootloader), then we could expect plic_handle_irq() to be
> called as soon as irq_set_chained_handler() is called.
>
> So the fix is to not call irq_set_chained_handler() until after the handlers are
> completely set up.
>
> I've sent a patch doing this:
> https://lore.kernel.org/linux-riscv/20240529215458.937817-1-samuel.holland@sifive.com/
Thanks, that fixed the issue!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v14 01/18] irqchip/sifive-plic: Convert PLIC driver into a platform driver
2024-05-29 14:22 4% ` Geert Uytterhoeven
@ 2024-05-29 22:04 0% ` Samuel Holland
2024-05-30 7:06 0% ` Geert Uytterhoeven
0 siblings, 1 reply; 200+ results
From: Samuel Holland @ 2024-05-29 22:04 UTC (permalink / raw)
To: Geert Uytterhoeven, Anup Patel
Cc: devicetree, Conor Dooley, Emil Renner Berthing, Saravana Kannan,
Marc Zyngier, Anup Patel, Atish Patra, linux-kernel,
Björn Töpel, Rob Herring, Palmer Dabbelt,
Krzysztof Kozlowski, Paul Walmsley, Thomas Gleixner,
Frank Rowand, linux-riscv, linux-arm-kernel, Andrew Jones
Hi Geert,
On 2024-05-29 9:22 AM, Geert Uytterhoeven wrote:
> Hi Anup,
>
> On Thu, Feb 22, 2024 at 10:41 AM Anup Patel <apatel@ventanamicro.com> wrote:
>> The PLIC driver does not require very early initialization so convert
>> it into a platform driver.
>>
>> After conversion, the PLIC driver is probed after CPUs are brought-up
>> so setup cpuhp state after context handler of all online CPUs are
>> initialized otherwise PLIC driver crashes for platforms with multiple
>> PLIC instances.
>>
>> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
>
> Thanks for your patch, which is now commit 8ec99b033147ef3b
> ("irqchip/sifive-plic: Convert PLIC driver into a platform
> driver") in v6.9.
>
> It looks like this conversion is causing issues on BeagleV Starlight
> Beta. After updating esmil/visionfive to v6.10-rc1, the kernel usually
> fails to boot. Adding "earlycon keep_bootcon" reveals these differences:
>
> -riscv-plic c000000.interrupt-controller: mapped 133 interrupts with 2
> handlers for 4 contexts.
> +------------[ cut here ]------------
> +WARNING: CPU: 0 PID: 1 at drivers/irqchip/irq-sifive-plic.c:373
> plic_handle_irq+0xf2/0xf6
> +Modules linked in:
> +CPU: 0 PID: 1 Comm: swapper/0 Not tainted
> 6.10.0-rc1-starlight-02342-g0ba4c76ca0e8-dirty #323
> +Hardware name: BeagleV Starlight Beta (DT)
> +epc : plic_handle_irq+0xf2/0xf6
> + ra : generic_handle_domain_irq+0x1c/0x2a
> +epc : ffffffff8033f994 ra : ffffffff8006319a sp : ffffffc800003f50
> + gp : ffffffff812d63f0 tp : ffffffd8800b8000 t0 : 0000000000000040
> + t1 : 0000000000000000 t2 : 0000000000001000 s0 : ffffffc800003fa0
> + s1 : 0000000000000009 a0 : ffffffd880183600 a1 : 0000000000000009
> + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000
> + a5 : 0000000000000000 a6 : ffffffd880400248 a7 : ffffffd8804002b8
> + s2 : ffffffd9f8fac458 s3 : 0000000000000004 s4 : 0000000000000000
> + s5 : ffffffff81293f58 s6 : ffffffd88014ac00 s7 : 0000000000000004
> + s8 : ffffffc800013b2c s9 : ffffffc800013b34 s10: 0000000000000006
> + s11: ffffffd9f8fc1458 t3 : 0000000000000002 t4 : 0000000000000402
> + t5 : ffffffd8800610c0 t6 : ffffffd8800610e0
> +status: 0000000200000100 badaddr: ffffffd9f8fac458 cause: 0000000000000003
> +[<ffffffff8033f994>] plic_handle_irq+0xf2/0xf6
> +[<ffffffff8006319a>] generic_handle_domain_irq+0x1c/0x2a
> +[<ffffffff8033d7aa>] riscv_intc_irq+0x26/0x60
> +[<ffffffff806c92ee>] handle_riscv_irq+0x4a/0x74
> +[<ffffffff806d2346>] call_on_irq_stack+0x32/0x40
> +---[ end trace 0000000000000000 ]---
> +Unable to handle kernel NULL pointer dereference at virtual address
> 0000000000000004
> +Oops [#1]
> +Modules linked in:
> +CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W
> 6.10.0-rc1-starlight-02342-g0ba4c76ca0e8-dirty #323
> +Hardware name: BeagleV Starlight Beta (DT)
> +epc : plic_handle_irq+0x66/0xf6
> + ra : generic_handle_domain_irq+0x1c/0x2a
> +epc : ffffffff8033f908 ra : ffffffff8006319a sp : ffffffc800003f50
> + gp : ffffffff812d63f0 tp : ffffffd8800b8000 t0 : 0000000000000040
> + t1 : 0000000000000000 t2 : 0000000000001000 s0 : ffffffc800003fa0
> + s1 : 0000000000000009 a0 : ffffffd880183600 a1 : 0000000000000009
> + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000
> + a5 : ffffffff8033d72a a6 : ffffffd880400248 a7 : ffffffd8804002b8
> + s2 : ffffffd9f8fac458 s3 : 0000000000000004 s4 : ffffffd880183630
> + s5 : ffffffff81293f58 s6 : ffffffff812948a0 s7 : ffffffff80c4e660
> + s8 : ffffffff80d9eea0 s9 : ffffffc800013b34 s10: 0000000000000006
> + s11: ffffffd9f8fc1458 t3 : 0000000000000002 t4 : 0000000000000402
> + t5 : ffffffd8800610c0 t6 : ffffffd8800610e0
> +status: 0000000200000100 badaddr: 0000000000000004 cause: 000000000000000d
> +[<ffffffff8033f908>] plic_handle_irq+0x66/0xf6
> +[<ffffffff8006319a>] generic_handle_domain_irq+0x1c/0x2a
> +[<ffffffff8033d7aa>] riscv_intc_irq+0x26/0x60
> +[<ffffffff806c92ee>] handle_riscv_irq+0x4a/0x74
> +[<ffffffff806d2346>] call_on_irq_stack+0x32/0x40
> +Code: 8b93 d70b 5b17 00f5 0b13 fa8b fc17 00a5 0c13 5a0c (a783) 0009
> +---[ end trace 0000000000000000 ]---
> +Kernel panic - not syncing: Fatal exception in interrupt
> +SMP: stopping secondary CPUs
> +---[ end Kernel panic - not syncing: Fatal exception in interrupt ]---
>
> As "mapped 133 interrupts" is no longer printed, it looks like an
> unexpected early interrupt comes in while still in plic_probe().
>
> Esmil suggested reverting all of:
> a7fb69ffd7ce438a irqchip/sifive-plic: Avoid explicit cpumask allocation on stack
> abb7205794900503 irqchip/sifive-plic: Improve locking safety by using
> irqsave/irqrestore
> 95652106478030f5 irqchip/sifive-plic: Parse number of interrupts and
> contexts early in plic_probe()
> a15587277a246c38 irqchip/sifive-plic: Cleanup PLIC contexts upon
> irqdomain creation failure
> 6c725f33d67b53f2 irqchip/sifive-plic: Use riscv_get_intc_hwnode() to
> get parent fwnode
> b68d0ff529a939a1 irqchip/sifive-plic: Use devm_xyz() for managed allocation
> 25d862e183d4efeb irqchip/sifive-plic: Use dev_xyz() in-place of pr_xyz()
> 8ec99b033147ef3b irqchip/sifive-plic: Convert PLIC driver into a platform driver
>
> After this, the PLIC is initialized earlier again, and this indeed
> seems to fix the issue for me.
> Before, the kernel booted fine in only ca. 1 out of 5 tries.
> After the reverts, it booted 5/5.
>
> Do you know what's going on? Is there a simpler fix?
The fact that you hit the warning indicates that plic_handle_irq() was called
before handler->present was set. Previously the PLIC driver was probed very
early, so it is unlikely that some peripheral already had a pending interrupt.
Now, while platform device drivers would not yet be able to request interrupts
(because the irqdomain is not registered yet), they could have programmed the
hardware in a way that generates an interrupt. If that interrupt was enabled at
the PLIC (e.g. by the bootloader), then we could expect plic_handle_irq() to be
called as soon as irq_set_chained_handler() is called.
So the fix is to not call irq_set_chained_handler() until after the handlers are
completely set up.
I've sent a patch doing this:
https://lore.kernel.org/linux-riscv/20240529215458.937817-1-samuel.holland@sifive.com/
Regards,
Samuel
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH] arm64/io: add constant-argument check
2024-05-29 12:29 5% ` Arnd Bergmann
@ 2024-05-29 15:08 0% ` Mark Rutland
0 siblings, 0 replies; 200+ results
From: Mark Rutland @ 2024-05-29 15:08 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Arnd Bergmann, Catalin Marinas, Will Deacon, Jason Gunthorpe,
Valentin Schneider, Baoquan He, Peter Zijlstra, linux-arm-kernel,
linux-kernel
On Wed, May 29, 2024 at 02:29:37PM +0200, Arnd Bergmann wrote:
> On Wed, May 29, 2024, at 13:14, Mark Rutland wrote:
> >> {
> >> - if (count == 8 || count == 4 || count == 2 || count == 1) {
> >> + if (__builtin_constant_p(count) &&
> >> + (count == 8 || count == 4 || count == 2 || count == 1)) {
> >> __const_memcpy_toio_aligned32(to, from, count);
> >> dgh();
> >> } else {
> >
> > I don't think this is the right fix.
> >
> > The idea was that this was checked in __iowrite32_copy(), which does:
> >
> > #define __iowrite32_copy(to, from, count) \
> > (__builtin_constant_p(count) ? \
> > __const_iowrite32_copy(to, from, count) : \
> > __iowrite32_copy_full(to, from, count))
> >
> > ... and so __const_iowrite32_copy() should really be marked as __always_inline,
> > and the same for __const_memcpy_toio_aligned32(), to guarantee that both get
> > inlined and such that __const_memcpy_toio_aligned32() sees a constant.
> >
> > The same reasoning applies to __const_iowrite64_copy() and
> > __const_memcpy_toio_aligned64().
> >
> > Checking for a constant in __const_iowrite32_copy() doesn't guarantee
> > that __const_memcpy_toio_aligned32() is inlined and will actually see a
> > constant.
> >
> > Does diff the below you for you?
>
> Yes, your version addresses both failures I ran into, and
> I think all other theoretical cases.
>
> I would prefer to combine both though, using __always_inline
> to force the compiler to pick the inline version over
> __iowrite32_copy_full() even when it is optimizing for size
> and it decides the inline version is larger, but removing
> the extra complexity from the macro.
Sorry, I'm not sure what you mean here. I don't see anything handling
optimizing for size today so I'm not sure what change your suggesting to
force the use of the inline version; AFAICT that'd always be forced for
a suitable constant size.
What change are you suggesting?
> According to Jason, he used a macro here to be sure
> that the compiler can detect an inline function argument
> as constant when the value is known but it is not
> a constant value according to the C standard.
>
> This was indeed a problem in older versions of clang
> that missed a lot of optimizations in the kernel, but
> clang-8 and higher were changed to have the same behavior
> as gcc here, so it is no longer necessary now that the
> older versions are unable to build kernels.
Getting rid of the macro is fine by me.
Mark.
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v14 01/18] irqchip/sifive-plic: Convert PLIC driver into a platform driver
@ 2024-05-29 14:22 4% ` Geert Uytterhoeven
2024-05-29 22:04 0% ` Samuel Holland
0 siblings, 1 reply; 200+ results
From: Geert Uytterhoeven @ 2024-05-29 14:22 UTC (permalink / raw)
To: Anup Patel
Cc: Palmer Dabbelt, Paul Walmsley, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Frank Rowand, Conor Dooley, Marc Zyngier,
Björn Töpel, Atish Patra, Andrew Jones, Sunil V L,
Saravana Kannan, Anup Patel, linux-riscv, linux-arm-kernel,
linux-kernel, devicetree, Emil Renner Berthing
Hi Anup,
On Thu, Feb 22, 2024 at 10:41 AM Anup Patel <apatel@ventanamicro.com> wrote:
> The PLIC driver does not require very early initialization so convert
> it into a platform driver.
>
> After conversion, the PLIC driver is probed after CPUs are brought-up
> so setup cpuhp state after context handler of all online CPUs are
> initialized otherwise PLIC driver crashes for platforms with multiple
> PLIC instances.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Thanks for your patch, which is now commit 8ec99b033147ef3b
("irqchip/sifive-plic: Convert PLIC driver into a platform
driver") in v6.9.
It looks like this conversion is causing issues on BeagleV Starlight
Beta. After updating esmil/visionfive to v6.10-rc1, the kernel usually
fails to boot. Adding "earlycon keep_bootcon" reveals these differences:
-riscv-plic c000000.interrupt-controller: mapped 133 interrupts with 2
handlers for 4 contexts.
+------------[ cut here ]------------
+WARNING: CPU: 0 PID: 1 at drivers/irqchip/irq-sifive-plic.c:373
plic_handle_irq+0xf2/0xf6
+Modules linked in:
+CPU: 0 PID: 1 Comm: swapper/0 Not tainted
6.10.0-rc1-starlight-02342-g0ba4c76ca0e8-dirty #323
+Hardware name: BeagleV Starlight Beta (DT)
+epc : plic_handle_irq+0xf2/0xf6
+ ra : generic_handle_domain_irq+0x1c/0x2a
+epc : ffffffff8033f994 ra : ffffffff8006319a sp : ffffffc800003f50
+ gp : ffffffff812d63f0 tp : ffffffd8800b8000 t0 : 0000000000000040
+ t1 : 0000000000000000 t2 : 0000000000001000 s0 : ffffffc800003fa0
+ s1 : 0000000000000009 a0 : ffffffd880183600 a1 : 0000000000000009
+ a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000
+ a5 : 0000000000000000 a6 : ffffffd880400248 a7 : ffffffd8804002b8
+ s2 : ffffffd9f8fac458 s3 : 0000000000000004 s4 : 0000000000000000
+ s5 : ffffffff81293f58 s6 : ffffffd88014ac00 s7 : 0000000000000004
+ s8 : ffffffc800013b2c s9 : ffffffc800013b34 s10: 0000000000000006
+ s11: ffffffd9f8fc1458 t3 : 0000000000000002 t4 : 0000000000000402
+ t5 : ffffffd8800610c0 t6 : ffffffd8800610e0
+status: 0000000200000100 badaddr: ffffffd9f8fac458 cause: 0000000000000003
+[<ffffffff8033f994>] plic_handle_irq+0xf2/0xf6
+[<ffffffff8006319a>] generic_handle_domain_irq+0x1c/0x2a
+[<ffffffff8033d7aa>] riscv_intc_irq+0x26/0x60
+[<ffffffff806c92ee>] handle_riscv_irq+0x4a/0x74
+[<ffffffff806d2346>] call_on_irq_stack+0x32/0x40
+---[ end trace 0000000000000000 ]---
+Unable to handle kernel NULL pointer dereference at virtual address
0000000000000004
+Oops [#1]
+Modules linked in:
+CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W
6.10.0-rc1-starlight-02342-g0ba4c76ca0e8-dirty #323
+Hardware name: BeagleV Starlight Beta (DT)
+epc : plic_handle_irq+0x66/0xf6
+ ra : generic_handle_domain_irq+0x1c/0x2a
+epc : ffffffff8033f908 ra : ffffffff8006319a sp : ffffffc800003f50
+ gp : ffffffff812d63f0 tp : ffffffd8800b8000 t0 : 0000000000000040
+ t1 : 0000000000000000 t2 : 0000000000001000 s0 : ffffffc800003fa0
+ s1 : 0000000000000009 a0 : ffffffd880183600 a1 : 0000000000000009
+ a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000
+ a5 : ffffffff8033d72a a6 : ffffffd880400248 a7 : ffffffd8804002b8
+ s2 : ffffffd9f8fac458 s3 : 0000000000000004 s4 : ffffffd880183630
+ s5 : ffffffff81293f58 s6 : ffffffff812948a0 s7 : ffffffff80c4e660
+ s8 : ffffffff80d9eea0 s9 : ffffffc800013b34 s10: 0000000000000006
+ s11: ffffffd9f8fc1458 t3 : 0000000000000002 t4 : 0000000000000402
+ t5 : ffffffd8800610c0 t6 : ffffffd8800610e0
+status: 0000000200000100 badaddr: 0000000000000004 cause: 000000000000000d
+[<ffffffff8033f908>] plic_handle_irq+0x66/0xf6
+[<ffffffff8006319a>] generic_handle_domain_irq+0x1c/0x2a
+[<ffffffff8033d7aa>] riscv_intc_irq+0x26/0x60
+[<ffffffff806c92ee>] handle_riscv_irq+0x4a/0x74
+[<ffffffff806d2346>] call_on_irq_stack+0x32/0x40
+Code: 8b93 d70b 5b17 00f5 0b13 fa8b fc17 00a5 0c13 5a0c (a783) 0009
+---[ end trace 0000000000000000 ]---
+Kernel panic - not syncing: Fatal exception in interrupt
+SMP: stopping secondary CPUs
+---[ end Kernel panic - not syncing: Fatal exception in interrupt ]---
As "mapped 133 interrupts" is no longer printed, it looks like an
unexpected early interrupt comes in while still in plic_probe().
Esmil suggested reverting all of:
a7fb69ffd7ce438a irqchip/sifive-plic: Avoid explicit cpumask allocation on stack
abb7205794900503 irqchip/sifive-plic: Improve locking safety by using
irqsave/irqrestore
95652106478030f5 irqchip/sifive-plic: Parse number of interrupts and
contexts early in plic_probe()
a15587277a246c38 irqchip/sifive-plic: Cleanup PLIC contexts upon
irqdomain creation failure
6c725f33d67b53f2 irqchip/sifive-plic: Use riscv_get_intc_hwnode() to
get parent fwnode
b68d0ff529a939a1 irqchip/sifive-plic: Use devm_xyz() for managed allocation
25d862e183d4efeb irqchip/sifive-plic: Use dev_xyz() in-place of pr_xyz()
8ec99b033147ef3b irqchip/sifive-plic: Convert PLIC driver into a platform driver
After this, the PLIC is initialized earlier again, and this indeed
seems to fix the issue for me.
Before, the kernel booted fine in only ca. 1 out of 5 tries.
After the reverts, it booted 5/5.
Do you know what's going on? Is there a simpler fix?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 4%]
* [PATCH v10 19/19] cpumask: Add enabled cpumask for present CPUs that can be brought online
2024-05-29 13:34 5% ` [PATCH v10 17/19] arm64: Kconfig: Enable hotplug CPU on arm64 if ACPI_PROCESSOR is enabled Jonathan Cameron
@ 2024-05-29 13:34 4% ` Jonathan Cameron
1 sibling, 0 replies; 200+ results
From: Jonathan Cameron @ 2024-05-29 13:34 UTC (permalink / raw)
To: Marc Zyngier, Will Deacon, Catalin Marinas, linux-acpi,
linux-arch, linux-kernel, linux-arm-kernel, linux-pm
Cc: Mark Rutland, Thomas Gleixner, Peter Zijlstra, loongarch, x86,
Russell King, Rafael J . Wysocki, Miguel Luis, James Morse,
Salil Mehta, Jean-Philippe Brucker, Hanjun Guo, Gavin Shan,
Ingo Molnar, Borislav Petkov, Dave Hansen, linuxarm, justin.he,
jianyong.wu
From: James Morse <james.morse@arm.com>
The 'offline' file in sysfs shows all offline CPUs, including those
that aren't present. User-space is expected to remove not-present CPUs
from this list to learn which CPUs could be brought online.
CPUs can be present but not-enabled. These CPUs can't be brought online
until the firmware policy changes, which comes with an ACPI notification
that will register the CPUs.
With only the offline and present files, user-space is unable to
determine which CPUs it can try to bring online. Add a new CPU mask
that shows this based on all the registered CPUs.
Signed-off-by: James Morse <james.morse@arm.com>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
Tested-by: Vishnu Pajjuri <vishnu@os.amperecomputing.com>
Tested-by: Jianyong Wu <jianyong.wu@arm.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
.../ABI/testing/sysfs-devices-system-cpu | 6 +++++
drivers/base/cpu.c | 10 ++++++++
include/linux/cpumask.h | 25 +++++++++++++++++++
kernel/cpu.c | 3 +++
4 files changed, 44 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
index e7e160954e79..53ed1a803422 100644
--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
@@ -694,3 +694,9 @@ Description:
(RO) indicates whether or not the kernel directly supports
modifying the crash elfcorehdr for CPU hot un/plug and/or
on/offline changes.
+
+What: /sys/devices/system/cpu/enabled
+Date: Nov 2022
+Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
+Description:
+ (RO) the list of CPUs that can be brought online.
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index 1487cd9761a4..b57326fd48d4 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -95,6 +95,7 @@ void unregister_cpu(struct cpu *cpu)
{
int logical_cpu = cpu->dev.id;
+ set_cpu_enabled(logical_cpu, false);
unregister_cpu_under_node(logical_cpu, cpu_to_node(logical_cpu));
device_unregister(&cpu->dev);
@@ -273,6 +274,13 @@ static ssize_t print_cpus_offline(struct device *dev,
}
static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL);
+static ssize_t print_cpus_enabled(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(cpu_enabled_mask));
+}
+static DEVICE_ATTR(enabled, 0444, print_cpus_enabled, NULL);
+
static ssize_t print_cpus_isolated(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -413,6 +421,7 @@ int register_cpu(struct cpu *cpu, int num)
register_cpu_under_node(num, cpu_to_node(num));
dev_pm_qos_expose_latency_limit(&cpu->dev,
PM_QOS_RESUME_LATENCY_NO_CONSTRAINT);
+ set_cpu_enabled(num, true);
return 0;
}
@@ -494,6 +503,7 @@ static struct attribute *cpu_root_attrs[] = {
&cpu_attrs[2].attr.attr,
&dev_attr_kernel_max.attr,
&dev_attr_offline.attr,
+ &dev_attr_enabled.attr,
&dev_attr_isolated.attr,
#ifdef CONFIG_NO_HZ_FULL
&dev_attr_nohz_full.attr,
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index 23686bed441d..954d4adc8f81 100644
--- a/include/linux/cpumask.h
+++ b/include/linux/cpumask.h
@@ -93,6 +93,7 @@ static inline void set_nr_cpu_ids(unsigned int nr)
*
* cpu_possible_mask- has bit 'cpu' set iff cpu is populatable
* cpu_present_mask - has bit 'cpu' set iff cpu is populated
+ * cpu_enabled_mask - has bit 'cpu' set iff cpu can be brought online
* cpu_online_mask - has bit 'cpu' set iff cpu available to scheduler
* cpu_active_mask - has bit 'cpu' set iff cpu available to migration
*
@@ -125,11 +126,13 @@ static inline void set_nr_cpu_ids(unsigned int nr)
extern struct cpumask __cpu_possible_mask;
extern struct cpumask __cpu_online_mask;
+extern struct cpumask __cpu_enabled_mask;
extern struct cpumask __cpu_present_mask;
extern struct cpumask __cpu_active_mask;
extern struct cpumask __cpu_dying_mask;
#define cpu_possible_mask ((const struct cpumask *)&__cpu_possible_mask)
#define cpu_online_mask ((const struct cpumask *)&__cpu_online_mask)
+#define cpu_enabled_mask ((const struct cpumask *)&__cpu_enabled_mask)
#define cpu_present_mask ((const struct cpumask *)&__cpu_present_mask)
#define cpu_active_mask ((const struct cpumask *)&__cpu_active_mask)
#define cpu_dying_mask ((const struct cpumask *)&__cpu_dying_mask)
@@ -1075,6 +1078,7 @@ extern const DECLARE_BITMAP(cpu_all_bits, NR_CPUS);
#else
#define for_each_possible_cpu(cpu) for_each_cpu((cpu), cpu_possible_mask)
#define for_each_online_cpu(cpu) for_each_cpu((cpu), cpu_online_mask)
+#define for_each_enabled_cpu(cpu) for_each_cpu((cpu), cpu_enabled_mask)
#define for_each_present_cpu(cpu) for_each_cpu((cpu), cpu_present_mask)
#endif
@@ -1092,6 +1096,15 @@ set_cpu_possible(unsigned int cpu, bool possible)
cpumask_clear_cpu(cpu, &__cpu_possible_mask);
}
+static inline void
+set_cpu_enabled(unsigned int cpu, bool can_be_onlined)
+{
+ if (can_be_onlined)
+ cpumask_set_cpu(cpu, &__cpu_enabled_mask);
+ else
+ cpumask_clear_cpu(cpu, &__cpu_enabled_mask);
+}
+
static inline void
set_cpu_present(unsigned int cpu, bool present)
{
@@ -1173,6 +1186,7 @@ static __always_inline unsigned int num_online_cpus(void)
return raw_atomic_read(&__num_online_cpus);
}
#define num_possible_cpus() cpumask_weight(cpu_possible_mask)
+#define num_enabled_cpus() cpumask_weight(cpu_enabled_mask)
#define num_present_cpus() cpumask_weight(cpu_present_mask)
#define num_active_cpus() cpumask_weight(cpu_active_mask)
@@ -1181,6 +1195,11 @@ static inline bool cpu_online(unsigned int cpu)
return cpumask_test_cpu(cpu, cpu_online_mask);
}
+static inline bool cpu_enabled(unsigned int cpu)
+{
+ return cpumask_test_cpu(cpu, cpu_enabled_mask);
+}
+
static inline bool cpu_possible(unsigned int cpu)
{
return cpumask_test_cpu(cpu, cpu_possible_mask);
@@ -1205,6 +1224,7 @@ static inline bool cpu_dying(unsigned int cpu)
#define num_online_cpus() 1U
#define num_possible_cpus() 1U
+#define num_enabled_cpus() 1U
#define num_present_cpus() 1U
#define num_active_cpus() 1U
@@ -1218,6 +1238,11 @@ static inline bool cpu_possible(unsigned int cpu)
return cpu == 0;
}
+static inline bool cpu_enabled(unsigned int cpu)
+{
+ return cpu == 0;
+}
+
static inline bool cpu_present(unsigned int cpu)
{
return cpu == 0;
diff --git a/kernel/cpu.c b/kernel/cpu.c
index 563877d6c28b..a2f3ad276814 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -3069,6 +3069,9 @@ EXPORT_SYMBOL(__cpu_possible_mask);
struct cpumask __cpu_online_mask __read_mostly;
EXPORT_SYMBOL(__cpu_online_mask);
+struct cpumask __cpu_enabled_mask __read_mostly;
+EXPORT_SYMBOL(__cpu_enabled_mask);
+
struct cpumask __cpu_present_mask __read_mostly;
EXPORT_SYMBOL(__cpu_present_mask);
--
2.39.2
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^ permalink raw reply related [relevance 4%]
* [PATCH v10 17/19] arm64: Kconfig: Enable hotplug CPU on arm64 if ACPI_PROCESSOR is enabled.
@ 2024-05-29 13:34 5% ` Jonathan Cameron
2024-05-29 13:34 4% ` [PATCH v10 19/19] cpumask: Add enabled cpumask for present CPUs that can be brought online Jonathan Cameron
1 sibling, 0 replies; 200+ results
From: Jonathan Cameron @ 2024-05-29 13:34 UTC (permalink / raw)
To: Marc Zyngier, Will Deacon, Catalin Marinas, linux-acpi,
linux-arch, linux-kernel, linux-arm-kernel, linux-pm
Cc: Mark Rutland, Thomas Gleixner, Peter Zijlstra, loongarch, x86,
Russell King, Rafael J . Wysocki, Miguel Luis, James Morse,
Salil Mehta, Jean-Philippe Brucker, Hanjun Guo, Gavin Shan,
Ingo Molnar, Borislav Petkov, Dave Hansen, linuxarm, justin.he,
jianyong.wu
In order to move arch_register_cpu() to be called via the same path
for initially present CPUs described by ACPI and hotplugged CPUs
ACPI_HOTPLUG_CPU needs to be enabled.
The protection against invalid IDs in acpi_map_cpu() is needed as
at least one production BIOS is in the wild which reports entries
in DSDT (with no _STA method, so assumed enabled and present)
that don't match MADT.
Tested-by: Miguel Luis <miguel.luis@oracle.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/acpi.c | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 5d91259ee7b5..e8f2ef2312db 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -5,6 +5,7 @@ config ARM64
select ACPI_CCA_REQUIRED if ACPI
select ACPI_GENERIC_GSI if ACPI
select ACPI_GTDT if ACPI
+ select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR
select ACPI_IORT if ACPI
select ACPI_REDUCED_HARDWARE_ONLY if ACPI
select ACPI_MCFG if (ACPI && PCI)
diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index e0e7b93c16cc..9360ba86678b 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -30,6 +30,7 @@
#include <linux/pgtable.h>
#include <acpi/ghes.h>
+#include <acpi/processor.h>
#include <asm/cputype.h>
#include <asm/cpu_ops.h>
#include <asm/daifflags.h>
@@ -423,6 +424,27 @@ void arch_reserve_mem_area(acpi_physical_address addr, size_t size)
memblock_mark_nomap(addr, size);
}
+#ifdef CONFIG_ACPI_HOTPLUG_CPU
+int acpi_map_cpu(acpi_handle handle, phys_cpuid_t physid, u32 apci_id,
+ int *pcpu)
+{
+ /* If an error code is passed in this stub can't fix it */
+ if (*pcpu < 0) {
+ pr_warn_once("Unable to map CPU to valid ID\n");
+ return *pcpu;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(acpi_map_cpu);
+
+int acpi_unmap_cpu(int cpu)
+{
+ return 0;
+}
+EXPORT_SYMBOL(acpi_unmap_cpu);
+#endif /* CONFIG_ACPI_HOTPLUG_CPU */
+
#ifdef CONFIG_ACPI_FFH
/*
* Implements ARM64 specific callbacks to support ACPI FFH Operation Region as
--
2.39.2
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^ permalink raw reply related [relevance 5%]
* Re: [PATCH] arm64/io: add constant-argument check
@ 2024-05-29 12:29 5% ` Arnd Bergmann
2024-05-29 15:08 0% ` Mark Rutland
0 siblings, 1 reply; 200+ results
From: Arnd Bergmann @ 2024-05-29 12:29 UTC (permalink / raw)
To: Mark Rutland, Arnd Bergmann
Cc: Catalin Marinas, Will Deacon, Jason Gunthorpe,
Valentin Schneider, Baoquan He, Peter Zijlstra, linux-arm-kernel,
linux-kernel
On Wed, May 29, 2024, at 13:14, Mark Rutland wrote:
>> {
>> - if (count == 8 || count == 4 || count == 2 || count == 1) {
>> + if (__builtin_constant_p(count) &&
>> + (count == 8 || count == 4 || count == 2 || count == 1)) {
>> __const_memcpy_toio_aligned32(to, from, count);
>> dgh();
>> } else {
>
> I don't think this is the right fix.
>
> The idea was that this was checked in __iowrite32_copy(), which does:
>
> #define __iowrite32_copy(to, from, count) \
> (__builtin_constant_p(count) ? \
> __const_iowrite32_copy(to, from, count) : \
> __iowrite32_copy_full(to, from, count))
>
> ... and so __const_iowrite32_copy() should really be marked as __always_inline,
> and the same for __const_memcpy_toio_aligned32(), to guarantee that both get
> inlined and such that __const_memcpy_toio_aligned32() sees a constant.
>
> The same reasoning applies to __const_iowrite64_copy() and
> __const_memcpy_toio_aligned64().
>
> Checking for a constant in __const_iowrite32_copy() doesn't guarantee
> that __const_memcpy_toio_aligned32() is inlined and will actually see a
> constant.
>
> Does diff the below you for you?
Yes, your version addresses both failures I ran into, and
I think all other theoretical cases.
I would prefer to combine both though, using __always_inline
to force the compiler to pick the inline version over
__iowrite32_copy_full() even when it is optimizing for size
and it decides the inline version is larger, but removing
the extra complexity from the macro.
According to Jason, he used a macro here to be sure
that the compiler can detect an inline function argument
as constant when the value is known but it is not
a constant value according to the C standard.
This was indeed a problem in older versions of clang
that missed a lot of optimizations in the kernel, but
clang-8 and higher were changed to have the same behavior
as gcc here, so it is no longer necessary now that the
older versions are unable to build kernels.
Arnd
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^ permalink raw reply [relevance 5%]
* [PATCH v7 2/2] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support
@ 2024-05-29 6:02 6% ` Richard Zhu
0 siblings, 0 replies; 200+ results
From: Richard Zhu @ 2024-05-29 6:02 UTC (permalink / raw)
To: conor, vkoul, kishon, robh+dt, krzysztof.kozlowski+dt, frank.li,
conor+dt
Cc: hongxing.zhu, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, kernel, imx
Add i.MX8QM HSIO PHY driver support.
i.MX8QM HSIO has three lane PHY instances, and can be bound to the
following controllers in the different use cases listed in below table.
- two lanes capable PCIEA controller.
- one lane PCIEB controller.
- AHCI SATA controller.
i.MX8QM HSIO PHYs support the following use cases.
+----------------------------------------------------+
| | Lane0| Lane1| Lane2|
|-------------------------------|------|------|------|
| use case 1: PCIEAX2SATA | PCIEA| PCIEA| SATA |
|-------------------------------|------|------|------|
| use case 2: PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB|
|-------------------------------|------|------|------|
| use case 3: PCIEAPCIEBSATA | PCIEA| PCIEB| SATA |
+----------------------------------------------------+
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
drivers/phy/freescale/Kconfig | 9 +-
drivers/phy/freescale/Makefile | 1 +
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 610 ++++++++++++++++++++
3 files changed, 619 insertions(+), 1 deletion(-)
create mode 100644 drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index 45aaaea14fb4..dcd9acff6d01 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -35,12 +35,19 @@ config PHY_FSL_IMX8M_PCIE
Enable this to add support for the PCIE PHY as found on
i.MX8M family of SOCs.
+config PHY_FSL_IMX8QM_HSIO
+ tristate "Freescale i.MX8QM HSIO PHY"
+ depends on OF && HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Enable this to add support for the HSIO PHY as found on
+ i.MX8QM family of SOCs.
+
config PHY_FSL_SAMSUNG_HDMI_PHY
tristate "Samsung HDMI PHY support"
depends on OF && HAS_IOMEM && COMMON_CLK
help
Enable this to add support for the Samsung HDMI PHY in i.MX8MP.
-
endif
config PHY_FSL_LYNX_28G
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index c4386bfdb853..658eac7d0a62 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -3,5 +3,6 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
+obj-$(CONFIG_PHY_FSL_IMX8QM_HSIO) += phy-fsl-imx8qm-hsio.o
obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
obj-$(CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY) += phy-fsl-samsung-hdmi.o
diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
new file mode 100644
index 000000000000..dcf9c45ff5d6
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
@@ -0,0 +1,610 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pci_regs.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/pcie.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#define MAX_NUM_LANE 3
+#define LANE_NUM_CLKS 5
+
+/* Parameters for the waiting for PCIe PHY PLL to lock */
+#define PHY_INIT_WAIT_USLEEP_MAX 10
+#define PHY_INIT_WAIT_TIMEOUT (1000 * PHY_INIT_WAIT_USLEEP_MAX)
+
+/* i.MX8Q HSIO registers */
+#define HSIO_CTRL0 0x0
+#define HSIO_APB_RSTN_0 BIT(0)
+#define HSIO_APB_RSTN_1 BIT(1)
+#define HSIO_PIPE_RSTN_0_MASK GENMASK(25, 24)
+#define HSIO_PIPE_RSTN_1_MASK GENMASK(27, 26)
+#define HSIO_MODE_MASK GENMASK(20, 17)
+#define HSIO_MODE_PCIE 0x0
+#define HSIO_MODE_SATA 0x4
+#define HSIO_DEVICE_TYPE_MASK GENMASK(27, 24)
+#define HSIO_EPCS_TXDEEMP BIT(5)
+#define HSIO_EPCS_TXDEEMP_SEL BIT(6)
+#define HSIO_EPCS_PHYRESET_N BIT(7)
+#define HSIO_RESET_N BIT(12)
+
+#define HSIO_IOB_RXENA BIT(0)
+#define HSIO_IOB_TXENA BIT(1)
+#define HSIO_IOB_A_0_TXOE BIT(2)
+#define HSIO_IOB_A_0_M1M0_2 BIT(4)
+#define HSIO_IOB_A_0_M1M0_MASK GENMASK(4, 3)
+#define HSIO_PHYX1_EPCS_SEL BIT(12)
+#define HSIO_PCIE_AB_SELECT BIT(13)
+
+#define HSIO_PHY_STS0 0x4
+#define HSIO_LANE0_TX_PLL_LOCK BIT(4)
+#define HSIO_LANE1_TX_PLL_LOCK BIT(12)
+
+#define HSIO_CTRL2 0x8
+#define HSIO_LTSSM_ENABLE BIT(4)
+#define HSIO_BUTTON_RST_N BIT(21)
+#define HSIO_PERST_N BIT(22)
+#define HSIO_POWER_UP_RST_N BIT(23)
+
+#define HSIO_PCIE_STS0 0xc
+#define HSIO_PM_REQ_CORE_RST BIT(19)
+
+#define HSIO_REG48_PMA_STATUS 0x30
+#define HSIO_REG48_PMA_RDY BIT(7)
+
+struct imx_hsio_drvdata {
+ int lane_num;
+};
+
+struct imx_hsio_lane {
+ u32 ctrl_index;
+ u32 ctrl_off;
+ u32 idx;
+ u32 phy_off;
+ u32 phy_type;
+ const char * const *clk_names;
+ struct clk_bulk_data clks[LANE_NUM_CLKS];
+ struct imx_hsio_priv *priv;
+ struct phy *phy;
+ enum phy_mode phy_mode;
+};
+
+struct imx_hsio_priv {
+ void __iomem *base;
+ struct device *dev;
+ struct mutex lock;
+ const char *hsio_cfg;
+ const char *refclk_pad;
+ u32 open_cnt;
+ struct regmap *phy;
+ struct regmap *ctrl;
+ struct regmap *misc;
+ const struct imx_hsio_drvdata *drvdata;
+ struct imx_hsio_lane lane[MAX_NUM_LANE];
+};
+
+static const char * const lan0_pcie_clks[] = {"apb_pclk0", "pclk0", "ctl0_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan1_pciea_clks[] = {"apb_pclk1", "pclk1", "ctl0_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan1_pcieb_clks[] = {"apb_pclk1", "pclk1", "ctl1_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan2_pcieb_clks[] = {"apb_pclk2", "pclk2", "ctl1_crr",
+ "phy1_crr", "misc_crr"};
+static const char * const lan2_sata_clks[] = {"pclk2", "epcs_tx", "epcs_rx",
+ "phy1_crr", "misc_crr"};
+
+static const struct regmap_config regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int imx_hsio_init(struct phy *phy)
+{
+ int ret, i;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+ struct device *dev = priv->dev;
+
+ /* Assign clocks refer to different modes */
+ switch (lane->phy_type) {
+ case PHY_TYPE_PCIE:
+ lane->phy_mode = PHY_MODE_PCIE;
+ if (lane->ctrl_index == 0) { /* PCIEA */
+ lane->ctrl_off = 0;
+ lane->phy_off = 0;
+
+ for (i = 0; i < LANE_NUM_CLKS; i++) {
+ if (lane->idx == 0)
+ lane->clks[i].id = lan0_pcie_clks[i];
+ else
+ lane->clks[i].id = lan1_pciea_clks[i];
+ }
+ } else { /* PCIEB */
+ if (lane->idx == 0) { /* i.MX8QXP */
+ lane->ctrl_off = 0;
+ lane->phy_off = 0;
+ } else {
+ /*
+ * On i.MX8QM, only second or third lane can be
+ * bound to PCIEB.
+ */
+ lane->ctrl_off = SZ_64K;
+ if (lane->idx == 1)
+ lane->phy_off = 0;
+ else /* the third lane is bound to PCIEB */
+ lane->phy_off = SZ_64K;
+ }
+
+ for (i = 0; i < LANE_NUM_CLKS; i++) {
+ if (lane->idx == 1)
+ lane->clks[i].id = lan1_pcieb_clks[i];
+ else if (lane->idx == 2)
+ lane->clks[i].id = lan2_pcieb_clks[i];
+ else /* i.MX8QXP only has PCIEB, idx is 0 */
+ lane->clks[i].id = lan0_pcie_clks[i];
+ }
+ }
+ break;
+ case PHY_TYPE_SATA:
+ /* On i.MX8QM, only the third lane can be bound to SATA */
+ lane->phy_mode = PHY_MODE_SATA;
+ lane->ctrl_off = SZ_128K;
+ lane->phy_off = SZ_64K;
+
+ for (i = 0; i < LANE_NUM_CLKS; i++)
+ lane->clks[i].id = lan2_sata_clks[i];
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Fetch clocks and enable them */
+ ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, lane->clks);
+ if (ret)
+ return ret;
+ ret = clk_bulk_prepare_enable(LANE_NUM_CLKS, lane->clks);
+ if (ret)
+ return ret;
+
+ /* allow the clocks to stabilize */
+ usleep_range(200, 500);
+ return 0;
+}
+
+static int imx_hsio_exit(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+
+ clk_bulk_disable_unprepare(LANE_NUM_CLKS, lane->clks);
+
+ return 0;
+}
+
+static void imx_hsio_pcie_phy_resets(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+
+ if (lane->idx == 1) {
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_1);
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_1_MASK);
+ } else {
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_0);
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_0_MASK);
+ }
+}
+
+static void imx_hsio_sata_phy_resets(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ /* clear PHY RST, then set it */
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_PHYRESET_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_PHYRESET_N);
+
+ /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
+ udelay(1);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_RESET_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
+}
+
+static void imx_hsio_configure_clk_pad(struct phy *phy)
+{
+ bool pll = false;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (strncmp(priv->refclk_pad, "output", 6) == 0) {
+ pll = true;
+ regmap_update_bits(priv->misc, HSIO_CTRL0,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_2);
+ } else {
+ regmap_update_bits(priv->misc, HSIO_CTRL0,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
+ 0);
+ }
+
+ regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_RXENA,
+ pll ? 0 : HSIO_IOB_RXENA);
+ regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_TXENA,
+ pll ? HSIO_IOB_TXENA : 0);
+}
+
+static void imx_hsio_pre_set(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (strncmp(priv->hsio_cfg, "pciea-x2-pcieb", 14) == 0) {
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
+ } else if (strncmp(priv->hsio_cfg, "pciea-x2-sata", 13) == 0) {
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
+ } else if (strncmp(priv->hsio_cfg, "pciea-pcieb-sata", 16) == 0) {
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
+ }
+
+ imx_hsio_configure_clk_pad(phy);
+}
+
+static int imx_hsio_pcie_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, addr, cond;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ imx_hsio_pcie_phy_resets(phy);
+
+ /* Toggle apb_pclk to make sure PM_REQ_CORE_RST is cleared. */
+ clk_disable_unprepare(lane->clks[0].clk);
+ mdelay(1);
+ ret = clk_prepare_enable(lane->clks[0].clk);
+ if (ret) {
+ dev_err(priv->dev, "unable to enable phy apb_pclk\n");
+ return ret;
+ }
+
+ addr = lane->ctrl_off + HSIO_PCIE_STS0;
+ cond = HSIO_PM_REQ_CORE_RST;
+ ret = regmap_read_poll_timeout(priv->ctrl, addr, val,
+ (val & cond) == 0,
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT);
+ if (ret)
+ dev_err(priv->dev, "HSIO_PM_REQ_CORE_RST is set\n");
+ return ret;
+}
+
+static int imx_hsio_sata_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, cond;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0, HSIO_APB_RSTN_0);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP_SEL);
+
+ imx_hsio_sata_phy_resets(phy);
+
+ cond = HSIO_REG48_PMA_RDY;
+ ret = read_poll_timeout(readb, val, ((val & cond) == cond),
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT, false,
+ priv->base + HSIO_REG48_PMA_STATUS);
+ if (ret)
+ dev_err(priv->dev, "PHY calibration is timeout\n");
+ else
+ dev_dbg(priv->dev, "PHY calibration is done\n");
+
+ return ret;
+}
+
+static int imx_hsio_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, cond;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ scoped_guard(mutex, &priv->lock) {
+ if (!priv->open_cnt)
+ imx_hsio_pre_set(phy);
+ priv->open_cnt++;
+ }
+
+ if (lane->phy_mode == PHY_MODE_PCIE)
+ ret = imx_hsio_pcie_power_on(phy);
+ else /* SATA */
+ ret = imx_hsio_sata_power_on(phy);
+ if (ret)
+ return ret;
+
+ /* Polling to check the PHY is ready or not. */
+ if (lane->idx == 1)
+ cond = HSIO_LANE1_TX_PLL_LOCK;
+ else
+ /*
+ * Except the phy_off, the bit-offset of lane2 is same to lane0.
+ * Merge the lane0 and lane2 bit-operations together.
+ */
+ cond = HSIO_LANE0_TX_PLL_LOCK;
+
+ ret = regmap_read_poll_timeout(priv->phy, lane->phy_off + HSIO_PHY_STS0,
+ val, ((val & cond) == cond),
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT);
+ if (ret) {
+ dev_err(priv->dev, "IMX8Q PHY%d PLL lock timeout\n", lane->idx);
+ return ret;
+ }
+ dev_dbg(priv->dev, "IMX8Q PHY%d PLL is locked\n", lane->idx);
+
+ return ret;
+}
+
+static int imx_hsio_power_off(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ scoped_guard(mutex, &priv->lock) {
+ priv->open_cnt--;
+ if (priv->open_cnt == 0) {
+ regmap_clear_bits(priv->misc, HSIO_CTRL0,
+ HSIO_PCIE_AB_SELECT);
+ regmap_clear_bits(priv->misc, HSIO_CTRL0,
+ HSIO_PHYX1_EPCS_SEL);
+
+ if (lane->phy_mode == PHY_MODE_PCIE) {
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+ } else {
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP_SEL);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL0,
+ HSIO_RESET_N);
+ }
+
+ if (lane->idx == 1) {
+ regmap_clear_bits(priv->phy,
+ lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_1);
+ regmap_clear_bits(priv->phy,
+ lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_1_MASK);
+ } else {
+ /*
+ * Except the phy_off, the bit-offset of lane2 is same
+ * to lane0. Merge the lane0 and lane2 bit-operations
+ * together.
+ */
+ regmap_clear_bits(priv->phy,
+ lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_0);
+ regmap_clear_bits(priv->phy,
+ lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_0_MASK);
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int imx_hsio_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ u32 val;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (lane->phy_mode != mode)
+ return -EINVAL;
+
+ val = (mode == PHY_MODE_PCIE) ? HSIO_MODE_PCIE : HSIO_MODE_SATA;
+ val = FIELD_PREP(HSIO_MODE_MASK, val);
+ regmap_update_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_MODE_MASK, val);
+
+ switch (submode) {
+ case PHY_MODE_PCIE_RC:
+ val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
+ break;
+ case PHY_MODE_PCIE_EP:
+ val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ENDPOINT);
+ break;
+ default: /* Support only PCIe EP and RC now. */
+ return 0;
+ }
+ if (submode)
+ regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_DEVICE_TYPE_MASK, val);
+
+ return 0;
+}
+
+static int imx_hsio_set_speed(struct phy *phy, int speed)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_LTSSM_ENABLE,
+ speed ? HSIO_LTSSM_ENABLE : 0);
+ return 0;
+}
+
+static const struct phy_ops imx_hsio_ops = {
+ .init = imx_hsio_init,
+ .exit = imx_hsio_exit,
+ .power_on = imx_hsio_power_on,
+ .power_off = imx_hsio_power_off,
+ .set_mode = imx_hsio_set_mode,
+ .set_speed = imx_hsio_set_speed,
+ .owner = THIS_MODULE,
+};
+
+static const struct imx_hsio_drvdata imx8qxp_hsio_drvdata = {
+ .lane_num = 0x1,
+};
+
+static const struct imx_hsio_drvdata imx8qm_hsio_drvdata = {
+ .lane_num = 0x3,
+};
+
+static const struct of_device_id imx_hsio_of_match[] = {
+ {.compatible = "fsl,imx8qm-hsio", .data = &imx8qm_hsio_drvdata},
+ {.compatible = "fsl,imx8qxp-hsio", .data = &imx8qxp_hsio_drvdata},
+ { },
+};
+MODULE_DEVICE_TABLE(of, imx_hsio_of_match);
+
+static struct phy *imx_hsio_xlate(struct device *dev,
+ const struct of_phandle_args *args)
+{
+ struct imx_hsio_priv *priv = dev_get_drvdata(dev);
+ int idx = args->args[0];
+ int phy_type = args->args[1];
+ int ctrl_index = args->args[2];
+
+ if (idx < 0 || idx >= priv->drvdata->lane_num)
+ return ERR_PTR(-EINVAL);
+ priv->lane[idx].idx = idx;
+ priv->lane[idx].phy_type = phy_type;
+ priv->lane[idx].ctrl_index = ctrl_index;
+
+ return priv->lane[idx].phy;
+}
+
+static int imx_hsio_probe(struct platform_device *pdev)
+{
+ int i;
+ void __iomem *off;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct imx_hsio_priv *priv;
+ struct phy_provider *provider;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ priv->dev = &pdev->dev;
+ priv->drvdata = of_device_get_match_data(dev);
+
+ /* Get HSIO configuration mode */
+ if (of_property_read_string(np, "fsl,hsio-cfg", &priv->hsio_cfg))
+ priv->hsio_cfg = "pciea-pcieb-sata";
+ /* Get PHY refclk pad mode */
+ if (of_property_read_string(np, "fsl,refclk-pad-mode",
+ &priv->refclk_pad))
+ priv->refclk_pad = NULL;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ off = devm_platform_ioremap_resource_byname(pdev, "phy");
+ priv->phy = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->phy))
+ return dev_err_probe(dev, PTR_ERR(priv->phy),
+ "unable to find phy csr registers\n");
+
+ off = devm_platform_ioremap_resource_byname(pdev, "ctrl");
+ priv->ctrl = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->ctrl))
+ return dev_err_probe(dev, PTR_ERR(priv->ctrl),
+ "unable to find ctrl csr registers\n");
+
+ off = devm_platform_ioremap_resource_byname(pdev, "misc");
+ priv->misc = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->misc))
+ return dev_err_probe(dev, PTR_ERR(priv->misc),
+ "unable to find misc csr registers\n");
+
+ for (i = 0; i < priv->drvdata->lane_num; i++) {
+ struct imx_hsio_lane *lane = &priv->lane[i];
+ struct phy *phy;
+
+ phy = devm_phy_create(&pdev->dev, NULL, &imx_hsio_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ lane->priv = priv;
+ lane->phy = phy;
+ lane->idx = i;
+ phy_set_drvdata(phy, lane);
+ }
+
+ dev_set_drvdata(dev, priv);
+ dev_set_drvdata(&pdev->dev, priv);
+
+ provider = devm_of_phy_provider_register(&pdev->dev, imx_hsio_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver imx_hsio_driver = {
+ .probe = imx_hsio_probe,
+ .driver = {
+ .name = "imx8qm-hsio-phy",
+ .of_match_table = imx_hsio_of_match,
+ }
+};
+module_platform_driver(imx_hsio_driver);
+
+MODULE_DESCRIPTION("FSL IMX8QM HSIO SERDES PHY driver");
+MODULE_LICENSE("GPL");
--
2.37.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 6%]
* [PATCH v5 11/12] PCI: imx6: Call: Common PHY API to set mode, speed, and submode
` (2 preceding siblings ...)
2024-05-28 19:39 10% ` [PATCH v5 05/12] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li
@ 2024-05-28 19:39 5% ` Frank Li
3 siblings, 0 replies; 200+ results
From: Frank Li @ 2024-05-28 19:39 UTC (permalink / raw)
To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley
Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree,
Frank Li
Invoke the common PHY API to configure mode, speed, and submode. While
these functions are optional in the PHY interface, they are necessary for
certain PHY drivers. Lack of support for these functions in a PHY driver
does not cause harm.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index c8d58481f80dc..5a725ef6ed0cb 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -29,6 +29,7 @@
#include <linux/interrupt.h>
#include <linux/reset.h>
#include <linux/phy/phy.h>
+#include <linux/phy/pcie.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
@@ -306,6 +307,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
id = imx_pcie->controller_id;
+ /* If mode_mask[0] is 0, means use phy driver to set mode */
+ if (!drvdata->mode_mask[0])
+ return;
+
/* If mode_mask[id] is zero, means each controller have its individual gpr */
if (!drvdata->mode_mask[id])
id = 0;
@@ -882,6 +887,7 @@ static void imx_pcie_ltssm_enable(struct device *dev)
struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
+ phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB);
if (drvdata->ltssm_mask)
regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
drvdata->ltssm_mask);
@@ -894,6 +900,7 @@ static void imx_pcie_ltssm_disable(struct device *dev)
struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
+ phy_set_speed(imx_pcie->phy, 0);
if (drvdata->ltssm_mask)
regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
drvdata->ltssm_mask, 0);
@@ -1029,6 +1036,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
goto err_clk_disable;
}
+ ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
+ if (ret) {
+ dev_err(dev, "unable to set pcie PHY mode\n");
+ goto err_phy_off;
+ }
+
ret = phy_power_on(imx_pcie->phy);
if (ret) {
dev_err(dev, "waiting for PHY ready timeout!\n");
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* [PATCH v5 05/12] PCI: imx6: Simplify switch-case logic by involve core_reset callback
2024-05-28 19:39 7% ` [PATCH v5 03/12] PCI: imx6: Rename imx6_* with imx_* Frank Li
2024-05-28 19:39 5% ` [PATCH v5 04/12] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li
@ 2024-05-28 19:39 10% ` Frank Li
2024-05-28 19:39 5% ` [PATCH v5 11/12] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Frank Li
3 siblings, 0 replies; 200+ results
From: Frank Li @ 2024-05-28 19:39 UTC (permalink / raw)
To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley
Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree,
Frank Li
Instead of using the switch case statement to assert/dassert the core reset
handled by this driver itself, let's introduce a new callback core_reset()
and define it for platforms that require it. This simplifies the code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 134 ++++++++++++++++++----------------
1 file changed, 71 insertions(+), 63 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index c5d490afa981e..5e21fc942e90e 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -103,6 +103,7 @@ struct imx_pcie_drvdata {
const struct pci_epc_features *epc_features;
int (*init_phy)(struct imx_pcie *pcie);
int (*set_ref_clk)(struct imx_pcie *pcie, bool enable);
+ int (*core_reset)(struct imx_pcie *pcie, bool assert);
};
struct imx_pcie {
@@ -670,35 +671,75 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
}
+static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+ if (assert)
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
+
+ /* Force PCIe PHY reset */
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET,
+ assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0);
+ return 0;
+}
+
+static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST,
+ assert ? IMX6Q_GPR1_PCIE_SW_RST : 0);
+ if (!assert)
+ usleep_range(200, 500);
+
+ return 0;
+}
+
+static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+ if (!assert)
+ return 0;
+
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD);
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN);
+
+ return 0;
+}
+
+static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+ struct dw_pcie *pci = imx_pcie->pci;
+ struct device *dev = pci->dev;
+
+ if (assert)
+ return 0;
+
+ /*
+ * Workaround for ERR010728, failure of PCI-e PLL VCO to
+ * oscillate, especially when cold. This turns off "Duty-cycle
+ * Corrector" and other mysterious undocumented things.
+ */
+
+ if (likely(imx_pcie->phy_base)) {
+ /* De-assert DCC_FB_EN */
+ writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
+ /* Assert RX_EQS and RX_EQS_SEL */
+ writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ,
+ imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
+ /* Assert ATT_MODE */
+ writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
+ } else {
+ dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
+ }
+ imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
+ return 0;
+}
+
static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
{
reset_control_assert(imx_pcie->pciephy_reset);
reset_control_assert(imx_pcie->apps_reset);
- switch (imx_pcie->drvdata->variant) {
- case IMX6SX:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
- IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
- IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
- /* Force PCIe PHY reset */
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
- IMX6SX_GPR5_PCIE_BTNRST_RESET,
- IMX6SX_GPR5_PCIE_BTNRST_RESET);
- break;
- case IMX6QP:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_SW_RST,
- IMX6Q_GPR1_PCIE_SW_RST);
- break;
- case IMX6Q:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
- break;
- default:
- break;
- }
+ if (imx_pcie->drvdata->core_reset)
+ imx_pcie->drvdata->core_reset(imx_pcie, true);
/* Some boards don't have PCIe reset GPIO. */
gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);
@@ -706,47 +747,10 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
{
- struct dw_pcie *pci = imx_pcie->pci;
- struct device *dev = pci->dev;
-
reset_control_deassert(imx_pcie->pciephy_reset);
- switch (imx_pcie->drvdata->variant) {
- case IMX7D:
- /* Workaround for ERR010728, failure of PCI-e PLL VCO to
- * oscillate, especially when cold. This turns off "Duty-cycle
- * Corrector" and other mysterious undocumented things.
- */
- if (likely(imx_pcie->phy_base)) {
- /* De-assert DCC_FB_EN */
- writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
- imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
- /* Assert RX_EQS and RX_EQS_SEL */
- writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
- | PCIE_PHY_CMN_REG24_RX_EQ,
- imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
- /* Assert ATT_MODE */
- writel(PCIE_PHY_CMN_REG26_ATT_MODE,
- imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
- } else {
- dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
- }
-
- imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
- break;
- case IMX6SX:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
- IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
- break;
- case IMX6QP:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_SW_RST, 0);
-
- usleep_range(200, 500);
- break;
- default:
- break;
- }
+ if (imx_pcie->drvdata->core_reset)
+ imx_pcie->drvdata->core_reset(imx_pcie, false);
/* Some boards don't have PCIe reset GPIO. */
if (imx_pcie->reset_gpiod) {
@@ -1442,6 +1446,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx_pcie_init_phy,
.set_ref_clk = imx6q_pcie_set_ref_clk,
+ .core_reset = imx6q_pcie_core_reset,
},
[IMX6SX] = {
.variant = IMX6SX,
@@ -1457,6 +1462,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx6sx_pcie_init_phy,
.set_ref_clk = imx6sx_pcie_set_ref_clk,
+ .core_reset = imx6sx_pcie_core_reset,
},
[IMX6QP] = {
.variant = IMX6QP,
@@ -1473,6 +1479,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx_pcie_init_phy,
.set_ref_clk = imx6q_pcie_set_ref_clk,
+ .core_reset = imx6qp_pcie_core_reset,
},
[IMX7D] = {
.variant = IMX7D,
@@ -1486,6 +1493,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx7d_pcie_init_phy,
.set_ref_clk = imx7d_pcie_set_ref_clk,
+ .core_reset = imx7d_pcie_core_reset,
},
[IMX8MQ] = {
.variant = IMX8MQ,
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 10%]
* [PATCH v5 04/12] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
2024-05-28 19:39 7% ` [PATCH v5 03/12] PCI: imx6: Rename imx6_* with imx_* Frank Li
@ 2024-05-28 19:39 5% ` Frank Li
2024-05-28 19:39 10% ` [PATCH v5 05/12] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li
2024-05-28 19:39 5% ` [PATCH v5 11/12] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Frank Li
3 siblings, 0 replies; 200+ results
From: Frank Li @ 2024-05-28 19:39 UTC (permalink / raw)
To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley
Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree,
Frank Li
Instead of using the switch case statement to enable/disable the reference
clock handled by this driver itself, let's introduce a new callback
set_ref_clk() and define it for platforms that require it. This simplifies
the code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 112 ++++++++++++++++------------------
1 file changed, 52 insertions(+), 60 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 72e973312d203..c5d490afa981e 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -102,6 +102,7 @@ struct imx_pcie_drvdata {
const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
const struct pci_epc_features *epc_features;
int (*init_phy)(struct imx_pcie *pcie);
+ int (*set_ref_clk)(struct imx_pcie *pcie, bool enable);
};
struct imx_pcie {
@@ -583,21 +584,19 @@ static int imx_pcie_attach_pd(struct device *dev)
return 0;
}
-static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
+static int imx6sx_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
{
- unsigned int offset;
- int ret = 0;
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
+ enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
- switch (imx_pcie->drvdata->variant) {
- case IMX6SX:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
- IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
- break;
- case IMX6QP:
- case IMX6Q:
+ return 0;
+}
+
+static int imx6q_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
+{
+ if (enable) {
/* power up core phy and enable ref clock */
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0);
/*
* the async reset input need ref clock to sync internally,
* when the ref clock comes after reset, internal synced
@@ -606,54 +605,34 @@ static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
*/
usleep_range(10, 100);
regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
- break;
- case IMX7D:
- case IMX95:
- case IMX95_EP:
- break;
- case IMX8MM:
- case IMX8MM_EP:
- case IMX8MQ:
- case IMX8MQ_EP:
- case IMX8MP:
- case IMX8MP_EP:
- offset = imx_pcie_grp_offset(imx_pcie);
- /*
- * Set the over ride low and enabled
- * make sure that REF_CLK is turned on.
- */
- regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
- IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
- 0);
- regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
- IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
- IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
- break;
+ IMX6Q_GPR1_PCIE_REF_CLK_EN, IMX6Q_GPR1_PCIE_REF_CLK_EN);
+ } else {
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD);
}
- return ret;
+ return 0;
}
-static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie)
+static int imx8mm_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
{
- switch (imx_pcie->drvdata->variant) {
- case IMX6QP:
- case IMX6Q:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_TEST_PD,
- IMX6Q_GPR1_PCIE_TEST_PD);
- break;
- case IMX7D:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
- IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
- IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
- break;
- default:
- break;
- }
+ int offset = imx_pcie_grp_offset(imx_pcie);
+
+ /* Set the over ride low and enabled make sure that REF_CLK is turned on.*/
+ regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
+ enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
+ enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0);
+ return 0;
+}
+
+static int imx7d_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
+{
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
+ enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
+ return 0;
}
static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
@@ -666,10 +645,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
if (ret)
return ret;
- ret = imx_pcie_enable_ref_clk(imx_pcie);
- if (ret) {
- dev_err(dev, "unable to enable pcie ref clock\n");
- goto err_ref_clk;
+ if (imx_pcie->drvdata->set_ref_clk) {
+ ret = imx_pcie->drvdata->set_ref_clk(imx_pcie, true);
+ if (ret) {
+ dev_err(dev, "Failed to enable PCIe REFCLK\n");
+ goto err_ref_clk;
+ }
}
/* allow the clocks to stabilize */
@@ -684,7 +665,8 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
{
- imx_pcie_disable_ref_clk(imx_pcie);
+ if (imx_pcie->drvdata->set_ref_clk)
+ imx_pcie->drvdata->set_ref_clk(imx_pcie, false);
clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
}
@@ -1459,6 +1441,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx_pcie_init_phy,
+ .set_ref_clk = imx6q_pcie_set_ref_clk,
},
[IMX6SX] = {
.variant = IMX6SX,
@@ -1473,6 +1456,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx6sx_pcie_init_phy,
+ .set_ref_clk = imx6sx_pcie_set_ref_clk,
},
[IMX6QP] = {
.variant = IMX6QP,
@@ -1488,6 +1472,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx_pcie_init_phy,
+ .set_ref_clk = imx6q_pcie_set_ref_clk,
},
[IMX7D] = {
.variant = IMX7D,
@@ -1500,6 +1485,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx7d_pcie_init_phy,
+ .set_ref_clk = imx7d_pcie_set_ref_clk,
},
[IMX8MQ] = {
.variant = IMX8MQ,
@@ -1513,6 +1499,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[1] = IOMUXC_GPR12,
.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
.init_phy = imx8mq_pcie_init_phy,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX8MM] = {
.variant = IMX8MM,
@@ -1524,6 +1511,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX8MP] = {
.variant = IMX8MP,
@@ -1535,6 +1523,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX95] = {
.variant = IMX95,
@@ -1561,6 +1550,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
.epc_features = &imx8m_pcie_epc_features,
.init_phy = imx8mq_pcie_init_phy,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX8MM_EP] = {
.variant = IMX8MM_EP,
@@ -1573,6 +1563,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.epc_features = &imx8m_pcie_epc_features,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX8MP_EP] = {
.variant = IMX8MP_EP,
@@ -1585,6 +1576,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.epc_features = &imx8m_pcie_epc_features,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX95_EP] = {
.variant = IMX95_EP,
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* [PATCH v5 03/12] PCI: imx6: Rename imx6_* with imx_*
@ 2024-05-28 19:39 7% ` Frank Li
2024-05-28 19:39 5% ` [PATCH v5 04/12] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li
` (2 subsequent siblings)
3 siblings, 0 replies; 200+ results
From: Frank Li @ 2024-05-28 19:39 UTC (permalink / raw)
To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley
Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree,
Frank Li
Since this driver has evolved to support other i.MX SoCs such as i.MX7/8/9,
let's rename the 'imx6' prefix to 'imx' to avoid confusion. But the driver
name is left unchanged to avoid breaking userspace scripts
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 748 +++++++++++++++++-----------------
1 file changed, 374 insertions(+), 374 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 282261b2e28e5..72e973312d203 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -54,9 +54,9 @@
#define IMX95_PE0_GEN_CTRL_3 0x1058
#define IMX95_PCIE_LTSSM_EN BIT(0)
-#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
+#define to_imx_pcie(x) dev_get_drvdata((x)->dev)
-enum imx6_pcie_variants {
+enum imx_pcie_variants {
IMX6Q,
IMX6SX,
IMX6QP,
@@ -71,25 +71,25 @@ enum imx6_pcie_variants {
IMX95_EP,
};
-#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
-#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
-#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
-#define IMX6_PCIE_FLAG_HAS_PHYDRV BIT(3)
-#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4)
-#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5)
-#define IMX6_PCIE_FLAG_HAS_SERDES BIT(6)
-#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7)
+#define IMX_PCIE_FLAG_IMX_PHY BIT(0)
+#define IMX_PCIE_FLAG_IMX_SPEED_CHANGE BIT(1)
+#define IMX_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
+#define IMX_PCIE_FLAG_HAS_PHYDRV BIT(3)
+#define IMX_PCIE_FLAG_HAS_APP_RESET BIT(4)
+#define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5)
+#define IMX_PCIE_FLAG_HAS_SERDES BIT(6)
+#define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7)
-#define imx6_check_flag(pci, val) (pci->drvdata->flags & val)
+#define imx_check_flag(pci, val) (pci->drvdata->flags & val)
-#define IMX6_PCIE_MAX_CLKS 6
+#define IMX_PCIE_MAX_CLKS 6
-#define IMX6_PCIE_MAX_INSTANCES 2
+#define IMX_PCIE_MAX_INSTANCES 2
-struct imx6_pcie;
+struct imx_pcie;
-struct imx6_pcie_drvdata {
- enum imx6_pcie_variants variant;
+struct imx_pcie_drvdata {
+ enum imx_pcie_variants variant;
enum dw_pcie_device_mode mode;
u32 flags;
int dbi_length;
@@ -98,17 +98,17 @@ struct imx6_pcie_drvdata {
const u32 clks_cnt;
const u32 ltssm_off;
const u32 ltssm_mask;
- const u32 mode_off[IMX6_PCIE_MAX_INSTANCES];
- const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES];
+ const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
+ const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
const struct pci_epc_features *epc_features;
- int (*init_phy)(struct imx6_pcie *pcie);
+ int (*init_phy)(struct imx_pcie *pcie);
};
-struct imx6_pcie {
+struct imx_pcie {
struct dw_pcie *pci;
struct gpio_desc *reset_gpiod;
bool link_is_up;
- struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS];
+ struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS];
struct regmap *iomuxc_gpr;
u16 msi_ctrl;
u32 controller_id;
@@ -129,7 +129,7 @@ struct imx6_pcie {
/* power domain for pcie phy */
struct device *pd_pcie_phy;
struct phy *phy;
- const struct imx6_pcie_drvdata *drvdata;
+ const struct imx_pcie_drvdata *drvdata;
};
/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
@@ -184,28 +184,28 @@ struct imx6_pcie {
#define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5)
#define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3)
-static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
+static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
{
- WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
- imx6_pcie->drvdata->variant != IMX8MQ_EP &&
- imx6_pcie->drvdata->variant != IMX8MM &&
- imx6_pcie->drvdata->variant != IMX8MM_EP &&
- imx6_pcie->drvdata->variant != IMX8MP &&
- imx6_pcie->drvdata->variant != IMX8MP_EP);
- return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
+ WARN_ON(imx_pcie->drvdata->variant != IMX8MQ &&
+ imx_pcie->drvdata->variant != IMX8MQ_EP &&
+ imx_pcie->drvdata->variant != IMX8MM &&
+ imx_pcie->drvdata->variant != IMX8MM_EP &&
+ imx_pcie->drvdata->variant != IMX8MP &&
+ imx_pcie->drvdata->variant != IMX8MP_EP);
+ return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
}
-static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
{
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX95_PCIE_SS_RW_REG_0,
IMX95_PCIE_PHY_CR_PARA_SEL,
IMX95_PCIE_PHY_CR_PARA_SEL);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX95_PCIE_PHY_GEN_CTRL,
IMX95_PCIE_REF_USE_PAD, 0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX95_PCIE_SS_RW_REG_0,
IMX95_PCIE_REF_CLKEN,
IMX95_PCIE_REF_CLKEN);
@@ -213,9 +213,9 @@ static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie)
return 0;
}
-static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
{
- const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
+ const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
unsigned int mask, val, mode, id;
if (drvdata->mode == DW_PCIE_EP_TYPE)
@@ -223,7 +223,7 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
else
mode = PCI_EXP_TYPE_ROOT_PORT;
- id = imx6_pcie->controller_id;
+ id = imx_pcie->controller_id;
/* If mode_mask[id] is zero, means each controller have its individual gpr */
if (!drvdata->mode_mask[id])
@@ -232,12 +232,12 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
mask = drvdata->mode_mask[id];
val = mode << (ffs(mask) - 1);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
}
-static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
+static int pcie_phy_poll_ack(struct imx_pcie *imx_pcie, bool exp_val)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
bool val;
u32 max_iterations = 10;
u32 wait_counter = 0;
@@ -256,9 +256,9 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
return -ETIMEDOUT;
}
-static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
+static int pcie_phy_wait_ack(struct imx_pcie *imx_pcie, int addr)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
u32 val;
int ret;
@@ -268,24 +268,24 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
val |= PCIE_PHY_CTRL_CAP_ADR;
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
- ret = pcie_phy_poll_ack(imx6_pcie, true);
+ ret = pcie_phy_poll_ack(imx_pcie, true);
if (ret)
return ret;
val = PCIE_PHY_CTRL_DATA(addr);
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
- return pcie_phy_poll_ack(imx6_pcie, false);
+ return pcie_phy_poll_ack(imx_pcie, false);
}
/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
-static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
+static int pcie_phy_read(struct imx_pcie *imx_pcie, int addr, u16 *data)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
u32 phy_ctl;
int ret;
- ret = pcie_phy_wait_ack(imx6_pcie, addr);
+ ret = pcie_phy_wait_ack(imx_pcie, addr);
if (ret)
return ret;
@@ -293,7 +293,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
phy_ctl = PCIE_PHY_CTRL_RD;
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
- ret = pcie_phy_poll_ack(imx6_pcie, true);
+ ret = pcie_phy_poll_ack(imx_pcie, true);
if (ret)
return ret;
@@ -302,18 +302,18 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
/* deassert Read signal */
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
- return pcie_phy_poll_ack(imx6_pcie, false);
+ return pcie_phy_poll_ack(imx_pcie, false);
}
-static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
+static int pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
u32 var;
int ret;
/* write addr */
/* cap addr */
- ret = pcie_phy_wait_ack(imx6_pcie, addr);
+ ret = pcie_phy_wait_ack(imx_pcie, addr);
if (ret)
return ret;
@@ -324,7 +324,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
var |= PCIE_PHY_CTRL_CAP_DAT;
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
- ret = pcie_phy_poll_ack(imx6_pcie, true);
+ ret = pcie_phy_poll_ack(imx_pcie, true);
if (ret)
return ret;
@@ -333,7 +333,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
/* wait for ack de-assertion */
- ret = pcie_phy_poll_ack(imx6_pcie, false);
+ ret = pcie_phy_poll_ack(imx_pcie, false);
if (ret)
return ret;
@@ -342,7 +342,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
/* wait for ack */
- ret = pcie_phy_poll_ack(imx6_pcie, true);
+ ret = pcie_phy_poll_ack(imx_pcie, true);
if (ret)
return ret;
@@ -351,7 +351,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
/* wait for ack de-assertion */
- ret = pcie_phy_poll_ack(imx6_pcie, false);
+ ret = pcie_phy_poll_ack(imx_pcie, false);
if (ret)
return ret;
@@ -360,74 +360,74 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
return 0;
}
-static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie)
{
/* TODO: Currently this code assumes external oscillator is being used */
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
- imx6_pcie_grp_offset(imx6_pcie),
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
+ imx_pcie_grp_offset(imx_pcie),
IMX8MQ_GPR_PCIE_REF_USE_PAD,
IMX8MQ_GPR_PCIE_REF_USE_PAD);
/*
* Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is
* supplied by 3.3V, the VREG_BYPASS should be cleared to zero.
*/
- if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000)
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
- imx6_pcie_grp_offset(imx6_pcie),
+ if (imx_pcie->vph && regulator_get_voltage(imx_pcie->vph) > 3000000)
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
+ imx_pcie_grp_offset(imx_pcie),
IMX8MQ_GPR_PCIE_VREG_BYPASS,
0);
return 0;
}
-static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie)
{
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
return 0;
}
-static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_init_phy(struct imx_pcie *imx_pcie)
{
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
/* configure constant input signal to the pcie ctrl and phy */
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_DEEMPH_GEN1,
- imx6_pcie->tx_deemph_gen1 << 0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ imx_pcie->tx_deemph_gen1 << 0);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
- imx6_pcie->tx_deemph_gen2_3p5db << 6);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ imx_pcie->tx_deemph_gen2_3p5db << 6);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
- imx6_pcie->tx_deemph_gen2_6db << 12);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ imx_pcie->tx_deemph_gen2_6db << 12);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_SWING_FULL,
- imx6_pcie->tx_swing_full << 18);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ imx_pcie->tx_swing_full << 18);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_SWING_LOW,
- imx6_pcie->tx_swing_low << 25);
+ imx_pcie->tx_swing_low << 25);
return 0;
}
-static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+static int imx6sx_pcie_init_phy(struct imx_pcie *imx_pcie)
{
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2);
- return imx6_pcie_init_phy(imx6_pcie);
+ return imx_pcie_init_phy(imx_pcie);
}
-static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
+static void imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
{
u32 val;
- struct device *dev = imx6_pcie->pci->dev;
+ struct device *dev = imx_pcie->pci->dev;
- if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
+ if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
IOMUXC_GPR22, val,
val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
PHY_PLL_LOCK_WAIT_USLEEP_MAX,
@@ -435,19 +435,19 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
dev_err(dev, "PCIe PLL lock timeout\n");
}
-static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
+static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie)
{
unsigned long phy_rate = 0;
int mult, div;
u16 val;
int i;
- if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
+ if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY))
return 0;
- for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++)
- if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0)
- phy_rate = clk_get_rate(imx6_pcie->clks[i].clk);
+ for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++)
+ if (strncmp(imx_pcie->clks[i].id, "pcie_phy", 8) == 0)
+ phy_rate = clk_get_rate(imx_pcie->clks[i].clk);
switch (phy_rate) {
case 125000000:
@@ -465,46 +465,46 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
div = 1;
break;
default:
- dev_err(imx6_pcie->pci->dev,
+ dev_err(imx_pcie->pci->dev,
"Unsupported PHY reference clock rate %lu\n", phy_rate);
return -EINVAL;
}
- pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
+ pcie_phy_read(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
- pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
+ pcie_phy_write(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
- pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
+ pcie_phy_read(imx_pcie, PCIE_PHY_ATEOVRD, &val);
val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
val |= PCIE_PHY_ATEOVRD_EN;
- pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
+ pcie_phy_write(imx_pcie, PCIE_PHY_ATEOVRD, val);
return 0;
}
-static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_reset_phy(struct imx_pcie *imx_pcie)
{
u16 tmp;
- if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
+ if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY))
return;
- pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
+ pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp);
tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
PHY_RX_OVRD_IN_LO_RX_PLL_EN);
- pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
+ pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp);
usleep_range(2000, 3000);
- pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
+ pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp);
tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
PHY_RX_OVRD_IN_LO_RX_PLL_EN);
- pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
+ pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp);
}
#ifdef CONFIG_ARM
@@ -543,22 +543,22 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
}
#endif
-static int imx6_pcie_attach_pd(struct device *dev)
+static int imx_pcie_attach_pd(struct device *dev)
{
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
struct device_link *link;
/* Do nothing when in a single power domain */
if (dev->pm_domain)
return 0;
- imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
- if (IS_ERR(imx6_pcie->pd_pcie))
- return PTR_ERR(imx6_pcie->pd_pcie);
+ imx_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
+ if (IS_ERR(imx_pcie->pd_pcie))
+ return PTR_ERR(imx_pcie->pd_pcie);
/* Do nothing when power domain missing */
- if (!imx6_pcie->pd_pcie)
+ if (!imx_pcie->pd_pcie)
return 0;
- link = device_link_add(dev, imx6_pcie->pd_pcie,
+ link = device_link_add(dev, imx_pcie->pd_pcie,
DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME |
DL_FLAG_RPM_ACTIVE);
@@ -567,11 +567,11 @@ static int imx6_pcie_attach_pd(struct device *dev)
return -EINVAL;
}
- imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
- if (IS_ERR(imx6_pcie->pd_pcie_phy))
- return PTR_ERR(imx6_pcie->pd_pcie_phy);
+ imx_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
+ if (IS_ERR(imx_pcie->pd_pcie_phy))
+ return PTR_ERR(imx_pcie->pd_pcie_phy);
- link = device_link_add(dev, imx6_pcie->pd_pcie_phy,
+ link = device_link_add(dev, imx_pcie->pd_pcie_phy,
DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME |
DL_FLAG_RPM_ACTIVE);
@@ -583,20 +583,20 @@ static int imx6_pcie_attach_pd(struct device *dev)
return 0;
}
-static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
{
unsigned int offset;
int ret = 0;
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX6SX:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
break;
case IMX6QP:
case IMX6Q:
/* power up core phy and enable ref clock */
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
/*
* the async reset input need ref clock to sync internally,
@@ -605,7 +605,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
* add one ~10us delay here.
*/
usleep_range(10, 100);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
break;
case IMX7D:
@@ -618,15 +618,15 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
case IMX8MQ_EP:
case IMX8MP:
case IMX8MP_EP:
- offset = imx6_pcie_grp_offset(imx6_pcie);
+ offset = imx_pcie_grp_offset(imx_pcie);
/*
* Set the over ride low and enabled
* make sure that REF_CLK is turned on.
*/
- regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
break;
@@ -635,19 +635,19 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
return ret;
}
-static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie)
{
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX6QP:
case IMX6Q:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD,
IMX6Q_GPR1_PCIE_TEST_PD);
break;
case IMX7D:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
break;
@@ -656,17 +656,17 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
}
}
-static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
struct device *dev = pci->dev;
int ret;
- ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
+ ret = clk_bulk_prepare_enable(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
if (ret)
return ret;
- ret = imx6_pcie_enable_ref_clk(imx6_pcie);
+ ret = imx_pcie_enable_ref_clk(imx_pcie);
if (ret) {
dev_err(dev, "unable to enable pcie ref clock\n");
goto err_ref_clk;
@@ -677,41 +677,41 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
return 0;
err_ref_clk:
- clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
+ clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
return ret;
}
-static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
{
- imx6_pcie_disable_ref_clk(imx6_pcie);
- clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
+ imx_pcie_disable_ref_clk(imx_pcie);
+ clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
}
-static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
{
- reset_control_assert(imx6_pcie->pciephy_reset);
- reset_control_assert(imx6_pcie->apps_reset);
+ reset_control_assert(imx_pcie->pciephy_reset);
+ reset_control_assert(imx_pcie->apps_reset);
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX6SX:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
/* Force PCIe PHY reset */
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
IMX6SX_GPR5_PCIE_BTNRST_RESET,
IMX6SX_GPR5_PCIE_BTNRST_RESET);
break;
case IMX6QP:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_SW_RST,
IMX6Q_GPR1_PCIE_SW_RST);
break;
case IMX6Q:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
break;
default:
@@ -719,45 +719,45 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
}
/* Some boards don't have PCIe reset GPIO. */
- gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 1);
+ gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);
}
-static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
struct device *dev = pci->dev;
- reset_control_deassert(imx6_pcie->pciephy_reset);
+ reset_control_deassert(imx_pcie->pciephy_reset);
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX7D:
/* Workaround for ERR010728, failure of PCI-e PLL VCO to
* oscillate, especially when cold. This turns off "Duty-cycle
* Corrector" and other mysterious undocumented things.
*/
- if (likely(imx6_pcie->phy_base)) {
+ if (likely(imx_pcie->phy_base)) {
/* De-assert DCC_FB_EN */
writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
- imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
+ imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
/* Assert RX_EQS and RX_EQS_SEL */
writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
| PCIE_PHY_CMN_REG24_RX_EQ,
- imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
+ imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
/* Assert ATT_MODE */
writel(PCIE_PHY_CMN_REG26_ATT_MODE,
- imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
+ imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
} else {
dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
}
- imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
+ imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
break;
case IMX6SX:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
break;
case IMX6QP:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_SW_RST, 0);
usleep_range(200, 500);
@@ -767,9 +767,9 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
}
/* Some boards don't have PCIe reset GPIO. */
- if (imx6_pcie->reset_gpiod) {
+ if (imx_pcie->reset_gpiod) {
msleep(100);
- gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 0);
+ gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);
/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
msleep(100);
}
@@ -777,9 +777,9 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
return 0;
}
-static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_wait_for_speed_change(struct imx_pcie *imx_pcie)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
struct device *dev = pci->dev;
u32 tmp;
unsigned int retries;
@@ -796,33 +796,33 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
return -ETIMEDOUT;
}
-static void imx6_pcie_ltssm_enable(struct device *dev)
+static void imx_pcie_ltssm_enable(struct device *dev)
{
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
if (drvdata->ltssm_mask)
- regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
drvdata->ltssm_mask);
- reset_control_deassert(imx6_pcie->apps_reset);
+ reset_control_deassert(imx_pcie->apps_reset);
}
-static void imx6_pcie_ltssm_disable(struct device *dev)
+static void imx_pcie_ltssm_disable(struct device *dev)
{
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
if (drvdata->ltssm_mask)
- regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
drvdata->ltssm_mask, 0);
- reset_control_assert(imx6_pcie->apps_reset);
+ reset_control_assert(imx_pcie->apps_reset);
}
-static int imx6_pcie_start_link(struct dw_pcie *pci)
+static int imx_pcie_start_link(struct dw_pcie *pci)
{
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pci);
struct device *dev = pci->dev;
u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
u32 tmp;
@@ -841,7 +841,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
dw_pcie_dbi_ro_wr_dis(pci);
/* Start LTSSM. */
- imx6_pcie_ltssm_enable(dev);
+ imx_pcie_ltssm_enable(dev);
ret = dw_pcie_wait_for_link(pci);
if (ret)
@@ -864,8 +864,8 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
dw_pcie_dbi_ro_wr_dis(pci);
- if (imx6_pcie->drvdata->flags &
- IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
+ if (imx_pcie->drvdata->flags &
+ IMX_PCIE_FLAG_IMX_SPEED_CHANGE) {
/*
* On i.MX7, DIRECT_SPEED_CHANGE behaves differently
* from i.MX6 family when no link speed transition
@@ -875,7 +875,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
* failure.
*/
- ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
+ ret = imx_pcie_wait_for_speed_change(imx_pcie);
if (ret) {
dev_err(dev, "Failed to bring link up!\n");
goto err_reset_phy;
@@ -890,37 +890,37 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
dev_info(dev, "Link: Only Gen1 is enabled\n");
}
- imx6_pcie->link_is_up = true;
+ imx_pcie->link_is_up = true;
tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
return 0;
err_reset_phy:
- imx6_pcie->link_is_up = false;
+ imx_pcie->link_is_up = false;
dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
- imx6_pcie_reset_phy(imx6_pcie);
+ imx_pcie_reset_phy(imx_pcie);
return 0;
}
-static void imx6_pcie_stop_link(struct dw_pcie *pci)
+static void imx_pcie_stop_link(struct dw_pcie *pci)
{
struct device *dev = pci->dev;
/* Turn off PCIe LTSSM */
- imx6_pcie_ltssm_disable(dev);
+ imx_pcie_ltssm_disable(dev);
}
-static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
+static int imx_pcie_host_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct device *dev = pci->dev;
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pci);
int ret;
- if (imx6_pcie->vpcie) {
- ret = regulator_enable(imx6_pcie->vpcie);
+ if (imx_pcie->vpcie) {
+ ret = regulator_enable(imx_pcie->vpcie);
if (ret) {
dev_err(dev, "failed to enable vpcie regulator: %d\n",
ret);
@@ -928,83 +928,83 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
}
}
- imx6_pcie_assert_core_reset(imx6_pcie);
+ imx_pcie_assert_core_reset(imx_pcie);
- if (imx6_pcie->drvdata->init_phy)
- imx6_pcie->drvdata->init_phy(imx6_pcie);
+ if (imx_pcie->drvdata->init_phy)
+ imx_pcie->drvdata->init_phy(imx_pcie);
- imx6_pcie_configure_type(imx6_pcie);
+ imx_pcie_configure_type(imx_pcie);
- ret = imx6_pcie_clk_enable(imx6_pcie);
+ ret = imx_pcie_clk_enable(imx_pcie);
if (ret) {
dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
goto err_reg_disable;
}
- if (imx6_pcie->phy) {
- ret = phy_init(imx6_pcie->phy);
+ if (imx_pcie->phy) {
+ ret = phy_init(imx_pcie->phy);
if (ret) {
dev_err(dev, "pcie PHY power up failed\n");
goto err_clk_disable;
}
}
- if (imx6_pcie->phy) {
- ret = phy_power_on(imx6_pcie->phy);
+ if (imx_pcie->phy) {
+ ret = phy_power_on(imx_pcie->phy);
if (ret) {
dev_err(dev, "waiting for PHY ready timeout!\n");
goto err_phy_off;
}
}
- ret = imx6_pcie_deassert_core_reset(imx6_pcie);
+ ret = imx_pcie_deassert_core_reset(imx_pcie);
if (ret < 0) {
dev_err(dev, "pcie deassert core reset failed: %d\n", ret);
goto err_phy_off;
}
- imx6_setup_phy_mpll(imx6_pcie);
+ imx_setup_phy_mpll(imx_pcie);
return 0;
err_phy_off:
- if (imx6_pcie->phy)
- phy_exit(imx6_pcie->phy);
+ if (imx_pcie->phy)
+ phy_exit(imx_pcie->phy);
err_clk_disable:
- imx6_pcie_clk_disable(imx6_pcie);
+ imx_pcie_clk_disable(imx_pcie);
err_reg_disable:
- if (imx6_pcie->vpcie)
- regulator_disable(imx6_pcie->vpcie);
+ if (imx_pcie->vpcie)
+ regulator_disable(imx_pcie->vpcie);
return ret;
}
-static void imx6_pcie_host_exit(struct dw_pcie_rp *pp)
+static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pci);
- if (imx6_pcie->phy) {
- if (phy_power_off(imx6_pcie->phy))
+ if (imx_pcie->phy) {
+ if (phy_power_off(imx_pcie->phy))
dev_err(pci->dev, "unable to power off PHY\n");
- phy_exit(imx6_pcie->phy);
+ phy_exit(imx_pcie->phy);
}
- imx6_pcie_clk_disable(imx6_pcie);
+ imx_pcie_clk_disable(imx_pcie);
- if (imx6_pcie->vpcie)
- regulator_disable(imx6_pcie->vpcie);
+ if (imx_pcie->vpcie)
+ regulator_disable(imx_pcie->vpcie);
}
-static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
- .init = imx6_pcie_host_init,
- .deinit = imx6_pcie_host_exit,
+static const struct dw_pcie_host_ops imx_pcie_host_ops = {
+ .init = imx_pcie_host_init,
+ .deinit = imx_pcie_host_exit,
};
static const struct dw_pcie_ops dw_pcie_ops = {
- .start_link = imx6_pcie_start_link,
- .stop_link = imx6_pcie_stop_link,
+ .start_link = imx_pcie_start_link,
+ .stop_link = imx_pcie_stop_link,
};
-static void imx6_pcie_ep_init(struct dw_pcie_ep *ep)
+static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
{
enum pci_barno bar;
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -1013,7 +1013,7 @@ static void imx6_pcie_ep_init(struct dw_pcie_ep *ep)
dw_pcie_ep_reset_bar(pci, bar);
}
-static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
+static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
unsigned int type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -1060,35 +1060,35 @@ static const struct pci_epc_features imx95_pcie_epc_features = {
};
static const struct pci_epc_features*
-imx6_pcie_ep_get_features(struct dw_pcie_ep *ep)
+imx_pcie_ep_get_features(struct dw_pcie_ep *ep)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pci);
- return imx6_pcie->drvdata->epc_features;
+ return imx_pcie->drvdata->epc_features;
}
static const struct dw_pcie_ep_ops pcie_ep_ops = {
- .init = imx6_pcie_ep_init,
- .raise_irq = imx6_pcie_ep_raise_irq,
- .get_features = imx6_pcie_ep_get_features,
+ .init = imx_pcie_ep_init,
+ .raise_irq = imx_pcie_ep_raise_irq,
+ .get_features = imx_pcie_ep_get_features,
};
-static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
+static int imx_add_pcie_ep(struct imx_pcie *imx_pcie,
struct platform_device *pdev)
{
int ret;
unsigned int pcie_dbi2_offset;
struct dw_pcie_ep *ep;
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
struct dw_pcie_rp *pp = &pci->pp;
struct device *dev = pci->dev;
- imx6_pcie_host_init(pp);
+ imx_pcie_host_init(pp);
ep = &pci->ep;
ep->ops = &pcie_ep_ops;
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX8MQ_EP:
case IMX8MM_EP:
case IMX8MP_EP:
@@ -1110,10 +1110,10 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
if (device_property_match_string(dev, "reg-names", "dbi2") >= 0)
pci->dbi_base2 = NULL;
- if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT))
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_SUPPORT_64BIT))
dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
- ep->page_size = imx6_pcie->drvdata->epc_features->align;
+ ep->page_size = imx_pcie->drvdata->epc_features->align;
ret = dw_pcie_ep_init(ep);
if (ret) {
@@ -1131,30 +1131,30 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
dw_pcie_ep_init_notify(ep);
/* Start LTSSM. */
- imx6_pcie_ltssm_enable(dev);
+ imx_pcie_ltssm_enable(dev);
return 0;
}
-static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_pm_turnoff(struct imx_pcie *imx_pcie)
{
- struct device *dev = imx6_pcie->pci->dev;
+ struct device *dev = imx_pcie->pci->dev;
/* Some variants have a turnoff reset in DT */
- if (imx6_pcie->turnoff_reset) {
- reset_control_assert(imx6_pcie->turnoff_reset);
- reset_control_deassert(imx6_pcie->turnoff_reset);
+ if (imx_pcie->turnoff_reset) {
+ reset_control_assert(imx_pcie->turnoff_reset);
+ reset_control_deassert(imx_pcie->turnoff_reset);
goto pm_turnoff_sleep;
}
/* Others poke directly at IOMUXC registers */
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX6SX:
case IMX6QP:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_PM_TURN_OFF,
IMX6SX_GPR12_PCIE_PM_TURN_OFF);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
break;
default:
@@ -1173,73 +1173,73 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
usleep_range(1000, 10000);
}
-static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save)
+static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save)
{
u8 offset;
u16 val;
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
if (pci_msi_enabled()) {
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
if (save) {
val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
- imx6_pcie->msi_ctrl = val;
+ imx_pcie->msi_ctrl = val;
} else {
dw_pcie_dbi_ro_wr_en(pci);
- val = imx6_pcie->msi_ctrl;
+ val = imx_pcie->msi_ctrl;
dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
dw_pcie_dbi_ro_wr_dis(pci);
}
}
}
-static int imx6_pcie_suspend_noirq(struct device *dev)
+static int imx_pcie_suspend_noirq(struct device *dev)
{
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ struct dw_pcie_rp *pp = &imx_pcie->pci->pp;
- if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
+ if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND))
return 0;
- imx6_pcie_msi_save_restore(imx6_pcie, true);
- imx6_pcie_pm_turnoff(imx6_pcie);
- imx6_pcie_stop_link(imx6_pcie->pci);
- imx6_pcie_host_exit(pp);
+ imx_pcie_msi_save_restore(imx_pcie, true);
+ imx_pcie_pm_turnoff(imx_pcie);
+ imx_pcie_stop_link(imx_pcie->pci);
+ imx_pcie_host_exit(pp);
return 0;
}
-static int imx6_pcie_resume_noirq(struct device *dev)
+static int imx_pcie_resume_noirq(struct device *dev)
{
int ret;
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ struct dw_pcie_rp *pp = &imx_pcie->pci->pp;
- if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
+ if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND))
return 0;
- ret = imx6_pcie_host_init(pp);
+ ret = imx_pcie_host_init(pp);
if (ret)
return ret;
- imx6_pcie_msi_save_restore(imx6_pcie, false);
+ imx_pcie_msi_save_restore(imx_pcie, false);
dw_pcie_setup_rc(pp);
- if (imx6_pcie->link_is_up)
- imx6_pcie_start_link(imx6_pcie->pci);
+ if (imx_pcie->link_is_up)
+ imx_pcie_start_link(imx_pcie->pci);
return 0;
}
-static const struct dev_pm_ops imx6_pcie_pm_ops = {
- NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
- imx6_pcie_resume_noirq)
+static const struct dev_pm_ops imx_pcie_pm_ops = {
+ NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_pcie_suspend_noirq,
+ imx_pcie_resume_noirq)
};
-static int imx6_pcie_probe(struct platform_device *pdev)
+static int imx_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct dw_pcie *pci;
- struct imx6_pcie *imx6_pcie;
+ struct imx_pcie *imx_pcie;
struct device_node *np;
struct resource *dbi_base;
struct device_node *node = dev->of_node;
@@ -1247,8 +1247,8 @@ static int imx6_pcie_probe(struct platform_device *pdev)
u16 val;
int i;
- imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
- if (!imx6_pcie)
+ imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
+ if (!imx_pcie)
return -ENOMEM;
pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
@@ -1257,10 +1257,10 @@ static int imx6_pcie_probe(struct platform_device *pdev)
pci->dev = dev;
pci->ops = &dw_pcie_ops;
- pci->pp.ops = &imx6_pcie_host_ops;
+ pci->pp.ops = &imx_pcie_host_ops;
- imx6_pcie->pci = pci;
- imx6_pcie->drvdata = of_device_get_match_data(dev);
+ imx_pcie->pci = pci;
+ imx_pcie->drvdata = of_device_get_match_data(dev);
/* Find the PHY if one is defined, only imx7d uses it */
np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
@@ -1272,9 +1272,9 @@ static int imx6_pcie_probe(struct platform_device *pdev)
dev_err(dev, "Unable to map PCIe PHY\n");
return ret;
}
- imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
- if (IS_ERR(imx6_pcie->phy_base))
- return PTR_ERR(imx6_pcie->phy_base);
+ imx_pcie->phy_base = devm_ioremap_resource(dev, &res);
+ if (IS_ERR(imx_pcie->phy_base))
+ return PTR_ERR(imx_pcie->phy_base);
}
pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base);
@@ -1282,72 +1282,72 @@ static int imx6_pcie_probe(struct platform_device *pdev)
return PTR_ERR(pci->dbi_base);
/* Fetch GPIOs */
- imx6_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
- if (IS_ERR(imx6_pcie->reset_gpiod))
- return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod),
+ imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(imx_pcie->reset_gpiod))
+ return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod),
"unable to get reset gpio\n");
- gpiod_set_consumer_name(imx6_pcie->reset_gpiod, "PCIe reset");
+ gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset");
- if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS)
+ if (imx_pcie->drvdata->clks_cnt >= IMX_PCIE_MAX_CLKS)
return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
- for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++)
- imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i];
+ for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++)
+ imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i];
/* Fetch clocks */
- ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
+ ret = devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
if (ret)
return ret;
- if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHYDRV)) {
- imx6_pcie->phy = devm_phy_get(dev, "pcie-phy");
- if (IS_ERR(imx6_pcie->phy))
- return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy),
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
+ imx_pcie->phy = devm_phy_get(dev, "pcie-phy");
+ if (IS_ERR(imx_pcie->phy))
+ return dev_err_probe(dev, PTR_ERR(imx_pcie->phy),
"failed to get pcie phy\n");
}
- if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) {
- imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps");
- if (IS_ERR(imx6_pcie->apps_reset))
- return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset),
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_APP_RESET)) {
+ imx_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps");
+ if (IS_ERR(imx_pcie->apps_reset))
+ return dev_err_probe(dev, PTR_ERR(imx_pcie->apps_reset),
"failed to get pcie apps reset control\n");
}
- if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) {
- imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy");
- if (IS_ERR(imx6_pcie->pciephy_reset))
- return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset),
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHY_RESET)) {
+ imx_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy");
+ if (IS_ERR(imx_pcie->pciephy_reset))
+ return dev_err_probe(dev, PTR_ERR(imx_pcie->pciephy_reset),
"Failed to get PCIEPHY reset control\n");
}
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX8MQ:
case IMX8MQ_EP:
case IMX7D:
if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
- imx6_pcie->controller_id = 1;
+ imx_pcie->controller_id = 1;
break;
default:
break;
}
/* Grab turnoff reset */
- imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
- if (IS_ERR(imx6_pcie->turnoff_reset)) {
+ imx_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
+ if (IS_ERR(imx_pcie->turnoff_reset)) {
dev_err(dev, "Failed to get TURNOFF reset control\n");
- return PTR_ERR(imx6_pcie->turnoff_reset);
+ return PTR_ERR(imx_pcie->turnoff_reset);
}
- if (imx6_pcie->drvdata->gpr) {
+ if (imx_pcie->drvdata->gpr) {
/* Grab GPR config register range */
- imx6_pcie->iomuxc_gpr =
- syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
- if (IS_ERR(imx6_pcie->iomuxc_gpr))
- return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
+ imx_pcie->iomuxc_gpr =
+ syscon_regmap_lookup_by_compatible(imx_pcie->drvdata->gpr);
+ if (IS_ERR(imx_pcie->iomuxc_gpr))
+ return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr),
"unable to find iomuxc registers\n");
}
- if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) {
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_SERDES)) {
void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app");
if (IS_ERR(off))
@@ -1360,59 +1360,59 @@ static int imx6_pcie_probe(struct platform_device *pdev)
.reg_stride = 4,
};
- imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config);
- if (IS_ERR(imx6_pcie->iomuxc_gpr))
- return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
+ imx_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(imx_pcie->iomuxc_gpr))
+ return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr),
"unable to find iomuxc registers\n");
}
/* Grab PCIe PHY Tx Settings */
if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
- &imx6_pcie->tx_deemph_gen1))
- imx6_pcie->tx_deemph_gen1 = 0;
+ &imx_pcie->tx_deemph_gen1))
+ imx_pcie->tx_deemph_gen1 = 0;
if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
- &imx6_pcie->tx_deemph_gen2_3p5db))
- imx6_pcie->tx_deemph_gen2_3p5db = 0;
+ &imx_pcie->tx_deemph_gen2_3p5db))
+ imx_pcie->tx_deemph_gen2_3p5db = 0;
if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
- &imx6_pcie->tx_deemph_gen2_6db))
- imx6_pcie->tx_deemph_gen2_6db = 20;
+ &imx_pcie->tx_deemph_gen2_6db))
+ imx_pcie->tx_deemph_gen2_6db = 20;
if (of_property_read_u32(node, "fsl,tx-swing-full",
- &imx6_pcie->tx_swing_full))
- imx6_pcie->tx_swing_full = 127;
+ &imx_pcie->tx_swing_full))
+ imx_pcie->tx_swing_full = 127;
if (of_property_read_u32(node, "fsl,tx-swing-low",
- &imx6_pcie->tx_swing_low))
- imx6_pcie->tx_swing_low = 127;
+ &imx_pcie->tx_swing_low))
+ imx_pcie->tx_swing_low = 127;
/* Limit link speed */
pci->link_gen = 1;
of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
- imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
- if (IS_ERR(imx6_pcie->vpcie)) {
- if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
- return PTR_ERR(imx6_pcie->vpcie);
- imx6_pcie->vpcie = NULL;
+ imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
+ if (IS_ERR(imx_pcie->vpcie)) {
+ if (PTR_ERR(imx_pcie->vpcie) != -ENODEV)
+ return PTR_ERR(imx_pcie->vpcie);
+ imx_pcie->vpcie = NULL;
}
- imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
- if (IS_ERR(imx6_pcie->vph)) {
- if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
- return PTR_ERR(imx6_pcie->vph);
- imx6_pcie->vph = NULL;
+ imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
+ if (IS_ERR(imx_pcie->vph)) {
+ if (PTR_ERR(imx_pcie->vph) != -ENODEV)
+ return PTR_ERR(imx_pcie->vph);
+ imx_pcie->vph = NULL;
}
- platform_set_drvdata(pdev, imx6_pcie);
+ platform_set_drvdata(pdev, imx_pcie);
- ret = imx6_pcie_attach_pd(dev);
+ ret = imx_pcie_attach_pd(dev);
if (ret)
return ret;
- if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
- ret = imx6_add_pcie_ep(imx6_pcie, pdev);
+ if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
+ ret = imx_add_pcie_ep(imx_pcie, pdev);
if (ret < 0)
return ret;
} else {
@@ -1432,12 +1432,12 @@ static int imx6_pcie_probe(struct platform_device *pdev)
return 0;
}
-static void imx6_pcie_shutdown(struct platform_device *pdev)
+static void imx_pcie_shutdown(struct platform_device *pdev)
{
- struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
+ struct imx_pcie *imx_pcie = platform_get_drvdata(pdev);
/* bring down link, so bootloader gets clean state in case of reboot */
- imx6_pcie_assert_core_reset(imx6_pcie);
+ imx_pcie_assert_core_reset(imx_pcie);
}
static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"};
@@ -1445,11 +1445,11 @@ static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"};
static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
-static const struct imx6_pcie_drvdata drvdata[] = {
+static const struct imx_pcie_drvdata drvdata[] = {
[IMX6Q] = {
.variant = IMX6Q,
- .flags = IMX6_PCIE_FLAG_IMX6_PHY |
- IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
+ .flags = IMX_PCIE_FLAG_IMX_PHY |
+ IMX_PCIE_FLAG_IMX_SPEED_CHANGE,
.dbi_length = 0x200,
.gpr = "fsl,imx6q-iomuxc-gpr",
.clk_names = imx6q_clks,
@@ -1458,13 +1458,13 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
- .init_phy = imx6_pcie_init_phy,
+ .init_phy = imx_pcie_init_phy,
},
[IMX6SX] = {
.variant = IMX6SX,
- .flags = IMX6_PCIE_FLAG_IMX6_PHY |
- IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
- IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
+ .flags = IMX_PCIE_FLAG_IMX_PHY |
+ IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
+ IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
.gpr = "fsl,imx6q-iomuxc-gpr",
.clk_names = imx6sx_clks,
.clks_cnt = ARRAY_SIZE(imx6sx_clks),
@@ -1476,9 +1476,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX6QP] = {
.variant = IMX6QP,
- .flags = IMX6_PCIE_FLAG_IMX6_PHY |
- IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
- IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
+ .flags = IMX_PCIE_FLAG_IMX_PHY |
+ IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
+ IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
.dbi_length = 0x200,
.gpr = "fsl,imx6q-iomuxc-gpr",
.clk_names = imx6q_clks,
@@ -1487,13 +1487,13 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
- .init_phy = imx6_pcie_init_phy,
+ .init_phy = imx_pcie_init_phy,
},
[IMX7D] = {
.variant = IMX7D,
- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
- IMX6_PCIE_FLAG_HAS_APP_RESET |
- IMX6_PCIE_FLAG_HAS_PHY_RESET,
+ .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
+ IMX_PCIE_FLAG_HAS_APP_RESET |
+ IMX_PCIE_FLAG_HAS_PHY_RESET,
.gpr = "fsl,imx7d-iomuxc-gpr",
.clk_names = imx6q_clks,
.clks_cnt = ARRAY_SIZE(imx6q_clks),
@@ -1503,8 +1503,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MQ] = {
.variant = IMX8MQ,
- .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
- IMX6_PCIE_FLAG_HAS_PHY_RESET,
+ .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
+ IMX_PCIE_FLAG_HAS_PHY_RESET,
.gpr = "fsl,imx8mq-iomuxc-gpr",
.clk_names = imx8mq_clks,
.clks_cnt = ARRAY_SIZE(imx8mq_clks),
@@ -1516,9 +1516,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MM] = {
.variant = IMX8MM,
- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
- IMX6_PCIE_FLAG_HAS_PHYDRV |
- IMX6_PCIE_FLAG_HAS_APP_RESET,
+ .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
+ IMX_PCIE_FLAG_HAS_PHYDRV |
+ IMX_PCIE_FLAG_HAS_APP_RESET,
.gpr = "fsl,imx8mm-iomuxc-gpr",
.clk_names = imx8mm_clks,
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
@@ -1527,9 +1527,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MP] = {
.variant = IMX8MP,
- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
- IMX6_PCIE_FLAG_HAS_PHYDRV |
- IMX6_PCIE_FLAG_HAS_APP_RESET,
+ .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
+ IMX_PCIE_FLAG_HAS_PHYDRV |
+ IMX_PCIE_FLAG_HAS_APP_RESET,
.gpr = "fsl,imx8mp-iomuxc-gpr",
.clk_names = imx8mm_clks,
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
@@ -1538,7 +1538,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX95] = {
.variant = IMX95,
- .flags = IMX6_PCIE_FLAG_HAS_SERDES,
+ .flags = IMX_PCIE_FLAG_HAS_SERDES,
.clk_names = imx8mq_clks,
.clks_cnt = ARRAY_SIZE(imx8mq_clks),
.ltssm_off = IMX95_PE0_GEN_CTRL_3,
@@ -1549,8 +1549,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MQ_EP] = {
.variant = IMX8MQ_EP,
- .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
- IMX6_PCIE_FLAG_HAS_PHY_RESET,
+ .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
+ IMX_PCIE_FLAG_HAS_PHY_RESET,
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mq-iomuxc-gpr",
.clk_names = imx8mq_clks,
@@ -1564,8 +1564,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MM_EP] = {
.variant = IMX8MM_EP,
- .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
- IMX6_PCIE_FLAG_HAS_PHYDRV,
+ .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
+ IMX_PCIE_FLAG_HAS_PHYDRV,
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mm-iomuxc-gpr",
.clk_names = imx8mm_clks,
@@ -1576,8 +1576,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MP_EP] = {
.variant = IMX8MP_EP,
- .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
- IMX6_PCIE_FLAG_HAS_PHYDRV,
+ .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
+ IMX_PCIE_FLAG_HAS_PHYDRV,
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mp-iomuxc-gpr",
.clk_names = imx8mm_clks,
@@ -1588,8 +1588,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX95_EP] = {
.variant = IMX95_EP,
- .flags = IMX6_PCIE_FLAG_HAS_SERDES |
- IMX6_PCIE_FLAG_SUPPORT_64BIT,
+ .flags = IMX_PCIE_FLAG_HAS_SERDES |
+ IMX_PCIE_FLAG_SUPPORT_64BIT,
.clk_names = imx8mq_clks,
.clks_cnt = ARRAY_SIZE(imx8mq_clks),
.ltssm_off = IMX95_PE0_GEN_CTRL_3,
@@ -1602,7 +1602,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
};
-static const struct of_device_id imx6_pcie_of_match[] = {
+static const struct of_device_id imx_pcie_of_match[] = {
{ .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
{ .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
@@ -1618,19 +1618,19 @@ static const struct of_device_id imx6_pcie_of_match[] = {
{},
};
-static struct platform_driver imx6_pcie_driver = {
+static struct platform_driver imx_pcie_driver = {
.driver = {
.name = "imx6q-pcie",
- .of_match_table = imx6_pcie_of_match,
+ .of_match_table = imx_pcie_of_match,
.suppress_bind_attrs = true,
- .pm = &imx6_pcie_pm_ops,
+ .pm = &imx_pcie_pm_ops,
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
- .probe = imx6_pcie_probe,
- .shutdown = imx6_pcie_shutdown,
+ .probe = imx_pcie_probe,
+ .shutdown = imx_pcie_shutdown,
};
-static void imx6_pcie_quirk(struct pci_dev *dev)
+static void imx_pcie_quirk(struct pci_dev *dev)
{
struct pci_bus *bus = dev->bus;
struct dw_pcie_rp *pp = bus->sysdata;
@@ -1640,33 +1640,33 @@ static void imx6_pcie_quirk(struct pci_dev *dev)
return;
/* Make sure we only quirk devices associated with this driver */
- if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver)
+ if (bus->dev.parent->parent->driver != &imx_pcie_driver.driver)
return;
if (pci_is_root_bus(bus)) {
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pci);
/*
* Limit config length to avoid the kernel reading beyond
* the register set and causing an abort on i.MX 6Quad
*/
- if (imx6_pcie->drvdata->dbi_length) {
- dev->cfg_size = imx6_pcie->drvdata->dbi_length;
+ if (imx_pcie->drvdata->dbi_length) {
+ dev->cfg_size = imx_pcie->drvdata->dbi_length;
dev_info(&dev->dev, "Limiting cfg_size to %d\n",
dev->cfg_size);
}
}
}
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd,
- PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk);
+ PCI_CLASS_BRIDGE_PCI, 8, imx_pcie_quirk);
-static int __init imx6_pcie_init(void)
+static int __init imx_pcie_init(void)
{
#ifdef CONFIG_ARM
struct device_node *np;
- np = of_find_matching_node(NULL, imx6_pcie_of_match);
+ np = of_find_matching_node(NULL, imx_pcie_of_match);
if (!np)
return -ENODEV;
of_node_put(np);
@@ -1682,6 +1682,6 @@ static int __init imx6_pcie_init(void)
"external abort on non-linefetch");
#endif
- return platform_driver_register(&imx6_pcie_driver);
+ return platform_driver_register(&imx_pcie_driver);
}
-device_initcall(imx6_pcie_init);
+device_initcall(imx_pcie_init);
--
2.34.1
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^ permalink raw reply related [relevance 7%]
* Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H616
2024-05-28 16:08 0% ` Chen-Yu Tsai
@ 2024-05-28 16:47 0% ` Dragan Simic
0 siblings, 0 replies; 200+ results
From: Dragan Simic @ 2024-05-28 16:47 UTC (permalink / raw)
To: wens
Cc: linux-sunxi, jernej.skrabec, samuel, linux-arm-kernel,
devicetree, robh, krzk+dt, conor+dt, linux-kernel,
Andre Przywara
On 2024-05-28 18:08, Chen-Yu Tsai wrote:
> On Fri, May 3, 2024 at 5:09 PM Dragan Simic <dsimic@manjaro.org> wrote:
>>
>> Add missing cache information to the Allwinner H616 SoC dtsi, to allow
>> the userspace, which includes lscpu(1) that uses the virtual files
>> provided
>> by the kernel under the /sys/devices/system/cpu directory, to display
>> the
>> proper H616 cache information.
>>
>> Adding the cache information to the H616 SoC dtsi also makes the
>> following
>> warning message in the kernel log go away:
>>
>> cacheinfo: Unable to detect cache hierarchy for CPU 0
>>
>> Rather conspicuously, almost no cache-related information is available
>> in
>> the publicly available Allwinner H616 datasheet (version 1.0) and H616
>> user
>> manual (version 1.0). Thus, the cache parameters for the H616 SoC
>> dtsi were
>> obtained and derived by hand from the cache size and layout
>> specifications
>> found in the following technical reference manual, and from the cache
>> size
>> and die revision hints available from the following community-provided
>> data
>> and memory subsystem benchmarks:
>>
>> - ARM Cortex-A53 revision r0p4 TRM, version J
>> - Summary of the two available H616 die revisions and their
>> differences
>> in cache sizes observed from the CSSIDR_EL1 register readouts,
>> provided
>> by Andre Przywara [1][2]
>> - Tinymembench benchmark results of the H616-based OrangePi Zero 2
>> SBC,
>> provided by Thomas Kaiser [3]
>>
>> For future reference, here's a brief summary of the available
>> documentation
>> and the community-provided data and memory subsystem benchmarks:
>>
>> - All caches employ the 64-byte cache line length
>> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative
>> instruction
>> cache and 32 KB of L1 4-way, set-associative data cache
>> - The size of the L2 cache depends on the actual H616 die revision
>> (there
>> are two die revisions), so the entire SoC can have either 256 KB
>> or 1 MB
>> of unified L2 16-way, set-associative cache [1]
>>
>> Also for future reference, here's the relevant excerpt from the
>> community-
>> provided H616 memory subsystem benchmark, [3] which confirms that 32
>> KB and
>> 256 KB are the L1 data and L2 cache sizes, respectively:
>>
>> block size : single random read / dual random read
>> 1024 : 0.0 ns / 0.0 ns
>> 2048 : 0.0 ns / 0.0 ns
>> 4096 : 0.0 ns / 0.0 ns
>> 8192 : 0.0 ns / 0.0 ns
>> 16384 : 0.0 ns / 0.0 ns
>> 32768 : 0.0 ns / 0.0 ns
>> 65536 : 4.3 ns / 7.3 ns
>> 131072 : 6.6 ns / 10.5 ns
>> 262144 : 9.8 ns / 15.2 ns
>> 524288 : 91.8 ns / 142.9 ns
>> 1048576 : 138.6 ns / 188.3 ns
>> 2097152 : 163.0 ns / 204.8 ns
>> 4194304 : 178.8 ns / 213.5 ns
>> 8388608 : 187.1 ns / 217.9 ns
>> 16777216 : 192.2 ns / 220.9 ns
>> 33554432 : 196.5 ns / 224.0 ns
>> 67108864 : 215.7 ns / 259.5 ns
>>
>> The changes introduced to the H616 SoC dtsi by this patch specify 256
>> KB as
>> the L2 cache size. As outlined by Andre Przywara, [2] a follow-up
>> TF-A patch
>> will perform runtime adjustment of the device tree data, making the
>> correct
>> L2 cache size of 1 MB present in the device tree for the boards based
>> on the
>> revision of H616 that actually provides 1 MB of L2 cache.
>>
>> [1]
>> https://lore.kernel.org/linux-sunxi/20240430114627.0cfcd14a@donnerap.manchester.arm.com/
>> [2]
>> https://lore.kernel.org/linux-sunxi/20240501103059.10a8f7de@donnerap.manchester.arm.com/
>> [3]
>> https://raw.githubusercontent.com/ThomasKaiser/sbc-bench/master/results/4knM.txt
>>
>> Suggested-by: Andre Przywara <andre.przywara@arm.com>
>> Helped-by: Andre Przywara <andre.przywara@arm.com>
>> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
>> ---
>> .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 37
>> +++++++++++++++++++
>> 1 file changed, 37 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
>> index b2e85e52d1a1..4faed88d8909 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
>> @@ -26,30 +26,67 @@ cpu0: cpu@0 {
>> reg = <0>;
>> enable-method = "psci";
>> clocks = <&ccu CLK_CPUX>;
>> + i-cache-size = <0x8000>;
>> + i-cache-line-size = <64>;
>> + i-cache-sets = <256>;
>> + d-cache-size = <0x8000>;
>> + d-cache-line-size = <64>;
>> + d-cache-sets = <128>;
>> + next-level-cache = <&l2_cache>;
>
> This no longer applies due to the CPU DVFS stuff getting merged.
> Can you rebase and resend?
Sure, just sent the rebased version as the v2. [1]
[1]
https://lore.kernel.org/linux-sunxi/e4b9cc3e3d366a571e552c31dafa5de847bc1c12.1716914537.git.dsimic@manjaro.org/
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^ permalink raw reply [relevance 0%]
* [PATCH v2] arm64: dts: allwinner: Add cache information to the SoC dtsi for H616
@ 2024-05-28 16:45 4% Dragan Simic
0 siblings, 0 replies; 200+ results
From: Dragan Simic @ 2024-05-28 16:45 UTC (permalink / raw)
To: linux-sunxi
Cc: wens, jernej.skrabec, samuel, linux-arm-kernel, devicetree,
robh+dt, krzk+dt, conor+dt, linux-kernel, Andre Przywara
Add missing cache information to the Allwinner H616 SoC dtsi, to allow
the userspace, which includes lscpu(1) that uses the virtual files provided
by the kernel under the /sys/devices/system/cpu directory, to display the
proper H616 cache information.
Adding the cache information to the H616 SoC dtsi also makes the following
warning message in the kernel log go away:
cacheinfo: Unable to detect cache hierarchy for CPU 0
Rather conspicuously, almost no cache-related information is available in
the publicly available Allwinner H616 datasheet (version 1.0) and H616 user
manual (version 1.0). Thus, the cache parameters for the H616 SoC dtsi were
obtained and derived by hand from the cache size and layout specifications
found in the following technical reference manual, and from the cache size
and die revision hints available from the following community-provided data
and memory subsystem benchmarks:
- ARM Cortex-A53 revision r0p4 TRM, version J
- Summary of the two available H616 die revisions and their differences
in cache sizes observed from the CSSIDR_EL1 register readouts, provided
by Andre Przywara [1][2]
- Tinymembench benchmark results of the H616-based OrangePi Zero 2 SBC,
provided by Thomas Kaiser [3]
For future reference, here's a brief summary of the available documentation
and the community-provided data and memory subsystem benchmarks:
- All caches employ the 64-byte cache line length
- Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction
cache and 32 KB of L1 4-way, set-associative data cache
- The size of the L2 cache depends on the actual H616 die revision (there
are two die revisions), so the entire SoC can have either 256 KB or 1 MB
of unified L2 16-way, set-associative cache [1]
Also for future reference, here's the relevant excerpt from the community-
provided H616 memory subsystem benchmark, [3] which confirms that 32 KB and
256 KB are the L1 data and L2 cache sizes, respectively:
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.3 ns / 7.3 ns
131072 : 6.6 ns / 10.5 ns
262144 : 9.8 ns / 15.2 ns
524288 : 91.8 ns / 142.9 ns
1048576 : 138.6 ns / 188.3 ns
2097152 : 163.0 ns / 204.8 ns
4194304 : 178.8 ns / 213.5 ns
8388608 : 187.1 ns / 217.9 ns
16777216 : 192.2 ns / 220.9 ns
33554432 : 196.5 ns / 224.0 ns
67108864 : 215.7 ns / 259.5 ns
The changes introduced to the H616 SoC dtsi by this patch specify 256 KB as
the L2 cache size. As outlined by Andre Przywara, [2] a follow-up TF-A patch
will perform runtime adjustment of the device tree data, making the correct
L2 cache size of 1 MB present in the device tree for the boards based on the
revision of H616 that actually provides 1 MB of L2 cache.
[1] https://lore.kernel.org/linux-sunxi/20240430114627.0cfcd14a@donnerap.manchester.arm.com/
[2] https://lore.kernel.org/linux-sunxi/20240501103059.10a8f7de@donnerap.manchester.arm.com/
[3] https://raw.githubusercontent.com/ThomasKaiser/sbc-bench/master/results/4knM.txt
Suggested-by: Andre Przywara <andre.przywara@arm.com>
Helped-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
---
Notes:
Link to v1: https://lore.kernel.org/linux-sunxi/9d52e6d338a059618d894abb0764015043330c2b.1714727227.git.dsimic@manjaro.org/T/#u
Changes in v2:
- Collected one Reviewed-by tag
- Rebased the patch to 6.10-rc1, as requested by Chen-Yu, [4] with
no functional changes introduced
[4] https://lore.kernel.org/linux-sunxi/CAGb2v67_4MHEZned0X1sFxisySahemHYo6sjn9sttQY+RO=VQw@mail.gmail.com/
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index 921d5f61d8d6..6595e0406b6d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -27,33 +27,70 @@ cpu0: cpu@0 {
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
};
};
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^ permalink raw reply related [relevance 4%]
* Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H616
2024-05-03 9:09 4% [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H616 Dragan Simic
2024-05-08 11:05 0% ` Andre Przywara
@ 2024-05-28 16:08 0% ` Chen-Yu Tsai
2024-05-28 16:47 0% ` Dragan Simic
1 sibling, 1 reply; 200+ results
From: Chen-Yu Tsai @ 2024-05-28 16:08 UTC (permalink / raw)
To: Dragan Simic
Cc: linux-sunxi, jernej.skrabec, samuel, linux-arm-kernel,
devicetree, robh, krzk+dt, conor+dt, linux-kernel,
Andre Przywara
On Fri, May 3, 2024 at 5:09 PM Dragan Simic <dsimic@manjaro.org> wrote:
>
> Add missing cache information to the Allwinner H616 SoC dtsi, to allow
> the userspace, which includes lscpu(1) that uses the virtual files provided
> by the kernel under the /sys/devices/system/cpu directory, to display the
> proper H616 cache information.
>
> Adding the cache information to the H616 SoC dtsi also makes the following
> warning message in the kernel log go away:
>
> cacheinfo: Unable to detect cache hierarchy for CPU 0
>
> Rather conspicuously, almost no cache-related information is available in
> the publicly available Allwinner H616 datasheet (version 1.0) and H616 user
> manual (version 1.0). Thus, the cache parameters for the H616 SoC dtsi were
> obtained and derived by hand from the cache size and layout specifications
> found in the following technical reference manual, and from the cache size
> and die revision hints available from the following community-provided data
> and memory subsystem benchmarks:
>
> - ARM Cortex-A53 revision r0p4 TRM, version J
> - Summary of the two available H616 die revisions and their differences
> in cache sizes observed from the CSSIDR_EL1 register readouts, provided
> by Andre Przywara [1][2]
> - Tinymembench benchmark results of the H616-based OrangePi Zero 2 SBC,
> provided by Thomas Kaiser [3]
>
> For future reference, here's a brief summary of the available documentation
> and the community-provided data and memory subsystem benchmarks:
>
> - All caches employ the 64-byte cache line length
> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction
> cache and 32 KB of L1 4-way, set-associative data cache
> - The size of the L2 cache depends on the actual H616 die revision (there
> are two die revisions), so the entire SoC can have either 256 KB or 1 MB
> of unified L2 16-way, set-associative cache [1]
>
> Also for future reference, here's the relevant excerpt from the community-
> provided H616 memory subsystem benchmark, [3] which confirms that 32 KB and
> 256 KB are the L1 data and L2 cache sizes, respectively:
>
> block size : single random read / dual random read
> 1024 : 0.0 ns / 0.0 ns
> 2048 : 0.0 ns / 0.0 ns
> 4096 : 0.0 ns / 0.0 ns
> 8192 : 0.0 ns / 0.0 ns
> 16384 : 0.0 ns / 0.0 ns
> 32768 : 0.0 ns / 0.0 ns
> 65536 : 4.3 ns / 7.3 ns
> 131072 : 6.6 ns / 10.5 ns
> 262144 : 9.8 ns / 15.2 ns
> 524288 : 91.8 ns / 142.9 ns
> 1048576 : 138.6 ns / 188.3 ns
> 2097152 : 163.0 ns / 204.8 ns
> 4194304 : 178.8 ns / 213.5 ns
> 8388608 : 187.1 ns / 217.9 ns
> 16777216 : 192.2 ns / 220.9 ns
> 33554432 : 196.5 ns / 224.0 ns
> 67108864 : 215.7 ns / 259.5 ns
>
> The changes introduced to the H616 SoC dtsi by this patch specify 256 KB as
> the L2 cache size. As outlined by Andre Przywara, [2] a follow-up TF-A patch
> will perform runtime adjustment of the device tree data, making the correct
> L2 cache size of 1 MB present in the device tree for the boards based on the
> revision of H616 that actually provides 1 MB of L2 cache.
>
> [1] https://lore.kernel.org/linux-sunxi/20240430114627.0cfcd14a@donnerap.manchester.arm.com/
> [2] https://lore.kernel.org/linux-sunxi/20240501103059.10a8f7de@donnerap.manchester.arm.com/
> [3] https://raw.githubusercontent.com/ThomasKaiser/sbc-bench/master/results/4knM.txt
>
> Suggested-by: Andre Przywara <andre.przywara@arm.com>
> Helped-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
> ---
> .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 37 +++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> index b2e85e52d1a1..4faed88d8909 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> @@ -26,30 +26,67 @@ cpu0: cpu@0 {
> reg = <0>;
> enable-method = "psci";
> clocks = <&ccu CLK_CPUX>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_cache>;
This no longer applies due to the CPU DVFS stuff getting merged.
Can you rebase and resend?
Thanks
ChenYu
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v6 2/2] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support
2024-05-28 2:59 6% ` [PATCH v6 2/2] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support Richard Zhu
@ 2024-05-28 14:52 0% ` Frank Li
0 siblings, 0 replies; 200+ results
From: Frank Li @ 2024-05-28 14:52 UTC (permalink / raw)
To: Richard Zhu
Cc: conor, vkoul, kishon, robh+dt, krzysztof.kozlowski+dt, conor+dt,
linux-phy, devicetree, linux-arm-kernel, linux-kernel, kernel,
imx
On Tue, May 28, 2024 at 10:59:14AM +0800, Richard Zhu wrote:
> Add i.MX8QM HSIO PHY driver support.
>
> i.MX8QM HSIO has three lane PHY instances, and can be bound to the
> following controllers in the different use cases listed in below table.
> - two lanes capable PCIEA controller.
> - one lane PCIEB controller.
> - AHCI SATA controller.
>
> i.MX8QM HSIO PHYs support the following use cases.
> +----------------------------------------------------+
> | | Lane0| Lane1| Lane2|
> |-------------------------------|------|------|------|
> | use case 1: PCIEAX2SATA | PCIEA| PCIEA| SATA |
> |-------------------------------|------|------|------|
> | use case 2: PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB|
> |-------------------------------|------|------|------|
> | use case 3: PCIEAPCIEBSATA | PCIEA| PCIEB| SATA |
> +----------------------------------------------------+
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
after fix below two nit.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
> drivers/phy/freescale/Kconfig | 8 +
> drivers/phy/freescale/Makefile | 1 +
> drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 612 ++++++++++++++++++++
> 3 files changed, 621 insertions(+)
> create mode 100644 drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
>
> diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
> index 853958fb2c06..c9ee48aeea9e 100644
> --- a/drivers/phy/freescale/Kconfig
> +++ b/drivers/phy/freescale/Kconfig
> @@ -35,6 +35,14 @@ config PHY_FSL_IMX8M_PCIE
> Enable this to add support for the PCIE PHY as found on
> i.MX8M family of SOCs.
>
> +config PHY_FSL_IMX8QM_HSIO
> + tristate "Freescale i.MX8QM HSIO PHY"
> + depends on OF && HAS_IOMEM
> + select GENERIC_PHY
> + help
> + Enable this to add support for the HSIO PHY as found on
> + i.MX8QM family of SOCs.
> +
> endif
>
> config PHY_FSL_LYNX_28G
> diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
> index cedb328bc4d2..b56b4d5c18ea 100644
> --- a/drivers/phy/freescale/Makefile
> +++ b/drivers/phy/freescale/Makefile
> @@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
> obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
> obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
> obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
> +obj-$(CONFIG_PHY_FSL_IMX8QM_HSIO) += phy-fsl-imx8qm-hsio.o
> obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
> diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> new file mode 100644
> index 000000000000..73e0c50fcdae
> --- /dev/null
> +++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> @@ -0,0 +1,612 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/pci_regs.h>
> +#include <linux/phy/phy.h>
> +#include <linux/phy/pcie.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/phy/phy-imx8-pcie.h>
> +
> +#define MAX_NUM_LANE 3
> +#define LANE_NUM_CLKS 5
> +
> +/* Parameters for the waiting for PCIe PHY PLL to lock */
> +#define PHY_INIT_WAIT_USLEEP_MAX 10
> +#define PHY_INIT_WAIT_TIMEOUT (1000 * PHY_INIT_WAIT_USLEEP_MAX)
> +
> +/* i.MX8Q HSIO registers */
> +#define HSIO_CTRL0 0x0
> +#define HSIO_APB_RSTN_0 BIT(0)
> +#define HSIO_APB_RSTN_1 BIT(1)
> +#define HSIO_PIPE_RSTN_0_MASK GENMASK(25, 24)
> +#define HSIO_PIPE_RSTN_1_MASK GENMASK(27, 26)
> +#define HSIO_MODE_MASK GENMASK(20, 17)
> +#define HSIO_MODE_PCIE 0x0
> +#define HSIO_MODE_SATA 0x4
> +#define HSIO_DEVICE_TYPE_MASK GENMASK(27, 24)
> +#define HSIO_EPCS_TXDEEMP BIT(5)
> +#define HSIO_EPCS_TXDEEMP_SEL BIT(6)
> +#define HSIO_EPCS_PHYRESET_N BIT(7)
> +#define HSIO_RESET_N BIT(12)
> +
> +#define HSIO_IOB_RXENA BIT(0)
> +#define HSIO_IOB_TXENA BIT(1)
> +#define HSIO_IOB_A_0_TXOE BIT(2)
> +#define HSIO_IOB_A_0_M1M0_2 BIT(4)
> +#define HSIO_IOB_A_0_M1M0_MASK GENMASK(4, 3)
> +#define HSIO_PHYX1_EPCS_SEL BIT(12)
> +#define HSIO_PCIE_AB_SELECT BIT(13)
> +
> +#define HSIO_PHY_STS0 0x4
> +#define HSIO_LANE0_TX_PLL_LOCK BIT(4)
> +#define HSIO_LANE1_TX_PLL_LOCK BIT(12)
> +
> +#define HSIO_CTRL2 0x8
> +#define HSIO_LTSSM_ENABLE BIT(4)
> +#define HSIO_BUTTON_RST_N BIT(21)
> +#define HSIO_PERST_N BIT(22)
> +#define HSIO_POWER_UP_RST_N BIT(23)
> +
> +#define HSIO_PCIE_STS0 0xc
> +#define HSIO_PM_REQ_CORE_RST BIT(19)
> +
> +#define HSIO_REG48_PMA_STATUS 0x30
> +#define HSIO_REG48_PMA_RDY BIT(7)
> +
> +struct imx_hsio_drvdata {
> + int lane_num;
> +};
> +
> +struct imx_hsio_lane {
> + u32 ctrl_index;
> + u32 ctrl_off;
> + u32 idx;
> + u32 phy_off;
> + u32 phy_type;
> + const char * const *clk_names;
> + struct clk_bulk_data clks[LANE_NUM_CLKS];
> + struct imx_hsio_priv *priv;
> + struct phy *phy;
> + enum phy_mode phy_mode;
> +};
> +
> +struct imx_hsio_priv {
> + void __iomem *base;
> + struct device *dev;
> + struct mutex lock;
> + const char *hsio_cfg;
> + const char *refclk_pad;
> + u32 open_cnt;
> + struct regmap *phy;
> + struct regmap *ctrl;
> + struct regmap *misc;
> + const struct imx_hsio_drvdata *drvdata;
> + struct imx_hsio_lane lane[MAX_NUM_LANE];
> +};
> +
> +static const char * const lan0_pcie_clks[] = {"apb_pclk0", "pclk0", "ctl0_crr",
> + "phy0_crr", "misc_crr"};
> +static const char * const lan1_pciea_clks[] = {"apb_pclk1", "pclk1", "ctl0_crr",
> + "phy0_crr", "misc_crr"};
> +static const char * const lan1_pcieb_clks[] = {"apb_pclk1", "pclk1", "ctl1_crr",
> + "phy0_crr", "misc_crr"};
> +static const char * const lan2_pcieb_clks[] = {"apb_pclk2", "pclk2", "ctl1_crr",
> + "phy1_crr", "misc_crr"};
> +static const char * const lan2_sata_clks[] = {"pclk2", "epcs_tx", "epcs_rx",
> + "phy1_crr", "misc_crr"};
> +
> +static const struct regmap_config regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +static int imx_hsio_init(struct phy *phy)
> +{
> + int ret, i;
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> + struct device *dev = priv->dev;
> +
> + /* Assign clocks refer to different modes */
> + switch (lane->phy_type) {
> + case PHY_TYPE_PCIE:
> + lane->phy_mode = PHY_MODE_PCIE;
> + if (lane->ctrl_index == 0) { /* PCIEA */
> + lane->ctrl_off = 0;
> + lane->phy_off = 0;
> +
> + for (i = 0; i < LANE_NUM_CLKS; i++) {
> + if (lane->idx == 0)
> + lane->clks[i].id = lan0_pcie_clks[i];
> + else
> + lane->clks[i].id = lan1_pciea_clks[i];
> + }
> + } else { /* PCIEB */
> + if (lane->idx == 0) { /* i.MX8QXP */
> + lane->ctrl_off = 0;
> + lane->phy_off = 0;
> + } else {
> + /*
> + * On i.MX8QM, only second or third lane can be
> + * bound to PCIEB.
> + */
> + lane->ctrl_off = SZ_64K;
> + if (lane->idx == 1)
> + lane->phy_off = 0;
> + else /* the third lane is bound to PCIEB */
> + lane->phy_off = SZ_64K;
> + }
> +
> + for (i = 0; i < LANE_NUM_CLKS; i++) {
> + if (lane->idx == 1)
> + lane->clks[i].id = lan1_pcieb_clks[i];
> + else if (lane->idx == 2)
> + lane->clks[i].id = lan2_pcieb_clks[i];
> + else /* i.MX8QXP only has PCIEB, idx is 0 */
> + lane->clks[i].id = lan0_pcie_clks[i];
> + }
> + }
> + break;
> + case PHY_TYPE_SATA:
> + /* On i.MX8QM, only the third lane can be bound to SATA */
> + lane->phy_mode = PHY_MODE_SATA;
> + lane->ctrl_off = SZ_128K;
> + lane->phy_off = SZ_64K;
> +
> + for (i = 0; i < LANE_NUM_CLKS; i++)
> + lane->clks[i].id = lan2_sata_clks[i];
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + /* Fetch clocks and enable them */
> + ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, lane->clks);
> + if (ret)
> + return ret;
> + ret = clk_bulk_prepare_enable(LANE_NUM_CLKS, lane->clks);
> + if (ret)
> + return ret;
> +
> + /* allow the clocks to stabilize */
> + usleep_range(200, 500);
> + return 0;
> +}
> +
> +static int imx_hsio_exit(struct phy *phy)
> +{
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> +
> + clk_bulk_disable_unprepare(LANE_NUM_CLKS, lane->clks);
> +
> + return 0;
> +}
> +
> +static void imx_hsio_pcie_phy_resets(struct phy *phy)
> +{
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_BUTTON_RST_N);
> + regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_PERST_N);
> + regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_POWER_UP_RST_N);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_BUTTON_RST_N);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_PERST_N);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_POWER_UP_RST_N);
> +
> + if (lane->idx == 1) {
> + regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_1);
> + regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_PIPE_RSTN_1_MASK);
> + } else {
> + regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_0);
> + regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_PIPE_RSTN_0_MASK);
> + }
> +}
> +
> +static void imx_hsio_sata_phy_resets(struct phy *phy)
> +{
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + /* clear PHY RST, then set it */
> + regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_PHYRESET_N);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_PHYRESET_N);
> +
> + /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
> + udelay(1);
> + regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
> + HSIO_RESET_N);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
> +}
> +
> +static void imx_hsio_configure_clk_pad(struct phy *phy)
> +{
> + bool pll = false;
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + if (strncmp(priv->refclk_pad, "output", 6) == 0) {
> + pll = true;
> + regmap_update_bits(priv->misc, HSIO_CTRL0,
> + HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
> + HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_2);
> + } else {
> + regmap_update_bits(priv->misc, HSIO_CTRL0,
> + HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
> + 0);
> + }
> +
> + regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_RXENA,
> + pll ? 0 : HSIO_IOB_RXENA);
> + regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_TXENA,
> + pll ? HSIO_IOB_TXENA : 0);
> +}
> +
> +static void imx_hsio_pre_set(struct phy *phy)
> +{
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + if (strncmp(priv->hsio_cfg, "pcieax2pcieb", 10) == 0) {
> + regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
> + } else if (strncmp(priv->hsio_cfg, "pcieax2sata", 9) == 0) {
> + regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
> + } else if (strncmp(priv->hsio_cfg, "pcieapciebsata", 12) == 0) {
> + regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
> + regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
> + }
> +
> + imx_hsio_configure_clk_pad(phy);
> +}
> +
> +static int imx_hsio_pcie_power_on(struct phy *phy)
> +{
> + int ret;
> + u32 val, addr, cond;
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + imx_hsio_pcie_phy_resets(phy);
> +
> + /* Toggle apb_pclk to make sure PM_REQ_CORE_RST is cleared. */
> + clk_disable_unprepare(lane->clks[0].clk);
> + mdelay(1);
> + ret = clk_prepare_enable(lane->clks[0].clk);
> + if (ret) {
> + dev_err(priv->dev, "unable to enable phy apb_pclk\n");
> + return ret;
> + }
> +
> + addr = lane->ctrl_off + HSIO_PCIE_STS0;
> + cond = HSIO_PM_REQ_CORE_RST;
> + ret = regmap_read_poll_timeout(priv->ctrl, addr, val,
> + (val & cond) == 0,
> + PHY_INIT_WAIT_USLEEP_MAX,
> + PHY_INIT_WAIT_TIMEOUT);
> + if (ret)
> + dev_err(priv->dev, "HSIO_PM_REQ_CORE_RST is set\n");
> + return ret;
> +}
> +
> +static int imx_hsio_sata_power_on(struct phy *phy)
> +{
> + int ret;
> + u32 val, cond;
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0, HSIO_APB_RSTN_0);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_TXDEEMP);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_TXDEEMP_SEL);
> +
> + imx_hsio_sata_phy_resets(phy);
> +
> + cond = HSIO_REG48_PMA_RDY;
> + ret = read_poll_timeout(readb, val, ((val & cond) == cond),
> + PHY_INIT_WAIT_USLEEP_MAX,
> + PHY_INIT_WAIT_TIMEOUT, false,
> + priv->base + HSIO_REG48_PMA_STATUS);
> + if (ret)
> + dev_err(priv->dev, "PHY calibration is timeout\n");
> + else
> + dev_dbg(priv->dev, "PHY calibration is done\n");
> +
> + return ret;
> +}
> +
> +static int imx_hsio_power_on(struct phy *phy)
> +{
> + int ret;
> + u32 val, cond;
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + scoped_guard(mutex, &priv->lock) {
> + if (!priv->open_cnt)
> + imx_hsio_pre_set(phy);
> + priv->open_cnt++;
> + }
> +
> + if (lane->phy_mode == PHY_MODE_PCIE)
> + ret = imx_hsio_pcie_power_on(phy);
> + else /* SATA */
> + ret = imx_hsio_sata_power_on(phy);
> + if (ret)
> + return ret;
> +
> + /* Polling to check the PHY is ready or not. */
> + if (lane->idx == 1)
> + cond = HSIO_LANE1_TX_PLL_LOCK;
> + else
> + /*
> + * Except the phy_off, the bit-offset of lane2 is same to lane0.
> + * Merge the lane0 and lane2 bit-operations together.
> + */
> + cond = HSIO_LANE0_TX_PLL_LOCK;
> +
> + ret = regmap_read_poll_timeout(priv->phy, lane->phy_off + HSIO_PHY_STS0,
> + val, ((val & cond) == cond),
> + PHY_INIT_WAIT_USLEEP_MAX,
> + PHY_INIT_WAIT_TIMEOUT);
> + if (ret) {
> + dev_err(priv->dev, "IMX8Q PHY%d PLL lock timeout\n", lane->idx);
> + return ret;
> + }
> + dev_dbg(priv->dev, "IMX8Q PHY%d PLL is locked\n", lane->idx);
> +
> + return ret;
> +}
> +
> +static int imx_hsio_power_off(struct phy *phy)
> +{
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + scoped_guard(mutex, &priv->lock) {
> + priv->open_cnt--;
> + if (priv->open_cnt == 0) {
> + regmap_clear_bits(priv->misc, HSIO_CTRL0,
> + HSIO_PCIE_AB_SELECT);
> + regmap_clear_bits(priv->misc, HSIO_CTRL0,
> + HSIO_PHYX1_EPCS_SEL);
> +
> + if (lane->phy_mode == PHY_MODE_PCIE) {
> + regmap_clear_bits(priv->ctrl,
> + lane->ctrl_off + HSIO_CTRL2,
> + HSIO_BUTTON_RST_N);
> + regmap_clear_bits(priv->ctrl,
> + lane->ctrl_off + HSIO_CTRL2,
> + HSIO_PERST_N);
> + regmap_clear_bits(priv->ctrl,
> + lane->ctrl_off + HSIO_CTRL2,
> + HSIO_POWER_UP_RST_N);
> + } else {
> + regmap_clear_bits(priv->ctrl,
> + lane->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_TXDEEMP);
> + regmap_clear_bits(priv->ctrl,
> + lane->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_TXDEEMP_SEL);
> + regmap_clear_bits(priv->ctrl,
> + lane->ctrl_off + HSIO_CTRL0,
> + HSIO_RESET_N);
> + }
> +
> + if (lane->idx == 1) {
> + regmap_clear_bits(priv->phy,
> + lane->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_1);
> + regmap_clear_bits(priv->phy,
> + lane->phy_off + HSIO_CTRL0,
> + HSIO_PIPE_RSTN_1_MASK);
> + } else {
> + /*
> + * Except the phy_off, the bit-offset of lane2 is same
> + * to lane0. Merge the lane0 and lane2 bit-operations
> + * together.
> + */
> + regmap_clear_bits(priv->phy,
> + lane->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_0);
> + regmap_clear_bits(priv->phy,
> + lane->phy_off + HSIO_CTRL0,
> + HSIO_PIPE_RSTN_0_MASK);
> + }
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int imx_hsio_set_mode(struct phy *phy, enum phy_mode mode,
> + int submode)
> +{
> + u32 val;
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + if (lane->phy_mode != mode)
> + return -EINVAL;
> +
> + val = (mode == PHY_MODE_PCIE) ? HSIO_MODE_PCIE : HSIO_MODE_SATA;
> + val = FIELD_PREP(HSIO_MODE_MASK, val);
> + regmap_update_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_MODE_MASK, val);
> +
> + switch (submode) {
> + case PHY_MODE_PCIE_RC:
> + val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
> + break;
> + case PHY_MODE_PCIE_EP:
> + val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ENDPOINT);
> + break;
> + default: /* Support only PCIe EP and RC now. */
> + return 0;
> + }
> + if (submode)
> + regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
> + HSIO_DEVICE_TYPE_MASK, val);
> +
> + return 0;
> +}
> +
> +static int imx_hsio_set_speed(struct phy *phy, int speed)
> +{
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_LTSSM_ENABLE,
> + speed ? HSIO_LTSSM_ENABLE : 0);
> + return 0;
> +}
> +
> +static const struct phy_ops imx_hsio_ops = {
> + .init = imx_hsio_init,
> + .exit = imx_hsio_exit,
> + .power_on = imx_hsio_power_on,
> + .power_off = imx_hsio_power_off,
> + .set_mode = imx_hsio_set_mode,
> + .set_speed = imx_hsio_set_speed,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct imx_hsio_drvdata imx8qxp_hsio_drvdata = {
> + .lane_num = 0x1,
> +};
> +
> +static const struct imx_hsio_drvdata imx_hsio_drvdata = {
nit: imx8qm_hsio_drvdata looks better name.
> + .lane_num = 0x3,
> +};
> +
> +static const struct of_device_id imx_hsio_of_match[] = {
> + {.compatible = "fsl,imx8qm-hsio", .data = &imx_hsio_drvdata},
> + {.compatible = "fsl,imx8qxp-hsio", .data = &imx8qxp_hsio_drvdata},
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, imx_hsio_of_match);
> +
> +static struct phy *imx_hsio_xlate(struct device *dev,
> + const struct of_phandle_args *args)
> +{
> + struct imx_hsio_priv *priv = dev_get_drvdata(dev);
> + int idx = args->args[0];
> + int phy_type = args->args[1];
> + int ctrl_index = args->args[2];
> +
> + if (idx < 0 || idx >= priv->drvdata->lane_num)
> + return ERR_PTR(-EINVAL);
> + priv->lane[idx].idx = idx;
> + priv->lane[idx].phy_type = phy_type;
> + priv->lane[idx].ctrl_index = ctrl_index;
> +
> + return priv->lane[idx].phy;
> +}
> +
> +static int imx_hsio_probe(struct platform_device *pdev)
> +{
> + int i;
> + void __iomem *off;
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct imx_hsio_priv *priv;
> + struct phy_provider *provider;
> +
> + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> + priv->dev = &pdev->dev;
> + priv->drvdata = of_device_get_match_data(dev);
> +
> + /* Get HSIO configuration mode */
> + if (of_property_read_string(np, "fsl,hsio-cfg", &priv->hsio_cfg))
> + priv->hsio_cfg = "pcieapciebsata";
> + /* Get PHY refclk pad mode */
> + if (of_property_read_string(np, "fsl,refclk-pad-mode",
> + &priv->refclk_pad))
> + priv->refclk_pad = NULL;
> +
> + priv->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(priv->base))
> + return PTR_ERR(priv->base);
> +
> + off = devm_platform_ioremap_resource_byname(pdev, "phy");
> + priv->phy = devm_regmap_init_mmio(dev, off, ®map_config);
> + if (IS_ERR(priv->phy))
> + return dev_err_probe(dev, PTR_ERR(priv->phy),
> + "unable to find phy csr registers\n");
> +
> + off = devm_platform_ioremap_resource_byname(pdev, "ctrl");
> + priv->ctrl = devm_regmap_init_mmio(dev, off, ®map_config);
> + if (IS_ERR(priv->ctrl))
> + return dev_err_probe(dev, PTR_ERR(priv->ctrl),
> + "unable to find ctrl csr registers\n");
> +
> + off = devm_platform_ioremap_resource_byname(pdev, "misc");
> + priv->misc = devm_regmap_init_mmio(dev, off, ®map_config);
> + if (IS_ERR(priv->misc))
> + return dev_err_probe(dev, PTR_ERR(priv->misc),
> + "unable to find misc csr registers\n");
> +
> + for (i = 0; i < priv->drvdata->lane_num; i++) {
> + struct imx_hsio_lane *lane = &priv->lane[i];
> + struct phy *phy;
> +
> + memset(lane, 0, sizeof(*lane));
nit: not neccessary to call memset, because devm_kzalloc() already init
everything to 0
> +
> + phy = devm_phy_create(&pdev->dev, NULL, &imx_hsio_ops);
> + if (IS_ERR(phy))
> + return PTR_ERR(phy);
> +
> + lane->priv = priv;
> + lane->phy = phy;
> + lane->idx = i;
> + phy_set_drvdata(phy, lane);
> + }
> +
> + dev_set_drvdata(dev, priv);
> + dev_set_drvdata(&pdev->dev, priv);
> +
> + provider = devm_of_phy_provider_register(&pdev->dev, imx_hsio_xlate);
> +
> + return PTR_ERR_OR_ZERO(provider);
> +}
> +
> +static struct platform_driver imx_hsio_driver = {
> + .probe = imx_hsio_probe,
> + .driver = {
> + .name = "imx8qm-hsio-phy",
> + .of_match_table = imx_hsio_of_match,
> + }
> +};
> +module_platform_driver(imx_hsio_driver);
> +
> +MODULE_DESCRIPTION("FSL IMX8QM HSIO SERDES PHY driver");
> +MODULE_LICENSE("GPL");
> --
> 2.37.1
>
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^ permalink raw reply [relevance 0%]
* [syzbot] [arm?] BUG: unable to handle kernel paging request in task_h_load
@ 2024-05-28 12:47 10% syzbot
0 siblings, 0 replies; 200+ results
From: syzbot @ 2024-05-28 12:47 UTC (permalink / raw)
To: catalin.marinas, linux-arm-kernel, linux-kernel, syzkaller-bugs, will
Hello,
syzbot found the following issue on:
HEAD commit: 6d69b6c12fce Merge tag 'nfs-for-6.10-1' of git://git.linux..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=164ce7f0980000
kernel config: https://syzkaller.appspot.com/x/.config?x=21de3d423116c304
dashboard link: https://syzkaller.appspot.com/bug?extid=8336c747d79a4c3a0944
compiler: aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40
userspace arch: arm64
syz repro: https://syzkaller.appspot.com/x/repro.syz?x=119fbe58980000
C reproducer: https://syzkaller.appspot.com/x/repro.c?x=13a8443c980000
Downloadable assets:
disk image (non-bootable): https://storage.googleapis.com/syzbot-assets/384ffdcca292/non_bootable_disk-6d69b6c1.raw.xz
vmlinux: https://storage.googleapis.com/syzbot-assets/9fa4d7c3665d/vmlinux-6d69b6c1.xz
kernel image: https://storage.googleapis.com/syzbot-assets/131ac291917c/Image-6d69b6c1.gz.xz
IMPORTANT: if you fix the issue, please add the following tag to the commit:
Reported-by: syzbot+8336c747d79a4c3a0944@syzkaller.appspotmail.com
Unable to handle kernel paging request at virtual address 007000000621a118
Mem abort info:
ESR = 0x0000000096000004
EC = 0x25: DABT (current EL), IL = 32 bits
SET = 0, FnV = 0
EA = 0, S1PTW = 0
FSC = 0x04: level 0 translation fault
Data abort info:
ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
CM = 0, WnR = 0, TnD = 0, TagAccess = 0
GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
[007000000621a118] address between user and kernel address ranges
Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP
Modules linked in:
CPU: 1 PID: 3189 Comm: syz-executor371 Not tainted 6.9.0-syzkaller-12124-g6d69b6c12fce #0
Hardware name: linux,dummy-virt (DT)
pstate: 204000c9 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : cfs_rq_of kernel/sched/sched.h:1468 [inline]
pc : update_cfs_rq_h_load kernel/sched/fair.c:9441 [inline]
pc : task_h_load+0x40/0xb8 kernel/sched/fair.c:9466
lr : detach_tasks kernel/sched/fair.c:9181 [inline]
lr : sched_balance_rq+0x80c/0xc94 kernel/sched/fair.c:11375
sp : ffff80008000bd50
x29: ffff80008000bd50 x28: f8f0000004c62538 x27: ffff8000825e3308
x26: 0000000000000001 x25: fff000007f8d6de0 x24: ffff80008000bf14
x23: fff000007f8d6340 x22: fff000007f8d6340 x21: fff000007f8d6d40
x20: ffff80008000be78 x19: f8f0000004c62480 x18: ffffffffffffffff
x17: fff07ffffd331000 x16: ffff800080008000 x15: 0000000000000001
x14: 000000000000000a x13: 0000000000000000 x12: 0000000000000011
x11: 0000000000000001 x10: 0000000000000001 x9 : 0000000000000da8
x8 : fff000007f8d6440 x7 : f4f000000621a200 x6 : 0000000000000001
x5 : 00000000ffffbd09 x4 : ffff80008000be78 x3 : f5f000000602ff40
x2 : f87000000621a080 x1 : 00000000ffffa6e9 x0 : f8f0000004c62480
Call trace:
update_cfs_rq_h_load kernel/sched/fair.c:9440 [inline]
task_h_load+0x40/0xb8 kernel/sched/fair.c:9466
sched_balance_domains+0x270/0x3ac kernel/sched/fair.c:11798
sched_balance_softirq+0x50/0x74 kernel/sched/fair.c:12503
handle_softirqs+0x10c/0x240 kernel/softirq.c:554
__do_softirq+0x14/0x20 kernel/softirq.c:588
____do_softirq+0x10/0x1c arch/arm64/kernel/irq.c:81
call_on_irq_stack+0x24/0x4c arch/arm64/kernel/entry.S:889
do_softirq_own_stack+0x1c/0x28 arch/arm64/kernel/irq.c:86
invoke_softirq kernel/softirq.c:435 [inline]
__irq_exit_rcu kernel/softirq.c:637 [inline]
irq_exit_rcu+0xbc/0xd8 kernel/softirq.c:649
__el1_irq arch/arm64/kernel/entry-common.c:537 [inline]
el1_interrupt+0x38/0x64 arch/arm64/kernel/entry-common.c:551
el1h_64_irq_handler+0x18/0x24 arch/arm64/kernel/entry-common.c:556
el1h_64_irq+0x64/0x68 arch/arm64/kernel/entry.S:594
__pte_offset_map+0x2c/0x100 mm/pgtable-generic.c:292
pte_offset_map_nolock+0x38/0xb0 mm/pgtable-generic.c:314
handle_pte_fault mm/memory.c:5366 [inline]
__handle_mm_fault+0x2e8/0xc20 mm/memory.c:5523
handle_mm_fault+0x68/0x27c mm/memory.c:5688
do_page_fault+0xf8/0x480 arch/arm64/mm/fault.c:578
do_translation_fault+0xac/0xbc arch/arm64/mm/fault.c:690
do_mem_abort+0x44/0x94 arch/arm64/mm/fault.c:826
el0_ia+0xa4/0x118 arch/arm64/kernel/entry-common.c:598
el0t_64_sync_handler+0xd0/0x12c arch/arm64/kernel/entry-common.c:736
el0t_64_sync+0x19c/0x1a0 arch/arm64/kernel/entry.S:598
Code: b5000082 1400001c f9404842 b4000382 (f9404c41)
---[ end trace 0000000000000000 ]---
----------------
Code disassembly (best guess):
0: b5000082 cbnz x2, 0x10
4: 1400001c b 0x74
8: f9404842 ldr x2, [x2, #144]
c: b4000382 cbz x2, 0x7c
* 10: f9404c41 ldr x1, [x2, #152] <-- trapping instruction
---
This report is generated by a bot. It may contain errors.
See https://goo.gl/tpsmEJ for more information about syzbot.
syzbot engineers can be reached at syzkaller@googlegroups.com.
syzbot will keep track of this issue. See:
https://goo.gl/tpsmEJ#status for how to communicate with syzbot.
If the report is already addressed, let syzbot know by replying with:
#syz fix: exact-commit-title
If you want syzbot to run the reproducer, reply with:
#syz test: git://repo/address.git branch-or-commit-hash
If you attach or paste a git patch, syzbot will apply it before testing.
If you want to overwrite report's subsystems, reply with:
#syz set subsystems: new-subsystem
(See the list of subsystem names on the web dashboard)
If the report is a duplicate of another one, reply with:
#syz dup: exact-subject-of-another-report
If you want to undo deduplication, reply with:
#syz undup
_______________________________________________
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^ permalink raw reply [relevance 10%]
* [PATCH] i2c: viai2c: turn common code into a proper module
@ 2024-05-28 12:06 3% Arnd Bergmann
0 siblings, 0 replies; 200+ results
From: Arnd Bergmann @ 2024-05-28 12:06 UTC (permalink / raw)
To: Andi Shyti, Hans Hu, Wolfram Sang
Cc: Arnd Bergmann, Wentong Wu, linux-i2c, linux-kernel, linux-arm-kernel
From: Arnd Bergmann <arnd@arndb.de>
The i2c-viai2c-common.c file is used by two drivers, but is not a proper
abstraction and can get linked into both modules in the same configuration,
which results in a warning:
scripts/Makefile.build:236: drivers/i2c/busses/Makefile: i2c-viai2c-common.o is added to multiple modules: i2c-wmt i2c-zhaoxin
The other problems with this include the incorrect use of a __weak function
when both are built-in, and the fact that the "common" module is sprinked
with 'if (i2c->plat == ...)' checks that have knowledge about the differences
between the drivers using it.
Avoid the link time warning by making the common driver a proper module
with MODULE_LICENCE()/MODULE_AUTHOR() tags, and remove the __weak function
by slightly rearranging the code.
This adds a little more duplication between the two main drivers, but
those versions get more readable in the process.
Fixes: a06b80e83011 ("i2c: add zhaoxin i2c controller driver")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/i2c/busses/Makefile | 6 +-
drivers/i2c/busses/i2c-viai2c-common.c | 71 ++-------------
drivers/i2c/busses/i2c-viai2c-common.h | 2 +-
drivers/i2c/busses/i2c-viai2c-wmt.c | 37 ++++++++
drivers/i2c/busses/i2c-viai2c-zhaoxin.c | 113 +++++++++++++++++++-----
5 files changed, 140 insertions(+), 89 deletions(-)
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 3d65934f5eb4..78d0561339e5 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -29,8 +29,7 @@ obj-$(CONFIG_I2C_SIS630) += i2c-sis630.o
obj-$(CONFIG_I2C_SIS96X) += i2c-sis96x.o
obj-$(CONFIG_I2C_VIA) += i2c-via.o
obj-$(CONFIG_I2C_VIAPRO) += i2c-viapro.o
-i2c-zhaoxin-objs := i2c-viai2c-zhaoxin.o i2c-viai2c-common.o
-obj-$(CONFIG_I2C_ZHAOXIN) += i2c-zhaoxin.o
+obj-$(CONFIG_I2C_ZHAOXIN) += i2c-viai2c-zhaoxin.o i2c-viai2c-common.o
# Mac SMBus host controller drivers
obj-$(CONFIG_I2C_HYDRA) += i2c-hydra.o
@@ -120,8 +119,7 @@ obj-$(CONFIG_I2C_TEGRA_BPMP) += i2c-tegra-bpmp.o
obj-$(CONFIG_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_I2C_UNIPHIER_F) += i2c-uniphier-f.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
-i2c-wmt-objs := i2c-viai2c-wmt.o i2c-viai2c-common.o
-obj-$(CONFIG_I2C_WMT) += i2c-wmt.o
+obj-$(CONFIG_I2C_WMT) += i2c-viai2c-wmt.o i2c-viai2c-common.o
i2c-octeon-objs := i2c-octeon-core.o i2c-octeon-platdrv.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
i2c-thunderx-objs := i2c-octeon-core.o i2c-thunderx-pcidrv.o
diff --git a/drivers/i2c/busses/i2c-viai2c-common.c b/drivers/i2c/busses/i2c-viai2c-common.c
index 1844d13f1f79..162b31306cba 100644
--- a/drivers/i2c/busses/i2c-viai2c-common.c
+++ b/drivers/i2c/busses/i2c-viai2c-common.c
@@ -17,6 +17,7 @@ int viai2c_wait_bus_not_busy(struct viai2c *i2c)
return 0;
}
+EXPORT_SYMBOL_GPL(viai2c_wait_bus_not_busy);
static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last)
{
@@ -121,6 +122,7 @@ int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
return (ret < 0) ? ret : i;
}
+EXPORT_SYMBOL_GPL(viai2c_xfer);
/*
* Main process of the byte mode xfer
@@ -130,7 +132,7 @@ int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
* 0: there is still data that needs to be transferred
* -EIO: error occurred
*/
-static int viai2c_irq_xfer(struct viai2c *i2c)
+int viai2c_irq_xfer(struct viai2c *i2c)
{
u16 val;
struct i2c_msg *msg = i2c->msg;
@@ -171,51 +173,11 @@ static int viai2c_irq_xfer(struct viai2c *i2c)
return i2c->xfered_len == msg->len;
}
-
-int __weak viai2c_fifo_irq_xfer(struct viai2c *i2c, bool irq)
-{
- return 0;
-}
-
-static irqreturn_t viai2c_isr(int irq, void *data)
-{
- struct viai2c *i2c = data;
- u8 status;
-
- /* save the status and write-clear it */
- status = readw(i2c->base + VIAI2C_REG_ISR);
- if (!status && i2c->platform == VIAI2C_PLAT_ZHAOXIN)
- return IRQ_NONE;
-
- writew(status, i2c->base + VIAI2C_REG_ISR);
-
- i2c->ret = 0;
- if (status & VIAI2C_ISR_NACK_ADDR)
- i2c->ret = -EIO;
-
- if (i2c->platform == VIAI2C_PLAT_WMT && (status & VIAI2C_ISR_SCL_TIMEOUT))
- i2c->ret = -ETIMEDOUT;
-
- if (!i2c->ret) {
- if (i2c->mode == VIAI2C_BYTE_MODE)
- i2c->ret = viai2c_irq_xfer(i2c);
- else
- i2c->ret = viai2c_fifo_irq_xfer(i2c, true);
- }
-
- /* All the data has been successfully transferred or error occurred */
- if (i2c->ret)
- complete(&i2c->complete);
-
- return IRQ_HANDLED;
-}
+EXPORT_SYMBOL_GPL(viai2c_irq_xfer);
int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat)
{
- int err;
- int irq_flags;
struct viai2c *i2c;
- struct device_node *np = pdev->dev.of_node;
i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
if (!i2c)
@@ -225,28 +187,8 @@ int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat)
if (IS_ERR(i2c->base))
return PTR_ERR(i2c->base);
- if (plat == VIAI2C_PLAT_WMT) {
- irq_flags = 0;
- i2c->irq = irq_of_parse_and_map(np, 0);
- if (!i2c->irq)
- return -EINVAL;
- } else if (plat == VIAI2C_PLAT_ZHAOXIN) {
- irq_flags = IRQF_SHARED;
- i2c->irq = platform_get_irq(pdev, 0);
- if (i2c->irq < 0)
- return i2c->irq;
- } else {
- return dev_err_probe(&pdev->dev, -EINVAL, "wrong platform type\n");
- }
-
i2c->platform = plat;
- err = devm_request_irq(&pdev->dev, i2c->irq, viai2c_isr,
- irq_flags, pdev->name, i2c);
- if (err)
- return dev_err_probe(&pdev->dev, err,
- "failed to request irq %i\n", i2c->irq);
-
i2c->dev = &pdev->dev;
init_completion(&i2c->complete);
platform_set_drvdata(pdev, i2c);
@@ -254,3 +196,8 @@ int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat)
*pi2c = i2c;
return 0;
}
+EXPORT_SYMBOL_GPL(viai2c_init);
+
+MODULE_DESCRIPTION("Via/Wondermedia/Zhaoxin I2C master-mode bus adapter");
+MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-viai2c-common.h b/drivers/i2c/busses/i2c-viai2c-common.h
index 81e827c54434..00f17733223c 100644
--- a/drivers/i2c/busses/i2c-viai2c-common.h
+++ b/drivers/i2c/busses/i2c-viai2c-common.h
@@ -80,6 +80,6 @@ struct viai2c {
int viai2c_wait_bus_not_busy(struct viai2c *i2c);
int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num);
int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat);
-int viai2c_fifo_irq_xfer(struct viai2c *i2c, bool irq);
+int viai2c_irq_xfer(struct viai2c *i2c);
#endif
diff --git a/drivers/i2c/busses/i2c-viai2c-wmt.c b/drivers/i2c/busses/i2c-viai2c-wmt.c
index e1988f946026..b3ab9633015a 100644
--- a/drivers/i2c/busses/i2c-viai2c-wmt.c
+++ b/drivers/i2c/busses/i2c-viai2c-wmt.c
@@ -72,6 +72,33 @@ static int wmt_i2c_reset_hardware(struct viai2c *i2c)
return 0;
}
+static irqreturn_t wmt_i2c_isr(int irq, void *data)
+{
+ struct viai2c *i2c = data;
+ u8 status;
+
+ /* save the status and write-clear it */
+ status = readw(i2c->base + VIAI2C_REG_ISR);
+ writew(status, i2c->base + VIAI2C_REG_ISR);
+
+ i2c->ret = 0;
+ if (status & VIAI2C_ISR_NACK_ADDR)
+ i2c->ret = -EIO;
+
+ if (status & VIAI2C_ISR_SCL_TIMEOUT)
+ i2c->ret = -ETIMEDOUT;
+
+ if (!i2c->ret)
+ i2c->ret = viai2c_irq_xfer(i2c);
+
+ /* All the data has been successfully transferred or error occurred */
+ if (i2c->ret)
+ complete(&i2c->complete);
+
+ return IRQ_HANDLED;
+}
+
+
static int wmt_i2c_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -84,6 +111,16 @@ static int wmt_i2c_probe(struct platform_device *pdev)
if (err)
return err;
+ i2c->irq = platform_get_irq(pdev, 0);
+ if (i2c->irq < 0)
+ return i2c->irq;
+
+ err = devm_request_irq(&pdev->dev, i2c->irq, wmt_i2c_isr,
+ 0, pdev->name, i2c);
+ if (err)
+ return dev_err_probe(&pdev->dev, err,
+ "failed to request irq %i\n", i2c->irq);
+
i2c->clk = of_clk_get(np, 0);
if (IS_ERR(i2c->clk)) {
dev_err(&pdev->dev, "unable to request clock\n");
diff --git a/drivers/i2c/busses/i2c-viai2c-zhaoxin.c b/drivers/i2c/busses/i2c-viai2c-zhaoxin.c
index 7e3ac2a3e1fd..dbcb904c74f0 100644
--- a/drivers/i2c/busses/i2c-viai2c-zhaoxin.c
+++ b/drivers/i2c/busses/i2c-viai2c-zhaoxin.c
@@ -49,8 +49,7 @@ struct viai2c_zhaoxin {
u16 xfer_len;
};
-/* 'irq == true' means in interrupt context */
-int viai2c_fifo_irq_xfer(struct viai2c *i2c, bool irq)
+static int viai2c_fifo_xfer(struct viai2c *i2c)
{
u16 i;
u8 tmp;
@@ -59,17 +58,6 @@ int viai2c_fifo_irq_xfer(struct viai2c *i2c, bool irq)
bool read = !!(msg->flags & I2C_M_RD);
struct viai2c_zhaoxin *priv = i2c->pltfm_priv;
- if (irq) {
- /* get the received data */
- if (read)
- for (i = 0; i < priv->xfer_len; i++)
- msg->buf[i2c->xfered_len + i] = ioread8(base + ZXI2C_REG_HRDR);
-
- i2c->xfered_len += priv->xfer_len;
- if (i2c->xfered_len == msg->len)
- return 1;
- }
-
/* reset fifo buffer */
tmp = ioread8(base + ZXI2C_REG_HCR);
iowrite8(tmp | ZXI2C_HCR_RST_FIFO, base + ZXI2C_REG_HCR);
@@ -92,18 +80,59 @@ int viai2c_fifo_irq_xfer(struct viai2c *i2c, bool irq)
iowrite8(tmp, base + VIAI2C_REG_CR);
}
- if (irq) {
- /* continue transmission */
- tmp = ioread8(base + VIAI2C_REG_CR);
- iowrite8(tmp |= VIAI2C_CR_CPU_RDY, base + VIAI2C_REG_CR);
+ u16 tcr_val = i2c->tcr;
+
+ /* start transmission */
+ tcr_val |= read ? VIAI2C_TCR_READ : 0;
+ writew(tcr_val | msg->addr, base + VIAI2C_REG_TCR);
+
+ return 0;
+}
+
+static int viai2c_fifo_irq_xfer(struct viai2c *i2c)
+{
+ u16 i;
+ u8 tmp;
+ struct i2c_msg *msg = i2c->msg;
+ void __iomem *base = i2c->base;
+ bool read = !!(msg->flags & I2C_M_RD);
+ struct viai2c_zhaoxin *priv = i2c->pltfm_priv;
+
+ /* get the received data */
+ if (read)
+ for (i = 0; i < priv->xfer_len; i++)
+ msg->buf[i2c->xfered_len + i] = ioread8(base + ZXI2C_REG_HRDR);
+
+ i2c->xfered_len += priv->xfer_len;
+ if (i2c->xfered_len == msg->len)
+ return 1;
+
+ /* reset fifo buffer */
+ tmp = ioread8(base + ZXI2C_REG_HCR);
+ iowrite8(tmp | ZXI2C_HCR_RST_FIFO, base + ZXI2C_REG_HCR);
+
+ /* set xfer len */
+ priv->xfer_len = min_t(u16, msg->len - i2c->xfered_len, ZXI2C_FIFO_SIZE);
+ if (read) {
+ iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HRLR);
} else {
- u16 tcr_val = i2c->tcr;
+ iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HTLR);
+ /* set write data */
+ for (i = 0; i < priv->xfer_len; i++)
+ iowrite8(msg->buf[i2c->xfered_len + i], base + ZXI2C_REG_HTDR);
+ }
- /* start transmission */
- tcr_val |= read ? VIAI2C_TCR_READ : 0;
- writew(tcr_val | msg->addr, base + VIAI2C_REG_TCR);
+ /* prepare to stop transmission */
+ if (priv->hrv && msg->len == (i2c->xfered_len + priv->xfer_len)) {
+ tmp = ioread8(base + VIAI2C_REG_CR);
+ tmp |= read ? VIAI2C_CR_RX_END : VIAI2C_CR_TX_END;
+ iowrite8(tmp, base + VIAI2C_REG_CR);
}
+ /* continue transmission */
+ tmp = ioread8(base + VIAI2C_REG_CR);
+ iowrite8(tmp |= VIAI2C_CR_CPU_RDY, base + VIAI2C_REG_CR);
+
return 0;
}
@@ -135,7 +164,7 @@ static int zxi2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int
priv->xfer_len = 0;
i2c->xfered_len = 0;
- viai2c_fifo_irq_xfer(i2c, 0);
+ viai2c_fifo_xfer(i2c);
if (!wait_for_completion_timeout(&i2c->complete, VIAI2C_TIMEOUT))
return -ETIMEDOUT;
@@ -228,6 +257,36 @@ static void zxi2c_get_bus_speed(struct viai2c *i2c)
dev_info(i2c->dev, "speed mode is %s\n", i2c_freq_mode_string(params[0]));
}
+static irqreturn_t zxi2c_isr(int irq, void *data)
+{
+ struct viai2c *i2c = data;
+ u8 status;
+
+ /* save the status and write-clear it */
+ status = readw(i2c->base + VIAI2C_REG_ISR);
+ if (!status)
+ return IRQ_NONE;
+
+ writew(status, i2c->base + VIAI2C_REG_ISR);
+
+ i2c->ret = 0;
+ if (status & VIAI2C_ISR_NACK_ADDR)
+ i2c->ret = -EIO;
+
+ if (!i2c->ret) {
+ if (i2c->mode == VIAI2C_BYTE_MODE)
+ i2c->ret = viai2c_irq_xfer(i2c);
+ else
+ i2c->ret = viai2c_fifo_irq_xfer(i2c);
+ }
+
+ /* All the data has been successfully transferred or error occurred */
+ if (i2c->ret)
+ complete(&i2c->complete);
+
+ return IRQ_HANDLED;
+}
+
static int zxi2c_probe(struct platform_device *pdev)
{
int error;
@@ -239,6 +298,16 @@ static int zxi2c_probe(struct platform_device *pdev)
if (error)
return error;
+ i2c->irq = platform_get_irq(pdev, 0);
+ if (i2c->irq < 0)
+ return i2c->irq;
+
+ error = devm_request_irq(&pdev->dev, i2c->irq, zxi2c_isr,
+ IRQF_SHARED, pdev->name, i2c);
+ if (error)
+ return dev_err_probe(&pdev->dev, error,
+ "failed to request irq %i\n", i2c->irq);
+
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
--
2.39.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 3%]
* [PATCH v6 2/2] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support
@ 2024-05-28 2:59 6% ` Richard Zhu
2024-05-28 14:52 0% ` Frank Li
0 siblings, 1 reply; 200+ results
From: Richard Zhu @ 2024-05-28 2:59 UTC (permalink / raw)
To: conor, vkoul, kishon, robh+dt, krzysztof.kozlowski+dt, frank.li,
conor+dt
Cc: hongxing.zhu, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, kernel, imx
Add i.MX8QM HSIO PHY driver support.
i.MX8QM HSIO has three lane PHY instances, and can be bound to the
following controllers in the different use cases listed in below table.
- two lanes capable PCIEA controller.
- one lane PCIEB controller.
- AHCI SATA controller.
i.MX8QM HSIO PHYs support the following use cases.
+----------------------------------------------------+
| | Lane0| Lane1| Lane2|
|-------------------------------|------|------|------|
| use case 1: PCIEAX2SATA | PCIEA| PCIEA| SATA |
|-------------------------------|------|------|------|
| use case 2: PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB|
|-------------------------------|------|------|------|
| use case 3: PCIEAPCIEBSATA | PCIEA| PCIEB| SATA |
+----------------------------------------------------+
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/phy/freescale/Kconfig | 8 +
drivers/phy/freescale/Makefile | 1 +
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 612 ++++++++++++++++++++
3 files changed, 621 insertions(+)
create mode 100644 drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index 853958fb2c06..c9ee48aeea9e 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -35,6 +35,14 @@ config PHY_FSL_IMX8M_PCIE
Enable this to add support for the PCIE PHY as found on
i.MX8M family of SOCs.
+config PHY_FSL_IMX8QM_HSIO
+ tristate "Freescale i.MX8QM HSIO PHY"
+ depends on OF && HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Enable this to add support for the HSIO PHY as found on
+ i.MX8QM family of SOCs.
+
endif
config PHY_FSL_LYNX_28G
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index cedb328bc4d2..b56b4d5c18ea 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
+obj-$(CONFIG_PHY_FSL_IMX8QM_HSIO) += phy-fsl-imx8qm-hsio.o
obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
new file mode 100644
index 000000000000..73e0c50fcdae
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
@@ -0,0 +1,612 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pci_regs.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/pcie.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#define MAX_NUM_LANE 3
+#define LANE_NUM_CLKS 5
+
+/* Parameters for the waiting for PCIe PHY PLL to lock */
+#define PHY_INIT_WAIT_USLEEP_MAX 10
+#define PHY_INIT_WAIT_TIMEOUT (1000 * PHY_INIT_WAIT_USLEEP_MAX)
+
+/* i.MX8Q HSIO registers */
+#define HSIO_CTRL0 0x0
+#define HSIO_APB_RSTN_0 BIT(0)
+#define HSIO_APB_RSTN_1 BIT(1)
+#define HSIO_PIPE_RSTN_0_MASK GENMASK(25, 24)
+#define HSIO_PIPE_RSTN_1_MASK GENMASK(27, 26)
+#define HSIO_MODE_MASK GENMASK(20, 17)
+#define HSIO_MODE_PCIE 0x0
+#define HSIO_MODE_SATA 0x4
+#define HSIO_DEVICE_TYPE_MASK GENMASK(27, 24)
+#define HSIO_EPCS_TXDEEMP BIT(5)
+#define HSIO_EPCS_TXDEEMP_SEL BIT(6)
+#define HSIO_EPCS_PHYRESET_N BIT(7)
+#define HSIO_RESET_N BIT(12)
+
+#define HSIO_IOB_RXENA BIT(0)
+#define HSIO_IOB_TXENA BIT(1)
+#define HSIO_IOB_A_0_TXOE BIT(2)
+#define HSIO_IOB_A_0_M1M0_2 BIT(4)
+#define HSIO_IOB_A_0_M1M0_MASK GENMASK(4, 3)
+#define HSIO_PHYX1_EPCS_SEL BIT(12)
+#define HSIO_PCIE_AB_SELECT BIT(13)
+
+#define HSIO_PHY_STS0 0x4
+#define HSIO_LANE0_TX_PLL_LOCK BIT(4)
+#define HSIO_LANE1_TX_PLL_LOCK BIT(12)
+
+#define HSIO_CTRL2 0x8
+#define HSIO_LTSSM_ENABLE BIT(4)
+#define HSIO_BUTTON_RST_N BIT(21)
+#define HSIO_PERST_N BIT(22)
+#define HSIO_POWER_UP_RST_N BIT(23)
+
+#define HSIO_PCIE_STS0 0xc
+#define HSIO_PM_REQ_CORE_RST BIT(19)
+
+#define HSIO_REG48_PMA_STATUS 0x30
+#define HSIO_REG48_PMA_RDY BIT(7)
+
+struct imx_hsio_drvdata {
+ int lane_num;
+};
+
+struct imx_hsio_lane {
+ u32 ctrl_index;
+ u32 ctrl_off;
+ u32 idx;
+ u32 phy_off;
+ u32 phy_type;
+ const char * const *clk_names;
+ struct clk_bulk_data clks[LANE_NUM_CLKS];
+ struct imx_hsio_priv *priv;
+ struct phy *phy;
+ enum phy_mode phy_mode;
+};
+
+struct imx_hsio_priv {
+ void __iomem *base;
+ struct device *dev;
+ struct mutex lock;
+ const char *hsio_cfg;
+ const char *refclk_pad;
+ u32 open_cnt;
+ struct regmap *phy;
+ struct regmap *ctrl;
+ struct regmap *misc;
+ const struct imx_hsio_drvdata *drvdata;
+ struct imx_hsio_lane lane[MAX_NUM_LANE];
+};
+
+static const char * const lan0_pcie_clks[] = {"apb_pclk0", "pclk0", "ctl0_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan1_pciea_clks[] = {"apb_pclk1", "pclk1", "ctl0_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan1_pcieb_clks[] = {"apb_pclk1", "pclk1", "ctl1_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan2_pcieb_clks[] = {"apb_pclk2", "pclk2", "ctl1_crr",
+ "phy1_crr", "misc_crr"};
+static const char * const lan2_sata_clks[] = {"pclk2", "epcs_tx", "epcs_rx",
+ "phy1_crr", "misc_crr"};
+
+static const struct regmap_config regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int imx_hsio_init(struct phy *phy)
+{
+ int ret, i;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+ struct device *dev = priv->dev;
+
+ /* Assign clocks refer to different modes */
+ switch (lane->phy_type) {
+ case PHY_TYPE_PCIE:
+ lane->phy_mode = PHY_MODE_PCIE;
+ if (lane->ctrl_index == 0) { /* PCIEA */
+ lane->ctrl_off = 0;
+ lane->phy_off = 0;
+
+ for (i = 0; i < LANE_NUM_CLKS; i++) {
+ if (lane->idx == 0)
+ lane->clks[i].id = lan0_pcie_clks[i];
+ else
+ lane->clks[i].id = lan1_pciea_clks[i];
+ }
+ } else { /* PCIEB */
+ if (lane->idx == 0) { /* i.MX8QXP */
+ lane->ctrl_off = 0;
+ lane->phy_off = 0;
+ } else {
+ /*
+ * On i.MX8QM, only second or third lane can be
+ * bound to PCIEB.
+ */
+ lane->ctrl_off = SZ_64K;
+ if (lane->idx == 1)
+ lane->phy_off = 0;
+ else /* the third lane is bound to PCIEB */
+ lane->phy_off = SZ_64K;
+ }
+
+ for (i = 0; i < LANE_NUM_CLKS; i++) {
+ if (lane->idx == 1)
+ lane->clks[i].id = lan1_pcieb_clks[i];
+ else if (lane->idx == 2)
+ lane->clks[i].id = lan2_pcieb_clks[i];
+ else /* i.MX8QXP only has PCIEB, idx is 0 */
+ lane->clks[i].id = lan0_pcie_clks[i];
+ }
+ }
+ break;
+ case PHY_TYPE_SATA:
+ /* On i.MX8QM, only the third lane can be bound to SATA */
+ lane->phy_mode = PHY_MODE_SATA;
+ lane->ctrl_off = SZ_128K;
+ lane->phy_off = SZ_64K;
+
+ for (i = 0; i < LANE_NUM_CLKS; i++)
+ lane->clks[i].id = lan2_sata_clks[i];
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Fetch clocks and enable them */
+ ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, lane->clks);
+ if (ret)
+ return ret;
+ ret = clk_bulk_prepare_enable(LANE_NUM_CLKS, lane->clks);
+ if (ret)
+ return ret;
+
+ /* allow the clocks to stabilize */
+ usleep_range(200, 500);
+ return 0;
+}
+
+static int imx_hsio_exit(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+
+ clk_bulk_disable_unprepare(LANE_NUM_CLKS, lane->clks);
+
+ return 0;
+}
+
+static void imx_hsio_pcie_phy_resets(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+
+ if (lane->idx == 1) {
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_1);
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_1_MASK);
+ } else {
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_0);
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_0_MASK);
+ }
+}
+
+static void imx_hsio_sata_phy_resets(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ /* clear PHY RST, then set it */
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_PHYRESET_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_PHYRESET_N);
+
+ /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
+ udelay(1);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_RESET_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
+}
+
+static void imx_hsio_configure_clk_pad(struct phy *phy)
+{
+ bool pll = false;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (strncmp(priv->refclk_pad, "output", 6) == 0) {
+ pll = true;
+ regmap_update_bits(priv->misc, HSIO_CTRL0,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_2);
+ } else {
+ regmap_update_bits(priv->misc, HSIO_CTRL0,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
+ 0);
+ }
+
+ regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_RXENA,
+ pll ? 0 : HSIO_IOB_RXENA);
+ regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_TXENA,
+ pll ? HSIO_IOB_TXENA : 0);
+}
+
+static void imx_hsio_pre_set(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (strncmp(priv->hsio_cfg, "pcieax2pcieb", 10) == 0) {
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
+ } else if (strncmp(priv->hsio_cfg, "pcieax2sata", 9) == 0) {
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
+ } else if (strncmp(priv->hsio_cfg, "pcieapciebsata", 12) == 0) {
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
+ }
+
+ imx_hsio_configure_clk_pad(phy);
+}
+
+static int imx_hsio_pcie_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, addr, cond;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ imx_hsio_pcie_phy_resets(phy);
+
+ /* Toggle apb_pclk to make sure PM_REQ_CORE_RST is cleared. */
+ clk_disable_unprepare(lane->clks[0].clk);
+ mdelay(1);
+ ret = clk_prepare_enable(lane->clks[0].clk);
+ if (ret) {
+ dev_err(priv->dev, "unable to enable phy apb_pclk\n");
+ return ret;
+ }
+
+ addr = lane->ctrl_off + HSIO_PCIE_STS0;
+ cond = HSIO_PM_REQ_CORE_RST;
+ ret = regmap_read_poll_timeout(priv->ctrl, addr, val,
+ (val & cond) == 0,
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT);
+ if (ret)
+ dev_err(priv->dev, "HSIO_PM_REQ_CORE_RST is set\n");
+ return ret;
+}
+
+static int imx_hsio_sata_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, cond;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0, HSIO_APB_RSTN_0);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP_SEL);
+
+ imx_hsio_sata_phy_resets(phy);
+
+ cond = HSIO_REG48_PMA_RDY;
+ ret = read_poll_timeout(readb, val, ((val & cond) == cond),
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT, false,
+ priv->base + HSIO_REG48_PMA_STATUS);
+ if (ret)
+ dev_err(priv->dev, "PHY calibration is timeout\n");
+ else
+ dev_dbg(priv->dev, "PHY calibration is done\n");
+
+ return ret;
+}
+
+static int imx_hsio_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, cond;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ scoped_guard(mutex, &priv->lock) {
+ if (!priv->open_cnt)
+ imx_hsio_pre_set(phy);
+ priv->open_cnt++;
+ }
+
+ if (lane->phy_mode == PHY_MODE_PCIE)
+ ret = imx_hsio_pcie_power_on(phy);
+ else /* SATA */
+ ret = imx_hsio_sata_power_on(phy);
+ if (ret)
+ return ret;
+
+ /* Polling to check the PHY is ready or not. */
+ if (lane->idx == 1)
+ cond = HSIO_LANE1_TX_PLL_LOCK;
+ else
+ /*
+ * Except the phy_off, the bit-offset of lane2 is same to lane0.
+ * Merge the lane0 and lane2 bit-operations together.
+ */
+ cond = HSIO_LANE0_TX_PLL_LOCK;
+
+ ret = regmap_read_poll_timeout(priv->phy, lane->phy_off + HSIO_PHY_STS0,
+ val, ((val & cond) == cond),
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT);
+ if (ret) {
+ dev_err(priv->dev, "IMX8Q PHY%d PLL lock timeout\n", lane->idx);
+ return ret;
+ }
+ dev_dbg(priv->dev, "IMX8Q PHY%d PLL is locked\n", lane->idx);
+
+ return ret;
+}
+
+static int imx_hsio_power_off(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ scoped_guard(mutex, &priv->lock) {
+ priv->open_cnt--;
+ if (priv->open_cnt == 0) {
+ regmap_clear_bits(priv->misc, HSIO_CTRL0,
+ HSIO_PCIE_AB_SELECT);
+ regmap_clear_bits(priv->misc, HSIO_CTRL0,
+ HSIO_PHYX1_EPCS_SEL);
+
+ if (lane->phy_mode == PHY_MODE_PCIE) {
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+ } else {
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP_SEL);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL0,
+ HSIO_RESET_N);
+ }
+
+ if (lane->idx == 1) {
+ regmap_clear_bits(priv->phy,
+ lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_1);
+ regmap_clear_bits(priv->phy,
+ lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_1_MASK);
+ } else {
+ /*
+ * Except the phy_off, the bit-offset of lane2 is same
+ * to lane0. Merge the lane0 and lane2 bit-operations
+ * together.
+ */
+ regmap_clear_bits(priv->phy,
+ lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_0);
+ regmap_clear_bits(priv->phy,
+ lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_0_MASK);
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int imx_hsio_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ u32 val;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (lane->phy_mode != mode)
+ return -EINVAL;
+
+ val = (mode == PHY_MODE_PCIE) ? HSIO_MODE_PCIE : HSIO_MODE_SATA;
+ val = FIELD_PREP(HSIO_MODE_MASK, val);
+ regmap_update_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_MODE_MASK, val);
+
+ switch (submode) {
+ case PHY_MODE_PCIE_RC:
+ val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
+ break;
+ case PHY_MODE_PCIE_EP:
+ val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ENDPOINT);
+ break;
+ default: /* Support only PCIe EP and RC now. */
+ return 0;
+ }
+ if (submode)
+ regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_DEVICE_TYPE_MASK, val);
+
+ return 0;
+}
+
+static int imx_hsio_set_speed(struct phy *phy, int speed)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_LTSSM_ENABLE,
+ speed ? HSIO_LTSSM_ENABLE : 0);
+ return 0;
+}
+
+static const struct phy_ops imx_hsio_ops = {
+ .init = imx_hsio_init,
+ .exit = imx_hsio_exit,
+ .power_on = imx_hsio_power_on,
+ .power_off = imx_hsio_power_off,
+ .set_mode = imx_hsio_set_mode,
+ .set_speed = imx_hsio_set_speed,
+ .owner = THIS_MODULE,
+};
+
+static const struct imx_hsio_drvdata imx8qxp_hsio_drvdata = {
+ .lane_num = 0x1,
+};
+
+static const struct imx_hsio_drvdata imx_hsio_drvdata = {
+ .lane_num = 0x3,
+};
+
+static const struct of_device_id imx_hsio_of_match[] = {
+ {.compatible = "fsl,imx8qm-hsio", .data = &imx_hsio_drvdata},
+ {.compatible = "fsl,imx8qxp-hsio", .data = &imx8qxp_hsio_drvdata},
+ { },
+};
+MODULE_DEVICE_TABLE(of, imx_hsio_of_match);
+
+static struct phy *imx_hsio_xlate(struct device *dev,
+ const struct of_phandle_args *args)
+{
+ struct imx_hsio_priv *priv = dev_get_drvdata(dev);
+ int idx = args->args[0];
+ int phy_type = args->args[1];
+ int ctrl_index = args->args[2];
+
+ if (idx < 0 || idx >= priv->drvdata->lane_num)
+ return ERR_PTR(-EINVAL);
+ priv->lane[idx].idx = idx;
+ priv->lane[idx].phy_type = phy_type;
+ priv->lane[idx].ctrl_index = ctrl_index;
+
+ return priv->lane[idx].phy;
+}
+
+static int imx_hsio_probe(struct platform_device *pdev)
+{
+ int i;
+ void __iomem *off;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct imx_hsio_priv *priv;
+ struct phy_provider *provider;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ priv->dev = &pdev->dev;
+ priv->drvdata = of_device_get_match_data(dev);
+
+ /* Get HSIO configuration mode */
+ if (of_property_read_string(np, "fsl,hsio-cfg", &priv->hsio_cfg))
+ priv->hsio_cfg = "pcieapciebsata";
+ /* Get PHY refclk pad mode */
+ if (of_property_read_string(np, "fsl,refclk-pad-mode",
+ &priv->refclk_pad))
+ priv->refclk_pad = NULL;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ off = devm_platform_ioremap_resource_byname(pdev, "phy");
+ priv->phy = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->phy))
+ return dev_err_probe(dev, PTR_ERR(priv->phy),
+ "unable to find phy csr registers\n");
+
+ off = devm_platform_ioremap_resource_byname(pdev, "ctrl");
+ priv->ctrl = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->ctrl))
+ return dev_err_probe(dev, PTR_ERR(priv->ctrl),
+ "unable to find ctrl csr registers\n");
+
+ off = devm_platform_ioremap_resource_byname(pdev, "misc");
+ priv->misc = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->misc))
+ return dev_err_probe(dev, PTR_ERR(priv->misc),
+ "unable to find misc csr registers\n");
+
+ for (i = 0; i < priv->drvdata->lane_num; i++) {
+ struct imx_hsio_lane *lane = &priv->lane[i];
+ struct phy *phy;
+
+ memset(lane, 0, sizeof(*lane));
+
+ phy = devm_phy_create(&pdev->dev, NULL, &imx_hsio_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ lane->priv = priv;
+ lane->phy = phy;
+ lane->idx = i;
+ phy_set_drvdata(phy, lane);
+ }
+
+ dev_set_drvdata(dev, priv);
+ dev_set_drvdata(&pdev->dev, priv);
+
+ provider = devm_of_phy_provider_register(&pdev->dev, imx_hsio_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver imx_hsio_driver = {
+ .probe = imx_hsio_probe,
+ .driver = {
+ .name = "imx8qm-hsio-phy",
+ .of_match_table = imx_hsio_of_match,
+ }
+};
+module_platform_driver(imx_hsio_driver);
+
+MODULE_DESCRIPTION("FSL IMX8QM HSIO SERDES PHY driver");
+MODULE_LICENSE("GPL");
--
2.37.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 6%]
* [PATCH v2 18/19] mfd: Add support for LAN966x PCI device
@ 2024-05-27 16:14 5% ` Herve Codina
0 siblings, 0 replies; 200+ results
From: Herve Codina @ 2024-05-27 16:14 UTC (permalink / raw)
To: Simon Horman, Sai Krishna Gajula, Herve Codina, Thomas Gleixner,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Lee Jones,
Arnd Bergmann, Horatiu Vultur, UNGLinuxDriver, Andrew Lunn,
Heiner Kallweit, Russell King, Saravana Kannan, Bjorn Helgaas,
Philipp Zabel, Lars Povlsen, Steen Hegelund, Daniel Machon,
Alexandre Belloni
Cc: linux-kernel, devicetree, netdev, linux-pci, linux-arm-kernel,
Allan Nielsen, Steen Hegelund, Luca Ceresoli, Thomas Petazzoni
Add a PCI driver that handles the LAN966x PCI device using a device-tree
overlay. This overlay is applied to the PCI device DT node and allows to
describe components that are present in the device.
The memory from the device-tree is remapped to the BAR memory thanks to
"ranges" properties computed at runtime by the PCI core during the PCI
enumeration.
The PCI device itself acts as an interrupt controller and is used as the
parent of the internal LAN966x interrupt controller to route the
interrupts to the assigned PCI INTx interrupt.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
drivers/mfd/Kconfig | 24 ++++
drivers/mfd/Makefile | 4 +
drivers/mfd/lan966x_pci.c | 229 +++++++++++++++++++++++++++++++++++
drivers/mfd/lan966x_pci.dtso | 167 +++++++++++++++++++++++++
drivers/pci/quirks.c | 1 +
5 files changed, 425 insertions(+)
create mode 100644 drivers/mfd/lan966x_pci.c
create mode 100644 drivers/mfd/lan966x_pci.dtso
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 266b4f54af60..15db144bc09b 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -144,6 +144,30 @@ config MFD_ATMEL_FLEXCOM
by the probe function of this MFD driver according to a device tree
property.
+config MFD_LAN966X_PCI
+ tristate "Microchip LAN966x PCIe Support"
+ depends on PCI
+ select OF
+ select OF_OVERLAY
+ select IRQ_DOMAIN
+ help
+ This enables the support for the LAN966x PCIe device.
+ This is used to drive the LAN966x PCIe device from the host system
+ to which it is connected.
+
+ This driver uses an overlay to load other drivers to support for
+ LAN966x internal components.
+ Even if this driver does not depend on these other drivers, in order
+ to have a fully functional board, the following drivers are needed:
+ - fixed-clock (COMMON_CLK)
+ - lan966x-oic (LAN966X_OIC)
+ - lan966x-cpu-syscon (MFD_SYSCON)
+ - lan966x-switch-reset (RESET_MCHP_SPARX5)
+ - lan966x-pinctrl (PINCTRL_OCELOT)
+ - lan966x-serdes (PHY_LAN966X_SERDES)
+ - lan966x-miim (MDIO_MSCC_MIIM)
+ - lan966x-switch (LAN966X_SWITCH)
+
config MFD_ATMEL_HLCDC
tristate "Atmel HLCDC (High-end LCD Controller)"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index c66f07edcd0e..165a9674ff48 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -284,3 +284,7 @@ rsmu-i2c-objs := rsmu_core.o rsmu_i2c.o
rsmu-spi-objs := rsmu_core.o rsmu_spi.o
obj-$(CONFIG_MFD_RSMU_I2C) += rsmu-i2c.o
obj-$(CONFIG_MFD_RSMU_SPI) += rsmu-spi.o
+
+lan966x-pci-objs := lan966x_pci.o
+lan966x-pci-objs += lan966x_pci.dtbo.o
+obj-$(CONFIG_MFD_LAN966X_PCI) += lan966x-pci.o
diff --git a/drivers/mfd/lan966x_pci.c b/drivers/mfd/lan966x_pci.c
new file mode 100644
index 000000000000..a0a59860928f
--- /dev/null
+++ b/drivers/mfd/lan966x_pci.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Microchip LAN966x PCI driver
+ *
+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
+ *
+ * Authors:
+ * Clément Léger <clement.leger@bootlin.com>
+ * Hervé Codina <herve.codina@bootlin.com>
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+
+/* Embedded dtbo symbols created by cmd_wrap_S_dtb in scripts/Makefile.lib */
+extern char __dtbo_lan966x_pci_begin[];
+extern char __dtbo_lan966x_pci_end[];
+
+struct pci_dev_intr_ctrl {
+ struct pci_dev *pci_dev;
+ struct irq_domain *irq_domain;
+ int irq;
+};
+
+static int pci_dev_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw)
+{
+ irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_simple_irq);
+ return 0;
+}
+
+static const struct irq_domain_ops pci_dev_irq_domain_ops = {
+ .map = pci_dev_irq_domain_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static irqreturn_t pci_dev_irq_handler(int irq, void *data)
+{
+ struct pci_dev_intr_ctrl *intr_ctrl = data;
+ int ret;
+
+ ret = generic_handle_domain_irq(intr_ctrl->irq_domain, 0);
+ return ret ? IRQ_NONE : IRQ_HANDLED;
+}
+
+static struct pci_dev_intr_ctrl *pci_dev_create_intr_ctrl(struct pci_dev *pdev)
+{
+ struct pci_dev_intr_ctrl *intr_ctrl;
+ struct fwnode_handle *fwnode;
+ int ret;
+
+ if (!pdev->irq)
+ return ERR_PTR(-EOPNOTSUPP);
+
+ fwnode = dev_fwnode(&pdev->dev);
+ if (!fwnode)
+ return ERR_PTR(-ENODEV);
+
+ intr_ctrl = kmalloc(sizeof(*intr_ctrl), GFP_KERNEL);
+ if (!intr_ctrl)
+ return ERR_PTR(-ENOMEM);
+
+ intr_ctrl->pci_dev = pdev;
+
+ intr_ctrl->irq_domain = irq_domain_create_linear(fwnode, 1, &pci_dev_irq_domain_ops,
+ intr_ctrl);
+ if (!intr_ctrl->irq_domain) {
+ pci_err(pdev, "Failed to create irqdomain\n");
+ ret = -ENOMEM;
+ goto err_free_intr_ctrl;
+ }
+
+ ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_INTX);
+ if (ret < 0) {
+ pci_err(pdev, "Unable alloc irq vector (%d)\n", ret);
+ goto err_remove_domain;
+ }
+ intr_ctrl->irq = pci_irq_vector(pdev, 0);
+ ret = request_irq(intr_ctrl->irq, pci_dev_irq_handler, IRQF_SHARED,
+ dev_name(&pdev->dev), intr_ctrl);
+ if (ret) {
+ pci_err(pdev, "Unable to request irq %d (%d)\n", intr_ctrl->irq, ret);
+ goto err_free_irq_vector;
+ }
+
+ return intr_ctrl;
+
+err_free_irq_vector:
+ pci_free_irq_vectors(pdev);
+err_remove_domain:
+ irq_domain_remove(intr_ctrl->irq_domain);
+err_free_intr_ctrl:
+ kfree(intr_ctrl);
+ return ERR_PTR(ret);
+}
+
+static void pci_dev_remove_intr_ctrl(struct pci_dev_intr_ctrl *intr_ctrl)
+{
+ free_irq(intr_ctrl->irq, intr_ctrl);
+ pci_free_irq_vectors(intr_ctrl->pci_dev);
+ irq_dispose_mapping(irq_find_mapping(intr_ctrl->irq_domain, 0));
+ irq_domain_remove(intr_ctrl->irq_domain);
+ kfree(intr_ctrl);
+}
+
+static void devm_pci_dev_remove_intr_ctrl(void *data)
+{
+ struct pci_dev_intr_ctrl *intr_ctrl = data;
+
+ pci_dev_remove_intr_ctrl(intr_ctrl);
+}
+
+static int devm_pci_dev_create_intr_ctrl(struct pci_dev *pdev)
+{
+ struct pci_dev_intr_ctrl *intr_ctrl;
+
+ intr_ctrl = pci_dev_create_intr_ctrl(pdev);
+
+ if (IS_ERR(intr_ctrl))
+ return PTR_ERR(intr_ctrl);
+
+ return devm_add_action_or_reset(&pdev->dev, devm_pci_dev_remove_intr_ctrl, intr_ctrl);
+}
+
+struct lan966x_pci {
+ struct device *dev;
+ struct pci_dev *pci_dev;
+ int ovcs_id;
+};
+
+static int lan966x_pci_load_overlay(struct lan966x_pci *data)
+{
+ u32 dtbo_size = __dtbo_lan966x_pci_end - __dtbo_lan966x_pci_begin;
+ void *dtbo_start = __dtbo_lan966x_pci_begin;
+ int ret;
+
+ ret = of_overlay_fdt_apply(dtbo_start, dtbo_size, &data->ovcs_id, data->dev->of_node);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void lan966x_pci_unload_overlay(struct lan966x_pci *data)
+{
+ of_overlay_remove(&data->ovcs_id);
+}
+
+static int lan966x_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct device *dev = &pdev->dev;
+ struct lan966x_pci *data;
+ int ret;
+
+ if (!dev->of_node) {
+ dev_err(dev, "Missing of_node for device\n");
+ return -EINVAL;
+ }
+
+ /* Need to be done before devm_pci_dev_create_intr_ctrl.
+ * It allocates an IRQ and so pdev->irq is updated
+ */
+ ret = pcim_enable_device(pdev);
+ if (ret)
+ return ret;
+
+ ret = devm_pci_dev_create_intr_ctrl(pdev);
+ if (ret)
+ return ret;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, data);
+ data->dev = dev;
+ data->pci_dev = pdev;
+
+ ret = lan966x_pci_load_overlay(data);
+ if (ret)
+ return ret;
+
+ pci_set_master(pdev);
+
+ ret = of_platform_default_populate(dev->of_node, NULL, dev);
+ if (ret)
+ goto err_unload_overlay;
+
+ return 0;
+
+err_unload_overlay:
+ lan966x_pci_unload_overlay(data);
+ return ret;
+}
+
+static void lan966x_pci_remove(struct pci_dev *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct lan966x_pci *data = dev_get_drvdata(dev);
+
+ of_platform_depopulate(dev);
+
+ lan966x_pci_unload_overlay(data);
+
+ pci_clear_master(pdev);
+}
+
+static struct pci_device_id lan966x_pci_ids[] = {
+ { PCI_DEVICE(0x1055, 0x9660) },
+ { 0, }
+};
+MODULE_DEVICE_TABLE(pci, lan966x_pci_ids);
+
+static struct pci_driver lan966x_pci_driver = {
+ .name = "mchp_lan966x_pci",
+ .id_table = lan966x_pci_ids,
+ .probe = lan966x_pci_probe,
+ .remove = lan966x_pci_remove,
+};
+module_pci_driver(lan966x_pci_driver);
+
+MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
+MODULE_DESCRIPTION("Microchip LAN966x PCI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/lan966x_pci.dtso b/drivers/mfd/lan966x_pci.dtso
new file mode 100644
index 000000000000..041f4319e4cd
--- /dev/null
+++ b/drivers/mfd/lan966x_pci.dtso
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Microchip UNG
+ */
+
+#include <dt-bindings/clock/microchip,lan966x.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/phy/phy-lan966x-serdes.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target-path="";
+ __overlay__ {
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pci-ep-bus@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * map @0xe2000000 (32MB) to BAR0 (CPU)
+ * map @0xe0000000 (16MB) to BAR1 (AMBA)
+ */
+ ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
+ 0xe0000000 0x01 0x00 0x00 0x1000000>;
+
+ oic: oic@e00c0120 {
+ compatible = "microchip,lan966x-oic";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <0>; /* PCI INTx assigned interrupt */
+ reg = <0xe00c0120 0x190>;
+ };
+
+ cpu_clk: cpu_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>; // CPU clock = 600MHz
+ };
+
+ ddr_clk: ddr_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>; // Fabric clock = 30MHz
+ };
+
+ sys_clk: sys_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <15625000>; // System clock = 15.625MHz
+ };
+
+ cpu_ctrl: syscon@e00c0000 {
+ compatible = "microchip,lan966x-cpu-syscon", "syscon";
+ reg = <0xe00c0000 0xa8>;
+ };
+
+ reset: reset@e200400c {
+ compatible = "microchip,lan966x-switch-reset";
+ reg = <0xe200400c 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
+ };
+
+ gpio: pinctrl@e2004064 {
+ compatible = "microchip,lan966x-pinctrl";
+ reg = <0xe2004064 0xb4>,
+ <0xe2010024 0x138>;
+ resets = <&reset 0>;
+ reset-names = "switch";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 78>;
+ interrupt-parent = <&oic>;
+ interrupt-controller;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+
+ tod_pins: tod_pins {
+ pins = "GPIO_36";
+ function = "ptpsync_1";
+ };
+
+ fc0_a_pins: fcb4-i2c-pins {
+ /* RXD, TXD */
+ pins = "GPIO_9", "GPIO_10";
+ function = "fc0_a";
+ };
+
+ };
+
+ serdes: serdes@e202c000 {
+ compatible = "microchip,lan966x-serdes";
+ reg = <0xe202c000 0x9c>,
+ <0xe2004010 0x4>;
+ #phy-cells = <2>;
+ };
+
+ mdio1: mdio@e200413c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "microchip,lan966x-miim";
+ reg = <0xe200413c 0x24>,
+ <0xe2010020 0x4>;
+
+ resets = <&reset 0>;
+ reset-names = "switch";
+
+ lan966x_phy0: ethernet-lan966x_phy@1 {
+ reg = <1>;
+ };
+
+ lan966x_phy1: ethernet-lan966x_phy@2 {
+ reg = <2>;
+ };
+ };
+
+ switch: switch@e0000000 {
+ compatible = "microchip,lan966x-switch";
+ reg = <0xe0000000 0x0100000>,
+ <0xe2000000 0x0800000>;
+ reg-names = "cpu", "gcb";
+
+ interrupt-parent = <&oic>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+ <9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "xtr", "ana";
+
+ resets = <&reset 0>;
+ reset-names = "switch";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tod_pins>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ phy-handle = <&lan966x_phy0>;
+
+ reg = <0>;
+ phy-mode = "gmii";
+ phys = <&serdes 0 CU(0)>;
+ };
+
+ port1: port@1 {
+ phy-handle = <&lan966x_phy1>;
+
+ reg = <1>;
+ phy-mode = "gmii";
+ phys = <&serdes 1 CU(1)>;
+ };
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 568410e64ce6..4bfc3f2aafa4 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -6241,6 +6241,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
+DECLARE_PCI_FIXUP_FINAL(0x1055, 0x9660, of_pci_make_dev_node);
/*
* Devices known to require a longer delay before first config space access
--
2.45.0
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^ permalink raw reply related [relevance 5%]
* Re: [PATCH v5 14/17] irqchip/riscv-imsic: Add ACPI support
2024-05-23 22:00 0% ` Thomas Gleixner
@ 2024-05-27 4:52 0% ` Sunil V L
0 siblings, 0 replies; 200+ results
From: Sunil V L @ 2024-05-27 4:52 UTC (permalink / raw)
To: Thomas Gleixner
Cc: linux-arm-kernel, linux-kernel, linux-riscv, linux-acpi,
linux-pci, linux-serial, acpica-devel, Catalin Marinas,
Will Deacon, Paul Walmsley, Albert Ou, Rafael J . Wysocki,
Len Brown, Bjorn Helgaas, Anup Patel, Samuel Holland,
Greg Kroah-Hartman, Jiri Slaby, Robert Moore, Conor Dooley,
Andrew Jones, Andy Shevchenko, Marc Zyngier, Atish Kumar Patra,
Andrei Warkentin, Haibo1 Xu, Björn Töpel
On Fri, May 24, 2024 at 12:00:21AM +0200, Thomas Gleixner wrote:
> On Wed, May 01 2024 at 17:47, Sunil V L wrote:
>
> > RISC-V IMSIC interrupt controller provides IPI and MSI support.
> > Currently, DT based drivers setup the IPI feature early during boot but
> > defer setting up the MSI functionality. However, in ACPI systems, ACPI,
> > both IPI and MSI features need to be initialized early itself.
>
> Why?
>
Sorry, commit message got truncated by mistake. Basically, in ACPI PCI
scan happens very early and there is no concept of msi-parent/dependency
on MSI controller like in DT. It just assumes MSI is setup already. Due
to this, we need to setup MSI controller early as well.
> > +
> > +#ifdef CONFIG_ACPI
> > +
> > +static struct fwnode_handle *imsic_acpi_fwnode;
> > +
> > +struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev)
>
> Why is this function global? It's only used in the very same file and
> under the same CONFIG_ACPI #ifdef, no?
>
For platform devices using MSIs, we need a way to determine the MSI
domain. This function is exported so that platform device like
APLIC/IOMMU can find the MSI irqdomain.
For PCI, pci_msi_register_fwnode_provider() is registered by the MSI
driver for this purpose.
Let me know if this can be made better.
> > +{
> > + return imsic_acpi_fwnode;
> > +}
> > +
> > +static int __init imsic_early_acpi_init(union acpi_subtable_headers *header,
> > + const unsigned long end)
> > +{
> > + struct acpi_madt_imsic *imsic = (struct acpi_madt_imsic *)header;
> > + int rc;
> > +
> > + imsic_acpi_fwnode = irq_domain_alloc_named_fwnode("imsic");
> > + if (!imsic_acpi_fwnode) {
> > + pr_err("unable to allocate IMSIC FW node\n");
> > + return -ENOMEM;
> > + }
> > +
> > + /* Setup IMSIC state */
> > + rc = imsic_setup_state(imsic_acpi_fwnode, (void *)imsic);
>
> Pointless (void *) cast.
>
Okay.
> > + if (rc) {
> > + pr_err("%pfwP: failed to setup state (error %d)\n", imsic_acpi_fwnode, rc);
> > + return rc;
> > + }
> > +
> > + /* Do early setup of IMSIC state and IPIs */
> > + rc = imsic_early_probe(imsic_acpi_fwnode);
> > + if (rc)
> > + return rc;
> > +
> > + rc = imsic_platform_acpi_probe(imsic_acpi_fwnode);
> > +
> > +#ifdef CONFIG_PCI
> > + if (!rc)
> > + pci_msi_register_fwnode_provider(&imsic_acpi_get_fwnode);
> > +#endif
> > +
> > + return rc;
>
> Any error return in this function leaks the firmware node and probably
> some more stuff.
>
Yeah, fwnode needs free up and need to update the code a bit. Thanks!
> > +}
> > +
> > +IRQCHIP_ACPI_DECLARE(riscv_imsic, ACPI_MADT_TYPE_IMSIC, NULL,
> > + 1, imsic_early_acpi_init);
> > +#endif
>
> ...
>
> > - /* Find number of interrupt identities */
> > - rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids",
> > - &global->nr_ids);
> > - if (rc) {
> > - pr_err("%pfwP: number of interrupt identities not found\n", fwnode);
> > - return rc;
> > + /* Find number of guest interrupt identities */
> > + rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids",
> > + &global->nr_guest_ids);
> > + if (rc)
> > + global->nr_guest_ids = global->nr_ids;
> > + } else {
> > + global->guest_index_bits = imsic->guest_index_bits;
> > + global->hart_index_bits = imsic->hart_index_bits;
> > + global->group_index_bits = imsic->group_index_bits;
> > + global->group_index_shift = imsic->group_index_shift;
> > + global->nr_ids = imsic->num_ids;
> > + global->nr_guest_ids = imsic->num_guest_ids;
> > }
>
> Seriously?
>
> Why can't you just split out the existing DT code into a separate
> function in an initial patch which avoulds all of this unreviewable
> churn of making the DT stuff indented ?
>
Sure, makes sense. let me create separate patch first as you suggested.
> > +#ifdef CONFIG_ACPI
> > +int imsic_platform_acpi_probe(struct fwnode_handle *fwnode);
> > +struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev);
> > +#else
> > +static inline struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev)
> > +{
> > + return NULL;
> > +}
> > +#endif
>
> Oh well.
>
I guess this is related to your prior comment about the need to make
this public function. Let me know if I am missing something.
Thanks!
Sunil
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^ permalink raw reply [relevance 0%]
* [PATCH v6 6/7] drm/mediatek: Add secure flow support to mediatek-drm
@ 2024-05-25 23:29 3% ` Jason-JH.Lin
0 siblings, 0 replies; 200+ results
From: Jason-JH.Lin @ 2024-05-25 23:29 UTC (permalink / raw)
To: Chun-Kuang Hu, AngeloGioacchino Del Regno, Maxime Ripard
Cc: David Airlie, Daniel Vetter, Matthias Brugger, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, dri-devel,
linux-media, linaro-mm-sig, Jason-ch Chen, Jason-JH . Lin,
Singo Chang, Nancy Lin, Shawn Sung,
Project_Global_Chrome_Upstream_Group, Jeffrey Kardatzke
To add secure flow support for mediatek-drm, each crtc have to
create a secure cmdq mailbox channel. Then cmdq packets with
display HW configuration will be sent to secure cmdq mailbox channel
and configured in the secure world.
Each crtc have to use secure cmdq interface to configure some secure
settings for display HW before sending cmdq packets to secure cmdq
mailbox channel.
If any of plane fbs get from current drm_atomic_state is secure, then
crtc will switch to the secure flow to configure display HW.
If all plane fbs are not secure in current drm_atomic_state, then crtc
will switch to the normal flow.
TODO:
1. Try to use secure mailbox channel to handle normal and secure flow.
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_crtc.c | 260 +++++++++++++++++++++++++--
drivers/gpu/drm/mediatek/mtk_crtc.h | 1 +
drivers/gpu/drm/mediatek/mtk_plane.c | 7 +
3 files changed, 258 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
index 6f34f573e127..59f6263ae806 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
@@ -56,6 +56,11 @@ struct mtk_crtc {
u32 cmdq_event;
u32 cmdq_vblank_cnt;
wait_queue_head_t cb_blocking_queue;
+
+ struct cmdq_client sec_cmdq_client;
+ struct cmdq_pkt sec_cmdq_handle;
+ bool sec_cmdq_working;
+ wait_queue_head_t sec_cb_blocking_queue;
#endif
struct device *mmsys_dev;
@@ -69,6 +74,7 @@ struct mtk_crtc {
/* lock for display hardware access */
struct mutex hw_lock;
bool config_updating;
+ bool sec_on;
};
struct mtk_crtc_state {
@@ -113,6 +119,144 @@ static void mtk_drm_finish_page_flip(struct mtk_crtc *mtk_crtc)
}
}
+void mtk_crtc_disable_secure_state(struct drm_crtc *crtc)
+{
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ enum cmdq_sec_scenario sec_scn = CMDQ_SEC_SCNR_MAX;
+ int i;
+ struct mtk_ddp_comp *ddp_first_comp;
+ struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
+
+ mutex_lock(&mtk_crtc->hw_lock);
+
+ if (!mtk_crtc->sec_cmdq_client.chan) {
+ pr_err("crtc-%d secure mbox channel is NULL\n", drm_crtc_index(crtc));
+ goto err;
+ }
+
+ if (!mtk_crtc->sec_on) {
+ pr_debug("crtc-%d is already disabled!\n", drm_crtc_index(crtc));
+ goto err;
+ }
+
+ mbox_flush(mtk_crtc->sec_cmdq_client.chan, 0);
+ mtk_crtc->sec_cmdq_handle.cmd_buf_size = 0;
+
+ if (mtk_crtc->sec_cmdq_handle.sec_data) {
+ struct cmdq_sec_data *sec_data;
+
+ sec_data = mtk_crtc->sec_cmdq_handle.sec_data;
+ sec_data->addr_metadata_cnt = 0;
+ sec_data->addr_metadatas = (uintptr_t)NULL;
+ }
+
+ /*
+ * Secure path only support DL mode, so we just wait
+ * the first path frame done here
+ */
+ cmdq_pkt_wfe(&mtk_crtc->sec_cmdq_handle, mtk_crtc->cmdq_event, false);
+
+ ddp_first_comp = mtk_crtc->ddp_comp[0];
+ for (i = 0; i < mtk_crtc->layer_nr; i++) {
+ struct drm_plane *plane = &mtk_crtc->planes[i];
+
+ /* make sure secure layer off before switching secure state */
+ if (!mtk_plane_fb_is_secure(plane->state->fb)) {
+ struct mtk_plane_state *plane_state = to_mtk_plane_state(plane->state);
+
+ plane_state->pending.enable = false;
+ mtk_ddp_comp_layer_config(ddp_first_comp, i, plane_state,
+ &mtk_crtc->sec_cmdq_handle);
+ }
+ }
+
+ /* Disable secure path */
+ if (drm_crtc_index(crtc) == 0)
+ sec_scn = CMDQ_SEC_SCNR_PRIMARY_DISP_DISABLE;
+ else if (drm_crtc_index(crtc) == 1)
+ sec_scn = CMDQ_SEC_SCNR_SUB_DISP_DISABLE;
+
+ cmdq_sec_pkt_set_data(&mtk_crtc->sec_cmdq_handle, sec_scn);
+
+ cmdq_pkt_finalize(&mtk_crtc->sec_cmdq_handle);
+ dma_sync_single_for_device(mtk_crtc->sec_cmdq_client.chan->mbox->dev,
+ mtk_crtc->sec_cmdq_handle.pa_base,
+ mtk_crtc->sec_cmdq_handle.cmd_buf_size,
+ DMA_TO_DEVICE);
+
+ mtk_crtc->sec_cmdq_working = true;
+ mbox_send_message(mtk_crtc->sec_cmdq_client.chan, &mtk_crtc->sec_cmdq_handle);
+ mbox_client_txdone(mtk_crtc->sec_cmdq_client.chan, 0);
+
+ // Wait for sec state to be disabled by cmdq
+ wait_event_timeout(mtk_crtc->sec_cb_blocking_queue,
+ !mtk_crtc->sec_cmdq_working,
+ msecs_to_jiffies(500));
+
+ mtk_crtc->sec_on = false;
+ pr_debug("crtc-%d disable secure plane!\n", drm_crtc_index(crtc));
+
+err:
+ mutex_unlock(&mtk_crtc->hw_lock);
+#endif
+}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+static void mtk_crtc_enable_secure_state(struct drm_crtc *crtc)
+{
+ enum cmdq_sec_scenario sec_scn = CMDQ_SEC_SCNR_MAX;
+ struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
+
+ if (drm_crtc_index(crtc) == 0)
+ sec_scn = CMDQ_SEC_SCNR_PRIMARY_DISP;
+ else if (drm_crtc_index(crtc) == 1)
+ sec_scn = CMDQ_SEC_SCNR_SUB_DISP;
+
+ cmdq_sec_pkt_set_data(&mtk_crtc->sec_cmdq_handle, sec_scn);
+
+ pr_debug("crtc-%d enable secure plane!\n", drm_crtc_index(crtc));
+}
+#endif
+
+static void mtk_crtc_plane_switch_sec_state(struct drm_crtc *crtc,
+ struct drm_atomic_state *state)
+{
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ bool sec_on[MAX_CRTC] = {0};
+ int i;
+ struct drm_crtc_state *crtc_state;
+ struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
+ struct drm_plane *plane;
+ struct drm_plane_state *old_plane_state;
+
+ for_each_old_plane_in_state(state, plane, old_plane_state, i) {
+ if (!old_plane_state->crtc || !plane->state->crtc)
+ continue;
+
+ if (plane->state->fb &&
+ mtk_plane_fb_is_secure(plane->state->fb) &&
+ mtk_crtc->sec_cmdq_client.chan)
+ sec_on[drm_crtc_index(plane->state->crtc)] = true;
+ }
+
+ for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
+ if (!crtc_state->active)
+ continue;
+
+ mtk_crtc = to_mtk_crtc(crtc);
+
+ if (!sec_on[i]) {
+ mtk_crtc_disable_secure_state(crtc);
+ continue;
+ }
+
+ mutex_lock(&mtk_crtc->hw_lock);
+ mtk_crtc->sec_on = true;
+ mutex_unlock(&mtk_crtc->hw_lock);
+ }
+#endif
+}
+
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
static int mtk_drm_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt,
size_t size)
@@ -148,22 +292,33 @@ static void mtk_drm_cmdq_pkt_destroy(struct cmdq_pkt *pkt)
dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size,
DMA_TO_DEVICE);
kfree(pkt->va_base);
+ kfree(pkt->sec_data);
}
#endif
static void mtk_crtc_destroy(struct drm_crtc *crtc)
{
struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
+ struct mtk_drm_private *priv = crtc->dev->dev_private;
int i;
+ priv = priv->all_drm_private[drm_crtc_index(crtc)];
+
mtk_mutex_put(mtk_crtc->mutex);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
mtk_drm_cmdq_pkt_destroy(&mtk_crtc->cmdq_handle);
+ mtk_drm_cmdq_pkt_destroy(&mtk_crtc->sec_cmdq_handle);
if (mtk_crtc->cmdq_client.chan) {
mbox_free_channel(mtk_crtc->cmdq_client.chan);
mtk_crtc->cmdq_client.chan = NULL;
}
+
+ if (mtk_crtc->sec_cmdq_client.chan) {
+ device_link_remove(priv->dev, mtk_crtc->sec_cmdq_client.chan->mbox->dev);
+ mbox_free_channel(mtk_crtc->sec_cmdq_client.chan);
+ mtk_crtc->sec_cmdq_client.chan = NULL;
+ }
#endif
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
@@ -312,6 +467,11 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
if (data->sta < 0)
return;
+ if (!data->pkt || !data->pkt->sec_data)
+ mtk_crtc = container_of(cmdq_cl, struct mtk_crtc, cmdq_client);
+ else
+ mtk_crtc = container_of(cmdq_cl, struct mtk_crtc, sec_cmdq_client);
+
state = to_mtk_crtc_state(mtk_crtc->base.state);
state->pending_config = false;
@@ -340,6 +500,11 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
mtk_crtc->pending_async_planes = false;
}
+ if (mtk_crtc->sec_cmdq_working) {
+ mtk_crtc->sec_cmdq_working = false;
+ wake_up(&mtk_crtc->sec_cb_blocking_queue);
+ }
+
mtk_crtc->cmdq_vblank_cnt = 0;
wake_up(&mtk_crtc->cb_blocking_queue);
}
@@ -563,7 +728,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
static void mtk_crtc_update_config(struct mtk_crtc *mtk_crtc, bool needs_vblank)
{
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
- struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;
+ struct cmdq_client cmdq_client;
+ struct cmdq_pkt *cmdq_handle;
#endif
struct drm_crtc *crtc = &mtk_crtc->base;
struct mtk_drm_private *priv = crtc->dev->dev_private;
@@ -601,14 +767,36 @@ static void mtk_crtc_update_config(struct mtk_crtc *mtk_crtc, bool needs_vblank)
mtk_mutex_release(mtk_crtc->mutex);
}
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
- if (mtk_crtc->cmdq_client.chan) {
+ if (mtk_crtc->sec_on) {
+ mbox_flush(mtk_crtc->sec_cmdq_client.chan, 0);
+ mtk_crtc->sec_cmdq_handle.cmd_buf_size = 0;
+
+ if (mtk_crtc->sec_cmdq_handle.sec_data) {
+ struct cmdq_sec_data *sec_data = mtk_crtc->sec_cmdq_handle.sec_data;
+
+ memset((void *)sec_data->addr_metadatas, 0,
+ sec_data->addr_metadata_cnt * sizeof(u64));
+ sec_data->addr_metadata_cnt = 0;
+ }
+
+ mtk_crtc_enable_secure_state(crtc);
+
+ cmdq_client = mtk_crtc->sec_cmdq_client;
+ cmdq_handle = &mtk_crtc->sec_cmdq_handle;
+ } else if (mtk_crtc->cmdq_client.chan) {
mbox_flush(mtk_crtc->cmdq_client.chan, 2000);
- cmdq_handle->cmd_buf_size = 0;
+ mtk_crtc->cmdq_handle.cmd_buf_size = 0;
+
+ cmdq_client = mtk_crtc->cmdq_client;
+ cmdq_handle = &mtk_crtc->cmdq_handle;
+ }
+
+ if (cmdq_client.chan) {
cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
mtk_crtc_ddp_config(crtc, cmdq_handle);
cmdq_pkt_finalize(cmdq_handle);
- dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev,
+ dma_sync_single_for_device(cmdq_client.chan->mbox->dev,
cmdq_handle->pa_base,
cmdq_handle->cmd_buf_size,
DMA_TO_DEVICE);
@@ -621,8 +809,8 @@ static void mtk_crtc_update_config(struct mtk_crtc *mtk_crtc, bool needs_vblank)
*/
mtk_crtc->cmdq_vblank_cnt = 3;
- mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle);
- mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0);
+ mbox_send_message(cmdq_client.chan, cmdq_handle);
+ mbox_client_txdone(cmdq_client.chan, 0);
}
#endif
mtk_crtc->config_updating = false;
@@ -764,6 +952,8 @@ static void mtk_crtc_atomic_disable(struct drm_crtc *crtc,
if (!mtk_crtc->enabled)
return;
+ mtk_crtc_disable_secure_state(crtc);
+
/* Set all pending plane state to disabled */
for (i = 0; i < mtk_crtc->layer_nr; i++) {
struct drm_plane *plane = &mtk_crtc->planes[i];
@@ -802,6 +992,8 @@ static void mtk_crtc_atomic_begin(struct drm_crtc *crtc,
struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
unsigned long flags;
+ mtk_crtc_plane_switch_sec_state(crtc, state);
+
if (mtk_crtc->event && mtk_crtc_state->base.event)
DRM_ERROR("new event while there is still a pending event\n");
@@ -1091,8 +1283,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
if (ret) {
dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
drm_crtc_index(&mtk_crtc->base));
- mbox_free_channel(mtk_crtc->cmdq_client.chan);
- mtk_crtc->cmdq_client.chan = NULL;
+ goto cmdq_err;
} else {
ret = mtk_drm_cmdq_pkt_create(&mtk_crtc->cmdq_client,
&mtk_crtc->cmdq_handle,
@@ -1100,14 +1291,63 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
if (ret) {
dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",
drm_crtc_index(&mtk_crtc->base));
- mbox_free_channel(mtk_crtc->cmdq_client.chan);
- mtk_crtc->cmdq_client.chan = NULL;
+ goto cmdq_err;
}
}
/* for sending blocking cmd in crtc disable */
init_waitqueue_head(&mtk_crtc->cb_blocking_queue);
}
+
+ mtk_crtc->sec_cmdq_client.client.dev = mtk_crtc->mmsys_dev;
+ mtk_crtc->sec_cmdq_client.client.tx_block = false;
+ mtk_crtc->sec_cmdq_client.client.knows_txdone = true;
+ mtk_crtc->sec_cmdq_client.client.rx_callback = ddp_cmdq_cb;
+ mtk_crtc->sec_cmdq_client.chan =
+ mbox_request_channel(&mtk_crtc->sec_cmdq_client.client, i + 1);
+ if (IS_ERR(mtk_crtc->sec_cmdq_client.chan)) {
+ dev_err(dev, "mtk_crtc %d failed to create sec mailbox client\n",
+ drm_crtc_index(&mtk_crtc->base));
+ mtk_crtc->sec_cmdq_client.chan = NULL;
+ }
+
+ if (mtk_crtc->sec_cmdq_client.chan) {
+ struct device_link *link;
+
+ /* add devlink to cmdq dev to make sure suspend/resume order is correct */
+ link = device_link_add(priv->dev, mtk_crtc->sec_cmdq_client.chan->mbox->dev,
+ DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
+ if (!link) {
+ dev_err(priv->dev, "Unable to link dev=%s\n",
+ dev_name(mtk_crtc->sec_cmdq_client.chan->mbox->dev));
+ ret = -ENODEV;
+ goto cmdq_err;
+ }
+
+ ret = mtk_drm_cmdq_pkt_create(&mtk_crtc->sec_cmdq_client,
+ &mtk_crtc->sec_cmdq_handle,
+ PAGE_SIZE);
+ if (ret) {
+ dev_dbg(dev, "mtk_crtc %d failed to create cmdq secure packet\n",
+ drm_crtc_index(&mtk_crtc->base));
+ goto cmdq_err;
+ }
+
+ /* for sending blocking cmd in crtc disable */
+ init_waitqueue_head(&mtk_crtc->sec_cb_blocking_queue);
+ }
+
+cmdq_err:
+ if (ret) {
+ if (mtk_crtc->cmdq_client.chan) {
+ mbox_free_channel(mtk_crtc->cmdq_client.chan);
+ mtk_crtc->cmdq_client.chan = NULL;
+ }
+ if (mtk_crtc->sec_cmdq_client.chan) {
+ mbox_free_channel(mtk_crtc->sec_cmdq_client.chan);
+ mtk_crtc->sec_cmdq_client.chan = NULL;
+ }
+ }
#endif
if (conn_routes) {
diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.h b/drivers/gpu/drm/mediatek/mtk_crtc.h
index 388e900b6f4d..0b0be01c25f2 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.h
@@ -19,6 +19,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
unsigned int path_len, int priv_data_index,
const struct mtk_drm_route *conn_routes,
unsigned int num_conn_routes);
+void mtk_crtc_disable_secure_state(struct drm_crtc *crtc);
int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediatek/mtk_plane.c
index 478206f21fd0..95e1b17091f0 100644
--- a/drivers/gpu/drm/mediatek/mtk_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_plane.c
@@ -287,6 +287,13 @@ static void mtk_plane_atomic_disable(struct drm_plane *plane,
mtk_plane_state->pending.enable = false;
wmb(); /* Make sure the above parameter is set before update */
mtk_plane_state->pending.dirty = true;
+
+ if (mtk_plane_state->pending.is_secure) {
+ struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane);
+
+ if (old_state->crtc)
+ mtk_crtc_disable_secure_state(old_state->crtc);
+ }
}
static void mtk_plane_atomic_update(struct drm_plane *plane,
--
2.18.0
_______________________________________________
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^ permalink raw reply related [relevance 3%]
* Re: [PATCH v2 4/5] firmware: imx: add driver for NXP EdgeLock Enclave
2024-05-23 10:49 3% ` [PATCH v2 4/5] firmware: imx: add driver for NXP EdgeLock Enclave Pankaj Gupta
@ 2024-05-24 9:07 0% ` Sascha Hauer
0 siblings, 0 replies; 200+ results
From: Sascha Hauer @ 2024-05-24 9:07 UTC (permalink / raw)
To: Pankaj Gupta
Cc: Jonathan Corbet, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Pengutronix Kernel Team, Fabio Estevam, Rob Herring,
Krzysztof Kozlowski, linux-doc, linux-kernel, devicetree, imx,
linux-arm-kernel
On Thu, May 23, 2024 at 04:19:35PM +0530, Pankaj Gupta wrote:
> NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE),
> are embedded in the SoC to support the features like HSM, SHE & V2X,
> using message based communication interface.
>
> The secure enclave FW communicates on a dedicated messaging unit(MU)
> based interface(s) with application core, where kernel is running.
> It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
>
> This patch adds the driver for communication interface to secure-enclave,
> for exchanging messages with NXP secure enclave HW IP(s) like EdgeLock
> Enclave (ELE) from Kernel-space, used by kernel management layers like
> - DM-Crypt.
>
> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> ---
> drivers/firmware/imx/Kconfig | 12 +
> drivers/firmware/imx/Makefile | 2 +
> drivers/firmware/imx/ele_base_msg.c | 286 +++++++++++++++++++
> drivers/firmware/imx/ele_base_msg.h | 92 +++++++
> drivers/firmware/imx/ele_common.c | 239 ++++++++++++++++
> drivers/firmware/imx/ele_common.h | 43 +++
> drivers/firmware/imx/se_ctrl.c | 531 ++++++++++++++++++++++++++++++++++++
> drivers/firmware/imx/se_ctrl.h | 99 +++++++
> include/linux/firmware/imx/se_api.h | 14 +
> 9 files changed, 1318 insertions(+)
>
> diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
> index 183613f82a11..56bdca9bd917 100644
> --- a/drivers/firmware/imx/Kconfig
> +++ b/drivers/firmware/imx/Kconfig
> @@ -22,3 +22,15 @@ config IMX_SCU
>
> This driver manages the IPC interface between host CPU and the
> SCU firmware running on M4.
> +
> +config IMX_SEC_ENCLAVE
> + tristate "i.MX Embedded Secure Enclave - EdgeLock Enclave Firmware driver."
> + depends on IMX_MBOX && ARCH_MXC && ARM64
> + default m if ARCH_MXC
> +
> + help
> + It is possible to use APIs exposed by the iMX Secure Enclave HW IP called:
> + - EdgeLock Enclave Firmware (for i.MX8ULP, i.MX93),
> + like base, HSM, V2X & SHE using the SAB protocol via the shared Messaging
> + Unit. This driver exposes these interfaces via a set of file descriptors
> + allowing to configure shared memory, send and receive messages.
> diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile
> index 8f9f04a513a8..aa9033e0e9e3 100644
> --- a/drivers/firmware/imx/Makefile
> +++ b/drivers/firmware/imx/Makefile
> @@ -1,3 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-$(CONFIG_IMX_DSP) += imx-dsp.o
> obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o
> +sec_enclave-objs = se_ctrl.o ele_common.o ele_base_msg.o
> +obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
> diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele_base_msg.c
> new file mode 100644
> index 000000000000..f072c613dba1
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_base_msg.c
> @@ -0,0 +1,286 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <linux/types.h>
> +#include <linux/completion.h>
> +#include <linux/dma-mapping.h>
> +
> +#include "ele_base_msg.h"
> +#include "ele_common.h"
> +
> +int ele_get_info(struct device *dev, struct ele_dev_info *s_info)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree) = NULL;
> + struct se_api_msg *rx_msg __free(kfree) = NULL;
> + phys_addr_t get_info_addr = 0;
> + u32 *get_info_data = NULL;
> + u32 status;
> + int ret = 0;
> +
> + memset(s_info, 0x0, sizeof(*s_info));
> +
> + if (priv->mem_pool_name)
> + get_info_data = get_phy_buf_mem_pool(dev,
> + priv->mem_pool_name,
> + &get_info_addr,
> + ELE_GET_INFO_BUFF_SZ);
> + else
> + get_info_data = dma_alloc_coherent(dev,
> + ELE_GET_INFO_BUFF_SZ,
> + &get_info_addr,
> + GFP_KERNEL);
> + if (!get_info_data) {
> + ret = -ENOMEM;
> + dev_dbg(dev,
> + "%s: Failed to allocate get_info_addr.\n",
> + __func__);
> + goto exit;
> + }
> +
> + tx_msg = kzalloc(ELE_GET_INFO_REQ_MSG_SZ, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + goto exit;
> + }
> +
> + rx_msg = kzalloc(ELE_GET_INFO_RSP_MSG_SZ, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + goto exit;
> + }
> +
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_GET_INFO_REQ,
> + ELE_GET_INFO_REQ_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + tx_msg->data[0] = upper_32_bits(get_info_addr);
> + tx_msg->data[1] = lower_32_bits(get_info_addr);
> + tx_msg->data[2] = sizeof(struct ele_dev_info);
> + ret = imx_ele_msg_send_rcv(priv, tx_msg, rx_msg);
> + if (ret < 0)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + &priv->rx_msg->header,
> + ELE_GET_INFO_REQ,
> + ELE_GET_INFO_RSP_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_GET_INFO_REQ, status);
> + ret = -EPERM;
> + }
> +
> + memcpy(s_info, get_info_data, sizeof(struct ele_dev_info));
> +
> +exit:
> + if (get_info_addr) {
> + if (priv->mem_pool_name)
> + free_phybuf_mem_pool(dev, priv->mem_pool_name,
> + get_info_data, ELE_GET_INFO_BUFF_SZ);
> + else
> + dma_free_coherent(dev,
> + ELE_GET_INFO_BUFF_SZ,
> + get_info_data,
> + get_info_addr);
> + }
> +
> + return ret;
> +}
> +
> +int ele_fetch_soc_info(struct device *dev, u16 *soc_rev, u64 *serial_num)
> +{
> + struct ele_dev_info s_info = {0};
> + int err = 0;
> +
> + err = ele_get_info(dev, &s_info);
> + if (err < 0) {
> + dev_err(dev, "Error");
> + return err;
> + }
> +
> + *soc_rev = s_info.d_info.soc_rev;
> + *serial_num = GET_SERIAL_NUM_FROM_UID(s_info.d_info.uid, MAX_UID_SIZE >> 2);
> +
> + return err;
> +}
> +
> +int ele_ping(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree) = NULL;
> + struct se_api_msg *rx_msg __free(kfree) = NULL;
> + u32 status;
> + int ret = 0;
> +
> + tx_msg = kzalloc(ELE_PING_REQ_SZ, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + goto exit;
> + }
> +
> + rx_msg = kzalloc(ELE_PING_RSP_SZ, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + goto exit;
> + }
> +
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_PING_REQ, ELE_PING_REQ_SZ,
> + true);
> + if (ret) {
> + dev_err(dev, "Error: plat_fill_cmd_msg_hdr failed.\n");
> + goto exit;
> + }
> +
> + ret = imx_ele_msg_send_rcv(priv, tx_msg, rx_msg);
> + if (ret)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + &priv->rx_msg->header,
> + ELE_PING_REQ,
> + ELE_PING_RSP_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_PING_REQ, status);
> + ret = -EPERM;
> + }
> +exit:
> + return ret;
> +}
> +
> +int ele_service_swap(struct device *dev,
> + phys_addr_t addr,
> + u32 addr_size, u16 flag)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree) = NULL;
> + struct se_api_msg *rx_msg __free(kfree) = NULL;
> + u32 status;
> + int ret = 0;
> +
> + tx_msg = kzalloc(ELE_SERVICE_SWAP_REQ_MSG_SZ, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + goto exit;
> + }
> +
> + rx_msg = kzalloc(ELE_SERVICE_SWAP_RSP_MSG_SZ, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + goto exit;
> + }
> +
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_SERVICE_SWAP_REQ,
> + ELE_SERVICE_SWAP_REQ_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + tx_msg->data[0] = flag;
> + tx_msg->data[1] = addr_size;
> + tx_msg->data[2] = ELE_NONE_VAL;
> + tx_msg->data[3] = lower_32_bits(addr);
> + tx_msg->data[4] = plat_add_msg_crc((uint32_t *)&tx_msg[0],
> + ELE_SERVICE_SWAP_REQ_MSG_SZ);
> + ret = imx_ele_msg_send_rcv(priv, tx_msg, rx_msg);
> + if (ret < 0)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + &priv->rx_msg->header,
> + ELE_SERVICE_SWAP_REQ,
> + ELE_SERVICE_SWAP_RSP_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_SERVICE_SWAP_REQ, status);
> + ret = -EPERM;
> + } else {
> + if (flag == ELE_IMEM_EXPORT)
> + ret = priv->rx_msg->data[1];
> + else
> + ret = 0;
> + }
> +exit:
> +
> + return ret;
> +}
> +
> +int ele_fw_authenticate(struct device *dev, phys_addr_t addr)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree) = NULL;
> + struct se_api_msg *rx_msg __free(kfree) = NULL;
> + u32 status;
> + int ret = 0;
> +
> + tx_msg = kzalloc(ELE_FW_AUTH_REQ_SZ, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + goto exit;
> + }
> +
> + rx_msg = kzalloc(ELE_FW_AUTH_RSP_MSG_SZ, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + goto exit;
> + }
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_FW_AUTH_REQ,
> + ELE_FW_AUTH_REQ_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + tx_msg->data[0] = addr;
> + tx_msg->data[1] = addr >> 32;
> + tx_msg->data[2] = addr;
> +
> + ret = imx_ele_msg_send_rcv(priv, tx_msg, rx_msg);
> + if (ret < 0)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + &priv->rx_msg->header,
> + ELE_FW_AUTH_REQ,
> + ELE_FW_AUTH_RSP_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_FW_AUTH_REQ, status);
> + ret = -EPERM;
> + }
> +exit:
> +
> + return ret;
> +}
> diff --git a/drivers/firmware/imx/ele_base_msg.h b/drivers/firmware/imx/ele_base_msg.h
> new file mode 100644
> index 000000000000..f00414f9d86d
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_base_msg.h
> @@ -0,0 +1,92 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + *
> + * Header file for the EdgeLock Enclave Base API(s).
> + */
> +
> +#ifndef ELE_BASE_MSG_H
> +#define ELE_BASE_MSG_H
> +
> +#include <linux/device.h>
> +#include <linux/types.h>
> +
> +#define WORD_SZ 4
This define is unused
> +#define ELE_NONE_VAL 0x0
> +
> +#define ELE_SUCCESS_IND 0xD6
This define is unused, instead you have hardcoded 0xd6 constants in your
code. Either use this define or drop it.
> +
> +#define ELE_GET_INFO_REQ 0xDA
> +#define ELE_GET_INFO_REQ_MSG_SZ 0x10
> +#define ELE_GET_INFO_RSP_MSG_SZ 0x08
> +
> +#define ELE_GET_INFO_BUFF_SZ 0x100
> +
> +#define DEFAULT_IMX_SOC_VER 0xA000
> +#define SOC_VER_MASK 0xFFFF0000
> +#define SOC_ID_MASK 0x0000FFFF
> +
> +#define MAX_UID_SIZE (16)
> +#define DEV_GETINFO_ROM_PATCH_SHA_SZ (32)
> +#define DEV_GETINFO_FW_SHA_SZ (32)
> +#define DEV_GETINFO_OEM_SRKH_SZ (64)
> +#define DEV_GETINFO_MIN_VER_MASK 0xFF
> +#define DEV_GETINFO_MAJ_VER_MASK 0xFF00
> +
> +struct dev_info {
> + uint8_t cmd;
> + uint8_t ver;
> + uint16_t length;
> + uint16_t soc_id;
> + uint16_t soc_rev;
> + uint16_t lmda_val;
> + uint8_t ssm_state;
> + uint8_t dev_atts_api_ver;
> + uint8_t uid[MAX_UID_SIZE];
> + uint8_t sha_rom_patch[DEV_GETINFO_ROM_PATCH_SHA_SZ];
> + uint8_t sha_fw[DEV_GETINFO_FW_SHA_SZ];
> +};
> +
> +struct dev_addn_info {
> + uint8_t oem_srkh[DEV_GETINFO_OEM_SRKH_SZ];
> + uint8_t trng_state;
> + uint8_t csal_state;
> + uint8_t imem_state;
> + uint8_t reserved2;
> +};
> +
> +struct ele_dev_info {
> + struct dev_info d_info;
> + struct dev_addn_info d_addn_info;
> +};
> +
> +#define GET_SERIAL_NUM_FROM_UID(x, uid_word_sz) \
> + (((u64)(((u32 *)(x))[(uid_word_sz) - 1]) << 32) | ((u32 *)(x))[0])
> +
> +#define ELE_PING_REQ 0x01
> +#define ELE_PING_REQ_SZ 0x04
> +#define ELE_PING_RSP_SZ 0x08
> +
> +#define ELE_SERVICE_SWAP_REQ 0xDF
> +#define ELE_SERVICE_SWAP_REQ_MSG_SZ 0x18
> +#define ELE_SERVICE_SWAP_RSP_MSG_SZ 0x0C
> +#define ELE_IMEM_SIZE 0x10000
> +#define ELE_IMEM_STATE_OK 0xCA
> +#define ELE_IMEM_STATE_BAD 0xFE
> +#define ELE_IMEM_STATE_WORD 0x27
> +#define ELE_IMEM_STATE_MASK 0x00ff0000
> +#define ELE_IMEM_EXPORT 0x1
> +#define ELE_IMEM_IMPORT 0x2
> +
> +#define ELE_FW_AUTH_REQ 0x02
> +#define ELE_FW_AUTH_REQ_SZ 0x10
> +#define ELE_FW_AUTH_RSP_MSG_SZ 0x08
> +
> +int ele_get_info(struct device *dev, struct ele_dev_info *s_info);
> +int ele_fetch_soc_info(struct device *dev, u16 *soc_rev, u64 *serial_num);
> +int ele_ping(struct device *dev);
> +int ele_service_swap(struct device *dev,
> + phys_addr_t addr,
> + u32 addr_size, u16 flag);
> +int ele_fw_authenticate(struct device *dev, phys_addr_t addr);
> +#endif
> diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_common.c
> new file mode 100644
> index 000000000000..c286c3d84d82
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_common.c
> @@ -0,0 +1,239 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include "ele_base_msg.h"
> +#include "ele_common.h"
> +
> +u32 plat_add_msg_crc(u32 *msg, u32 msg_len)
Please use a proper function name prefix.
> +{
> + u32 nb_words = msg_len / (u32)sizeof(u32);
> + u32 crc = 0;
> + u32 i;
> +
> + for (i = 0; i < nb_words - 1; i++)
> + crc ^= *(msg + i);
> +
> + return crc;
> +}
> +
> +int imx_ele_msg_rcv(struct se_if_priv *priv)
> +{
> + u32 wait;
> + int err = 0;
> +
> + lockdep_assert_held(&priv->se_if_cmd_lock);
> +
> + wait = msecs_to_jiffies(1000);
> + if (!wait_for_completion_timeout(&priv->done, wait)) {
> + dev_err(priv->dev,
> + "Error: wait_for_completion timed out.\n");
> + err = -ETIMEDOUT;
> + }
> +
> + return err;
> +}
> +
> +int imx_ele_msg_send(struct se_if_priv *priv, void *tx_msg)
> +{
> + struct se_msg_hdr *header;
> + int err;
> +
> + header = (struct se_msg_hdr *) tx_msg;
> +
> + if (header->tag == priv->cmd_tag)
> + lockdep_assert_held(&priv->se_if_cmd_lock);
> +
> + scoped_guard(mutex, &priv->se_if_lock);
> +
> + err = mbox_send_message(priv->tx_chan, tx_msg);
> + if (err < 0) {
> + dev_err(priv->dev, "Error: mbox_send_message failure.\n");
> + return err;
> + }
> +
> + return err;
> +}
> +
> +/* API used for send/receive blocking call. */
> +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *tx_msg, void *rx_msg)
> +{
> + int err;
> +
> + scoped_guard(mutex, &priv->se_if_cmd_lock);
> + if (priv->waiting_rsp_dev) {
> + dev_warn(priv->dev,
> + "There should be no misc dev-ctx, waiting for resp.\n");
> + priv->waiting_rsp_dev = NULL;
> + }
> + priv->rx_msg = rx_msg;
> + err = imx_ele_msg_send(priv, tx_msg);
> + if (err < 0)
> + goto exit;
> +
> + err = imx_ele_msg_rcv(priv);
> +
> +exit:
> + return err;
> +}
> +
> +/*
> + * Callback called by mailbox FW, when data is received.
> + */
> +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg)
> +{
> + struct device *dev = mbox_cl->dev;
> + struct se_if_priv *priv;
> + struct se_msg_hdr *header;
> +
> + priv = dev_get_drvdata(dev);
> +
> + /* The function can be called with NULL msg */
> + if (!msg) {
> + dev_err(dev, "Message is invalid\n");
> + return;
> + }
> +
> + header = (struct se_msg_hdr *) msg;
> +
> + if (header->tag == priv->rsp_tag) {
> + if (!priv->waiting_rsp_dev) {
> + /*
> + * Reading the EdgeLock Enclave response
> + * to the command, sent by other
> + * linux kernel services.
> + */
> + spin_lock(&priv->lock);
> + memcpy(priv->rx_msg, msg, header->size << 2);
> +
> + complete(&priv->done);
> + spin_unlock(&priv->lock);
> + return;
> + }
> + } else {
> + dev_err(dev, "Failed to select a device for message: %.8x\n",
> + *((u32 *) header));
> + return;
> + }
> +}
> +
> +int validate_rsp_hdr(struct se_if_priv *priv,
> + struct se_msg_hdr *header,
> + uint8_t msg_id,
> + uint8_t sz,
> + bool is_base_api)
> +{
> + int ret = -EINVAL;
> +
> + if (header->tag != priv->rsp_tag) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: Resp tag mismatch. (0x%x != 0x%x)",
> + msg_id, header->tag, priv->rsp_tag);
> + return ret;
Just return -EINVAL. Drop the variable 'ret' entirely from this
function.
> + }
> +
> + if (header->command != msg_id) {
> + dev_err(priv->dev,
> + "MSG Header: Cmd id mismatch. (0x%x != 0x%x)",
> + header->command, msg_id);
> + return ret;
> + }
> +
> + if (header->size != (sz >> 2)) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: Cmd size mismatch. (0x%x != 0x%x)",
> + msg_id, header->size, (sz >> 2));
> + return ret;
> + }
> +
> + if (is_base_api && (header->ver != priv->base_api_ver)) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: Base API Vers mismatch. (0x%x != 0x%x)",
> + msg_id, header->ver, priv->base_api_ver);
> + return ret;
> + } else if (!is_base_api && header->ver != priv->fw_api_ver) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: FW API Vers mismatch. (0x%x != 0x%x)",
> + msg_id, header->ver, priv->fw_api_ver);
> + return ret;
> + }
> +
> + ret = 0;
> +
> + return ret;
> +}
> +
> +int se_save_imem_state(struct device *dev)
This function is used internally by the driver code. It should take a
struct struct se_if_priv * directly here. Same applies for several
other functions in this patch.
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + int ret;
> +
> + /* EXPORT command will save encrypted IMEM to given address,
> + * so later in resume, IMEM can be restored from the given
> + * address.
> + *
> + * Size must be at least 64 kB.
> + */
> + ret = ele_service_swap(dev,
> + priv->imem.phyaddr,
> + ELE_IMEM_SIZE,
> + ELE_IMEM_EXPORT);
> + if (ret < 0)
> + dev_err(dev, "Failed to export IMEM\n");
> + else
> + dev_info(dev,
> + "Exported %d bytes of encrypted IMEM\n",
> + ret);
> +
> + return ret;
> +}
> +
> +int se_restore_imem_state(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct ele_dev_info s_info;
> + int ret;
> +
> + /* get info from ELE */
> + ret = ele_get_info(dev, &s_info);
> + if (ret) {
> + dev_err(dev, "Failed to get info from ELE.\n");
> + return ret;
> + }
> +
> + /* Get IMEM state, if 0xFE then import IMEM */
> + if (s_info.d_addn_info.imem_state == ELE_IMEM_STATE_BAD) {
> + /* IMPORT command will restore IMEM from the given
> + * address, here size is the actual size returned by ELE
> + * during the export operation
> + */
> + ret = ele_service_swap(dev,
> + priv->imem.phyaddr,
> + priv->imem.size,
> + ELE_IMEM_IMPORT);
> + if (ret) {
> + dev_err(dev, "Failed to import IMEM\n");
> + goto exit;
> + }
> + } else
> + goto exit;
> +
> + /* After importing IMEM, check if IMEM state is equal to 0xCA
> + * to ensure IMEM is fully loaded and
> + * ELE functionality can be used.
> + */
> + ret = ele_get_info(dev, &s_info);
> + if (ret) {
> + dev_err(dev, "Failed to get info from ELE.\n");
> + goto exit;
> + }
> +
> + if (s_info.d_addn_info.imem_state == ELE_IMEM_STATE_OK)
> + dev_info(dev, "Successfully restored IMEM\n");
> + else
> + dev_err(dev, "Failed to restore IMEM\n");
> +
> +exit:
> + return ret;
> +}
> diff --git a/drivers/firmware/imx/ele_common.h b/drivers/firmware/imx/ele_common.h
> new file mode 100644
> index 000000000000..76777ac629d6
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_common.h
> @@ -0,0 +1,43 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +
> +#ifndef __ELE_COMMON_H__
> +#define __ELE_COMMON_H__
> +
> +#include "se_ctrl.h"
> +
> +#define IMX_ELE_FW_DIR "imx/ele/"
> +
> +uint32_t plat_add_msg_crc(uint32_t *msg, uint32_t msg_len);
> +int imx_ele_msg_rcv(struct se_if_priv *priv);
> +int imx_ele_msg_send(struct se_if_priv *priv, void *tx_msg);
> +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *tx_msg, void *rx_msg);
> +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg);
> +int validate_rsp_hdr(struct se_if_priv *priv,
> + struct se_msg_hdr *header,
> + uint8_t msg_id,
> + uint8_t sz,
> + bool is_base_api);
> +
> +/* Fill a command message header with a given command ID and length in bytes. */
> +static inline int plat_fill_cmd_msg_hdr(struct se_if_priv *priv,
> + struct se_msg_hdr *hdr,
> + u8 cmd,
> + u32 len,
> + bool is_base_api)
> +{
> + hdr->tag = priv->cmd_tag;
> + hdr->ver = (is_base_api) ? priv->base_api_ver : priv->fw_api_ver;
> + hdr->command = cmd;
> + hdr->size = len >> 2;
> +
> + return 0;
> +}
> +
> +int se_save_imem_state(struct device *dev);
> +int se_restore_imem_state(struct device *dev);
> +
> +#endif /*__ELE_COMMON_H__ */
> diff --git a/drivers/firmware/imx/se_ctrl.c b/drivers/firmware/imx/se_ctrl.c
> new file mode 100644
> index 000000000000..0642d349b3d3
> --- /dev/null
> +++ b/drivers/firmware/imx/se_ctrl.c
> @@ -0,0 +1,531 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/dev_printk.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/errno.h>
> +#include <linux/export.h>
> +#include <linux/firmware.h>
> +#include <linux/firmware/imx/se_api.h>
> +#include <linux/genalloc.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/miscdevice.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_reserved_mem.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/sys_soc.h>
> +
> +#include "ele_base_msg.h"
> +#include "ele_common.h"
> +#include "se_ctrl.h"
> +
> +#define RESERVED_DMA_POOL BIT(0)
> +
> +struct imx_se_node_info {
> + u8 se_if_id;
> + u8 se_if_did;
> + u8 max_dev_ctx;
> + u8 cmd_tag;
> + u8 rsp_tag;
> + u8 success_tag;
> + u8 base_api_ver;
> + u8 fw_api_ver;
> + u8 *se_name;
> + u8 *mbox_tx_name;
> + u8 *mbox_rx_name;
> + u8 *pool_name;
> + u8 *fw_name_in_rfs;
> + bool soc_register;
> + bool reserved_dma_ranges;
> + bool imem_mgmt;
> + int (*se_fetch_soc_info)(struct device *dev, u16 *soc_rev, u64 *serial_num);
> +};
> +
> +struct imx_se_node_info_list {
> + u8 num_mu;
> + u16 soc_id;
> + struct imx_se_node_info info[];
> +};
> +
> +static const struct imx_se_node_info_list imx8ulp_info = {
> + .num_mu = 1,
> + .soc_id = SOC_ID_OF_IMX8ULP,
> + .info = {
> + {
> + .se_if_id = 2,
> + .se_if_did = 7,
> + .max_dev_ctx = 4,
> + .cmd_tag = 0x17,
> + .rsp_tag = 0xe1,
> + .success_tag = 0xd6,
> + .base_api_ver = MESSAGING_VERSION_6,
> + .fw_api_ver = MESSAGING_VERSION_7,
> + .se_name = "hsm1",
> + .mbox_tx_name = "tx",
> + .mbox_rx_name = "rx",
> + .pool_name = "sram",
> + .fw_name_in_rfs = IMX_ELE_FW_DIR
> + "mx8ulpa2ext-ahab-container.img",
> + .soc_register = true,
> + .reserved_dma_ranges = true,
> + .imem_mgmt = true,
> + .se_fetch_soc_info = ele_fetch_soc_info,
> + },
Indentation level is one too deep here.
> + },
> +};
> +
> +static const struct imx_se_node_info_list imx93_info = {
> + .num_mu = 1,
> + .soc_id = SOC_ID_OF_IMX93,
> + .info = {
> + {
> + .se_if_id = 2,
> + .se_if_did = 3,
> + .max_dev_ctx = 4,
> + .cmd_tag = 0x17,
> + .rsp_tag = 0xe1,
> + .success_tag = 0xd6,
> + .base_api_ver = MESSAGING_VERSION_6,
> + .fw_api_ver = MESSAGING_VERSION_7,
> + .se_name = "hsm1",
> + .mbox_tx_name = "tx",
> + .mbox_rx_name = "rx",
> + .reserved_dma_ranges = true,
> + .imem_mgmt = true,
> + .soc_register = true,
> + },
Drop all fields from this struct that are common to all currently
supported SoCs. You can always re-add them later when actually needed.
This will make your code easier to review.
> + },
> +};
> +
> +static const struct of_device_id se_match[] = {
> + { .compatible = "fsl,imx8ulp-ele", .data = (void *)&imx8ulp_info},
> + { .compatible = "fsl,imx93-ele", .data = (void *)&imx93_info},
> + {},
> +};
> +
> +static struct imx_se_node_info
> + *get_imx_se_node_info(struct imx_se_node_info_list *info_list,
> + const u32 idx)
> +{
> + if (idx > info_list->num_mu)
> + return NULL;
> +
> + return &info_list->info[idx];
> +}
> +
> +void *get_phy_buf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + dma_addr_t *buf,
> + u32 size)
> +{
> + struct device_node *of_node = dev->of_node;
> + struct gen_pool *mem_pool;
> +
> + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> + if (!mem_pool) {
> + dev_err(dev,
> + "Unable to get sram pool = %s\n",
> + mem_pool_name);
> + return 0;
> + }
> +
> + return gen_pool_dma_alloc(mem_pool, size, buf);
> +}
> +
> +void free_phybuf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + u32 *buf,
> + u32 size)
> +{
> + struct device_node *of_node = dev->of_node;
> + struct gen_pool *mem_pool;
> +
> + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> + if (!mem_pool)
> + dev_err(dev,
> + "%s: Failed: Unable to get sram pool.\n",
> + __func__);
> +
> + gen_pool_free(mem_pool, (u64)buf, size);
> +}
> +
> +static int imx_fetch_se_soc_info(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct imx_se_node_info_list *info_list;
> + const struct imx_se_node_info *info;
> + struct soc_device_attribute *attr;
> + struct soc_device *sdev;
> + u64 serial_num;
> + u16 soc_rev;
> + int err = 0;
> +
> + info = priv->info;
> + info_list = (struct imx_se_node_info_list *)
> + device_get_match_data(dev);
> +
> + /* This function should be called once.
> + * Check if the soc_rev is zero to continue.
> + */
> + if (priv->soc_rev)
> + return err;
> +
> + err = info->se_fetch_soc_info(dev, &soc_rev, &serial_num);
> + if (err < 0) {
> + dev_err(dev, "Failed to fetch SoC Info.");
> + return err;
> + }
> +
> + priv->soc_rev = soc_rev;
> + if (!info->soc_register)
> + return 0;
> +
> + attr = devm_kzalloc(dev, sizeof(*attr), GFP_KERNEL);
> + if (!attr)
> + return -ENOMEM;
> +
> + if (FIELD_GET(DEV_GETINFO_MIN_VER_MASK, soc_rev))
> + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x.%x",
> + FIELD_GET(DEV_GETINFO_MIN_VER_MASK,
> + soc_rev),
> + FIELD_GET(DEV_GETINFO_MAJ_VER_MASK,
> + soc_rev));
> + else
> + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x",
> + FIELD_GET(DEV_GETINFO_MAJ_VER_MASK,
> + soc_rev));
> +
> + switch (info_list->soc_id) {
> + case SOC_ID_OF_IMX8ULP:
> + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> + "i.MX8ULP");
> + break;
> + case SOC_ID_OF_IMX93:
> + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> + "i.MX93");
> + break;
> + }
> +
> + err = of_property_read_string(of_root, "model",
> + &attr->machine);
> + if (err)
> + return -EINVAL;
> +
> + attr->family = devm_kasprintf(dev, GFP_KERNEL, "Freescale i.MX");
> +
> + attr->serial_number
> + = devm_kasprintf(dev, GFP_KERNEL, "%016llX", serial_num);
> +
> + sdev = soc_device_register(attr);
> + if (IS_ERR(sdev))
> + return PTR_ERR(sdev);
> +
> + return 0;
> +}
> +
> +/* interface for managed res to free a mailbox channel */
> +static void if_mbox_free_channel(void *mbox_chan)
> +{
> + mbox_free_channel(mbox_chan);
> +}
> +
> +static int se_if_request_channel(struct device *dev,
> + struct mbox_chan **chan,
> + struct mbox_client *cl,
> + const char *name)
> +{
> + struct mbox_chan *t_chan;
> + int ret = 0;
> +
> + t_chan = mbox_request_channel_byname(cl, name);
> + if (IS_ERR(t_chan)) {
> + ret = PTR_ERR(t_chan);
> + return dev_err_probe(dev, ret,
> + "Failed to request %s channel.", name);
> + }
> +
> + ret = devm_add_action(dev, if_mbox_free_channel, t_chan);
> + if (ret) {
> + dev_err(dev, "failed to add devm removal of mbox %s\n", name);
> + goto exit;
> + }
> +
> + *chan = t_chan;
> +
> +exit:
> + return ret;
> +}
> +
> +static int se_probe_if_cleanup(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct se_if_priv *priv;
> + int ret = 0;
> +
> + priv = dev_get_drvdata(dev);
> + if (!priv) {
> + ret = 0;
> + dev_dbg(dev, "SE-MU Priv data is NULL;");
> + return ret;
> + }
This can't happen. Drop the check and let this function return void.
> +
> + if (priv->tx_chan)
> + mbox_free_channel(priv->tx_chan);
> + if (priv->rx_chan)
> + mbox_free_channel(priv->rx_chan);
> +
> + /* free the buffer in se remove, previously allocated
> + * in se probe to store encrypted IMEM
> + */
> + if (priv->imem.buf) {
> + dmam_free_coherent(dev,
> + ELE_IMEM_SIZE,
> + priv->imem.buf,
> + priv->imem.phyaddr);
> + priv->imem.buf = NULL;
> + }
> +
> + if (priv->flags & RESERVED_DMA_POOL) {
> + of_reserved_mem_device_release(dev);
> + priv->flags &= (~RESERVED_DMA_POOL);
> + }
> +
> + return ret;
> +}
> +
> +static void se_load_firmware(const struct firmware *fw, void *context)
> +{
> + struct se_if_priv *priv = (struct se_if_priv *) context;
> + const struct imx_se_node_info *info = priv->info;
> + const u8 *se_fw_name = info->fw_name_in_rfs;
> + phys_addr_t se_fw_phyaddr;
> + u8 *se_fw_buf;
> +
> + if (!fw) {
> + if (priv->fw_fail > MAX_FW_LOAD_RETRIES)
> + dev_dbg(priv->dev,
> + "External FW not found, using ROM FW.\n");
> + else {
> + /*add a bit delay to wait for firmware priv released */
> + msleep(20);
> +
> + /* Load firmware one more time if timeout */
> + request_firmware_nowait(THIS_MODULE,
> + FW_ACTION_UEVENT, info->fw_name_in_rfs,
> + priv->dev, GFP_KERNEL, priv,
> + se_load_firmware);
> + priv->fw_fail++;
> + dev_dbg(priv->dev, "Value of retries = 0x%x.\n",
> + priv->fw_fail);
> + }
What's the point of retrying this? It won't succeed when it failed once,
no?
Besides, calling request_firmware_nowait() in the completion callback of
that very same function looks strange.
> +
> + return;
> + }
> +
> + /* allocate buffer to store the SE FW */
> + se_fw_buf = dmam_alloc_coherent(priv->dev, fw->size,
> + &se_fw_phyaddr,
> + GFP_KERNEL);
Use unmanaged dma_alloc_coherent().
> + if (!se_fw_buf) {
> + dev_err(priv->dev, "Failed to alloc SE fw buffer memory\n");
> + goto exit;
No need to free it when you weren't able to allocate it.
> + }
> +
> + memcpy(se_fw_buf, fw->data, fw->size);
> +
> + if (ele_fw_authenticate(priv->dev, se_fw_phyaddr))
> + dev_err(priv->dev,
> + "Failed to authenticate & load SE firmware %s.\n",
> + se_fw_name);
> +
> +exit:
> + dmam_free_coherent(priv->dev,
> + fw->size,
> + se_fw_buf,
> + se_fw_phyaddr);
> +
> + release_firmware(fw);
> +}
> +
> +static int se_if_probe(struct platform_device *pdev)
> +{
> + struct imx_se_node_info_list *info_list;
> + struct device *dev = &pdev->dev;
> + struct imx_se_node_info *info;
> + struct se_if_priv *priv;
> + u32 idx;
> + int ret;
> +
> + if (of_property_read_u32(dev->of_node, "reg", &idx)) {
> + ret = -EINVAL;
> + goto exit;
> + }
> +
> + info_list = (struct imx_se_node_info_list *)
> + device_get_match_data(dev);
> + info = get_imx_se_node_info(info_list, idx);
get_imx_se_node_info() can return NULL. You should catch this here.
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv) {
> + ret = -ENOMEM;
> + goto exit;
> + }
> +
> + dev_set_drvdata(dev, priv);
> +
> + /* Mailbox client configuration */
> + priv->se_mb_cl.dev = dev;
> + priv->se_mb_cl.tx_block = false;
> + priv->se_mb_cl.knows_txdone = true;
> + priv->se_mb_cl.rx_callback = se_if_rx_callback;
> +
> + ret = se_if_request_channel(dev, &priv->tx_chan,
> + &priv->se_mb_cl, info->mbox_tx_name);
> + if (ret)
> + goto exit;
> +
> + ret = se_if_request_channel(dev, &priv->rx_chan,
> + &priv->se_mb_cl, info->mbox_rx_name);
> + if (ret)
> + goto exit;
> +
> + priv->dev = dev;
> + priv->info = info;
> +
> + /* Initialize the mutex. */
This comment doesn't provide any useful information.
> + mutex_init(&priv->se_if_lock);
> + mutex_init(&priv->se_if_cmd_lock);
> +
> + priv->cmd_receiver_dev = NULL;
> + priv->waiting_rsp_dev = NULL;
> + priv->max_dev_ctx = info->max_dev_ctx;
> + priv->cmd_tag = info->cmd_tag;
> + priv->rsp_tag = info->rsp_tag;
> + priv->mem_pool_name = info->pool_name;
> + priv->success_tag = info->success_tag;
> + priv->base_api_ver = info->base_api_ver;
> + priv->fw_api_ver = info->fw_api_ver;
> +
> + init_completion(&priv->done);
> + spin_lock_init(&priv->lock);
> +
> + if (info->reserved_dma_ranges) {
> + ret = of_reserved_mem_device_init(dev);
> + if (ret) {
> + dev_err(dev,
> + "failed to init reserved memory region %d\n",
> + ret);
> + priv->flags &= (~RESERVED_DMA_POOL);
priv->flags is still 0. You just allocated it.
> + goto exit;
> + }
> + priv->flags |= RESERVED_DMA_POOL;
> + }
> +
> + if (info->fw_name_in_rfs) {
> + ret = request_firmware_nowait(THIS_MODULE,
> + FW_ACTION_UEVENT,
> + info->fw_name_in_rfs,
> + dev, GFP_KERNEL, priv,
> + se_load_firmware);
> + if (ret)
> + dev_warn(dev, "Failed to get firmware [%s].\n",
> + info->fw_name_in_rfs);
> + }
> +
> + ret = imx_fetch_se_soc_info(dev);
> + if (ret) {
> + dev_err(dev,
> + "failed[%pe] to fetch SoC Info\n", ERR_PTR(ret));
> + goto exit;
> + }
> +
> + if (info->imem_mgmt) {
> + /* allocate buffer where SE store encrypted IMEM */
> + priv->imem.buf = dmam_alloc_coherent(dev, ELE_IMEM_SIZE,
> + &priv->imem.phyaddr,
> + GFP_KERNEL);
> + if (!priv->imem.buf) {
> + dev_err(dev,
> + "dmam-alloc-failed: To store encr-IMEM.\n");
> + ret = -ENOMEM;
> + goto exit;
> + }
> + }
> +
> + dev_info(dev, "i.MX secure-enclave: %s interface to firmware, configured.\n",
> + info->se_name);
> + return devm_of_platform_populate(dev);
What is this good for?
> +
> +exit:
> + /* if execution control reaches here, if probe fails.
> + * hence doing the cleanup
> + */
> + if (se_probe_if_cleanup(pdev))
> + dev_err(dev,
> + "Failed to clean-up the child node probe.\n");
> +
> + return ret;
> +}
> +
> +static int se_remove(struct platform_device *pdev)
> +{
> + if (se_probe_if_cleanup(pdev))
> + dev_err(&pdev->dev,
> + "i.MX Secure Enclave is not cleanly un-probed.");
> +
> + return 0;
> +}
> +
> +static int se_suspend(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + const struct imx_se_node_info *info
> + = priv->info;
> +
> + if (info && info->imem_mgmt)
> + priv->imem.size = se_save_imem_state(dev);
imem.size has type u32. se_save_imem_state() might return an error code.
You use imem.size as third argument to ele_service_swap(). This looks
fishy.
> +
> + return 0;
> +}
> +
> +static int se_resume(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + const struct imx_se_node_info *info
> + = priv->info;
> +
> + if (info && info->imem_mgmt)
> + se_restore_imem_state(dev);
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops se_pm = {
> + RUNTIME_PM_OPS(se_suspend, se_resume, NULL)
> +};
> +
> +static struct platform_driver se_driver = {
> + .driver = {
> + .name = "fsl-se-fw",
> + .of_match_table = se_match,
> + .pm = &se_pm,
> + },
> + .probe = se_if_probe,
> + .remove = se_remove,
> +};
> +MODULE_DEVICE_TABLE(of, se_match);
> +
> +module_platform_driver(se_driver);
> +
> +MODULE_AUTHOR("Pankaj Gupta <pankaj.gupta@nxp.com>");
> +MODULE_DESCRIPTION("iMX Secure Enclave Driver.");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/firmware/imx/se_ctrl.h b/drivers/firmware/imx/se_ctrl.h
> new file mode 100644
> index 000000000000..7d4f439a6158
> --- /dev/null
> +++ b/drivers/firmware/imx/se_ctrl.h
> @@ -0,0 +1,99 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#ifndef SE_MU_H
> +#define SE_MU_H
> +
> +#include <linux/miscdevice.h>
> +#include <linux/semaphore.h>
> +#include <linux/mailbox_client.h>
> +
> +#define MAX_FW_LOAD_RETRIES 50
> +
> +#define RES_STATUS(x) FIELD_GET(0x000000ff, x)
> +#define MESSAGING_VERSION_6 0x6
> +#define MESSAGING_VERSION_7 0x7
> +
> +struct se_imem_buf {
> + u8 *buf;
> + phys_addr_t phyaddr;
> + u32 size;
> +};
> +
> +/* Header of the messages exchange with the EdgeLock Enclave */
> +struct se_msg_hdr {
> + u8 ver;
> + u8 size;
> + u8 command;
> + u8 tag;
> +} __packed;
> +
> +#define SE_MU_HDR_SZ 4
> +
> +struct se_api_msg {
> + struct se_msg_hdr header;
> + u32 data[];
> +};
> +
> +struct se_if_priv {
> + struct se_if_device_ctx *cmd_receiver_dev;
> + /* Update to the waiting_rsp_dev, to be protected
> + * under se_if_lock.
> + */
> + struct se_if_device_ctx *waiting_rsp_dev;
> + /*
> + * prevent parallel access to the se interface registers
> + * e.g. a user trying to send a command while the other one is
> + * sending a response.
> + */
> + struct mutex se_if_lock;
> + /*
> + * prevent a command to be sent on the se interface while another one is
> + * still processing. (response to a command is allowed)
> + */
> + struct mutex se_if_cmd_lock;
> + struct device *dev;
> + u8 *mem_pool_name;
> + u8 cmd_tag;
> + u8 rsp_tag;
> + u8 success_tag;
> + u8 base_api_ver;
> + u8 fw_api_ver;
> + u32 fw_fail;
> + u16 soc_rev;
> + const void *info;
> +
> + struct mbox_client se_mb_cl;
> + struct mbox_chan *tx_chan, *rx_chan;
> +
> + /* Assignment of the rx_msg buffer to held till the
> + * received content as part callback function, is copied.
> + */
> + struct se_api_msg *rx_msg;
> + struct completion done;
> + spinlock_t lock;
> + /*
> + * Flag to retain the state of initialization done at
> + * the time of se-if probe.
> + */
> + uint32_t flags;
> + u8 max_dev_ctx;
> + struct se_if_device_ctx **ctxs;
> + struct se_imem_buf imem;
> +};
> +
> +void *get_phy_buf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + dma_addr_t *buf,
> + u32 size);
> +phys_addr_t get_phy_buf_mem_pool1(struct device *dev,
> + u8 *mem_pool_name,
> + u32 **buf,
> + u32 size);
This function is never defined.
> +void free_phybuf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + u32 *buf,
> + u32 size);
> +#endif
> diff --git a/include/linux/firmware/imx/se_api.h b/include/linux/firmware/imx/se_api.h
> new file mode 100644
> index 000000000000..c47f84906837
> --- /dev/null
> +++ b/include/linux/firmware/imx/se_api.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#ifndef __SE_API_H__
> +#define __SE_API_H__
> +
> +#include <linux/types.h>
> +
> +#define SOC_ID_OF_IMX8ULP 0x084D
> +#define SOC_ID_OF_IMX93 0x9300
> +
> +#endif /* __SE_API_H__ */
>
> --
> 2.34.1
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 14/17] irqchip/riscv-imsic: Add ACPI support
2024-05-01 12:17 3% ` [PATCH v5 14/17] irqchip/riscv-imsic: Add ACPI support Sunil V L
@ 2024-05-23 22:00 0% ` Thomas Gleixner
2024-05-27 4:52 0% ` Sunil V L
0 siblings, 1 reply; 200+ results
From: Thomas Gleixner @ 2024-05-23 22:00 UTC (permalink / raw)
To: Sunil V L, linux-arm-kernel, linux-kernel, linux-riscv,
linux-acpi, linux-pci, linux-serial, acpica-devel
Cc: Catalin Marinas, Will Deacon, Paul Walmsley, Albert Ou,
Rafael J . Wysocki, Len Brown, Bjorn Helgaas, Anup Patel,
Samuel Holland, Greg Kroah-Hartman, Jiri Slaby, Robert Moore,
Conor Dooley, Andrew Jones, Andy Shevchenko, Marc Zyngier,
Atish Kumar Patra, Andrei Warkentin, Haibo1 Xu,
Björn Töpel, Sunil V L
On Wed, May 01 2024 at 17:47, Sunil V L wrote:
> RISC-V IMSIC interrupt controller provides IPI and MSI support.
> Currently, DT based drivers setup the IPI feature early during boot but
> defer setting up the MSI functionality. However, in ACPI systems, ACPI,
> both IPI and MSI features need to be initialized early itself.
Why?
> +
> +#ifdef CONFIG_ACPI
> +
> +static struct fwnode_handle *imsic_acpi_fwnode;
> +
> +struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev)
Why is this function global? It's only used in the very same file and
under the same CONFIG_ACPI #ifdef, no?
> +{
> + return imsic_acpi_fwnode;
> +}
> +
> +static int __init imsic_early_acpi_init(union acpi_subtable_headers *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_imsic *imsic = (struct acpi_madt_imsic *)header;
> + int rc;
> +
> + imsic_acpi_fwnode = irq_domain_alloc_named_fwnode("imsic");
> + if (!imsic_acpi_fwnode) {
> + pr_err("unable to allocate IMSIC FW node\n");
> + return -ENOMEM;
> + }
> +
> + /* Setup IMSIC state */
> + rc = imsic_setup_state(imsic_acpi_fwnode, (void *)imsic);
Pointless (void *) cast.
> + if (rc) {
> + pr_err("%pfwP: failed to setup state (error %d)\n", imsic_acpi_fwnode, rc);
> + return rc;
> + }
> +
> + /* Do early setup of IMSIC state and IPIs */
> + rc = imsic_early_probe(imsic_acpi_fwnode);
> + if (rc)
> + return rc;
> +
> + rc = imsic_platform_acpi_probe(imsic_acpi_fwnode);
> +
> +#ifdef CONFIG_PCI
> + if (!rc)
> + pci_msi_register_fwnode_provider(&imsic_acpi_get_fwnode);
> +#endif
> +
> + return rc;
Any error return in this function leaks the firmware node and probably
some more stuff.
> +}
> +
> +IRQCHIP_ACPI_DECLARE(riscv_imsic, ACPI_MADT_TYPE_IMSIC, NULL,
> + 1, imsic_early_acpi_init);
> +#endif
...
> - /* Find number of interrupt identities */
> - rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids",
> - &global->nr_ids);
> - if (rc) {
> - pr_err("%pfwP: number of interrupt identities not found\n", fwnode);
> - return rc;
> + /* Find number of guest interrupt identities */
> + rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids",
> + &global->nr_guest_ids);
> + if (rc)
> + global->nr_guest_ids = global->nr_ids;
> + } else {
> + global->guest_index_bits = imsic->guest_index_bits;
> + global->hart_index_bits = imsic->hart_index_bits;
> + global->group_index_bits = imsic->group_index_bits;
> + global->group_index_shift = imsic->group_index_shift;
> + global->nr_ids = imsic->num_ids;
> + global->nr_guest_ids = imsic->num_guest_ids;
> }
Seriously?
Why can't you just split out the existing DT code into a separate
function in an initial patch which avoulds all of this unreviewable
churn of making the DT stuff indented ?
> +#ifdef CONFIG_ACPI
> +int imsic_platform_acpi_probe(struct fwnode_handle *fwnode);
> +struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev);
> +#else
> +static inline struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev)
> +{
> + return NULL;
> +}
> +#endif
Oh well.
> #endif
Thanks,
tglx
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^ permalink raw reply [relevance 0%]
* [PATCH v2 4/5] firmware: imx: add driver for NXP EdgeLock Enclave
@ 2024-05-23 10:49 3% ` Pankaj Gupta
2024-05-24 9:07 0% ` Sascha Hauer
0 siblings, 1 reply; 200+ results
From: Pankaj Gupta @ 2024-05-23 10:49 UTC (permalink / raw)
To: Jonathan Corbet, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski
Cc: linux-doc, linux-kernel, devicetree, imx, linux-arm-kernel, Pankaj Gupta
NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE),
are embedded in the SoC to support the features like HSM, SHE & V2X,
using message based communication interface.
The secure enclave FW communicates on a dedicated messaging unit(MU)
based interface(s) with application core, where kernel is running.
It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
This patch adds the driver for communication interface to secure-enclave,
for exchanging messages with NXP secure enclave HW IP(s) like EdgeLock
Enclave (ELE) from Kernel-space, used by kernel management layers like
- DM-Crypt.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
---
drivers/firmware/imx/Kconfig | 12 +
drivers/firmware/imx/Makefile | 2 +
drivers/firmware/imx/ele_base_msg.c | 286 +++++++++++++++++++
drivers/firmware/imx/ele_base_msg.h | 92 +++++++
drivers/firmware/imx/ele_common.c | 239 ++++++++++++++++
drivers/firmware/imx/ele_common.h | 43 +++
drivers/firmware/imx/se_ctrl.c | 531 ++++++++++++++++++++++++++++++++++++
drivers/firmware/imx/se_ctrl.h | 99 +++++++
include/linux/firmware/imx/se_api.h | 14 +
9 files changed, 1318 insertions(+)
diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
index 183613f82a11..56bdca9bd917 100644
--- a/drivers/firmware/imx/Kconfig
+++ b/drivers/firmware/imx/Kconfig
@@ -22,3 +22,15 @@ config IMX_SCU
This driver manages the IPC interface between host CPU and the
SCU firmware running on M4.
+
+config IMX_SEC_ENCLAVE
+ tristate "i.MX Embedded Secure Enclave - EdgeLock Enclave Firmware driver."
+ depends on IMX_MBOX && ARCH_MXC && ARM64
+ default m if ARCH_MXC
+
+ help
+ It is possible to use APIs exposed by the iMX Secure Enclave HW IP called:
+ - EdgeLock Enclave Firmware (for i.MX8ULP, i.MX93),
+ like base, HSM, V2X & SHE using the SAB protocol via the shared Messaging
+ Unit. This driver exposes these interfaces via a set of file descriptors
+ allowing to configure shared memory, send and receive messages.
diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile
index 8f9f04a513a8..aa9033e0e9e3 100644
--- a/drivers/firmware/imx/Makefile
+++ b/drivers/firmware/imx/Makefile
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_IMX_DSP) += imx-dsp.o
obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o
+sec_enclave-objs = se_ctrl.o ele_common.o ele_base_msg.o
+obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele_base_msg.c
new file mode 100644
index 000000000000..f072c613dba1
--- /dev/null
+++ b/drivers/firmware/imx/ele_base_msg.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/types.h>
+#include <linux/completion.h>
+#include <linux/dma-mapping.h>
+
+#include "ele_base_msg.h"
+#include "ele_common.h"
+
+int ele_get_info(struct device *dev, struct ele_dev_info *s_info)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ struct se_api_msg *tx_msg __free(kfree) = NULL;
+ struct se_api_msg *rx_msg __free(kfree) = NULL;
+ phys_addr_t get_info_addr = 0;
+ u32 *get_info_data = NULL;
+ u32 status;
+ int ret = 0;
+
+ memset(s_info, 0x0, sizeof(*s_info));
+
+ if (priv->mem_pool_name)
+ get_info_data = get_phy_buf_mem_pool(dev,
+ priv->mem_pool_name,
+ &get_info_addr,
+ ELE_GET_INFO_BUFF_SZ);
+ else
+ get_info_data = dma_alloc_coherent(dev,
+ ELE_GET_INFO_BUFF_SZ,
+ &get_info_addr,
+ GFP_KERNEL);
+ if (!get_info_data) {
+ ret = -ENOMEM;
+ dev_dbg(dev,
+ "%s: Failed to allocate get_info_addr.\n",
+ __func__);
+ goto exit;
+ }
+
+ tx_msg = kzalloc(ELE_GET_INFO_REQ_MSG_SZ, GFP_KERNEL);
+ if (!tx_msg) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ rx_msg = kzalloc(ELE_GET_INFO_RSP_MSG_SZ, GFP_KERNEL);
+ if (!rx_msg) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct se_msg_hdr *)&tx_msg->header,
+ ELE_GET_INFO_REQ,
+ ELE_GET_INFO_REQ_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ tx_msg->data[0] = upper_32_bits(get_info_addr);
+ tx_msg->data[1] = lower_32_bits(get_info_addr);
+ tx_msg->data[2] = sizeof(struct ele_dev_info);
+ ret = imx_ele_msg_send_rcv(priv, tx_msg, rx_msg);
+ if (ret < 0)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ &priv->rx_msg->header,
+ ELE_GET_INFO_REQ,
+ ELE_GET_INFO_RSP_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_GET_INFO_REQ, status);
+ ret = -EPERM;
+ }
+
+ memcpy(s_info, get_info_data, sizeof(struct ele_dev_info));
+
+exit:
+ if (get_info_addr) {
+ if (priv->mem_pool_name)
+ free_phybuf_mem_pool(dev, priv->mem_pool_name,
+ get_info_data, ELE_GET_INFO_BUFF_SZ);
+ else
+ dma_free_coherent(dev,
+ ELE_GET_INFO_BUFF_SZ,
+ get_info_data,
+ get_info_addr);
+ }
+
+ return ret;
+}
+
+int ele_fetch_soc_info(struct device *dev, u16 *soc_rev, u64 *serial_num)
+{
+ struct ele_dev_info s_info = {0};
+ int err = 0;
+
+ err = ele_get_info(dev, &s_info);
+ if (err < 0) {
+ dev_err(dev, "Error");
+ return err;
+ }
+
+ *soc_rev = s_info.d_info.soc_rev;
+ *serial_num = GET_SERIAL_NUM_FROM_UID(s_info.d_info.uid, MAX_UID_SIZE >> 2);
+
+ return err;
+}
+
+int ele_ping(struct device *dev)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ struct se_api_msg *tx_msg __free(kfree) = NULL;
+ struct se_api_msg *rx_msg __free(kfree) = NULL;
+ u32 status;
+ int ret = 0;
+
+ tx_msg = kzalloc(ELE_PING_REQ_SZ, GFP_KERNEL);
+ if (!tx_msg) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ rx_msg = kzalloc(ELE_PING_RSP_SZ, GFP_KERNEL);
+ if (!rx_msg) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct se_msg_hdr *)&tx_msg->header,
+ ELE_PING_REQ, ELE_PING_REQ_SZ,
+ true);
+ if (ret) {
+ dev_err(dev, "Error: plat_fill_cmd_msg_hdr failed.\n");
+ goto exit;
+ }
+
+ ret = imx_ele_msg_send_rcv(priv, tx_msg, rx_msg);
+ if (ret)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ &priv->rx_msg->header,
+ ELE_PING_REQ,
+ ELE_PING_RSP_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_PING_REQ, status);
+ ret = -EPERM;
+ }
+exit:
+ return ret;
+}
+
+int ele_service_swap(struct device *dev,
+ phys_addr_t addr,
+ u32 addr_size, u16 flag)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ struct se_api_msg *tx_msg __free(kfree) = NULL;
+ struct se_api_msg *rx_msg __free(kfree) = NULL;
+ u32 status;
+ int ret = 0;
+
+ tx_msg = kzalloc(ELE_SERVICE_SWAP_REQ_MSG_SZ, GFP_KERNEL);
+ if (!tx_msg) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ rx_msg = kzalloc(ELE_SERVICE_SWAP_RSP_MSG_SZ, GFP_KERNEL);
+ if (!rx_msg) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct se_msg_hdr *)&tx_msg->header,
+ ELE_SERVICE_SWAP_REQ,
+ ELE_SERVICE_SWAP_REQ_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ tx_msg->data[0] = flag;
+ tx_msg->data[1] = addr_size;
+ tx_msg->data[2] = ELE_NONE_VAL;
+ tx_msg->data[3] = lower_32_bits(addr);
+ tx_msg->data[4] = plat_add_msg_crc((uint32_t *)&tx_msg[0],
+ ELE_SERVICE_SWAP_REQ_MSG_SZ);
+ ret = imx_ele_msg_send_rcv(priv, tx_msg, rx_msg);
+ if (ret < 0)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ &priv->rx_msg->header,
+ ELE_SERVICE_SWAP_REQ,
+ ELE_SERVICE_SWAP_RSP_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_SERVICE_SWAP_REQ, status);
+ ret = -EPERM;
+ } else {
+ if (flag == ELE_IMEM_EXPORT)
+ ret = priv->rx_msg->data[1];
+ else
+ ret = 0;
+ }
+exit:
+
+ return ret;
+}
+
+int ele_fw_authenticate(struct device *dev, phys_addr_t addr)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ struct se_api_msg *tx_msg __free(kfree) = NULL;
+ struct se_api_msg *rx_msg __free(kfree) = NULL;
+ u32 status;
+ int ret = 0;
+
+ tx_msg = kzalloc(ELE_FW_AUTH_REQ_SZ, GFP_KERNEL);
+ if (!tx_msg) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ rx_msg = kzalloc(ELE_FW_AUTH_RSP_MSG_SZ, GFP_KERNEL);
+ if (!rx_msg) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct se_msg_hdr *)&tx_msg->header,
+ ELE_FW_AUTH_REQ,
+ ELE_FW_AUTH_REQ_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ tx_msg->data[0] = addr;
+ tx_msg->data[1] = addr >> 32;
+ tx_msg->data[2] = addr;
+
+ ret = imx_ele_msg_send_rcv(priv, tx_msg, rx_msg);
+ if (ret < 0)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ &priv->rx_msg->header,
+ ELE_FW_AUTH_REQ,
+ ELE_FW_AUTH_RSP_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_FW_AUTH_REQ, status);
+ ret = -EPERM;
+ }
+exit:
+
+ return ret;
+}
diff --git a/drivers/firmware/imx/ele_base_msg.h b/drivers/firmware/imx/ele_base_msg.h
new file mode 100644
index 000000000000..f00414f9d86d
--- /dev/null
+++ b/drivers/firmware/imx/ele_base_msg.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ *
+ * Header file for the EdgeLock Enclave Base API(s).
+ */
+
+#ifndef ELE_BASE_MSG_H
+#define ELE_BASE_MSG_H
+
+#include <linux/device.h>
+#include <linux/types.h>
+
+#define WORD_SZ 4
+#define ELE_NONE_VAL 0x0
+
+#define ELE_SUCCESS_IND 0xD6
+
+#define ELE_GET_INFO_REQ 0xDA
+#define ELE_GET_INFO_REQ_MSG_SZ 0x10
+#define ELE_GET_INFO_RSP_MSG_SZ 0x08
+
+#define ELE_GET_INFO_BUFF_SZ 0x100
+
+#define DEFAULT_IMX_SOC_VER 0xA000
+#define SOC_VER_MASK 0xFFFF0000
+#define SOC_ID_MASK 0x0000FFFF
+
+#define MAX_UID_SIZE (16)
+#define DEV_GETINFO_ROM_PATCH_SHA_SZ (32)
+#define DEV_GETINFO_FW_SHA_SZ (32)
+#define DEV_GETINFO_OEM_SRKH_SZ (64)
+#define DEV_GETINFO_MIN_VER_MASK 0xFF
+#define DEV_GETINFO_MAJ_VER_MASK 0xFF00
+
+struct dev_info {
+ uint8_t cmd;
+ uint8_t ver;
+ uint16_t length;
+ uint16_t soc_id;
+ uint16_t soc_rev;
+ uint16_t lmda_val;
+ uint8_t ssm_state;
+ uint8_t dev_atts_api_ver;
+ uint8_t uid[MAX_UID_SIZE];
+ uint8_t sha_rom_patch[DEV_GETINFO_ROM_PATCH_SHA_SZ];
+ uint8_t sha_fw[DEV_GETINFO_FW_SHA_SZ];
+};
+
+struct dev_addn_info {
+ uint8_t oem_srkh[DEV_GETINFO_OEM_SRKH_SZ];
+ uint8_t trng_state;
+ uint8_t csal_state;
+ uint8_t imem_state;
+ uint8_t reserved2;
+};
+
+struct ele_dev_info {
+ struct dev_info d_info;
+ struct dev_addn_info d_addn_info;
+};
+
+#define GET_SERIAL_NUM_FROM_UID(x, uid_word_sz) \
+ (((u64)(((u32 *)(x))[(uid_word_sz) - 1]) << 32) | ((u32 *)(x))[0])
+
+#define ELE_PING_REQ 0x01
+#define ELE_PING_REQ_SZ 0x04
+#define ELE_PING_RSP_SZ 0x08
+
+#define ELE_SERVICE_SWAP_REQ 0xDF
+#define ELE_SERVICE_SWAP_REQ_MSG_SZ 0x18
+#define ELE_SERVICE_SWAP_RSP_MSG_SZ 0x0C
+#define ELE_IMEM_SIZE 0x10000
+#define ELE_IMEM_STATE_OK 0xCA
+#define ELE_IMEM_STATE_BAD 0xFE
+#define ELE_IMEM_STATE_WORD 0x27
+#define ELE_IMEM_STATE_MASK 0x00ff0000
+#define ELE_IMEM_EXPORT 0x1
+#define ELE_IMEM_IMPORT 0x2
+
+#define ELE_FW_AUTH_REQ 0x02
+#define ELE_FW_AUTH_REQ_SZ 0x10
+#define ELE_FW_AUTH_RSP_MSG_SZ 0x08
+
+int ele_get_info(struct device *dev, struct ele_dev_info *s_info);
+int ele_fetch_soc_info(struct device *dev, u16 *soc_rev, u64 *serial_num);
+int ele_ping(struct device *dev);
+int ele_service_swap(struct device *dev,
+ phys_addr_t addr,
+ u32 addr_size, u16 flag);
+int ele_fw_authenticate(struct device *dev, phys_addr_t addr);
+#endif
diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_common.c
new file mode 100644
index 000000000000..c286c3d84d82
--- /dev/null
+++ b/drivers/firmware/imx/ele_common.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "ele_base_msg.h"
+#include "ele_common.h"
+
+u32 plat_add_msg_crc(u32 *msg, u32 msg_len)
+{
+ u32 nb_words = msg_len / (u32)sizeof(u32);
+ u32 crc = 0;
+ u32 i;
+
+ for (i = 0; i < nb_words - 1; i++)
+ crc ^= *(msg + i);
+
+ return crc;
+}
+
+int imx_ele_msg_rcv(struct se_if_priv *priv)
+{
+ u32 wait;
+ int err = 0;
+
+ lockdep_assert_held(&priv->se_if_cmd_lock);
+
+ wait = msecs_to_jiffies(1000);
+ if (!wait_for_completion_timeout(&priv->done, wait)) {
+ dev_err(priv->dev,
+ "Error: wait_for_completion timed out.\n");
+ err = -ETIMEDOUT;
+ }
+
+ return err;
+}
+
+int imx_ele_msg_send(struct se_if_priv *priv, void *tx_msg)
+{
+ struct se_msg_hdr *header;
+ int err;
+
+ header = (struct se_msg_hdr *) tx_msg;
+
+ if (header->tag == priv->cmd_tag)
+ lockdep_assert_held(&priv->se_if_cmd_lock);
+
+ scoped_guard(mutex, &priv->se_if_lock);
+
+ err = mbox_send_message(priv->tx_chan, tx_msg);
+ if (err < 0) {
+ dev_err(priv->dev, "Error: mbox_send_message failure.\n");
+ return err;
+ }
+
+ return err;
+}
+
+/* API used for send/receive blocking call. */
+int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *tx_msg, void *rx_msg)
+{
+ int err;
+
+ scoped_guard(mutex, &priv->se_if_cmd_lock);
+ if (priv->waiting_rsp_dev) {
+ dev_warn(priv->dev,
+ "There should be no misc dev-ctx, waiting for resp.\n");
+ priv->waiting_rsp_dev = NULL;
+ }
+ priv->rx_msg = rx_msg;
+ err = imx_ele_msg_send(priv, tx_msg);
+ if (err < 0)
+ goto exit;
+
+ err = imx_ele_msg_rcv(priv);
+
+exit:
+ return err;
+}
+
+/*
+ * Callback called by mailbox FW, when data is received.
+ */
+void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg)
+{
+ struct device *dev = mbox_cl->dev;
+ struct se_if_priv *priv;
+ struct se_msg_hdr *header;
+
+ priv = dev_get_drvdata(dev);
+
+ /* The function can be called with NULL msg */
+ if (!msg) {
+ dev_err(dev, "Message is invalid\n");
+ return;
+ }
+
+ header = (struct se_msg_hdr *) msg;
+
+ if (header->tag == priv->rsp_tag) {
+ if (!priv->waiting_rsp_dev) {
+ /*
+ * Reading the EdgeLock Enclave response
+ * to the command, sent by other
+ * linux kernel services.
+ */
+ spin_lock(&priv->lock);
+ memcpy(priv->rx_msg, msg, header->size << 2);
+
+ complete(&priv->done);
+ spin_unlock(&priv->lock);
+ return;
+ }
+ } else {
+ dev_err(dev, "Failed to select a device for message: %.8x\n",
+ *((u32 *) header));
+ return;
+ }
+}
+
+int validate_rsp_hdr(struct se_if_priv *priv,
+ struct se_msg_hdr *header,
+ uint8_t msg_id,
+ uint8_t sz,
+ bool is_base_api)
+{
+ int ret = -EINVAL;
+
+ if (header->tag != priv->rsp_tag) {
+ dev_err(priv->dev,
+ "MSG[0x%x] Hdr: Resp tag mismatch. (0x%x != 0x%x)",
+ msg_id, header->tag, priv->rsp_tag);
+ return ret;
+ }
+
+ if (header->command != msg_id) {
+ dev_err(priv->dev,
+ "MSG Header: Cmd id mismatch. (0x%x != 0x%x)",
+ header->command, msg_id);
+ return ret;
+ }
+
+ if (header->size != (sz >> 2)) {
+ dev_err(priv->dev,
+ "MSG[0x%x] Hdr: Cmd size mismatch. (0x%x != 0x%x)",
+ msg_id, header->size, (sz >> 2));
+ return ret;
+ }
+
+ if (is_base_api && (header->ver != priv->base_api_ver)) {
+ dev_err(priv->dev,
+ "MSG[0x%x] Hdr: Base API Vers mismatch. (0x%x != 0x%x)",
+ msg_id, header->ver, priv->base_api_ver);
+ return ret;
+ } else if (!is_base_api && header->ver != priv->fw_api_ver) {
+ dev_err(priv->dev,
+ "MSG[0x%x] Hdr: FW API Vers mismatch. (0x%x != 0x%x)",
+ msg_id, header->ver, priv->fw_api_ver);
+ return ret;
+ }
+
+ ret = 0;
+
+ return ret;
+}
+
+int se_save_imem_state(struct device *dev)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ int ret;
+
+ /* EXPORT command will save encrypted IMEM to given address,
+ * so later in resume, IMEM can be restored from the given
+ * address.
+ *
+ * Size must be at least 64 kB.
+ */
+ ret = ele_service_swap(dev,
+ priv->imem.phyaddr,
+ ELE_IMEM_SIZE,
+ ELE_IMEM_EXPORT);
+ if (ret < 0)
+ dev_err(dev, "Failed to export IMEM\n");
+ else
+ dev_info(dev,
+ "Exported %d bytes of encrypted IMEM\n",
+ ret);
+
+ return ret;
+}
+
+int se_restore_imem_state(struct device *dev)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ struct ele_dev_info s_info;
+ int ret;
+
+ /* get info from ELE */
+ ret = ele_get_info(dev, &s_info);
+ if (ret) {
+ dev_err(dev, "Failed to get info from ELE.\n");
+ return ret;
+ }
+
+ /* Get IMEM state, if 0xFE then import IMEM */
+ if (s_info.d_addn_info.imem_state == ELE_IMEM_STATE_BAD) {
+ /* IMPORT command will restore IMEM from the given
+ * address, here size is the actual size returned by ELE
+ * during the export operation
+ */
+ ret = ele_service_swap(dev,
+ priv->imem.phyaddr,
+ priv->imem.size,
+ ELE_IMEM_IMPORT);
+ if (ret) {
+ dev_err(dev, "Failed to import IMEM\n");
+ goto exit;
+ }
+ } else
+ goto exit;
+
+ /* After importing IMEM, check if IMEM state is equal to 0xCA
+ * to ensure IMEM is fully loaded and
+ * ELE functionality can be used.
+ */
+ ret = ele_get_info(dev, &s_info);
+ if (ret) {
+ dev_err(dev, "Failed to get info from ELE.\n");
+ goto exit;
+ }
+
+ if (s_info.d_addn_info.imem_state == ELE_IMEM_STATE_OK)
+ dev_info(dev, "Successfully restored IMEM\n");
+ else
+ dev_err(dev, "Failed to restore IMEM\n");
+
+exit:
+ return ret;
+}
diff --git a/drivers/firmware/imx/ele_common.h b/drivers/firmware/imx/ele_common.h
new file mode 100644
index 000000000000..76777ac629d6
--- /dev/null
+++ b/drivers/firmware/imx/ele_common.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+
+#ifndef __ELE_COMMON_H__
+#define __ELE_COMMON_H__
+
+#include "se_ctrl.h"
+
+#define IMX_ELE_FW_DIR "imx/ele/"
+
+uint32_t plat_add_msg_crc(uint32_t *msg, uint32_t msg_len);
+int imx_ele_msg_rcv(struct se_if_priv *priv);
+int imx_ele_msg_send(struct se_if_priv *priv, void *tx_msg);
+int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *tx_msg, void *rx_msg);
+void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg);
+int validate_rsp_hdr(struct se_if_priv *priv,
+ struct se_msg_hdr *header,
+ uint8_t msg_id,
+ uint8_t sz,
+ bool is_base_api);
+
+/* Fill a command message header with a given command ID and length in bytes. */
+static inline int plat_fill_cmd_msg_hdr(struct se_if_priv *priv,
+ struct se_msg_hdr *hdr,
+ u8 cmd,
+ u32 len,
+ bool is_base_api)
+{
+ hdr->tag = priv->cmd_tag;
+ hdr->ver = (is_base_api) ? priv->base_api_ver : priv->fw_api_ver;
+ hdr->command = cmd;
+ hdr->size = len >> 2;
+
+ return 0;
+}
+
+int se_save_imem_state(struct device *dev);
+int se_restore_imem_state(struct device *dev);
+
+#endif /*__ELE_COMMON_H__ */
diff --git a/drivers/firmware/imx/se_ctrl.c b/drivers/firmware/imx/se_ctrl.c
new file mode 100644
index 000000000000..0642d349b3d3
--- /dev/null
+++ b/drivers/firmware/imx/se_ctrl.c
@@ -0,0 +1,531 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/dev_printk.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <linux/export.h>
+#include <linux/firmware.h>
+#include <linux/firmware/imx/se_api.h>
+#include <linux/genalloc.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/miscdevice.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/sys_soc.h>
+
+#include "ele_base_msg.h"
+#include "ele_common.h"
+#include "se_ctrl.h"
+
+#define RESERVED_DMA_POOL BIT(0)
+
+struct imx_se_node_info {
+ u8 se_if_id;
+ u8 se_if_did;
+ u8 max_dev_ctx;
+ u8 cmd_tag;
+ u8 rsp_tag;
+ u8 success_tag;
+ u8 base_api_ver;
+ u8 fw_api_ver;
+ u8 *se_name;
+ u8 *mbox_tx_name;
+ u8 *mbox_rx_name;
+ u8 *pool_name;
+ u8 *fw_name_in_rfs;
+ bool soc_register;
+ bool reserved_dma_ranges;
+ bool imem_mgmt;
+ int (*se_fetch_soc_info)(struct device *dev, u16 *soc_rev, u64 *serial_num);
+};
+
+struct imx_se_node_info_list {
+ u8 num_mu;
+ u16 soc_id;
+ struct imx_se_node_info info[];
+};
+
+static const struct imx_se_node_info_list imx8ulp_info = {
+ .num_mu = 1,
+ .soc_id = SOC_ID_OF_IMX8ULP,
+ .info = {
+ {
+ .se_if_id = 2,
+ .se_if_did = 7,
+ .max_dev_ctx = 4,
+ .cmd_tag = 0x17,
+ .rsp_tag = 0xe1,
+ .success_tag = 0xd6,
+ .base_api_ver = MESSAGING_VERSION_6,
+ .fw_api_ver = MESSAGING_VERSION_7,
+ .se_name = "hsm1",
+ .mbox_tx_name = "tx",
+ .mbox_rx_name = "rx",
+ .pool_name = "sram",
+ .fw_name_in_rfs = IMX_ELE_FW_DIR
+ "mx8ulpa2ext-ahab-container.img",
+ .soc_register = true,
+ .reserved_dma_ranges = true,
+ .imem_mgmt = true,
+ .se_fetch_soc_info = ele_fetch_soc_info,
+ },
+ },
+};
+
+static const struct imx_se_node_info_list imx93_info = {
+ .num_mu = 1,
+ .soc_id = SOC_ID_OF_IMX93,
+ .info = {
+ {
+ .se_if_id = 2,
+ .se_if_did = 3,
+ .max_dev_ctx = 4,
+ .cmd_tag = 0x17,
+ .rsp_tag = 0xe1,
+ .success_tag = 0xd6,
+ .base_api_ver = MESSAGING_VERSION_6,
+ .fw_api_ver = MESSAGING_VERSION_7,
+ .se_name = "hsm1",
+ .mbox_tx_name = "tx",
+ .mbox_rx_name = "rx",
+ .reserved_dma_ranges = true,
+ .imem_mgmt = true,
+ .soc_register = true,
+ },
+ },
+};
+
+static const struct of_device_id se_match[] = {
+ { .compatible = "fsl,imx8ulp-ele", .data = (void *)&imx8ulp_info},
+ { .compatible = "fsl,imx93-ele", .data = (void *)&imx93_info},
+ {},
+};
+
+static struct imx_se_node_info
+ *get_imx_se_node_info(struct imx_se_node_info_list *info_list,
+ const u32 idx)
+{
+ if (idx > info_list->num_mu)
+ return NULL;
+
+ return &info_list->info[idx];
+}
+
+void *get_phy_buf_mem_pool(struct device *dev,
+ u8 *mem_pool_name,
+ dma_addr_t *buf,
+ u32 size)
+{
+ struct device_node *of_node = dev->of_node;
+ struct gen_pool *mem_pool;
+
+ mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
+ if (!mem_pool) {
+ dev_err(dev,
+ "Unable to get sram pool = %s\n",
+ mem_pool_name);
+ return 0;
+ }
+
+ return gen_pool_dma_alloc(mem_pool, size, buf);
+}
+
+void free_phybuf_mem_pool(struct device *dev,
+ u8 *mem_pool_name,
+ u32 *buf,
+ u32 size)
+{
+ struct device_node *of_node = dev->of_node;
+ struct gen_pool *mem_pool;
+
+ mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
+ if (!mem_pool)
+ dev_err(dev,
+ "%s: Failed: Unable to get sram pool.\n",
+ __func__);
+
+ gen_pool_free(mem_pool, (u64)buf, size);
+}
+
+static int imx_fetch_se_soc_info(struct device *dev)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ struct imx_se_node_info_list *info_list;
+ const struct imx_se_node_info *info;
+ struct soc_device_attribute *attr;
+ struct soc_device *sdev;
+ u64 serial_num;
+ u16 soc_rev;
+ int err = 0;
+
+ info = priv->info;
+ info_list = (struct imx_se_node_info_list *)
+ device_get_match_data(dev);
+
+ /* This function should be called once.
+ * Check if the soc_rev is zero to continue.
+ */
+ if (priv->soc_rev)
+ return err;
+
+ err = info->se_fetch_soc_info(dev, &soc_rev, &serial_num);
+ if (err < 0) {
+ dev_err(dev, "Failed to fetch SoC Info.");
+ return err;
+ }
+
+ priv->soc_rev = soc_rev;
+ if (!info->soc_register)
+ return 0;
+
+ attr = devm_kzalloc(dev, sizeof(*attr), GFP_KERNEL);
+ if (!attr)
+ return -ENOMEM;
+
+ if (FIELD_GET(DEV_GETINFO_MIN_VER_MASK, soc_rev))
+ attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x.%x",
+ FIELD_GET(DEV_GETINFO_MIN_VER_MASK,
+ soc_rev),
+ FIELD_GET(DEV_GETINFO_MAJ_VER_MASK,
+ soc_rev));
+ else
+ attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x",
+ FIELD_GET(DEV_GETINFO_MAJ_VER_MASK,
+ soc_rev));
+
+ switch (info_list->soc_id) {
+ case SOC_ID_OF_IMX8ULP:
+ attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
+ "i.MX8ULP");
+ break;
+ case SOC_ID_OF_IMX93:
+ attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
+ "i.MX93");
+ break;
+ }
+
+ err = of_property_read_string(of_root, "model",
+ &attr->machine);
+ if (err)
+ return -EINVAL;
+
+ attr->family = devm_kasprintf(dev, GFP_KERNEL, "Freescale i.MX");
+
+ attr->serial_number
+ = devm_kasprintf(dev, GFP_KERNEL, "%016llX", serial_num);
+
+ sdev = soc_device_register(attr);
+ if (IS_ERR(sdev))
+ return PTR_ERR(sdev);
+
+ return 0;
+}
+
+/* interface for managed res to free a mailbox channel */
+static void if_mbox_free_channel(void *mbox_chan)
+{
+ mbox_free_channel(mbox_chan);
+}
+
+static int se_if_request_channel(struct device *dev,
+ struct mbox_chan **chan,
+ struct mbox_client *cl,
+ const char *name)
+{
+ struct mbox_chan *t_chan;
+ int ret = 0;
+
+ t_chan = mbox_request_channel_byname(cl, name);
+ if (IS_ERR(t_chan)) {
+ ret = PTR_ERR(t_chan);
+ return dev_err_probe(dev, ret,
+ "Failed to request %s channel.", name);
+ }
+
+ ret = devm_add_action(dev, if_mbox_free_channel, t_chan);
+ if (ret) {
+ dev_err(dev, "failed to add devm removal of mbox %s\n", name);
+ goto exit;
+ }
+
+ *chan = t_chan;
+
+exit:
+ return ret;
+}
+
+static int se_probe_if_cleanup(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct se_if_priv *priv;
+ int ret = 0;
+
+ priv = dev_get_drvdata(dev);
+ if (!priv) {
+ ret = 0;
+ dev_dbg(dev, "SE-MU Priv data is NULL;");
+ return ret;
+ }
+
+ if (priv->tx_chan)
+ mbox_free_channel(priv->tx_chan);
+ if (priv->rx_chan)
+ mbox_free_channel(priv->rx_chan);
+
+ /* free the buffer in se remove, previously allocated
+ * in se probe to store encrypted IMEM
+ */
+ if (priv->imem.buf) {
+ dmam_free_coherent(dev,
+ ELE_IMEM_SIZE,
+ priv->imem.buf,
+ priv->imem.phyaddr);
+ priv->imem.buf = NULL;
+ }
+
+ if (priv->flags & RESERVED_DMA_POOL) {
+ of_reserved_mem_device_release(dev);
+ priv->flags &= (~RESERVED_DMA_POOL);
+ }
+
+ return ret;
+}
+
+static void se_load_firmware(const struct firmware *fw, void *context)
+{
+ struct se_if_priv *priv = (struct se_if_priv *) context;
+ const struct imx_se_node_info *info = priv->info;
+ const u8 *se_fw_name = info->fw_name_in_rfs;
+ phys_addr_t se_fw_phyaddr;
+ u8 *se_fw_buf;
+
+ if (!fw) {
+ if (priv->fw_fail > MAX_FW_LOAD_RETRIES)
+ dev_dbg(priv->dev,
+ "External FW not found, using ROM FW.\n");
+ else {
+ /*add a bit delay to wait for firmware priv released */
+ msleep(20);
+
+ /* Load firmware one more time if timeout */
+ request_firmware_nowait(THIS_MODULE,
+ FW_ACTION_UEVENT, info->fw_name_in_rfs,
+ priv->dev, GFP_KERNEL, priv,
+ se_load_firmware);
+ priv->fw_fail++;
+ dev_dbg(priv->dev, "Value of retries = 0x%x.\n",
+ priv->fw_fail);
+ }
+
+ return;
+ }
+
+ /* allocate buffer to store the SE FW */
+ se_fw_buf = dmam_alloc_coherent(priv->dev, fw->size,
+ &se_fw_phyaddr,
+ GFP_KERNEL);
+ if (!se_fw_buf) {
+ dev_err(priv->dev, "Failed to alloc SE fw buffer memory\n");
+ goto exit;
+ }
+
+ memcpy(se_fw_buf, fw->data, fw->size);
+
+ if (ele_fw_authenticate(priv->dev, se_fw_phyaddr))
+ dev_err(priv->dev,
+ "Failed to authenticate & load SE firmware %s.\n",
+ se_fw_name);
+
+exit:
+ dmam_free_coherent(priv->dev,
+ fw->size,
+ se_fw_buf,
+ se_fw_phyaddr);
+
+ release_firmware(fw);
+}
+
+static int se_if_probe(struct platform_device *pdev)
+{
+ struct imx_se_node_info_list *info_list;
+ struct device *dev = &pdev->dev;
+ struct imx_se_node_info *info;
+ struct se_if_priv *priv;
+ u32 idx;
+ int ret;
+
+ if (of_property_read_u32(dev->of_node, "reg", &idx)) {
+ ret = -EINVAL;
+ goto exit;
+ }
+
+ info_list = (struct imx_se_node_info_list *)
+ device_get_match_data(dev);
+ info = get_imx_se_node_info(info_list, idx);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ dev_set_drvdata(dev, priv);
+
+ /* Mailbox client configuration */
+ priv->se_mb_cl.dev = dev;
+ priv->se_mb_cl.tx_block = false;
+ priv->se_mb_cl.knows_txdone = true;
+ priv->se_mb_cl.rx_callback = se_if_rx_callback;
+
+ ret = se_if_request_channel(dev, &priv->tx_chan,
+ &priv->se_mb_cl, info->mbox_tx_name);
+ if (ret)
+ goto exit;
+
+ ret = se_if_request_channel(dev, &priv->rx_chan,
+ &priv->se_mb_cl, info->mbox_rx_name);
+ if (ret)
+ goto exit;
+
+ priv->dev = dev;
+ priv->info = info;
+
+ /* Initialize the mutex. */
+ mutex_init(&priv->se_if_lock);
+ mutex_init(&priv->se_if_cmd_lock);
+
+ priv->cmd_receiver_dev = NULL;
+ priv->waiting_rsp_dev = NULL;
+ priv->max_dev_ctx = info->max_dev_ctx;
+ priv->cmd_tag = info->cmd_tag;
+ priv->rsp_tag = info->rsp_tag;
+ priv->mem_pool_name = info->pool_name;
+ priv->success_tag = info->success_tag;
+ priv->base_api_ver = info->base_api_ver;
+ priv->fw_api_ver = info->fw_api_ver;
+
+ init_completion(&priv->done);
+ spin_lock_init(&priv->lock);
+
+ if (info->reserved_dma_ranges) {
+ ret = of_reserved_mem_device_init(dev);
+ if (ret) {
+ dev_err(dev,
+ "failed to init reserved memory region %d\n",
+ ret);
+ priv->flags &= (~RESERVED_DMA_POOL);
+ goto exit;
+ }
+ priv->flags |= RESERVED_DMA_POOL;
+ }
+
+ if (info->fw_name_in_rfs) {
+ ret = request_firmware_nowait(THIS_MODULE,
+ FW_ACTION_UEVENT,
+ info->fw_name_in_rfs,
+ dev, GFP_KERNEL, priv,
+ se_load_firmware);
+ if (ret)
+ dev_warn(dev, "Failed to get firmware [%s].\n",
+ info->fw_name_in_rfs);
+ }
+
+ ret = imx_fetch_se_soc_info(dev);
+ if (ret) {
+ dev_err(dev,
+ "failed[%pe] to fetch SoC Info\n", ERR_PTR(ret));
+ goto exit;
+ }
+
+ if (info->imem_mgmt) {
+ /* allocate buffer where SE store encrypted IMEM */
+ priv->imem.buf = dmam_alloc_coherent(dev, ELE_IMEM_SIZE,
+ &priv->imem.phyaddr,
+ GFP_KERNEL);
+ if (!priv->imem.buf) {
+ dev_err(dev,
+ "dmam-alloc-failed: To store encr-IMEM.\n");
+ ret = -ENOMEM;
+ goto exit;
+ }
+ }
+
+ dev_info(dev, "i.MX secure-enclave: %s interface to firmware, configured.\n",
+ info->se_name);
+ return devm_of_platform_populate(dev);
+
+exit:
+ /* if execution control reaches here, if probe fails.
+ * hence doing the cleanup
+ */
+ if (se_probe_if_cleanup(pdev))
+ dev_err(dev,
+ "Failed to clean-up the child node probe.\n");
+
+ return ret;
+}
+
+static int se_remove(struct platform_device *pdev)
+{
+ if (se_probe_if_cleanup(pdev))
+ dev_err(&pdev->dev,
+ "i.MX Secure Enclave is not cleanly un-probed.");
+
+ return 0;
+}
+
+static int se_suspend(struct device *dev)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ const struct imx_se_node_info *info
+ = priv->info;
+
+ if (info && info->imem_mgmt)
+ priv->imem.size = se_save_imem_state(dev);
+
+ return 0;
+}
+
+static int se_resume(struct device *dev)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ const struct imx_se_node_info *info
+ = priv->info;
+
+ if (info && info->imem_mgmt)
+ se_restore_imem_state(dev);
+
+ return 0;
+}
+
+static const struct dev_pm_ops se_pm = {
+ RUNTIME_PM_OPS(se_suspend, se_resume, NULL)
+};
+
+static struct platform_driver se_driver = {
+ .driver = {
+ .name = "fsl-se-fw",
+ .of_match_table = se_match,
+ .pm = &se_pm,
+ },
+ .probe = se_if_probe,
+ .remove = se_remove,
+};
+MODULE_DEVICE_TABLE(of, se_match);
+
+module_platform_driver(se_driver);
+
+MODULE_AUTHOR("Pankaj Gupta <pankaj.gupta@nxp.com>");
+MODULE_DESCRIPTION("iMX Secure Enclave Driver.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/firmware/imx/se_ctrl.h b/drivers/firmware/imx/se_ctrl.h
new file mode 100644
index 000000000000..7d4f439a6158
--- /dev/null
+++ b/drivers/firmware/imx/se_ctrl.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef SE_MU_H
+#define SE_MU_H
+
+#include <linux/miscdevice.h>
+#include <linux/semaphore.h>
+#include <linux/mailbox_client.h>
+
+#define MAX_FW_LOAD_RETRIES 50
+
+#define RES_STATUS(x) FIELD_GET(0x000000ff, x)
+#define MESSAGING_VERSION_6 0x6
+#define MESSAGING_VERSION_7 0x7
+
+struct se_imem_buf {
+ u8 *buf;
+ phys_addr_t phyaddr;
+ u32 size;
+};
+
+/* Header of the messages exchange with the EdgeLock Enclave */
+struct se_msg_hdr {
+ u8 ver;
+ u8 size;
+ u8 command;
+ u8 tag;
+} __packed;
+
+#define SE_MU_HDR_SZ 4
+
+struct se_api_msg {
+ struct se_msg_hdr header;
+ u32 data[];
+};
+
+struct se_if_priv {
+ struct se_if_device_ctx *cmd_receiver_dev;
+ /* Update to the waiting_rsp_dev, to be protected
+ * under se_if_lock.
+ */
+ struct se_if_device_ctx *waiting_rsp_dev;
+ /*
+ * prevent parallel access to the se interface registers
+ * e.g. a user trying to send a command while the other one is
+ * sending a response.
+ */
+ struct mutex se_if_lock;
+ /*
+ * prevent a command to be sent on the se interface while another one is
+ * still processing. (response to a command is allowed)
+ */
+ struct mutex se_if_cmd_lock;
+ struct device *dev;
+ u8 *mem_pool_name;
+ u8 cmd_tag;
+ u8 rsp_tag;
+ u8 success_tag;
+ u8 base_api_ver;
+ u8 fw_api_ver;
+ u32 fw_fail;
+ u16 soc_rev;
+ const void *info;
+
+ struct mbox_client se_mb_cl;
+ struct mbox_chan *tx_chan, *rx_chan;
+
+ /* Assignment of the rx_msg buffer to held till the
+ * received content as part callback function, is copied.
+ */
+ struct se_api_msg *rx_msg;
+ struct completion done;
+ spinlock_t lock;
+ /*
+ * Flag to retain the state of initialization done at
+ * the time of se-if probe.
+ */
+ uint32_t flags;
+ u8 max_dev_ctx;
+ struct se_if_device_ctx **ctxs;
+ struct se_imem_buf imem;
+};
+
+void *get_phy_buf_mem_pool(struct device *dev,
+ u8 *mem_pool_name,
+ dma_addr_t *buf,
+ u32 size);
+phys_addr_t get_phy_buf_mem_pool1(struct device *dev,
+ u8 *mem_pool_name,
+ u32 **buf,
+ u32 size);
+void free_phybuf_mem_pool(struct device *dev,
+ u8 *mem_pool_name,
+ u32 *buf,
+ u32 size);
+#endif
diff --git a/include/linux/firmware/imx/se_api.h b/include/linux/firmware/imx/se_api.h
new file mode 100644
index 000000000000..c47f84906837
--- /dev/null
+++ b/include/linux/firmware/imx/se_api.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __SE_API_H__
+#define __SE_API_H__
+
+#include <linux/types.h>
+
+#define SOC_ID_OF_IMX8ULP 0x084D
+#define SOC_ID_OF_IMX93 0x9300
+
+#endif /* __SE_API_H__ */
--
2.34.1
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^ permalink raw reply related [relevance 3%]
* arm64: kernel panic on 4G RAM platform
@ 2024-05-23 8:16 6% Alexander Wilhelm
0 siblings, 0 replies; 200+ results
From: Alexander Wilhelm @ 2024-05-23 8:16 UTC (permalink / raw)
To: Catalin Marinas; +Cc: linux-arm-kernel
Hello ARM64 developers,
I have a kernel panic problem on my ARM64 architecture board but I'm not sure if
it's a problem in kernel or otherwise. Maybe one could help me.
My problem is the following: I'm using the NXP TQ board with ARM64 architecture
to run OpenWRT operating system with linux kernel v5.15. The current
revision of the board (TQMLS1046A-CB.0203) has now a 4GiB RAM instead of 2GiB.
Therefore I adapted the U-Boot to use the entire memory. But now it leads to
kernel crash. Interesting is that if I only use 2GiB the problem doesn't occur.
The memory is splitted up in two different banks.
While analyzing my problem I tried to narrow down the source of my problem. But
with each new "print message" that should me help to trace the problem I get
another one. It seems like the error happens unpredictable like due to race
condition or memory access. Then I tried different RAM sizes something
in-between like 3GiB. I could boot successfully but then I got errors from
"swiotlb" if my wireless driver tried to allocate memory from my CMA pool. I
understand that the error description is vary vague but I give my best to
explain my problem. Please refer to my log of the current kernel panic state:
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd082]
[ 0.000000] Linux version 5.15.158 (########@##############) (aarch64-openwrt-linux-gnu-gcc (OpenWrt GCC 12.3.0 r23630-842932a63d) 12.3.0, GNU ld (GNU Binutils) 2.37) #0 SMP Wed May 22 13:15:09 2024
[ 0.000000] Machine model: #########
[ 0.000000] earlycon: uart8250 at MMIO 0x00000000021c0500 (options '')
[ 0.000000] printk: bootconsole [uart8250] enabled
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000008ff800000, size 8 MiB
[ 0.000000] OF: reserved mem: initialized node qman-fqd, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000008fc000000, size 32 MiB
[ 0.000000] OF: reserved mem: initialized node qman-pfdr, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x00000008fe000000, size 16 MiB
[ 0.000000] OF: reserved mem: initialized node bman-fbpr, compatible id shared-dma-pool
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000080000000-0x00000000ffffffff]
[ 0.000000] DMA32 empty
[ 0.000000] Normal [mem 0x0000000100000000-0x00000008ffffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080000000-0x00000000fbdfffff]
[ 0.000000] node 0: [mem 0x0000000880000000-0x00000008fbffffff]
[ 0.000000] node 0: [mem 0x00000008fc000000-0x00000008feffffff]
[ 0.000000] node 0: [mem 0x00000008ff000000-0x00000008ff7fffff]
[ 0.000000] node 0: [mem 0x00000008ff800000-0x00000008ffffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff]
[ 0.000000] On node 0, zone Normal: 16896 pages in unavailable ranges
[ 0.000000] cma: Reserved 192 MiB at 0x00000000ee800000
[ 0.000000] Failed to find device node for boot cpu
[ 0.000000] /cpus/cpu@0: missing reg property
[ 0.000000] /cpus/cpu@1: missing reg property
[ 0.000000] /cpus/cpu@2: missing reg property
[ 0.000000] /cpus/cpu@3: missing reg property
[ 0.000000] Number of cores (5) exceeds configured maximum of 2 - clipping
[ 0.000000] missing boot CPU MPIDR, not enabling secondaries
[ 0.000000] percpu: Embedded 19 pages/cpu s37976 r8192 d31656 u77824
[ 0.000000] Detected PIPT I-cache on CPU0
[ 0.000000] CPU features: detected: Spectre-v2
[ 0.000000] CPU features: detected: Spectre-v4
[ 0.000000] CPU features: detected: Spectre-BHB
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1017344
[ 0.000000] Kernel command line: #######################
[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] software IO TLB: mapped [mem 0x00000000ea800000-0x00000000ee800000] (64MB)
[ 0.000000] Memory: 3698904K/4126720K available (11776K kernel code, 968K rwdata, 3280K rodata, 576K init, 367K bss, 231208K reserved, 196608K cma-reserved)
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
[ 0.000000] Trampoline variant of Tasks RCU enabled.
[ 0.000000] Rude variant of Tasks RCU enabled.
[ 0.000000] Tracing variant of Tasks RCU enabled.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] timer_probe: no matching timers found
[ 0.000000] Kernel panic - not syncing: Unable to initialise architected timer.
[ 0.000000] ---[ end Kernel panic - not syncing: Unable to initialise architected timer. ]---
Best regards
Alexander Wilhelm
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 6%]
* [PATCH] kselftest/arm64: Include kernel mode NEON in fp-stress
@ 2024-05-21 18:18 3% Mark Brown
0 siblings, 0 replies; 200+ results
From: Mark Brown @ 2024-05-21 18:18 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Shuah Khan
Cc: Johannes Nixdorf, Ard Biesheuvel, Dave Martin, linux-kernel,
linux-arm-kernel, linux-kselftest, Mark Brown
Currently fp-stress only covers userspace use of floating point, it does
not cover any kernel mode uses. Since currently kernel mode floating
point usage can't be preempted and there are explicit preemption points in
the existing implementations this isn't so important for fp-stress but
when we readd preemption it will be good to try to exercise it.
When the arm64 accelerated crypto operations are implemented we can
relatively straightforwardly trigger kernel mode floating point usage by
using the crypto userspace API to hash data, using the splice() support
in an effort to minimise copying. We use /proc/crypto to check which
accelerated implementations are available, picking the first symmetric
hash we find. We run the kernel mode test unconditionally, replacing the
second copy of the FPSIMD testcase for systems with FPSIMD only. If we
don't think there are any suitable kernel mode implementations we fall back
to running another copy of fpsimd-stress.
There are a number issues with this approach, we don't actually verify
that we are using an accelerated (or even CPU) implementation of the
algorithm being tested and even with attempting to use splice() to
minimise copying there are sizing limits on how much data gets spliced
at once.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
This is mainly focused on trying to reproduce the issues reported by
Asahi users with preemptable kernel mode floating point - as noted in
the commit log it needs reenablement of preemptable floating point and
removal of the preemption points in the current algorithm
implementations to really have anything to exercise directly. There
also seem to be race conditions when AF_ALG is built as a module,
attempting to bind triggers module load but does not block.
---
tools/testing/selftests/arm64/fp/.gitignore | 1 +
tools/testing/selftests/arm64/fp/Makefile | 1 +
tools/testing/selftests/arm64/fp/fp-stress.c | 26 +-
tools/testing/selftests/arm64/fp/kernel-test.c | 324 +++++++++++++++++++++++++
4 files changed, 343 insertions(+), 9 deletions(-)
diff --git a/tools/testing/selftests/arm64/fp/.gitignore b/tools/testing/selftests/arm64/fp/.gitignore
index 00e52c966281..8362e7ec35ad 100644
--- a/tools/testing/selftests/arm64/fp/.gitignore
+++ b/tools/testing/selftests/arm64/fp/.gitignore
@@ -2,6 +2,7 @@ fp-pidbench
fp-ptrace
fp-stress
fpsimd-test
+kernel-test
rdvl-sme
rdvl-sve
sve-probe-vls
diff --git a/tools/testing/selftests/arm64/fp/Makefile b/tools/testing/selftests/arm64/fp/Makefile
index 55d4f00d9e8e..d171021e4cdd 100644
--- a/tools/testing/selftests/arm64/fp/Makefile
+++ b/tools/testing/selftests/arm64/fp/Makefile
@@ -12,6 +12,7 @@ TEST_GEN_PROGS := \
vec-syscfg \
za-fork za-ptrace
TEST_GEN_PROGS_EXTENDED := fp-pidbench fpsimd-test \
+ kernel-test \
rdvl-sme rdvl-sve \
sve-test \
ssve-test \
diff --git a/tools/testing/selftests/arm64/fp/fp-stress.c b/tools/testing/selftests/arm64/fp/fp-stress.c
index dd31647b00a2..faac24bdefeb 100644
--- a/tools/testing/selftests/arm64/fp/fp-stress.c
+++ b/tools/testing/selftests/arm64/fp/fp-stress.c
@@ -319,6 +319,19 @@ static void start_fpsimd(struct child_data *child, int cpu, int copy)
ksft_print_msg("Started %s\n", child->name);
}
+static void start_kernel(struct child_data *child, int cpu, int copy)
+{
+ int ret;
+
+ ret = asprintf(&child->name, "KERNEL-%d-%d", cpu, copy);
+ if (ret == -1)
+ ksft_exit_fail_msg("asprintf() failed\n");
+
+ child_start(child, "./kernel-test");
+
+ ksft_print_msg("Started %s\n", child->name);
+}
+
static void start_sve(struct child_data *child, int vl, int cpu)
{
int ret;
@@ -438,7 +451,7 @@ int main(int argc, char **argv)
int ret;
int timeout = 10;
int cpus, i, j, c;
- int sve_vl_count, sme_vl_count, fpsimd_per_cpu;
+ int sve_vl_count, sme_vl_count;
bool all_children_started = false;
int seen_children;
int sve_vls[MAX_VLS], sme_vls[MAX_VLS];
@@ -482,12 +495,7 @@ int main(int argc, char **argv)
have_sme2 = false;
}
- /* Force context switching if we only have FPSIMD */
- if (!sve_vl_count && !sme_vl_count)
- fpsimd_per_cpu = 2;
- else
- fpsimd_per_cpu = 1;
- tests += cpus * fpsimd_per_cpu;
+ tests += cpus * 2;
ksft_print_header();
ksft_set_plan(tests);
@@ -542,8 +550,8 @@ int main(int argc, char **argv)
tests);
for (i = 0; i < cpus; i++) {
- for (j = 0; j < fpsimd_per_cpu; j++)
- start_fpsimd(&children[num_children++], i, j);
+ start_fpsimd(&children[num_children++], i, 0);
+ start_kernel(&children[num_children++], i, 0);
for (j = 0; j < sve_vl_count; j++)
start_sve(&children[num_children++], sve_vls[j], i);
diff --git a/tools/testing/selftests/arm64/fp/kernel-test.c b/tools/testing/selftests/arm64/fp/kernel-test.c
new file mode 100644
index 000000000000..50db26a3ed79
--- /dev/null
+++ b/tools/testing/selftests/arm64/fp/kernel-test.c
@@ -0,0 +1,324 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2024 ARM Limited.
+ */
+
+#define _GNU_SOURCE
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <signal.h>
+#include <string.h>
+#include <unistd.h>
+
+#include <sys/socket.h>
+
+#include <linux/kernel.h>
+#include <linux/if_alg.h>
+
+#define DATA_SIZE (16 * 4096)
+
+static int base, sock;
+
+static int digest_len;
+static char *ref;
+static char *digest;
+static char *alg_name;
+
+static struct iovec data_iov;
+static int zerocopy[2];
+static int sigs;
+static int iter;
+
+static void handle_exit_signal(int sig, siginfo_t *info, void *context)
+{
+ printf("Terminated by signal %d, iterations=%d, signals=%d\n",
+ sig, iter, sigs);
+ exit(0);
+}
+
+static void handle_kick_signal(int sig, siginfo_t *info, void *context)
+{
+ sigs++;
+}
+
+static char *drivers[] = {
+ "crct10dif-arm64-ce",
+ /* "crct10dif-arm64-neon", - Same priority as generic */
+ "sha1-ce",
+ "sha224-arm64",
+ "sha224-arm64-neon",
+ "sha224-ce",
+ "sha256-arm64",
+ "sha256-arm64-neon",
+ "sha256-ce",
+ "sha384-ce",
+ "sha512-ce",
+ "sha3-224-ce",
+ "sha3-256-ce",
+ "sha3-384-ce",
+ "sha3-512-ce",
+ "sm3-ce",
+ "sm3-neon",
+};
+
+static bool create_socket(void)
+{
+ FILE *proc;
+ struct sockaddr_alg addr;
+ char buf[1024];
+ char *c, *driver_name;
+ bool is_shash, match;
+ int ret, i;
+
+ ret = socket(AF_ALG, SOCK_SEQPACKET, 0);
+ if (ret < 0) {
+ if (errno == EAFNOSUPPORT) {
+ printf("AF_ALG not supported\n");
+ return false;
+ }
+
+ printf("Failed to create AF_ALG socket: %s (%d)\n",
+ strerror(errno), errno);
+ return false;
+ }
+ base = ret;
+
+ memset(&addr, 0, sizeof(addr));
+ addr.salg_family = AF_ALG;
+ strncpy((char *)addr.salg_type, "hash", sizeof(addr.salg_type));
+
+ proc = fopen("/proc/crypto", "r");
+ if (!proc) {
+ printf("Unable to open /proc/crypto\n");
+ return false;
+ }
+
+ driver_name = NULL;
+ is_shash = false;
+ match = false;
+
+ /* Look through /proc/crypto for a driver with kernel mode FP usage */
+ while (!match) {
+ c = fgets(buf, sizeof(buf), proc);
+ if (!c) {
+ if (feof(proc)) {
+ printf("Nothing found in /proc/crypto\n");
+ return false;
+ }
+ continue;
+ }
+
+ /* Algorithm descriptions are separated by a blank line */
+ if (*c == '\n') {
+ if (is_shash && driver_name) {
+ for (i = 0; i < ARRAY_SIZE(drivers); i++) {
+ if (strcmp(drivers[i],
+ driver_name) == 0) {
+ match = true;
+ }
+ }
+ }
+
+ if (!match) {
+ digest_len = 0;
+
+ free(driver_name);
+ driver_name = NULL;
+
+ free(alg_name);
+ alg_name = NULL;
+
+ is_shash = false;
+ }
+ continue;
+ }
+
+ /* Remove trailing newline */
+ c = strchr(buf, '\n');
+ if (c)
+ *c = '\0';
+
+ /* Find the field/value separator and start of the value */
+ c = strchr(buf, ':');
+ if (!c)
+ continue;
+ c += 2;
+
+ if (strncmp(buf, "digestsize", strlen("digestsize")) == 0)
+ sscanf(c, "%d", &digest_len);
+
+ if (strncmp(buf, "name", strlen("name")) == 0)
+ alg_name = strdup(c);
+
+ if (strncmp(buf, "driver", strlen("driver")) == 0)
+ driver_name = strdup(c);
+
+ if (strncmp(buf, "type", strlen("type")) == 0)
+ if (strncmp(c, "shash", strlen("shash")) == 0)
+ is_shash = true;
+ }
+
+ strncpy((char *)addr.salg_name, alg_name,
+ sizeof(addr.salg_name) - 1);
+
+ ret = bind(base, (struct sockaddr *)&addr, sizeof(addr));
+ if (ret < 0) {
+ printf("Failed to bind %s: %s (%d)\n",
+ addr.salg_name, strerror(errno), errno);
+ return false;
+ }
+
+ ret = accept(base, NULL, 0);
+ if (ret < 0) {
+ printf("Failed to accept %s: %s (%d)\n",
+ addr.salg_name, strerror(errno), errno);
+ return false;
+ }
+
+ sock = ret;
+
+ ret = pipe(zerocopy);
+ if (ret != 0) {
+ printf("Failed to create zerocopy pipe: %s (%d)\n",
+ strerror(errno), errno);
+ return false;
+ }
+
+ ref = malloc(digest_len);
+ if (!ref) {
+ printf("Failed to allocated %d byte reference\n", digest_len);
+ return false;
+ }
+
+ digest = malloc(digest_len);
+ if (!digest) {
+ printf("Failed to allocated %d byte digest\n", digest_len);
+ return false;
+ }
+
+ return true;
+}
+
+static bool compute_digest(void *buf)
+{
+ struct iovec iov;
+ int ret, wrote;
+
+ iov = data_iov;
+ while (iov.iov_len) {
+ ret = vmsplice(zerocopy[1], &iov, 1, SPLICE_F_GIFT);
+ if (ret < 0) {
+ printf("Failed to send buffer: %s (%d)\n",
+ strerror(errno), errno);
+ return false;
+ }
+
+ wrote = ret;
+ ret = splice(zerocopy[0], NULL, sock, NULL, wrote, 0);
+ if (ret < 0) {
+ printf("Failed to splice buffer: %s (%d)\n",
+ strerror(errno), errno);
+ } else if (ret != wrote) {
+ printf("Short splice: %d < %d\n", ret, wrote);
+ }
+
+ iov.iov_len -= wrote;
+ iov.iov_base += wrote;
+ }
+
+reread:
+ ret = recv(sock, buf, digest_len, 0);
+ if (ret == 0) {
+ printf("No disgest returned\n");
+ return false;
+ }
+ if (ret != digest_len) {
+ if (errno == -EAGAIN)
+ goto reread;
+ printf("Failed to get digest: %s (%d)\n",
+ strerror(errno), errno);
+ return false;
+ }
+
+ return true;
+}
+
+int main(void)
+{
+ char *data;
+ struct sigaction sa;
+ int ret;
+
+ /* Ensure we have unbuffered output */
+ setvbuf(stdout, NULL, _IOLBF, 0);
+
+ /* The parent will communicate with us via signals */
+ memset(&sa, 0, sizeof(sa));
+ sa.sa_sigaction = handle_exit_signal;
+ sa.sa_flags = SA_RESTART | SA_SIGINFO;
+ sigemptyset(&sa.sa_mask);
+ ret = sigaction(SIGTERM, &sa, NULL);
+ if (ret < 0)
+ printf("Failed to install SIGTERM handler: %s (%d)\n",
+ strerror(errno), errno);
+
+ sa.sa_sigaction = handle_kick_signal;
+ ret = sigaction(SIGUSR2, &sa, NULL);
+ if (ret < 0)
+ printf("Failed to install SIGUSR2 handler: %s (%d)\n",
+ strerror(errno), errno);
+
+ data = malloc(DATA_SIZE);
+ if (!data) {
+ printf("Failed to allocate data buffer\n");
+ return EXIT_FAILURE;
+ }
+ memset(data, 0, DATA_SIZE);
+
+ data_iov.iov_base = data;
+ data_iov.iov_len = DATA_SIZE;
+
+ /*
+ * If we can't create a socket assume it's a lack of system
+ * support and fall back to a basic FPSIMD test for the
+ * benefit of fp-stress.
+ */
+ if (!create_socket()) {
+ execl("./fpsimd-test", "./fpsimd-test", NULL);
+ printf("Failed to fall back to fspimd-test: %d (%s)\n",
+ errno, strerror(errno));
+ return EXIT_FAILURE;
+ }
+
+ /*
+ * Compute a reference digest we hope is repeatable, we do
+ * this at runtime partly to make it easier to play with
+ * parameters.
+ */
+ if (!compute_digest(ref)) {
+ printf("Failed to compute reference digest\n");
+ return EXIT_FAILURE;
+ }
+
+ printf("AF_ALG using %s\n", alg_name);
+
+ while (true) {
+ if (!compute_digest(digest)) {
+ printf("Failed to coempute digest, iter=%d\n", iter);
+ return EXIT_FAILURE;
+ }
+
+ if (memcmp(ref, digest, digest_len) != 0) {
+ printf("Digest mismatch, iter=%d\n", iter);
+ return EXIT_FAILURE;
+ }
+
+ iter++;
+ }
+
+ return EXIT_FAILURE;
+}
---
base-commit: a38297e3fb012ddfa7ce0321a7e5a8daeb1872b6
change-id: 20240517-arm64-fp-stress-kernel-a09011b96f42
Best regards,
--
Mark Brown <broonie@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 3%]
* [RESEND PATCH v5 1/7] remoteproc: Add TEE support
@ 2024-05-21 12:24 3% ` Arnaud Pouliquen
0 siblings, 0 replies; 200+ results
From: Arnaud Pouliquen @ 2024-05-21 12:24 UTC (permalink / raw)
To: Bjorn Andersson, Mathieu Poirier, Jens Wiklander, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-stm32, linux-arm-kernel, linux-remoteproc, linux-kernel,
op-tee, devicetree, Arnaud Pouliquen
Add a remoteproc TEE (Trusted Execution Environment) driver
that will be probed by the TEE bus. If the associated Trusted
application is supported on secure part this driver offers a client
interface to load a firmware in the secure part.
This firmware could be authenticated by the secure trusted application.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
---
update from V4
- fix commit message,
- fix Kconfig typo,
- introduce tee_rproc_release_loaded_rsc_table function to release the
resource table,
- reorder function variables in declaration in reverse ascending order,
- introduce try_module_get and module_put to prevent module removed while
used,
- remove rsc_table field in tee_rproc structure,
- remove tee_rproc_find_loaded_rsc_table as seems not correspond to the
propoer usage regarding ops definition [1]. The resource table is
loaded before used,
- add __force attribute when cast the type aof the resource table to fix
build warning.
[1]https://elixir.bootlin.com/linux/latest/source/include/linux/remoteproc.h#L374
---
drivers/remoteproc/Kconfig | 10 +
drivers/remoteproc/Makefile | 1 +
drivers/remoteproc/tee_remoteproc.c | 429 ++++++++++++++++++++++++++++
include/linux/remoteproc.h | 4 +
include/linux/tee_remoteproc.h | 99 +++++++
5 files changed, 543 insertions(+)
create mode 100644 drivers/remoteproc/tee_remoteproc.c
create mode 100644 include/linux/tee_remoteproc.h
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 48845dc8fa85..6c1c07202276 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -365,6 +365,16 @@ config XLNX_R5_REMOTEPROC
It's safe to say N if not interested in using RPU r5f cores.
+
+config TEE_REMOTEPROC
+ tristate "Remoteproc support by a TEE application"
+ depends on OPTEE
+ help
+ Support a remote processor with a TEE application. The Trusted
+ Execution Context is responsible for loading the trusted firmware
+ image and managing the remote processor's lifecycle.
+ This can be either built-in or a loadable module.
+
endif # REMOTEPROC
endmenu
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 91314a9b43ce..fa8daebce277 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_RCAR_REMOTEPROC) += rcar_rproc.o
obj-$(CONFIG_ST_REMOTEPROC) += st_remoteproc.o
obj-$(CONFIG_ST_SLIM_REMOTEPROC) += st_slim_rproc.o
obj-$(CONFIG_STM32_RPROC) += stm32_rproc.o
+obj-$(CONFIG_TEE_REMOTEPROC) += tee_remoteproc.o
obj-$(CONFIG_TI_K3_DSP_REMOTEPROC) += ti_k3_dsp_remoteproc.o
obj-$(CONFIG_TI_K3_R5_REMOTEPROC) += ti_k3_r5_remoteproc.o
obj-$(CONFIG_XLNX_R5_REMOTEPROC) += xlnx_r5_remoteproc.o
diff --git a/drivers/remoteproc/tee_remoteproc.c b/drivers/remoteproc/tee_remoteproc.c
new file mode 100644
index 000000000000..f13546628ec9
--- /dev/null
+++ b/drivers/remoteproc/tee_remoteproc.c
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) STMicroelectronics 2024 - All Rights Reserved
+ * Author: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
+ */
+
+#include <linux/firmware.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/remoteproc.h>
+#include <linux/slab.h>
+#include <linux/tee_drv.h>
+#include <linux/tee_remoteproc.h>
+
+#include "remoteproc_internal.h"
+
+#define MAX_TEE_PARAM_ARRY_MEMBER 4
+
+/*
+ * Authentication of the firmware and load in the remote processor memory
+ *
+ * [in] params[0].value.a: unique 32bit identifier of the remote processor
+ * [in] params[1].memref: buffer containing the image of the buffer
+ */
+#define TA_RPROC_FW_CMD_LOAD_FW 1
+
+/*
+ * Start the remote processor
+ *
+ * [in] params[0].value.a: unique 32bit identifier of the remote processor
+ */
+#define TA_RPROC_FW_CMD_START_FW 2
+
+/*
+ * Stop the remote processor
+ *
+ * [in] params[0].value.a: unique 32bit identifier of the remote processor
+ */
+#define TA_RPROC_FW_CMD_STOP_FW 3
+
+/*
+ * Return the address of the resource table, or 0 if not found
+ * No check is done to verify that the address returned is accessible by
+ * the non secure context. If the resource table is loaded in a protected
+ * memory the access by the non secure context will lead to a data abort.
+ *
+ * [in] params[0].value.a: unique 32bit identifier of the remote processor
+ * [out] params[1].value.a: 32bit LSB resource table memory address
+ * [out] params[1].value.b: 32bit MSB resource table memory address
+ * [out] params[2].value.a: 32bit LSB resource table memory size
+ * [out] params[2].value.b: 32bit MSB resource table memory size
+ */
+#define TA_RPROC_FW_CMD_GET_RSC_TABLE 4
+
+/*
+ * Return the address of the core dump
+ *
+ * [in] params[0].value.a: unique 32bit identifier of the remote processor
+ * [out] params[1].memref: address of the core dump image if exist,
+ * else return Null
+ */
+#define TA_RPROC_FW_CMD_GET_COREDUMP 5
+
+struct tee_rproc_context {
+ struct list_head sessions;
+ struct tee_context *tee_ctx;
+ struct device *dev;
+};
+
+static struct tee_rproc_context *tee_rproc_ctx;
+
+static void tee_rproc_prepare_args(struct tee_rproc *trproc, int cmd,
+ struct tee_ioctl_invoke_arg *arg,
+ struct tee_param *param,
+ unsigned int num_params)
+{
+ memset(arg, 0, sizeof(*arg));
+ memset(param, 0, MAX_TEE_PARAM_ARRY_MEMBER * sizeof(*param));
+
+ arg->func = cmd;
+ arg->session = trproc->session_id;
+ arg->num_params = num_params + 1;
+
+ param[0] = (struct tee_param) {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
+ .u.value.a = trproc->rproc_id,
+ };
+}
+
+static void tee_rproc_release_loaded_rsc_table(struct rproc *rproc)
+{
+ if (rproc->table_ptr) {
+ iounmap((__force __iomem void *)rproc->table_ptr);
+ /*
+ * Use a copy of the resource table for the remainder of the
+ * shutdown or recovery process.
+ */
+ rproc->table_ptr = rproc->cached_table;
+ }
+}
+
+int tee_rproc_load_fw(struct rproc *rproc, const struct firmware *fw)
+{
+ struct tee_param param[MAX_TEE_PARAM_ARRY_MEMBER];
+ struct tee_rproc *trproc = rproc->tee_interface;
+ struct tee_ioctl_invoke_arg arg;
+ struct tee_shm *fw_shm;
+ int ret;
+
+ if (!trproc)
+ return -EINVAL;
+
+ fw_shm = tee_shm_register_kernel_buf(tee_rproc_ctx->tee_ctx, (void *)fw->data, fw->size);
+ if (IS_ERR(fw_shm))
+ return PTR_ERR(fw_shm);
+
+ tee_rproc_prepare_args(trproc, TA_RPROC_FW_CMD_LOAD_FW, &arg, param, 1);
+
+ /* Provide the address of the firmware image */
+ param[1] = (struct tee_param) {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT,
+ .u.memref = {
+ .shm = fw_shm,
+ .size = fw->size,
+ .shm_offs = 0,
+ },
+ };
+
+ ret = tee_client_invoke_func(tee_rproc_ctx->tee_ctx, &arg, param);
+ if (ret < 0 || arg.ret != 0) {
+ dev_err(tee_rproc_ctx->dev,
+ "TA_RPROC_FW_CMD_LOAD_FW invoke failed TEE err: %x, ret:%x\n",
+ arg.ret, ret);
+ if (!ret)
+ ret = -EIO;
+ }
+
+ tee_shm_free(fw_shm);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(tee_rproc_load_fw);
+
+struct resource_table *tee_rproc_get_loaded_rsc_table(struct rproc *rproc, size_t *table_sz)
+{
+ struct tee_param param[MAX_TEE_PARAM_ARRY_MEMBER];
+ struct tee_rproc *trproc = rproc->tee_interface;
+ struct resource_table *rsc_table;
+ struct tee_ioctl_invoke_arg arg;
+ int ret;
+
+ if (!trproc)
+ return ERR_PTR(-EINVAL);
+
+ tee_rproc_prepare_args(trproc, TA_RPROC_FW_CMD_GET_RSC_TABLE, &arg, param, 2);
+
+ param[1].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_OUTPUT;
+ param[2].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_OUTPUT;
+
+ ret = tee_client_invoke_func(tee_rproc_ctx->tee_ctx, &arg, param);
+ if (ret < 0 || arg.ret != 0) {
+ dev_err(tee_rproc_ctx->dev,
+ "TA_RPROC_FW_CMD_GET_RSC_TABLE invoke failed TEE err: %x, ret:%x\n",
+ arg.ret, ret);
+ return ERR_PTR(-EIO);
+ }
+
+ *table_sz = param[2].u.value.a;
+
+ /* If the size is null no resource table defined in the image */
+ if (!*table_sz)
+ return NULL;
+
+ /* Store the resource table address that would be updated by the remote core. */
+ rsc_table = (__force struct resource_table *)ioremap_wc(param[1].u.value.a, *table_sz);
+ if (IS_ERR_OR_NULL(rsc_table)) {
+ dev_err(tee_rproc_ctx->dev, "Unable to map memory region: %lld+%zx\n",
+ param[1].u.value.a, *table_sz);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ return rsc_table;
+}
+EXPORT_SYMBOL_GPL(tee_rproc_get_loaded_rsc_table);
+
+int tee_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
+{
+ struct resource_table *rsc_table;
+ size_t table_sz;
+ int ret;
+
+ ret = tee_rproc_load_fw(rproc, fw);
+ if (ret)
+ return ret;
+
+ rsc_table = rproc_get_loaded_rsc_table(rproc, &table_sz);
+ if (IS_ERR(rsc_table))
+ return PTR_ERR(rsc_table);
+
+ rproc->table_ptr = rsc_table;
+ rproc->table_sz = table_sz;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(tee_rproc_parse_fw);
+
+int tee_rproc_start(struct rproc *rproc)
+{
+ struct tee_param param[MAX_TEE_PARAM_ARRY_MEMBER];
+ struct tee_rproc *trproc = rproc->tee_interface;
+ struct tee_ioctl_invoke_arg arg;
+ int ret = 0;
+
+ if (!trproc) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ tee_rproc_prepare_args(trproc, TA_RPROC_FW_CMD_START_FW, &arg, param, 0);
+
+ ret = tee_client_invoke_func(tee_rproc_ctx->tee_ctx, &arg, param);
+ if (ret < 0 || arg.ret != 0) {
+ dev_err(tee_rproc_ctx->dev,
+ "TA_RPROC_FW_CMD_START_FW invoke failed TEE err: %x, ret:%x\n",
+ arg.ret, ret);
+ if (!ret)
+ ret = -EIO;
+ goto err;
+ }
+
+ return 0;
+
+err:
+ tee_rproc_release_loaded_rsc_table(rproc);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(tee_rproc_start);
+
+int tee_rproc_stop(struct rproc *rproc)
+{
+ struct tee_param param[MAX_TEE_PARAM_ARRY_MEMBER];
+ struct tee_rproc *trproc = rproc->tee_interface;
+ struct tee_ioctl_invoke_arg arg;
+ int ret;
+
+ if (!trproc)
+ return -EINVAL;
+
+ tee_rproc_prepare_args(trproc, TA_RPROC_FW_CMD_STOP_FW, &arg, param, 0);
+
+ ret = tee_client_invoke_func(tee_rproc_ctx->tee_ctx, &arg, param);
+ if (ret < 0 || arg.ret != 0) {
+ dev_err(tee_rproc_ctx->dev,
+ "TA_RPROC_FW_CMD_STOP_FW invoke failed TEE err: %x, ret:%x\n",
+ arg.ret, ret);
+ if (!ret)
+ ret = -EIO;
+ }
+
+ tee_rproc_release_loaded_rsc_table(rproc);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(tee_rproc_stop);
+
+static const struct tee_client_device_id stm32_tee_rproc_id_table[] = {
+ {UUID_INIT(0x80a4c275, 0x0a47, 0x4905,
+ 0x82, 0x85, 0x14, 0x86, 0xa9, 0x77, 0x1a, 0x08)},
+ {}
+};
+
+struct tee_rproc *tee_rproc_register(struct device *dev, struct rproc *rproc, unsigned int rproc_id)
+{
+ struct tee_param param[MAX_TEE_PARAM_ARRY_MEMBER];
+ struct tee_ioctl_open_session_arg sess_arg;
+ struct tee_client_device *tee_device;
+ struct tee_rproc *trproc, *p_err;
+ int ret;
+
+ /*
+ * Test if the device has been probed by the TEE bus. In case of failure, we ignore the
+ * reason. The bus could be not yet probed or the service not available in the secure
+ * firmware.The assumption in such a case is that the TEE remoteproc is not probed.
+ */
+ if (!tee_rproc_ctx)
+ return ERR_PTR(-EPROBE_DEFER);
+
+ /* Prevent tee rproc module from being removed */
+ if (!try_module_get(THIS_MODULE)) {
+ dev_err(tee_rproc_ctx->dev, "can't get owner\n");
+ p_err = ERR_PTR(-ENODEV);
+ goto module_put;
+ }
+
+ trproc = devm_kzalloc(dev, sizeof(*trproc), GFP_KERNEL);
+ if (!trproc) {
+ p_err = ERR_PTR(-ENOMEM);
+ goto module_put;
+ }
+ tee_device = to_tee_client_device(tee_rproc_ctx->dev);
+ memset(&sess_arg, 0, sizeof(sess_arg));
+
+ memcpy(sess_arg.uuid, tee_device->id.uuid.b, TEE_IOCTL_UUID_LEN);
+
+ sess_arg.clnt_login = TEE_IOCTL_LOGIN_REE_KERNEL;
+ sess_arg.num_params = 1;
+
+ param[0] = (struct tee_param) {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
+ .u.value.a = rproc_id,
+ };
+
+ ret = tee_client_open_session(tee_rproc_ctx->tee_ctx, &sess_arg, param);
+ if (ret < 0 || sess_arg.ret != 0) {
+ dev_err(dev, "tee_client_open_session failed, err: %x\n", sess_arg.ret);
+ p_err = ERR_PTR(-EINVAL);
+ goto module_put;
+ }
+
+ trproc->parent = dev;
+ trproc->rproc_id = rproc_id;
+ trproc->session_id = sess_arg.session;
+
+ trproc->rproc = rproc;
+ rproc->tee_interface = trproc;
+
+ list_add_tail(&trproc->node, &tee_rproc_ctx->sessions);
+
+ return trproc;
+
+module_put:
+ module_put(THIS_MODULE);
+ return p_err;
+}
+EXPORT_SYMBOL_GPL(tee_rproc_register);
+
+int tee_rproc_unregister(struct tee_rproc *trproc)
+{
+ struct rproc *rproc = trproc->rproc;
+ int ret;
+
+ ret = tee_client_close_session(tee_rproc_ctx->tee_ctx, trproc->session_id);
+ if (ret < 0)
+ dev_err(trproc->parent, "tee_client_close_session failed, err: %x\n", ret);
+
+ list_del(&trproc->node);
+ rproc->tee_interface = NULL;
+
+ module_put(THIS_MODULE);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(tee_rproc_unregister);
+
+static int tee_rproc_ctx_match(struct tee_ioctl_version_data *ver, const void *data)
+{
+ /* Today we support only the OP-TEE, could be extend to other tees */
+ return (ver->impl_id == TEE_IMPL_ID_OPTEE);
+}
+
+static int tee_rproc_probe(struct device *dev)
+{
+ struct tee_context *tee_ctx;
+ int ret;
+
+ /* Open context with TEE driver */
+ tee_ctx = tee_client_open_context(NULL, tee_rproc_ctx_match, NULL, NULL);
+ if (IS_ERR(tee_ctx))
+ return PTR_ERR(tee_ctx);
+
+ tee_rproc_ctx = devm_kzalloc(dev, sizeof(*tee_ctx), GFP_KERNEL);
+ if (!tee_rproc_ctx) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ tee_rproc_ctx->dev = dev;
+ tee_rproc_ctx->tee_ctx = tee_ctx;
+ INIT_LIST_HEAD(&tee_rproc_ctx->sessions);
+
+ return 0;
+err:
+ tee_client_close_context(tee_ctx);
+
+ return ret;
+}
+
+static int tee_rproc_remove(struct device *dev)
+{
+ struct tee_rproc *entry, *tmp;
+
+ list_for_each_entry_safe(entry, tmp, &tee_rproc_ctx->sessions, node) {
+ tee_client_close_session(tee_rproc_ctx->tee_ctx, entry->session_id);
+ list_del(&entry->node);
+ kfree(entry);
+ }
+
+ tee_client_close_context(tee_rproc_ctx->tee_ctx);
+
+ return 0;
+}
+
+MODULE_DEVICE_TABLE(tee, stm32_tee_rproc_id_table);
+
+static struct tee_client_driver tee_rproc_fw_driver = {
+ .id_table = stm32_tee_rproc_id_table,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .bus = &tee_bus_type,
+ .probe = tee_rproc_probe,
+ .remove = tee_rproc_remove,
+ },
+};
+
+static int __init tee_rproc_fw_mod_init(void)
+{
+ return driver_register(&tee_rproc_fw_driver.driver);
+}
+
+static void __exit tee_rproc_fw_mod_exit(void)
+{
+ driver_unregister(&tee_rproc_fw_driver.driver);
+}
+
+module_init(tee_rproc_fw_mod_init);
+module_exit(tee_rproc_fw_mod_exit);
+
+MODULE_DESCRIPTION(" TEE remote processor control driver");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index b4795698d8c2..8b678009e481 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -503,6 +503,8 @@ enum rproc_features {
RPROC_MAX_FEATURES,
};
+struct tee_rproc;
+
/**
* struct rproc - represents a physical remote processor device
* @node: list node of this rproc object
@@ -545,6 +547,7 @@ enum rproc_features {
* @cdev: character device of the rproc
* @cdev_put_on_release: flag to indicate if remoteproc should be shutdown on @char_dev release
* @features: indicate remoteproc features
+ * @tee_interface: pointer to the remoteproc tee context
*/
struct rproc {
struct list_head node;
@@ -586,6 +589,7 @@ struct rproc {
struct cdev cdev;
bool cdev_put_on_release;
DECLARE_BITMAP(features, RPROC_MAX_FEATURES);
+ struct tee_rproc *tee_interface;
};
/**
diff --git a/include/linux/tee_remoteproc.h b/include/linux/tee_remoteproc.h
new file mode 100644
index 000000000000..7fbb5c3423a8
--- /dev/null
+++ b/include/linux/tee_remoteproc.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright(c) 2024 STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef TEE_REMOTEPROC_H
+#define TEE_REMOTEPROC_H
+
+#include <linux/tee_drv.h>
+#include <linux/firmware.h>
+#include <linux/remoteproc.h>
+
+struct rproc;
+
+/**
+ * struct tee_rproc - TEE remoteproc structure
+ * @node: Reference in list
+ * @rproc: Remoteproc reference
+ * @parent: Parent device
+ * @rproc_id: Identifier of the target firmware
+ * @session_id: TEE session identifier
+ */
+struct tee_rproc {
+ struct list_head node;
+ struct rproc *rproc;
+ struct device *parent;
+ u32 rproc_id;
+ u32 session_id;
+};
+
+#if IS_REACHABLE(CONFIG_TEE_REMOTEPROC)
+
+struct tee_rproc *tee_rproc_register(struct device *dev, struct rproc *rproc,
+ unsigned int rproc_id);
+int tee_rproc_unregister(struct tee_rproc *trproc);
+int tee_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw);
+int tee_rproc_load_fw(struct rproc *rproc, const struct firmware *fw);
+struct resource_table *tee_rproc_get_loaded_rsc_table(struct rproc *rproc, size_t *table_sz);
+int tee_rproc_start(struct rproc *rproc);
+int tee_rproc_stop(struct rproc *rproc);
+
+#else
+
+static inline struct tee_rproc *tee_rproc_register(struct device *dev, struct rproc *rproc,
+ unsigned int rproc_id)
+{
+ return ERR_PTR(-ENODEV);
+}
+
+static int tee_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return 0;
+}
+
+static inline int tee_rproc_unregister(struct tee_rproc *trproc)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return 0;
+}
+
+static inline int tee_rproc_load_fw(struct rproc *rproc, const struct firmware *fw)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return 0;
+}
+
+static inline int tee_rproc_start(struct rproc *rproc)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return 0;
+}
+
+static inline int tee_rproc_stop(struct rproc *rproc)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return 0;
+}
+
+static inline struct resource_table *
+tee_rproc_get_loaded_rsc_table(struct rproc *rproc, size_t *table_sz)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return NULL;
+}
+#endif /* CONFIG_TEE_REMOTEPROC */
+#endif /* TEE_REMOTEPROC_H */
--
2.25.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 3%]
* [PATCH v2 1/1] PCI : Refactoring error log prints for better readability
[not found] <CGME20240521061553epcas5p1c7db70b37a70f599face675bc4dedda9@epcas5p1.samsung.com>
@ 2024-05-21 6:15 4% ` Onkarnarth
0 siblings, 0 replies; 200+ results
From: Onkarnarth @ 2024-05-21 6:15 UTC (permalink / raw)
To: bhelgaas, helgaas, vigneshr, s-vadapalli, lpieralisi, kw, robh,
yue.wang, neil.armstrong, khilman, jbrunet, martin.blumenstingl,
thomas.petazzoni, shawn.guo, lchuanhua, srikanth.thokala,
songxiaowei, wangbinghui, manivannan.sadhasivam, thierry.reding,
jonathanh, hayashi.kunihiko, mhiramat, pali, toan,
daire.mcnamara, conor.dooley, marek.vasut+renesas, shawn.lin,
heiko, nirmal.patel, jonathan.derrick, kishon, jdmason,
dave.jiang, rafael, lenb, mahesh, oohall
Cc: linux-pci, linux-kernel, linux-omap, linux-arm-kernel,
linux-amlogic, linux-arm-msm, linux-tegra, r.thapliyal,
Onkarnath, Maninder Singh
From: Onkarnath <onkarnath.1@samsung.com>
As %pe is already introduced, it's better to use it in place of (%ld) or
(%d) for printing error in logs. It will enhance readability of logs.
Error print style is more consistent now.
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Co-developed-by: Maninder Singh <maninder1.s@samsung.com>
Signed-off-by: Maninder Singh <maninder1.s@samsung.com>
Signed-off-by: Onkarnath <onkarnath.1@samsung.com>
---
Suggested by Bjorn Helgaas in below discussion
https://patchwork.kernel.org/comment/25712288/
v1 -> v2: Added suggested by tag
drivers/pci/bus.c | 2 +-
drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
drivers/pci/controller/dwc/pci-meson.c | 16 +--
drivers/pci/controller/dwc/pcie-armada8k.c | 4 +-
drivers/pci/controller/dwc/pcie-histb.c | 6 +-
drivers/pci/controller/dwc/pcie-intel-gw.c | 10 +-
drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
drivers/pci/controller/dwc/pcie-kirin.c | 6 +-
drivers/pci/controller/dwc/pcie-qcom-ep.c | 18 +--
drivers/pci/controller/dwc/pcie-qcom.c | 18 +--
drivers/pci/controller/dwc/pcie-tegra194.c | 132 +++++++++---------
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 2 +-
drivers/pci/controller/pci-aardvark.c | 6 +-
drivers/pci/controller/pci-ftpci100.c | 2 +-
drivers/pci/controller/pci-tegra.c | 86 ++++++------
drivers/pci/controller/pci-xgene.c | 4 +-
drivers/pci/controller/pcie-microchip-host.c | 2 +-
drivers/pci/controller/pcie-rcar-host.c | 14 +-
drivers/pci/controller/pcie-rockchip.c | 34 ++---
drivers/pci/controller/vmd.c | 2 +-
drivers/pci/doe.c | 4 +-
drivers/pci/endpoint/functions/pci-epf-mhi.c | 8 +-
drivers/pci/endpoint/functions/pci-epf-ntb.c | 2 +-
drivers/pci/endpoint/functions/pci-epf-test.c | 4 +-
drivers/pci/endpoint/functions/pci-epf-vntb.c | 2 +-
drivers/pci/endpoint/pci-ep-cfs.c | 12 +-
drivers/pci/endpoint/pci-epf-core.c | 16 +--
drivers/pci/hotplug/acpiphp_core.c | 2 +-
drivers/pci/hotplug/pciehp_core.c | 8 +-
drivers/pci/hotplug/shpchp_core.c | 4 +-
drivers/pci/of.c | 6 +-
drivers/pci/pci-driver.c | 4 +-
drivers/pci/pcie/dpc.c | 4 +-
drivers/pci/quirks.c | 2 +-
drivers/pci/setup-bus.c | 2 +-
drivers/pci/slot.c | 4 +-
drivers/pci/vgaarb.c | 2 +-
37 files changed, 227 insertions(+), 227 deletions(-)
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index 826b5016a101..dbc16cf5a246 100644
--- a/drivers/pci/bus.c
+++ b/drivers/pci/bus.c
@@ -351,7 +351,7 @@ void pci_bus_add_device(struct pci_dev *dev)
dev->match_driver = !dn || of_device_is_available(dn);
retval = device_attach(&dev->dev);
if (retval < 0 && retval != -EPROBE_DEFER)
- pci_warn(dev, "device attach failed (%d)\n", retval);
+ pci_warn(dev, "device attach failed: %pe\n", ERR_PTR(retval));
pci_dev_assign_added(dev, true);
}
diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index d2d17d37d3e0..79b6cc7f0287 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -801,7 +801,7 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
if (IS_ERR(reset)) {
ret = PTR_ERR(reset);
- dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
+ dev_err(&pdev->dev, "gpio request failed: %pe\n", ERR_PTR(ret));
goto err_gpio;
}
diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
index 6477c83262c2..c449d7af9d5b 100644
--- a/drivers/pci/controller/dwc/pci-meson.c
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -183,7 +183,7 @@ static inline struct clk *meson_pcie_probe_clock(struct device *dev,
if (rate) {
ret = clk_set_rate(clk, rate);
if (ret) {
- dev_err(dev, "set clk rate failed, ret = %d\n", ret);
+ dev_err(dev, "set clk rate failed: %pe\n", ERR_PTR(ret));
return ERR_PTR(ret);
}
}
@@ -416,7 +416,7 @@ static int meson_pcie_probe(struct platform_device *pdev)
mp->phy = devm_phy_get(dev, "pcie");
if (IS_ERR(mp->phy)) {
- dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
+ dev_err(dev, "get phy failed: %pe\n", mp->phy);
return PTR_ERR(mp->phy);
}
@@ -428,31 +428,31 @@ static int meson_pcie_probe(struct platform_device *pdev)
ret = meson_pcie_get_resets(mp);
if (ret) {
- dev_err(dev, "get reset resource failed, %d\n", ret);
+ dev_err(dev, "get reset resource failed: %pe\n", ERR_PTR(ret));
return ret;
}
ret = meson_pcie_get_mems(pdev, mp);
if (ret) {
- dev_err(dev, "get memory resource failed, %d\n", ret);
+ dev_err(dev, "get memory resource failed: %pe\n", ERR_PTR(ret));
return ret;
}
ret = meson_pcie_power_on(mp);
if (ret) {
- dev_err(dev, "phy power on failed, %d\n", ret);
+ dev_err(dev, "phy power on failed: %pe\n", ERR_PTR(ret));
return ret;
}
ret = meson_pcie_reset(mp);
if (ret) {
- dev_err(dev, "reset failed, %d\n", ret);
+ dev_err(dev, "reset failed: %pe\n", ERR_PTR(ret));
goto err_phy;
}
ret = meson_pcie_probe_clocks(mp);
if (ret) {
- dev_err(dev, "init clock resources failed, %d\n", ret);
+ dev_err(dev, "init clock resources failed: %pe\n", ERR_PTR(ret));
goto err_phy;
}
@@ -460,7 +460,7 @@ static int meson_pcie_probe(struct platform_device *pdev)
ret = dw_pcie_host_init(&pci->pp);
if (ret < 0) {
- dev_err(dev, "Add PCIe port failed, %d\n", ret);
+ dev_err(dev, "Add PCIe port failed: %pe\n", ERR_PTR(ret));
goto err_phy;
}
diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c
index b5c599ccaacf..581ed3e44d3b 100644
--- a/drivers/pci/controller/dwc/pcie-armada8k.c
+++ b/drivers/pci/controller/dwc/pcie-armada8k.c
@@ -134,7 +134,7 @@ static int armada8k_pcie_setup_phys(struct armada8k_pcie *pcie)
ret = armada8k_pcie_enable_phys(pcie);
if (ret)
- dev_err(dev, "Failed to initialize PHY(s) (%d)\n", ret);
+ dev_err(dev, "Failed to initialize PHY(s): %pe\n", ERR_PTR(ret));
return ret;
}
@@ -251,7 +251,7 @@ static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
ret = dw_pcie_host_init(pp);
if (ret) {
- dev_err(dev, "failed to initialize host: %d\n", ret);
+ dev_err(dev, "failed to initialize host: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c
index 7a11c618b9d9..4dde61f79024 100644
--- a/drivers/pci/controller/dwc/pcie-histb.c
+++ b/drivers/pci/controller/dwc/pcie-histb.c
@@ -230,7 +230,7 @@ static int histb_pcie_host_enable(struct dw_pcie_rp *pp)
if (hipcie->vpcie) {
ret = regulator_enable(hipcie->vpcie);
if (ret) {
- dev_err(dev, "failed to enable regulator: %d\n", ret);
+ dev_err(dev, "failed to enable regulator: %pe\n", ERR_PTR(ret));
return ret;
}
}
@@ -337,14 +337,14 @@ static int histb_pcie_probe(struct platform_device *pdev)
GPIOD_OUT_HIGH);
ret = PTR_ERR_OR_ZERO(hipcie->reset_gpio);
if (ret) {
- dev_err(dev, "unable to request reset gpio: %d\n", ret);
+ dev_err(dev, "unable to request reset gpio: %pe\n", ERR_PTR(ret));
return ret;
}
ret = gpiod_set_consumer_name(hipcie->reset_gpio,
"PCIe device power control");
if (ret) {
- dev_err(dev, "unable to set reset gpio name: %d\n", ret);
+ dev_err(dev, "unable to set reset gpio name: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index acbe4f6d3291..3a94feed4fbf 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -155,7 +155,7 @@ static int intel_pcie_ep_rst_init(struct intel_pcie *pcie)
if (IS_ERR(pcie->reset_gpio)) {
ret = PTR_ERR(pcie->reset_gpio);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to request PCIe GPIO: %d\n", ret);
+ dev_err(dev, "Failed to request PCIe GPIO: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -214,7 +214,7 @@ static int intel_pcie_get_resources(struct platform_device *pdev)
if (IS_ERR(pcie->core_clk)) {
ret = PTR_ERR(pcie->core_clk);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get clks: %d\n", ret);
+ dev_err(dev, "Failed to get clks: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -222,7 +222,7 @@ static int intel_pcie_get_resources(struct platform_device *pdev)
if (IS_ERR(pcie->core_rst)) {
ret = PTR_ERR(pcie->core_rst);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get resets: %d\n", ret);
+ dev_err(dev, "Failed to get resets: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -239,7 +239,7 @@ static int intel_pcie_get_resources(struct platform_device *pdev)
if (IS_ERR(pcie->phy)) {
ret = PTR_ERR(pcie->phy);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Couldn't get pcie-phy: %d\n", ret);
+ dev_err(dev, "Couldn't get pcie-phy: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -295,7 +295,7 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)
ret = clk_prepare_enable(pcie->core_clk);
if (ret) {
- dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret);
+ dev_err(pcie->pci.dev, "Core clock enable failed: %pe\n", ERR_PTR(ret));
goto clk_err;
}
diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
index 98bbc83182b4..6b406d2e6e5d 100644
--- a/drivers/pci/controller/dwc/pcie-keembay.c
+++ b/drivers/pci/controller/dwc/pcie-keembay.c
@@ -377,7 +377,7 @@ static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie,
ret = dw_pcie_host_init(pp);
if (ret) {
keembay_ep_reset_assert(pcie);
- dev_err(dev, "Failed to initialize host: %d\n", ret);
+ dev_err(dev, "Failed to initialize host: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
index d5523f302102..cb0ab71b2fc7 100644
--- a/drivers/pci/controller/dwc/pcie-kirin.c
+++ b/drivers/pci/controller/dwc/pcie-kirin.c
@@ -421,7 +421,7 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
ret = of_pci_get_devfn(child);
if (ret < 0) {
- dev_err(dev, "failed to parse devfn: %d\n", ret);
+ dev_err(dev, "failed to parse devfn: %pe\n", ERR_PTR(ret));
goto put_node;
}
@@ -555,8 +555,8 @@ static int kirin_pcie_add_bus(struct pci_bus *bus)
for (i = 0; i < kirin_pcie->num_slots; i++) {
ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1);
if (ret) {
- dev_err(pci->dev, "PERST# %s error: %d\n",
- kirin_pcie->reset_names[i], ret);
+ dev_err(pci->dev, "PERST# %s error: %pe\n",
+ kirin_pcie->reset_names[i], ERR_PTR(ret));
}
}
usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 2fb8c15e7a91..be31a60bc693 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -296,8 +296,8 @@ static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
if (ret)
- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
- ret);
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %pe\n",
+ ERR_PTR(ret));
}
static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
@@ -334,8 +334,8 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
*/
ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
if (ret) {
- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
- ret);
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %pe\n",
+ ERR_PTR(ret));
goto err_phy_off;
}
@@ -368,7 +368,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
ret = qcom_pcie_enable_resources(pcie_ep);
if (ret) {
- dev_err(dev, "Failed to enable resources: %d\n", ret);
+ dev_err(dev, "Failed to enable resources: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -465,7 +465,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep);
if (ret) {
- dev_err(dev, "Failed to complete initialization: %d\n", ret);
+ dev_err(dev, "Failed to complete initialization: %pe\n", ERR_PTR(ret));
goto err_disable_resources;
}
@@ -591,7 +591,7 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);
if (ret) {
- dev_err(dev, "Failed to get io resources %d\n", ret);
+ dev_err(dev, "Failed to get io resources: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -824,13 +824,13 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev)
ret = qcom_pcie_enable_resources(pcie_ep);
if (ret) {
- dev_err(dev, "Failed to enable resources: %d\n", ret);
+ dev_err(dev, "Failed to enable resources: %pe\n", ERR_PTR(ret));
return ret;
}
ret = dw_pcie_ep_init(&pcie_ep->pci.ep);
if (ret) {
- dev_err(dev, "Failed to initialize endpoint: %d\n", ret);
+ dev_err(dev, "Failed to initialize endpoint: %pe\n", ERR_PTR(ret));
goto err_disable_resources;
}
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 14772edcf0d3..9aa78672f64d 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -931,7 +931,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
ret = reset_control_assert(res->rst);
if (ret) {
- dev_err(dev, "reset assert failed (%d)\n", ret);
+ dev_err(dev, "reset assert failed: %pe\n", ERR_PTR(ret));
goto err_disable_clocks;
}
@@ -939,7 +939,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
ret = reset_control_deassert(res->rst);
if (ret) {
- dev_err(dev, "reset deassert failed (%d)\n", ret);
+ dev_err(dev, "reset deassert failed: %pe\n", ERR_PTR(ret));
goto err_disable_clocks;
}
@@ -1135,7 +1135,7 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
ret = reset_control_assert(res->rst);
if (ret) {
- dev_err(dev, "reset assert failed (%d)\n", ret);
+ dev_err(dev, "reset assert failed: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -1147,7 +1147,7 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
ret = reset_control_deassert(res->rst);
if (ret) {
- dev_err(dev, "reset deassert failed (%d)\n", ret);
+ dev_err(dev, "reset deassert failed: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -1418,8 +1418,8 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
*/
ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
if (ret) {
- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
- ret);
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %pe\n",
+ ERR_PTR(ret));
return ret;
}
@@ -1448,8 +1448,8 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
if (ret) {
- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
- ret);
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %pe\n",
+ ERR_PTR(ret));
}
}
@@ -1610,7 +1610,7 @@ static int qcom_pcie_suspend_noirq(struct device *dev)
*/
ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));
if (ret) {
- dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret);
+ dev_err(dev, "Failed to set interconnect bandwidth: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 93f5433c5c55..3c93bb11e068 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1114,38 +1114,38 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt);
if (ret < 0) {
- dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);
+ dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %pe\n", ERR_PTR(ret));
return ret;
}
ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us",
&pcie->aspm_pwr_on_t);
if (ret < 0)
- dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n",
- ret);
+ dev_info(pcie->dev, "Failed to read ASPM Power On time: %pe\n",
+ ERR_PTR(ret));
ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us",
&pcie->aspm_l0s_enter_lat);
if (ret < 0)
dev_info(pcie->dev,
- "Failed to read ASPM L0s Entrance latency: %d\n", ret);
+ "Failed to read ASPM L0s Entrance latency: %pe\n", ERR_PTR(ret));
ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
if (ret < 0) {
- dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
+ dev_err(pcie->dev, "Failed to read num-lanes: %pe\n", ERR_PTR(ret));
return ret;
}
ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid);
if (ret) {
- dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret);
+ dev_err(pcie->dev, "Failed to read Controller-ID: %pe\n", ERR_PTR(ret));
return ret;
}
ret = of_property_count_strings(np, "phy-names");
if (ret < 0) {
- dev_err(pcie->dev, "Failed to find PHY entries: %d\n",
- ret);
+ dev_err(pcie->dev, "Failed to find PHY entries: %pe\n",
+ ERR_PTR(ret));
return ret;
}
pcie->phy_count = ret;
@@ -1186,8 +1186,8 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
level = KERN_DEBUG;
dev_printk(level, pcie->dev,
- dev_fmt("Failed to get PERST GPIO: %d\n"),
- err);
+ dev_fmt("Failed to get PERST GPIO: %pe\n"),
+ ERR_PTR(err));
return err;
}
@@ -1202,8 +1202,8 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
level = KERN_DEBUG;
dev_printk(level, pcie->dev,
- dev_fmt("Failed to get REFCLK select GPIOs: %d\n"),
- err);
+ dev_fmt("Failed to get REFCLK select GPIOs: %pe\n"),
+ ERR_PTR(err));
pcie->pex_refclk_sel_gpiod = NULL;
}
@@ -1336,7 +1336,7 @@ static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
ret = regulator_enable(pcie->slot_ctl_3v3);
if (ret < 0) {
dev_err(pcie->dev,
- "Failed to enable 3.3V slot supply: %d\n", ret);
+ "Failed to enable 3.3V slot supply: %pe\n", ERR_PTR(ret));
return ret;
}
}
@@ -1345,7 +1345,7 @@ static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
ret = regulator_enable(pcie->slot_ctl_12v);
if (ret < 0) {
dev_err(pcie->dev,
- "Failed to enable 12V slot supply: %d\n", ret);
+ "Failed to enable 12V slot supply: %pe\n", ERR_PTR(ret));
goto fail_12v_enable;
}
}
@@ -1383,14 +1383,14 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
if (ret) {
dev_err(pcie->dev,
- "Failed to enable controller %u: %d\n", pcie->cid, ret);
+ "Failed to enable controller %u: %pe\n", pcie->cid, ERR_PTR(ret));
return ret;
}
if (pcie->enable_ext_refclk) {
ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
if (ret) {
- dev_err(pcie->dev, "Failed to init UPHY: %d\n", ret);
+ dev_err(pcie->dev, "Failed to init UPHY: %pe\n", ERR_PTR(ret));
goto fail_pll_init;
}
}
@@ -1401,20 +1401,20 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
ret = regulator_enable(pcie->pex_ctl_supply);
if (ret < 0) {
- dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
+ dev_err(pcie->dev, "Failed to enable regulator: %pe\n", ERR_PTR(ret));
goto fail_reg_en;
}
ret = clk_prepare_enable(pcie->core_clk);
if (ret) {
- dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret);
+ dev_err(pcie->dev, "Failed to enable core clock: %pe\n", ERR_PTR(ret));
goto fail_core_clk;
}
ret = reset_control_deassert(pcie->core_apb_rst);
if (ret) {
- dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n",
- ret);
+ dev_err(pcie->dev, "Failed to deassert core APB reset: %pe\n",
+ ERR_PTR(ret));
goto fail_core_apb_rst;
}
@@ -1431,7 +1431,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
ret = tegra_pcie_enable_phy(pcie);
if (ret) {
- dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret);
+ dev_err(pcie->dev, "Failed to enable PHY: %pe\n", ERR_PTR(ret));
goto fail_phy;
}
@@ -1503,32 +1503,32 @@ static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie)
ret = reset_control_assert(pcie->core_rst);
if (ret)
- dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret);
+ dev_err(pcie->dev, "Failed to assert \"core\" reset: %pe\n", ERR_PTR(ret));
tegra_pcie_disable_phy(pcie);
ret = reset_control_assert(pcie->core_apb_rst);
if (ret)
- dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret);
+ dev_err(pcie->dev, "Failed to assert APB reset: %pe\n", ERR_PTR(ret));
clk_disable_unprepare(pcie->core_clk);
ret = regulator_disable(pcie->pex_ctl_supply);
if (ret)
- dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret);
+ dev_err(pcie->dev, "Failed to disable regulator: %pe\n", ERR_PTR(ret));
tegra_pcie_disable_slot_regulators(pcie);
if (pcie->enable_ext_refclk) {
ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
if (ret)
- dev_err(pcie->dev, "Failed to deinit UPHY: %d\n", ret);
+ dev_err(pcie->dev, "Failed to deinit UPHY: %pe\n", ERR_PTR(ret));
}
ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
if (ret)
- dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
- pcie->cid, ret);
+ dev_err(pcie->dev, "Failed to disable controller %d: %pe\n",
+ pcie->cid, ERR_PTR(ret));
}
static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
@@ -1545,7 +1545,7 @@ static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
ret = dw_pcie_host_init(pp);
if (ret < 0) {
- dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret);
+ dev_err(pcie->dev, "Failed to add PCIe port: %pe\n", ERR_PTR(ret));
goto fail_host_init;
}
@@ -1652,20 +1652,20 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
ret = pm_runtime_get_sync(dev);
if (ret < 0) {
- dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
- ret);
+ dev_err(dev, "Failed to get runtime sync for PCIe dev: %pe\n",
+ ERR_PTR(ret));
goto fail_pm_get_sync;
}
ret = pinctrl_pm_select_default_state(dev);
if (ret < 0) {
- dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
+ dev_err(dev, "Failed to configure sideband pins: %pe\n", ERR_PTR(ret));
goto fail_pm_get_sync;
}
ret = tegra_pcie_init_controller(pcie);
if (ret < 0) {
- dev_err(dev, "Failed to initialize controller: %d\n", ret);
+ dev_err(dev, "Failed to initialize controller: %pe\n", ERR_PTR(ret));
goto fail_pm_get_sync;
}
@@ -1713,7 +1713,7 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
LTSSM_STATE_PRE_DETECT,
1, LTSSM_TIMEOUT);
if (ret)
- dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
+ dev_err(pcie->dev, "Failed to go Detect state: %pe\n", ERR_PTR(ret));
dw_pcie_ep_cleanup(&pcie->pci.ep);
@@ -1730,13 +1730,13 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
if (pcie->enable_ext_refclk) {
ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
if (ret)
- dev_err(pcie->dev, "Failed to turn off UPHY: %d\n",
- ret);
+ dev_err(pcie->dev, "Failed to turn off UPHY: %pe\n",
+ ERR_PTR(ret));
}
ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
if (ret)
- dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret);
+ dev_err(pcie->dev, "Failed to turn off UPHY: %pe\n", ERR_PTR(ret));
pcie->ep_state = EP_STATE_DISABLED;
dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n");
@@ -1756,42 +1756,42 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
ret = pm_runtime_resume_and_get(dev);
if (ret < 0) {
- dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
- ret);
+ dev_err(dev, "Failed to get runtime sync for PCIe dev: %pe\n",
+ ERR_PTR(ret));
return;
}
ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
if (ret) {
- dev_err(pcie->dev, "Failed to enable controller %u: %d\n",
- pcie->cid, ret);
+ dev_err(pcie->dev, "Failed to enable controller %u: %pe\n",
+ pcie->cid, ERR_PTR(ret));
goto fail_set_ctrl_state;
}
if (pcie->enable_ext_refclk) {
ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
if (ret) {
- dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n",
- ret);
+ dev_err(dev, "Failed to init UPHY for PCIe EP: %pe\n",
+ ERR_PTR(ret));
goto fail_pll_init;
}
}
ret = clk_prepare_enable(pcie->core_clk);
if (ret) {
- dev_err(dev, "Failed to enable core clock: %d\n", ret);
+ dev_err(dev, "Failed to enable core clock: %pe\n", ERR_PTR(ret));
goto fail_core_clk_enable;
}
ret = reset_control_deassert(pcie->core_apb_rst);
if (ret) {
- dev_err(dev, "Failed to deassert core APB reset: %d\n", ret);
+ dev_err(dev, "Failed to deassert core APB reset: %pe\n", ERR_PTR(ret));
goto fail_core_apb_rst;
}
ret = tegra_pcie_enable_phy(pcie);
if (ret) {
- dev_err(dev, "Failed to enable PHY: %d\n", ret);
+ dev_err(dev, "Failed to enable PHY: %pe\n", ERR_PTR(ret));
goto fail_phy;
}
@@ -1899,7 +1899,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
ret = dw_pcie_ep_init_registers(ep);
if (ret) {
- dev_err(dev, "Failed to complete initialization: %d\n", ret);
+ dev_err(dev, "Failed to complete initialization: %pe\n", ERR_PTR(ret));
goto fail_init_complete;
}
@@ -2044,14 +2044,14 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME);
if (ret < 0) {
- dev_err(dev, "Failed to set PERST GPIO debounce time: %d\n",
- ret);
+ dev_err(dev, "Failed to set PERST GPIO debounce time: %pe\n",
+ ERR_PTR(ret));
return ret;
}
ret = gpiod_to_irq(pcie->pex_rst_gpiod);
if (ret < 0) {
- dev_err(dev, "Failed to get IRQ for PERST GPIO: %d\n", ret);
+ dev_err(dev, "Failed to get IRQ for PERST GPIO: %pe\n", ERR_PTR(ret));
return ret;
}
pcie->pex_rst_irq = (unsigned int)ret;
@@ -2073,7 +2073,7 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
name, (void *)pcie);
if (ret < 0) {
- dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret);
+ dev_err(dev, "Failed to request IRQ for PERST: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -2081,8 +2081,8 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
ret = dw_pcie_ep_init(ep);
if (ret) {
- dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %d\n",
- ret);
+ dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %pe\n",
+ ERR_PTR(ret));
pm_runtime_disable(dev);
return ret;
}
@@ -2152,15 +2152,15 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
if (IS_ERR(pcie->pex_ctl_supply)) {
ret = PTR_ERR(pcie->pex_ctl_supply);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get regulator: %ld\n",
- PTR_ERR(pcie->pex_ctl_supply));
+ dev_err(dev, "Failed to get regulator: %pe\n",
+ pcie->pex_ctl_supply);
return ret;
}
pcie->core_clk = devm_clk_get(dev, "core");
if (IS_ERR(pcie->core_clk)) {
- dev_err(dev, "Failed to get core clock: %ld\n",
- PTR_ERR(pcie->core_clk));
+ dev_err(dev, "Failed to get core clock: %pe\n",
+ pcie->core_clk);
return PTR_ERR(pcie->core_clk);
}
@@ -2177,8 +2177,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
if (IS_ERR(pcie->core_apb_rst)) {
- dev_err(dev, "Failed to get APB reset: %ld\n",
- PTR_ERR(pcie->core_apb_rst));
+ dev_err(dev, "Failed to get APB reset: %pe\n",
+ pcie->core_apb_rst);
return PTR_ERR(pcie->core_apb_rst);
}
@@ -2197,7 +2197,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
if (IS_ERR(phys[i])) {
ret = PTR_ERR(phys[i]);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get PHY: %d\n", ret);
+ dev_err(dev, "Failed to get PHY: %pe\n", ERR_PTR(ret));
return ret;
}
}
@@ -2219,8 +2219,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
pcie->core_rst = devm_reset_control_get(dev, "core");
if (IS_ERR(pcie->core_rst)) {
- dev_err(dev, "Failed to get core reset: %ld\n",
- PTR_ERR(pcie->core_rst));
+ dev_err(dev, "Failed to get core reset: %pe\n",
+ pcie->core_rst);
return PTR_ERR(pcie->core_rst);
}
@@ -2247,8 +2247,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler,
IRQF_SHARED, "tegra-pcie-intr", pcie);
if (ret) {
- dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
- ret);
+ dev_err(dev, "Failed to request IRQ %d: %pe\n", pp->irq,
+ ERR_PTR(ret));
goto fail;
}
@@ -2266,8 +2266,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
IRQF_SHARED | IRQF_ONESHOT,
"tegra-pcie-ep-intr", pcie);
if (ret) {
- dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
- ret);
+ dev_err(dev, "Failed to request IRQ %d: %pe\n", pp->irq,
+ ERR_PTR(ret));
goto fail;
}
@@ -2364,7 +2364,7 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)
ret = tegra_pcie_dw_host_init(&pcie->pci.pp);
if (ret < 0) {
- dev_err(dev, "Failed to init host: %d\n", ret);
+ dev_err(dev, "Failed to init host: %pe\n", ERR_PTR(ret));
goto fail_host_init;
}
diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index a2b844268e28..9a3d5445f181 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -388,7 +388,7 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
priv->phy = devm_phy_optional_get(dev, "pcie-phy");
if (IS_ERR(priv->phy)) {
ret = PTR_ERR(priv->phy);
- dev_err(dev, "Failed to get phy (%d)\n", ret);
+ dev_err(dev, "Failed to get phy: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 71ecd7ddcc8a..f34e0e163642 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -1743,14 +1743,14 @@ static int advk_pcie_setup_phy(struct advk_pcie *pcie)
/* Old bindings miss the PHY handle */
if (IS_ERR(pcie->phy)) {
- dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy));
+ dev_warn(dev, "PHY unavailable: %pe\n", pcie->phy);
pcie->phy = NULL;
return 0;
}
ret = advk_pcie_enable_phy(pcie);
if (ret)
- dev_err(dev, "Failed to initialize PHY (%d)\n", ret);
+ dev_err(dev, "Failed to initialize PHY: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -1863,7 +1863,7 @@ static int advk_pcie_probe(struct platform_device *pdev)
ret = PTR_ERR_OR_ZERO(pcie->reset_gpio);
if (ret) {
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get reset-gpio: %i\n", ret);
+ dev_err(dev, "Failed to get reset-gpio: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/pci-ftpci100.c b/drivers/pci/controller/pci-ftpci100.c
index ffdeed25e961..b5127dbdd313 100644
--- a/drivers/pci/controller/pci-ftpci100.c
+++ b/drivers/pci/controller/pci-ftpci100.c
@@ -502,7 +502,7 @@ static int faraday_pci_probe(struct platform_device *pdev)
ret = pci_scan_root_bus_bridge(host);
if (ret) {
- dev_err(dev, "failed to scan host: %d\n", ret);
+ dev_err(dev, "failed to scan host: %pe\n", ERR_PTR(ret));
return ret;
}
p->bus = host->bus;
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 038d974a318e..ead171db29b7 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -946,7 +946,7 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
/* wait for the PLL to lock */
err = tegra_pcie_pll_wait(pcie, 500);
if (err < 0) {
- dev_err(dev, "PLL failed to lock: %d\n", err);
+ dev_err(dev, "PLL failed to lock: %pe\n", ERR_PTR(err));
return err;
}
@@ -997,7 +997,7 @@ static int tegra_pcie_port_phy_power_on(struct tegra_pcie_port *port)
for (i = 0; i < port->lanes; i++) {
err = phy_power_on(port->phys[i]);
if (err < 0) {
- dev_err(dev, "failed to power on PHY#%u: %d\n", i, err);
+ dev_err(dev, "failed to power on PHY#%u: %pe\n", i, ERR_PTR(err));
return err;
}
}
@@ -1014,8 +1014,8 @@ static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
for (i = 0; i < port->lanes; i++) {
err = phy_power_off(port->phys[i]);
if (err < 0) {
- dev_err(dev, "failed to power off PHY#%u: %d\n", i,
- err);
+ dev_err(dev, "failed to power off PHY#%u: %pe\n", i,
+ ERR_PTR(err));
return err;
}
}
@@ -1036,7 +1036,7 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
err = tegra_pcie_phy_enable(pcie);
if (err < 0)
- dev_err(dev, "failed to power on PHY: %d\n", err);
+ dev_err(dev, "failed to power on PHY: %pe\n", ERR_PTR(err));
return err;
}
@@ -1045,8 +1045,8 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
err = tegra_pcie_port_phy_power_on(port);
if (err < 0) {
dev_err(dev,
- "failed to power on PCIe port %u PHY: %d\n",
- port->index, err);
+ "failed to power on PCIe port %u PHY: %pe\n",
+ port->index, ERR_PTR(err));
return err;
}
}
@@ -1067,7 +1067,7 @@ static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
err = tegra_pcie_phy_disable(pcie);
if (err < 0)
- dev_err(dev, "failed to power off PHY: %d\n", err);
+ dev_err(dev, "failed to power off PHY: %pe\n", ERR_PTR(err));
return err;
}
@@ -1076,8 +1076,8 @@ static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
err = tegra_pcie_port_phy_power_off(port);
if (err < 0) {
dev_err(dev,
- "failed to power off PCIe port %u PHY: %d\n",
- port->index, err);
+ "failed to power off PCIe port %u PHY: %pe\n",
+ port->index, ERR_PTR(err));
return err;
}
}
@@ -1167,7 +1167,7 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
if (err < 0)
- dev_warn(dev, "failed to disable regulators: %d\n", err);
+ dev_warn(dev, "failed to disable regulators: %pe\n", ERR_PTR(err));
}
static int tegra_pcie_power_on(struct tegra_pcie *pcie)
@@ -1186,38 +1186,38 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
/* enable regulators */
err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
if (err < 0)
- dev_err(dev, "failed to enable regulators: %d\n", err);
+ dev_err(dev, "failed to enable regulators: %pe\n", ERR_PTR(err));
if (!dev->pm_domain) {
err = tegra_powergate_power_on(TEGRA_POWERGATE_PCIE);
if (err) {
- dev_err(dev, "failed to power ungate: %d\n", err);
+ dev_err(dev, "failed to power ungate: %pe\n", ERR_PTR(err));
goto regulator_disable;
}
err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_PCIE);
if (err) {
- dev_err(dev, "failed to remove clamp: %d\n", err);
+ dev_err(dev, "failed to remove clamp: %pe\n", ERR_PTR(err));
goto powergate;
}
}
err = clk_prepare_enable(pcie->afi_clk);
if (err < 0) {
- dev_err(dev, "failed to enable AFI clock: %d\n", err);
+ dev_err(dev, "failed to enable AFI clock: %pe\n", ERR_PTR(err));
goto powergate;
}
if (soc->has_cml_clk) {
err = clk_prepare_enable(pcie->cml_clk);
if (err < 0) {
- dev_err(dev, "failed to enable CML clock: %d\n", err);
+ dev_err(dev, "failed to enable CML clock: %pe\n", ERR_PTR(err));
goto disable_afi_clk;
}
}
err = clk_prepare_enable(pcie->pll_e);
if (err < 0) {
- dev_err(dev, "failed to enable PLLE clock: %d\n", err);
+ dev_err(dev, "failed to enable PLLE clock: %pe\n", ERR_PTR(err));
goto disable_cml_clk;
}
@@ -1303,13 +1303,13 @@ static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie)
pcie->phy = devm_phy_optional_get(dev, "pcie");
if (IS_ERR(pcie->phy)) {
err = PTR_ERR(pcie->phy);
- dev_err(dev, "failed to get PHY: %d\n", err);
+ dev_err(dev, "failed to get PHY: %pe\n", ERR_PTR(err));
return err;
}
err = phy_init(pcie->phy);
if (err < 0) {
- dev_err(dev, "failed to initialize PHY: %d\n", err);
+ dev_err(dev, "failed to initialize PHY: %pe\n", ERR_PTR(err));
return err;
}
@@ -1350,15 +1350,15 @@ static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port)
for (i = 0; i < port->lanes; i++) {
phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i);
if (IS_ERR(phy)) {
- dev_err(dev, "failed to get PHY#%u: %ld\n", i,
- PTR_ERR(phy));
+ dev_err(dev, "failed to get PHY#%u: %pe\n", i,
+ phy);
return PTR_ERR(phy);
}
err = phy_init(phy);
if (err < 0) {
- dev_err(dev, "failed to initialize PHY#%u: %d\n", i,
- err);
+ dev_err(dev, "failed to initialize PHY#%u: %pe\n", i,
+ ERR_PTR(err));
return err;
}
@@ -1396,7 +1396,7 @@ static void tegra_pcie_phys_put(struct tegra_pcie *pcie)
if (pcie->legacy_phy) {
err = phy_exit(pcie->phy);
if (err < 0)
- dev_err(dev, "failed to teardown PHY: %d\n", err);
+ dev_err(dev, "failed to teardown PHY: %pe\n", ERR_PTR(err));
return;
}
@@ -1404,8 +1404,8 @@ static void tegra_pcie_phys_put(struct tegra_pcie *pcie)
for (i = 0; i < port->lanes; i++) {
err = phy_exit(port->phys[i]);
if (err < 0)
- dev_err(dev, "failed to teardown PHY#%u: %d\n",
- i, err);
+ dev_err(dev, "failed to teardown PHY#%u: %pe\n",
+ i, ERR_PTR(err));
}
}
}
@@ -1420,20 +1420,20 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
err = tegra_pcie_clocks_get(pcie);
if (err) {
- dev_err(dev, "failed to get clocks: %d\n", err);
+ dev_err(dev, "failed to get clocks: %pe\n", ERR_PTR(err));
return err;
}
err = tegra_pcie_resets_get(pcie);
if (err) {
- dev_err(dev, "failed to get resets: %d\n", err);
+ dev_err(dev, "failed to get resets: %pe\n", ERR_PTR(err));
return err;
}
if (soc->program_uphy) {
err = tegra_pcie_phys_get(pcie);
if (err < 0) {
- dev_err(dev, "failed to get PHYs: %d\n", err);
+ dev_err(dev, "failed to get PHYs: %pe\n", ERR_PTR(err));
return err;
}
}
@@ -1477,7 +1477,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
if (err) {
- dev_err(dev, "failed to register IRQ: %d\n", err);
+ dev_err(dev, "failed to register IRQ: %pe\n", ERR_PTR(err));
goto phys_put;
}
@@ -2127,7 +2127,7 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
err = of_pci_get_devfn(port);
if (err < 0) {
- dev_err(dev, "failed to parse address: %d\n", err);
+ dev_err(dev, "failed to parse address: %pe\n", ERR_PTR(err));
goto err_node_put;
}
@@ -2143,8 +2143,8 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
err = of_property_read_u32(port, "nvidia,num-lanes", &value);
if (err < 0) {
- dev_err(dev, "failed to parse # of lanes: %d\n",
- err);
+ dev_err(dev, "failed to parse # of lanes: %pe\n",
+ ERR_PTR(err));
goto err_node_put;
}
@@ -2172,7 +2172,7 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
err = of_address_to_resource(port, 0, &rp->regs);
if (err < 0) {
- dev_err(dev, "failed to parse address: %d\n", err);
+ dev_err(dev, "failed to parse address: %pe\n", ERR_PTR(err));
goto err_node_put;
}
@@ -2640,20 +2640,20 @@ static int tegra_pcie_probe(struct platform_device *pdev)
err = tegra_pcie_get_resources(pcie);
if (err < 0) {
- dev_err(dev, "failed to request resources: %d\n", err);
+ dev_err(dev, "failed to request resources: %pe\n", ERR_PTR(err));
return err;
}
err = tegra_pcie_msi_setup(pcie);
if (err < 0) {
- dev_err(dev, "failed to enable MSI support: %d\n", err);
+ dev_err(dev, "failed to enable MSI support: %pe\n", ERR_PTR(err));
goto put_resources;
}
pm_runtime_enable(pcie->dev);
err = pm_runtime_get_sync(pcie->dev);
if (err < 0) {
- dev_err(dev, "fail to enable pcie controller: %d\n", err);
+ dev_err(dev, "fail to enable pcie controller: %pe\n", ERR_PTR(err));
goto pm_runtime_put;
}
@@ -2662,7 +2662,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
err = pci_host_probe(host);
if (err < 0) {
- dev_err(dev, "failed to register host: %d\n", err);
+ dev_err(dev, "failed to register host: %pe\n", ERR_PTR(err));
goto pm_runtime_put;
}
@@ -2723,7 +2723,7 @@ static int tegra_pcie_pm_suspend(struct device *dev)
if (pcie->soc->program_uphy) {
err = tegra_pcie_phy_power_off(pcie);
if (err < 0)
- dev_err(dev, "failed to power off PHY(s): %d\n", err);
+ dev_err(dev, "failed to power off PHY(s): %pe\n", ERR_PTR(err));
}
reset_control_assert(pcie->pex_rst);
@@ -2745,13 +2745,13 @@ static int tegra_pcie_pm_resume(struct device *dev)
err = tegra_pcie_power_on(pcie);
if (err) {
- dev_err(dev, "tegra pcie power on fail: %d\n", err);
+ dev_err(dev, "tegra pcie power on fail: %pe\n", ERR_PTR(err));
return err;
}
err = pinctrl_pm_select_default_state(dev);
if (err < 0) {
- dev_err(dev, "failed to disable PCIe IO DPD: %d\n", err);
+ dev_err(dev, "failed to disable PCIe IO DPD: %pe\n", ERR_PTR(err));
goto poweroff;
}
@@ -2763,7 +2763,7 @@ static int tegra_pcie_pm_resume(struct device *dev)
err = clk_prepare_enable(pcie->pex_clk);
if (err) {
- dev_err(dev, "failed to enable PEX clock: %d\n", err);
+ dev_err(dev, "failed to enable PEX clock: %pe\n", ERR_PTR(err));
goto pex_dpd_enable;
}
@@ -2772,7 +2772,7 @@ static int tegra_pcie_pm_resume(struct device *dev)
if (pcie->soc->program_uphy) {
err = tegra_pcie_phy_power_on(pcie);
if (err < 0) {
- dev_err(dev, "failed to power on PHY(s): %d\n", err);
+ dev_err(dev, "failed to power on PHY(s): %pe\n", ERR_PTR(err));
goto disable_pex_clk;
}
}
diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
index 8e457fa450a2..9cdc0b24e00d 100644
--- a/drivers/pci/controller/pci-xgene.c
+++ b/drivers/pci/controller/pci-xgene.c
@@ -206,8 +206,8 @@ static int xgene_get_csr_resource(struct acpi_device *adev,
acpi_dev_filter_resource_type_cb,
(void *) flags);
if (ret < 0) {
- dev_err(dev, "failed to parse _CRS method, error code %d\n",
- ret);
+ dev_err(dev, "failed to parse _CRS method, error code %pe\n",
+ ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c
index 137fb8570ba2..9670a31a02c8 100644
--- a/drivers/pci/controller/pcie-microchip-host.c
+++ b/drivers/pci/controller/pcie-microchip-host.c
@@ -1175,7 +1175,7 @@ static int mc_host_probe(struct platform_device *pdev)
ret = mc_pcie_init_clks(dev);
if (ret) {
- dev_err(dev, "failed to get clock resources, error %d\n", ret);
+ dev_err(dev, "failed to get clock resources, error: %pe\n", ERR_PTR(ret));
return -ENODEV;
}
diff --git a/drivers/pci/controller/pcie-rcar-host.c b/drivers/pci/controller/pcie-rcar-host.c
index 996077ab7cfd..3dfe6729e3ed 100644
--- a/drivers/pci/controller/pcie-rcar-host.c
+++ b/drivers/pci/controller/pcie-rcar-host.c
@@ -78,7 +78,7 @@ static int rcar_pcie_wakeup(struct device *pcie_dev, void __iomem *pcie_base)
writel(L1IATN, pcie_base + PMCTLR);
ret = readl_poll_timeout_atomic(pcie_base + PMSR, val,
val & L1FAEG, 10, 1000);
- WARN(ret, "Timeout waiting for L1 link state, ret=%d\n", ret);
+ WARN(ret, "Timeout waiting for L1 link state, ret=%pe\n", ERR_PTR(ret));
writel(L1FAEG | PMEL1RX, pcie_base + PMSR);
}
@@ -782,7 +782,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
IRQF_SHARED | IRQF_NO_THREAD,
rcar_msi_bottom_chip.name, host);
if (err < 0) {
- dev_err(dev, "failed to request IRQ: %d\n", err);
+ dev_err(dev, "failed to request IRQ: %pe\n", ERR_PTR(err));
goto err;
}
@@ -790,7 +790,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
IRQF_SHARED | IRQF_NO_THREAD,
rcar_msi_bottom_chip.name, host);
if (err < 0) {
- dev_err(dev, "failed to request IRQ: %d\n", err);
+ dev_err(dev, "failed to request IRQ: %pe\n", ERR_PTR(err));
goto err;
}
@@ -996,13 +996,13 @@ static int rcar_pcie_probe(struct platform_device *pdev)
err = rcar_pcie_get_resources(host);
if (err < 0) {
- dev_err(dev, "failed to request resources: %d\n", err);
+ dev_err(dev, "failed to request resources: %pe\n", ERR_PTR(err));
goto err_pm_put;
}
err = clk_prepare_enable(host->bus_clk);
if (err) {
- dev_err(dev, "failed to enable bus clock: %d\n", err);
+ dev_err(dev, "failed to enable bus clock: %pe\n", ERR_PTR(err));
goto err_unmap_msi_irqs;
}
@@ -1031,8 +1031,8 @@ static int rcar_pcie_probe(struct platform_device *pdev)
err = rcar_pcie_enable_msi(host);
if (err < 0) {
dev_err(dev,
- "failed to enable MSI support: %d\n",
- err);
+ "failed to enable MSI support: %pe\n",
+ ERR_PTR(err));
goto err_phy_shutdown;
}
}
diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
index 0ef2e622d36e..10bd6aec67bd 100644
--- a/drivers/pci/controller/pcie-rockchip.c
+++ b/drivers/pci/controller/pcie-rockchip.c
@@ -169,51 +169,51 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
err = reset_control_assert(rockchip->aclk_rst);
if (err) {
- dev_err(dev, "assert aclk_rst err %d\n", err);
+ dev_err(dev, "assert aclk_rst err: %pe\n", ERR_PTR(err));
return err;
}
err = reset_control_assert(rockchip->pclk_rst);
if (err) {
- dev_err(dev, "assert pclk_rst err %d\n", err);
+ dev_err(dev, "assert pclk_rst err: %pe\n", ERR_PTR(err));
return err;
}
err = reset_control_assert(rockchip->pm_rst);
if (err) {
- dev_err(dev, "assert pm_rst err %d\n", err);
+ dev_err(dev, "assert pm_rst err: %pe\n", ERR_PTR(err));
return err;
}
for (i = 0; i < MAX_LANE_NUM; i++) {
err = phy_init(rockchip->phys[i]);
if (err) {
- dev_err(dev, "init phy%d err %d\n", i, err);
+ dev_err(dev, "init phy%d err: %pe\n", i, ERR_PTR(err));
goto err_exit_phy;
}
}
err = reset_control_assert(rockchip->core_rst);
if (err) {
- dev_err(dev, "assert core_rst err %d\n", err);
+ dev_err(dev, "assert core_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_assert(rockchip->mgmt_rst);
if (err) {
- dev_err(dev, "assert mgmt_rst err %d\n", err);
+ dev_err(dev, "assert mgmt_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_assert(rockchip->mgmt_sticky_rst);
if (err) {
- dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
+ dev_err(dev, "assert mgmt_sticky_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_assert(rockchip->pipe_rst);
if (err) {
- dev_err(dev, "assert pipe_rst err %d\n", err);
+ dev_err(dev, "assert pipe_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
@@ -221,19 +221,19 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
err = reset_control_deassert(rockchip->pm_rst);
if (err) {
- dev_err(dev, "deassert pm_rst err %d\n", err);
+ dev_err(dev, "deassert pm_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_deassert(rockchip->aclk_rst);
if (err) {
- dev_err(dev, "deassert aclk_rst err %d\n", err);
+ dev_err(dev, "deassert aclk_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_deassert(rockchip->pclk_rst);
if (err) {
- dev_err(dev, "deassert pclk_rst err %d\n", err);
+ dev_err(dev, "deassert pclk_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
@@ -257,7 +257,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
for (i = 0; i < MAX_LANE_NUM; i++) {
err = phy_power_on(rockchip->phys[i]);
if (err) {
- dev_err(dev, "power on phy%d err %d\n", i, err);
+ dev_err(dev, "power on phy%d err: %pe\n", i, ERR_PTR(err));
goto err_power_off_phy;
}
}
@@ -268,7 +268,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
RK_PHY_PLL_LOCK_SLEEP_US,
RK_PHY_PLL_LOCK_TIMEOUT_US);
if (err) {
- dev_err(dev, "PHY PLLs could not lock, %d\n", err);
+ dev_err(dev, "PHY PLLs could not lock: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
@@ -278,25 +278,25 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
*/
err = reset_control_deassert(rockchip->mgmt_sticky_rst);
if (err) {
- dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
+ dev_err(dev, "deassert mgmt_sticky_rst err: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
err = reset_control_deassert(rockchip->core_rst);
if (err) {
- dev_err(dev, "deassert core_rst err %d\n", err);
+ dev_err(dev, "deassert core_rst err: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
err = reset_control_deassert(rockchip->mgmt_rst);
if (err) {
- dev_err(dev, "deassert mgmt_rst err %d\n", err);
+ dev_err(dev, "deassert mgmt_rst err: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
err = reset_control_deassert(rockchip->pipe_rst);
if (err) {
- dev_err(dev, "deassert pipe_rst err %d\n", err);
+ dev_err(dev, "deassert pipe_rst err: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c
index 87b7856f375a..7bc123865b1f 100644
--- a/drivers/pci/controller/vmd.c
+++ b/drivers/pci/controller/vmd.c
@@ -943,7 +943,7 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
struct pci_dev, bus_list);
ret = pci_reset_bus(dev);
if (ret)
- pci_warn(dev, "can't reset device: %d\n", ret);
+ pci_warn(dev, "can't reset device: %pe\n", ERR_PTR(ret));
break;
}
diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c
index 652d63df9d22..8019a7140028 100644
--- a/drivers/pci/doe.c
+++ b/drivers/pci/doe.c
@@ -512,8 +512,8 @@ static struct pci_doe_mb *pci_doe_create_mb(struct pci_dev *pdev,
*/
rc = pci_doe_cache_protocols(doe_mb);
if (rc) {
- pci_err(pdev, "[%x] failed to cache protocols : %d\n",
- doe_mb->cap_offset, rc);
+ pci_err(pdev, "[%x] failed to cache protocols : %pe\n",
+ doe_mb->cap_offset, ERR_PTR(rc));
goto err_cancel;
}
diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c
index 2c54d80107cf..78d64eecfa04 100644
--- a/drivers/pci/endpoint/functions/pci-epf-mhi.c
+++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c
@@ -738,14 +738,14 @@ static int pci_epf_mhi_core_init(struct pci_epf *epf)
ret = pci_epc_set_msi(epc, epf->func_no, epf->vfunc_no,
order_base_2(info->msi_count));
if (ret) {
- dev_err(dev, "Failed to set MSI configuration: %d\n", ret);
+ dev_err(dev, "Failed to set MSI configuration: %pe\n", ERR_PTR(ret));
return ret;
}
ret = pci_epc_write_header(epc, epf->func_no, epf->vfunc_no,
epf->header);
if (ret) {
- dev_err(dev, "Failed to set Configuration header: %d\n", ret);
+ dev_err(dev, "Failed to set Configuration header: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -768,7 +768,7 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf)
if (info->flags & MHI_EPF_USE_DMA) {
ret = pci_epf_mhi_dma_init(epf_mhi);
if (ret) {
- dev_err(dev, "Failed to initialize DMA: %d\n", ret);
+ dev_err(dev, "Failed to initialize DMA: %pe\n", ERR_PTR(ret));
return ret;
}
}
@@ -794,7 +794,7 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf)
/* Register the MHI EP controller */
ret = mhi_ep_register_controller(mhi_cntrl, info->config);
if (ret) {
- dev_err(dev, "Failed to register MHI EP controller: %d\n", ret);
+ dev_err(dev, "Failed to register MHI EP controller: %pe\n", ERR_PTR(ret));
if (info->flags & MHI_EPF_USE_DMA)
pci_epf_mhi_dma_deinit(epf_mhi);
return ret;
diff --git a/drivers/pci/endpoint/functions/pci-epf-ntb.c b/drivers/pci/endpoint/functions/pci-epf-ntb.c
index e01a98e74d21..d807b0329805 100644
--- a/drivers/pci/endpoint/functions/pci-epf-ntb.c
+++ b/drivers/pci/endpoint/functions/pci-epf-ntb.c
@@ -2129,7 +2129,7 @@ static int __init epf_ntb_init(void)
ret = pci_epf_register_driver(&epf_ntb_driver);
if (ret) {
destroy_workqueue(kpcintb_workqueue);
- pr_err("Failed to register pci epf ntb driver --> %d\n", ret);
+ pr_err("Failed to register pci epf ntb driver: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index 977fb79c1567..15e745dcdc40 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -167,7 +167,7 @@ static int pci_epf_test_data_transfer(struct pci_epf_test *epf_test,
ret = dma_submit_error(epf_test->transfer_cookie);
if (ret) {
- dev_err(dev, "Failed to do DMA tx_submit %d\n", ret);
+ dev_err(dev, "Failed to do DMA tx_submit: %pe\n", ERR_PTR(ret));
goto terminate;
}
@@ -949,7 +949,7 @@ static int __init pci_epf_test_init(void)
ret = pci_epf_register_driver(&test_driver);
if (ret) {
destroy_workqueue(kpcitest_workqueue);
- pr_err("Failed to register pci epf test driver --> %d\n", ret);
+ pr_err("Failed to register pci epf test driver: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c
index 8e779eecd62d..de52f0613078 100644
--- a/drivers/pci/endpoint/functions/pci-epf-vntb.c
+++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c
@@ -1430,7 +1430,7 @@ static int __init epf_ntb_init(void)
ret = pci_epf_register_driver(&epf_ntb_driver);
if (ret) {
destroy_workqueue(kpcintb_workqueue);
- pr_err("Failed to register pci epf ntb driver --> %d\n", ret);
+ pr_err("Failed to register pci epf ntb driver: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c
index 3b21e28f9b59..a44437aaa4bc 100644
--- a/drivers/pci/endpoint/pci-ep-cfs.c
+++ b/drivers/pci/endpoint/pci-ep-cfs.c
@@ -727,8 +727,8 @@ static int __init pci_ep_cfs_init(void)
ret = configfs_register_subsystem(&pci_ep_cfs_subsys);
if (ret) {
- pr_err("Error %d while registering subsystem %s\n",
- ret, root->cg_item.ci_namebuf);
+ pr_err("Error while registering subsystem %s: %pe\n",
+ root->cg_item.ci_namebuf, ERR_PTR(ret));
goto err;
}
@@ -736,8 +736,8 @@ static int __init pci_ep_cfs_init(void)
&pci_functions_type);
if (IS_ERR(functions_group)) {
ret = PTR_ERR(functions_group);
- pr_err("Error %d while registering functions group\n",
- ret);
+ pr_err("Error while registering functions group: %pe\n",
+ ERR_PTR(ret));
goto err_functions_group;
}
@@ -746,8 +746,8 @@ static int __init pci_ep_cfs_init(void)
&pci_controllers_type);
if (IS_ERR(controllers_group)) {
ret = PTR_ERR(controllers_group);
- pr_err("Error %d while registering controllers group\n",
- ret);
+ pr_err("Error while registering controllers group: %pe\n",
+ ERR_PTR(ret));
goto err_controllers_group;
}
diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c
index 323f2a60ab16..08146b5c5d01 100644
--- a/drivers/pci/endpoint/pci-epf-core.c
+++ b/drivers/pci/endpoint/pci-epf-core.c
@@ -77,8 +77,8 @@ int pci_epf_bind(struct pci_epf *epf)
vfunc_no = epf_vf->vfunc_no;
if (vfunc_no < 1) {
- dev_err(dev, "Invalid virtual function number\n");
ret = -EINVAL;
+ dev_err(dev, "Invalid virtual function number: %pe\n", ERR_PTR(ret));
goto ret;
}
@@ -86,15 +86,15 @@ int pci_epf_bind(struct pci_epf *epf)
func_no = epf->func_no;
if (!IS_ERR_OR_NULL(epc)) {
if (!epc->max_vfs) {
- dev_err(dev, "No support for virt function\n");
ret = -EINVAL;
+ dev_err(dev, "No support for virt function: %pe\n", ERR_PTR(ret));
goto ret;
}
if (vfunc_no > epc->max_vfs[func_no]) {
- dev_err(dev, "PF%d: Exceeds max vfunc number\n",
- func_no);
ret = -EINVAL;
+ dev_err(dev, "PF%d: Exceeds max vfunc number: %pe\n",
+ func_no, ERR_PTR(ret));
goto ret;
}
}
@@ -103,15 +103,15 @@ int pci_epf_bind(struct pci_epf *epf)
func_no = epf->sec_epc_func_no;
if (!IS_ERR_OR_NULL(epc)) {
if (!epc->max_vfs) {
- dev_err(dev, "No support for virt function\n");
ret = -EINVAL;
+ dev_err(dev, "No support for virt function: %pe\n", ERR_PTR(ret));
goto ret;
}
if (vfunc_no > epc->max_vfs[func_no]) {
- dev_err(dev, "PF%d: Exceeds max vfunc number\n",
- func_no);
ret = -EINVAL;
+ dev_err(dev, "PF%d: Exceeds max vfunc number: %pe\n",
+ func_no, ERR_PTR(ret));
goto ret;
}
}
@@ -535,7 +535,7 @@ static int __init pci_epf_init(void)
ret = bus_register(&pci_epf_bus_type);
if (ret) {
- pr_err("failed to register pci epf bus --> %d\n", ret);
+ pr_err("failed to register pci epf bus: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/hotplug/acpiphp_core.c b/drivers/pci/hotplug/acpiphp_core.c
index 9dad14e80bcf..0f5523666e85 100644
--- a/drivers/pci/hotplug/acpiphp_core.c
+++ b/drivers/pci/hotplug/acpiphp_core.c
@@ -277,7 +277,7 @@ int acpiphp_register_hotplug_slot(struct acpiphp_slot *acpiphp_slot,
if (retval == -EBUSY)
goto error_slot;
if (retval) {
- pr_err("pci_hp_register failed with error %d\n", retval);
+ pr_err("pci_hp_register failed with error: %pe\n", ERR_PTR(retval));
goto error_slot;
}
diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c
index ddd55ad97a58..c1ccff9c282e 100644
--- a/drivers/pci/hotplug/pciehp_core.c
+++ b/drivers/pci/hotplug/pciehp_core.c
@@ -81,7 +81,7 @@ static int init_slot(struct controller *ctrl)
retval = pci_hp_initialize(&ctrl->hotplug_slot,
ctrl->pcie->port->subordinate, 0, name);
if (retval) {
- ctrl_err(ctrl, "pci_hp_initialize failed: error %d\n", retval);
+ ctrl_err(ctrl, "pci_hp_initialize failed with error: %pe\n", ERR_PTR(retval));
kfree(ops);
}
return retval;
@@ -210,21 +210,21 @@ static int pciehp_probe(struct pcie_device *dev)
if (rc == -EBUSY)
ctrl_warn(ctrl, "Slot already registered by another hotplug driver\n");
else
- ctrl_err(ctrl, "Slot initialization failed (%d)\n", rc);
+ ctrl_err(ctrl, "Slot initialization failed: %pe\n", ERR_PTR(rc));
goto err_out_release_ctlr;
}
/* Enable events after we have setup the data structures */
rc = pcie_init_notification(ctrl);
if (rc) {
- ctrl_err(ctrl, "Notification initialization failed (%d)\n", rc);
+ ctrl_err(ctrl, "Notification initialization failed: %d\n", rc);
goto err_out_free_ctrl_slot;
}
/* Publish to user space */
rc = pci_hp_add(&ctrl->hotplug_slot);
if (rc) {
- ctrl_err(ctrl, "Publication to user space failed (%d)\n", rc);
+ ctrl_err(ctrl, "Publication to user space failed: %pe\n", ERR_PTR(rc));
goto err_out_shutdown_notification;
}
diff --git a/drivers/pci/hotplug/shpchp_core.c b/drivers/pci/hotplug/shpchp_core.c
index 56c7795ed890..b4e3cef70bf6 100644
--- a/drivers/pci/hotplug/shpchp_core.c
+++ b/drivers/pci/hotplug/shpchp_core.c
@@ -104,8 +104,8 @@ static int init_slots(struct controller *ctrl)
retval = pci_hp_register(hotplug_slot,
ctrl->pci_dev->subordinate, slot->device, name);
if (retval) {
- ctrl_err(ctrl, "pci_hp_register failed with error %d\n",
- retval);
+ ctrl_err(ctrl, "pci_hp_register failed with error: %pe\n",
+ ERR_PTR(retval));
goto error_slotwq;
}
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index 51e3dd0ea5ab..2163ee1eda46 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -518,7 +518,7 @@ static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *
pr_warn_once("%s: possibly some PCI slots don't have level triggered interrupts capability\n",
__func__);
} else {
- dev_err(&pdev->dev, "%s: failed with rc=%d\n", __func__, rc);
+ dev_err(&pdev->dev, "%s: failed with rc=%pe\n", __func__, ERR_PTR(rc));
}
return rc;
}
@@ -573,8 +573,8 @@ static int pci_parse_request_of_pci_ranges(struct device *dev,
case IORESOURCE_IO:
err = devm_pci_remap_iospace(dev, res, iobase);
if (err) {
- dev_warn(dev, "error %d: failed to map resource %pR\n",
- err, res);
+ dev_warn(dev, "failed to map resource %pR with error: %pe\n",
+ res, ERR_PTR(err));
resource_list_destroy_entry(win);
}
break;
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index af2996d0d17f..bbe409ce5d97 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -1313,8 +1313,8 @@ static int pci_pm_runtime_suspend(struct device *dev)
pm->runtime_suspend, error);
return error;
} else if (error) {
- pci_err(pci_dev, "can't suspend (%ps returned %d)\n",
- pm->runtime_suspend, error);
+ pci_err(pci_dev, "can't suspend: %ps returned %pe)\n",
+ pm->runtime_suspend, ERR_PTR(error));
return error;
}
}
diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c
index a668820696dc..789c44d33b1b 100644
--- a/drivers/pci/pcie/dpc.c
+++ b/drivers/pci/pcie/dpc.c
@@ -427,8 +427,8 @@ static int dpc_probe(struct pcie_device *dev)
dpc_handler, IRQF_SHARED,
"pcie-dpc", pdev);
if (status) {
- pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
- status);
+ pci_warn(pdev, "request IRQ%d failed: %pe\n", dev->irq,
+ ERR_PTR(status));
return status;
}
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 568410e64ce6..cd856a42801e 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -6019,7 +6019,7 @@ static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
ret = pci_reset_bus(pdev);
if (ret < 0)
- pci_err(pdev, "Failed to reset GPU: %d\n", ret);
+ pci_err(pdev, "Failed to reset GPU: %pe\n", ERR_PTR(ret));
}
iounmap(map);
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 909e6a7c3cc3..75fdfdbadeef 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -2221,7 +2221,7 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
enable_all:
retval = pci_reenable_device(bridge);
if (retval)
- pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
+ pci_err(bridge, "Error reenabling bridge: %pe\n", ERR_PTR(retval));
pci_set_master(bridge);
}
EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c
index 0f87cade10f7..638b5130215d 100644
--- a/drivers/pci/slot.c
+++ b/drivers/pci/slot.c
@@ -343,8 +343,8 @@ void pci_hp_create_module_link(struct pci_slot *pci_slot)
return;
ret = sysfs_create_link(&pci_slot->kobj, kobj, "module");
if (ret)
- dev_err(&pci_slot->bus->dev, "Error creating sysfs link (%d)\n",
- ret);
+ dev_err(&pci_slot->bus->dev, "Error creating sysfs link: %pe\n",
+ ERR_PTR(ret));
kobject_put(kobj);
}
EXPORT_SYMBOL_GPL(pci_hp_create_module_link);
diff --git a/drivers/pci/vgaarb.c b/drivers/pci/vgaarb.c
index 78748e8d2dba..4e3daf243cb5 100644
--- a/drivers/pci/vgaarb.c
+++ b/drivers/pci/vgaarb.c
@@ -1542,7 +1542,7 @@ static int __init vga_arb_device_init(void)
rc = misc_register(&vga_arb_device);
if (rc < 0)
- pr_err("error %d registering device\n", rc);
+ pr_err("error registering device: %pe\n", ERR_PTR(rc));
bus_register_notifier(&pci_bus_type, &pci_notifier);
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 4%]
* [PATCH v4 03/10] drm/rockchip:hdmi: migrate to use inno-hdmi bridge driver
@ 2024-05-21 10:58 5% ` keith
0 siblings, 0 replies; 200+ results
From: keith @ 2024-05-21 10:58 UTC (permalink / raw)
To: andrzej.hajda, neil.armstrong, rfoss, Laurent.pinchart, jonas,
jernej.skrabec, maarten.lankhorst, mripard, tzimmermann, airlied,
daniel, robh, krzk+dt, conor+dt, hjc, heiko, andy.yan, xingyu.wu,
p.zabel, jack.zhu, shengyang.chen
Cc: dri-devel, devicetree, linux-kernel, linux-arm-kernel, keith.zhao
Add the ROCKCHIP inno hdmi driver that uses the Inno DesignWare
HDMI TX bridge and remove the old separate one.
Signed-off-by: keith <keith.zhao@starfivetech.com>
---
drivers/gpu/drm/rockchip/Kconfig | 1 +
drivers/gpu/drm/rockchip/Makefile | 2 +-
drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c | 517 ++++++++
.../{inno_hdmi.h => inno_hdmi-rockchip.h} | 45 -
drivers/gpu/drm/rockchip/inno_hdmi.c | 1073 -----------------
5 files changed, 519 insertions(+), 1119 deletions(-)
create mode 100644 drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c
rename drivers/gpu/drm/rockchip/{inno_hdmi.h => inno_hdmi-rockchip.h} (85%)
delete mode 100644 drivers/gpu/drm/rockchip/inno_hdmi.c
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 1bf3e2829cd0..cc6cfd5a30d6 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -74,6 +74,7 @@ config ROCKCHIP_DW_MIPI_DSI
config ROCKCHIP_INNO_HDMI
bool "Rockchip specific extensions for Innosilicon HDMI"
+ select DRM_INNO_HDMI
help
This selects support for Rockchip SoC specific extensions
for the Innosilicon HDMI driver. If you want to enable
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index 3ff7b21c0414..4b2d0cba8db3 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -12,7 +12,7 @@ rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o
-rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
rockchipdrm-$(CONFIG_ROCKCHIP_RGB) += rockchip_rgb.o
rockchipdrm-$(CONFIG_ROCKCHIP_RK3066_HDMI) += rk3066_hdmi.o
diff --git a/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c
new file mode 100644
index 000000000000..69d0e913e13b
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c
@@ -0,0 +1,517 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Zheng Yang <zhengyang@rock-chips.com>
+ * Yakir Yang <ykk@rock-chips.com>
+ */
+
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/hdmi.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+
+#include <drm/bridge/inno_hdmi.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include "rockchip_drm_drv.h"
+
+#include "inno_hdmi-rockchip.h"
+
+#define INNO_HDMI_MIN_TMDS_CLOCK 25000000U
+
+struct rk_inno_hdmi {
+ struct rockchip_encoder encoder;
+ struct inno_hdmi inno_hdmi;
+ struct clk *pclk;
+ struct clk *refclk;
+};
+
+static struct inno_hdmi *rk_encoder_to_inno_hdmi(struct drm_encoder *encoder)
+{
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
+ struct rk_inno_hdmi *rk_hdmi = container_of(rkencoder, struct rk_inno_hdmi, encoder);
+
+ return &rk_hdmi->inno_hdmi;
+}
+
+enum {
+ CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
+ CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
+ CSC_RGB_0_255_TO_RGB_16_235_8BIT,
+};
+
+static const char coeff_csc[][24] = {
+ /*
+ * RGB2YUV:601 SD mode:
+ * Cb = -0.291G - 0.148R + 0.439B + 128
+ * Y = 0.504G + 0.257R + 0.098B + 16
+ * Cr = -0.368G + 0.439R - 0.071B + 128
+ */
+ {
+ 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80,
+ 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e,
+ 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80
+ },
+ /*
+ * RGB2YUV:709 HD mode:
+ * Cb = - 0.338G - 0.101R + 0.439B + 128
+ * Y = 0.614G + 0.183R + 0.062B + 16
+ * Cr = - 0.399G + 0.439R - 0.040B + 128
+ */
+ {
+ 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
+ 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
+ 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
+ },
+ /*
+ * RGB[0:255]2RGB[16:235]:
+ * R' = R x (235-16)/255 + 16;
+ * G' = G x (235-16)/255 + 16;
+ * B' = B x (235-16)/255 + 16;
+ */
+ {
+ 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10,
+ 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10
+ },
+};
+
+static struct inno_hdmi_phy_config rk3036_hdmi_phy_configs[] = {
+ { 74250000, 0x3f, 0xbb },
+ { 165000000, 0x6f, 0xbb },
+ { ~0UL, 0x00, 0x00 }
+};
+
+static struct inno_hdmi_phy_config rk3128_hdmi_phy_configs[] = {
+ { 74250000, 0x3f, 0xaa },
+ { 165000000, 0x5f, 0xaa },
+ { ~0UL, 0x00, 0x00 }
+};
+
+static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi,
+ unsigned long pixelclk)
+{
+ const struct inno_hdmi_phy_config *phy_configs = hdmi->plat_data->phy_configs;
+ int i;
+
+ for (i = 0; phy_configs[i].pixelclock != ~0UL; i++) {
+ if (pixelclk <= phy_configs[i].pixelclock)
+ return i;
+ }
+
+ DRM_DEV_DEBUG(hdmi->dev, "No phy configuration for pixelclock %lu\n",
+ pixelclk);
+
+ return -EINVAL;
+}
+
+static void inno_hdmi_standby(struct inno_hdmi *hdmi)
+{
+ inno_hdmi_sys_power(hdmi, false);
+
+ hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00);
+ hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00);
+ hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00);
+ hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
+};
+
+static void inno_hdmi_power_up(struct inno_hdmi *hdmi,
+ unsigned long mpixelclock)
+{
+ struct inno_hdmi_phy_config *phy_config;
+ int ret = inno_hdmi_find_phy_config(hdmi, mpixelclock);
+
+ if (ret < 0) {
+ phy_config = hdmi->plat_data->default_phy_config;
+ DRM_DEV_ERROR(hdmi->dev,
+ "Using default phy configuration for TMDS rate %lu",
+ mpixelclock);
+ } else {
+ phy_config = &hdmi->plat_data->phy_configs[ret];
+ }
+
+ inno_hdmi_sys_power(hdmi, false);
+
+ hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis);
+ hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control);
+ hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
+ hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14);
+ hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10);
+ hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f);
+ hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00);
+ hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01);
+
+ inno_hdmi_sys_power(hdmi, true);
+};
+
+static void inno_hdmi_reset(struct inno_hdmi *hdmi)
+{
+ u32 val;
+ u32 msk;
+
+ hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL);
+ udelay(100);
+
+ hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG);
+ udelay(100);
+
+ msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL;
+ val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH;
+ hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val);
+
+ inno_hdmi_standby(hdmi);
+}
+
+static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi)
+{
+ struct drm_connector *connector = &hdmi->connector;
+ struct drm_connector_state *conn_state = connector->state;
+ struct inno_hdmi_connector_state *inno_conn_state =
+ to_inno_hdmi_conn_state(conn_state);
+ int c0_c2_change = 0;
+ int csc_enable = 0;
+ int csc_mode = 0;
+ int auto_csc = 0;
+ int value;
+ int i;
+
+ /* Input video mode is SDR RGB24bit, data enable signal from external */
+ hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL |
+ v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444));
+
+ /* Input color hardcode to RGB, and output color hardcode to RGB888 */
+ value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
+ v_VIDEO_OUTPUT_COLOR(0) |
+ v_VIDEO_INPUT_CSP(0);
+ hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value);
+
+ if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_RGB) {
+ if (inno_conn_state->rgb_limited_range) {
+ csc_mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
+ auto_csc = AUTO_CSC_DISABLE;
+ c0_c2_change = C0_C2_CHANGE_DISABLE;
+ csc_enable = v_CSC_ENABLE;
+
+ } else {
+ value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1);
+ hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
+
+ hdmi_modb(hdmi, HDMI_VIDEO_CONTRL,
+ m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP,
+ v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) |
+ v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE));
+ return 0;
+ }
+ } else {
+ if (inno_conn_state->colorimetry == HDMI_COLORIMETRY_ITU_601) {
+ if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444) {
+ csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
+ auto_csc = AUTO_CSC_DISABLE;
+ c0_c2_change = C0_C2_CHANGE_DISABLE;
+ csc_enable = v_CSC_ENABLE;
+ }
+ } else {
+ if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444) {
+ csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
+ auto_csc = AUTO_CSC_DISABLE;
+ c0_c2_change = C0_C2_CHANGE_DISABLE;
+ csc_enable = v_CSC_ENABLE;
+ }
+ }
+ }
+
+ for (i = 0; i < 24; i++)
+ hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i,
+ coeff_csc[csc_mode][i]);
+
+ value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1);
+ hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
+ hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC |
+ m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) |
+ v_VIDEO_C0_C2_SWAP(c0_c2_change));
+
+ return 0;
+}
+
+static int inno_hdmi_setup(struct inno_hdmi *hdmi,
+ struct drm_display_mode *mode)
+{
+ struct drm_display_info *display = &hdmi->connector.display_info;
+ unsigned long mpixelclock = mode->clock * 1000;
+
+ /* Mute video and audio output */
+ hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
+ v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
+
+ /* Set HDMI Mode */
+ hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
+ v_HDMI_DVI(display->is_hdmi));
+
+ inno_hdmi_config_video_timing(hdmi, mode);
+
+ inno_hdmi_config_video_csc(hdmi);
+
+ if (display->is_hdmi)
+ inno_hdmi_config_video_avi(hdmi, mode);
+
+ /*
+ * When IP controller have configured to an accurate video
+ * timing, then the TMDS clock source would be switched to
+ * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
+ * clock rate, and reconfigure the DDC clock.
+ */
+ inno_hdmi_i2c_init(hdmi, mpixelclock);
+
+ /* Unmute video and audio output */
+ hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
+ v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0));
+
+ inno_hdmi_power_up(hdmi, mpixelclock);
+
+ return 0;
+}
+
+static enum drm_mode_status rk_inno_hdmi_connector_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
+ struct rk_inno_hdmi *rk_hdmi = dev_get_drvdata(hdmi->dev);
+
+ unsigned long mpixelclk, max_tolerance;
+ long rounded_refclk;
+
+ /* No support for double-clock modes */
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ return MODE_BAD;
+
+ mpixelclk = mode->clock * 1000;
+
+ if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK)
+ return MODE_CLOCK_LOW;
+
+ if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0)
+ return MODE_CLOCK_HIGH;
+
+ if (rk_hdmi->refclk) {
+ rounded_refclk = clk_round_rate(rk_hdmi->refclk, mpixelclk);
+ if (rounded_refclk < 0)
+ return MODE_BAD;
+
+ /* Vesa DMT standard mentions +/- 0.5% max tolerance */
+ max_tolerance = mpixelclk / 200;
+ if (abs_diff((unsigned long)rounded_refclk, mpixelclk) > max_tolerance)
+ return MODE_NOCLOCK;
+ }
+
+ return MODE_OK;
+}
+
+static void rk_inno_hdmi_encoder_enable(struct drm_encoder *encoder,
+ struct drm_atomic_state *state)
+{
+ struct inno_hdmi *hdmi = rk_encoder_to_inno_hdmi(encoder);
+ struct drm_connector_state *conn_state;
+ struct drm_crtc_state *crtc_state;
+
+ conn_state = drm_atomic_get_new_connector_state(state, &hdmi->connector);
+ if (WARN_ON(!conn_state))
+ return;
+
+ crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
+ if (WARN_ON(!crtc_state))
+ return;
+
+ inno_hdmi_setup(hdmi, &crtc_state->adjusted_mode);
+}
+
+static void rk_inno_hdmi_encoder_disable(struct drm_encoder *encoder,
+ struct drm_atomic_state *state)
+{
+ struct inno_hdmi *hdmi = rk_encoder_to_inno_hdmi(encoder);
+
+ inno_hdmi_standby(hdmi);
+}
+
+static int
+rk_inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+ struct drm_display_mode *mode = &crtc_state->adjusted_mode;
+ u8 vic = drm_match_cea_mode(mode);
+ struct inno_hdmi_connector_state *inno_conn_state =
+ to_inno_hdmi_conn_state(conn_state);
+
+ s->output_mode = ROCKCHIP_OUT_MODE_P888;
+ s->output_type = DRM_MODE_CONNECTOR_HDMIA;
+
+ if (vic == 6 || vic == 7 ||
+ vic == 21 || vic == 22 ||
+ vic == 2 || vic == 3 ||
+ vic == 17 || vic == 18)
+ inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_601;
+ else
+ inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
+
+ inno_conn_state->enc_out_format = HDMI_COLORSPACE_RGB;
+ inno_conn_state->rgb_limited_range =
+ drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED;
+
+ return rk_inno_hdmi_connector_mode_valid(conn_state->connector,
+ &crtc_state->adjusted_mode) == MODE_OK ? 0 : -EINVAL;
+}
+
+static const struct drm_encoder_helper_funcs rk_inno_encoder_helper_funcs = {
+ .atomic_check = rk_inno_hdmi_encoder_atomic_check,
+ .atomic_enable = rk_inno_hdmi_encoder_enable,
+ .atomic_disable = rk_inno_hdmi_encoder_disable,
+};
+
+static int rk_inno_hdmi_bind(struct device *dev, struct device *master, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct drm_device *drm = data;
+ struct inno_hdmi *hdmi;
+ int ret;
+ struct rk_inno_hdmi *rk_hdmi;
+
+ rk_hdmi = devm_kzalloc(dev, sizeof(*rk_hdmi), GFP_KERNEL);
+ if (!rk_hdmi)
+ return -ENOMEM;
+ hdmi = &rk_hdmi->inno_hdmi;
+
+ hdmi->dev = dev;
+ hdmi->plat_data = (struct inno_hdmi_plat_data *)of_device_get_match_data(dev);
+
+ hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(hdmi->regs))
+ return PTR_ERR(hdmi->regs);
+
+ rk_hdmi->pclk = devm_clk_get(hdmi->dev, "pclk");
+ if (IS_ERR(rk_hdmi->pclk)) {
+ DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n");
+ return PTR_ERR(rk_hdmi->pclk);
+ }
+
+ ret = clk_prepare_enable(rk_hdmi->pclk);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev,
+ "Cannot enable HDMI pclk clock: %d\n", ret);
+ return ret;
+ }
+
+ rk_hdmi->refclk = devm_clk_get_optional(hdmi->dev, "ref");
+ if (IS_ERR(rk_hdmi->refclk)) {
+ DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI reference clock\n");
+ ret = PTR_ERR(rk_hdmi->refclk);
+ goto err_disable_pclk;
+ }
+
+ ret = clk_prepare_enable(rk_hdmi->refclk);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev,
+ "Cannot enable HDMI reference clock: %d\n", ret);
+ goto err_disable_pclk;
+ }
+
+ inno_hdmi_reset(hdmi);
+ /*
+ * When the controller isn't configured to an accurate
+ * video timing and there is no reference clock available,
+ * then the TMDS clock source would be switched to PCLK_HDMI,
+ * so we need to init the TMDS rate to PCLK rate, and
+ * reconfigure the DDC clock.
+ */
+ if (rk_hdmi->refclk)
+ inno_hdmi_i2c_init(hdmi, clk_get_rate(rk_hdmi->refclk));
+ else
+ inno_hdmi_i2c_init(hdmi, clk_get_rate(rk_hdmi->pclk));
+
+ ret = inno_hdmi_bind(drm, hdmi, &rk_hdmi->encoder.encoder);
+ if (ret)
+ goto err_cleanup_hdmi;
+
+ dev_set_drvdata(dev, rk_hdmi);
+
+ return 0;
+
+err_cleanup_hdmi:
+ rk_hdmi->encoder.encoder.funcs->destroy(&rk_hdmi->encoder.encoder);
+ clk_disable_unprepare(rk_hdmi->refclk);
+err_disable_pclk:
+ clk_disable_unprepare(rk_hdmi->pclk);
+ return ret;
+}
+
+static void rk_inno_hdmi_unbind(struct device *dev, struct device *master, void *data)
+{
+ struct rk_inno_hdmi *rk_hdmi = dev_get_drvdata(dev);
+ struct inno_hdmi *hdmi = &rk_hdmi->inno_hdmi;
+
+ rk_hdmi->encoder.encoder.funcs->destroy(&rk_hdmi->encoder.encoder);
+ i2c_put_adapter(hdmi->ddc);
+ clk_disable_unprepare(rk_hdmi->refclk);
+ clk_disable_unprepare(rk_hdmi->pclk);
+}
+
+static const struct component_ops inno_hdmi_ops = {
+ .bind = rk_inno_hdmi_bind,
+ .unbind = rk_inno_hdmi_unbind,
+};
+
+static int inno_hdmi_probe(struct platform_device *pdev)
+{
+ return component_add(&pdev->dev, &inno_hdmi_ops);
+}
+
+static void inno_hdmi_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &inno_hdmi_ops);
+}
+
+static const struct inno_hdmi_plat_data rk3036_inno_info = {
+ .soc_type = RK3036_HDMI,
+ .mode_valid = rk_inno_hdmi_connector_mode_valid,
+ .helper_private = &rk_inno_encoder_helper_funcs,
+ .phy_configs = rk3036_hdmi_phy_configs,
+ .default_phy_config = &rk3036_hdmi_phy_configs[1],
+};
+
+static const struct inno_hdmi_plat_data rk3128_inno_info = {
+ .soc_type = RK3128_HDMI,
+ .mode_valid = rk_inno_hdmi_connector_mode_valid,
+ .helper_private = &rk_inno_encoder_helper_funcs,
+ .phy_configs = rk3128_hdmi_phy_configs,
+ .default_phy_config = &rk3128_hdmi_phy_configs[1],
+};
+
+static const struct of_device_id inno_hdmi_dt_ids[] = {
+ { .compatible = "rockchip,rk3036-inno-hdmi",
+ .data = &rk3036_inno_info,
+ },
+ { .compatible = "rockchip,rk3128-inno-hdmi",
+ .data = &rk3128_inno_info,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids);
+
+struct platform_driver inno_hdmi_driver = {
+ .probe = inno_hdmi_probe,
+ .remove_new = inno_hdmi_remove,
+ .driver = {
+ .name = "innohdmi-rockchip",
+ .of_match_table = inno_hdmi_dt_ids,
+ },
+};
diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.h b/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.h
similarity index 85%
rename from drivers/gpu/drm/rockchip/inno_hdmi.h
rename to drivers/gpu/drm/rockchip/inno_hdmi-rockchip.h
index a7edf3559e60..c90458d75378 100644
--- a/drivers/gpu/drm/rockchip/inno_hdmi.h
+++ b/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.h
@@ -8,12 +8,6 @@
#ifndef __INNO_HDMI_H__
#define __INNO_HDMI_H__
-#define DDC_SEGMENT_ADDR 0x30
-
-#define HDMI_SCL_RATE (100*1000)
-#define DDC_BUS_FREQ_L 0x4b
-#define DDC_BUS_FREQ_H 0x4c
-
#define HDMI_SYS_CTRL 0x00
#define m_RST_ANALOG (1 << 6)
#define v_RST_ANALOG (0 << 6)
@@ -98,26 +92,6 @@ enum {
#define v_AUDIO_MUTE(n) (n << 1)
#define v_VIDEO_MUTE(n) (n << 0)
-#define HDMI_VIDEO_TIMING_CTL 0x08
-#define v_HSYNC_POLARITY(n) (n << 3)
-#define v_VSYNC_POLARITY(n) (n << 2)
-#define v_INETLACE(n) (n << 1)
-#define v_EXTERANL_VIDEO(n) (n << 0)
-
-#define HDMI_VIDEO_EXT_HTOTAL_L 0x09
-#define HDMI_VIDEO_EXT_HTOTAL_H 0x0a
-#define HDMI_VIDEO_EXT_HBLANK_L 0x0b
-#define HDMI_VIDEO_EXT_HBLANK_H 0x0c
-#define HDMI_VIDEO_EXT_HDELAY_L 0x0d
-#define HDMI_VIDEO_EXT_HDELAY_H 0x0e
-#define HDMI_VIDEO_EXT_HDURATION_L 0x0f
-#define HDMI_VIDEO_EXT_HDURATION_H 0x10
-#define HDMI_VIDEO_EXT_VTOTAL_L 0x11
-#define HDMI_VIDEO_EXT_VTOTAL_H 0x12
-#define HDMI_VIDEO_EXT_VBLANK 0x13
-#define HDMI_VIDEO_EXT_VDELAY 0x14
-#define HDMI_VIDEO_EXT_VDURATION 0x15
-
#define HDMI_VIDEO_CSC_COEF 0x18
#define HDMI_AUDIO_CTRL1 0x35
@@ -202,14 +176,6 @@ enum {
#define HDMI_AUDIO_CTS_M 0x46
#define HDMI_AUDIO_CTS_L 0x47
-#define HDMI_DDC_CLK_L 0x4b
-#define HDMI_DDC_CLK_H 0x4c
-
-#define HDMI_EDID_SEGMENT_POINTER 0x4d
-#define HDMI_EDID_WORD_ADDR 0x4e
-#define HDMI_EDID_FIFO_OFFSET 0x4f
-#define HDMI_EDID_FIFO_ADDR 0x50
-
#define HDMI_PACKET_SEND_MANUAL 0x9c
#define HDMI_PACKET_SEND_AUTO 0x9d
#define m_PACKET_GCP_EN (1 << 7)
@@ -254,23 +220,12 @@ enum {
#define m_HDMI_DVI (1 << 1)
#define v_HDMI_DVI(n) (n << 1)
-#define HDMI_INTERRUPT_MASK1 0xc0
-#define HDMI_INTERRUPT_STATUS1 0xc1
-#define m_INT_ACTIVE_VSYNC (1 << 5)
-#define m_INT_EDID_READY (1 << 2)
-
#define HDMI_INTERRUPT_MASK2 0xc2
#define HDMI_INTERRUPT_STATUS2 0xc3
#define m_INT_HDCP_ERR (1 << 7)
#define m_INT_BKSV_FLAG (1 << 6)
#define m_INT_HDCP_OK (1 << 4)
-#define HDMI_STATUS 0xc8
-#define m_HOTPLUG (1 << 7)
-#define m_MASK_INT_HOTPLUG (1 << 5)
-#define m_INT_HOTPLUG (1 << 1)
-#define v_MASK_INT_HOTPLUG(n) ((n & 0x1) << 5)
-
#define HDMI_COLORBAR 0xc9
#define HDMI_PHY_SYNC 0xce
diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c
deleted file mode 100644
index 3df2cfcf9998..000000000000
--- a/drivers/gpu/drm/rockchip/inno_hdmi.c
+++ /dev/null
@@ -1,1073 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
- * Zheng Yang <zhengyang@rock-chips.com>
- * Yakir Yang <ykk@rock-chips.com>
- */
-
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/hdmi.h>
-#include <linux/mod_devicetable.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-
-#include <drm/drm_atomic.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_edid.h>
-#include <drm/drm_of.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_simple_kms_helper.h>
-
-#include "rockchip_drm_drv.h"
-
-#include "inno_hdmi.h"
-
-#define INNO_HDMI_MIN_TMDS_CLOCK 25000000U
-
-struct inno_hdmi_phy_config {
- unsigned long pixelclock;
- u8 pre_emphasis;
- u8 voltage_level_control;
-};
-
-struct inno_hdmi_variant {
- struct inno_hdmi_phy_config *phy_configs;
- struct inno_hdmi_phy_config *default_phy_config;
-};
-
-struct inno_hdmi_i2c {
- struct i2c_adapter adap;
-
- u8 ddc_addr;
- u8 segment_addr;
-
- struct mutex lock;
- struct completion cmp;
-};
-
-struct inno_hdmi {
- struct device *dev;
-
- struct clk *pclk;
- struct clk *refclk;
- void __iomem *regs;
-
- struct drm_connector connector;
- struct rockchip_encoder encoder;
-
- struct inno_hdmi_i2c *i2c;
- struct i2c_adapter *ddc;
-
- const struct inno_hdmi_variant *variant;
-};
-
-struct inno_hdmi_connector_state {
- struct drm_connector_state base;
- unsigned int enc_out_format;
- unsigned int colorimetry;
- bool rgb_limited_range;
-};
-
-static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder)
-{
- struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
-
- return container_of(rkencoder, struct inno_hdmi, encoder);
-}
-
-static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector)
-{
- return container_of(connector, struct inno_hdmi, connector);
-}
-
-#define to_inno_hdmi_conn_state(conn_state) \
- container_of_const(conn_state, struct inno_hdmi_connector_state, base)
-
-enum {
- CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
- CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
- CSC_RGB_0_255_TO_RGB_16_235_8BIT,
-};
-
-static const char coeff_csc[][24] = {
- /*
- * RGB2YUV:601 SD mode:
- * Cb = -0.291G - 0.148R + 0.439B + 128
- * Y = 0.504G + 0.257R + 0.098B + 16
- * Cr = -0.368G + 0.439R - 0.071B + 128
- */
- {
- 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80,
- 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e,
- 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80
- },
- /*
- * RGB2YUV:709 HD mode:
- * Cb = - 0.338G - 0.101R + 0.439B + 128
- * Y = 0.614G + 0.183R + 0.062B + 16
- * Cr = - 0.399G + 0.439R - 0.040B + 128
- */
- {
- 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
- 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
- 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
- },
- /*
- * RGB[0:255]2RGB[16:235]:
- * R' = R x (235-16)/255 + 16;
- * G' = G x (235-16)/255 + 16;
- * B' = B x (235-16)/255 + 16;
- */
- {
- 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10,
- 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
- 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10
- },
-};
-
-static struct inno_hdmi_phy_config rk3036_hdmi_phy_configs[] = {
- { 74250000, 0x3f, 0xbb },
- { 165000000, 0x6f, 0xbb },
- { ~0UL, 0x00, 0x00 }
-};
-
-static struct inno_hdmi_phy_config rk3128_hdmi_phy_configs[] = {
- { 74250000, 0x3f, 0xaa },
- { 165000000, 0x5f, 0xaa },
- { ~0UL, 0x00, 0x00 }
-};
-
-static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi,
- unsigned long pixelclk)
-{
- const struct inno_hdmi_phy_config *phy_configs =
- hdmi->variant->phy_configs;
- int i;
-
- for (i = 0; phy_configs[i].pixelclock != ~0UL; i++) {
- if (pixelclk <= phy_configs[i].pixelclock)
- return i;
- }
-
- DRM_DEV_DEBUG(hdmi->dev, "No phy configuration for pixelclock %lu\n",
- pixelclk);
-
- return -EINVAL;
-}
-
-static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset)
-{
- return readl_relaxed(hdmi->regs + (offset) * 0x04);
-}
-
-static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val)
-{
- writel_relaxed(val, hdmi->regs + (offset) * 0x04);
-}
-
-static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset,
- u32 msk, u32 val)
-{
- u8 temp = hdmi_readb(hdmi, offset) & ~msk;
-
- temp |= val & msk;
- hdmi_writeb(hdmi, offset, temp);
-}
-
-static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi, unsigned long long rate)
-{
- unsigned long long ddc_bus_freq = rate >> 2;
-
- do_div(ddc_bus_freq, HDMI_SCL_RATE);
-
- hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
- hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
-
- /* Clear the EDID interrupt flag and mute the interrupt */
- hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
- hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
-}
-
-static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable)
-{
- if (enable)
- hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON);
- else
- hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF);
-}
-
-static void inno_hdmi_standby(struct inno_hdmi *hdmi)
-{
- inno_hdmi_sys_power(hdmi, false);
-
- hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00);
- hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00);
- hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00);
- hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
-};
-
-static void inno_hdmi_power_up(struct inno_hdmi *hdmi,
- unsigned long mpixelclock)
-{
- struct inno_hdmi_phy_config *phy_config;
- int ret = inno_hdmi_find_phy_config(hdmi, mpixelclock);
-
- if (ret < 0) {
- phy_config = hdmi->variant->default_phy_config;
- DRM_DEV_ERROR(hdmi->dev,
- "Using default phy configuration for TMDS rate %lu",
- mpixelclock);
- } else {
- phy_config = &hdmi->variant->phy_configs[ret];
- }
-
- inno_hdmi_sys_power(hdmi, false);
-
- hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis);
- hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control);
- hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
- hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14);
- hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10);
- hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f);
- hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00);
- hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01);
-
- inno_hdmi_sys_power(hdmi, true);
-};
-
-static void inno_hdmi_reset(struct inno_hdmi *hdmi)
-{
- u32 val;
- u32 msk;
-
- hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL);
- udelay(100);
-
- hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG);
- udelay(100);
-
- msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL;
- val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH;
- hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val);
-
- inno_hdmi_standby(hdmi);
-}
-
-static void inno_hdmi_disable_frame(struct inno_hdmi *hdmi,
- enum hdmi_infoframe_type type)
-{
- struct drm_connector *connector = &hdmi->connector;
-
- if (type != HDMI_INFOFRAME_TYPE_AVI) {
- drm_err(connector->dev,
- "Unsupported infoframe type: %u\n", type);
- return;
- }
-
- hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, INFOFRAME_AVI);
-}
-
-static int inno_hdmi_upload_frame(struct inno_hdmi *hdmi,
- union hdmi_infoframe *frame, enum hdmi_infoframe_type type)
-{
- struct drm_connector *connector = &hdmi->connector;
- u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
- ssize_t rc, i;
-
- if (type != HDMI_INFOFRAME_TYPE_AVI) {
- drm_err(connector->dev,
- "Unsupported infoframe type: %u\n", type);
- return 0;
- }
-
- inno_hdmi_disable_frame(hdmi, type);
-
- rc = hdmi_infoframe_pack(frame, packed_frame,
- sizeof(packed_frame));
- if (rc < 0)
- return rc;
-
- for (i = 0; i < rc; i++)
- hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i,
- packed_frame[i]);
-
- return 0;
-}
-
-static int inno_hdmi_config_video_avi(struct inno_hdmi *hdmi,
- struct drm_display_mode *mode)
-{
- struct drm_connector *connector = &hdmi->connector;
- struct drm_connector_state *conn_state = connector->state;
- struct inno_hdmi_connector_state *inno_conn_state =
- to_inno_hdmi_conn_state(conn_state);
- union hdmi_infoframe frame;
- int rc;
-
- rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
- &hdmi->connector,
- mode);
- if (rc) {
- inno_hdmi_disable_frame(hdmi, HDMI_INFOFRAME_TYPE_AVI);
- return rc;
- }
-
- if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444)
- frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
- else if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV422)
- frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
- else
- frame.avi.colorspace = HDMI_COLORSPACE_RGB;
-
- if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_RGB) {
- drm_hdmi_avi_infoframe_quant_range(&frame.avi,
- connector, mode,
- inno_conn_state->rgb_limited_range ?
- HDMI_QUANTIZATION_RANGE_LIMITED :
- HDMI_QUANTIZATION_RANGE_FULL);
- } else {
- frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
- frame.avi.ycc_quantization_range =
- HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
- }
-
- return inno_hdmi_upload_frame(hdmi, &frame, HDMI_INFOFRAME_TYPE_AVI);
-}
-
-static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi)
-{
- struct drm_connector *connector = &hdmi->connector;
- struct drm_connector_state *conn_state = connector->state;
- struct inno_hdmi_connector_state *inno_conn_state =
- to_inno_hdmi_conn_state(conn_state);
- int c0_c2_change = 0;
- int csc_enable = 0;
- int csc_mode = 0;
- int auto_csc = 0;
- int value;
- int i;
-
- /* Input video mode is SDR RGB24bit, data enable signal from external */
- hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL |
- v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444));
-
- /* Input color hardcode to RGB, and output color hardcode to RGB888 */
- value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
- v_VIDEO_OUTPUT_COLOR(0) |
- v_VIDEO_INPUT_CSP(0);
- hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value);
-
- if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_RGB) {
- if (inno_conn_state->rgb_limited_range) {
- csc_mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
- auto_csc = AUTO_CSC_DISABLE;
- c0_c2_change = C0_C2_CHANGE_DISABLE;
- csc_enable = v_CSC_ENABLE;
-
- } else {
- value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1);
- hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
-
- hdmi_modb(hdmi, HDMI_VIDEO_CONTRL,
- m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP,
- v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) |
- v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE));
- return 0;
- }
- } else {
- if (inno_conn_state->colorimetry == HDMI_COLORIMETRY_ITU_601) {
- if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444) {
- csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
- auto_csc = AUTO_CSC_DISABLE;
- c0_c2_change = C0_C2_CHANGE_DISABLE;
- csc_enable = v_CSC_ENABLE;
- }
- } else {
- if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444) {
- csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
- auto_csc = AUTO_CSC_DISABLE;
- c0_c2_change = C0_C2_CHANGE_DISABLE;
- csc_enable = v_CSC_ENABLE;
- }
- }
- }
-
- for (i = 0; i < 24; i++)
- hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i,
- coeff_csc[csc_mode][i]);
-
- value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1);
- hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
- hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC |
- m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) |
- v_VIDEO_C0_C2_SWAP(c0_c2_change));
-
- return 0;
-}
-
-static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi,
- struct drm_display_mode *mode)
-{
- int value;
-
- /* Set detail external video timing polarity and interlace mode */
- value = v_EXTERANL_VIDEO(1);
- value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
- v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0);
- value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
- v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0);
- value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
- v_INETLACE(1) : v_INETLACE(0);
- hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value);
-
- /* Set detail external video timing */
- value = mode->htotal;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF);
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF);
-
- value = mode->htotal - mode->hdisplay;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF);
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF);
-
- value = mode->htotal - mode->hsync_start;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF);
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF);
-
- value = mode->hsync_end - mode->hsync_start;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF);
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF);
-
- value = mode->vtotal;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF);
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF);
-
- value = mode->vtotal - mode->vdisplay;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF);
-
- value = mode->vtotal - mode->vsync_start;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF);
-
- value = mode->vsync_end - mode->vsync_start;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF);
-
- hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e);
- hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c);
- hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01);
-
- return 0;
-}
-
-static int inno_hdmi_setup(struct inno_hdmi *hdmi,
- struct drm_display_mode *mode)
-{
- struct drm_display_info *display = &hdmi->connector.display_info;
- unsigned long mpixelclock = mode->clock * 1000;
-
- /* Mute video and audio output */
- hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
- v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
-
- /* Set HDMI Mode */
- hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
- v_HDMI_DVI(display->is_hdmi));
-
- inno_hdmi_config_video_timing(hdmi, mode);
-
- inno_hdmi_config_video_csc(hdmi);
-
- if (display->is_hdmi)
- inno_hdmi_config_video_avi(hdmi, mode);
-
- /*
- * When IP controller have configured to an accurate video
- * timing, then the TMDS clock source would be switched to
- * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
- * clock rate, and reconfigure the DDC clock.
- */
- inno_hdmi_i2c_init(hdmi, mpixelclock);
-
- /* Unmute video and audio output */
- hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
- v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0));
-
- inno_hdmi_power_up(hdmi, mpixelclock);
-
- return 0;
-}
-
-static enum drm_mode_status inno_hdmi_display_mode_valid(struct inno_hdmi *hdmi,
- struct drm_display_mode *mode)
-{
- unsigned long mpixelclk, max_tolerance;
- long rounded_refclk;
-
- /* No support for double-clock modes */
- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
- return MODE_BAD;
-
- mpixelclk = mode->clock * 1000;
-
- if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK)
- return MODE_CLOCK_LOW;
-
- if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0)
- return MODE_CLOCK_HIGH;
-
- if (hdmi->refclk) {
- rounded_refclk = clk_round_rate(hdmi->refclk, mpixelclk);
- if (rounded_refclk < 0)
- return MODE_BAD;
-
- /* Vesa DMT standard mentions +/- 0.5% max tolerance */
- max_tolerance = mpixelclk / 200;
- if (abs_diff((unsigned long)rounded_refclk, mpixelclk) > max_tolerance)
- return MODE_NOCLOCK;
- }
-
- return MODE_OK;
-}
-
-static void inno_hdmi_encoder_enable(struct drm_encoder *encoder,
- struct drm_atomic_state *state)
-{
- struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
- struct drm_connector_state *conn_state;
- struct drm_crtc_state *crtc_state;
-
- conn_state = drm_atomic_get_new_connector_state(state, &hdmi->connector);
- if (WARN_ON(!conn_state))
- return;
-
- crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
- if (WARN_ON(!crtc_state))
- return;
-
- inno_hdmi_setup(hdmi, &crtc_state->adjusted_mode);
-}
-
-static void inno_hdmi_encoder_disable(struct drm_encoder *encoder,
- struct drm_atomic_state *state)
-{
- struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
-
- inno_hdmi_standby(hdmi);
-}
-
-static int
-inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
- struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
- struct drm_display_mode *mode = &crtc_state->adjusted_mode;
- u8 vic = drm_match_cea_mode(mode);
- struct inno_hdmi_connector_state *inno_conn_state =
- to_inno_hdmi_conn_state(conn_state);
-
- s->output_mode = ROCKCHIP_OUT_MODE_P888;
- s->output_type = DRM_MODE_CONNECTOR_HDMIA;
-
- if (vic == 6 || vic == 7 ||
- vic == 21 || vic == 22 ||
- vic == 2 || vic == 3 ||
- vic == 17 || vic == 18)
- inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_601;
- else
- inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
-
- inno_conn_state->enc_out_format = HDMI_COLORSPACE_RGB;
- inno_conn_state->rgb_limited_range =
- drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED;
-
- return inno_hdmi_display_mode_valid(hdmi,
- &crtc_state->adjusted_mode) == MODE_OK ? 0 : -EINVAL;
-}
-
-static struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = {
- .atomic_check = inno_hdmi_encoder_atomic_check,
- .atomic_enable = inno_hdmi_encoder_enable,
- .atomic_disable = inno_hdmi_encoder_disable,
-};
-
-static enum drm_connector_status
-inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
-{
- struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
-
- return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ?
- connector_status_connected : connector_status_disconnected;
-}
-
-static int inno_hdmi_connector_get_modes(struct drm_connector *connector)
-{
- struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
- const struct drm_edid *drm_edid;
- int ret = 0;
-
- if (!hdmi->ddc)
- return 0;
-
- drm_edid = drm_edid_read_ddc(connector, hdmi->ddc);
- drm_edid_connector_update(connector, drm_edid);
- ret = drm_edid_connector_add_modes(connector);
- drm_edid_free(drm_edid);
-
- return ret;
-}
-
-static enum drm_mode_status
-inno_hdmi_connector_mode_valid(struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
-
- return inno_hdmi_display_mode_valid(hdmi, mode);
-}
-
-static void inno_hdmi_connector_destroy(struct drm_connector *connector)
-{
- drm_connector_unregister(connector);
- drm_connector_cleanup(connector);
-}
-
-static void
-inno_hdmi_connector_destroy_state(struct drm_connector *connector,
- struct drm_connector_state *state)
-{
- struct inno_hdmi_connector_state *inno_conn_state =
- to_inno_hdmi_conn_state(state);
-
- __drm_atomic_helper_connector_destroy_state(&inno_conn_state->base);
- kfree(inno_conn_state);
-}
-
-static void inno_hdmi_connector_reset(struct drm_connector *connector)
-{
- struct inno_hdmi_connector_state *inno_conn_state;
-
- if (connector->state) {
- inno_hdmi_connector_destroy_state(connector, connector->state);
- connector->state = NULL;
- }
-
- inno_conn_state = kzalloc(sizeof(*inno_conn_state), GFP_KERNEL);
- if (!inno_conn_state)
- return;
-
- __drm_atomic_helper_connector_reset(connector, &inno_conn_state->base);
-
- inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
- inno_conn_state->enc_out_format = HDMI_COLORSPACE_RGB;
- inno_conn_state->rgb_limited_range = false;
-}
-
-static struct drm_connector_state *
-inno_hdmi_connector_duplicate_state(struct drm_connector *connector)
-{
- struct inno_hdmi_connector_state *inno_conn_state;
-
- if (WARN_ON(!connector->state))
- return NULL;
-
- inno_conn_state = kmemdup(to_inno_hdmi_conn_state(connector->state),
- sizeof(*inno_conn_state), GFP_KERNEL);
-
- if (!inno_conn_state)
- return NULL;
-
- __drm_atomic_helper_connector_duplicate_state(connector,
- &inno_conn_state->base);
-
- return &inno_conn_state->base;
-}
-
-static const struct drm_connector_funcs inno_hdmi_connector_funcs = {
- .fill_modes = drm_helper_probe_single_connector_modes,
- .detect = inno_hdmi_connector_detect,
- .destroy = inno_hdmi_connector_destroy,
- .reset = inno_hdmi_connector_reset,
- .atomic_duplicate_state = inno_hdmi_connector_duplicate_state,
- .atomic_destroy_state = inno_hdmi_connector_destroy_state,
-};
-
-static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = {
- .get_modes = inno_hdmi_connector_get_modes,
- .mode_valid = inno_hdmi_connector_mode_valid,
-};
-
-static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi)
-{
- struct drm_encoder *encoder = &hdmi->encoder.encoder;
- struct device *dev = hdmi->dev;
-
- encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
-
- /*
- * If we failed to find the CRTC(s) which this encoder is
- * supposed to be connected to, it's because the CRTC has
- * not been registered yet. Defer probing, and hope that
- * the required CRTC is added later.
- */
- if (encoder->possible_crtcs == 0)
- return -EPROBE_DEFER;
-
- drm_encoder_helper_add(encoder, &inno_hdmi_encoder_helper_funcs);
- drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
-
- hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
-
- drm_connector_helper_add(&hdmi->connector,
- &inno_hdmi_connector_helper_funcs);
- drm_connector_init_with_ddc(drm, &hdmi->connector,
- &inno_hdmi_connector_funcs,
- DRM_MODE_CONNECTOR_HDMIA,
- hdmi->ddc);
-
- drm_connector_attach_encoder(&hdmi->connector, encoder);
-
- return 0;
-}
-
-static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi)
-{
- struct inno_hdmi_i2c *i2c = hdmi->i2c;
- u8 stat;
-
- stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1);
- if (!(stat & m_INT_EDID_READY))
- return IRQ_NONE;
-
- /* Clear HDMI EDID interrupt flag */
- hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
-
- complete(&i2c->cmp);
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id)
-{
- struct inno_hdmi *hdmi = dev_id;
- irqreturn_t ret = IRQ_NONE;
- u8 interrupt;
-
- if (hdmi->i2c)
- ret = inno_hdmi_i2c_irq(hdmi);
-
- interrupt = hdmi_readb(hdmi, HDMI_STATUS);
- if (interrupt & m_INT_HOTPLUG) {
- hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG);
- ret = IRQ_WAKE_THREAD;
- }
-
- return ret;
-}
-
-static irqreturn_t inno_hdmi_irq(int irq, void *dev_id)
-{
- struct inno_hdmi *hdmi = dev_id;
-
- drm_helper_hpd_irq_event(hdmi->connector.dev);
-
- return IRQ_HANDLED;
-}
-
-static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
-{
- int length = msgs->len;
- u8 *buf = msgs->buf;
- int ret;
-
- ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10);
- if (!ret)
- return -EAGAIN;
-
- while (length--)
- *buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR);
-
- return 0;
-}
-
-static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
-{
- /*
- * The DDC module only support read EDID message, so
- * we assume that each word write to this i2c adapter
- * should be the offset of EDID word address.
- */
- if ((msgs->len != 1) ||
- ((msgs->addr != DDC_ADDR) && (msgs->addr != DDC_SEGMENT_ADDR)))
- return -EINVAL;
-
- reinit_completion(&hdmi->i2c->cmp);
-
- if (msgs->addr == DDC_SEGMENT_ADDR)
- hdmi->i2c->segment_addr = msgs->buf[0];
- if (msgs->addr == DDC_ADDR)
- hdmi->i2c->ddc_addr = msgs->buf[0];
-
- /* Set edid fifo first addr */
- hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00);
-
- /* Set edid word address 0x00/0x80 */
- hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
-
- /* Set edid segment pointer */
- hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
-
- return 0;
-}
-
-static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap,
- struct i2c_msg *msgs, int num)
-{
- struct inno_hdmi *hdmi = i2c_get_adapdata(adap);
- struct inno_hdmi_i2c *i2c = hdmi->i2c;
- int i, ret = 0;
-
- mutex_lock(&i2c->lock);
-
- /* Clear the EDID interrupt flag and unmute the interrupt */
- hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY);
- hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
-
- for (i = 0; i < num; i++) {
- DRM_DEV_DEBUG(hdmi->dev,
- "xfer: num: %d/%d, len: %d, flags: %#x\n",
- i + 1, num, msgs[i].len, msgs[i].flags);
-
- if (msgs[i].flags & I2C_M_RD)
- ret = inno_hdmi_i2c_read(hdmi, &msgs[i]);
- else
- ret = inno_hdmi_i2c_write(hdmi, &msgs[i]);
-
- if (ret < 0)
- break;
- }
-
- if (!ret)
- ret = num;
-
- /* Mute HDMI EDID interrupt */
- hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
-
- mutex_unlock(&i2c->lock);
-
- return ret;
-}
-
-static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter)
-{
- return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-}
-
-static const struct i2c_algorithm inno_hdmi_algorithm = {
- .master_xfer = inno_hdmi_i2c_xfer,
- .functionality = inno_hdmi_i2c_func,
-};
-
-static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi)
-{
- struct i2c_adapter *adap;
- struct inno_hdmi_i2c *i2c;
- int ret;
-
- i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
- if (!i2c)
- return ERR_PTR(-ENOMEM);
-
- mutex_init(&i2c->lock);
- init_completion(&i2c->cmp);
-
- adap = &i2c->adap;
- adap->owner = THIS_MODULE;
- adap->dev.parent = hdmi->dev;
- adap->dev.of_node = hdmi->dev->of_node;
- adap->algo = &inno_hdmi_algorithm;
- strscpy(adap->name, "Inno HDMI", sizeof(adap->name));
- i2c_set_adapdata(adap, hdmi);
-
- ret = i2c_add_adapter(adap);
- if (ret) {
- dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
- devm_kfree(hdmi->dev, i2c);
- return ERR_PTR(ret);
- }
-
- hdmi->i2c = i2c;
-
- DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
-
- return adap;
-}
-
-static int inno_hdmi_bind(struct device *dev, struct device *master,
- void *data)
-{
- struct platform_device *pdev = to_platform_device(dev);
- struct drm_device *drm = data;
- struct inno_hdmi *hdmi;
- const struct inno_hdmi_variant *variant;
- int irq;
- int ret;
-
- hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
- if (!hdmi)
- return -ENOMEM;
-
- hdmi->dev = dev;
-
- variant = of_device_get_match_data(hdmi->dev);
- if (!variant)
- return -EINVAL;
-
- hdmi->variant = variant;
-
- hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(hdmi->regs))
- return PTR_ERR(hdmi->regs);
-
- hdmi->pclk = devm_clk_get(hdmi->dev, "pclk");
- if (IS_ERR(hdmi->pclk)) {
- DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n");
- return PTR_ERR(hdmi->pclk);
- }
-
- ret = clk_prepare_enable(hdmi->pclk);
- if (ret) {
- DRM_DEV_ERROR(hdmi->dev,
- "Cannot enable HDMI pclk clock: %d\n", ret);
- return ret;
- }
-
- hdmi->refclk = devm_clk_get_optional(hdmi->dev, "ref");
- if (IS_ERR(hdmi->refclk)) {
- DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI reference clock\n");
- ret = PTR_ERR(hdmi->refclk);
- goto err_disable_pclk;
- }
-
- ret = clk_prepare_enable(hdmi->refclk);
- if (ret) {
- DRM_DEV_ERROR(hdmi->dev,
- "Cannot enable HDMI reference clock: %d\n", ret);
- goto err_disable_pclk;
- }
-
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- ret = irq;
- goto err_disable_clk;
- }
-
- inno_hdmi_reset(hdmi);
-
- hdmi->ddc = inno_hdmi_i2c_adapter(hdmi);
- if (IS_ERR(hdmi->ddc)) {
- ret = PTR_ERR(hdmi->ddc);
- hdmi->ddc = NULL;
- goto err_disable_clk;
- }
-
- /*
- * When the controller isn't configured to an accurate
- * video timing and there is no reference clock available,
- * then the TMDS clock source would be switched to PCLK_HDMI,
- * so we need to init the TMDS rate to PCLK rate, and
- * reconfigure the DDC clock.
- */
- if (hdmi->refclk)
- inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->refclk));
- else
- inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->pclk));
-
- ret = inno_hdmi_register(drm, hdmi);
- if (ret)
- goto err_put_adapter;
-
- dev_set_drvdata(dev, hdmi);
-
- /* Unmute hotplug interrupt */
- hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1));
-
- ret = devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq,
- inno_hdmi_irq, IRQF_SHARED,
- dev_name(dev), hdmi);
- if (ret < 0)
- goto err_cleanup_hdmi;
-
- return 0;
-err_cleanup_hdmi:
- hdmi->connector.funcs->destroy(&hdmi->connector);
- hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
-err_put_adapter:
- i2c_put_adapter(hdmi->ddc);
-err_disable_clk:
- clk_disable_unprepare(hdmi->refclk);
-err_disable_pclk:
- clk_disable_unprepare(hdmi->pclk);
- return ret;
-}
-
-static void inno_hdmi_unbind(struct device *dev, struct device *master,
- void *data)
-{
- struct inno_hdmi *hdmi = dev_get_drvdata(dev);
-
- hdmi->connector.funcs->destroy(&hdmi->connector);
- hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
-
- i2c_put_adapter(hdmi->ddc);
- clk_disable_unprepare(hdmi->refclk);
- clk_disable_unprepare(hdmi->pclk);
-}
-
-static const struct component_ops inno_hdmi_ops = {
- .bind = inno_hdmi_bind,
- .unbind = inno_hdmi_unbind,
-};
-
-static int inno_hdmi_probe(struct platform_device *pdev)
-{
- return component_add(&pdev->dev, &inno_hdmi_ops);
-}
-
-static void inno_hdmi_remove(struct platform_device *pdev)
-{
- component_del(&pdev->dev, &inno_hdmi_ops);
-}
-
-static const struct inno_hdmi_variant rk3036_inno_hdmi_variant = {
- .phy_configs = rk3036_hdmi_phy_configs,
- .default_phy_config = &rk3036_hdmi_phy_configs[1],
-};
-
-static const struct inno_hdmi_variant rk3128_inno_hdmi_variant = {
- .phy_configs = rk3128_hdmi_phy_configs,
- .default_phy_config = &rk3128_hdmi_phy_configs[1],
-};
-
-static const struct of_device_id inno_hdmi_dt_ids[] = {
- { .compatible = "rockchip,rk3036-inno-hdmi",
- .data = &rk3036_inno_hdmi_variant,
- },
- { .compatible = "rockchip,rk3128-inno-hdmi",
- .data = &rk3128_inno_hdmi_variant,
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids);
-
-struct platform_driver inno_hdmi_driver = {
- .probe = inno_hdmi_probe,
- .remove_new = inno_hdmi_remove,
- .driver = {
- .name = "innohdmi-rockchip",
- .of_match_table = inno_hdmi_dt_ids,
- },
-};
--
2.27.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* [PATCH v9 3/3] pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driver
@ 2024-05-21 1:24 1% ` Jacky Huang
0 siblings, 0 replies; 200+ results
From: Jacky Huang @ 2024-05-21 1:24 UTC (permalink / raw)
To: linus.walleij, robh+dt, krzysztof.kozlowski+dt, conor+dt, p.zabel
Cc: linux-arm-kernel, linux-gpio, devicetree, linux-kernel, ychuang3, schung
From: Jacky Huang <ychuang3@nuvoton.com>
Add common pinctrl and GPIO driver for Nuvoton MA35 series SoC, and
add support for ma35d1 pinctrl.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
drivers/pinctrl/nuvoton/Kconfig | 19 +
drivers/pinctrl/nuvoton/Makefile | 2 +
drivers/pinctrl/nuvoton/pinctrl-ma35.c | 1187 ++++++++++++++
drivers/pinctrl/nuvoton/pinctrl-ma35.h | 52 +
drivers/pinctrl/nuvoton/pinctrl-ma35d1.c | 1799 ++++++++++++++++++++++
5 files changed, 3059 insertions(+)
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35.c
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35.h
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
index 2abbfcec1fae..7eadaaf48d6e 100644
--- a/drivers/pinctrl/nuvoton/Kconfig
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -45,3 +45,22 @@ config PINCTRL_NPCM8XX
Say Y or M here to enable pin controller and GPIO support for
the Nuvoton NPCM8XX SoC. This is strongly recommended when
building a kernel that will run on this chip.
+
+config PINCTRL_MA35
+ bool
+ depends on (ARCH_MA35 || COMPILE_TEST) && OF
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ select GPIOLIB
+ select GPIO_GENERIC
+ select GPIOLIB_IRQCHIP
+ select MFD_SYSCON
+
+config PINCTRL_MA35D1
+ bool "Pinctrl and GPIO driver for Nuvoton MA35D1"
+ depends on (ARCH_MA35 || COMPILE_TEST) && OF
+ select PINCTRL_MA35
+ help
+ Say Y here to enable pin controller and GPIO support
+ for Nuvoton MA35D1 SoC.
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
index 08031eab0af6..346c5082bc60 100644
--- a/drivers/pinctrl/nuvoton/Makefile
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -4,3 +4,5 @@
obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o
obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o
obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o
+obj-$(CONFIG_PINCTRL_MA35) += pinctrl-ma35.o
+obj-$(CONFIG_PINCTRL_MA35D1) += pinctrl-ma35d1.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c
new file mode 100644
index 000000000000..fb933cddde91
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c
@@ -0,0 +1,1187 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Nuvoton Technology Corp.
+ *
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ * * Jacky Huang <ychuang3@nuvoton.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/cleanup.h>
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "../core.h"
+#include "../pinconf.h"
+#include "pinctrl-ma35.h"
+
+#define MA35_MFP_REG_BASE 0x80
+#define MA35_MFP_REG_SZ_PER_BANK 8
+#define MA35_MFP_BITS_PER_PORT 4
+
+#define MA35_GPIO_BANK_MAX 14
+#define MA35_GPIO_PORT_MAX 16
+
+/* GPIO control registers */
+#define MA35_GP_REG_MODE 0x00
+#define MA35_GP_REG_DINOFF 0x04
+#define MA35_GP_REG_DOUT 0x08
+#define MA35_GP_REG_DATMSK 0x0c
+#define MA35_GP_REG_PIN 0x10
+#define MA35_GP_REG_DBEN 0x14
+#define MA35_GP_REG_INTTYPE 0x18
+#define MA35_GP_REG_INTEN 0x1c
+#define MA35_GP_REG_INTSRC 0x20
+#define MA35_GP_REG_SMTEN 0x24
+#define MA35_GP_REG_SLEWCTL 0x28
+#define MA35_GP_REG_SPW 0x2c
+#define MA35_GP_REG_PUSEL 0x30
+#define MA35_GP_REG_DSL 0x38
+#define MA35_GP_REG_DSH 0x3c
+
+/* GPIO mode control */
+#define MA35_GP_MODE_INPUT 0x0
+#define MA35_GP_MODE_OUTPUT 0x1
+#define MA35_GP_MODE_OPEN_DRAIN 0x2
+#define MA35_GP_MODE_QUASI 0x3
+#define MA35_GP_MODE_MASK(n) GENMASK(n * 2 + 1, n * 2)
+
+#define MA35_GP_SLEWCTL_MASK(n) GENMASK(n * 2 + 1, n * 2)
+
+/* GPIO pull-up and pull-down selection control */
+#define MA35_GP_PUSEL_DISABLE 0x0
+#define MA35_GP_PUSEL_PULL_UP 0x1
+#define MA35_GP_PUSEL_PULL_DOWN 0x2
+#define MA35_GP_PUSEL_MASK(n) GENMASK(n * 2 + 1, n * 2)
+
+/*
+ * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
+ * while bits 16 ~ 31 control high-level or rising edge trigger.
+ */
+#define MA35_GP_INTEN_L(n) BIT(n)
+#define MA35_GP_INTEN_H(n) BIT(n + 16)
+#define MA35_GP_INTEN_BOTH(n) (MA35_GP_INTEN_H(n) | MA35_GP_INTEN_L(n))
+
+/*
+ * The MA35_GP_REG_DSL register controls ports 0 to 7, while the MA35_GP_REG_DSH
+ * register controls ports 8 to 15. Each port occupies a width of 4 bits, with 3
+ * bits being effective.
+ */
+#define MA35_GP_DS_REG(n) (n < 8 ? MA35_GP_REG_DSL : MA35_GP_REG_DSH)
+#define MA35_GP_DS_MASK(n) GENMASK((n % 8) * 4 + 3, (n % 8) * 4)
+
+#define MVOLT_1800 0
+#define MVOLT_3300 1
+
+/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
+#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
+#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
+
+static const char * const gpio_group_name[] = {
+ "gpioa", "gpiob", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog",
+ "gpioh", "gpioi", "gpioj", "gpiok", "gpiol", "gpiom", "gpion",
+};
+
+static const u32 ds_1800mv_tbl[] = {
+ 2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000,
+};
+
+static const u32 ds_3300mv_tbl[] = {
+ 17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000,
+};
+
+struct ma35_pin_func {
+ const char *name;
+ const char **groups;
+ u32 ngroups;
+};
+
+struct ma35_pin_setting {
+ u32 offset;
+ u32 shift;
+ u32 muxval;
+ unsigned long *configs;
+ unsigned int nconfigs;
+};
+
+struct ma35_pin_group {
+ const char *name;
+ unsigned int npins;
+ unsigned int *pins;
+ struct ma35_pin_setting *settings;
+};
+
+struct ma35_pin_bank {
+ void __iomem *reg_base;
+ struct clk *clk;
+ int irq;
+ u8 bank_num;
+ u8 nr_pins;
+ bool valid;
+ const char *name;
+ struct fwnode_handle *fwnode;
+ struct gpio_chip chip;
+ u32 irqtype;
+ u32 irqinten;
+ struct regmap *regmap;
+ struct device *dev;
+};
+
+struct ma35_pin_ctrl {
+ struct ma35_pin_bank *pin_banks;
+ u32 nr_banks;
+ u32 nr_pins;
+};
+
+struct ma35_pinctrl {
+ struct device *dev;
+ struct ma35_pin_ctrl *ctrl;
+ struct pinctrl_dev *pctl;
+ const struct ma35_pinctrl_soc_info *info;
+ struct regmap *regmap;
+ struct ma35_pin_group *groups;
+ unsigned int ngroups;
+ struct ma35_pin_func *functions;
+ unsigned int nfunctions;
+};
+
+static DEFINE_RAW_SPINLOCK(ma35_lock);
+
+static int ma35_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return npctl->ngroups;
+}
+
+static const char *ma35_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return npctl->groups[selector].name;
+}
+
+static int ma35_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
+ const unsigned int **pins, unsigned int *npins)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+ if (selector >= npctl->ngroups)
+ return -EINVAL;
+
+ *pins = npctl->groups[selector].pins;
+ *npins = npctl->groups[selector].npins;
+
+ return 0;
+}
+
+static struct ma35_pin_group *ma35_pinctrl_find_group_by_name(
+ const struct ma35_pinctrl *npctl, const char *name)
+{
+ int i;
+
+ for (i = 0; i < npctl->ngroups; i++) {
+ if (!strcmp(npctl->groups[i].name, name))
+ return &npctl->groups[i];
+ }
+ return NULL;
+}
+
+static int ma35_pinctrl_dt_node_to_map_func(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map,
+ unsigned int *num_maps)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+ struct ma35_pin_group *grp;
+ struct pinctrl_map *new_map;
+ struct device_node *parent;
+ int map_num = 1;
+ int i;
+
+ /*
+ * first find the group of this node and check if we need create
+ * config maps for pins
+ */
+ grp = ma35_pinctrl_find_group_by_name(npctl, np->name);
+ if (!grp) {
+ dev_err(npctl->dev, "unable to find group for node %s\n", np->name);
+ return -EINVAL;
+ }
+
+ map_num += grp->npins;
+ new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), GFP_KERNEL);
+ if (!new_map)
+ return -ENOMEM;
+
+ *map = new_map;
+ *num_maps = map_num;
+ /* create mux map */
+ parent = of_get_parent(np);
+ if (!parent)
+ return -EINVAL;
+
+ new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+ new_map[0].data.mux.function = parent->name;
+ new_map[0].data.mux.group = np->name;
+ of_node_put(parent);
+
+ new_map++;
+ for (i = 0; i < grp->npins; i++) {
+ new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->pins[i]);
+ new_map[i].data.configs.configs = grp->settings[i].configs;
+ new_map[i].data.configs.num_configs = grp->settings[i].nconfigs;
+ }
+ dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+ (*map)->data.mux.function, (*map)->data.mux.group, map_num);
+
+ return 0;
+}
+
+static const struct pinctrl_ops ma35_pctrl_ops = {
+ .get_groups_count = ma35_get_groups_count,
+ .get_group_name = ma35_get_group_name,
+ .get_group_pins = ma35_get_group_pins,
+ .dt_node_to_map = ma35_pinctrl_dt_node_to_map_func,
+ .dt_free_map = pinconf_generic_dt_free_map,
+};
+
+static int ma35_pinmux_get_func_count(struct pinctrl_dev *pctldev)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return npctl->nfunctions;
+}
+
+static const char *ma35_pinmux_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return npctl->functions[selector].name;
+}
+
+static int ma35_pinmux_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ const char *const **groups,
+ unsigned int *const num_groups)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = npctl->functions[function].groups;
+ *num_groups = npctl->functions[function].ngroups;
+
+ return 0;
+}
+
+static int ma35_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
+ unsigned int group)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+ struct ma35_pin_group *grp = &npctl->groups[group];
+ struct ma35_pin_setting *setting = grp->settings;
+ u32 i, regval;
+
+ dev_dbg(npctl->dev, "enable function %s group %s\n",
+ npctl->functions[selector].name, npctl->groups[group].name);
+
+ for (i = 0; i < grp->npins; i++) {
+ regmap_read(npctl->regmap, setting->offset, ®val);
+ regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1,
+ setting->shift);
+ regval |= setting->muxval << setting->shift;
+ regmap_write(npctl->regmap, setting->offset, regval);
+ setting++;
+ }
+ return 0;
+}
+
+static const struct pinmux_ops ma35_pmx_ops = {
+ .get_functions_count = ma35_pinmux_get_func_count,
+ .get_function_name = ma35_pinmux_get_func_name,
+ .get_function_groups = ma35_pinmux_get_func_groups,
+ .set_mux = ma35_pinmux_set_mux,
+ .strict = true,
+};
+
+static void ma35_gpio_set_mode(void __iomem *reg_mode, unsigned int gpio, u32 mode)
+{
+ u32 regval = readl(reg_mode);
+
+ regval &= ~MA35_GP_MODE_MASK(gpio);
+ regval |= field_prep(MA35_GP_MODE_MASK(gpio), mode);
+
+ writel(regval, reg_mode);
+}
+
+static u32 ma35_gpio_get_mode(void __iomem *reg_mode, unsigned int gpio)
+{
+ u32 regval = readl(reg_mode);
+
+ return field_get(MA35_GP_MODE_MASK(gpio), regval);
+}
+
+static int ma35_gpio_core_direction_in(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+ void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
+
+ guard(raw_spinlock_irqsave)(&ma35_lock);
+
+ ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_INPUT);
+
+ return 0;
+}
+
+static int ma35_gpio_core_direction_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+ void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
+ void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
+ unsigned int regval;
+
+ guard(raw_spinlock_irqsave)(&ma35_lock);
+
+ regval = readl(reg_dout);
+ if (val)
+ regval |= BIT(gpio);
+ else
+ regval &= ~BIT(gpio);
+ writel(regval, reg_dout);
+
+ ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_OUTPUT);
+
+ return 0;
+}
+
+static int ma35_gpio_core_get(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+ void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN;
+
+ return !!(readl(reg_pin) & BIT(gpio));
+}
+
+static void ma35_gpio_core_set(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+ void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
+ u32 regval;
+
+ if (val)
+ regval = readl(reg_dout) | BIT(gpio);
+ else
+ regval = readl(reg_dout) & ~BIT(gpio);
+
+ writel(regval, reg_dout);
+}
+
+static int ma35_gpio_core_to_request(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+ u32 reg_offs, bit_offs, regval;
+
+ if (gpio < 8) {
+ /* The MFP low register controls port 0 ~ 7 */
+ reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK;
+ bit_offs = gpio * MA35_MFP_BITS_PER_PORT;
+ } else {
+ /* The MFP high register controls port 8 ~ 15 */
+ reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK + 4;
+ bit_offs = (gpio - 8) * MA35_MFP_BITS_PER_PORT;
+ }
+
+ regmap_read(bank->regmap, MA35_MFP_REG_BASE + reg_offs, ®val);
+ regval &= ~GENMASK(bit_offs + MA35_MFP_BITS_PER_PORT - 1, bit_offs);
+ regmap_write(bank->regmap, MA35_MFP_REG_BASE + reg_offs, regval);
+
+ return 0;
+}
+
+static void ma35_irq_gpio_ack(struct irq_data *d)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ void __iomem *reg_intsrc = bank->reg_base + MA35_GP_REG_INTSRC;
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+
+ writel(BIT(hwirq), reg_intsrc);
+}
+
+static void ma35_irq_gpio_mask(struct irq_data *d)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+ u32 regval;
+
+ regval = readl(reg_ien);
+
+ regval &= ~MA35_GP_INTEN_BOTH(hwirq);
+
+ writel(regval, reg_ien);
+}
+
+static void ma35_irq_gpio_unmask(struct irq_data *d)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ void __iomem *reg_itype = bank->reg_base + MA35_GP_REG_INTTYPE;
+ void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+ u32 bval, regval;
+
+ bval = bank->irqtype & BIT(hwirq);
+ regval = readl(reg_itype);
+ regval &= ~BIT(hwirq);
+ writel(regval | bval, reg_itype);
+
+ bval = bank->irqinten & MA35_GP_INTEN_BOTH(hwirq);
+ regval = readl(reg_ien);
+ regval &= ~MA35_GP_INTEN_BOTH(hwirq);
+ writel(regval | bval, reg_ien);
+}
+
+static int ma35_irq_irqtype(struct irq_data *d, unsigned int type)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_BOTH:
+ irq_set_handler_locked(d, handle_edge_irq);
+ bank->irqtype &= ~BIT(hwirq);
+ bank->irqinten |= MA35_GP_INTEN_BOTH(hwirq);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ case IRQ_TYPE_LEVEL_HIGH:
+ irq_set_handler_locked(d, handle_edge_irq);
+ bank->irqtype &= ~BIT(hwirq);
+ bank->irqinten |= MA35_GP_INTEN_H(hwirq);
+ bank->irqinten &= ~MA35_GP_INTEN_L(hwirq);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ case IRQ_TYPE_LEVEL_LOW:
+ irq_set_handler_locked(d, handle_edge_irq);
+ bank->irqtype &= ~BIT(hwirq);
+ bank->irqinten |= MA35_GP_INTEN_L(hwirq);
+ bank->irqinten &= ~MA35_GP_INTEN_H(hwirq);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ writel(bank->irqtype, bank->reg_base + MA35_GP_REG_INTTYPE);
+ writel(bank->irqinten, bank->reg_base + MA35_GP_REG_INTEN);
+
+ return 0;
+}
+
+static struct irq_chip ma35_gpio_irqchip = {
+ .name = "MA35-GPIO-IRQ",
+ .irq_disable = ma35_irq_gpio_mask,
+ .irq_enable = ma35_irq_gpio_unmask,
+ .irq_ack = ma35_irq_gpio_ack,
+ .irq_mask = ma35_irq_gpio_mask,
+ .irq_unmask = ma35_irq_gpio_unmask,
+ .irq_set_type = ma35_irq_irqtype,
+ .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
+ GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static void ma35_irq_demux_intgroup(struct irq_desc *desc)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(irq_desc_get_handler_data(desc));
+ struct irq_domain *irqdomain = bank->chip.irq.domain;
+ struct irq_chip *irqchip = irq_desc_get_chip(desc);
+ unsigned long isr;
+ int offset;
+
+ chained_irq_enter(irqchip, desc);
+
+ isr = readl(bank->reg_base + MA35_GP_REG_INTSRC);
+
+ for_each_set_bit(offset, &isr, bank->nr_pins)
+ generic_handle_irq(irq_find_mapping(irqdomain, offset));
+
+ chained_irq_exit(irqchip, desc);
+}
+
+static int ma35_gpiolib_register(struct platform_device *pdev, struct ma35_pinctrl *npctl)
+{
+ struct ma35_pin_ctrl *ctrl = npctl->ctrl;
+ struct ma35_pin_bank *bank = ctrl->pin_banks;
+ int ret;
+ int i;
+
+ for (i = 0; i < ctrl->nr_banks; i++, bank++) {
+ if (!bank->valid) {
+ dev_warn(&pdev->dev, "%pfw: bank is not valid\n", bank->fwnode);
+ continue;
+ }
+ bank->irqtype = 0;
+ bank->irqinten = 0;
+ bank->chip.label = bank->name;
+ bank->chip.of_gpio_n_cells = 2;
+ bank->chip.parent = &pdev->dev;
+ bank->chip.request = ma35_gpio_core_to_request;
+ bank->chip.direction_input = ma35_gpio_core_direction_in;
+ bank->chip.direction_output = ma35_gpio_core_direction_out;
+ bank->chip.get = ma35_gpio_core_get;
+ bank->chip.set = ma35_gpio_core_set;
+ bank->chip.base = -1;
+ bank->chip.ngpio = bank->nr_pins;
+ bank->chip.can_sleep = false;
+
+ if (bank->irq > 0) {
+ struct gpio_irq_chip *girq;
+
+ girq = &bank->chip.irq;
+ gpio_irq_chip_set_chip(girq, &ma35_gpio_irqchip);
+ girq->parent_handler = ma35_irq_demux_intgroup;
+ girq->num_parents = 1;
+
+ girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
+ sizeof(*girq->parents), GFP_KERNEL);
+ if (!girq->parents)
+ return -ENOMEM;
+
+ girq->parents[0] = bank->irq;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_bad_irq;
+ }
+
+ ret = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
+ bank->chip.label, ret);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static int ma35_get_bank_data(struct ma35_pin_bank *bank)
+{
+ bank->reg_base = fwnode_iomap(bank->fwnode, 0);
+ if (IS_ERR(bank->reg_base))
+ return PTR_ERR(bank->reg_base);
+
+ bank->irq = fwnode_irq_get(bank->fwnode, 0);
+
+ bank->nr_pins = MA35_GPIO_PORT_MAX;
+
+ bank->clk = of_clk_get(to_of_node(bank->fwnode), 0);
+ if (IS_ERR(bank->clk))
+ return PTR_ERR(bank->clk);
+
+ return clk_prepare_enable(bank->clk);
+}
+
+static int ma35_pinctrl_get_soc_data(struct ma35_pinctrl *pctl, struct platform_device *pdev)
+{
+ struct fwnode_handle *child;
+ struct ma35_pin_ctrl *ctrl;
+ struct ma35_pin_bank *bank;
+ int i, id = 0;
+
+ ctrl = pctl->ctrl;
+ ctrl->nr_banks = MA35_GPIO_BANK_MAX;
+
+ ctrl->pin_banks = devm_kcalloc(&pdev->dev, ctrl->nr_banks,
+ sizeof(*ctrl->pin_banks), GFP_KERNEL);
+ if (!ctrl->pin_banks)
+ return -ENOMEM;
+
+ for (i = 0; i < ctrl->nr_banks; i++) {
+ ctrl->pin_banks[i].bank_num = i;
+ ctrl->pin_banks[i].name = gpio_group_name[i];
+ }
+
+ for_each_gpiochip_node(&pdev->dev, child) {
+ bank = &ctrl->pin_banks[id];
+ bank->fwnode = child;
+ bank->regmap = pctl->regmap;
+ bank->dev = &pdev->dev;
+ if (!ma35_get_bank_data(bank))
+ bank->valid = true;
+ id++;
+ }
+ return 0;
+}
+
+static void ma35_gpio_cla_port(unsigned int gpio_num, unsigned int *group,
+ unsigned int *num)
+{
+ *group = gpio_num / MA35_GPIO_PORT_MAX;
+ *num = gpio_num % MA35_GPIO_PORT_MAX;
+}
+
+static int ma35_pinconf_set_pull(struct ma35_pinctrl *npctl, unsigned int pin,
+ int pull_up)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval, pull_sel = MA35_GP_PUSEL_DISABLE;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_PUSEL);
+ regval &= ~MA35_GP_PUSEL_MASK(port);
+
+ switch (pull_up) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ pull_sel = MA35_GP_PUSEL_PULL_UP;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ pull_sel = MA35_GP_PUSEL_PULL_DOWN;
+ break;
+
+ case PIN_CONFIG_BIAS_DISABLE:
+ pull_sel = MA35_GP_PUSEL_DISABLE;
+ break;
+ }
+
+ regval |= field_prep(MA35_GP_PUSEL_MASK(port), pull_sel);
+ writel(regval, base + MA35_GP_REG_PUSEL);
+
+ return 0;
+}
+
+static int ma35_pinconf_get_output(struct ma35_pinctrl *npctl, unsigned int pin)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 mode;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ mode = ma35_gpio_get_mode(base + MA35_GP_REG_MODE, port);
+ if (mode == MA35_GP_MODE_OUTPUT)
+ return 1;
+
+ return 0;
+}
+
+static int ma35_pinconf_get_pull(struct ma35_pinctrl *npctl, unsigned int pin)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval, pull_sel;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_PUSEL);
+
+ pull_sel = field_get(MA35_GP_PUSEL_MASK(port), regval);
+
+ switch (pull_sel) {
+ case MA35_GP_PUSEL_PULL_UP:
+ return PIN_CONFIG_BIAS_PULL_UP;
+
+ case MA35_GP_PUSEL_PULL_DOWN:
+ return PIN_CONFIG_BIAS_PULL_DOWN;
+
+ case MA35_GP_PUSEL_DISABLE:
+ return PIN_CONFIG_BIAS_DISABLE;
+ }
+
+ return PIN_CONFIG_BIAS_DISABLE;
+}
+
+static int ma35_pinconf_set_output(struct ma35_pinctrl *npctl, unsigned int pin, bool out)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ ma35_gpio_set_mode(base + MA35_GP_REG_MODE, port, MA35_GP_MODE_OUTPUT);
+
+ return 0;
+}
+
+static int ma35_pinconf_get_power_source(struct ma35_pinctrl *npctl, unsigned int pin)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_SPW);
+
+ if (regval & BIT(port))
+ return MVOLT_3300;
+ else
+ return MVOLT_1800;
+}
+
+static int ma35_pinconf_set_power_source(struct ma35_pinctrl *npctl,
+ unsigned int pin, int arg)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval;
+
+ if ((arg != MVOLT_1800) && (arg != MVOLT_3300))
+ return -EINVAL;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_SPW);
+
+ if (arg == MVOLT_1800)
+ regval &= ~BIT(port);
+ else
+ regval |= BIT(port);
+
+ writel(regval, base + MA35_GP_REG_SPW);
+
+ return 0;
+}
+
+static int ma35_pinconf_get_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin,
+ u32 *strength)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval, ds_val;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_DS_REG(port));
+ ds_val = field_get(MA35_GP_DS_MASK(port), regval);
+
+ if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800)
+ *strength = ds_1800mv_tbl[ds_val];
+ else
+ *strength = ds_3300mv_tbl[ds_val];
+
+ return 0;
+}
+
+static int ma35_pinconf_set_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin,
+ int strength)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ int i, ds_val = -1;
+ u32 regval;
+
+ if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800) {
+ for (i = 0; i < ARRAY_SIZE(ds_1800mv_tbl); i++) {
+ if (ds_1800mv_tbl[i] == strength) {
+ ds_val = i;
+ break;
+ }
+ }
+ } else {
+ for (i = 0; i < ARRAY_SIZE(ds_3300mv_tbl); i++) {
+ if (ds_3300mv_tbl[i] == strength) {
+ ds_val = i;
+ break;
+ }
+ }
+ }
+ if (ds_val == -1)
+ return -EINVAL;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_DS_REG(port));
+ regval &= ~MA35_GP_DS_MASK(port);
+ regval |= field_prep(MA35_GP_DS_MASK(port), ds_val);
+
+ writel(regval, base + MA35_GP_DS_REG(port));
+
+ return 0;
+}
+
+static int ma35_pinconf_get_schmitt_enable(struct ma35_pinctrl *npctl, unsigned int pin)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_SMTEN);
+
+ return !!(regval & BIT(port));
+}
+
+static int ma35_pinconf_set_schmitt(struct ma35_pinctrl *npctl, unsigned int pin, int enable)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_SMTEN);
+
+ if (enable)
+ regval |= BIT(port);
+ else
+ regval &= ~BIT(port);
+
+ writel(regval, base + MA35_GP_REG_SMTEN);
+
+ return 0;
+}
+
+static int ma35_pinconf_get_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_SLEWCTL);
+
+ return field_get(MA35_GP_SLEWCTL_MASK(port), regval);
+}
+
+static int ma35_pinconf_set_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin, int rate)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_SLEWCTL);
+ regval &= ~MA35_GP_SLEWCTL_MASK(port);
+ regval |= field_prep(MA35_GP_SLEWCTL_MASK(port), rate);
+
+ writel(regval, base + MA35_GP_REG_SLEWCTL);
+
+ return 0;
+}
+
+static int ma35_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ u32 arg;
+ int ret;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (ma35_pinconf_get_pull(npctl, pin) != param)
+ return -EINVAL;
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ ret = ma35_pinconf_get_drive_strength(npctl, pin, &arg);
+ if (ret)
+ return ret;
+ break;
+
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ arg = ma35_pinconf_get_schmitt_enable(npctl, pin);
+ break;
+
+ case PIN_CONFIG_SLEW_RATE:
+ arg = ma35_pinconf_get_slew_rate(npctl, pin);
+ break;
+
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ arg = ma35_pinconf_get_output(npctl, pin);
+ break;
+
+ case PIN_CONFIG_POWER_SOURCE:
+ arg = ma35_pinconf_get_power_source(npctl, pin);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ *config = pinconf_to_config_packed(param, arg);
+
+ return 0;
+}
+
+static int ma35_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param;
+ unsigned int arg = 0;
+ int i, ret = 0;
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ ret = ma35_pinconf_set_pull(npctl, pin, param);
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ ret = ma35_pinconf_set_drive_strength(npctl, pin, arg);
+ break;
+
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ ret = ma35_pinconf_set_schmitt(npctl, pin, 1);
+ break;
+
+ case PIN_CONFIG_INPUT_SCHMITT:
+ ret = ma35_pinconf_set_schmitt(npctl, pin, arg);
+ break;
+
+ case PIN_CONFIG_SLEW_RATE:
+ ret = ma35_pinconf_set_slew_rate(npctl, pin, arg);
+ break;
+
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ ret = ma35_pinconf_set_output(npctl, pin, arg);
+ break;
+
+ case PIN_CONFIG_POWER_SOURCE:
+ ret = ma35_pinconf_set_power_source(npctl, pin, arg);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ if (ret)
+ break;
+ }
+ return ret;
+}
+
+static const struct pinconf_ops ma35_pinconf_ops = {
+ .pin_config_get = ma35_pinconf_get,
+ .pin_config_set = ma35_pinconf_set,
+ .is_generic = true,
+};
+
+static int ma35_pinctrl_parse_groups(struct device_node *np, struct ma35_pin_group *grp,
+ struct ma35_pinctrl *npctl, u32 index)
+{
+ struct ma35_pin_setting *pin;
+ unsigned long *configs;
+ unsigned int nconfigs;
+ int i, j, count, ret;
+ u32 *elems;
+
+ grp->name = np->name;
+
+ ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &nconfigs);
+ if (ret)
+ return ret;
+
+ count = of_property_count_elems_of_size(np, "nuvoton,pins", sizeof(u32));
+ if (!count || count % 3)
+ return -EINVAL;
+
+ elems = devm_kmalloc_array(npctl->dev, count, sizeof(u32), GFP_KERNEL);
+ if (!elems)
+ return -ENOMEM;
+
+ ret = of_property_read_u32_array(np, "nuvoton,pins", elems, count);
+ if (ret)
+ return -EINVAL;
+
+ grp->npins = count / 3;
+
+ grp->pins = devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
+ if (!grp->pins)
+ return -ENOMEM;
+
+ grp->settings = devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->settings), GFP_KERNEL);
+ if (!grp->settings)
+ return -ENOMEM;
+
+ pin = grp->settings;
+
+ for (i = 0, j = 0; i < count; i += 3, j++) {
+ pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE;
+ pin->shift = (elems[i + 1] * MA35_MFP_BITS_PER_PORT) % 32;
+ pin->muxval = elems[i + 2];
+ pin->configs = configs;
+ pin->nconfigs = nconfigs;
+ grp->pins[j] = npctl->info->get_pin_num(pin->offset, pin->shift);
+ pin++;
+ }
+ return 0;
+}
+
+static int ma35_pinctrl_parse_functions(struct device_node *np, struct ma35_pinctrl *npctl,
+ u32 index)
+{
+ struct device_node *child;
+ struct ma35_pin_func *func;
+ struct ma35_pin_group *grp;
+ static u32 grp_index;
+ u32 ret, i = 0;
+
+ dev_dbg(npctl->dev, "parse function(%d): %s\n", index, np->name);
+
+ func = &npctl->functions[index];
+ func->name = np->name;
+ func->ngroups = of_get_child_count(np);
+
+ if (func->ngroups <= 0)
+ return 0;
+
+ func->groups = devm_kcalloc(npctl->dev, func->ngroups, sizeof(char *), GFP_KERNEL);
+ if (!func->groups)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ func->groups[i] = child->name;
+ grp = &npctl->groups[grp_index++];
+ ret = ma35_pinctrl_parse_groups(child, grp, npctl, i++);
+ if (ret) {
+ of_node_put(child);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinctrl *npctl)
+{
+ struct fwnode_handle *child;
+ u32 idx = 0;
+ int ret;
+
+ device_for_each_child_node(&pdev->dev, child) {
+ if (fwnode_property_present(child, "gpio-controller"))
+ continue;
+ npctl->nfunctions++;
+ npctl->ngroups += of_get_child_count(to_of_node(child));
+ }
+
+ if (!npctl->nfunctions)
+ return -EINVAL;
+
+ npctl->functions = devm_kcalloc(&pdev->dev, npctl->nfunctions,
+ sizeof(*npctl->functions), GFP_KERNEL);
+ if (!npctl->functions)
+ return -ENOMEM;
+
+ npctl->groups = devm_kcalloc(&pdev->dev, npctl->ngroups,
+ sizeof(*npctl->groups), GFP_KERNEL);
+ if (!npctl->groups)
+ return -ENOMEM;
+
+ device_for_each_child_node(&pdev->dev, child) {
+ if (fwnode_property_present(child, "gpio-controller"))
+ continue;
+
+ ret = ma35_pinctrl_parse_functions(to_of_node(child), npctl, idx++);
+ if (ret) {
+ fwnode_handle_put(child);
+ dev_err(&pdev->dev, "failed to parse function\n");
+ return ret;
+ }
+ }
+ return 0;
+}
+
+int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_soc_info *info)
+{
+ struct pinctrl_desc *ma35_pinctrl_desc;
+ struct device *dev = &pdev->dev;
+ struct ma35_pinctrl *npctl;
+ int ret;
+
+ if (!info || !info->pins || !info->npins) {
+ dev_err(&pdev->dev, "wrong pinctrl info\n");
+ return -EINVAL;
+ }
+
+ npctl = devm_kzalloc(&pdev->dev, sizeof(*npctl), GFP_KERNEL);
+ if (!npctl)
+ return -ENOMEM;
+
+ ma35_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ma35_pinctrl_desc), GFP_KERNEL);
+ if (!ma35_pinctrl_desc)
+ return -ENOMEM;
+
+ npctl->ctrl = devm_kzalloc(&pdev->dev, sizeof(*npctl->ctrl), GFP_KERNEL);
+ if (!npctl->ctrl)
+ return -ENOMEM;
+
+ ma35_pinctrl_desc->name = dev_name(&pdev->dev);
+ ma35_pinctrl_desc->pins = info->pins;
+ ma35_pinctrl_desc->npins = info->npins;
+ ma35_pinctrl_desc->pctlops = &ma35_pctrl_ops;
+ ma35_pinctrl_desc->pmxops = &ma35_pmx_ops;
+ ma35_pinctrl_desc->confops = &ma35_pinconf_ops;
+ ma35_pinctrl_desc->owner = THIS_MODULE;
+
+ npctl->info = info;
+ npctl->dev = &pdev->dev;
+
+ npctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "nuvoton,sys");
+ if (IS_ERR(npctl->regmap))
+ return dev_err_probe(&pdev->dev, PTR_ERR(npctl->regmap),
+ "No syscfg phandle specified\n");
+
+ ret = ma35_pinctrl_get_soc_data(npctl, pdev);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "fail to get soc data\n");
+
+ platform_set_drvdata(pdev, npctl);
+
+ ret = ma35_pinctrl_probe_dt(pdev, npctl);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "fail to probe MA35 pinctrl dt\n");
+
+ ret = devm_pinctrl_register_and_init(dev, ma35_pinctrl_desc, npctl, &npctl->pctl);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "fail to register MA35 pinctrl\n");
+
+ ret = pinctrl_enable(npctl->pctl);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "fail to enable MA35 pinctrl\n");
+
+ return ma35_gpiolib_register(pdev, npctl);
+}
+
+int ma35_pinctrl_suspend(struct device *dev)
+{
+ struct ma35_pinctrl *npctl = dev_get_drvdata(dev);
+
+ return pinctrl_force_sleep(npctl->pctl);
+}
+
+int ma35_pinctrl_resume(struct device *dev)
+{
+ struct ma35_pinctrl *npctl = dev_get_drvdata(dev);
+
+ return pinctrl_force_default(npctl->pctl);
+}
diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.h b/drivers/pinctrl/nuvoton/pinctrl-ma35.h
new file mode 100644
index 000000000000..218084100541
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Nuvoton Technology Corp.
+ *
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ * * Jacky Huang <ychuang3@nuvoton.com>
+ */
+#ifndef __PINCTRL_MA35_H
+#define __PINCTRL_MA35_H
+
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+
+struct ma35_mux_desc {
+ const char *name;
+ u32 muxval;
+};
+
+struct ma35_pin_data {
+ u32 offset;
+ u32 shift;
+ struct ma35_mux_desc *muxes;
+};
+
+struct ma35_pinctrl_soc_info {
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ int (*get_pin_num)(int offset, int shift);
+};
+
+#define MA35_PIN(num, n, o, s, ...) { \
+ .number = num, \
+ .name = #n, \
+ .drv_data = &(struct ma35_pin_data) { \
+ .offset = o, \
+ .shift = s, \
+ .muxes = (struct ma35_mux_desc[]) { \
+ __VA_ARGS__, { } }, \
+ }, \
+}
+
+#define MA35_MUX(_val, _name) { \
+ .name = _name, \
+ .muxval = _val, \
+}
+
+int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_soc_info *info);
+int ma35_pinctrl_suspend(struct device *dev);
+int ma35_pinctrl_resume(struct device *dev);
+
+#endif /* __PINCTRL_MA35_H */
diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c b/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
new file mode 100644
index 000000000000..8bb9a5a35954
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
@@ -0,0 +1,1799 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Nuvoton Technology Corp.
+ *
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ * * Jacky Huang <ychuang3@nuvoton.com>
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-ma35.h"
+
+static const struct pinctrl_pin_desc ma35d1_pins[] = {
+ MA35_PIN(0, PA0, 0x80, 0x0,
+ MA35_MUX(0x0, "GPA0"),
+ MA35_MUX(0x2, "UART1_nCTS"),
+ MA35_MUX(0x3, "UART16_RXD"),
+ MA35_MUX(0x6, "NAND_DATA0"),
+ MA35_MUX(0x7, "EBI_AD0"),
+ MA35_MUX(0x9, "EBI_ADR0")),
+ MA35_PIN(1, PA1, 0x80, 0x4,
+ MA35_MUX(0x0, "GPA1"),
+ MA35_MUX(0x2, "UART1_nRTS"),
+ MA35_MUX(0x3, "UART16_TXD"),
+ MA35_MUX(0x6, "NAND_DATA1"),
+ MA35_MUX(0x7, "EBI_AD1"),
+ MA35_MUX(0x9, "EBI_ADR1")),
+ MA35_PIN(2, PA2, 0x80, 0x8,
+ MA35_MUX(0x0, "GPA2"),
+ MA35_MUX(0x2, "UART1_RXD"),
+ MA35_MUX(0x6, "NAND_DATA2"),
+ MA35_MUX(0x7, "EBI_AD2"),
+ MA35_MUX(0x9, "EBI_ADR2")),
+ MA35_PIN(3, PA3, 0x80, 0xc,
+ MA35_MUX(0x0, "GPA3"),
+ MA35_MUX(0x2, "UART1_TXD"),
+ MA35_MUX(0x6, "NAND_DATA3"),
+ MA35_MUX(0x7, "EBI_AD3"),
+ MA35_MUX(0x9, "EBI_ADR3")),
+ MA35_PIN(4, PA4, 0x80, 0x10,
+ MA35_MUX(0x0, "GPA4"),
+ MA35_MUX(0x2, "UART3_nCTS"),
+ MA35_MUX(0x3, "UART2_RXD"),
+ MA35_MUX(0x6, "NAND_DATA4"),
+ MA35_MUX(0x7, "EBI_AD4"),
+ MA35_MUX(0x9, "EBI_ADR4")),
+ MA35_PIN(5, PA5, 0x80, 0x14,
+ MA35_MUX(0x0, "GPA5"),
+ MA35_MUX(0x2, "UART3_nRTS"),
+ MA35_MUX(0x3, "UART2_TXD"),
+ MA35_MUX(0x6, "NAND_DATA5"),
+ MA35_MUX(0x7, "EBI_AD5"),
+ MA35_MUX(0x9, "EBI_ADR5")),
+ MA35_PIN(6, PA6, 0x80, 0x18,
+ MA35_MUX(0x0, "GPA6"),
+ MA35_MUX(0x2, "UART3_RXD"),
+ MA35_MUX(0x6, "NAND_DATA6"),
+ MA35_MUX(0x7, "EBI_AD6"),
+ MA35_MUX(0x9, "EBI_ADR6")),
+ MA35_PIN(7, PA7, 0x80, 0x1c,
+ MA35_MUX(0x0, "GPA7"),
+ MA35_MUX(0x2, "UART3_TXD"),
+ MA35_MUX(0x6, "NAND_DATA7"),
+ MA35_MUX(0x7, "EBI_AD7"),
+ MA35_MUX(0x9, "EBI_ADR7")),
+ MA35_PIN(8, PA8, 0x84, 0x0,
+ MA35_MUX(0x0, "GPA8"),
+ MA35_MUX(0x2, "UART5_nCTS"),
+ MA35_MUX(0x3, "UART4_RXD"),
+ MA35_MUX(0x6, "NAND_RDY0"),
+ MA35_MUX(0x7, "EBI_AD8"),
+ MA35_MUX(0x9, "EBI_ADR8")),
+ MA35_PIN(9, PA9, 0x84, 0x4,
+ MA35_MUX(0x0, "GPA9"),
+ MA35_MUX(0x2, "UART5_nRTS"),
+ MA35_MUX(0x3, "UART4_TXD"),
+ MA35_MUX(0x6, "NAND_nRE"),
+ MA35_MUX(0x7, "EBI_AD9"),
+ MA35_MUX(0x9, "EBI_ADR9")),
+ MA35_PIN(10, PA10, 0x84, 0x8,
+ MA35_MUX(0x0, "GPA10"),
+ MA35_MUX(0x2, "UART5_RXD"),
+ MA35_MUX(0x6, "NAND_nWE"),
+ MA35_MUX(0x7, "EBI_AD10"),
+ MA35_MUX(0x9, "EBI_ADR10")),
+ MA35_PIN(11, PA11, 0x84, 0xc,
+ MA35_MUX(0x0, "GPA11"),
+ MA35_MUX(0x2, "UART5_TXD"),
+ MA35_MUX(0x6, "NAND_CLE"),
+ MA35_MUX(0x7, "EBI_AD11"),
+ MA35_MUX(0x9, "EBI_ADR11")),
+ MA35_PIN(12, PA12, 0x84, 0x10,
+ MA35_MUX(0x0, "GPA12"),
+ MA35_MUX(0x2, "UART7_nCTS"),
+ MA35_MUX(0x3, "UART8_RXD"),
+ MA35_MUX(0x6, "NAND_ALE"),
+ MA35_MUX(0x7, "EBI_AD12"),
+ MA35_MUX(0x9, "EBI_ADR12")),
+ MA35_PIN(13, PA13, 0x84, 0x14,
+ MA35_MUX(0x0, "GPA13"),
+ MA35_MUX(0x2, "UART7_nRTS"),
+ MA35_MUX(0x3, "UART8_TXD"),
+ MA35_MUX(0x6, "NAND_nCS0"),
+ MA35_MUX(0x7, "EBI_AD13"),
+ MA35_MUX(0x9, "EBI_ADR13")),
+ MA35_PIN(14, PA14, 0x84, 0x18,
+ MA35_MUX(0x0, "GPA14"),
+ MA35_MUX(0x2, "UART7_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x6, "NAND_nWP"),
+ MA35_MUX(0x7, "EBI_AD14"),
+ MA35_MUX(0x9, "EBI_ADR14")),
+ MA35_PIN(15, PA15, 0x84, 0x1c,
+ MA35_MUX(0x0, "GPA15"),
+ MA35_MUX(0x1, "EPWM0_CH2"),
+ MA35_MUX(0x2, "UART9_nCTS"),
+ MA35_MUX(0x3, "UART6_RXD"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x5, "CAN2_RXD"),
+ MA35_MUX(0x7, "EBI_ALE"),
+ MA35_MUX(0x9, "QEI0_A"),
+ MA35_MUX(0xb, "TM1"),
+ MA35_MUX(0xe, "RGMII0_PPS"),
+ MA35_MUX(0xf, "RMII0_PPS")),
+ MA35_PIN(16, PB0, 0x88, 0x0,
+ MA35_MUX(0x0, "GPB0"),
+ MA35_MUX(0x8, "EADC0_CH0")),
+ MA35_PIN(17, PB1, 0x88, 0x4,
+ MA35_MUX(0x0, "GPB1"),
+ MA35_MUX(0x8, "EADC0_CH1")),
+ MA35_PIN(18, PB2, 0x88, 0x8,
+ MA35_MUX(0x0, "GPB2"),
+ MA35_MUX(0x8, "EADC0_CH2")),
+ MA35_PIN(19, PB3, 0x88, 0xc,
+ MA35_MUX(0x0, "GPB3"),
+ MA35_MUX(0x8, "EADC0_CH3")),
+ MA35_PIN(20, PB4, 0x88, 0x10,
+ MA35_MUX(0x0, "GPB4"),
+ MA35_MUX(0x8, "EADC0_CH4")),
+ MA35_PIN(21, PB5, 0x88, 0x14,
+ MA35_MUX(0x0, "GPB5"),
+ MA35_MUX(0x8, "EADC0_CH5")),
+ MA35_PIN(22, PB6, 0x88, 0x18,
+ MA35_MUX(0x0, "GPB6"),
+ MA35_MUX(0x8, "EADC0_CH6")),
+ MA35_PIN(23, PB7, 0x88, 0x1c,
+ MA35_MUX(0x0, "GPB7"),
+ MA35_MUX(0x8, "EADC0_CH7")),
+ MA35_PIN(24, PB8, 0x8c, 0x0,
+ MA35_MUX(0x0, "GPB8"),
+ MA35_MUX(0x1, "EPWM2_BRAKE0"),
+ MA35_MUX(0x2, "UART2_nCTS"),
+ MA35_MUX(0x3, "UART1_RXD"),
+ MA35_MUX(0x4, "I2C2_SDA"),
+ MA35_MUX(0x5, "SPI0_SS1"),
+ MA35_MUX(0x6, "SPI0_I2SMCLK"),
+ MA35_MUX(0x8, "ADC0_CH0"),
+ MA35_MUX(0x9, "EBI_nCS0"),
+ MA35_MUX(0xb, "TM4"),
+ MA35_MUX(0xe, "QEI2_INDEX"),
+ MA35_MUX(0xf, "KPI_ROW6")),
+ MA35_PIN(25, PB9, 0x8c, 0x4,
+ MA35_MUX(0x0, "GPB9"),
+ MA35_MUX(0x1, "EPWM2_CH4"),
+ MA35_MUX(0x2, "UART2_nRTS"),
+ MA35_MUX(0x3, "UART1_TXD"),
+ MA35_MUX(0x4, "I2C2_SCL"),
+ MA35_MUX(0x5, "SPI0_CLK"),
+ MA35_MUX(0x6, "I2S0_MCLK"),
+ MA35_MUX(0x7, "CCAP1_HSYNC"),
+ MA35_MUX(0x8, "ADC0_CH1"),
+ MA35_MUX(0x9, "EBI_ALE"),
+ MA35_MUX(0xa, "EBI_AD13"),
+ MA35_MUX(0xb, "TM0_EXT"),
+ MA35_MUX(0xc, "I2S1_MCLK"),
+ MA35_MUX(0xd, "SC0_nCD"),
+ MA35_MUX(0xe, "QEI2_A"),
+ MA35_MUX(0xf, "KPI_ROW7")),
+ MA35_PIN(26, PB10, 0x8c, 0x8,
+ MA35_MUX(0x0, "GPB10"),
+ MA35_MUX(0x1, "EPWM2_CH5"),
+ MA35_MUX(0x2, "UART2_RXD"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x5, "SPI0_MOSI"),
+ MA35_MUX(0x6, "EBI_MCLK"),
+ MA35_MUX(0x7, "CCAP1_VSYNC"),
+ MA35_MUX(0x8, "ADC0_CH2"),
+ MA35_MUX(0x9, "EBI_ADR15"),
+ MA35_MUX(0xa, "EBI_AD14"),
+ MA35_MUX(0xb, "TM5"),
+ MA35_MUX(0xc, "I2C1_SDA"),
+ MA35_MUX(0xd, "INT1"),
+ MA35_MUX(0xe, "QEI2_B")),
+ MA35_PIN(27, PB11, 0x8c, 0xc,
+ MA35_MUX(0x0, "GPB11"),
+ MA35_MUX(0x1, "EPWM2_BRAKE1"),
+ MA35_MUX(0x2, "UART2_TXD"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x5, "SPI0_MISO"),
+ MA35_MUX(0x6, "I2S1_MCLK"),
+ MA35_MUX(0x7, "CCAP1_SFIELD"),
+ MA35_MUX(0x8, "ADC0_CH3"),
+ MA35_MUX(0x9, "EBI_nCS2"),
+ MA35_MUX(0xa, "EBI_ALE"),
+ MA35_MUX(0xb, "TM5_EXT"),
+ MA35_MUX(0xc, "I2C1_SCL"),
+ MA35_MUX(0xd, "INT2"),
+ MA35_MUX(0xe, "QEI2_INDEX")),
+ MA35_PIN(28, PB12, 0x8c, 0x10,
+ MA35_MUX(0x0, "GPB12"),
+ MA35_MUX(0x1, "EPWM2_CH0"),
+ MA35_MUX(0x2, "UART4_nCTS"),
+ MA35_MUX(0x3, "UART3_RXD"),
+ MA35_MUX(0x4, "I2C3_SDA"),
+ MA35_MUX(0x5, "CAN2_RXD"),
+ MA35_MUX(0x6, "I2S1_LRCK"),
+ MA35_MUX(0x8, "ADC0_CH4"),
+ MA35_MUX(0x9, "EBI_ADR16"),
+ MA35_MUX(0xe, "ECAP2_IC0")),
+ MA35_PIN(29, PB13, 0x8c, 0x14,
+ MA35_MUX(0x0, "GPB13"),
+ MA35_MUX(0x1, "EPWM2_CH1"),
+ MA35_MUX(0x2, "UART4_nRTS"),
+ MA35_MUX(0x3, "UART3_TXD"),
+ MA35_MUX(0x4, "I2C3_SCL"),
+ MA35_MUX(0x5, "CAN2_TXD"),
+ MA35_MUX(0x6, "I2S1_BCLK"),
+ MA35_MUX(0x8, "ADC0_CH5"),
+ MA35_MUX(0x9, "EBI_ADR17"),
+ MA35_MUX(0xe, "ECAP2_IC1")),
+ MA35_PIN(30, PB14, 0x8c, 0x18,
+ MA35_MUX(0x0, "GPB14"),
+ MA35_MUX(0x1, "EPWM2_CH2"),
+ MA35_MUX(0x2, "UART4_RXD"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x5, "I2C4_SDA"),
+ MA35_MUX(0x6, "I2S1_DI"),
+ MA35_MUX(0x8, "ADC0_CH6"),
+ MA35_MUX(0x9, "EBI_ADR18"),
+ MA35_MUX(0xe, "ECAP2_IC2")),
+ MA35_PIN(31, PB15, 0x8c, 0x1c,
+ MA35_MUX(0x0, "GPB15"),
+ MA35_MUX(0x1, "EPWM2_CH3"),
+ MA35_MUX(0x2, "UART4_TXD"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x5, "I2C4_SCL"),
+ MA35_MUX(0x6, "I2S1_DO"),
+ MA35_MUX(0x8, "ADC0_CH7"),
+ MA35_MUX(0x9, "EBI_ADR19")),
+ MA35_PIN(32, PC0, 0x90, 0x0,
+ MA35_MUX(0x0, "GPC0"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x6, "SD0_CMD/eMMC0_CMD")),
+ MA35_PIN(33, PC1, 0x90, 0x4,
+ MA35_MUX(0x0, "GPC1"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x6, "SD0_CLK/eMMC0_CLK")),
+ MA35_PIN(34, PC2, 0x90, 0x8,
+ MA35_MUX(0x0, "GPC2"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x6, "SD0_DAT0/eMMC0_DAT0")),
+ MA35_PIN(35, PC3, 0x90, 0xc,
+ MA35_MUX(0x0, "GPC3"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x6, "SD0_DAT1/eMMC0_DAT1")),
+ MA35_PIN(36, PC4, 0x90, 0x10,
+ MA35_MUX(0x0, "GPC4"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x6, "SD0_DAT2/eMMC0_DAT2")),
+ MA35_PIN(37, PC5, 0x90, 0x14,
+ MA35_MUX(0x0, "GPC5"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x6, "SD0_DAT3/eMMC0_DAT3")),
+ MA35_PIN(38, PC6, 0x90, 0x18,
+ MA35_MUX(0x0, "GPC6"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x6, "SD0_nCD")),
+ MA35_PIN(39, PC7, 0x90, 0x1c,
+ MA35_MUX(0x0, "GPC7"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x6, "SD0_WP")),
+ MA35_PIN(40, PC12, 0x94, 0x10,
+ MA35_MUX(0x0, "GPC12"),
+ MA35_MUX(0x2, "UART12_nCTS"),
+ MA35_MUX(0x3, "UART11_RXD"),
+ MA35_MUX(0x6, "LCM_DATA16")),
+ MA35_PIN(41, PC13, 0x94, 0x14,
+ MA35_MUX(0x0, "GPC13"),
+ MA35_MUX(0x2, "UART12_nRTS"),
+ MA35_MUX(0x3, "UART11_TXD"),
+ MA35_MUX(0x6, "LCM_DATA17")),
+ MA35_PIN(42, PC14, 0x94, 0x18,
+ MA35_MUX(0x0, "GPC14"),
+ MA35_MUX(0x2, "UART12_RXD"),
+ MA35_MUX(0x6, "LCM_DATA18")),
+ MA35_PIN(43, PC15, 0x94, 0x1c,
+ MA35_MUX(0x0, "GPC15"),
+ MA35_MUX(0x2, "UART12_TXD"),
+ MA35_MUX(0x6, "LCM_DATA19"),
+ MA35_MUX(0x7, "LCM_MPU_TE"),
+ MA35_MUX(0x8, "LCM_MPU_VSYNC")),
+ MA35_PIN(44, PD0, 0x98, 0x0,
+ MA35_MUX(0x0, "GPD0"),
+ MA35_MUX(0x2, "UART3_nCTS"),
+ MA35_MUX(0x3, "UART4_RXD"),
+ MA35_MUX(0x5, "QSPI0_SS0")),
+ MA35_PIN(45, PD1, 0x98, 0x4,
+ MA35_MUX(0x0, "GPD1"),
+ MA35_MUX(0x2, "UART3_nRTS"),
+ MA35_MUX(0x3, "UART4_TXD"),
+ MA35_MUX(0x5, "QSPI0_CLK")),
+ MA35_PIN(46, PD2, 0x98, 0x8,
+ MA35_MUX(0x0, "GPD2"),
+ MA35_MUX(0x2, "UART3_RXD"),
+ MA35_MUX(0x5, "QSPI0_MOSI0")),
+ MA35_PIN(47, PD3, 0x98, 0xc,
+ MA35_MUX(0x0, "GPD3"),
+ MA35_MUX(0x2, "UART3_TXD"),
+ MA35_MUX(0x5, "QSPI0_MISO0")),
+ MA35_PIN(48, PD4, 0x98, 0x10,
+ MA35_MUX(0x0, "GPD4"),
+ MA35_MUX(0x2, "UART1_nCTS"),
+ MA35_MUX(0x3, "UART2_RXD"),
+ MA35_MUX(0x4, "I2C2_SDA"),
+ MA35_MUX(0x5, "QSPI0_MOSI1")),
+ MA35_PIN(49, PD5, 0x98, 0x14,
+ MA35_MUX(0x0, "GPD5"),
+ MA35_MUX(0x2, "UART1_nRTS"),
+ MA35_MUX(0x3, "UART2_TXD"),
+ MA35_MUX(0x4, "I2C2_SCL"),
+ MA35_MUX(0x5, "QSPI0_MISO1")),
+ MA35_PIN(50, PD6, 0x98, 0x18,
+ MA35_MUX(0x0, "GPD6"),
+ MA35_MUX(0x1, "EPWM0_SYNC_IN"),
+ MA35_MUX(0x2, "UART1_RXD"),
+ MA35_MUX(0x5, "QSPI1_MOSI1"),
+ MA35_MUX(0x6, "I2C0_SDA"),
+ MA35_MUX(0x7, "I2S0_MCLK"),
+ MA35_MUX(0x8, "EPWM0_CH0"),
+ MA35_MUX(0x9, "EBI_AD5"),
+ MA35_MUX(0xa, "SPI3_SS1"),
+ MA35_MUX(0xb, "TRACE_CLK")),
+ MA35_PIN(51, PD7, 0x98, 0x1c,
+ MA35_MUX(0x0, "GPD7"),
+ MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
+ MA35_MUX(0x2, "UART1_TXD"),
+ MA35_MUX(0x5, "QSPI1_MISO1"),
+ MA35_MUX(0x6, "I2C0_SCL"),
+ MA35_MUX(0x7, "I2S1_MCLK"),
+ MA35_MUX(0x8, "EPWM0_CH1"),
+ MA35_MUX(0x9, "EBI_AD6"),
+ MA35_MUX(0xa, "SC1_nCD"),
+ MA35_MUX(0xb, "EADC0_ST")),
+ MA35_PIN(52, PD8, 0x9c, 0x0,
+ MA35_MUX(0x0, "GPD8"),
+ MA35_MUX(0x1, "EPWM0_BRAKE0"),
+ MA35_MUX(0x2, "UART16_nCTS"),
+ MA35_MUX(0x3, "UART15_RXD"),
+ MA35_MUX(0x5, "QSPI1_SS0"),
+ MA35_MUX(0x7, "I2S1_LRCK"),
+ MA35_MUX(0x8, "EPWM0_CH2"),
+ MA35_MUX(0x9, "EBI_AD7"),
+ MA35_MUX(0xa, "SC1_CLK"),
+ MA35_MUX(0xb, "TM0")),
+ MA35_PIN(53, PD9, 0x9c, 0x4,
+ MA35_MUX(0x0, "GPD9"),
+ MA35_MUX(0x1, "EPWM0_BRAKE1"),
+ MA35_MUX(0x2, "UART16_nRTS"),
+ MA35_MUX(0x3, "UART15_TXD"),
+ MA35_MUX(0x5, "QSPI1_CLK"),
+ MA35_MUX(0x7, "I2S1_BCLK"),
+ MA35_MUX(0x8, "EPWM0_CH3"),
+ MA35_MUX(0x9, "EBI_AD8"),
+ MA35_MUX(0xa, "SC1_DAT"),
+ MA35_MUX(0xb, "TM0_EXT")),
+ MA35_PIN(54, PD10, 0x9c, 0x8,
+ MA35_MUX(0x0, "GPD10"),
+ MA35_MUX(0x1, "EPWM1_BRAKE0"),
+ MA35_MUX(0x2, "UART16_RXD"),
+ MA35_MUX(0x5, "QSPI1_MOSI0"),
+ MA35_MUX(0x7, "I2S1_DI"),
+ MA35_MUX(0x8, "EPWM0_CH4"),
+ MA35_MUX(0x9, "EBI_AD9"),
+ MA35_MUX(0xa, "SC1_RST"),
+ MA35_MUX(0xb, "TM2")),
+ MA35_PIN(55, PD11, 0x9c, 0xc,
+ MA35_MUX(0x0, "GPD11"),
+ MA35_MUX(0x1, "EPWM1_BRAKE1"),
+ MA35_MUX(0x2, "UART16_TXD"),
+ MA35_MUX(0x5, "QSPI1_MISO0"),
+ MA35_MUX(0x7, "I2S1_DO"),
+ MA35_MUX(0x8, "EPWM0_CH5"),
+ MA35_MUX(0x9, "EBI_AD10"),
+ MA35_MUX(0xa, "SC1_PWR"),
+ MA35_MUX(0xb, "TM2_EXT")),
+ MA35_PIN(56, PD12, 0x9c, 0x10,
+ MA35_MUX(0x0, "GPD12"),
+ MA35_MUX(0x1, "EPWM0_BRAKE0"),
+ MA35_MUX(0x2, "UART11_TXD"),
+ MA35_MUX(0x3, "UART10_RXD"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x6, "TRACE_DATA0"),
+ MA35_MUX(0x7, "EBI_nCS1"),
+ MA35_MUX(0x8, "EBI_AD4"),
+ MA35_MUX(0x9, "QEI0_INDEX"),
+ MA35_MUX(0xb, "TM5"),
+ MA35_MUX(0xc, "I2S1_LRCK"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(57, PD13, 0x9c, 0x14,
+ MA35_MUX(0x0, "GPD13"),
+ MA35_MUX(0x1, "EPWM0_BRAKE1"),
+ MA35_MUX(0x2, "UART11_RXD"),
+ MA35_MUX(0x3, "UART10_TXD"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x6, "TRACE_DATA1"),
+ MA35_MUX(0x7, "EBI_nCS2"),
+ MA35_MUX(0x8, "EBI_AD5"),
+ MA35_MUX(0x9, "ECAP0_IC0"),
+ MA35_MUX(0xb, "TM5_EXT"),
+ MA35_MUX(0xc, "I2S1_BCLK")),
+ MA35_PIN(58, PD14, 0x9c, 0x18,
+ MA35_MUX(0x0, "GPD14"),
+ MA35_MUX(0x1, "EPWM0_SYNC_IN"),
+ MA35_MUX(0x2, "UART11_nCTS"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x6, "TRACE_DATA2"),
+ MA35_MUX(0x7, "EBI_MCLK"),
+ MA35_MUX(0x8, "EBI_AD6"),
+ MA35_MUX(0x9, "ECAP0_IC1"),
+ MA35_MUX(0xb, "TM6"),
+ MA35_MUX(0xc, "I2S1_DI"),
+ MA35_MUX(0xd, "INT3")),
+ MA35_PIN(59, PD15, 0x9c, 0x1c,
+ MA35_MUX(0x0, "GPD15"),
+ MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
+ MA35_MUX(0x2, "UART11_nRTS"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x6, "TRACE_DATA3"),
+ MA35_MUX(0x7, "EBI_ALE"),
+ MA35_MUX(0x8, "EBI_AD7"),
+ MA35_MUX(0x9, "ECAP0_IC2"),
+ MA35_MUX(0xb, "TM6_EXT"),
+ MA35_MUX(0xc, "I2S1_DO")),
+ MA35_PIN(60, PE0, 0xa0, 0x0,
+ MA35_MUX(0x0, "GPE0"),
+ MA35_MUX(0x2, "UART9_nCTS"),
+ MA35_MUX(0x3, "UART8_RXD"),
+ MA35_MUX(0x7, "CCAP1_DATA0"),
+ MA35_MUX(0x8, "RGMII0_MDC"),
+ MA35_MUX(0x9, "RMII0_MDC")),
+ MA35_PIN(61, PE1, 0xa0, 0x4,
+ MA35_MUX(0x0, "GPE1"),
+ MA35_MUX(0x2, "UART9_nRTS"),
+ MA35_MUX(0x3, "UART8_TXD"),
+ MA35_MUX(0x7, "CCAP1_DATA1"),
+ MA35_MUX(0x8, "RGMII0_MDIO"),
+ MA35_MUX(0x9, "RMII0_MDIO")),
+ MA35_PIN(62, PE2, 0xa0, 0x8,
+ MA35_MUX(0x0, "GPE2"),
+ MA35_MUX(0x2, "UART9_RXD"),
+ MA35_MUX(0x7, "CCAP1_DATA2"),
+ MA35_MUX(0x8, "RGMII0_TXCTL"),
+ MA35_MUX(0x9, "RMII0_TXEN")),
+ MA35_PIN(63, PE3, 0xa0, 0xc,
+ MA35_MUX(0x0, "GPE3"),
+ MA35_MUX(0x2, "UART9_TXD"),
+ MA35_MUX(0x7, "CCAP1_DATA3"),
+ MA35_MUX(0x8, "RGMII0_TXD0"),
+ MA35_MUX(0x9, "RMII0_TXD0")),
+ MA35_PIN(64, PE4, 0xa0, 0x10,
+ MA35_MUX(0x0, "GPE4"),
+ MA35_MUX(0x2, "UART4_nCTS"),
+ MA35_MUX(0x3, "UART3_RXD"),
+ MA35_MUX(0x7, "CCAP1_DATA4"),
+ MA35_MUX(0x8, "RGMII0_TXD1"),
+ MA35_MUX(0x9, "RMII0_TXD1")),
+ MA35_PIN(65, PE5, 0xa0, 0x14,
+ MA35_MUX(0x0, "GPE5"),
+ MA35_MUX(0x2, "UART4_nRTS"),
+ MA35_MUX(0x3, "UART3_TXD"),
+ MA35_MUX(0x7, "CCAP1_DATA5"),
+ MA35_MUX(0x8, "RGMII0_RXCLK"),
+ MA35_MUX(0x9, "RMII0_REFCLK")),
+ MA35_PIN(66, PE6, 0xa0, 0x18,
+ MA35_MUX(0x0, "GPE6"),
+ MA35_MUX(0x2, "UART4_RXD"),
+ MA35_MUX(0x7, "CCAP1_DATA6"),
+ MA35_MUX(0x8, "RGMII0_RXCTL"),
+ MA35_MUX(0x9, "RMII0_CRSDV")),
+ MA35_PIN(67, PE7, 0xa0, 0x1c,
+ MA35_MUX(0x0, "GPE7"),
+ MA35_MUX(0x2, "UART4_TXD"),
+ MA35_MUX(0x7, "CCAP1_DATA7"),
+ MA35_MUX(0x8, "RGMII0_RXD0"),
+ MA35_MUX(0x9, "RMII0_RXD0")),
+ MA35_PIN(68, PE8, 0xa4, 0x0,
+ MA35_MUX(0x0, "GPE8"),
+ MA35_MUX(0x2, "UART13_nCTS"),
+ MA35_MUX(0x3, "UART12_RXD"),
+ MA35_MUX(0x7, "CCAP1_SCLK"),
+ MA35_MUX(0x8, "RGMII0_RXD1"),
+ MA35_MUX(0x9, "RMII0_RXD1")),
+ MA35_PIN(69, PE9, 0xa4, 0x4,
+ MA35_MUX(0x0, "GPE9"),
+ MA35_MUX(0x2, "UART13_nRTS"),
+ MA35_MUX(0x3, "UART12_TXD"),
+ MA35_MUX(0x7, "CCAP1_PIXCLK"),
+ MA35_MUX(0x8, "RGMII0_RXD2"),
+ MA35_MUX(0x9, "RMII0_RXERR")),
+ MA35_PIN(70, PE10, 0xa4, 0x8,
+ MA35_MUX(0x0, "GPE10"),
+ MA35_MUX(0x2, "UART15_nCTS"),
+ MA35_MUX(0x3, "UART14_RXD"),
+ MA35_MUX(0x5, "SPI1_SS0"),
+ MA35_MUX(0x7, "CCAP1_HSYNC"),
+ MA35_MUX(0x8, "RGMII0_RXD3")),
+ MA35_PIN(71, PE11, 0xa4, 0xc,
+ MA35_MUX(0x0, "GPE11"),
+ MA35_MUX(0x2, "UART15_nRTS"),
+ MA35_MUX(0x3, "UART14_TXD"),
+ MA35_MUX(0x5, "SPI1_CLK"),
+ MA35_MUX(0x7, "CCAP1_VSYNC"),
+ MA35_MUX(0x8, "RGMII0_TXCLK")),
+ MA35_PIN(72, PE12, 0xa4, 0x10,
+ MA35_MUX(0x0, "GPE12"),
+ MA35_MUX(0x2, "UART15_RXD"),
+ MA35_MUX(0x5, "SPI1_MOSI"),
+ MA35_MUX(0x7, "CCAP1_DATA8"),
+ MA35_MUX(0x8, "RGMII0_TXD2")),
+ MA35_PIN(73, PE13, 0xa4, 0x14,
+ MA35_MUX(0x0, "GPE13"),
+ MA35_MUX(0x2, "UART15_TXD"),
+ MA35_MUX(0x5, "SPI1_MISO"),
+ MA35_MUX(0x7, "CCAP1_DATA9"),
+ MA35_MUX(0x8, "RGMII0_TXD3")),
+ MA35_PIN(74, PE14, 0xa4, 0x18,
+ MA35_MUX(0x0, "GPE14"),
+ MA35_MUX(0x1, "UART0_TXD")),
+ MA35_PIN(75, PE15, 0xa4, 0x1c,
+ MA35_MUX(0x0, "GPE15"),
+ MA35_MUX(0x1, "UART0_RXD")),
+ MA35_PIN(76, PF0, 0xa8, 0x0,
+ MA35_MUX(0x0, "GPF0"),
+ MA35_MUX(0x2, "UART2_nCTS"),
+ MA35_MUX(0x3, "UART1_RXD"),
+ MA35_MUX(0x6, "RGMII0_RXD3"),
+ MA35_MUX(0x8, "RGMII1_MDC"),
+ MA35_MUX(0x9, "RMII1_MDC"),
+ MA35_MUX(0xe, "KPI_COL0")),
+ MA35_PIN(77, PF1, 0xa8, 0x4,
+ MA35_MUX(0x0, "GPF1"),
+ MA35_MUX(0x2, "UART2_nRTS"),
+ MA35_MUX(0x3, "UART1_TXD"),
+ MA35_MUX(0x6, "RGMII0_TXCLK"),
+ MA35_MUX(0x8, "RGMII1_MDIO"),
+ MA35_MUX(0x9, "RMII1_MDIO"),
+ MA35_MUX(0xe, "KPI_COL1")),
+ MA35_PIN(78, PF2, 0xa8, 0x8,
+ MA35_MUX(0x0, "GPF2"),
+ MA35_MUX(0x2, "UART2_RXD"),
+ MA35_MUX(0x6, "RGMII0_TXD2"),
+ MA35_MUX(0x8, "RGMII1_TXCTL"),
+ MA35_MUX(0x9, "RMII1_TXEN"),
+ MA35_MUX(0xe, "KPI_COL2")),
+ MA35_PIN(79, PF3, 0xa8, 0xc,
+ MA35_MUX(0x0, "GPF3"),
+ MA35_MUX(0x2, "UART2_TXD"),
+ MA35_MUX(0x6, "RGMII0_TXD3"),
+ MA35_MUX(0x8, "RGMII1_TXD0"),
+ MA35_MUX(0x9, "RMII1_TXD0"),
+ MA35_MUX(0xe, "KPI_COL3")),
+ MA35_PIN(80, PF4, 0xa8, 0x10,
+ MA35_MUX(0x0, "GPF4"),
+ MA35_MUX(0x2, "UART11_nCTS"),
+ MA35_MUX(0x3, "UART10_RXD"),
+ MA35_MUX(0x4, "I2S0_LRCK"),
+ MA35_MUX(0x5, "SPI1_SS0"),
+ MA35_MUX(0x8, "RGMII1_TXD1"),
+ MA35_MUX(0x9, "RMII1_TXD1"),
+ MA35_MUX(0xd, "CAN2_RXD"),
+ MA35_MUX(0xe, "KPI_ROW0")),
+ MA35_PIN(81, PF5, 0xa8, 0x14,
+ MA35_MUX(0x0, "GPF5"),
+ MA35_MUX(0x2, "UART11_nRTS"),
+ MA35_MUX(0x3, "UART10_TXD"),
+ MA35_MUX(0x4, "I2S0_BCLK"),
+ MA35_MUX(0x5, "SPI1_CLK"),
+ MA35_MUX(0x8, "RGMII1_RXCLK"),
+ MA35_MUX(0x9, "RMII1_REFCLK"),
+ MA35_MUX(0xd, "CAN2_TXD"),
+ MA35_MUX(0xe, "KPI_ROW1")),
+ MA35_PIN(82, PF6, 0xa8, 0x18,
+ MA35_MUX(0x0, "GPF6"),
+ MA35_MUX(0x2, "UART11_RXD"),
+ MA35_MUX(0x4, "I2S0_DI"),
+ MA35_MUX(0x5, "SPI1_MOSI"),
+ MA35_MUX(0x8, "RGMII1_RXCTL"),
+ MA35_MUX(0x9, "RMII1_CRSDV"),
+ MA35_MUX(0xa, "I2C4_SDA"),
+ MA35_MUX(0xd, "SC0_CLK"),
+ MA35_MUX(0xe, "KPI_ROW2")),
+ MA35_PIN(83, PF7, 0xa8, 0x1c,
+ MA35_MUX(0x0, "GPF7"),
+ MA35_MUX(0x2, "UART11_TXD"),
+ MA35_MUX(0x4, "I2S0_DO"),
+ MA35_MUX(0x5, "SPI1_MISO"),
+ MA35_MUX(0x8, "RGMII1_RXD0"),
+ MA35_MUX(0x9, "RMII1_RXD0"),
+ MA35_MUX(0xa, "I2C4_SCL"),
+ MA35_MUX(0xd, "SC0_DAT"),
+ MA35_MUX(0xe, "KPI_ROW3")),
+ MA35_PIN(84, PF8, 0xac, 0x0,
+ MA35_MUX(0x0, "GPF8"),
+ MA35_MUX(0x2, "UART13_RXD"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x5, "SPI0_SS0"),
+ MA35_MUX(0x8, "RGMII1_RXD1"),
+ MA35_MUX(0x9, "RMII1_RXD1"),
+ MA35_MUX(0xd, "SC0_RST"),
+ MA35_MUX(0xe, "KPI_COL4")),
+ MA35_PIN(85, PF9, 0xac, 0x4,
+ MA35_MUX(0x0, "GPF9"),
+ MA35_MUX(0x2, "UART13_TXD"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x5, "SPI0_SS1"),
+ MA35_MUX(0x8, "RGMII1_RXD2"),
+ MA35_MUX(0x9, "RMII1_RXERR"),
+ MA35_MUX(0xd, "SC0_PWR"),
+ MA35_MUX(0xe, "KPI_COL5")),
+ MA35_PIN(86, PF10, 0xac, 0x8,
+ MA35_MUX(0x0, "GPF10"),
+ MA35_MUX(0x2, "UART13_nCTS"),
+ MA35_MUX(0x5, "I2S0_LRCK"),
+ MA35_MUX(0x6, "SPI1_SS0"),
+ MA35_MUX(0x8, "RGMII1_RXD3"),
+ MA35_MUX(0x9, "SC0_CLK"),
+ MA35_MUX(0xe, "KPI_COL6")),
+ MA35_PIN(87, PF11, 0xac, 0xc,
+ MA35_MUX(0x0, "GPF11"),
+ MA35_MUX(0x2, "UART13_nRTS"),
+ MA35_MUX(0x5, "I2S0_BCLK"),
+ MA35_MUX(0x6, "SPI1_CLK"),
+ MA35_MUX(0x8, "RGMII1_TXCLK"),
+ MA35_MUX(0x9, "SC0_DAT"),
+ MA35_MUX(0xe, "KPI_COL7")),
+ MA35_PIN(88, PF12, 0xac, 0x10,
+ MA35_MUX(0x0, "GPF12"),
+ MA35_MUX(0x5, "I2S0_DI"),
+ MA35_MUX(0x6, "SPI1_MOSI"),
+ MA35_MUX(0x8, "RGMII1_TXD2"),
+ MA35_MUX(0x9, "SC0_RST"),
+ MA35_MUX(0xe, "KPI_ROW4")),
+ MA35_PIN(89, PF13, 0xac, 0x14,
+ MA35_MUX(0x0, "GPF13"),
+ MA35_MUX(0x5, "I2S0_DO"),
+ MA35_MUX(0x6, "SPI1_MISO"),
+ MA35_MUX(0x8, "RGMII1_TXD3"),
+ MA35_MUX(0x9, "SC0_PWR"),
+ MA35_MUX(0xe, "KPI_ROW5")),
+ MA35_PIN(90, PF14, 0xac, 0x18,
+ MA35_MUX(0x0, "GPF14"),
+ MA35_MUX(0x1, "EPWM2_BRAKE0"),
+ MA35_MUX(0x2, "EADC0_ST"),
+ MA35_MUX(0x3, "RGMII1_PPS"),
+ MA35_MUX(0x4, "RMII1_PPS"),
+ MA35_MUX(0x5, "SPI0_I2SMCLK"),
+ MA35_MUX(0x6, "SPI1_I2SMCLK"),
+ MA35_MUX(0x7, "CCAP1_SFIELD"),
+ MA35_MUX(0x8, "RGMII0_PPS"),
+ MA35_MUX(0x9, "RMII0_PPS"),
+ MA35_MUX(0xb, "TM0"),
+ MA35_MUX(0xc, "INT0"),
+ MA35_MUX(0xd, "SPI1_SS1"),
+ MA35_MUX(0xe, "QEI2_INDEX"),
+ MA35_MUX(0xf, "I2S0_MCLK")),
+ MA35_PIN(91, PF15, 0xac, 0x1c,
+ MA35_MUX(0x0, "GPF15"),
+ MA35_MUX(0x1, "HSUSB0_VBUSVLD")),
+ MA35_PIN(92, PG0, 0xb0, 0x0,
+ MA35_MUX(0x0, "GPG0"),
+ MA35_MUX(0x1, "EPWM0_CH0"),
+ MA35_MUX(0x2, "UART7_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "SPI0_SS0"),
+ MA35_MUX(0x6, "EADC0_ST"),
+ MA35_MUX(0x7, "EBI_AD15"),
+ MA35_MUX(0x9, "I2S1_MCLK"),
+ MA35_MUX(0xa, "QEI0_INDEX"),
+ MA35_MUX(0xb, "TM1"),
+ MA35_MUX(0xc, "CLKO"),
+ MA35_MUX(0xd, "INT0"),
+ MA35_MUX(0xf, "EBI_ADR15")),
+ MA35_PIN(93, PG1, 0xb0, 0x4,
+ MA35_MUX(0x0, "GPG1"),
+ MA35_MUX(0x1, "EPWM0_CH3"),
+ MA35_MUX(0x2, "UART9_nRTS"),
+ MA35_MUX(0x3, "UART6_TXD"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x5, "CAN2_TXD"),
+ MA35_MUX(0x7, "EBI_nCS0"),
+ MA35_MUX(0x9, "QEI0_B"),
+ MA35_MUX(0xb, "TM1_EXT"),
+ MA35_MUX(0xe, "RGMII1_PPS"),
+ MA35_MUX(0xf, "RMII1_PPS")),
+ MA35_PIN(94, PG2, 0xb0, 0x8,
+ MA35_MUX(0x0, "GPG2"),
+ MA35_MUX(0x1, "EPWM0_CH4"),
+ MA35_MUX(0x2, "UART9_RXD"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x5, "SPI0_SS1"),
+ MA35_MUX(0x7, "EBI_ADR16"),
+ MA35_MUX(0x8, "EBI_nCS2"),
+ MA35_MUX(0xa, "QEI0_A"),
+ MA35_MUX(0xb, "TM3"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(95, PG3, 0xb0, 0xc,
+ MA35_MUX(0x0, "GPG3"),
+ MA35_MUX(0x1, "EPWM0_CH5"),
+ MA35_MUX(0x2, "UART9_TXD"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x5, "SPI0_I2SMCLK"),
+ MA35_MUX(0x7, "EBI_ADR17"),
+ MA35_MUX(0x8, "EBI_nCS1"),
+ MA35_MUX(0x9, "EBI_MCLK"),
+ MA35_MUX(0xa, "QEI0_B"),
+ MA35_MUX(0xb, "TM3_EXT"),
+ MA35_MUX(0xc, "I2S1_MCLK")),
+ MA35_PIN(96, PG4, 0xb0, 0x10,
+ MA35_MUX(0x0, "GPG4"),
+ MA35_MUX(0x1, "EPWM1_CH0"),
+ MA35_MUX(0x2, "UART5_nCTS"),
+ MA35_MUX(0x3, "UART6_RXD"),
+ MA35_MUX(0x5, "SPI3_SS0"),
+ MA35_MUX(0x6, "QEI1_INDEX"),
+ MA35_MUX(0x7, "EBI_ADR18"),
+ MA35_MUX(0x8, "EBI_nCS0"),
+ MA35_MUX(0x9, "I2S1_DO"),
+ MA35_MUX(0xa, "SC1_CLK"),
+ MA35_MUX(0xb, "TM4"),
+ MA35_MUX(0xd, "INT2"),
+ MA35_MUX(0xe, "ECAP1_IC2")),
+ MA35_PIN(97, PG5, 0xb0, 0x14,
+ MA35_MUX(0x0, "GPG5"),
+ MA35_MUX(0x1, "EPWM1_CH1"),
+ MA35_MUX(0x2, "UART5_nRTS"),
+ MA35_MUX(0x3, "UART6_TXD"),
+ MA35_MUX(0x5, "SPI3_CLK"),
+ MA35_MUX(0x6, "ECAP0_IC0"),
+ MA35_MUX(0x7, "EBI_ADR19"),
+ MA35_MUX(0x8, "EBI_ALE"),
+ MA35_MUX(0x9, "I2S1_DI"),
+ MA35_MUX(0xa, "SC1_DAT"),
+ MA35_MUX(0xb, "TM4_EXT")),
+ MA35_PIN(98, PG6, 0xb0, 0x18,
+ MA35_MUX(0x0, "GPG6"),
+ MA35_MUX(0x1, "EPWM1_CH2"),
+ MA35_MUX(0x2, "UART5_RXD"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x5, "SPI3_MOSI"),
+ MA35_MUX(0x6, "ECAP0_IC1"),
+ MA35_MUX(0x7, "EBI_nRD"),
+ MA35_MUX(0x9, "I2S1_BCLK"),
+ MA35_MUX(0xa, "SC1_RST"),
+ MA35_MUX(0xb, "TM7"),
+ MA35_MUX(0xd, "INT3")),
+ MA35_PIN(99, PG7, 0xb0, 0x1c,
+ MA35_MUX(0x0, "GPG7"),
+ MA35_MUX(0x1, "EPWM1_CH3"),
+ MA35_MUX(0x2, "UART5_TXD"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x5, "SPI3_MISO"),
+ MA35_MUX(0x6, "ECAP0_IC2"),
+ MA35_MUX(0x7, "EBI_nWR"),
+ MA35_MUX(0x9, "I2S1_LRCK"),
+ MA35_MUX(0xa, "SC1_PWR"),
+ MA35_MUX(0xb, "TM7_EXT")),
+ MA35_PIN(100, PG8, 0xb4, 0x0,
+ MA35_MUX(0x0, "GPG8"),
+ MA35_MUX(0x1, "EPWM1_CH4"),
+ MA35_MUX(0x2, "UART12_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x5, "SPI2_SS0"),
+ MA35_MUX(0x6, "LCM_VSYNC"),
+ MA35_MUX(0x7, "I2C3_SDA"),
+ MA35_MUX(0xc, "EBI_AD7"),
+ MA35_MUX(0xd, "EBI_nCS0")),
+ MA35_PIN(101, PG9, 0xb4, 0x4,
+ MA35_MUX(0x0, "GPG9"),
+ MA35_MUX(0x1, "EPWM1_CH5"),
+ MA35_MUX(0x2, "UART12_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "SPI2_CLK"),
+ MA35_MUX(0x6, "LCM_HSYNC"),
+ MA35_MUX(0x7, "I2C3_SCL"),
+ MA35_MUX(0xc, "EBI_AD8"),
+ MA35_MUX(0xd, "EBI_nCS1")),
+ MA35_PIN(102, PG10, 0xb4, 0x8,
+ MA35_MUX(0x0, "GPG10"),
+ MA35_MUX(0x2, "UART12_nRTS"),
+ MA35_MUX(0x3, "UART13_TXD"),
+ MA35_MUX(0x5, "SPI2_MOSI"),
+ MA35_MUX(0x6, "LCM_CLK"),
+ MA35_MUX(0xc, "EBI_AD9"),
+ MA35_MUX(0xd, "EBI_nWRH")),
+ MA35_PIN(103, PG11, 0xb4, 0xc,
+ MA35_MUX(0x0, "GPG11"),
+ MA35_MUX(0x3, "JTAG_TDO"),
+ MA35_MUX(0x5, "I2S0_MCLK"),
+ MA35_MUX(0x6, "NAND_RDY1"),
+ MA35_MUX(0x7, "EBI_nWRH"),
+ MA35_MUX(0x8, "EBI_nCS1"),
+ MA35_MUX(0xa, "EBI_AD0")),
+ MA35_PIN(104, PG12, 0xb4, 0x10,
+ MA35_MUX(0x0, "GPG12"),
+ MA35_MUX(0x3, "JTAG_TCK/SW_CLK"),
+ MA35_MUX(0x5, "I2S0_LRCK"),
+ MA35_MUX(0x7, "EBI_nWRL"),
+ MA35_MUX(0xa, "EBI_AD1")),
+ MA35_PIN(105, PG13, 0xb4, 0x14,
+ MA35_MUX(0x0, "GPG13"),
+ MA35_MUX(0x3, "JTAG_TMS/SW_DIO"),
+ MA35_MUX(0x5, "I2S0_BCLK"),
+ MA35_MUX(0x7, "EBI_MCLK"),
+ MA35_MUX(0xa, "EBI_AD2")),
+ MA35_PIN(106, PG14, 0xb4, 0x18,
+ MA35_MUX(0x0, "GPG14"),
+ MA35_MUX(0x3, "JTAG_TDI"),
+ MA35_MUX(0x5, "I2S0_DI"),
+ MA35_MUX(0x6, "NAND_nCS1"),
+ MA35_MUX(0x7, "EBI_ALE"),
+ MA35_MUX(0xa, "EBI_AD3")),
+ MA35_PIN(107, PG15, 0xb4, 0x1c,
+ MA35_MUX(0x0, "GPG15"),
+ MA35_MUX(0x3, "JTAG_nTRST"),
+ MA35_MUX(0x5, "I2S0_DO"),
+ MA35_MUX(0x7, "EBI_nCS0"),
+ MA35_MUX(0xa, "EBI_AD4")),
+ MA35_PIN(108, PH0, 0xb8, 0x0,
+ MA35_MUX(0x0, "GPH0"),
+ MA35_MUX(0x2, "UART8_nCTS"),
+ MA35_MUX(0x3, "UART7_RXD"),
+ MA35_MUX(0x6, "LCM_DATA8")),
+ MA35_PIN(109, PH1, 0xb8, 0x4,
+ MA35_MUX(0x0, "GPH1"),
+ MA35_MUX(0x2, "UART8_nRTS"),
+ MA35_MUX(0x3, "UART7_TXD"),
+ MA35_MUX(0x6, "LCM_DATA9")),
+ MA35_PIN(110, PH2, 0xb8, 0x8,
+ MA35_MUX(0x0, "GPH2"),
+ MA35_MUX(0x2, "UART8_RXD"),
+ MA35_MUX(0x6, "LCM_DATA10")),
+ MA35_PIN(111, PH3, 0xb8, 0xc,
+ MA35_MUX(0x0, "GPH3"),
+ MA35_MUX(0x2, "UART8_TXD"),
+ MA35_MUX(0x6, "LCM_DATA11")),
+ MA35_PIN(112, PH4, 0xb8, 0x10,
+ MA35_MUX(0x0, "GPH4"),
+ MA35_MUX(0x2, "UART10_nCTS"),
+ MA35_MUX(0x3, "UART9_RXD"),
+ MA35_MUX(0x6, "LCM_DATA12")),
+ MA35_PIN(113, PH5, 0xb8, 0x14,
+ MA35_MUX(0x0, "GPH5"),
+ MA35_MUX(0x2, "UART10_nRTS"),
+ MA35_MUX(0x3, "UART9_TXD"),
+ MA35_MUX(0x6, "LCM_DATA13")),
+ MA35_PIN(114, PH6, 0xb8, 0x18,
+ MA35_MUX(0x0, "GPH6"),
+ MA35_MUX(0x2, "UART10_RXD"),
+ MA35_MUX(0x6, "LCM_DATA14")),
+ MA35_PIN(115, PH7, 0xb8, 0x1c,
+ MA35_MUX(0x0, "GPH7"),
+ MA35_MUX(0x2, "UART10_TXD"),
+ MA35_MUX(0x6, "LCM_DATA15")),
+ MA35_PIN(116, PH8, 0xbc, 0x0,
+ MA35_MUX(0x0, "GPH8"),
+ MA35_MUX(0x6, "TAMPER0")),
+ MA35_PIN(117, PH9, 0xbc, 0x4,
+ MA35_MUX(0x0, "GPH9"),
+ MA35_MUX(0x4, "CLK_32KOUT"),
+ MA35_MUX(0x6, "TAMPER1")),
+ MA35_PIN(118, PH12, 0xbc, 0x10,
+ MA35_MUX(0x0, "GPH12"),
+ MA35_MUX(0x2, "UART14_nCTS"),
+ MA35_MUX(0x3, "UART13_RXD"),
+ MA35_MUX(0x6, "LCM_DATA20")),
+ MA35_PIN(119, PH13, 0xbc, 0x14,
+ MA35_MUX(0x0, "GPH13"),
+ MA35_MUX(0x2, "UART14_nRTS"),
+ MA35_MUX(0x3, "UART13_TXD"),
+ MA35_MUX(0x6, "LCM_DATA21")),
+ MA35_PIN(120, PH14, 0xbc, 0x18,
+ MA35_MUX(0x0, "GPH14"),
+ MA35_MUX(0x2, "UART14_RXD"),
+ MA35_MUX(0x6, "LCM_DATA22")),
+ MA35_PIN(121, PH15, 0xbc, 0x1c,
+ MA35_MUX(0x0, "GPH15"),
+ MA35_MUX(0x2, "UART14_TXD"),
+ MA35_MUX(0x6, "LCM_DATA23")),
+ MA35_PIN(122, PI0, 0xc0, 0x0,
+ MA35_MUX(0x0, "GPI0"),
+ MA35_MUX(0x1, "EPWM0_CH0"),
+ MA35_MUX(0x2, "UART12_nCTS"),
+ MA35_MUX(0x3, "UART11_RXD"),
+ MA35_MUX(0x4, "I2C2_SDA"),
+ MA35_MUX(0x5, "SPI3_SS0"),
+ MA35_MUX(0x7, "SC0_nCD"),
+ MA35_MUX(0x8, "EBI_ADR0"),
+ MA35_MUX(0xb, "TM0"),
+ MA35_MUX(0xc, "ECAP1_IC0")),
+ MA35_PIN(123, PI1, 0xc0, 0x4,
+ MA35_MUX(0x0, "GPI1"),
+ MA35_MUX(0x1, "EPWM0_CH1"),
+ MA35_MUX(0x2, "UART12_nRTS"),
+ MA35_MUX(0x3, "UART11_TXD"),
+ MA35_MUX(0x4, "I2C2_SCL"),
+ MA35_MUX(0x5, "SPI3_CLK"),
+ MA35_MUX(0x7, "SC0_CLK"),
+ MA35_MUX(0x8, "EBI_ADR1"),
+ MA35_MUX(0xb, "TM0_EXT"),
+ MA35_MUX(0xc, "ECAP1_IC1")),
+ MA35_PIN(124, PI2, 0xc0, 0x8,
+ MA35_MUX(0x0, "GPI2"),
+ MA35_MUX(0x1, "EPWM0_CH2"),
+ MA35_MUX(0x2, "UART12_RXD"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x5, "SPI3_MOSI"),
+ MA35_MUX(0x7, "SC0_DAT"),
+ MA35_MUX(0x8, "EBI_ADR2"),
+ MA35_MUX(0xb, "TM1"),
+ MA35_MUX(0xc, "ECAP1_IC2")),
+ MA35_PIN(125, PI3, 0xc0, 0xc,
+ MA35_MUX(0x0, "GPI3"),
+ MA35_MUX(0x1, "EPWM0_CH3"),
+ MA35_MUX(0x2, "UART12_TXD"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x5, "SPI3_MISO"),
+ MA35_MUX(0x7, "SC0_RST"),
+ MA35_MUX(0x8, "EBI_ADR3"),
+ MA35_MUX(0xb, "TM1_EXT")),
+ MA35_PIN(126, PI4, 0xc0, 0x10,
+ MA35_MUX(0x0, "GPI4"),
+ MA35_MUX(0x1, "EPWM0_CH4"),
+ MA35_MUX(0x2, "UART14_nCTS"),
+ MA35_MUX(0x3, "UART13_RXD"),
+ MA35_MUX(0x4, "I2C3_SDA"),
+ MA35_MUX(0x5, "SPI2_SS1"),
+ MA35_MUX(0x6, "I2S1_LRCK"),
+ MA35_MUX(0x8, "EBI_ADR4"),
+ MA35_MUX(0xd, "INT0")),
+ MA35_PIN(127, PI5, 0xc0, 0x14,
+ MA35_MUX(0x0, "GPI5"),
+ MA35_MUX(0x1, "EPWM0_CH5"),
+ MA35_MUX(0x2, "UART14_nRTS"),
+ MA35_MUX(0x3, "UART13_TXD"),
+ MA35_MUX(0x4, "I2C3_SCL"),
+ MA35_MUX(0x6, "I2S1_BCLK"),
+ MA35_MUX(0x8, "EBI_ADR5"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(128, PI6, 0xc0, 0x18,
+ MA35_MUX(0x0, "GPI6"),
+ MA35_MUX(0x1, "EPWM0_BRAKE0"),
+ MA35_MUX(0x2, "UART14_RXD"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x6, "I2S1_DI"),
+ MA35_MUX(0x8, "EBI_ADR6"),
+ MA35_MUX(0xc, "QEI1_INDEX"),
+ MA35_MUX(0xd, "INT2")),
+ MA35_PIN(129, PI7, 0xc0, 0x1c,
+ MA35_MUX(0x0, "GPI7"),
+ MA35_MUX(0x1, "EPWM0_BRAKE1"),
+ MA35_MUX(0x2, "UART14_TXD"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x6, "I2S1_DO"),
+ MA35_MUX(0x8, "EBI_ADR7"),
+ MA35_MUX(0xc, "ECAP0_IC0"),
+ MA35_MUX(0xd, "INT3")),
+ MA35_PIN(130, PI8, 0xc4, 0x0,
+ MA35_MUX(0x0, "GPI8"),
+ MA35_MUX(0x2, "UART4_nCTS"),
+ MA35_MUX(0x3, "UART3_RXD"),
+ MA35_MUX(0x6, "LCM_DATA0"),
+ MA35_MUX(0xc, "EBI_AD11")),
+ MA35_PIN(131, PI9, 0xc4, 0x4,
+ MA35_MUX(0x0, "GPI9"),
+ MA35_MUX(0x2, "UART4_nRTS"),
+ MA35_MUX(0x3, "UART3_TXD"),
+ MA35_MUX(0x6, "LCM_DATA1"),
+ MA35_MUX(0xc, "EBI_AD12")),
+ MA35_PIN(132, PI10, 0xc4, 0x8,
+ MA35_MUX(0x0, "GPI10"),
+ MA35_MUX(0x2, "UART4_RXD"),
+ MA35_MUX(0x6, "LCM_DATA2"),
+ MA35_MUX(0xc, "EBI_AD13")),
+ MA35_PIN(133, PI11, 0xC4, 0xc,
+ MA35_MUX(0x0, "GPI11"),
+ MA35_MUX(0x2, "UART4_TXD"),
+ MA35_MUX(0x6, "LCM_DATA3"),
+ MA35_MUX(0xc, "EBI_AD14")),
+ MA35_PIN(134, PI12, 0xc4, 0x10,
+ MA35_MUX(0x0, "GPI12"),
+ MA35_MUX(0x2, "UART6_nCTS"),
+ MA35_MUX(0x3, "UART5_RXD"),
+ MA35_MUX(0x6, "LCM_DATA4")),
+ MA35_PIN(135, PI13, 0xc4, 0x14,
+ MA35_MUX(0x0, "GPI13"),
+ MA35_MUX(0x2, "UART6_nRTS"),
+ MA35_MUX(0x3, "UART5_TXD"),
+ MA35_MUX(0x6, "LCM_DATA5")),
+ MA35_PIN(136, PI14, 0xc4, 0x18,
+ MA35_MUX(0x0, "GPI14"),
+ MA35_MUX(0x2, "UART6_RXD"),
+ MA35_MUX(0x6, "LCM_DATA6")),
+ MA35_PIN(137, PI15, 0xc4, 0x1c,
+ MA35_MUX(0x0, "GPI15"),
+ MA35_MUX(0x2, "UART6_TXD"),
+ MA35_MUX(0x6, "LCM_DATA7")),
+ MA35_PIN(138, PJ0, 0xc8, 0x0,
+ MA35_MUX(0x0, "GPJ0"),
+ MA35_MUX(0x1, "EPWM1_BRAKE0"),
+ MA35_MUX(0x2, "UART8_nCTS"),
+ MA35_MUX(0x3, "UART7_RXD"),
+ MA35_MUX(0x4, "I2C2_SDA"),
+ MA35_MUX(0x5, "SPI2_SS0"),
+ MA35_MUX(0x6, "eMMC1_DAT4"),
+ MA35_MUX(0x7, "I2S0_LRCK"),
+ MA35_MUX(0x8, "SC0_CLK"),
+ MA35_MUX(0x9, "EBI_AD11"),
+ MA35_MUX(0xa, "EBI_ADR16"),
+ MA35_MUX(0xb, "EBI_nCS0"),
+ MA35_MUX(0xc, "EBI_AD7")),
+ MA35_PIN(139, PJ1, 0xc8, 0x4,
+ MA35_MUX(0x0, "GPJ1"),
+ MA35_MUX(0x1, "EPWM1_BRAKE1"),
+ MA35_MUX(0x2, "UART8_nRTS"),
+ MA35_MUX(0x3, "UART7_TXD"),
+ MA35_MUX(0x4, "I2C2_SCL"),
+ MA35_MUX(0x5, "SPI2_CLK"),
+ MA35_MUX(0x6, "eMMC1_DAT5"),
+ MA35_MUX(0x7, "I2S0_BCLK"),
+ MA35_MUX(0x8, "SC0_DAT"),
+ MA35_MUX(0x9, "EBI_AD12"),
+ MA35_MUX(0xa, "EBI_ADR17"),
+ MA35_MUX(0xb, "EBI_nCS1"),
+ MA35_MUX(0xc, "EBI_AD8")),
+ MA35_PIN(140, PJ2, 0xc8, 0x8,
+ MA35_MUX(0x0, "GPJ2"),
+ MA35_MUX(0x1, "EPWM1_CH4"),
+ MA35_MUX(0x2, "UART8_RXD"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x5, "SPI2_MOSI"),
+ MA35_MUX(0x6, "eMMC1_DAT6"),
+ MA35_MUX(0x7, "I2S0_DI"),
+ MA35_MUX(0x8, "SC0_RST"),
+ MA35_MUX(0x9, "EBI_AD13"),
+ MA35_MUX(0xa, "EBI_ADR18"),
+ MA35_MUX(0xb, "EBI_nWRH"),
+ MA35_MUX(0xc, "EBI_AD9")),
+ MA35_PIN(141, PJ3, 0xc8, 0xc,
+ MA35_MUX(0x0, "GPJ3"),
+ MA35_MUX(0x1, "EPWM1_CH5"),
+ MA35_MUX(0x2, "UART8_TXD"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x5, "SPI2_MISO"),
+ MA35_MUX(0x6, "eMMC1_DAT7"),
+ MA35_MUX(0x7, "I2S0_DO"),
+ MA35_MUX(0x8, "SC0_PWR"),
+ MA35_MUX(0x9, "EBI_AD14"),
+ MA35_MUX(0xa, "EBI_ADR19"),
+ MA35_MUX(0xb, "EBI_nWRL"),
+ MA35_MUX(0xc, "EBI_AD10")),
+ MA35_PIN(142, PJ4, 0xc8, 0x10,
+ MA35_MUX(0x0, "GPJ4"),
+ MA35_MUX(0x4, "I2C3_SDA"),
+ MA35_MUX(0x6, "SD1_WP")),
+ MA35_PIN(143, PJ5, 0xc8, 0x14,
+ MA35_MUX(0x0, "GPJ5"),
+ MA35_MUX(0x4, "I2C3_SCL"),
+ MA35_MUX(0x6, "SD1_nCD")),
+ MA35_PIN(144, PJ6, 0xc8, 0x18,
+ MA35_MUX(0x0, "GPJ6"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x6, "SD1_CMD/eMMC1_CMD")),
+ MA35_PIN(145, PJ7, 0xc8, 0x1c,
+ MA35_MUX(0x0, "GPJ7"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x6, "SD1_CLK/eMMC1_CLK")),
+ MA35_PIN(146, PJ8, 0xcc, 0x0,
+ MA35_MUX(0x0, "GPJ8"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x6, "SD1_DAT0/eMMC1_DAT0")),
+ MA35_PIN(147, PJ9, 0xcc, 0x4,
+ MA35_MUX(0x0, "GPJ9"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x6, "SD1_DAT1/eMMC1_DAT1")),
+ MA35_PIN(148, PJ10, 0xcc, 0x8,
+ MA35_MUX(0x0, "GPJ10"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x6, "SD1_DAT2/eMMC1_DAT2")),
+ MA35_PIN(149, PJ11, 0xcc, 0xc,
+ MA35_MUX(0x0, "GPJ11"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x6, "SD1_DAT3/eMMC1_DAT3")),
+ MA35_PIN(150, PJ12, 0xcc, 0x10,
+ MA35_MUX(0x0, "GPJ12"),
+ MA35_MUX(0x1, "EPWM1_CH2"),
+ MA35_MUX(0x2, "UART2_nCTS"),
+ MA35_MUX(0x3, "UART1_RXD"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x5, "SPI3_SS0"),
+ MA35_MUX(0x7, "SC1_CLK"),
+ MA35_MUX(0x8, "EBI_ADR12"),
+ MA35_MUX(0xb, "TM2"),
+ MA35_MUX(0xc, "QEI0_INDEX")),
+ MA35_PIN(151, PJ13, 0xcc, 0x14,
+ MA35_MUX(0x0, "GPJ13"),
+ MA35_MUX(0x1, "EPWM1_CH3"),
+ MA35_MUX(0x2, "UART2_nRTS"),
+ MA35_MUX(0x3, "UART1_TXD"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x5, "SPI3_MOSI"),
+ MA35_MUX(0x7, "SC1_DAT"),
+ MA35_MUX(0x8, "EBI_ADR13"),
+ MA35_MUX(0xb, "TM2_EXT")),
+ MA35_PIN(152, PJ14, 0xcc, 0x18,
+ MA35_MUX(0x0, "GPJ14"),
+ MA35_MUX(0x1, "EPWM1_CH4"),
+ MA35_MUX(0x2, "UART2_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x5, "SPI3_MISO"),
+ MA35_MUX(0x7, "SC1_RST"),
+ MA35_MUX(0x8, "EBI_ADR14"),
+ MA35_MUX(0xb, "TM3")),
+ MA35_PIN(153, PJ15, 0xcc, 0x1c,
+ MA35_MUX(0x0, "GPJ15"),
+ MA35_MUX(0x1, "EPWM1_CH5"),
+ MA35_MUX(0x2, "UART2_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "SPI3_CLK"),
+ MA35_MUX(0x6, "EADC0_ST"),
+ MA35_MUX(0x7, "SC1_PWR"),
+ MA35_MUX(0x8, "EBI_ADR15"),
+ MA35_MUX(0xb, "TM3_EXT"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(154, PK0, 0xd0, 0x0,
+ MA35_MUX(0x0, "GPK0"),
+ MA35_MUX(0x1, "EPWM0_SYNC_IN"),
+ MA35_MUX(0x2, "UART16_nCTS"),
+ MA35_MUX(0x3, "UART15_RXD"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x6, "I2S1_MCLK"),
+ MA35_MUX(0x8, "EBI_ADR8"),
+ MA35_MUX(0xb, "TM7"),
+ MA35_MUX(0xc, "ECAP0_IC1")),
+ MA35_PIN(155, PK1, 0xd0, 0x4,
+ MA35_MUX(0x0, "GPK1"),
+ MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
+ MA35_MUX(0x2, "UART16_nRTS"),
+ MA35_MUX(0x3, "UART15_TXD"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x6, "EADC0_ST"),
+ MA35_MUX(0x8, "EBI_ADR9"),
+ MA35_MUX(0xb, "TM7_EXT"),
+ MA35_MUX(0xc, "ECAP0_IC2")),
+ MA35_PIN(156, PK2, 0xd0, 0x8,
+ MA35_MUX(0x0, "GPK2"),
+ MA35_MUX(0x1, "EPWM1_CH0"),
+ MA35_MUX(0x2, "UART16_RXD"),
+ MA35_MUX(0x3, "CAN2_RXD"),
+ MA35_MUX(0x5, "SPI3_I2SMCLK"),
+ MA35_MUX(0x7, "SC0_PWR"),
+ MA35_MUX(0x8, "EBI_ADR10"),
+ MA35_MUX(0xc, "QEI0_A")),
+ MA35_PIN(157, PK3, 0xd0, 0xc,
+ MA35_MUX(0x0, "GPK3"),
+ MA35_MUX(0x1, "EPWM1_CH1"),
+ MA35_MUX(0x2, "UART16_TXD"),
+ MA35_MUX(0x3, "CAN2_TXD"),
+ MA35_MUX(0x5, "SPI3_SS1"),
+ MA35_MUX(0x7, "SC1_nCD"),
+ MA35_MUX(0x8, "EBI_ADR11"),
+ MA35_MUX(0xc, "QEI0_B")),
+ MA35_PIN(158, PK4, 0xd0, 0x10,
+ MA35_MUX(0x0, "GPK4"),
+ MA35_MUX(0x2, "UART12_nCTS"),
+ MA35_MUX(0x3, "UART13_RXD"),
+ MA35_MUX(0x5, "SPI2_MISO"),
+ MA35_MUX(0x6, "LCM_DEN"),
+ MA35_MUX(0xc, "EBI_AD10"),
+ MA35_MUX(0xd, "EBI_nWRL")),
+ MA35_PIN(159, PK5, 0xd0, 0x14,
+ MA35_MUX(0x0, "GPK5"),
+ MA35_MUX(0x1, "EPWM1_CH1"),
+ MA35_MUX(0x2, "UART12_nRTS"),
+ MA35_MUX(0x3, "UART13_TXD"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x5, "SPI2_CLK"),
+ MA35_MUX(0x7, "I2S1_DI"),
+ MA35_MUX(0x8, "SC0_DAT"),
+ MA35_MUX(0x9, "EADC0_ST"),
+ MA35_MUX(0xb, "TM8_EXT"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(160, PK6, 0xd0, 0x18,
+ MA35_MUX(0x0, "GPK6"),
+ MA35_MUX(0x1, "EPWM1_CH2"),
+ MA35_MUX(0x2, "UART12_RXD"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x5, "SPI2_MOSI"),
+ MA35_MUX(0x7, "I2S1_BCLK"),
+ MA35_MUX(0x8, "SC0_RST"),
+ MA35_MUX(0xb, "TM6"),
+ MA35_MUX(0xd, "INT2")),
+ MA35_PIN(161, PK7, 0xd0, 0x1c,
+ MA35_MUX(0x0, "GPK7"),
+ MA35_MUX(0x1, "EPWM1_CH3"),
+ MA35_MUX(0x2, "UART12_TXD"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x5, "SPI2_MISO"),
+ MA35_MUX(0x7, "I2S1_LRCK"),
+ MA35_MUX(0x8, "SC0_PWR"),
+ MA35_MUX(0x9, "CLKO"),
+ MA35_MUX(0xb, "TM6_EXT"),
+ MA35_MUX(0xd, "INT3")),
+ MA35_PIN(162, PK8, 0xd4, 0x0,
+ MA35_MUX(0x0, "GPK8"),
+ MA35_MUX(0x1, "EPWM1_CH0"),
+ MA35_MUX(0x4, "I2C3_SDA"),
+ MA35_MUX(0x5, "SPI3_CLK"),
+ MA35_MUX(0x7, "EADC0_ST"),
+ MA35_MUX(0x8, "EBI_AD15"),
+ MA35_MUX(0x9, "EBI_MCLK"),
+ MA35_MUX(0xa, "EBI_ADR15"),
+ MA35_MUX(0xb, "TM8"),
+ MA35_MUX(0xc, "QEI1_INDEX")),
+ MA35_PIN(163, PK9, 0xd4, 0x4,
+ MA35_MUX(0x0, "GPK9"),
+ MA35_MUX(0x4, "I2C3_SCL"),
+ MA35_MUX(0x6, "CCAP0_SCLK"),
+ MA35_MUX(0x8, "EBI_AD0"),
+ MA35_MUX(0xa, "EBI_ADR0")),
+ MA35_PIN(164, PK10, 0xd4, 0x8,
+ MA35_MUX(0x0, "GPK10"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x6, "CCAP0_PIXCLK"),
+ MA35_MUX(0x8, "EBI_AD1"),
+ MA35_MUX(0xa, "EBI_ADR1")),
+ MA35_PIN(165, PK11, 0xd4, 0xc,
+ MA35_MUX(0x0, "GPK11"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x6, "CCAP0_HSYNC"),
+ MA35_MUX(0x8, "EBI_AD2"),
+ MA35_MUX(0xa, "EBI_ADR2")),
+ MA35_PIN(166, PK12, 0xd4, 0x10,
+ MA35_MUX(0x0, "GPK12"),
+ MA35_MUX(0x1, "EPWM2_CH0"),
+ MA35_MUX(0x2, "UART1_nCTS"),
+ MA35_MUX(0x3, "UART13_RXD"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x5, "I2S0_LRCK"),
+ MA35_MUX(0x6, "SPI1_SS0"),
+ MA35_MUX(0x8, "SC0_CLK"),
+ MA35_MUX(0xb, "TM10"),
+ MA35_MUX(0xd, "INT2")),
+ MA35_PIN(167, PK13, 0xd4, 0x14,
+ MA35_MUX(0x0, "GPK13"),
+ MA35_MUX(0x1, "EPWM2_CH1"),
+ MA35_MUX(0x2, "UART1_nRTS"),
+ MA35_MUX(0x3, "UART13_TXD"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x5, "I2S0_BCLK"),
+ MA35_MUX(0x6, "SPI1_CLK"),
+ MA35_MUX(0x8, "SC0_DAT"),
+ MA35_MUX(0xb, "TM10_EXT")),
+ MA35_PIN(168, PK14, 0xd4, 0x18,
+ MA35_MUX(0x0, "GPK14"),
+ MA35_MUX(0x1, "EPWM2_CH2"),
+ MA35_MUX(0x2, "UART1_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x5, "I2S0_DI"),
+ MA35_MUX(0x6, "SPI1_MOSI"),
+ MA35_MUX(0x8, "SC0_RST"),
+ MA35_MUX(0xa, "I2C5_SDA"),
+ MA35_MUX(0xb, "TM11"),
+ MA35_MUX(0xd, "INT3")),
+ MA35_PIN(169, PK15, 0xd4, 0x1c,
+ MA35_MUX(0x0, "GPK15"),
+ MA35_MUX(0x1, "EPWM2_CH3"),
+ MA35_MUX(0x2, "UART1_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "I2S0_DO"),
+ MA35_MUX(0x6, "SPI1_MISO"),
+ MA35_MUX(0x8, "SC0_PWR"),
+ MA35_MUX(0xa, "I2C5_SCL"),
+ MA35_MUX(0xb, "TM11_EXT")),
+ MA35_PIN(170, PL0, 0xd8, 0x0,
+ MA35_MUX(0x0, "GPL0"),
+ MA35_MUX(0x1, "EPWM1_CH0"),
+ MA35_MUX(0x2, "UART11_nCTS"),
+ MA35_MUX(0x3, "UART10_RXD"),
+ MA35_MUX(0x4, "I2C3_SDA"),
+ MA35_MUX(0x5, "SPI2_MOSI"),
+ MA35_MUX(0x6, "QSPI1_MOSI1"),
+ MA35_MUX(0x7, "I2S0_LRCK"),
+ MA35_MUX(0x8, "EBI_AD11"),
+ MA35_MUX(0x9, "SC1_CLK"),
+ MA35_MUX(0xb, "TM5"),
+ MA35_MUX(0xc, "QEI1_A")),
+ MA35_PIN(171, PL1, 0xd8, 0x4,
+ MA35_MUX(0x0, "GPL1"),
+ MA35_MUX(0x1, "EPWM1_CH1"),
+ MA35_MUX(0x2, "UART11_nRTS"),
+ MA35_MUX(0x3, "UART10_TXD"),
+ MA35_MUX(0x4, "I2C3_SCL"),
+ MA35_MUX(0x5, "SPI2_MISO"),
+ MA35_MUX(0x6, "QSPI1_MISO1"),
+ MA35_MUX(0x7, "I2S0_BCLK"),
+ MA35_MUX(0x8, "EBI_AD12"),
+ MA35_MUX(0x9, "SC1_DAT"),
+ MA35_MUX(0xb, "TM5_EXT"),
+ MA35_MUX(0xc, "QEI1_B")),
+ MA35_PIN(172, PL2, 0xd8, 0x8,
+ MA35_MUX(0x0, "GPL2"),
+ MA35_MUX(0x1, "EPWM1_CH2"),
+ MA35_MUX(0x2, "UART11_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x5, "SPI2_SS0"),
+ MA35_MUX(0x6, "QSPI1_SS1"),
+ MA35_MUX(0x7, "I2S0_DI"),
+ MA35_MUX(0x8, "EBI_AD13"),
+ MA35_MUX(0x9, "SC1_RST"),
+ MA35_MUX(0xb, "TM7"),
+ MA35_MUX(0xc, "QEI1_INDEX")),
+ MA35_PIN(173, PL3, 0xd8, 0xc,
+ MA35_MUX(0x0, "GPL3"),
+ MA35_MUX(0x1, "EPWM1_CH3"),
+ MA35_MUX(0x2, "UART11_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "SPI2_CLK"),
+ MA35_MUX(0x6, "QSPI1_CLK"),
+ MA35_MUX(0x7, "I2S0_DO"),
+ MA35_MUX(0x8, "EBI_AD14"),
+ MA35_MUX(0x9, "SC1_PWR"),
+ MA35_MUX(0xb, "TM7_EXT"),
+ MA35_MUX(0xc, "ECAP0_IC0")),
+ MA35_PIN(174, PL4, 0xd8, 0x10,
+ MA35_MUX(0x0, "GPL4"),
+ MA35_MUX(0x1, "EPWM1_CH4"),
+ MA35_MUX(0x2, "UART2_nCTS"),
+ MA35_MUX(0x3, "UART1_RXD"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x5, "SPI3_MOSI"),
+ MA35_MUX(0x6, "QSPI1_MOSI0"),
+ MA35_MUX(0x7, "I2S0_MCLK"),
+ MA35_MUX(0x8, "EBI_nRD"),
+ MA35_MUX(0x9, "SC1_nCD"),
+ MA35_MUX(0xb, "TM9"),
+ MA35_MUX(0xc, "ECAP0_IC1")),
+ MA35_PIN(175, PL5, 0xd8, 0x14,
+ MA35_MUX(0x0, "GPL5"),
+ MA35_MUX(0x1, "EPWM1_CH5"),
+ MA35_MUX(0x2, "UART2_nRTS"),
+ MA35_MUX(0x3, "UART1_TXD"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x5, "SPI3_MISO"),
+ MA35_MUX(0x6, "QSPI1_MISO0"),
+ MA35_MUX(0x7, "I2S1_MCLK"),
+ MA35_MUX(0x8, "EBI_nWR"),
+ MA35_MUX(0x9, "SC0_nCD"),
+ MA35_MUX(0xb, "TM9_EXT"),
+ MA35_MUX(0xc, "ECAP0_IC2")),
+ MA35_PIN(176, PL6, 0xd8, 0x18,
+ MA35_MUX(0x0, "GPL6"),
+ MA35_MUX(0x1, "EPWM0_CH0"),
+ MA35_MUX(0x2, "UART2_RXD"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x6, "QSPI1_MOSI1"),
+ MA35_MUX(0x7, "TRACE_CLK"),
+ MA35_MUX(0x8, "EBI_AD5"),
+ MA35_MUX(0xb, "TM3"),
+ MA35_MUX(0xc, "ECAP1_IC0"),
+ MA35_MUX(0xd, "INT0")),
+ MA35_PIN(177, PL7, 0xd8, 0x1c,
+ MA35_MUX(0x0, "GPL7"),
+ MA35_MUX(0x1, "EPWM0_CH1"),
+ MA35_MUX(0x2, "UART2_TXD"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x6, "QSPI1_MISO1"),
+ MA35_MUX(0x8, "EBI_AD6"),
+ MA35_MUX(0xb, "TM3_EXT"),
+ MA35_MUX(0xc, "ECAP1_IC1"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(178, PL8, 0xdc, 0x0,
+ MA35_MUX(0x0, "GPL8"),
+ MA35_MUX(0x1, "EPWM0_CH2"),
+ MA35_MUX(0x2, "UART14_nCTS"),
+ MA35_MUX(0x3, "UART13_RXD"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x5, "SPI3_SS0"),
+ MA35_MUX(0x6, "EPWM0_CH4"),
+ MA35_MUX(0x7, "I2S1_LRCK"),
+ MA35_MUX(0x8, "EBI_AD7"),
+ MA35_MUX(0x9, "SC0_CLK"),
+ MA35_MUX(0xb, "TM4"),
+ MA35_MUX(0xc, "ECAP1_IC2"),
+ MA35_MUX(0xd, "INT2")),
+ MA35_PIN(179, PL9, 0xdc, 0x4,
+ MA35_MUX(0x0, "GPL9"),
+ MA35_MUX(0x1, "EPWM0_CH3"),
+ MA35_MUX(0x2, "UART14_nRTS"),
+ MA35_MUX(0x3, "UART13_TXD"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x5, "SPI3_CLK"),
+ MA35_MUX(0x6, "EPWM1_CH4"),
+ MA35_MUX(0x7, "I2S1_BCLK"),
+ MA35_MUX(0x8, "EBI_AD8"),
+ MA35_MUX(0x9, "SC0_DAT"),
+ MA35_MUX(0xb, "TM4_EXT"),
+ MA35_MUX(0xc, "QEI0_A"),
+ MA35_MUX(0xd, "INT3")),
+ MA35_PIN(180, PL10, 0xdc, 0x8,
+ MA35_MUX(0x0, "GPL10"),
+ MA35_MUX(0x1, "EPWM0_CH4"),
+ MA35_MUX(0x2, "UART14_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x5, "SPI3_MOSI"),
+ MA35_MUX(0x6, "EPWM0_CH5"),
+ MA35_MUX(0x7, "I2S1_DI"),
+ MA35_MUX(0x8, "EBI_AD9"),
+ MA35_MUX(0x9, "SC0_RST"),
+ MA35_MUX(0xb, "EBI_nWRH"),
+ MA35_MUX(0xc, "QEI0_B")),
+ MA35_PIN(181, PL11, 0xdc, 0xc,
+ MA35_MUX(0x0, "GPL11"),
+ MA35_MUX(0x1, "EPWM0_CH5"),
+ MA35_MUX(0x2, "UART14_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "SPI3_MISO"),
+ MA35_MUX(0x6, "EPWM1_CH5"),
+ MA35_MUX(0x7, "I2S1_DO"),
+ MA35_MUX(0x8, "EBI_AD10"),
+ MA35_MUX(0x9, "SC0_PWR"),
+ MA35_MUX(0xb, "EBI_nWRL"),
+ MA35_MUX(0xc, "QEI0_INDEX")),
+ MA35_PIN(182, PL12, 0xdc, 0x10,
+ MA35_MUX(0x0, "GPL12"),
+ MA35_MUX(0x1, "EPWM0_SYNC_IN"),
+ MA35_MUX(0x2, "UART7_nCTS"),
+ MA35_MUX(0x3, "ECAP1_IC0"),
+ MA35_MUX(0x4, "UART14_RXD"),
+ MA35_MUX(0x5, "SPI0_SS0"),
+ MA35_MUX(0x6, "I2S1_LRCK"),
+ MA35_MUX(0x7, "SC1_CLK"),
+ MA35_MUX(0x8, "EBI_AD0"),
+ MA35_MUX(0x9, "HSUSBH_PWREN"),
+ MA35_MUX(0xa, "I2C2_SDA"),
+ MA35_MUX(0xb, "TM0"),
+ MA35_MUX(0xc, "EPWM0_CH2"),
+ MA35_MUX(0xd, "EBI_AD11"),
+ MA35_MUX(0xe, "RGMII0_PPS"),
+ MA35_MUX(0xf, "RMII0_PPS")),
+ MA35_PIN(183, PL13, 0xdc, 0x14,
+ MA35_MUX(0x0, "GPL13"),
+ MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
+ MA35_MUX(0x2, "UART7_nRTS"),
+ MA35_MUX(0x3, "ECAP1_IC1"),
+ MA35_MUX(0x4, "UART14_TXD"),
+ MA35_MUX(0x5, "SPI0_CLK"),
+ MA35_MUX(0x6, "I2S1_BCLK"),
+ MA35_MUX(0x7, "SC1_DAT"),
+ MA35_MUX(0x8, "EBI_AD1"),
+ MA35_MUX(0x9, "HSUSBH_OVC"),
+ MA35_MUX(0xa, "I2C2_SCL"),
+ MA35_MUX(0xb, "TM0_EXT"),
+ MA35_MUX(0xc, "EPWM0_CH3"),
+ MA35_MUX(0xd, "EBI_AD12"),
+ MA35_MUX(0xe, "RGMII1_PPS"),
+ MA35_MUX(0xf, "RMII1_PPS")),
+ MA35_PIN(184, PL14, 0xdc, 0x18,
+ MA35_MUX(0x0, "GPL14"),
+ MA35_MUX(0x1, "EPWM0_CH2"),
+ MA35_MUX(0x2, "UART7_RXD"),
+ MA35_MUX(0x4, "CAN1_RXD"),
+ MA35_MUX(0x5, "SPI0_MOSI"),
+ MA35_MUX(0x6, "I2S1_DI"),
+ MA35_MUX(0x7, "SC1_RST"),
+ MA35_MUX(0x8, "EBI_AD2"),
+ MA35_MUX(0xb, "TM2"),
+ MA35_MUX(0xc, "INT0"),
+ MA35_MUX(0xd, "EBI_AD13")),
+ MA35_PIN(185, PL15, 0xdc, 0x1c,
+ MA35_MUX(0x0, "GPL15"),
+ MA35_MUX(0x1, "EPWM0_CH1"),
+ MA35_MUX(0x2, "UART7_TXD"),
+ MA35_MUX(0x3, "TRACE_CLK"),
+ MA35_MUX(0x4, "CAN1_TXD"),
+ MA35_MUX(0x5, "SPI0_MISO"),
+ MA35_MUX(0x6, "I2S1_DO"),
+ MA35_MUX(0x7, "SC1_PWR"),
+ MA35_MUX(0x8, "EBI_AD3"),
+ MA35_MUX(0xb, "TM2_EXT"),
+ MA35_MUX(0xc, "INT2"),
+ MA35_MUX(0xd, "EBI_AD14")),
+ MA35_PIN(186, PM0, 0xe0, 0x0,
+ MA35_MUX(0x0, "GPM0"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x6, "CCAP0_VSYNC"),
+ MA35_MUX(0x8, "EBI_AD3"),
+ MA35_MUX(0xa, "EBI_ADR3")),
+ MA35_PIN(187, PM1, 0xe0, 0x4,
+ MA35_MUX(0x0, "GPM1"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x5, "SPI3_I2SMCLK"),
+ MA35_MUX(0x6, "CCAP0_SFIELD"),
+ MA35_MUX(0x8, "EBI_AD4"),
+ MA35_MUX(0xa, "EBI_ADR4")),
+ MA35_PIN(188, PM2, 0xe0, 0x8,
+ MA35_MUX(0x0, "GPM2"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x6, "CCAP0_DATA0"),
+ MA35_MUX(0x8, "EBI_AD5"),
+ MA35_MUX(0xa, "EBI_ADR5")),
+ MA35_PIN(189, PM3, 0xe0, 0xc,
+ MA35_MUX(0x0, "GPM3"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x6, "CCAP0_DATA1"),
+ MA35_MUX(0x8, "EBI_AD6"),
+ MA35_MUX(0xa, "EBI_ADR6")),
+ MA35_PIN(190, PM4, 0xe0, 0x10,
+ MA35_MUX(0x0, "GPM4"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x6, "CCAP0_DATA2"),
+ MA35_MUX(0x8, "EBI_AD7"),
+ MA35_MUX(0xa, "EBI_ADR7")),
+ MA35_PIN(191, PM5, 0xe0, 0x14,
+ MA35_MUX(0x0, "GPM5"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x6, "CCAP0_DATA3"),
+ MA35_MUX(0x8, "EBI_AD8"),
+ MA35_MUX(0xa, "EBI_ADR8")),
+ MA35_PIN(192, PM6, 0xe0, 0x18,
+ MA35_MUX(0x0, "GPM6"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x6, "CCAP0_DATA4"),
+ MA35_MUX(0x8, "EBI_AD9"),
+ MA35_MUX(0xa, "EBI_ADR9")),
+ MA35_PIN(193, PM7, 0xe0, 0x1c,
+ MA35_MUX(0x0, "GPM7"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x6, "CCAP0_DATA5"),
+ MA35_MUX(0x8, "EBI_AD10"),
+ MA35_MUX(0xa, "EBI_ADR10")),
+ MA35_PIN(194, PM8, 0xe4, 0x0,
+ MA35_MUX(0x0, "GPM8"),
+ MA35_MUX(0x4, "I2C0_SDA"),
+ MA35_MUX(0x6, "CCAP0_DATA6"),
+ MA35_MUX(0x8, "EBI_AD11"),
+ MA35_MUX(0xa, "EBI_ADR11")),
+ MA35_PIN(195, PM9, 0xe4, 0x4,
+ MA35_MUX(0x0, "GPM9"),
+ MA35_MUX(0x4, "I2C0_SCL"),
+ MA35_MUX(0x6, "CCAP0_DATA7"),
+ MA35_MUX(0x8, "EBI_AD12"),
+ MA35_MUX(0xa, "EBI_ADR12")),
+ MA35_PIN(196, PM10, 0xe4, 0x8,
+ MA35_MUX(0x0, "GPM10"),
+ MA35_MUX(0x1, "EPWM1_CH2"),
+ MA35_MUX(0x3, "CAN2_RXD"),
+ MA35_MUX(0x5, "SPI3_SS0"),
+ MA35_MUX(0x6, "CCAP0_DATA8"),
+ MA35_MUX(0x7, "SPI2_I2SMCLK"),
+ MA35_MUX(0x8, "EBI_AD13"),
+ MA35_MUX(0xa, "EBI_ADR13")),
+ MA35_PIN(197, PM11, 0xe4, 0xc,
+ MA35_MUX(0x0, "GPM11"),
+ MA35_MUX(0x1, "EPWM1_CH3"),
+ MA35_MUX(0x3, "CAN2_TXD"),
+ MA35_MUX(0x5, "SPI3_SS1"),
+ MA35_MUX(0x6, "CCAP0_DATA9"),
+ MA35_MUX(0x7, "SPI2_SS1"),
+ MA35_MUX(0x8, "EBI_AD14"),
+ MA35_MUX(0xa, "EBI_ADR14")),
+ MA35_PIN(198, PM12, 0xe4, 0x10,
+ MA35_MUX(0x0, "GPM12"),
+ MA35_MUX(0x1, "EPWM1_CH4"),
+ MA35_MUX(0x2, "UART10_nCTS"),
+ MA35_MUX(0x3, "TRACE_DATA0"),
+ MA35_MUX(0x4, "UART11_RXD"),
+ MA35_MUX(0x5, "I2C2_SDA"),
+ MA35_MUX(0x7, "SC1_nCD"),
+ MA35_MUX(0x8, "EBI_AD8"),
+ MA35_MUX(0x9, "I2S1_MCLK"),
+ MA35_MUX(0xb, "TM8")),
+ MA35_PIN(199, PM13, 0xe4, 0x14,
+ MA35_MUX(0x0, "GPM13"),
+ MA35_MUX(0x1, "EPWM1_CH5"),
+ MA35_MUX(0x2, "UART10_nRTS"),
+ MA35_MUX(0x3, "TRACE_DATA1"),
+ MA35_MUX(0x4, "UART11_TXD"),
+ MA35_MUX(0x5, "I2C2_SCL"),
+ MA35_MUX(0x8, "EBI_AD9"),
+ MA35_MUX(0x9, "ECAP1_IC0"),
+ MA35_MUX(0xb, "TM8_EXT")),
+ MA35_PIN(200, PM14, 0xe4, 0x18,
+ MA35_MUX(0x0, "GPM14"),
+ MA35_MUX(0x1, "EPWM1_BRAKE0"),
+ MA35_MUX(0x2, "UART10_RXD"),
+ MA35_MUX(0x3, "TRACE_DATA2"),
+ MA35_MUX(0x4, "CAN2_RXD"),
+ MA35_MUX(0x6, "I2C3_SDA"),
+ MA35_MUX(0x8, "EBI_AD10"),
+ MA35_MUX(0x9, "ECAP1_IC1"),
+ MA35_MUX(0xb, "TM10"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(201, PM15, 0xe4, 0x1c,
+ MA35_MUX(0x0, "GPM15"),
+ MA35_MUX(0x1, "EPWM1_BRAKE1"),
+ MA35_MUX(0x2, "UART10_TXD"),
+ MA35_MUX(0x3, "TRACE_DATA3"),
+ MA35_MUX(0x4, "CAN2_TXD"),
+ MA35_MUX(0x6, "I2C3_SCL"),
+ MA35_MUX(0x8, "EBI_AD11"),
+ MA35_MUX(0x9, "ECAP1_IC2"),
+ MA35_MUX(0xb, "TM10_EXT"),
+ MA35_MUX(0xd, "INT2")),
+ MA35_PIN(202, PN0, 0xe8, 0x0,
+ MA35_MUX(0x0, "GPN0"),
+ MA35_MUX(0x4, "I2C2_SDA"),
+ MA35_MUX(0x6, "CCAP1_DATA0")),
+ MA35_PIN(203, PN1, 0xe8, 0x4,
+ MA35_MUX(0x0, "GPN1"),
+ MA35_MUX(0x4, "I2C2_SCL"),
+ MA35_MUX(0x6, "CCAP1_DATA1")),
+ MA35_PIN(204, PN2, 0xe8, 0x8,
+ MA35_MUX(0x0, "GPN2"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x6, "CCAP1_DATA2")),
+ MA35_PIN(205, PN3, 0xe8, 0xc,
+ MA35_MUX(0x0, "GPN3"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x6, "CCAP1_DATA3")),
+ MA35_PIN(206, PN4, 0xe8, 0x10,
+ MA35_MUX(0x0, "GPN4"),
+ MA35_MUX(0x4, "I2C1_SDA"),
+ MA35_MUX(0x6, "CCAP1_DATA4")),
+ MA35_PIN(207, PN5, 0xe8, 0x14,
+ MA35_MUX(0x0, "GPN5"),
+ MA35_MUX(0x4, "I2C1_SCL"),
+ MA35_MUX(0x6, "CCAP1_DATA5")),
+ MA35_PIN(208, PN6, 0xe8, 0x18,
+ MA35_MUX(0x0, "GPN6"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x6, "CCAP1_DATA6")),
+ MA35_PIN(209, PN7, 0xe8, 0x1c,
+ MA35_MUX(0x0, "GPN7"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x6, "CCAP1_DATA7")),
+ MA35_PIN(210, PN10, 0xec, 0x8,
+ MA35_MUX(0x0, "GPN10"),
+ MA35_MUX(0x3, "CAN2_RXD"),
+ MA35_MUX(0x6, "CCAP1_SCLK")),
+ MA35_PIN(211, PN11, 0xec, 0xc,
+ MA35_MUX(0x0, "GPN11"),
+ MA35_MUX(0x3, "CAN2_TXD"),
+ MA35_MUX(0x6, "CCAP1_PIXCLK")),
+ MA35_PIN(212, PN12, 0xec, 0x10,
+ MA35_MUX(0x0, "GPN12"),
+ MA35_MUX(0x2, "UART6_nCTS"),
+ MA35_MUX(0x3, "UART12_RXD"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x6, "CCAP1_HSYNC")),
+ MA35_PIN(213, PN13, 0xec, 0x14,
+ MA35_MUX(0x0, "GPN13"),
+ MA35_MUX(0x2, "UART6_nRTS"),
+ MA35_MUX(0x3, "UART12_TXD"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x6, "CCAP1_VSYNC")),
+ MA35_PIN(214, PN14, 0xec, 0x18,
+ MA35_MUX(0x0, "GPN14"),
+ MA35_MUX(0x2, "UART6_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x5, "SPI1_SS1"),
+ MA35_MUX(0x6, "CCAP1_SFIELD"),
+ MA35_MUX(0x7, "SPI1_I2SMCLK")),
+ MA35_PIN(215, PN15, 0xec, 0x1c,
+ MA35_MUX(0x0, "GPN15"),
+ MA35_MUX(0x1, "EPWM2_CH4"),
+ MA35_MUX(0x2, "UART6_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "I2S0_MCLK"),
+ MA35_MUX(0x6, "SPI1_SS1"),
+ MA35_MUX(0x7, "SPI1_I2SMCLK"),
+ MA35_MUX(0x8, "SC0_nCD"),
+ MA35_MUX(0x9, "EADC0_ST"),
+ MA35_MUX(0xa, "CLKO"),
+ MA35_MUX(0xb, "TM6")),
+ MA35_PIN(216, PN8, 0xec, 0x0,
+ MA35_MUX(0x0, "GPN8"),
+ MA35_MUX(0x1, "EPWM2_CH4"),
+ MA35_MUX(0x4, "I2C0_SDA"),
+ MA35_MUX(0x5, "SPI2_I2SMCLK"),
+ MA35_MUX(0x6, "CCAP1_DATA8")),
+ MA35_PIN(217, PN9, 0xec, 0x4,
+ MA35_MUX(0x0, "GPN9"),
+ MA35_MUX(0x1, "EPWM2_CH5"),
+ MA35_MUX(0x4, "I2C0_SCL"),
+ MA35_MUX(0x5, "SPI1_I2SMCLK"),
+ MA35_MUX(0x6, "CCAP1_DATA9")),
+ MA35_PIN(218, PN10, 0xec, 0x8,
+ MA35_MUX(0x0, "GPN10"),
+ MA35_MUX(0x3, "CAN2_RXD"),
+ MA35_MUX(0x4, "USBHL2_DM"),
+ MA35_MUX(0x6, "CCAP1_SCLK")),
+ MA35_PIN(219, PN11, 0xec, 0xc,
+ MA35_MUX(0x0, "GPN11"),
+ MA35_MUX(0x3, "CAN2_TXD"),
+ MA35_MUX(0x4, "USBHL2_DP"),
+ MA35_MUX(0x6, "CCAP1_PIXCLK")),
+ MA35_PIN(220, PN12, 0xec, 0x10,
+ MA35_MUX(0x0, "GPN12"),
+ MA35_MUX(0x2, "UART6_nCTS"),
+ MA35_MUX(0x3, "UART12_RXD"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x6, "CCAP1_HSYNC")),
+ MA35_PIN(221, PN13, 0xec, 0x14,
+ MA35_MUX(0x0, "GPN13"),
+ MA35_MUX(0x2, "UART6_nRTS"),
+ MA35_MUX(0x3, "UART12_TXD"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x6, "CCAP1_VSYNC")),
+ MA35_PIN(222, PN14, 0xec, 0x18,
+ MA35_MUX(0x0, "GPN14"),
+ MA35_MUX(0x2, "UART6_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x4, "USBHL3_DM"),
+ MA35_MUX(0x5, "SPI1_SS1"),
+ MA35_MUX(0x6, "CCAP1_SFIELD"),
+ MA35_MUX(0x7, "SPI1_I2SMCLK")),
+ MA35_PIN(223, PN15, 0xec, 0x1c,
+ MA35_MUX(0x0, "GPN15"),
+ MA35_MUX(0x1, "EPWM2_CH4"),
+ MA35_MUX(0x2, "UART6_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x4, "USBHL3_DP"),
+ MA35_MUX(0x5, "I2S0_MCLK"),
+ MA35_MUX(0x6, "SPI1_SS1"),
+ MA35_MUX(0x7, "SPI1_I2SMCLK"),
+ MA35_MUX(0x8, "SC0_nCD"),
+ MA35_MUX(0x9, "EADC0_ST"),
+ MA35_MUX(0xa, "CLKO"),
+ MA35_MUX(0xb, "TM6")),
+};
+
+static int ma35d1_get_pin_num(int offset, int shift)
+{
+ return (offset - 0x80) * 2 + shift / 4;
+}
+
+static struct ma35_pinctrl_soc_info ma35d1_pinctrl_info = {
+ .pins = ma35d1_pins,
+ .npins = ARRAY_SIZE(ma35d1_pins),
+ .get_pin_num = ma35d1_get_pin_num,
+};
+
+static DEFINE_NOIRQ_DEV_PM_OPS(ma35_pinctrl_pm_ops, ma35_pinctrl_suspend, ma35_pinctrl_resume);
+
+static int ma35d1_pinctrl_probe(struct platform_device *pdev)
+{
+ return ma35_pinctrl_probe(pdev, &ma35d1_pinctrl_info);
+}
+
+static const struct of_device_id ma35d1_pinctrl_of_match[] = {
+ { .compatible = "nuvoton,ma35d1-pinctrl" },
+ { },
+};
+
+static struct platform_driver ma35d1_pinctrl_driver = {
+ .probe = ma35d1_pinctrl_probe,
+ .driver = {
+ .name = "ma35d1-pinctrl",
+ .pm = pm_sleep_ptr(&ma35_pinctrl_pm_ops),
+ .of_match_table = ma35d1_pinctrl_of_match,
+ },
+};
+
+static int __init ma35d1_pinctrl_init(void)
+{
+ return platform_driver_register(&ma35d1_pinctrl_driver);
+}
+arch_initcall(ma35d1_pinctrl_init);
+
+MODULE_AUTHOR("schung@nuvoton.com");
+MODULE_DESCRIPTION("Nuvoton MA35D1 pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.34.1
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 1%]
* Re: [PATCH] iommu/arm-smmu: Don't disable next-page prefetcher on devices it works on
2024-05-17 16:37 0% ` Will Deacon
@ 2024-05-17 17:19 5% ` Doug Anderson
0 siblings, 0 replies; 200+ results
From: Doug Anderson @ 2024-05-17 17:19 UTC (permalink / raw)
To: Will Deacon
Cc: Robin Murphy, Joerg Roedel, Stephen Boyd, Chen Lin, iommu,
linux-arm-kernel, linux-kernel
Hi,
On Fri, May 17, 2024 at 9:37 AM Will Deacon <will@kernel.org> wrote:
>
> Hi Doug,
>
> On Mon, May 13, 2024 at 04:13:47PM -0700, Douglas Anderson wrote:
> > On sc7180 trogdor devices we get a scary warning at bootup:
> > arm-smmu 15000000.iommu:
> > Failed to disable prefetcher [errata #841119 and #826419], check ACR.CACHE_LOCK
> >
> > We spent some time trying to figure out how we were going to fix these
> > errata and whether we needed to do a firmware update. Upon closer
> > inspection, however, we realized that the errata don't apply to us.
> > Specifically, the errata document says that for these errata:
> > * Found in: r0p0
> > * Fixed in: r2p2
> >
> > ...and trogdor devices appear to be running r2p4. That means that they
> > are unaffected despite the scary warning.
> >
> > The issue is that the kernel unconditionally tries to disable the
> > prefetcher even on unaffected devices and then warns when it's unable
> > to.
> >
> > Let's change the kernel to only disable the prefetcher on affected
> > devices, which will get rid of the scary warning on devices that are
> > unaffected. As per the comment the prefetcher is
> > "not-particularly-beneficial" but it shouldn't hurt to leave it on for
> > devices where it doesn't cause problems.
> >
> > Fixes: f87f6e5b4539 ("iommu/arm-smmu: Warn once when the perfetcher errata patch fails to apply")
> > Signed-off-by: Douglas Anderson <dianders@chromium.org>
> > ---
> >
> > drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 21 +++++++++++++--------
> > 1 file changed, 13 insertions(+), 8 deletions(-)
>
>
> Just curious, but did you see any performance impact (good or bad) as a
> result of this patch? The next-page prefetcher has always looked a little
> naive to me and, with a tendency for tiny TLBs in some implementations,
> there's a possibility it could do more harm than good.
This patch actually makes no difference on trogdor today other than
getting rid of the scary warning. Specifically on trogdor the
ACR.CACHE_LOCK bit seems to be set so the kernel is unable to change
the setting anyway and has never been able to. We are working on
figuring out how to fix the firmware and then we have to get a
firmware spin before we can really see any changes. I'll keep an eye
out to see if performance numbers change when the firmware uprevs.
BTW: any idea how big of a deal these errata are? We're _just_
finishing a firmware uprev process and there is always pushback
against kicking off a new one unless the issue is important. Given
that we've been living with this issue since devices shipped I'm going
to assume we don't need to rush a firmware update, but if this is
really scary and needs to be addressed sooner we can figure that out.
-Doug
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^ permalink raw reply [relevance 5%]
* Re: [PATCH] iommu/arm-smmu: Don't disable next-page prefetcher on devices it works on
2024-05-13 23:13 5% [PATCH] iommu/arm-smmu: Don't disable next-page prefetcher on devices it works on Douglas Anderson
2024-05-14 17:14 0% ` Robin Murphy
@ 2024-05-17 16:37 0% ` Will Deacon
2024-05-17 17:19 5% ` Doug Anderson
1 sibling, 1 reply; 200+ results
From: Will Deacon @ 2024-05-17 16:37 UTC (permalink / raw)
To: Douglas Anderson
Cc: Robin Murphy, Joerg Roedel, Stephen Boyd, Chen Lin, iommu,
linux-arm-kernel, linux-kernel
Hi Doug,
On Mon, May 13, 2024 at 04:13:47PM -0700, Douglas Anderson wrote:
> On sc7180 trogdor devices we get a scary warning at bootup:
> arm-smmu 15000000.iommu:
> Failed to disable prefetcher [errata #841119 and #826419], check ACR.CACHE_LOCK
>
> We spent some time trying to figure out how we were going to fix these
> errata and whether we needed to do a firmware update. Upon closer
> inspection, however, we realized that the errata don't apply to us.
> Specifically, the errata document says that for these errata:
> * Found in: r0p0
> * Fixed in: r2p2
>
> ...and trogdor devices appear to be running r2p4. That means that they
> are unaffected despite the scary warning.
>
> The issue is that the kernel unconditionally tries to disable the
> prefetcher even on unaffected devices and then warns when it's unable
> to.
>
> Let's change the kernel to only disable the prefetcher on affected
> devices, which will get rid of the scary warning on devices that are
> unaffected. As per the comment the prefetcher is
> "not-particularly-beneficial" but it shouldn't hurt to leave it on for
> devices where it doesn't cause problems.
>
> Fixes: f87f6e5b4539 ("iommu/arm-smmu: Warn once when the perfetcher errata patch fails to apply")
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---
>
> drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)
Just curious, but did you see any performance impact (good or bad) as a
result of this patch? The next-page prefetcher has always looked a little
naive to me and, with a tendency for tiny TLBs in some implementations,
there's a possibility it could do more harm than good.
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* [PATCH 1/1] PCI : Refactoring error log prints for better readability
[not found] <CGME20240517105941epcas5p3e8dbb97f19c9553bf9942ad146124806@epcas5p3.samsung.com>
@ 2024-05-17 10:59 4% ` Onkarnarth
0 siblings, 0 replies; 200+ results
From: Onkarnarth @ 2024-05-17 10:59 UTC (permalink / raw)
To: bhelgaas, vigneshr, s-vadapalli, lpieralisi, kw, robh, yue.wang,
neil.armstrong, khilman, jbrunet, martin.blumenstingl,
thomas.petazzoni, shawn.guo, lchuanhua, srikanth.thokala,
songxiaowei, wangbinghui, manivannan.sadhasivam, thierry.reding,
jonathanh, hayashi.kunihiko, mhiramat, pali, toan,
daire.mcnamara, conor.dooley, marek.vasut+renesas, shawn.lin,
heiko, nirmal.patel, jonathan.derrick, kishon, jdmason,
dave.jiang, rafael, lenb, mahesh, oohall
Cc: linux-pci, linux-kernel, linux-omap, linux-arm-kernel,
linux-amlogic, linux-arm-msm, linux-tegra, r.thapliyal,
Onkarnath, Maninder Singh
From: Onkarnath <onkarnath.1@samsung.com>
As %pe is already introduced, it's better to use it in place of (%ld) or (%d) for
printing error in logs. It will enhance readability of logs.
Error print style is more consistent now.
Co-developed-by: Maninder Singh <maninder1.s@samsung.com>
Signed-off-by: Maninder Singh <maninder1.s@samsung.com>
Signed-off-by: Onkarnath <onkarnath.1@samsung.com>
---
Suggested by Bjorn Helgaas in below discussion
https://patchwork.kernel.org/comment/25712288/
drivers/pci/bus.c | 2 +-
drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
drivers/pci/controller/dwc/pci-meson.c | 16 +--
drivers/pci/controller/dwc/pcie-armada8k.c | 4 +-
drivers/pci/controller/dwc/pcie-histb.c | 6 +-
drivers/pci/controller/dwc/pcie-intel-gw.c | 10 +-
drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
drivers/pci/controller/dwc/pcie-kirin.c | 6 +-
drivers/pci/controller/dwc/pcie-qcom-ep.c | 18 +--
drivers/pci/controller/dwc/pcie-qcom.c | 18 +--
drivers/pci/controller/dwc/pcie-tegra194.c | 132 +++++++++---------
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 2 +-
drivers/pci/controller/pci-aardvark.c | 6 +-
drivers/pci/controller/pci-ftpci100.c | 2 +-
drivers/pci/controller/pci-tegra.c | 86 ++++++------
drivers/pci/controller/pci-xgene.c | 4 +-
drivers/pci/controller/pcie-microchip-host.c | 2 +-
drivers/pci/controller/pcie-rcar-host.c | 14 +-
drivers/pci/controller/pcie-rockchip.c | 34 ++---
drivers/pci/controller/vmd.c | 2 +-
drivers/pci/doe.c | 4 +-
drivers/pci/endpoint/functions/pci-epf-mhi.c | 8 +-
drivers/pci/endpoint/functions/pci-epf-ntb.c | 2 +-
drivers/pci/endpoint/functions/pci-epf-test.c | 4 +-
drivers/pci/endpoint/functions/pci-epf-vntb.c | 2 +-
drivers/pci/endpoint/pci-ep-cfs.c | 12 +-
drivers/pci/endpoint/pci-epf-core.c | 16 +--
drivers/pci/hotplug/acpiphp_core.c | 2 +-
drivers/pci/hotplug/pciehp_core.c | 8 +-
drivers/pci/hotplug/shpchp_core.c | 4 +-
drivers/pci/of.c | 6 +-
drivers/pci/pci-driver.c | 4 +-
drivers/pci/pcie/dpc.c | 4 +-
drivers/pci/quirks.c | 2 +-
drivers/pci/setup-bus.c | 2 +-
drivers/pci/slot.c | 4 +-
drivers/pci/vgaarb.c | 2 +-
37 files changed, 227 insertions(+), 227 deletions(-)
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index 826b5016a101..dbc16cf5a246 100644
--- a/drivers/pci/bus.c
+++ b/drivers/pci/bus.c
@@ -351,7 +351,7 @@ void pci_bus_add_device(struct pci_dev *dev)
dev->match_driver = !dn || of_device_is_available(dn);
retval = device_attach(&dev->dev);
if (retval < 0 && retval != -EPROBE_DEFER)
- pci_warn(dev, "device attach failed (%d)\n", retval);
+ pci_warn(dev, "device attach failed: %pe\n", ERR_PTR(retval));
pci_dev_assign_added(dev, true);
}
diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index d2d17d37d3e0..79b6cc7f0287 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -801,7 +801,7 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
if (IS_ERR(reset)) {
ret = PTR_ERR(reset);
- dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
+ dev_err(&pdev->dev, "gpio request failed: %pe\n", ERR_PTR(ret));
goto err_gpio;
}
diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
index 6477c83262c2..c449d7af9d5b 100644
--- a/drivers/pci/controller/dwc/pci-meson.c
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -183,7 +183,7 @@ static inline struct clk *meson_pcie_probe_clock(struct device *dev,
if (rate) {
ret = clk_set_rate(clk, rate);
if (ret) {
- dev_err(dev, "set clk rate failed, ret = %d\n", ret);
+ dev_err(dev, "set clk rate failed: %pe\n", ERR_PTR(ret));
return ERR_PTR(ret);
}
}
@@ -416,7 +416,7 @@ static int meson_pcie_probe(struct platform_device *pdev)
mp->phy = devm_phy_get(dev, "pcie");
if (IS_ERR(mp->phy)) {
- dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
+ dev_err(dev, "get phy failed: %pe\n", mp->phy);
return PTR_ERR(mp->phy);
}
@@ -428,31 +428,31 @@ static int meson_pcie_probe(struct platform_device *pdev)
ret = meson_pcie_get_resets(mp);
if (ret) {
- dev_err(dev, "get reset resource failed, %d\n", ret);
+ dev_err(dev, "get reset resource failed: %pe\n", ERR_PTR(ret));
return ret;
}
ret = meson_pcie_get_mems(pdev, mp);
if (ret) {
- dev_err(dev, "get memory resource failed, %d\n", ret);
+ dev_err(dev, "get memory resource failed: %pe\n", ERR_PTR(ret));
return ret;
}
ret = meson_pcie_power_on(mp);
if (ret) {
- dev_err(dev, "phy power on failed, %d\n", ret);
+ dev_err(dev, "phy power on failed: %pe\n", ERR_PTR(ret));
return ret;
}
ret = meson_pcie_reset(mp);
if (ret) {
- dev_err(dev, "reset failed, %d\n", ret);
+ dev_err(dev, "reset failed: %pe\n", ERR_PTR(ret));
goto err_phy;
}
ret = meson_pcie_probe_clocks(mp);
if (ret) {
- dev_err(dev, "init clock resources failed, %d\n", ret);
+ dev_err(dev, "init clock resources failed: %pe\n", ERR_PTR(ret));
goto err_phy;
}
@@ -460,7 +460,7 @@ static int meson_pcie_probe(struct platform_device *pdev)
ret = dw_pcie_host_init(&pci->pp);
if (ret < 0) {
- dev_err(dev, "Add PCIe port failed, %d\n", ret);
+ dev_err(dev, "Add PCIe port failed: %pe\n", ERR_PTR(ret));
goto err_phy;
}
diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c
index b5c599ccaacf..581ed3e44d3b 100644
--- a/drivers/pci/controller/dwc/pcie-armada8k.c
+++ b/drivers/pci/controller/dwc/pcie-armada8k.c
@@ -134,7 +134,7 @@ static int armada8k_pcie_setup_phys(struct armada8k_pcie *pcie)
ret = armada8k_pcie_enable_phys(pcie);
if (ret)
- dev_err(dev, "Failed to initialize PHY(s) (%d)\n", ret);
+ dev_err(dev, "Failed to initialize PHY(s): %pe\n", ERR_PTR(ret));
return ret;
}
@@ -251,7 +251,7 @@ static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
ret = dw_pcie_host_init(pp);
if (ret) {
- dev_err(dev, "failed to initialize host: %d\n", ret);
+ dev_err(dev, "failed to initialize host: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c
index 7a11c618b9d9..4dde61f79024 100644
--- a/drivers/pci/controller/dwc/pcie-histb.c
+++ b/drivers/pci/controller/dwc/pcie-histb.c
@@ -230,7 +230,7 @@ static int histb_pcie_host_enable(struct dw_pcie_rp *pp)
if (hipcie->vpcie) {
ret = regulator_enable(hipcie->vpcie);
if (ret) {
- dev_err(dev, "failed to enable regulator: %d\n", ret);
+ dev_err(dev, "failed to enable regulator: %pe\n", ERR_PTR(ret));
return ret;
}
}
@@ -337,14 +337,14 @@ static int histb_pcie_probe(struct platform_device *pdev)
GPIOD_OUT_HIGH);
ret = PTR_ERR_OR_ZERO(hipcie->reset_gpio);
if (ret) {
- dev_err(dev, "unable to request reset gpio: %d\n", ret);
+ dev_err(dev, "unable to request reset gpio: %pe\n", ERR_PTR(ret));
return ret;
}
ret = gpiod_set_consumer_name(hipcie->reset_gpio,
"PCIe device power control");
if (ret) {
- dev_err(dev, "unable to set reset gpio name: %d\n", ret);
+ dev_err(dev, "unable to set reset gpio name: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index acbe4f6d3291..3a94feed4fbf 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -155,7 +155,7 @@ static int intel_pcie_ep_rst_init(struct intel_pcie *pcie)
if (IS_ERR(pcie->reset_gpio)) {
ret = PTR_ERR(pcie->reset_gpio);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to request PCIe GPIO: %d\n", ret);
+ dev_err(dev, "Failed to request PCIe GPIO: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -214,7 +214,7 @@ static int intel_pcie_get_resources(struct platform_device *pdev)
if (IS_ERR(pcie->core_clk)) {
ret = PTR_ERR(pcie->core_clk);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get clks: %d\n", ret);
+ dev_err(dev, "Failed to get clks: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -222,7 +222,7 @@ static int intel_pcie_get_resources(struct platform_device *pdev)
if (IS_ERR(pcie->core_rst)) {
ret = PTR_ERR(pcie->core_rst);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get resets: %d\n", ret);
+ dev_err(dev, "Failed to get resets: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -239,7 +239,7 @@ static int intel_pcie_get_resources(struct platform_device *pdev)
if (IS_ERR(pcie->phy)) {
ret = PTR_ERR(pcie->phy);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Couldn't get pcie-phy: %d\n", ret);
+ dev_err(dev, "Couldn't get pcie-phy: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -295,7 +295,7 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)
ret = clk_prepare_enable(pcie->core_clk);
if (ret) {
- dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret);
+ dev_err(pcie->pci.dev, "Core clock enable failed: %pe\n", ERR_PTR(ret));
goto clk_err;
}
diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
index 98bbc83182b4..6b406d2e6e5d 100644
--- a/drivers/pci/controller/dwc/pcie-keembay.c
+++ b/drivers/pci/controller/dwc/pcie-keembay.c
@@ -377,7 +377,7 @@ static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie,
ret = dw_pcie_host_init(pp);
if (ret) {
keembay_ep_reset_assert(pcie);
- dev_err(dev, "Failed to initialize host: %d\n", ret);
+ dev_err(dev, "Failed to initialize host: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
index d5523f302102..cb0ab71b2fc7 100644
--- a/drivers/pci/controller/dwc/pcie-kirin.c
+++ b/drivers/pci/controller/dwc/pcie-kirin.c
@@ -421,7 +421,7 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
ret = of_pci_get_devfn(child);
if (ret < 0) {
- dev_err(dev, "failed to parse devfn: %d\n", ret);
+ dev_err(dev, "failed to parse devfn: %pe\n", ERR_PTR(ret));
goto put_node;
}
@@ -555,8 +555,8 @@ static int kirin_pcie_add_bus(struct pci_bus *bus)
for (i = 0; i < kirin_pcie->num_slots; i++) {
ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1);
if (ret) {
- dev_err(pci->dev, "PERST# %s error: %d\n",
- kirin_pcie->reset_names[i], ret);
+ dev_err(pci->dev, "PERST# %s error: %pe\n",
+ kirin_pcie->reset_names[i], ERR_PTR(ret));
}
}
usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 2fb8c15e7a91..be31a60bc693 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -296,8 +296,8 @@ static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
if (ret)
- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
- ret);
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %pe\n",
+ ERR_PTR(ret));
}
static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
@@ -334,8 +334,8 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
*/
ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
if (ret) {
- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
- ret);
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %pe\n",
+ ERR_PTR(ret));
goto err_phy_off;
}
@@ -368,7 +368,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
ret = qcom_pcie_enable_resources(pcie_ep);
if (ret) {
- dev_err(dev, "Failed to enable resources: %d\n", ret);
+ dev_err(dev, "Failed to enable resources: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -465,7 +465,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep);
if (ret) {
- dev_err(dev, "Failed to complete initialization: %d\n", ret);
+ dev_err(dev, "Failed to complete initialization: %pe\n", ERR_PTR(ret));
goto err_disable_resources;
}
@@ -591,7 +591,7 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);
if (ret) {
- dev_err(dev, "Failed to get io resources %d\n", ret);
+ dev_err(dev, "Failed to get io resources: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -824,13 +824,13 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev)
ret = qcom_pcie_enable_resources(pcie_ep);
if (ret) {
- dev_err(dev, "Failed to enable resources: %d\n", ret);
+ dev_err(dev, "Failed to enable resources: %pe\n", ERR_PTR(ret));
return ret;
}
ret = dw_pcie_ep_init(&pcie_ep->pci.ep);
if (ret) {
- dev_err(dev, "Failed to initialize endpoint: %d\n", ret);
+ dev_err(dev, "Failed to initialize endpoint: %pe\n", ERR_PTR(ret));
goto err_disable_resources;
}
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 14772edcf0d3..9aa78672f64d 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -931,7 +931,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
ret = reset_control_assert(res->rst);
if (ret) {
- dev_err(dev, "reset assert failed (%d)\n", ret);
+ dev_err(dev, "reset assert failed: %pe\n", ERR_PTR(ret));
goto err_disable_clocks;
}
@@ -939,7 +939,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
ret = reset_control_deassert(res->rst);
if (ret) {
- dev_err(dev, "reset deassert failed (%d)\n", ret);
+ dev_err(dev, "reset deassert failed: %pe\n", ERR_PTR(ret));
goto err_disable_clocks;
}
@@ -1135,7 +1135,7 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
ret = reset_control_assert(res->rst);
if (ret) {
- dev_err(dev, "reset assert failed (%d)\n", ret);
+ dev_err(dev, "reset assert failed: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -1147,7 +1147,7 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
ret = reset_control_deassert(res->rst);
if (ret) {
- dev_err(dev, "reset deassert failed (%d)\n", ret);
+ dev_err(dev, "reset deassert failed: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -1418,8 +1418,8 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
*/
ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
if (ret) {
- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
- ret);
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %pe\n",
+ ERR_PTR(ret));
return ret;
}
@@ -1448,8 +1448,8 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
if (ret) {
- dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
- ret);
+ dev_err(pci->dev, "failed to set interconnect bandwidth: %pe\n",
+ ERR_PTR(ret));
}
}
@@ -1610,7 +1610,7 @@ static int qcom_pcie_suspend_noirq(struct device *dev)
*/
ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));
if (ret) {
- dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret);
+ dev_err(dev, "Failed to set interconnect bandwidth: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 93f5433c5c55..3c93bb11e068 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1114,38 +1114,38 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt);
if (ret < 0) {
- dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);
+ dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %pe\n", ERR_PTR(ret));
return ret;
}
ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us",
&pcie->aspm_pwr_on_t);
if (ret < 0)
- dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n",
- ret);
+ dev_info(pcie->dev, "Failed to read ASPM Power On time: %pe\n",
+ ERR_PTR(ret));
ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us",
&pcie->aspm_l0s_enter_lat);
if (ret < 0)
dev_info(pcie->dev,
- "Failed to read ASPM L0s Entrance latency: %d\n", ret);
+ "Failed to read ASPM L0s Entrance latency: %pe\n", ERR_PTR(ret));
ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
if (ret < 0) {
- dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
+ dev_err(pcie->dev, "Failed to read num-lanes: %pe\n", ERR_PTR(ret));
return ret;
}
ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid);
if (ret) {
- dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret);
+ dev_err(pcie->dev, "Failed to read Controller-ID: %pe\n", ERR_PTR(ret));
return ret;
}
ret = of_property_count_strings(np, "phy-names");
if (ret < 0) {
- dev_err(pcie->dev, "Failed to find PHY entries: %d\n",
- ret);
+ dev_err(pcie->dev, "Failed to find PHY entries: %pe\n",
+ ERR_PTR(ret));
return ret;
}
pcie->phy_count = ret;
@@ -1186,8 +1186,8 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
level = KERN_DEBUG;
dev_printk(level, pcie->dev,
- dev_fmt("Failed to get PERST GPIO: %d\n"),
- err);
+ dev_fmt("Failed to get PERST GPIO: %pe\n"),
+ ERR_PTR(err));
return err;
}
@@ -1202,8 +1202,8 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
level = KERN_DEBUG;
dev_printk(level, pcie->dev,
- dev_fmt("Failed to get REFCLK select GPIOs: %d\n"),
- err);
+ dev_fmt("Failed to get REFCLK select GPIOs: %pe\n"),
+ ERR_PTR(err));
pcie->pex_refclk_sel_gpiod = NULL;
}
@@ -1336,7 +1336,7 @@ static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
ret = regulator_enable(pcie->slot_ctl_3v3);
if (ret < 0) {
dev_err(pcie->dev,
- "Failed to enable 3.3V slot supply: %d\n", ret);
+ "Failed to enable 3.3V slot supply: %pe\n", ERR_PTR(ret));
return ret;
}
}
@@ -1345,7 +1345,7 @@ static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
ret = regulator_enable(pcie->slot_ctl_12v);
if (ret < 0) {
dev_err(pcie->dev,
- "Failed to enable 12V slot supply: %d\n", ret);
+ "Failed to enable 12V slot supply: %pe\n", ERR_PTR(ret));
goto fail_12v_enable;
}
}
@@ -1383,14 +1383,14 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
if (ret) {
dev_err(pcie->dev,
- "Failed to enable controller %u: %d\n", pcie->cid, ret);
+ "Failed to enable controller %u: %pe\n", pcie->cid, ERR_PTR(ret));
return ret;
}
if (pcie->enable_ext_refclk) {
ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
if (ret) {
- dev_err(pcie->dev, "Failed to init UPHY: %d\n", ret);
+ dev_err(pcie->dev, "Failed to init UPHY: %pe\n", ERR_PTR(ret));
goto fail_pll_init;
}
}
@@ -1401,20 +1401,20 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
ret = regulator_enable(pcie->pex_ctl_supply);
if (ret < 0) {
- dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
+ dev_err(pcie->dev, "Failed to enable regulator: %pe\n", ERR_PTR(ret));
goto fail_reg_en;
}
ret = clk_prepare_enable(pcie->core_clk);
if (ret) {
- dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret);
+ dev_err(pcie->dev, "Failed to enable core clock: %pe\n", ERR_PTR(ret));
goto fail_core_clk;
}
ret = reset_control_deassert(pcie->core_apb_rst);
if (ret) {
- dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n",
- ret);
+ dev_err(pcie->dev, "Failed to deassert core APB reset: %pe\n",
+ ERR_PTR(ret));
goto fail_core_apb_rst;
}
@@ -1431,7 +1431,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
ret = tegra_pcie_enable_phy(pcie);
if (ret) {
- dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret);
+ dev_err(pcie->dev, "Failed to enable PHY: %pe\n", ERR_PTR(ret));
goto fail_phy;
}
@@ -1503,32 +1503,32 @@ static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie)
ret = reset_control_assert(pcie->core_rst);
if (ret)
- dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret);
+ dev_err(pcie->dev, "Failed to assert \"core\" reset: %pe\n", ERR_PTR(ret));
tegra_pcie_disable_phy(pcie);
ret = reset_control_assert(pcie->core_apb_rst);
if (ret)
- dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret);
+ dev_err(pcie->dev, "Failed to assert APB reset: %pe\n", ERR_PTR(ret));
clk_disable_unprepare(pcie->core_clk);
ret = regulator_disable(pcie->pex_ctl_supply);
if (ret)
- dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret);
+ dev_err(pcie->dev, "Failed to disable regulator: %pe\n", ERR_PTR(ret));
tegra_pcie_disable_slot_regulators(pcie);
if (pcie->enable_ext_refclk) {
ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
if (ret)
- dev_err(pcie->dev, "Failed to deinit UPHY: %d\n", ret);
+ dev_err(pcie->dev, "Failed to deinit UPHY: %pe\n", ERR_PTR(ret));
}
ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
if (ret)
- dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
- pcie->cid, ret);
+ dev_err(pcie->dev, "Failed to disable controller %d: %pe\n",
+ pcie->cid, ERR_PTR(ret));
}
static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
@@ -1545,7 +1545,7 @@ static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
ret = dw_pcie_host_init(pp);
if (ret < 0) {
- dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret);
+ dev_err(pcie->dev, "Failed to add PCIe port: %pe\n", ERR_PTR(ret));
goto fail_host_init;
}
@@ -1652,20 +1652,20 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
ret = pm_runtime_get_sync(dev);
if (ret < 0) {
- dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
- ret);
+ dev_err(dev, "Failed to get runtime sync for PCIe dev: %pe\n",
+ ERR_PTR(ret));
goto fail_pm_get_sync;
}
ret = pinctrl_pm_select_default_state(dev);
if (ret < 0) {
- dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
+ dev_err(dev, "Failed to configure sideband pins: %pe\n", ERR_PTR(ret));
goto fail_pm_get_sync;
}
ret = tegra_pcie_init_controller(pcie);
if (ret < 0) {
- dev_err(dev, "Failed to initialize controller: %d\n", ret);
+ dev_err(dev, "Failed to initialize controller: %pe\n", ERR_PTR(ret));
goto fail_pm_get_sync;
}
@@ -1713,7 +1713,7 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
LTSSM_STATE_PRE_DETECT,
1, LTSSM_TIMEOUT);
if (ret)
- dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
+ dev_err(pcie->dev, "Failed to go Detect state: %pe\n", ERR_PTR(ret));
dw_pcie_ep_cleanup(&pcie->pci.ep);
@@ -1730,13 +1730,13 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
if (pcie->enable_ext_refclk) {
ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
if (ret)
- dev_err(pcie->dev, "Failed to turn off UPHY: %d\n",
- ret);
+ dev_err(pcie->dev, "Failed to turn off UPHY: %pe\n",
+ ERR_PTR(ret));
}
ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
if (ret)
- dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret);
+ dev_err(pcie->dev, "Failed to turn off UPHY: %pe\n", ERR_PTR(ret));
pcie->ep_state = EP_STATE_DISABLED;
dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n");
@@ -1756,42 +1756,42 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
ret = pm_runtime_resume_and_get(dev);
if (ret < 0) {
- dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
- ret);
+ dev_err(dev, "Failed to get runtime sync for PCIe dev: %pe\n",
+ ERR_PTR(ret));
return;
}
ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
if (ret) {
- dev_err(pcie->dev, "Failed to enable controller %u: %d\n",
- pcie->cid, ret);
+ dev_err(pcie->dev, "Failed to enable controller %u: %pe\n",
+ pcie->cid, ERR_PTR(ret));
goto fail_set_ctrl_state;
}
if (pcie->enable_ext_refclk) {
ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
if (ret) {
- dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n",
- ret);
+ dev_err(dev, "Failed to init UPHY for PCIe EP: %pe\n",
+ ERR_PTR(ret));
goto fail_pll_init;
}
}
ret = clk_prepare_enable(pcie->core_clk);
if (ret) {
- dev_err(dev, "Failed to enable core clock: %d\n", ret);
+ dev_err(dev, "Failed to enable core clock: %pe\n", ERR_PTR(ret));
goto fail_core_clk_enable;
}
ret = reset_control_deassert(pcie->core_apb_rst);
if (ret) {
- dev_err(dev, "Failed to deassert core APB reset: %d\n", ret);
+ dev_err(dev, "Failed to deassert core APB reset: %pe\n", ERR_PTR(ret));
goto fail_core_apb_rst;
}
ret = tegra_pcie_enable_phy(pcie);
if (ret) {
- dev_err(dev, "Failed to enable PHY: %d\n", ret);
+ dev_err(dev, "Failed to enable PHY: %pe\n", ERR_PTR(ret));
goto fail_phy;
}
@@ -1899,7 +1899,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
ret = dw_pcie_ep_init_registers(ep);
if (ret) {
- dev_err(dev, "Failed to complete initialization: %d\n", ret);
+ dev_err(dev, "Failed to complete initialization: %pe\n", ERR_PTR(ret));
goto fail_init_complete;
}
@@ -2044,14 +2044,14 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME);
if (ret < 0) {
- dev_err(dev, "Failed to set PERST GPIO debounce time: %d\n",
- ret);
+ dev_err(dev, "Failed to set PERST GPIO debounce time: %pe\n",
+ ERR_PTR(ret));
return ret;
}
ret = gpiod_to_irq(pcie->pex_rst_gpiod);
if (ret < 0) {
- dev_err(dev, "Failed to get IRQ for PERST GPIO: %d\n", ret);
+ dev_err(dev, "Failed to get IRQ for PERST GPIO: %pe\n", ERR_PTR(ret));
return ret;
}
pcie->pex_rst_irq = (unsigned int)ret;
@@ -2073,7 +2073,7 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
name, (void *)pcie);
if (ret < 0) {
- dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret);
+ dev_err(dev, "Failed to request IRQ for PERST: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -2081,8 +2081,8 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
ret = dw_pcie_ep_init(ep);
if (ret) {
- dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %d\n",
- ret);
+ dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %pe\n",
+ ERR_PTR(ret));
pm_runtime_disable(dev);
return ret;
}
@@ -2152,15 +2152,15 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
if (IS_ERR(pcie->pex_ctl_supply)) {
ret = PTR_ERR(pcie->pex_ctl_supply);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get regulator: %ld\n",
- PTR_ERR(pcie->pex_ctl_supply));
+ dev_err(dev, "Failed to get regulator: %pe\n",
+ pcie->pex_ctl_supply);
return ret;
}
pcie->core_clk = devm_clk_get(dev, "core");
if (IS_ERR(pcie->core_clk)) {
- dev_err(dev, "Failed to get core clock: %ld\n",
- PTR_ERR(pcie->core_clk));
+ dev_err(dev, "Failed to get core clock: %pe\n",
+ pcie->core_clk);
return PTR_ERR(pcie->core_clk);
}
@@ -2177,8 +2177,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
if (IS_ERR(pcie->core_apb_rst)) {
- dev_err(dev, "Failed to get APB reset: %ld\n",
- PTR_ERR(pcie->core_apb_rst));
+ dev_err(dev, "Failed to get APB reset: %pe\n",
+ pcie->core_apb_rst);
return PTR_ERR(pcie->core_apb_rst);
}
@@ -2197,7 +2197,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
if (IS_ERR(phys[i])) {
ret = PTR_ERR(phys[i]);
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get PHY: %d\n", ret);
+ dev_err(dev, "Failed to get PHY: %pe\n", ERR_PTR(ret));
return ret;
}
}
@@ -2219,8 +2219,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
pcie->core_rst = devm_reset_control_get(dev, "core");
if (IS_ERR(pcie->core_rst)) {
- dev_err(dev, "Failed to get core reset: %ld\n",
- PTR_ERR(pcie->core_rst));
+ dev_err(dev, "Failed to get core reset: %pe\n",
+ pcie->core_rst);
return PTR_ERR(pcie->core_rst);
}
@@ -2247,8 +2247,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler,
IRQF_SHARED, "tegra-pcie-intr", pcie);
if (ret) {
- dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
- ret);
+ dev_err(dev, "Failed to request IRQ %d: %pe\n", pp->irq,
+ ERR_PTR(ret));
goto fail;
}
@@ -2266,8 +2266,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
IRQF_SHARED | IRQF_ONESHOT,
"tegra-pcie-ep-intr", pcie);
if (ret) {
- dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
- ret);
+ dev_err(dev, "Failed to request IRQ %d: %pe\n", pp->irq,
+ ERR_PTR(ret));
goto fail;
}
@@ -2364,7 +2364,7 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)
ret = tegra_pcie_dw_host_init(&pcie->pci.pp);
if (ret < 0) {
- dev_err(dev, "Failed to init host: %d\n", ret);
+ dev_err(dev, "Failed to init host: %pe\n", ERR_PTR(ret));
goto fail_host_init;
}
diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index a2b844268e28..9a3d5445f181 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -388,7 +388,7 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
priv->phy = devm_phy_optional_get(dev, "pcie-phy");
if (IS_ERR(priv->phy)) {
ret = PTR_ERR(priv->phy);
- dev_err(dev, "Failed to get phy (%d)\n", ret);
+ dev_err(dev, "Failed to get phy: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 71ecd7ddcc8a..f34e0e163642 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -1743,14 +1743,14 @@ static int advk_pcie_setup_phy(struct advk_pcie *pcie)
/* Old bindings miss the PHY handle */
if (IS_ERR(pcie->phy)) {
- dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy));
+ dev_warn(dev, "PHY unavailable: %pe\n", pcie->phy);
pcie->phy = NULL;
return 0;
}
ret = advk_pcie_enable_phy(pcie);
if (ret)
- dev_err(dev, "Failed to initialize PHY (%d)\n", ret);
+ dev_err(dev, "Failed to initialize PHY: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -1863,7 +1863,7 @@ static int advk_pcie_probe(struct platform_device *pdev)
ret = PTR_ERR_OR_ZERO(pcie->reset_gpio);
if (ret) {
if (ret != -EPROBE_DEFER)
- dev_err(dev, "Failed to get reset-gpio: %i\n", ret);
+ dev_err(dev, "Failed to get reset-gpio: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/pci-ftpci100.c b/drivers/pci/controller/pci-ftpci100.c
index ffdeed25e961..b5127dbdd313 100644
--- a/drivers/pci/controller/pci-ftpci100.c
+++ b/drivers/pci/controller/pci-ftpci100.c
@@ -502,7 +502,7 @@ static int faraday_pci_probe(struct platform_device *pdev)
ret = pci_scan_root_bus_bridge(host);
if (ret) {
- dev_err(dev, "failed to scan host: %d\n", ret);
+ dev_err(dev, "failed to scan host: %pe\n", ERR_PTR(ret));
return ret;
}
p->bus = host->bus;
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 038d974a318e..ead171db29b7 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -946,7 +946,7 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
/* wait for the PLL to lock */
err = tegra_pcie_pll_wait(pcie, 500);
if (err < 0) {
- dev_err(dev, "PLL failed to lock: %d\n", err);
+ dev_err(dev, "PLL failed to lock: %pe\n", ERR_PTR(err));
return err;
}
@@ -997,7 +997,7 @@ static int tegra_pcie_port_phy_power_on(struct tegra_pcie_port *port)
for (i = 0; i < port->lanes; i++) {
err = phy_power_on(port->phys[i]);
if (err < 0) {
- dev_err(dev, "failed to power on PHY#%u: %d\n", i, err);
+ dev_err(dev, "failed to power on PHY#%u: %pe\n", i, ERR_PTR(err));
return err;
}
}
@@ -1014,8 +1014,8 @@ static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
for (i = 0; i < port->lanes; i++) {
err = phy_power_off(port->phys[i]);
if (err < 0) {
- dev_err(dev, "failed to power off PHY#%u: %d\n", i,
- err);
+ dev_err(dev, "failed to power off PHY#%u: %pe\n", i,
+ ERR_PTR(err));
return err;
}
}
@@ -1036,7 +1036,7 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
err = tegra_pcie_phy_enable(pcie);
if (err < 0)
- dev_err(dev, "failed to power on PHY: %d\n", err);
+ dev_err(dev, "failed to power on PHY: %pe\n", ERR_PTR(err));
return err;
}
@@ -1045,8 +1045,8 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
err = tegra_pcie_port_phy_power_on(port);
if (err < 0) {
dev_err(dev,
- "failed to power on PCIe port %u PHY: %d\n",
- port->index, err);
+ "failed to power on PCIe port %u PHY: %pe\n",
+ port->index, ERR_PTR(err));
return err;
}
}
@@ -1067,7 +1067,7 @@ static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
err = tegra_pcie_phy_disable(pcie);
if (err < 0)
- dev_err(dev, "failed to power off PHY: %d\n", err);
+ dev_err(dev, "failed to power off PHY: %pe\n", ERR_PTR(err));
return err;
}
@@ -1076,8 +1076,8 @@ static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
err = tegra_pcie_port_phy_power_off(port);
if (err < 0) {
dev_err(dev,
- "failed to power off PCIe port %u PHY: %d\n",
- port->index, err);
+ "failed to power off PCIe port %u PHY: %pe\n",
+ port->index, ERR_PTR(err));
return err;
}
}
@@ -1167,7 +1167,7 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
if (err < 0)
- dev_warn(dev, "failed to disable regulators: %d\n", err);
+ dev_warn(dev, "failed to disable regulators: %pe\n", ERR_PTR(err));
}
static int tegra_pcie_power_on(struct tegra_pcie *pcie)
@@ -1186,38 +1186,38 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
/* enable regulators */
err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
if (err < 0)
- dev_err(dev, "failed to enable regulators: %d\n", err);
+ dev_err(dev, "failed to enable regulators: %pe\n", ERR_PTR(err));
if (!dev->pm_domain) {
err = tegra_powergate_power_on(TEGRA_POWERGATE_PCIE);
if (err) {
- dev_err(dev, "failed to power ungate: %d\n", err);
+ dev_err(dev, "failed to power ungate: %pe\n", ERR_PTR(err));
goto regulator_disable;
}
err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_PCIE);
if (err) {
- dev_err(dev, "failed to remove clamp: %d\n", err);
+ dev_err(dev, "failed to remove clamp: %pe\n", ERR_PTR(err));
goto powergate;
}
}
err = clk_prepare_enable(pcie->afi_clk);
if (err < 0) {
- dev_err(dev, "failed to enable AFI clock: %d\n", err);
+ dev_err(dev, "failed to enable AFI clock: %pe\n", ERR_PTR(err));
goto powergate;
}
if (soc->has_cml_clk) {
err = clk_prepare_enable(pcie->cml_clk);
if (err < 0) {
- dev_err(dev, "failed to enable CML clock: %d\n", err);
+ dev_err(dev, "failed to enable CML clock: %pe\n", ERR_PTR(err));
goto disable_afi_clk;
}
}
err = clk_prepare_enable(pcie->pll_e);
if (err < 0) {
- dev_err(dev, "failed to enable PLLE clock: %d\n", err);
+ dev_err(dev, "failed to enable PLLE clock: %pe\n", ERR_PTR(err));
goto disable_cml_clk;
}
@@ -1303,13 +1303,13 @@ static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie)
pcie->phy = devm_phy_optional_get(dev, "pcie");
if (IS_ERR(pcie->phy)) {
err = PTR_ERR(pcie->phy);
- dev_err(dev, "failed to get PHY: %d\n", err);
+ dev_err(dev, "failed to get PHY: %pe\n", ERR_PTR(err));
return err;
}
err = phy_init(pcie->phy);
if (err < 0) {
- dev_err(dev, "failed to initialize PHY: %d\n", err);
+ dev_err(dev, "failed to initialize PHY: %pe\n", ERR_PTR(err));
return err;
}
@@ -1350,15 +1350,15 @@ static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port)
for (i = 0; i < port->lanes; i++) {
phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i);
if (IS_ERR(phy)) {
- dev_err(dev, "failed to get PHY#%u: %ld\n", i,
- PTR_ERR(phy));
+ dev_err(dev, "failed to get PHY#%u: %pe\n", i,
+ phy);
return PTR_ERR(phy);
}
err = phy_init(phy);
if (err < 0) {
- dev_err(dev, "failed to initialize PHY#%u: %d\n", i,
- err);
+ dev_err(dev, "failed to initialize PHY#%u: %pe\n", i,
+ ERR_PTR(err));
return err;
}
@@ -1396,7 +1396,7 @@ static void tegra_pcie_phys_put(struct tegra_pcie *pcie)
if (pcie->legacy_phy) {
err = phy_exit(pcie->phy);
if (err < 0)
- dev_err(dev, "failed to teardown PHY: %d\n", err);
+ dev_err(dev, "failed to teardown PHY: %pe\n", ERR_PTR(err));
return;
}
@@ -1404,8 +1404,8 @@ static void tegra_pcie_phys_put(struct tegra_pcie *pcie)
for (i = 0; i < port->lanes; i++) {
err = phy_exit(port->phys[i]);
if (err < 0)
- dev_err(dev, "failed to teardown PHY#%u: %d\n",
- i, err);
+ dev_err(dev, "failed to teardown PHY#%u: %pe\n",
+ i, ERR_PTR(err));
}
}
}
@@ -1420,20 +1420,20 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
err = tegra_pcie_clocks_get(pcie);
if (err) {
- dev_err(dev, "failed to get clocks: %d\n", err);
+ dev_err(dev, "failed to get clocks: %pe\n", ERR_PTR(err));
return err;
}
err = tegra_pcie_resets_get(pcie);
if (err) {
- dev_err(dev, "failed to get resets: %d\n", err);
+ dev_err(dev, "failed to get resets: %pe\n", ERR_PTR(err));
return err;
}
if (soc->program_uphy) {
err = tegra_pcie_phys_get(pcie);
if (err < 0) {
- dev_err(dev, "failed to get PHYs: %d\n", err);
+ dev_err(dev, "failed to get PHYs: %pe\n", ERR_PTR(err));
return err;
}
}
@@ -1477,7 +1477,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
if (err) {
- dev_err(dev, "failed to register IRQ: %d\n", err);
+ dev_err(dev, "failed to register IRQ: %pe\n", ERR_PTR(err));
goto phys_put;
}
@@ -2127,7 +2127,7 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
err = of_pci_get_devfn(port);
if (err < 0) {
- dev_err(dev, "failed to parse address: %d\n", err);
+ dev_err(dev, "failed to parse address: %pe\n", ERR_PTR(err));
goto err_node_put;
}
@@ -2143,8 +2143,8 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
err = of_property_read_u32(port, "nvidia,num-lanes", &value);
if (err < 0) {
- dev_err(dev, "failed to parse # of lanes: %d\n",
- err);
+ dev_err(dev, "failed to parse # of lanes: %pe\n",
+ ERR_PTR(err));
goto err_node_put;
}
@@ -2172,7 +2172,7 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
err = of_address_to_resource(port, 0, &rp->regs);
if (err < 0) {
- dev_err(dev, "failed to parse address: %d\n", err);
+ dev_err(dev, "failed to parse address: %pe\n", ERR_PTR(err));
goto err_node_put;
}
@@ -2640,20 +2640,20 @@ static int tegra_pcie_probe(struct platform_device *pdev)
err = tegra_pcie_get_resources(pcie);
if (err < 0) {
- dev_err(dev, "failed to request resources: %d\n", err);
+ dev_err(dev, "failed to request resources: %pe\n", ERR_PTR(err));
return err;
}
err = tegra_pcie_msi_setup(pcie);
if (err < 0) {
- dev_err(dev, "failed to enable MSI support: %d\n", err);
+ dev_err(dev, "failed to enable MSI support: %pe\n", ERR_PTR(err));
goto put_resources;
}
pm_runtime_enable(pcie->dev);
err = pm_runtime_get_sync(pcie->dev);
if (err < 0) {
- dev_err(dev, "fail to enable pcie controller: %d\n", err);
+ dev_err(dev, "fail to enable pcie controller: %pe\n", ERR_PTR(err));
goto pm_runtime_put;
}
@@ -2662,7 +2662,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
err = pci_host_probe(host);
if (err < 0) {
- dev_err(dev, "failed to register host: %d\n", err);
+ dev_err(dev, "failed to register host: %pe\n", ERR_PTR(err));
goto pm_runtime_put;
}
@@ -2723,7 +2723,7 @@ static int tegra_pcie_pm_suspend(struct device *dev)
if (pcie->soc->program_uphy) {
err = tegra_pcie_phy_power_off(pcie);
if (err < 0)
- dev_err(dev, "failed to power off PHY(s): %d\n", err);
+ dev_err(dev, "failed to power off PHY(s): %pe\n", ERR_PTR(err));
}
reset_control_assert(pcie->pex_rst);
@@ -2745,13 +2745,13 @@ static int tegra_pcie_pm_resume(struct device *dev)
err = tegra_pcie_power_on(pcie);
if (err) {
- dev_err(dev, "tegra pcie power on fail: %d\n", err);
+ dev_err(dev, "tegra pcie power on fail: %pe\n", ERR_PTR(err));
return err;
}
err = pinctrl_pm_select_default_state(dev);
if (err < 0) {
- dev_err(dev, "failed to disable PCIe IO DPD: %d\n", err);
+ dev_err(dev, "failed to disable PCIe IO DPD: %pe\n", ERR_PTR(err));
goto poweroff;
}
@@ -2763,7 +2763,7 @@ static int tegra_pcie_pm_resume(struct device *dev)
err = clk_prepare_enable(pcie->pex_clk);
if (err) {
- dev_err(dev, "failed to enable PEX clock: %d\n", err);
+ dev_err(dev, "failed to enable PEX clock: %pe\n", ERR_PTR(err));
goto pex_dpd_enable;
}
@@ -2772,7 +2772,7 @@ static int tegra_pcie_pm_resume(struct device *dev)
if (pcie->soc->program_uphy) {
err = tegra_pcie_phy_power_on(pcie);
if (err < 0) {
- dev_err(dev, "failed to power on PHY(s): %d\n", err);
+ dev_err(dev, "failed to power on PHY(s): %pe\n", ERR_PTR(err));
goto disable_pex_clk;
}
}
diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
index 8e457fa450a2..9cdc0b24e00d 100644
--- a/drivers/pci/controller/pci-xgene.c
+++ b/drivers/pci/controller/pci-xgene.c
@@ -206,8 +206,8 @@ static int xgene_get_csr_resource(struct acpi_device *adev,
acpi_dev_filter_resource_type_cb,
(void *) flags);
if (ret < 0) {
- dev_err(dev, "failed to parse _CRS method, error code %d\n",
- ret);
+ dev_err(dev, "failed to parse _CRS method, error code %pe\n",
+ ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c
index 137fb8570ba2..9670a31a02c8 100644
--- a/drivers/pci/controller/pcie-microchip-host.c
+++ b/drivers/pci/controller/pcie-microchip-host.c
@@ -1175,7 +1175,7 @@ static int mc_host_probe(struct platform_device *pdev)
ret = mc_pcie_init_clks(dev);
if (ret) {
- dev_err(dev, "failed to get clock resources, error %d\n", ret);
+ dev_err(dev, "failed to get clock resources, error: %pe\n", ERR_PTR(ret));
return -ENODEV;
}
diff --git a/drivers/pci/controller/pcie-rcar-host.c b/drivers/pci/controller/pcie-rcar-host.c
index 996077ab7cfd..3dfe6729e3ed 100644
--- a/drivers/pci/controller/pcie-rcar-host.c
+++ b/drivers/pci/controller/pcie-rcar-host.c
@@ -78,7 +78,7 @@ static int rcar_pcie_wakeup(struct device *pcie_dev, void __iomem *pcie_base)
writel(L1IATN, pcie_base + PMCTLR);
ret = readl_poll_timeout_atomic(pcie_base + PMSR, val,
val & L1FAEG, 10, 1000);
- WARN(ret, "Timeout waiting for L1 link state, ret=%d\n", ret);
+ WARN(ret, "Timeout waiting for L1 link state, ret=%pe\n", ERR_PTR(ret));
writel(L1FAEG | PMEL1RX, pcie_base + PMSR);
}
@@ -782,7 +782,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
IRQF_SHARED | IRQF_NO_THREAD,
rcar_msi_bottom_chip.name, host);
if (err < 0) {
- dev_err(dev, "failed to request IRQ: %d\n", err);
+ dev_err(dev, "failed to request IRQ: %pe\n", ERR_PTR(err));
goto err;
}
@@ -790,7 +790,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
IRQF_SHARED | IRQF_NO_THREAD,
rcar_msi_bottom_chip.name, host);
if (err < 0) {
- dev_err(dev, "failed to request IRQ: %d\n", err);
+ dev_err(dev, "failed to request IRQ: %pe\n", ERR_PTR(err));
goto err;
}
@@ -996,13 +996,13 @@ static int rcar_pcie_probe(struct platform_device *pdev)
err = rcar_pcie_get_resources(host);
if (err < 0) {
- dev_err(dev, "failed to request resources: %d\n", err);
+ dev_err(dev, "failed to request resources: %pe\n", ERR_PTR(err));
goto err_pm_put;
}
err = clk_prepare_enable(host->bus_clk);
if (err) {
- dev_err(dev, "failed to enable bus clock: %d\n", err);
+ dev_err(dev, "failed to enable bus clock: %pe\n", ERR_PTR(err));
goto err_unmap_msi_irqs;
}
@@ -1031,8 +1031,8 @@ static int rcar_pcie_probe(struct platform_device *pdev)
err = rcar_pcie_enable_msi(host);
if (err < 0) {
dev_err(dev,
- "failed to enable MSI support: %d\n",
- err);
+ "failed to enable MSI support: %pe\n",
+ ERR_PTR(err));
goto err_phy_shutdown;
}
}
diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
index 0ef2e622d36e..10bd6aec67bd 100644
--- a/drivers/pci/controller/pcie-rockchip.c
+++ b/drivers/pci/controller/pcie-rockchip.c
@@ -169,51 +169,51 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
err = reset_control_assert(rockchip->aclk_rst);
if (err) {
- dev_err(dev, "assert aclk_rst err %d\n", err);
+ dev_err(dev, "assert aclk_rst err: %pe\n", ERR_PTR(err));
return err;
}
err = reset_control_assert(rockchip->pclk_rst);
if (err) {
- dev_err(dev, "assert pclk_rst err %d\n", err);
+ dev_err(dev, "assert pclk_rst err: %pe\n", ERR_PTR(err));
return err;
}
err = reset_control_assert(rockchip->pm_rst);
if (err) {
- dev_err(dev, "assert pm_rst err %d\n", err);
+ dev_err(dev, "assert pm_rst err: %pe\n", ERR_PTR(err));
return err;
}
for (i = 0; i < MAX_LANE_NUM; i++) {
err = phy_init(rockchip->phys[i]);
if (err) {
- dev_err(dev, "init phy%d err %d\n", i, err);
+ dev_err(dev, "init phy%d err: %pe\n", i, ERR_PTR(err));
goto err_exit_phy;
}
}
err = reset_control_assert(rockchip->core_rst);
if (err) {
- dev_err(dev, "assert core_rst err %d\n", err);
+ dev_err(dev, "assert core_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_assert(rockchip->mgmt_rst);
if (err) {
- dev_err(dev, "assert mgmt_rst err %d\n", err);
+ dev_err(dev, "assert mgmt_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_assert(rockchip->mgmt_sticky_rst);
if (err) {
- dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
+ dev_err(dev, "assert mgmt_sticky_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_assert(rockchip->pipe_rst);
if (err) {
- dev_err(dev, "assert pipe_rst err %d\n", err);
+ dev_err(dev, "assert pipe_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
@@ -221,19 +221,19 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
err = reset_control_deassert(rockchip->pm_rst);
if (err) {
- dev_err(dev, "deassert pm_rst err %d\n", err);
+ dev_err(dev, "deassert pm_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_deassert(rockchip->aclk_rst);
if (err) {
- dev_err(dev, "deassert aclk_rst err %d\n", err);
+ dev_err(dev, "deassert aclk_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
err = reset_control_deassert(rockchip->pclk_rst);
if (err) {
- dev_err(dev, "deassert pclk_rst err %d\n", err);
+ dev_err(dev, "deassert pclk_rst err: %pe\n", ERR_PTR(err));
goto err_exit_phy;
}
@@ -257,7 +257,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
for (i = 0; i < MAX_LANE_NUM; i++) {
err = phy_power_on(rockchip->phys[i]);
if (err) {
- dev_err(dev, "power on phy%d err %d\n", i, err);
+ dev_err(dev, "power on phy%d err: %pe\n", i, ERR_PTR(err));
goto err_power_off_phy;
}
}
@@ -268,7 +268,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
RK_PHY_PLL_LOCK_SLEEP_US,
RK_PHY_PLL_LOCK_TIMEOUT_US);
if (err) {
- dev_err(dev, "PHY PLLs could not lock, %d\n", err);
+ dev_err(dev, "PHY PLLs could not lock: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
@@ -278,25 +278,25 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
*/
err = reset_control_deassert(rockchip->mgmt_sticky_rst);
if (err) {
- dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
+ dev_err(dev, "deassert mgmt_sticky_rst err: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
err = reset_control_deassert(rockchip->core_rst);
if (err) {
- dev_err(dev, "deassert core_rst err %d\n", err);
+ dev_err(dev, "deassert core_rst err: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
err = reset_control_deassert(rockchip->mgmt_rst);
if (err) {
- dev_err(dev, "deassert mgmt_rst err %d\n", err);
+ dev_err(dev, "deassert mgmt_rst err: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
err = reset_control_deassert(rockchip->pipe_rst);
if (err) {
- dev_err(dev, "deassert pipe_rst err %d\n", err);
+ dev_err(dev, "deassert pipe_rst err: %pe\n", ERR_PTR(err));
goto err_power_off_phy;
}
diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c
index 87b7856f375a..7bc123865b1f 100644
--- a/drivers/pci/controller/vmd.c
+++ b/drivers/pci/controller/vmd.c
@@ -943,7 +943,7 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
struct pci_dev, bus_list);
ret = pci_reset_bus(dev);
if (ret)
- pci_warn(dev, "can't reset device: %d\n", ret);
+ pci_warn(dev, "can't reset device: %pe\n", ERR_PTR(ret));
break;
}
diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c
index 652d63df9d22..8019a7140028 100644
--- a/drivers/pci/doe.c
+++ b/drivers/pci/doe.c
@@ -512,8 +512,8 @@ static struct pci_doe_mb *pci_doe_create_mb(struct pci_dev *pdev,
*/
rc = pci_doe_cache_protocols(doe_mb);
if (rc) {
- pci_err(pdev, "[%x] failed to cache protocols : %d\n",
- doe_mb->cap_offset, rc);
+ pci_err(pdev, "[%x] failed to cache protocols : %pe\n",
+ doe_mb->cap_offset, ERR_PTR(rc));
goto err_cancel;
}
diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c
index 2c54d80107cf..78d64eecfa04 100644
--- a/drivers/pci/endpoint/functions/pci-epf-mhi.c
+++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c
@@ -738,14 +738,14 @@ static int pci_epf_mhi_core_init(struct pci_epf *epf)
ret = pci_epc_set_msi(epc, epf->func_no, epf->vfunc_no,
order_base_2(info->msi_count));
if (ret) {
- dev_err(dev, "Failed to set MSI configuration: %d\n", ret);
+ dev_err(dev, "Failed to set MSI configuration: %pe\n", ERR_PTR(ret));
return ret;
}
ret = pci_epc_write_header(epc, epf->func_no, epf->vfunc_no,
epf->header);
if (ret) {
- dev_err(dev, "Failed to set Configuration header: %d\n", ret);
+ dev_err(dev, "Failed to set Configuration header: %pe\n", ERR_PTR(ret));
return ret;
}
@@ -768,7 +768,7 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf)
if (info->flags & MHI_EPF_USE_DMA) {
ret = pci_epf_mhi_dma_init(epf_mhi);
if (ret) {
- dev_err(dev, "Failed to initialize DMA: %d\n", ret);
+ dev_err(dev, "Failed to initialize DMA: %pe\n", ERR_PTR(ret));
return ret;
}
}
@@ -794,7 +794,7 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf)
/* Register the MHI EP controller */
ret = mhi_ep_register_controller(mhi_cntrl, info->config);
if (ret) {
- dev_err(dev, "Failed to register MHI EP controller: %d\n", ret);
+ dev_err(dev, "Failed to register MHI EP controller: %pe\n", ERR_PTR(ret));
if (info->flags & MHI_EPF_USE_DMA)
pci_epf_mhi_dma_deinit(epf_mhi);
return ret;
diff --git a/drivers/pci/endpoint/functions/pci-epf-ntb.c b/drivers/pci/endpoint/functions/pci-epf-ntb.c
index e01a98e74d21..d807b0329805 100644
--- a/drivers/pci/endpoint/functions/pci-epf-ntb.c
+++ b/drivers/pci/endpoint/functions/pci-epf-ntb.c
@@ -2129,7 +2129,7 @@ static int __init epf_ntb_init(void)
ret = pci_epf_register_driver(&epf_ntb_driver);
if (ret) {
destroy_workqueue(kpcintb_workqueue);
- pr_err("Failed to register pci epf ntb driver --> %d\n", ret);
+ pr_err("Failed to register pci epf ntb driver: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index 977fb79c1567..15e745dcdc40 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -167,7 +167,7 @@ static int pci_epf_test_data_transfer(struct pci_epf_test *epf_test,
ret = dma_submit_error(epf_test->transfer_cookie);
if (ret) {
- dev_err(dev, "Failed to do DMA tx_submit %d\n", ret);
+ dev_err(dev, "Failed to do DMA tx_submit: %pe\n", ERR_PTR(ret));
goto terminate;
}
@@ -949,7 +949,7 @@ static int __init pci_epf_test_init(void)
ret = pci_epf_register_driver(&test_driver);
if (ret) {
destroy_workqueue(kpcitest_workqueue);
- pr_err("Failed to register pci epf test driver --> %d\n", ret);
+ pr_err("Failed to register pci epf test driver: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c
index 8e779eecd62d..de52f0613078 100644
--- a/drivers/pci/endpoint/functions/pci-epf-vntb.c
+++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c
@@ -1430,7 +1430,7 @@ static int __init epf_ntb_init(void)
ret = pci_epf_register_driver(&epf_ntb_driver);
if (ret) {
destroy_workqueue(kpcintb_workqueue);
- pr_err("Failed to register pci epf ntb driver --> %d\n", ret);
+ pr_err("Failed to register pci epf ntb driver: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c
index 3b21e28f9b59..a44437aaa4bc 100644
--- a/drivers/pci/endpoint/pci-ep-cfs.c
+++ b/drivers/pci/endpoint/pci-ep-cfs.c
@@ -727,8 +727,8 @@ static int __init pci_ep_cfs_init(void)
ret = configfs_register_subsystem(&pci_ep_cfs_subsys);
if (ret) {
- pr_err("Error %d while registering subsystem %s\n",
- ret, root->cg_item.ci_namebuf);
+ pr_err("Error while registering subsystem %s: %pe\n",
+ root->cg_item.ci_namebuf, ERR_PTR(ret));
goto err;
}
@@ -736,8 +736,8 @@ static int __init pci_ep_cfs_init(void)
&pci_functions_type);
if (IS_ERR(functions_group)) {
ret = PTR_ERR(functions_group);
- pr_err("Error %d while registering functions group\n",
- ret);
+ pr_err("Error while registering functions group: %pe\n",
+ ERR_PTR(ret));
goto err_functions_group;
}
@@ -746,8 +746,8 @@ static int __init pci_ep_cfs_init(void)
&pci_controllers_type);
if (IS_ERR(controllers_group)) {
ret = PTR_ERR(controllers_group);
- pr_err("Error %d while registering controllers group\n",
- ret);
+ pr_err("Error while registering controllers group: %pe\n",
+ ERR_PTR(ret));
goto err_controllers_group;
}
diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c
index 323f2a60ab16..08146b5c5d01 100644
--- a/drivers/pci/endpoint/pci-epf-core.c
+++ b/drivers/pci/endpoint/pci-epf-core.c
@@ -77,8 +77,8 @@ int pci_epf_bind(struct pci_epf *epf)
vfunc_no = epf_vf->vfunc_no;
if (vfunc_no < 1) {
- dev_err(dev, "Invalid virtual function number\n");
ret = -EINVAL;
+ dev_err(dev, "Invalid virtual function number: %pe\n", ERR_PTR(ret));
goto ret;
}
@@ -86,15 +86,15 @@ int pci_epf_bind(struct pci_epf *epf)
func_no = epf->func_no;
if (!IS_ERR_OR_NULL(epc)) {
if (!epc->max_vfs) {
- dev_err(dev, "No support for virt function\n");
ret = -EINVAL;
+ dev_err(dev, "No support for virt function: %pe\n", ERR_PTR(ret));
goto ret;
}
if (vfunc_no > epc->max_vfs[func_no]) {
- dev_err(dev, "PF%d: Exceeds max vfunc number\n",
- func_no);
ret = -EINVAL;
+ dev_err(dev, "PF%d: Exceeds max vfunc number: %pe\n",
+ func_no, ERR_PTR(ret));
goto ret;
}
}
@@ -103,15 +103,15 @@ int pci_epf_bind(struct pci_epf *epf)
func_no = epf->sec_epc_func_no;
if (!IS_ERR_OR_NULL(epc)) {
if (!epc->max_vfs) {
- dev_err(dev, "No support for virt function\n");
ret = -EINVAL;
+ dev_err(dev, "No support for virt function: %pe\n", ERR_PTR(ret));
goto ret;
}
if (vfunc_no > epc->max_vfs[func_no]) {
- dev_err(dev, "PF%d: Exceeds max vfunc number\n",
- func_no);
ret = -EINVAL;
+ dev_err(dev, "PF%d: Exceeds max vfunc number: %pe\n",
+ func_no, ERR_PTR(ret));
goto ret;
}
}
@@ -535,7 +535,7 @@ static int __init pci_epf_init(void)
ret = bus_register(&pci_epf_bus_type);
if (ret) {
- pr_err("failed to register pci epf bus --> %d\n", ret);
+ pr_err("failed to register pci epf bus: %pe\n", ERR_PTR(ret));
return ret;
}
diff --git a/drivers/pci/hotplug/acpiphp_core.c b/drivers/pci/hotplug/acpiphp_core.c
index 9dad14e80bcf..0f5523666e85 100644
--- a/drivers/pci/hotplug/acpiphp_core.c
+++ b/drivers/pci/hotplug/acpiphp_core.c
@@ -277,7 +277,7 @@ int acpiphp_register_hotplug_slot(struct acpiphp_slot *acpiphp_slot,
if (retval == -EBUSY)
goto error_slot;
if (retval) {
- pr_err("pci_hp_register failed with error %d\n", retval);
+ pr_err("pci_hp_register failed with error: %pe\n", ERR_PTR(retval));
goto error_slot;
}
diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c
index ddd55ad97a58..c1ccff9c282e 100644
--- a/drivers/pci/hotplug/pciehp_core.c
+++ b/drivers/pci/hotplug/pciehp_core.c
@@ -81,7 +81,7 @@ static int init_slot(struct controller *ctrl)
retval = pci_hp_initialize(&ctrl->hotplug_slot,
ctrl->pcie->port->subordinate, 0, name);
if (retval) {
- ctrl_err(ctrl, "pci_hp_initialize failed: error %d\n", retval);
+ ctrl_err(ctrl, "pci_hp_initialize failed with error: %pe\n", ERR_PTR(retval));
kfree(ops);
}
return retval;
@@ -210,21 +210,21 @@ static int pciehp_probe(struct pcie_device *dev)
if (rc == -EBUSY)
ctrl_warn(ctrl, "Slot already registered by another hotplug driver\n");
else
- ctrl_err(ctrl, "Slot initialization failed (%d)\n", rc);
+ ctrl_err(ctrl, "Slot initialization failed: %pe\n", ERR_PTR(rc));
goto err_out_release_ctlr;
}
/* Enable events after we have setup the data structures */
rc = pcie_init_notification(ctrl);
if (rc) {
- ctrl_err(ctrl, "Notification initialization failed (%d)\n", rc);
+ ctrl_err(ctrl, "Notification initialization failed: %d\n", rc);
goto err_out_free_ctrl_slot;
}
/* Publish to user space */
rc = pci_hp_add(&ctrl->hotplug_slot);
if (rc) {
- ctrl_err(ctrl, "Publication to user space failed (%d)\n", rc);
+ ctrl_err(ctrl, "Publication to user space failed: %pe\n", ERR_PTR(rc));
goto err_out_shutdown_notification;
}
diff --git a/drivers/pci/hotplug/shpchp_core.c b/drivers/pci/hotplug/shpchp_core.c
index 56c7795ed890..b4e3cef70bf6 100644
--- a/drivers/pci/hotplug/shpchp_core.c
+++ b/drivers/pci/hotplug/shpchp_core.c
@@ -104,8 +104,8 @@ static int init_slots(struct controller *ctrl)
retval = pci_hp_register(hotplug_slot,
ctrl->pci_dev->subordinate, slot->device, name);
if (retval) {
- ctrl_err(ctrl, "pci_hp_register failed with error %d\n",
- retval);
+ ctrl_err(ctrl, "pci_hp_register failed with error: %pe\n",
+ ERR_PTR(retval));
goto error_slotwq;
}
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index 51e3dd0ea5ab..2163ee1eda46 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -518,7 +518,7 @@ static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *
pr_warn_once("%s: possibly some PCI slots don't have level triggered interrupts capability\n",
__func__);
} else {
- dev_err(&pdev->dev, "%s: failed with rc=%d\n", __func__, rc);
+ dev_err(&pdev->dev, "%s: failed with rc=%pe\n", __func__, ERR_PTR(rc));
}
return rc;
}
@@ -573,8 +573,8 @@ static int pci_parse_request_of_pci_ranges(struct device *dev,
case IORESOURCE_IO:
err = devm_pci_remap_iospace(dev, res, iobase);
if (err) {
- dev_warn(dev, "error %d: failed to map resource %pR\n",
- err, res);
+ dev_warn(dev, "failed to map resource %pR with error: %pe\n",
+ res, ERR_PTR(err));
resource_list_destroy_entry(win);
}
break;
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index af2996d0d17f..bbe409ce5d97 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -1313,8 +1313,8 @@ static int pci_pm_runtime_suspend(struct device *dev)
pm->runtime_suspend, error);
return error;
} else if (error) {
- pci_err(pci_dev, "can't suspend (%ps returned %d)\n",
- pm->runtime_suspend, error);
+ pci_err(pci_dev, "can't suspend: %ps returned %pe)\n",
+ pm->runtime_suspend, ERR_PTR(error));
return error;
}
}
diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c
index a668820696dc..789c44d33b1b 100644
--- a/drivers/pci/pcie/dpc.c
+++ b/drivers/pci/pcie/dpc.c
@@ -427,8 +427,8 @@ static int dpc_probe(struct pcie_device *dev)
dpc_handler, IRQF_SHARED,
"pcie-dpc", pdev);
if (status) {
- pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
- status);
+ pci_warn(pdev, "request IRQ%d failed: %pe\n", dev->irq,
+ ERR_PTR(status));
return status;
}
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 568410e64ce6..cd856a42801e 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -6019,7 +6019,7 @@ static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
ret = pci_reset_bus(pdev);
if (ret < 0)
- pci_err(pdev, "Failed to reset GPU: %d\n", ret);
+ pci_err(pdev, "Failed to reset GPU: %pe\n", ERR_PTR(ret));
}
iounmap(map);
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 909e6a7c3cc3..75fdfdbadeef 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -2221,7 +2221,7 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
enable_all:
retval = pci_reenable_device(bridge);
if (retval)
- pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
+ pci_err(bridge, "Error reenabling bridge: %pe\n", ERR_PTR(retval));
pci_set_master(bridge);
}
EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c
index 0f87cade10f7..638b5130215d 100644
--- a/drivers/pci/slot.c
+++ b/drivers/pci/slot.c
@@ -343,8 +343,8 @@ void pci_hp_create_module_link(struct pci_slot *pci_slot)
return;
ret = sysfs_create_link(&pci_slot->kobj, kobj, "module");
if (ret)
- dev_err(&pci_slot->bus->dev, "Error creating sysfs link (%d)\n",
- ret);
+ dev_err(&pci_slot->bus->dev, "Error creating sysfs link: %pe\n",
+ ERR_PTR(ret));
kobject_put(kobj);
}
EXPORT_SYMBOL_GPL(pci_hp_create_module_link);
diff --git a/drivers/pci/vgaarb.c b/drivers/pci/vgaarb.c
index 78748e8d2dba..4e3daf243cb5 100644
--- a/drivers/pci/vgaarb.c
+++ b/drivers/pci/vgaarb.c
@@ -1542,7 +1542,7 @@ static int __init vga_arb_device_init(void)
rc = misc_register(&vga_arb_device);
if (rc < 0)
- pr_err("error %d registering device\n", rc);
+ pr_err("error registering device: %pe\n", ERR_PTR(rc));
bus_register_notifier(&pci_bus_type, &pci_notifier);
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 4%]
* Re: [PATCH v6 03/17] riscv: vector: Use vlenb from DT
2024-05-03 18:18 5% ` [PATCH v6 03/17] riscv: vector: Use vlenb from DT Charlie Jenkins
2024-05-16 13:11 0% ` Andy Chiu
@ 2024-05-16 14:00 0% ` Andy Chiu
1 sibling, 0 replies; 200+ results
From: Andy Chiu @ 2024-05-16 14:00 UTC (permalink / raw)
To: Charlie Jenkins
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Guo Ren, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Conor Dooley, Evan Green,
Clément Léger, Jonathan Corbet, Shuah Khan,
linux-riscv, devicetree, linux-kernel, Palmer Dabbelt,
linux-arm-kernel, linux-sunxi, linux-doc, linux-kselftest
Sorry Charlie, I forgot to include the mailing list. Here is the same as
what I sent in the private message.
On Sat, May 4, 2024 at 2:21 AM Charlie Jenkins <charlie@rivosinc.com> wrote:
>
> If vlenb is provided in the device tree, prefer that over reading the
> vlenb csr.
>
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> ---
> arch/riscv/include/asm/cpufeature.h | 2 ++
> arch/riscv/kernel/cpufeature.c | 47 +++++++++++++++++++++++++++++++++++++
> arch/riscv/kernel/vector.c | 12 +++++++++-
> 3 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 347805446151..0c4f08577015 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
> /* Per-cpu ISA extensions. */
> extern struct riscv_isainfo hart_isa[NR_CPUS];
>
> +extern u32 riscv_vlenb_of;
> +
> void riscv_user_isa_enable(void);
>
> #if defined(CONFIG_RISCV_MISALIGNED)
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 3ed2359eae35..6c143ea9592b 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
> /* Per-cpu ISA extensions. */
> struct riscv_isainfo hart_isa[NR_CPUS];
>
> +u32 riscv_vlenb_of;
> +
> /**
> * riscv_isa_extension_base() - Get base extension word
> *
> @@ -648,6 +650,46 @@ static int __init riscv_isa_fallback_setup(char *__unused)
> early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
> #endif
>
> +static int has_riscv_homogeneous_vlenb(void)
> +{
> + int cpu;
> + u32 prev_vlenb = 0;
> + u32 vlenb;
> +
> + /* Ignore vlenb if vector is not enabled in the kernel */
> + if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
> + return 0;
> +
> + for_each_possible_cpu(cpu) {
> + struct device_node *cpu_node;
> +
> + cpu_node = of_cpu_device_node_get(cpu);
> + if (!cpu_node) {
> + pr_warn("Unable to find cpu node\n");
> + return -ENOENT;
> + }
> +
> + if (of_property_read_u32(cpu_node, "riscv,vlenb", &vlenb)) {
> + of_node_put(cpu_node);
> +
> + if (prev_vlenb)
> + return -ENOENT;
> + continue;
> + }
> +
> + if (prev_vlenb && vlenb != prev_vlenb) {
> + of_node_put(cpu_node);
> + return -ENOENT;
> + }
> +
> + prev_vlenb = vlenb;
> + of_node_put(cpu_node);
> + }
> +
> + riscv_vlenb_of = vlenb;
> + return 0;
> +}
> +
> void __init riscv_fill_hwcap(void)
> {
> char print_str[NUM_ALPHA_EXTS + 1];
> @@ -671,6 +713,11 @@ void __init riscv_fill_hwcap(void)
> pr_info("Falling back to deprecated \"riscv,isa\"\n");
> riscv_fill_hwcap_from_isa_string(isa2hwcap);
> }
> +
> + if (elf_hwcap & COMPAT_HWCAP_ISA_V && has_riscv_homogeneous_vlenb() < 0) {
> + pr_warn("Unsupported heterogeneous vlen detected, vector extension disabled.\> + elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
> + }
We only touch COMPAT_HWCAP_ISA_V and the failed case only turns off the
rectified V. So here we have nothing to do with the Xtheadvector.
However, I am still confused because I think Xtheadvector would also
need to call into this check, so as to setup vlenb.
Apart from that, it seems like some vendor stating Xtheadvector is
actually vector-0.7. Please correct me if I speak anything wrong. One
thing I noticed is that Xtheadvector wouldn't trap on reading
th.vlenb but vector-0.7 would. If that is the case, should we require
Xtheadvector to specify `riscv,vlenb` on the device tree?
> }
>
> /*
> diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> index 6727d1d3b8f2..e04586cdb7f0 100644
> --- a/arch/riscv/kernel/vector.c
> +++ b/arch/riscv/kernel/vector.c
> @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void)
> {
> unsigned long this_vsize;
>
> - /* There are 32 vector registers with vlenb length. */
> + /*
> + * There are 32 vector registers with vlenb length.
> + *
> + * If the riscv,vlenb property was provided by the firmware, use that
> + * instead of probing the CSRs.
> + */
> + if (riscv_vlenb_of) {
> + this_vsize = riscv_vlenb_of * 32;
> + return 0;
> + }
> +
> riscv_v_enable();
> this_vsize = csr_read(CSR_VLENB) * 32;
> riscv_v_disable();
>
> --
> 2.44.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Thanks,
Andy
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v6 03/17] riscv: vector: Use vlenb from DT
2024-05-03 18:18 5% ` [PATCH v6 03/17] riscv: vector: Use vlenb from DT Charlie Jenkins
@ 2024-05-16 13:11 0% ` Andy Chiu
2024-05-16 14:00 0% ` Andy Chiu
1 sibling, 0 replies; 200+ results
From: Andy Chiu @ 2024-05-16 13:11 UTC (permalink / raw)
To: Charlie Jenkins
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Guo Ren, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Conor Dooley, Evan Green,
Clément Léger, Jonathan Corbet, Shuah Khan,
linux-riscv, devicetree, linux-kernel, Palmer Dabbelt,
linux-arm-kernel, linux-sunxi, linux-doc, linux-kselftest
On Sat, May 4, 2024 at 2:21 AM Charlie Jenkins <charlie@rivosinc.com> wrote:
>
> If vlenb is provided in the device tree, prefer that over reading the
> vlenb csr.
>
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
I agree with Conor that we need a mechanism to turn off v and all
depending extensions with has_riscv_homogeneous_vlenb(). And that can
come after this.
Thanks for adding the homogeneous vlen checking!
Reviewed-by: Andy Chiu <andy.chiu@sifive.com>
> ---
> arch/riscv/include/asm/cpufeature.h | 2 ++
> arch/riscv/kernel/cpufeature.c | 47 +++++++++++++++++++++++++++++++++++++
> arch/riscv/kernel/vector.c | 12 +++++++++-
> 3 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 347805446151..0c4f08577015 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
> /* Per-cpu ISA extensions. */
> extern struct riscv_isainfo hart_isa[NR_CPUS];
>
> +extern u32 riscv_vlenb_of;
> +
> void riscv_user_isa_enable(void);
>
> #if defined(CONFIG_RISCV_MISALIGNED)
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 3ed2359eae35..6c143ea9592b 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
> /* Per-cpu ISA extensions. */
> struct riscv_isainfo hart_isa[NR_CPUS];
>
> +u32 riscv_vlenb_of;
> +
> /**
> * riscv_isa_extension_base() - Get base extension word
> *
> @@ -648,6 +650,46 @@ static int __init riscv_isa_fallback_setup(char *__unused)
> early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
> #endif
>
> +static int has_riscv_homogeneous_vlenb(void)
> +{
> + int cpu;
> + u32 prev_vlenb = 0;
> + u32 vlenb;
> +
> + /* Ignore vlenb if vector is not enabled in the kernel */
> + if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
> + return 0;
> +
> + for_each_possible_cpu(cpu) {
> + struct device_node *cpu_node;
> +
> + cpu_node = of_cpu_device_node_get(cpu);
> + if (!cpu_node) {
> + pr_warn("Unable to find cpu node\n");
> + return -ENOENT;
> + }
> +
> + if (of_property_read_u32(cpu_node, "riscv,vlenb", &vlenb)) {
> + of_node_put(cpu_node);
> +
> + if (prev_vlenb)
> + return -ENOENT;
> + continue;
> + }
> +
> + if (prev_vlenb && vlenb != prev_vlenb) {
> + of_node_put(cpu_node);
> + return -ENOENT;
> + }
> +
> + prev_vlenb = vlenb;
> + of_node_put(cpu_node);
> + }
> +
> + riscv_vlenb_of = vlenb;
> + return 0;
> +}
> +
> void __init riscv_fill_hwcap(void)
> {
> char print_str[NUM_ALPHA_EXTS + 1];
> @@ -671,6 +713,11 @@ void __init riscv_fill_hwcap(void)
> pr_info("Falling back to deprecated \"riscv,isa\"\n");
> riscv_fill_hwcap_from_isa_string(isa2hwcap);
> }
> +
> + if (elf_hwcap & COMPAT_HWCAP_ISA_V && has_riscv_homogeneous_vlenb() < 0) {
> + pr_warn("Unsupported heterogeneous vlen detected, vector extension disabled.\n");
> + elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
> + }
> }
>
> /*
> diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> index 6727d1d3b8f2..e04586cdb7f0 100644
> --- a/arch/riscv/kernel/vector.c
> +++ b/arch/riscv/kernel/vector.c
> @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void)
> {
> unsigned long this_vsize;
>
> - /* There are 32 vector registers with vlenb length. */
> + /*
> + * There are 32 vector registers with vlenb length.
> + *
> + * If the riscv,vlenb property was provided by the firmware, use that
> + * instead of probing the CSRs.
> + */
> + if (riscv_vlenb_of) {
> + this_vsize = riscv_vlenb_of * 32;
> + return 0;
> + }
> +
> riscv_v_enable();
> this_vsize = csr_read(CSR_VLENB) * 32;
> riscv_v_disable();
>
> --
> 2.44.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* RE: [EXT] [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave
2024-05-16 4:47 0% ` Amit Singh Tomar
@ 2024-05-16 4:52 0% ` Pankaj Gupta
0 siblings, 0 replies; 200+ results
From: Pankaj Gupta @ 2024-05-16 4:52 UTC (permalink / raw)
To: Amit Singh Tomar, Jonathan Corbet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: linux-doc, linux-kernel, devicetree, imx, linux-arm-kernel
> -----Original Message-----
> From: Amit Singh Tomar <amitsinght@marvell.com>
> Sent: Thursday, May 16, 2024 10:18 AM
> To: Pankaj Gupta <pankaj.gupta@nxp.com>; Jonathan Corbet
> <corbet@lwn.net>; Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Conor Dooley <conor+dt@kernel.org>;
> Shawn Guo <shawnguo@kernel.org>; Sascha Hauer
> <s.hauer@pengutronix.de>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>
> Cc: linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; imx@lists.linux.dev; linux-arm-
> kernel@lists.infradead.org
> Subject: [EXT] [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock
> Enclave
>
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
>
>
> > ----------------------------------------------------------------------
> > NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE),
> > are embedded in the SoC to support the features like HSM, SHE & V2X,
> > using message based communication interface.
> >
> > The secure enclave FW communicates on a dedicated messaging unit(MU)
> > based interface(s) with application core, where kernel is running.
> > It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
> >
> > This patch adds the driver for communication interface to secure-enclave,
> > for exchanging messages with NXP secure enclave HW IP(s) like EdgeLock
> Enclave,
> > both from:
> > - User-Space Applications via character driver.
> > - Kernel-space, used by kernel management layers like DM-Crypt.
> >
> > ABI documentation for the NXP secure-enclave driver.
> >
> > User-space library using this driver:
> > - i.MX Secure Enclave library:
> > -- URL:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Furldefe
> nse.proofpoint.com%2Fv2%2Furl%3Fu%3Dhttps-3A__github.com_nxp-
> 2Dimx_imx-2Dsecure-
> 2Denclave.git%26d%3DDwICAg%26c%3DnKjWec2b6R0mOyPaz7xtfQ%26r%3
> DV_GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-
> JKU%26m%3DlRJFNDYT5J3dZTYPCtbQrN6ho5BaZc62rCnOKShFGK0aosnXA0JK
> Gr_OrCPlpaat%26s%3DGFFpXM8z8-
> pliprvP1Xs1NsiJ8yEvE9xFQuUIGLYoe8%26e%3D&data=05%7C02%7Cpankaj.g
> upta%40nxp.com%7C416c8e43e7a2481741e008dc75636b25%7C686ea1d3b
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C638514317087244086%7CUnkno
> wn%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1h
> aWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=5j5163PSPSKmQo%2BkFfD
> Rio%2Fleez0beSeLcppLrStC0Q%3D&reserved=0 ,
> > - i.MX Secure Middle-Ware:
> > -- URL:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Furldefe
> nse.proofpoint.com%2Fv2%2Furl%3Fu%3Dhttps-3A__github.com_nxp-
> 2Dimx_imx-
> 2Dsmw.git%26d%3DDwICAg%26c%3DnKjWec2b6R0mOyPaz7xtfQ%26r%3DV
> _GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-
> JKU%26m%3DlRJFNDYT5J3dZTYPCtbQrN6ho5BaZc62rCnOKShFGK0aosnXA0JK
> Gr_OrCPlpaat%26s%3DaCsO_lLG71KPvjVgXlx9Ly0Ed05XnSUJ4z-
> xxqxSze8%26e%3D&data=05%7C02%7Cpankaj.gupta%40nxp.com%7C416c8e
> 43e7a2481741e008dc75636b25%7C686ea1d3bc2b4c6fa92cd99c5c301635%
> 7C0%7C0%7C638514317087252827%7CUnknown%7CTWFpbGZsb3d8eyJWIj
> oiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0
> %7C%7C%7C&sdata=u6WyD94p8RRYMBUy6gsv0flZTTnz8LCkc0XbTU6FTt8%
> 3D&reserved=0
> >
> > Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> > ---
> > Documentation/ABI/testing/se-cdev | 42 ++
> > drivers/firmware/imx/Kconfig | 12 +
> > drivers/firmware/imx/Makefile | 2 +
> > drivers/firmware/imx/ele_base_msg.c | 287 ++++++++
> > drivers/firmware/imx/ele_base_msg.h | 70 ++
> > drivers/firmware/imx/ele_common.c | 341 +++++++++
> > drivers/firmware/imx/ele_common.h | 43 ++
> > drivers/firmware/imx/se_ctrl.c | 1339
> +++++++++++++++++++++++++++++++++++
> > drivers/firmware/imx/se_ctrl.h | 151 ++++
> > include/linux/firmware/imx/se_api.h | 14 +
> > include/uapi/linux/se_ioctl.h | 88 +++
> > 11 files changed, 2389 insertions(+)
> >
> > diff --git a/Documentation/ABI/testing/se-cdev
> b/Documentation/ABI/testing/se-cdev
> > new file mode 100644
> > index 000000000000..699525af6b86
> > --- /dev/null
> > +++ b/Documentation/ABI/testing/se-cdev
> > @@ -0,0 +1,42 @@
> > +What: /dev/<se>_mu[0-9]+_ch[0-9]+
> > +Date: May 2024
> > +KernelVersion: 6.8
> > +Contact: linux-imx@nxp.com, pankaj.gupta@nxp.com
> > +Description:
> > + NXP offers multiple hardware IP(s) for secure-enclaves like
> EdgeLock-
> > + Enclave(ELE), SECO. The character device file-descriptors
> > + /dev/<se>_mu*_ch* are the interface between user-space NXP's
> secure-
> > + enclave shared-library and the kernel driver.
> > +
> > + The ioctl(2)-based ABI is defined and documented in
> > + [include]<linux/firmware/imx/ele_mu_ioctl.h>
> > + ioctl(s) are used primarily for:
> > + - shared memory management
> > + - allocation of I/O buffers
> > + - get mu info
> > + - setting a dev-ctx as receiver that is slave to fw
> > + - get SoC info
> > +
> > + The following file operations are supported:
> > +
> > + open(2)
> > + Currently the only useful flags are O_RDWR.
> > +
> > + read(2)
> > + Every read() from the opened character device context is waiting
> on
> > + wakeup_intruptible, that gets set by the registered mailbox
> callback
> > + function; indicating a message received from the firmware on
> message-
> > + unit.
> > +
> > + write(2)
> > + Every write() to the opened character device context needs to
> acquire
> > + mailbox_lock, before sending message on to the message unit.
> > +
> > + close(2)
> > + Stops and free up the I/O contexts that was associated
> > + with the file descriptor.
> > +
> > +Users:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Furldefe
> nse.proofpoint.com%2Fv2%2Furl%3Fu%3Dhttps-3A__github.com_nxp-
> 2Dimx_imx-2Dsecure-
> 2Denclave.git%26d%3DDwICAg%26c%3DnKjWec2b6R0mOyPaz7xtfQ%26r%3
> DV_GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-
> JKU%26m%3DlRJFNDYT5J3dZTYPCtbQrN6ho5BaZc62rCnOKShFGK0aosnXA0JK
> Gr_OrCPlpaat%26s%3DGFFpXM8z8-
> pliprvP1Xs1NsiJ8yEvE9xFQuUIGLYoe8%26e%3D&data=05%7C02%7Cpankaj.g
> upta%40nxp.com%7C416c8e43e7a2481741e008dc75636b25%7C686ea1d3b
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C638514317087258839%7CUnkno
> wn%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1h
> aWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=Ca5NSJ0QWvGQHdJ3xvtg
> BQKOY1Whgs0HqonsnCdZuQ4%3D&reserved=0 ,
> > +
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Furldefe
> nse.proofpoint.com%2Fv2%2Furl%3Fu%3Dhttps-3A__github.com_nxp-
> 2Dimx_imx-
> 2Dsmw.git%26d%3DDwICAg%26c%3DnKjWec2b6R0mOyPaz7xtfQ%26r%3DV
> _GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-
> JKU%26m%3DlRJFNDYT5J3dZTYPCtbQrN6ho5BaZc62rCnOKShFGK0aosnXA0JK
> Gr_OrCPlpaat%26s%3DaCsO_lLG71KPvjVgXlx9Ly0Ed05XnSUJ4z-
> xxqxSze8%26e%3D&data=05%7C02%7Cpankaj.gupta%40nxp.com%7C416c8e
> 43e7a2481741e008dc75636b25%7C686ea1d3bc2b4c6fa92cd99c5c301635%
> 7C0%7C0%7C638514317087264038%7CUnknown%7CTWFpbGZsb3d8eyJWIj
> oiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0
> %7C%7C%7C&sdata=UGEFyRkAnlyWjATv3w6r%2Fy%2B1CXL2fGDMBk3jCL%2
> F%2BGNg%3D&reserved=0
> > + crypto/skcipher,
> > + drivers/nvmem/imx-ocotp-ele.c
> > diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
> > index 183613f82a11..56bdca9bd917 100644
> > --- a/drivers/firmware/imx/Kconfig
> > +++ b/drivers/firmware/imx/Kconfig
> > @@ -22,3 +22,15 @@ config IMX_SCU
> >
> > This driver manages the IPC interface between host CPU and the
> > SCU firmware running on M4.
> > +
> > +config IMX_SEC_ENCLAVE
> > + tristate "i.MX Embedded Secure Enclave - EdgeLock Enclave Firmware
> driver."
> > + depends on IMX_MBOX && ARCH_MXC && ARM64
> > + default m if ARCH_MXC
> > +
> > + help
> > + It is possible to use APIs exposed by the iMX Secure Enclave HW IP
> called:
> > + - EdgeLock Enclave Firmware (for i.MX8ULP, i.MX93),
> > + like base, HSM, V2X & SHE using the SAB protocol via the shared
> Messaging
> > + Unit. This driver exposes these interfaces via a set of file descriptors
> > + allowing to configure shared memory, send and receive messages.
> > diff --git a/drivers/firmware/imx/Makefile
> b/drivers/firmware/imx/Makefile
> > index 8f9f04a513a8..aa9033e0e9e3 100644
> > --- a/drivers/firmware/imx/Makefile
> > +++ b/drivers/firmware/imx/Makefile
> > @@ -1,3 +1,5 @@
> > # SPDX-License-Identifier: GPL-2.0
> > obj-$(CONFIG_IMX_DSP) += imx-dsp.o
> > obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o
> imx-scu-soc.o
> > +sec_enclave-objs = se_ctrl.o ele_common.o ele_base_msg.o
> > +obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
> > diff --git a/drivers/firmware/imx/ele_base_msg.c
> b/drivers/firmware/imx/ele_base_msg.c
> > new file mode 100644
> > index 000000000000..0463f26d93c7
> > --- /dev/null
> > +++ b/drivers/firmware/imx/ele_base_msg.c
> > @@ -0,0 +1,287 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#include <linux/types.h>
> > +#include <linux/completion.h>
> > +#include <linux/dma-mapping.h>
> > +
> > +#include "ele_base_msg.h"
> > +#include "ele_common.h"
> > +
> > +int ele_get_info(struct device *dev, struct soc_info *s_info)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + struct se_api_msg *tx_msg __free(kfree);
> > + struct se_api_msg *rx_msg __free(kfree);
> > + phys_addr_t get_info_addr;
> > + u32 *get_info_data;
> > + u32 status;
> > + int ret;
> > +
> > + if (!priv || !s_info)
> > + goto exit;
> > +
> > + memset(s_info, 0x0, sizeof(*s_info));
> > +
> > + if (priv->mem_pool_name)
> > + get_info_data = get_phy_buf_mem_pool(dev,
> > + priv->mem_pool_name,
> > + &get_info_addr,
> > + ELE_GET_INFO_BUFF_SZ);
> > + else
> > + get_info_data = dmam_alloc_coherent(dev,
> > + ELE_GET_INFO_BUFF_SZ,
> > + &get_info_addr,
> > + GFP_KERNEL);
> > + if (!get_info_data) {
> > + ret = -ENOMEM;
> > + dev_err(dev,
> > + "%s: Failed to allocate get_info_addr.\n",
> > + __func__);
> > + goto exit;
> > + }
> > +
> > + tx_msg = kzalloc(ELE_GET_INFO_REQ_MSG_SZ << 2, GFP_KERNEL);
> > + if (!tx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + rx_msg = kzalloc(ELE_GET_INFO_RSP_MSG_SZ << 2, GFP_KERNEL);
> > + if (!rx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + ret = plat_fill_cmd_msg_hdr(priv,
> > + (struct se_msg_hdr *)&tx_msg->header,
> > + ELE_GET_INFO_REQ,
> > + ELE_GET_INFO_REQ_MSG_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + tx_msg->data[0] = upper_32_bits(get_info_addr);
> > + tx_msg->data[1] = lower_32_bits(get_info_addr);
> > + tx_msg->data[2] = ELE_GET_INFO_READ_SZ;
> > + priv->rx_msg = rx_msg;
> > + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> > + if (ret < 0)
> > + goto exit;
> > +
> > + ret = validate_rsp_hdr(priv,
> > + priv->rx_msg->header,
> > + ELE_GET_INFO_REQ,
> > + ELE_GET_INFO_RSP_MSG_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + status = RES_STATUS(priv->rx_msg->data[0]);
> > + if (status != priv->success_tag) {
> > + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> > + ELE_GET_INFO_REQ, status);
> > + ret = -1;
> > + }
> > +
> > + s_info->imem_state = (get_info_data[ELE_IMEM_STATE_WORD]
> > + & ELE_IMEM_STATE_MASK) >> 16;
> > + s_info->major_ver =
> (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> > + & SOC_VER_MASK) >> 24;
> > + s_info->minor_ver =
> ((get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> > + & SOC_VER_MASK) >> 16) & 0xFF;
> > + s_info->soc_rev =
> (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> > + & SOC_VER_MASK) >> 16;
> > + s_info->soc_id = get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> > + & SOC_ID_MASK;
> > + s_info->serial_num
> > + = (u64)get_info_data[GET_INFO_SL_NUM_MSB_WORD_OFF] <<
> 32
> > + | get_info_data[GET_INFO_SL_NUM_LSB_WORD_OFF];
> > +exit:
> > + if (get_info_addr) {
> > + if (priv->mem_pool_name)
> > + free_phybuf_mem_pool(dev, priv->mem_pool_name,
> > + get_info_data, ELE_GET_INFO_BUFF_SZ);
> > + else
> > + dmam_free_coherent(dev,
> > + ELE_GET_INFO_BUFF_SZ,
> > + get_info_data,
> > + get_info_addr);
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +int ele_ping(struct device *dev)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + struct se_api_msg *tx_msg __free(kfree);
> > + struct se_api_msg *rx_msg __free(kfree);
> > + u32 status;
> > + int ret;
> > +
> > + tx_msg = kzalloc(ELE_PING_REQ_SZ << 2, GFP_KERNEL);
> > + if (!tx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + rx_msg = kzalloc(ELE_PING_RSP_SZ << 2, GFP_KERNEL);
> > + if (!rx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + ret = plat_fill_cmd_msg_hdr(priv,
> > + (struct se_msg_hdr *)&tx_msg->header,
> > + ELE_PING_REQ, ELE_PING_REQ_SZ,
> > + true);
> > + if (ret) {
> > + dev_err(dev, "Error: plat_fill_cmd_msg_hdr failed.\n");
> > + goto exit;
> > + }
> > +
> > + priv->rx_msg = rx_msg;
> > + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> > + if (ret)
> > + goto exit;
> > +
> > + ret = validate_rsp_hdr(priv,
> > + priv->rx_msg->header,
> > + ELE_PING_REQ,
> > + ELE_PING_RSP_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + status = RES_STATUS(priv->rx_msg->data[0]);
> > + if (status != priv->success_tag) {
> > + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> > + ELE_PING_REQ, status);
> > + ret = -1;
> > + }
> > +exit:
> > + return ret;
> > +}
> > +
> > +int ele_service_swap(struct device *dev,
> > + phys_addr_t addr,
> > + u32 addr_size, u16 flag)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + struct se_api_msg *tx_msg __free(kfree);
> > + struct se_api_msg *rx_msg __free(kfree);
> > + u32 status;
> > + int ret;
> > +
> > + tx_msg = kzalloc(ELE_SERVICE_SWAP_REQ_MSG_SZ << 2,
> GFP_KERNEL);
> > + if (!tx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + rx_msg = kzalloc(ELE_SERVICE_SWAP_RSP_MSG_SZ << 2, GFP_KERNEL);
> > + if (!rx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + ret = plat_fill_cmd_msg_hdr(priv,
> > + (struct se_msg_hdr *)&tx_msg->header,
> > + ELE_SERVICE_SWAP_REQ,
> > + ELE_SERVICE_SWAP_REQ_MSG_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + tx_msg->data[0] = flag;
> > + tx_msg->data[1] = addr_size;
> > + tx_msg->data[2] = ELE_NONE_VAL;
> > + tx_msg->data[3] = lower_32_bits(addr);
> > + tx_msg->data[4] = plat_add_msg_crc((uint32_t *)&tx_msg[0],
> > + ELE_SERVICE_SWAP_REQ_MSG_SZ);
> > + priv->rx_msg = rx_msg;
> > + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> > + if (ret < 0)
> > + goto exit;
> > +
> > + ret = validate_rsp_hdr(priv,
> > + priv->rx_msg->header,
> > + ELE_SERVICE_SWAP_REQ,
> > + ELE_SERVICE_SWAP_RSP_MSG_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + status = RES_STATUS(priv->rx_msg->data[0]);
> > + if (status != priv->success_tag) {
> > + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> > + ELE_SERVICE_SWAP_REQ, status);
> > + ret = -1;
> > + } else {
> > + if (flag == ELE_IMEM_EXPORT)
> > + ret = priv->rx_msg->data[1];
> > + else
> > + ret = 0;
> > + }
> > +exit:
> > +
> > + return ret;
> > +}
> > +
> > +int ele_fw_authenticate(struct device *dev, phys_addr_t addr)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + struct se_api_msg *tx_msg __free(kfree);
> > + struct se_api_msg *rx_msg __free(kfree);
> > + u32 status;
> > + int ret;
> > +
> > + tx_msg = kzalloc(ELE_FW_AUTH_REQ_SZ << 2, GFP_KERNEL);
> > + if (!tx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + rx_msg = kzalloc(ELE_FW_AUTH_RSP_MSG_SZ << 2, GFP_KERNEL);
> > + if (!rx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > + ret = plat_fill_cmd_msg_hdr(priv,
> > + (struct se_msg_hdr *)&tx_msg->header,
> > + ELE_FW_AUTH_REQ,
> > + ELE_FW_AUTH_REQ_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + tx_msg->data[0] = addr;
> > + tx_msg->data[1] = 0x0;
> > + tx_msg->data[2] = addr;
> > +
> > + priv->rx_msg = rx_msg;
> > + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> > + if (ret < 0)
> > + goto exit;
> > +
> > + ret = validate_rsp_hdr(priv,
> > + priv->rx_msg->header,
> > + ELE_FW_AUTH_REQ,
> > + ELE_FW_AUTH_RSP_MSG_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + status = RES_STATUS(priv->rx_msg->data[0]);
> > + if (status != priv->success_tag) {
> > + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> > + ELE_FW_AUTH_REQ, status);
> > + ret = -1;
> > + }
> > +exit:
> > +
> > + return ret;
> > +}
> > diff --git a/drivers/firmware/imx/ele_base_msg.h
> b/drivers/firmware/imx/ele_base_msg.h
> > new file mode 100644
> > index 000000000000..3b3d2bf04a84
> > --- /dev/null
> > +++ b/drivers/firmware/imx/ele_base_msg.h
> > @@ -0,0 +1,70 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2024 NXP
> > + *
> > + * Header file for the EdgeLock Enclave Base API(s).
> > + */
> > +
> > +#ifndef ELE_BASE_MSG_H
> > +#define ELE_BASE_MSG_H
> > +
> > +#include <linux/device.h>
> > +#include <linux/types.h>
> > +
> > +#define WORD_SZ 4
> > +#define ELE_NONE_VAL 0x0
> > +
> > +#define ELE_SUCCESS_IND 0xD6
> > +
> > +#define ELE_GET_INFO_REQ 0xDA
> > +#define ELE_GET_INFO_REQ_MSG_SZ 0x10
> > +#define ELE_GET_INFO_RSP_MSG_SZ 0x08
> > +
> > +#define ELE_GET_INFO_BUFF_SZ 0x100
> > +#define ELE_GET_INFO_READ_SZ 0xA0
> > +
> > +#define DEFAULT_IMX_SOC_VER 0xA0
> > +#define SOC_VER_MASK 0xFFFF0000
> > +#define SOC_ID_MASK 0x0000FFFF
> > +struct soc_info {
> > + u32 imem_state;
> > + u8 major_ver;
> > + u8 minor_ver;
> > + u16 soc_id;
> > + u16 soc_rev;
> > + u64 serial_num;
> > +};
> > +
> > +#define GET_INFO_SOC_INFO_WORD_OFFSET 1
> > +#define GET_INFO_UUID_WORD_OFFSET 3
> > +#define GET_INFO_SL_NUM_MSB_WORD_OFF \
> > + (GET_INFO_UUID_WORD_OFFSET + 3)
> > +#define GET_INFO_SL_NUM_LSB_WORD_OFF \
> > + (GET_INFO_UUID_WORD_OFFSET + 0)
> > +
> > +#define ELE_PING_REQ 0x01
> > +#define ELE_PING_REQ_SZ 0x04
> > +#define ELE_PING_RSP_SZ 0x08
> > +
> > +#define ELE_SERVICE_SWAP_REQ 0xDF
> > +#define ELE_SERVICE_SWAP_REQ_MSG_SZ 0x18
> > +#define ELE_SERVICE_SWAP_RSP_MSG_SZ 0x0C
> > +#define ELE_IMEM_SIZE 0x10000
> > +#define ELE_IMEM_STATE_OK 0xCA
> > +#define ELE_IMEM_STATE_BAD 0xFE
> > +#define ELE_IMEM_STATE_WORD 0x27
> > +#define ELE_IMEM_STATE_MASK 0x00ff0000
> > +#define ELE_IMEM_EXPORT 0x1
> > +#define ELE_IMEM_IMPORT 0x2
> > +
> > +#define ELE_FW_AUTH_REQ 0x02
> > +#define ELE_FW_AUTH_REQ_SZ 0x10
> > +#define ELE_FW_AUTH_RSP_MSG_SZ 0x08
> > +
> > +int ele_get_info(struct device *dev, struct soc_info *s_info);
> > +int ele_ping(struct device *dev);
> > +int ele_service_swap(struct device *dev,
> > + phys_addr_t addr,
> > + u32 addr_size, u16 flag);
> > +int ele_fw_authenticate(struct device *dev, phys_addr_t addr);
> > +#endif
> > diff --git a/drivers/firmware/imx/ele_common.c
> b/drivers/firmware/imx/ele_common.c
> > new file mode 100644
> > index 000000000000..dcf7f9034653
> > --- /dev/null
> > +++ b/drivers/firmware/imx/ele_common.c
> > @@ -0,0 +1,341 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#include "ele_base_msg.h"
> > +#include "ele_common.h"
> > +
> > +u32 plat_add_msg_crc(u32 *msg, u32 msg_len)
> > +{
> > + u32 nb_words = msg_len / (u32)sizeof(u32);
> > + u32 crc = 0;
> > + u32 i;
> > +
> > + for (i = 0; i < nb_words - 1; i++)
> > + crc ^= *(msg + i);
> > +
> > + return crc;
> > +}
> > +
> > +int imx_ele_msg_rcv(struct se_if_priv *priv)
> > +{
> > + u32 wait;
> > + int err;
> > +
> > + wait = msecs_to_jiffies(1000);
> > + if (!wait_for_completion_timeout(&priv->done, wait)) {
> > + dev_err(priv->dev,
> > + "Error: wait_for_completion timed out.\n");
> > + err = -ETIMEDOUT;
> > + }
> > +
> > + mutex_unlock(&priv->se_if_cmd_lock);
> > + priv->no_dev_ctx_used = false;
> > +
> > + return err;
> > +}
> > +
> > +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg)
> > +{
> > + bool is_cmd_lock_tobe_taken = false;
> > + int err;
> > +
> > + if (!priv->waiting_rsp_dev || priv->no_dev_ctx_used) {
> > + is_cmd_lock_tobe_taken = true;
> > + mutex_lock(&priv->se_if_cmd_lock);
> > + }
> > + scoped_guard(mutex, &priv->se_if_lock);
> > +
> > + err = mbox_send_message(priv->tx_chan, mssg);
> > + if (err < 0) {
> > + dev_err(priv->dev, "Error: mbox_send_message failure.\n");
> > + if (is_cmd_lock_tobe_taken)
> > + mutex_unlock(&priv->se_if_cmd_lock);
> > + return err;
> > + }
> > + err = 0;
>
> It looks odd, you can simply return 0 in the following statement.
Accepted. Already corrected for v2.
>
> > +
> > + return err;
> > +}
> > +
> > +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg)
> > +{
> > + int err;
> > +
> > + priv->no_dev_ctx_used = true;
> > + err = imx_ele_msg_send(priv, mssg);
> > + if (err)
> > + goto exit;
> > +
> > + err = imx_ele_msg_rcv(priv);
> > +
> > +exit:
> > + return err;
> > +}
> > +
> > +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *dev_ctx)
> > +{
> > + struct se_msg_hdr header = {0};
> > + int err;
> > +
> > + err = wait_event_interruptible(dev_ctx->wq, dev_ctx->pending_hdr !=
> 0);
> > + if (err)
> > + dev_err(dev_ctx->dev,
> > + "%s: Err[0x%x]:Interrupted by signal.\n",
> > + dev_ctx->miscdev.name, err);
> > +
> > + header = *((struct se_msg_hdr *) (&dev_ctx->temp_resp[0]));
> > +
> > + if (header.tag == dev_ctx->priv->rsp_tag)
> > + mutex_unlock(&dev_ctx->priv->se_if_cmd_lock);
> > +
> > + return err;
> > +}
> > +
> > +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
> > + void *tx_msg, int tx_msg_sz)
> > +{
> > + struct se_if_priv *priv = dev_ctx->priv;
> > + struct se_msg_hdr header = {0};
> > + int err;
> > +
> > + header = *((struct se_msg_hdr *) tx_msg);
> > +
> > + /*
> > + * Check that the size passed as argument matches the size
> > + * carried in the message.
> > + */
> > + err = header.size << 2;
> > +
> > + if (err != tx_msg_sz) {
> > + err = -EINVAL;
> > + dev_err(priv->dev,
> > + "%s: User buffer too small\n",
> > + dev_ctx->miscdev.name);
> > + goto exit;
> > + }
> > + /* Check the message is valid according to tags */
> > + if (header.tag == priv->cmd_tag)
> > + priv->waiting_rsp_dev = dev_ctx;
> > + else if (header.tag == priv->rsp_tag) {
> > + /* Check the device context can send the command */
> > + if (dev_ctx != priv->cmd_receiver_dev) {
> > + dev_err(priv->dev,
> > + "%s: Channel not configured to send resp to FW.",
> > + dev_ctx->miscdev.name);
> > + err = -EPERM;
> > + goto exit;
> > + }
> > + } else {
> > + dev_err(priv->dev,
> > + "%s: The message does not have a valid TAG\n",
> > + dev_ctx->miscdev.name);
> > + err = -EINVAL;
> > + goto exit;
> > + }
> > + err = imx_ele_msg_send(priv, tx_msg);
> > +exit:
> > + return err;
> > +}
> > +
> > +/*
> > + * Callback called by mailbox FW, when data is received.
> > + */
> > +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg)
> > +{
> > + struct device *dev = mbox_cl->dev;
> > + struct se_if_device_ctx *dev_ctx;
> > + struct se_api_msg *rx_msg;
> > + bool is_response = false;
> > + struct se_if_priv *priv;
> > + struct se_msg_hdr header;
> > +
> > + priv = dev_get_drvdata(dev);
> > + if (!priv) {
> > + dev_err(dev, "SE-MU Priv data is NULL;");
> > + return;
> > + }
> > +
> > + /* The function can be called with NULL msg */
> > + if (!msg) {
> > + dev_err(dev, "Message is invalid\n");
> > + return;
> > + }
> > +
> > + header.tag = ((u8 *)msg)[TAG_OFFSET];
> > + header.command = ((u8 *)msg)[CMD_OFFSET];
> > + header.size = ((u8 *)msg)[SZ_OFFSET];
> > + header.ver = ((u8 *)msg)[VER_OFFSET];
> > +
> > + /* Incoming command: wake up the receiver if any. */
> > + if (header.tag == priv->cmd_tag) {
> > + dev_dbg(dev, "Selecting cmd receiver\n");
> > + dev_ctx = priv->cmd_receiver_dev;
> > + } else if (header.tag == priv->rsp_tag) {
> > + if (priv->waiting_rsp_dev) {
> > + dev_dbg(dev, "Selecting rsp waiter\n");
> > + dev_ctx = priv->waiting_rsp_dev;
> > + is_response = true;
> > + } else {
> > + /*
> > + * Reading the EdgeLock Enclave response
> > + * to the command, sent by other
> > + * linux kernel services.
> > + */
> > + spin_lock(&priv->lock);
> > + memcpy(&priv->rx_msg, msg, header.size << 2);
> > +
> > + complete(&priv->done);
> > + spin_unlock(&priv->lock);
> > + return;
> > + }
> > + } else {
> > + dev_err(dev, "Failed to select a device for message: %.8x\n",
> > + *((u32 *) &header));
> > + return;
> > + }
> > + /* Init reception */
> > + rx_msg = kzalloc(header.size << 2, GFP_KERNEL);
> > + if (rx_msg)
> > + memcpy(rx_msg, msg, header.size << 2);
> > +
> > + dev_ctx->temp_resp = (u32 *)rx_msg;
> > + dev_ctx->temp_resp_size = header.size;
> > +
> > + /* Allow user to read */
> > + dev_ctx->pending_hdr = 1;
> > + wake_up_interruptible(&dev_ctx->wq);
> > +
> > + if (is_response)
> > + priv->waiting_rsp_dev = NULL;
> > +}
> > +
> > +int validate_rsp_hdr(struct se_if_priv *priv, u32 header,
> > + uint8_t msg_id, uint8_t sz, bool is_base_api)
> > +{
> > + int ret = -EINVAL;
> > + u32 size;
> > + u32 cmd;
> > + u32 tag;
> > + u32 ver;
> > +
> > + tag = MSG_TAG(header);
> > + cmd = MSG_COMMAND(header);
> > + size = MSG_SIZE(header);
> > + ver = MSG_VER(header);
> > +
> > + do {
> > + if (tag != priv->rsp_tag) {
> > + dev_err(priv->dev,
> > + "MSG[0x%x] Hdr: Resp tag mismatch. (0x%x != 0x%x)",
> > + msg_id, tag, priv->rsp_tag);
> > + break;
> > + }
> > +
> > + if (cmd != msg_id) {
> > + dev_err(priv->dev,
> > + "MSG Header: Cmd id mismatch. (0x%x != 0x%x)",
> > + cmd, msg_id);
> > + break;
> > + }
> > +
> > + if (size != (sz >> 2)) {
> > + dev_err(priv->dev,
> > + "MSG[0x%x] Hdr: Cmd size mismatch. (0x%x != 0x%x)",
> > + msg_id, size, (sz >> 2));
> > + break;
> > + }
> > +
> > + if (is_base_api && (ver != priv->base_api_ver)) {
> > + dev_err(priv->dev,
> > + "MSG[0x%x] Hdr: Base API Vers mismatch. (0x%x !=
> 0x%x)",
> > + msg_id, ver, priv->base_api_ver);
> > + break;
> > + } else if (!is_base_api && ver != priv->fw_api_ver) {
> > + dev_err(priv->dev,
> > + "MSG[0x%x] Hdr: FW API Vers mismatch. (0x%x != 0x%x)",
> > + msg_id, ver, priv->fw_api_ver);
> > + break;
> > + }
> > +
> > + ret = 0;
> > +
> > + } while (false);
> > +
> > + return ret;
> > +}
> > +
> > +int se_save_imem_state(struct device *dev)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + int ret;
> > +
> > + /* EXPORT command will save encrypted IMEM to given address,
> > + * so later in resume, IMEM can be restored from the given
> > + * address.
> > + *
> > + * Size must be at least 64 kB.
> > + */
> > + ret = ele_service_swap(dev,
> > + priv->imem.phyaddr,
> > + ELE_IMEM_SIZE,
> > + ELE_IMEM_EXPORT);
> > + if (ret < 0)
> > + dev_err(dev, "Failed to export IMEM\n");
> > + else
> > + dev_info(dev,
> > + "Exported %d bytes of encrypted IMEM\n",
> > + ret);
> > +
> > + return ret;
> > +}
> > +
> > +int se_restore_imem_state(struct device *dev)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + struct soc_info s_info;
> > + int ret;
> > +
> > + /* get info from ELE */
> > + ret = ele_get_info(dev, &s_info);
> > + if (ret) {
> > + dev_err(dev, "Failed to get info from ELE.\n");
> > + return ret;
> > + }
> > +
> > + /* Get IMEM state, if 0xFE then import IMEM */
> > + if (s_info.imem_state == ELE_IMEM_STATE_BAD) {
> > + /* IMPORT command will restore IMEM from the given
> > + * address, here size is the actual size returned by ELE
> > + * during the export operation
> > + */
> > + ret = ele_service_swap(dev,
> > + priv->imem.phyaddr,
> > + priv->imem.size,
> > + ELE_IMEM_IMPORT);
> > + if (ret) {
> > + dev_err(dev, "Failed to import IMEM\n");
> > + goto exit;
> > + }
> > + } else
> > + goto exit;
> > +
> > + /* After importing IMEM, check if IMEM state is equal to 0xCA
> > + * to ensure IMEM is fully loaded and
> > + * ELE functionality can be used.
> > + */
> > + ret = ele_get_info(dev, &s_info);
> > + if (ret) {
> > + dev_err(dev, "Failed to get info from ELE.\n");
> > + goto exit;
> > + }
> > +
> > + if (s_info.imem_state == ELE_IMEM_STATE_OK)
> > + dev_info(dev, "Successfully restored IMEM\n");
> > + else
> > + dev_err(dev, "Failed to restore IMEM\n");
> > +
> > +exit:
> > + return ret;
> > +}
> > diff --git a/drivers/firmware/imx/ele_common.h
> b/drivers/firmware/imx/ele_common.h
> > new file mode 100644
> > index 000000000000..6e3a2114bb56
> > --- /dev/null
> > +++ b/drivers/firmware/imx/ele_common.h
> > @@ -0,0 +1,43 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +
> > +#ifndef __ELE_COMMON_H__
> > +#define __ELE_COMMON_H__
> > +
> > +#include "se_ctrl.h"
> > +
> > +#define IMX_ELE_FW_DIR "imx/ele/"
> > +
> > +uint32_t plat_add_msg_crc(uint32_t *msg, uint32_t msg_len);
> > +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *priv);
> > +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
> > + void *tx_msg, int tx_msg_sz);
> > +int imx_ele_msg_rcv(struct se_if_priv *priv);
> > +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg);
> > +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg);
> > +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg);
> > +int validate_rsp_hdr(struct se_if_priv *priv, unsigned int header,
> > + u8 msg_id, u8 sz, bool is_base_api);
> > +
> > +/* Fill a command message header with a given command ID and length in
> bytes. */
> > +static inline int plat_fill_cmd_msg_hdr(struct se_if_priv *priv,
> > + struct se_msg_hdr *hdr,
> > + u8 cmd,
> > + u32 len,
> > + bool is_base_api)
> > +{
> > + hdr->tag = priv->cmd_tag;
> > + hdr->ver = (is_base_api) ? priv->base_api_ver : priv->fw_api_ver;
> > + hdr->command = cmd;
> > + hdr->size = len >> 2;
> > +
> > + return 0;
> > +}
> > +
> > +int se_save_imem_state(struct device *dev);
> > +int se_restore_imem_state(struct device *dev);
> > +
> > +#endif /*__ELE_COMMON_H__ */
> > diff --git a/drivers/firmware/imx/se_ctrl.c b/drivers/firmware/imx/se_ctrl.c
> > new file mode 100644
> > index 000000000000..11c5eaa7353f
> > --- /dev/null
> > +++ b/drivers/firmware/imx/se_ctrl.c
> > @@ -0,0 +1,1339 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#include <linux/completion.h>
> > +#include <linux/delay.h>
> > +#include <linux/dev_printk.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/errno.h>
> > +#include <linux/export.h>
> > +#include <linux/firmware.h>
> > +#include <linux/firmware/imx/se_api.h>
> > +#include <linux/genalloc.h>
> > +#include <linux/init.h>
> > +#include <linux/io.h>
> > +#include <linux/miscdevice.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/module.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/of_reserved_mem.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +#include <linux/string.h>
> > +#include <linux/sys_soc.h>
> > +#include <uapi/linux/se_ioctl.h>
> > +
> > +#include "ele_base_msg.h"
> > +#include "ele_common.h"
> > +#include "se_ctrl.h"
> > +
> > +#define RESERVED_DMA_POOL BIT(1)
> > +
> > +struct imx_se_node_info {
> > + u8 se_if_id;
> > + u8 se_if_did;
> > + u8 max_dev_ctx;
> > + u8 cmd_tag;
> > + u8 rsp_tag;
> > + u8 success_tag;
> > + u8 base_api_ver;
> > + u8 fw_api_ver;
> > + u8 *se_name;
> > + u8 *mbox_tx_name;
> > + u8 *mbox_rx_name;
> > + u8 *pool_name;
> > + u8 *fw_name_in_rfs;
> > + bool soc_register;
> > + bool reserved_dma_ranges;
> > + bool imem_mgmt;
> > +};
> > +
> > +struct imx_se_node_info_list {
> > + u8 num_mu;
> > + u16 soc_id;
> > + u16 soc_rev;
> > + struct imx_se_node_info info[];
> > +};
> > +
> > +static const struct imx_se_node_info_list imx8ulp_info = {
> > + .num_mu = 1,
> > + .soc_id = SOC_ID_OF_IMX8ULP,
> > + .info = {
> > + {
> > + .se_if_id = 2,
> > + .se_if_did = 7,
> > + .max_dev_ctx = 4,
> > + .cmd_tag = 0x17,
> > + .rsp_tag = 0xe1,
> > + .success_tag = 0xd6,
> > + .base_api_ver = MESSAGING_VERSION_6,
> > + .fw_api_ver = MESSAGING_VERSION_7,
> > + .se_name = "hsm1",
> > + .mbox_tx_name = "tx",
> > + .mbox_rx_name = "rx",
> > + .pool_name = "sram",
> > + .fw_name_in_rfs = IMX_ELE_FW_DIR\
> > + "mx8ulpa2ext-ahab-container.img",
> > + .soc_register = true,
> > + .reserved_dma_ranges = true,
> > + .imem_mgmt = true,
> > + },
> > + },
> > +};
> > +
> > +static const struct imx_se_node_info_list imx93_info = {
> > + .num_mu = 1,
> > + .soc_id = SOC_ID_OF_IMX93,
> > + .info = {
> > + {
> > + .se_if_id = 2,
> > + .se_if_did = 3,
> > + .max_dev_ctx = 4,
> > + .cmd_tag = 0x17,
> > + .rsp_tag = 0xe1,
> > + .success_tag = 0xd6,
> > + .base_api_ver = MESSAGING_VERSION_6,
> > + .fw_api_ver = MESSAGING_VERSION_7,
> > + .se_name = "hsm1",
> > + .mbox_tx_name = "tx",
> > + .mbox_rx_name = "rx",
> > + .reserved_dma_ranges = true,
> > + .imem_mgmt = true,
> > + .soc_register = true,
> > + },
> > + },
> > +};
> > +
> > +static const struct of_device_id se_match[] = {
> > + { .compatible = "fsl,imx8ulp-ele", .data = (void *)&imx8ulp_info},
> > + { .compatible = "fsl,imx93-ele", .data = (void *)&imx93_info},
> > + {},
> > +};
> > +
> > +static struct imx_se_node_info
> > + *get_imx_se_node_info(struct imx_se_node_info_list *info_list,
> > + const u32 idx)
> > +{
> > + if (idx < 0 || idx > info_list->num_mu)
> > + return NULL;
> > +
> > + return &info_list->info[idx];
> > +}
> > +
> > +void *get_phy_buf_mem_pool(struct device *dev,
> > + u8 *mem_pool_name,
> > + dma_addr_t *buf,
> > + u32 size)
> > +{
> > + struct device_node *of_node = dev->of_node;
> > + struct gen_pool *mem_pool;
> > +
> > + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> > + if (!mem_pool) {
> > + dev_err(dev,
> > + "Unable to get sram pool = %s\n",
> > + mem_pool_name);
> > + return 0;
> > + }
> > +
> > + return gen_pool_dma_alloc(mem_pool, size, buf);
> > +}
> > +
> > +void free_phybuf_mem_pool(struct device *dev,
> > + u8 *mem_pool_name,
> > + u32 *buf,
> > + u32 size)
> > +{
> > + struct device_node *of_node = dev->of_node;
> > + struct gen_pool *mem_pool;
> > +
> > + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> > + if (!mem_pool)
> > + dev_err(dev,
> > + "%s: Failed: Unable to get sram pool.\n",
> > + __func__);
> > +
> > + gen_pool_free(mem_pool, (u64)buf, size);
> > +}
> > +
> > +static int imx_fetch_soc_info(struct device *dev)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + struct imx_se_node_info_list *info_list;
> > + const struct imx_se_node_info *info;
> > + struct soc_device_attribute *attr;
> > + struct soc_device *sdev;
> > + struct soc_info s_info;
> > + int err = 0;
> > +
> > + info = priv->info;
> > + info_list = (struct imx_se_node_info_list *)
> > + device_get_match_data(dev->parent);
> > + if (info_list->soc_rev)
> > + return err;
> > +
> > + err = ele_get_info(dev, &s_info);
> > + if (err)
> > + s_info.major_ver = DEFAULT_IMX_SOC_VER;
> > +
> > + info_list->soc_rev = s_info.soc_rev;
> > +
> > + if (!info->soc_register)
> > + return 0;
> > +
> > + attr = devm_kzalloc(dev, sizeof(*attr), GFP_KERNEL);
> > + if (!attr)
> > + return -ENOMEM;
> > +
> > + if (s_info.minor_ver)
> > + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x.%x",
> > + s_info.major_ver,
> > + s_info.minor_ver);
> > + else
> > + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x",
> > + s_info.major_ver);
> > +
> > + switch (s_info.soc_id) {
> > + case SOC_ID_OF_IMX8ULP:
> > + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> > + "i.MX8ULP");
> > + break;
> > + case SOC_ID_OF_IMX93:
> > + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> > + "i.MX93");
> > + break;
> > + }
> > +
> > + err = of_property_read_string(of_root, "model",
> > + &attr->machine);
> > + if (err) {
> > + devm_kfree(dev, attr);
> > + return -EINVAL;
> > + }
> > + attr->family = devm_kasprintf(dev, GFP_KERNEL, "Freescale i.MX");
> > +
> > + attr->serial_number
> > + = devm_kasprintf(dev, GFP_KERNEL, "%016llX", s_info.serial_num);
> > +
> > + sdev = soc_device_register(attr);
> > + if (IS_ERR(sdev)) {
> > + devm_kfree(dev, attr->soc_id);
> > + devm_kfree(dev, attr->serial_number);
> > + devm_kfree(dev, attr->revision);
> > + devm_kfree(dev, attr->family);
> > + devm_kfree(dev, attr->machine);
> > + devm_kfree(dev, attr);
> > + return PTR_ERR(sdev);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * File operations for user-space
> > + */
> > +
> > +/* Write a message to the MU. */
> > +static ssize_t se_if_fops_write(struct file *fp, const char __user *buf,
> > + size_t size, loff_t *ppos)
> > +{
> > + struct se_api_msg *tx_msg __free(kfree);
> > + struct se_if_device_ctx *dev_ctx;
> > + struct se_if_priv *priv;
> > + int err;
> > +
> > + dev_ctx = container_of(fp->private_data,
> > + struct se_if_device_ctx,
> > + miscdev);
> > + priv = dev_ctx->priv;
> > + dev_dbg(priv->dev,
> > + "%s: write from buf (%p)%zu, ppos=%lld\n",
> > + dev_ctx->miscdev.name,
> > + buf, size, ((ppos) ? *ppos : 0));
> > +
> > + if (down_interruptible(&dev_ctx->fops_lock))
> > + return -EBUSY;
> > +
> > + if (dev_ctx->status != MU_OPENED) {
> > + err = -EINVAL;
> > + goto exit;
> > + }
> > +
> > + if (size < SE_MU_HDR_SZ) {
> > + dev_err(priv->dev,
> > + "%s: User buffer too small(%zu < %d)\n",
> > + dev_ctx->miscdev.name,
> > + size, SE_MU_HDR_SZ);
> > + err = -ENOSPC;
> > + goto exit;
> > + }
> > +
> > + tx_msg = memdup_user((void __user *)ppos, size);
> > + if (!tx_msg) {
> > + err = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > + /* Copy data to buffer */
> > + if (copy_from_user(tx_msg, buf, size)) {
> > + err = -EFAULT;
> > + dev_err(priv->dev,
> > + "%s: Fail copy message from user\n",
> > + dev_ctx->miscdev.name);
> > + goto exit;
> > + }
> > +
> > + print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4,
> > + tx_msg, size, false);
> > +
> > + err = imx_ele_miscdev_msg_send(dev_ctx, tx_msg, size);
> > +
> > +exit:
> > + up(&dev_ctx->fops_lock);
> > + return err;
> > +}
> > +
> > +/*
> > + * Read a message from the MU.
> > + * Blocking until a message is available.
> > + */
> > +static ssize_t se_if_fops_read(struct file *fp, char __user *buf,
> > + size_t size, loff_t *ppos)
> > +{
> > + struct se_if_device_ctx *dev_ctx;
> > + struct se_buf_desc *b_desc;
> > + struct se_if_priv *priv;
> > + u32 size_to_copy;
> > + int err;
> > +
> > + dev_ctx = container_of(fp->private_data,
> > + struct se_if_device_ctx,
> > + miscdev);
> > + priv = dev_ctx->priv;
> > + dev_dbg(priv->dev,
> > + "%s: read to buf %p(%zu), ppos=%lld\n",
> > + dev_ctx->miscdev.name,
> > + buf, size, ((ppos) ? *ppos : 0));
> > +
> > + if (down_interruptible(&dev_ctx->fops_lock))
> > + return -EBUSY;
> > +
> > + if (dev_ctx->status != MU_OPENED) {
> > + err = -EINVAL;
> > + goto exit;
> > + }
> > +
> > + err = imx_ele_miscdev_msg_rcv(dev_ctx);
> > + if (err)
> > + goto exit;
> > +
> > + /* Buffer containing the message from FW, is
> > + * allocated in callback function.
> > + * Check if buffer allocation failed.
> > + */
> > + if (!dev_ctx->temp_resp) {
> > + err = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > + dev_dbg(priv->dev,
> > + "%s: %s %s\n",
> > + dev_ctx->miscdev.name,
> > + __func__,
> > + "message received, start transmit to user");
> > +
> > + /*
> > + * Check that the size passed as argument is larger than
> > + * the one carried in the message.
> > + */
> > + size_to_copy = dev_ctx->temp_resp_size << 2;
> > + if (size_to_copy > size) {
> > + dev_dbg(priv->dev,
> > + "%s: User buffer too small (%zu < %d)\n",
> > + dev_ctx->miscdev.name,
> > + size, size_to_copy);
> > + size_to_copy = size;
> > + }
> > +
> > + /*
> > + * We may need to copy the output data to user before
> > + * delivering the completion message.
> > + */
> > + while (!list_empty(&dev_ctx->pending_out)) {
> > + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> > + struct se_buf_desc,
> > + link);
> > + if (!b_desc)
> > + continue;
> > +
> > + if (b_desc->usr_buf_ptr && b_desc->shared_buf_ptr) {
> > +
> > + dev_dbg(priv->dev,
> > + "%s: Copy output data to user\n",
> > + dev_ctx->miscdev.name);
> > + if (copy_to_user(b_desc->usr_buf_ptr,
> > + b_desc->shared_buf_ptr,
> > + b_desc->size)) {
> > + dev_err(priv->dev,
> > + "%s: Failure copying output data to user.",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > + }
> > +
> > + if (b_desc->shared_buf_ptr)
> > + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> > +
> > + __list_del_entry(&b_desc->link);
> > + kfree(b_desc);
> > + }
> > +
> > + /* Copy data from the buffer */
> > + print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4,
> > + dev_ctx->temp_resp, size_to_copy, false);
> > + if (copy_to_user(buf, dev_ctx->temp_resp, size_to_copy)) {
> > + dev_err(priv->dev,
> > + "%s: Failed to copy to user\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > +
> > + err = size_to_copy;
> > + kfree(dev_ctx->temp_resp);
> > +
> > + /* free memory allocated on the shared buffers. */
> > + dev_ctx->secure_mem.pos = 0;
> > + dev_ctx->non_secure_mem.pos = 0;
> > +
> > + dev_ctx->pending_hdr = 0;
> > +
> > +exit:
> > + /*
> > + * Clean the used Shared Memory space,
> > + * whether its Input Data copied from user buffers, or
> > + * Data received from FW.
> > + */
> > + while (!list_empty(&dev_ctx->pending_in) ||
> > + !list_empty(&dev_ctx->pending_out)) {
> > + if (!list_empty(&dev_ctx->pending_in))
> > + b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
> > + struct se_buf_desc,
> > + link);
> > + else
> > + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> > + struct se_buf_desc,
> > + link);
> > +
> > + if (!b_desc)
> > + continue;
> > +
> > + if (b_desc->shared_buf_ptr)
> > + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> > +
> > + __list_del_entry(&b_desc->link);
> > + kfree(b_desc);
> > + }
> > +
> > + up(&dev_ctx->fops_lock);
> > + return err;
> > +}
> > +
> > +/* Give access to EdgeLock Enclave, to the memory we want to share */
> > +static int se_if_setup_se_mem_access(struct se_if_device_ctx *dev_ctx,
> > + u64 addr, u32 len)
> > +{
> > + /* Assuming EdgeLock Enclave has access to all the memory regions */
> > + int ret = 0;
> > +
> > + if (ret) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Fail find memreg\n", dev_ctx->miscdev.name);
> > + goto exit;
> > + }
> > +
> > + if (ret) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Fail set permission for resource\n",
> > + dev_ctx->miscdev.name);
> > + goto exit;
> > + }
> > +
> > +exit:
> > + return ret;
> > +}
> > +
> > +static int se_ioctl_get_mu_info(struct se_if_device_ctx *dev_ctx,
> > + u64 arg)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev_ctx->dev);
> > + struct imx_se_node_info *if_node_info;
> > + struct se_ioctl_get_if_info info;
> > + int err = 0;
> > +
> > + if_node_info = (struct imx_se_node_info *)priv->info;
> > +
> > + info.se_if_id = if_node_info->se_if_id;
> > + info.interrupt_idx = 0;
> > + info.tz = 0;
> > + info.did = if_node_info->se_if_did;
> > + info.cmd_tag = if_node_info->cmd_tag;
> > + info.rsp_tag = if_node_info->rsp_tag;
> > + info.success_tag = if_node_info->success_tag;
> > + info.base_api_ver = if_node_info->base_api_ver;
> > + info.fw_api_ver = if_node_info->fw_api_ver;
> > +
> > + dev_dbg(priv->dev,
> > + "%s: info [se_if_id: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n",
> > + dev_ctx->miscdev.name,
> > + info.se_if_id, info.interrupt_idx, info.tz, info.did);
> > +
> > + if (copy_to_user((u8 *)arg, &info, sizeof(info))) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed to copy mu info to user\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > +
> > +exit:
> > + return err;
> > +}
> > +
> > +/*
> > + * Copy a buffer of data to/from the user and return the address to use in
> > + * messages
> > + */
> > +static int se_ioctl_setup_iobuf_handler(struct se_if_device_ctx *dev_ctx,
> > + u64 arg)
> > +{
> > + struct se_ioctl_setup_iobuf io = {0};
> > + struct se_shared_mem *shared_mem;
> > + struct se_buf_desc *b_desc;
> > + int err = 0;
> > + u32 pos;
> > +
> > + if (copy_from_user(&io, (u8 *)arg, sizeof(io))) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed copy iobuf config from user\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > +
> > + dev_dbg(dev_ctx->priv->dev,
> > + "%s: io [buf: %p(%d) flag: %x]\n",
> > + dev_ctx->miscdev.name,
> > + io.user_buf, io.length, io.flags);
> > +
> > + if (io.length == 0 || !io.user_buf) {
> > + /*
> > + * Accept NULL pointers since some buffers are optional
> > + * in FW commands. In this case we should return 0 as
> > + * pointer to be embedded into the message.
> > + * Skip all data copy part of code below.
> > + */
> > + io.ele_addr = 0;
> > + goto copy;
> > + }
> > +
> > + /* Select the shared memory to be used for this buffer. */
> > + if (io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) {
> > + /* App requires to use secure memory for this buffer.*/
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed allocate SEC MEM memory\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + } else {
> > + /* No specific requirement for this buffer. */
> > + shared_mem = &dev_ctx->non_secure_mem;
> > + }
> > +
> > + /* Check there is enough space in the shared memory. */
> > + if (shared_mem->size < shared_mem->pos
> > + || io.length >= shared_mem->size - shared_mem->pos) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Not enough space in shared memory\n",
> > + dev_ctx->miscdev.name);
> > + err = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > + /* Allocate space in shared memory. 8 bytes aligned. */
> > + pos = shared_mem->pos;
> > + shared_mem->pos += round_up(io.length, 8u);
> > + io.ele_addr = (u64)shared_mem->dma_addr + pos;
> > +
> > + if ((io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) &&
> > + !(io.flags & SE_MU_IO_FLAGS_USE_SHORT_ADDR)) {
> > + /*Add base address to get full address.*/
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed allocate SEC MEM memory\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > +
> > + memset(shared_mem->ptr + pos, 0, io.length);
> > + if ((io.flags & SE_IO_BUF_FLAGS_IS_INPUT) ||
> > + (io.flags & SE_IO_BUF_FLAGS_IS_IN_OUT)) {
> > + /*
> > + * buffer is input:
> > + * copy data from user space to this allocated buffer.
> > + */
> > + if (copy_from_user(shared_mem->ptr + pos, io.user_buf,
> > + io.length)) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed copy data to shared memory\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > + }
> > +
> > + b_desc = kzalloc(sizeof(*b_desc), GFP_KERNEL);
> > + if (!b_desc) {
> > + err = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > +copy:
> > + /* Provide the EdgeLock Enclave address to user space only if success.*/
> > + if (copy_to_user((u8 *)arg, &io, sizeof(io))) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed to copy iobuff setup to user\n",
> > + dev_ctx->miscdev.name);
> > + kfree(b_desc);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > +
> > + if (b_desc) {
> > + b_desc->shared_buf_ptr = shared_mem->ptr + pos;
> > + b_desc->usr_buf_ptr = io.user_buf;
> > + b_desc->size = io.length;
> > +
> > + if (io.flags & SE_IO_BUF_FLAGS_IS_INPUT) {
> > + /*
> > + * buffer is input:
> > + * add an entry in the "pending input buffers" list so
> > + * that copied data can be cleaned from shared memory
> > + * later.
> > + */
> > + list_add_tail(&b_desc->link, &dev_ctx->pending_in);
> > + } else {
> > + /*
> > + * buffer is output:
> > + * add an entry in the "pending out buffers" list so data
> > + * can be copied to user space when receiving Secure-Enclave
> > + * response.
> > + */
> > + list_add_tail(&b_desc->link, &dev_ctx->pending_out);
> > + }
> > + }
> > +
> > +exit:
> > + return err;
> > +}
> > +
> > +/* IOCTL to provide SoC information */
> > +static int se_ioctl_get_soc_info_handler(struct se_if_device_ctx *dev_ctx,
> > + u64 arg)
> > +{
> > + struct imx_se_node_info_list *info_list;
> > + struct se_ioctl_get_soc_info soc_info;
> > + int err = -EINVAL;
> > +
> > + info_list = (struct imx_se_node_info_list *)
> > + device_get_match_data(dev_ctx->priv->dev->parent);
> > + if (!info_list)
> > + goto exit;
> > +
> > + soc_info.soc_id = info_list->soc_id;
> > + soc_info.soc_rev = info_list->soc_rev;
> > +
> > + err = (int)copy_to_user((u8 *)arg, (u8 *)(&soc_info), sizeof(soc_info));
> > + if (err) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed to copy soc info to user\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > +
> > +exit:
> > + return err;
> > +}
> > +
> > +/* Open a character device. */
> > +static int se_if_fops_open(struct inode *nd, struct file *fp)
> > +{
> > + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> > + struct se_if_device_ctx,
> > + miscdev);
> > + int err;
> > +
> > + /* Avoid race if opened at the same time */
> > + if (down_trylock(&dev_ctx->fops_lock))
> > + return -EBUSY;
> > +
> > + /* Authorize only 1 instance. */
> > + if (dev_ctx->status != MU_FREE) {
> > + err = -EBUSY;
> > + goto exit;
> > + }
> > +
> > + /*
> > + * Allocate some memory for data exchanges with S40x.
> > + * This will be used for data not requiring secure memory.
> > + */
> > + dev_ctx->non_secure_mem.ptr = dmam_alloc_coherent(dev_ctx->dev,
> > + MAX_DATA_SIZE_PER_USER,
> > + &dev_ctx->non_secure_mem.dma_addr,
> > + GFP_KERNEL);
> > + if (!dev_ctx->non_secure_mem.ptr) {
> > + err = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > + err = se_if_setup_se_mem_access(dev_ctx,
> > + dev_ctx->non_secure_mem.dma_addr,
> > + MAX_DATA_SIZE_PER_USER);
> > + if (err) {
> > + err = -EPERM;
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed to share access to shared memory\n",
> > + dev_ctx->miscdev.name);
> > + goto free_coherent;
> > + }
> > +
> > + dev_ctx->non_secure_mem.size = MAX_DATA_SIZE_PER_USER;
> > + dev_ctx->non_secure_mem.pos = 0;
> > + dev_ctx->status = MU_OPENED;
> > +
> > + dev_ctx->pending_hdr = 0;
> > +
> > + goto exit;
> > +
> > +free_coherent:
> > + dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
> > + dev_ctx->non_secure_mem.ptr,
> > + dev_ctx->non_secure_mem.dma_addr);
> > +
> > +exit:
> > + up(&dev_ctx->fops_lock);
> > + return err;
> > +}
> > +
> > +/* Close a character device. */
> > +static int se_if_fops_close(struct inode *nd, struct file *fp)
> > +{
> > + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> > + struct se_if_device_ctx,
> > + miscdev);
> > + struct se_if_priv *priv = dev_ctx->priv;
> > + struct se_buf_desc *b_desc;
> > +
> > + /* Avoid race if closed at the same time */
> > + if (down_trylock(&dev_ctx->fops_lock))
> > + return -EBUSY;
> > +
> > + /* The device context has not been opened */
> > + if (dev_ctx->status != MU_OPENED)
> > + goto exit;
> > +
> > + /* check if this device was registered as command receiver. */
> > + if (priv->cmd_receiver_dev == dev_ctx)
> > + priv->cmd_receiver_dev = NULL;
> > +
> > + /* check if this device was registered as waiting response. */
> > + if (priv->waiting_rsp_dev == dev_ctx) {
> > + priv->waiting_rsp_dev = NULL;
> > + mutex_unlock(&priv->se_if_cmd_lock);
> > + }
> > +
> > + /* Unmap secure memory shared buffer. */
> > + if (dev_ctx->secure_mem.ptr)
> > + devm_iounmap(dev_ctx->dev, dev_ctx->secure_mem.ptr);
> > +
> > + dev_ctx->secure_mem.ptr = NULL;
> > + dev_ctx->secure_mem.dma_addr = 0;
> > + dev_ctx->secure_mem.size = 0;
> > + dev_ctx->secure_mem.pos = 0;
> > +
> > + /* Free non-secure shared buffer. */
> > + dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
> > + dev_ctx->non_secure_mem.ptr,
> > + dev_ctx->non_secure_mem.dma_addr);
> > +
> > + dev_ctx->non_secure_mem.ptr = NULL;
> > + dev_ctx->non_secure_mem.dma_addr = 0;
> > + dev_ctx->non_secure_mem.size = 0;
> > + dev_ctx->non_secure_mem.pos = 0;
> > +
> > + while (!list_empty(&dev_ctx->pending_in) ||
> > + !list_empty(&dev_ctx->pending_out)) {
> > + if (!list_empty(&dev_ctx->pending_in))
> > + b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
> > + struct se_buf_desc,
> > + link);
> > + else
> > + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> > + struct se_buf_desc,
> > + link);
> > +
> > + if (!b_desc)
> > + continue;
> > +
> > + if (b_desc->shared_buf_ptr)
> > + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> > +
> > + __list_del_entry(&b_desc->link);
> > + devm_kfree(dev_ctx->dev, b_desc);
> > + }
> > +
> > + dev_ctx->status = MU_FREE;
> > +
> > +exit:
> > + up(&dev_ctx->fops_lock);
> > + return 0;
> > +}
> > +
> > +/* IOCTL entry point of a character device */
> > +static long se_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
> > +//static long se_ioctl(struct file *fp, u32 cmd, u64 arg)
> > +{
> > + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> > + struct se_if_device_ctx,
> > + miscdev);
> > + struct se_if_priv *se_if_priv = dev_ctx->priv;
> > + int err = -EINVAL;
> > +
> > + /* Prevent race during change of device context */
> > + if (down_interruptible(&dev_ctx->fops_lock))
> > + return -EBUSY;
> > +
> > + switch (cmd) {
> > + case SE_IOCTL_ENABLE_CMD_RCV:
> > + if (!se_if_priv->cmd_receiver_dev) {
> > + se_if_priv->cmd_receiver_dev = dev_ctx;
> > + err = 0;
> > + }
> > + break;
> > + case SE_IOCTL_GET_MU_INFO:
> > + err = se_ioctl_get_mu_info(dev_ctx, arg);
> > + break;
> > + case SE_IOCTL_SETUP_IOBUF:
> > + err = se_ioctl_setup_iobuf_handler(dev_ctx, arg);
> > + break;
> > + case SE_IOCTL_GET_SOC_INFO:
> > + err = se_ioctl_get_soc_info_handler(dev_ctx, arg);
> > + break;
> > +
> > + default:
> > + err = -EINVAL;
> > + dev_dbg(se_if_priv->dev,
> > + "%s: IOCTL %.8x not supported\n",
> > + dev_ctx->miscdev.name,
> > + cmd);
> > + }
> > +
> > + up(&dev_ctx->fops_lock);
> > + return (long)err;
> > +}
> > +
> > +/* Char driver setup */
> > +static const struct file_operations se_if_fops = {
> > + .open = se_if_fops_open,
> > + .owner = THIS_MODULE,
> > + .release = se_if_fops_close,
> > + .unlocked_ioctl = se_ioctl,
> > + .read = se_if_fops_read,
> > + .write = se_if_fops_write,
> > +};
> > +
> > +/* interface for managed res to free a mailbox channel */
> > +static void if_mbox_free_channel(void *mbox_chan)
> > +{
> > + mbox_free_channel(mbox_chan);
> > +}
> > +
> > +/* interface for managed res to unregister a character device */
> > +static void if_misc_deregister(void *miscdevice)
> > +{
> > + misc_deregister(miscdevice);
> > +}
> > +
> > +static int se_if_request_channel(struct device *dev,
> > + struct mbox_chan **chan,
> > + struct mbox_client *cl,
> > + const u8 *name)
> > +{
> > + struct mbox_chan *t_chan;
> > + int ret = 0;
> > +
> > + t_chan = mbox_request_channel_byname(cl, name);
> > + if (IS_ERR(t_chan)) {
> > + ret = PTR_ERR(t_chan);
> > + if (ret != -EPROBE_DEFER)
> > + dev_err(dev,
> > + "Failed to request chan %s ret %d\n", name,
> > + ret);
> > + goto exit;
> > + }
> > +
> > + ret = devm_add_action(dev, if_mbox_free_channel, t_chan);
> > + if (ret) {
> > + dev_err(dev, "failed to add devm removal of mbox %s\n", name);
> > + goto exit;
> > + }
> > +
> > + *chan = t_chan;
> > +
> > +exit:
> > + return ret;
> > +}
> > +
> > +static int se_probe_if_cleanup(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct se_if_priv *priv;
> > + int ret = 0;
> > + int i;
> > +
> > + priv = dev_get_drvdata(dev);
> > + if (!priv) {
> > + ret = 0;
> > + dev_dbg(dev, "SE-MU Priv data is NULL;");
> > + return ret;
> > + }
> > +
> > + if (priv->tx_chan)
> > + mbox_free_channel(priv->tx_chan);
> > + if (priv->rx_chan)
> > + mbox_free_channel(priv->rx_chan);
> > +
> > + /* free the buffer in se remove, previously allocated
> > + * in se probe to store encrypted IMEM
> > + */
> > + if (priv->imem.buf) {
> > + dmam_free_coherent(dev,
> > + ELE_IMEM_SIZE,
> > + priv->imem.buf,
> > + priv->imem.phyaddr);
> > + priv->imem.buf = NULL;
> > + }
> > +
> > + if (priv->ctxs) {
> > + for (i = 0; i < priv->max_dev_ctx; i++) {
> > + if (priv->ctxs[i]) {
> > + devm_remove_action(dev,
> > + if_misc_deregister,
> > + &priv->ctxs[i]->miscdev);
> > + misc_deregister(&priv->ctxs[i]->miscdev);
> > + devm_kfree(dev, priv->ctxs[i]);
> > + }
> > + }
> > + devm_kfree(dev, priv->ctxs);
> > + }
> > +
> > + if (priv->flags & RESERVED_DMA_POOL) {
> > + of_reserved_mem_device_release(dev);
> > + priv->flags &= (~RESERVED_DMA_POOL);
> > + }
> > +
> > + devm_kfree(dev, priv);
> > + of_node_put(dev->of_node);
> > + of_platform_device_destroy(dev, NULL);
> > +
> > + return ret;
> > +}
> > +
> > +static int se_probe_cleanup(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *if_dn;
> > +
> > + /* Enumerate se-interface device nodes. */
> > + for_each_child_of_node(dev->of_node, if_dn) {
> > + struct platform_device *if_pdev
> > + = of_find_device_by_node(if_dn);
> > + if (se_probe_if_cleanup(if_pdev))
> > + dev_err(dev,
> > + "Failed to clean-up child node probe.\n");
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int init_device_context(struct device *dev)
> > +{
> > + const struct imx_se_node_info *info;
> > + struct se_if_device_ctx *dev_ctx;
> > + struct se_if_priv *priv;
> > + u8 *devname;
> > + int ret = 0;
> > + int i;
> > +
> > + priv = dev_get_drvdata(dev);
> > +
> > + if (!priv) {
> > + ret = -EINVAL;
> > + dev_err(dev, "Invalid SE-MU Priv data");
> > + return ret;
> > + }
> > + info = priv->info;
> > +
> > + priv->ctxs = devm_kzalloc(dev, sizeof(dev_ctx) * priv->max_dev_ctx,
> > + GFP_KERNEL);
> > +
> > + if (!priv->ctxs) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + /* Create users */
> > + for (i = 0; i < priv->max_dev_ctx; i++) {
> > + dev_ctx = devm_kzalloc(dev, sizeof(*dev_ctx), GFP_KERNEL);
> > + if (!dev_ctx) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + dev_ctx->dev = dev;
> > + dev_ctx->status = MU_FREE;
> > + dev_ctx->priv = priv;
> > +
> > + priv->ctxs[i] = dev_ctx;
> > +
> > + /* Default value invalid for an header. */
> > + init_waitqueue_head(&dev_ctx->wq);
> > +
> > + INIT_LIST_HEAD(&dev_ctx->pending_out);
> > + INIT_LIST_HEAD(&dev_ctx->pending_in);
> > + sema_init(&dev_ctx->fops_lock, 1);
> > +
> > + devname = devm_kasprintf(dev, GFP_KERNEL, "%s_ch%d",
> > + info->se_name, i);
> > + if (!devname) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + dev_ctx->miscdev.name = devname;
> > + dev_ctx->miscdev.minor = MISC_DYNAMIC_MINOR;
> > + dev_ctx->miscdev.fops = &se_if_fops;
> > + dev_ctx->miscdev.parent = dev;
> > + ret = misc_register(&dev_ctx->miscdev);
> > + if (ret) {
> > + dev_err(dev, "failed to register misc device %d\n",
> > + ret);
> > + return ret;
> > + }
> > +
> > + ret = devm_add_action(dev, if_misc_deregister,
> > + &dev_ctx->miscdev);
> > + if (ret) {
> > + dev_err(dev,
> > + "failed[%d] to add action to the misc-dev\n",
> > + ret);
> > + return ret;
> > + }
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static void se_load_firmware(const struct firmware *fw, void *context)
> > +{
> > + struct se_if_priv *priv = (struct se_if_priv *) context;
> > + const struct imx_se_node_info *info = priv->info;
> > + const u8 *se_fw_name = info->fw_name_in_rfs;
> > + phys_addr_t se_fw_phyaddr;
> > + u8 *se_fw_buf;
> > +
> > + if (!fw) {
> > + if (priv->fw_fail > MAX_FW_LOAD_RETRIES)
> > + dev_dbg(priv->dev,
> > + "External FW not found, using ROM FW.\n");
> > + else {
> > + /*add a bit delay to wait for firmware priv released */
> > + msleep(20);
> > +
> > + /* Load firmware one more time if timeout */
> > + request_firmware_nowait(THIS_MODULE,
> > + FW_ACTION_UEVENT, info->fw_name_in_rfs,
> > + priv->dev, GFP_KERNEL, priv,
> > + se_load_firmware);
> > + priv->fw_fail++;
> > + dev_dbg(priv->dev, "Value of retries = 0x%x.\n",
> > + priv->fw_fail);
> > + }
> > +
> > + return;
> > + }
> > +
> > + /* allocate buffer to store the SE FW */
> > + se_fw_buf = dmam_alloc_coherent(priv->dev, fw->size,
> > + &se_fw_phyaddr,
> > + GFP_KERNEL);
> > + if (!se_fw_buf) {
> > + dev_err(priv->dev, "Failed to alloc SE fw buffer memory\n");
> > + goto exit;
> > + }
> > +
> > + memcpy(se_fw_buf, fw->data, fw->size);
> > +
> > + if (ele_fw_authenticate(priv->dev, se_fw_phyaddr))
> > + dev_err(priv->dev,
> > + "Failed to authenticate & load SE firmware %s.\n",
> > + se_fw_name);
> > +
> > +exit:
> > + dmam_free_coherent(priv->dev,
> > + fw->size,
> > + se_fw_buf,
> > + se_fw_phyaddr);
> > +
> > + release_firmware(fw);
> > +}
> > +
> > +static int se_if_probe(struct platform_device *pdev)
> > +{
> > + struct imx_se_node_info_list *info_list;
> > + struct device *dev = &pdev->dev;
> > + struct imx_se_node_info *info;
> > + struct se_if_priv *priv;
> > + u32 idx;
> > + int ret;
> > +
> > + if (of_property_read_u32(dev->of_node, "reg", &idx)) {
> > + ret = -EINVAL;
> > + goto exit;
> > + }
> > +
> > + info_list = (struct imx_se_node_info_list *)
> > + device_get_match_data(dev->parent);
> > + info = get_imx_se_node_info(info_list, idx);
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv) {
> > + ret = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > + dev_set_drvdata(dev, priv);
> > +
> > + /* Mailbox client configuration */
> > + priv->se_mb_cl.dev = dev;
> > + priv->se_mb_cl.tx_block = false;
> > + priv->se_mb_cl.knows_txdone = true;
> > + priv->se_mb_cl.rx_callback = se_if_rx_callback;
> > +
> > + ret = se_if_request_channel(dev, &priv->tx_chan,
> > + &priv->se_mb_cl, info->mbox_tx_name);
> > + if (ret) {
> > + if (ret == -EPROBE_DEFER)
> > + dev_err(dev, "Mailbox tx channel, is not ready.\n");
> > + else
> > + dev_err(dev, "Failed to request tx channel\n");
> > +
> > + goto exit;
> > + }
> > +
> > + ret = se_if_request_channel(dev, &priv->rx_chan,
> > + &priv->se_mb_cl, info->mbox_rx_name);
> > + if (ret) {
> > + if (ret == -EPROBE_DEFER)
> > + dev_err(dev, "Mailbox rx channel, is not ready.\n");
> > + else
> > + dev_dbg(dev, "Failed to request rx channel\n");
> > +
> > + goto exit;
> > + }
> > +
> > + priv->dev = dev;
> > + priv->info = info;
> > +
> > + /* Initialize the mutex. */
> > + mutex_init(&priv->se_if_lock);
> > + mutex_init(&priv->se_if_cmd_lock);
> > +
> > + priv->cmd_receiver_dev = NULL;
> > + priv->waiting_rsp_dev = NULL;
> > + priv->max_dev_ctx = info->max_dev_ctx;
> > + priv->cmd_tag = info->cmd_tag;
> > + priv->rsp_tag = info->rsp_tag;
> > + priv->mem_pool_name = info->pool_name;
> > + priv->success_tag = info->success_tag;
> > + priv->base_api_ver = info->base_api_ver;
> > + priv->fw_api_ver = info->fw_api_ver;
> > +
> > + init_completion(&priv->done);
> > + spin_lock_init(&priv->lock);
> > +
> > + if (info->reserved_dma_ranges) {
> > + ret = of_reserved_mem_device_init(dev);
> > + if (ret) {
> > + dev_err(dev,
> > + "failed to init reserved memory region %d\n",
> > + ret);
> > + priv->flags &= (~RESERVED_DMA_POOL);
> > + goto exit;
> > + }
> > + priv->flags |= RESERVED_DMA_POOL;
> > + }
> > +
> > + if (info->fw_name_in_rfs) {
> > + ret = request_firmware_nowait(THIS_MODULE,
> > + FW_ACTION_UEVENT,
> > + info->fw_name_in_rfs,
> > + dev, GFP_KERNEL, priv,
> > + se_load_firmware);
> > + if (ret)
> > + dev_warn(dev, "Failed to get firmware [%s].\n",
> > + info->fw_name_in_rfs);
> > + }
> > +
> > + ret = imx_fetch_soc_info(dev);
> > + if (ret) {
> > + dev_err(dev,
> > + "failed[%d] to fetch SoC Info\n", ret);
> > + goto exit;
> > + }
> > +
> > + if (info->imem_mgmt) {
> > + /* allocate buffer where SE store encrypted IMEM */
> > + priv->imem.buf = dmam_alloc_coherent(dev, ELE_IMEM_SIZE,
> > + &priv->imem.phyaddr,
> > + GFP_KERNEL);
> > + if (!priv->imem.buf) {
> > + dev_err(dev,
> > + "dmam-alloc-failed: To store encr-IMEM.\n");
> > + ret = -ENOMEM;
> > + goto exit;
> > + }
> > + }
> > +
> > + if (info->max_dev_ctx) {
> > + ret = init_device_context(dev);
> > + if (ret) {
> > + dev_err(dev,
> > + "Failed[0x%x] to create device contexts.\n",
> > + ret);
> > + goto exit;
> > + }
> > + }
> > +
> > + dev_info(dev, "i.MX secure-enclave: %s interface to firmware,
> configured.\n",
> > + info->se_name);
> > + return devm_of_platform_populate(dev);
> > +
> > +exit:
> > + /* if execution control reaches here, if probe fails.
> > + * hence doing the cleanup
> > + */
> > + if (se_probe_if_cleanup(pdev))
> > + dev_err(dev,
> > + "Failed to clean-up the child node probe.\n");
> > +
> > + return ret;
> > +}
> > +
> > +static int se_probe(struct platform_device *pdev)
> > +{
> > + struct device_node *enum_dev_node;
> > + struct device *dev = &pdev->dev;
> > + int enum_count;
> > + int ret;
> > +
> > + enum_count = of_get_child_count(dev->of_node);
> > + if (!enum_count) {
> > + ret = -EINVAL;
> > + dev_err(dev, "Zero Tx/Rx path MU nodes.\n");
> > + return ret;
> > + }
> > +
> > + for_each_child_of_node(dev->of_node, enum_dev_node) {
> > + struct platform_device *enum_plat_dev __maybe_unused;
> > +
> > + if (!of_device_is_available(enum_dev_node))
> > + continue;
> > +
> > + enum_plat_dev = of_platform_device_create(enum_dev_node,
> > + NULL,
> > + dev);
> > + if (!enum_plat_dev) {
> > + ret = -EINVAL;
> > + of_node_put(enum_dev_node);
> > + dev_err(dev,
> > + "Failed to create enumerated platform device.");
> > + break;
> > + }
> > +
> > + ret = se_if_probe(enum_plat_dev);
> > + }
> > + return ret;
> > +}
> > +
> > +static int se_remove(struct platform_device *pdev)
> > +{
> > + if (se_probe_cleanup(pdev))
> > + dev_err(&pdev->dev,
> > + "i.MX Secure Enclave is not cleanly un-probed.");
> > +
> > + return 0;
> > +}
> > +
> > +static int se_suspend(struct device *dev)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + const struct imx_se_node_info *info
> > + = priv->info;
> > +
> > + if (info && info->imem_mgmt)
> > + priv->imem.size = se_save_imem_state(dev);
> > +
> > + return 0;
> > +}
> > +
> > +static int se_resume(struct device *dev)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + const struct imx_se_node_info *info
> > + = priv->info;
> > + int i;
> > +
> > + for (i = 0; i < priv->max_dev_ctx; i++)
> > + wake_up_interruptible(&priv->ctxs[i]->wq);
> > +
> > + if (info && info->imem_mgmt)
> > + se_restore_imem_state(dev);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct dev_pm_ops se_pm = {
> > + RUNTIME_PM_OPS(se_suspend, se_resume, NULL)
> > +};
> > +
> > +static struct platform_driver se_driver = {
> > + .driver = {
> > + .name = "fsl-se-fw",
> > + .of_match_table = se_match,
> > + .pm = &se_pm,
> > + },
> > + .probe = se_probe,
> > + .remove = se_remove,
> > +};
> > +MODULE_DEVICE_TABLE(of, se_match);
> > +
> > +module_platform_driver(se_driver);
> > +
> > +MODULE_AUTHOR("Pankaj Gupta <pankaj.gupta@nxp.com>");
> > +MODULE_DESCRIPTION("iMX Secure Enclave Driver.");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/firmware/imx/se_ctrl.h b/drivers/firmware/imx/se_ctrl.h
> > new file mode 100644
> > index 000000000000..76e1ce77c52f
> > --- /dev/null
> > +++ b/drivers/firmware/imx/se_ctrl.h
> > @@ -0,0 +1,151 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#ifndef SE_MU_H
> > +#define SE_MU_H
> > +
> > +#include <linux/miscdevice.h>
> > +#include <linux/semaphore.h>
> > +#include <linux/mailbox_client.h>
> > +
> > +#define MAX_FW_LOAD_RETRIES 50
> > +
> > +#define MSG_TAG(x) (((x) & 0xff000000) >> 24)
> > +#define MSG_COMMAND(x) (((x) & 0x00ff0000) >> 16)
> > +#define MSG_SIZE(x) (((x) & 0x0000ff00) >> 8)
> > +#define MSG_VER(x) ((x) & 0x000000ff)
> > +#define RES_STATUS(x) ((x) & 0x000000ff)
> > +#define MAX_DATA_SIZE_PER_USER (65 * 1024)
> > +#define S4_DEFAULT_MUAP_INDEX (2)
> > +#define S4_MUAP_DEFAULT_MAX_USERS (4)
> > +#define MESSAGING_VERSION_6 0x6
> > +#define MESSAGING_VERSION_7 0x7
> > +
> > +#define DEFAULT_MESSAGING_TAG_COMMAND (0x17u)
> > +#define DEFAULT_MESSAGING_TAG_RESPONSE (0xe1u)
> > +
> > +#define SE_MU_IO_FLAGS_USE_SEC_MEM (0x02u)
> > +#define SE_MU_IO_FLAGS_USE_SHORT_ADDR (0x04u)
> > +
> > +struct se_imem_buf {
> > + u8 *buf;
> > + phys_addr_t phyaddr;
> > + u32 size;
> > +};
> > +
> > +struct se_buf_desc {
> > + u8 *shared_buf_ptr;
> > + u8 *usr_buf_ptr;
> > + u32 size;
> > + struct list_head link;
> > +};
> > +
> > +/* Status of a char device */
> > +enum se_if_dev_ctx_status_t {
> > + MU_FREE,
> > + MU_OPENED
> > +};
> > +
> > +struct se_shared_mem {
> > + dma_addr_t dma_addr;
> > + u32 size;
> > + u32 pos;
> > + u8 *ptr;
> > +};
> > +
> > +/* Private struct for each char device instance. */
> > +struct se_if_device_ctx {
> > + struct device *dev;
> > + struct se_if_priv *priv;
> > + struct miscdevice miscdev;
> > +
> > + enum se_if_dev_ctx_status_t status;
> > + wait_queue_head_t wq;
> > + struct semaphore fops_lock;
> > +
> > + u32 pending_hdr;
> > + struct list_head pending_in;
> > + struct list_head pending_out;
> > +
> > + struct se_shared_mem secure_mem;
> > + struct se_shared_mem non_secure_mem;
> > +
> > + u32 *temp_resp;
> > + u32 temp_resp_size;
> > + struct notifier_block se_notify;
> > +};
> > +
> > +/* Header of the messages exchange with the EdgeLock Enclave */
> > +struct se_msg_hdr {
> > + u8 ver;
> > + u8 size;
> > + u8 command;
> > + u8 tag;
> > +} __packed;
> > +
> > +#define SE_MU_HDR_SZ 4
> > +#define TAG_OFFSET (SE_MU_HDR_SZ - 1)
> > +#define CMD_OFFSET (SE_MU_HDR_SZ - 2)
> > +#define SZ_OFFSET (SE_MU_HDR_SZ - 3)
> > +#define VER_OFFSET (SE_MU_HDR_SZ - 4)
> > +
> > +struct se_api_msg {
> > + u32 header; /* u8 Tag; u8 Command; u8 Size; u8 Ver; */
> > + u32 *data;
> > +};
> > +
> > +struct se_if_priv {
> > + struct se_if_device_ctx *cmd_receiver_dev;
> > + struct se_if_device_ctx *waiting_rsp_dev;
> > + bool no_dev_ctx_used;
> > + /*
> > + * prevent parallel access to the se interface registers
> > + * e.g. a user trying to send a command while the other one is
> > + * sending a response.
> > + */
> > + struct mutex se_if_lock;
> > + /*
> > + * prevent a command to be sent on the se interface while another one
> is
> > + * still processing. (response to a command is allowed)
> > + */
> > + struct mutex se_if_cmd_lock;
> > + struct device *dev;
> > + u8 *mem_pool_name;
> > + u8 cmd_tag;
> > + u8 rsp_tag;
> > + u8 success_tag;
> > + u8 base_api_ver;
> > + u8 fw_api_ver;
> > + u32 fw_fail;
> > + const void *info;
> > +
> > + struct mbox_client se_mb_cl;
> > + struct mbox_chan *tx_chan, *rx_chan;
> > + struct se_api_msg *rx_msg;
> > + struct completion done;
> > + spinlock_t lock;
> > + /*
> > + * Flag to retain the state of initialization done at
> > + * the time of se-mu probe.
> > + */
> > + uint32_t flags;
> > + u8 max_dev_ctx;
> > + struct se_if_device_ctx **ctxs;
> > + struct se_imem_buf imem;
> > +};
> > +
> > +void *get_phy_buf_mem_pool(struct device *dev,
> > + u8 *mem_pool_name,
> > + dma_addr_t *buf,
> > + u32 size);
> > +phys_addr_t get_phy_buf_mem_pool1(struct device *dev,
> > + u8 *mem_pool_name,
> > + u32 **buf,
> > + u32 size);
> > +void free_phybuf_mem_pool(struct device *dev,
> > + u8 *mem_pool_name,
> > + u32 *buf,
> > + u32 size);
> > +#endif
> > diff --git a/include/linux/firmware/imx/se_api.h
> b/include/linux/firmware/imx/se_api.h
> > new file mode 100644
> > index 000000000000..c47f84906837
> > --- /dev/null
> > +++ b/include/linux/firmware/imx/se_api.h
> > @@ -0,0 +1,14 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#ifndef __SE_API_H__
> > +#define __SE_API_H__
> > +
> > +#include <linux/types.h>
> > +
> > +#define SOC_ID_OF_IMX8ULP 0x084D
> > +#define SOC_ID_OF_IMX93 0x9300
> > +
> > +#endif /* __SE_API_H__ */
> > diff --git a/include/uapi/linux/se_ioctl.h b/include/uapi/linux/se_ioctl.h
> > new file mode 100644
> > index 000000000000..f68a36e9da2c
> > --- /dev/null
> > +++ b/include/uapi/linux/se_ioctl.h
> > @@ -0,0 +1,88 @@
> > +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-
> Clause*/
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#ifndef SE_IOCTL_H
> > +#define SE_IOCTL_H
> > +
> > +/* IOCTL definitions. */
> > +
> > +struct se_ioctl_setup_iobuf {
> > + u8 *user_buf;
> > + u32 length;
> > + u32 flags;
> > + u64 ele_addr;
> > +};
> > +
> > +struct se_ioctl_shared_mem_cfg {
> > + u32 base_offset;
> > + u32 size;
> > +};
> > +
> > +struct se_ioctl_get_if_info {
> > + u8 se_if_id;
> > + u8 interrupt_idx;
> > + u8 tz;
> > + u8 did;
> > + u8 cmd_tag;
> > + u8 rsp_tag;
> > + u8 success_tag;
> > + u8 base_api_ver;
> > + u8 fw_api_ver;
> > +};
> > +
> > +struct se_ioctl_signed_message {
> > + u8 *message;
> > + u32 msg_size;
> > + u32 error_code;
> > +};
> > +
> > +struct se_ioctl_get_soc_info {
> > + u16 soc_id;
> > + u16 soc_rev;
> > +};
> > +
> > +/* IO Buffer Flags */
> > +#define SE_IO_BUF_FLAGS_IS_OUTPUT (0x00u)
> > +#define SE_IO_BUF_FLAGS_IS_INPUT (0x01u)
> > +#define SE_IO_BUF_FLAGS_USE_SEC_MEM (0x02u)
> > +#define SE_IO_BUF_FLAGS_USE_SHORT_ADDR (0x04u)
> > +#define SE_IO_BUF_FLAGS_IS_IN_OUT (0x10u)
> > +
> > +/* IOCTLS */
> > +#define SE_IOCTL 0x0A /* like MISC_MAJOR. */
> > +
> > +/*
> > + * ioctl to designated the current fd as logical-reciever.
> > + * This is ioctl is send when the nvm-daemon, a slave to the
> > + * firmware is started by the user.
> > + */
> > +#define SE_IOCTL_ENABLE_CMD_RCV _IO(SE_IOCTL, 0x01)
> > +
> > +/*
> > + * ioctl to get the buffer allocated from the memory, which is shared
> > + * between kernel and FW.
> > + * Post allocation, the kernel tagged the allocated memory with:
> > + * Output
> > + * Input
> > + * Input-Output
> > + * Short address
> > + * Secure-memory
> > + */
> > +#define SE_IOCTL_SETUP_IOBUF _IOWR(SE_IOCTL, 0x03, \
> > + struct se_ioctl_setup_iobuf)
> > +
> > +/*
> > + * ioctl to get the mu information, that is used to exchange message
> > + * with FW, from user-spaced.
> > + */
> > +#define SE_IOCTL_GET_MU_INFO _IOR(SE_IOCTL, 0x04, \
> > + struct se_ioctl_get_if_info)
> > +/*
> > + * ioctl to get SoC Info from user-space.
> > + */
> > +#define SE_IOCTL_GET_SOC_INFO _IOR(SE_IOCTL, 0x06, \
> > + struct se_ioctl_get_soc_info)
> > +
> > +#endif
> >
_______________________________________________
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^ permalink raw reply [relevance 0%]
* [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave
2024-05-10 13:27 2% ` [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave Pankaj Gupta
2024-05-10 16:41 0% ` Frank Li
2024-05-13 10:54 0% ` Marc Kleine-Budde
@ 2024-05-16 4:47 0% ` Amit Singh Tomar
2024-05-16 4:52 0% ` [EXT] " Pankaj Gupta
2 siblings, 1 reply; 200+ results
From: Amit Singh Tomar @ 2024-05-16 4:47 UTC (permalink / raw)
To: Pankaj Gupta, Jonathan Corbet, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: linux-doc, linux-kernel, devicetree, imx, linux-arm-kernel
> ----------------------------------------------------------------------
> NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE),
> are embedded in the SoC to support the features like HSM, SHE & V2X,
> using message based communication interface.
>
> The secure enclave FW communicates on a dedicated messaging unit(MU)
> based interface(s) with application core, where kernel is running.
> It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
>
> This patch adds the driver for communication interface to secure-enclave,
> for exchanging messages with NXP secure enclave HW IP(s) like EdgeLock Enclave,
> both from:
> - User-Space Applications via character driver.
> - Kernel-space, used by kernel management layers like DM-Crypt.
>
> ABI documentation for the NXP secure-enclave driver.
>
> User-space library using this driver:
> - i.MX Secure Enclave library:
> -- URL: https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_nxp-2Dimx_imx-2Dsecure-2Denclave.git&d=DwICAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=V_GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-JKU&m=lRJFNDYT5J3dZTYPCtbQrN6ho5BaZc62rCnOKShFGK0aosnXA0JKGr_OrCPlpaat&s=GFFpXM8z8-pliprvP1Xs1NsiJ8yEvE9xFQuUIGLYoe8&e= ,
> - i.MX Secure Middle-Ware:
> -- URL: https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_nxp-2Dimx_imx-2Dsmw.git&d=DwICAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=V_GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-JKU&m=lRJFNDYT5J3dZTYPCtbQrN6ho5BaZc62rCnOKShFGK0aosnXA0JKGr_OrCPlpaat&s=aCsO_lLG71KPvjVgXlx9Ly0Ed05XnSUJ4z-xxqxSze8&e=
>
> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> ---
> Documentation/ABI/testing/se-cdev | 42 ++
> drivers/firmware/imx/Kconfig | 12 +
> drivers/firmware/imx/Makefile | 2 +
> drivers/firmware/imx/ele_base_msg.c | 287 ++++++++
> drivers/firmware/imx/ele_base_msg.h | 70 ++
> drivers/firmware/imx/ele_common.c | 341 +++++++++
> drivers/firmware/imx/ele_common.h | 43 ++
> drivers/firmware/imx/se_ctrl.c | 1339 +++++++++++++++++++++++++++++++++++
> drivers/firmware/imx/se_ctrl.h | 151 ++++
> include/linux/firmware/imx/se_api.h | 14 +
> include/uapi/linux/se_ioctl.h | 88 +++
> 11 files changed, 2389 insertions(+)
>
> diff --git a/Documentation/ABI/testing/se-cdev b/Documentation/ABI/testing/se-cdev
> new file mode 100644
> index 000000000000..699525af6b86
> --- /dev/null
> +++ b/Documentation/ABI/testing/se-cdev
> @@ -0,0 +1,42 @@
> +What: /dev/<se>_mu[0-9]+_ch[0-9]+
> +Date: May 2024
> +KernelVersion: 6.8
> +Contact: linux-imx@nxp.com, pankaj.gupta@nxp.com
> +Description:
> + NXP offers multiple hardware IP(s) for secure-enclaves like EdgeLock-
> + Enclave(ELE), SECO. The character device file-descriptors
> + /dev/<se>_mu*_ch* are the interface between user-space NXP's secure-
> + enclave shared-library and the kernel driver.
> +
> + The ioctl(2)-based ABI is defined and documented in
> + [include]<linux/firmware/imx/ele_mu_ioctl.h>
> + ioctl(s) are used primarily for:
> + - shared memory management
> + - allocation of I/O buffers
> + - get mu info
> + - setting a dev-ctx as receiver that is slave to fw
> + - get SoC info
> +
> + The following file operations are supported:
> +
> + open(2)
> + Currently the only useful flags are O_RDWR.
> +
> + read(2)
> + Every read() from the opened character device context is waiting on
> + wakeup_intruptible, that gets set by the registered mailbox callback
> + function; indicating a message received from the firmware on message-
> + unit.
> +
> + write(2)
> + Every write() to the opened character device context needs to acquire
> + mailbox_lock, before sending message on to the message unit.
> +
> + close(2)
> + Stops and free up the I/O contexts that was associated
> + with the file descriptor.
> +
> +Users: https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_nxp-2Dimx_imx-2Dsecure-2Denclave.git&d=DwICAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=V_GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-JKU&m=lRJFNDYT5J3dZTYPCtbQrN6ho5BaZc62rCnOKShFGK0aosnXA0JKGr_OrCPlpaat&s=GFFpXM8z8-pliprvP1Xs1NsiJ8yEvE9xFQuUIGLYoe8&e= ,
> + https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_nxp-2Dimx_imx-2Dsmw.git&d=DwICAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=V_GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-JKU&m=lRJFNDYT5J3dZTYPCtbQrN6ho5BaZc62rCnOKShFGK0aosnXA0JKGr_OrCPlpaat&s=aCsO_lLG71KPvjVgXlx9Ly0Ed05XnSUJ4z-xxqxSze8&e=
> + crypto/skcipher,
> + drivers/nvmem/imx-ocotp-ele.c
> diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
> index 183613f82a11..56bdca9bd917 100644
> --- a/drivers/firmware/imx/Kconfig
> +++ b/drivers/firmware/imx/Kconfig
> @@ -22,3 +22,15 @@ config IMX_SCU
>
> This driver manages the IPC interface between host CPU and the
> SCU firmware running on M4.
> +
> +config IMX_SEC_ENCLAVE
> + tristate "i.MX Embedded Secure Enclave - EdgeLock Enclave Firmware driver."
> + depends on IMX_MBOX && ARCH_MXC && ARM64
> + default m if ARCH_MXC
> +
> + help
> + It is possible to use APIs exposed by the iMX Secure Enclave HW IP called:
> + - EdgeLock Enclave Firmware (for i.MX8ULP, i.MX93),
> + like base, HSM, V2X & SHE using the SAB protocol via the shared Messaging
> + Unit. This driver exposes these interfaces via a set of file descriptors
> + allowing to configure shared memory, send and receive messages.
> diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile
> index 8f9f04a513a8..aa9033e0e9e3 100644
> --- a/drivers/firmware/imx/Makefile
> +++ b/drivers/firmware/imx/Makefile
> @@ -1,3 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-$(CONFIG_IMX_DSP) += imx-dsp.o
> obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o
> +sec_enclave-objs = se_ctrl.o ele_common.o ele_base_msg.o
> +obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
> diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele_base_msg.c
> new file mode 100644
> index 000000000000..0463f26d93c7
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_base_msg.c
> @@ -0,0 +1,287 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <linux/types.h>
> +#include <linux/completion.h>
> +#include <linux/dma-mapping.h>
> +
> +#include "ele_base_msg.h"
> +#include "ele_common.h"
> +
> +int ele_get_info(struct device *dev, struct soc_info *s_info)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_api_msg *rx_msg __free(kfree);
> + phys_addr_t get_info_addr;
> + u32 *get_info_data;
> + u32 status;
> + int ret;
> +
> + if (!priv || !s_info)
> + goto exit;
> +
> + memset(s_info, 0x0, sizeof(*s_info));
> +
> + if (priv->mem_pool_name)
> + get_info_data = get_phy_buf_mem_pool(dev,
> + priv->mem_pool_name,
> + &get_info_addr,
> + ELE_GET_INFO_BUFF_SZ);
> + else
> + get_info_data = dmam_alloc_coherent(dev,
> + ELE_GET_INFO_BUFF_SZ,
> + &get_info_addr,
> + GFP_KERNEL);
> + if (!get_info_data) {
> + ret = -ENOMEM;
> + dev_err(dev,
> + "%s: Failed to allocate get_info_addr.\n",
> + __func__);
> + goto exit;
> + }
> +
> + tx_msg = kzalloc(ELE_GET_INFO_REQ_MSG_SZ << 2, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + rx_msg = kzalloc(ELE_GET_INFO_RSP_MSG_SZ << 2, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_GET_INFO_REQ,
> + ELE_GET_INFO_REQ_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + tx_msg->data[0] = upper_32_bits(get_info_addr);
> + tx_msg->data[1] = lower_32_bits(get_info_addr);
> + tx_msg->data[2] = ELE_GET_INFO_READ_SZ;
> + priv->rx_msg = rx_msg;
> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> + if (ret < 0)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + priv->rx_msg->header,
> + ELE_GET_INFO_REQ,
> + ELE_GET_INFO_RSP_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_GET_INFO_REQ, status);
> + ret = -1;
> + }
> +
> + s_info->imem_state = (get_info_data[ELE_IMEM_STATE_WORD]
> + & ELE_IMEM_STATE_MASK) >> 16;
> + s_info->major_ver = (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> + & SOC_VER_MASK) >> 24;
> + s_info->minor_ver = ((get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> + & SOC_VER_MASK) >> 16) & 0xFF;
> + s_info->soc_rev = (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> + & SOC_VER_MASK) >> 16;
> + s_info->soc_id = get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> + & SOC_ID_MASK;
> + s_info->serial_num
> + = (u64)get_info_data[GET_INFO_SL_NUM_MSB_WORD_OFF] << 32
> + | get_info_data[GET_INFO_SL_NUM_LSB_WORD_OFF];
> +exit:
> + if (get_info_addr) {
> + if (priv->mem_pool_name)
> + free_phybuf_mem_pool(dev, priv->mem_pool_name,
> + get_info_data, ELE_GET_INFO_BUFF_SZ);
> + else
> + dmam_free_coherent(dev,
> + ELE_GET_INFO_BUFF_SZ,
> + get_info_data,
> + get_info_addr);
> + }
> +
> + return ret;
> +}
> +
> +int ele_ping(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_api_msg *rx_msg __free(kfree);
> + u32 status;
> + int ret;
> +
> + tx_msg = kzalloc(ELE_PING_REQ_SZ << 2, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + rx_msg = kzalloc(ELE_PING_RSP_SZ << 2, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_PING_REQ, ELE_PING_REQ_SZ,
> + true);
> + if (ret) {
> + dev_err(dev, "Error: plat_fill_cmd_msg_hdr failed.\n");
> + goto exit;
> + }
> +
> + priv->rx_msg = rx_msg;
> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> + if (ret)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + priv->rx_msg->header,
> + ELE_PING_REQ,
> + ELE_PING_RSP_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_PING_REQ, status);
> + ret = -1;
> + }
> +exit:
> + return ret;
> +}
> +
> +int ele_service_swap(struct device *dev,
> + phys_addr_t addr,
> + u32 addr_size, u16 flag)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_api_msg *rx_msg __free(kfree);
> + u32 status;
> + int ret;
> +
> + tx_msg = kzalloc(ELE_SERVICE_SWAP_REQ_MSG_SZ << 2, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + rx_msg = kzalloc(ELE_SERVICE_SWAP_RSP_MSG_SZ << 2, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_SERVICE_SWAP_REQ,
> + ELE_SERVICE_SWAP_REQ_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + tx_msg->data[0] = flag;
> + tx_msg->data[1] = addr_size;
> + tx_msg->data[2] = ELE_NONE_VAL;
> + tx_msg->data[3] = lower_32_bits(addr);
> + tx_msg->data[4] = plat_add_msg_crc((uint32_t *)&tx_msg[0],
> + ELE_SERVICE_SWAP_REQ_MSG_SZ);
> + priv->rx_msg = rx_msg;
> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> + if (ret < 0)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + priv->rx_msg->header,
> + ELE_SERVICE_SWAP_REQ,
> + ELE_SERVICE_SWAP_RSP_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_SERVICE_SWAP_REQ, status);
> + ret = -1;
> + } else {
> + if (flag == ELE_IMEM_EXPORT)
> + ret = priv->rx_msg->data[1];
> + else
> + ret = 0;
> + }
> +exit:
> +
> + return ret;
> +}
> +
> +int ele_fw_authenticate(struct device *dev, phys_addr_t addr)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_api_msg *rx_msg __free(kfree);
> + u32 status;
> + int ret;
> +
> + tx_msg = kzalloc(ELE_FW_AUTH_REQ_SZ << 2, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + rx_msg = kzalloc(ELE_FW_AUTH_RSP_MSG_SZ << 2, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_FW_AUTH_REQ,
> + ELE_FW_AUTH_REQ_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + tx_msg->data[0] = addr;
> + tx_msg->data[1] = 0x0;
> + tx_msg->data[2] = addr;
> +
> + priv->rx_msg = rx_msg;
> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> + if (ret < 0)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + priv->rx_msg->header,
> + ELE_FW_AUTH_REQ,
> + ELE_FW_AUTH_RSP_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_FW_AUTH_REQ, status);
> + ret = -1;
> + }
> +exit:
> +
> + return ret;
> +}
> diff --git a/drivers/firmware/imx/ele_base_msg.h b/drivers/firmware/imx/ele_base_msg.h
> new file mode 100644
> index 000000000000..3b3d2bf04a84
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_base_msg.h
> @@ -0,0 +1,70 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + *
> + * Header file for the EdgeLock Enclave Base API(s).
> + */
> +
> +#ifndef ELE_BASE_MSG_H
> +#define ELE_BASE_MSG_H
> +
> +#include <linux/device.h>
> +#include <linux/types.h>
> +
> +#define WORD_SZ 4
> +#define ELE_NONE_VAL 0x0
> +
> +#define ELE_SUCCESS_IND 0xD6
> +
> +#define ELE_GET_INFO_REQ 0xDA
> +#define ELE_GET_INFO_REQ_MSG_SZ 0x10
> +#define ELE_GET_INFO_RSP_MSG_SZ 0x08
> +
> +#define ELE_GET_INFO_BUFF_SZ 0x100
> +#define ELE_GET_INFO_READ_SZ 0xA0
> +
> +#define DEFAULT_IMX_SOC_VER 0xA0
> +#define SOC_VER_MASK 0xFFFF0000
> +#define SOC_ID_MASK 0x0000FFFF
> +struct soc_info {
> + u32 imem_state;
> + u8 major_ver;
> + u8 minor_ver;
> + u16 soc_id;
> + u16 soc_rev;
> + u64 serial_num;
> +};
> +
> +#define GET_INFO_SOC_INFO_WORD_OFFSET 1
> +#define GET_INFO_UUID_WORD_OFFSET 3
> +#define GET_INFO_SL_NUM_MSB_WORD_OFF \
> + (GET_INFO_UUID_WORD_OFFSET + 3)
> +#define GET_INFO_SL_NUM_LSB_WORD_OFF \
> + (GET_INFO_UUID_WORD_OFFSET + 0)
> +
> +#define ELE_PING_REQ 0x01
> +#define ELE_PING_REQ_SZ 0x04
> +#define ELE_PING_RSP_SZ 0x08
> +
> +#define ELE_SERVICE_SWAP_REQ 0xDF
> +#define ELE_SERVICE_SWAP_REQ_MSG_SZ 0x18
> +#define ELE_SERVICE_SWAP_RSP_MSG_SZ 0x0C
> +#define ELE_IMEM_SIZE 0x10000
> +#define ELE_IMEM_STATE_OK 0xCA
> +#define ELE_IMEM_STATE_BAD 0xFE
> +#define ELE_IMEM_STATE_WORD 0x27
> +#define ELE_IMEM_STATE_MASK 0x00ff0000
> +#define ELE_IMEM_EXPORT 0x1
> +#define ELE_IMEM_IMPORT 0x2
> +
> +#define ELE_FW_AUTH_REQ 0x02
> +#define ELE_FW_AUTH_REQ_SZ 0x10
> +#define ELE_FW_AUTH_RSP_MSG_SZ 0x08
> +
> +int ele_get_info(struct device *dev, struct soc_info *s_info);
> +int ele_ping(struct device *dev);
> +int ele_service_swap(struct device *dev,
> + phys_addr_t addr,
> + u32 addr_size, u16 flag);
> +int ele_fw_authenticate(struct device *dev, phys_addr_t addr);
> +#endif
> diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_common.c
> new file mode 100644
> index 000000000000..dcf7f9034653
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_common.c
> @@ -0,0 +1,341 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include "ele_base_msg.h"
> +#include "ele_common.h"
> +
> +u32 plat_add_msg_crc(u32 *msg, u32 msg_len)
> +{
> + u32 nb_words = msg_len / (u32)sizeof(u32);
> + u32 crc = 0;
> + u32 i;
> +
> + for (i = 0; i < nb_words - 1; i++)
> + crc ^= *(msg + i);
> +
> + return crc;
> +}
> +
> +int imx_ele_msg_rcv(struct se_if_priv *priv)
> +{
> + u32 wait;
> + int err;
> +
> + wait = msecs_to_jiffies(1000);
> + if (!wait_for_completion_timeout(&priv->done, wait)) {
> + dev_err(priv->dev,
> + "Error: wait_for_completion timed out.\n");
> + err = -ETIMEDOUT;
> + }
> +
> + mutex_unlock(&priv->se_if_cmd_lock);
> + priv->no_dev_ctx_used = false;
> +
> + return err;
> +}
> +
> +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg)
> +{
> + bool is_cmd_lock_tobe_taken = false;
> + int err;
> +
> + if (!priv->waiting_rsp_dev || priv->no_dev_ctx_used) {
> + is_cmd_lock_tobe_taken = true;
> + mutex_lock(&priv->se_if_cmd_lock);
> + }
> + scoped_guard(mutex, &priv->se_if_lock);
> +
> + err = mbox_send_message(priv->tx_chan, mssg);
> + if (err < 0) {
> + dev_err(priv->dev, "Error: mbox_send_message failure.\n");
> + if (is_cmd_lock_tobe_taken)
> + mutex_unlock(&priv->se_if_cmd_lock);
> + return err;
> + }
> + err = 0;
It looks odd, you can simply return 0 in the following statement.
> +
> + return err;
> +}
> +
> +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg)
> +{
> + int err;
> +
> + priv->no_dev_ctx_used = true;
> + err = imx_ele_msg_send(priv, mssg);
> + if (err)
> + goto exit;
> +
> + err = imx_ele_msg_rcv(priv);
> +
> +exit:
> + return err;
> +}
> +
> +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *dev_ctx)
> +{
> + struct se_msg_hdr header = {0};
> + int err;
> +
> + err = wait_event_interruptible(dev_ctx->wq, dev_ctx->pending_hdr != 0);
> + if (err)
> + dev_err(dev_ctx->dev,
> + "%s: Err[0x%x]:Interrupted by signal.\n",
> + dev_ctx->miscdev.name, err);
> +
> + header = *((struct se_msg_hdr *) (&dev_ctx->temp_resp[0]));
> +
> + if (header.tag == dev_ctx->priv->rsp_tag)
> + mutex_unlock(&dev_ctx->priv->se_if_cmd_lock);
> +
> + return err;
> +}
> +
> +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
> + void *tx_msg, int tx_msg_sz)
> +{
> + struct se_if_priv *priv = dev_ctx->priv;
> + struct se_msg_hdr header = {0};
> + int err;
> +
> + header = *((struct se_msg_hdr *) tx_msg);
> +
> + /*
> + * Check that the size passed as argument matches the size
> + * carried in the message.
> + */
> + err = header.size << 2;
> +
> + if (err != tx_msg_sz) {
> + err = -EINVAL;
> + dev_err(priv->dev,
> + "%s: User buffer too small\n",
> + dev_ctx->miscdev.name);
> + goto exit;
> + }
> + /* Check the message is valid according to tags */
> + if (header.tag == priv->cmd_tag)
> + priv->waiting_rsp_dev = dev_ctx;
> + else if (header.tag == priv->rsp_tag) {
> + /* Check the device context can send the command */
> + if (dev_ctx != priv->cmd_receiver_dev) {
> + dev_err(priv->dev,
> + "%s: Channel not configured to send resp to FW.",
> + dev_ctx->miscdev.name);
> + err = -EPERM;
> + goto exit;
> + }
> + } else {
> + dev_err(priv->dev,
> + "%s: The message does not have a valid TAG\n",
> + dev_ctx->miscdev.name);
> + err = -EINVAL;
> + goto exit;
> + }
> + err = imx_ele_msg_send(priv, tx_msg);
> +exit:
> + return err;
> +}
> +
> +/*
> + * Callback called by mailbox FW, when data is received.
> + */
> +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg)
> +{
> + struct device *dev = mbox_cl->dev;
> + struct se_if_device_ctx *dev_ctx;
> + struct se_api_msg *rx_msg;
> + bool is_response = false;
> + struct se_if_priv *priv;
> + struct se_msg_hdr header;
> +
> + priv = dev_get_drvdata(dev);
> + if (!priv) {
> + dev_err(dev, "SE-MU Priv data is NULL;");
> + return;
> + }
> +
> + /* The function can be called with NULL msg */
> + if (!msg) {
> + dev_err(dev, "Message is invalid\n");
> + return;
> + }
> +
> + header.tag = ((u8 *)msg)[TAG_OFFSET];
> + header.command = ((u8 *)msg)[CMD_OFFSET];
> + header.size = ((u8 *)msg)[SZ_OFFSET];
> + header.ver = ((u8 *)msg)[VER_OFFSET];
> +
> + /* Incoming command: wake up the receiver if any. */
> + if (header.tag == priv->cmd_tag) {
> + dev_dbg(dev, "Selecting cmd receiver\n");
> + dev_ctx = priv->cmd_receiver_dev;
> + } else if (header.tag == priv->rsp_tag) {
> + if (priv->waiting_rsp_dev) {
> + dev_dbg(dev, "Selecting rsp waiter\n");
> + dev_ctx = priv->waiting_rsp_dev;
> + is_response = true;
> + } else {
> + /*
> + * Reading the EdgeLock Enclave response
> + * to the command, sent by other
> + * linux kernel services.
> + */
> + spin_lock(&priv->lock);
> + memcpy(&priv->rx_msg, msg, header.size << 2);
> +
> + complete(&priv->done);
> + spin_unlock(&priv->lock);
> + return;
> + }
> + } else {
> + dev_err(dev, "Failed to select a device for message: %.8x\n",
> + *((u32 *) &header));
> + return;
> + }
> + /* Init reception */
> + rx_msg = kzalloc(header.size << 2, GFP_KERNEL);
> + if (rx_msg)
> + memcpy(rx_msg, msg, header.size << 2);
> +
> + dev_ctx->temp_resp = (u32 *)rx_msg;
> + dev_ctx->temp_resp_size = header.size;
> +
> + /* Allow user to read */
> + dev_ctx->pending_hdr = 1;
> + wake_up_interruptible(&dev_ctx->wq);
> +
> + if (is_response)
> + priv->waiting_rsp_dev = NULL;
> +}
> +
> +int validate_rsp_hdr(struct se_if_priv *priv, u32 header,
> + uint8_t msg_id, uint8_t sz, bool is_base_api)
> +{
> + int ret = -EINVAL;
> + u32 size;
> + u32 cmd;
> + u32 tag;
> + u32 ver;
> +
> + tag = MSG_TAG(header);
> + cmd = MSG_COMMAND(header);
> + size = MSG_SIZE(header);
> + ver = MSG_VER(header);
> +
> + do {
> + if (tag != priv->rsp_tag) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: Resp tag mismatch. (0x%x != 0x%x)",
> + msg_id, tag, priv->rsp_tag);
> + break;
> + }
> +
> + if (cmd != msg_id) {
> + dev_err(priv->dev,
> + "MSG Header: Cmd id mismatch. (0x%x != 0x%x)",
> + cmd, msg_id);
> + break;
> + }
> +
> + if (size != (sz >> 2)) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: Cmd size mismatch. (0x%x != 0x%x)",
> + msg_id, size, (sz >> 2));
> + break;
> + }
> +
> + if (is_base_api && (ver != priv->base_api_ver)) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: Base API Vers mismatch. (0x%x != 0x%x)",
> + msg_id, ver, priv->base_api_ver);
> + break;
> + } else if (!is_base_api && ver != priv->fw_api_ver) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: FW API Vers mismatch. (0x%x != 0x%x)",
> + msg_id, ver, priv->fw_api_ver);
> + break;
> + }
> +
> + ret = 0;
> +
> + } while (false);
> +
> + return ret;
> +}
> +
> +int se_save_imem_state(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + int ret;
> +
> + /* EXPORT command will save encrypted IMEM to given address,
> + * so later in resume, IMEM can be restored from the given
> + * address.
> + *
> + * Size must be at least 64 kB.
> + */
> + ret = ele_service_swap(dev,
> + priv->imem.phyaddr,
> + ELE_IMEM_SIZE,
> + ELE_IMEM_EXPORT);
> + if (ret < 0)
> + dev_err(dev, "Failed to export IMEM\n");
> + else
> + dev_info(dev,
> + "Exported %d bytes of encrypted IMEM\n",
> + ret);
> +
> + return ret;
> +}
> +
> +int se_restore_imem_state(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct soc_info s_info;
> + int ret;
> +
> + /* get info from ELE */
> + ret = ele_get_info(dev, &s_info);
> + if (ret) {
> + dev_err(dev, "Failed to get info from ELE.\n");
> + return ret;
> + }
> +
> + /* Get IMEM state, if 0xFE then import IMEM */
> + if (s_info.imem_state == ELE_IMEM_STATE_BAD) {
> + /* IMPORT command will restore IMEM from the given
> + * address, here size is the actual size returned by ELE
> + * during the export operation
> + */
> + ret = ele_service_swap(dev,
> + priv->imem.phyaddr,
> + priv->imem.size,
> + ELE_IMEM_IMPORT);
> + if (ret) {
> + dev_err(dev, "Failed to import IMEM\n");
> + goto exit;
> + }
> + } else
> + goto exit;
> +
> + /* After importing IMEM, check if IMEM state is equal to 0xCA
> + * to ensure IMEM is fully loaded and
> + * ELE functionality can be used.
> + */
> + ret = ele_get_info(dev, &s_info);
> + if (ret) {
> + dev_err(dev, "Failed to get info from ELE.\n");
> + goto exit;
> + }
> +
> + if (s_info.imem_state == ELE_IMEM_STATE_OK)
> + dev_info(dev, "Successfully restored IMEM\n");
> + else
> + dev_err(dev, "Failed to restore IMEM\n");
> +
> +exit:
> + return ret;
> +}
> diff --git a/drivers/firmware/imx/ele_common.h b/drivers/firmware/imx/ele_common.h
> new file mode 100644
> index 000000000000..6e3a2114bb56
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_common.h
> @@ -0,0 +1,43 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +
> +#ifndef __ELE_COMMON_H__
> +#define __ELE_COMMON_H__
> +
> +#include "se_ctrl.h"
> +
> +#define IMX_ELE_FW_DIR "imx/ele/"
> +
> +uint32_t plat_add_msg_crc(uint32_t *msg, uint32_t msg_len);
> +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *priv);
> +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
> + void *tx_msg, int tx_msg_sz);
> +int imx_ele_msg_rcv(struct se_if_priv *priv);
> +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg);
> +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg);
> +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg);
> +int validate_rsp_hdr(struct se_if_priv *priv, unsigned int header,
> + u8 msg_id, u8 sz, bool is_base_api);
> +
> +/* Fill a command message header with a given command ID and length in bytes. */
> +static inline int plat_fill_cmd_msg_hdr(struct se_if_priv *priv,
> + struct se_msg_hdr *hdr,
> + u8 cmd,
> + u32 len,
> + bool is_base_api)
> +{
> + hdr->tag = priv->cmd_tag;
> + hdr->ver = (is_base_api) ? priv->base_api_ver : priv->fw_api_ver;
> + hdr->command = cmd;
> + hdr->size = len >> 2;
> +
> + return 0;
> +}
> +
> +int se_save_imem_state(struct device *dev);
> +int se_restore_imem_state(struct device *dev);
> +
> +#endif /*__ELE_COMMON_H__ */
> diff --git a/drivers/firmware/imx/se_ctrl.c b/drivers/firmware/imx/se_ctrl.c
> new file mode 100644
> index 000000000000..11c5eaa7353f
> --- /dev/null
> +++ b/drivers/firmware/imx/se_ctrl.c
> @@ -0,0 +1,1339 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/dev_printk.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/errno.h>
> +#include <linux/export.h>
> +#include <linux/firmware.h>
> +#include <linux/firmware/imx/se_api.h>
> +#include <linux/genalloc.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/miscdevice.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_reserved_mem.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/sys_soc.h>
> +#include <uapi/linux/se_ioctl.h>
> +
> +#include "ele_base_msg.h"
> +#include "ele_common.h"
> +#include "se_ctrl.h"
> +
> +#define RESERVED_DMA_POOL BIT(1)
> +
> +struct imx_se_node_info {
> + u8 se_if_id;
> + u8 se_if_did;
> + u8 max_dev_ctx;
> + u8 cmd_tag;
> + u8 rsp_tag;
> + u8 success_tag;
> + u8 base_api_ver;
> + u8 fw_api_ver;
> + u8 *se_name;
> + u8 *mbox_tx_name;
> + u8 *mbox_rx_name;
> + u8 *pool_name;
> + u8 *fw_name_in_rfs;
> + bool soc_register;
> + bool reserved_dma_ranges;
> + bool imem_mgmt;
> +};
> +
> +struct imx_se_node_info_list {
> + u8 num_mu;
> + u16 soc_id;
> + u16 soc_rev;
> + struct imx_se_node_info info[];
> +};
> +
> +static const struct imx_se_node_info_list imx8ulp_info = {
> + .num_mu = 1,
> + .soc_id = SOC_ID_OF_IMX8ULP,
> + .info = {
> + {
> + .se_if_id = 2,
> + .se_if_did = 7,
> + .max_dev_ctx = 4,
> + .cmd_tag = 0x17,
> + .rsp_tag = 0xe1,
> + .success_tag = 0xd6,
> + .base_api_ver = MESSAGING_VERSION_6,
> + .fw_api_ver = MESSAGING_VERSION_7,
> + .se_name = "hsm1",
> + .mbox_tx_name = "tx",
> + .mbox_rx_name = "rx",
> + .pool_name = "sram",
> + .fw_name_in_rfs = IMX_ELE_FW_DIR\
> + "mx8ulpa2ext-ahab-container.img",
> + .soc_register = true,
> + .reserved_dma_ranges = true,
> + .imem_mgmt = true,
> + },
> + },
> +};
> +
> +static const struct imx_se_node_info_list imx93_info = {
> + .num_mu = 1,
> + .soc_id = SOC_ID_OF_IMX93,
> + .info = {
> + {
> + .se_if_id = 2,
> + .se_if_did = 3,
> + .max_dev_ctx = 4,
> + .cmd_tag = 0x17,
> + .rsp_tag = 0xe1,
> + .success_tag = 0xd6,
> + .base_api_ver = MESSAGING_VERSION_6,
> + .fw_api_ver = MESSAGING_VERSION_7,
> + .se_name = "hsm1",
> + .mbox_tx_name = "tx",
> + .mbox_rx_name = "rx",
> + .reserved_dma_ranges = true,
> + .imem_mgmt = true,
> + .soc_register = true,
> + },
> + },
> +};
> +
> +static const struct of_device_id se_match[] = {
> + { .compatible = "fsl,imx8ulp-ele", .data = (void *)&imx8ulp_info},
> + { .compatible = "fsl,imx93-ele", .data = (void *)&imx93_info},
> + {},
> +};
> +
> +static struct imx_se_node_info
> + *get_imx_se_node_info(struct imx_se_node_info_list *info_list,
> + const u32 idx)
> +{
> + if (idx < 0 || idx > info_list->num_mu)
> + return NULL;
> +
> + return &info_list->info[idx];
> +}
> +
> +void *get_phy_buf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + dma_addr_t *buf,
> + u32 size)
> +{
> + struct device_node *of_node = dev->of_node;
> + struct gen_pool *mem_pool;
> +
> + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> + if (!mem_pool) {
> + dev_err(dev,
> + "Unable to get sram pool = %s\n",
> + mem_pool_name);
> + return 0;
> + }
> +
> + return gen_pool_dma_alloc(mem_pool, size, buf);
> +}
> +
> +void free_phybuf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + u32 *buf,
> + u32 size)
> +{
> + struct device_node *of_node = dev->of_node;
> + struct gen_pool *mem_pool;
> +
> + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> + if (!mem_pool)
> + dev_err(dev,
> + "%s: Failed: Unable to get sram pool.\n",
> + __func__);
> +
> + gen_pool_free(mem_pool, (u64)buf, size);
> +}
> +
> +static int imx_fetch_soc_info(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct imx_se_node_info_list *info_list;
> + const struct imx_se_node_info *info;
> + struct soc_device_attribute *attr;
> + struct soc_device *sdev;
> + struct soc_info s_info;
> + int err = 0;
> +
> + info = priv->info;
> + info_list = (struct imx_se_node_info_list *)
> + device_get_match_data(dev->parent);
> + if (info_list->soc_rev)
> + return err;
> +
> + err = ele_get_info(dev, &s_info);
> + if (err)
> + s_info.major_ver = DEFAULT_IMX_SOC_VER;
> +
> + info_list->soc_rev = s_info.soc_rev;
> +
> + if (!info->soc_register)
> + return 0;
> +
> + attr = devm_kzalloc(dev, sizeof(*attr), GFP_KERNEL);
> + if (!attr)
> + return -ENOMEM;
> +
> + if (s_info.minor_ver)
> + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x.%x",
> + s_info.major_ver,
> + s_info.minor_ver);
> + else
> + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x",
> + s_info.major_ver);
> +
> + switch (s_info.soc_id) {
> + case SOC_ID_OF_IMX8ULP:
> + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> + "i.MX8ULP");
> + break;
> + case SOC_ID_OF_IMX93:
> + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> + "i.MX93");
> + break;
> + }
> +
> + err = of_property_read_string(of_root, "model",
> + &attr->machine);
> + if (err) {
> + devm_kfree(dev, attr);
> + return -EINVAL;
> + }
> + attr->family = devm_kasprintf(dev, GFP_KERNEL, "Freescale i.MX");
> +
> + attr->serial_number
> + = devm_kasprintf(dev, GFP_KERNEL, "%016llX", s_info.serial_num);
> +
> + sdev = soc_device_register(attr);
> + if (IS_ERR(sdev)) {
> + devm_kfree(dev, attr->soc_id);
> + devm_kfree(dev, attr->serial_number);
> + devm_kfree(dev, attr->revision);
> + devm_kfree(dev, attr->family);
> + devm_kfree(dev, attr->machine);
> + devm_kfree(dev, attr);
> + return PTR_ERR(sdev);
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * File operations for user-space
> + */
> +
> +/* Write a message to the MU. */
> +static ssize_t se_if_fops_write(struct file *fp, const char __user *buf,
> + size_t size, loff_t *ppos)
> +{
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_if_device_ctx *dev_ctx;
> + struct se_if_priv *priv;
> + int err;
> +
> + dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + priv = dev_ctx->priv;
> + dev_dbg(priv->dev,
> + "%s: write from buf (%p)%zu, ppos=%lld\n",
> + dev_ctx->miscdev.name,
> + buf, size, ((ppos) ? *ppos : 0));
> +
> + if (down_interruptible(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + if (dev_ctx->status != MU_OPENED) {
> + err = -EINVAL;
> + goto exit;
> + }
> +
> + if (size < SE_MU_HDR_SZ) {
> + dev_err(priv->dev,
> + "%s: User buffer too small(%zu < %d)\n",
> + dev_ctx->miscdev.name,
> + size, SE_MU_HDR_SZ);
> + err = -ENOSPC;
> + goto exit;
> + }
> +
> + tx_msg = memdup_user((void __user *)ppos, size);
> + if (!tx_msg) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + /* Copy data to buffer */
> + if (copy_from_user(tx_msg, buf, size)) {
> + err = -EFAULT;
> + dev_err(priv->dev,
> + "%s: Fail copy message from user\n",
> + dev_ctx->miscdev.name);
> + goto exit;
> + }
> +
> + print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4,
> + tx_msg, size, false);
> +
> + err = imx_ele_miscdev_msg_send(dev_ctx, tx_msg, size);
> +
> +exit:
> + up(&dev_ctx->fops_lock);
> + return err;
> +}
> +
> +/*
> + * Read a message from the MU.
> + * Blocking until a message is available.
> + */
> +static ssize_t se_if_fops_read(struct file *fp, char __user *buf,
> + size_t size, loff_t *ppos)
> +{
> + struct se_if_device_ctx *dev_ctx;
> + struct se_buf_desc *b_desc;
> + struct se_if_priv *priv;
> + u32 size_to_copy;
> + int err;
> +
> + dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + priv = dev_ctx->priv;
> + dev_dbg(priv->dev,
> + "%s: read to buf %p(%zu), ppos=%lld\n",
> + dev_ctx->miscdev.name,
> + buf, size, ((ppos) ? *ppos : 0));
> +
> + if (down_interruptible(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + if (dev_ctx->status != MU_OPENED) {
> + err = -EINVAL;
> + goto exit;
> + }
> +
> + err = imx_ele_miscdev_msg_rcv(dev_ctx);
> + if (err)
> + goto exit;
> +
> + /* Buffer containing the message from FW, is
> + * allocated in callback function.
> + * Check if buffer allocation failed.
> + */
> + if (!dev_ctx->temp_resp) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + dev_dbg(priv->dev,
> + "%s: %s %s\n",
> + dev_ctx->miscdev.name,
> + __func__,
> + "message received, start transmit to user");
> +
> + /*
> + * Check that the size passed as argument is larger than
> + * the one carried in the message.
> + */
> + size_to_copy = dev_ctx->temp_resp_size << 2;
> + if (size_to_copy > size) {
> + dev_dbg(priv->dev,
> + "%s: User buffer too small (%zu < %d)\n",
> + dev_ctx->miscdev.name,
> + size, size_to_copy);
> + size_to_copy = size;
> + }
> +
> + /*
> + * We may need to copy the output data to user before
> + * delivering the completion message.
> + */
> + while (!list_empty(&dev_ctx->pending_out)) {
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> + struct se_buf_desc,
> + link);
> + if (!b_desc)
> + continue;
> +
> + if (b_desc->usr_buf_ptr && b_desc->shared_buf_ptr) {
> +
> + dev_dbg(priv->dev,
> + "%s: Copy output data to user\n",
> + dev_ctx->miscdev.name);
> + if (copy_to_user(b_desc->usr_buf_ptr,
> + b_desc->shared_buf_ptr,
> + b_desc->size)) {
> + dev_err(priv->dev,
> + "%s: Failure copying output data to user.",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> + }
> +
> + if (b_desc->shared_buf_ptr)
> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> +
> + __list_del_entry(&b_desc->link);
> + kfree(b_desc);
> + }
> +
> + /* Copy data from the buffer */
> + print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4,
> + dev_ctx->temp_resp, size_to_copy, false);
> + if (copy_to_user(buf, dev_ctx->temp_resp, size_to_copy)) {
> + dev_err(priv->dev,
> + "%s: Failed to copy to user\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> + err = size_to_copy;
> + kfree(dev_ctx->temp_resp);
> +
> + /* free memory allocated on the shared buffers. */
> + dev_ctx->secure_mem.pos = 0;
> + dev_ctx->non_secure_mem.pos = 0;
> +
> + dev_ctx->pending_hdr = 0;
> +
> +exit:
> + /*
> + * Clean the used Shared Memory space,
> + * whether its Input Data copied from user buffers, or
> + * Data received from FW.
> + */
> + while (!list_empty(&dev_ctx->pending_in) ||
> + !list_empty(&dev_ctx->pending_out)) {
> + if (!list_empty(&dev_ctx->pending_in))
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
> + struct se_buf_desc,
> + link);
> + else
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> + struct se_buf_desc,
> + link);
> +
> + if (!b_desc)
> + continue;
> +
> + if (b_desc->shared_buf_ptr)
> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> +
> + __list_del_entry(&b_desc->link);
> + kfree(b_desc);
> + }
> +
> + up(&dev_ctx->fops_lock);
> + return err;
> +}
> +
> +/* Give access to EdgeLock Enclave, to the memory we want to share */
> +static int se_if_setup_se_mem_access(struct se_if_device_ctx *dev_ctx,
> + u64 addr, u32 len)
> +{
> + /* Assuming EdgeLock Enclave has access to all the memory regions */
> + int ret = 0;
> +
> + if (ret) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Fail find memreg\n", dev_ctx->miscdev.name);
> + goto exit;
> + }
> +
> + if (ret) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Fail set permission for resource\n",
> + dev_ctx->miscdev.name);
> + goto exit;
> + }
> +
> +exit:
> + return ret;
> +}
> +
> +static int se_ioctl_get_mu_info(struct se_if_device_ctx *dev_ctx,
> + u64 arg)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev_ctx->dev);
> + struct imx_se_node_info *if_node_info;
> + struct se_ioctl_get_if_info info;
> + int err = 0;
> +
> + if_node_info = (struct imx_se_node_info *)priv->info;
> +
> + info.se_if_id = if_node_info->se_if_id;
> + info.interrupt_idx = 0;
> + info.tz = 0;
> + info.did = if_node_info->se_if_did;
> + info.cmd_tag = if_node_info->cmd_tag;
> + info.rsp_tag = if_node_info->rsp_tag;
> + info.success_tag = if_node_info->success_tag;
> + info.base_api_ver = if_node_info->base_api_ver;
> + info.fw_api_ver = if_node_info->fw_api_ver;
> +
> + dev_dbg(priv->dev,
> + "%s: info [se_if_id: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n",
> + dev_ctx->miscdev.name,
> + info.se_if_id, info.interrupt_idx, info.tz, info.did);
> +
> + if (copy_to_user((u8 *)arg, &info, sizeof(info))) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed to copy mu info to user\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> +exit:
> + return err;
> +}
> +
> +/*
> + * Copy a buffer of data to/from the user and return the address to use in
> + * messages
> + */
> +static int se_ioctl_setup_iobuf_handler(struct se_if_device_ctx *dev_ctx,
> + u64 arg)
> +{
> + struct se_ioctl_setup_iobuf io = {0};
> + struct se_shared_mem *shared_mem;
> + struct se_buf_desc *b_desc;
> + int err = 0;
> + u32 pos;
> +
> + if (copy_from_user(&io, (u8 *)arg, sizeof(io))) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed copy iobuf config from user\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> + dev_dbg(dev_ctx->priv->dev,
> + "%s: io [buf: %p(%d) flag: %x]\n",
> + dev_ctx->miscdev.name,
> + io.user_buf, io.length, io.flags);
> +
> + if (io.length == 0 || !io.user_buf) {
> + /*
> + * Accept NULL pointers since some buffers are optional
> + * in FW commands. In this case we should return 0 as
> + * pointer to be embedded into the message.
> + * Skip all data copy part of code below.
> + */
> + io.ele_addr = 0;
> + goto copy;
> + }
> +
> + /* Select the shared memory to be used for this buffer. */
> + if (io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) {
> + /* App requires to use secure memory for this buffer.*/
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed allocate SEC MEM memory\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + } else {
> + /* No specific requirement for this buffer. */
> + shared_mem = &dev_ctx->non_secure_mem;
> + }
> +
> + /* Check there is enough space in the shared memory. */
> + if (shared_mem->size < shared_mem->pos
> + || io.length >= shared_mem->size - shared_mem->pos) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Not enough space in shared memory\n",
> + dev_ctx->miscdev.name);
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + /* Allocate space in shared memory. 8 bytes aligned. */
> + pos = shared_mem->pos;
> + shared_mem->pos += round_up(io.length, 8u);
> + io.ele_addr = (u64)shared_mem->dma_addr + pos;
> +
> + if ((io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) &&
> + !(io.flags & SE_MU_IO_FLAGS_USE_SHORT_ADDR)) {
> + /*Add base address to get full address.*/
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed allocate SEC MEM memory\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> + memset(shared_mem->ptr + pos, 0, io.length);
> + if ((io.flags & SE_IO_BUF_FLAGS_IS_INPUT) ||
> + (io.flags & SE_IO_BUF_FLAGS_IS_IN_OUT)) {
> + /*
> + * buffer is input:
> + * copy data from user space to this allocated buffer.
> + */
> + if (copy_from_user(shared_mem->ptr + pos, io.user_buf,
> + io.length)) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed copy data to shared memory\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> + }
> +
> + b_desc = kzalloc(sizeof(*b_desc), GFP_KERNEL);
> + if (!b_desc) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> +copy:
> + /* Provide the EdgeLock Enclave address to user space only if success.*/
> + if (copy_to_user((u8 *)arg, &io, sizeof(io))) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed to copy iobuff setup to user\n",
> + dev_ctx->miscdev.name);
> + kfree(b_desc);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> + if (b_desc) {
> + b_desc->shared_buf_ptr = shared_mem->ptr + pos;
> + b_desc->usr_buf_ptr = io.user_buf;
> + b_desc->size = io.length;
> +
> + if (io.flags & SE_IO_BUF_FLAGS_IS_INPUT) {
> + /*
> + * buffer is input:
> + * add an entry in the "pending input buffers" list so
> + * that copied data can be cleaned from shared memory
> + * later.
> + */
> + list_add_tail(&b_desc->link, &dev_ctx->pending_in);
> + } else {
> + /*
> + * buffer is output:
> + * add an entry in the "pending out buffers" list so data
> + * can be copied to user space when receiving Secure-Enclave
> + * response.
> + */
> + list_add_tail(&b_desc->link, &dev_ctx->pending_out);
> + }
> + }
> +
> +exit:
> + return err;
> +}
> +
> +/* IOCTL to provide SoC information */
> +static int se_ioctl_get_soc_info_handler(struct se_if_device_ctx *dev_ctx,
> + u64 arg)
> +{
> + struct imx_se_node_info_list *info_list;
> + struct se_ioctl_get_soc_info soc_info;
> + int err = -EINVAL;
> +
> + info_list = (struct imx_se_node_info_list *)
> + device_get_match_data(dev_ctx->priv->dev->parent);
> + if (!info_list)
> + goto exit;
> +
> + soc_info.soc_id = info_list->soc_id;
> + soc_info.soc_rev = info_list->soc_rev;
> +
> + err = (int)copy_to_user((u8 *)arg, (u8 *)(&soc_info), sizeof(soc_info));
> + if (err) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed to copy soc info to user\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> +exit:
> + return err;
> +}
> +
> +/* Open a character device. */
> +static int se_if_fops_open(struct inode *nd, struct file *fp)
> +{
> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + int err;
> +
> + /* Avoid race if opened at the same time */
> + if (down_trylock(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + /* Authorize only 1 instance. */
> + if (dev_ctx->status != MU_FREE) {
> + err = -EBUSY;
> + goto exit;
> + }
> +
> + /*
> + * Allocate some memory for data exchanges with S40x.
> + * This will be used for data not requiring secure memory.
> + */
> + dev_ctx->non_secure_mem.ptr = dmam_alloc_coherent(dev_ctx->dev,
> + MAX_DATA_SIZE_PER_USER,
> + &dev_ctx->non_secure_mem.dma_addr,
> + GFP_KERNEL);
> + if (!dev_ctx->non_secure_mem.ptr) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + err = se_if_setup_se_mem_access(dev_ctx,
> + dev_ctx->non_secure_mem.dma_addr,
> + MAX_DATA_SIZE_PER_USER);
> + if (err) {
> + err = -EPERM;
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed to share access to shared memory\n",
> + dev_ctx->miscdev.name);
> + goto free_coherent;
> + }
> +
> + dev_ctx->non_secure_mem.size = MAX_DATA_SIZE_PER_USER;
> + dev_ctx->non_secure_mem.pos = 0;
> + dev_ctx->status = MU_OPENED;
> +
> + dev_ctx->pending_hdr = 0;
> +
> + goto exit;
> +
> +free_coherent:
> + dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
> + dev_ctx->non_secure_mem.ptr,
> + dev_ctx->non_secure_mem.dma_addr);
> +
> +exit:
> + up(&dev_ctx->fops_lock);
> + return err;
> +}
> +
> +/* Close a character device. */
> +static int se_if_fops_close(struct inode *nd, struct file *fp)
> +{
> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + struct se_if_priv *priv = dev_ctx->priv;
> + struct se_buf_desc *b_desc;
> +
> + /* Avoid race if closed at the same time */
> + if (down_trylock(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + /* The device context has not been opened */
> + if (dev_ctx->status != MU_OPENED)
> + goto exit;
> +
> + /* check if this device was registered as command receiver. */
> + if (priv->cmd_receiver_dev == dev_ctx)
> + priv->cmd_receiver_dev = NULL;
> +
> + /* check if this device was registered as waiting response. */
> + if (priv->waiting_rsp_dev == dev_ctx) {
> + priv->waiting_rsp_dev = NULL;
> + mutex_unlock(&priv->se_if_cmd_lock);
> + }
> +
> + /* Unmap secure memory shared buffer. */
> + if (dev_ctx->secure_mem.ptr)
> + devm_iounmap(dev_ctx->dev, dev_ctx->secure_mem.ptr);
> +
> + dev_ctx->secure_mem.ptr = NULL;
> + dev_ctx->secure_mem.dma_addr = 0;
> + dev_ctx->secure_mem.size = 0;
> + dev_ctx->secure_mem.pos = 0;
> +
> + /* Free non-secure shared buffer. */
> + dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
> + dev_ctx->non_secure_mem.ptr,
> + dev_ctx->non_secure_mem.dma_addr);
> +
> + dev_ctx->non_secure_mem.ptr = NULL;
> + dev_ctx->non_secure_mem.dma_addr = 0;
> + dev_ctx->non_secure_mem.size = 0;
> + dev_ctx->non_secure_mem.pos = 0;
> +
> + while (!list_empty(&dev_ctx->pending_in) ||
> + !list_empty(&dev_ctx->pending_out)) {
> + if (!list_empty(&dev_ctx->pending_in))
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
> + struct se_buf_desc,
> + link);
> + else
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> + struct se_buf_desc,
> + link);
> +
> + if (!b_desc)
> + continue;
> +
> + if (b_desc->shared_buf_ptr)
> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> +
> + __list_del_entry(&b_desc->link);
> + devm_kfree(dev_ctx->dev, b_desc);
> + }
> +
> + dev_ctx->status = MU_FREE;
> +
> +exit:
> + up(&dev_ctx->fops_lock);
> + return 0;
> +}
> +
> +/* IOCTL entry point of a character device */
> +static long se_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
> +//static long se_ioctl(struct file *fp, u32 cmd, u64 arg)
> +{
> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + struct se_if_priv *se_if_priv = dev_ctx->priv;
> + int err = -EINVAL;
> +
> + /* Prevent race during change of device context */
> + if (down_interruptible(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + switch (cmd) {
> + case SE_IOCTL_ENABLE_CMD_RCV:
> + if (!se_if_priv->cmd_receiver_dev) {
> + se_if_priv->cmd_receiver_dev = dev_ctx;
> + err = 0;
> + }
> + break;
> + case SE_IOCTL_GET_MU_INFO:
> + err = se_ioctl_get_mu_info(dev_ctx, arg);
> + break;
> + case SE_IOCTL_SETUP_IOBUF:
> + err = se_ioctl_setup_iobuf_handler(dev_ctx, arg);
> + break;
> + case SE_IOCTL_GET_SOC_INFO:
> + err = se_ioctl_get_soc_info_handler(dev_ctx, arg);
> + break;
> +
> + default:
> + err = -EINVAL;
> + dev_dbg(se_if_priv->dev,
> + "%s: IOCTL %.8x not supported\n",
> + dev_ctx->miscdev.name,
> + cmd);
> + }
> +
> + up(&dev_ctx->fops_lock);
> + return (long)err;
> +}
> +
> +/* Char driver setup */
> +static const struct file_operations se_if_fops = {
> + .open = se_if_fops_open,
> + .owner = THIS_MODULE,
> + .release = se_if_fops_close,
> + .unlocked_ioctl = se_ioctl,
> + .read = se_if_fops_read,
> + .write = se_if_fops_write,
> +};
> +
> +/* interface for managed res to free a mailbox channel */
> +static void if_mbox_free_channel(void *mbox_chan)
> +{
> + mbox_free_channel(mbox_chan);
> +}
> +
> +/* interface for managed res to unregister a character device */
> +static void if_misc_deregister(void *miscdevice)
> +{
> + misc_deregister(miscdevice);
> +}
> +
> +static int se_if_request_channel(struct device *dev,
> + struct mbox_chan **chan,
> + struct mbox_client *cl,
> + const u8 *name)
> +{
> + struct mbox_chan *t_chan;
> + int ret = 0;
> +
> + t_chan = mbox_request_channel_byname(cl, name);
> + if (IS_ERR(t_chan)) {
> + ret = PTR_ERR(t_chan);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev,
> + "Failed to request chan %s ret %d\n", name,
> + ret);
> + goto exit;
> + }
> +
> + ret = devm_add_action(dev, if_mbox_free_channel, t_chan);
> + if (ret) {
> + dev_err(dev, "failed to add devm removal of mbox %s\n", name);
> + goto exit;
> + }
> +
> + *chan = t_chan;
> +
> +exit:
> + return ret;
> +}
> +
> +static int se_probe_if_cleanup(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct se_if_priv *priv;
> + int ret = 0;
> + int i;
> +
> + priv = dev_get_drvdata(dev);
> + if (!priv) {
> + ret = 0;
> + dev_dbg(dev, "SE-MU Priv data is NULL;");
> + return ret;
> + }
> +
> + if (priv->tx_chan)
> + mbox_free_channel(priv->tx_chan);
> + if (priv->rx_chan)
> + mbox_free_channel(priv->rx_chan);
> +
> + /* free the buffer in se remove, previously allocated
> + * in se probe to store encrypted IMEM
> + */
> + if (priv->imem.buf) {
> + dmam_free_coherent(dev,
> + ELE_IMEM_SIZE,
> + priv->imem.buf,
> + priv->imem.phyaddr);
> + priv->imem.buf = NULL;
> + }
> +
> + if (priv->ctxs) {
> + for (i = 0; i < priv->max_dev_ctx; i++) {
> + if (priv->ctxs[i]) {
> + devm_remove_action(dev,
> + if_misc_deregister,
> + &priv->ctxs[i]->miscdev);
> + misc_deregister(&priv->ctxs[i]->miscdev);
> + devm_kfree(dev, priv->ctxs[i]);
> + }
> + }
> + devm_kfree(dev, priv->ctxs);
> + }
> +
> + if (priv->flags & RESERVED_DMA_POOL) {
> + of_reserved_mem_device_release(dev);
> + priv->flags &= (~RESERVED_DMA_POOL);
> + }
> +
> + devm_kfree(dev, priv);
> + of_node_put(dev->of_node);
> + of_platform_device_destroy(dev, NULL);
> +
> + return ret;
> +}
> +
> +static int se_probe_cleanup(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *if_dn;
> +
> + /* Enumerate se-interface device nodes. */
> + for_each_child_of_node(dev->of_node, if_dn) {
> + struct platform_device *if_pdev
> + = of_find_device_by_node(if_dn);
> + if (se_probe_if_cleanup(if_pdev))
> + dev_err(dev,
> + "Failed to clean-up child node probe.\n");
> + }
> +
> + return 0;
> +}
> +
> +static int init_device_context(struct device *dev)
> +{
> + const struct imx_se_node_info *info;
> + struct se_if_device_ctx *dev_ctx;
> + struct se_if_priv *priv;
> + u8 *devname;
> + int ret = 0;
> + int i;
> +
> + priv = dev_get_drvdata(dev);
> +
> + if (!priv) {
> + ret = -EINVAL;
> + dev_err(dev, "Invalid SE-MU Priv data");
> + return ret;
> + }
> + info = priv->info;
> +
> + priv->ctxs = devm_kzalloc(dev, sizeof(dev_ctx) * priv->max_dev_ctx,
> + GFP_KERNEL);
> +
> + if (!priv->ctxs) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + /* Create users */
> + for (i = 0; i < priv->max_dev_ctx; i++) {
> + dev_ctx = devm_kzalloc(dev, sizeof(*dev_ctx), GFP_KERNEL);
> + if (!dev_ctx) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + dev_ctx->dev = dev;
> + dev_ctx->status = MU_FREE;
> + dev_ctx->priv = priv;
> +
> + priv->ctxs[i] = dev_ctx;
> +
> + /* Default value invalid for an header. */
> + init_waitqueue_head(&dev_ctx->wq);
> +
> + INIT_LIST_HEAD(&dev_ctx->pending_out);
> + INIT_LIST_HEAD(&dev_ctx->pending_in);
> + sema_init(&dev_ctx->fops_lock, 1);
> +
> + devname = devm_kasprintf(dev, GFP_KERNEL, "%s_ch%d",
> + info->se_name, i);
> + if (!devname) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + dev_ctx->miscdev.name = devname;
> + dev_ctx->miscdev.minor = MISC_DYNAMIC_MINOR;
> + dev_ctx->miscdev.fops = &se_if_fops;
> + dev_ctx->miscdev.parent = dev;
> + ret = misc_register(&dev_ctx->miscdev);
> + if (ret) {
> + dev_err(dev, "failed to register misc device %d\n",
> + ret);
> + return ret;
> + }
> +
> + ret = devm_add_action(dev, if_misc_deregister,
> + &dev_ctx->miscdev);
> + if (ret) {
> + dev_err(dev,
> + "failed[%d] to add action to the misc-dev\n",
> + ret);
> + return ret;
> + }
> + }
> +
> + return ret;
> +}
> +
> +static void se_load_firmware(const struct firmware *fw, void *context)
> +{
> + struct se_if_priv *priv = (struct se_if_priv *) context;
> + const struct imx_se_node_info *info = priv->info;
> + const u8 *se_fw_name = info->fw_name_in_rfs;
> + phys_addr_t se_fw_phyaddr;
> + u8 *se_fw_buf;
> +
> + if (!fw) {
> + if (priv->fw_fail > MAX_FW_LOAD_RETRIES)
> + dev_dbg(priv->dev,
> + "External FW not found, using ROM FW.\n");
> + else {
> + /*add a bit delay to wait for firmware priv released */
> + msleep(20);
> +
> + /* Load firmware one more time if timeout */
> + request_firmware_nowait(THIS_MODULE,
> + FW_ACTION_UEVENT, info->fw_name_in_rfs,
> + priv->dev, GFP_KERNEL, priv,
> + se_load_firmware);
> + priv->fw_fail++;
> + dev_dbg(priv->dev, "Value of retries = 0x%x.\n",
> + priv->fw_fail);
> + }
> +
> + return;
> + }
> +
> + /* allocate buffer to store the SE FW */
> + se_fw_buf = dmam_alloc_coherent(priv->dev, fw->size,
> + &se_fw_phyaddr,
> + GFP_KERNEL);
> + if (!se_fw_buf) {
> + dev_err(priv->dev, "Failed to alloc SE fw buffer memory\n");
> + goto exit;
> + }
> +
> + memcpy(se_fw_buf, fw->data, fw->size);
> +
> + if (ele_fw_authenticate(priv->dev, se_fw_phyaddr))
> + dev_err(priv->dev,
> + "Failed to authenticate & load SE firmware %s.\n",
> + se_fw_name);
> +
> +exit:
> + dmam_free_coherent(priv->dev,
> + fw->size,
> + se_fw_buf,
> + se_fw_phyaddr);
> +
> + release_firmware(fw);
> +}
> +
> +static int se_if_probe(struct platform_device *pdev)
> +{
> + struct imx_se_node_info_list *info_list;
> + struct device *dev = &pdev->dev;
> + struct imx_se_node_info *info;
> + struct se_if_priv *priv;
> + u32 idx;
> + int ret;
> +
> + if (of_property_read_u32(dev->of_node, "reg", &idx)) {
> + ret = -EINVAL;
> + goto exit;
> + }
> +
> + info_list = (struct imx_se_node_info_list *)
> + device_get_match_data(dev->parent);
> + info = get_imx_se_node_info(info_list, idx);
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv) {
> + ret = -ENOMEM;
> + goto exit;
> + }
> +
> + dev_set_drvdata(dev, priv);
> +
> + /* Mailbox client configuration */
> + priv->se_mb_cl.dev = dev;
> + priv->se_mb_cl.tx_block = false;
> + priv->se_mb_cl.knows_txdone = true;
> + priv->se_mb_cl.rx_callback = se_if_rx_callback;
> +
> + ret = se_if_request_channel(dev, &priv->tx_chan,
> + &priv->se_mb_cl, info->mbox_tx_name);
> + if (ret) {
> + if (ret == -EPROBE_DEFER)
> + dev_err(dev, "Mailbox tx channel, is not ready.\n");
> + else
> + dev_err(dev, "Failed to request tx channel\n");
> +
> + goto exit;
> + }
> +
> + ret = se_if_request_channel(dev, &priv->rx_chan,
> + &priv->se_mb_cl, info->mbox_rx_name);
> + if (ret) {
> + if (ret == -EPROBE_DEFER)
> + dev_err(dev, "Mailbox rx channel, is not ready.\n");
> + else
> + dev_dbg(dev, "Failed to request rx channel\n");
> +
> + goto exit;
> + }
> +
> + priv->dev = dev;
> + priv->info = info;
> +
> + /* Initialize the mutex. */
> + mutex_init(&priv->se_if_lock);
> + mutex_init(&priv->se_if_cmd_lock);
> +
> + priv->cmd_receiver_dev = NULL;
> + priv->waiting_rsp_dev = NULL;
> + priv->max_dev_ctx = info->max_dev_ctx;
> + priv->cmd_tag = info->cmd_tag;
> + priv->rsp_tag = info->rsp_tag;
> + priv->mem_pool_name = info->pool_name;
> + priv->success_tag = info->success_tag;
> + priv->base_api_ver = info->base_api_ver;
> + priv->fw_api_ver = info->fw_api_ver;
> +
> + init_completion(&priv->done);
> + spin_lock_init(&priv->lock);
> +
> + if (info->reserved_dma_ranges) {
> + ret = of_reserved_mem_device_init(dev);
> + if (ret) {
> + dev_err(dev,
> + "failed to init reserved memory region %d\n",
> + ret);
> + priv->flags &= (~RESERVED_DMA_POOL);
> + goto exit;
> + }
> + priv->flags |= RESERVED_DMA_POOL;
> + }
> +
> + if (info->fw_name_in_rfs) {
> + ret = request_firmware_nowait(THIS_MODULE,
> + FW_ACTION_UEVENT,
> + info->fw_name_in_rfs,
> + dev, GFP_KERNEL, priv,
> + se_load_firmware);
> + if (ret)
> + dev_warn(dev, "Failed to get firmware [%s].\n",
> + info->fw_name_in_rfs);
> + }
> +
> + ret = imx_fetch_soc_info(dev);
> + if (ret) {
> + dev_err(dev,
> + "failed[%d] to fetch SoC Info\n", ret);
> + goto exit;
> + }
> +
> + if (info->imem_mgmt) {
> + /* allocate buffer where SE store encrypted IMEM */
> + priv->imem.buf = dmam_alloc_coherent(dev, ELE_IMEM_SIZE,
> + &priv->imem.phyaddr,
> + GFP_KERNEL);
> + if (!priv->imem.buf) {
> + dev_err(dev,
> + "dmam-alloc-failed: To store encr-IMEM.\n");
> + ret = -ENOMEM;
> + goto exit;
> + }
> + }
> +
> + if (info->max_dev_ctx) {
> + ret = init_device_context(dev);
> + if (ret) {
> + dev_err(dev,
> + "Failed[0x%x] to create device contexts.\n",
> + ret);
> + goto exit;
> + }
> + }
> +
> + dev_info(dev, "i.MX secure-enclave: %s interface to firmware, configured.\n",
> + info->se_name);
> + return devm_of_platform_populate(dev);
> +
> +exit:
> + /* if execution control reaches here, if probe fails.
> + * hence doing the cleanup
> + */
> + if (se_probe_if_cleanup(pdev))
> + dev_err(dev,
> + "Failed to clean-up the child node probe.\n");
> +
> + return ret;
> +}
> +
> +static int se_probe(struct platform_device *pdev)
> +{
> + struct device_node *enum_dev_node;
> + struct device *dev = &pdev->dev;
> + int enum_count;
> + int ret;
> +
> + enum_count = of_get_child_count(dev->of_node);
> + if (!enum_count) {
> + ret = -EINVAL;
> + dev_err(dev, "Zero Tx/Rx path MU nodes.\n");
> + return ret;
> + }
> +
> + for_each_child_of_node(dev->of_node, enum_dev_node) {
> + struct platform_device *enum_plat_dev __maybe_unused;
> +
> + if (!of_device_is_available(enum_dev_node))
> + continue;
> +
> + enum_plat_dev = of_platform_device_create(enum_dev_node,
> + NULL,
> + dev);
> + if (!enum_plat_dev) {
> + ret = -EINVAL;
> + of_node_put(enum_dev_node);
> + dev_err(dev,
> + "Failed to create enumerated platform device.");
> + break;
> + }
> +
> + ret = se_if_probe(enum_plat_dev);
> + }
> + return ret;
> +}
> +
> +static int se_remove(struct platform_device *pdev)
> +{
> + if (se_probe_cleanup(pdev))
> + dev_err(&pdev->dev,
> + "i.MX Secure Enclave is not cleanly un-probed.");
> +
> + return 0;
> +}
> +
> +static int se_suspend(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + const struct imx_se_node_info *info
> + = priv->info;
> +
> + if (info && info->imem_mgmt)
> + priv->imem.size = se_save_imem_state(dev);
> +
> + return 0;
> +}
> +
> +static int se_resume(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + const struct imx_se_node_info *info
> + = priv->info;
> + int i;
> +
> + for (i = 0; i < priv->max_dev_ctx; i++)
> + wake_up_interruptible(&priv->ctxs[i]->wq);
> +
> + if (info && info->imem_mgmt)
> + se_restore_imem_state(dev);
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops se_pm = {
> + RUNTIME_PM_OPS(se_suspend, se_resume, NULL)
> +};
> +
> +static struct platform_driver se_driver = {
> + .driver = {
> + .name = "fsl-se-fw",
> + .of_match_table = se_match,
> + .pm = &se_pm,
> + },
> + .probe = se_probe,
> + .remove = se_remove,
> +};
> +MODULE_DEVICE_TABLE(of, se_match);
> +
> +module_platform_driver(se_driver);
> +
> +MODULE_AUTHOR("Pankaj Gupta <pankaj.gupta@nxp.com>");
> +MODULE_DESCRIPTION("iMX Secure Enclave Driver.");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/firmware/imx/se_ctrl.h b/drivers/firmware/imx/se_ctrl.h
> new file mode 100644
> index 000000000000..76e1ce77c52f
> --- /dev/null
> +++ b/drivers/firmware/imx/se_ctrl.h
> @@ -0,0 +1,151 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#ifndef SE_MU_H
> +#define SE_MU_H
> +
> +#include <linux/miscdevice.h>
> +#include <linux/semaphore.h>
> +#include <linux/mailbox_client.h>
> +
> +#define MAX_FW_LOAD_RETRIES 50
> +
> +#define MSG_TAG(x) (((x) & 0xff000000) >> 24)
> +#define MSG_COMMAND(x) (((x) & 0x00ff0000) >> 16)
> +#define MSG_SIZE(x) (((x) & 0x0000ff00) >> 8)
> +#define MSG_VER(x) ((x) & 0x000000ff)
> +#define RES_STATUS(x) ((x) & 0x000000ff)
> +#define MAX_DATA_SIZE_PER_USER (65 * 1024)
> +#define S4_DEFAULT_MUAP_INDEX (2)
> +#define S4_MUAP_DEFAULT_MAX_USERS (4)
> +#define MESSAGING_VERSION_6 0x6
> +#define MESSAGING_VERSION_7 0x7
> +
> +#define DEFAULT_MESSAGING_TAG_COMMAND (0x17u)
> +#define DEFAULT_MESSAGING_TAG_RESPONSE (0xe1u)
> +
> +#define SE_MU_IO_FLAGS_USE_SEC_MEM (0x02u)
> +#define SE_MU_IO_FLAGS_USE_SHORT_ADDR (0x04u)
> +
> +struct se_imem_buf {
> + u8 *buf;
> + phys_addr_t phyaddr;
> + u32 size;
> +};
> +
> +struct se_buf_desc {
> + u8 *shared_buf_ptr;
> + u8 *usr_buf_ptr;
> + u32 size;
> + struct list_head link;
> +};
> +
> +/* Status of a char device */
> +enum se_if_dev_ctx_status_t {
> + MU_FREE,
> + MU_OPENED
> +};
> +
> +struct se_shared_mem {
> + dma_addr_t dma_addr;
> + u32 size;
> + u32 pos;
> + u8 *ptr;
> +};
> +
> +/* Private struct for each char device instance. */
> +struct se_if_device_ctx {
> + struct device *dev;
> + struct se_if_priv *priv;
> + struct miscdevice miscdev;
> +
> + enum se_if_dev_ctx_status_t status;
> + wait_queue_head_t wq;
> + struct semaphore fops_lock;
> +
> + u32 pending_hdr;
> + struct list_head pending_in;
> + struct list_head pending_out;
> +
> + struct se_shared_mem secure_mem;
> + struct se_shared_mem non_secure_mem;
> +
> + u32 *temp_resp;
> + u32 temp_resp_size;
> + struct notifier_block se_notify;
> +};
> +
> +/* Header of the messages exchange with the EdgeLock Enclave */
> +struct se_msg_hdr {
> + u8 ver;
> + u8 size;
> + u8 command;
> + u8 tag;
> +} __packed;
> +
> +#define SE_MU_HDR_SZ 4
> +#define TAG_OFFSET (SE_MU_HDR_SZ - 1)
> +#define CMD_OFFSET (SE_MU_HDR_SZ - 2)
> +#define SZ_OFFSET (SE_MU_HDR_SZ - 3)
> +#define VER_OFFSET (SE_MU_HDR_SZ - 4)
> +
> +struct se_api_msg {
> + u32 header; /* u8 Tag; u8 Command; u8 Size; u8 Ver; */
> + u32 *data;
> +};
> +
> +struct se_if_priv {
> + struct se_if_device_ctx *cmd_receiver_dev;
> + struct se_if_device_ctx *waiting_rsp_dev;
> + bool no_dev_ctx_used;
> + /*
> + * prevent parallel access to the se interface registers
> + * e.g. a user trying to send a command while the other one is
> + * sending a response.
> + */
> + struct mutex se_if_lock;
> + /*
> + * prevent a command to be sent on the se interface while another one is
> + * still processing. (response to a command is allowed)
> + */
> + struct mutex se_if_cmd_lock;
> + struct device *dev;
> + u8 *mem_pool_name;
> + u8 cmd_tag;
> + u8 rsp_tag;
> + u8 success_tag;
> + u8 base_api_ver;
> + u8 fw_api_ver;
> + u32 fw_fail;
> + const void *info;
> +
> + struct mbox_client se_mb_cl;
> + struct mbox_chan *tx_chan, *rx_chan;
> + struct se_api_msg *rx_msg;
> + struct completion done;
> + spinlock_t lock;
> + /*
> + * Flag to retain the state of initialization done at
> + * the time of se-mu probe.
> + */
> + uint32_t flags;
> + u8 max_dev_ctx;
> + struct se_if_device_ctx **ctxs;
> + struct se_imem_buf imem;
> +};
> +
> +void *get_phy_buf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + dma_addr_t *buf,
> + u32 size);
> +phys_addr_t get_phy_buf_mem_pool1(struct device *dev,
> + u8 *mem_pool_name,
> + u32 **buf,
> + u32 size);
> +void free_phybuf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + u32 *buf,
> + u32 size);
> +#endif
> diff --git a/include/linux/firmware/imx/se_api.h b/include/linux/firmware/imx/se_api.h
> new file mode 100644
> index 000000000000..c47f84906837
> --- /dev/null
> +++ b/include/linux/firmware/imx/se_api.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#ifndef __SE_API_H__
> +#define __SE_API_H__
> +
> +#include <linux/types.h>
> +
> +#define SOC_ID_OF_IMX8ULP 0x084D
> +#define SOC_ID_OF_IMX93 0x9300
> +
> +#endif /* __SE_API_H__ */
> diff --git a/include/uapi/linux/se_ioctl.h b/include/uapi/linux/se_ioctl.h
> new file mode 100644
> index 000000000000..f68a36e9da2c
> --- /dev/null
> +++ b/include/uapi/linux/se_ioctl.h
> @@ -0,0 +1,88 @@
> +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause*/
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#ifndef SE_IOCTL_H
> +#define SE_IOCTL_H
> +
> +/* IOCTL definitions. */
> +
> +struct se_ioctl_setup_iobuf {
> + u8 *user_buf;
> + u32 length;
> + u32 flags;
> + u64 ele_addr;
> +};
> +
> +struct se_ioctl_shared_mem_cfg {
> + u32 base_offset;
> + u32 size;
> +};
> +
> +struct se_ioctl_get_if_info {
> + u8 se_if_id;
> + u8 interrupt_idx;
> + u8 tz;
> + u8 did;
> + u8 cmd_tag;
> + u8 rsp_tag;
> + u8 success_tag;
> + u8 base_api_ver;
> + u8 fw_api_ver;
> +};
> +
> +struct se_ioctl_signed_message {
> + u8 *message;
> + u32 msg_size;
> + u32 error_code;
> +};
> +
> +struct se_ioctl_get_soc_info {
> + u16 soc_id;
> + u16 soc_rev;
> +};
> +
> +/* IO Buffer Flags */
> +#define SE_IO_BUF_FLAGS_IS_OUTPUT (0x00u)
> +#define SE_IO_BUF_FLAGS_IS_INPUT (0x01u)
> +#define SE_IO_BUF_FLAGS_USE_SEC_MEM (0x02u)
> +#define SE_IO_BUF_FLAGS_USE_SHORT_ADDR (0x04u)
> +#define SE_IO_BUF_FLAGS_IS_IN_OUT (0x10u)
> +
> +/* IOCTLS */
> +#define SE_IOCTL 0x0A /* like MISC_MAJOR. */
> +
> +/*
> + * ioctl to designated the current fd as logical-reciever.
> + * This is ioctl is send when the nvm-daemon, a slave to the
> + * firmware is started by the user.
> + */
> +#define SE_IOCTL_ENABLE_CMD_RCV _IO(SE_IOCTL, 0x01)
> +
> +/*
> + * ioctl to get the buffer allocated from the memory, which is shared
> + * between kernel and FW.
> + * Post allocation, the kernel tagged the allocated memory with:
> + * Output
> + * Input
> + * Input-Output
> + * Short address
> + * Secure-memory
> + */
> +#define SE_IOCTL_SETUP_IOBUF _IOWR(SE_IOCTL, 0x03, \
> + struct se_ioctl_setup_iobuf)
> +
> +/*
> + * ioctl to get the mu information, that is used to exchange message
> + * with FW, from user-spaced.
> + */
> +#define SE_IOCTL_GET_MU_INFO _IOR(SE_IOCTL, 0x04, \
> + struct se_ioctl_get_if_info)
> +/*
> + * ioctl to get SoC Info from user-space.
> + */
> +#define SE_IOCTL_GET_SOC_INFO _IOR(SE_IOCTL, 0x06, \
> + struct se_ioctl_get_soc_info)
> +
> +#endif
>
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^ permalink raw reply [relevance 0%]
* Re: [PATCH] arm64: dts: rockchip: remove startup-delay-us from vcc3v3_pcie2x1l0 on rock-5b
@ 2024-05-15 18:12 0% ` Marc Giger
0 siblings, 0 replies; 200+ results
From: Marc Giger @ 2024-05-15 18:12 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Shawn Lin, Jianfeng Liu, robh, krzysztof.kozlowski+dt, conor+dt,
heiko, sfr, devicetree, linux-kernel, linux-rockchip,
linux-arm-kernel
Hi,
On Fri, 12 Apr 2024 18:09:13 +0200
Sebastian Reichel <sebastian.reichel@collabora.com> wrote:
> Hi,
>
> On Wed, Apr 10, 2024 at 02:30:16PM +0800, Shawn Lin wrote:
> > Hi Jianfeng,
> >
> > On 2024/4/1 16:13, Jianfeng Liu wrote:
> > > Property startup-delay-us is copied from vendor dts and it will
> > > make kernel not detect pcie wifi device. If I run command:
> > > "echo 1 > /sys/bus/pci/rescan", pcie wifi device is detected, but
> > > my wifi device RTL8822CE failed to load driver. Another device
> > > RTL8723BE can load driver but no wifi signal is detected.
> > >
> > > Removing this property will fix issues above.
> > >
> > > Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
> >
> > startup-delay-us just make sure the power rail is stable before
> > any action is taken to start the link, preventing the device from
> > unable to work stably. So it shouldn't be the root cause I think.
> >
> > Could you help try this patch to checkout if it works for you?
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > index d684214..df30127 100644
> > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > @@ -167,7 +167,7 @@ static int rockchip_pcie_start_link(struct
> > dw_pcie *pci) struct rockchip_pcie *rockchip =
> > to_rockchip_pcie(pci);
> >
> > /* Reset device */
> > - gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
> > + //gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
>
> Is this removal actually needed?
>
> >
> > rockchip_pcie_enable_ltssm(rockchip);
> >
> > @@ -180,7 +180,7 @@ static int rockchip_pcie_start_link(struct
> > dw_pcie *pci)
> > * We need more extra time as before, rather than setting
> > just
> > * 100us as we don't know how long should the device need
> > to reset. */
> > - msleep(100);
> > + msleep(300);
> > gpiod_set_value_cansleep(rockchip->rst_gpio, 1);
> >
> > return 0;
> > @@ -311,6 +311,8 @@ static int rockchip_pcie_probe(struct
> > platform_device *pdev)
> > if (ret)
> > return ret;
> >
> > + gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
>
> I suppose it makes sense to use GPIOD_OUT_LOW in
> rockchip_pcie_resource_get(), so that the GPIO is requested low from
> the start instead of being high for a very short amount of time.
>
I see the very same issue as the original reporter on a Orange Pi 5
(rk3588s) and a Orange Pi 5 plus (rk3588). In my case the onboard
ethernet interfaces and/or the nvme drive are randomly not
initialized properly. This is with Linux 6.8.9. Funny enough it seemed
to work all the time on 6.8.4 without any issued (having the bifurcation
patches applied).
After applying the following patch (with the incorporated suggestions
from Sebastian) everything seems to work on the Opi5 plus but on the
Opi5 the nvme drive still wan't to properly initialize.
In dmesg the only difference in repect to pcie/nvme I can see is that on
a working system the following to lines are shown whereby they are
missing when the nvme was not initialized properly:
nvme nvme0: Shutdown timeout set to 10 seconds
nvme nvme0: 8/0/0 default/read/poll queues
---
debian-linux.orig/drivers/pci/controller/dwc/pcie-dw-rockchip.c
2024-05-02 14:35:35.000000000 +0000 +++
debian-linux/drivers/pci/controller/dwc/pcie-dw-rockchip.c
2024-05-14 19:25:18.519434456 +0000 @@ -180,7 +180,7 @@
* We need more extra time as before, rather than setting just
* 100us as we don't know how long should the device need to
reset. */
- msleep(100);
+ msleep(300);
gpiod_set_value_cansleep(rockchip->rst_gpio, 1);
return 0;
@@ -240,7 +240,7 @@
return PTR_ERR(rockchip->apb_base);
rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev,
"reset",
- GPIOD_OUT_HIGH);
+ GPIOD_OUT_LOW);
if (IS_ERR(rockchip->rst_gpio))
return PTR_ERR(rockchip->rst_gpio);
@@ -311,6 +311,8 @@
if (ret)
return ret;
+ gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
+
/* DON'T MOVE ME: must be enable before PHY init */
rockchip->vpcie3v3 = devm_regulator_get_optional(dev,
"vpcie3v3"); if (IS_ERR(rockchip->vpcie3v3)) {
Thanks,
Marc
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^ permalink raw reply [relevance 0%]
* [PATCH v6 04/12] mux: add mux_chip_resume() function
@ 2024-05-15 10:01 6% ` Thomas Richard
0 siblings, 0 replies; 200+ results
From: Thomas Richard @ 2024-05-15 10:01 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Tony Lindgren, Aaro Koskinen,
Janusz Krzysztofik, Vignesh R, Andi Shyti, Peter Rosin,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Bjorn Helgaas, Siddharth Vadapalli
Cc: linux-gpio, linux-kernel, linux-omap, linux-i2c, linux-pci,
linux-arm-kernel, gregory.clement, theo.lebrun, thomas.petazzoni,
u-kumar1, Thomas Richard
The mux_chip_resume() function restores a mux_chip using the cached state
of each mux.
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
---
drivers/mux/core.c | 29 +++++++++++++++++++++++++++++
include/linux/mux/driver.h | 1 +
2 files changed, 30 insertions(+)
diff --git a/drivers/mux/core.c b/drivers/mux/core.c
index 775816112932..0742aa2a7c73 100644
--- a/drivers/mux/core.c
+++ b/drivers/mux/core.c
@@ -215,6 +215,35 @@ void mux_chip_free(struct mux_chip *mux_chip)
}
EXPORT_SYMBOL_GPL(mux_chip_free);
+/**
+ * mux_chip_resume() - restores the mux-chip state
+ * @mux_chip: The mux-chip to resume.
+ *
+ * Restores the mux-chip state.
+ *
+ * Return: Zero on success or a negative errno on error.
+ */
+int mux_chip_resume(struct mux_chip *mux_chip)
+{
+ int ret, i;
+
+ for (i = 0; i < mux_chip->controllers; ++i) {
+ struct mux_control *mux = &mux_chip->mux[i];
+
+ if (mux->cached_state == MUX_CACHE_UNKNOWN)
+ continue;
+
+ ret = mux_control_set(mux, mux->cached_state);
+ if (ret < 0) {
+ dev_err(&mux_chip->dev, "unable to restore state\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mux_chip_resume);
+
static void devm_mux_chip_release(struct device *dev, void *res)
{
struct mux_chip *mux_chip = *(struct mux_chip **)res;
diff --git a/include/linux/mux/driver.h b/include/linux/mux/driver.h
index 18824064f8c0..2a7e5ec5d540 100644
--- a/include/linux/mux/driver.h
+++ b/include/linux/mux/driver.h
@@ -88,6 +88,7 @@ struct mux_chip *mux_chip_alloc(struct device *dev,
int mux_chip_register(struct mux_chip *mux_chip);
void mux_chip_unregister(struct mux_chip *mux_chip);
void mux_chip_free(struct mux_chip *mux_chip);
+int mux_chip_resume(struct mux_chip *mux_chip);
struct mux_chip *devm_mux_chip_alloc(struct device *dev,
unsigned int controllers,
--
2.39.2
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^ permalink raw reply related [relevance 6%]
* Re: [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement
2024-05-14 17:03 0% ` Russell King (Oracle)
@ 2024-05-14 18:26 0% ` Florian Fainelli
0 siblings, 0 replies; 200+ results
From: Florian Fainelli @ 2024-05-14 18:26 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Geert Uytterhoeven, Ard Biesheuvel, Linus Walleij, Arnd Bergmann,
Stefan Wahren, Kees Cook, linux-arm-kernel, Catalin Marinas
On 5/14/24 10:03, Russell King (Oracle) wrote:
> On Tue, May 14, 2024 at 09:54:07AM -0700, Florian Fainelli wrote:
>> On 5/14/24 09:06, Geert Uytterhoeven wrote:
>>> On Tue, May 14, 2024 at 1:28 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>>>> On Tue, May 14, 2024 at 10:25 AM Ard Biesheuvel <ardb@kernel.org> wrote:
>>>>> On Tue, 14 May 2024 at 10:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>>>>>> On Tue, May 14, 2024 at 9:59 AM Ard Biesheuvel <ardb@kernel.org> wrote:
>>>>>>> On Tue, 14 May 2024 at 09:46, Linus Walleij <linus.walleij@linaro.org> wrote:
>>>>>>>> On Tue, May 14, 2024 at 8:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>>>>>>>>
>>>>>>>>> I sent you a small initramfs by PM.
>>>>>>>>
>>>>>>>> Booted this just fine on Vexpress QEMU:
>>>>>>>>
>>>>>>>> Run /init as init process
>>>>>>>> sysctl: error: 'kernel.hotplug' is an unknown key
>>>>>>>>
>>>>>>>>
>>>>>>>> boot (Linux 6.9.0-rc1+, BusyBox v1.16.0.git, kexec-tools 2.0.1-git)
>>>>>>>> / # mount -t debugfs none /sys/kernel/debug
>>>>>>>> / # echo "ACCESS_USERSPACE" | cat >/sys/kernel/debug/provoke-crash/DIRECT
>>>>>>>> lkdtm: Performing direct entry ACCESS_USERSPACE
>>>>>>>> lkdtm: attempting bad read at 76fea000
>>>>>>>> 8<--- cut here ---
>>>>>>>> Unable to handle kernel paging request at virtual address 76fea000 when read
>>>>>>>> [76fea000] *pgd=82c93003, *pmd=82c94003, *pte=a00000811e2f5f
>>>>>>>> Internal error: Oops: 206 [#1] SMP ARM
>>>>>>>> CPU: 1 PID: 86 Comm: cat Not tainted 6.9.0-rc1+ #46
>>>>>>>> Hardware name: ARM-Versatile Express
>>>>>>>> PC is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
>>>>>>>> LR is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
>>>>>>>>
>>>>>>>> I'm starting to think it is something about different LPAE implementations here.
>>>>>>>
>>>>>>> I have built multi_v7_defconfig with the following enabled
>>>>>>>
>>>>>>> CONFIG_ARM_LPAE=y
>>>>>>> CONFIG_CPU_TTBR0_PAN=y
>>>>>>> CONFIG_LKDTM=y
>>>>>>>
>>>>>>> and the resulting kernel boots happily as a 32-bit VM running under a
>>>>>>> Rpi4 KVM host.
>>>>>>>
>>>>>>> Could someone post an actual .config that reproduces this? Rpi4 is
>>>>>>> A72, which both works and doesn't work in Florian's testing, so I'd be
>>>>>>> highly surprised if this is not a config issue.
>>>>>>
>>>>>> shmobile_defconfig with CONFIG_LPAE=y added failed for me before.
>>>>>>
>>>>>> Building multi_v7_defconfig with the above enabled...
>>>>
>>>> And that works, while shmobile_defconfig with the above does not!
>>>> So it is config-related.
>>>
>>> I ran tools/testing/ktest/config-bisect.pl and found the "offending"
>>> config option: CONFIG_CC_OPTIMIZE_FOR_SIZE=y gives a broken
>>> kernel, CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y works.
>>> (verified by just enabling CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE in my
>>> broken config)....
>>
>> I second that, my working configuration has
>> CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y whereas my
>> broken one has CONFIG_CC_OPTIMIZE_FOR_SIZE=y, sure enough, changing the
>> broken configuration to have CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y turns it
>> into a "working" configuration on the Raspberry Pi 4B in AArch32 mode.
>>
>> That makes more sense because BCM7211 and BCM2711 are exactly the same CPU,
>> thanks for restoring sanity!
>
> I would imagine that the problem is cpu_set_ttbcr(). Please try adding
> a "memory" clobber to the asm() instruction in there.
>
I can confirm that with CONFIG_CC_OPTIMIZE_FOR_SIZE=y and the hunk below:
diff --git a/arch/arm/include/asm/proc-fns.h
b/arch/arm/include/asm/proc-fns.h
index 9b3105a2a5e0..1087bd2af433 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -187,7 +187,7 @@ static inline unsigned int cpu_get_ttbcr(void)
static inline void cpu_set_ttbcr(unsigned int ttbcr)
{
- asm("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
+ asm("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr) : "memory");
}
#else /*!CONFIG_MMU */
my Raspberry Pi 4B in AArch32 mode boots and runs user-space properly.
Thanks a lot Russell!
--
Florian
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* Re: [PATCH] iommu/arm-smmu: Don't disable next-page prefetcher on devices it works on
2024-05-13 23:13 5% [PATCH] iommu/arm-smmu: Don't disable next-page prefetcher on devices it works on Douglas Anderson
@ 2024-05-14 17:14 0% ` Robin Murphy
2024-05-17 16:37 0% ` Will Deacon
1 sibling, 0 replies; 200+ results
From: Robin Murphy @ 2024-05-14 17:14 UTC (permalink / raw)
To: Douglas Anderson, Will Deacon, Joerg Roedel
Cc: Stephen Boyd, Chen Lin, iommu, linux-arm-kernel, linux-kernel
Hi Doug,
On 2024-05-14 12:13 am, Douglas Anderson wrote:
> On sc7180 trogdor devices we get a scary warning at bootup:
> arm-smmu 15000000.iommu:
> Failed to disable prefetcher [errata #841119 and #826419], check ACR.CACHE_LOCK
>
> We spent some time trying to figure out how we were going to fix these
> errata and whether we needed to do a firmware update. Upon closer
> inspection, however, we realized that the errata don't apply to us.
> Specifically, the errata document says that for these errata:
> * Found in: r0p0
> * Fixed in: r2p2
>
> ...and trogdor devices appear to be running r2p4. That means that they
> are unaffected despite the scary warning.
>
> The issue is that the kernel unconditionally tries to disable the
> prefetcher even on unaffected devices and then warns when it's unable
> to.
>
> Let's change the kernel to only disable the prefetcher on affected
> devices, which will get rid of the scary warning on devices that are
> unaffected. As per the comment the prefetcher is
> "not-particularly-beneficial" but it shouldn't hurt to leave it on for
> devices where it doesn't cause problems.
Unfortunately by now there are also at least #562869 and #1047329, plus
a small possibility of further corners of systemic brokenness in the
prefetcher yet to be discovered (or at least characterised sufficiently
to be reported as an erratum). One could argue that we're not currently
meeting the conditions for #1047329 yet, but with the IOMMUFD APIs
finally falling into place, and potential pKVM use-cases on the horizon
too, there's a distinct chance that someone will be interested in
nesting support for SMMUv2 sooner or later.
Thanks,
Robin.
> Fixes: f87f6e5b4539 ("iommu/arm-smmu: Warn once when the perfetcher errata patch fails to apply")
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---
>
> drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
> index 9dc772f2cbb2..d9b38b0db0d4 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
> @@ -109,7 +109,7 @@ static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smm
>
> int arm_mmu500_reset(struct arm_smmu_device *smmu)
> {
> - u32 reg, major;
> + u32 reg, major, minor;
> int i;
> /*
> * On MMU-500 r2p0 onwards we need to clear ACR.CACHE_LOCK before
> @@ -118,6 +118,7 @@ int arm_mmu500_reset(struct arm_smmu_device *smmu)
> */
> reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID7);
> major = FIELD_GET(ARM_SMMU_ID7_MAJOR, reg);
> + minor = FIELD_GET(ARM_SMMU_ID7_MINOR, reg);
> reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sACR);
> if (major >= 2)
> reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
> @@ -131,14 +132,18 @@ int arm_mmu500_reset(struct arm_smmu_device *smmu)
> /*
> * Disable MMU-500's not-particularly-beneficial next-page
> * prefetcher for the sake of errata #841119 and #826419.
> + * These errata only affect r0p0 through r2p1 (fixed in r2p2).
> */
> - for (i = 0; i < smmu->num_context_banks; ++i) {
> - reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
> - reg &= ~ARM_MMU500_ACTLR_CPRE;
> - arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
> - reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
> - if (reg & ARM_MMU500_ACTLR_CPRE)
> - dev_warn_once(smmu->dev, "Failed to disable prefetcher [errata #841119 and #826419], check ACR.CACHE_LOCK\n");
> + if (major < 2 || (major == 2 && minor < 2)) {
> + for (i = 0; i < smmu->num_context_banks; ++i) {
> + reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
> + reg &= ~ARM_MMU500_ACTLR_CPRE;
> + arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
> + reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
> + if (reg & ARM_MMU500_ACTLR_CPRE)
> + dev_warn_once(smmu->dev,
> + "Failed to disable prefetcher [errata #841119 and #826419], check ACR.CACHE_LOCK\n");
> + }
> }
>
> return 0;
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* Re: [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement
2024-05-14 16:54 0% ` Florian Fainelli
@ 2024-05-14 17:03 0% ` Russell King (Oracle)
2024-05-14 18:26 0% ` Florian Fainelli
0 siblings, 1 reply; 200+ results
From: Russell King (Oracle) @ 2024-05-14 17:03 UTC (permalink / raw)
To: Florian Fainelli
Cc: Geert Uytterhoeven, Ard Biesheuvel, Linus Walleij, Arnd Bergmann,
Stefan Wahren, Kees Cook, linux-arm-kernel, Catalin Marinas
On Tue, May 14, 2024 at 09:54:07AM -0700, Florian Fainelli wrote:
> On 5/14/24 09:06, Geert Uytterhoeven wrote:
> > On Tue, May 14, 2024 at 1:28 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Tue, May 14, 2024 at 10:25 AM Ard Biesheuvel <ardb@kernel.org> wrote:
> > > > On Tue, 14 May 2024 at 10:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > On Tue, May 14, 2024 at 9:59 AM Ard Biesheuvel <ardb@kernel.org> wrote:
> > > > > > On Tue, 14 May 2024 at 09:46, Linus Walleij <linus.walleij@linaro.org> wrote:
> > > > > > > On Tue, May 14, 2024 at 8:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > > >
> > > > > > > > I sent you a small initramfs by PM.
> > > > > > >
> > > > > > > Booted this just fine on Vexpress QEMU:
> > > > > > >
> > > > > > > Run /init as init process
> > > > > > > sysctl: error: 'kernel.hotplug' is an unknown key
> > > > > > >
> > > > > > >
> > > > > > > boot (Linux 6.9.0-rc1+, BusyBox v1.16.0.git, kexec-tools 2.0.1-git)
> > > > > > > / # mount -t debugfs none /sys/kernel/debug
> > > > > > > / # echo "ACCESS_USERSPACE" | cat >/sys/kernel/debug/provoke-crash/DIRECT
> > > > > > > lkdtm: Performing direct entry ACCESS_USERSPACE
> > > > > > > lkdtm: attempting bad read at 76fea000
> > > > > > > 8<--- cut here ---
> > > > > > > Unable to handle kernel paging request at virtual address 76fea000 when read
> > > > > > > [76fea000] *pgd=82c93003, *pmd=82c94003, *pte=a00000811e2f5f
> > > > > > > Internal error: Oops: 206 [#1] SMP ARM
> > > > > > > CPU: 1 PID: 86 Comm: cat Not tainted 6.9.0-rc1+ #46
> > > > > > > Hardware name: ARM-Versatile Express
> > > > > > > PC is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> > > > > > > LR is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> > > > > > >
> > > > > > > I'm starting to think it is something about different LPAE implementations here.
> > > > > >
> > > > > > I have built multi_v7_defconfig with the following enabled
> > > > > >
> > > > > > CONFIG_ARM_LPAE=y
> > > > > > CONFIG_CPU_TTBR0_PAN=y
> > > > > > CONFIG_LKDTM=y
> > > > > >
> > > > > > and the resulting kernel boots happily as a 32-bit VM running under a
> > > > > > Rpi4 KVM host.
> > > > > >
> > > > > > Could someone post an actual .config that reproduces this? Rpi4 is
> > > > > > A72, which both works and doesn't work in Florian's testing, so I'd be
> > > > > > highly surprised if this is not a config issue.
> > > > >
> > > > > shmobile_defconfig with CONFIG_LPAE=y added failed for me before.
> > > > >
> > > > > Building multi_v7_defconfig with the above enabled...
> > >
> > > And that works, while shmobile_defconfig with the above does not!
> > > So it is config-related.
> >
> > I ran tools/testing/ktest/config-bisect.pl and found the "offending"
> > config option: CONFIG_CC_OPTIMIZE_FOR_SIZE=y gives a broken
> > kernel, CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y works.
> > (verified by just enabling CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE in my
> > broken config)....
>
> I second that, my working configuration has
> CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y whereas my
> broken one has CONFIG_CC_OPTIMIZE_FOR_SIZE=y, sure enough, changing the
> broken configuration to have CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y turns it
> into a "working" configuration on the Raspberry Pi 4B in AArch32 mode.
>
> That makes more sense because BCM7211 and BCM2711 are exactly the same CPU,
> thanks for restoring sanity!
I would imagine that the problem is cpu_set_ttbcr(). Please try adding
a "memory" clobber to the asm() instruction in there.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
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* Re: [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement
2024-05-14 16:06 0% ` Geert Uytterhoeven
@ 2024-05-14 16:54 0% ` Florian Fainelli
2024-05-14 17:03 0% ` Russell King (Oracle)
0 siblings, 1 reply; 200+ results
From: Florian Fainelli @ 2024-05-14 16:54 UTC (permalink / raw)
To: Geert Uytterhoeven, Ard Biesheuvel
Cc: Linus Walleij, Russell King, Arnd Bergmann, Stefan Wahren,
Kees Cook, linux-arm-kernel, Catalin Marinas
On 5/14/24 09:06, Geert Uytterhoeven wrote:
> On Tue, May 14, 2024 at 1:28 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>> On Tue, May 14, 2024 at 10:25 AM Ard Biesheuvel <ardb@kernel.org> wrote:
>>> On Tue, 14 May 2024 at 10:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>>>> On Tue, May 14, 2024 at 9:59 AM Ard Biesheuvel <ardb@kernel.org> wrote:
>>>>> On Tue, 14 May 2024 at 09:46, Linus Walleij <linus.walleij@linaro.org> wrote:
>>>>>> On Tue, May 14, 2024 at 8:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>>>>>>
>>>>>>> I sent you a small initramfs by PM.
>>>>>>
>>>>>> Booted this just fine on Vexpress QEMU:
>>>>>>
>>>>>> Run /init as init process
>>>>>> sysctl: error: 'kernel.hotplug' is an unknown key
>>>>>>
>>>>>>
>>>>>> boot (Linux 6.9.0-rc1+, BusyBox v1.16.0.git, kexec-tools 2.0.1-git)
>>>>>> / # mount -t debugfs none /sys/kernel/debug
>>>>>> / # echo "ACCESS_USERSPACE" | cat >/sys/kernel/debug/provoke-crash/DIRECT
>>>>>> lkdtm: Performing direct entry ACCESS_USERSPACE
>>>>>> lkdtm: attempting bad read at 76fea000
>>>>>> 8<--- cut here ---
>>>>>> Unable to handle kernel paging request at virtual address 76fea000 when read
>>>>>> [76fea000] *pgd=82c93003, *pmd=82c94003, *pte=a00000811e2f5f
>>>>>> Internal error: Oops: 206 [#1] SMP ARM
>>>>>> CPU: 1 PID: 86 Comm: cat Not tainted 6.9.0-rc1+ #46
>>>>>> Hardware name: ARM-Versatile Express
>>>>>> PC is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
>>>>>> LR is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
>>>>>>
>>>>>> I'm starting to think it is something about different LPAE implementations here.
>>>>>
>>>>> I have built multi_v7_defconfig with the following enabled
>>>>>
>>>>> CONFIG_ARM_LPAE=y
>>>>> CONFIG_CPU_TTBR0_PAN=y
>>>>> CONFIG_LKDTM=y
>>>>>
>>>>> and the resulting kernel boots happily as a 32-bit VM running under a
>>>>> Rpi4 KVM host.
>>>>>
>>>>> Could someone post an actual .config that reproduces this? Rpi4 is
>>>>> A72, which both works and doesn't work in Florian's testing, so I'd be
>>>>> highly surprised if this is not a config issue.
>>>>
>>>> shmobile_defconfig with CONFIG_LPAE=y added failed for me before.
>>>>
>>>> Building multi_v7_defconfig with the above enabled...
>>
>> And that works, while shmobile_defconfig with the above does not!
>> So it is config-related.
>
> I ran tools/testing/ktest/config-bisect.pl and found the "offending"
> config option: CONFIG_CC_OPTIMIZE_FOR_SIZE=y gives a broken
> kernel, CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y works.
> (verified by just enabling CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE in my
> broken config)....
I second that, my working configuration has
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y whereas my
broken one has CONFIG_CC_OPTIMIZE_FOR_SIZE=y, sure enough, changing the
broken configuration to have CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y turns
it into a "working" configuration on the Raspberry Pi 4B in AArch32 mode.
That makes more sense because BCM7211 and BCM2711 are exactly the same
CPU, thanks for restoring sanity!
--
Florian
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* Re: [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement
2024-05-14 11:28 0% ` Geert Uytterhoeven
@ 2024-05-14 16:06 0% ` Geert Uytterhoeven
2024-05-14 16:54 0% ` Florian Fainelli
0 siblings, 1 reply; 200+ results
From: Geert Uytterhoeven @ 2024-05-14 16:06 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Linus Walleij, Russell King, Arnd Bergmann, Stefan Wahren,
Kees Cook, linux-arm-kernel, Catalin Marinas
On Tue, May 14, 2024 at 1:28 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Tue, May 14, 2024 at 10:25 AM Ard Biesheuvel <ardb@kernel.org> wrote:
> > On Tue, 14 May 2024 at 10:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Tue, May 14, 2024 at 9:59 AM Ard Biesheuvel <ardb@kernel.org> wrote:
> > > > On Tue, 14 May 2024 at 09:46, Linus Walleij <linus.walleij@linaro.org> wrote:
> > > > > On Tue, May 14, 2024 at 8:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > >
> > > > > > I sent you a small initramfs by PM.
> > > > >
> > > > > Booted this just fine on Vexpress QEMU:
> > > > >
> > > > > Run /init as init process
> > > > > sysctl: error: 'kernel.hotplug' is an unknown key
> > > > >
> > > > >
> > > > > boot (Linux 6.9.0-rc1+, BusyBox v1.16.0.git, kexec-tools 2.0.1-git)
> > > > > / # mount -t debugfs none /sys/kernel/debug
> > > > > / # echo "ACCESS_USERSPACE" | cat >/sys/kernel/debug/provoke-crash/DIRECT
> > > > > lkdtm: Performing direct entry ACCESS_USERSPACE
> > > > > lkdtm: attempting bad read at 76fea000
> > > > > 8<--- cut here ---
> > > > > Unable to handle kernel paging request at virtual address 76fea000 when read
> > > > > [76fea000] *pgd=82c93003, *pmd=82c94003, *pte=a00000811e2f5f
> > > > > Internal error: Oops: 206 [#1] SMP ARM
> > > > > CPU: 1 PID: 86 Comm: cat Not tainted 6.9.0-rc1+ #46
> > > > > Hardware name: ARM-Versatile Express
> > > > > PC is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> > > > > LR is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> > > > >
> > > > > I'm starting to think it is something about different LPAE implementations here.
> > > >
> > > > I have built multi_v7_defconfig with the following enabled
> > > >
> > > > CONFIG_ARM_LPAE=y
> > > > CONFIG_CPU_TTBR0_PAN=y
> > > > CONFIG_LKDTM=y
> > > >
> > > > and the resulting kernel boots happily as a 32-bit VM running under a
> > > > Rpi4 KVM host.
> > > >
> > > > Could someone post an actual .config that reproduces this? Rpi4 is
> > > > A72, which both works and doesn't work in Florian's testing, so I'd be
> > > > highly surprised if this is not a config issue.
> > >
> > > shmobile_defconfig with CONFIG_LPAE=y added failed for me before.
> > >
> > > Building multi_v7_defconfig with the above enabled...
>
> And that works, while shmobile_defconfig with the above does not!
> So it is config-related.
I ran tools/testing/ktest/config-bisect.pl and found the "offending"
config option: CONFIG_CC_OPTIMIZE_FOR_SIZE=y gives a broken
kernel, CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y works.
(verified by just enabling CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE in my
broken config)....
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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* Re: [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement
2024-05-14 12:38 6% ` Russell King (Oracle)
@ 2024-05-14 15:03 0% ` Catalin Marinas
0 siblings, 0 replies; 200+ results
From: Catalin Marinas @ 2024-05-14 15:03 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Geert Uytterhoeven, Florian Fainelli, Linus Walleij,
Ard Biesheuvel, Arnd Bergmann, Stefan Wahren, Kees Cook,
linux-arm-kernel
On Tue, May 14, 2024 at 01:38:07PM +0100, Russell King wrote:
> On Tue, May 14, 2024 at 02:32:23PM +0200, Geert Uytterhoeven wrote:
> > On Tue, May 14, 2024 at 1:33 PM Russell King (Oracle)
> > <linux@armlinux.org.uk> wrote:
> > > On Tue, May 14, 2024 at 01:22:36PM +0200, Geert Uytterhoeven wrote:
> > > > On Tue, May 14, 2024 at 10:15 AM Russell King (Oracle)
> > > > <linux@armlinux.org.uk> wrote:
> > > > > On Mon, May 13, 2024 at 08:56:20PM -0700, Florian Fainelli wrote:
> > > > > > [ 11.299106] Freeing unused kernel image (initmem) memory: 79872K
> > > > > > [ 11.305720] Run /init as init process
> > > > > > [ 11.314070] Kernel panic - not syncing: Attempted to kill init!
> > > > > > exitcode=0x00000004
> > > > > > [ 11.321888] CPU: 0 PID: 1 Comm: init Not tainted 6.9.0-next-20240513 #32
> > > > > > [ 11.328709] Hardware name: BCM2711
> > > > > > [ 11.332169] Call trace:
> > > > > > [ 11.332179] unwind_backtrace from show_stack+0x10/0x14
> > > > > > [ 11.340087] show_stack from panic+0x20c/0x55c
> > > > > > [ 11.344615] panic from do_exit+0x6b0/0x1e74
> > > > > > [ 11.348972] do_exit from do_group_exit+0xcc/0x280
> > > > > > [ 11.353857] do_group_exit from get_signal+0xfb4/0x1340
> > > > > > [ 11.359182] get_signal from do_work_pending+0x2c0/0x7bc
> > > > > > [ 11.364590] do_work_pending from slow_work_pending+0xc/0x24
> > > > > > [ 11.370351] Exception stack(0xf082bfb0 to 0xf082bff8)
> > > > > > [ 11.375492] bfa0: b6bca568 00000000
> > > > > > 003fa0d6 aedf3d20
> > > > > > [ 11.383811] bfc0: aedf4a28 b6bca6f8 b6bca73c b6bca710 b6bca748 b6bca6f8
> > > > > > aedf4a28 b6bca6f8
> > > > > > [ 11.392127] bfe0: b6bca590 b6bca548 aeddae15 aedeb660 200f0030 ffffffff
> > > > > > [ 11.398954] ---[ end Kernel panic - not syncing: Attempted to kill init!
> > > > > > exitcode=0x00000004 ]---
> > > > >
> > > > > You could enable CONFiG_DEBUG_USER, and then pass "user_debug=24" to
> > > > > the kernel to get a report for the conditions that lead to SEGV/BUS
> > > > > signals being delivered to a userspace processd.
> > > >
> > > > That does not seem to make any difference for me, i.e. no report?
> > >
> > > Then it's not a SEGV/BUS (iow page fault.) Please try user_debug=31
> > > in that case. Thanks.
> >
> > Thanks, much better:
> >
> > init (1): undefined instruction: pc=b6f4feda
> > CPU: 1 PID: 1 Comm: init Not tainted
> > 6.9.0-shmobile-09158-g1218ffc3659e #1820
> > Hardware name: Generic R-Car Gen2 (Flattened Device Tree)
> > PC is at 0xb6f4feda
> > LR is at 0xb6f4ed31
> > pc : [<b6f4feda>] lr : [<b6f4ed31>] psr: 60000030
> > sp : be970630 ip : be970678 fp : b6f67978
> > r10: 00000000 r9 : 004d48ff r8 : be970844
> > r7 : be9707f8 r6 : b6f67978 r5 : be970850 r4 : be970844
> > r3 : b6f669b0 r2 : 003fb0d6 r1 : 00000000 r0 : be970650
> > Flags: nZCv IRQs on FIQs on Mode USER_32 ISA Thumb Segment user
> > Control: 30c5387d Table: 41f6cac0 DAC: 55555555
> > Code: bad PC value
>
> Well, that points to another issue... get_user() appears to be unable
> to access userspace. Userspace can, however, as we wouldn't get an
> undefined instruction abort unless it can successfully access the
> address.
>
> This points to something being very wrong with this implementation.
Yeah, it doesn't look great. Let's see if TLBIALLIS solves anything,
though not as an upstream solution as it's expensive, just to understand
the problem a bit better. So maybe revert the last patch from the
series, the first three seem inoffensive.
For the flush_tlb_all(), I think the mcr incantation is:
mov r0, #0
mcr p15, 0, r0, c8, c7, 0
Linus, if you attempt this in the uaccess_enable/disable macros, also
force the ISB to be always on just in case the TTBRC update does not
take place before the MCR.
--
Catalin
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^ permalink raw reply [relevance 0%]
* Re: [PATCH 16/17] mfd: Add support for LAN966x PCI device
2024-05-08 8:20 0% ` Steen.Hegelund
@ 2024-05-14 12:55 0% ` Herve Codina
0 siblings, 0 replies; 200+ results
From: Herve Codina @ 2024-05-14 12:55 UTC (permalink / raw)
To: Steen.Hegelund
Cc: tglx, robh, krzk+dt, conor+dt, davem, edumazet, kuba, pabeni,
lee, arnd, Horatiu.Vultur, UNGLinuxDriver, andrew, hkallweit1,
linux, saravanak, bhelgaas, p.zabel, Lars.Povlsen, Daniel.Machon,
alexandre.belloni, linux-kernel, devicetree, netdev, linux-pci,
linux-arm-kernel, Allan.Nielsen, luca.ceresoli, thomas.petazzoni
Hi Steen,
On Wed, 8 May 2024 08:20:04 +0000
<Steen.Hegelund@microchip.com> wrote:
...
> > +
> > +static irqreturn_t pci_dev_irq_handler(int irq, void *data)
> > +{
> > + struct pci_dev_intr_ctrl *intr_ctrl = data;
> > + int ret;
> > +
> > + ret = generic_handle_domain_irq(intr_ctrl->irq_domain, 0);
> > + return ret ? IRQ_NONE : IRQ_HANDLED;
> > +}
> > +
> > +static struct pci_dev_intr_ctrl *pci_dev_create_intr_ctrl(struct pci_dev *pdev)
> > +{
> > + struct pci_dev_intr_ctrl *intr_ctrl;
> > + struct fwnode_handle *fwnode;
> > + int ret;
> > +
> > + if (!pdev->irq)
> > + return ERR_PTR(-EOPNOTSUPP);
> > +
> > + fwnode = dev_fwnode(&pdev->dev);
> > + if (!fwnode)
> > + return ERR_PTR(-ENODEV);
> > +
> > + intr_ctrl = kmalloc(sizeof(*intr_ctrl), GFP_KERNEL);
> > + if (!intr_ctrl)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + intr_ctrl->pci_dev = pdev;
> > +
> > + intr_ctrl->irq_domain = irq_domain_create_linear(fwnode, 1, &pci_dev_irq_domain_ops,
> > + intr_ctrl);
> > + if (!intr_ctrl->irq_domain) {
> > + pci_err(pdev, "Failed to create irqdomain\n");
> > + ret = -ENOMEM;
> > + goto err_free_intr_ctrl;
> > + }
> > +
> > + ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
> > + if (ret < 0) {
> > + pci_err(pdev, "Unable alloc irq vector (%d)\n", ret);
> > + goto err_remove_domain;
> > + }
> > + intr_ctrl->irq = pci_irq_vector(pdev, 0);
> > + ret = request_irq(intr_ctrl->irq, pci_dev_irq_handler, IRQF_SHARED,
> > + dev_name(&pdev->dev), intr_ctrl);
> > + if (ret) {
> > + pci_err(pdev, "Unable to request irq %d (%d)\n", intr_ctrl->irq, ret);
> > + goto err_free_irq_vector;
> > + }
> > +
> > + return intr_ctrl;
> > +
> > +err_free_irq_vector:
> > + pci_free_irq_vectors(pdev);
> > +err_remove_domain:
> > + irq_domain_remove(intr_ctrl->irq_domain);
> > +err_free_intr_ctrl:
> > + kfree(intr_ctrl);
> > + return ERR_PTR(ret);
> > +}
> > +
> > +static void pci_dev_remove_intr_ctrl(struct pci_dev_intr_ctrl *intr_ctrl)
> > +{
> > + free_irq(intr_ctrl->irq, intr_ctrl);
> > + pci_free_irq_vectors(intr_ctrl->pci_dev);
> > + irq_dispose_mapping(irq_find_mapping(intr_ctrl->irq_domain, 0));
> > + irq_domain_remove(intr_ctrl->irq_domain);
> > + kfree(intr_ctrl);
> > +}
> > +
>
> It looks like the two functions below (and their helper functions) are so
> generic that they could be part of the pci driver core support.
> Any plans for that?
Indeed, I tried to write them in a generic way.
Right now, at least for the next iteration of this series, I don't plan to
move them as part of the PCI code.
This piece of code did not get any feedback and I would prefer to keep them
here for the moment.
Of course, they could be move out of the LAN966x PCI driver later.
>
> > +static void devm_pci_dev_remove_intr_ctrl(void *data)
> > +{
> > + struct pci_dev_intr_ctrl *intr_ctrl = data;
> > +
> > + pci_dev_remove_intr_ctrl(intr_ctrl);
> > +}
> > +
> > +static int devm_pci_dev_create_intr_ctrl(struct pci_dev *pdev)
> > +{
> > + struct pci_dev_intr_ctrl *intr_ctrl;
> > +
> > + intr_ctrl = pci_dev_create_intr_ctrl(pdev);
> > +
> > + if (IS_ERR(intr_ctrl))
> > + return PTR_ERR(intr_ctrl);
> > +
> > + return devm_add_action_or_reset(&pdev->dev, devm_pci_dev_remove_intr_ctrl, intr_ctrl);
> > +}
> > +
>
Best regards,
Hervé
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement
@ 2024-05-14 12:38 6% ` Russell King (Oracle)
2024-05-14 15:03 0% ` Catalin Marinas
0 siblings, 1 reply; 200+ results
From: Russell King (Oracle) @ 2024-05-14 12:38 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Florian Fainelli, Linus Walleij, Ard Biesheuvel, Arnd Bergmann,
Stefan Wahren, Kees Cook, linux-arm-kernel, Catalin Marinas
On Tue, May 14, 2024 at 02:32:23PM +0200, Geert Uytterhoeven wrote:
> Hi Russell,
>
> On Tue, May 14, 2024 at 1:33 PM Russell King (Oracle)
> <linux@armlinux.org.uk> wrote:
> > On Tue, May 14, 2024 at 01:22:36PM +0200, Geert Uytterhoeven wrote:
> > > On Tue, May 14, 2024 at 10:15 AM Russell King (Oracle)
> > > <linux@armlinux.org.uk> wrote:
> > > > On Mon, May 13, 2024 at 08:56:20PM -0700, Florian Fainelli wrote:
> > > > > [ 11.299106] Freeing unused kernel image (initmem) memory: 79872K
> > > > > [ 11.305720] Run /init as init process
> > > > > [ 11.314070] Kernel panic - not syncing: Attempted to kill init!
> > > > > exitcode=0x00000004
> > > > > [ 11.321888] CPU: 0 PID: 1 Comm: init Not tainted 6.9.0-next-20240513 #32
> > > > > [ 11.328709] Hardware name: BCM2711
> > > > > [ 11.332169] Call trace:
> > > > > [ 11.332179] unwind_backtrace from show_stack+0x10/0x14
> > > > > [ 11.340087] show_stack from panic+0x20c/0x55c
> > > > > [ 11.344615] panic from do_exit+0x6b0/0x1e74
> > > > > [ 11.348972] do_exit from do_group_exit+0xcc/0x280
> > > > > [ 11.353857] do_group_exit from get_signal+0xfb4/0x1340
> > > > > [ 11.359182] get_signal from do_work_pending+0x2c0/0x7bc
> > > > > [ 11.364590] do_work_pending from slow_work_pending+0xc/0x24
> > > > > [ 11.370351] Exception stack(0xf082bfb0 to 0xf082bff8)
> > > > > [ 11.375492] bfa0: b6bca568 00000000
> > > > > 003fa0d6 aedf3d20
> > > > > [ 11.383811] bfc0: aedf4a28 b6bca6f8 b6bca73c b6bca710 b6bca748 b6bca6f8
> > > > > aedf4a28 b6bca6f8
> > > > > [ 11.392127] bfe0: b6bca590 b6bca548 aeddae15 aedeb660 200f0030 ffffffff
> > > > > [ 11.398954] ---[ end Kernel panic - not syncing: Attempted to kill init!
> > > > > exitcode=0x00000004 ]---
> > > >
> > > > You could enable CONFiG_DEBUG_USER, and then pass "user_debug=24" to
> > > > the kernel to get a report for the conditions that lead to SEGV/BUS
> > > > signals being delivered to a userspace processd.
> > >
> > > That does not seem to make any difference for me, i.e. no report?
> >
> > Then it's not a SEGV/BUS (iow page fault.) Please try user_debug=31
> > in that case. Thanks.
>
> Thanks, much better:
>
> init (1): undefined instruction: pc=b6f4feda
> CPU: 1 PID: 1 Comm: init Not tainted
> 6.9.0-shmobile-09158-g1218ffc3659e #1820
> Hardware name: Generic R-Car Gen2 (Flattened Device Tree)
> PC is at 0xb6f4feda
> LR is at 0xb6f4ed31
> pc : [<b6f4feda>] lr : [<b6f4ed31>] psr: 60000030
> sp : be970630 ip : be970678 fp : b6f67978
> r10: 00000000 r9 : 004d48ff r8 : be970844
> r7 : be9707f8 r6 : b6f67978 r5 : be970850 r4 : be970844
> r3 : b6f669b0 r2 : 003fb0d6 r1 : 00000000 r0 : be970650
> Flags: nZCv IRQs on FIQs on Mode USER_32 ISA Thumb Segment user
> Control: 30c5387d Table: 41f6cac0 DAC: 55555555
> Code: bad PC value
Well, that points to another issue... get_user() appears to be unable
to access userspace. Userspace can, however, as we wouldn't get an
undefined instruction abort unless it can successfully access the
address.
This points to something being very wrong with this implementation.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
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^ permalink raw reply [relevance 6%]
* Re: [PATCH v2 0/3] drm/mediatek: Add support for OF graphs
@ 2024-05-14 12:00 6% ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 200+ results
From: AngeloGioacchino Del Regno @ 2024-05-14 12:00 UTC (permalink / raw)
To: Alexandre Mergnat, chunkuang.hu
Cc: robh, krzysztof.kozlowski+dt, conor+dt, p.zabel, airlied, daniel,
maarten.lankhorst, mripard, tzimmermann, matthias.bgg,
shawn.sung, yu-chang.lee, ck.hu, jitao.shi, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel, wenst,
kernel
Il 14/05/24 11:46, Alexandre Mergnat ha scritto:
> Hi Angelo,
>
> Gentle ping because I'm stuck if I rebase my serie on top of yours.
>
Sorry, I was unable to find time to get back to this... I plan to look at it
between today and tomorrow.
In the meanwhile - does your platform use OVL_ADAPTOR?
If it does, that's the actual issue; otherwise, there may be some mistake on
your side, because the EPs' ports<->ids relationship was verified before sending
this to the lists.
Cheers,
Angelo
> On 02/05/2024 18:53, Alexandre Mergnat wrote:
>>
>>
>> On 30/04/2024 13:33, AngeloGioacchino Del Regno wrote:
>>> Il 30/04/24 12:17, Alexandre Mergnat ha scritto:
>>>> Hi Angelo,
>>>>
>>>> On 09/04/2024 14:02, AngeloGioacchino Del Regno wrote:
>>>>> This series was tested on MT8195 Cherry Tomato and on MT8395 Radxa
>>>>> NIO-12L with both hardcoded paths, OF graph support and partially
>>>>> hardcoded paths (meaning main display through OF graph and external
>>>>> display hardcoded, because of OVL_ADAPTOR).
>>>>
>>>> Is that make sense for you to add the DTS changes of these boards into this
>>>> serie ?
>>>> I asked because, IMHO, that could help to understand the serie.
>>>>
>>>
>>> Yes and no... but I imagine that you're asking this because you're trying to
>>> prepare something with a different SoC+board(s) combination :-)
>>>
>>> In that case, I'm preventively sorry because what follows here is not 100%
>>> perfectly tidy yet as I didn't mean to send the devicetree commits upstream
>>> before this series got picked....
>>>
>>> ... but there you go - I'm sure that you won't mind and that the example will
>>> be more than good enough for you.
>>>
>>> Please note that one of the reasons why I didn't want to add this to the series
>>> is that the following changes show only a mere 50% of the reasons why we want OF
>>> graph support on mediatek-drm (but mainly, it's because I didn't have time to
>>> actually rebase etc :-P )
>>
>> Thanks for the explanations and examples.
>> Unfortunately, I have 2 display but only one is working (the main: DSI0) when I
>> use the dts method.
>> I've probably missed something but I don't know what.
>>
>> In my "mmsys" node, if I swap display (the ext endpoint with the main endpoint),
>> the DPI0 is working, but not the DSI0. I conclude my both paths are good.
>>
>> Then, I've put some trace into "mtk_drm_of_ddp_path_build" to check if it parse
>> the two endpoint of the node. Both are parsed, but "of_ep.port" is always = 0.
>> According to "of_graph_parse_endpoint" function, "port" is the value of the
>> parent "reg", whereas "id" is the value of the endpoint "reg".
>> So I replaced "of_ep.port" by "of_ep.id". Now I've of_ep.id = 0 for main and
>> of_ep.id = 1 for EXT.
>>
>> Now I've the good CRTC path, I get this error:
>> mediatek-drm mediatek-drm.1.auto: Invalid display hw pipeline. Last component:
>> 54 (ret=-2)
>> mediatek-drm mediatek-drm.1.auto: probe with driver mediatek-drm failed with
>> error -22
>>
>> After quick look, the "cpath" into "mtk_drm_of_ddp_path_build_one" (or deeper
>> functions) seems not be used as it should, due to the previous "of_ep.port" =>
>> "of_ep.id" change of course.
>>
>> But I probably have to fix "of_ep.port" because I've mis-coded something. Just in
>> case, I share you my diff:
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
>> b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
>> index 1aa3426f561b..f660481d3fe8 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
>> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
>> @@ -109,15 +109,51 @@ vsys_lcm_reg: regulator-vsys-lcm {
>> };
>> };
>>
>> +&cpu0 {
>> + proc-supply = <&mt6357_vproc_reg>;
>> + sram-supply = <&mt6357_vsram_proc_reg>;
>> +};
>> +
>> +&cpu1 {
>> + proc-supply = <&mt6357_vproc_reg>;
>> + sram-supply = <&mt6357_vsram_proc_reg>;
>> +};
>> +
>> +&cpu2 {
>> + proc-supply = <&mt6357_vproc_reg>;
>> + sram-supply = <&mt6357_vsram_proc_reg>;
>> +};
>> +
>> +&cpu3 {
>> + proc-supply = <&mt6357_vproc_reg>;
>> + sram-supply = <&mt6357_vsram_proc_reg>;
>> +};
>> +
>> +&dither0_out {
>> + remote-endpoint = <&dsi0_in>;
>> +};
>> +
>> &dpi0 {
>> pinctrl-0 = <&dpi_default_pins>;
>> pinctrl-1 = <&dpi_idle_pins>;
>> pinctrl-names = "default", "sleep";
>> status = "okay";
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>>
>> - port {
>> - dpi_out: endpoint {
>> - remote-endpoint = <&it66121_in>;
>> + port@0 {
>> + reg = <0>;
>> + dpi0_in: endpoint {
>> + remote-endpoint = <&rdma1_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + dpi0_out: endpoint {
>> + remote-endpoint = <&it66121_in>;
>> + };
>> };
>> };
>> };
>> @@ -137,36 +173,28 @@ panel@0 {
>>
>> port {
>> panel_in: endpoint {
>> - remote-endpoint = <&dsi_out>;
>> + remote-endpoint = <&dsi0_out>;
>> };
>> };
>> };
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>>
>> - port {
>> - dsi_out: endpoint {
>> - remote-endpoint = <&panel_in>;
>> + port@0 {
>> + reg = <0>;
>> + dsi0_in: endpoint {
>> + remote-endpoint = <&dither0_out>;
>> + };
>> };
>> - };
>> -};
>>
>> -&cpu0 {
>> - proc-supply = <&mt6357_vproc_reg>;
>> - sram-supply = <&mt6357_vsram_proc_reg>;
>> -};
>> -
>> -&cpu1 {
>> - proc-supply = <&mt6357_vproc_reg>;
>> - sram-supply = <&mt6357_vsram_proc_reg>;
>> -};
>> -
>> -&cpu2 {
>> - proc-supply = <&mt6357_vproc_reg>;
>> - sram-supply = <&mt6357_vsram_proc_reg>;
>> -};
>> -
>> -&cpu3 {
>> - proc-supply = <&mt6357_vproc_reg>;
>> - sram-supply = <&mt6357_vsram_proc_reg>;
>> + port@1 {
>> + reg = <1>;
>> + dsi0_out: endpoint {
>> + remote-endpoint = <&panel_in>;
>> + };
>> + };
>> + };
>> };
>>
>> ðernet {
>> @@ -229,7 +257,7 @@ port@0 {
>> reg = <0>;
>> it66121_in: endpoint {
>> bus-width = <12>;
>> - remote-endpoint = <&dpi_out>;
>> + remote-endpoint = <&dpi0_out>;
>> };
>> };
>>
>> @@ -557,6 +585,10 @@ &pwm {
>> status = "okay";
>> };
>>
>> +&rdma1_out {
>> + remote-endpoint = <&dpi0_in>;
>> +};
>> +
>> &ssusb {
>> dr_mode = "otg";
>> maximum-speed = "high-speed";
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
>> index d34519a33c90..dbb559959a9d 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
>> @@ -762,6 +762,19 @@ mmsys: syscon@14000000 {
>> compatible = "mediatek,mt8365-mmsys", "syscon";
>> reg = <0 0x14000000 0 0x1000>;
>> #clock-cells = <1>;
>> + port {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + mmsys_main: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&ovl0_in>;
>> + };
>> + mmsys_ext: endpoint@1 {
>> + reg = <1>;
>> + remote-endpoint = <&rdma1_in>;
>> + };
>> + };
>> };
>>
>> mutex: mutex@14001000 {
>> @@ -801,6 +814,24 @@ ovl0: ovl@1400b000 {
>> interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
>> iommus = <&iommu M4U_PORT_DISP_OVL0>;
>> power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + ovl0_in: endpoint {
>> + remote-endpoint = <&mmsys_main>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + ovl0_out: endpoint {
>> + remote-endpoint = <&rdma0_in>;
>> + };
>> + };
>> + };
>> };
>>
>> rdma0: rdma@1400d000 {
>> @@ -811,6 +842,24 @@ rdma0: rdma@1400d000 {
>> iommus = <&iommu M4U_PORT_DISP_RDMA0>;
>> mediatek,rdma-fifo-size = <5120>;
>> power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + rdma0_in: endpoint {
>> + remote-endpoint = <&ovl0_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + rdma0_out: endpoint {
>> + remote-endpoint = <&color0_in>;
>> + };
>> + };
>> + };
>> };
>>
>> color0: color@1400f000 {
>> @@ -819,6 +868,24 @@ color0: color@1400f000 {
>> clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>;
>> interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
>> power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + color0_in: endpoint {
>> + remote-endpoint = <&rdma0_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + color0_out: endpoint {
>> + remote-endpoint = <&ccorr0_in>;
>> + };
>> + };
>> + };
>> };
>>
>> ccorr0: ccorr@14010000 {
>> @@ -827,6 +894,24 @@ ccorr0: ccorr@14010000 {
>> clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>;
>> interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>;
>> power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + ccorr0_in: endpoint {
>> + remote-endpoint = <&color0_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + ccorr0_out: endpoint {
>> + remote-endpoint = <&aal0_in>;
>> + };
>> + };
>> + };
>> };
>>
>> aal0: aal@14011000 {
>> @@ -835,6 +920,24 @@ aal0: aal@14011000 {
>> clocks = <&mmsys CLK_MM_MM_DISP_AAL0>;
>> interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
>> power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + aal0_in: endpoint {
>> + remote-endpoint = <&ccorr0_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + aal0_out: endpoint {
>> + remote-endpoint = <&gamma0_in>;
>> + };
>> + };
>> + };
>> };
>>
>> gamma0: gamma@14012000 {
>> @@ -843,6 +946,24 @@ gamma0: gamma@14012000 {
>> clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>;
>> interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
>> power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + gamma0_in: endpoint {
>> + remote-endpoint = <&aal0_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + gamma0_out: endpoint {
>> + remote-endpoint = <&dither0_in>;
>> + };
>> + };
>> + };
>> };
>>
>> dither0: dither@14013000 {
>> @@ -851,6 +972,23 @@ dither0: dither@14013000 {
>> clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>;
>> interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
>> power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + dither0_in: endpoint {
>> + remote-endpoint = <&gamma0_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + dither0_out: endpoint {
>> + };
>> + };
>> + };
>> };
>>
>> dsi0: dsi@14014000 {
>> @@ -874,6 +1012,23 @@ rdma1: rdma@14016000 {
>> iommus = <&iommu M4U_PORT_DISP_RDMA1>;
>> mediatek,rdma-fifo-size = <2048>;
>> power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + rdma1_in: endpoint {
>> + remote-endpoint = <&mmsys_ext>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + rdma1_out: endpoint {
>> + };
>> + };
>> + };
>> };
>>
>> dpi0: dpi@14018000 {
>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> index dacf4eaa3457..5992b7865310 100644
>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> @@ -230,22 +230,6 @@ static const unsigned int mt8195_mtk_ddp_ext[] = {
>> DDP_COMPONENT_DP_INTF1,
>> };
>>
>> -static const unsigned int mt8365_mtk_ddp_main[] = {
>> - DDP_COMPONENT_OVL0,
>> - DDP_COMPONENT_RDMA0,
>> - DDP_COMPONENT_COLOR0,
>> - DDP_COMPONENT_CCORR,
>> - DDP_COMPONENT_AAL0,
>> - DDP_COMPONENT_GAMMA,
>> - DDP_COMPONENT_DITHER0,
>> - DDP_COMPONENT_DSI0,
>> -};
>> -
>> -static const unsigned int mt8365_mtk_ddp_ext[] = {
>> - DDP_COMPONENT_RDMA1,
>> - DDP_COMPONENT_DPI0,
>> -};
>> -
>> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>> .main_path = mt2701_mtk_ddp_main,
>> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
>> @@ -334,10 +318,6 @@ static const struct mtk_mmsys_driver_data
>> mt8195_vdosys1_driver_data = {
>> };
>>
>> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
>> - .main_path = mt8365_mtk_ddp_main,
>> - .main_len = ARRAY_SIZE(mt8365_mtk_ddp_main),
>> - .ext_path = mt8365_mtk_ddp_ext,
>> - .ext_len = ARRAY_SIZE(mt8365_mtk_ddp_ext),
>> .mmsys_dev_num = 1,
>> };
>>
>>
>>
>> --
>> Regards,
>> Alexandre
>
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^ permalink raw reply [relevance 6%]
* Re: [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement
2024-05-14 8:25 0% ` Ard Biesheuvel
2024-05-14 9:22 0% ` Russell King (Oracle)
@ 2024-05-14 11:28 0% ` Geert Uytterhoeven
2024-05-14 16:06 0% ` Geert Uytterhoeven
1 sibling, 1 reply; 200+ results
From: Geert Uytterhoeven @ 2024-05-14 11:28 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Linus Walleij, Russell King, Arnd Bergmann, Stefan Wahren,
Kees Cook, linux-arm-kernel, Catalin Marinas
Hi Ard,
On Tue, May 14, 2024 at 10:25 AM Ard Biesheuvel <ardb@kernel.org> wrote:
> On Tue, 14 May 2024 at 10:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, May 14, 2024 at 9:59 AM Ard Biesheuvel <ardb@kernel.org> wrote:
> > > On Tue, 14 May 2024 at 09:46, Linus Walleij <linus.walleij@linaro.org> wrote:
> > > > On Tue, May 14, 2024 at 8:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > >
> > > > > I sent you a small initramfs by PM.
> > > >
> > > > Booted this just fine on Vexpress QEMU:
> > > >
> > > > Run /init as init process
> > > > sysctl: error: 'kernel.hotplug' is an unknown key
> > > >
> > > >
> > > > boot (Linux 6.9.0-rc1+, BusyBox v1.16.0.git, kexec-tools 2.0.1-git)
> > > > / # mount -t debugfs none /sys/kernel/debug
> > > > / # echo "ACCESS_USERSPACE" | cat >/sys/kernel/debug/provoke-crash/DIRECT
> > > > lkdtm: Performing direct entry ACCESS_USERSPACE
> > > > lkdtm: attempting bad read at 76fea000
> > > > 8<--- cut here ---
> > > > Unable to handle kernel paging request at virtual address 76fea000 when read
> > > > [76fea000] *pgd=82c93003, *pmd=82c94003, *pte=a00000811e2f5f
> > > > Internal error: Oops: 206 [#1] SMP ARM
> > > > CPU: 1 PID: 86 Comm: cat Not tainted 6.9.0-rc1+ #46
> > > > Hardware name: ARM-Versatile Express
> > > > PC is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> > > > LR is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> > > >
> > > > I'm starting to think it is something about different LPAE implementations here.
> > >
> > > I have built multi_v7_defconfig with the following enabled
> > >
> > > CONFIG_ARM_LPAE=y
> > > CONFIG_CPU_TTBR0_PAN=y
> > > CONFIG_LKDTM=y
> > >
> > > and the resulting kernel boots happily as a 32-bit VM running under a
> > > Rpi4 KVM host.
> > >
> > > Could someone post an actual .config that reproduces this? Rpi4 is
> > > A72, which both works and doesn't work in Florian's testing, so I'd be
> > > highly surprised if this is not a config issue.
> >
> > shmobile_defconfig with CONFIG_LPAE=y added failed for me before.
> >
> > Building multi_v7_defconfig with the above enabled...
And that works, while shmobile_defconfig with the above does not!
So it is config-related.
FTR, plain multi_v7_defconfig also works.
> What are you passing as the command line?
ignore_loglevel ip=dhcp root=/dev/nfs rw nfsroot=<ip>:<path>/debian-armhf,tcp,v3
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement
2024-05-14 8:25 0% ` Ard Biesheuvel
@ 2024-05-14 9:22 0% ` Russell King (Oracle)
2024-05-14 11:28 0% ` Geert Uytterhoeven
1 sibling, 0 replies; 200+ results
From: Russell King (Oracle) @ 2024-05-14 9:22 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Geert Uytterhoeven, Linus Walleij, Arnd Bergmann, Stefan Wahren,
Kees Cook, linux-arm-kernel, Catalin Marinas
On Tue, May 14, 2024 at 10:25:28AM +0200, Ard Biesheuvel wrote:
> On Tue, 14 May 2024 at 10:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> >
> > Hi Ard,
> >
> > On Tue, May 14, 2024 at 9:59 AM Ard Biesheuvel <ardb@kernel.org> wrote:
> > > On Tue, 14 May 2024 at 09:46, Linus Walleij <linus.walleij@linaro.org> wrote:
> > > > On Tue, May 14, 2024 at 8:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > >
> > > > > I sent you a small initramfs by PM.
> > > >
> > > > Booted this just fine on Vexpress QEMU:
> > > >
> > > > Run /init as init process
> > > > sysctl: error: 'kernel.hotplug' is an unknown key
> > > >
> > > >
> > > > boot (Linux 6.9.0-rc1+, BusyBox v1.16.0.git, kexec-tools 2.0.1-git)
> > > > / # mount -t debugfs none /sys/kernel/debug
> > > > / # echo "ACCESS_USERSPACE" | cat >/sys/kernel/debug/provoke-crash/DIRECT
> > > > lkdtm: Performing direct entry ACCESS_USERSPACE
> > > > lkdtm: attempting bad read at 76fea000
> > > > 8<--- cut here ---
> > > > Unable to handle kernel paging request at virtual address 76fea000 when read
> > > > [76fea000] *pgd=82c93003, *pmd=82c94003, *pte=a00000811e2f5f
> > > > Internal error: Oops: 206 [#1] SMP ARM
> > > > CPU: 1 PID: 86 Comm: cat Not tainted 6.9.0-rc1+ #46
> > > > Hardware name: ARM-Versatile Express
> > > > PC is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> > > > LR is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> > > >
> > > > I'm starting to think it is something about different LPAE implementations here.
> > > >
> > >
> > > I have built multi_v7_defconfig with the following enabled
> > >
> > > CONFIG_ARM_LPAE=y
> > > CONFIG_CPU_TTBR0_PAN=y
> > > CONFIG_LKDTM=y
> > >
> > > and the resulting kernel boots happily as a 32-bit VM running under a
> > > Rpi4 KVM host.
> > >
> > > Could someone post an actual .config that reproduces this? Rpi4 is
> > > A72, which both works and doesn't work in Florian's testing, so I'd be
> > > highly surprised if this is not a config issue.
> >
> > shmobile_defconfig with CONFIG_LPAE=y added failed for me before.
> >
> > Building multi_v7_defconfig with the above enabled...
> >
>
> What are you passing as the command line?
A more relevant question at this point in time - what do people want me
to do with these patches given that we're now in the merge window?
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement
2024-05-14 8:04 0% ` Geert Uytterhoeven
@ 2024-05-14 8:25 0% ` Ard Biesheuvel
2024-05-14 9:22 0% ` Russell King (Oracle)
2024-05-14 11:28 0% ` Geert Uytterhoeven
0 siblings, 2 replies; 200+ results
From: Ard Biesheuvel @ 2024-05-14 8:25 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linus Walleij, Russell King, Arnd Bergmann, Stefan Wahren,
Kees Cook, linux-arm-kernel, Catalin Marinas
On Tue, 14 May 2024 at 10:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Ard,
>
> On Tue, May 14, 2024 at 9:59 AM Ard Biesheuvel <ardb@kernel.org> wrote:
> > On Tue, 14 May 2024 at 09:46, Linus Walleij <linus.walleij@linaro.org> wrote:
> > > On Tue, May 14, 2024 at 8:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > >
> > > > I sent you a small initramfs by PM.
> > >
> > > Booted this just fine on Vexpress QEMU:
> > >
> > > Run /init as init process
> > > sysctl: error: 'kernel.hotplug' is an unknown key
> > >
> > >
> > > boot (Linux 6.9.0-rc1+, BusyBox v1.16.0.git, kexec-tools 2.0.1-git)
> > > / # mount -t debugfs none /sys/kernel/debug
> > > / # echo "ACCESS_USERSPACE" | cat >/sys/kernel/debug/provoke-crash/DIRECT
> > > lkdtm: Performing direct entry ACCESS_USERSPACE
> > > lkdtm: attempting bad read at 76fea000
> > > 8<--- cut here ---
> > > Unable to handle kernel paging request at virtual address 76fea000 when read
> > > [76fea000] *pgd=82c93003, *pmd=82c94003, *pte=a00000811e2f5f
> > > Internal error: Oops: 206 [#1] SMP ARM
> > > CPU: 1 PID: 86 Comm: cat Not tainted 6.9.0-rc1+ #46
> > > Hardware name: ARM-Versatile Express
> > > PC is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> > > LR is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> > >
> > > I'm starting to think it is something about different LPAE implementations here.
> > >
> >
> > I have built multi_v7_defconfig with the following enabled
> >
> > CONFIG_ARM_LPAE=y
> > CONFIG_CPU_TTBR0_PAN=y
> > CONFIG_LKDTM=y
> >
> > and the resulting kernel boots happily as a 32-bit VM running under a
> > Rpi4 KVM host.
> >
> > Could someone post an actual .config that reproduces this? Rpi4 is
> > A72, which both works and doesn't work in Florian's testing, so I'd be
> > highly surprised if this is not a config issue.
>
> shmobile_defconfig with CONFIG_LPAE=y added failed for me before.
>
> Building multi_v7_defconfig with the above enabled...
>
What are you passing as the command line?
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement
2024-05-14 7:59 0% ` Ard Biesheuvel
@ 2024-05-14 8:04 0% ` Geert Uytterhoeven
2024-05-14 8:25 0% ` Ard Biesheuvel
0 siblings, 1 reply; 200+ results
From: Geert Uytterhoeven @ 2024-05-14 8:04 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Linus Walleij, Russell King, Arnd Bergmann, Stefan Wahren,
Kees Cook, linux-arm-kernel, Catalin Marinas
Hi Ard,
On Tue, May 14, 2024 at 9:59 AM Ard Biesheuvel <ardb@kernel.org> wrote:
> On Tue, 14 May 2024 at 09:46, Linus Walleij <linus.walleij@linaro.org> wrote:
> > On Tue, May 14, 2024 at 8:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> >
> > > I sent you a small initramfs by PM.
> >
> > Booted this just fine on Vexpress QEMU:
> >
> > Run /init as init process
> > sysctl: error: 'kernel.hotplug' is an unknown key
> >
> >
> > boot (Linux 6.9.0-rc1+, BusyBox v1.16.0.git, kexec-tools 2.0.1-git)
> > / # mount -t debugfs none /sys/kernel/debug
> > / # echo "ACCESS_USERSPACE" | cat >/sys/kernel/debug/provoke-crash/DIRECT
> > lkdtm: Performing direct entry ACCESS_USERSPACE
> > lkdtm: attempting bad read at 76fea000
> > 8<--- cut here ---
> > Unable to handle kernel paging request at virtual address 76fea000 when read
> > [76fea000] *pgd=82c93003, *pmd=82c94003, *pte=a00000811e2f5f
> > Internal error: Oops: 206 [#1] SMP ARM
> > CPU: 1 PID: 86 Comm: cat Not tainted 6.9.0-rc1+ #46
> > Hardware name: ARM-Versatile Express
> > PC is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> > LR is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> >
> > I'm starting to think it is something about different LPAE implementations here.
> >
>
> I have built multi_v7_defconfig with the following enabled
>
> CONFIG_ARM_LPAE=y
> CONFIG_CPU_TTBR0_PAN=y
> CONFIG_LKDTM=y
>
> and the resulting kernel boots happily as a 32-bit VM running under a
> Rpi4 KVM host.
>
> Could someone post an actual .config that reproduces this? Rpi4 is
> A72, which both works and doesn't work in Florian's testing, so I'd be
> highly surprised if this is not a config issue.
shmobile_defconfig with CONFIG_LPAE=y added failed for me before.
Building multi_v7_defconfig with the above enabled...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement
2024-05-14 7:46 6% ` Linus Walleij
@ 2024-05-14 7:59 0% ` Ard Biesheuvel
2024-05-14 8:04 0% ` Geert Uytterhoeven
0 siblings, 1 reply; 200+ results
From: Ard Biesheuvel @ 2024-05-14 7:59 UTC (permalink / raw)
To: Linus Walleij
Cc: Geert Uytterhoeven, Russell King, Arnd Bergmann, Stefan Wahren,
Kees Cook, linux-arm-kernel, Catalin Marinas
On Tue, 14 May 2024 at 09:46, Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Tue, May 14, 2024 at 8:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> > I sent you a small initramfs by PM.
>
> Booted this just fine on Vexpress QEMU:
>
> Run /init as init process
> sysctl: error: 'kernel.hotplug' is an unknown key
>
>
> boot (Linux 6.9.0-rc1+, BusyBox v1.16.0.git, kexec-tools 2.0.1-git)
> / # mount -t debugfs none /sys/kernel/debug
> / # echo "ACCESS_USERSPACE" | cat >/sys/kernel/debug/provoke-crash/DIRECT
> lkdtm: Performing direct entry ACCESS_USERSPACE
> lkdtm: attempting bad read at 76fea000
> 8<--- cut here ---
> Unable to handle kernel paging request at virtual address 76fea000 when read
> [76fea000] *pgd=82c93003, *pmd=82c94003, *pte=a00000811e2f5f
> Internal error: Oops: 206 [#1] SMP ARM
> CPU: 1 PID: 86 Comm: cat Not tainted 6.9.0-rc1+ #46
> Hardware name: ARM-Versatile Express
> PC is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
> LR is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
>
> I'm starting to think it is something about different LPAE implementations here.
>
I have built multi_v7_defconfig with the following enabled
CONFIG_ARM_LPAE=y
CONFIG_CPU_TTBR0_PAN=y
CONFIG_LKDTM=y
and the resulting kernel boots happily as a 32-bit VM running under a
Rpi4 KVM host.
Could someone post an actual .config that reproduces this? Rpi4 is
A72, which both works and doesn't work in Florian's testing, so I'd be
highly surprised if this is not a config issue.
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement
@ 2024-05-14 7:46 6% ` Linus Walleij
2024-05-14 7:59 0% ` Ard Biesheuvel
0 siblings, 1 reply; 200+ results
From: Linus Walleij @ 2024-05-14 7:46 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Russell King, Ard Biesheuvel, Arnd Bergmann, Stefan Wahren,
Kees Cook, linux-arm-kernel, Catalin Marinas
On Tue, May 14, 2024 at 8:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> I sent you a small initramfs by PM.
Booted this just fine on Vexpress QEMU:
Run /init as init process
sysctl: error: 'kernel.hotplug' is an unknown key
boot (Linux 6.9.0-rc1+, BusyBox v1.16.0.git, kexec-tools 2.0.1-git)
/ # mount -t debugfs none /sys/kernel/debug
/ # echo "ACCESS_USERSPACE" | cat >/sys/kernel/debug/provoke-crash/DIRECT
lkdtm: Performing direct entry ACCESS_USERSPACE
lkdtm: attempting bad read at 76fea000
8<--- cut here ---
Unable to handle kernel paging request at virtual address 76fea000 when read
[76fea000] *pgd=82c93003, *pmd=82c94003, *pte=a00000811e2f5f
Internal error: Oops: 206 [#1] SMP ARM
CPU: 1 PID: 86 Comm: cat Not tainted 6.9.0-rc1+ #46
Hardware name: ARM-Versatile Express
PC is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
LR is at lkdtm_ACCESS_USERSPACE+0xc0/0x138
I'm starting to think it is something about different LPAE implementations here.
Yours,
Linus Walleij
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^ permalink raw reply [relevance 6%]
* [PATCH] iommu/arm-smmu: Don't disable next-page prefetcher on devices it works on
@ 2024-05-13 23:13 5% Douglas Anderson
2024-05-14 17:14 0% ` Robin Murphy
2024-05-17 16:37 0% ` Will Deacon
0 siblings, 2 replies; 200+ results
From: Douglas Anderson @ 2024-05-13 23:13 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel
Cc: Stephen Boyd, Douglas Anderson, Chen Lin, iommu,
linux-arm-kernel, linux-kernel
On sc7180 trogdor devices we get a scary warning at bootup:
arm-smmu 15000000.iommu:
Failed to disable prefetcher [errata #841119 and #826419], check ACR.CACHE_LOCK
We spent some time trying to figure out how we were going to fix these
errata and whether we needed to do a firmware update. Upon closer
inspection, however, we realized that the errata don't apply to us.
Specifically, the errata document says that for these errata:
* Found in: r0p0
* Fixed in: r2p2
...and trogdor devices appear to be running r2p4. That means that they
are unaffected despite the scary warning.
The issue is that the kernel unconditionally tries to disable the
prefetcher even on unaffected devices and then warns when it's unable
to.
Let's change the kernel to only disable the prefetcher on affected
devices, which will get rid of the scary warning on devices that are
unaffected. As per the comment the prefetcher is
"not-particularly-beneficial" but it shouldn't hurt to leave it on for
devices where it doesn't cause problems.
Fixes: f87f6e5b4539 ("iommu/arm-smmu: Warn once when the perfetcher errata patch fails to apply")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
index 9dc772f2cbb2..d9b38b0db0d4 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
@@ -109,7 +109,7 @@ static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smm
int arm_mmu500_reset(struct arm_smmu_device *smmu)
{
- u32 reg, major;
+ u32 reg, major, minor;
int i;
/*
* On MMU-500 r2p0 onwards we need to clear ACR.CACHE_LOCK before
@@ -118,6 +118,7 @@ int arm_mmu500_reset(struct arm_smmu_device *smmu)
*/
reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID7);
major = FIELD_GET(ARM_SMMU_ID7_MAJOR, reg);
+ minor = FIELD_GET(ARM_SMMU_ID7_MINOR, reg);
reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sACR);
if (major >= 2)
reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
@@ -131,14 +132,18 @@ int arm_mmu500_reset(struct arm_smmu_device *smmu)
/*
* Disable MMU-500's not-particularly-beneficial next-page
* prefetcher for the sake of errata #841119 and #826419.
+ * These errata only affect r0p0 through r2p1 (fixed in r2p2).
*/
- for (i = 0; i < smmu->num_context_banks; ++i) {
- reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
- reg &= ~ARM_MMU500_ACTLR_CPRE;
- arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
- reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
- if (reg & ARM_MMU500_ACTLR_CPRE)
- dev_warn_once(smmu->dev, "Failed to disable prefetcher [errata #841119 and #826419], check ACR.CACHE_LOCK\n");
+ if (major < 2 || (major == 2 && minor < 2)) {
+ for (i = 0; i < smmu->num_context_banks; ++i) {
+ reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
+ reg &= ~ARM_MMU500_ACTLR_CPRE;
+ arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
+ reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
+ if (reg & ARM_MMU500_ACTLR_CPRE)
+ dev_warn_once(smmu->dev,
+ "Failed to disable prefetcher [errata #841119 and #826419], check ACR.CACHE_LOCK\n");
+ }
}
return 0;
--
2.45.0.rc1.225.g2a3ae87e7f-goog
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^ permalink raw reply related [relevance 5%]
* Re: [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave
2024-05-10 13:27 2% ` [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave Pankaj Gupta
2024-05-10 16:41 0% ` Frank Li
@ 2024-05-13 10:54 0% ` Marc Kleine-Budde
2024-05-16 4:47 0% ` Amit Singh Tomar
2 siblings, 0 replies; 200+ results
From: Marc Kleine-Budde @ 2024-05-13 10:54 UTC (permalink / raw)
To: Pankaj Gupta
Cc: Jonathan Corbet, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
linux-doc, linux-kernel, devicetree, imx, linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 72382 bytes --]
On 10.05.2024 18:57:30, Pankaj Gupta wrote:
> NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE),
> are embedded in the SoC to support the features like HSM, SHE & V2X,
> using message based communication interface.
>
> The secure enclave FW communicates on a dedicated messaging unit(MU)
> based interface(s) with application core, where kernel is running.
> It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
>
> This patch adds the driver for communication interface to secure-enclave,
> for exchanging messages with NXP secure enclave HW IP(s) like EdgeLock Enclave,
> both from:
> - User-Space Applications via character driver.
> - Kernel-space, used by kernel management layers like DM-Crypt.
>
> ABI documentation for the NXP secure-enclave driver.
Can you add the user space misc dev in a different patch?
>
> User-space library using this driver:
> - i.MX Secure Enclave library:
> -- URL: https://github.com/nxp-imx/imx-secure-enclave.git,
> - i.MX Secure Middle-Ware:
> -- URL: https://github.com/nxp-imx/imx-smw.git
>
> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> ---
> Documentation/ABI/testing/se-cdev | 42 ++
> drivers/firmware/imx/Kconfig | 12 +
> drivers/firmware/imx/Makefile | 2 +
> drivers/firmware/imx/ele_base_msg.c | 287 ++++++++
> drivers/firmware/imx/ele_base_msg.h | 70 ++
> drivers/firmware/imx/ele_common.c | 341 +++++++++
> drivers/firmware/imx/ele_common.h | 43 ++
> drivers/firmware/imx/se_ctrl.c | 1339 +++++++++++++++++++++++++++++++++++
> drivers/firmware/imx/se_ctrl.h | 151 ++++
> include/linux/firmware/imx/se_api.h | 14 +
> include/uapi/linux/se_ioctl.h | 88 +++
> 11 files changed, 2389 insertions(+)
>
> diff --git a/Documentation/ABI/testing/se-cdev b/Documentation/ABI/testing/se-cdev
> new file mode 100644
> index 000000000000..699525af6b86
> --- /dev/null
> +++ b/Documentation/ABI/testing/se-cdev
> @@ -0,0 +1,42 @@
> +What: /dev/<se>_mu[0-9]+_ch[0-9]+
> +Date: May 2024
> +KernelVersion: 6.8
> +Contact: linux-imx@nxp.com, pankaj.gupta@nxp.com
> +Description:
> + NXP offers multiple hardware IP(s) for secure-enclaves like EdgeLock-
> + Enclave(ELE), SECO. The character device file-descriptors
> + /dev/<se>_mu*_ch* are the interface between user-space NXP's secure-
> + enclave shared-library and the kernel driver.
> +
> + The ioctl(2)-based ABI is defined and documented in
> + [include]<linux/firmware/imx/ele_mu_ioctl.h>
> + ioctl(s) are used primarily for:
> + - shared memory management
> + - allocation of I/O buffers
> + - get mu info
> + - setting a dev-ctx as receiver that is slave to fw
> + - get SoC info
> +
> + The following file operations are supported:
> +
> + open(2)
> + Currently the only useful flags are O_RDWR.
> +
> + read(2)
> + Every read() from the opened character device context is waiting on
> + wakeup_intruptible, that gets set by the registered mailbox callback
> + function; indicating a message received from the firmware on message-
> + unit.
> +
> + write(2)
> + Every write() to the opened character device context needs to acquire
> + mailbox_lock, before sending message on to the message unit.
> +
> + close(2)
> + Stops and free up the I/O contexts that was associated
> + with the file descriptor.
> +
> +Users: https://github.com/nxp-imx/imx-secure-enclave.git,
> + https://github.com/nxp-imx/imx-smw.git
> + crypto/skcipher,
> + drivers/nvmem/imx-ocotp-ele.c
> diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
> index 183613f82a11..56bdca9bd917 100644
> --- a/drivers/firmware/imx/Kconfig
> +++ b/drivers/firmware/imx/Kconfig
> @@ -22,3 +22,15 @@ config IMX_SCU
>
> This driver manages the IPC interface between host CPU and the
> SCU firmware running on M4.
> +
> +config IMX_SEC_ENCLAVE
> + tristate "i.MX Embedded Secure Enclave - EdgeLock Enclave Firmware driver."
> + depends on IMX_MBOX && ARCH_MXC && ARM64
> + default m if ARCH_MXC
> +
> + help
> + It is possible to use APIs exposed by the iMX Secure Enclave HW IP called:
> + - EdgeLock Enclave Firmware (for i.MX8ULP, i.MX93),
> + like base, HSM, V2X & SHE using the SAB protocol via the shared Messaging
> + Unit. This driver exposes these interfaces via a set of file descriptors
> + allowing to configure shared memory, send and receive messages.
> diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile
> index 8f9f04a513a8..aa9033e0e9e3 100644
> --- a/drivers/firmware/imx/Makefile
> +++ b/drivers/firmware/imx/Makefile
> @@ -1,3 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-$(CONFIG_IMX_DSP) += imx-dsp.o
> obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o
> +sec_enclave-objs = se_ctrl.o ele_common.o ele_base_msg.o
> +obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
> diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele_base_msg.c
> new file mode 100644
> index 000000000000..0463f26d93c7
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_base_msg.c
> @@ -0,0 +1,287 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <linux/types.h>
> +#include <linux/completion.h>
> +#include <linux/dma-mapping.h>
> +
> +#include "ele_base_msg.h"
> +#include "ele_common.h"
> +
> +int ele_get_info(struct device *dev, struct soc_info *s_info)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_api_msg *rx_msg __free(kfree);
> + phys_addr_t get_info_addr;
> + u32 *get_info_data;
> + u32 status;
> + int ret;
> +
> + if (!priv || !s_info)
> + goto exit;
You should code properly, so that this doesn't happen, your cleanup is
broken, it will work on uninitialized data, as Sascha already mentioned.
> +
> + memset(s_info, 0x0, sizeof(*s_info));
> +
> + if (priv->mem_pool_name)
> + get_info_data = get_phy_buf_mem_pool(dev,
> + priv->mem_pool_name,
> + &get_info_addr,
> + ELE_GET_INFO_BUFF_SZ);
> + else
> + get_info_data = dmam_alloc_coherent(dev,
> + ELE_GET_INFO_BUFF_SZ,
> + &get_info_addr,
> + GFP_KERNEL);
It's better style to move the init of the dma memory into the probe
function.
> + if (!get_info_data) {
> + ret = -ENOMEM;
> + dev_err(dev,
> + "%s: Failed to allocate get_info_addr.\n",
> + __func__);
> + goto exit;
> + }
> +
> + tx_msg = kzalloc(ELE_GET_INFO_REQ_MSG_SZ << 2, GFP_KERNEL);
^^^^^^^^^^^^^^^^^^^^^^^
Is ELE_GET_INFO_REQ_MSG_SZ is in multiple of u32?
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + rx_msg = kzalloc(ELE_GET_INFO_RSP_MSG_SZ << 2, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_GET_INFO_REQ,
> + ELE_GET_INFO_REQ_MSG_SZ,
Here you feed in ELE_GET_INFO_REQ_MSG_SZ and in plat_fill_cmd_msg_hdr()
you use "len >> 2". This look quite strange to me. Better use length in
bytes everywhere.
> + true);
> + if (ret)
> + goto exit;
> +
> + tx_msg->data[0] = upper_32_bits(get_info_addr);
> + tx_msg->data[1] = lower_32_bits(get_info_addr);
> + tx_msg->data[2] = ELE_GET_INFO_READ_SZ;
Can you use a proper struct for this. Sascha has already commented on
the null pointer here.
> + priv->rx_msg = rx_msg;
> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
This API looks strange, why put the tx_msg as a parameter the rx_msg
into the private struct?
> + if (ret < 0)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
^^
single space
> + priv->rx_msg->header,
> + ELE_GET_INFO_REQ,
> + ELE_GET_INFO_RSP_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
use FIELD_GET()
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_GET_INFO_REQ, status);
> + ret = -1;
> + }
> +
> + s_info->imem_state = (get_info_data[ELE_IMEM_STATE_WORD]
> + & ELE_IMEM_STATE_MASK) >> 16;
can you use a struct for get_info_data and use FIELD_GET() (if needed)
> + s_info->major_ver = (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> + & SOC_VER_MASK) >> 24;
> + s_info->minor_ver = ((get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> + & SOC_VER_MASK) >> 16) & 0xFF;
> + s_info->soc_rev = (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> + & SOC_VER_MASK) >> 16;
> + s_info->soc_id = get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> + & SOC_ID_MASK;
> + s_info->serial_num
> + = (u64)get_info_data[GET_INFO_SL_NUM_MSB_WORD_OFF] << 32
> + | get_info_data[GET_INFO_SL_NUM_LSB_WORD_OFF];
The "|" goes to the end of the previous line.
> +exit:
> + if (get_info_addr) {
> + if (priv->mem_pool_name)
> + free_phybuf_mem_pool(dev, priv->mem_pool_name,
> + get_info_data, ELE_GET_INFO_BUFF_SZ);
> + else
> + dmam_free_coherent(dev,
> + ELE_GET_INFO_BUFF_SZ,
> + get_info_data,
> + get_info_addr);
> + }
> +
> + return ret;
> +}
> +
> +int ele_ping(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_api_msg *rx_msg __free(kfree);
> + u32 status;
> + int ret;
> +
> + tx_msg = kzalloc(ELE_PING_REQ_SZ << 2, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + rx_msg = kzalloc(ELE_PING_RSP_SZ << 2, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_PING_REQ, ELE_PING_REQ_SZ,
> + true);
> + if (ret) {
> + dev_err(dev, "Error: plat_fill_cmd_msg_hdr failed.\n");
> + goto exit;
> + }
> +
> + priv->rx_msg = rx_msg;
> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> + if (ret)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + priv->rx_msg->header,
> + ELE_PING_REQ,
> + ELE_PING_RSP_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_PING_REQ, status);
> + ret = -1;
> + }
> +exit:
> + return ret;
> +}
> +
> +int ele_service_swap(struct device *dev,
> + phys_addr_t addr,
> + u32 addr_size, u16 flag)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_api_msg *rx_msg __free(kfree);
> + u32 status;
> + int ret;
> +
> + tx_msg = kzalloc(ELE_SERVICE_SWAP_REQ_MSG_SZ << 2, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + rx_msg = kzalloc(ELE_SERVICE_SWAP_RSP_MSG_SZ << 2, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_SERVICE_SWAP_REQ,
> + ELE_SERVICE_SWAP_REQ_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + tx_msg->data[0] = flag;
> + tx_msg->data[1] = addr_size;
> + tx_msg->data[2] = ELE_NONE_VAL;
> + tx_msg->data[3] = lower_32_bits(addr);
> + tx_msg->data[4] = plat_add_msg_crc((uint32_t *)&tx_msg[0],
> + ELE_SERVICE_SWAP_REQ_MSG_SZ);
> + priv->rx_msg = rx_msg;
> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> + if (ret < 0)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + priv->rx_msg->header,
> + ELE_SERVICE_SWAP_REQ,
> + ELE_SERVICE_SWAP_RSP_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_SERVICE_SWAP_REQ, status);
> + ret = -1;
> + } else {
> + if (flag == ELE_IMEM_EXPORT)
> + ret = priv->rx_msg->data[1];
> + else
> + ret = 0;
> + }
> +exit:
> +
> + return ret;
> +}
> +
> +int ele_fw_authenticate(struct device *dev, phys_addr_t addr)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_api_msg *rx_msg __free(kfree);
> + u32 status;
> + int ret;
> +
> + tx_msg = kzalloc(ELE_FW_AUTH_REQ_SZ << 2, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + rx_msg = kzalloc(ELE_FW_AUTH_RSP_MSG_SZ << 2, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_FW_AUTH_REQ,
> + ELE_FW_AUTH_REQ_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + tx_msg->data[0] = addr;
> + tx_msg->data[1] = 0x0;
> + tx_msg->data[2] = addr;
> +
> + priv->rx_msg = rx_msg;
> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> + if (ret < 0)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + priv->rx_msg->header,
> + ELE_FW_AUTH_REQ,
> + ELE_FW_AUTH_RSP_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_FW_AUTH_REQ, status);
> + ret = -1;
> + }
> +exit:
> +
> + return ret;
> +}
> diff --git a/drivers/firmware/imx/ele_base_msg.h b/drivers/firmware/imx/ele_base_msg.h
> new file mode 100644
> index 000000000000..3b3d2bf04a84
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_base_msg.h
> @@ -0,0 +1,70 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + *
> + * Header file for the EdgeLock Enclave Base API(s).
> + */
> +
> +#ifndef ELE_BASE_MSG_H
> +#define ELE_BASE_MSG_H
> +
> +#include <linux/device.h>
> +#include <linux/types.h>
> +
> +#define WORD_SZ 4
> +#define ELE_NONE_VAL 0x0
> +
> +#define ELE_SUCCESS_IND 0xD6
> +
> +#define ELE_GET_INFO_REQ 0xDA
> +#define ELE_GET_INFO_REQ_MSG_SZ 0x10
> +#define ELE_GET_INFO_RSP_MSG_SZ 0x08
> +
> +#define ELE_GET_INFO_BUFF_SZ 0x100
> +#define ELE_GET_INFO_READ_SZ 0xA0
> +
> +#define DEFAULT_IMX_SOC_VER 0xA0
> +#define SOC_VER_MASK 0xFFFF0000
> +#define SOC_ID_MASK 0x0000FFFF
> +struct soc_info {
> + u32 imem_state;
> + u8 major_ver;
> + u8 minor_ver;
> + u16 soc_id;
> + u16 soc_rev;
> + u64 serial_num;
> +};
> +
> +#define GET_INFO_SOC_INFO_WORD_OFFSET 1
> +#define GET_INFO_UUID_WORD_OFFSET 3
> +#define GET_INFO_SL_NUM_MSB_WORD_OFF \
> + (GET_INFO_UUID_WORD_OFFSET + 3)
> +#define GET_INFO_SL_NUM_LSB_WORD_OFF \
> + (GET_INFO_UUID_WORD_OFFSET + 0)
> +
> +#define ELE_PING_REQ 0x01
> +#define ELE_PING_REQ_SZ 0x04
> +#define ELE_PING_RSP_SZ 0x08
> +
> +#define ELE_SERVICE_SWAP_REQ 0xDF
> +#define ELE_SERVICE_SWAP_REQ_MSG_SZ 0x18
> +#define ELE_SERVICE_SWAP_RSP_MSG_SZ 0x0C
> +#define ELE_IMEM_SIZE 0x10000
> +#define ELE_IMEM_STATE_OK 0xCA
> +#define ELE_IMEM_STATE_BAD 0xFE
> +#define ELE_IMEM_STATE_WORD 0x27
> +#define ELE_IMEM_STATE_MASK 0x00ff0000
> +#define ELE_IMEM_EXPORT 0x1
> +#define ELE_IMEM_IMPORT 0x2
> +
> +#define ELE_FW_AUTH_REQ 0x02
> +#define ELE_FW_AUTH_REQ_SZ 0x10
> +#define ELE_FW_AUTH_RSP_MSG_SZ 0x08
> +
> +int ele_get_info(struct device *dev, struct soc_info *s_info);
> +int ele_ping(struct device *dev);
> +int ele_service_swap(struct device *dev,
> + phys_addr_t addr,
> + u32 addr_size, u16 flag);
> +int ele_fw_authenticate(struct device *dev, phys_addr_t addr);
> +#endif
> diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_common.c
> new file mode 100644
> index 000000000000..dcf7f9034653
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_common.c
> @@ -0,0 +1,341 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include "ele_base_msg.h"
> +#include "ele_common.h"
> +
> +u32 plat_add_msg_crc(u32 *msg, u32 msg_len)
> +{
> + u32 nb_words = msg_len / (u32)sizeof(u32);
> + u32 crc = 0;
> + u32 i;
> +
> + for (i = 0; i < nb_words - 1; i++)
> + crc ^= *(msg + i);
> +
> + return crc;
> +}
> +
> +int imx_ele_msg_rcv(struct se_if_priv *priv)
> +{
> + u32 wait;
> + int err;
> +
> + wait = msecs_to_jiffies(1000);
> + if (!wait_for_completion_timeout(&priv->done, wait)) {
> + dev_err(priv->dev,
> + "Error: wait_for_completion timed out.\n");
> + err = -ETIMEDOUT;
> + }
> +
> + mutex_unlock(&priv->se_if_cmd_lock);
> + priv->no_dev_ctx_used = false;
> +
> + return err;
> +}
> +
> +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg)
> +{
> + bool is_cmd_lock_tobe_taken = false;
> + int err;
> +
> + if (!priv->waiting_rsp_dev || priv->no_dev_ctx_used) {
> + is_cmd_lock_tobe_taken = true;
> + mutex_lock(&priv->se_if_cmd_lock);
> + }
> + scoped_guard(mutex, &priv->se_if_lock);
> +
> + err = mbox_send_message(priv->tx_chan, mssg);
> + if (err < 0) {
> + dev_err(priv->dev, "Error: mbox_send_message failure.\n");
> + if (is_cmd_lock_tobe_taken)
> + mutex_unlock(&priv->se_if_cmd_lock);
Only dropping the lock in case of failure doesn't look right to me. It
seems you should better move the lock to the callers of this function.
> + return err;
> + }
> + err = 0;
> +
> + return err;
> +}
> +
> +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg)
> +{
> + int err;
> +
> + priv->no_dev_ctx_used = true;
> + err = imx_ele_msg_send(priv, mssg);
> + if (err)
> + goto exit;
> +
> + err = imx_ele_msg_rcv(priv);
> +
> +exit:
> + return err;
> +}
> +
> +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *dev_ctx)
> +{
> + struct se_msg_hdr header = {0};
> + int err;
> +
> + err = wait_event_interruptible(dev_ctx->wq, dev_ctx->pending_hdr != 0);
> + if (err)
> + dev_err(dev_ctx->dev,
> + "%s: Err[0x%x]:Interrupted by signal.\n",
> + dev_ctx->miscdev.name, err);
> +
> + header = *((struct se_msg_hdr *) (&dev_ctx->temp_resp[0]));
> +
> + if (header.tag == dev_ctx->priv->rsp_tag)
> + mutex_unlock(&dev_ctx->priv->se_if_cmd_lock);
> +
> + return err;
> +}
> +
> +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
> + void *tx_msg, int tx_msg_sz)
> +{
> + struct se_if_priv *priv = dev_ctx->priv;
> + struct se_msg_hdr header = {0};
> + int err;
> +
> + header = *((struct se_msg_hdr *) tx_msg);
> +
> + /*
> + * Check that the size passed as argument matches the size
> + * carried in the message.
> + */
> + err = header.size << 2;
> +
> + if (err != tx_msg_sz) {
> + err = -EINVAL;
> + dev_err(priv->dev,
> + "%s: User buffer too small\n",
> + dev_ctx->miscdev.name);
> + goto exit;
> + }
> + /* Check the message is valid according to tags */
> + if (header.tag == priv->cmd_tag)
> + priv->waiting_rsp_dev = dev_ctx;
> + else if (header.tag == priv->rsp_tag) {
> + /* Check the device context can send the command */
> + if (dev_ctx != priv->cmd_receiver_dev) {
> + dev_err(priv->dev,
> + "%s: Channel not configured to send resp to FW.",
> + dev_ctx->miscdev.name);
> + err = -EPERM;
> + goto exit;
> + }
> + } else {
> + dev_err(priv->dev,
> + "%s: The message does not have a valid TAG\n",
> + dev_ctx->miscdev.name);
> + err = -EINVAL;
> + goto exit;
> + }
> + err = imx_ele_msg_send(priv, tx_msg);
> +exit:
> + return err;
> +}
> +
> +/*
> + * Callback called by mailbox FW, when data is received.
> + */
> +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg)
> +{
> + struct device *dev = mbox_cl->dev;
> + struct se_if_device_ctx *dev_ctx;
> + struct se_api_msg *rx_msg;
> + bool is_response = false;
> + struct se_if_priv *priv;
> + struct se_msg_hdr header;
> +
> + priv = dev_get_drvdata(dev);
> + if (!priv) {
> + dev_err(dev, "SE-MU Priv data is NULL;");
> + return;
> + }
If you code you probe and cleanup functions correctly, this should not
happen.
> +
> + /* The function can be called with NULL msg */
> + if (!msg) {
> + dev_err(dev, "Message is invalid\n");
> + return;
> + }
> +
> + header.tag = ((u8 *)msg)[TAG_OFFSET];
> + header.command = ((u8 *)msg)[CMD_OFFSET];
> + header.size = ((u8 *)msg)[SZ_OFFSET];
> + header.ver = ((u8 *)msg)[VER_OFFSET];
Use a proper struct and FIELD_GET() if needed
> +
> + /* Incoming command: wake up the receiver if any. */
> + if (header.tag == priv->cmd_tag) {
> + dev_dbg(dev, "Selecting cmd receiver\n");
> + dev_ctx = priv->cmd_receiver_dev;
> + } else if (header.tag == priv->rsp_tag) {
> + if (priv->waiting_rsp_dev) {
> + dev_dbg(dev, "Selecting rsp waiter\n");
> + dev_ctx = priv->waiting_rsp_dev;
> + is_response = true;
> + } else {
> + /*
> + * Reading the EdgeLock Enclave response
> + * to the command, sent by other
> + * linux kernel services.
> + */
> + spin_lock(&priv->lock);
> + memcpy(&priv->rx_msg, msg, header.size << 2);
> +
> + complete(&priv->done);
> + spin_unlock(&priv->lock);
> + return;
> + }
> + } else {
> + dev_err(dev, "Failed to select a device for message: %.8x\n",
> + *((u32 *) &header));
> + return;
> + }
> + /* Init reception */
> + rx_msg = kzalloc(header.size << 2, GFP_KERNEL);
> + if (rx_msg)
> + memcpy(rx_msg, msg, header.size << 2);
> +
> + dev_ctx->temp_resp = (u32 *)rx_msg;
> + dev_ctx->temp_resp_size = header.size;
> +
> + /* Allow user to read */
> + dev_ctx->pending_hdr = 1;
> + wake_up_interruptible(&dev_ctx->wq);
> +
> + if (is_response)
> + priv->waiting_rsp_dev = NULL;
This looks racy to me.
> +}
> +
> +int validate_rsp_hdr(struct se_if_priv *priv, u32 header,
> + uint8_t msg_id, uint8_t sz, bool is_base_api)
> +{
> + int ret = -EINVAL;
> + u32 size;
> + u32 cmd;
> + u32 tag;
> + u32 ver;
> +
> + tag = MSG_TAG(header);
> + cmd = MSG_COMMAND(header);
> + size = MSG_SIZE(header);
> + ver = MSG_VER(header);
> +
> + do {
using a do-while loop is uncommong coding style, Why not use return
instead?
> + if (tag != priv->rsp_tag) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: Resp tag mismatch. (0x%x != 0x%x)",
> + msg_id, tag, priv->rsp_tag);
> + break;
> + }
> +
> + if (cmd != msg_id) {
> + dev_err(priv->dev,
> + "MSG Header: Cmd id mismatch. (0x%x != 0x%x)",
> + cmd, msg_id);
> + break;
> + }
> +
> + if (size != (sz >> 2)) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: Cmd size mismatch. (0x%x != 0x%x)",
> + msg_id, size, (sz >> 2));
> + break;
> + }
> +
> + if (is_base_api && (ver != priv->base_api_ver)) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: Base API Vers mismatch. (0x%x != 0x%x)",
> + msg_id, ver, priv->base_api_ver);
> + break;
> + } else if (!is_base_api && ver != priv->fw_api_ver) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: FW API Vers mismatch. (0x%x != 0x%x)",
> + msg_id, ver, priv->fw_api_ver);
> + break;
> + }
> +
> + ret = 0;
> +
> + } while (false);
> +
> + return ret;
> +}
> +
> +int se_save_imem_state(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + int ret;
> +
> + /* EXPORT command will save encrypted IMEM to given address,
> + * so later in resume, IMEM can be restored from the given
> + * address.
> + *
> + * Size must be at least 64 kB.
> + */
> + ret = ele_service_swap(dev,
> + priv->imem.phyaddr,
> + ELE_IMEM_SIZE,
> + ELE_IMEM_EXPORT);
> + if (ret < 0)
> + dev_err(dev, "Failed to export IMEM\n");
> + else
> + dev_info(dev,
> + "Exported %d bytes of encrypted IMEM\n",
> + ret);
> +
> + return ret;
> +}
> +
> +int se_restore_imem_state(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct soc_info s_info;
> + int ret;
> +
> + /* get info from ELE */
> + ret = ele_get_info(dev, &s_info);
> + if (ret) {
> + dev_err(dev, "Failed to get info from ELE.\n");
> + return ret;
> + }
> +
> + /* Get IMEM state, if 0xFE then import IMEM */
> + if (s_info.imem_state == ELE_IMEM_STATE_BAD) {
> + /* IMPORT command will restore IMEM from the given
> + * address, here size is the actual size returned by ELE
> + * during the export operation
> + */
> + ret = ele_service_swap(dev,
> + priv->imem.phyaddr,
> + priv->imem.size,
> + ELE_IMEM_IMPORT);
> + if (ret) {
> + dev_err(dev, "Failed to import IMEM\n");
> + goto exit;
> + }
> + } else
> + goto exit;
> +
> + /* After importing IMEM, check if IMEM state is equal to 0xCA
> + * to ensure IMEM is fully loaded and
> + * ELE functionality can be used.
> + */
> + ret = ele_get_info(dev, &s_info);
> + if (ret) {
> + dev_err(dev, "Failed to get info from ELE.\n");
> + goto exit;
> + }
> +
> + if (s_info.imem_state == ELE_IMEM_STATE_OK)
> + dev_info(dev, "Successfully restored IMEM\n");
> + else
> + dev_err(dev, "Failed to restore IMEM\n");
> +
> +exit:
> + return ret;
> +}
> diff --git a/drivers/firmware/imx/ele_common.h b/drivers/firmware/imx/ele_common.h
> new file mode 100644
> index 000000000000..6e3a2114bb56
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_common.h
> @@ -0,0 +1,43 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +
> +#ifndef __ELE_COMMON_H__
> +#define __ELE_COMMON_H__
> +
> +#include "se_ctrl.h"
> +
> +#define IMX_ELE_FW_DIR "imx/ele/"
> +
> +uint32_t plat_add_msg_crc(uint32_t *msg, uint32_t msg_len);
> +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *priv);
> +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
> + void *tx_msg, int tx_msg_sz);
> +int imx_ele_msg_rcv(struct se_if_priv *priv);
> +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg);
> +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg);
> +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg);
> +int validate_rsp_hdr(struct se_if_priv *priv, unsigned int header,
> + u8 msg_id, u8 sz, bool is_base_api);
> +
> +/* Fill a command message header with a given command ID and length in bytes. */
> +static inline int plat_fill_cmd_msg_hdr(struct se_if_priv *priv,
> + struct se_msg_hdr *hdr,
> + u8 cmd,
> + u32 len,
> + bool is_base_api)
> +{
> + hdr->tag = priv->cmd_tag;
> + hdr->ver = (is_base_api) ? priv->base_api_ver : priv->fw_api_ver;
> + hdr->command = cmd;
> + hdr->size = len >> 2;
> +
> + return 0;
> +}
> +
> +int se_save_imem_state(struct device *dev);
> +int se_restore_imem_state(struct device *dev);
> +
> +#endif /*__ELE_COMMON_H__ */
> diff --git a/drivers/firmware/imx/se_ctrl.c b/drivers/firmware/imx/se_ctrl.c
> new file mode 100644
> index 000000000000..11c5eaa7353f
> --- /dev/null
> +++ b/drivers/firmware/imx/se_ctrl.c
> @@ -0,0 +1,1339 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/dev_printk.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/errno.h>
> +#include <linux/export.h>
> +#include <linux/firmware.h>
> +#include <linux/firmware/imx/se_api.h>
> +#include <linux/genalloc.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/miscdevice.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_reserved_mem.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/sys_soc.h>
> +#include <uapi/linux/se_ioctl.h>
> +
> +#include "ele_base_msg.h"
> +#include "ele_common.h"
> +#include "se_ctrl.h"
> +
> +#define RESERVED_DMA_POOL BIT(1)
BIT(0)?
> +
> +struct imx_se_node_info {
> + u8 se_if_id;
> + u8 se_if_did;
> + u8 max_dev_ctx;
> + u8 cmd_tag;
> + u8 rsp_tag;
> + u8 success_tag;
> + u8 base_api_ver;
> + u8 fw_api_ver;
> + u8 *se_name;
> + u8 *mbox_tx_name;
> + u8 *mbox_rx_name;
> + u8 *pool_name;
> + u8 *fw_name_in_rfs;
> + bool soc_register;
> + bool reserved_dma_ranges;
> + bool imem_mgmt;
> +};
> +
> +struct imx_se_node_info_list {
> + u8 num_mu;
> + u16 soc_id;
> + u16 soc_rev;
> + struct imx_se_node_info info[];
> +};
> +
> +static const struct imx_se_node_info_list imx8ulp_info = {
> + .num_mu = 1,
> + .soc_id = SOC_ID_OF_IMX8ULP,
> + .info = {
> + {
> + .se_if_id = 2,
> + .se_if_did = 7,
> + .max_dev_ctx = 4,
> + .cmd_tag = 0x17,
> + .rsp_tag = 0xe1,
> + .success_tag = 0xd6,
> + .base_api_ver = MESSAGING_VERSION_6,
> + .fw_api_ver = MESSAGING_VERSION_7,
> + .se_name = "hsm1",
> + .mbox_tx_name = "tx",
> + .mbox_rx_name = "rx",
> + .pool_name = "sram",
> + .fw_name_in_rfs = IMX_ELE_FW_DIR\
^
not needed
> + "mx8ulpa2ext-ahab-container.img",
> + .soc_register = true,
> + .reserved_dma_ranges = true,
> + .imem_mgmt = true,
> + },
> + },
> +};
> +
> +static const struct imx_se_node_info_list imx93_info = {
> + .num_mu = 1,
> + .soc_id = SOC_ID_OF_IMX93,
> + .info = {
> + {
> + .se_if_id = 2,
> + .se_if_did = 3,
> + .max_dev_ctx = 4,
> + .cmd_tag = 0x17,
> + .rsp_tag = 0xe1,
> + .success_tag = 0xd6,
> + .base_api_ver = MESSAGING_VERSION_6,
> + .fw_api_ver = MESSAGING_VERSION_7,
> + .se_name = "hsm1",
> + .mbox_tx_name = "tx",
> + .mbox_rx_name = "rx",
> + .reserved_dma_ranges = true,
> + .imem_mgmt = true,
> + .soc_register = true,
> + },
> + },
Some (most?) members of these structs are the same. Why do you have this
abstraction if it's not needed right now?
> +};
> +
> +static const struct of_device_id se_match[] = {
> + { .compatible = "fsl,imx8ulp-ele", .data = (void *)&imx8ulp_info},
^^^^^^^^ cast not needed
> + { .compatible = "fsl,imx93-ele", .data = (void *)&imx93_info},
> + {},
> +};
> +
> +static struct imx_se_node_info
> + *get_imx_se_node_info(struct imx_se_node_info_list *info_list,
> + const u32 idx)
> +{
> + if (idx < 0 || idx > info_list->num_mu)
u32 cannot be < 0
> + return NULL;
> +
> + return &info_list->info[idx];
> +}
> +
> +void *get_phy_buf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + dma_addr_t *buf,
> + u32 size)
> +{
> + struct device_node *of_node = dev->of_node;
> + struct gen_pool *mem_pool;
> +
> + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> + if (!mem_pool) {
> + dev_err(dev,
> + "Unable to get sram pool = %s\n",
> + mem_pool_name);
> + return 0;
> + }
> +
> + return gen_pool_dma_alloc(mem_pool, size, buf);
> +}
> +
> +void free_phybuf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + u32 *buf,
> + u32 size)
> +{
> + struct device_node *of_node = dev->of_node;
> + struct gen_pool *mem_pool;
> +
> + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> + if (!mem_pool)
> + dev_err(dev,
> + "%s: Failed: Unable to get sram pool.\n",
> + __func__);
> +
> + gen_pool_free(mem_pool, (u64)buf, size);
> +}
> +
> +static int imx_fetch_soc_info(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct imx_se_node_info_list *info_list;
> + const struct imx_se_node_info *info;
> + struct soc_device_attribute *attr;
> + struct soc_device *sdev;
> + struct soc_info s_info;
> + int err = 0;
> +
> + info = priv->info;
> + info_list = (struct imx_se_node_info_list *)
> + device_get_match_data(dev->parent);
I think cast is not needed.
> + if (info_list->soc_rev)
> + return err;
What does this check do? You'll only get data you put in the info_list
in the first place.
> +
> + err = ele_get_info(dev, &s_info);
> + if (err)
> + s_info.major_ver = DEFAULT_IMX_SOC_VER;
Why continue here in case of error?
> +
> + info_list->soc_rev = s_info.soc_rev;
> +
> + if (!info->soc_register)
> + return 0;
> +
> + attr = devm_kzalloc(dev, sizeof(*attr), GFP_KERNEL);
> + if (!attr)
> + return -ENOMEM;
> +
> + if (s_info.minor_ver)
> + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x.%x",
> + s_info.major_ver,
> + s_info.minor_ver);
> + else
> + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x",
> + s_info.major_ver);
> +
> + switch (s_info.soc_id) {
> + case SOC_ID_OF_IMX8ULP:
> + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> + "i.MX8ULP");
> + break;
> + case SOC_ID_OF_IMX93:
> + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> + "i.MX93");
> + break;
> + }
> +
> + err = of_property_read_string(of_root, "model",
> + &attr->machine);
> + if (err) {
> + devm_kfree(dev, attr);
Why do you do a manual cleanup of devm managed resources? Same applies
to the other devm managed resources, too.
> + return -EINVAL;
> + }
> + attr->family = devm_kasprintf(dev, GFP_KERNEL, "Freescale i.MX");
> +
> + attr->serial_number
> + = devm_kasprintf(dev, GFP_KERNEL, "%016llX", s_info.serial_num);
> +
> + sdev = soc_device_register(attr);
> + if (IS_ERR(sdev)) {
> + devm_kfree(dev, attr->soc_id);
> + devm_kfree(dev, attr->serial_number);
> + devm_kfree(dev, attr->revision);
> + devm_kfree(dev, attr->family);
> + devm_kfree(dev, attr->machine);
> + devm_kfree(dev, attr);
> + return PTR_ERR(sdev);
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * File operations for user-space
> + */
> +
> +/* Write a message to the MU. */
> +static ssize_t se_if_fops_write(struct file *fp, const char __user *buf,
> + size_t size, loff_t *ppos)
> +{
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_if_device_ctx *dev_ctx;
> + struct se_if_priv *priv;
> + int err;
> +
> + dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + priv = dev_ctx->priv;
> + dev_dbg(priv->dev,
> + "%s: write from buf (%p)%zu, ppos=%lld\n",
> + dev_ctx->miscdev.name,
> + buf, size, ((ppos) ? *ppos : 0));
> +
> + if (down_interruptible(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + if (dev_ctx->status != MU_OPENED) {
> + err = -EINVAL;
> + goto exit;
> + }
> +
> + if (size < SE_MU_HDR_SZ) {
> + dev_err(priv->dev,
> + "%s: User buffer too small(%zu < %d)\n",
> + dev_ctx->miscdev.name,
> + size, SE_MU_HDR_SZ);
> + err = -ENOSPC;
> + goto exit;
> + }
> +
> + tx_msg = memdup_user((void __user *)ppos, size);
> + if (!tx_msg) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + /* Copy data to buffer */
> + if (copy_from_user(tx_msg, buf, size)) {
> + err = -EFAULT;
> + dev_err(priv->dev,
> + "%s: Fail copy message from user\n",
> + dev_ctx->miscdev.name);
> + goto exit;
> + }
> +
> + print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4,
> + tx_msg, size, false);
> +
> + err = imx_ele_miscdev_msg_send(dev_ctx, tx_msg, size);
> +
> +exit:
> + up(&dev_ctx->fops_lock);
> + return err;
> +}
> +
> +/*
> + * Read a message from the MU.
> + * Blocking until a message is available.
> + */
> +static ssize_t se_if_fops_read(struct file *fp, char __user *buf,
> + size_t size, loff_t *ppos)
> +{
> + struct se_if_device_ctx *dev_ctx;
> + struct se_buf_desc *b_desc;
> + struct se_if_priv *priv;
> + u32 size_to_copy;
> + int err;
> +
> + dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + priv = dev_ctx->priv;
> + dev_dbg(priv->dev,
> + "%s: read to buf %p(%zu), ppos=%lld\n",
> + dev_ctx->miscdev.name,
> + buf, size, ((ppos) ? *ppos : 0));
> +
> + if (down_interruptible(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + if (dev_ctx->status != MU_OPENED) {
> + err = -EINVAL;
> + goto exit;
> + }
> +
> + err = imx_ele_miscdev_msg_rcv(dev_ctx);
> + if (err)
> + goto exit;
> +
> + /* Buffer containing the message from FW, is
> + * allocated in callback function.
> + * Check if buffer allocation failed.
> + */
> + if (!dev_ctx->temp_resp) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + dev_dbg(priv->dev,
> + "%s: %s %s\n",
> + dev_ctx->miscdev.name,
> + __func__,
> + "message received, start transmit to user");
> +
> + /*
> + * Check that the size passed as argument is larger than
> + * the one carried in the message.
> + */
> + size_to_copy = dev_ctx->temp_resp_size << 2;
> + if (size_to_copy > size) {
> + dev_dbg(priv->dev,
> + "%s: User buffer too small (%zu < %d)\n",
> + dev_ctx->miscdev.name,
> + size, size_to_copy);
> + size_to_copy = size;
> + }
> +
> + /*
> + * We may need to copy the output data to user before
> + * delivering the completion message.
> + */
> + while (!list_empty(&dev_ctx->pending_out)) {
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> + struct se_buf_desc,
> + link);
> + if (!b_desc)
> + continue;
> +
> + if (b_desc->usr_buf_ptr && b_desc->shared_buf_ptr) {
> +
> + dev_dbg(priv->dev,
> + "%s: Copy output data to user\n",
> + dev_ctx->miscdev.name);
> + if (copy_to_user(b_desc->usr_buf_ptr,
> + b_desc->shared_buf_ptr,
> + b_desc->size)) {
> + dev_err(priv->dev,
> + "%s: Failure copying output data to user.",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> + }
> +
> + if (b_desc->shared_buf_ptr)
> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> +
> + __list_del_entry(&b_desc->link);
> + kfree(b_desc);
> + }
> +
> + /* Copy data from the buffer */
> + print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4,
> + dev_ctx->temp_resp, size_to_copy, false);
> + if (copy_to_user(buf, dev_ctx->temp_resp, size_to_copy)) {
> + dev_err(priv->dev,
> + "%s: Failed to copy to user\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> + err = size_to_copy;
> + kfree(dev_ctx->temp_resp);
> +
> + /* free memory allocated on the shared buffers. */
> + dev_ctx->secure_mem.pos = 0;
> + dev_ctx->non_secure_mem.pos = 0;
> +
> + dev_ctx->pending_hdr = 0;
> +
> +exit:
> + /*
> + * Clean the used Shared Memory space,
> + * whether its Input Data copied from user buffers, or
> + * Data received from FW.
> + */
> + while (!list_empty(&dev_ctx->pending_in) ||
> + !list_empty(&dev_ctx->pending_out)) {
> + if (!list_empty(&dev_ctx->pending_in))
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
> + struct se_buf_desc,
> + link);
> + else
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> + struct se_buf_desc,
> + link);
> +
> + if (!b_desc)
> + continue;
> +
> + if (b_desc->shared_buf_ptr)
> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> +
> + __list_del_entry(&b_desc->link);
> + kfree(b_desc);
> + }
> +
> + up(&dev_ctx->fops_lock);
> + return err;
> +}
> +
> +/* Give access to EdgeLock Enclave, to the memory we want to share */
> +static int se_if_setup_se_mem_access(struct se_if_device_ctx *dev_ctx,
> + u64 addr, u32 len)
> +{
> + /* Assuming EdgeLock Enclave has access to all the memory regions */
> + int ret = 0;
> +
> + if (ret) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Fail find memreg\n", dev_ctx->miscdev.name);
> + goto exit;
> + }
> +
> + if (ret) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Fail set permission for resource\n",
> + dev_ctx->miscdev.name);
> + goto exit;
> + }
> +
> +exit:
> + return ret;
> +}
> +
> +static int se_ioctl_get_mu_info(struct se_if_device_ctx *dev_ctx,
> + u64 arg)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev_ctx->dev);
> + struct imx_se_node_info *if_node_info;
> + struct se_ioctl_get_if_info info;
> + int err = 0;
> +
> + if_node_info = (struct imx_se_node_info *)priv->info;
> +
> + info.se_if_id = if_node_info->se_if_id;
> + info.interrupt_idx = 0;
> + info.tz = 0;
> + info.did = if_node_info->se_if_did;
> + info.cmd_tag = if_node_info->cmd_tag;
> + info.rsp_tag = if_node_info->rsp_tag;
> + info.success_tag = if_node_info->success_tag;
> + info.base_api_ver = if_node_info->base_api_ver;
> + info.fw_api_ver = if_node_info->fw_api_ver;
> +
> + dev_dbg(priv->dev,
> + "%s: info [se_if_id: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n",
> + dev_ctx->miscdev.name,
> + info.se_if_id, info.interrupt_idx, info.tz, info.did);
> +
> + if (copy_to_user((u8 *)arg, &info, sizeof(info))) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed to copy mu info to user\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> +exit:
> + return err;
> +}
> +
> +/*
> + * Copy a buffer of data to/from the user and return the address to use in
> + * messages
> + */
> +static int se_ioctl_setup_iobuf_handler(struct se_if_device_ctx *dev_ctx,
> + u64 arg)
> +{
> + struct se_ioctl_setup_iobuf io = {0};
> + struct se_shared_mem *shared_mem;
> + struct se_buf_desc *b_desc;
> + int err = 0;
> + u32 pos;
> +
> + if (copy_from_user(&io, (u8 *)arg, sizeof(io))) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed copy iobuf config from user\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> + dev_dbg(dev_ctx->priv->dev,
> + "%s: io [buf: %p(%d) flag: %x]\n",
> + dev_ctx->miscdev.name,
> + io.user_buf, io.length, io.flags);
> +
> + if (io.length == 0 || !io.user_buf) {
> + /*
> + * Accept NULL pointers since some buffers are optional
> + * in FW commands. In this case we should return 0 as
> + * pointer to be embedded into the message.
> + * Skip all data copy part of code below.
> + */
> + io.ele_addr = 0;
> + goto copy;
> + }
> +
> + /* Select the shared memory to be used for this buffer. */
> + if (io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) {
> + /* App requires to use secure memory for this buffer.*/
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed allocate SEC MEM memory\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + } else {
> + /* No specific requirement for this buffer. */
> + shared_mem = &dev_ctx->non_secure_mem;
> + }
> +
> + /* Check there is enough space in the shared memory. */
> + if (shared_mem->size < shared_mem->pos
> + || io.length >= shared_mem->size - shared_mem->pos) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Not enough space in shared memory\n",
> + dev_ctx->miscdev.name);
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + /* Allocate space in shared memory. 8 bytes aligned. */
> + pos = shared_mem->pos;
> + shared_mem->pos += round_up(io.length, 8u);
> + io.ele_addr = (u64)shared_mem->dma_addr + pos;
> +
> + if ((io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) &&
> + !(io.flags & SE_MU_IO_FLAGS_USE_SHORT_ADDR)) {
> + /*Add base address to get full address.*/
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed allocate SEC MEM memory\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> + memset(shared_mem->ptr + pos, 0, io.length);
> + if ((io.flags & SE_IO_BUF_FLAGS_IS_INPUT) ||
> + (io.flags & SE_IO_BUF_FLAGS_IS_IN_OUT)) {
> + /*
> + * buffer is input:
> + * copy data from user space to this allocated buffer.
> + */
> + if (copy_from_user(shared_mem->ptr + pos, io.user_buf,
> + io.length)) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed copy data to shared memory\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> + }
> +
> + b_desc = kzalloc(sizeof(*b_desc), GFP_KERNEL);
> + if (!b_desc) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> +copy:
> + /* Provide the EdgeLock Enclave address to user space only if success.*/
> + if (copy_to_user((u8 *)arg, &io, sizeof(io))) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed to copy iobuff setup to user\n",
> + dev_ctx->miscdev.name);
> + kfree(b_desc);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> + if (b_desc) {
> + b_desc->shared_buf_ptr = shared_mem->ptr + pos;
> + b_desc->usr_buf_ptr = io.user_buf;
> + b_desc->size = io.length;
> +
> + if (io.flags & SE_IO_BUF_FLAGS_IS_INPUT) {
> + /*
> + * buffer is input:
> + * add an entry in the "pending input buffers" list so
> + * that copied data can be cleaned from shared memory
> + * later.
> + */
> + list_add_tail(&b_desc->link, &dev_ctx->pending_in);
> + } else {
> + /*
> + * buffer is output:
> + * add an entry in the "pending out buffers" list so data
> + * can be copied to user space when receiving Secure-Enclave
> + * response.
> + */
> + list_add_tail(&b_desc->link, &dev_ctx->pending_out);
> + }
> + }
> +
> +exit:
> + return err;
> +}
> +
> +/* IOCTL to provide SoC information */
> +static int se_ioctl_get_soc_info_handler(struct se_if_device_ctx *dev_ctx,
> + u64 arg)
> +{
> + struct imx_se_node_info_list *info_list;
> + struct se_ioctl_get_soc_info soc_info;
> + int err = -EINVAL;
> +
> + info_list = (struct imx_se_node_info_list *)
> + device_get_match_data(dev_ctx->priv->dev->parent);
> + if (!info_list)
> + goto exit;
> +
> + soc_info.soc_id = info_list->soc_id;
> + soc_info.soc_rev = info_list->soc_rev;
> +
> + err = (int)copy_to_user((u8 *)arg, (u8 *)(&soc_info), sizeof(soc_info));
> + if (err) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed to copy soc info to user\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> +exit:
> + return err;
> +}
> +
> +/* Open a character device. */
> +static int se_if_fops_open(struct inode *nd, struct file *fp)
> +{
> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + int err;
> +
> + /* Avoid race if opened at the same time */
> + if (down_trylock(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + /* Authorize only 1 instance. */
> + if (dev_ctx->status != MU_FREE) {
> + err = -EBUSY;
> + goto exit;
> + }
> +
> + /*
> + * Allocate some memory for data exchanges with S40x.
> + * This will be used for data not requiring secure memory.
> + */
> + dev_ctx->non_secure_mem.ptr = dmam_alloc_coherent(dev_ctx->dev,
> + MAX_DATA_SIZE_PER_USER,
> + &dev_ctx->non_secure_mem.dma_addr,
> + GFP_KERNEL);
> + if (!dev_ctx->non_secure_mem.ptr) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + err = se_if_setup_se_mem_access(dev_ctx,
> + dev_ctx->non_secure_mem.dma_addr,
> + MAX_DATA_SIZE_PER_USER);
> + if (err) {
> + err = -EPERM;
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed to share access to shared memory\n",
> + dev_ctx->miscdev.name);
> + goto free_coherent;
> + }
> +
> + dev_ctx->non_secure_mem.size = MAX_DATA_SIZE_PER_USER;
> + dev_ctx->non_secure_mem.pos = 0;
> + dev_ctx->status = MU_OPENED;
> +
> + dev_ctx->pending_hdr = 0;
> +
> + goto exit;
> +
> +free_coherent:
> + dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
> + dev_ctx->non_secure_mem.ptr,
> + dev_ctx->non_secure_mem.dma_addr);
> +
> +exit:
> + up(&dev_ctx->fops_lock);
> + return err;
> +}
> +
> +/* Close a character device. */
> +static int se_if_fops_close(struct inode *nd, struct file *fp)
> +{
> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + struct se_if_priv *priv = dev_ctx->priv;
> + struct se_buf_desc *b_desc;
> +
> + /* Avoid race if closed at the same time */
> + if (down_trylock(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + /* The device context has not been opened */
> + if (dev_ctx->status != MU_OPENED)
> + goto exit;
> +
> + /* check if this device was registered as command receiver. */
> + if (priv->cmd_receiver_dev == dev_ctx)
> + priv->cmd_receiver_dev = NULL;
> +
> + /* check if this device was registered as waiting response. */
> + if (priv->waiting_rsp_dev == dev_ctx) {
> + priv->waiting_rsp_dev = NULL;
> + mutex_unlock(&priv->se_if_cmd_lock);
> + }
> +
> + /* Unmap secure memory shared buffer. */
> + if (dev_ctx->secure_mem.ptr)
> + devm_iounmap(dev_ctx->dev, dev_ctx->secure_mem.ptr);
> +
> + dev_ctx->secure_mem.ptr = NULL;
> + dev_ctx->secure_mem.dma_addr = 0;
> + dev_ctx->secure_mem.size = 0;
> + dev_ctx->secure_mem.pos = 0;
> +
> + /* Free non-secure shared buffer. */
> + dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
> + dev_ctx->non_secure_mem.ptr,
> + dev_ctx->non_secure_mem.dma_addr);
> +
> + dev_ctx->non_secure_mem.ptr = NULL;
> + dev_ctx->non_secure_mem.dma_addr = 0;
> + dev_ctx->non_secure_mem.size = 0;
> + dev_ctx->non_secure_mem.pos = 0;
> +
> + while (!list_empty(&dev_ctx->pending_in) ||
> + !list_empty(&dev_ctx->pending_out)) {
> + if (!list_empty(&dev_ctx->pending_in))
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
> + struct se_buf_desc,
> + link);
> + else
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> + struct se_buf_desc,
> + link);
> +
> + if (!b_desc)
> + continue;
> +
> + if (b_desc->shared_buf_ptr)
> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> +
> + __list_del_entry(&b_desc->link);
> + devm_kfree(dev_ctx->dev, b_desc);
> + }
> +
> + dev_ctx->status = MU_FREE;
> +
> +exit:
> + up(&dev_ctx->fops_lock);
> + return 0;
> +}
> +
> +/* IOCTL entry point of a character device */
> +static long se_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
> +//static long se_ioctl(struct file *fp, u32 cmd, u64 arg)
> +{
> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + struct se_if_priv *se_if_priv = dev_ctx->priv;
> + int err = -EINVAL;
> +
> + /* Prevent race during change of device context */
> + if (down_interruptible(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + switch (cmd) {
> + case SE_IOCTL_ENABLE_CMD_RCV:
> + if (!se_if_priv->cmd_receiver_dev) {
> + se_if_priv->cmd_receiver_dev = dev_ctx;
> + err = 0;
> + }
> + break;
> + case SE_IOCTL_GET_MU_INFO:
> + err = se_ioctl_get_mu_info(dev_ctx, arg);
> + break;
> + case SE_IOCTL_SETUP_IOBUF:
> + err = se_ioctl_setup_iobuf_handler(dev_ctx, arg);
> + break;
> + case SE_IOCTL_GET_SOC_INFO:
> + err = se_ioctl_get_soc_info_handler(dev_ctx, arg);
> + break;
> +
> + default:
> + err = -EINVAL;
> + dev_dbg(se_if_priv->dev,
> + "%s: IOCTL %.8x not supported\n",
> + dev_ctx->miscdev.name,
> + cmd);
> + }
> +
> + up(&dev_ctx->fops_lock);
> + return (long)err;
> +}
> +
> +/* Char driver setup */
> +static const struct file_operations se_if_fops = {
> + .open = se_if_fops_open,
> + .owner = THIS_MODULE,
> + .release = se_if_fops_close,
> + .unlocked_ioctl = se_ioctl,
> + .read = se_if_fops_read,
> + .write = se_if_fops_write,
> +};
> +
> +/* interface for managed res to free a mailbox channel */
> +static void if_mbox_free_channel(void *mbox_chan)
> +{
> + mbox_free_channel(mbox_chan);
> +}
> +
> +/* interface for managed res to unregister a character device */
> +static void if_misc_deregister(void *miscdevice)
> +{
> + misc_deregister(miscdevice);
> +}
> +
> +static int se_if_request_channel(struct device *dev,
> + struct mbox_chan **chan,
> + struct mbox_client *cl,
> + const u8 *name)
^^
mbox_request_channel_byname() uses a "char" for the name not a u8.
> +{
> + struct mbox_chan *t_chan;
> + int ret = 0;
> +
> + t_chan = mbox_request_channel_byname(cl, name);
> + if (IS_ERR(t_chan)) {
> + ret = PTR_ERR(t_chan);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev,
> + "Failed to request chan %s ret %d\n", name,
> + ret);
> + goto exit;
> + }
> +
> + ret = devm_add_action(dev, if_mbox_free_channel, t_chan);
> + if (ret) {
> + dev_err(dev, "failed to add devm removal of mbox %s\n", name);
> + goto exit;
> + }
> +
> + *chan = t_chan;
> +
> +exit:
> + return ret;
> +}
> +
> +static int se_probe_if_cleanup(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct se_if_priv *priv;
> + int ret = 0;
> + int i;
> +
> + priv = dev_get_drvdata(dev);
> + if (!priv) {
> + ret = 0;
> + dev_dbg(dev, "SE-MU Priv data is NULL;");
> + return ret;
> + }
> +
> + if (priv->tx_chan)
> + mbox_free_channel(priv->tx_chan);
> + if (priv->rx_chan)
> + mbox_free_channel(priv->rx_chan);
> +
> + /* free the buffer in se remove, previously allocated
> + * in se probe to store encrypted IMEM
> + */
> + if (priv->imem.buf) {
> + dmam_free_coherent(dev,
> + ELE_IMEM_SIZE,
> + priv->imem.buf,
> + priv->imem.phyaddr);
> + priv->imem.buf = NULL;
> + }
Why cleanup devm managed resources?
> +
> + if (priv->ctxs) {
> + for (i = 0; i < priv->max_dev_ctx; i++) {
> + if (priv->ctxs[i]) {
> + devm_remove_action(dev,
> + if_misc_deregister,
> + &priv->ctxs[i]->miscdev);
> + misc_deregister(&priv->ctxs[i]->miscdev);
> + devm_kfree(dev, priv->ctxs[i]);
> + }
> + }
> + devm_kfree(dev, priv->ctxs);
> + }
> +
> + if (priv->flags & RESERVED_DMA_POOL) {
> + of_reserved_mem_device_release(dev);
> + priv->flags &= (~RESERVED_DMA_POOL);
> + }
> +
> + devm_kfree(dev, priv);
> + of_node_put(dev->of_node);
> + of_platform_device_destroy(dev, NULL);
> +
> + return ret;
> +}
> +
> +static int se_probe_cleanup(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *if_dn;
> +
> + /* Enumerate se-interface device nodes. */
> + for_each_child_of_node(dev->of_node, if_dn) {
> + struct platform_device *if_pdev
> + = of_find_device_by_node(if_dn);
> + if (se_probe_if_cleanup(if_pdev))
> + dev_err(dev,
> + "Failed to clean-up child node probe.\n");
> + }
> +
> + return 0;
> +}
> +
> +static int init_device_context(struct device *dev)
> +{
> + const struct imx_se_node_info *info;
> + struct se_if_device_ctx *dev_ctx;
> + struct se_if_priv *priv;
> + u8 *devname;
> + int ret = 0;
> + int i;
> +
> + priv = dev_get_drvdata(dev);
> +
> + if (!priv) {
> + ret = -EINVAL;
> + dev_err(dev, "Invalid SE-MU Priv data");
> + return ret;
> + }
> + info = priv->info;
> +
> + priv->ctxs = devm_kzalloc(dev, sizeof(dev_ctx) * priv->max_dev_ctx,
> + GFP_KERNEL);
> +
> + if (!priv->ctxs) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + /* Create users */
> + for (i = 0; i < priv->max_dev_ctx; i++) {
> + dev_ctx = devm_kzalloc(dev, sizeof(*dev_ctx), GFP_KERNEL);
> + if (!dev_ctx) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + dev_ctx->dev = dev;
> + dev_ctx->status = MU_FREE;
> + dev_ctx->priv = priv;
> +
> + priv->ctxs[i] = dev_ctx;
> +
> + /* Default value invalid for an header. */
> + init_waitqueue_head(&dev_ctx->wq);
> +
> + INIT_LIST_HEAD(&dev_ctx->pending_out);
> + INIT_LIST_HEAD(&dev_ctx->pending_in);
> + sema_init(&dev_ctx->fops_lock, 1);
> +
> + devname = devm_kasprintf(dev, GFP_KERNEL, "%s_ch%d",
> + info->se_name, i);
> + if (!devname) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + dev_ctx->miscdev.name = devname;
> + dev_ctx->miscdev.minor = MISC_DYNAMIC_MINOR;
> + dev_ctx->miscdev.fops = &se_if_fops;
> + dev_ctx->miscdev.parent = dev;
> + ret = misc_register(&dev_ctx->miscdev);
> + if (ret) {
> + dev_err(dev, "failed to register misc device %d\n",
> + ret);
> + return ret;
> + }
> +
> + ret = devm_add_action(dev, if_misc_deregister,
> + &dev_ctx->miscdev);
> + if (ret) {
> + dev_err(dev,
> + "failed[%d] to add action to the misc-dev\n",
> + ret);
> + return ret;
> + }
> + }
> +
> + return ret;
> +}
> +
> +static void se_load_firmware(const struct firmware *fw, void *context)
> +{
> + struct se_if_priv *priv = (struct se_if_priv *) context;
> + const struct imx_se_node_info *info = priv->info;
> + const u8 *se_fw_name = info->fw_name_in_rfs;
> + phys_addr_t se_fw_phyaddr;
> + u8 *se_fw_buf;
> +
> + if (!fw) {
> + if (priv->fw_fail > MAX_FW_LOAD_RETRIES)
> + dev_dbg(priv->dev,
> + "External FW not found, using ROM FW.\n");
> + else {
> + /*add a bit delay to wait for firmware priv released */
> + msleep(20);
> +
> + /* Load firmware one more time if timeout */
> + request_firmware_nowait(THIS_MODULE,
> + FW_ACTION_UEVENT, info->fw_name_in_rfs,
> + priv->dev, GFP_KERNEL, priv,
> + se_load_firmware);
> + priv->fw_fail++;
> + dev_dbg(priv->dev, "Value of retries = 0x%x.\n",
> + priv->fw_fail);
> + }
> +
> + return;
> + }
> +
> + /* allocate buffer to store the SE FW */
> + se_fw_buf = dmam_alloc_coherent(priv->dev, fw->size,
> + &se_fw_phyaddr,
> + GFP_KERNEL);
> + if (!se_fw_buf) {
> + dev_err(priv->dev, "Failed to alloc SE fw buffer memory\n");
> + goto exit;
> + }
> +
> + memcpy(se_fw_buf, fw->data, fw->size);
> +
> + if (ele_fw_authenticate(priv->dev, se_fw_phyaddr))
> + dev_err(priv->dev,
> + "Failed to authenticate & load SE firmware %s.\n",
> + se_fw_name);
> +
> +exit:
> + dmam_free_coherent(priv->dev,
> + fw->size,
> + se_fw_buf,
> + se_fw_phyaddr);
> +
> + release_firmware(fw);
> +}
> +
> +static int se_if_probe(struct platform_device *pdev)
> +{
> + struct imx_se_node_info_list *info_list;
> + struct device *dev = &pdev->dev;
> + struct imx_se_node_info *info;
> + struct se_if_priv *priv;
> + u32 idx;
> + int ret;
> +
> + if (of_property_read_u32(dev->of_node, "reg", &idx)) {
> + ret = -EINVAL;
> + goto exit;
> + }
> +
> + info_list = (struct imx_se_node_info_list *)
> + device_get_match_data(dev->parent);
> + info = get_imx_se_node_info(info_list, idx);
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv) {
> + ret = -ENOMEM;
> + goto exit;
> + }
> +
> + dev_set_drvdata(dev, priv);
> +
> + /* Mailbox client configuration */
> + priv->se_mb_cl.dev = dev;
> + priv->se_mb_cl.tx_block = false;
> + priv->se_mb_cl.knows_txdone = true;
> + priv->se_mb_cl.rx_callback = se_if_rx_callback;
> +
> + ret = se_if_request_channel(dev, &priv->tx_chan,
> + &priv->se_mb_cl, info->mbox_tx_name);
> + if (ret) {
> + if (ret == -EPROBE_DEFER)
Don't test for -EPROBE_DEFER, use dev_err_probe().
> + dev_err(dev, "Mailbox tx channel, is not ready.\n");
> + else
> + dev_err(dev, "Failed to request tx channel\n");
> +
> + goto exit;
> + }
> +
> + ret = se_if_request_channel(dev, &priv->rx_chan,
> + &priv->se_mb_cl, info->mbox_rx_name);
> + if (ret) {
> + if (ret == -EPROBE_DEFER)
> + dev_err(dev, "Mailbox rx channel, is not ready.\n");
> + else
> + dev_dbg(dev, "Failed to request rx channel\n");
> +
> + goto exit;
> + }
> +
> + priv->dev = dev;
> + priv->info = info;
> +
> + /* Initialize the mutex. */
> + mutex_init(&priv->se_if_lock);
> + mutex_init(&priv->se_if_cmd_lock);
> +
> + priv->cmd_receiver_dev = NULL;
> + priv->waiting_rsp_dev = NULL;
> + priv->max_dev_ctx = info->max_dev_ctx;
> + priv->cmd_tag = info->cmd_tag;
> + priv->rsp_tag = info->rsp_tag;
> + priv->mem_pool_name = info->pool_name;
> + priv->success_tag = info->success_tag;
> + priv->base_api_ver = info->base_api_ver;
> + priv->fw_api_ver = info->fw_api_ver;
> +
> + init_completion(&priv->done);
> + spin_lock_init(&priv->lock);
> +
> + if (info->reserved_dma_ranges) {
> + ret = of_reserved_mem_device_init(dev);
> + if (ret) {
> + dev_err(dev,
> + "failed to init reserved memory region %d\n",
> + ret);
> + priv->flags &= (~RESERVED_DMA_POOL);
> + goto exit;
> + }
> + priv->flags |= RESERVED_DMA_POOL;
> + }
> +
> + if (info->fw_name_in_rfs) {
> + ret = request_firmware_nowait(THIS_MODULE,
> + FW_ACTION_UEVENT,
> + info->fw_name_in_rfs,
> + dev, GFP_KERNEL, priv,
> + se_load_firmware);
> + if (ret)
> + dev_warn(dev, "Failed to get firmware [%s].\n",
> + info->fw_name_in_rfs);
> + }
> +
> + ret = imx_fetch_soc_info(dev);
> + if (ret) {
> + dev_err(dev,
> + "failed[%d] to fetch SoC Info\n", ret);
Use %pe to print error values
> + goto exit;
> + }
> +
> + if (info->imem_mgmt) {
> + /* allocate buffer where SE store encrypted IMEM */
> + priv->imem.buf = dmam_alloc_coherent(dev, ELE_IMEM_SIZE,
> + &priv->imem.phyaddr,
> + GFP_KERNEL);
> + if (!priv->imem.buf) {
> + dev_err(dev,
> + "dmam-alloc-failed: To store encr-IMEM.\n");
> + ret = -ENOMEM;
> + goto exit;
> + }
> + }
> +
> + if (info->max_dev_ctx) {
> + ret = init_device_context(dev);
> + if (ret) {
> + dev_err(dev,
> + "Failed[0x%x] to create device contexts.\n",
> + ret);
> + goto exit;
> + }
> + }
> +
> + dev_info(dev, "i.MX secure-enclave: %s interface to firmware, configured.\n",
> + info->se_name);
> + return devm_of_platform_populate(dev);
> +
> +exit:
> + /* if execution control reaches here, if probe fails.
> + * hence doing the cleanup
> + */
> + if (se_probe_if_cleanup(pdev))
> + dev_err(dev,
> + "Failed to clean-up the child node probe.\n");
> +
> + return ret;
> +}
> +
> +static int se_probe(struct platform_device *pdev)
> +{
> + struct device_node *enum_dev_node;
> + struct device *dev = &pdev->dev;
> + int enum_count;
> + int ret;
> +
> + enum_count = of_get_child_count(dev->of_node);
> + if (!enum_count) {
> + ret = -EINVAL;
> + dev_err(dev, "Zero Tx/Rx path MU nodes.\n");
> + return ret;
> + }
> +
> + for_each_child_of_node(dev->of_node, enum_dev_node) {
> + struct platform_device *enum_plat_dev __maybe_unused;
Why is this __maybe_unused?
> +
> + if (!of_device_is_available(enum_dev_node))
> + continue;
> +
> + enum_plat_dev = of_platform_device_create(enum_dev_node,
> + NULL,
> + dev);
> + if (!enum_plat_dev) {
> + ret = -EINVAL;
> + of_node_put(enum_dev_node);
> + dev_err(dev,
> + "Failed to create enumerated platform device.");
> + break;
> + }
> +
> + ret = se_if_probe(enum_plat_dev);
> + }
> + return ret;
> +}
> +
> +static int se_remove(struct platform_device *pdev)
> +{
> + if (se_probe_cleanup(pdev))
> + dev_err(&pdev->dev,
> + "i.MX Secure Enclave is not cleanly un-probed.");
> +
> + return 0;
> +}
> +
> +static int se_suspend(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + const struct imx_se_node_info *info
> + = priv->info;
> +
> + if (info && info->imem_mgmt)
> + priv->imem.size = se_save_imem_state(dev);
> +
> + return 0;
> +}
> +
> +static int se_resume(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + const struct imx_se_node_info *info
> + = priv->info;
> + int i;
> +
> + for (i = 0; i < priv->max_dev_ctx; i++)
> + wake_up_interruptible(&priv->ctxs[i]->wq);
> +
> + if (info && info->imem_mgmt)
> + se_restore_imem_state(dev);
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops se_pm = {
> + RUNTIME_PM_OPS(se_suspend, se_resume, NULL)
> +};
> +
> +static struct platform_driver se_driver = {
> + .driver = {
> + .name = "fsl-se-fw",
> + .of_match_table = se_match,
> + .pm = &se_pm,
> + },
> + .probe = se_probe,
> + .remove = se_remove,
> +};
> +MODULE_DEVICE_TABLE(of, se_match);
> +
> +module_platform_driver(se_driver);
> +
> +MODULE_AUTHOR("Pankaj Gupta <pankaj.gupta@nxp.com>");
> +MODULE_DESCRIPTION("iMX Secure Enclave Driver.");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/firmware/imx/se_ctrl.h b/drivers/firmware/imx/se_ctrl.h
> new file mode 100644
> index 000000000000..76e1ce77c52f
> --- /dev/null
> +++ b/drivers/firmware/imx/se_ctrl.h
> @@ -0,0 +1,151 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#ifndef SE_MU_H
> +#define SE_MU_H
> +
> +#include <linux/miscdevice.h>
> +#include <linux/semaphore.h>
> +#include <linux/mailbox_client.h>
> +
> +#define MAX_FW_LOAD_RETRIES 50
> +
> +#define MSG_TAG(x) (((x) & 0xff000000) >> 24)
> +#define MSG_COMMAND(x) (((x) & 0x00ff0000) >> 16)
> +#define MSG_SIZE(x) (((x) & 0x0000ff00) >> 8)
> +#define MSG_VER(x) ((x) & 0x000000ff)
> +#define RES_STATUS(x) ((x) & 0x000000ff)
please use FIELD_GET(), FIELD_PREP() for these
> +#define MAX_DATA_SIZE_PER_USER (65 * 1024)
> +#define S4_DEFAULT_MUAP_INDEX (2)
> +#define S4_MUAP_DEFAULT_MAX_USERS (4)
> +#define MESSAGING_VERSION_6 0x6
> +#define MESSAGING_VERSION_7 0x7
> +
> +#define DEFAULT_MESSAGING_TAG_COMMAND (0x17u)
> +#define DEFAULT_MESSAGING_TAG_RESPONSE (0xe1u)
> +
> +#define SE_MU_IO_FLAGS_USE_SEC_MEM (0x02u)
> +#define SE_MU_IO_FLAGS_USE_SHORT_ADDR (0x04u)
> +
> +struct se_imem_buf {
> + u8 *buf;
> + phys_addr_t phyaddr;
> + u32 size;
> +};
> +
> +struct se_buf_desc {
> + u8 *shared_buf_ptr;
> + u8 *usr_buf_ptr;
> + u32 size;
> + struct list_head link;
> +};
> +
> +/* Status of a char device */
> +enum se_if_dev_ctx_status_t {
> + MU_FREE,
> + MU_OPENED
> +};
> +
> +struct se_shared_mem {
> + dma_addr_t dma_addr;
> + u32 size;
> + u32 pos;
> + u8 *ptr;
> +};
> +
> +/* Private struct for each char device instance. */
> +struct se_if_device_ctx {
> + struct device *dev;
> + struct se_if_priv *priv;
> + struct miscdevice miscdev;
> +
> + enum se_if_dev_ctx_status_t status;
> + wait_queue_head_t wq;
> + struct semaphore fops_lock;
> +
> + u32 pending_hdr;
> + struct list_head pending_in;
> + struct list_head pending_out;
> +
> + struct se_shared_mem secure_mem;
> + struct se_shared_mem non_secure_mem;
> +
> + u32 *temp_resp;
> + u32 temp_resp_size;
> + struct notifier_block se_notify;
> +};
> +
> +/* Header of the messages exchange with the EdgeLock Enclave */
> +struct se_msg_hdr {
> + u8 ver;
> + u8 size;
> + u8 command;
> + u8 tag;
> +} __packed;
> +
> +#define SE_MU_HDR_SZ 4
> +#define TAG_OFFSET (SE_MU_HDR_SZ - 1)
> +#define CMD_OFFSET (SE_MU_HDR_SZ - 2)
> +#define SZ_OFFSET (SE_MU_HDR_SZ - 3)
> +#define VER_OFFSET (SE_MU_HDR_SZ - 4)
> +
> +struct se_api_msg {
> + u32 header; /* u8 Tag; u8 Command; u8 Size; u8 Ver; */
> + u32 *data;
> +};
> +
> +struct se_if_priv {
> + struct se_if_device_ctx *cmd_receiver_dev;
> + struct se_if_device_ctx *waiting_rsp_dev;
> + bool no_dev_ctx_used;
What does no_dev_ctx_used do?
> + /*
> + * prevent parallel access to the se interface registers
> + * e.g. a user trying to send a command while the other one is
> + * sending a response.
> + */
> + struct mutex se_if_lock;
> + /*
> + * prevent a command to be sent on the se interface while another one is
> + * still processing. (response to a command is allowed)
> + */
> + struct mutex se_if_cmd_lock;
Please explain why you need 2 mutexes here?
> + struct device *dev;
> + u8 *mem_pool_name;
> + u8 cmd_tag;
> + u8 rsp_tag;
> + u8 success_tag;
> + u8 base_api_ver;
> + u8 fw_api_ver;
> + u32 fw_fail;
> + const void *info;
> +
> + struct mbox_client se_mb_cl;
> + struct mbox_chan *tx_chan, *rx_chan;
> + struct se_api_msg *rx_msg;
> + struct completion done;
> + spinlock_t lock;
> + /*
> + * Flag to retain the state of initialization done at
> + * the time of se-mu probe.
> + */
> + uint32_t flags;
> + u8 max_dev_ctx;
> + struct se_if_device_ctx **ctxs;
> + struct se_imem_buf imem;
> +};
> +
> +void *get_phy_buf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + dma_addr_t *buf,
> + u32 size);
> +phys_addr_t get_phy_buf_mem_pool1(struct device *dev,
> + u8 *mem_pool_name,
> + u32 **buf,
> + u32 size);
> +void free_phybuf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + u32 *buf,
> + u32 size);
> +#endif
> diff --git a/include/linux/firmware/imx/se_api.h b/include/linux/firmware/imx/se_api.h
> new file mode 100644
> index 000000000000..c47f84906837
> --- /dev/null
> +++ b/include/linux/firmware/imx/se_api.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#ifndef __SE_API_H__
> +#define __SE_API_H__
> +
> +#include <linux/types.h>
> +
> +#define SOC_ID_OF_IMX8ULP 0x084D
> +#define SOC_ID_OF_IMX93 0x9300
> +
> +#endif /* __SE_API_H__ */
> diff --git a/include/uapi/linux/se_ioctl.h b/include/uapi/linux/se_ioctl.h
> new file mode 100644
> index 000000000000..f68a36e9da2c
> --- /dev/null
> +++ b/include/uapi/linux/se_ioctl.h
> @@ -0,0 +1,88 @@
> +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause*/
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#ifndef SE_IOCTL_H
> +#define SE_IOCTL_H
> +
> +/* IOCTL definitions. */
> +
> +struct se_ioctl_setup_iobuf {
> + u8 *user_buf;
> + u32 length;
> + u32 flags;
> + u64 ele_addr;
> +};
> +
> +struct se_ioctl_shared_mem_cfg {
> + u32 base_offset;
> + u32 size;
> +};
> +
> +struct se_ioctl_get_if_info {
> + u8 se_if_id;
> + u8 interrupt_idx;
> + u8 tz;
> + u8 did;
> + u8 cmd_tag;
> + u8 rsp_tag;
> + u8 success_tag;
> + u8 base_api_ver;
> + u8 fw_api_ver;
> +};
> +
> +struct se_ioctl_signed_message {
> + u8 *message;
> + u32 msg_size;
> + u32 error_code;
> +};
> +
> +struct se_ioctl_get_soc_info {
> + u16 soc_id;
> + u16 soc_rev;
> +};
> +
> +/* IO Buffer Flags */
> +#define SE_IO_BUF_FLAGS_IS_OUTPUT (0x00u)
> +#define SE_IO_BUF_FLAGS_IS_INPUT (0x01u)
> +#define SE_IO_BUF_FLAGS_USE_SEC_MEM (0x02u)
> +#define SE_IO_BUF_FLAGS_USE_SHORT_ADDR (0x04u)
> +#define SE_IO_BUF_FLAGS_IS_IN_OUT (0x10u)
> +
> +/* IOCTLS */
> +#define SE_IOCTL 0x0A /* like MISC_MAJOR. */
> +
> +/*
> + * ioctl to designated the current fd as logical-reciever.
> + * This is ioctl is send when the nvm-daemon, a slave to the
> + * firmware is started by the user.
> + */
> +#define SE_IOCTL_ENABLE_CMD_RCV _IO(SE_IOCTL, 0x01)
> +
> +/*
> + * ioctl to get the buffer allocated from the memory, which is shared
> + * between kernel and FW.
> + * Post allocation, the kernel tagged the allocated memory with:
> + * Output
> + * Input
> + * Input-Output
> + * Short address
> + * Secure-memory
> + */
> +#define SE_IOCTL_SETUP_IOBUF _IOWR(SE_IOCTL, 0x03, \
> + struct se_ioctl_setup_iobuf)
> +
> +/*
> + * ioctl to get the mu information, that is used to exchange message
> + * with FW, from user-spaced.
> + */
> +#define SE_IOCTL_GET_MU_INFO _IOR(SE_IOCTL, 0x04, \
> + struct se_ioctl_get_if_info)
> +/*
> + * ioctl to get SoC Info from user-space.
> + */
> +#define SE_IOCTL_GET_SOC_INFO _IOR(SE_IOCTL, 0x06, \
> + struct se_ioctl_get_soc_info)
> +
> +#endif
>
> --
> 2.34.1
>
regards,
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
Vertretung Nürnberg | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
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_______________________________________________
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^ permalink raw reply [relevance 0%]
* RE: [EXT] Re: [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave
2024-05-10 19:39 0% ` Amit Singh Tomar
@ 2024-05-13 9:16 0% ` Pankaj Gupta
0 siblings, 0 replies; 200+ results
From: Pankaj Gupta @ 2024-05-13 9:16 UTC (permalink / raw)
To: Amit Singh Tomar, Frank Li
Cc: Jonathan Corbet, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
linux-doc, linux-kernel, devicetree, imx, linux-arm-kernel
> -----Original Message-----
> From: Amit Singh Tomar <amitsinght@marvell.com>
> Sent: Saturday, May 11, 2024 1:09 AM
> To: Frank Li <frank.li@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>
> Cc: Jonathan Corbet <corbet@lwn.net>; Rob Herring <robh+dt@kernel.org>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Conor Dooley
> <conor+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Sascha Hauer
> <s.hauer@pengutronix.de>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>; linux-
> doc@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; imx@lists.linux.dev; linux-arm-
> kernel@lists.infradead.org
> Subject: [EXT] Re: [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock
> Enclave
>
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
>
>
> Hi,
> >
> > ----------------------------------------------------------------------
> > On Fri, May 10, 2024 at 06:57:30PM +0530, Pankaj Gupta wrote:
> >> NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE),
> >> are embedded in the SoC to support the features like HSM, SHE & V2X,
> >> using message based communication interface.
> >>
> >> The secure enclave FW communicates on a dedicated messaging unit(MU)
> >> based interface(s) with application core, where kernel is running.
> >> It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
> >>
> >> This patch adds the driver for communication interface to secure-enclave,
> >> for exchanging messages with NXP secure enclave HW IP(s) like EdgeLock
> Enclave,
> >> both from:
> >> - User-Space Applications via character driver.
> >> - Kernel-space, used by kernel management layers like DM-Crypt.
> >>
> >> ABI documentation for the NXP secure-enclave driver.
> >>
> >> User-space library using this driver:
> >> - i.MX Secure Enclave library:
> >> -- URL:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Furldefe
> nse.proofpoint.com%2Fv2%2Furl%3Fu%3Dhttps-3A__github.com_nxp-
> 2Dimx_imx-2Dsecure-
> 2Denclave.git%26d%3DDwICAg%26c%3DnKjWec2b6R0mOyPaz7xtfQ%26r%3
> DV_GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-
> JKU%26m%3DeKFfdy51aVVEAe4I9Lk2CN77y_4Hxf2pI_9fv5pVWLo9DwQNgC
> pca6smAwvwFycf%26s%3DIfKbvjSfdUcqz-
> WEWdhbj1_TnqGryOffX1dV0T5Rf_A%26e%3D&data=05%7C02%7Cpankaj.gu
> pta%40nxp.com%7C111dd89e61f149b5f7e708dc71290348%7C686ea1d3bc2
> b4c6fa92cd99c5c301635%7C0%7C0%7C638509668202231639%7CUnknown
> %7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> wiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=FEt3DR2WBF3v8fNgnliJhVB10
> MCCkaf8KYGmLz3fk3A%3D&reserved=0 ,
> >> - i.MX Secure Middle-Ware:
> >> -- URL:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Furldefe
> nse.proofpoint.com%2Fv2%2Furl%3Fu%3Dhttps-3A__github.com_nxp-
> 2Dimx_imx-
> 2Dsmw.git%26d%3DDwICAg%26c%3DnKjWec2b6R0mOyPaz7xtfQ%26r%3DV
> _GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-
> JKU%26m%3DeKFfdy51aVVEAe4I9Lk2CN77y_4Hxf2pI_9fv5pVWLo9DwQNgC
> pca6smAwvwFycf%26s%3DLLz2plXTM1AS-
> zJ1HlZRKiBE8GmRJBduR_0dnOuFjRo%26e%3D&data=05%7C02%7Cpankaj.gu
> pta%40nxp.com%7C111dd89e61f149b5f7e708dc71290348%7C686ea1d3bc2
> b4c6fa92cd99c5c301635%7C0%7C0%7C638509668202240209%7CUnknown
> %7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> wiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=YOBEbhRl7XJeLu%2BdaznovR
> 4lDrbyoOlmxUP9BiYZ330%3D&reserved=0
> >>
> >> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> >> ---
> >> Documentation/ABI/testing/se-cdev | 42 ++
> >> drivers/firmware/imx/Kconfig | 12 +
> >> drivers/firmware/imx/Makefile | 2 +
> >> drivers/firmware/imx/ele_base_msg.c | 287 ++++++++
> >> drivers/firmware/imx/ele_base_msg.h | 70 ++
> >> drivers/firmware/imx/ele_common.c | 341 +++++++++
> >> drivers/firmware/imx/ele_common.h | 43 ++
> >> drivers/firmware/imx/se_ctrl.c | 1339
> +++++++++++++++++++++++++++++++++++
> >> drivers/firmware/imx/se_ctrl.h | 151 ++++
> >> include/linux/firmware/imx/se_api.h | 14 +
> >> include/uapi/linux/se_ioctl.h | 88 +++
> >> 11 files changed, 2389 insertions(+)
> >>
> >> diff --git a/Documentation/ABI/testing/se-cdev
> b/Documentation/ABI/testing/se-cdev
> >> new file mode 100644
> >> index 000000000000..699525af6b86
> >> --- /dev/null
> >> +++ b/Documentation/ABI/testing/se-cdev
> >> @@ -0,0 +1,42 @@
> >> +What: /dev/<se>_mu[0-9]+_ch[0-9]+
> >> +Date: May 2024
> >> +KernelVersion: 6.8
> >> +Contact: linux-imx@nxp.com, pankaj.gupta@nxp.com
> >> +Description:
> >> + NXP offers multiple hardware IP(s) for secure-enclaves like
> EdgeLock-
> >> + Enclave(ELE), SECO. The character device file-descriptors
> >> + /dev/<se>_mu*_ch* are the interface between user-space NXP's
> secure-
> >> + enclave shared-library and the kernel driver.
> >> +
> >> + The ioctl(2)-based ABI is defined and documented in
> >> + [include]<linux/firmware/imx/ele_mu_ioctl.h>
> >> + ioctl(s) are used primarily for:
> >> + - shared memory management
> >> + - allocation of I/O buffers
> >> + - get mu info
> >> + - setting a dev-ctx as receiver that is slave to fw
> >> + - get SoC info
> >> +
> >> + The following file operations are supported:
> >> +
> >> + open(2)
> >> + Currently the only useful flags are O_RDWR.
> >> +
> >> + read(2)
> >> + Every read() from the opened character device context is waiting
> on
> >> + wakeup_intruptible, that gets set by the registered mailbox
> callback
> >> + function; indicating a message received from the firmware on
> message-
> >> + unit.
> >> +
> >> + write(2)
> >> + Every write() to the opened character device context needs to
> acquire
> >> + mailbox_lock, before sending message on to the message unit.
> >> +
> >> + close(2)
> >> + Stops and free up the I/O contexts that was associated
> >> + with the file descriptor.
> >> +
> >> +Users:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Furldefe
> nse.proofpoint.com%2Fv2%2Furl%3Fu%3Dhttps-3A__github.com_nxp-
> 2Dimx_imx-2Dsecure-
> 2Denclave.git%26d%3DDwICAg%26c%3DnKjWec2b6R0mOyPaz7xtfQ%26r%3
> DV_GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-
> JKU%26m%3DeKFfdy51aVVEAe4I9Lk2CN77y_4Hxf2pI_9fv5pVWLo9DwQNgC
> pca6smAwvwFycf%26s%3DIfKbvjSfdUcqz-
> WEWdhbj1_TnqGryOffX1dV0T5Rf_A%26e%3D&data=05%7C02%7Cpankaj.gu
> pta%40nxp.com%7C111dd89e61f149b5f7e708dc71290348%7C686ea1d3bc2
> b4c6fa92cd99c5c301635%7C0%7C0%7C638509668202246211%7CUnknown
> %7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> wiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=5Cpw4sCLsKzv%2FRiikt2aA4d
> ILonYXeFzcnMo4UugdQ4%3D&reserved=0 ,
> >> +
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Furldefe
> nse.proofpoint.com%2Fv2%2Furl%3Fu%3Dhttps-3A__github.com_nxp-
> 2Dimx_imx-
> 2Dsmw.git%26d%3DDwICAg%26c%3DnKjWec2b6R0mOyPaz7xtfQ%26r%3DV
> _GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-
> JKU%26m%3DeKFfdy51aVVEAe4I9Lk2CN77y_4Hxf2pI_9fv5pVWLo9DwQNgC
> pca6smAwvwFycf%26s%3DLLz2plXTM1AS-
> zJ1HlZRKiBE8GmRJBduR_0dnOuFjRo%26e%3D&data=05%7C02%7Cpankaj.gu
> pta%40nxp.com%7C111dd89e61f149b5f7e708dc71290348%7C686ea1d3bc2
> b4c6fa92cd99c5c301635%7C0%7C0%7C638509668202250817%7CUnknown
> %7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> wiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=m5NZLmshBmqnnbb2U%2Bm
> cMYYbv7LS8X%2ByzMVTs%2BI7tkI%3D&reserved=0
> >> + crypto/skcipher,
> >> + drivers/nvmem/imx-ocotp-ele.c
> >> diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
> >> index 183613f82a11..56bdca9bd917 100644
> >> --- a/drivers/firmware/imx/Kconfig
> >> +++ b/drivers/firmware/imx/Kconfig
> >> @@ -22,3 +22,15 @@ config IMX_SCU
> >>
> >> This driver manages the IPC interface between host CPU and the
> >> SCU firmware running on M4.
> >> +
> >> +config IMX_SEC_ENCLAVE
> >> + tristate "i.MX Embedded Secure Enclave - EdgeLock Enclave Firmware
> driver."
> >> + depends on IMX_MBOX && ARCH_MXC && ARM64
> >> + default m if ARCH_MXC
> >> +
> >> + help
> >> + It is possible to use APIs exposed by the iMX Secure Enclave HW IP
> called:
> >> + - EdgeLock Enclave Firmware (for i.MX8ULP, i.MX93),
> >> + like base, HSM, V2X & SHE using the SAB protocol via the shared
> Messaging
> >> + Unit. This driver exposes these interfaces via a set of file descriptors
> >> + allowing to configure shared memory, send and receive messages.
> >> diff --git a/drivers/firmware/imx/Makefile
> b/drivers/firmware/imx/Makefile
> >> index 8f9f04a513a8..aa9033e0e9e3 100644
> >> --- a/drivers/firmware/imx/Makefile
> >> +++ b/drivers/firmware/imx/Makefile
> >> @@ -1,3 +1,5 @@
> >> # SPDX-License-Identifier: GPL-2.0
> >> obj-$(CONFIG_IMX_DSP) += imx-dsp.o
> >> obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o
> imx-scu-soc.o
> >> +sec_enclave-objs = se_ctrl.o ele_common.o ele_base_msg.o
> >> +obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
> >> diff --git a/drivers/firmware/imx/ele_base_msg.c
> b/drivers/firmware/imx/ele_base_msg.c
> >> new file mode 100644
> >> index 000000000000..0463f26d93c7
> >> --- /dev/null
> >> +++ b/drivers/firmware/imx/ele_base_msg.c
> >> @@ -0,0 +1,287 @@
> >> +// SPDX-License-Identifier: GPL-2.0+
> >> +/*
> >> + * Copyright 2024 NXP
> >> + */
> >> +
> >> +#include <linux/types.h>
> >> +#include <linux/completion.h>
> >> +#include <linux/dma-mapping.h>
> >> +
> >> +#include "ele_base_msg.h"
> >> +#include "ele_common.h"
> >> +
> >> +int ele_get_info(struct device *dev, struct soc_info *s_info)
> >> +{
> >> + struct se_if_priv *priv = dev_get_drvdata(dev);
> >> + struct se_api_msg *tx_msg __free(kfree);
> >> + struct se_api_msg *rx_msg __free(kfree);
> >> + phys_addr_t get_info_addr;
> >> + u32 *get_info_data;
> >> + u32 status;
> >> + int ret;
> >> +
> >> + if (!priv || !s_info)
> >> + goto exit;
> >> +
> >> + memset(s_info, 0x0, sizeof(*s_info));
> >> +
> >> + if (priv->mem_pool_name)
> >> + get_info_data = get_phy_buf_mem_pool(dev,
> >> + priv->mem_pool_name,
> >> + &get_info_addr,
> >> + ELE_GET_INFO_BUFF_SZ);
> >> + else
> >> + get_info_data = dmam_alloc_coherent(dev,
> >> + ELE_GET_INFO_BUFF_SZ,
> >> + &get_info_addr,
> >> + GFP_KERNEL);
> >> + if (!get_info_data) {
> >> + ret = -ENOMEM;
> >> + dev_err(dev,
> >> + "%s: Failed to allocate get_info_addr.\n",
> >> + __func__);
> >> + goto exit;
> >> + }
> >> +
> >> + tx_msg = kzalloc(ELE_GET_INFO_REQ_MSG_SZ << 2, GFP_KERNEL);
> >> + if (!tx_msg) {
> >> + ret = -ENOMEM;
> >> + return ret;
> It seems like you intended to use goto exit; instead of returning
> directly from here. This would ensure that you can free the buffer
> allocated with get_phy_buf_mem_pool in case of an allocation failure.
Accepted.
> >> + }
> >> +
> >> + rx_msg = kzalloc(ELE_GET_INFO_RSP_MSG_SZ << 2, GFP_KERNEL);
> >> + if (!rx_msg) {
> >> + ret = -ENOMEM;
> >> + return ret;
> >> + }
Will correct here as well.
> >> +
> >> + ret = plat_fill_cmd_msg_hdr(priv,
> >> + (struct se_msg_hdr *)&tx_msg->header,
> >> + ELE_GET_INFO_REQ,
> >> + ELE_GET_INFO_REQ_MSG_SZ,
> >> + true);
> >> + if (ret)
> >> + goto exit;
> >> +
> >> + tx_msg->data[0] = upper_32_bits(get_info_addr);
> >> + tx_msg->data[1] = lower_32_bits(get_info_addr);
> >> + tx_msg->data[2] = ELE_GET_INFO_READ_SZ;
> >> + priv->rx_msg = rx_msg;
> >> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> >> + if (ret < 0)
> >> + goto exit;
> >> +
> >> + ret = validate_rsp_hdr(priv,
> >> + priv->rx_msg->header,
> >> + ELE_GET_INFO_REQ,
> >> + ELE_GET_INFO_RSP_MSG_SZ,
> >> + true);
> >> + if (ret)
> >> + goto exit;
> >> +
> >> + status = RES_STATUS(priv->rx_msg->data[0]);
> >> + if (status != priv->success_tag) {
> >> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> >> + ELE_GET_INFO_REQ, status);
> >> + ret = -1;
> >> + }
> >> +
> >> + s_info->imem_state = (get_info_data[ELE_IMEM_STATE_WORD]
> >> + & ELE_IMEM_STATE_MASK) >> 16;
> >> + s_info->major_ver =
> (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> >> + & SOC_VER_MASK) >> 24;
> >> + s_info->minor_ver =
> ((get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> >> + & SOC_VER_MASK) >> 16) & 0xFF;
> >> + s_info->soc_rev =
> (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> >> + & SOC_VER_MASK) >> 16;
> >> + s_info->soc_id = get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> >> + & SOC_ID_MASK;
> >> + s_info->serial_num
> >> + = (u64)get_info_data[GET_INFO_SL_NUM_MSB_WORD_OFF] <<
> 32
> >> + | get_info_data[GET_INFO_SL_NUM_LSB_WORD_OFF];
> >> +exit:
> >> + if (get_info_addr) {
> >> + if (priv->mem_pool_name)
> >> + free_phybuf_mem_pool(dev, priv->mem_pool_name,
> >> + get_info_data, ELE_GET_INFO_BUFF_SZ);
> >> + else
> >> + dmam_free_coherent(dev,
> >> + ELE_GET_INFO_BUFF_SZ,
> >> + get_info_data,
> >> + get_info_addr);
> >> + }
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +int ele_ping(struct device *dev)
> >> +{
> >> + struct se_if_priv *priv = dev_get_drvdata(dev);
> >> + struct se_api_msg *tx_msg __free(kfree);
> >> + struct se_api_msg *rx_msg __free(kfree);
> >
> > If you want __free(kfree) it should be
> >
> > struct se_api_msg *tx_msg __free(kfree) = NULL;
> > struct se_api_msg *rx_msg __free(kfree) = NULL;
> >
> > Or
> >
> > struct se_api_msg *tx_msg __free(kfree) = kzalloc(ELE_PING_REQ_SZ << 2,
> GFP_KERNEL)
> > struct se_api_msg *rx_msg __free(kfree) = kzalloc(ELE_PING_RSP_SZ << 2,
> GFP_KERNEL)
> >
> > otherwise when
> > if (!tx_msg) {
> > return ret;
> >
> > ^^ when go here, rx_msg is random value. So kfree(rx_msg) will
> > access random address.
> >
> > }
> >
> >> + u32 status;
> >> + int ret;
> >> +
> >> + tx_msg = kzalloc(ELE_PING_REQ_SZ << 2, GFP_KERNEL);
> >> + if (!tx_msg) {
> >> + ret = -ENOMEM;
> >> + return ret;
> >
> >
> > return -ENOMEM
> >
> > Frank
> >
> >> + }
> >> +
> >> + rx_msg = kzalloc(ELE_PING_RSP_SZ << 2, GFP_KERNEL);
> >> + if (!rx_msg) {
> >> + ret = -ENOMEM;
> >> + return ret;
> >> + }
> >> +
> >> + ret = plat_fill_cmd_msg_hdr(priv,
> >> + (struct se_msg_hdr *)&tx_msg->header,
> >> + ELE_PING_REQ, ELE_PING_REQ_SZ,
> >> + true);
> >> + if (ret) {
> >> + dev_err(dev, "Error: plat_fill_cmd_msg_hdr failed.\n");
> >> + goto exit;
> >> + }
> >> +
> >> + priv->rx_msg = rx_msg;
> >> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> >> + if (ret)
> >> + goto exit;
> >> +
> >> + ret = validate_rsp_hdr(priv,
> >> + priv->rx_msg->header,
> >> + ELE_PING_REQ,
> >> + ELE_PING_RSP_SZ,
> >> + true);
> >> + if (ret)
> >> + goto exit;
> >> +
> >> + status = RES_STATUS(priv->rx_msg->data[0]);
> >> + if (status != priv->success_tag) {
> >> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> >> + ELE_PING_REQ, status);
> >> + ret = -1;
> >> + }
> >> +exit:
> >> + return ret;
> >> +}
> >> +
> >> +int ele_service_swap(struct device *dev,
> >> + phys_addr_t addr,
> >> + u32 addr_size, u16 flag)
> >> +{
> >> + struct se_if_priv *priv = dev_get_drvdata(dev);
> >> + struct se_api_msg *tx_msg __free(kfree);
> >> + struct se_api_msg *rx_msg __free(kfree);
> >> + u32 status;
> >> + int ret;
> >> +
> >> + tx_msg = kzalloc(ELE_SERVICE_SWAP_REQ_MSG_SZ << 2,
> GFP_KERNEL);
> >> + if (!tx_msg) {
> >> + ret = -ENOMEM;
> >> + return ret;
> >> + }
> >> +
> >> + rx_msg = kzalloc(ELE_SERVICE_SWAP_RSP_MSG_SZ << 2,
> GFP_KERNEL);
> >> + if (!rx_msg) {
> >> + ret = -ENOMEM;
> >> + return ret;
> >> + }
> >> +
> >> + ret = plat_fill_cmd_msg_hdr(priv,
> >> + (struct se_msg_hdr *)&tx_msg->header,
> >> + ELE_SERVICE_SWAP_REQ,
> >> + ELE_SERVICE_SWAP_REQ_MSG_SZ,
> >> + true);
> >> + if (ret)
> >> + goto exit;
> >> +
> >> + tx_msg->data[0] = flag;
> >> + tx_msg->data[1] = addr_size;
> >> + tx_msg->data[2] = ELE_NONE_VAL;
> >> + tx_msg->data[3] = lower_32_bits(addr);
> >> + tx_msg->data[4] = plat_add_msg_crc((uint32_t *)&tx_msg[0],
> >> + ELE_SERVICE_SWAP_REQ_MSG_SZ);
> >> + priv->rx_msg = rx_msg;
> >> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> >> + if (ret < 0)
> >> + goto exit;
> >> +
> >> + ret = validate_rsp_hdr(priv,
> >> + priv->rx_msg->header,
> >> + ELE_SERVICE_SWAP_REQ,
> >> + ELE_SERVICE_SWAP_RSP_MSG_SZ,
> >> + true);
> >> + if (ret)
> >> + goto exit;
> >> +
> >> + status = RES_STATUS(priv->rx_msg->data[0]);
> >> + if (status != priv->success_tag) {
> >> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> >> + ELE_SERVICE_SWAP_REQ, status);
> >> + ret = -1;
> >> + } else {
> >> + if (flag == ELE_IMEM_EXPORT)
> >> + ret = priv->rx_msg->data[1];
> >> + else
> >> + ret = 0;
> >> + }
> >> +exit:
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +int ele_fw_authenticate(struct device *dev, phys_addr_t addr)
> >> +{
> >> + struct se_if_priv *priv = dev_get_drvdata(dev);
> >> + struct se_api_msg *tx_msg __free(kfree);
> >> + struct se_api_msg *rx_msg __free(kfree);
> >> + u32 status;
> >> + int ret;
> >> +
> >> + tx_msg = kzalloc(ELE_FW_AUTH_REQ_SZ << 2, GFP_KERNEL);
> >> + if (!tx_msg) {
> >> + ret = -ENOMEM;
> >> + return ret;
> >> + }
> >> +
> >> + rx_msg = kzalloc(ELE_FW_AUTH_RSP_MSG_SZ << 2, GFP_KERNEL);
> >> + if (!rx_msg) {
> >> + ret = -ENOMEM;
> >> + return ret;
> >> + }
> >> + ret = plat_fill_cmd_msg_hdr(priv,
> >> + (struct se_msg_hdr *)&tx_msg->header,
> >> + ELE_FW_AUTH_REQ,
> >> + ELE_FW_AUTH_REQ_SZ,
> >> + true);
> >> + if (ret)
> >> + goto exit;
> >> +
> >> + tx_msg->data[0] = addr;
> >> + tx_msg->data[1] = 0x0;
> >> + tx_msg->data[2] = addr;
> >> +
> >> + priv->rx_msg = rx_msg;
> >> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> >> + if (ret < 0)
> >> + goto exit;
> >> +
> >> + ret = validate_rsp_hdr(priv,
> >> + priv->rx_msg->header,
> >> + ELE_FW_AUTH_REQ,
> >> + ELE_FW_AUTH_RSP_MSG_SZ,
> >> + true);
> >> + if (ret)
> >> + goto exit;
> >> +
> >> + status = RES_STATUS(priv->rx_msg->data[0]);
> >> + if (status != priv->success_tag) {
> >> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> >> + ELE_FW_AUTH_REQ, status);
> >> + ret = -1;
> >> + }
> >> +exit:
> >> +
> >> + return ret;
> >> +}
> >> diff --git a/drivers/firmware/imx/ele_base_msg.h
> b/drivers/firmware/imx/ele_base_msg.h
> >> new file mode 100644
> >> index 000000000000..3b3d2bf04a84
> >> --- /dev/null
> >> +++ b/drivers/firmware/imx/ele_base_msg.h
> >> @@ -0,0 +1,70 @@
> >> +/* SPDX-License-Identifier: GPL-2.0+ */
> >> +/*
> >> + * Copyright 2024 NXP
> >> + *
> >> + * Header file for the EdgeLock Enclave Base API(s).
> >> + */
> >> +
> >> +#ifndef ELE_BASE_MSG_H
> >> +#define ELE_BASE_MSG_H
> >> +
> >> +#include <linux/device.h>
> >> +#include <linux/types.h>
> >> +
> >> +#define WORD_SZ 4
> >> +#define ELE_NONE_VAL 0x0
> >> +
> >> +#define ELE_SUCCESS_IND 0xD6
> >> +
> >> +#define ELE_GET_INFO_REQ 0xDA
> >> +#define ELE_GET_INFO_REQ_MSG_SZ 0x10
> >> +#define ELE_GET_INFO_RSP_MSG_SZ 0x08
> >> +
> >> +#define ELE_GET_INFO_BUFF_SZ 0x100
> >> +#define ELE_GET_INFO_READ_SZ 0xA0
> >> +
> >> +#define DEFAULT_IMX_SOC_VER 0xA0
> >> +#define SOC_VER_MASK 0xFFFF0000
> >> +#define SOC_ID_MASK 0x0000FFFF
> >> +struct soc_info {
> >> + u32 imem_state;
> >> + u8 major_ver;
> >> + u8 minor_ver;
> >> + u16 soc_id;
> >> + u16 soc_rev;
> >> + u64 serial_num;
> >> +};
> >> +
> >> +#define GET_INFO_SOC_INFO_WORD_OFFSET 1
> >> +#define GET_INFO_UUID_WORD_OFFSET 3
> >> +#define GET_INFO_SL_NUM_MSB_WORD_OFF \
> >> + (GET_INFO_UUID_WORD_OFFSET + 3)
> >> +#define GET_INFO_SL_NUM_LSB_WORD_OFF \
> >> + (GET_INFO_UUID_WORD_OFFSET + 0)
> >> +
> >> +#define ELE_PING_REQ 0x01
> >> +#define ELE_PING_REQ_SZ 0x04
> >> +#define ELE_PING_RSP_SZ 0x08
> >> +
> >> +#define ELE_SERVICE_SWAP_REQ 0xDF
> >> +#define ELE_SERVICE_SWAP_REQ_MSG_SZ 0x18
> >> +#define ELE_SERVICE_SWAP_RSP_MSG_SZ 0x0C
> >> +#define ELE_IMEM_SIZE 0x10000
> >> +#define ELE_IMEM_STATE_OK 0xCA
> >> +#define ELE_IMEM_STATE_BAD 0xFE
> >> +#define ELE_IMEM_STATE_WORD 0x27
> >> +#define ELE_IMEM_STATE_MASK 0x00ff0000
> >> +#define ELE_IMEM_EXPORT 0x1
> >> +#define ELE_IMEM_IMPORT 0x2
> >> +
> >> +#define ELE_FW_AUTH_REQ 0x02
> >> +#define ELE_FW_AUTH_REQ_SZ 0x10
> >> +#define ELE_FW_AUTH_RSP_MSG_SZ 0x08
> >> +
> >> +int ele_get_info(struct device *dev, struct soc_info *s_info);
> >> +int ele_ping(struct device *dev);
> >> +int ele_service_swap(struct device *dev,
> >> + phys_addr_t addr,
> >> + u32 addr_size, u16 flag);
> >> +int ele_fw_authenticate(struct device *dev, phys_addr_t addr);
> >> +#endif
> >> diff --git a/drivers/firmware/imx/ele_common.c
> b/drivers/firmware/imx/ele_common.c
> >> new file mode 100644
> >> index 000000000000..dcf7f9034653
> >> --- /dev/null
> >> +++ b/drivers/firmware/imx/ele_common.c
> >> @@ -0,0 +1,341 @@
> >> +// SPDX-License-Identifier: GPL-2.0+
> >> +/*
> >> + * Copyright 2024 NXP
> >> + */
> >> +
> >> +#include "ele_base_msg.h"
> >> +#include "ele_common.h"
> >> +
> >> +u32 plat_add_msg_crc(u32 *msg, u32 msg_len)
> >> +{
> >> + u32 nb_words = msg_len / (u32)sizeof(u32);
> >> + u32 crc = 0;
> >> + u32 i;
> >> +
> >> + for (i = 0; i < nb_words - 1; i++)
> >> + crc ^= *(msg + i);
> >> +
> >> + return crc;
> >> +}
> >> +
> >> +int imx_ele_msg_rcv(struct se_if_priv *priv)
> >> +{
> >> + u32 wait;
> >> + int err;
> >> +
> >> + wait = msecs_to_jiffies(1000);
> >> + if (!wait_for_completion_timeout(&priv->done, wait)) {
> >> + dev_err(priv->dev,
> >> + "Error: wait_for_completion timed out.\n");
> >> + err = -ETIMEDOUT;
> >> + }
> >> +
> >> + mutex_unlock(&priv->se_if_cmd_lock);
> >> + priv->no_dev_ctx_used = false;
> >> +
> >> + return err;
> >> +}
> >> +
> >> +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg)
> >> +{
> >> + bool is_cmd_lock_tobe_taken = false;
> >> + int err;
> >> +
> >> + if (!priv->waiting_rsp_dev || priv->no_dev_ctx_used) {
> >> + is_cmd_lock_tobe_taken = true;
> >> + mutex_lock(&priv->se_if_cmd_lock);
> >> + }
> >> + scoped_guard(mutex, &priv->se_if_lock);
> >> +
> >> + err = mbox_send_message(priv->tx_chan, mssg);
> >> + if (err < 0) {
> >> + dev_err(priv->dev, "Error: mbox_send_message failure.\n");
> >> + if (is_cmd_lock_tobe_taken)
> >> + mutex_unlock(&priv->se_if_cmd_lock);
> >> + return err;
> >> + }
> >> + err = 0;
> >> +
> >> + return err;
> >> +}
> >> +
> >> +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg)
> >> +{
> >> + int err;
> >> +
> >> + priv->no_dev_ctx_used = true;
> >> + err = imx_ele_msg_send(priv, mssg);
> >> + if (err)
> >> + goto exit;
> >> +
> >> + err = imx_ele_msg_rcv(priv);
> >> +
> >> +exit:
> >> + return err;
> >> +}
> >> +
> >> +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *dev_ctx)
> >> +{
> >> + struct se_msg_hdr header = {0};
> >> + int err;
> >> +
> >> + err = wait_event_interruptible(dev_ctx->wq, dev_ctx->pending_hdr !=
> 0);
> >> + if (err)
> >> + dev_err(dev_ctx->dev,
> >> + "%s: Err[0x%x]:Interrupted by signal.\n",
> >> + dev_ctx->miscdev.name, err);
> >> +
> >> + header = *((struct se_msg_hdr *) (&dev_ctx->temp_resp[0]));
> >> +
> >> + if (header.tag == dev_ctx->priv->rsp_tag)
> >> + mutex_unlock(&dev_ctx->priv->se_if_cmd_lock);
> >> +
> >> + return err;
> >> +}
> >> +
> >> +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
> >> + void *tx_msg, int tx_msg_sz)
> >> +{
> >> + struct se_if_priv *priv = dev_ctx->priv;
> >> + struct se_msg_hdr header = {0};
> >> + int err;
> >> +
> >> + header = *((struct se_msg_hdr *) tx_msg);
> >> +
> >> + /*
> >> + * Check that the size passed as argument matches the size
> >> + * carried in the message.
> >> + */
> >> + err = header.size << 2;
> >> +
> >> + if (err != tx_msg_sz) {
> >> + err = -EINVAL;
> >> + dev_err(priv->dev,
> >> + "%s: User buffer too small\n",
> >> + dev_ctx->miscdev.name);
> >> + goto exit;
> >> + }
> >> + /* Check the message is valid according to tags */
> >> + if (header.tag == priv->cmd_tag)
> >> + priv->waiting_rsp_dev = dev_ctx;
> >> + else if (header.tag == priv->rsp_tag) {
> >> + /* Check the device context can send the command */
> >> + if (dev_ctx != priv->cmd_receiver_dev) {
> >> + dev_err(priv->dev,
> >> + "%s: Channel not configured to send resp to FW.",
> >> + dev_ctx->miscdev.name);
> >> + err = -EPERM;
> >> + goto exit;
> >> + }
> >> + } else {
> >> + dev_err(priv->dev,
> >> + "%s: The message does not have a valid TAG\n",
> >> + dev_ctx->miscdev.name);
> >> + err = -EINVAL;
> >> + goto exit;
> >> + }
> >> + err = imx_ele_msg_send(priv, tx_msg);
> >> +exit:
> >> + return err;
> >> +}
> >> +
> >> +/*
> >> + * Callback called by mailbox FW, when data is received.
> >> + */
> >> +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg)
> >> +{
> >> + struct device *dev = mbox_cl->dev;
> >> + struct se_if_device_ctx *dev_ctx;
> >> + struct se_api_msg *rx_msg;
> >> + bool is_response = false;
> >> + struct se_if_priv *priv;
> >> + struct se_msg_hdr header;
> >> +
> >> + priv = dev_get_drvdata(dev);
> >> + if (!priv) {
> >> + dev_err(dev, "SE-MU Priv data is NULL;");
> >> + return;
> >> + }
> >> +
> >> + /* The function can be called with NULL msg */
> >> + if (!msg) {
> >> + dev_err(dev, "Message is invalid\n");
> >> + return;
> >> + }
> >> +
> >> + header.tag = ((u8 *)msg)[TAG_OFFSET];
> >> + header.command = ((u8 *)msg)[CMD_OFFSET];
> >> + header.size = ((u8 *)msg)[SZ_OFFSET];
> >> + header.ver = ((u8 *)msg)[VER_OFFSET];
> >> +
> >> + /* Incoming command: wake up the receiver if any. */
> >> + if (header.tag == priv->cmd_tag) {
> >> + dev_dbg(dev, "Selecting cmd receiver\n");
> >> + dev_ctx = priv->cmd_receiver_dev;
> >> + } else if (header.tag == priv->rsp_tag) {
> >> + if (priv->waiting_rsp_dev) {
> >> + dev_dbg(dev, "Selecting rsp waiter\n");
> >> + dev_ctx = priv->waiting_rsp_dev;
> >> + is_response = true;
> >> + } else {
> >> + /*
> >> + * Reading the EdgeLock Enclave response
> >> + * to the command, sent by other
> >> + * linux kernel services.
> >> + */
> >> + spin_lock(&priv->lock);
> >> + memcpy(&priv->rx_msg, msg, header.size << 2);
> >> +
> >> + complete(&priv->done);
> >> + spin_unlock(&priv->lock);
> >> + return;
> >> + }
> >> + } else {
> >> + dev_err(dev, "Failed to select a device for message: %.8x\n",
> >> + *((u32 *) &header));
> >> + return;
> >> + }
> >> + /* Init reception */
> >> + rx_msg = kzalloc(header.size << 2, GFP_KERNEL);
> >> + if (rx_msg)
> >> + memcpy(rx_msg, msg, header.size << 2);
> >> +
> >> + dev_ctx->temp_resp = (u32 *)rx_msg;
> >> + dev_ctx->temp_resp_size = header.size;
> >> +
> >> + /* Allow user to read */
> >> + dev_ctx->pending_hdr = 1;
> >> + wake_up_interruptible(&dev_ctx->wq);
> >> +
> >> + if (is_response)
> >> + priv->waiting_rsp_dev = NULL;
> >> +}
> >> +
> >> +int validate_rsp_hdr(struct se_if_priv *priv, u32 header,
> >> + uint8_t msg_id, uint8_t sz, bool is_base_api)
> >> +{
> >> + int ret = -EINVAL;
> >> + u32 size;
> >> + u32 cmd;
> >> + u32 tag;
> >> + u32 ver;
> >> +
> >> + tag = MSG_TAG(header);
> >> + cmd = MSG_COMMAND(header);
> >> + size = MSG_SIZE(header);
> >> + ver = MSG_VER(header);
> >> +
> >> + do {
> >> + if (tag != priv->rsp_tag) {
> >> + dev_err(priv->dev,
> >> + "MSG[0x%x] Hdr: Resp tag mismatch. (0x%x != 0x%x)",
> >> + msg_id, tag, priv->rsp_tag);
> >> + break;
> >> + }
> >> +
> >> + if (cmd != msg_id) {
> >> + dev_err(priv->dev,
> >> + "MSG Header: Cmd id mismatch. (0x%x != 0x%x)",
> >> + cmd, msg_id);
> >> + break;
> >> + }
> >> +
> >> + if (size != (sz >> 2)) {
> >> + dev_err(priv->dev,
> >> + "MSG[0x%x] Hdr: Cmd size mismatch. (0x%x != 0x%x)",
> >> + msg_id, size, (sz >> 2));
> >> + break;
> >> + }
> >> +
> >> + if (is_base_api && (ver != priv->base_api_ver)) {
> >> + dev_err(priv->dev,
> >> + "MSG[0x%x] Hdr: Base API Vers mismatch. (0x%x !=
> 0x%x)",
> >> + msg_id, ver, priv->base_api_ver);
> >> + break;
> >> + } else if (!is_base_api && ver != priv->fw_api_ver) {
> >> + dev_err(priv->dev,
> >> + "MSG[0x%x] Hdr: FW API Vers mismatch. (0x%x != 0x%x)",
> >> + msg_id, ver, priv->fw_api_ver);
> >> + break;
> >> + }
> >> +
> >> + ret = 0;
> >> +
> >> + } while (false);
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +int se_save_imem_state(struct device *dev)
> >> +{
> >> + struct se_if_priv *priv = dev_get_drvdata(dev);
> >> + int ret;
> >> +
> >> + /* EXPORT command will save encrypted IMEM to given address,
> >> + * so later in resume, IMEM can be restored from the given
> >> + * address.
> >> + *
> >> + * Size must be at least 64 kB.
> >> + */
> >> + ret = ele_service_swap(dev,
> >> + priv->imem.phyaddr,
> >> + ELE_IMEM_SIZE,
> >> + ELE_IMEM_EXPORT);
> >> + if (ret < 0)
> >> + dev_err(dev, "Failed to export IMEM\n");
> >> + else
> >> + dev_info(dev,
> >> + "Exported %d bytes of encrypted IMEM\n",
> >> + ret);
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +int se_restore_imem_state(struct device *dev)
> >> +{
> >> + struct se_if_priv *priv = dev_get_drvdata(dev);
> >> + struct soc_info s_info;
> >> + int ret;
> >> +
> >> + /* get info from ELE */
> >> + ret = ele_get_info(dev, &s_info);
> >> + if (ret) {
> >> + dev_err(dev, "Failed to get info from ELE.\n");
> >> + return ret;
> >> + }
> >> +
> >> + /* Get IMEM state, if 0xFE then import IMEM */
> >> + if (s_info.imem_state == ELE_IMEM_STATE_BAD) {
> >> + /* IMPORT command will restore IMEM from the given
> >> + * address, here size is the actual size returned by ELE
> >> + * during the export operation
> >> + */
> >> + ret = ele_service_swap(dev,
> >> + priv->imem.phyaddr,
> >> + priv->imem.size,
> >> + ELE_IMEM_IMPORT);
> >> + if (ret) {
> >> + dev_err(dev, "Failed to import IMEM\n");
> >> + goto exit;
> >> + }
> >> + } else
> >> + goto exit;
> >> +
> >> + /* After importing IMEM, check if IMEM state is equal to 0xCA
> >> + * to ensure IMEM is fully loaded and
> >> + * ELE functionality can be used.
> >> + */
> >> + ret = ele_get_info(dev, &s_info);
> >> + if (ret) {
> >> + dev_err(dev, "Failed to get info from ELE.\n");
> >> + goto exit;
> >> + }
> >> +
> >> + if (s_info.imem_state == ELE_IMEM_STATE_OK)
> >> + dev_info(dev, "Successfully restored IMEM\n");
> >> + else
> >> + dev_err(dev, "Failed to restore IMEM\n");
> >> +
> >> +exit:
> >> + return ret;
> >> +}
> >> diff --git a/drivers/firmware/imx/ele_common.h
> b/drivers/firmware/imx/ele_common.h
> >> new file mode 100644
> >> index 000000000000..6e3a2114bb56
> >> --- /dev/null
> >> +++ b/drivers/firmware/imx/ele_common.h
> >> @@ -0,0 +1,43 @@
> >> +/* SPDX-License-Identifier: GPL-2.0+ */
> >> +/*
> >> + * Copyright 2024 NXP
> >> + */
> >> +
> >> +
> >> +#ifndef __ELE_COMMON_H__
> >> +#define __ELE_COMMON_H__
> >> +
> >> +#include "se_ctrl.h"
> >> +
> >> +#define IMX_ELE_FW_DIR "imx/ele/"
> >> +
> >> +uint32_t plat_add_msg_crc(uint32_t *msg, uint32_t msg_len);
> >> +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *priv);
> >> +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
> >> + void *tx_msg, int tx_msg_sz);
> >> +int imx_ele_msg_rcv(struct se_if_priv *priv);
> >> +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg);
> >> +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg);
> >> +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg);
> >> +int validate_rsp_hdr(struct se_if_priv *priv, unsigned int header,
> >> + u8 msg_id, u8 sz, bool is_base_api);
> >> +
> >> +/* Fill a command message header with a given command ID and length
> in bytes. */
> >> +static inline int plat_fill_cmd_msg_hdr(struct se_if_priv *priv,
> >> + struct se_msg_hdr *hdr,
> >> + u8 cmd,
> >> + u32 len,
> >> + bool is_base_api)
> >> +{
> >> + hdr->tag = priv->cmd_tag;
> >> + hdr->ver = (is_base_api) ? priv->base_api_ver : priv->fw_api_ver;
> >> + hdr->command = cmd;
> >> + hdr->size = len >> 2;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +int se_save_imem_state(struct device *dev);
> >> +int se_restore_imem_state(struct device *dev);
> >> +
> >> +#endif /*__ELE_COMMON_H__ */
> >> diff --git a/drivers/firmware/imx/se_ctrl.c
> b/drivers/firmware/imx/se_ctrl.c
> >> new file mode 100644
> >> index 000000000000..11c5eaa7353f
> >> --- /dev/null
> >> +++ b/drivers/firmware/imx/se_ctrl.c
> >> @@ -0,0 +1,1339 @@
> >> +// SPDX-License-Identifier: GPL-2.0+
> >> +/*
> >> + * Copyright 2024 NXP
> >> + */
> >> +
> >> +#include <linux/completion.h>
> >> +#include <linux/delay.h>
> >> +#include <linux/dev_printk.h>
> >> +#include <linux/dma-mapping.h>
> >> +#include <linux/errno.h>
> >> +#include <linux/export.h>
> >> +#include <linux/firmware.h>
> >> +#include <linux/firmware/imx/se_api.h>
> >> +#include <linux/genalloc.h>
> >> +#include <linux/init.h>
> >> +#include <linux/io.h>
> >> +#include <linux/miscdevice.h>
> >> +#include <linux/mod_devicetable.h>
> >> +#include <linux/module.h>
> >> +#include <linux/of_platform.h>
> >> +#include <linux/of_reserved_mem.h>
> >> +#include <linux/platform_device.h>
> >> +#include <linux/slab.h>
> >> +#include <linux/string.h>
> >> +#include <linux/sys_soc.h>
> >> +#include <uapi/linux/se_ioctl.h>
> >> +
> >> +#include "ele_base_msg.h"
> >> +#include "ele_common.h"
> >> +#include "se_ctrl.h"
> >> +
> >> +#define RESERVED_DMA_POOL BIT(1)
> >> +
> >> +struct imx_se_node_info {
> >> + u8 se_if_id;
> >> + u8 se_if_did;
> >> + u8 max_dev_ctx;
> >> + u8 cmd_tag;
> >> + u8 rsp_tag;
> >> + u8 success_tag;
> >> + u8 base_api_ver;
> >> + u8 fw_api_ver;
> >> + u8 *se_name;
> >> + u8 *mbox_tx_name;
> >> + u8 *mbox_rx_name;
> >> + u8 *pool_name;
> >> + u8 *fw_name_in_rfs;
> >> + bool soc_register;
> >> + bool reserved_dma_ranges;
> >> + bool imem_mgmt;
> >> +};
> >> +
> >> +struct imx_se_node_info_list {
> >> + u8 num_mu;
> >> + u16 soc_id;
> >> + u16 soc_rev;
> >> + struct imx_se_node_info info[];
> >> +};
> >> +
> >> +static const struct imx_se_node_info_list imx8ulp_info = {
> >> + .num_mu = 1,
> >> + .soc_id = SOC_ID_OF_IMX8ULP,
> >> + .info = {
> >> + {
> >> + .se_if_id = 2,
> >> + .se_if_did = 7,
> >> + .max_dev_ctx = 4,
> >> + .cmd_tag = 0x17,
> >> + .rsp_tag = 0xe1,
> >> + .success_tag = 0xd6,
> >> + .base_api_ver = MESSAGING_VERSION_6,
> >> + .fw_api_ver = MESSAGING_VERSION_7,
> >> + .se_name = "hsm1",
> >> + .mbox_tx_name = "tx",
> >> + .mbox_rx_name = "rx",
> >> + .pool_name = "sram",
> >> + .fw_name_in_rfs = IMX_ELE_FW_DIR\
> >> + "mx8ulpa2ext-ahab-container.img",
> >> + .soc_register = true,
> >> + .reserved_dma_ranges = true,
> >> + .imem_mgmt = true,
> >> + },
> >> + },
> >> +};
> >> +
> >> +static const struct imx_se_node_info_list imx93_info = {
> >> + .num_mu = 1,
> >> + .soc_id = SOC_ID_OF_IMX93,
> >> + .info = {
> >> + {
> >> + .se_if_id = 2,
> >> + .se_if_did = 3,
> >> + .max_dev_ctx = 4,
> >> + .cmd_tag = 0x17,
> >> + .rsp_tag = 0xe1,
> >> + .success_tag = 0xd6,
> >> + .base_api_ver = MESSAGING_VERSION_6,
> >> + .fw_api_ver = MESSAGING_VERSION_7,
> >> + .se_name = "hsm1",
> >> + .mbox_tx_name = "tx",
> >> + .mbox_rx_name = "rx",
> >> + .reserved_dma_ranges = true,
> >> + .imem_mgmt = true,
> >> + .soc_register = true,
> >> + },
> >> + },
> >> +};
> >> +
> >> +static const struct of_device_id se_match[] = {
> >> + { .compatible = "fsl,imx8ulp-ele", .data = (void *)&imx8ulp_info},
> >> + { .compatible = "fsl,imx93-ele", .data = (void *)&imx93_info},
> >> + {},
> >> +};
> >> +
> >> +static struct imx_se_node_info
> >> + *get_imx_se_node_info(struct imx_se_node_info_list *info_list,
> >> + const u32 idx)
> >> +{
> >> + if (idx < 0 || idx > info_list->num_mu)
> >> + return NULL;
> >> +
> >> + return &info_list->info[idx];
> >> +}
> >> +
> >> +void *get_phy_buf_mem_pool(struct device *dev,
> >> + u8 *mem_pool_name,
> >> + dma_addr_t *buf,
> >> + u32 size)
> >> +{
> >> + struct device_node *of_node = dev->of_node;
> >> + struct gen_pool *mem_pool;
> >> +
> >> + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> >> + if (!mem_pool) {
> >> + dev_err(dev,
> >> + "Unable to get sram pool = %s\n",
> >> + mem_pool_name);
> >> + return 0;
> >> + }
> >> +
> >> + return gen_pool_dma_alloc(mem_pool, size, buf);
> >> +}
> >> +
> >> +void free_phybuf_mem_pool(struct device *dev,
> >> + u8 *mem_pool_name,
> >> + u32 *buf,
> >> + u32 size)
> >> +{
> >> + struct device_node *of_node = dev->of_node;
> >> + struct gen_pool *mem_pool;
> >> +
> >> + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> >> + if (!mem_pool)
> >> + dev_err(dev,
> >> + "%s: Failed: Unable to get sram pool.\n",
> >> + __func__);
> >> +
> >> + gen_pool_free(mem_pool, (u64)buf, size);
> >> +}
> >> +
> >> +static int imx_fetch_soc_info(struct device *dev)
> >> +{
> >> + struct se_if_priv *priv = dev_get_drvdata(dev);
> >> + struct imx_se_node_info_list *info_list;
> >> + const struct imx_se_node_info *info;
> >> + struct soc_device_attribute *attr;
> >> + struct soc_device *sdev;
> >> + struct soc_info s_info;
> >> + int err = 0;
> >> +
> >> + info = priv->info;
> >> + info_list = (struct imx_se_node_info_list *)
> >> + device_get_match_data(dev->parent);
> >> + if (info_list->soc_rev)
> >> + return err;
> >> +
> >> + err = ele_get_info(dev, &s_info);
> >> + if (err)
> >> + s_info.major_ver = DEFAULT_IMX_SOC_VER;
> >> +
> >> + info_list->soc_rev = s_info.soc_rev;
> >> +
> >> + if (!info->soc_register)
> >> + return 0;
> >> +
> >> + attr = devm_kzalloc(dev, sizeof(*attr), GFP_KERNEL);
> >> + if (!attr)
> >> + return -ENOMEM;
> >> +
> >> + if (s_info.minor_ver)
> >> + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x.%x",
> >> + s_info.major_ver,
> >> + s_info.minor_ver);
> >> + else
> >> + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x",
> >> + s_info.major_ver);
> >> +
> >> + switch (s_info.soc_id) {
> >> + case SOC_ID_OF_IMX8ULP:
> >> + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> >> + "i.MX8ULP");
> >> + break;
> >> + case SOC_ID_OF_IMX93:
> >> + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> >> + "i.MX93");
> >> + break;
> >> + }
> >> +
> >> + err = of_property_read_string(of_root, "model",
> >> + &attr->machine);
> >> + if (err) {
> >> + devm_kfree(dev, attr);
> >> + return -EINVAL;
> >> + }
> >> + attr->family = devm_kasprintf(dev, GFP_KERNEL, "Freescale i.MX");
> >> +
> >> + attr->serial_number
> >> + = devm_kasprintf(dev, GFP_KERNEL, "%016llX", s_info.serial_num);
> >> +
> >> + sdev = soc_device_register(attr);
> >> + if (IS_ERR(sdev)) {
> >> + devm_kfree(dev, attr->soc_id);
> >> + devm_kfree(dev, attr->serial_number);
> >> + devm_kfree(dev, attr->revision);
> >> + devm_kfree(dev, attr->family);
> >> + devm_kfree(dev, attr->machine);
> >> + devm_kfree(dev, attr);
> >> + return PTR_ERR(sdev);
> >> + }
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +/*
> >> + * File operations for user-space
> >> + */
> >> +
> >> +/* Write a message to the MU. */
> >> +static ssize_t se_if_fops_write(struct file *fp, const char __user *buf,
> >> + size_t size, loff_t *ppos)
> >> +{
> >> + struct se_api_msg *tx_msg __free(kfree);
> >> + struct se_if_device_ctx *dev_ctx;
> >> + struct se_if_priv *priv;
> >> + int err;
> >> +
> >> + dev_ctx = container_of(fp->private_data,
> >> + struct se_if_device_ctx,
> >> + miscdev);
> >> + priv = dev_ctx->priv;
> >> + dev_dbg(priv->dev,
> >> + "%s: write from buf (%p)%zu, ppos=%lld\n",
> >> + dev_ctx->miscdev.name,
> >> + buf, size, ((ppos) ? *ppos : 0));
> >> +
> >> + if (down_interruptible(&dev_ctx->fops_lock))
> >> + return -EBUSY;
> >> +
> >> + if (dev_ctx->status != MU_OPENED) {
> >> + err = -EINVAL;
> >> + goto exit;
> >> + }
> >> +
> >> + if (size < SE_MU_HDR_SZ) {
> >> + dev_err(priv->dev,
> >> + "%s: User buffer too small(%zu < %d)\n",
> >> + dev_ctx->miscdev.name,
> >> + size, SE_MU_HDR_SZ);
> >> + err = -ENOSPC;
> >> + goto exit;
> >> + }
> >> +
> >> + tx_msg = memdup_user((void __user *)ppos, size);
> >> + if (!tx_msg) {
> >> + err = -ENOMEM;
> >> + goto exit;
> >> + }
> >> +
> >> + /* Copy data to buffer */
> >> + if (copy_from_user(tx_msg, buf, size)) {
> >> + err = -EFAULT;
> >> + dev_err(priv->dev,
> >> + "%s: Fail copy message from user\n",
> >> + dev_ctx->miscdev.name);
> >> + goto exit;
> >> + }
> >> +
> >> + print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4,
> >> + tx_msg, size, false);
> >> +
> >> + err = imx_ele_miscdev_msg_send(dev_ctx, tx_msg, size);
> >> +
> >> +exit:
> >> + up(&dev_ctx->fops_lock);
> >> + return err;
> >> +}
> >> +
> >> +/*
> >> + * Read a message from the MU.
> >> + * Blocking until a message is available.
> >> + */
> >> +static ssize_t se_if_fops_read(struct file *fp, char __user *buf,
> >> + size_t size, loff_t *ppos)
> >> +{
> >> + struct se_if_device_ctx *dev_ctx;
> >> + struct se_buf_desc *b_desc;
> >> + struct se_if_priv *priv;
> >> + u32 size_to_copy;
> >> + int err;
> >> +
> >> + dev_ctx = container_of(fp->private_data,
> >> + struct se_if_device_ctx,
> >> + miscdev);
> >> + priv = dev_ctx->priv;
> >> + dev_dbg(priv->dev,
> >> + "%s: read to buf %p(%zu), ppos=%lld\n",
> >> + dev_ctx->miscdev.name,
> >> + buf, size, ((ppos) ? *ppos : 0));
> >> +
> >> + if (down_interruptible(&dev_ctx->fops_lock))
> >> + return -EBUSY;
> >> +
> >> + if (dev_ctx->status != MU_OPENED) {
> >> + err = -EINVAL;
> >> + goto exit;
> >> + }
> >> +
> >> + err = imx_ele_miscdev_msg_rcv(dev_ctx);
> >> + if (err)
> >> + goto exit;
> >> +
> >> + /* Buffer containing the message from FW, is
> >> + * allocated in callback function.
> >> + * Check if buffer allocation failed.
> >> + */
> >> + if (!dev_ctx->temp_resp) {
> >> + err = -ENOMEM;
> >> + goto exit;
> >> + }
> >> +
> >> + dev_dbg(priv->dev,
> >> + "%s: %s %s\n",
> >> + dev_ctx->miscdev.name,
> >> + __func__,
> >> + "message received, start transmit to user");
> >> +
> >> + /*
> >> + * Check that the size passed as argument is larger than
> >> + * the one carried in the message.
> >> + */
> >> + size_to_copy = dev_ctx->temp_resp_size << 2;
> >> + if (size_to_copy > size) {
> >> + dev_dbg(priv->dev,
> >> + "%s: User buffer too small (%zu < %d)\n",
> >> + dev_ctx->miscdev.name,
> >> + size, size_to_copy);
> >> + size_to_copy = size;
> >> + }
> >> +
> >> + /*
> >> + * We may need to copy the output data to user before
> >> + * delivering the completion message.
> >> + */
> >> + while (!list_empty(&dev_ctx->pending_out)) {
> >> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> >> + struct se_buf_desc,
> >> + link);
> >> + if (!b_desc)
> >> + continue;
> >> +
> >> + if (b_desc->usr_buf_ptr && b_desc->shared_buf_ptr) {
> >> +
> >> + dev_dbg(priv->dev,
> >> + "%s: Copy output data to user\n",
> >> + dev_ctx->miscdev.name);
> >> + if (copy_to_user(b_desc->usr_buf_ptr,
> >> + b_desc->shared_buf_ptr,
> >> + b_desc->size)) {
> >> + dev_err(priv->dev,
> >> + "%s: Failure copying output data to user.",
> >> + dev_ctx->miscdev.name);
> >> + err = -EFAULT;
> >> + goto exit;
> >> + }
> >> + }
> >> +
> >> + if (b_desc->shared_buf_ptr)
> >> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> >> +
> >> + __list_del_entry(&b_desc->link);
> >> + kfree(b_desc);
> >> + }
> >> +
> >> + /* Copy data from the buffer */
> >> + print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4,
> >> + dev_ctx->temp_resp, size_to_copy, false);
> >> + if (copy_to_user(buf, dev_ctx->temp_resp, size_to_copy)) {
> >> + dev_err(priv->dev,
> >> + "%s: Failed to copy to user\n",
> >> + dev_ctx->miscdev.name);
> >> + err = -EFAULT;
> >> + goto exit;
> >> + }
> >> +
> >> + err = size_to_copy;
> >> + kfree(dev_ctx->temp_resp);
> >> +
> >> + /* free memory allocated on the shared buffers. */
> >> + dev_ctx->secure_mem.pos = 0;
> >> + dev_ctx->non_secure_mem.pos = 0;
> >> +
> >> + dev_ctx->pending_hdr = 0;
> >> +
> >> +exit:
> >> + /*
> >> + * Clean the used Shared Memory space,
> >> + * whether its Input Data copied from user buffers, or
> >> + * Data received from FW.
> >> + */
> >> + while (!list_empty(&dev_ctx->pending_in) ||
> >> + !list_empty(&dev_ctx->pending_out)) {
> >> + if (!list_empty(&dev_ctx->pending_in))
> >> + b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
> >> + struct se_buf_desc,
> >> + link);
> >> + else
> >> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> >> + struct se_buf_desc,
> >> + link);
> >> +
> >> + if (!b_desc)
> >> + continue;
> >> +
> >> + if (b_desc->shared_buf_ptr)
> >> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> >> +
> >> + __list_del_entry(&b_desc->link);
> >> + kfree(b_desc);
> >> + }
> >> +
> >> + up(&dev_ctx->fops_lock);
> >> + return err;
> >> +}
> >> +
> >> +/* Give access to EdgeLock Enclave, to the memory we want to share */
> >> +static int se_if_setup_se_mem_access(struct se_if_device_ctx *dev_ctx,
> >> + u64 addr, u32 len)
> >> +{
> >> + /* Assuming EdgeLock Enclave has access to all the memory regions */
> >> + int ret = 0;
> >> +
> >> + if (ret) {
> >> + dev_err(dev_ctx->priv->dev,
> >> + "%s: Fail find memreg\n", dev_ctx->miscdev.name);
> >> + goto exit;
> >> + }
> >> +
> >> + if (ret) {
> >> + dev_err(dev_ctx->priv->dev,
> >> + "%s: Fail set permission for resource\n",
> >> + dev_ctx->miscdev.name);
> >> + goto exit;
> >> + }
> >> +
> >> +exit:
> >> + return ret;
> >> +}
> >> +
> >> +static int se_ioctl_get_mu_info(struct se_if_device_ctx *dev_ctx,
> >> + u64 arg)
> >> +{
> >> + struct se_if_priv *priv = dev_get_drvdata(dev_ctx->dev);
> >> + struct imx_se_node_info *if_node_info;
> >> + struct se_ioctl_get_if_info info;
> >> + int err = 0;
> >> +
> >> + if_node_info = (struct imx_se_node_info *)priv->info;
> >> +
> >> + info.se_if_id = if_node_info->se_if_id;
> >> + info.interrupt_idx = 0;
> >> + info.tz = 0;
> >> + info.did = if_node_info->se_if_did;
> >> + info.cmd_tag = if_node_info->cmd_tag;
> >> + info.rsp_tag = if_node_info->rsp_tag;
> >> + info.success_tag = if_node_info->success_tag;
> >> + info.base_api_ver = if_node_info->base_api_ver;
> >> + info.fw_api_ver = if_node_info->fw_api_ver;
> >> +
> >> + dev_dbg(priv->dev,
> >> + "%s: info [se_if_id: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n",
> >> + dev_ctx->miscdev.name,
> >> + info.se_if_id, info.interrupt_idx, info.tz, info.did);
> >> +
> >> + if (copy_to_user((u8 *)arg, &info, sizeof(info))) {
> >> + dev_err(dev_ctx->priv->dev,
> >> + "%s: Failed to copy mu info to user\n",
> >> + dev_ctx->miscdev.name);
> >> + err = -EFAULT;
> >> + goto exit;
> >> + }
> >> +
> >> +exit:
> >> + return err;
> >> +}
> >> +
> >> +/*
> >> + * Copy a buffer of data to/from the user and return the address to use in
> >> + * messages
> >> + */
> >> +static int se_ioctl_setup_iobuf_handler(struct se_if_device_ctx *dev_ctx,
> >> + u64 arg)
> >> +{
> >> + struct se_ioctl_setup_iobuf io = {0};
> >> + struct se_shared_mem *shared_mem;
> >> + struct se_buf_desc *b_desc;
> >> + int err = 0;
> >> + u32 pos;
> >> +
> >> + if (copy_from_user(&io, (u8 *)arg, sizeof(io))) {
> >> + dev_err(dev_ctx->priv->dev,
> >> + "%s: Failed copy iobuf config from user\n",
> >> + dev_ctx->miscdev.name);
> >> + err = -EFAULT;
> >> + goto exit;
> >> + }
> >> +
> >> + dev_dbg(dev_ctx->priv->dev,
> >> + "%s: io [buf: %p(%d) flag: %x]\n",
> >> + dev_ctx->miscdev.name,
> >> + io.user_buf, io.length, io.flags);
> >> +
> >> + if (io.length == 0 || !io.user_buf) {
> >> + /*
> >> + * Accept NULL pointers since some buffers are optional
> >> + * in FW commands. In this case we should return 0 as
> >> + * pointer to be embedded into the message.
> >> + * Skip all data copy part of code below.
> >> + */
> >> + io.ele_addr = 0;
> >> + goto copy;
> >> + }
> >> +
> >> + /* Select the shared memory to be used for this buffer. */
> >> + if (io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) {
> >> + /* App requires to use secure memory for this buffer.*/
> >> + dev_err(dev_ctx->priv->dev,
> >> + "%s: Failed allocate SEC MEM memory\n",
> >> + dev_ctx->miscdev.name);
> >> + err = -EFAULT;
> >> + goto exit;
> >> + } else {
> >> + /* No specific requirement for this buffer. */
> >> + shared_mem = &dev_ctx->non_secure_mem;
> >> + }
> >> +
> >> + /* Check there is enough space in the shared memory. */
> >> + if (shared_mem->size < shared_mem->pos
> >> + || io.length >= shared_mem->size - shared_mem->pos) {
> >> + dev_err(dev_ctx->priv->dev,
> >> + "%s: Not enough space in shared memory\n",
> >> + dev_ctx->miscdev.name);
> >> + err = -ENOMEM;
> >> + goto exit;
> >> + }
> >> +
> >> + /* Allocate space in shared memory. 8 bytes aligned. */
> >> + pos = shared_mem->pos;
> >> + shared_mem->pos += round_up(io.length, 8u);
> >> + io.ele_addr = (u64)shared_mem->dma_addr + pos;
> >> +
> >> + if ((io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) &&
> >> + !(io.flags & SE_MU_IO_FLAGS_USE_SHORT_ADDR)) {
> >> + /*Add base address to get full address.*/
> >> + dev_err(dev_ctx->priv->dev,
> >> + "%s: Failed allocate SEC MEM memory\n",
> >> + dev_ctx->miscdev.name);
> >> + err = -EFAULT;
> >> + goto exit;
> >> + }
> >> +
> >> + memset(shared_mem->ptr + pos, 0, io.length);
> >> + if ((io.flags & SE_IO_BUF_FLAGS_IS_INPUT) ||
> >> + (io.flags & SE_IO_BUF_FLAGS_IS_IN_OUT)) {
> >> + /*
> >> + * buffer is input:
> >> + * copy data from user space to this allocated buffer.
> >> + */
> >> + if (copy_from_user(shared_mem->ptr + pos, io.user_buf,
> >> + io.length)) {
> >> + dev_err(dev_ctx->priv->dev,
> >> + "%s: Failed copy data to shared memory\n",
> >> + dev_ctx->miscdev.name);
> >> + err = -EFAULT;
> >> + goto exit;
> >> + }
> >> + }
> >> +
> >> + b_desc = kzalloc(sizeof(*b_desc), GFP_KERNEL);
> >> + if (!b_desc) {
> >> + err = -ENOMEM;
> >> + goto exit;
> >> + }
> >> +
> >> +copy:
> >> + /* Provide the EdgeLock Enclave address to user space only if
> success.*/
> >> + if (copy_to_user((u8 *)arg, &io, sizeof(io))) {
> >> + dev_err(dev_ctx->priv->dev,
> >> + "%s: Failed to copy iobuff setup to user\n",
> >> + dev_ctx->miscdev.name);
> >> + kfree(b_desc);
> >> + err = -EFAULT;
> >> + goto exit;
> >> + }
> >> +
> >> + if (b_desc) {
> >> + b_desc->shared_buf_ptr = shared_mem->ptr + pos;
> >> + b_desc->usr_buf_ptr = io.user_buf;
> >> + b_desc->size = io.length;
> >> +
> >> + if (io.flags & SE_IO_BUF_FLAGS_IS_INPUT) {
> >> + /*
> >> + * buffer is input:
> >> + * add an entry in the "pending input buffers" list so
> >> + * that copied data can be cleaned from shared memory
> >> + * later.
> >> + */
> >> + list_add_tail(&b_desc->link, &dev_ctx->pending_in);
> >> + } else {
> >> + /*
> >> + * buffer is output:
> >> + * add an entry in the "pending out buffers" list so data
> >> + * can be copied to user space when receiving Secure-Enclave
> >> + * response.
> >> + */
> >> + list_add_tail(&b_desc->link, &dev_ctx->pending_out);
> >> + }
> >> + }
> >> +
> >> +exit:
> >> + return err;
> >> +}
> >> +
> >> +/* IOCTL to provide SoC information */
> >> +static int se_ioctl_get_soc_info_handler(struct se_if_device_ctx
> *dev_ctx,
> >> + u64 arg)
> >> +{
> >> + struct imx_se_node_info_list *info_list;
> >> + struct se_ioctl_get_soc_info soc_info;
> >> + int err = -EINVAL;
> >> +
> >> + info_list = (struct imx_se_node_info_list *)
> >> + device_get_match_data(dev_ctx->priv->dev->parent);
> >> + if (!info_list)
> >> + goto exit;
> >> +
> >> + soc_info.soc_id = info_list->soc_id;
> >> + soc_info.soc_rev = info_list->soc_rev;
> >> +
> >> + err = (int)copy_to_user((u8 *)arg, (u8 *)(&soc_info), sizeof(soc_info));
> >> + if (err) {
> >> + dev_err(dev_ctx->priv->dev,
> >> + "%s: Failed to copy soc info to user\n",
> >> + dev_ctx->miscdev.name);
> >> + err = -EFAULT;
> >> + goto exit;
> >> + }
> >> +
> >> +exit:
> >> + return err;
> >> +}
> >> +
> >> +/* Open a character device. */
> >> +static int se_if_fops_open(struct inode *nd, struct file *fp)
> >> +{
> >> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> >> + struct se_if_device_ctx,
> >> + miscdev);
> >> + int err;
> >> +
> >> + /* Avoid race if opened at the same time */
> >> + if (down_trylock(&dev_ctx->fops_lock))
> >> + return -EBUSY;
> >> +
> >> + /* Authorize only 1 instance. */
> >> + if (dev_ctx->status != MU_FREE) {
> >> + err = -EBUSY;
> >> + goto exit;
> >> + }
> >> +
> >> + /*
> >> + * Allocate some memory for data exchanges with S40x.
> >> + * This will be used for data not requiring secure memory.
> >> + */
> >> + dev_ctx->non_secure_mem.ptr = dmam_alloc_coherent(dev_ctx->dev,
> >> + MAX_DATA_SIZE_PER_USER,
> >> + &dev_ctx->non_secure_mem.dma_addr,
> >> + GFP_KERNEL);
> >> + if (!dev_ctx->non_secure_mem.ptr) {
> >> + err = -ENOMEM;
> >> + goto exit;
> >> + }
> >> +
> >> + err = se_if_setup_se_mem_access(dev_ctx,
> >> + dev_ctx->non_secure_mem.dma_addr,
> >> + MAX_DATA_SIZE_PER_USER);
> >> + if (err) {
> >> + err = -EPERM;
> >> + dev_err(dev_ctx->priv->dev,
> >> + "%s: Failed to share access to shared memory\n",
> >> + dev_ctx->miscdev.name);
> >> + goto free_coherent;
> >> + }
> >> +
> >> + dev_ctx->non_secure_mem.size = MAX_DATA_SIZE_PER_USER;
> >> + dev_ctx->non_secure_mem.pos = 0;
> >> + dev_ctx->status = MU_OPENED;
> >> +
> >> + dev_ctx->pending_hdr = 0;
> >> +
> >> + goto exit;
> >> +
> >> +free_coherent:
> >> + dmam_free_coherent(dev_ctx->priv->dev,
> MAX_DATA_SIZE_PER_USER,
> >> + dev_ctx->non_secure_mem.ptr,
> >> + dev_ctx->non_secure_mem.dma_addr);
> >> +
> >> +exit:
> >> + up(&dev_ctx->fops_lock);
> >> + return err;
> >> +}
> >> +
> >> +/* Close a character device. */
> >> +static int se_if_fops_close(struct inode *nd, struct file *fp)
> >> +{
> >> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> >> + struct se_if_device_ctx,
> >> + miscdev);
> >> + struct se_if_priv *priv = dev_ctx->priv;
> >> + struct se_buf_desc *b_desc;
> >> +
> >> + /* Avoid race if closed at the same time */
> >> + if (down_trylock(&dev_ctx->fops_lock))
> >> + return -EBUSY;
> >> +
> >> + /* The device context has not been opened */
> >> + if (dev_ctx->status != MU_OPENED)
> >> + goto exit;
> >> +
> >> + /* check if this device was registered as command receiver. */
> >> + if (priv->cmd_receiver_dev == dev_ctx)
> >> + priv->cmd_receiver_dev = NULL;
> >> +
> >> + /* check if this device was registered as waiting response. */
> >> + if (priv->waiting_rsp_dev == dev_ctx) {
> >> + priv->waiting_rsp_dev = NULL;
> >> + mutex_unlock(&priv->se_if_cmd_lock);
> >> + }
> >> +
> >> + /* Unmap secure memory shared buffer. */
> >> + if (dev_ctx->secure_mem.ptr)
> >> + devm_iounmap(dev_ctx->dev, dev_ctx->secure_mem.ptr);
> >> +
> >> + dev_ctx->secure_mem.ptr = NULL;
> >> + dev_ctx->secure_mem.dma_addr = 0;
> >> + dev_ctx->secure_mem.size = 0;
> >> + dev_ctx->secure_mem.pos = 0;
> >> +
> >> + /* Free non-secure shared buffer. */
> >> + dmam_free_coherent(dev_ctx->priv->dev,
> MAX_DATA_SIZE_PER_USER,
> >> + dev_ctx->non_secure_mem.ptr,
> >> + dev_ctx->non_secure_mem.dma_addr);
> >> +
> >> + dev_ctx->non_secure_mem.ptr = NULL;
> >> + dev_ctx->non_secure_mem.dma_addr = 0;
> >> + dev_ctx->non_secure_mem.size = 0;
> >> + dev_ctx->non_secure_mem.pos = 0;
> >> +
> >> + while (!list_empty(&dev_ctx->pending_in) ||
> >> + !list_empty(&dev_ctx->pending_out)) {
> >> + if (!list_empty(&dev_ctx->pending_in))
> >> + b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
> >> + struct se_buf_desc,
> >> + link);
> >> + else
> >> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> >> + struct se_buf_desc,
> >> + link);
> >> +
> >> + if (!b_desc)
> >> + continue;
> >> +
> >> + if (b_desc->shared_buf_ptr)
> >> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> >> +
> >> + __list_del_entry(&b_desc->link);
> >> + devm_kfree(dev_ctx->dev, b_desc);
> >> + }
> >> +
> >> + dev_ctx->status = MU_FREE;
> >> +
> >> +exit:
> >> + up(&dev_ctx->fops_lock);
> >> + return 0;
> >> +}
> >> +
> >> +/* IOCTL entry point of a character device */
> >> +static long se_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
> >> +//static long se_ioctl(struct file *fp, u32 cmd, u64 arg)
> >> +{
> >> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> >> + struct se_if_device_ctx,
> >> + miscdev);
> >> + struct se_if_priv *se_if_priv = dev_ctx->priv;
> >> + int err = -EINVAL;
> >> +
> >> + /* Prevent race during change of device context */
> >> + if (down_interruptible(&dev_ctx->fops_lock))
> >> + return -EBUSY;
> >> +
> >> + switch (cmd) {
> >> + case SE_IOCTL_ENABLE_CMD_RCV:
> >> + if (!se_if_priv->cmd_receiver_dev) {
> >> + se_if_priv->cmd_receiver_dev = dev_ctx;
> >> + err = 0;
> >> + }
> >> + break;
> >> + case SE_IOCTL_GET_MU_INFO:
> >> + err = se_ioctl_get_mu_info(dev_ctx, arg);
> >> + break;
> >> + case SE_IOCTL_SETUP_IOBUF:
> >> + err = se_ioctl_setup_iobuf_handler(dev_ctx, arg);
> >> + break;
> >> + case SE_IOCTL_GET_SOC_INFO:
> >> + err = se_ioctl_get_soc_info_handler(dev_ctx, arg);
> >> + break;
> >> +
> >> + default:
> >> + err = -EINVAL;
> >> + dev_dbg(se_if_priv->dev,
> >> + "%s: IOCTL %.8x not supported\n",
> >> + dev_ctx->miscdev.name,
> >> + cmd);
> >> + }
> >> +
> >> + up(&dev_ctx->fops_lock);
> >> + return (long)err;
> >> +}
> >> +
> >> +/* Char driver setup */
> >> +static const struct file_operations se_if_fops = {
> >> + .open = se_if_fops_open,
> >> + .owner = THIS_MODULE,
> >> + .release = se_if_fops_close,
> >> + .unlocked_ioctl = se_ioctl,
> >> + .read = se_if_fops_read,
> >> + .write = se_if_fops_write,
> >> +};
> >> +
> >> +/* interface for managed res to free a mailbox channel */
> >> +static void if_mbox_free_channel(void *mbox_chan)
> >> +{
> >> + mbox_free_channel(mbox_chan);
> >> +}
> >> +
> >> +/* interface for managed res to unregister a character device */
> >> +static void if_misc_deregister(void *miscdevice)
> >> +{
> >> + misc_deregister(miscdevice);
> >> +}
> >> +
> >> +static int se_if_request_channel(struct device *dev,
> >> + struct mbox_chan **chan,
> >> + struct mbox_client *cl,
> >> + const u8 *name)
> >> +{
> >> + struct mbox_chan *t_chan;
> >> + int ret = 0;
> >> +
> >> + t_chan = mbox_request_channel_byname(cl, name);
> >> + if (IS_ERR(t_chan)) {
> >> + ret = PTR_ERR(t_chan);
> >> + if (ret != -EPROBE_DEFER)
> >> + dev_err(dev,
> >> + "Failed to request chan %s ret %d\n", name,
> >> + ret);
> >> + goto exit;
> >> + }
> >> +
> >> + ret = devm_add_action(dev, if_mbox_free_channel, t_chan);
> >> + if (ret) {
> >> + dev_err(dev, "failed to add devm removal of mbox %s\n", name);
> >> + goto exit;
> >> + }
> >> +
> >> + *chan = t_chan;
> >> +
> >> +exit:
> >> + return ret;
> >> +}
> >> +
> >> +static int se_probe_if_cleanup(struct platform_device *pdev)
> >> +{
> >> + struct device *dev = &pdev->dev;
> >> + struct se_if_priv *priv;
> >> + int ret = 0;
> >> + int i;
> >> +
> >> + priv = dev_get_drvdata(dev);
> >> + if (!priv) {
> >> + ret = 0;
> >> + dev_dbg(dev, "SE-MU Priv data is NULL;");
> >> + return ret;
> >> + }
> >> +
> >> + if (priv->tx_chan)
> >> + mbox_free_channel(priv->tx_chan);
> >> + if (priv->rx_chan)
> >> + mbox_free_channel(priv->rx_chan);
> >> +
> >> + /* free the buffer in se remove, previously allocated
> >> + * in se probe to store encrypted IMEM
> >> + */
> >> + if (priv->imem.buf) {
> >> + dmam_free_coherent(dev,
> >> + ELE_IMEM_SIZE,
> >> + priv->imem.buf,
> >> + priv->imem.phyaddr);
> >> + priv->imem.buf = NULL;
> >> + }
> >> +
> >> + if (priv->ctxs) {
> >> + for (i = 0; i < priv->max_dev_ctx; i++) {
> >> + if (priv->ctxs[i]) {
> >> + devm_remove_action(dev,
> >> + if_misc_deregister,
> >> + &priv->ctxs[i]->miscdev);
> >> + misc_deregister(&priv->ctxs[i]->miscdev);
> >> + devm_kfree(dev, priv->ctxs[i]);
> >> + }
> >> + }
> >> + devm_kfree(dev, priv->ctxs);
> >> + }
> >> +
> >> + if (priv->flags & RESERVED_DMA_POOL) {
> >> + of_reserved_mem_device_release(dev);
> >> + priv->flags &= (~RESERVED_DMA_POOL);
> >> + }
> >> +
> >> + devm_kfree(dev, priv);
> >> + of_node_put(dev->of_node);
> >> + of_platform_device_destroy(dev, NULL);
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +static int se_probe_cleanup(struct platform_device *pdev)
> >> +{
> >> + struct device *dev = &pdev->dev;
> >> + struct device_node *if_dn;
> >> +
> >> + /* Enumerate se-interface device nodes. */
> >> + for_each_child_of_node(dev->of_node, if_dn) {
> >> + struct platform_device *if_pdev
> >> + = of_find_device_by_node(if_dn);
> >> + if (se_probe_if_cleanup(if_pdev))
> >> + dev_err(dev,
> >> + "Failed to clean-up child node probe.\n");
> >> + }
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int init_device_context(struct device *dev)
> >> +{
> >> + const struct imx_se_node_info *info;
> >> + struct se_if_device_ctx *dev_ctx;
> >> + struct se_if_priv *priv;
> >> + u8 *devname;
> >> + int ret = 0;
> >> + int i;
> >> +
> >> + priv = dev_get_drvdata(dev);
> >> +
> >> + if (!priv) {
> >> + ret = -EINVAL;
> >> + dev_err(dev, "Invalid SE-MU Priv data");
> >> + return ret;
> >> + }
> >> + info = priv->info;
> >> +
> >> + priv->ctxs = devm_kzalloc(dev, sizeof(dev_ctx) * priv->max_dev_ctx,
> >> + GFP_KERNEL);
> >> +
> >> + if (!priv->ctxs) {
> >> + ret = -ENOMEM;
> >> + return ret;
> >> + }
> >> +
> >> + /* Create users */
> >> + for (i = 0; i < priv->max_dev_ctx; i++) {
> >> + dev_ctx = devm_kzalloc(dev, sizeof(*dev_ctx), GFP_KERNEL);
> >> + if (!dev_ctx) {
> >> + ret = -ENOMEM;
> >> + return ret;
> >> + }
> >> +
> >> + dev_ctx->dev = dev;
> >> + dev_ctx->status = MU_FREE;
> >> + dev_ctx->priv = priv;
> >> +
> >> + priv->ctxs[i] = dev_ctx;
> >> +
> >> + /* Default value invalid for an header. */
> >> + init_waitqueue_head(&dev_ctx->wq);
> >> +
> >> + INIT_LIST_HEAD(&dev_ctx->pending_out);
> >> + INIT_LIST_HEAD(&dev_ctx->pending_in);
> >> + sema_init(&dev_ctx->fops_lock, 1);
> >> +
> >> + devname = devm_kasprintf(dev, GFP_KERNEL, "%s_ch%d",
> >> + info->se_name, i);
> >> + if (!devname) {
> >> + ret = -ENOMEM;
> >> + return ret;
> >> + }
> >> +
> >> + dev_ctx->miscdev.name = devname;
> >> + dev_ctx->miscdev.minor = MISC_DYNAMIC_MINOR;
> >> + dev_ctx->miscdev.fops = &se_if_fops;
> >> + dev_ctx->miscdev.parent = dev;
> >> + ret = misc_register(&dev_ctx->miscdev);
> >> + if (ret) {
> >> + dev_err(dev, "failed to register misc device %d\n",
> >> + ret);
> >> + return ret;
> >> + }
> >> +
> >> + ret = devm_add_action(dev, if_misc_deregister,
> >> + &dev_ctx->miscdev);
> >> + if (ret) {
> >> + dev_err(dev,
> >> + "failed[%d] to add action to the misc-dev\n",
> >> + ret);
> >> + return ret;
> >> + }
> >> + }
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +static void se_load_firmware(const struct firmware *fw, void *context)
> >> +{
> >> + struct se_if_priv *priv = (struct se_if_priv *) context;
> >> + const struct imx_se_node_info *info = priv->info;
> >> + const u8 *se_fw_name = info->fw_name_in_rfs;
> >> + phys_addr_t se_fw_phyaddr;
> >> + u8 *se_fw_buf;
> >> +
> >> + if (!fw) {
> >> + if (priv->fw_fail > MAX_FW_LOAD_RETRIES)
> >> + dev_dbg(priv->dev,
> >> + "External FW not found, using ROM FW.\n");
> >> + else {
> >> + /*add a bit delay to wait for firmware priv released */
> >> + msleep(20);
> >> +
> >> + /* Load firmware one more time if timeout */
> >> + request_firmware_nowait(THIS_MODULE,
> >> + FW_ACTION_UEVENT, info->fw_name_in_rfs,
> >> + priv->dev, GFP_KERNEL, priv,
> >> + se_load_firmware);
> >> + priv->fw_fail++;
> >> + dev_dbg(priv->dev, "Value of retries = 0x%x.\n",
> >> + priv->fw_fail);
> >> + }
> >> +
> >> + return;
> >> + }
> >> +
> >> + /* allocate buffer to store the SE FW */
> >> + se_fw_buf = dmam_alloc_coherent(priv->dev, fw->size,
> >> + &se_fw_phyaddr,
> >> + GFP_KERNEL);
> >> + if (!se_fw_buf) {
> >> + dev_err(priv->dev, "Failed to alloc SE fw buffer memory\n");
> >> + goto exit;
> >> + }
> >> +
> >> + memcpy(se_fw_buf, fw->data, fw->size);
> >> +
> >> + if (ele_fw_authenticate(priv->dev, se_fw_phyaddr))
> >> + dev_err(priv->dev,
> >> + "Failed to authenticate & load SE firmware %s.\n",
> >> + se_fw_name);
> >> +
> >> +exit:
> >> + dmam_free_coherent(priv->dev,
> >> + fw->size,
> >> + se_fw_buf,
> >> + se_fw_phyaddr);
> >> +
> >> + release_firmware(fw);
> >> +}
> >> +
> >> +static int se_if_probe(struct platform_device *pdev)
> >> +{
> >> + struct imx_se_node_info_list *info_list;
> >> + struct device *dev = &pdev->dev;
> >> + struct imx_se_node_info *info;
> >> + struct se_if_priv *priv;
> >> + u32 idx;
> >> + int ret;
> >> +
> >> + if (of_property_read_u32(dev->of_node, "reg", &idx)) {
> >> + ret = -EINVAL;
> >> + goto exit;
> >> + }
> >> +
> >> + info_list = (struct imx_se_node_info_list *)
> >> + device_get_match_data(dev->parent);
> >> + info = get_imx_se_node_info(info_list, idx);
> >> +
> >> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> >> + if (!priv) {
> >> + ret = -ENOMEM;
> >> + goto exit;
> >> + }
> >> +
> >> + dev_set_drvdata(dev, priv);
> >> +
> >> + /* Mailbox client configuration */
> >> + priv->se_mb_cl.dev = dev;
> >> + priv->se_mb_cl.tx_block = false;
> >> + priv->se_mb_cl.knows_txdone = true;
> >> + priv->se_mb_cl.rx_callback = se_if_rx_callback;
> >> +
> >> + ret = se_if_request_channel(dev, &priv->tx_chan,
> >> + &priv->se_mb_cl, info->mbox_tx_name);
> >> + if (ret) {
> >> + if (ret == -EPROBE_DEFER)
> >> + dev_err(dev, "Mailbox tx channel, is not ready.\n");
> >> + else
> >> + dev_err(dev, "Failed to request tx channel\n");
> >> +
> >> + goto exit;
> >> + }
> >> +
> >> + ret = se_if_request_channel(dev, &priv->rx_chan,
> >> + &priv->se_mb_cl, info->mbox_rx_name);
> >> + if (ret) {
> >> + if (ret == -EPROBE_DEFER)
> >> + dev_err(dev, "Mailbox rx channel, is not ready.\n");
> >> + else
> >> + dev_dbg(dev, "Failed to request rx channel\n");
> >> +
> >> + goto exit;
> >> + }
> >> +
> >> + priv->dev = dev;
> >> + priv->info = info;
> >> +
> >> + /* Initialize the mutex. */
> >> + mutex_init(&priv->se_if_lock);
> >> + mutex_init(&priv->se_if_cmd_lock);
> >> +
> >> + priv->cmd_receiver_dev = NULL;
> >> + priv->waiting_rsp_dev = NULL;
> >> + priv->max_dev_ctx = info->max_dev_ctx;
> >> + priv->cmd_tag = info->cmd_tag;
> >> + priv->rsp_tag = info->rsp_tag;
> >> + priv->mem_pool_name = info->pool_name;
> >> + priv->success_tag = info->success_tag;
> >> + priv->base_api_ver = info->base_api_ver;
> >> + priv->fw_api_ver = info->fw_api_ver;
> >> +
> >> + init_completion(&priv->done);
> >> + spin_lock_init(&priv->lock);
> >> +
> >> + if (info->reserved_dma_ranges) {
> >> + ret = of_reserved_mem_device_init(dev);
> >> + if (ret) {
> >> + dev_err(dev,
> >> + "failed to init reserved memory region %d\n",
> >> + ret);
> >> + priv->flags &= (~RESERVED_DMA_POOL);
> >> + goto exit;
> >> + }
> >> + priv->flags |= RESERVED_DMA_POOL;
> >> + }
> >> +
> >> + if (info->fw_name_in_rfs) {
> >> + ret = request_firmware_nowait(THIS_MODULE,
> >> + FW_ACTION_UEVENT,
> >> + info->fw_name_in_rfs,
> >> + dev, GFP_KERNEL, priv,
> >> + se_load_firmware);
> >> + if (ret)
> >> + dev_warn(dev, "Failed to get firmware [%s].\n",
> >> + info->fw_name_in_rfs);
> >> + }
> >> +
> >> + ret = imx_fetch_soc_info(dev);
> >> + if (ret) {
> >> + dev_err(dev,
> >> + "failed[%d] to fetch SoC Info\n", ret);
> >> + goto exit;
> >> + }
> >> +
> >> + if (info->imem_mgmt) {
> >> + /* allocate buffer where SE store encrypted IMEM */
> >> + priv->imem.buf = dmam_alloc_coherent(dev, ELE_IMEM_SIZE,
> >> + &priv->imem.phyaddr,
> >> + GFP_KERNEL);
> >> + if (!priv->imem.buf) {
> >> + dev_err(dev,
> >> + "dmam-alloc-failed: To store encr-IMEM.\n");
> >> + ret = -ENOMEM;
> >> + goto exit;
> >> + }
> >> + }
> >> +
> >> + if (info->max_dev_ctx) {
> >> + ret = init_device_context(dev);
> >> + if (ret) {
> >> + dev_err(dev,
> >> + "Failed[0x%x] to create device contexts.\n",
> >> + ret);
> >> + goto exit;
> >> + }
> >> + }
> >> +
> >> + dev_info(dev, "i.MX secure-enclave: %s interface to firmware,
> configured.\n",
> >> + info->se_name);
> >> + return devm_of_platform_populate(dev);
> >> +
> >> +exit:
> >> + /* if execution control reaches here, if probe fails.
> >> + * hence doing the cleanup
> >> + */
> >> + if (se_probe_if_cleanup(pdev))
> >> + dev_err(dev,
> >> + "Failed to clean-up the child node probe.\n");
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +static int se_probe(struct platform_device *pdev)
> >> +{
> >> + struct device_node *enum_dev_node;
> >> + struct device *dev = &pdev->dev;
> >> + int enum_count;
> >> + int ret;
> >> +
> >> + enum_count = of_get_child_count(dev->of_node);
> >> + if (!enum_count) {
> >> + ret = -EINVAL;
> >> + dev_err(dev, "Zero Tx/Rx path MU nodes.\n");
> >> + return ret;
> >> + }
> >> +
> >> + for_each_child_of_node(dev->of_node, enum_dev_node) {
> >> + struct platform_device *enum_plat_dev __maybe_unused;
> >> +
> >> + if (!of_device_is_available(enum_dev_node))
> >> + continue;
> >> +
> >> + enum_plat_dev = of_platform_device_create(enum_dev_node,
> >> + NULL,
> >> + dev);
> >> + if (!enum_plat_dev) {
> >> + ret = -EINVAL;
> >> + of_node_put(enum_dev_node);
> >> + dev_err(dev,
> >> + "Failed to create enumerated platform device.");
> >> + break;
> >> + }
> >> +
> >> + ret = se_if_probe(enum_plat_dev);
> >> + }
> >> + return ret;
> >> +}
> >> +
> >> +static int se_remove(struct platform_device *pdev)
> >> +{
> >> + if (se_probe_cleanup(pdev))
> >> + dev_err(&pdev->dev,
> >> + "i.MX Secure Enclave is not cleanly un-probed.");
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int se_suspend(struct device *dev)
> >> +{
> >> + struct se_if_priv *priv = dev_get_drvdata(dev);
> >> + const struct imx_se_node_info *info
> >> + = priv->info;
> >> +
> >> + if (info && info->imem_mgmt)
> >> + priv->imem.size = se_save_imem_state(dev);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int se_resume(struct device *dev)
> >> +{
> >> + struct se_if_priv *priv = dev_get_drvdata(dev);
> >> + const struct imx_se_node_info *info
> >> + = priv->info;
> >> + int i;
> >> +
> >> + for (i = 0; i < priv->max_dev_ctx; i++)
> >> + wake_up_interruptible(&priv->ctxs[i]->wq);
> >> +
> >> + if (info && info->imem_mgmt)
> >> + se_restore_imem_state(dev);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static const struct dev_pm_ops se_pm = {
> >> + RUNTIME_PM_OPS(se_suspend, se_resume, NULL)
> >> +};
> >> +
> >> +static struct platform_driver se_driver = {
> >> + .driver = {
> >> + .name = "fsl-se-fw",
> >> + .of_match_table = se_match,
> >> + .pm = &se_pm,
> >> + },
> >> + .probe = se_probe,
> >> + .remove = se_remove,
> >> +};
> >> +MODULE_DEVICE_TABLE(of, se_match);
> >> +
> >> +module_platform_driver(se_driver);
> >> +
> >> +MODULE_AUTHOR("Pankaj Gupta <pankaj.gupta@nxp.com>");
> >> +MODULE_DESCRIPTION("iMX Secure Enclave Driver.");
> >> +MODULE_LICENSE("GPL");
> >> diff --git a/drivers/firmware/imx/se_ctrl.h
> b/drivers/firmware/imx/se_ctrl.h
> >> new file mode 100644
> >> index 000000000000..76e1ce77c52f
> >> --- /dev/null
> >> +++ b/drivers/firmware/imx/se_ctrl.h
> >> @@ -0,0 +1,151 @@
> >> +/* SPDX-License-Identifier: GPL-2.0+ */
> >> +/*
> >> + * Copyright 2024 NXP
> >> + */
> >> +
> >> +#ifndef SE_MU_H
> >> +#define SE_MU_H
> >> +
> >> +#include <linux/miscdevice.h>
> >> +#include <linux/semaphore.h>
> >> +#include <linux/mailbox_client.h>
> >> +
> >> +#define MAX_FW_LOAD_RETRIES 50
> >> +
> >> +#define MSG_TAG(x) (((x) & 0xff000000) >> 24)
> >> +#define MSG_COMMAND(x) (((x) & 0x00ff0000) >> 16)
> >> +#define MSG_SIZE(x) (((x) & 0x0000ff00) >> 8)
> >> +#define MSG_VER(x) ((x) & 0x000000ff)
> >> +#define RES_STATUS(x) ((x) & 0x000000ff)
> >> +#define MAX_DATA_SIZE_PER_USER (65 * 1024)
> >> +#define S4_DEFAULT_MUAP_INDEX (2)
> >> +#define S4_MUAP_DEFAULT_MAX_USERS (4)
> >> +#define MESSAGING_VERSION_6 0x6
> >> +#define MESSAGING_VERSION_7 0x7
> >> +
> >> +#define DEFAULT_MESSAGING_TAG_COMMAND (0x17u)
> >> +#define DEFAULT_MESSAGING_TAG_RESPONSE (0xe1u)
> >> +
> >> +#define SE_MU_IO_FLAGS_USE_SEC_MEM (0x02u)
> >> +#define SE_MU_IO_FLAGS_USE_SHORT_ADDR (0x04u)
> >> +
> >> +struct se_imem_buf {
> >> + u8 *buf;
> >> + phys_addr_t phyaddr;
> >> + u32 size;
> >> +};
> >> +
> >> +struct se_buf_desc {
> >> + u8 *shared_buf_ptr;
> >> + u8 *usr_buf_ptr;
> >> + u32 size;
> >> + struct list_head link;
> >> +};
> >> +
> >> +/* Status of a char device */
> >> +enum se_if_dev_ctx_status_t {
> >> + MU_FREE,
> >> + MU_OPENED
> >> +};
> >> +
> >> +struct se_shared_mem {
> >> + dma_addr_t dma_addr;
> >> + u32 size;
> >> + u32 pos;
> >> + u8 *ptr;
> >> +};
> >> +
> >> +/* Private struct for each char device instance. */
> >> +struct se_if_device_ctx {
> >> + struct device *dev;
> >> + struct se_if_priv *priv;
> >> + struct miscdevice miscdev;
> >> +
> >> + enum se_if_dev_ctx_status_t status;
> >> + wait_queue_head_t wq;
> >> + struct semaphore fops_lock;
> >> +
> >> + u32 pending_hdr;
> >> + struct list_head pending_in;
> >> + struct list_head pending_out;
> >> +
> >> + struct se_shared_mem secure_mem;
> >> + struct se_shared_mem non_secure_mem;
> >> +
> >> + u32 *temp_resp;
> >> + u32 temp_resp_size;
> >> + struct notifier_block se_notify;
> >> +};
> >> +
> >> +/* Header of the messages exchange with the EdgeLock Enclave */
> >> +struct se_msg_hdr {
> >> + u8 ver;
> >> + u8 size;
> >> + u8 command;
> >> + u8 tag;
> >> +} __packed;
> >> +
> >> +#define SE_MU_HDR_SZ 4
> >> +#define TAG_OFFSET (SE_MU_HDR_SZ - 1)
> >> +#define CMD_OFFSET (SE_MU_HDR_SZ - 2)
> >> +#define SZ_OFFSET (SE_MU_HDR_SZ - 3)
> >> +#define VER_OFFSET (SE_MU_HDR_SZ - 4)
> >> +
> >> +struct se_api_msg {
> >> + u32 header; /* u8 Tag; u8 Command; u8 Size; u8 Ver; */
> >> + u32 *data;
> >> +};
> >> +
> >> +struct se_if_priv {
> >> + struct se_if_device_ctx *cmd_receiver_dev;
> >> + struct se_if_device_ctx *waiting_rsp_dev;
> >> + bool no_dev_ctx_used;
> >> + /*
> >> + * prevent parallel access to the se interface registers
> >> + * e.g. a user trying to send a command while the other one is
> >> + * sending a response.
> >> + */
> >> + struct mutex se_if_lock;
> >> + /*
> >> + * prevent a command to be sent on the se interface while another one
> is
> >> + * still processing. (response to a command is allowed)
> >> + */
> >> + struct mutex se_if_cmd_lock;
> >> + struct device *dev;
> >> + u8 *mem_pool_name;
> >> + u8 cmd_tag;
> >> + u8 rsp_tag;
> >> + u8 success_tag;
> >> + u8 base_api_ver;
> >> + u8 fw_api_ver;
> >> + u32 fw_fail;
> >> + const void *info;
> >> +
> >> + struct mbox_client se_mb_cl;
> >> + struct mbox_chan *tx_chan, *rx_chan;
> >> + struct se_api_msg *rx_msg;
> >> + struct completion done;
> >> + spinlock_t lock;
> >> + /*
> >> + * Flag to retain the state of initialization done at
> >> + * the time of se-mu probe.
> >> + */
> >> + uint32_t flags;
> >> + u8 max_dev_ctx;
> >> + struct se_if_device_ctx **ctxs;
> >> + struct se_imem_buf imem;
> >> +};
> >> +
> >> +void *get_phy_buf_mem_pool(struct device *dev,
> >> + u8 *mem_pool_name,
> >> + dma_addr_t *buf,
> >> + u32 size);
> >> +phys_addr_t get_phy_buf_mem_pool1(struct device *dev,
> >> + u8 *mem_pool_name,
> >> + u32 **buf,
> >> + u32 size);
> >> +void free_phybuf_mem_pool(struct device *dev,
> >> + u8 *mem_pool_name,
> >> + u32 *buf,
> >> + u32 size);
> >> +#endif
> >> diff --git a/include/linux/firmware/imx/se_api.h
> b/include/linux/firmware/imx/se_api.h
> >> new file mode 100644
> >> index 000000000000..c47f84906837
> >> --- /dev/null
> >> +++ b/include/linux/firmware/imx/se_api.h
> >> @@ -0,0 +1,14 @@
> >> +/* SPDX-License-Identifier: GPL-2.0+ */
> >> +/*
> >> + * Copyright 2024 NXP
> >> + */
> >> +
> >> +#ifndef __SE_API_H__
> >> +#define __SE_API_H__
> >> +
> >> +#include <linux/types.h>
> >> +
> >> +#define SOC_ID_OF_IMX8ULP 0x084D
> >> +#define SOC_ID_OF_IMX93 0x9300
> >> +
> >> +#endif /* __SE_API_H__ */
> >> diff --git a/include/uapi/linux/se_ioctl.h b/include/uapi/linux/se_ioctl.h
> >> new file mode 100644
> >> index 000000000000..f68a36e9da2c
> >> --- /dev/null
> >> +++ b/include/uapi/linux/se_ioctl.h
> >> @@ -0,0 +1,88 @@
> >> +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-
> Clause*/
> >> +/*
> >> + * Copyright 2024 NXP
> >> + */
> >> +
> >> +#ifndef SE_IOCTL_H
> >> +#define SE_IOCTL_H
> >> +
> >> +/* IOCTL definitions. */
> >> +
> >> +struct se_ioctl_setup_iobuf {
> >> + u8 *user_buf;
> >> + u32 length;
> >> + u32 flags;
> >> + u64 ele_addr;
> >> +};
> >> +
> >> +struct se_ioctl_shared_mem_cfg {
> >> + u32 base_offset;
> >> + u32 size;
> >> +};
> >> +
> >> +struct se_ioctl_get_if_info {
> >> + u8 se_if_id;
> >> + u8 interrupt_idx;
> >> + u8 tz;
> >> + u8 did;
> >> + u8 cmd_tag;
> >> + u8 rsp_tag;
> >> + u8 success_tag;
> >> + u8 base_api_ver;
> >> + u8 fw_api_ver;
> >> +};
> >> +
> >> +struct se_ioctl_signed_message {
> >> + u8 *message;
> >> + u32 msg_size;
> >> + u32 error_code;
> >> +};
> >> +
> >> +struct se_ioctl_get_soc_info {
> >> + u16 soc_id;
> >> + u16 soc_rev;
> >> +};
> >> +
> >> +/* IO Buffer Flags */
> >> +#define SE_IO_BUF_FLAGS_IS_OUTPUT (0x00u)
> >> +#define SE_IO_BUF_FLAGS_IS_INPUT (0x01u)
> >> +#define SE_IO_BUF_FLAGS_USE_SEC_MEM (0x02u)
> >> +#define SE_IO_BUF_FLAGS_USE_SHORT_ADDR (0x04u)
> >> +#define SE_IO_BUF_FLAGS_IS_IN_OUT (0x10u)
> >> +
> >> +/* IOCTLS */
> >> +#define SE_IOCTL 0x0A /* like MISC_MAJOR. */
> >> +
> >> +/*
> >> + * ioctl to designated the current fd as logical-reciever.
> >> + * This is ioctl is send when the nvm-daemon, a slave to the
> >> + * firmware is started by the user.
> >> + */
> >> +#define SE_IOCTL_ENABLE_CMD_RCV _IO(SE_IOCTL, 0x01)
> >> +
> >> +/*
> >> + * ioctl to get the buffer allocated from the memory, which is shared
> >> + * between kernel and FW.
> >> + * Post allocation, the kernel tagged the allocated memory with:
> >> + * Output
> >> + * Input
> >> + * Input-Output
> >> + * Short address
> >> + * Secure-memory
> >> + */
> >> +#define SE_IOCTL_SETUP_IOBUF _IOWR(SE_IOCTL, 0x03, \
> >> + struct se_ioctl_setup_iobuf)
> >> +
> >> +/*
> >> + * ioctl to get the mu information, that is used to exchange message
> >> + * with FW, from user-spaced.
> >> + */
> >> +#define SE_IOCTL_GET_MU_INFO _IOR(SE_IOCTL, 0x04, \
> >> + struct se_ioctl_get_if_info)
> >> +/*
> >> + * ioctl to get SoC Info from user-space.
> >> + */
> >> +#define SE_IOCTL_GET_SOC_INFO _IOR(SE_IOCTL, 0x06, \
> >> + struct se_ioctl_get_soc_info)
> >> +
> >> +#endif
> >>
> >> --
> >> 2.34.1
> >>
> >
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* RE: [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave
2024-05-10 16:41 0% ` Frank Li
2024-05-10 19:39 0% ` Amit Singh Tomar
@ 2024-05-13 9:12 0% ` Pankaj Gupta
1 sibling, 0 replies; 200+ results
From: Pankaj Gupta @ 2024-05-13 9:12 UTC (permalink / raw)
To: Frank Li
Cc: Jonathan Corbet, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
linux-doc, linux-kernel, devicetree, imx, linux-arm-kernel
> -----Original Message-----
> From: Frank Li <frank.li@nxp.com>
> Sent: Friday, May 10, 2024 10:11 PM
> To: Pankaj Gupta <pankaj.gupta@nxp.com>
> Cc: Jonathan Corbet <corbet@lwn.net>; Rob Herring <robh+dt@kernel.org>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Conor Dooley
> <conor+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Sascha Hauer
> <s.hauer@pengutronix.de>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>; linux-
> doc@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; imx@lists.linux.dev; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave
>
> On Fri, May 10, 2024 at 06:57:30PM +0530, Pankaj Gupta wrote:
> > NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE),
> > are embedded in the SoC to support the features like HSM, SHE & V2X,
> > using message based communication interface.
> >
> > The secure enclave FW communicates on a dedicated messaging unit(MU)
> > based interface(s) with application core, where kernel is running.
> > It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
> >
> > This patch adds the driver for communication interface to secure-enclave,
> > for exchanging messages with NXP secure enclave HW IP(s) like EdgeLock
> Enclave,
> > both from:
> > - User-Space Applications via character driver.
> > - Kernel-space, used by kernel management layers like DM-Crypt.
> >
> > ABI documentation for the NXP secure-enclave driver.
> >
> > User-space library using this driver:
> > - i.MX Secure Enclave library:
> > -- URL: https://github.com/nxp-imx/imx-secure-enclave.git,
> > - i.MX Secure Middle-Ware:
> > -- URL: https://github.com/nxp-imx/imx-smw.git
> >
> > Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> > ---
> > Documentation/ABI/testing/se-cdev | 42 ++
> > drivers/firmware/imx/Kconfig | 12 +
> > drivers/firmware/imx/Makefile | 2 +
> > drivers/firmware/imx/ele_base_msg.c | 287 ++++++++
> > drivers/firmware/imx/ele_base_msg.h | 70 ++
> > drivers/firmware/imx/ele_common.c | 341 +++++++++
> > drivers/firmware/imx/ele_common.h | 43 ++
> > drivers/firmware/imx/se_ctrl.c | 1339
> +++++++++++++++++++++++++++++++++++
> > drivers/firmware/imx/se_ctrl.h | 151 ++++
> > include/linux/firmware/imx/se_api.h | 14 +
> > include/uapi/linux/se_ioctl.h | 88 +++
> > 11 files changed, 2389 insertions(+)
> >
> > diff --git a/Documentation/ABI/testing/se-cdev
> b/Documentation/ABI/testing/se-cdev
> > new file mode 100644
> > index 000000000000..699525af6b86
> > --- /dev/null
> > +++ b/Documentation/ABI/testing/se-cdev
> > @@ -0,0 +1,42 @@
> > +What: /dev/<se>_mu[0-9]+_ch[0-9]+
> > +Date: May 2024
> > +KernelVersion: 6.8
> > +Contact: linux-imx@nxp.com, pankaj.gupta@nxp.com
> > +Description:
> > + NXP offers multiple hardware IP(s) for secure-enclaves like
> EdgeLock-
> > + Enclave(ELE), SECO. The character device file-descriptors
> > + /dev/<se>_mu*_ch* are the interface between user-space
> NXP's secure-
> > + enclave shared-library and the kernel driver.
> > +
> > + The ioctl(2)-based ABI is defined and documented in
> > + [include]<linux/firmware/imx/ele_mu_ioctl.h>
> > + ioctl(s) are used primarily for:
> > + - shared memory management
> > + - allocation of I/O buffers
> > + - get mu info
> > + - setting a dev-ctx as receiver that is slave to fw
> > + - get SoC info
> > +
> > + The following file operations are supported:
> > +
> > + open(2)
> > + Currently the only useful flags are O_RDWR.
> > +
> > + read(2)
> > + Every read() from the opened character device context is
> waiting on
> > + wakeup_intruptible, that gets set by the registered mailbox
> callback
> > + function; indicating a message received from the firmware
> on message-
> > + unit.
> > +
> > + write(2)
> > + Every write() to the opened character device context needs
> to acquire
> > + mailbox_lock, before sending message on to the message
> unit.
> > +
> > + close(2)
> > + Stops and free up the I/O contexts that was associated
> > + with the file descriptor.
> > +
> > +Users: https://github.com/nxp-imx/imx-secure-enclave.git,
> > + https://github.com/nxp-imx/imx-smw.git
> > + crypto/skcipher,
> > + drivers/nvmem/imx-ocotp-ele.c
> > diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
> > index 183613f82a11..56bdca9bd917 100644
> > --- a/drivers/firmware/imx/Kconfig
> > +++ b/drivers/firmware/imx/Kconfig
> > @@ -22,3 +22,15 @@ config IMX_SCU
> >
> > This driver manages the IPC interface between host CPU and the
> > SCU firmware running on M4.
> > +
> > +config IMX_SEC_ENCLAVE
> > + tristate "i.MX Embedded Secure Enclave - EdgeLock Enclave Firmware
> driver."
> > + depends on IMX_MBOX && ARCH_MXC && ARM64
> > + default m if ARCH_MXC
> > +
> > + help
> > + It is possible to use APIs exposed by the iMX Secure Enclave HW IP
> called:
> > + - EdgeLock Enclave Firmware (for i.MX8ULP, i.MX93),
> > + like base, HSM, V2X & SHE using the SAB protocol via the shared
> Messaging
> > + Unit. This driver exposes these interfaces via a set of file descriptors
> > + allowing to configure shared memory, send and receive messages.
> > diff --git a/drivers/firmware/imx/Makefile
> b/drivers/firmware/imx/Makefile
> > index 8f9f04a513a8..aa9033e0e9e3 100644
> > --- a/drivers/firmware/imx/Makefile
> > +++ b/drivers/firmware/imx/Makefile
> > @@ -1,3 +1,5 @@
> > # SPDX-License-Identifier: GPL-2.0
> > obj-$(CONFIG_IMX_DSP) += imx-dsp.o
> > obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o
> rm.o imx-scu-soc.o
> > +sec_enclave-objs = se_ctrl.o ele_common.o ele_base_msg.o
> > +obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
> > diff --git a/drivers/firmware/imx/ele_base_msg.c
> b/drivers/firmware/imx/ele_base_msg.c
> > new file mode 100644
> > index 000000000000..0463f26d93c7
> > --- /dev/null
> > +++ b/drivers/firmware/imx/ele_base_msg.c
> > @@ -0,0 +1,287 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#include <linux/types.h>
> > +#include <linux/completion.h>
> > +#include <linux/dma-mapping.h>
> > +
> > +#include "ele_base_msg.h"
> > +#include "ele_common.h"
> > +
> > +int ele_get_info(struct device *dev, struct soc_info *s_info)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + struct se_api_msg *tx_msg __free(kfree);
> > + struct se_api_msg *rx_msg __free(kfree);
> > + phys_addr_t get_info_addr;
> > + u32 *get_info_data;
> > + u32 status;
> > + int ret;
> > +
> > + if (!priv || !s_info)
> > + goto exit;
> > +
> > + memset(s_info, 0x0, sizeof(*s_info));
> > +
> > + if (priv->mem_pool_name)
> > + get_info_data = get_phy_buf_mem_pool(dev,
> > + priv->mem_pool_name,
> > + &get_info_addr,
> > + ELE_GET_INFO_BUFF_SZ);
> > + else
> > + get_info_data = dmam_alloc_coherent(dev,
> > + ELE_GET_INFO_BUFF_SZ,
> > + &get_info_addr,
> > + GFP_KERNEL);
> > + if (!get_info_data) {
> > + ret = -ENOMEM;
> > + dev_err(dev,
> > + "%s: Failed to allocate get_info_addr.\n",
> > + __func__);
> > + goto exit;
> > + }
> > +
> > + tx_msg = kzalloc(ELE_GET_INFO_REQ_MSG_SZ << 2, GFP_KERNEL);
> > + if (!tx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + rx_msg = kzalloc(ELE_GET_INFO_RSP_MSG_SZ << 2, GFP_KERNEL);
> > + if (!rx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + ret = plat_fill_cmd_msg_hdr(priv,
> > + (struct se_msg_hdr *)&tx_msg->header,
> > + ELE_GET_INFO_REQ,
> > + ELE_GET_INFO_REQ_MSG_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + tx_msg->data[0] = upper_32_bits(get_info_addr);
> > + tx_msg->data[1] = lower_32_bits(get_info_addr);
> > + tx_msg->data[2] = ELE_GET_INFO_READ_SZ;
> > + priv->rx_msg = rx_msg;
> > + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> > + if (ret < 0)
> > + goto exit;
> > +
> > + ret = validate_rsp_hdr(priv,
> > + priv->rx_msg->header,
> > + ELE_GET_INFO_REQ,
> > + ELE_GET_INFO_RSP_MSG_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + status = RES_STATUS(priv->rx_msg->data[0]);
> > + if (status != priv->success_tag) {
> > + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> > + ELE_GET_INFO_REQ, status);
> > + ret = -1;
> > + }
> > +
> > + s_info->imem_state = (get_info_data[ELE_IMEM_STATE_WORD]
> > + & ELE_IMEM_STATE_MASK) >> 16;
> > + s_info->major_ver =
> (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> > + & SOC_VER_MASK) >> 24;
> > + s_info->minor_ver =
> ((get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> > + & SOC_VER_MASK) >> 16) & 0xFF;
> > + s_info->soc_rev =
> (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> > + & SOC_VER_MASK) >> 16;
> > + s_info->soc_id =
> get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> > + & SOC_ID_MASK;
> > + s_info->serial_num
> > + = (u64)get_info_data[GET_INFO_SL_NUM_MSB_WORD_OFF]
> << 32
> > + |
> get_info_data[GET_INFO_SL_NUM_LSB_WORD_OFF];
> > +exit:
> > + if (get_info_addr) {
> > + if (priv->mem_pool_name)
> > + free_phybuf_mem_pool(dev, priv->mem_pool_name,
> > + get_info_data,
> ELE_GET_INFO_BUFF_SZ);
> > + else
> > + dmam_free_coherent(dev,
> > + ELE_GET_INFO_BUFF_SZ,
> > + get_info_data,
> > + get_info_addr);
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +int ele_ping(struct device *dev)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + struct se_api_msg *tx_msg __free(kfree);
> > + struct se_api_msg *rx_msg __free(kfree);
>
> If you want __free(kfree) it should be
>
> struct se_api_msg *tx_msg __free(kfree) = NULL;
> struct se_api_msg *rx_msg __free(kfree) = NULL;
>
> Or
Accepted.
>
> struct se_api_msg *tx_msg __free(kfree) = kzalloc(ELE_PING_REQ_SZ << 2,
> GFP_KERNEL)
> struct se_api_msg *rx_msg __free(kfree) = kzalloc(ELE_PING_RSP_SZ << 2,
> GFP_KERNEL)
>
> otherwise when
> if (!tx_msg) {
> return ret;
>
> ^^ when go here, rx_msg is random value. So kfree(rx_msg) will
> access random address.
Understood.
>
> }
>
> > + u32 status;
> > + int ret;
> > +
> > + tx_msg = kzalloc(ELE_PING_REQ_SZ << 2, GFP_KERNEL);
> > + if (!tx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
>
>
> return -ENOMEM
>
> Frank
Accepted.
>
> > + }
> > +
> > + rx_msg = kzalloc(ELE_PING_RSP_SZ << 2, GFP_KERNEL);
> > + if (!rx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + ret = plat_fill_cmd_msg_hdr(priv,
> > + (struct se_msg_hdr *)&tx_msg->header,
> > + ELE_PING_REQ, ELE_PING_REQ_SZ,
> > + true);
> > + if (ret) {
> > + dev_err(dev, "Error: plat_fill_cmd_msg_hdr failed.\n");
> > + goto exit;
> > + }
> > +
> > + priv->rx_msg = rx_msg;
> > + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> > + if (ret)
> > + goto exit;
> > +
> > + ret = validate_rsp_hdr(priv,
> > + priv->rx_msg->header,
> > + ELE_PING_REQ,
> > + ELE_PING_RSP_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + status = RES_STATUS(priv->rx_msg->data[0]);
> > + if (status != priv->success_tag) {
> > + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> > + ELE_PING_REQ, status);
> > + ret = -1;
> > + }
> > +exit:
> > + return ret;
> > +}
> > +
> > +int ele_service_swap(struct device *dev,
> > + phys_addr_t addr,
> > + u32 addr_size, u16 flag)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + struct se_api_msg *tx_msg __free(kfree);
> > + struct se_api_msg *rx_msg __free(kfree);
> > + u32 status;
> > + int ret;
> > +
> > + tx_msg = kzalloc(ELE_SERVICE_SWAP_REQ_MSG_SZ << 2,
> GFP_KERNEL);
> > + if (!tx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + rx_msg = kzalloc(ELE_SERVICE_SWAP_RSP_MSG_SZ << 2,
> GFP_KERNEL);
> > + if (!rx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + ret = plat_fill_cmd_msg_hdr(priv,
> > + (struct se_msg_hdr *)&tx_msg->header,
> > + ELE_SERVICE_SWAP_REQ,
> > + ELE_SERVICE_SWAP_REQ_MSG_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + tx_msg->data[0] = flag;
> > + tx_msg->data[1] = addr_size;
> > + tx_msg->data[2] = ELE_NONE_VAL;
> > + tx_msg->data[3] = lower_32_bits(addr);
> > + tx_msg->data[4] = plat_add_msg_crc((uint32_t *)&tx_msg[0],
> > +
> ELE_SERVICE_SWAP_REQ_MSG_SZ);
> > + priv->rx_msg = rx_msg;
> > + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> > + if (ret < 0)
> > + goto exit;
> > +
> > + ret = validate_rsp_hdr(priv,
> > + priv->rx_msg->header,
> > + ELE_SERVICE_SWAP_REQ,
> > + ELE_SERVICE_SWAP_RSP_MSG_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + status = RES_STATUS(priv->rx_msg->data[0]);
> > + if (status != priv->success_tag) {
> > + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> > + ELE_SERVICE_SWAP_REQ, status);
> > + ret = -1;
> > + } else {
> > + if (flag == ELE_IMEM_EXPORT)
> > + ret = priv->rx_msg->data[1];
> > + else
> > + ret = 0;
> > + }
> > +exit:
> > +
> > + return ret;
> > +}
> > +
> > +int ele_fw_authenticate(struct device *dev, phys_addr_t addr)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + struct se_api_msg *tx_msg __free(kfree);
> > + struct se_api_msg *rx_msg __free(kfree);
> > + u32 status;
> > + int ret;
> > +
> > + tx_msg = kzalloc(ELE_FW_AUTH_REQ_SZ << 2, GFP_KERNEL);
> > + if (!tx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + rx_msg = kzalloc(ELE_FW_AUTH_RSP_MSG_SZ << 2, GFP_KERNEL);
> > + if (!rx_msg) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > + ret = plat_fill_cmd_msg_hdr(priv,
> > + (struct se_msg_hdr *)&tx_msg->header,
> > + ELE_FW_AUTH_REQ,
> > + ELE_FW_AUTH_REQ_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + tx_msg->data[0] = addr;
> > + tx_msg->data[1] = 0x0;
> > + tx_msg->data[2] = addr;
> > +
> > + priv->rx_msg = rx_msg;
> > + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> > + if (ret < 0)
> > + goto exit;
> > +
> > + ret = validate_rsp_hdr(priv,
> > + priv->rx_msg->header,
> > + ELE_FW_AUTH_REQ,
> > + ELE_FW_AUTH_RSP_MSG_SZ,
> > + true);
> > + if (ret)
> > + goto exit;
> > +
> > + status = RES_STATUS(priv->rx_msg->data[0]);
> > + if (status != priv->success_tag) {
> > + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> > + ELE_FW_AUTH_REQ, status);
> > + ret = -1;
> > + }
> > +exit:
> > +
> > + return ret;
> > +}
> > diff --git a/drivers/firmware/imx/ele_base_msg.h
> b/drivers/firmware/imx/ele_base_msg.h
> > new file mode 100644
> > index 000000000000..3b3d2bf04a84
> > --- /dev/null
> > +++ b/drivers/firmware/imx/ele_base_msg.h
> > @@ -0,0 +1,70 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2024 NXP
> > + *
> > + * Header file for the EdgeLock Enclave Base API(s).
> > + */
> > +
> > +#ifndef ELE_BASE_MSG_H
> > +#define ELE_BASE_MSG_H
> > +
> > +#include <linux/device.h>
> > +#include <linux/types.h>
> > +
> > +#define WORD_SZ 4
> > +#define ELE_NONE_VAL 0x0
> > +
> > +#define ELE_SUCCESS_IND 0xD6
> > +
> > +#define ELE_GET_INFO_REQ 0xDA
> > +#define ELE_GET_INFO_REQ_MSG_SZ 0x10
> > +#define ELE_GET_INFO_RSP_MSG_SZ 0x08
> > +
> > +#define ELE_GET_INFO_BUFF_SZ 0x100
> > +#define ELE_GET_INFO_READ_SZ 0xA0
> > +
> > +#define DEFAULT_IMX_SOC_VER 0xA0
> > +#define SOC_VER_MASK 0xFFFF0000
> > +#define SOC_ID_MASK 0x0000FFFF
> > +struct soc_info {
> > + u32 imem_state;
> > + u8 major_ver;
> > + u8 minor_ver;
> > + u16 soc_id;
> > + u16 soc_rev;
> > + u64 serial_num;
> > +};
> > +
> > +#define GET_INFO_SOC_INFO_WORD_OFFSET 1
> > +#define GET_INFO_UUID_WORD_OFFSET 3
> > +#define GET_INFO_SL_NUM_MSB_WORD_OFF \
> > + (GET_INFO_UUID_WORD_OFFSET + 3)
> > +#define GET_INFO_SL_NUM_LSB_WORD_OFF \
> > + (GET_INFO_UUID_WORD_OFFSET + 0)
> > +
> > +#define ELE_PING_REQ 0x01
> > +#define ELE_PING_REQ_SZ 0x04
> > +#define ELE_PING_RSP_SZ 0x08
> > +
> > +#define ELE_SERVICE_SWAP_REQ 0xDF
> > +#define ELE_SERVICE_SWAP_REQ_MSG_SZ 0x18
> > +#define ELE_SERVICE_SWAP_RSP_MSG_SZ 0x0C
> > +#define ELE_IMEM_SIZE 0x10000
> > +#define ELE_IMEM_STATE_OK 0xCA
> > +#define ELE_IMEM_STATE_BAD 0xFE
> > +#define ELE_IMEM_STATE_WORD 0x27
> > +#define ELE_IMEM_STATE_MASK 0x00ff0000
> > +#define ELE_IMEM_EXPORT 0x1
> > +#define ELE_IMEM_IMPORT 0x2
> > +
> > +#define ELE_FW_AUTH_REQ 0x02
> > +#define ELE_FW_AUTH_REQ_SZ 0x10
> > +#define ELE_FW_AUTH_RSP_MSG_SZ 0x08
> > +
> > +int ele_get_info(struct device *dev, struct soc_info *s_info);
> > +int ele_ping(struct device *dev);
> > +int ele_service_swap(struct device *dev,
> > + phys_addr_t addr,
> > + u32 addr_size, u16 flag);
> > +int ele_fw_authenticate(struct device *dev, phys_addr_t addr);
> > +#endif
> > diff --git a/drivers/firmware/imx/ele_common.c
> b/drivers/firmware/imx/ele_common.c
> > new file mode 100644
> > index 000000000000..dcf7f9034653
> > --- /dev/null
> > +++ b/drivers/firmware/imx/ele_common.c
> > @@ -0,0 +1,341 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#include "ele_base_msg.h"
> > +#include "ele_common.h"
> > +
> > +u32 plat_add_msg_crc(u32 *msg, u32 msg_len)
> > +{
> > + u32 nb_words = msg_len / (u32)sizeof(u32);
> > + u32 crc = 0;
> > + u32 i;
> > +
> > + for (i = 0; i < nb_words - 1; i++)
> > + crc ^= *(msg + i);
> > +
> > + return crc;
> > +}
> > +
> > +int imx_ele_msg_rcv(struct se_if_priv *priv)
> > +{
> > + u32 wait;
> > + int err;
> > +
> > + wait = msecs_to_jiffies(1000);
> > + if (!wait_for_completion_timeout(&priv->done, wait)) {
> > + dev_err(priv->dev,
> > + "Error: wait_for_completion timed out.\n");
> > + err = -ETIMEDOUT;
> > + }
> > +
> > + mutex_unlock(&priv->se_if_cmd_lock);
> > + priv->no_dev_ctx_used = false;
> > +
> > + return err;
> > +}
> > +
> > +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg)
> > +{
> > + bool is_cmd_lock_tobe_taken = false;
> > + int err;
> > +
> > + if (!priv->waiting_rsp_dev || priv->no_dev_ctx_used) {
> > + is_cmd_lock_tobe_taken = true;
> > + mutex_lock(&priv->se_if_cmd_lock);
> > + }
> > + scoped_guard(mutex, &priv->se_if_lock);
> > +
> > + err = mbox_send_message(priv->tx_chan, mssg);
> > + if (err < 0) {
> > + dev_err(priv->dev, "Error: mbox_send_message failure.\n");
> > + if (is_cmd_lock_tobe_taken)
> > + mutex_unlock(&priv->se_if_cmd_lock);
> > + return err;
> > + }
> > + err = 0;
> > +
> > + return err;
> > +}
> > +
> > +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg)
> > +{
> > + int err;
> > +
> > + priv->no_dev_ctx_used = true;
> > + err = imx_ele_msg_send(priv, mssg);
> > + if (err)
> > + goto exit;
> > +
> > + err = imx_ele_msg_rcv(priv);
> > +
> > +exit:
> > + return err;
> > +}
> > +
> > +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *dev_ctx)
> > +{
> > + struct se_msg_hdr header = {0};
> > + int err;
> > +
> > + err = wait_event_interruptible(dev_ctx->wq, dev_ctx-
> >pending_hdr != 0);
> > + if (err)
> > + dev_err(dev_ctx->dev,
> > + "%s: Err[0x%x]:Interrupted by signal.\n",
> > + dev_ctx->miscdev.name, err);
> > +
> > + header = *((struct se_msg_hdr *) (&dev_ctx->temp_resp[0]));
> > +
> > + if (header.tag == dev_ctx->priv->rsp_tag)
> > + mutex_unlock(&dev_ctx->priv->se_if_cmd_lock);
> > +
> > + return err;
> > +}
> > +
> > +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
> > + void *tx_msg, int tx_msg_sz)
> > +{
> > + struct se_if_priv *priv = dev_ctx->priv;
> > + struct se_msg_hdr header = {0};
> > + int err;
> > +
> > + header = *((struct se_msg_hdr *) tx_msg);
> > +
> > + /*
> > + * Check that the size passed as argument matches the size
> > + * carried in the message.
> > + */
> > + err = header.size << 2;
> > +
> > + if (err != tx_msg_sz) {
> > + err = -EINVAL;
> > + dev_err(priv->dev,
> > + "%s: User buffer too small\n",
> > + dev_ctx->miscdev.name);
> > + goto exit;
> > + }
> > + /* Check the message is valid according to tags */
> > + if (header.tag == priv->cmd_tag)
> > + priv->waiting_rsp_dev = dev_ctx;
> > + else if (header.tag == priv->rsp_tag) {
> > + /* Check the device context can send the command */
> > + if (dev_ctx != priv->cmd_receiver_dev) {
> > + dev_err(priv->dev,
> > + "%s: Channel not configured to send resp to
> FW.",
> > + dev_ctx->miscdev.name);
> > + err = -EPERM;
> > + goto exit;
> > + }
> > + } else {
> > + dev_err(priv->dev,
> > + "%s: The message does not have a valid TAG\n",
> > + dev_ctx->miscdev.name);
> > + err = -EINVAL;
> > + goto exit;
> > + }
> > + err = imx_ele_msg_send(priv, tx_msg);
> > +exit:
> > + return err;
> > +}
> > +
> > +/*
> > + * Callback called by mailbox FW, when data is received.
> > + */
> > +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg)
> > +{
> > + struct device *dev = mbox_cl->dev;
> > + struct se_if_device_ctx *dev_ctx;
> > + struct se_api_msg *rx_msg;
> > + bool is_response = false;
> > + struct se_if_priv *priv;
> > + struct se_msg_hdr header;
> > +
> > + priv = dev_get_drvdata(dev);
> > + if (!priv) {
> > + dev_err(dev, "SE-MU Priv data is NULL;");
> > + return;
> > + }
> > +
> > + /* The function can be called with NULL msg */
> > + if (!msg) {
> > + dev_err(dev, "Message is invalid\n");
> > + return;
> > + }
> > +
> > + header.tag = ((u8 *)msg)[TAG_OFFSET];
> > + header.command = ((u8 *)msg)[CMD_OFFSET];
> > + header.size = ((u8 *)msg)[SZ_OFFSET];
> > + header.ver = ((u8 *)msg)[VER_OFFSET];
> > +
> > + /* Incoming command: wake up the receiver if any. */
> > + if (header.tag == priv->cmd_tag) {
> > + dev_dbg(dev, "Selecting cmd receiver\n");
> > + dev_ctx = priv->cmd_receiver_dev;
> > + } else if (header.tag == priv->rsp_tag) {
> > + if (priv->waiting_rsp_dev) {
> > + dev_dbg(dev, "Selecting rsp waiter\n");
> > + dev_ctx = priv->waiting_rsp_dev;
> > + is_response = true;
> > + } else {
> > + /*
> > + * Reading the EdgeLock Enclave response
> > + * to the command, sent by other
> > + * linux kernel services.
> > + */
> > + spin_lock(&priv->lock);
> > + memcpy(&priv->rx_msg, msg, header.size << 2);
> > +
> > + complete(&priv->done);
> > + spin_unlock(&priv->lock);
> > + return;
> > + }
> > + } else {
> > + dev_err(dev, "Failed to select a device for message: %.8x\n",
> > + *((u32 *) &header));
> > + return;
> > + }
> > + /* Init reception */
> > + rx_msg = kzalloc(header.size << 2, GFP_KERNEL);
> > + if (rx_msg)
> > + memcpy(rx_msg, msg, header.size << 2);
> > +
> > + dev_ctx->temp_resp = (u32 *)rx_msg;
> > + dev_ctx->temp_resp_size = header.size;
> > +
> > + /* Allow user to read */
> > + dev_ctx->pending_hdr = 1;
> > + wake_up_interruptible(&dev_ctx->wq);
> > +
> > + if (is_response)
> > + priv->waiting_rsp_dev = NULL;
> > +}
> > +
> > +int validate_rsp_hdr(struct se_if_priv *priv, u32 header,
> > + uint8_t msg_id, uint8_t sz, bool is_base_api)
> > +{
> > + int ret = -EINVAL;
> > + u32 size;
> > + u32 cmd;
> > + u32 tag;
> > + u32 ver;
> > +
> > + tag = MSG_TAG(header);
> > + cmd = MSG_COMMAND(header);
> > + size = MSG_SIZE(header);
> > + ver = MSG_VER(header);
> > +
> > + do {
> > + if (tag != priv->rsp_tag) {
> > + dev_err(priv->dev,
> > + "MSG[0x%x] Hdr: Resp tag mismatch.
> (0x%x != 0x%x)",
> > + msg_id, tag, priv->rsp_tag);
> > + break;
> > + }
> > +
> > + if (cmd != msg_id) {
> > + dev_err(priv->dev,
> > + "MSG Header: Cmd id mismatch. (0x%x !=
> 0x%x)",
> > + cmd, msg_id);
> > + break;
> > + }
> > +
> > + if (size != (sz >> 2)) {
> > + dev_err(priv->dev,
> > + "MSG[0x%x] Hdr: Cmd size mismatch.
> (0x%x != 0x%x)",
> > + msg_id, size, (sz >> 2));
> > + break;
> > + }
> > +
> > + if (is_base_api && (ver != priv->base_api_ver)) {
> > + dev_err(priv->dev,
> > + "MSG[0x%x] Hdr: Base API Vers mismatch.
> (0x%x != 0x%x)",
> > + msg_id, ver, priv->base_api_ver);
> > + break;
> > + } else if (!is_base_api && ver != priv->fw_api_ver) {
> > + dev_err(priv->dev,
> > + "MSG[0x%x] Hdr: FW API Vers mismatch.
> (0x%x != 0x%x)",
> > + msg_id, ver, priv->fw_api_ver);
> > + break;
> > + }
> > +
> > + ret = 0;
> > +
> > + } while (false);
> > +
> > + return ret;
> > +}
> > +
> > +int se_save_imem_state(struct device *dev)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + int ret;
> > +
> > + /* EXPORT command will save encrypted IMEM to given address,
> > + * so later in resume, IMEM can be restored from the given
> > + * address.
> > + *
> > + * Size must be at least 64 kB.
> > + */
> > + ret = ele_service_swap(dev,
> > + priv->imem.phyaddr,
> > + ELE_IMEM_SIZE,
> > + ELE_IMEM_EXPORT);
> > + if (ret < 0)
> > + dev_err(dev, "Failed to export IMEM\n");
> > + else
> > + dev_info(dev,
> > + "Exported %d bytes of encrypted IMEM\n",
> > + ret);
> > +
> > + return ret;
> > +}
> > +
> > +int se_restore_imem_state(struct device *dev)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + struct soc_info s_info;
> > + int ret;
> > +
> > + /* get info from ELE */
> > + ret = ele_get_info(dev, &s_info);
> > + if (ret) {
> > + dev_err(dev, "Failed to get info from ELE.\n");
> > + return ret;
> > + }
> > +
> > + /* Get IMEM state, if 0xFE then import IMEM */
> > + if (s_info.imem_state == ELE_IMEM_STATE_BAD) {
> > + /* IMPORT command will restore IMEM from the given
> > + * address, here size is the actual size returned by ELE
> > + * during the export operation
> > + */
> > + ret = ele_service_swap(dev,
> > + priv->imem.phyaddr,
> > + priv->imem.size,
> > + ELE_IMEM_IMPORT);
> > + if (ret) {
> > + dev_err(dev, "Failed to import IMEM\n");
> > + goto exit;
> > + }
> > + } else
> > + goto exit;
> > +
> > + /* After importing IMEM, check if IMEM state is equal to 0xCA
> > + * to ensure IMEM is fully loaded and
> > + * ELE functionality can be used.
> > + */
> > + ret = ele_get_info(dev, &s_info);
> > + if (ret) {
> > + dev_err(dev, "Failed to get info from ELE.\n");
> > + goto exit;
> > + }
> > +
> > + if (s_info.imem_state == ELE_IMEM_STATE_OK)
> > + dev_info(dev, "Successfully restored IMEM\n");
> > + else
> > + dev_err(dev, "Failed to restore IMEM\n");
> > +
> > +exit:
> > + return ret;
> > +}
> > diff --git a/drivers/firmware/imx/ele_common.h
> b/drivers/firmware/imx/ele_common.h
> > new file mode 100644
> > index 000000000000..6e3a2114bb56
> > --- /dev/null
> > +++ b/drivers/firmware/imx/ele_common.h
> > @@ -0,0 +1,43 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +
> > +#ifndef __ELE_COMMON_H__
> > +#define __ELE_COMMON_H__
> > +
> > +#include "se_ctrl.h"
> > +
> > +#define IMX_ELE_FW_DIR "imx/ele/"
> > +
> > +uint32_t plat_add_msg_crc(uint32_t *msg, uint32_t msg_len);
> > +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *priv);
> > +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
> > + void *tx_msg, int tx_msg_sz);
> > +int imx_ele_msg_rcv(struct se_if_priv *priv);
> > +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg);
> > +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg);
> > +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg);
> > +int validate_rsp_hdr(struct se_if_priv *priv, unsigned int header,
> > + u8 msg_id, u8 sz, bool is_base_api);
> > +
> > +/* Fill a command message header with a given command ID and length in
> bytes. */
> > +static inline int plat_fill_cmd_msg_hdr(struct se_if_priv *priv,
> > + struct se_msg_hdr *hdr,
> > + u8 cmd,
> > + u32 len,
> > + bool is_base_api)
> > +{
> > + hdr->tag = priv->cmd_tag;
> > + hdr->ver = (is_base_api) ? priv->base_api_ver : priv->fw_api_ver;
> > + hdr->command = cmd;
> > + hdr->size = len >> 2;
> > +
> > + return 0;
> > +}
> > +
> > +int se_save_imem_state(struct device *dev);
> > +int se_restore_imem_state(struct device *dev);
> > +
> > +#endif /*__ELE_COMMON_H__ */
> > diff --git a/drivers/firmware/imx/se_ctrl.c b/drivers/firmware/imx/se_ctrl.c
> > new file mode 100644
> > index 000000000000..11c5eaa7353f
> > --- /dev/null
> > +++ b/drivers/firmware/imx/se_ctrl.c
> > @@ -0,0 +1,1339 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#include <linux/completion.h>
> > +#include <linux/delay.h>
> > +#include <linux/dev_printk.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/errno.h>
> > +#include <linux/export.h>
> > +#include <linux/firmware.h>
> > +#include <linux/firmware/imx/se_api.h>
> > +#include <linux/genalloc.h>
> > +#include <linux/init.h>
> > +#include <linux/io.h>
> > +#include <linux/miscdevice.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/module.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/of_reserved_mem.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +#include <linux/string.h>
> > +#include <linux/sys_soc.h>
> > +#include <uapi/linux/se_ioctl.h>
> > +
> > +#include "ele_base_msg.h"
> > +#include "ele_common.h"
> > +#include "se_ctrl.h"
> > +
> > +#define RESERVED_DMA_POOL BIT(1)
> > +
> > +struct imx_se_node_info {
> > + u8 se_if_id;
> > + u8 se_if_did;
> > + u8 max_dev_ctx;
> > + u8 cmd_tag;
> > + u8 rsp_tag;
> > + u8 success_tag;
> > + u8 base_api_ver;
> > + u8 fw_api_ver;
> > + u8 *se_name;
> > + u8 *mbox_tx_name;
> > + u8 *mbox_rx_name;
> > + u8 *pool_name;
> > + u8 *fw_name_in_rfs;
> > + bool soc_register;
> > + bool reserved_dma_ranges;
> > + bool imem_mgmt;
> > +};
> > +
> > +struct imx_se_node_info_list {
> > + u8 num_mu;
> > + u16 soc_id;
> > + u16 soc_rev;
> > + struct imx_se_node_info info[];
> > +};
> > +
> > +static const struct imx_se_node_info_list imx8ulp_info = {
> > + .num_mu = 1,
> > + .soc_id = SOC_ID_OF_IMX8ULP,
> > + .info = {
> > + {
> > + .se_if_id = 2,
> > + .se_if_did = 7,
> > + .max_dev_ctx = 4,
> > + .cmd_tag = 0x17,
> > + .rsp_tag = 0xe1,
> > + .success_tag = 0xd6,
> > + .base_api_ver = MESSAGING_VERSION_6,
> > + .fw_api_ver = MESSAGING_VERSION_7,
> > + .se_name = "hsm1",
> > + .mbox_tx_name = "tx",
> > + .mbox_rx_name = "rx",
> > + .pool_name = "sram",
> > + .fw_name_in_rfs = IMX_ELE_FW_DIR\
> > + "mx8ulpa2ext-ahab-
> container.img",
> > + .soc_register = true,
> > + .reserved_dma_ranges = true,
> > + .imem_mgmt = true,
> > + },
> > + },
> > +};
> > +
> > +static const struct imx_se_node_info_list imx93_info = {
> > + .num_mu = 1,
> > + .soc_id = SOC_ID_OF_IMX93,
> > + .info = {
> > + {
> > + .se_if_id = 2,
> > + .se_if_did = 3,
> > + .max_dev_ctx = 4,
> > + .cmd_tag = 0x17,
> > + .rsp_tag = 0xe1,
> > + .success_tag = 0xd6,
> > + .base_api_ver = MESSAGING_VERSION_6,
> > + .fw_api_ver = MESSAGING_VERSION_7,
> > + .se_name = "hsm1",
> > + .mbox_tx_name = "tx",
> > + .mbox_rx_name = "rx",
> > + .reserved_dma_ranges = true,
> > + .imem_mgmt = true,
> > + .soc_register = true,
> > + },
> > + },
> > +};
> > +
> > +static const struct of_device_id se_match[] = {
> > + { .compatible = "fsl,imx8ulp-ele", .data = (void *)&imx8ulp_info},
> > + { .compatible = "fsl,imx93-ele", .data = (void *)&imx93_info},
> > + {},
> > +};
> > +
> > +static struct imx_se_node_info
> > + *get_imx_se_node_info(struct imx_se_node_info_list
> *info_list,
> > + const u32 idx)
> > +{
> > + if (idx < 0 || idx > info_list->num_mu)
> > + return NULL;
> > +
> > + return &info_list->info[idx];
> > +}
> > +
> > +void *get_phy_buf_mem_pool(struct device *dev,
> > + u8 *mem_pool_name,
> > + dma_addr_t *buf,
> > + u32 size)
> > +{
> > + struct device_node *of_node = dev->of_node;
> > + struct gen_pool *mem_pool;
> > +
> > + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> > + if (!mem_pool) {
> > + dev_err(dev,
> > + "Unable to get sram pool = %s\n",
> > + mem_pool_name);
> > + return 0;
> > + }
> > +
> > + return gen_pool_dma_alloc(mem_pool, size, buf);
> > +}
> > +
> > +void free_phybuf_mem_pool(struct device *dev,
> > + u8 *mem_pool_name,
> > + u32 *buf,
> > + u32 size)
> > +{
> > + struct device_node *of_node = dev->of_node;
> > + struct gen_pool *mem_pool;
> > +
> > + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> > + if (!mem_pool)
> > + dev_err(dev,
> > + "%s: Failed: Unable to get sram pool.\n",
> > + __func__);
> > +
> > + gen_pool_free(mem_pool, (u64)buf, size);
> > +}
> > +
> > +static int imx_fetch_soc_info(struct device *dev)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + struct imx_se_node_info_list *info_list;
> > + const struct imx_se_node_info *info;
> > + struct soc_device_attribute *attr;
> > + struct soc_device *sdev;
> > + struct soc_info s_info;
> > + int err = 0;
> > +
> > + info = priv->info;
> > + info_list = (struct imx_se_node_info_list *)
> > + device_get_match_data(dev->parent);
> > + if (info_list->soc_rev)
> > + return err;
> > +
> > + err = ele_get_info(dev, &s_info);
> > + if (err)
> > + s_info.major_ver = DEFAULT_IMX_SOC_VER;
> > +
> > + info_list->soc_rev = s_info.soc_rev;
> > +
> > + if (!info->soc_register)
> > + return 0;
> > +
> > + attr = devm_kzalloc(dev, sizeof(*attr), GFP_KERNEL);
> > + if (!attr)
> > + return -ENOMEM;
> > +
> > + if (s_info.minor_ver)
> > + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x.%x",
> > + s_info.major_ver,
> > + s_info.minor_ver);
> > + else
> > + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x",
> > + s_info.major_ver);
> > +
> > + switch (s_info.soc_id) {
> > + case SOC_ID_OF_IMX8ULP:
> > + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> > + "i.MX8ULP");
> > + break;
> > + case SOC_ID_OF_IMX93:
> > + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> > + "i.MX93");
> > + break;
> > + }
> > +
> > + err = of_property_read_string(of_root, "model",
> > + &attr->machine);
> > + if (err) {
> > + devm_kfree(dev, attr);
> > + return -EINVAL;
> > + }
> > + attr->family = devm_kasprintf(dev, GFP_KERNEL, "Freescale i.MX");
> > +
> > + attr->serial_number
> > + = devm_kasprintf(dev, GFP_KERNEL, "%016llX",
> s_info.serial_num);
> > +
> > + sdev = soc_device_register(attr);
> > + if (IS_ERR(sdev)) {
> > + devm_kfree(dev, attr->soc_id);
> > + devm_kfree(dev, attr->serial_number);
> > + devm_kfree(dev, attr->revision);
> > + devm_kfree(dev, attr->family);
> > + devm_kfree(dev, attr->machine);
> > + devm_kfree(dev, attr);
> > + return PTR_ERR(sdev);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * File operations for user-space
> > + */
> > +
> > +/* Write a message to the MU. */
> > +static ssize_t se_if_fops_write(struct file *fp, const char __user *buf,
> > + size_t size, loff_t *ppos)
> > +{
> > + struct se_api_msg *tx_msg __free(kfree);
> > + struct se_if_device_ctx *dev_ctx;
> > + struct se_if_priv *priv;
> > + int err;
> > +
> > + dev_ctx = container_of(fp->private_data,
> > + struct se_if_device_ctx,
> > + miscdev);
> > + priv = dev_ctx->priv;
> > + dev_dbg(priv->dev,
> > + "%s: write from buf (%p)%zu, ppos=%lld\n",
> > + dev_ctx->miscdev.name,
> > + buf, size, ((ppos) ? *ppos : 0));
> > +
> > + if (down_interruptible(&dev_ctx->fops_lock))
> > + return -EBUSY;
> > +
> > + if (dev_ctx->status != MU_OPENED) {
> > + err = -EINVAL;
> > + goto exit;
> > + }
> > +
> > + if (size < SE_MU_HDR_SZ) {
> > + dev_err(priv->dev,
> > + "%s: User buffer too small(%zu < %d)\n",
> > + dev_ctx->miscdev.name,
> > + size, SE_MU_HDR_SZ);
> > + err = -ENOSPC;
> > + goto exit;
> > + }
> > +
> > + tx_msg = memdup_user((void __user *)ppos, size);
> > + if (!tx_msg) {
> > + err = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > + /* Copy data to buffer */
> > + if (copy_from_user(tx_msg, buf, size)) {
> > + err = -EFAULT;
> > + dev_err(priv->dev,
> > + "%s: Fail copy message from user\n",
> > + dev_ctx->miscdev.name);
> > + goto exit;
> > + }
> > +
> > + print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4,
> > + tx_msg, size, false);
> > +
> > + err = imx_ele_miscdev_msg_send(dev_ctx, tx_msg, size);
> > +
> > +exit:
> > + up(&dev_ctx->fops_lock);
> > + return err;
> > +}
> > +
> > +/*
> > + * Read a message from the MU.
> > + * Blocking until a message is available.
> > + */
> > +static ssize_t se_if_fops_read(struct file *fp, char __user *buf,
> > + size_t size, loff_t *ppos)
> > +{
> > + struct se_if_device_ctx *dev_ctx;
> > + struct se_buf_desc *b_desc;
> > + struct se_if_priv *priv;
> > + u32 size_to_copy;
> > + int err;
> > +
> > + dev_ctx = container_of(fp->private_data,
> > + struct se_if_device_ctx,
> > + miscdev);
> > + priv = dev_ctx->priv;
> > + dev_dbg(priv->dev,
> > + "%s: read to buf %p(%zu), ppos=%lld\n",
> > + dev_ctx->miscdev.name,
> > + buf, size, ((ppos) ? *ppos : 0));
> > +
> > + if (down_interruptible(&dev_ctx->fops_lock))
> > + return -EBUSY;
> > +
> > + if (dev_ctx->status != MU_OPENED) {
> > + err = -EINVAL;
> > + goto exit;
> > + }
> > +
> > + err = imx_ele_miscdev_msg_rcv(dev_ctx);
> > + if (err)
> > + goto exit;
> > +
> > + /* Buffer containing the message from FW, is
> > + * allocated in callback function.
> > + * Check if buffer allocation failed.
> > + */
> > + if (!dev_ctx->temp_resp) {
> > + err = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > + dev_dbg(priv->dev,
> > + "%s: %s %s\n",
> > + dev_ctx->miscdev.name,
> > + __func__,
> > + "message received, start transmit to user");
> > +
> > + /*
> > + * Check that the size passed as argument is larger than
> > + * the one carried in the message.
> > + */
> > + size_to_copy = dev_ctx->temp_resp_size << 2;
> > + if (size_to_copy > size) {
> > + dev_dbg(priv->dev,
> > + "%s: User buffer too small (%zu < %d)\n",
> > + dev_ctx->miscdev.name,
> > + size, size_to_copy);
> > + size_to_copy = size;
> > + }
> > +
> > + /*
> > + * We may need to copy the output data to user before
> > + * delivering the completion message.
> > + */
> > + while (!list_empty(&dev_ctx->pending_out)) {
> > + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> > + struct se_buf_desc,
> > + link);
> > + if (!b_desc)
> > + continue;
> > +
> > + if (b_desc->usr_buf_ptr && b_desc->shared_buf_ptr) {
> > +
> > + dev_dbg(priv->dev,
> > + "%s: Copy output data to user\n",
> > + dev_ctx->miscdev.name);
> > + if (copy_to_user(b_desc->usr_buf_ptr,
> > + b_desc->shared_buf_ptr,
> > + b_desc->size)) {
> > + dev_err(priv->dev,
> > + "%s: Failure copying output data to
> user.",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > + }
> > +
> > + if (b_desc->shared_buf_ptr)
> > + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> > +
> > + __list_del_entry(&b_desc->link);
> > + kfree(b_desc);
> > + }
> > +
> > + /* Copy data from the buffer */
> > + print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4,
> > + dev_ctx->temp_resp, size_to_copy, false);
> > + if (copy_to_user(buf, dev_ctx->temp_resp, size_to_copy)) {
> > + dev_err(priv->dev,
> > + "%s: Failed to copy to user\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > +
> > + err = size_to_copy;
> > + kfree(dev_ctx->temp_resp);
> > +
> > + /* free memory allocated on the shared buffers. */
> > + dev_ctx->secure_mem.pos = 0;
> > + dev_ctx->non_secure_mem.pos = 0;
> > +
> > + dev_ctx->pending_hdr = 0;
> > +
> > +exit:
> > + /*
> > + * Clean the used Shared Memory space,
> > + * whether its Input Data copied from user buffers, or
> > + * Data received from FW.
> > + */
> > + while (!list_empty(&dev_ctx->pending_in) ||
> > + !list_empty(&dev_ctx->pending_out)) {
> > + if (!list_empty(&dev_ctx->pending_in))
> > + b_desc = list_first_entry_or_null(&dev_ctx-
> >pending_in,
> > + struct se_buf_desc,
> > + link);
> > + else
> > + b_desc = list_first_entry_or_null(&dev_ctx-
> >pending_out,
> > + struct se_buf_desc,
> > + link);
> > +
> > + if (!b_desc)
> > + continue;
> > +
> > + if (b_desc->shared_buf_ptr)
> > + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> > +
> > + __list_del_entry(&b_desc->link);
> > + kfree(b_desc);
> > + }
> > +
> > + up(&dev_ctx->fops_lock);
> > + return err;
> > +}
> > +
> > +/* Give access to EdgeLock Enclave, to the memory we want to share */
> > +static int se_if_setup_se_mem_access(struct se_if_device_ctx *dev_ctx,
> > + u64 addr, u32 len)
> > +{
> > + /* Assuming EdgeLock Enclave has access to all the memory regions
> */
> > + int ret = 0;
> > +
> > + if (ret) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Fail find memreg\n", dev_ctx->miscdev.name);
> > + goto exit;
> > + }
> > +
> > + if (ret) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Fail set permission for resource\n",
> > + dev_ctx->miscdev.name);
> > + goto exit;
> > + }
> > +
> > +exit:
> > + return ret;
> > +}
> > +
> > +static int se_ioctl_get_mu_info(struct se_if_device_ctx *dev_ctx,
> > + u64 arg)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev_ctx->dev);
> > + struct imx_se_node_info *if_node_info;
> > + struct se_ioctl_get_if_info info;
> > + int err = 0;
> > +
> > + if_node_info = (struct imx_se_node_info *)priv->info;
> > +
> > + info.se_if_id = if_node_info->se_if_id;
> > + info.interrupt_idx = 0;
> > + info.tz = 0;
> > + info.did = if_node_info->se_if_did;
> > + info.cmd_tag = if_node_info->cmd_tag;
> > + info.rsp_tag = if_node_info->rsp_tag;
> > + info.success_tag = if_node_info->success_tag;
> > + info.base_api_ver = if_node_info->base_api_ver;
> > + info.fw_api_ver = if_node_info->fw_api_ver;
> > +
> > + dev_dbg(priv->dev,
> > + "%s: info [se_if_id: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n",
> > + dev_ctx->miscdev.name,
> > + info.se_if_id, info.interrupt_idx, info.tz, info.did);
> > +
> > + if (copy_to_user((u8 *)arg, &info, sizeof(info))) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed to copy mu info to user\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > +
> > +exit:
> > + return err;
> > +}
> > +
> > +/*
> > + * Copy a buffer of data to/from the user and return the address to use in
> > + * messages
> > + */
> > +static int se_ioctl_setup_iobuf_handler(struct se_if_device_ctx *dev_ctx,
> > + u64 arg)
> > +{
> > + struct se_ioctl_setup_iobuf io = {0};
> > + struct se_shared_mem *shared_mem;
> > + struct se_buf_desc *b_desc;
> > + int err = 0;
> > + u32 pos;
> > +
> > + if (copy_from_user(&io, (u8 *)arg, sizeof(io))) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed copy iobuf config from user\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > +
> > + dev_dbg(dev_ctx->priv->dev,
> > + "%s: io [buf: %p(%d) flag: %x]\n",
> > + dev_ctx->miscdev.name,
> > + io.user_buf, io.length, io.flags);
> > +
> > + if (io.length == 0 || !io.user_buf) {
> > + /*
> > + * Accept NULL pointers since some buffers are optional
> > + * in FW commands. In this case we should return 0 as
> > + * pointer to be embedded into the message.
> > + * Skip all data copy part of code below.
> > + */
> > + io.ele_addr = 0;
> > + goto copy;
> > + }
> > +
> > + /* Select the shared memory to be used for this buffer. */
> > + if (io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) {
> > + /* App requires to use secure memory for this buffer.*/
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed allocate SEC MEM memory\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + } else {
> > + /* No specific requirement for this buffer. */
> > + shared_mem = &dev_ctx->non_secure_mem;
> > + }
> > +
> > + /* Check there is enough space in the shared memory. */
> > + if (shared_mem->size < shared_mem->pos
> > + || io.length >= shared_mem->size - shared_mem-
> >pos) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Not enough space in shared memory\n",
> > + dev_ctx->miscdev.name);
> > + err = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > + /* Allocate space in shared memory. 8 bytes aligned. */
> > + pos = shared_mem->pos;
> > + shared_mem->pos += round_up(io.length, 8u);
> > + io.ele_addr = (u64)shared_mem->dma_addr + pos;
> > +
> > + if ((io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) &&
> > + !(io.flags & SE_MU_IO_FLAGS_USE_SHORT_ADDR)) {
> > + /*Add base address to get full address.*/
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed allocate SEC MEM memory\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > +
> > + memset(shared_mem->ptr + pos, 0, io.length);
> > + if ((io.flags & SE_IO_BUF_FLAGS_IS_INPUT) ||
> > + (io.flags & SE_IO_BUF_FLAGS_IS_IN_OUT)) {
> > + /*
> > + * buffer is input:
> > + * copy data from user space to this allocated buffer.
> > + */
> > + if (copy_from_user(shared_mem->ptr + pos, io.user_buf,
> > + io.length)) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed copy data to shared memory\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > + }
> > +
> > + b_desc = kzalloc(sizeof(*b_desc), GFP_KERNEL);
> > + if (!b_desc) {
> > + err = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > +copy:
> > + /* Provide the EdgeLock Enclave address to user space only if
> success.*/
> > + if (copy_to_user((u8 *)arg, &io, sizeof(io))) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed to copy iobuff setup to user\n",
> > + dev_ctx->miscdev.name);
> > + kfree(b_desc);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > +
> > + if (b_desc) {
> > + b_desc->shared_buf_ptr = shared_mem->ptr + pos;
> > + b_desc->usr_buf_ptr = io.user_buf;
> > + b_desc->size = io.length;
> > +
> > + if (io.flags & SE_IO_BUF_FLAGS_IS_INPUT) {
> > + /*
> > + * buffer is input:
> > + * add an entry in the "pending input buffers" list so
> > + * that copied data can be cleaned from shared
> memory
> > + * later.
> > + */
> > + list_add_tail(&b_desc->link, &dev_ctx->pending_in);
> > + } else {
> > + /*
> > + * buffer is output:
> > + * add an entry in the "pending out buffers" list so
> data
> > + * can be copied to user space when receiving Secure-
> Enclave
> > + * response.
> > + */
> > + list_add_tail(&b_desc->link, &dev_ctx->pending_out);
> > + }
> > + }
> > +
> > +exit:
> > + return err;
> > +}
> > +
> > +/* IOCTL to provide SoC information */
> > +static int se_ioctl_get_soc_info_handler(struct se_if_device_ctx *dev_ctx,
> > + u64 arg)
> > +{
> > + struct imx_se_node_info_list *info_list;
> > + struct se_ioctl_get_soc_info soc_info;
> > + int err = -EINVAL;
> > +
> > + info_list = (struct imx_se_node_info_list *)
> > + device_get_match_data(dev_ctx->priv->dev-
> >parent);
> > + if (!info_list)
> > + goto exit;
> > +
> > + soc_info.soc_id = info_list->soc_id;
> > + soc_info.soc_rev = info_list->soc_rev;
> > +
> > + err = (int)copy_to_user((u8 *)arg, (u8 *)(&soc_info), sizeof(soc_info));
> > + if (err) {
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed to copy soc info to user\n",
> > + dev_ctx->miscdev.name);
> > + err = -EFAULT;
> > + goto exit;
> > + }
> > +
> > +exit:
> > + return err;
> > +}
> > +
> > +/* Open a character device. */
> > +static int se_if_fops_open(struct inode *nd, struct file *fp)
> > +{
> > + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> > + struct
> se_if_device_ctx,
> > + miscdev);
> > + int err;
> > +
> > + /* Avoid race if opened at the same time */
> > + if (down_trylock(&dev_ctx->fops_lock))
> > + return -EBUSY;
> > +
> > + /* Authorize only 1 instance. */
> > + if (dev_ctx->status != MU_FREE) {
> > + err = -EBUSY;
> > + goto exit;
> > + }
> > +
> > + /*
> > + * Allocate some memory for data exchanges with S40x.
> > + * This will be used for data not requiring secure memory.
> > + */
> > + dev_ctx->non_secure_mem.ptr = dmam_alloc_coherent(dev_ctx-
> >dev,
> > + MAX_DATA_SIZE_PER_USER,
> > + &dev_ctx-
> >non_secure_mem.dma_addr,
> > + GFP_KERNEL);
> > + if (!dev_ctx->non_secure_mem.ptr) {
> > + err = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > + err = se_if_setup_se_mem_access(dev_ctx,
> > + dev_ctx-
> >non_secure_mem.dma_addr,
> > + MAX_DATA_SIZE_PER_USER);
> > + if (err) {
> > + err = -EPERM;
> > + dev_err(dev_ctx->priv->dev,
> > + "%s: Failed to share access to shared memory\n",
> > + dev_ctx->miscdev.name);
> > + goto free_coherent;
> > + }
> > +
> > + dev_ctx->non_secure_mem.size = MAX_DATA_SIZE_PER_USER;
> > + dev_ctx->non_secure_mem.pos = 0;
> > + dev_ctx->status = MU_OPENED;
> > +
> > + dev_ctx->pending_hdr = 0;
> > +
> > + goto exit;
> > +
> > +free_coherent:
> > + dmam_free_coherent(dev_ctx->priv->dev,
> MAX_DATA_SIZE_PER_USER,
> > + dev_ctx->non_secure_mem.ptr,
> > + dev_ctx->non_secure_mem.dma_addr);
> > +
> > +exit:
> > + up(&dev_ctx->fops_lock);
> > + return err;
> > +}
> > +
> > +/* Close a character device. */
> > +static int se_if_fops_close(struct inode *nd, struct file *fp)
> > +{
> > + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> > + struct
> se_if_device_ctx,
> > + miscdev);
> > + struct se_if_priv *priv = dev_ctx->priv;
> > + struct se_buf_desc *b_desc;
> > +
> > + /* Avoid race if closed at the same time */
> > + if (down_trylock(&dev_ctx->fops_lock))
> > + return -EBUSY;
> > +
> > + /* The device context has not been opened */
> > + if (dev_ctx->status != MU_OPENED)
> > + goto exit;
> > +
> > + /* check if this device was registered as command receiver. */
> > + if (priv->cmd_receiver_dev == dev_ctx)
> > + priv->cmd_receiver_dev = NULL;
> > +
> > + /* check if this device was registered as waiting response. */
> > + if (priv->waiting_rsp_dev == dev_ctx) {
> > + priv->waiting_rsp_dev = NULL;
> > + mutex_unlock(&priv->se_if_cmd_lock);
> > + }
> > +
> > + /* Unmap secure memory shared buffer. */
> > + if (dev_ctx->secure_mem.ptr)
> > + devm_iounmap(dev_ctx->dev, dev_ctx->secure_mem.ptr);
> > +
> > + dev_ctx->secure_mem.ptr = NULL;
> > + dev_ctx->secure_mem.dma_addr = 0;
> > + dev_ctx->secure_mem.size = 0;
> > + dev_ctx->secure_mem.pos = 0;
> > +
> > + /* Free non-secure shared buffer. */
> > + dmam_free_coherent(dev_ctx->priv->dev,
> MAX_DATA_SIZE_PER_USER,
> > + dev_ctx->non_secure_mem.ptr,
> > + dev_ctx->non_secure_mem.dma_addr);
> > +
> > + dev_ctx->non_secure_mem.ptr = NULL;
> > + dev_ctx->non_secure_mem.dma_addr = 0;
> > + dev_ctx->non_secure_mem.size = 0;
> > + dev_ctx->non_secure_mem.pos = 0;
> > +
> > + while (!list_empty(&dev_ctx->pending_in) ||
> > + !list_empty(&dev_ctx->pending_out)) {
> > + if (!list_empty(&dev_ctx->pending_in))
> > + b_desc = list_first_entry_or_null(&dev_ctx-
> >pending_in,
> > + struct se_buf_desc,
> > + link);
> > + else
> > + b_desc = list_first_entry_or_null(&dev_ctx-
> >pending_out,
> > + struct se_buf_desc,
> > + link);
> > +
> > + if (!b_desc)
> > + continue;
> > +
> > + if (b_desc->shared_buf_ptr)
> > + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> > +
> > + __list_del_entry(&b_desc->link);
> > + devm_kfree(dev_ctx->dev, b_desc);
> > + }
> > +
> > + dev_ctx->status = MU_FREE;
> > +
> > +exit:
> > + up(&dev_ctx->fops_lock);
> > + return 0;
> > +}
> > +
> > +/* IOCTL entry point of a character device */
> > +static long se_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
> > +//static long se_ioctl(struct file *fp, u32 cmd, u64 arg)
> > +{
> > + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> > + struct
> se_if_device_ctx,
> > + miscdev);
> > + struct se_if_priv *se_if_priv = dev_ctx->priv;
> > + int err = -EINVAL;
> > +
> > + /* Prevent race during change of device context */
> > + if (down_interruptible(&dev_ctx->fops_lock))
> > + return -EBUSY;
> > +
> > + switch (cmd) {
> > + case SE_IOCTL_ENABLE_CMD_RCV:
> > + if (!se_if_priv->cmd_receiver_dev) {
> > + se_if_priv->cmd_receiver_dev = dev_ctx;
> > + err = 0;
> > + }
> > + break;
> > + case SE_IOCTL_GET_MU_INFO:
> > + err = se_ioctl_get_mu_info(dev_ctx, arg);
> > + break;
> > + case SE_IOCTL_SETUP_IOBUF:
> > + err = se_ioctl_setup_iobuf_handler(dev_ctx, arg);
> > + break;
> > + case SE_IOCTL_GET_SOC_INFO:
> > + err = se_ioctl_get_soc_info_handler(dev_ctx, arg);
> > + break;
> > +
> > + default:
> > + err = -EINVAL;
> > + dev_dbg(se_if_priv->dev,
> > + "%s: IOCTL %.8x not supported\n",
> > + dev_ctx->miscdev.name,
> > + cmd);
> > + }
> > +
> > + up(&dev_ctx->fops_lock);
> > + return (long)err;
> > +}
> > +
> > +/* Char driver setup */
> > +static const struct file_operations se_if_fops = {
> > + .open = se_if_fops_open,
> > + .owner = THIS_MODULE,
> > + .release = se_if_fops_close,
> > + .unlocked_ioctl = se_ioctl,
> > + .read = se_if_fops_read,
> > + .write = se_if_fops_write,
> > +};
> > +
> > +/* interface for managed res to free a mailbox channel */
> > +static void if_mbox_free_channel(void *mbox_chan)
> > +{
> > + mbox_free_channel(mbox_chan);
> > +}
> > +
> > +/* interface for managed res to unregister a character device */
> > +static void if_misc_deregister(void *miscdevice)
> > +{
> > + misc_deregister(miscdevice);
> > +}
> > +
> > +static int se_if_request_channel(struct device *dev,
> > + struct mbox_chan **chan,
> > + struct mbox_client *cl,
> > + const u8 *name)
> > +{
> > + struct mbox_chan *t_chan;
> > + int ret = 0;
> > +
> > + t_chan = mbox_request_channel_byname(cl, name);
> > + if (IS_ERR(t_chan)) {
> > + ret = PTR_ERR(t_chan);
> > + if (ret != -EPROBE_DEFER)
> > + dev_err(dev,
> > + "Failed to request chan %s ret %d\n", name,
> > + ret);
> > + goto exit;
> > + }
> > +
> > + ret = devm_add_action(dev, if_mbox_free_channel, t_chan);
> > + if (ret) {
> > + dev_err(dev, "failed to add devm removal of mbox %s\n",
> name);
> > + goto exit;
> > + }
> > +
> > + *chan = t_chan;
> > +
> > +exit:
> > + return ret;
> > +}
> > +
> > +static int se_probe_if_cleanup(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct se_if_priv *priv;
> > + int ret = 0;
> > + int i;
> > +
> > + priv = dev_get_drvdata(dev);
> > + if (!priv) {
> > + ret = 0;
> > + dev_dbg(dev, "SE-MU Priv data is NULL;");
> > + return ret;
> > + }
> > +
> > + if (priv->tx_chan)
> > + mbox_free_channel(priv->tx_chan);
> > + if (priv->rx_chan)
> > + mbox_free_channel(priv->rx_chan);
> > +
> > + /* free the buffer in se remove, previously allocated
> > + * in se probe to store encrypted IMEM
> > + */
> > + if (priv->imem.buf) {
> > + dmam_free_coherent(dev,
> > + ELE_IMEM_SIZE,
> > + priv->imem.buf,
> > + priv->imem.phyaddr);
> > + priv->imem.buf = NULL;
> > + }
> > +
> > + if (priv->ctxs) {
> > + for (i = 0; i < priv->max_dev_ctx; i++) {
> > + if (priv->ctxs[i]) {
> > + devm_remove_action(dev,
> > + if_misc_deregister,
> > + &priv->ctxs[i]->miscdev);
> > + misc_deregister(&priv->ctxs[i]->miscdev);
> > + devm_kfree(dev, priv->ctxs[i]);
> > + }
> > + }
> > + devm_kfree(dev, priv->ctxs);
> > + }
> > +
> > + if (priv->flags & RESERVED_DMA_POOL) {
> > + of_reserved_mem_device_release(dev);
> > + priv->flags &= (~RESERVED_DMA_POOL);
> > + }
> > +
> > + devm_kfree(dev, priv);
> > + of_node_put(dev->of_node);
> > + of_platform_device_destroy(dev, NULL);
> > +
> > + return ret;
> > +}
> > +
> > +static int se_probe_cleanup(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *if_dn;
> > +
> > + /* Enumerate se-interface device nodes. */
> > + for_each_child_of_node(dev->of_node, if_dn) {
> > + struct platform_device *if_pdev
> > + = of_find_device_by_node(if_dn);
> > + if (se_probe_if_cleanup(if_pdev))
> > + dev_err(dev,
> > + "Failed to clean-up child node probe.\n");
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int init_device_context(struct device *dev)
> > +{
> > + const struct imx_se_node_info *info;
> > + struct se_if_device_ctx *dev_ctx;
> > + struct se_if_priv *priv;
> > + u8 *devname;
> > + int ret = 0;
> > + int i;
> > +
> > + priv = dev_get_drvdata(dev);
> > +
> > + if (!priv) {
> > + ret = -EINVAL;
> > + dev_err(dev, "Invalid SE-MU Priv data");
> > + return ret;
> > + }
> > + info = priv->info;
> > +
> > + priv->ctxs = devm_kzalloc(dev, sizeof(dev_ctx) * priv->max_dev_ctx,
> > + GFP_KERNEL);
> > +
> > + if (!priv->ctxs) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + /* Create users */
> > + for (i = 0; i < priv->max_dev_ctx; i++) {
> > + dev_ctx = devm_kzalloc(dev, sizeof(*dev_ctx), GFP_KERNEL);
> > + if (!dev_ctx) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + dev_ctx->dev = dev;
> > + dev_ctx->status = MU_FREE;
> > + dev_ctx->priv = priv;
> > +
> > + priv->ctxs[i] = dev_ctx;
> > +
> > + /* Default value invalid for an header. */
> > + init_waitqueue_head(&dev_ctx->wq);
> > +
> > + INIT_LIST_HEAD(&dev_ctx->pending_out);
> > + INIT_LIST_HEAD(&dev_ctx->pending_in);
> > + sema_init(&dev_ctx->fops_lock, 1);
> > +
> > + devname = devm_kasprintf(dev, GFP_KERNEL, "%s_ch%d",
> > + info->se_name, i);
> > + if (!devname) {
> > + ret = -ENOMEM;
> > + return ret;
> > + }
> > +
> > + dev_ctx->miscdev.name = devname;
> > + dev_ctx->miscdev.minor = MISC_DYNAMIC_MINOR;
> > + dev_ctx->miscdev.fops = &se_if_fops;
> > + dev_ctx->miscdev.parent = dev;
> > + ret = misc_register(&dev_ctx->miscdev);
> > + if (ret) {
> > + dev_err(dev, "failed to register misc device %d\n",
> > + ret);
> > + return ret;
> > + }
> > +
> > + ret = devm_add_action(dev, if_misc_deregister,
> > + &dev_ctx->miscdev);
> > + if (ret) {
> > + dev_err(dev,
> > + "failed[%d] to add action to the misc-dev\n",
> > + ret);
> > + return ret;
> > + }
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static void se_load_firmware(const struct firmware *fw, void *context)
> > +{
> > + struct se_if_priv *priv = (struct se_if_priv *) context;
> > + const struct imx_se_node_info *info = priv->info;
> > + const u8 *se_fw_name = info->fw_name_in_rfs;
> > + phys_addr_t se_fw_phyaddr;
> > + u8 *se_fw_buf;
> > +
> > + if (!fw) {
> > + if (priv->fw_fail > MAX_FW_LOAD_RETRIES)
> > + dev_dbg(priv->dev,
> > + "External FW not found, using ROM FW.\n");
> > + else {
> > + /*add a bit delay to wait for firmware priv released */
> > + msleep(20);
> > +
> > + /* Load firmware one more time if timeout */
> > + request_firmware_nowait(THIS_MODULE,
> > + FW_ACTION_UEVENT, info-
> >fw_name_in_rfs,
> > + priv->dev, GFP_KERNEL, priv,
> > + se_load_firmware);
> > + priv->fw_fail++;
> > + dev_dbg(priv->dev, "Value of retries = 0x%x.\n",
> > + priv->fw_fail);
> > + }
> > +
> > + return;
> > + }
> > +
> > + /* allocate buffer to store the SE FW */
> > + se_fw_buf = dmam_alloc_coherent(priv->dev, fw->size,
> > + &se_fw_phyaddr,
> > + GFP_KERNEL);
> > + if (!se_fw_buf) {
> > + dev_err(priv->dev, "Failed to alloc SE fw buffer memory\n");
> > + goto exit;
> > + }
> > +
> > + memcpy(se_fw_buf, fw->data, fw->size);
> > +
> > + if (ele_fw_authenticate(priv->dev, se_fw_phyaddr))
> > + dev_err(priv->dev,
> > + "Failed to authenticate & load SE firmware %s.\n",
> > + se_fw_name);
> > +
> > +exit:
> > + dmam_free_coherent(priv->dev,
> > + fw->size,
> > + se_fw_buf,
> > + se_fw_phyaddr);
> > +
> > + release_firmware(fw);
> > +}
> > +
> > +static int se_if_probe(struct platform_device *pdev)
> > +{
> > + struct imx_se_node_info_list *info_list;
> > + struct device *dev = &pdev->dev;
> > + struct imx_se_node_info *info;
> > + struct se_if_priv *priv;
> > + u32 idx;
> > + int ret;
> > +
> > + if (of_property_read_u32(dev->of_node, "reg", &idx)) {
> > + ret = -EINVAL;
> > + goto exit;
> > + }
> > +
> > + info_list = (struct imx_se_node_info_list *)
> > + device_get_match_data(dev->parent);
> > + info = get_imx_se_node_info(info_list, idx);
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv) {
> > + ret = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > + dev_set_drvdata(dev, priv);
> > +
> > + /* Mailbox client configuration */
> > + priv->se_mb_cl.dev = dev;
> > + priv->se_mb_cl.tx_block = false;
> > + priv->se_mb_cl.knows_txdone = true;
> > + priv->se_mb_cl.rx_callback = se_if_rx_callback;
> > +
> > + ret = se_if_request_channel(dev, &priv->tx_chan,
> > + &priv->se_mb_cl, info->mbox_tx_name);
> > + if (ret) {
> > + if (ret == -EPROBE_DEFER)
> > + dev_err(dev, "Mailbox tx channel, is not ready.\n");
> > + else
> > + dev_err(dev, "Failed to request tx channel\n");
> > +
> > + goto exit;
> > + }
> > +
> > + ret = se_if_request_channel(dev, &priv->rx_chan,
> > + &priv->se_mb_cl, info->mbox_rx_name);
> > + if (ret) {
> > + if (ret == -EPROBE_DEFER)
> > + dev_err(dev, "Mailbox rx channel, is not ready.\n");
> > + else
> > + dev_dbg(dev, "Failed to request rx channel\n");
> > +
> > + goto exit;
> > + }
> > +
> > + priv->dev = dev;
> > + priv->info = info;
> > +
> > + /* Initialize the mutex. */
> > + mutex_init(&priv->se_if_lock);
> > + mutex_init(&priv->se_if_cmd_lock);
> > +
> > + priv->cmd_receiver_dev = NULL;
> > + priv->waiting_rsp_dev = NULL;
> > + priv->max_dev_ctx = info->max_dev_ctx;
> > + priv->cmd_tag = info->cmd_tag;
> > + priv->rsp_tag = info->rsp_tag;
> > + priv->mem_pool_name = info->pool_name;
> > + priv->success_tag = info->success_tag;
> > + priv->base_api_ver = info->base_api_ver;
> > + priv->fw_api_ver = info->fw_api_ver;
> > +
> > + init_completion(&priv->done);
> > + spin_lock_init(&priv->lock);
> > +
> > + if (info->reserved_dma_ranges) {
> > + ret = of_reserved_mem_device_init(dev);
> > + if (ret) {
> > + dev_err(dev,
> > + "failed to init reserved memory region %d\n",
> > + ret);
> > + priv->flags &= (~RESERVED_DMA_POOL);
> > + goto exit;
> > + }
> > + priv->flags |= RESERVED_DMA_POOL;
> > + }
> > +
> > + if (info->fw_name_in_rfs) {
> > + ret = request_firmware_nowait(THIS_MODULE,
> > + FW_ACTION_UEVENT,
> > + info->fw_name_in_rfs,
> > + dev, GFP_KERNEL, priv,
> > + se_load_firmware);
> > + if (ret)
> > + dev_warn(dev, "Failed to get firmware [%s].\n",
> > + info->fw_name_in_rfs);
> > + }
> > +
> > + ret = imx_fetch_soc_info(dev);
> > + if (ret) {
> > + dev_err(dev,
> > + "failed[%d] to fetch SoC Info\n", ret);
> > + goto exit;
> > + }
> > +
> > + if (info->imem_mgmt) {
> > + /* allocate buffer where SE store encrypted IMEM */
> > + priv->imem.buf = dmam_alloc_coherent(dev,
> ELE_IMEM_SIZE,
> > + &priv->imem.phyaddr,
> > + GFP_KERNEL);
> > + if (!priv->imem.buf) {
> > + dev_err(dev,
> > + "dmam-alloc-failed: To store encr-IMEM.\n");
> > + ret = -ENOMEM;
> > + goto exit;
> > + }
> > + }
> > +
> > + if (info->max_dev_ctx) {
> > + ret = init_device_context(dev);
> > + if (ret) {
> > + dev_err(dev,
> > + "Failed[0x%x] to create device contexts.\n",
> > + ret);
> > + goto exit;
> > + }
> > + }
> > +
> > + dev_info(dev, "i.MX secure-enclave: %s interface to firmware,
> configured.\n",
> > + info->se_name);
> > + return devm_of_platform_populate(dev);
> > +
> > +exit:
> > + /* if execution control reaches here, if probe fails.
> > + * hence doing the cleanup
> > + */
> > + if (se_probe_if_cleanup(pdev))
> > + dev_err(dev,
> > + "Failed to clean-up the child node probe.\n");
> > +
> > + return ret;
> > +}
> > +
> > +static int se_probe(struct platform_device *pdev)
> > +{
> > + struct device_node *enum_dev_node;
> > + struct device *dev = &pdev->dev;
> > + int enum_count;
> > + int ret;
> > +
> > + enum_count = of_get_child_count(dev->of_node);
> > + if (!enum_count) {
> > + ret = -EINVAL;
> > + dev_err(dev, "Zero Tx/Rx path MU nodes.\n");
> > + return ret;
> > + }
> > +
> > + for_each_child_of_node(dev->of_node, enum_dev_node) {
> > + struct platform_device *enum_plat_dev __maybe_unused;
> > +
> > + if (!of_device_is_available(enum_dev_node))
> > + continue;
> > +
> > + enum_plat_dev =
> of_platform_device_create(enum_dev_node,
> > + NULL,
> > + dev);
> > + if (!enum_plat_dev) {
> > + ret = -EINVAL;
> > + of_node_put(enum_dev_node);
> > + dev_err(dev,
> > + "Failed to create enumerated platform
> device.");
> > + break;
> > + }
> > +
> > + ret = se_if_probe(enum_plat_dev);
> > + }
> > + return ret;
> > +}
> > +
> > +static int se_remove(struct platform_device *pdev)
> > +{
> > + if (se_probe_cleanup(pdev))
> > + dev_err(&pdev->dev,
> > + "i.MX Secure Enclave is not cleanly un-probed.");
> > +
> > + return 0;
> > +}
> > +
> > +static int se_suspend(struct device *dev)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + const struct imx_se_node_info *info
> > + = priv->info;
> > +
> > + if (info && info->imem_mgmt)
> > + priv->imem.size = se_save_imem_state(dev);
> > +
> > + return 0;
> > +}
> > +
> > +static int se_resume(struct device *dev)
> > +{
> > + struct se_if_priv *priv = dev_get_drvdata(dev);
> > + const struct imx_se_node_info *info
> > + = priv->info;
> > + int i;
> > +
> > + for (i = 0; i < priv->max_dev_ctx; i++)
> > + wake_up_interruptible(&priv->ctxs[i]->wq);
> > +
> > + if (info && info->imem_mgmt)
> > + se_restore_imem_state(dev);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct dev_pm_ops se_pm = {
> > + RUNTIME_PM_OPS(se_suspend, se_resume, NULL)
> > +};
> > +
> > +static struct platform_driver se_driver = {
> > + .driver = {
> > + .name = "fsl-se-fw",
> > + .of_match_table = se_match,
> > + .pm = &se_pm,
> > + },
> > + .probe = se_probe,
> > + .remove = se_remove,
> > +};
> > +MODULE_DEVICE_TABLE(of, se_match);
> > +
> > +module_platform_driver(se_driver);
> > +
> > +MODULE_AUTHOR("Pankaj Gupta <pankaj.gupta@nxp.com>");
> > +MODULE_DESCRIPTION("iMX Secure Enclave Driver.");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/firmware/imx/se_ctrl.h b/drivers/firmware/imx/se_ctrl.h
> > new file mode 100644
> > index 000000000000..76e1ce77c52f
> > --- /dev/null
> > +++ b/drivers/firmware/imx/se_ctrl.h
> > @@ -0,0 +1,151 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#ifndef SE_MU_H
> > +#define SE_MU_H
> > +
> > +#include <linux/miscdevice.h>
> > +#include <linux/semaphore.h>
> > +#include <linux/mailbox_client.h>
> > +
> > +#define MAX_FW_LOAD_RETRIES 50
> > +
> > +#define MSG_TAG(x) (((x) & 0xff000000) >> 24)
> > +#define MSG_COMMAND(x) (((x) & 0x00ff0000) >> 16)
> > +#define MSG_SIZE(x) (((x) & 0x0000ff00) >> 8)
> > +#define MSG_VER(x) ((x) & 0x000000ff)
> > +#define RES_STATUS(x) ((x) & 0x000000ff)
> > +#define MAX_DATA_SIZE_PER_USER (65 * 1024)
> > +#define S4_DEFAULT_MUAP_INDEX (2)
> > +#define S4_MUAP_DEFAULT_MAX_USERS (4)
> > +#define MESSAGING_VERSION_6 0x6
> > +#define MESSAGING_VERSION_7 0x7
> > +
> > +#define DEFAULT_MESSAGING_TAG_COMMAND (0x17u)
> > +#define DEFAULT_MESSAGING_TAG_RESPONSE (0xe1u)
> > +
> > +#define SE_MU_IO_FLAGS_USE_SEC_MEM (0x02u)
> > +#define SE_MU_IO_FLAGS_USE_SHORT_ADDR (0x04u)
> > +
> > +struct se_imem_buf {
> > + u8 *buf;
> > + phys_addr_t phyaddr;
> > + u32 size;
> > +};
> > +
> > +struct se_buf_desc {
> > + u8 *shared_buf_ptr;
> > + u8 *usr_buf_ptr;
> > + u32 size;
> > + struct list_head link;
> > +};
> > +
> > +/* Status of a char device */
> > +enum se_if_dev_ctx_status_t {
> > + MU_FREE,
> > + MU_OPENED
> > +};
> > +
> > +struct se_shared_mem {
> > + dma_addr_t dma_addr;
> > + u32 size;
> > + u32 pos;
> > + u8 *ptr;
> > +};
> > +
> > +/* Private struct for each char device instance. */
> > +struct se_if_device_ctx {
> > + struct device *dev;
> > + struct se_if_priv *priv;
> > + struct miscdevice miscdev;
> > +
> > + enum se_if_dev_ctx_status_t status;
> > + wait_queue_head_t wq;
> > + struct semaphore fops_lock;
> > +
> > + u32 pending_hdr;
> > + struct list_head pending_in;
> > + struct list_head pending_out;
> > +
> > + struct se_shared_mem secure_mem;
> > + struct se_shared_mem non_secure_mem;
> > +
> > + u32 *temp_resp;
> > + u32 temp_resp_size;
> > + struct notifier_block se_notify;
> > +};
> > +
> > +/* Header of the messages exchange with the EdgeLock Enclave */
> > +struct se_msg_hdr {
> > + u8 ver;
> > + u8 size;
> > + u8 command;
> > + u8 tag;
> > +} __packed;
> > +
> > +#define SE_MU_HDR_SZ 4
> > +#define TAG_OFFSET (SE_MU_HDR_SZ - 1)
> > +#define CMD_OFFSET (SE_MU_HDR_SZ - 2)
> > +#define SZ_OFFSET (SE_MU_HDR_SZ - 3)
> > +#define VER_OFFSET (SE_MU_HDR_SZ - 4)
> > +
> > +struct se_api_msg {
> > + u32 header; /* u8 Tag; u8 Command; u8 Size; u8 Ver; */
> > + u32 *data;
> > +};
> > +
> > +struct se_if_priv {
> > + struct se_if_device_ctx *cmd_receiver_dev;
> > + struct se_if_device_ctx *waiting_rsp_dev;
> > + bool no_dev_ctx_used;
> > + /*
> > + * prevent parallel access to the se interface registers
> > + * e.g. a user trying to send a command while the other one is
> > + * sending a response.
> > + */
> > + struct mutex se_if_lock;
> > + /*
> > + * prevent a command to be sent on the se interface while another
> one is
> > + * still processing. (response to a command is allowed)
> > + */
> > + struct mutex se_if_cmd_lock;
> > + struct device *dev;
> > + u8 *mem_pool_name;
> > + u8 cmd_tag;
> > + u8 rsp_tag;
> > + u8 success_tag;
> > + u8 base_api_ver;
> > + u8 fw_api_ver;
> > + u32 fw_fail;
> > + const void *info;
> > +
> > + struct mbox_client se_mb_cl;
> > + struct mbox_chan *tx_chan, *rx_chan;
> > + struct se_api_msg *rx_msg;
> > + struct completion done;
> > + spinlock_t lock;
> > + /*
> > + * Flag to retain the state of initialization done at
> > + * the time of se-mu probe.
> > + */
> > + uint32_t flags;
> > + u8 max_dev_ctx;
> > + struct se_if_device_ctx **ctxs;
> > + struct se_imem_buf imem;
> > +};
> > +
> > +void *get_phy_buf_mem_pool(struct device *dev,
> > + u8 *mem_pool_name,
> > + dma_addr_t *buf,
> > + u32 size);
> > +phys_addr_t get_phy_buf_mem_pool1(struct device *dev,
> > + u8 *mem_pool_name,
> > + u32 **buf,
> > + u32 size);
> > +void free_phybuf_mem_pool(struct device *dev,
> > + u8 *mem_pool_name,
> > + u32 *buf,
> > + u32 size);
> > +#endif
> > diff --git a/include/linux/firmware/imx/se_api.h
> b/include/linux/firmware/imx/se_api.h
> > new file mode 100644
> > index 000000000000..c47f84906837
> > --- /dev/null
> > +++ b/include/linux/firmware/imx/se_api.h
> > @@ -0,0 +1,14 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#ifndef __SE_API_H__
> > +#define __SE_API_H__
> > +
> > +#include <linux/types.h>
> > +
> > +#define SOC_ID_OF_IMX8ULP 0x084D
> > +#define SOC_ID_OF_IMX93 0x9300
> > +
> > +#endif /* __SE_API_H__ */
> > diff --git a/include/uapi/linux/se_ioctl.h b/include/uapi/linux/se_ioctl.h
> > new file mode 100644
> > index 000000000000..f68a36e9da2c
> > --- /dev/null
> > +++ b/include/uapi/linux/se_ioctl.h
> > @@ -0,0 +1,88 @@
> > +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-
> Clause*/
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#ifndef SE_IOCTL_H
> > +#define SE_IOCTL_H
> > +
> > +/* IOCTL definitions. */
> > +
> > +struct se_ioctl_setup_iobuf {
> > + u8 *user_buf;
> > + u32 length;
> > + u32 flags;
> > + u64 ele_addr;
> > +};
> > +
> > +struct se_ioctl_shared_mem_cfg {
> > + u32 base_offset;
> > + u32 size;
> > +};
> > +
> > +struct se_ioctl_get_if_info {
> > + u8 se_if_id;
> > + u8 interrupt_idx;
> > + u8 tz;
> > + u8 did;
> > + u8 cmd_tag;
> > + u8 rsp_tag;
> > + u8 success_tag;
> > + u8 base_api_ver;
> > + u8 fw_api_ver;
> > +};
> > +
> > +struct se_ioctl_signed_message {
> > + u8 *message;
> > + u32 msg_size;
> > + u32 error_code;
> > +};
> > +
> > +struct se_ioctl_get_soc_info {
> > + u16 soc_id;
> > + u16 soc_rev;
> > +};
> > +
> > +/* IO Buffer Flags */
> > +#define SE_IO_BUF_FLAGS_IS_OUTPUT (0x00u)
> > +#define SE_IO_BUF_FLAGS_IS_INPUT (0x01u)
> > +#define SE_IO_BUF_FLAGS_USE_SEC_MEM (0x02u)
> > +#define SE_IO_BUF_FLAGS_USE_SHORT_ADDR (0x04u)
> > +#define SE_IO_BUF_FLAGS_IS_IN_OUT (0x10u)
> > +
> > +/* IOCTLS */
> > +#define SE_IOCTL 0x0A /* like MISC_MAJOR. */
> > +
> > +/*
> > + * ioctl to designated the current fd as logical-reciever.
> > + * This is ioctl is send when the nvm-daemon, a slave to the
> > + * firmware is started by the user.
> > + */
> > +#define SE_IOCTL_ENABLE_CMD_RCV _IO(SE_IOCTL, 0x01)
> > +
> > +/*
> > + * ioctl to get the buffer allocated from the memory, which is shared
> > + * between kernel and FW.
> > + * Post allocation, the kernel tagged the allocated memory with:
> > + * Output
> > + * Input
> > + * Input-Output
> > + * Short address
> > + * Secure-memory
> > + */
> > +#define SE_IOCTL_SETUP_IOBUF _IOWR(SE_IOCTL, 0x03, \
> > + struct se_ioctl_setup_iobuf)
> > +
> > +/*
> > + * ioctl to get the mu information, that is used to exchange message
> > + * with FW, from user-spaced.
> > + */
> > +#define SE_IOCTL_GET_MU_INFO _IOR(SE_IOCTL, 0x04, \
> > + struct se_ioctl_get_if_info)
> > +/*
> > + * ioctl to get SoC Info from user-space.
> > + */
> > +#define SE_IOCTL_GET_SOC_INFO _IOR(SE_IOCTL, 0x06, \
> > + struct se_ioctl_get_soc_info)
> > +
> > +#endif
> >
> > --
> > 2.34.1
> >
_______________________________________________
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^ permalink raw reply [relevance 0%]
* [PATCH v5 2/2] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support
@ 2024-05-13 1:22 6% ` Richard Zhu
0 siblings, 0 replies; 200+ results
From: Richard Zhu @ 2024-05-13 1:22 UTC (permalink / raw)
To: conor, vkoul, kishon, robh+dt, krzysztof.kozlowski+dt, frank.li,
conor+dt
Cc: hongxing.zhu, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, kernel, imx
Add i.MX8QM HSIO PHY driver support.
i.MX8QM HSIO has three lane PHY instances, and can be bound to the
following controllers in the different use cases listed in below table.
- two lanes capable PCIEA controller.
- one lane PCIEB controller.
- AHCI SATA controller.
i.MX8QM HSIO PHYs support the following use cases.
+----------------------------------------------------+
| | Lane0| Lane1| Lane2|
|-------------------------------|------|------|------|
| use case 1: PCIEAX2SATA | PCIEA| PCIEA| SATA |
|-------------------------------|------|------|------|
| use case 2: PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB|
|-------------------------------|------|------|------|
| use case 3: PCIEAPCIEBSATA | PCIEA| PCIEB| SATA |
+----------------------------------------------------+
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/phy/freescale/Kconfig | 8 +
drivers/phy/freescale/Makefile | 1 +
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 608 ++++++++++++++++++++
3 files changed, 617 insertions(+)
create mode 100644 drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index 853958fb2c06..c9ee48aeea9e 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -35,6 +35,14 @@ config PHY_FSL_IMX8M_PCIE
Enable this to add support for the PCIE PHY as found on
i.MX8M family of SOCs.
+config PHY_FSL_IMX8QM_HSIO
+ tristate "Freescale i.MX8QM HSIO PHY"
+ depends on OF && HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Enable this to add support for the HSIO PHY as found on
+ i.MX8QM family of SOCs.
+
endif
config PHY_FSL_LYNX_28G
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index cedb328bc4d2..b56b4d5c18ea 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
+obj-$(CONFIG_PHY_FSL_IMX8QM_HSIO) += phy-fsl-imx8qm-hsio.o
obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
new file mode 100644
index 000000000000..bb3c377cbf27
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
@@ -0,0 +1,608 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pci_regs.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/pcie.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#define MAX_NUM_LANE 3
+#define LANE_NUM_CLKS 5
+
+/* Parameters for the waiting for PCIe PHY PLL to lock */
+#define PHY_INIT_WAIT_USLEEP_MAX 10
+#define PHY_INIT_WAIT_TIMEOUT (1000 * PHY_INIT_WAIT_USLEEP_MAX)
+
+/* i.MX8Q HSIO registers */
+#define HSIO_CTRL0 0x0
+#define HSIO_APB_RSTN_0 BIT(0)
+#define HSIO_APB_RSTN_1 BIT(1)
+#define HSIO_PIPE_RSTN_0_MASK GENMASK(25, 24)
+#define HSIO_PIPE_RSTN_1_MASK GENMASK(27, 26)
+#define HSIO_MODE_MASK GENMASK(20, 17)
+#define HSIO_MODE_PCIE 0x0
+#define HSIO_MODE_SATA 0x4
+#define HSIO_DEVICE_TYPE_MASK GENMASK(27, 24)
+#define HSIO_EPCS_TXDEEMP BIT(5)
+#define HSIO_EPCS_TXDEEMP_SEL BIT(6)
+#define HSIO_EPCS_PHYRESET_N BIT(7)
+#define HSIO_RESET_N BIT(12)
+
+#define HSIO_IOB_RXENA BIT(0)
+#define HSIO_IOB_TXENA BIT(1)
+#define HSIO_IOB_A_0_TXOE BIT(2)
+#define HSIO_IOB_A_0_M1M0_2 BIT(4)
+#define HSIO_IOB_A_0_M1M0_MASK GENMASK(4, 3)
+#define HSIO_PHYX1_EPCS_SEL BIT(12)
+#define HSIO_PCIE_AB_SELECT BIT(13)
+
+#define HSIO_PHY_STS0 0x4
+#define HSIO_LANE0_TX_PLL_LOCK BIT(4)
+#define HSIO_LANE1_TX_PLL_LOCK BIT(12)
+
+#define HSIO_CTRL2 0x8
+#define HSIO_LTSSM_ENABLE BIT(4)
+#define HSIO_BUTTON_RST_N BIT(21)
+#define HSIO_PERST_N BIT(22)
+#define HSIO_POWER_UP_RST_N BIT(23)
+
+#define HSIO_PCIE_STS0 0xc
+#define HSIO_PM_REQ_CORE_RST BIT(19)
+
+#define HSIO_REG48_PMA_STATUS 0x30
+#define HSIO_REG48_PMA_RDY BIT(7)
+
+struct imx_hsio_drvdata {
+ int lane_num;
+};
+
+struct imx_hsio_lane {
+ u32 ctrl_index;
+ u32 ctrl_off;
+ u32 idx;
+ u32 phy_off;
+ u32 phy_type;
+ const char * const *clk_names;
+ struct clk_bulk_data clks[LANE_NUM_CLKS];
+ struct imx_hsio_priv *priv;
+ struct phy *phy;
+ enum phy_mode phy_mode;
+};
+
+struct imx_hsio_priv {
+ void __iomem *base;
+ struct device *dev;
+ struct mutex lock;
+ const char *refclk_pad;
+ u32 hsio_cfg;
+ u32 open_cnt;
+ struct regmap *phy;
+ struct regmap *ctrl;
+ struct regmap *misc;
+ const struct imx_hsio_drvdata *drvdata;
+ struct imx_hsio_lane lane[MAX_NUM_LANE];
+};
+
+static const char * const lan0_pcie_clks[] = {"apb_pclk0", "pclk0", "ctl0_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan1_pciea_clks[] = {"apb_pclk1", "pclk1", "ctl0_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan1_pcieb_clks[] = {"apb_pclk1", "pclk1", "ctl1_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan2_pcieb_clks[] = {"apb_pclk2", "pclk2", "ctl1_crr",
+ "phy1_crr", "misc_crr"};
+static const char * const lan2_sata_clks[] = {"pclk2", "epcs_tx", "epcs_rx",
+ "phy1_crr", "misc_crr"};
+
+static const struct regmap_config regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int imx_hsio_init(struct phy *phy)
+{
+ int ret, i;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+ struct device *dev = priv->dev;
+
+ /* Assign clocks refer to different modes */
+ switch (lane->phy_type) {
+ case PHY_TYPE_PCIE:
+ lane->phy_mode = PHY_MODE_PCIE;
+ if (lane->ctrl_index == 0) { /* PCIEA */
+ lane->ctrl_off = 0;
+ lane->phy_off = 0;
+
+ for (i = 0; i < LANE_NUM_CLKS; i++) {
+ if (lane->idx == 0)
+ lane->clks[i].id = lan0_pcie_clks[i];
+ else
+ lane->clks[i].id = lan1_pciea_clks[i];
+ }
+ } else { /* PCIEB */
+ if (lane->idx == 0) { /* i.MX8QXP */
+ lane->ctrl_off = 0;
+ lane->phy_off = 0;
+ } else {
+ /*
+ * On i.MX8QM, only second or third lane can be
+ * bound to PCIEB.
+ */
+ lane->ctrl_off = SZ_64K;
+ if (lane->idx == 1)
+ lane->phy_off = 0;
+ else /* the third lane is bound to PCIEB */
+ lane->phy_off = SZ_64K;
+ }
+
+ for (i = 0; i < LANE_NUM_CLKS; i++) {
+ if (lane->idx == 1)
+ lane->clks[i].id = lan1_pcieb_clks[i];
+ else if (lane->idx == 2)
+ lane->clks[i].id = lan2_pcieb_clks[i];
+ else /* i.MX8QXP only has PCIEB, idx is 0 */
+ lane->clks[i].id = lan0_pcie_clks[i];
+ }
+ }
+ break;
+ case PHY_TYPE_SATA:
+ /* On i.MX8QM, only the third lane can be bound to SATA */
+ lane->phy_mode = PHY_MODE_SATA;
+ lane->ctrl_off = SZ_128K;
+ lane->phy_off = SZ_64K;
+
+ for (i = 0; i < LANE_NUM_CLKS; i++)
+ lane->clks[i].id = lan2_sata_clks[i];
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Fetch clocks and enable them */
+ ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, lane->clks);
+ if (ret)
+ return ret;
+ ret = clk_bulk_prepare_enable(LANE_NUM_CLKS, lane->clks);
+ if (ret)
+ return ret;
+
+ /* allow the clocks to stabilize */
+ usleep_range(200, 500);
+ return 0;
+}
+
+static int imx_hsio_exit(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+
+ clk_bulk_disable_unprepare(LANE_NUM_CLKS, lane->clks);
+
+ return 0;
+}
+
+static void imx_hsio_pcie_phy_resets(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+
+ if (lane->idx == 1) {
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_1);
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_1_MASK);
+ } else {
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_0);
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_0_MASK);
+ }
+}
+
+static void imx_hsio_sata_phy_resets(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ /* clear PHY RST, then set it */
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_PHYRESET_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_PHYRESET_N);
+
+ /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
+ udelay(1);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_RESET_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
+}
+
+static void imx_hsio_configure_clk_pad(struct phy *phy)
+{
+ bool pll = false;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (strncmp(priv->refclk_pad, "output", 6) == 0) {
+ pll = true;
+ regmap_update_bits(priv->misc, HSIO_CTRL0,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_2);
+ } else {
+ regmap_update_bits(priv->misc, HSIO_CTRL0,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
+ 0);
+ }
+
+ regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_RXENA,
+ pll ? 0 : HSIO_IOB_RXENA);
+ regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_TXENA,
+ pll ? HSIO_IOB_TXENA : 0);
+}
+
+static void imx_hsio_pre_set(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2PCIEB)
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
+ if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2SATA)
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
+
+ imx_hsio_configure_clk_pad(phy);
+}
+
+static int imx_hsio_pcie_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, addr, cond;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ imx_hsio_pcie_phy_resets(phy);
+
+ /* Toggle apb_pclk to make sure PM_REQ_CORE_RST is cleared. */
+ clk_disable_unprepare(lane->clks[0].clk);
+ mdelay(1);
+ ret = clk_prepare_enable(lane->clks[0].clk);
+ if (ret) {
+ dev_err(priv->dev, "unable to enable phy apb_pclk\n");
+ return ret;
+ }
+
+ addr = lane->ctrl_off + HSIO_PCIE_STS0;
+ cond = HSIO_PM_REQ_CORE_RST;
+ ret = regmap_read_poll_timeout(priv->ctrl, addr, val,
+ (val & cond) == 0,
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT);
+ if (ret)
+ dev_err(priv->dev, "HSIO_PM_REQ_CORE_RST is set\n");
+ return ret;
+}
+
+static int imx_hsio_sata_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, cond;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0, HSIO_APB_RSTN_0);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP_SEL);
+
+ imx_hsio_sata_phy_resets(phy);
+
+ cond = HSIO_REG48_PMA_RDY;
+ ret = read_poll_timeout(readb, val, ((val & cond) == cond),
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT, false,
+ priv->base + HSIO_REG48_PMA_STATUS);
+ if (ret)
+ dev_err(priv->dev, "PHY calibration is timeout\n");
+ else
+ dev_dbg(priv->dev, "PHY calibration is done\n");
+
+ return ret;
+}
+
+static int imx_hsio_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, cond;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ scoped_guard(mutex, &priv->lock) {
+ if (!priv->open_cnt)
+ imx_hsio_pre_set(phy);
+ priv->open_cnt++;
+ }
+
+ if (lane->phy_mode == PHY_MODE_PCIE)
+ ret = imx_hsio_pcie_power_on(phy);
+ else /* SATA */
+ ret = imx_hsio_sata_power_on(phy);
+ if (ret)
+ return ret;
+
+ /* Polling to check the PHY is ready or not. */
+ if (lane->idx == 1)
+ cond = HSIO_LANE1_TX_PLL_LOCK;
+ else
+ /*
+ * Except the phy_off, the bit-offset of lane2 is same to lane0.
+ * Merge the lane0 and lane2 bit-operations together.
+ */
+ cond = HSIO_LANE0_TX_PLL_LOCK;
+
+ ret = regmap_read_poll_timeout(priv->phy, lane->phy_off + HSIO_PHY_STS0,
+ val, ((val & cond) == cond),
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT);
+ if (ret) {
+ dev_err(priv->dev, "IMX8Q PHY%d PLL lock timeout\n", lane->idx);
+ return ret;
+ }
+ dev_dbg(priv->dev, "IMX8Q PHY%d PLL is locked\n", lane->idx);
+
+ return ret;
+}
+
+static int imx_hsio_power_off(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ scoped_guard(mutex, &priv->lock) {
+ priv->open_cnt--;
+ if (priv->open_cnt == 0) {
+ regmap_clear_bits(priv->misc, HSIO_CTRL0,
+ HSIO_PCIE_AB_SELECT);
+ regmap_clear_bits(priv->misc, HSIO_CTRL0,
+ HSIO_PHYX1_EPCS_SEL);
+
+ if (lane->phy_mode == PHY_MODE_PCIE) {
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+ } else {
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP_SEL);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL0,
+ HSIO_RESET_N);
+ }
+
+ if (lane->idx == 1) {
+ regmap_clear_bits(priv->phy,
+ lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_1);
+ regmap_clear_bits(priv->phy,
+ lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_1_MASK);
+ } else {
+ /*
+ * Except the phy_off, the bit-offset of lane2 is same
+ * to lane0. Merge the lane0 and lane2 bit-operations
+ * together.
+ */
+ regmap_clear_bits(priv->phy,
+ lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_0);
+ regmap_clear_bits(priv->phy,
+ lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_0_MASK);
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int imx_hsio_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ u32 val;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (lane->phy_mode != mode)
+ return -EINVAL;
+
+ val = (mode == PHY_MODE_PCIE) ? HSIO_MODE_PCIE : HSIO_MODE_SATA;
+ val = FIELD_PREP(HSIO_MODE_MASK, val);
+ regmap_update_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_MODE_MASK, val);
+
+ switch (submode) {
+ case PHY_MODE_PCIE_RC:
+ val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
+ break;
+ case PHY_MODE_PCIE_EP:
+ val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ENDPOINT);
+ break;
+ default: /* Support only PCIe EP and RC now. */
+ return 0;
+ }
+ if (submode)
+ regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_DEVICE_TYPE_MASK, val);
+
+ return 0;
+}
+
+static int imx_hsio_set_speed(struct phy *phy, int speed)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_LTSSM_ENABLE,
+ speed ? HSIO_LTSSM_ENABLE : 0);
+ return 0;
+}
+
+static const struct phy_ops imx_hsio_ops = {
+ .init = imx_hsio_init,
+ .exit = imx_hsio_exit,
+ .power_on = imx_hsio_power_on,
+ .power_off = imx_hsio_power_off,
+ .set_mode = imx_hsio_set_mode,
+ .set_speed = imx_hsio_set_speed,
+ .owner = THIS_MODULE,
+};
+
+static const struct imx_hsio_drvdata imx8qxp_hsio_drvdata = {
+ .lane_num = 0x1,
+};
+
+static const struct imx_hsio_drvdata imx_hsio_drvdata = {
+ .lane_num = 0x3,
+};
+
+static const struct of_device_id imx_hsio_of_match[] = {
+ {.compatible = "fsl,imx8qm-hsio", .data = &imx_hsio_drvdata},
+ {.compatible = "fsl,imx8qxp-hsio", .data = &imx8qxp_hsio_drvdata},
+ { },
+};
+MODULE_DEVICE_TABLE(of, imx_hsio_of_match);
+
+static struct phy *imx_hsio_xlate(struct device *dev,
+ const struct of_phandle_args *args)
+{
+ struct imx_hsio_priv *priv = dev_get_drvdata(dev);
+ int idx = args->args[0];
+ int phy_type = args->args[1];
+ int ctrl_index = args->args[2];
+
+ if (idx < 0 || idx >= priv->drvdata->lane_num)
+ return ERR_PTR(-EINVAL);
+ priv->lane[idx].idx = idx;
+ priv->lane[idx].phy_type = phy_type;
+ priv->lane[idx].ctrl_index = ctrl_index;
+
+ return priv->lane[idx].phy;
+}
+
+static int imx_hsio_probe(struct platform_device *pdev)
+{
+ int i;
+ void __iomem *off;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct imx_hsio_priv *priv;
+ struct phy_provider *provider;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ priv->dev = &pdev->dev;
+ priv->drvdata = of_device_get_match_data(dev);
+
+ /* Get HSIO configuration mode */
+ if (of_property_read_u32(np, "fsl,hsio-cfg", &priv->hsio_cfg))
+ priv->hsio_cfg = 0;
+ /* Get PHY refclk pad mode */
+ if (of_property_read_string(np, "fsl,refclk-pad-mode",
+ &priv->refclk_pad))
+ priv->refclk_pad = NULL;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ off = devm_platform_ioremap_resource_byname(pdev, "phy");
+ priv->phy = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->phy))
+ return dev_err_probe(dev, PTR_ERR(priv->phy),
+ "unable to find phy csr registers\n");
+
+ off = devm_platform_ioremap_resource_byname(pdev, "ctrl");
+ priv->ctrl = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->ctrl))
+ return dev_err_probe(dev, PTR_ERR(priv->ctrl),
+ "unable to find ctrl csr registers\n");
+
+ off = devm_platform_ioremap_resource_byname(pdev, "misc");
+ priv->misc = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->misc))
+ return dev_err_probe(dev, PTR_ERR(priv->misc),
+ "unable to find misc csr registers\n");
+
+ for (i = 0; i < priv->drvdata->lane_num; i++) {
+ struct imx_hsio_lane *lane = &priv->lane[i];
+ struct phy *phy;
+
+ memset(lane, 0, sizeof(*lane));
+
+ phy = devm_phy_create(&pdev->dev, NULL, &imx_hsio_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ lane->priv = priv;
+ lane->phy = phy;
+ lane->idx = i;
+ phy_set_drvdata(phy, lane);
+ }
+
+ dev_set_drvdata(dev, priv);
+ dev_set_drvdata(&pdev->dev, priv);
+
+ provider = devm_of_phy_provider_register(&pdev->dev, imx_hsio_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver imx_hsio_driver = {
+ .probe = imx_hsio_probe,
+ .driver = {
+ .name = "imx8qm-hsio-phy",
+ .of_match_table = imx_hsio_of_match,
+ }
+};
+module_platform_driver(imx_hsio_driver);
+
+MODULE_DESCRIPTION("FSL IMX8QM HSIO SERDES PHY driver");
+MODULE_LICENSE("GPL");
--
2.37.1
_______________________________________________
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^ permalink raw reply related [relevance 6%]
* Re: [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave
2024-05-10 16:41 0% ` Frank Li
@ 2024-05-10 19:39 0% ` Amit Singh Tomar
2024-05-13 9:16 0% ` [EXT] " Pankaj Gupta
2024-05-13 9:12 0% ` Pankaj Gupta
1 sibling, 1 reply; 200+ results
From: Amit Singh Tomar @ 2024-05-10 19:39 UTC (permalink / raw)
To: Frank Li, Pankaj Gupta
Cc: Jonathan Corbet, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
linux-doc, linux-kernel, devicetree, imx, linux-arm-kernel
Hi,
>
> ----------------------------------------------------------------------
> On Fri, May 10, 2024 at 06:57:30PM +0530, Pankaj Gupta wrote:
>> NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE),
>> are embedded in the SoC to support the features like HSM, SHE & V2X,
>> using message based communication interface.
>>
>> The secure enclave FW communicates on a dedicated messaging unit(MU)
>> based interface(s) with application core, where kernel is running.
>> It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
>>
>> This patch adds the driver for communication interface to secure-enclave,
>> for exchanging messages with NXP secure enclave HW IP(s) like EdgeLock Enclave,
>> both from:
>> - User-Space Applications via character driver.
>> - Kernel-space, used by kernel management layers like DM-Crypt.
>>
>> ABI documentation for the NXP secure-enclave driver.
>>
>> User-space library using this driver:
>> - i.MX Secure Enclave library:
>> -- URL: https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_nxp-2Dimx_imx-2Dsecure-2Denclave.git&d=DwICAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=V_GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-JKU&m=eKFfdy51aVVEAe4I9Lk2CN77y_4Hxf2pI_9fv5pVWLo9DwQNgCpca6smAwvwFycf&s=IfKbvjSfdUcqz-WEWdhbj1_TnqGryOffX1dV0T5Rf_A&e= ,
>> - i.MX Secure Middle-Ware:
>> -- URL: https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_nxp-2Dimx_imx-2Dsmw.git&d=DwICAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=V_GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-JKU&m=eKFfdy51aVVEAe4I9Lk2CN77y_4Hxf2pI_9fv5pVWLo9DwQNgCpca6smAwvwFycf&s=LLz2plXTM1AS-zJ1HlZRKiBE8GmRJBduR_0dnOuFjRo&e=
>>
>> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
>> ---
>> Documentation/ABI/testing/se-cdev | 42 ++
>> drivers/firmware/imx/Kconfig | 12 +
>> drivers/firmware/imx/Makefile | 2 +
>> drivers/firmware/imx/ele_base_msg.c | 287 ++++++++
>> drivers/firmware/imx/ele_base_msg.h | 70 ++
>> drivers/firmware/imx/ele_common.c | 341 +++++++++
>> drivers/firmware/imx/ele_common.h | 43 ++
>> drivers/firmware/imx/se_ctrl.c | 1339 +++++++++++++++++++++++++++++++++++
>> drivers/firmware/imx/se_ctrl.h | 151 ++++
>> include/linux/firmware/imx/se_api.h | 14 +
>> include/uapi/linux/se_ioctl.h | 88 +++
>> 11 files changed, 2389 insertions(+)
>>
>> diff --git a/Documentation/ABI/testing/se-cdev b/Documentation/ABI/testing/se-cdev
>> new file mode 100644
>> index 000000000000..699525af6b86
>> --- /dev/null
>> +++ b/Documentation/ABI/testing/se-cdev
>> @@ -0,0 +1,42 @@
>> +What: /dev/<se>_mu[0-9]+_ch[0-9]+
>> +Date: May 2024
>> +KernelVersion: 6.8
>> +Contact: linux-imx@nxp.com, pankaj.gupta@nxp.com
>> +Description:
>> + NXP offers multiple hardware IP(s) for secure-enclaves like EdgeLock-
>> + Enclave(ELE), SECO. The character device file-descriptors
>> + /dev/<se>_mu*_ch* are the interface between user-space NXP's secure-
>> + enclave shared-library and the kernel driver.
>> +
>> + The ioctl(2)-based ABI is defined and documented in
>> + [include]<linux/firmware/imx/ele_mu_ioctl.h>
>> + ioctl(s) are used primarily for:
>> + - shared memory management
>> + - allocation of I/O buffers
>> + - get mu info
>> + - setting a dev-ctx as receiver that is slave to fw
>> + - get SoC info
>> +
>> + The following file operations are supported:
>> +
>> + open(2)
>> + Currently the only useful flags are O_RDWR.
>> +
>> + read(2)
>> + Every read() from the opened character device context is waiting on
>> + wakeup_intruptible, that gets set by the registered mailbox callback
>> + function; indicating a message received from the firmware on message-
>> + unit.
>> +
>> + write(2)
>> + Every write() to the opened character device context needs to acquire
>> + mailbox_lock, before sending message on to the message unit.
>> +
>> + close(2)
>> + Stops and free up the I/O contexts that was associated
>> + with the file descriptor.
>> +
>> +Users: https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_nxp-2Dimx_imx-2Dsecure-2Denclave.git&d=DwICAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=V_GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-JKU&m=eKFfdy51aVVEAe4I9Lk2CN77y_4Hxf2pI_9fv5pVWLo9DwQNgCpca6smAwvwFycf&s=IfKbvjSfdUcqz-WEWdhbj1_TnqGryOffX1dV0T5Rf_A&e= ,
>> + https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_nxp-2Dimx_imx-2Dsmw.git&d=DwICAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=V_GK7jRuCHDErm6txmgDK1-MbUihtnSQ3gPgB-A-JKU&m=eKFfdy51aVVEAe4I9Lk2CN77y_4Hxf2pI_9fv5pVWLo9DwQNgCpca6smAwvwFycf&s=LLz2plXTM1AS-zJ1HlZRKiBE8GmRJBduR_0dnOuFjRo&e=
>> + crypto/skcipher,
>> + drivers/nvmem/imx-ocotp-ele.c
>> diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
>> index 183613f82a11..56bdca9bd917 100644
>> --- a/drivers/firmware/imx/Kconfig
>> +++ b/drivers/firmware/imx/Kconfig
>> @@ -22,3 +22,15 @@ config IMX_SCU
>>
>> This driver manages the IPC interface between host CPU and the
>> SCU firmware running on M4.
>> +
>> +config IMX_SEC_ENCLAVE
>> + tristate "i.MX Embedded Secure Enclave - EdgeLock Enclave Firmware driver."
>> + depends on IMX_MBOX && ARCH_MXC && ARM64
>> + default m if ARCH_MXC
>> +
>> + help
>> + It is possible to use APIs exposed by the iMX Secure Enclave HW IP called:
>> + - EdgeLock Enclave Firmware (for i.MX8ULP, i.MX93),
>> + like base, HSM, V2X & SHE using the SAB protocol via the shared Messaging
>> + Unit. This driver exposes these interfaces via a set of file descriptors
>> + allowing to configure shared memory, send and receive messages.
>> diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile
>> index 8f9f04a513a8..aa9033e0e9e3 100644
>> --- a/drivers/firmware/imx/Makefile
>> +++ b/drivers/firmware/imx/Makefile
>> @@ -1,3 +1,5 @@
>> # SPDX-License-Identifier: GPL-2.0
>> obj-$(CONFIG_IMX_DSP) += imx-dsp.o
>> obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o
>> +sec_enclave-objs = se_ctrl.o ele_common.o ele_base_msg.o
>> +obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
>> diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele_base_msg.c
>> new file mode 100644
>> index 000000000000..0463f26d93c7
>> --- /dev/null
>> +++ b/drivers/firmware/imx/ele_base_msg.c
>> @@ -0,0 +1,287 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright 2024 NXP
>> + */
>> +
>> +#include <linux/types.h>
>> +#include <linux/completion.h>
>> +#include <linux/dma-mapping.h>
>> +
>> +#include "ele_base_msg.h"
>> +#include "ele_common.h"
>> +
>> +int ele_get_info(struct device *dev, struct soc_info *s_info)
>> +{
>> + struct se_if_priv *priv = dev_get_drvdata(dev);
>> + struct se_api_msg *tx_msg __free(kfree);
>> + struct se_api_msg *rx_msg __free(kfree);
>> + phys_addr_t get_info_addr;
>> + u32 *get_info_data;
>> + u32 status;
>> + int ret;
>> +
>> + if (!priv || !s_info)
>> + goto exit;
>> +
>> + memset(s_info, 0x0, sizeof(*s_info));
>> +
>> + if (priv->mem_pool_name)
>> + get_info_data = get_phy_buf_mem_pool(dev,
>> + priv->mem_pool_name,
>> + &get_info_addr,
>> + ELE_GET_INFO_BUFF_SZ);
>> + else
>> + get_info_data = dmam_alloc_coherent(dev,
>> + ELE_GET_INFO_BUFF_SZ,
>> + &get_info_addr,
>> + GFP_KERNEL);
>> + if (!get_info_data) {
>> + ret = -ENOMEM;
>> + dev_err(dev,
>> + "%s: Failed to allocate get_info_addr.\n",
>> + __func__);
>> + goto exit;
>> + }
>> +
>> + tx_msg = kzalloc(ELE_GET_INFO_REQ_MSG_SZ << 2, GFP_KERNEL);
>> + if (!tx_msg) {
>> + ret = -ENOMEM;
>> + return ret;
It seems like you intended to use goto exit; instead of returning
directly from here. This would ensure that you can free the buffer
allocated with get_phy_buf_mem_pool in case of an allocation failure.
>> + }
>> +
>> + rx_msg = kzalloc(ELE_GET_INFO_RSP_MSG_SZ << 2, GFP_KERNEL);
>> + if (!rx_msg) {
>> + ret = -ENOMEM;
>> + return ret;
>> + }
>> +
>> + ret = plat_fill_cmd_msg_hdr(priv,
>> + (struct se_msg_hdr *)&tx_msg->header,
>> + ELE_GET_INFO_REQ,
>> + ELE_GET_INFO_REQ_MSG_SZ,
>> + true);
>> + if (ret)
>> + goto exit;
>> +
>> + tx_msg->data[0] = upper_32_bits(get_info_addr);
>> + tx_msg->data[1] = lower_32_bits(get_info_addr);
>> + tx_msg->data[2] = ELE_GET_INFO_READ_SZ;
>> + priv->rx_msg = rx_msg;
>> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
>> + if (ret < 0)
>> + goto exit;
>> +
>> + ret = validate_rsp_hdr(priv,
>> + priv->rx_msg->header,
>> + ELE_GET_INFO_REQ,
>> + ELE_GET_INFO_RSP_MSG_SZ,
>> + true);
>> + if (ret)
>> + goto exit;
>> +
>> + status = RES_STATUS(priv->rx_msg->data[0]);
>> + if (status != priv->success_tag) {
>> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
>> + ELE_GET_INFO_REQ, status);
>> + ret = -1;
>> + }
>> +
>> + s_info->imem_state = (get_info_data[ELE_IMEM_STATE_WORD]
>> + & ELE_IMEM_STATE_MASK) >> 16;
>> + s_info->major_ver = (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
>> + & SOC_VER_MASK) >> 24;
>> + s_info->minor_ver = ((get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
>> + & SOC_VER_MASK) >> 16) & 0xFF;
>> + s_info->soc_rev = (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
>> + & SOC_VER_MASK) >> 16;
>> + s_info->soc_id = get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
>> + & SOC_ID_MASK;
>> + s_info->serial_num
>> + = (u64)get_info_data[GET_INFO_SL_NUM_MSB_WORD_OFF] << 32
>> + | get_info_data[GET_INFO_SL_NUM_LSB_WORD_OFF];
>> +exit:
>> + if (get_info_addr) {
>> + if (priv->mem_pool_name)
>> + free_phybuf_mem_pool(dev, priv->mem_pool_name,
>> + get_info_data, ELE_GET_INFO_BUFF_SZ);
>> + else
>> + dmam_free_coherent(dev,
>> + ELE_GET_INFO_BUFF_SZ,
>> + get_info_data,
>> + get_info_addr);
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +int ele_ping(struct device *dev)
>> +{
>> + struct se_if_priv *priv = dev_get_drvdata(dev);
>> + struct se_api_msg *tx_msg __free(kfree);
>> + struct se_api_msg *rx_msg __free(kfree);
>
> If you want __free(kfree) it should be
>
> struct se_api_msg *tx_msg __free(kfree) = NULL;
> struct se_api_msg *rx_msg __free(kfree) = NULL;
>
> Or
>
> struct se_api_msg *tx_msg __free(kfree) = kzalloc(ELE_PING_REQ_SZ << 2, GFP_KERNEL)
> struct se_api_msg *rx_msg __free(kfree) = kzalloc(ELE_PING_RSP_SZ << 2, GFP_KERNEL)
>
> otherwise when
> if (!tx_msg) {
> return ret;
>
> ^^ when go here, rx_msg is random value. So kfree(rx_msg) will
> access random address.
>
> }
>
>> + u32 status;
>> + int ret;
>> +
>> + tx_msg = kzalloc(ELE_PING_REQ_SZ << 2, GFP_KERNEL);
>> + if (!tx_msg) {
>> + ret = -ENOMEM;
>> + return ret;
>
>
> return -ENOMEM
>
> Frank
>
>> + }
>> +
>> + rx_msg = kzalloc(ELE_PING_RSP_SZ << 2, GFP_KERNEL);
>> + if (!rx_msg) {
>> + ret = -ENOMEM;
>> + return ret;
>> + }
>> +
>> + ret = plat_fill_cmd_msg_hdr(priv,
>> + (struct se_msg_hdr *)&tx_msg->header,
>> + ELE_PING_REQ, ELE_PING_REQ_SZ,
>> + true);
>> + if (ret) {
>> + dev_err(dev, "Error: plat_fill_cmd_msg_hdr failed.\n");
>> + goto exit;
>> + }
>> +
>> + priv->rx_msg = rx_msg;
>> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
>> + if (ret)
>> + goto exit;
>> +
>> + ret = validate_rsp_hdr(priv,
>> + priv->rx_msg->header,
>> + ELE_PING_REQ,
>> + ELE_PING_RSP_SZ,
>> + true);
>> + if (ret)
>> + goto exit;
>> +
>> + status = RES_STATUS(priv->rx_msg->data[0]);
>> + if (status != priv->success_tag) {
>> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
>> + ELE_PING_REQ, status);
>> + ret = -1;
>> + }
>> +exit:
>> + return ret;
>> +}
>> +
>> +int ele_service_swap(struct device *dev,
>> + phys_addr_t addr,
>> + u32 addr_size, u16 flag)
>> +{
>> + struct se_if_priv *priv = dev_get_drvdata(dev);
>> + struct se_api_msg *tx_msg __free(kfree);
>> + struct se_api_msg *rx_msg __free(kfree);
>> + u32 status;
>> + int ret;
>> +
>> + tx_msg = kzalloc(ELE_SERVICE_SWAP_REQ_MSG_SZ << 2, GFP_KERNEL);
>> + if (!tx_msg) {
>> + ret = -ENOMEM;
>> + return ret;
>> + }
>> +
>> + rx_msg = kzalloc(ELE_SERVICE_SWAP_RSP_MSG_SZ << 2, GFP_KERNEL);
>> + if (!rx_msg) {
>> + ret = -ENOMEM;
>> + return ret;
>> + }
>> +
>> + ret = plat_fill_cmd_msg_hdr(priv,
>> + (struct se_msg_hdr *)&tx_msg->header,
>> + ELE_SERVICE_SWAP_REQ,
>> + ELE_SERVICE_SWAP_REQ_MSG_SZ,
>> + true);
>> + if (ret)
>> + goto exit;
>> +
>> + tx_msg->data[0] = flag;
>> + tx_msg->data[1] = addr_size;
>> + tx_msg->data[2] = ELE_NONE_VAL;
>> + tx_msg->data[3] = lower_32_bits(addr);
>> + tx_msg->data[4] = plat_add_msg_crc((uint32_t *)&tx_msg[0],
>> + ELE_SERVICE_SWAP_REQ_MSG_SZ);
>> + priv->rx_msg = rx_msg;
>> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
>> + if (ret < 0)
>> + goto exit;
>> +
>> + ret = validate_rsp_hdr(priv,
>> + priv->rx_msg->header,
>> + ELE_SERVICE_SWAP_REQ,
>> + ELE_SERVICE_SWAP_RSP_MSG_SZ,
>> + true);
>> + if (ret)
>> + goto exit;
>> +
>> + status = RES_STATUS(priv->rx_msg->data[0]);
>> + if (status != priv->success_tag) {
>> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
>> + ELE_SERVICE_SWAP_REQ, status);
>> + ret = -1;
>> + } else {
>> + if (flag == ELE_IMEM_EXPORT)
>> + ret = priv->rx_msg->data[1];
>> + else
>> + ret = 0;
>> + }
>> +exit:
>> +
>> + return ret;
>> +}
>> +
>> +int ele_fw_authenticate(struct device *dev, phys_addr_t addr)
>> +{
>> + struct se_if_priv *priv = dev_get_drvdata(dev);
>> + struct se_api_msg *tx_msg __free(kfree);
>> + struct se_api_msg *rx_msg __free(kfree);
>> + u32 status;
>> + int ret;
>> +
>> + tx_msg = kzalloc(ELE_FW_AUTH_REQ_SZ << 2, GFP_KERNEL);
>> + if (!tx_msg) {
>> + ret = -ENOMEM;
>> + return ret;
>> + }
>> +
>> + rx_msg = kzalloc(ELE_FW_AUTH_RSP_MSG_SZ << 2, GFP_KERNEL);
>> + if (!rx_msg) {
>> + ret = -ENOMEM;
>> + return ret;
>> + }
>> + ret = plat_fill_cmd_msg_hdr(priv,
>> + (struct se_msg_hdr *)&tx_msg->header,
>> + ELE_FW_AUTH_REQ,
>> + ELE_FW_AUTH_REQ_SZ,
>> + true);
>> + if (ret)
>> + goto exit;
>> +
>> + tx_msg->data[0] = addr;
>> + tx_msg->data[1] = 0x0;
>> + tx_msg->data[2] = addr;
>> +
>> + priv->rx_msg = rx_msg;
>> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
>> + if (ret < 0)
>> + goto exit;
>> +
>> + ret = validate_rsp_hdr(priv,
>> + priv->rx_msg->header,
>> + ELE_FW_AUTH_REQ,
>> + ELE_FW_AUTH_RSP_MSG_SZ,
>> + true);
>> + if (ret)
>> + goto exit;
>> +
>> + status = RES_STATUS(priv->rx_msg->data[0]);
>> + if (status != priv->success_tag) {
>> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
>> + ELE_FW_AUTH_REQ, status);
>> + ret = -1;
>> + }
>> +exit:
>> +
>> + return ret;
>> +}
>> diff --git a/drivers/firmware/imx/ele_base_msg.h b/drivers/firmware/imx/ele_base_msg.h
>> new file mode 100644
>> index 000000000000..3b3d2bf04a84
>> --- /dev/null
>> +++ b/drivers/firmware/imx/ele_base_msg.h
>> @@ -0,0 +1,70 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright 2024 NXP
>> + *
>> + * Header file for the EdgeLock Enclave Base API(s).
>> + */
>> +
>> +#ifndef ELE_BASE_MSG_H
>> +#define ELE_BASE_MSG_H
>> +
>> +#include <linux/device.h>
>> +#include <linux/types.h>
>> +
>> +#define WORD_SZ 4
>> +#define ELE_NONE_VAL 0x0
>> +
>> +#define ELE_SUCCESS_IND 0xD6
>> +
>> +#define ELE_GET_INFO_REQ 0xDA
>> +#define ELE_GET_INFO_REQ_MSG_SZ 0x10
>> +#define ELE_GET_INFO_RSP_MSG_SZ 0x08
>> +
>> +#define ELE_GET_INFO_BUFF_SZ 0x100
>> +#define ELE_GET_INFO_READ_SZ 0xA0
>> +
>> +#define DEFAULT_IMX_SOC_VER 0xA0
>> +#define SOC_VER_MASK 0xFFFF0000
>> +#define SOC_ID_MASK 0x0000FFFF
>> +struct soc_info {
>> + u32 imem_state;
>> + u8 major_ver;
>> + u8 minor_ver;
>> + u16 soc_id;
>> + u16 soc_rev;
>> + u64 serial_num;
>> +};
>> +
>> +#define GET_INFO_SOC_INFO_WORD_OFFSET 1
>> +#define GET_INFO_UUID_WORD_OFFSET 3
>> +#define GET_INFO_SL_NUM_MSB_WORD_OFF \
>> + (GET_INFO_UUID_WORD_OFFSET + 3)
>> +#define GET_INFO_SL_NUM_LSB_WORD_OFF \
>> + (GET_INFO_UUID_WORD_OFFSET + 0)
>> +
>> +#define ELE_PING_REQ 0x01
>> +#define ELE_PING_REQ_SZ 0x04
>> +#define ELE_PING_RSP_SZ 0x08
>> +
>> +#define ELE_SERVICE_SWAP_REQ 0xDF
>> +#define ELE_SERVICE_SWAP_REQ_MSG_SZ 0x18
>> +#define ELE_SERVICE_SWAP_RSP_MSG_SZ 0x0C
>> +#define ELE_IMEM_SIZE 0x10000
>> +#define ELE_IMEM_STATE_OK 0xCA
>> +#define ELE_IMEM_STATE_BAD 0xFE
>> +#define ELE_IMEM_STATE_WORD 0x27
>> +#define ELE_IMEM_STATE_MASK 0x00ff0000
>> +#define ELE_IMEM_EXPORT 0x1
>> +#define ELE_IMEM_IMPORT 0x2
>> +
>> +#define ELE_FW_AUTH_REQ 0x02
>> +#define ELE_FW_AUTH_REQ_SZ 0x10
>> +#define ELE_FW_AUTH_RSP_MSG_SZ 0x08
>> +
>> +int ele_get_info(struct device *dev, struct soc_info *s_info);
>> +int ele_ping(struct device *dev);
>> +int ele_service_swap(struct device *dev,
>> + phys_addr_t addr,
>> + u32 addr_size, u16 flag);
>> +int ele_fw_authenticate(struct device *dev, phys_addr_t addr);
>> +#endif
>> diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_common.c
>> new file mode 100644
>> index 000000000000..dcf7f9034653
>> --- /dev/null
>> +++ b/drivers/firmware/imx/ele_common.c
>> @@ -0,0 +1,341 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright 2024 NXP
>> + */
>> +
>> +#include "ele_base_msg.h"
>> +#include "ele_common.h"
>> +
>> +u32 plat_add_msg_crc(u32 *msg, u32 msg_len)
>> +{
>> + u32 nb_words = msg_len / (u32)sizeof(u32);
>> + u32 crc = 0;
>> + u32 i;
>> +
>> + for (i = 0; i < nb_words - 1; i++)
>> + crc ^= *(msg + i);
>> +
>> + return crc;
>> +}
>> +
>> +int imx_ele_msg_rcv(struct se_if_priv *priv)
>> +{
>> + u32 wait;
>> + int err;
>> +
>> + wait = msecs_to_jiffies(1000);
>> + if (!wait_for_completion_timeout(&priv->done, wait)) {
>> + dev_err(priv->dev,
>> + "Error: wait_for_completion timed out.\n");
>> + err = -ETIMEDOUT;
>> + }
>> +
>> + mutex_unlock(&priv->se_if_cmd_lock);
>> + priv->no_dev_ctx_used = false;
>> +
>> + return err;
>> +}
>> +
>> +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg)
>> +{
>> + bool is_cmd_lock_tobe_taken = false;
>> + int err;
>> +
>> + if (!priv->waiting_rsp_dev || priv->no_dev_ctx_used) {
>> + is_cmd_lock_tobe_taken = true;
>> + mutex_lock(&priv->se_if_cmd_lock);
>> + }
>> + scoped_guard(mutex, &priv->se_if_lock);
>> +
>> + err = mbox_send_message(priv->tx_chan, mssg);
>> + if (err < 0) {
>> + dev_err(priv->dev, "Error: mbox_send_message failure.\n");
>> + if (is_cmd_lock_tobe_taken)
>> + mutex_unlock(&priv->se_if_cmd_lock);
>> + return err;
>> + }
>> + err = 0;
>> +
>> + return err;
>> +}
>> +
>> +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg)
>> +{
>> + int err;
>> +
>> + priv->no_dev_ctx_used = true;
>> + err = imx_ele_msg_send(priv, mssg);
>> + if (err)
>> + goto exit;
>> +
>> + err = imx_ele_msg_rcv(priv);
>> +
>> +exit:
>> + return err;
>> +}
>> +
>> +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *dev_ctx)
>> +{
>> + struct se_msg_hdr header = {0};
>> + int err;
>> +
>> + err = wait_event_interruptible(dev_ctx->wq, dev_ctx->pending_hdr != 0);
>> + if (err)
>> + dev_err(dev_ctx->dev,
>> + "%s: Err[0x%x]:Interrupted by signal.\n",
>> + dev_ctx->miscdev.name, err);
>> +
>> + header = *((struct se_msg_hdr *) (&dev_ctx->temp_resp[0]));
>> +
>> + if (header.tag == dev_ctx->priv->rsp_tag)
>> + mutex_unlock(&dev_ctx->priv->se_if_cmd_lock);
>> +
>> + return err;
>> +}
>> +
>> +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
>> + void *tx_msg, int tx_msg_sz)
>> +{
>> + struct se_if_priv *priv = dev_ctx->priv;
>> + struct se_msg_hdr header = {0};
>> + int err;
>> +
>> + header = *((struct se_msg_hdr *) tx_msg);
>> +
>> + /*
>> + * Check that the size passed as argument matches the size
>> + * carried in the message.
>> + */
>> + err = header.size << 2;
>> +
>> + if (err != tx_msg_sz) {
>> + err = -EINVAL;
>> + dev_err(priv->dev,
>> + "%s: User buffer too small\n",
>> + dev_ctx->miscdev.name);
>> + goto exit;
>> + }
>> + /* Check the message is valid according to tags */
>> + if (header.tag == priv->cmd_tag)
>> + priv->waiting_rsp_dev = dev_ctx;
>> + else if (header.tag == priv->rsp_tag) {
>> + /* Check the device context can send the command */
>> + if (dev_ctx != priv->cmd_receiver_dev) {
>> + dev_err(priv->dev,
>> + "%s: Channel not configured to send resp to FW.",
>> + dev_ctx->miscdev.name);
>> + err = -EPERM;
>> + goto exit;
>> + }
>> + } else {
>> + dev_err(priv->dev,
>> + "%s: The message does not have a valid TAG\n",
>> + dev_ctx->miscdev.name);
>> + err = -EINVAL;
>> + goto exit;
>> + }
>> + err = imx_ele_msg_send(priv, tx_msg);
>> +exit:
>> + return err;
>> +}
>> +
>> +/*
>> + * Callback called by mailbox FW, when data is received.
>> + */
>> +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg)
>> +{
>> + struct device *dev = mbox_cl->dev;
>> + struct se_if_device_ctx *dev_ctx;
>> + struct se_api_msg *rx_msg;
>> + bool is_response = false;
>> + struct se_if_priv *priv;
>> + struct se_msg_hdr header;
>> +
>> + priv = dev_get_drvdata(dev);
>> + if (!priv) {
>> + dev_err(dev, "SE-MU Priv data is NULL;");
>> + return;
>> + }
>> +
>> + /* The function can be called with NULL msg */
>> + if (!msg) {
>> + dev_err(dev, "Message is invalid\n");
>> + return;
>> + }
>> +
>> + header.tag = ((u8 *)msg)[TAG_OFFSET];
>> + header.command = ((u8 *)msg)[CMD_OFFSET];
>> + header.size = ((u8 *)msg)[SZ_OFFSET];
>> + header.ver = ((u8 *)msg)[VER_OFFSET];
>> +
>> + /* Incoming command: wake up the receiver if any. */
>> + if (header.tag == priv->cmd_tag) {
>> + dev_dbg(dev, "Selecting cmd receiver\n");
>> + dev_ctx = priv->cmd_receiver_dev;
>> + } else if (header.tag == priv->rsp_tag) {
>> + if (priv->waiting_rsp_dev) {
>> + dev_dbg(dev, "Selecting rsp waiter\n");
>> + dev_ctx = priv->waiting_rsp_dev;
>> + is_response = true;
>> + } else {
>> + /*
>> + * Reading the EdgeLock Enclave response
>> + * to the command, sent by other
>> + * linux kernel services.
>> + */
>> + spin_lock(&priv->lock);
>> + memcpy(&priv->rx_msg, msg, header.size << 2);
>> +
>> + complete(&priv->done);
>> + spin_unlock(&priv->lock);
>> + return;
>> + }
>> + } else {
>> + dev_err(dev, "Failed to select a device for message: %.8x\n",
>> + *((u32 *) &header));
>> + return;
>> + }
>> + /* Init reception */
>> + rx_msg = kzalloc(header.size << 2, GFP_KERNEL);
>> + if (rx_msg)
>> + memcpy(rx_msg, msg, header.size << 2);
>> +
>> + dev_ctx->temp_resp = (u32 *)rx_msg;
>> + dev_ctx->temp_resp_size = header.size;
>> +
>> + /* Allow user to read */
>> + dev_ctx->pending_hdr = 1;
>> + wake_up_interruptible(&dev_ctx->wq);
>> +
>> + if (is_response)
>> + priv->waiting_rsp_dev = NULL;
>> +}
>> +
>> +int validate_rsp_hdr(struct se_if_priv *priv, u32 header,
>> + uint8_t msg_id, uint8_t sz, bool is_base_api)
>> +{
>> + int ret = -EINVAL;
>> + u32 size;
>> + u32 cmd;
>> + u32 tag;
>> + u32 ver;
>> +
>> + tag = MSG_TAG(header);
>> + cmd = MSG_COMMAND(header);
>> + size = MSG_SIZE(header);
>> + ver = MSG_VER(header);
>> +
>> + do {
>> + if (tag != priv->rsp_tag) {
>> + dev_err(priv->dev,
>> + "MSG[0x%x] Hdr: Resp tag mismatch. (0x%x != 0x%x)",
>> + msg_id, tag, priv->rsp_tag);
>> + break;
>> + }
>> +
>> + if (cmd != msg_id) {
>> + dev_err(priv->dev,
>> + "MSG Header: Cmd id mismatch. (0x%x != 0x%x)",
>> + cmd, msg_id);
>> + break;
>> + }
>> +
>> + if (size != (sz >> 2)) {
>> + dev_err(priv->dev,
>> + "MSG[0x%x] Hdr: Cmd size mismatch. (0x%x != 0x%x)",
>> + msg_id, size, (sz >> 2));
>> + break;
>> + }
>> +
>> + if (is_base_api && (ver != priv->base_api_ver)) {
>> + dev_err(priv->dev,
>> + "MSG[0x%x] Hdr: Base API Vers mismatch. (0x%x != 0x%x)",
>> + msg_id, ver, priv->base_api_ver);
>> + break;
>> + } else if (!is_base_api && ver != priv->fw_api_ver) {
>> + dev_err(priv->dev,
>> + "MSG[0x%x] Hdr: FW API Vers mismatch. (0x%x != 0x%x)",
>> + msg_id, ver, priv->fw_api_ver);
>> + break;
>> + }
>> +
>> + ret = 0;
>> +
>> + } while (false);
>> +
>> + return ret;
>> +}
>> +
>> +int se_save_imem_state(struct device *dev)
>> +{
>> + struct se_if_priv *priv = dev_get_drvdata(dev);
>> + int ret;
>> +
>> + /* EXPORT command will save encrypted IMEM to given address,
>> + * so later in resume, IMEM can be restored from the given
>> + * address.
>> + *
>> + * Size must be at least 64 kB.
>> + */
>> + ret = ele_service_swap(dev,
>> + priv->imem.phyaddr,
>> + ELE_IMEM_SIZE,
>> + ELE_IMEM_EXPORT);
>> + if (ret < 0)
>> + dev_err(dev, "Failed to export IMEM\n");
>> + else
>> + dev_info(dev,
>> + "Exported %d bytes of encrypted IMEM\n",
>> + ret);
>> +
>> + return ret;
>> +}
>> +
>> +int se_restore_imem_state(struct device *dev)
>> +{
>> + struct se_if_priv *priv = dev_get_drvdata(dev);
>> + struct soc_info s_info;
>> + int ret;
>> +
>> + /* get info from ELE */
>> + ret = ele_get_info(dev, &s_info);
>> + if (ret) {
>> + dev_err(dev, "Failed to get info from ELE.\n");
>> + return ret;
>> + }
>> +
>> + /* Get IMEM state, if 0xFE then import IMEM */
>> + if (s_info.imem_state == ELE_IMEM_STATE_BAD) {
>> + /* IMPORT command will restore IMEM from the given
>> + * address, here size is the actual size returned by ELE
>> + * during the export operation
>> + */
>> + ret = ele_service_swap(dev,
>> + priv->imem.phyaddr,
>> + priv->imem.size,
>> + ELE_IMEM_IMPORT);
>> + if (ret) {
>> + dev_err(dev, "Failed to import IMEM\n");
>> + goto exit;
>> + }
>> + } else
>> + goto exit;
>> +
>> + /* After importing IMEM, check if IMEM state is equal to 0xCA
>> + * to ensure IMEM is fully loaded and
>> + * ELE functionality can be used.
>> + */
>> + ret = ele_get_info(dev, &s_info);
>> + if (ret) {
>> + dev_err(dev, "Failed to get info from ELE.\n");
>> + goto exit;
>> + }
>> +
>> + if (s_info.imem_state == ELE_IMEM_STATE_OK)
>> + dev_info(dev, "Successfully restored IMEM\n");
>> + else
>> + dev_err(dev, "Failed to restore IMEM\n");
>> +
>> +exit:
>> + return ret;
>> +}
>> diff --git a/drivers/firmware/imx/ele_common.h b/drivers/firmware/imx/ele_common.h
>> new file mode 100644
>> index 000000000000..6e3a2114bb56
>> --- /dev/null
>> +++ b/drivers/firmware/imx/ele_common.h
>> @@ -0,0 +1,43 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright 2024 NXP
>> + */
>> +
>> +
>> +#ifndef __ELE_COMMON_H__
>> +#define __ELE_COMMON_H__
>> +
>> +#include "se_ctrl.h"
>> +
>> +#define IMX_ELE_FW_DIR "imx/ele/"
>> +
>> +uint32_t plat_add_msg_crc(uint32_t *msg, uint32_t msg_len);
>> +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *priv);
>> +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
>> + void *tx_msg, int tx_msg_sz);
>> +int imx_ele_msg_rcv(struct se_if_priv *priv);
>> +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg);
>> +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg);
>> +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg);
>> +int validate_rsp_hdr(struct se_if_priv *priv, unsigned int header,
>> + u8 msg_id, u8 sz, bool is_base_api);
>> +
>> +/* Fill a command message header with a given command ID and length in bytes. */
>> +static inline int plat_fill_cmd_msg_hdr(struct se_if_priv *priv,
>> + struct se_msg_hdr *hdr,
>> + u8 cmd,
>> + u32 len,
>> + bool is_base_api)
>> +{
>> + hdr->tag = priv->cmd_tag;
>> + hdr->ver = (is_base_api) ? priv->base_api_ver : priv->fw_api_ver;
>> + hdr->command = cmd;
>> + hdr->size = len >> 2;
>> +
>> + return 0;
>> +}
>> +
>> +int se_save_imem_state(struct device *dev);
>> +int se_restore_imem_state(struct device *dev);
>> +
>> +#endif /*__ELE_COMMON_H__ */
>> diff --git a/drivers/firmware/imx/se_ctrl.c b/drivers/firmware/imx/se_ctrl.c
>> new file mode 100644
>> index 000000000000..11c5eaa7353f
>> --- /dev/null
>> +++ b/drivers/firmware/imx/se_ctrl.c
>> @@ -0,0 +1,1339 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright 2024 NXP
>> + */
>> +
>> +#include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/dev_printk.h>
>> +#include <linux/dma-mapping.h>
>> +#include <linux/errno.h>
>> +#include <linux/export.h>
>> +#include <linux/firmware.h>
>> +#include <linux/firmware/imx/se_api.h>
>> +#include <linux/genalloc.h>
>> +#include <linux/init.h>
>> +#include <linux/io.h>
>> +#include <linux/miscdevice.h>
>> +#include <linux/mod_devicetable.h>
>> +#include <linux/module.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/of_reserved_mem.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/slab.h>
>> +#include <linux/string.h>
>> +#include <linux/sys_soc.h>
>> +#include <uapi/linux/se_ioctl.h>
>> +
>> +#include "ele_base_msg.h"
>> +#include "ele_common.h"
>> +#include "se_ctrl.h"
>> +
>> +#define RESERVED_DMA_POOL BIT(1)
>> +
>> +struct imx_se_node_info {
>> + u8 se_if_id;
>> + u8 se_if_did;
>> + u8 max_dev_ctx;
>> + u8 cmd_tag;
>> + u8 rsp_tag;
>> + u8 success_tag;
>> + u8 base_api_ver;
>> + u8 fw_api_ver;
>> + u8 *se_name;
>> + u8 *mbox_tx_name;
>> + u8 *mbox_rx_name;
>> + u8 *pool_name;
>> + u8 *fw_name_in_rfs;
>> + bool soc_register;
>> + bool reserved_dma_ranges;
>> + bool imem_mgmt;
>> +};
>> +
>> +struct imx_se_node_info_list {
>> + u8 num_mu;
>> + u16 soc_id;
>> + u16 soc_rev;
>> + struct imx_se_node_info info[];
>> +};
>> +
>> +static const struct imx_se_node_info_list imx8ulp_info = {
>> + .num_mu = 1,
>> + .soc_id = SOC_ID_OF_IMX8ULP,
>> + .info = {
>> + {
>> + .se_if_id = 2,
>> + .se_if_did = 7,
>> + .max_dev_ctx = 4,
>> + .cmd_tag = 0x17,
>> + .rsp_tag = 0xe1,
>> + .success_tag = 0xd6,
>> + .base_api_ver = MESSAGING_VERSION_6,
>> + .fw_api_ver = MESSAGING_VERSION_7,
>> + .se_name = "hsm1",
>> + .mbox_tx_name = "tx",
>> + .mbox_rx_name = "rx",
>> + .pool_name = "sram",
>> + .fw_name_in_rfs = IMX_ELE_FW_DIR\
>> + "mx8ulpa2ext-ahab-container.img",
>> + .soc_register = true,
>> + .reserved_dma_ranges = true,
>> + .imem_mgmt = true,
>> + },
>> + },
>> +};
>> +
>> +static const struct imx_se_node_info_list imx93_info = {
>> + .num_mu = 1,
>> + .soc_id = SOC_ID_OF_IMX93,
>> + .info = {
>> + {
>> + .se_if_id = 2,
>> + .se_if_did = 3,
>> + .max_dev_ctx = 4,
>> + .cmd_tag = 0x17,
>> + .rsp_tag = 0xe1,
>> + .success_tag = 0xd6,
>> + .base_api_ver = MESSAGING_VERSION_6,
>> + .fw_api_ver = MESSAGING_VERSION_7,
>> + .se_name = "hsm1",
>> + .mbox_tx_name = "tx",
>> + .mbox_rx_name = "rx",
>> + .reserved_dma_ranges = true,
>> + .imem_mgmt = true,
>> + .soc_register = true,
>> + },
>> + },
>> +};
>> +
>> +static const struct of_device_id se_match[] = {
>> + { .compatible = "fsl,imx8ulp-ele", .data = (void *)&imx8ulp_info},
>> + { .compatible = "fsl,imx93-ele", .data = (void *)&imx93_info},
>> + {},
>> +};
>> +
>> +static struct imx_se_node_info
>> + *get_imx_se_node_info(struct imx_se_node_info_list *info_list,
>> + const u32 idx)
>> +{
>> + if (idx < 0 || idx > info_list->num_mu)
>> + return NULL;
>> +
>> + return &info_list->info[idx];
>> +}
>> +
>> +void *get_phy_buf_mem_pool(struct device *dev,
>> + u8 *mem_pool_name,
>> + dma_addr_t *buf,
>> + u32 size)
>> +{
>> + struct device_node *of_node = dev->of_node;
>> + struct gen_pool *mem_pool;
>> +
>> + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
>> + if (!mem_pool) {
>> + dev_err(dev,
>> + "Unable to get sram pool = %s\n",
>> + mem_pool_name);
>> + return 0;
>> + }
>> +
>> + return gen_pool_dma_alloc(mem_pool, size, buf);
>> +}
>> +
>> +void free_phybuf_mem_pool(struct device *dev,
>> + u8 *mem_pool_name,
>> + u32 *buf,
>> + u32 size)
>> +{
>> + struct device_node *of_node = dev->of_node;
>> + struct gen_pool *mem_pool;
>> +
>> + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
>> + if (!mem_pool)
>> + dev_err(dev,
>> + "%s: Failed: Unable to get sram pool.\n",
>> + __func__);
>> +
>> + gen_pool_free(mem_pool, (u64)buf, size);
>> +}
>> +
>> +static int imx_fetch_soc_info(struct device *dev)
>> +{
>> + struct se_if_priv *priv = dev_get_drvdata(dev);
>> + struct imx_se_node_info_list *info_list;
>> + const struct imx_se_node_info *info;
>> + struct soc_device_attribute *attr;
>> + struct soc_device *sdev;
>> + struct soc_info s_info;
>> + int err = 0;
>> +
>> + info = priv->info;
>> + info_list = (struct imx_se_node_info_list *)
>> + device_get_match_data(dev->parent);
>> + if (info_list->soc_rev)
>> + return err;
>> +
>> + err = ele_get_info(dev, &s_info);
>> + if (err)
>> + s_info.major_ver = DEFAULT_IMX_SOC_VER;
>> +
>> + info_list->soc_rev = s_info.soc_rev;
>> +
>> + if (!info->soc_register)
>> + return 0;
>> +
>> + attr = devm_kzalloc(dev, sizeof(*attr), GFP_KERNEL);
>> + if (!attr)
>> + return -ENOMEM;
>> +
>> + if (s_info.minor_ver)
>> + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x.%x",
>> + s_info.major_ver,
>> + s_info.minor_ver);
>> + else
>> + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x",
>> + s_info.major_ver);
>> +
>> + switch (s_info.soc_id) {
>> + case SOC_ID_OF_IMX8ULP:
>> + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
>> + "i.MX8ULP");
>> + break;
>> + case SOC_ID_OF_IMX93:
>> + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
>> + "i.MX93");
>> + break;
>> + }
>> +
>> + err = of_property_read_string(of_root, "model",
>> + &attr->machine);
>> + if (err) {
>> + devm_kfree(dev, attr);
>> + return -EINVAL;
>> + }
>> + attr->family = devm_kasprintf(dev, GFP_KERNEL, "Freescale i.MX");
>> +
>> + attr->serial_number
>> + = devm_kasprintf(dev, GFP_KERNEL, "%016llX", s_info.serial_num);
>> +
>> + sdev = soc_device_register(attr);
>> + if (IS_ERR(sdev)) {
>> + devm_kfree(dev, attr->soc_id);
>> + devm_kfree(dev, attr->serial_number);
>> + devm_kfree(dev, attr->revision);
>> + devm_kfree(dev, attr->family);
>> + devm_kfree(dev, attr->machine);
>> + devm_kfree(dev, attr);
>> + return PTR_ERR(sdev);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * File operations for user-space
>> + */
>> +
>> +/* Write a message to the MU. */
>> +static ssize_t se_if_fops_write(struct file *fp, const char __user *buf,
>> + size_t size, loff_t *ppos)
>> +{
>> + struct se_api_msg *tx_msg __free(kfree);
>> + struct se_if_device_ctx *dev_ctx;
>> + struct se_if_priv *priv;
>> + int err;
>> +
>> + dev_ctx = container_of(fp->private_data,
>> + struct se_if_device_ctx,
>> + miscdev);
>> + priv = dev_ctx->priv;
>> + dev_dbg(priv->dev,
>> + "%s: write from buf (%p)%zu, ppos=%lld\n",
>> + dev_ctx->miscdev.name,
>> + buf, size, ((ppos) ? *ppos : 0));
>> +
>> + if (down_interruptible(&dev_ctx->fops_lock))
>> + return -EBUSY;
>> +
>> + if (dev_ctx->status != MU_OPENED) {
>> + err = -EINVAL;
>> + goto exit;
>> + }
>> +
>> + if (size < SE_MU_HDR_SZ) {
>> + dev_err(priv->dev,
>> + "%s: User buffer too small(%zu < %d)\n",
>> + dev_ctx->miscdev.name,
>> + size, SE_MU_HDR_SZ);
>> + err = -ENOSPC;
>> + goto exit;
>> + }
>> +
>> + tx_msg = memdup_user((void __user *)ppos, size);
>> + if (!tx_msg) {
>> + err = -ENOMEM;
>> + goto exit;
>> + }
>> +
>> + /* Copy data to buffer */
>> + if (copy_from_user(tx_msg, buf, size)) {
>> + err = -EFAULT;
>> + dev_err(priv->dev,
>> + "%s: Fail copy message from user\n",
>> + dev_ctx->miscdev.name);
>> + goto exit;
>> + }
>> +
>> + print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4,
>> + tx_msg, size, false);
>> +
>> + err = imx_ele_miscdev_msg_send(dev_ctx, tx_msg, size);
>> +
>> +exit:
>> + up(&dev_ctx->fops_lock);
>> + return err;
>> +}
>> +
>> +/*
>> + * Read a message from the MU.
>> + * Blocking until a message is available.
>> + */
>> +static ssize_t se_if_fops_read(struct file *fp, char __user *buf,
>> + size_t size, loff_t *ppos)
>> +{
>> + struct se_if_device_ctx *dev_ctx;
>> + struct se_buf_desc *b_desc;
>> + struct se_if_priv *priv;
>> + u32 size_to_copy;
>> + int err;
>> +
>> + dev_ctx = container_of(fp->private_data,
>> + struct se_if_device_ctx,
>> + miscdev);
>> + priv = dev_ctx->priv;
>> + dev_dbg(priv->dev,
>> + "%s: read to buf %p(%zu), ppos=%lld\n",
>> + dev_ctx->miscdev.name,
>> + buf, size, ((ppos) ? *ppos : 0));
>> +
>> + if (down_interruptible(&dev_ctx->fops_lock))
>> + return -EBUSY;
>> +
>> + if (dev_ctx->status != MU_OPENED) {
>> + err = -EINVAL;
>> + goto exit;
>> + }
>> +
>> + err = imx_ele_miscdev_msg_rcv(dev_ctx);
>> + if (err)
>> + goto exit;
>> +
>> + /* Buffer containing the message from FW, is
>> + * allocated in callback function.
>> + * Check if buffer allocation failed.
>> + */
>> + if (!dev_ctx->temp_resp) {
>> + err = -ENOMEM;
>> + goto exit;
>> + }
>> +
>> + dev_dbg(priv->dev,
>> + "%s: %s %s\n",
>> + dev_ctx->miscdev.name,
>> + __func__,
>> + "message received, start transmit to user");
>> +
>> + /*
>> + * Check that the size passed as argument is larger than
>> + * the one carried in the message.
>> + */
>> + size_to_copy = dev_ctx->temp_resp_size << 2;
>> + if (size_to_copy > size) {
>> + dev_dbg(priv->dev,
>> + "%s: User buffer too small (%zu < %d)\n",
>> + dev_ctx->miscdev.name,
>> + size, size_to_copy);
>> + size_to_copy = size;
>> + }
>> +
>> + /*
>> + * We may need to copy the output data to user before
>> + * delivering the completion message.
>> + */
>> + while (!list_empty(&dev_ctx->pending_out)) {
>> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
>> + struct se_buf_desc,
>> + link);
>> + if (!b_desc)
>> + continue;
>> +
>> + if (b_desc->usr_buf_ptr && b_desc->shared_buf_ptr) {
>> +
>> + dev_dbg(priv->dev,
>> + "%s: Copy output data to user\n",
>> + dev_ctx->miscdev.name);
>> + if (copy_to_user(b_desc->usr_buf_ptr,
>> + b_desc->shared_buf_ptr,
>> + b_desc->size)) {
>> + dev_err(priv->dev,
>> + "%s: Failure copying output data to user.",
>> + dev_ctx->miscdev.name);
>> + err = -EFAULT;
>> + goto exit;
>> + }
>> + }
>> +
>> + if (b_desc->shared_buf_ptr)
>> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
>> +
>> + __list_del_entry(&b_desc->link);
>> + kfree(b_desc);
>> + }
>> +
>> + /* Copy data from the buffer */
>> + print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4,
>> + dev_ctx->temp_resp, size_to_copy, false);
>> + if (copy_to_user(buf, dev_ctx->temp_resp, size_to_copy)) {
>> + dev_err(priv->dev,
>> + "%s: Failed to copy to user\n",
>> + dev_ctx->miscdev.name);
>> + err = -EFAULT;
>> + goto exit;
>> + }
>> +
>> + err = size_to_copy;
>> + kfree(dev_ctx->temp_resp);
>> +
>> + /* free memory allocated on the shared buffers. */
>> + dev_ctx->secure_mem.pos = 0;
>> + dev_ctx->non_secure_mem.pos = 0;
>> +
>> + dev_ctx->pending_hdr = 0;
>> +
>> +exit:
>> + /*
>> + * Clean the used Shared Memory space,
>> + * whether its Input Data copied from user buffers, or
>> + * Data received from FW.
>> + */
>> + while (!list_empty(&dev_ctx->pending_in) ||
>> + !list_empty(&dev_ctx->pending_out)) {
>> + if (!list_empty(&dev_ctx->pending_in))
>> + b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
>> + struct se_buf_desc,
>> + link);
>> + else
>> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
>> + struct se_buf_desc,
>> + link);
>> +
>> + if (!b_desc)
>> + continue;
>> +
>> + if (b_desc->shared_buf_ptr)
>> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
>> +
>> + __list_del_entry(&b_desc->link);
>> + kfree(b_desc);
>> + }
>> +
>> + up(&dev_ctx->fops_lock);
>> + return err;
>> +}
>> +
>> +/* Give access to EdgeLock Enclave, to the memory we want to share */
>> +static int se_if_setup_se_mem_access(struct se_if_device_ctx *dev_ctx,
>> + u64 addr, u32 len)
>> +{
>> + /* Assuming EdgeLock Enclave has access to all the memory regions */
>> + int ret = 0;
>> +
>> + if (ret) {
>> + dev_err(dev_ctx->priv->dev,
>> + "%s: Fail find memreg\n", dev_ctx->miscdev.name);
>> + goto exit;
>> + }
>> +
>> + if (ret) {
>> + dev_err(dev_ctx->priv->dev,
>> + "%s: Fail set permission for resource\n",
>> + dev_ctx->miscdev.name);
>> + goto exit;
>> + }
>> +
>> +exit:
>> + return ret;
>> +}
>> +
>> +static int se_ioctl_get_mu_info(struct se_if_device_ctx *dev_ctx,
>> + u64 arg)
>> +{
>> + struct se_if_priv *priv = dev_get_drvdata(dev_ctx->dev);
>> + struct imx_se_node_info *if_node_info;
>> + struct se_ioctl_get_if_info info;
>> + int err = 0;
>> +
>> + if_node_info = (struct imx_se_node_info *)priv->info;
>> +
>> + info.se_if_id = if_node_info->se_if_id;
>> + info.interrupt_idx = 0;
>> + info.tz = 0;
>> + info.did = if_node_info->se_if_did;
>> + info.cmd_tag = if_node_info->cmd_tag;
>> + info.rsp_tag = if_node_info->rsp_tag;
>> + info.success_tag = if_node_info->success_tag;
>> + info.base_api_ver = if_node_info->base_api_ver;
>> + info.fw_api_ver = if_node_info->fw_api_ver;
>> +
>> + dev_dbg(priv->dev,
>> + "%s: info [se_if_id: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n",
>> + dev_ctx->miscdev.name,
>> + info.se_if_id, info.interrupt_idx, info.tz, info.did);
>> +
>> + if (copy_to_user((u8 *)arg, &info, sizeof(info))) {
>> + dev_err(dev_ctx->priv->dev,
>> + "%s: Failed to copy mu info to user\n",
>> + dev_ctx->miscdev.name);
>> + err = -EFAULT;
>> + goto exit;
>> + }
>> +
>> +exit:
>> + return err;
>> +}
>> +
>> +/*
>> + * Copy a buffer of data to/from the user and return the address to use in
>> + * messages
>> + */
>> +static int se_ioctl_setup_iobuf_handler(struct se_if_device_ctx *dev_ctx,
>> + u64 arg)
>> +{
>> + struct se_ioctl_setup_iobuf io = {0};
>> + struct se_shared_mem *shared_mem;
>> + struct se_buf_desc *b_desc;
>> + int err = 0;
>> + u32 pos;
>> +
>> + if (copy_from_user(&io, (u8 *)arg, sizeof(io))) {
>> + dev_err(dev_ctx->priv->dev,
>> + "%s: Failed copy iobuf config from user\n",
>> + dev_ctx->miscdev.name);
>> + err = -EFAULT;
>> + goto exit;
>> + }
>> +
>> + dev_dbg(dev_ctx->priv->dev,
>> + "%s: io [buf: %p(%d) flag: %x]\n",
>> + dev_ctx->miscdev.name,
>> + io.user_buf, io.length, io.flags);
>> +
>> + if (io.length == 0 || !io.user_buf) {
>> + /*
>> + * Accept NULL pointers since some buffers are optional
>> + * in FW commands. In this case we should return 0 as
>> + * pointer to be embedded into the message.
>> + * Skip all data copy part of code below.
>> + */
>> + io.ele_addr = 0;
>> + goto copy;
>> + }
>> +
>> + /* Select the shared memory to be used for this buffer. */
>> + if (io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) {
>> + /* App requires to use secure memory for this buffer.*/
>> + dev_err(dev_ctx->priv->dev,
>> + "%s: Failed allocate SEC MEM memory\n",
>> + dev_ctx->miscdev.name);
>> + err = -EFAULT;
>> + goto exit;
>> + } else {
>> + /* No specific requirement for this buffer. */
>> + shared_mem = &dev_ctx->non_secure_mem;
>> + }
>> +
>> + /* Check there is enough space in the shared memory. */
>> + if (shared_mem->size < shared_mem->pos
>> + || io.length >= shared_mem->size - shared_mem->pos) {
>> + dev_err(dev_ctx->priv->dev,
>> + "%s: Not enough space in shared memory\n",
>> + dev_ctx->miscdev.name);
>> + err = -ENOMEM;
>> + goto exit;
>> + }
>> +
>> + /* Allocate space in shared memory. 8 bytes aligned. */
>> + pos = shared_mem->pos;
>> + shared_mem->pos += round_up(io.length, 8u);
>> + io.ele_addr = (u64)shared_mem->dma_addr + pos;
>> +
>> + if ((io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) &&
>> + !(io.flags & SE_MU_IO_FLAGS_USE_SHORT_ADDR)) {
>> + /*Add base address to get full address.*/
>> + dev_err(dev_ctx->priv->dev,
>> + "%s: Failed allocate SEC MEM memory\n",
>> + dev_ctx->miscdev.name);
>> + err = -EFAULT;
>> + goto exit;
>> + }
>> +
>> + memset(shared_mem->ptr + pos, 0, io.length);
>> + if ((io.flags & SE_IO_BUF_FLAGS_IS_INPUT) ||
>> + (io.flags & SE_IO_BUF_FLAGS_IS_IN_OUT)) {
>> + /*
>> + * buffer is input:
>> + * copy data from user space to this allocated buffer.
>> + */
>> + if (copy_from_user(shared_mem->ptr + pos, io.user_buf,
>> + io.length)) {
>> + dev_err(dev_ctx->priv->dev,
>> + "%s: Failed copy data to shared memory\n",
>> + dev_ctx->miscdev.name);
>> + err = -EFAULT;
>> + goto exit;
>> + }
>> + }
>> +
>> + b_desc = kzalloc(sizeof(*b_desc), GFP_KERNEL);
>> + if (!b_desc) {
>> + err = -ENOMEM;
>> + goto exit;
>> + }
>> +
>> +copy:
>> + /* Provide the EdgeLock Enclave address to user space only if success.*/
>> + if (copy_to_user((u8 *)arg, &io, sizeof(io))) {
>> + dev_err(dev_ctx->priv->dev,
>> + "%s: Failed to copy iobuff setup to user\n",
>> + dev_ctx->miscdev.name);
>> + kfree(b_desc);
>> + err = -EFAULT;
>> + goto exit;
>> + }
>> +
>> + if (b_desc) {
>> + b_desc->shared_buf_ptr = shared_mem->ptr + pos;
>> + b_desc->usr_buf_ptr = io.user_buf;
>> + b_desc->size = io.length;
>> +
>> + if (io.flags & SE_IO_BUF_FLAGS_IS_INPUT) {
>> + /*
>> + * buffer is input:
>> + * add an entry in the "pending input buffers" list so
>> + * that copied data can be cleaned from shared memory
>> + * later.
>> + */
>> + list_add_tail(&b_desc->link, &dev_ctx->pending_in);
>> + } else {
>> + /*
>> + * buffer is output:
>> + * add an entry in the "pending out buffers" list so data
>> + * can be copied to user space when receiving Secure-Enclave
>> + * response.
>> + */
>> + list_add_tail(&b_desc->link, &dev_ctx->pending_out);
>> + }
>> + }
>> +
>> +exit:
>> + return err;
>> +}
>> +
>> +/* IOCTL to provide SoC information */
>> +static int se_ioctl_get_soc_info_handler(struct se_if_device_ctx *dev_ctx,
>> + u64 arg)
>> +{
>> + struct imx_se_node_info_list *info_list;
>> + struct se_ioctl_get_soc_info soc_info;
>> + int err = -EINVAL;
>> +
>> + info_list = (struct imx_se_node_info_list *)
>> + device_get_match_data(dev_ctx->priv->dev->parent);
>> + if (!info_list)
>> + goto exit;
>> +
>> + soc_info.soc_id = info_list->soc_id;
>> + soc_info.soc_rev = info_list->soc_rev;
>> +
>> + err = (int)copy_to_user((u8 *)arg, (u8 *)(&soc_info), sizeof(soc_info));
>> + if (err) {
>> + dev_err(dev_ctx->priv->dev,
>> + "%s: Failed to copy soc info to user\n",
>> + dev_ctx->miscdev.name);
>> + err = -EFAULT;
>> + goto exit;
>> + }
>> +
>> +exit:
>> + return err;
>> +}
>> +
>> +/* Open a character device. */
>> +static int se_if_fops_open(struct inode *nd, struct file *fp)
>> +{
>> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
>> + struct se_if_device_ctx,
>> + miscdev);
>> + int err;
>> +
>> + /* Avoid race if opened at the same time */
>> + if (down_trylock(&dev_ctx->fops_lock))
>> + return -EBUSY;
>> +
>> + /* Authorize only 1 instance. */
>> + if (dev_ctx->status != MU_FREE) {
>> + err = -EBUSY;
>> + goto exit;
>> + }
>> +
>> + /*
>> + * Allocate some memory for data exchanges with S40x.
>> + * This will be used for data not requiring secure memory.
>> + */
>> + dev_ctx->non_secure_mem.ptr = dmam_alloc_coherent(dev_ctx->dev,
>> + MAX_DATA_SIZE_PER_USER,
>> + &dev_ctx->non_secure_mem.dma_addr,
>> + GFP_KERNEL);
>> + if (!dev_ctx->non_secure_mem.ptr) {
>> + err = -ENOMEM;
>> + goto exit;
>> + }
>> +
>> + err = se_if_setup_se_mem_access(dev_ctx,
>> + dev_ctx->non_secure_mem.dma_addr,
>> + MAX_DATA_SIZE_PER_USER);
>> + if (err) {
>> + err = -EPERM;
>> + dev_err(dev_ctx->priv->dev,
>> + "%s: Failed to share access to shared memory\n",
>> + dev_ctx->miscdev.name);
>> + goto free_coherent;
>> + }
>> +
>> + dev_ctx->non_secure_mem.size = MAX_DATA_SIZE_PER_USER;
>> + dev_ctx->non_secure_mem.pos = 0;
>> + dev_ctx->status = MU_OPENED;
>> +
>> + dev_ctx->pending_hdr = 0;
>> +
>> + goto exit;
>> +
>> +free_coherent:
>> + dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
>> + dev_ctx->non_secure_mem.ptr,
>> + dev_ctx->non_secure_mem.dma_addr);
>> +
>> +exit:
>> + up(&dev_ctx->fops_lock);
>> + return err;
>> +}
>> +
>> +/* Close a character device. */
>> +static int se_if_fops_close(struct inode *nd, struct file *fp)
>> +{
>> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
>> + struct se_if_device_ctx,
>> + miscdev);
>> + struct se_if_priv *priv = dev_ctx->priv;
>> + struct se_buf_desc *b_desc;
>> +
>> + /* Avoid race if closed at the same time */
>> + if (down_trylock(&dev_ctx->fops_lock))
>> + return -EBUSY;
>> +
>> + /* The device context has not been opened */
>> + if (dev_ctx->status != MU_OPENED)
>> + goto exit;
>> +
>> + /* check if this device was registered as command receiver. */
>> + if (priv->cmd_receiver_dev == dev_ctx)
>> + priv->cmd_receiver_dev = NULL;
>> +
>> + /* check if this device was registered as waiting response. */
>> + if (priv->waiting_rsp_dev == dev_ctx) {
>> + priv->waiting_rsp_dev = NULL;
>> + mutex_unlock(&priv->se_if_cmd_lock);
>> + }
>> +
>> + /* Unmap secure memory shared buffer. */
>> + if (dev_ctx->secure_mem.ptr)
>> + devm_iounmap(dev_ctx->dev, dev_ctx->secure_mem.ptr);
>> +
>> + dev_ctx->secure_mem.ptr = NULL;
>> + dev_ctx->secure_mem.dma_addr = 0;
>> + dev_ctx->secure_mem.size = 0;
>> + dev_ctx->secure_mem.pos = 0;
>> +
>> + /* Free non-secure shared buffer. */
>> + dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
>> + dev_ctx->non_secure_mem.ptr,
>> + dev_ctx->non_secure_mem.dma_addr);
>> +
>> + dev_ctx->non_secure_mem.ptr = NULL;
>> + dev_ctx->non_secure_mem.dma_addr = 0;
>> + dev_ctx->non_secure_mem.size = 0;
>> + dev_ctx->non_secure_mem.pos = 0;
>> +
>> + while (!list_empty(&dev_ctx->pending_in) ||
>> + !list_empty(&dev_ctx->pending_out)) {
>> + if (!list_empty(&dev_ctx->pending_in))
>> + b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
>> + struct se_buf_desc,
>> + link);
>> + else
>> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
>> + struct se_buf_desc,
>> + link);
>> +
>> + if (!b_desc)
>> + continue;
>> +
>> + if (b_desc->shared_buf_ptr)
>> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
>> +
>> + __list_del_entry(&b_desc->link);
>> + devm_kfree(dev_ctx->dev, b_desc);
>> + }
>> +
>> + dev_ctx->status = MU_FREE;
>> +
>> +exit:
>> + up(&dev_ctx->fops_lock);
>> + return 0;
>> +}
>> +
>> +/* IOCTL entry point of a character device */
>> +static long se_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
>> +//static long se_ioctl(struct file *fp, u32 cmd, u64 arg)
>> +{
>> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
>> + struct se_if_device_ctx,
>> + miscdev);
>> + struct se_if_priv *se_if_priv = dev_ctx->priv;
>> + int err = -EINVAL;
>> +
>> + /* Prevent race during change of device context */
>> + if (down_interruptible(&dev_ctx->fops_lock))
>> + return -EBUSY;
>> +
>> + switch (cmd) {
>> + case SE_IOCTL_ENABLE_CMD_RCV:
>> + if (!se_if_priv->cmd_receiver_dev) {
>> + se_if_priv->cmd_receiver_dev = dev_ctx;
>> + err = 0;
>> + }
>> + break;
>> + case SE_IOCTL_GET_MU_INFO:
>> + err = se_ioctl_get_mu_info(dev_ctx, arg);
>> + break;
>> + case SE_IOCTL_SETUP_IOBUF:
>> + err = se_ioctl_setup_iobuf_handler(dev_ctx, arg);
>> + break;
>> + case SE_IOCTL_GET_SOC_INFO:
>> + err = se_ioctl_get_soc_info_handler(dev_ctx, arg);
>> + break;
>> +
>> + default:
>> + err = -EINVAL;
>> + dev_dbg(se_if_priv->dev,
>> + "%s: IOCTL %.8x not supported\n",
>> + dev_ctx->miscdev.name,
>> + cmd);
>> + }
>> +
>> + up(&dev_ctx->fops_lock);
>> + return (long)err;
>> +}
>> +
>> +/* Char driver setup */
>> +static const struct file_operations se_if_fops = {
>> + .open = se_if_fops_open,
>> + .owner = THIS_MODULE,
>> + .release = se_if_fops_close,
>> + .unlocked_ioctl = se_ioctl,
>> + .read = se_if_fops_read,
>> + .write = se_if_fops_write,
>> +};
>> +
>> +/* interface for managed res to free a mailbox channel */
>> +static void if_mbox_free_channel(void *mbox_chan)
>> +{
>> + mbox_free_channel(mbox_chan);
>> +}
>> +
>> +/* interface for managed res to unregister a character device */
>> +static void if_misc_deregister(void *miscdevice)
>> +{
>> + misc_deregister(miscdevice);
>> +}
>> +
>> +static int se_if_request_channel(struct device *dev,
>> + struct mbox_chan **chan,
>> + struct mbox_client *cl,
>> + const u8 *name)
>> +{
>> + struct mbox_chan *t_chan;
>> + int ret = 0;
>> +
>> + t_chan = mbox_request_channel_byname(cl, name);
>> + if (IS_ERR(t_chan)) {
>> + ret = PTR_ERR(t_chan);
>> + if (ret != -EPROBE_DEFER)
>> + dev_err(dev,
>> + "Failed to request chan %s ret %d\n", name,
>> + ret);
>> + goto exit;
>> + }
>> +
>> + ret = devm_add_action(dev, if_mbox_free_channel, t_chan);
>> + if (ret) {
>> + dev_err(dev, "failed to add devm removal of mbox %s\n", name);
>> + goto exit;
>> + }
>> +
>> + *chan = t_chan;
>> +
>> +exit:
>> + return ret;
>> +}
>> +
>> +static int se_probe_if_cleanup(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct se_if_priv *priv;
>> + int ret = 0;
>> + int i;
>> +
>> + priv = dev_get_drvdata(dev);
>> + if (!priv) {
>> + ret = 0;
>> + dev_dbg(dev, "SE-MU Priv data is NULL;");
>> + return ret;
>> + }
>> +
>> + if (priv->tx_chan)
>> + mbox_free_channel(priv->tx_chan);
>> + if (priv->rx_chan)
>> + mbox_free_channel(priv->rx_chan);
>> +
>> + /* free the buffer in se remove, previously allocated
>> + * in se probe to store encrypted IMEM
>> + */
>> + if (priv->imem.buf) {
>> + dmam_free_coherent(dev,
>> + ELE_IMEM_SIZE,
>> + priv->imem.buf,
>> + priv->imem.phyaddr);
>> + priv->imem.buf = NULL;
>> + }
>> +
>> + if (priv->ctxs) {
>> + for (i = 0; i < priv->max_dev_ctx; i++) {
>> + if (priv->ctxs[i]) {
>> + devm_remove_action(dev,
>> + if_misc_deregister,
>> + &priv->ctxs[i]->miscdev);
>> + misc_deregister(&priv->ctxs[i]->miscdev);
>> + devm_kfree(dev, priv->ctxs[i]);
>> + }
>> + }
>> + devm_kfree(dev, priv->ctxs);
>> + }
>> +
>> + if (priv->flags & RESERVED_DMA_POOL) {
>> + of_reserved_mem_device_release(dev);
>> + priv->flags &= (~RESERVED_DMA_POOL);
>> + }
>> +
>> + devm_kfree(dev, priv);
>> + of_node_put(dev->of_node);
>> + of_platform_device_destroy(dev, NULL);
>> +
>> + return ret;
>> +}
>> +
>> +static int se_probe_cleanup(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct device_node *if_dn;
>> +
>> + /* Enumerate se-interface device nodes. */
>> + for_each_child_of_node(dev->of_node, if_dn) {
>> + struct platform_device *if_pdev
>> + = of_find_device_by_node(if_dn);
>> + if (se_probe_if_cleanup(if_pdev))
>> + dev_err(dev,
>> + "Failed to clean-up child node probe.\n");
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int init_device_context(struct device *dev)
>> +{
>> + const struct imx_se_node_info *info;
>> + struct se_if_device_ctx *dev_ctx;
>> + struct se_if_priv *priv;
>> + u8 *devname;
>> + int ret = 0;
>> + int i;
>> +
>> + priv = dev_get_drvdata(dev);
>> +
>> + if (!priv) {
>> + ret = -EINVAL;
>> + dev_err(dev, "Invalid SE-MU Priv data");
>> + return ret;
>> + }
>> + info = priv->info;
>> +
>> + priv->ctxs = devm_kzalloc(dev, sizeof(dev_ctx) * priv->max_dev_ctx,
>> + GFP_KERNEL);
>> +
>> + if (!priv->ctxs) {
>> + ret = -ENOMEM;
>> + return ret;
>> + }
>> +
>> + /* Create users */
>> + for (i = 0; i < priv->max_dev_ctx; i++) {
>> + dev_ctx = devm_kzalloc(dev, sizeof(*dev_ctx), GFP_KERNEL);
>> + if (!dev_ctx) {
>> + ret = -ENOMEM;
>> + return ret;
>> + }
>> +
>> + dev_ctx->dev = dev;
>> + dev_ctx->status = MU_FREE;
>> + dev_ctx->priv = priv;
>> +
>> + priv->ctxs[i] = dev_ctx;
>> +
>> + /* Default value invalid for an header. */
>> + init_waitqueue_head(&dev_ctx->wq);
>> +
>> + INIT_LIST_HEAD(&dev_ctx->pending_out);
>> + INIT_LIST_HEAD(&dev_ctx->pending_in);
>> + sema_init(&dev_ctx->fops_lock, 1);
>> +
>> + devname = devm_kasprintf(dev, GFP_KERNEL, "%s_ch%d",
>> + info->se_name, i);
>> + if (!devname) {
>> + ret = -ENOMEM;
>> + return ret;
>> + }
>> +
>> + dev_ctx->miscdev.name = devname;
>> + dev_ctx->miscdev.minor = MISC_DYNAMIC_MINOR;
>> + dev_ctx->miscdev.fops = &se_if_fops;
>> + dev_ctx->miscdev.parent = dev;
>> + ret = misc_register(&dev_ctx->miscdev);
>> + if (ret) {
>> + dev_err(dev, "failed to register misc device %d\n",
>> + ret);
>> + return ret;
>> + }
>> +
>> + ret = devm_add_action(dev, if_misc_deregister,
>> + &dev_ctx->miscdev);
>> + if (ret) {
>> + dev_err(dev,
>> + "failed[%d] to add action to the misc-dev\n",
>> + ret);
>> + return ret;
>> + }
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static void se_load_firmware(const struct firmware *fw, void *context)
>> +{
>> + struct se_if_priv *priv = (struct se_if_priv *) context;
>> + const struct imx_se_node_info *info = priv->info;
>> + const u8 *se_fw_name = info->fw_name_in_rfs;
>> + phys_addr_t se_fw_phyaddr;
>> + u8 *se_fw_buf;
>> +
>> + if (!fw) {
>> + if (priv->fw_fail > MAX_FW_LOAD_RETRIES)
>> + dev_dbg(priv->dev,
>> + "External FW not found, using ROM FW.\n");
>> + else {
>> + /*add a bit delay to wait for firmware priv released */
>> + msleep(20);
>> +
>> + /* Load firmware one more time if timeout */
>> + request_firmware_nowait(THIS_MODULE,
>> + FW_ACTION_UEVENT, info->fw_name_in_rfs,
>> + priv->dev, GFP_KERNEL, priv,
>> + se_load_firmware);
>> + priv->fw_fail++;
>> + dev_dbg(priv->dev, "Value of retries = 0x%x.\n",
>> + priv->fw_fail);
>> + }
>> +
>> + return;
>> + }
>> +
>> + /* allocate buffer to store the SE FW */
>> + se_fw_buf = dmam_alloc_coherent(priv->dev, fw->size,
>> + &se_fw_phyaddr,
>> + GFP_KERNEL);
>> + if (!se_fw_buf) {
>> + dev_err(priv->dev, "Failed to alloc SE fw buffer memory\n");
>> + goto exit;
>> + }
>> +
>> + memcpy(se_fw_buf, fw->data, fw->size);
>> +
>> + if (ele_fw_authenticate(priv->dev, se_fw_phyaddr))
>> + dev_err(priv->dev,
>> + "Failed to authenticate & load SE firmware %s.\n",
>> + se_fw_name);
>> +
>> +exit:
>> + dmam_free_coherent(priv->dev,
>> + fw->size,
>> + se_fw_buf,
>> + se_fw_phyaddr);
>> +
>> + release_firmware(fw);
>> +}
>> +
>> +static int se_if_probe(struct platform_device *pdev)
>> +{
>> + struct imx_se_node_info_list *info_list;
>> + struct device *dev = &pdev->dev;
>> + struct imx_se_node_info *info;
>> + struct se_if_priv *priv;
>> + u32 idx;
>> + int ret;
>> +
>> + if (of_property_read_u32(dev->of_node, "reg", &idx)) {
>> + ret = -EINVAL;
>> + goto exit;
>> + }
>> +
>> + info_list = (struct imx_se_node_info_list *)
>> + device_get_match_data(dev->parent);
>> + info = get_imx_se_node_info(info_list, idx);
>> +
>> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>> + if (!priv) {
>> + ret = -ENOMEM;
>> + goto exit;
>> + }
>> +
>> + dev_set_drvdata(dev, priv);
>> +
>> + /* Mailbox client configuration */
>> + priv->se_mb_cl.dev = dev;
>> + priv->se_mb_cl.tx_block = false;
>> + priv->se_mb_cl.knows_txdone = true;
>> + priv->se_mb_cl.rx_callback = se_if_rx_callback;
>> +
>> + ret = se_if_request_channel(dev, &priv->tx_chan,
>> + &priv->se_mb_cl, info->mbox_tx_name);
>> + if (ret) {
>> + if (ret == -EPROBE_DEFER)
>> + dev_err(dev, "Mailbox tx channel, is not ready.\n");
>> + else
>> + dev_err(dev, "Failed to request tx channel\n");
>> +
>> + goto exit;
>> + }
>> +
>> + ret = se_if_request_channel(dev, &priv->rx_chan,
>> + &priv->se_mb_cl, info->mbox_rx_name);
>> + if (ret) {
>> + if (ret == -EPROBE_DEFER)
>> + dev_err(dev, "Mailbox rx channel, is not ready.\n");
>> + else
>> + dev_dbg(dev, "Failed to request rx channel\n");
>> +
>> + goto exit;
>> + }
>> +
>> + priv->dev = dev;
>> + priv->info = info;
>> +
>> + /* Initialize the mutex. */
>> + mutex_init(&priv->se_if_lock);
>> + mutex_init(&priv->se_if_cmd_lock);
>> +
>> + priv->cmd_receiver_dev = NULL;
>> + priv->waiting_rsp_dev = NULL;
>> + priv->max_dev_ctx = info->max_dev_ctx;
>> + priv->cmd_tag = info->cmd_tag;
>> + priv->rsp_tag = info->rsp_tag;
>> + priv->mem_pool_name = info->pool_name;
>> + priv->success_tag = info->success_tag;
>> + priv->base_api_ver = info->base_api_ver;
>> + priv->fw_api_ver = info->fw_api_ver;
>> +
>> + init_completion(&priv->done);
>> + spin_lock_init(&priv->lock);
>> +
>> + if (info->reserved_dma_ranges) {
>> + ret = of_reserved_mem_device_init(dev);
>> + if (ret) {
>> + dev_err(dev,
>> + "failed to init reserved memory region %d\n",
>> + ret);
>> + priv->flags &= (~RESERVED_DMA_POOL);
>> + goto exit;
>> + }
>> + priv->flags |= RESERVED_DMA_POOL;
>> + }
>> +
>> + if (info->fw_name_in_rfs) {
>> + ret = request_firmware_nowait(THIS_MODULE,
>> + FW_ACTION_UEVENT,
>> + info->fw_name_in_rfs,
>> + dev, GFP_KERNEL, priv,
>> + se_load_firmware);
>> + if (ret)
>> + dev_warn(dev, "Failed to get firmware [%s].\n",
>> + info->fw_name_in_rfs);
>> + }
>> +
>> + ret = imx_fetch_soc_info(dev);
>> + if (ret) {
>> + dev_err(dev,
>> + "failed[%d] to fetch SoC Info\n", ret);
>> + goto exit;
>> + }
>> +
>> + if (info->imem_mgmt) {
>> + /* allocate buffer where SE store encrypted IMEM */
>> + priv->imem.buf = dmam_alloc_coherent(dev, ELE_IMEM_SIZE,
>> + &priv->imem.phyaddr,
>> + GFP_KERNEL);
>> + if (!priv->imem.buf) {
>> + dev_err(dev,
>> + "dmam-alloc-failed: To store encr-IMEM.\n");
>> + ret = -ENOMEM;
>> + goto exit;
>> + }
>> + }
>> +
>> + if (info->max_dev_ctx) {
>> + ret = init_device_context(dev);
>> + if (ret) {
>> + dev_err(dev,
>> + "Failed[0x%x] to create device contexts.\n",
>> + ret);
>> + goto exit;
>> + }
>> + }
>> +
>> + dev_info(dev, "i.MX secure-enclave: %s interface to firmware, configured.\n",
>> + info->se_name);
>> + return devm_of_platform_populate(dev);
>> +
>> +exit:
>> + /* if execution control reaches here, if probe fails.
>> + * hence doing the cleanup
>> + */
>> + if (se_probe_if_cleanup(pdev))
>> + dev_err(dev,
>> + "Failed to clean-up the child node probe.\n");
>> +
>> + return ret;
>> +}
>> +
>> +static int se_probe(struct platform_device *pdev)
>> +{
>> + struct device_node *enum_dev_node;
>> + struct device *dev = &pdev->dev;
>> + int enum_count;
>> + int ret;
>> +
>> + enum_count = of_get_child_count(dev->of_node);
>> + if (!enum_count) {
>> + ret = -EINVAL;
>> + dev_err(dev, "Zero Tx/Rx path MU nodes.\n");
>> + return ret;
>> + }
>> +
>> + for_each_child_of_node(dev->of_node, enum_dev_node) {
>> + struct platform_device *enum_plat_dev __maybe_unused;
>> +
>> + if (!of_device_is_available(enum_dev_node))
>> + continue;
>> +
>> + enum_plat_dev = of_platform_device_create(enum_dev_node,
>> + NULL,
>> + dev);
>> + if (!enum_plat_dev) {
>> + ret = -EINVAL;
>> + of_node_put(enum_dev_node);
>> + dev_err(dev,
>> + "Failed to create enumerated platform device.");
>> + break;
>> + }
>> +
>> + ret = se_if_probe(enum_plat_dev);
>> + }
>> + return ret;
>> +}
>> +
>> +static int se_remove(struct platform_device *pdev)
>> +{
>> + if (se_probe_cleanup(pdev))
>> + dev_err(&pdev->dev,
>> + "i.MX Secure Enclave is not cleanly un-probed.");
>> +
>> + return 0;
>> +}
>> +
>> +static int se_suspend(struct device *dev)
>> +{
>> + struct se_if_priv *priv = dev_get_drvdata(dev);
>> + const struct imx_se_node_info *info
>> + = priv->info;
>> +
>> + if (info && info->imem_mgmt)
>> + priv->imem.size = se_save_imem_state(dev);
>> +
>> + return 0;
>> +}
>> +
>> +static int se_resume(struct device *dev)
>> +{
>> + struct se_if_priv *priv = dev_get_drvdata(dev);
>> + const struct imx_se_node_info *info
>> + = priv->info;
>> + int i;
>> +
>> + for (i = 0; i < priv->max_dev_ctx; i++)
>> + wake_up_interruptible(&priv->ctxs[i]->wq);
>> +
>> + if (info && info->imem_mgmt)
>> + se_restore_imem_state(dev);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct dev_pm_ops se_pm = {
>> + RUNTIME_PM_OPS(se_suspend, se_resume, NULL)
>> +};
>> +
>> +static struct platform_driver se_driver = {
>> + .driver = {
>> + .name = "fsl-se-fw",
>> + .of_match_table = se_match,
>> + .pm = &se_pm,
>> + },
>> + .probe = se_probe,
>> + .remove = se_remove,
>> +};
>> +MODULE_DEVICE_TABLE(of, se_match);
>> +
>> +module_platform_driver(se_driver);
>> +
>> +MODULE_AUTHOR("Pankaj Gupta <pankaj.gupta@nxp.com>");
>> +MODULE_DESCRIPTION("iMX Secure Enclave Driver.");
>> +MODULE_LICENSE("GPL");
>> diff --git a/drivers/firmware/imx/se_ctrl.h b/drivers/firmware/imx/se_ctrl.h
>> new file mode 100644
>> index 000000000000..76e1ce77c52f
>> --- /dev/null
>> +++ b/drivers/firmware/imx/se_ctrl.h
>> @@ -0,0 +1,151 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright 2024 NXP
>> + */
>> +
>> +#ifndef SE_MU_H
>> +#define SE_MU_H
>> +
>> +#include <linux/miscdevice.h>
>> +#include <linux/semaphore.h>
>> +#include <linux/mailbox_client.h>
>> +
>> +#define MAX_FW_LOAD_RETRIES 50
>> +
>> +#define MSG_TAG(x) (((x) & 0xff000000) >> 24)
>> +#define MSG_COMMAND(x) (((x) & 0x00ff0000) >> 16)
>> +#define MSG_SIZE(x) (((x) & 0x0000ff00) >> 8)
>> +#define MSG_VER(x) ((x) & 0x000000ff)
>> +#define RES_STATUS(x) ((x) & 0x000000ff)
>> +#define MAX_DATA_SIZE_PER_USER (65 * 1024)
>> +#define S4_DEFAULT_MUAP_INDEX (2)
>> +#define S4_MUAP_DEFAULT_MAX_USERS (4)
>> +#define MESSAGING_VERSION_6 0x6
>> +#define MESSAGING_VERSION_7 0x7
>> +
>> +#define DEFAULT_MESSAGING_TAG_COMMAND (0x17u)
>> +#define DEFAULT_MESSAGING_TAG_RESPONSE (0xe1u)
>> +
>> +#define SE_MU_IO_FLAGS_USE_SEC_MEM (0x02u)
>> +#define SE_MU_IO_FLAGS_USE_SHORT_ADDR (0x04u)
>> +
>> +struct se_imem_buf {
>> + u8 *buf;
>> + phys_addr_t phyaddr;
>> + u32 size;
>> +};
>> +
>> +struct se_buf_desc {
>> + u8 *shared_buf_ptr;
>> + u8 *usr_buf_ptr;
>> + u32 size;
>> + struct list_head link;
>> +};
>> +
>> +/* Status of a char device */
>> +enum se_if_dev_ctx_status_t {
>> + MU_FREE,
>> + MU_OPENED
>> +};
>> +
>> +struct se_shared_mem {
>> + dma_addr_t dma_addr;
>> + u32 size;
>> + u32 pos;
>> + u8 *ptr;
>> +};
>> +
>> +/* Private struct for each char device instance. */
>> +struct se_if_device_ctx {
>> + struct device *dev;
>> + struct se_if_priv *priv;
>> + struct miscdevice miscdev;
>> +
>> + enum se_if_dev_ctx_status_t status;
>> + wait_queue_head_t wq;
>> + struct semaphore fops_lock;
>> +
>> + u32 pending_hdr;
>> + struct list_head pending_in;
>> + struct list_head pending_out;
>> +
>> + struct se_shared_mem secure_mem;
>> + struct se_shared_mem non_secure_mem;
>> +
>> + u32 *temp_resp;
>> + u32 temp_resp_size;
>> + struct notifier_block se_notify;
>> +};
>> +
>> +/* Header of the messages exchange with the EdgeLock Enclave */
>> +struct se_msg_hdr {
>> + u8 ver;
>> + u8 size;
>> + u8 command;
>> + u8 tag;
>> +} __packed;
>> +
>> +#define SE_MU_HDR_SZ 4
>> +#define TAG_OFFSET (SE_MU_HDR_SZ - 1)
>> +#define CMD_OFFSET (SE_MU_HDR_SZ - 2)
>> +#define SZ_OFFSET (SE_MU_HDR_SZ - 3)
>> +#define VER_OFFSET (SE_MU_HDR_SZ - 4)
>> +
>> +struct se_api_msg {
>> + u32 header; /* u8 Tag; u8 Command; u8 Size; u8 Ver; */
>> + u32 *data;
>> +};
>> +
>> +struct se_if_priv {
>> + struct se_if_device_ctx *cmd_receiver_dev;
>> + struct se_if_device_ctx *waiting_rsp_dev;
>> + bool no_dev_ctx_used;
>> + /*
>> + * prevent parallel access to the se interface registers
>> + * e.g. a user trying to send a command while the other one is
>> + * sending a response.
>> + */
>> + struct mutex se_if_lock;
>> + /*
>> + * prevent a command to be sent on the se interface while another one is
>> + * still processing. (response to a command is allowed)
>> + */
>> + struct mutex se_if_cmd_lock;
>> + struct device *dev;
>> + u8 *mem_pool_name;
>> + u8 cmd_tag;
>> + u8 rsp_tag;
>> + u8 success_tag;
>> + u8 base_api_ver;
>> + u8 fw_api_ver;
>> + u32 fw_fail;
>> + const void *info;
>> +
>> + struct mbox_client se_mb_cl;
>> + struct mbox_chan *tx_chan, *rx_chan;
>> + struct se_api_msg *rx_msg;
>> + struct completion done;
>> + spinlock_t lock;
>> + /*
>> + * Flag to retain the state of initialization done at
>> + * the time of se-mu probe.
>> + */
>> + uint32_t flags;
>> + u8 max_dev_ctx;
>> + struct se_if_device_ctx **ctxs;
>> + struct se_imem_buf imem;
>> +};
>> +
>> +void *get_phy_buf_mem_pool(struct device *dev,
>> + u8 *mem_pool_name,
>> + dma_addr_t *buf,
>> + u32 size);
>> +phys_addr_t get_phy_buf_mem_pool1(struct device *dev,
>> + u8 *mem_pool_name,
>> + u32 **buf,
>> + u32 size);
>> +void free_phybuf_mem_pool(struct device *dev,
>> + u8 *mem_pool_name,
>> + u32 *buf,
>> + u32 size);
>> +#endif
>> diff --git a/include/linux/firmware/imx/se_api.h b/include/linux/firmware/imx/se_api.h
>> new file mode 100644
>> index 000000000000..c47f84906837
>> --- /dev/null
>> +++ b/include/linux/firmware/imx/se_api.h
>> @@ -0,0 +1,14 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright 2024 NXP
>> + */
>> +
>> +#ifndef __SE_API_H__
>> +#define __SE_API_H__
>> +
>> +#include <linux/types.h>
>> +
>> +#define SOC_ID_OF_IMX8ULP 0x084D
>> +#define SOC_ID_OF_IMX93 0x9300
>> +
>> +#endif /* __SE_API_H__ */
>> diff --git a/include/uapi/linux/se_ioctl.h b/include/uapi/linux/se_ioctl.h
>> new file mode 100644
>> index 000000000000..f68a36e9da2c
>> --- /dev/null
>> +++ b/include/uapi/linux/se_ioctl.h
>> @@ -0,0 +1,88 @@
>> +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause*/
>> +/*
>> + * Copyright 2024 NXP
>> + */
>> +
>> +#ifndef SE_IOCTL_H
>> +#define SE_IOCTL_H
>> +
>> +/* IOCTL definitions. */
>> +
>> +struct se_ioctl_setup_iobuf {
>> + u8 *user_buf;
>> + u32 length;
>> + u32 flags;
>> + u64 ele_addr;
>> +};
>> +
>> +struct se_ioctl_shared_mem_cfg {
>> + u32 base_offset;
>> + u32 size;
>> +};
>> +
>> +struct se_ioctl_get_if_info {
>> + u8 se_if_id;
>> + u8 interrupt_idx;
>> + u8 tz;
>> + u8 did;
>> + u8 cmd_tag;
>> + u8 rsp_tag;
>> + u8 success_tag;
>> + u8 base_api_ver;
>> + u8 fw_api_ver;
>> +};
>> +
>> +struct se_ioctl_signed_message {
>> + u8 *message;
>> + u32 msg_size;
>> + u32 error_code;
>> +};
>> +
>> +struct se_ioctl_get_soc_info {
>> + u16 soc_id;
>> + u16 soc_rev;
>> +};
>> +
>> +/* IO Buffer Flags */
>> +#define SE_IO_BUF_FLAGS_IS_OUTPUT (0x00u)
>> +#define SE_IO_BUF_FLAGS_IS_INPUT (0x01u)
>> +#define SE_IO_BUF_FLAGS_USE_SEC_MEM (0x02u)
>> +#define SE_IO_BUF_FLAGS_USE_SHORT_ADDR (0x04u)
>> +#define SE_IO_BUF_FLAGS_IS_IN_OUT (0x10u)
>> +
>> +/* IOCTLS */
>> +#define SE_IOCTL 0x0A /* like MISC_MAJOR. */
>> +
>> +/*
>> + * ioctl to designated the current fd as logical-reciever.
>> + * This is ioctl is send when the nvm-daemon, a slave to the
>> + * firmware is started by the user.
>> + */
>> +#define SE_IOCTL_ENABLE_CMD_RCV _IO(SE_IOCTL, 0x01)
>> +
>> +/*
>> + * ioctl to get the buffer allocated from the memory, which is shared
>> + * between kernel and FW.
>> + * Post allocation, the kernel tagged the allocated memory with:
>> + * Output
>> + * Input
>> + * Input-Output
>> + * Short address
>> + * Secure-memory
>> + */
>> +#define SE_IOCTL_SETUP_IOBUF _IOWR(SE_IOCTL, 0x03, \
>> + struct se_ioctl_setup_iobuf)
>> +
>> +/*
>> + * ioctl to get the mu information, that is used to exchange message
>> + * with FW, from user-spaced.
>> + */
>> +#define SE_IOCTL_GET_MU_INFO _IOR(SE_IOCTL, 0x04, \
>> + struct se_ioctl_get_if_info)
>> +/*
>> + * ioctl to get SoC Info from user-space.
>> + */
>> +#define SE_IOCTL_GET_SOC_INFO _IOR(SE_IOCTL, 0x06, \
>> + struct se_ioctl_get_soc_info)
>> +
>> +#endif
>>
>> --
>> 2.34.1
>>
>
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^ permalink raw reply [relevance 0%]
* Re: [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave
2024-05-10 13:27 2% ` [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave Pankaj Gupta
@ 2024-05-10 16:41 0% ` Frank Li
2024-05-10 19:39 0% ` Amit Singh Tomar
2024-05-13 9:12 0% ` Pankaj Gupta
2024-05-13 10:54 0% ` Marc Kleine-Budde
2024-05-16 4:47 0% ` Amit Singh Tomar
2 siblings, 2 replies; 200+ results
From: Frank Li @ 2024-05-10 16:41 UTC (permalink / raw)
To: Pankaj Gupta
Cc: Jonathan Corbet, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
linux-doc, linux-kernel, devicetree, imx, linux-arm-kernel
On Fri, May 10, 2024 at 06:57:30PM +0530, Pankaj Gupta wrote:
> NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE),
> are embedded in the SoC to support the features like HSM, SHE & V2X,
> using message based communication interface.
>
> The secure enclave FW communicates on a dedicated messaging unit(MU)
> based interface(s) with application core, where kernel is running.
> It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
>
> This patch adds the driver for communication interface to secure-enclave,
> for exchanging messages with NXP secure enclave HW IP(s) like EdgeLock Enclave,
> both from:
> - User-Space Applications via character driver.
> - Kernel-space, used by kernel management layers like DM-Crypt.
>
> ABI documentation for the NXP secure-enclave driver.
>
> User-space library using this driver:
> - i.MX Secure Enclave library:
> -- URL: https://github.com/nxp-imx/imx-secure-enclave.git,
> - i.MX Secure Middle-Ware:
> -- URL: https://github.com/nxp-imx/imx-smw.git
>
> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> ---
> Documentation/ABI/testing/se-cdev | 42 ++
> drivers/firmware/imx/Kconfig | 12 +
> drivers/firmware/imx/Makefile | 2 +
> drivers/firmware/imx/ele_base_msg.c | 287 ++++++++
> drivers/firmware/imx/ele_base_msg.h | 70 ++
> drivers/firmware/imx/ele_common.c | 341 +++++++++
> drivers/firmware/imx/ele_common.h | 43 ++
> drivers/firmware/imx/se_ctrl.c | 1339 +++++++++++++++++++++++++++++++++++
> drivers/firmware/imx/se_ctrl.h | 151 ++++
> include/linux/firmware/imx/se_api.h | 14 +
> include/uapi/linux/se_ioctl.h | 88 +++
> 11 files changed, 2389 insertions(+)
>
> diff --git a/Documentation/ABI/testing/se-cdev b/Documentation/ABI/testing/se-cdev
> new file mode 100644
> index 000000000000..699525af6b86
> --- /dev/null
> +++ b/Documentation/ABI/testing/se-cdev
> @@ -0,0 +1,42 @@
> +What: /dev/<se>_mu[0-9]+_ch[0-9]+
> +Date: May 2024
> +KernelVersion: 6.8
> +Contact: linux-imx@nxp.com, pankaj.gupta@nxp.com
> +Description:
> + NXP offers multiple hardware IP(s) for secure-enclaves like EdgeLock-
> + Enclave(ELE), SECO. The character device file-descriptors
> + /dev/<se>_mu*_ch* are the interface between user-space NXP's secure-
> + enclave shared-library and the kernel driver.
> +
> + The ioctl(2)-based ABI is defined and documented in
> + [include]<linux/firmware/imx/ele_mu_ioctl.h>
> + ioctl(s) are used primarily for:
> + - shared memory management
> + - allocation of I/O buffers
> + - get mu info
> + - setting a dev-ctx as receiver that is slave to fw
> + - get SoC info
> +
> + The following file operations are supported:
> +
> + open(2)
> + Currently the only useful flags are O_RDWR.
> +
> + read(2)
> + Every read() from the opened character device context is waiting on
> + wakeup_intruptible, that gets set by the registered mailbox callback
> + function; indicating a message received from the firmware on message-
> + unit.
> +
> + write(2)
> + Every write() to the opened character device context needs to acquire
> + mailbox_lock, before sending message on to the message unit.
> +
> + close(2)
> + Stops and free up the I/O contexts that was associated
> + with the file descriptor.
> +
> +Users: https://github.com/nxp-imx/imx-secure-enclave.git,
> + https://github.com/nxp-imx/imx-smw.git
> + crypto/skcipher,
> + drivers/nvmem/imx-ocotp-ele.c
> diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
> index 183613f82a11..56bdca9bd917 100644
> --- a/drivers/firmware/imx/Kconfig
> +++ b/drivers/firmware/imx/Kconfig
> @@ -22,3 +22,15 @@ config IMX_SCU
>
> This driver manages the IPC interface between host CPU and the
> SCU firmware running on M4.
> +
> +config IMX_SEC_ENCLAVE
> + tristate "i.MX Embedded Secure Enclave - EdgeLock Enclave Firmware driver."
> + depends on IMX_MBOX && ARCH_MXC && ARM64
> + default m if ARCH_MXC
> +
> + help
> + It is possible to use APIs exposed by the iMX Secure Enclave HW IP called:
> + - EdgeLock Enclave Firmware (for i.MX8ULP, i.MX93),
> + like base, HSM, V2X & SHE using the SAB protocol via the shared Messaging
> + Unit. This driver exposes these interfaces via a set of file descriptors
> + allowing to configure shared memory, send and receive messages.
> diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile
> index 8f9f04a513a8..aa9033e0e9e3 100644
> --- a/drivers/firmware/imx/Makefile
> +++ b/drivers/firmware/imx/Makefile
> @@ -1,3 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-$(CONFIG_IMX_DSP) += imx-dsp.o
> obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o
> +sec_enclave-objs = se_ctrl.o ele_common.o ele_base_msg.o
> +obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
> diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele_base_msg.c
> new file mode 100644
> index 000000000000..0463f26d93c7
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_base_msg.c
> @@ -0,0 +1,287 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <linux/types.h>
> +#include <linux/completion.h>
> +#include <linux/dma-mapping.h>
> +
> +#include "ele_base_msg.h"
> +#include "ele_common.h"
> +
> +int ele_get_info(struct device *dev, struct soc_info *s_info)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_api_msg *rx_msg __free(kfree);
> + phys_addr_t get_info_addr;
> + u32 *get_info_data;
> + u32 status;
> + int ret;
> +
> + if (!priv || !s_info)
> + goto exit;
> +
> + memset(s_info, 0x0, sizeof(*s_info));
> +
> + if (priv->mem_pool_name)
> + get_info_data = get_phy_buf_mem_pool(dev,
> + priv->mem_pool_name,
> + &get_info_addr,
> + ELE_GET_INFO_BUFF_SZ);
> + else
> + get_info_data = dmam_alloc_coherent(dev,
> + ELE_GET_INFO_BUFF_SZ,
> + &get_info_addr,
> + GFP_KERNEL);
> + if (!get_info_data) {
> + ret = -ENOMEM;
> + dev_err(dev,
> + "%s: Failed to allocate get_info_addr.\n",
> + __func__);
> + goto exit;
> + }
> +
> + tx_msg = kzalloc(ELE_GET_INFO_REQ_MSG_SZ << 2, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + rx_msg = kzalloc(ELE_GET_INFO_RSP_MSG_SZ << 2, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_GET_INFO_REQ,
> + ELE_GET_INFO_REQ_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + tx_msg->data[0] = upper_32_bits(get_info_addr);
> + tx_msg->data[1] = lower_32_bits(get_info_addr);
> + tx_msg->data[2] = ELE_GET_INFO_READ_SZ;
> + priv->rx_msg = rx_msg;
> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> + if (ret < 0)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + priv->rx_msg->header,
> + ELE_GET_INFO_REQ,
> + ELE_GET_INFO_RSP_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_GET_INFO_REQ, status);
> + ret = -1;
> + }
> +
> + s_info->imem_state = (get_info_data[ELE_IMEM_STATE_WORD]
> + & ELE_IMEM_STATE_MASK) >> 16;
> + s_info->major_ver = (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> + & SOC_VER_MASK) >> 24;
> + s_info->minor_ver = ((get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> + & SOC_VER_MASK) >> 16) & 0xFF;
> + s_info->soc_rev = (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> + & SOC_VER_MASK) >> 16;
> + s_info->soc_id = get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
> + & SOC_ID_MASK;
> + s_info->serial_num
> + = (u64)get_info_data[GET_INFO_SL_NUM_MSB_WORD_OFF] << 32
> + | get_info_data[GET_INFO_SL_NUM_LSB_WORD_OFF];
> +exit:
> + if (get_info_addr) {
> + if (priv->mem_pool_name)
> + free_phybuf_mem_pool(dev, priv->mem_pool_name,
> + get_info_data, ELE_GET_INFO_BUFF_SZ);
> + else
> + dmam_free_coherent(dev,
> + ELE_GET_INFO_BUFF_SZ,
> + get_info_data,
> + get_info_addr);
> + }
> +
> + return ret;
> +}
> +
> +int ele_ping(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_api_msg *rx_msg __free(kfree);
If you want __free(kfree) it should be
struct se_api_msg *tx_msg __free(kfree) = NULL;
struct se_api_msg *rx_msg __free(kfree) = NULL;
Or
struct se_api_msg *tx_msg __free(kfree) = kzalloc(ELE_PING_REQ_SZ << 2, GFP_KERNEL)
struct se_api_msg *rx_msg __free(kfree) = kzalloc(ELE_PING_RSP_SZ << 2, GFP_KERNEL)
otherwise when
if (!tx_msg) {
return ret;
^^ when go here, rx_msg is random value. So kfree(rx_msg) will
access random address.
}
> + u32 status;
> + int ret;
> +
> + tx_msg = kzalloc(ELE_PING_REQ_SZ << 2, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + return ret;
return -ENOMEM
Frank
> + }
> +
> + rx_msg = kzalloc(ELE_PING_RSP_SZ << 2, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_PING_REQ, ELE_PING_REQ_SZ,
> + true);
> + if (ret) {
> + dev_err(dev, "Error: plat_fill_cmd_msg_hdr failed.\n");
> + goto exit;
> + }
> +
> + priv->rx_msg = rx_msg;
> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> + if (ret)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + priv->rx_msg->header,
> + ELE_PING_REQ,
> + ELE_PING_RSP_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_PING_REQ, status);
> + ret = -1;
> + }
> +exit:
> + return ret;
> +}
> +
> +int ele_service_swap(struct device *dev,
> + phys_addr_t addr,
> + u32 addr_size, u16 flag)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_api_msg *rx_msg __free(kfree);
> + u32 status;
> + int ret;
> +
> + tx_msg = kzalloc(ELE_SERVICE_SWAP_REQ_MSG_SZ << 2, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + rx_msg = kzalloc(ELE_SERVICE_SWAP_RSP_MSG_SZ << 2, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_SERVICE_SWAP_REQ,
> + ELE_SERVICE_SWAP_REQ_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + tx_msg->data[0] = flag;
> + tx_msg->data[1] = addr_size;
> + tx_msg->data[2] = ELE_NONE_VAL;
> + tx_msg->data[3] = lower_32_bits(addr);
> + tx_msg->data[4] = plat_add_msg_crc((uint32_t *)&tx_msg[0],
> + ELE_SERVICE_SWAP_REQ_MSG_SZ);
> + priv->rx_msg = rx_msg;
> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> + if (ret < 0)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + priv->rx_msg->header,
> + ELE_SERVICE_SWAP_REQ,
> + ELE_SERVICE_SWAP_RSP_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_SERVICE_SWAP_REQ, status);
> + ret = -1;
> + } else {
> + if (flag == ELE_IMEM_EXPORT)
> + ret = priv->rx_msg->data[1];
> + else
> + ret = 0;
> + }
> +exit:
> +
> + return ret;
> +}
> +
> +int ele_fw_authenticate(struct device *dev, phys_addr_t addr)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_api_msg *rx_msg __free(kfree);
> + u32 status;
> + int ret;
> +
> + tx_msg = kzalloc(ELE_FW_AUTH_REQ_SZ << 2, GFP_KERNEL);
> + if (!tx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + rx_msg = kzalloc(ELE_FW_AUTH_RSP_MSG_SZ << 2, GFP_KERNEL);
> + if (!rx_msg) {
> + ret = -ENOMEM;
> + return ret;
> + }
> + ret = plat_fill_cmd_msg_hdr(priv,
> + (struct se_msg_hdr *)&tx_msg->header,
> + ELE_FW_AUTH_REQ,
> + ELE_FW_AUTH_REQ_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + tx_msg->data[0] = addr;
> + tx_msg->data[1] = 0x0;
> + tx_msg->data[2] = addr;
> +
> + priv->rx_msg = rx_msg;
> + ret = imx_ele_msg_send_rcv(priv, tx_msg);
> + if (ret < 0)
> + goto exit;
> +
> + ret = validate_rsp_hdr(priv,
> + priv->rx_msg->header,
> + ELE_FW_AUTH_REQ,
> + ELE_FW_AUTH_RSP_MSG_SZ,
> + true);
> + if (ret)
> + goto exit;
> +
> + status = RES_STATUS(priv->rx_msg->data[0]);
> + if (status != priv->success_tag) {
> + dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
> + ELE_FW_AUTH_REQ, status);
> + ret = -1;
> + }
> +exit:
> +
> + return ret;
> +}
> diff --git a/drivers/firmware/imx/ele_base_msg.h b/drivers/firmware/imx/ele_base_msg.h
> new file mode 100644
> index 000000000000..3b3d2bf04a84
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_base_msg.h
> @@ -0,0 +1,70 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + *
> + * Header file for the EdgeLock Enclave Base API(s).
> + */
> +
> +#ifndef ELE_BASE_MSG_H
> +#define ELE_BASE_MSG_H
> +
> +#include <linux/device.h>
> +#include <linux/types.h>
> +
> +#define WORD_SZ 4
> +#define ELE_NONE_VAL 0x0
> +
> +#define ELE_SUCCESS_IND 0xD6
> +
> +#define ELE_GET_INFO_REQ 0xDA
> +#define ELE_GET_INFO_REQ_MSG_SZ 0x10
> +#define ELE_GET_INFO_RSP_MSG_SZ 0x08
> +
> +#define ELE_GET_INFO_BUFF_SZ 0x100
> +#define ELE_GET_INFO_READ_SZ 0xA0
> +
> +#define DEFAULT_IMX_SOC_VER 0xA0
> +#define SOC_VER_MASK 0xFFFF0000
> +#define SOC_ID_MASK 0x0000FFFF
> +struct soc_info {
> + u32 imem_state;
> + u8 major_ver;
> + u8 minor_ver;
> + u16 soc_id;
> + u16 soc_rev;
> + u64 serial_num;
> +};
> +
> +#define GET_INFO_SOC_INFO_WORD_OFFSET 1
> +#define GET_INFO_UUID_WORD_OFFSET 3
> +#define GET_INFO_SL_NUM_MSB_WORD_OFF \
> + (GET_INFO_UUID_WORD_OFFSET + 3)
> +#define GET_INFO_SL_NUM_LSB_WORD_OFF \
> + (GET_INFO_UUID_WORD_OFFSET + 0)
> +
> +#define ELE_PING_REQ 0x01
> +#define ELE_PING_REQ_SZ 0x04
> +#define ELE_PING_RSP_SZ 0x08
> +
> +#define ELE_SERVICE_SWAP_REQ 0xDF
> +#define ELE_SERVICE_SWAP_REQ_MSG_SZ 0x18
> +#define ELE_SERVICE_SWAP_RSP_MSG_SZ 0x0C
> +#define ELE_IMEM_SIZE 0x10000
> +#define ELE_IMEM_STATE_OK 0xCA
> +#define ELE_IMEM_STATE_BAD 0xFE
> +#define ELE_IMEM_STATE_WORD 0x27
> +#define ELE_IMEM_STATE_MASK 0x00ff0000
> +#define ELE_IMEM_EXPORT 0x1
> +#define ELE_IMEM_IMPORT 0x2
> +
> +#define ELE_FW_AUTH_REQ 0x02
> +#define ELE_FW_AUTH_REQ_SZ 0x10
> +#define ELE_FW_AUTH_RSP_MSG_SZ 0x08
> +
> +int ele_get_info(struct device *dev, struct soc_info *s_info);
> +int ele_ping(struct device *dev);
> +int ele_service_swap(struct device *dev,
> + phys_addr_t addr,
> + u32 addr_size, u16 flag);
> +int ele_fw_authenticate(struct device *dev, phys_addr_t addr);
> +#endif
> diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_common.c
> new file mode 100644
> index 000000000000..dcf7f9034653
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_common.c
> @@ -0,0 +1,341 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include "ele_base_msg.h"
> +#include "ele_common.h"
> +
> +u32 plat_add_msg_crc(u32 *msg, u32 msg_len)
> +{
> + u32 nb_words = msg_len / (u32)sizeof(u32);
> + u32 crc = 0;
> + u32 i;
> +
> + for (i = 0; i < nb_words - 1; i++)
> + crc ^= *(msg + i);
> +
> + return crc;
> +}
> +
> +int imx_ele_msg_rcv(struct se_if_priv *priv)
> +{
> + u32 wait;
> + int err;
> +
> + wait = msecs_to_jiffies(1000);
> + if (!wait_for_completion_timeout(&priv->done, wait)) {
> + dev_err(priv->dev,
> + "Error: wait_for_completion timed out.\n");
> + err = -ETIMEDOUT;
> + }
> +
> + mutex_unlock(&priv->se_if_cmd_lock);
> + priv->no_dev_ctx_used = false;
> +
> + return err;
> +}
> +
> +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg)
> +{
> + bool is_cmd_lock_tobe_taken = false;
> + int err;
> +
> + if (!priv->waiting_rsp_dev || priv->no_dev_ctx_used) {
> + is_cmd_lock_tobe_taken = true;
> + mutex_lock(&priv->se_if_cmd_lock);
> + }
> + scoped_guard(mutex, &priv->se_if_lock);
> +
> + err = mbox_send_message(priv->tx_chan, mssg);
> + if (err < 0) {
> + dev_err(priv->dev, "Error: mbox_send_message failure.\n");
> + if (is_cmd_lock_tobe_taken)
> + mutex_unlock(&priv->se_if_cmd_lock);
> + return err;
> + }
> + err = 0;
> +
> + return err;
> +}
> +
> +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg)
> +{
> + int err;
> +
> + priv->no_dev_ctx_used = true;
> + err = imx_ele_msg_send(priv, mssg);
> + if (err)
> + goto exit;
> +
> + err = imx_ele_msg_rcv(priv);
> +
> +exit:
> + return err;
> +}
> +
> +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *dev_ctx)
> +{
> + struct se_msg_hdr header = {0};
> + int err;
> +
> + err = wait_event_interruptible(dev_ctx->wq, dev_ctx->pending_hdr != 0);
> + if (err)
> + dev_err(dev_ctx->dev,
> + "%s: Err[0x%x]:Interrupted by signal.\n",
> + dev_ctx->miscdev.name, err);
> +
> + header = *((struct se_msg_hdr *) (&dev_ctx->temp_resp[0]));
> +
> + if (header.tag == dev_ctx->priv->rsp_tag)
> + mutex_unlock(&dev_ctx->priv->se_if_cmd_lock);
> +
> + return err;
> +}
> +
> +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
> + void *tx_msg, int tx_msg_sz)
> +{
> + struct se_if_priv *priv = dev_ctx->priv;
> + struct se_msg_hdr header = {0};
> + int err;
> +
> + header = *((struct se_msg_hdr *) tx_msg);
> +
> + /*
> + * Check that the size passed as argument matches the size
> + * carried in the message.
> + */
> + err = header.size << 2;
> +
> + if (err != tx_msg_sz) {
> + err = -EINVAL;
> + dev_err(priv->dev,
> + "%s: User buffer too small\n",
> + dev_ctx->miscdev.name);
> + goto exit;
> + }
> + /* Check the message is valid according to tags */
> + if (header.tag == priv->cmd_tag)
> + priv->waiting_rsp_dev = dev_ctx;
> + else if (header.tag == priv->rsp_tag) {
> + /* Check the device context can send the command */
> + if (dev_ctx != priv->cmd_receiver_dev) {
> + dev_err(priv->dev,
> + "%s: Channel not configured to send resp to FW.",
> + dev_ctx->miscdev.name);
> + err = -EPERM;
> + goto exit;
> + }
> + } else {
> + dev_err(priv->dev,
> + "%s: The message does not have a valid TAG\n",
> + dev_ctx->miscdev.name);
> + err = -EINVAL;
> + goto exit;
> + }
> + err = imx_ele_msg_send(priv, tx_msg);
> +exit:
> + return err;
> +}
> +
> +/*
> + * Callback called by mailbox FW, when data is received.
> + */
> +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg)
> +{
> + struct device *dev = mbox_cl->dev;
> + struct se_if_device_ctx *dev_ctx;
> + struct se_api_msg *rx_msg;
> + bool is_response = false;
> + struct se_if_priv *priv;
> + struct se_msg_hdr header;
> +
> + priv = dev_get_drvdata(dev);
> + if (!priv) {
> + dev_err(dev, "SE-MU Priv data is NULL;");
> + return;
> + }
> +
> + /* The function can be called with NULL msg */
> + if (!msg) {
> + dev_err(dev, "Message is invalid\n");
> + return;
> + }
> +
> + header.tag = ((u8 *)msg)[TAG_OFFSET];
> + header.command = ((u8 *)msg)[CMD_OFFSET];
> + header.size = ((u8 *)msg)[SZ_OFFSET];
> + header.ver = ((u8 *)msg)[VER_OFFSET];
> +
> + /* Incoming command: wake up the receiver if any. */
> + if (header.tag == priv->cmd_tag) {
> + dev_dbg(dev, "Selecting cmd receiver\n");
> + dev_ctx = priv->cmd_receiver_dev;
> + } else if (header.tag == priv->rsp_tag) {
> + if (priv->waiting_rsp_dev) {
> + dev_dbg(dev, "Selecting rsp waiter\n");
> + dev_ctx = priv->waiting_rsp_dev;
> + is_response = true;
> + } else {
> + /*
> + * Reading the EdgeLock Enclave response
> + * to the command, sent by other
> + * linux kernel services.
> + */
> + spin_lock(&priv->lock);
> + memcpy(&priv->rx_msg, msg, header.size << 2);
> +
> + complete(&priv->done);
> + spin_unlock(&priv->lock);
> + return;
> + }
> + } else {
> + dev_err(dev, "Failed to select a device for message: %.8x\n",
> + *((u32 *) &header));
> + return;
> + }
> + /* Init reception */
> + rx_msg = kzalloc(header.size << 2, GFP_KERNEL);
> + if (rx_msg)
> + memcpy(rx_msg, msg, header.size << 2);
> +
> + dev_ctx->temp_resp = (u32 *)rx_msg;
> + dev_ctx->temp_resp_size = header.size;
> +
> + /* Allow user to read */
> + dev_ctx->pending_hdr = 1;
> + wake_up_interruptible(&dev_ctx->wq);
> +
> + if (is_response)
> + priv->waiting_rsp_dev = NULL;
> +}
> +
> +int validate_rsp_hdr(struct se_if_priv *priv, u32 header,
> + uint8_t msg_id, uint8_t sz, bool is_base_api)
> +{
> + int ret = -EINVAL;
> + u32 size;
> + u32 cmd;
> + u32 tag;
> + u32 ver;
> +
> + tag = MSG_TAG(header);
> + cmd = MSG_COMMAND(header);
> + size = MSG_SIZE(header);
> + ver = MSG_VER(header);
> +
> + do {
> + if (tag != priv->rsp_tag) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: Resp tag mismatch. (0x%x != 0x%x)",
> + msg_id, tag, priv->rsp_tag);
> + break;
> + }
> +
> + if (cmd != msg_id) {
> + dev_err(priv->dev,
> + "MSG Header: Cmd id mismatch. (0x%x != 0x%x)",
> + cmd, msg_id);
> + break;
> + }
> +
> + if (size != (sz >> 2)) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: Cmd size mismatch. (0x%x != 0x%x)",
> + msg_id, size, (sz >> 2));
> + break;
> + }
> +
> + if (is_base_api && (ver != priv->base_api_ver)) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: Base API Vers mismatch. (0x%x != 0x%x)",
> + msg_id, ver, priv->base_api_ver);
> + break;
> + } else if (!is_base_api && ver != priv->fw_api_ver) {
> + dev_err(priv->dev,
> + "MSG[0x%x] Hdr: FW API Vers mismatch. (0x%x != 0x%x)",
> + msg_id, ver, priv->fw_api_ver);
> + break;
> + }
> +
> + ret = 0;
> +
> + } while (false);
> +
> + return ret;
> +}
> +
> +int se_save_imem_state(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + int ret;
> +
> + /* EXPORT command will save encrypted IMEM to given address,
> + * so later in resume, IMEM can be restored from the given
> + * address.
> + *
> + * Size must be at least 64 kB.
> + */
> + ret = ele_service_swap(dev,
> + priv->imem.phyaddr,
> + ELE_IMEM_SIZE,
> + ELE_IMEM_EXPORT);
> + if (ret < 0)
> + dev_err(dev, "Failed to export IMEM\n");
> + else
> + dev_info(dev,
> + "Exported %d bytes of encrypted IMEM\n",
> + ret);
> +
> + return ret;
> +}
> +
> +int se_restore_imem_state(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct soc_info s_info;
> + int ret;
> +
> + /* get info from ELE */
> + ret = ele_get_info(dev, &s_info);
> + if (ret) {
> + dev_err(dev, "Failed to get info from ELE.\n");
> + return ret;
> + }
> +
> + /* Get IMEM state, if 0xFE then import IMEM */
> + if (s_info.imem_state == ELE_IMEM_STATE_BAD) {
> + /* IMPORT command will restore IMEM from the given
> + * address, here size is the actual size returned by ELE
> + * during the export operation
> + */
> + ret = ele_service_swap(dev,
> + priv->imem.phyaddr,
> + priv->imem.size,
> + ELE_IMEM_IMPORT);
> + if (ret) {
> + dev_err(dev, "Failed to import IMEM\n");
> + goto exit;
> + }
> + } else
> + goto exit;
> +
> + /* After importing IMEM, check if IMEM state is equal to 0xCA
> + * to ensure IMEM is fully loaded and
> + * ELE functionality can be used.
> + */
> + ret = ele_get_info(dev, &s_info);
> + if (ret) {
> + dev_err(dev, "Failed to get info from ELE.\n");
> + goto exit;
> + }
> +
> + if (s_info.imem_state == ELE_IMEM_STATE_OK)
> + dev_info(dev, "Successfully restored IMEM\n");
> + else
> + dev_err(dev, "Failed to restore IMEM\n");
> +
> +exit:
> + return ret;
> +}
> diff --git a/drivers/firmware/imx/ele_common.h b/drivers/firmware/imx/ele_common.h
> new file mode 100644
> index 000000000000..6e3a2114bb56
> --- /dev/null
> +++ b/drivers/firmware/imx/ele_common.h
> @@ -0,0 +1,43 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +
> +#ifndef __ELE_COMMON_H__
> +#define __ELE_COMMON_H__
> +
> +#include "se_ctrl.h"
> +
> +#define IMX_ELE_FW_DIR "imx/ele/"
> +
> +uint32_t plat_add_msg_crc(uint32_t *msg, uint32_t msg_len);
> +int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *priv);
> +int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
> + void *tx_msg, int tx_msg_sz);
> +int imx_ele_msg_rcv(struct se_if_priv *priv);
> +int imx_ele_msg_send(struct se_if_priv *priv, void *mssg);
> +int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg);
> +void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg);
> +int validate_rsp_hdr(struct se_if_priv *priv, unsigned int header,
> + u8 msg_id, u8 sz, bool is_base_api);
> +
> +/* Fill a command message header with a given command ID and length in bytes. */
> +static inline int plat_fill_cmd_msg_hdr(struct se_if_priv *priv,
> + struct se_msg_hdr *hdr,
> + u8 cmd,
> + u32 len,
> + bool is_base_api)
> +{
> + hdr->tag = priv->cmd_tag;
> + hdr->ver = (is_base_api) ? priv->base_api_ver : priv->fw_api_ver;
> + hdr->command = cmd;
> + hdr->size = len >> 2;
> +
> + return 0;
> +}
> +
> +int se_save_imem_state(struct device *dev);
> +int se_restore_imem_state(struct device *dev);
> +
> +#endif /*__ELE_COMMON_H__ */
> diff --git a/drivers/firmware/imx/se_ctrl.c b/drivers/firmware/imx/se_ctrl.c
> new file mode 100644
> index 000000000000..11c5eaa7353f
> --- /dev/null
> +++ b/drivers/firmware/imx/se_ctrl.c
> @@ -0,0 +1,1339 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/dev_printk.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/errno.h>
> +#include <linux/export.h>
> +#include <linux/firmware.h>
> +#include <linux/firmware/imx/se_api.h>
> +#include <linux/genalloc.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/miscdevice.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_reserved_mem.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/sys_soc.h>
> +#include <uapi/linux/se_ioctl.h>
> +
> +#include "ele_base_msg.h"
> +#include "ele_common.h"
> +#include "se_ctrl.h"
> +
> +#define RESERVED_DMA_POOL BIT(1)
> +
> +struct imx_se_node_info {
> + u8 se_if_id;
> + u8 se_if_did;
> + u8 max_dev_ctx;
> + u8 cmd_tag;
> + u8 rsp_tag;
> + u8 success_tag;
> + u8 base_api_ver;
> + u8 fw_api_ver;
> + u8 *se_name;
> + u8 *mbox_tx_name;
> + u8 *mbox_rx_name;
> + u8 *pool_name;
> + u8 *fw_name_in_rfs;
> + bool soc_register;
> + bool reserved_dma_ranges;
> + bool imem_mgmt;
> +};
> +
> +struct imx_se_node_info_list {
> + u8 num_mu;
> + u16 soc_id;
> + u16 soc_rev;
> + struct imx_se_node_info info[];
> +};
> +
> +static const struct imx_se_node_info_list imx8ulp_info = {
> + .num_mu = 1,
> + .soc_id = SOC_ID_OF_IMX8ULP,
> + .info = {
> + {
> + .se_if_id = 2,
> + .se_if_did = 7,
> + .max_dev_ctx = 4,
> + .cmd_tag = 0x17,
> + .rsp_tag = 0xe1,
> + .success_tag = 0xd6,
> + .base_api_ver = MESSAGING_VERSION_6,
> + .fw_api_ver = MESSAGING_VERSION_7,
> + .se_name = "hsm1",
> + .mbox_tx_name = "tx",
> + .mbox_rx_name = "rx",
> + .pool_name = "sram",
> + .fw_name_in_rfs = IMX_ELE_FW_DIR\
> + "mx8ulpa2ext-ahab-container.img",
> + .soc_register = true,
> + .reserved_dma_ranges = true,
> + .imem_mgmt = true,
> + },
> + },
> +};
> +
> +static const struct imx_se_node_info_list imx93_info = {
> + .num_mu = 1,
> + .soc_id = SOC_ID_OF_IMX93,
> + .info = {
> + {
> + .se_if_id = 2,
> + .se_if_did = 3,
> + .max_dev_ctx = 4,
> + .cmd_tag = 0x17,
> + .rsp_tag = 0xe1,
> + .success_tag = 0xd6,
> + .base_api_ver = MESSAGING_VERSION_6,
> + .fw_api_ver = MESSAGING_VERSION_7,
> + .se_name = "hsm1",
> + .mbox_tx_name = "tx",
> + .mbox_rx_name = "rx",
> + .reserved_dma_ranges = true,
> + .imem_mgmt = true,
> + .soc_register = true,
> + },
> + },
> +};
> +
> +static const struct of_device_id se_match[] = {
> + { .compatible = "fsl,imx8ulp-ele", .data = (void *)&imx8ulp_info},
> + { .compatible = "fsl,imx93-ele", .data = (void *)&imx93_info},
> + {},
> +};
> +
> +static struct imx_se_node_info
> + *get_imx_se_node_info(struct imx_se_node_info_list *info_list,
> + const u32 idx)
> +{
> + if (idx < 0 || idx > info_list->num_mu)
> + return NULL;
> +
> + return &info_list->info[idx];
> +}
> +
> +void *get_phy_buf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + dma_addr_t *buf,
> + u32 size)
> +{
> + struct device_node *of_node = dev->of_node;
> + struct gen_pool *mem_pool;
> +
> + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> + if (!mem_pool) {
> + dev_err(dev,
> + "Unable to get sram pool = %s\n",
> + mem_pool_name);
> + return 0;
> + }
> +
> + return gen_pool_dma_alloc(mem_pool, size, buf);
> +}
> +
> +void free_phybuf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + u32 *buf,
> + u32 size)
> +{
> + struct device_node *of_node = dev->of_node;
> + struct gen_pool *mem_pool;
> +
> + mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
> + if (!mem_pool)
> + dev_err(dev,
> + "%s: Failed: Unable to get sram pool.\n",
> + __func__);
> +
> + gen_pool_free(mem_pool, (u64)buf, size);
> +}
> +
> +static int imx_fetch_soc_info(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + struct imx_se_node_info_list *info_list;
> + const struct imx_se_node_info *info;
> + struct soc_device_attribute *attr;
> + struct soc_device *sdev;
> + struct soc_info s_info;
> + int err = 0;
> +
> + info = priv->info;
> + info_list = (struct imx_se_node_info_list *)
> + device_get_match_data(dev->parent);
> + if (info_list->soc_rev)
> + return err;
> +
> + err = ele_get_info(dev, &s_info);
> + if (err)
> + s_info.major_ver = DEFAULT_IMX_SOC_VER;
> +
> + info_list->soc_rev = s_info.soc_rev;
> +
> + if (!info->soc_register)
> + return 0;
> +
> + attr = devm_kzalloc(dev, sizeof(*attr), GFP_KERNEL);
> + if (!attr)
> + return -ENOMEM;
> +
> + if (s_info.minor_ver)
> + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x.%x",
> + s_info.major_ver,
> + s_info.minor_ver);
> + else
> + attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x",
> + s_info.major_ver);
> +
> + switch (s_info.soc_id) {
> + case SOC_ID_OF_IMX8ULP:
> + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> + "i.MX8ULP");
> + break;
> + case SOC_ID_OF_IMX93:
> + attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
> + "i.MX93");
> + break;
> + }
> +
> + err = of_property_read_string(of_root, "model",
> + &attr->machine);
> + if (err) {
> + devm_kfree(dev, attr);
> + return -EINVAL;
> + }
> + attr->family = devm_kasprintf(dev, GFP_KERNEL, "Freescale i.MX");
> +
> + attr->serial_number
> + = devm_kasprintf(dev, GFP_KERNEL, "%016llX", s_info.serial_num);
> +
> + sdev = soc_device_register(attr);
> + if (IS_ERR(sdev)) {
> + devm_kfree(dev, attr->soc_id);
> + devm_kfree(dev, attr->serial_number);
> + devm_kfree(dev, attr->revision);
> + devm_kfree(dev, attr->family);
> + devm_kfree(dev, attr->machine);
> + devm_kfree(dev, attr);
> + return PTR_ERR(sdev);
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * File operations for user-space
> + */
> +
> +/* Write a message to the MU. */
> +static ssize_t se_if_fops_write(struct file *fp, const char __user *buf,
> + size_t size, loff_t *ppos)
> +{
> + struct se_api_msg *tx_msg __free(kfree);
> + struct se_if_device_ctx *dev_ctx;
> + struct se_if_priv *priv;
> + int err;
> +
> + dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + priv = dev_ctx->priv;
> + dev_dbg(priv->dev,
> + "%s: write from buf (%p)%zu, ppos=%lld\n",
> + dev_ctx->miscdev.name,
> + buf, size, ((ppos) ? *ppos : 0));
> +
> + if (down_interruptible(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + if (dev_ctx->status != MU_OPENED) {
> + err = -EINVAL;
> + goto exit;
> + }
> +
> + if (size < SE_MU_HDR_SZ) {
> + dev_err(priv->dev,
> + "%s: User buffer too small(%zu < %d)\n",
> + dev_ctx->miscdev.name,
> + size, SE_MU_HDR_SZ);
> + err = -ENOSPC;
> + goto exit;
> + }
> +
> + tx_msg = memdup_user((void __user *)ppos, size);
> + if (!tx_msg) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + /* Copy data to buffer */
> + if (copy_from_user(tx_msg, buf, size)) {
> + err = -EFAULT;
> + dev_err(priv->dev,
> + "%s: Fail copy message from user\n",
> + dev_ctx->miscdev.name);
> + goto exit;
> + }
> +
> + print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4,
> + tx_msg, size, false);
> +
> + err = imx_ele_miscdev_msg_send(dev_ctx, tx_msg, size);
> +
> +exit:
> + up(&dev_ctx->fops_lock);
> + return err;
> +}
> +
> +/*
> + * Read a message from the MU.
> + * Blocking until a message is available.
> + */
> +static ssize_t se_if_fops_read(struct file *fp, char __user *buf,
> + size_t size, loff_t *ppos)
> +{
> + struct se_if_device_ctx *dev_ctx;
> + struct se_buf_desc *b_desc;
> + struct se_if_priv *priv;
> + u32 size_to_copy;
> + int err;
> +
> + dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + priv = dev_ctx->priv;
> + dev_dbg(priv->dev,
> + "%s: read to buf %p(%zu), ppos=%lld\n",
> + dev_ctx->miscdev.name,
> + buf, size, ((ppos) ? *ppos : 0));
> +
> + if (down_interruptible(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + if (dev_ctx->status != MU_OPENED) {
> + err = -EINVAL;
> + goto exit;
> + }
> +
> + err = imx_ele_miscdev_msg_rcv(dev_ctx);
> + if (err)
> + goto exit;
> +
> + /* Buffer containing the message from FW, is
> + * allocated in callback function.
> + * Check if buffer allocation failed.
> + */
> + if (!dev_ctx->temp_resp) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + dev_dbg(priv->dev,
> + "%s: %s %s\n",
> + dev_ctx->miscdev.name,
> + __func__,
> + "message received, start transmit to user");
> +
> + /*
> + * Check that the size passed as argument is larger than
> + * the one carried in the message.
> + */
> + size_to_copy = dev_ctx->temp_resp_size << 2;
> + if (size_to_copy > size) {
> + dev_dbg(priv->dev,
> + "%s: User buffer too small (%zu < %d)\n",
> + dev_ctx->miscdev.name,
> + size, size_to_copy);
> + size_to_copy = size;
> + }
> +
> + /*
> + * We may need to copy the output data to user before
> + * delivering the completion message.
> + */
> + while (!list_empty(&dev_ctx->pending_out)) {
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> + struct se_buf_desc,
> + link);
> + if (!b_desc)
> + continue;
> +
> + if (b_desc->usr_buf_ptr && b_desc->shared_buf_ptr) {
> +
> + dev_dbg(priv->dev,
> + "%s: Copy output data to user\n",
> + dev_ctx->miscdev.name);
> + if (copy_to_user(b_desc->usr_buf_ptr,
> + b_desc->shared_buf_ptr,
> + b_desc->size)) {
> + dev_err(priv->dev,
> + "%s: Failure copying output data to user.",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> + }
> +
> + if (b_desc->shared_buf_ptr)
> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> +
> + __list_del_entry(&b_desc->link);
> + kfree(b_desc);
> + }
> +
> + /* Copy data from the buffer */
> + print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4,
> + dev_ctx->temp_resp, size_to_copy, false);
> + if (copy_to_user(buf, dev_ctx->temp_resp, size_to_copy)) {
> + dev_err(priv->dev,
> + "%s: Failed to copy to user\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> + err = size_to_copy;
> + kfree(dev_ctx->temp_resp);
> +
> + /* free memory allocated on the shared buffers. */
> + dev_ctx->secure_mem.pos = 0;
> + dev_ctx->non_secure_mem.pos = 0;
> +
> + dev_ctx->pending_hdr = 0;
> +
> +exit:
> + /*
> + * Clean the used Shared Memory space,
> + * whether its Input Data copied from user buffers, or
> + * Data received from FW.
> + */
> + while (!list_empty(&dev_ctx->pending_in) ||
> + !list_empty(&dev_ctx->pending_out)) {
> + if (!list_empty(&dev_ctx->pending_in))
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
> + struct se_buf_desc,
> + link);
> + else
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> + struct se_buf_desc,
> + link);
> +
> + if (!b_desc)
> + continue;
> +
> + if (b_desc->shared_buf_ptr)
> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> +
> + __list_del_entry(&b_desc->link);
> + kfree(b_desc);
> + }
> +
> + up(&dev_ctx->fops_lock);
> + return err;
> +}
> +
> +/* Give access to EdgeLock Enclave, to the memory we want to share */
> +static int se_if_setup_se_mem_access(struct se_if_device_ctx *dev_ctx,
> + u64 addr, u32 len)
> +{
> + /* Assuming EdgeLock Enclave has access to all the memory regions */
> + int ret = 0;
> +
> + if (ret) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Fail find memreg\n", dev_ctx->miscdev.name);
> + goto exit;
> + }
> +
> + if (ret) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Fail set permission for resource\n",
> + dev_ctx->miscdev.name);
> + goto exit;
> + }
> +
> +exit:
> + return ret;
> +}
> +
> +static int se_ioctl_get_mu_info(struct se_if_device_ctx *dev_ctx,
> + u64 arg)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev_ctx->dev);
> + struct imx_se_node_info *if_node_info;
> + struct se_ioctl_get_if_info info;
> + int err = 0;
> +
> + if_node_info = (struct imx_se_node_info *)priv->info;
> +
> + info.se_if_id = if_node_info->se_if_id;
> + info.interrupt_idx = 0;
> + info.tz = 0;
> + info.did = if_node_info->se_if_did;
> + info.cmd_tag = if_node_info->cmd_tag;
> + info.rsp_tag = if_node_info->rsp_tag;
> + info.success_tag = if_node_info->success_tag;
> + info.base_api_ver = if_node_info->base_api_ver;
> + info.fw_api_ver = if_node_info->fw_api_ver;
> +
> + dev_dbg(priv->dev,
> + "%s: info [se_if_id: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n",
> + dev_ctx->miscdev.name,
> + info.se_if_id, info.interrupt_idx, info.tz, info.did);
> +
> + if (copy_to_user((u8 *)arg, &info, sizeof(info))) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed to copy mu info to user\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> +exit:
> + return err;
> +}
> +
> +/*
> + * Copy a buffer of data to/from the user and return the address to use in
> + * messages
> + */
> +static int se_ioctl_setup_iobuf_handler(struct se_if_device_ctx *dev_ctx,
> + u64 arg)
> +{
> + struct se_ioctl_setup_iobuf io = {0};
> + struct se_shared_mem *shared_mem;
> + struct se_buf_desc *b_desc;
> + int err = 0;
> + u32 pos;
> +
> + if (copy_from_user(&io, (u8 *)arg, sizeof(io))) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed copy iobuf config from user\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> + dev_dbg(dev_ctx->priv->dev,
> + "%s: io [buf: %p(%d) flag: %x]\n",
> + dev_ctx->miscdev.name,
> + io.user_buf, io.length, io.flags);
> +
> + if (io.length == 0 || !io.user_buf) {
> + /*
> + * Accept NULL pointers since some buffers are optional
> + * in FW commands. In this case we should return 0 as
> + * pointer to be embedded into the message.
> + * Skip all data copy part of code below.
> + */
> + io.ele_addr = 0;
> + goto copy;
> + }
> +
> + /* Select the shared memory to be used for this buffer. */
> + if (io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) {
> + /* App requires to use secure memory for this buffer.*/
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed allocate SEC MEM memory\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + } else {
> + /* No specific requirement for this buffer. */
> + shared_mem = &dev_ctx->non_secure_mem;
> + }
> +
> + /* Check there is enough space in the shared memory. */
> + if (shared_mem->size < shared_mem->pos
> + || io.length >= shared_mem->size - shared_mem->pos) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Not enough space in shared memory\n",
> + dev_ctx->miscdev.name);
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + /* Allocate space in shared memory. 8 bytes aligned. */
> + pos = shared_mem->pos;
> + shared_mem->pos += round_up(io.length, 8u);
> + io.ele_addr = (u64)shared_mem->dma_addr + pos;
> +
> + if ((io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) &&
> + !(io.flags & SE_MU_IO_FLAGS_USE_SHORT_ADDR)) {
> + /*Add base address to get full address.*/
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed allocate SEC MEM memory\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> + memset(shared_mem->ptr + pos, 0, io.length);
> + if ((io.flags & SE_IO_BUF_FLAGS_IS_INPUT) ||
> + (io.flags & SE_IO_BUF_FLAGS_IS_IN_OUT)) {
> + /*
> + * buffer is input:
> + * copy data from user space to this allocated buffer.
> + */
> + if (copy_from_user(shared_mem->ptr + pos, io.user_buf,
> + io.length)) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed copy data to shared memory\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> + }
> +
> + b_desc = kzalloc(sizeof(*b_desc), GFP_KERNEL);
> + if (!b_desc) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> +copy:
> + /* Provide the EdgeLock Enclave address to user space only if success.*/
> + if (copy_to_user((u8 *)arg, &io, sizeof(io))) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed to copy iobuff setup to user\n",
> + dev_ctx->miscdev.name);
> + kfree(b_desc);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> + if (b_desc) {
> + b_desc->shared_buf_ptr = shared_mem->ptr + pos;
> + b_desc->usr_buf_ptr = io.user_buf;
> + b_desc->size = io.length;
> +
> + if (io.flags & SE_IO_BUF_FLAGS_IS_INPUT) {
> + /*
> + * buffer is input:
> + * add an entry in the "pending input buffers" list so
> + * that copied data can be cleaned from shared memory
> + * later.
> + */
> + list_add_tail(&b_desc->link, &dev_ctx->pending_in);
> + } else {
> + /*
> + * buffer is output:
> + * add an entry in the "pending out buffers" list so data
> + * can be copied to user space when receiving Secure-Enclave
> + * response.
> + */
> + list_add_tail(&b_desc->link, &dev_ctx->pending_out);
> + }
> + }
> +
> +exit:
> + return err;
> +}
> +
> +/* IOCTL to provide SoC information */
> +static int se_ioctl_get_soc_info_handler(struct se_if_device_ctx *dev_ctx,
> + u64 arg)
> +{
> + struct imx_se_node_info_list *info_list;
> + struct se_ioctl_get_soc_info soc_info;
> + int err = -EINVAL;
> +
> + info_list = (struct imx_se_node_info_list *)
> + device_get_match_data(dev_ctx->priv->dev->parent);
> + if (!info_list)
> + goto exit;
> +
> + soc_info.soc_id = info_list->soc_id;
> + soc_info.soc_rev = info_list->soc_rev;
> +
> + err = (int)copy_to_user((u8 *)arg, (u8 *)(&soc_info), sizeof(soc_info));
> + if (err) {
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed to copy soc info to user\n",
> + dev_ctx->miscdev.name);
> + err = -EFAULT;
> + goto exit;
> + }
> +
> +exit:
> + return err;
> +}
> +
> +/* Open a character device. */
> +static int se_if_fops_open(struct inode *nd, struct file *fp)
> +{
> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + int err;
> +
> + /* Avoid race if opened at the same time */
> + if (down_trylock(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + /* Authorize only 1 instance. */
> + if (dev_ctx->status != MU_FREE) {
> + err = -EBUSY;
> + goto exit;
> + }
> +
> + /*
> + * Allocate some memory for data exchanges with S40x.
> + * This will be used for data not requiring secure memory.
> + */
> + dev_ctx->non_secure_mem.ptr = dmam_alloc_coherent(dev_ctx->dev,
> + MAX_DATA_SIZE_PER_USER,
> + &dev_ctx->non_secure_mem.dma_addr,
> + GFP_KERNEL);
> + if (!dev_ctx->non_secure_mem.ptr) {
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + err = se_if_setup_se_mem_access(dev_ctx,
> + dev_ctx->non_secure_mem.dma_addr,
> + MAX_DATA_SIZE_PER_USER);
> + if (err) {
> + err = -EPERM;
> + dev_err(dev_ctx->priv->dev,
> + "%s: Failed to share access to shared memory\n",
> + dev_ctx->miscdev.name);
> + goto free_coherent;
> + }
> +
> + dev_ctx->non_secure_mem.size = MAX_DATA_SIZE_PER_USER;
> + dev_ctx->non_secure_mem.pos = 0;
> + dev_ctx->status = MU_OPENED;
> +
> + dev_ctx->pending_hdr = 0;
> +
> + goto exit;
> +
> +free_coherent:
> + dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
> + dev_ctx->non_secure_mem.ptr,
> + dev_ctx->non_secure_mem.dma_addr);
> +
> +exit:
> + up(&dev_ctx->fops_lock);
> + return err;
> +}
> +
> +/* Close a character device. */
> +static int se_if_fops_close(struct inode *nd, struct file *fp)
> +{
> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + struct se_if_priv *priv = dev_ctx->priv;
> + struct se_buf_desc *b_desc;
> +
> + /* Avoid race if closed at the same time */
> + if (down_trylock(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + /* The device context has not been opened */
> + if (dev_ctx->status != MU_OPENED)
> + goto exit;
> +
> + /* check if this device was registered as command receiver. */
> + if (priv->cmd_receiver_dev == dev_ctx)
> + priv->cmd_receiver_dev = NULL;
> +
> + /* check if this device was registered as waiting response. */
> + if (priv->waiting_rsp_dev == dev_ctx) {
> + priv->waiting_rsp_dev = NULL;
> + mutex_unlock(&priv->se_if_cmd_lock);
> + }
> +
> + /* Unmap secure memory shared buffer. */
> + if (dev_ctx->secure_mem.ptr)
> + devm_iounmap(dev_ctx->dev, dev_ctx->secure_mem.ptr);
> +
> + dev_ctx->secure_mem.ptr = NULL;
> + dev_ctx->secure_mem.dma_addr = 0;
> + dev_ctx->secure_mem.size = 0;
> + dev_ctx->secure_mem.pos = 0;
> +
> + /* Free non-secure shared buffer. */
> + dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
> + dev_ctx->non_secure_mem.ptr,
> + dev_ctx->non_secure_mem.dma_addr);
> +
> + dev_ctx->non_secure_mem.ptr = NULL;
> + dev_ctx->non_secure_mem.dma_addr = 0;
> + dev_ctx->non_secure_mem.size = 0;
> + dev_ctx->non_secure_mem.pos = 0;
> +
> + while (!list_empty(&dev_ctx->pending_in) ||
> + !list_empty(&dev_ctx->pending_out)) {
> + if (!list_empty(&dev_ctx->pending_in))
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
> + struct se_buf_desc,
> + link);
> + else
> + b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
> + struct se_buf_desc,
> + link);
> +
> + if (!b_desc)
> + continue;
> +
> + if (b_desc->shared_buf_ptr)
> + memset(b_desc->shared_buf_ptr, 0, b_desc->size);
> +
> + __list_del_entry(&b_desc->link);
> + devm_kfree(dev_ctx->dev, b_desc);
> + }
> +
> + dev_ctx->status = MU_FREE;
> +
> +exit:
> + up(&dev_ctx->fops_lock);
> + return 0;
> +}
> +
> +/* IOCTL entry point of a character device */
> +static long se_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
> +//static long se_ioctl(struct file *fp, u32 cmd, u64 arg)
> +{
> + struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
> + struct se_if_device_ctx,
> + miscdev);
> + struct se_if_priv *se_if_priv = dev_ctx->priv;
> + int err = -EINVAL;
> +
> + /* Prevent race during change of device context */
> + if (down_interruptible(&dev_ctx->fops_lock))
> + return -EBUSY;
> +
> + switch (cmd) {
> + case SE_IOCTL_ENABLE_CMD_RCV:
> + if (!se_if_priv->cmd_receiver_dev) {
> + se_if_priv->cmd_receiver_dev = dev_ctx;
> + err = 0;
> + }
> + break;
> + case SE_IOCTL_GET_MU_INFO:
> + err = se_ioctl_get_mu_info(dev_ctx, arg);
> + break;
> + case SE_IOCTL_SETUP_IOBUF:
> + err = se_ioctl_setup_iobuf_handler(dev_ctx, arg);
> + break;
> + case SE_IOCTL_GET_SOC_INFO:
> + err = se_ioctl_get_soc_info_handler(dev_ctx, arg);
> + break;
> +
> + default:
> + err = -EINVAL;
> + dev_dbg(se_if_priv->dev,
> + "%s: IOCTL %.8x not supported\n",
> + dev_ctx->miscdev.name,
> + cmd);
> + }
> +
> + up(&dev_ctx->fops_lock);
> + return (long)err;
> +}
> +
> +/* Char driver setup */
> +static const struct file_operations se_if_fops = {
> + .open = se_if_fops_open,
> + .owner = THIS_MODULE,
> + .release = se_if_fops_close,
> + .unlocked_ioctl = se_ioctl,
> + .read = se_if_fops_read,
> + .write = se_if_fops_write,
> +};
> +
> +/* interface for managed res to free a mailbox channel */
> +static void if_mbox_free_channel(void *mbox_chan)
> +{
> + mbox_free_channel(mbox_chan);
> +}
> +
> +/* interface for managed res to unregister a character device */
> +static void if_misc_deregister(void *miscdevice)
> +{
> + misc_deregister(miscdevice);
> +}
> +
> +static int se_if_request_channel(struct device *dev,
> + struct mbox_chan **chan,
> + struct mbox_client *cl,
> + const u8 *name)
> +{
> + struct mbox_chan *t_chan;
> + int ret = 0;
> +
> + t_chan = mbox_request_channel_byname(cl, name);
> + if (IS_ERR(t_chan)) {
> + ret = PTR_ERR(t_chan);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev,
> + "Failed to request chan %s ret %d\n", name,
> + ret);
> + goto exit;
> + }
> +
> + ret = devm_add_action(dev, if_mbox_free_channel, t_chan);
> + if (ret) {
> + dev_err(dev, "failed to add devm removal of mbox %s\n", name);
> + goto exit;
> + }
> +
> + *chan = t_chan;
> +
> +exit:
> + return ret;
> +}
> +
> +static int se_probe_if_cleanup(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct se_if_priv *priv;
> + int ret = 0;
> + int i;
> +
> + priv = dev_get_drvdata(dev);
> + if (!priv) {
> + ret = 0;
> + dev_dbg(dev, "SE-MU Priv data is NULL;");
> + return ret;
> + }
> +
> + if (priv->tx_chan)
> + mbox_free_channel(priv->tx_chan);
> + if (priv->rx_chan)
> + mbox_free_channel(priv->rx_chan);
> +
> + /* free the buffer in se remove, previously allocated
> + * in se probe to store encrypted IMEM
> + */
> + if (priv->imem.buf) {
> + dmam_free_coherent(dev,
> + ELE_IMEM_SIZE,
> + priv->imem.buf,
> + priv->imem.phyaddr);
> + priv->imem.buf = NULL;
> + }
> +
> + if (priv->ctxs) {
> + for (i = 0; i < priv->max_dev_ctx; i++) {
> + if (priv->ctxs[i]) {
> + devm_remove_action(dev,
> + if_misc_deregister,
> + &priv->ctxs[i]->miscdev);
> + misc_deregister(&priv->ctxs[i]->miscdev);
> + devm_kfree(dev, priv->ctxs[i]);
> + }
> + }
> + devm_kfree(dev, priv->ctxs);
> + }
> +
> + if (priv->flags & RESERVED_DMA_POOL) {
> + of_reserved_mem_device_release(dev);
> + priv->flags &= (~RESERVED_DMA_POOL);
> + }
> +
> + devm_kfree(dev, priv);
> + of_node_put(dev->of_node);
> + of_platform_device_destroy(dev, NULL);
> +
> + return ret;
> +}
> +
> +static int se_probe_cleanup(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *if_dn;
> +
> + /* Enumerate se-interface device nodes. */
> + for_each_child_of_node(dev->of_node, if_dn) {
> + struct platform_device *if_pdev
> + = of_find_device_by_node(if_dn);
> + if (se_probe_if_cleanup(if_pdev))
> + dev_err(dev,
> + "Failed to clean-up child node probe.\n");
> + }
> +
> + return 0;
> +}
> +
> +static int init_device_context(struct device *dev)
> +{
> + const struct imx_se_node_info *info;
> + struct se_if_device_ctx *dev_ctx;
> + struct se_if_priv *priv;
> + u8 *devname;
> + int ret = 0;
> + int i;
> +
> + priv = dev_get_drvdata(dev);
> +
> + if (!priv) {
> + ret = -EINVAL;
> + dev_err(dev, "Invalid SE-MU Priv data");
> + return ret;
> + }
> + info = priv->info;
> +
> + priv->ctxs = devm_kzalloc(dev, sizeof(dev_ctx) * priv->max_dev_ctx,
> + GFP_KERNEL);
> +
> + if (!priv->ctxs) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + /* Create users */
> + for (i = 0; i < priv->max_dev_ctx; i++) {
> + dev_ctx = devm_kzalloc(dev, sizeof(*dev_ctx), GFP_KERNEL);
> + if (!dev_ctx) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + dev_ctx->dev = dev;
> + dev_ctx->status = MU_FREE;
> + dev_ctx->priv = priv;
> +
> + priv->ctxs[i] = dev_ctx;
> +
> + /* Default value invalid for an header. */
> + init_waitqueue_head(&dev_ctx->wq);
> +
> + INIT_LIST_HEAD(&dev_ctx->pending_out);
> + INIT_LIST_HEAD(&dev_ctx->pending_in);
> + sema_init(&dev_ctx->fops_lock, 1);
> +
> + devname = devm_kasprintf(dev, GFP_KERNEL, "%s_ch%d",
> + info->se_name, i);
> + if (!devname) {
> + ret = -ENOMEM;
> + return ret;
> + }
> +
> + dev_ctx->miscdev.name = devname;
> + dev_ctx->miscdev.minor = MISC_DYNAMIC_MINOR;
> + dev_ctx->miscdev.fops = &se_if_fops;
> + dev_ctx->miscdev.parent = dev;
> + ret = misc_register(&dev_ctx->miscdev);
> + if (ret) {
> + dev_err(dev, "failed to register misc device %d\n",
> + ret);
> + return ret;
> + }
> +
> + ret = devm_add_action(dev, if_misc_deregister,
> + &dev_ctx->miscdev);
> + if (ret) {
> + dev_err(dev,
> + "failed[%d] to add action to the misc-dev\n",
> + ret);
> + return ret;
> + }
> + }
> +
> + return ret;
> +}
> +
> +static void se_load_firmware(const struct firmware *fw, void *context)
> +{
> + struct se_if_priv *priv = (struct se_if_priv *) context;
> + const struct imx_se_node_info *info = priv->info;
> + const u8 *se_fw_name = info->fw_name_in_rfs;
> + phys_addr_t se_fw_phyaddr;
> + u8 *se_fw_buf;
> +
> + if (!fw) {
> + if (priv->fw_fail > MAX_FW_LOAD_RETRIES)
> + dev_dbg(priv->dev,
> + "External FW not found, using ROM FW.\n");
> + else {
> + /*add a bit delay to wait for firmware priv released */
> + msleep(20);
> +
> + /* Load firmware one more time if timeout */
> + request_firmware_nowait(THIS_MODULE,
> + FW_ACTION_UEVENT, info->fw_name_in_rfs,
> + priv->dev, GFP_KERNEL, priv,
> + se_load_firmware);
> + priv->fw_fail++;
> + dev_dbg(priv->dev, "Value of retries = 0x%x.\n",
> + priv->fw_fail);
> + }
> +
> + return;
> + }
> +
> + /* allocate buffer to store the SE FW */
> + se_fw_buf = dmam_alloc_coherent(priv->dev, fw->size,
> + &se_fw_phyaddr,
> + GFP_KERNEL);
> + if (!se_fw_buf) {
> + dev_err(priv->dev, "Failed to alloc SE fw buffer memory\n");
> + goto exit;
> + }
> +
> + memcpy(se_fw_buf, fw->data, fw->size);
> +
> + if (ele_fw_authenticate(priv->dev, se_fw_phyaddr))
> + dev_err(priv->dev,
> + "Failed to authenticate & load SE firmware %s.\n",
> + se_fw_name);
> +
> +exit:
> + dmam_free_coherent(priv->dev,
> + fw->size,
> + se_fw_buf,
> + se_fw_phyaddr);
> +
> + release_firmware(fw);
> +}
> +
> +static int se_if_probe(struct platform_device *pdev)
> +{
> + struct imx_se_node_info_list *info_list;
> + struct device *dev = &pdev->dev;
> + struct imx_se_node_info *info;
> + struct se_if_priv *priv;
> + u32 idx;
> + int ret;
> +
> + if (of_property_read_u32(dev->of_node, "reg", &idx)) {
> + ret = -EINVAL;
> + goto exit;
> + }
> +
> + info_list = (struct imx_se_node_info_list *)
> + device_get_match_data(dev->parent);
> + info = get_imx_se_node_info(info_list, idx);
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv) {
> + ret = -ENOMEM;
> + goto exit;
> + }
> +
> + dev_set_drvdata(dev, priv);
> +
> + /* Mailbox client configuration */
> + priv->se_mb_cl.dev = dev;
> + priv->se_mb_cl.tx_block = false;
> + priv->se_mb_cl.knows_txdone = true;
> + priv->se_mb_cl.rx_callback = se_if_rx_callback;
> +
> + ret = se_if_request_channel(dev, &priv->tx_chan,
> + &priv->se_mb_cl, info->mbox_tx_name);
> + if (ret) {
> + if (ret == -EPROBE_DEFER)
> + dev_err(dev, "Mailbox tx channel, is not ready.\n");
> + else
> + dev_err(dev, "Failed to request tx channel\n");
> +
> + goto exit;
> + }
> +
> + ret = se_if_request_channel(dev, &priv->rx_chan,
> + &priv->se_mb_cl, info->mbox_rx_name);
> + if (ret) {
> + if (ret == -EPROBE_DEFER)
> + dev_err(dev, "Mailbox rx channel, is not ready.\n");
> + else
> + dev_dbg(dev, "Failed to request rx channel\n");
> +
> + goto exit;
> + }
> +
> + priv->dev = dev;
> + priv->info = info;
> +
> + /* Initialize the mutex. */
> + mutex_init(&priv->se_if_lock);
> + mutex_init(&priv->se_if_cmd_lock);
> +
> + priv->cmd_receiver_dev = NULL;
> + priv->waiting_rsp_dev = NULL;
> + priv->max_dev_ctx = info->max_dev_ctx;
> + priv->cmd_tag = info->cmd_tag;
> + priv->rsp_tag = info->rsp_tag;
> + priv->mem_pool_name = info->pool_name;
> + priv->success_tag = info->success_tag;
> + priv->base_api_ver = info->base_api_ver;
> + priv->fw_api_ver = info->fw_api_ver;
> +
> + init_completion(&priv->done);
> + spin_lock_init(&priv->lock);
> +
> + if (info->reserved_dma_ranges) {
> + ret = of_reserved_mem_device_init(dev);
> + if (ret) {
> + dev_err(dev,
> + "failed to init reserved memory region %d\n",
> + ret);
> + priv->flags &= (~RESERVED_DMA_POOL);
> + goto exit;
> + }
> + priv->flags |= RESERVED_DMA_POOL;
> + }
> +
> + if (info->fw_name_in_rfs) {
> + ret = request_firmware_nowait(THIS_MODULE,
> + FW_ACTION_UEVENT,
> + info->fw_name_in_rfs,
> + dev, GFP_KERNEL, priv,
> + se_load_firmware);
> + if (ret)
> + dev_warn(dev, "Failed to get firmware [%s].\n",
> + info->fw_name_in_rfs);
> + }
> +
> + ret = imx_fetch_soc_info(dev);
> + if (ret) {
> + dev_err(dev,
> + "failed[%d] to fetch SoC Info\n", ret);
> + goto exit;
> + }
> +
> + if (info->imem_mgmt) {
> + /* allocate buffer where SE store encrypted IMEM */
> + priv->imem.buf = dmam_alloc_coherent(dev, ELE_IMEM_SIZE,
> + &priv->imem.phyaddr,
> + GFP_KERNEL);
> + if (!priv->imem.buf) {
> + dev_err(dev,
> + "dmam-alloc-failed: To store encr-IMEM.\n");
> + ret = -ENOMEM;
> + goto exit;
> + }
> + }
> +
> + if (info->max_dev_ctx) {
> + ret = init_device_context(dev);
> + if (ret) {
> + dev_err(dev,
> + "Failed[0x%x] to create device contexts.\n",
> + ret);
> + goto exit;
> + }
> + }
> +
> + dev_info(dev, "i.MX secure-enclave: %s interface to firmware, configured.\n",
> + info->se_name);
> + return devm_of_platform_populate(dev);
> +
> +exit:
> + /* if execution control reaches here, if probe fails.
> + * hence doing the cleanup
> + */
> + if (se_probe_if_cleanup(pdev))
> + dev_err(dev,
> + "Failed to clean-up the child node probe.\n");
> +
> + return ret;
> +}
> +
> +static int se_probe(struct platform_device *pdev)
> +{
> + struct device_node *enum_dev_node;
> + struct device *dev = &pdev->dev;
> + int enum_count;
> + int ret;
> +
> + enum_count = of_get_child_count(dev->of_node);
> + if (!enum_count) {
> + ret = -EINVAL;
> + dev_err(dev, "Zero Tx/Rx path MU nodes.\n");
> + return ret;
> + }
> +
> + for_each_child_of_node(dev->of_node, enum_dev_node) {
> + struct platform_device *enum_plat_dev __maybe_unused;
> +
> + if (!of_device_is_available(enum_dev_node))
> + continue;
> +
> + enum_plat_dev = of_platform_device_create(enum_dev_node,
> + NULL,
> + dev);
> + if (!enum_plat_dev) {
> + ret = -EINVAL;
> + of_node_put(enum_dev_node);
> + dev_err(dev,
> + "Failed to create enumerated platform device.");
> + break;
> + }
> +
> + ret = se_if_probe(enum_plat_dev);
> + }
> + return ret;
> +}
> +
> +static int se_remove(struct platform_device *pdev)
> +{
> + if (se_probe_cleanup(pdev))
> + dev_err(&pdev->dev,
> + "i.MX Secure Enclave is not cleanly un-probed.");
> +
> + return 0;
> +}
> +
> +static int se_suspend(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + const struct imx_se_node_info *info
> + = priv->info;
> +
> + if (info && info->imem_mgmt)
> + priv->imem.size = se_save_imem_state(dev);
> +
> + return 0;
> +}
> +
> +static int se_resume(struct device *dev)
> +{
> + struct se_if_priv *priv = dev_get_drvdata(dev);
> + const struct imx_se_node_info *info
> + = priv->info;
> + int i;
> +
> + for (i = 0; i < priv->max_dev_ctx; i++)
> + wake_up_interruptible(&priv->ctxs[i]->wq);
> +
> + if (info && info->imem_mgmt)
> + se_restore_imem_state(dev);
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops se_pm = {
> + RUNTIME_PM_OPS(se_suspend, se_resume, NULL)
> +};
> +
> +static struct platform_driver se_driver = {
> + .driver = {
> + .name = "fsl-se-fw",
> + .of_match_table = se_match,
> + .pm = &se_pm,
> + },
> + .probe = se_probe,
> + .remove = se_remove,
> +};
> +MODULE_DEVICE_TABLE(of, se_match);
> +
> +module_platform_driver(se_driver);
> +
> +MODULE_AUTHOR("Pankaj Gupta <pankaj.gupta@nxp.com>");
> +MODULE_DESCRIPTION("iMX Secure Enclave Driver.");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/firmware/imx/se_ctrl.h b/drivers/firmware/imx/se_ctrl.h
> new file mode 100644
> index 000000000000..76e1ce77c52f
> --- /dev/null
> +++ b/drivers/firmware/imx/se_ctrl.h
> @@ -0,0 +1,151 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#ifndef SE_MU_H
> +#define SE_MU_H
> +
> +#include <linux/miscdevice.h>
> +#include <linux/semaphore.h>
> +#include <linux/mailbox_client.h>
> +
> +#define MAX_FW_LOAD_RETRIES 50
> +
> +#define MSG_TAG(x) (((x) & 0xff000000) >> 24)
> +#define MSG_COMMAND(x) (((x) & 0x00ff0000) >> 16)
> +#define MSG_SIZE(x) (((x) & 0x0000ff00) >> 8)
> +#define MSG_VER(x) ((x) & 0x000000ff)
> +#define RES_STATUS(x) ((x) & 0x000000ff)
> +#define MAX_DATA_SIZE_PER_USER (65 * 1024)
> +#define S4_DEFAULT_MUAP_INDEX (2)
> +#define S4_MUAP_DEFAULT_MAX_USERS (4)
> +#define MESSAGING_VERSION_6 0x6
> +#define MESSAGING_VERSION_7 0x7
> +
> +#define DEFAULT_MESSAGING_TAG_COMMAND (0x17u)
> +#define DEFAULT_MESSAGING_TAG_RESPONSE (0xe1u)
> +
> +#define SE_MU_IO_FLAGS_USE_SEC_MEM (0x02u)
> +#define SE_MU_IO_FLAGS_USE_SHORT_ADDR (0x04u)
> +
> +struct se_imem_buf {
> + u8 *buf;
> + phys_addr_t phyaddr;
> + u32 size;
> +};
> +
> +struct se_buf_desc {
> + u8 *shared_buf_ptr;
> + u8 *usr_buf_ptr;
> + u32 size;
> + struct list_head link;
> +};
> +
> +/* Status of a char device */
> +enum se_if_dev_ctx_status_t {
> + MU_FREE,
> + MU_OPENED
> +};
> +
> +struct se_shared_mem {
> + dma_addr_t dma_addr;
> + u32 size;
> + u32 pos;
> + u8 *ptr;
> +};
> +
> +/* Private struct for each char device instance. */
> +struct se_if_device_ctx {
> + struct device *dev;
> + struct se_if_priv *priv;
> + struct miscdevice miscdev;
> +
> + enum se_if_dev_ctx_status_t status;
> + wait_queue_head_t wq;
> + struct semaphore fops_lock;
> +
> + u32 pending_hdr;
> + struct list_head pending_in;
> + struct list_head pending_out;
> +
> + struct se_shared_mem secure_mem;
> + struct se_shared_mem non_secure_mem;
> +
> + u32 *temp_resp;
> + u32 temp_resp_size;
> + struct notifier_block se_notify;
> +};
> +
> +/* Header of the messages exchange with the EdgeLock Enclave */
> +struct se_msg_hdr {
> + u8 ver;
> + u8 size;
> + u8 command;
> + u8 tag;
> +} __packed;
> +
> +#define SE_MU_HDR_SZ 4
> +#define TAG_OFFSET (SE_MU_HDR_SZ - 1)
> +#define CMD_OFFSET (SE_MU_HDR_SZ - 2)
> +#define SZ_OFFSET (SE_MU_HDR_SZ - 3)
> +#define VER_OFFSET (SE_MU_HDR_SZ - 4)
> +
> +struct se_api_msg {
> + u32 header; /* u8 Tag; u8 Command; u8 Size; u8 Ver; */
> + u32 *data;
> +};
> +
> +struct se_if_priv {
> + struct se_if_device_ctx *cmd_receiver_dev;
> + struct se_if_device_ctx *waiting_rsp_dev;
> + bool no_dev_ctx_used;
> + /*
> + * prevent parallel access to the se interface registers
> + * e.g. a user trying to send a command while the other one is
> + * sending a response.
> + */
> + struct mutex se_if_lock;
> + /*
> + * prevent a command to be sent on the se interface while another one is
> + * still processing. (response to a command is allowed)
> + */
> + struct mutex se_if_cmd_lock;
> + struct device *dev;
> + u8 *mem_pool_name;
> + u8 cmd_tag;
> + u8 rsp_tag;
> + u8 success_tag;
> + u8 base_api_ver;
> + u8 fw_api_ver;
> + u32 fw_fail;
> + const void *info;
> +
> + struct mbox_client se_mb_cl;
> + struct mbox_chan *tx_chan, *rx_chan;
> + struct se_api_msg *rx_msg;
> + struct completion done;
> + spinlock_t lock;
> + /*
> + * Flag to retain the state of initialization done at
> + * the time of se-mu probe.
> + */
> + uint32_t flags;
> + u8 max_dev_ctx;
> + struct se_if_device_ctx **ctxs;
> + struct se_imem_buf imem;
> +};
> +
> +void *get_phy_buf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + dma_addr_t *buf,
> + u32 size);
> +phys_addr_t get_phy_buf_mem_pool1(struct device *dev,
> + u8 *mem_pool_name,
> + u32 **buf,
> + u32 size);
> +void free_phybuf_mem_pool(struct device *dev,
> + u8 *mem_pool_name,
> + u32 *buf,
> + u32 size);
> +#endif
> diff --git a/include/linux/firmware/imx/se_api.h b/include/linux/firmware/imx/se_api.h
> new file mode 100644
> index 000000000000..c47f84906837
> --- /dev/null
> +++ b/include/linux/firmware/imx/se_api.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#ifndef __SE_API_H__
> +#define __SE_API_H__
> +
> +#include <linux/types.h>
> +
> +#define SOC_ID_OF_IMX8ULP 0x084D
> +#define SOC_ID_OF_IMX93 0x9300
> +
> +#endif /* __SE_API_H__ */
> diff --git a/include/uapi/linux/se_ioctl.h b/include/uapi/linux/se_ioctl.h
> new file mode 100644
> index 000000000000..f68a36e9da2c
> --- /dev/null
> +++ b/include/uapi/linux/se_ioctl.h
> @@ -0,0 +1,88 @@
> +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause*/
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#ifndef SE_IOCTL_H
> +#define SE_IOCTL_H
> +
> +/* IOCTL definitions. */
> +
> +struct se_ioctl_setup_iobuf {
> + u8 *user_buf;
> + u32 length;
> + u32 flags;
> + u64 ele_addr;
> +};
> +
> +struct se_ioctl_shared_mem_cfg {
> + u32 base_offset;
> + u32 size;
> +};
> +
> +struct se_ioctl_get_if_info {
> + u8 se_if_id;
> + u8 interrupt_idx;
> + u8 tz;
> + u8 did;
> + u8 cmd_tag;
> + u8 rsp_tag;
> + u8 success_tag;
> + u8 base_api_ver;
> + u8 fw_api_ver;
> +};
> +
> +struct se_ioctl_signed_message {
> + u8 *message;
> + u32 msg_size;
> + u32 error_code;
> +};
> +
> +struct se_ioctl_get_soc_info {
> + u16 soc_id;
> + u16 soc_rev;
> +};
> +
> +/* IO Buffer Flags */
> +#define SE_IO_BUF_FLAGS_IS_OUTPUT (0x00u)
> +#define SE_IO_BUF_FLAGS_IS_INPUT (0x01u)
> +#define SE_IO_BUF_FLAGS_USE_SEC_MEM (0x02u)
> +#define SE_IO_BUF_FLAGS_USE_SHORT_ADDR (0x04u)
> +#define SE_IO_BUF_FLAGS_IS_IN_OUT (0x10u)
> +
> +/* IOCTLS */
> +#define SE_IOCTL 0x0A /* like MISC_MAJOR. */
> +
> +/*
> + * ioctl to designated the current fd as logical-reciever.
> + * This is ioctl is send when the nvm-daemon, a slave to the
> + * firmware is started by the user.
> + */
> +#define SE_IOCTL_ENABLE_CMD_RCV _IO(SE_IOCTL, 0x01)
> +
> +/*
> + * ioctl to get the buffer allocated from the memory, which is shared
> + * between kernel and FW.
> + * Post allocation, the kernel tagged the allocated memory with:
> + * Output
> + * Input
> + * Input-Output
> + * Short address
> + * Secure-memory
> + */
> +#define SE_IOCTL_SETUP_IOBUF _IOWR(SE_IOCTL, 0x03, \
> + struct se_ioctl_setup_iobuf)
> +
> +/*
> + * ioctl to get the mu information, that is used to exchange message
> + * with FW, from user-spaced.
> + */
> +#define SE_IOCTL_GET_MU_INFO _IOR(SE_IOCTL, 0x04, \
> + struct se_ioctl_get_if_info)
> +/*
> + * ioctl to get SoC Info from user-space.
> + */
> +#define SE_IOCTL_GET_SOC_INFO _IOR(SE_IOCTL, 0x06, \
> + struct se_ioctl_get_soc_info)
> +
> +#endif
>
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave
@ 2024-05-10 13:27 2% ` Pankaj Gupta
2024-05-10 16:41 0% ` Frank Li
` (2 more replies)
0 siblings, 3 replies; 200+ results
From: Pankaj Gupta @ 2024-05-10 13:27 UTC (permalink / raw)
To: Jonathan Corbet, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: linux-doc, linux-kernel, devicetree, imx, linux-arm-kernel, Pankaj Gupta
NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE),
are embedded in the SoC to support the features like HSM, SHE & V2X,
using message based communication interface.
The secure enclave FW communicates on a dedicated messaging unit(MU)
based interface(s) with application core, where kernel is running.
It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
This patch adds the driver for communication interface to secure-enclave,
for exchanging messages with NXP secure enclave HW IP(s) like EdgeLock Enclave,
both from:
- User-Space Applications via character driver.
- Kernel-space, used by kernel management layers like DM-Crypt.
ABI documentation for the NXP secure-enclave driver.
User-space library using this driver:
- i.MX Secure Enclave library:
-- URL: https://github.com/nxp-imx/imx-secure-enclave.git,
- i.MX Secure Middle-Ware:
-- URL: https://github.com/nxp-imx/imx-smw.git
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
---
Documentation/ABI/testing/se-cdev | 42 ++
drivers/firmware/imx/Kconfig | 12 +
drivers/firmware/imx/Makefile | 2 +
drivers/firmware/imx/ele_base_msg.c | 287 ++++++++
drivers/firmware/imx/ele_base_msg.h | 70 ++
drivers/firmware/imx/ele_common.c | 341 +++++++++
drivers/firmware/imx/ele_common.h | 43 ++
drivers/firmware/imx/se_ctrl.c | 1339 +++++++++++++++++++++++++++++++++++
drivers/firmware/imx/se_ctrl.h | 151 ++++
include/linux/firmware/imx/se_api.h | 14 +
include/uapi/linux/se_ioctl.h | 88 +++
11 files changed, 2389 insertions(+)
diff --git a/Documentation/ABI/testing/se-cdev b/Documentation/ABI/testing/se-cdev
new file mode 100644
index 000000000000..699525af6b86
--- /dev/null
+++ b/Documentation/ABI/testing/se-cdev
@@ -0,0 +1,42 @@
+What: /dev/<se>_mu[0-9]+_ch[0-9]+
+Date: May 2024
+KernelVersion: 6.8
+Contact: linux-imx@nxp.com, pankaj.gupta@nxp.com
+Description:
+ NXP offers multiple hardware IP(s) for secure-enclaves like EdgeLock-
+ Enclave(ELE), SECO. The character device file-descriptors
+ /dev/<se>_mu*_ch* are the interface between user-space NXP's secure-
+ enclave shared-library and the kernel driver.
+
+ The ioctl(2)-based ABI is defined and documented in
+ [include]<linux/firmware/imx/ele_mu_ioctl.h>
+ ioctl(s) are used primarily for:
+ - shared memory management
+ - allocation of I/O buffers
+ - get mu info
+ - setting a dev-ctx as receiver that is slave to fw
+ - get SoC info
+
+ The following file operations are supported:
+
+ open(2)
+ Currently the only useful flags are O_RDWR.
+
+ read(2)
+ Every read() from the opened character device context is waiting on
+ wakeup_intruptible, that gets set by the registered mailbox callback
+ function; indicating a message received from the firmware on message-
+ unit.
+
+ write(2)
+ Every write() to the opened character device context needs to acquire
+ mailbox_lock, before sending message on to the message unit.
+
+ close(2)
+ Stops and free up the I/O contexts that was associated
+ with the file descriptor.
+
+Users: https://github.com/nxp-imx/imx-secure-enclave.git,
+ https://github.com/nxp-imx/imx-smw.git
+ crypto/skcipher,
+ drivers/nvmem/imx-ocotp-ele.c
diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig
index 183613f82a11..56bdca9bd917 100644
--- a/drivers/firmware/imx/Kconfig
+++ b/drivers/firmware/imx/Kconfig
@@ -22,3 +22,15 @@ config IMX_SCU
This driver manages the IPC interface between host CPU and the
SCU firmware running on M4.
+
+config IMX_SEC_ENCLAVE
+ tristate "i.MX Embedded Secure Enclave - EdgeLock Enclave Firmware driver."
+ depends on IMX_MBOX && ARCH_MXC && ARM64
+ default m if ARCH_MXC
+
+ help
+ It is possible to use APIs exposed by the iMX Secure Enclave HW IP called:
+ - EdgeLock Enclave Firmware (for i.MX8ULP, i.MX93),
+ like base, HSM, V2X & SHE using the SAB protocol via the shared Messaging
+ Unit. This driver exposes these interfaces via a set of file descriptors
+ allowing to configure shared memory, send and receive messages.
diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile
index 8f9f04a513a8..aa9033e0e9e3 100644
--- a/drivers/firmware/imx/Makefile
+++ b/drivers/firmware/imx/Makefile
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_IMX_DSP) += imx-dsp.o
obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o
+sec_enclave-objs = se_ctrl.o ele_common.o ele_base_msg.o
+obj-${CONFIG_IMX_SEC_ENCLAVE} += sec_enclave.o
diff --git a/drivers/firmware/imx/ele_base_msg.c b/drivers/firmware/imx/ele_base_msg.c
new file mode 100644
index 000000000000..0463f26d93c7
--- /dev/null
+++ b/drivers/firmware/imx/ele_base_msg.c
@@ -0,0 +1,287 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/types.h>
+#include <linux/completion.h>
+#include <linux/dma-mapping.h>
+
+#include "ele_base_msg.h"
+#include "ele_common.h"
+
+int ele_get_info(struct device *dev, struct soc_info *s_info)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ struct se_api_msg *tx_msg __free(kfree);
+ struct se_api_msg *rx_msg __free(kfree);
+ phys_addr_t get_info_addr;
+ u32 *get_info_data;
+ u32 status;
+ int ret;
+
+ if (!priv || !s_info)
+ goto exit;
+
+ memset(s_info, 0x0, sizeof(*s_info));
+
+ if (priv->mem_pool_name)
+ get_info_data = get_phy_buf_mem_pool(dev,
+ priv->mem_pool_name,
+ &get_info_addr,
+ ELE_GET_INFO_BUFF_SZ);
+ else
+ get_info_data = dmam_alloc_coherent(dev,
+ ELE_GET_INFO_BUFF_SZ,
+ &get_info_addr,
+ GFP_KERNEL);
+ if (!get_info_data) {
+ ret = -ENOMEM;
+ dev_err(dev,
+ "%s: Failed to allocate get_info_addr.\n",
+ __func__);
+ goto exit;
+ }
+
+ tx_msg = kzalloc(ELE_GET_INFO_REQ_MSG_SZ << 2, GFP_KERNEL);
+ if (!tx_msg) {
+ ret = -ENOMEM;
+ return ret;
+ }
+
+ rx_msg = kzalloc(ELE_GET_INFO_RSP_MSG_SZ << 2, GFP_KERNEL);
+ if (!rx_msg) {
+ ret = -ENOMEM;
+ return ret;
+ }
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct se_msg_hdr *)&tx_msg->header,
+ ELE_GET_INFO_REQ,
+ ELE_GET_INFO_REQ_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ tx_msg->data[0] = upper_32_bits(get_info_addr);
+ tx_msg->data[1] = lower_32_bits(get_info_addr);
+ tx_msg->data[2] = ELE_GET_INFO_READ_SZ;
+ priv->rx_msg = rx_msg;
+ ret = imx_ele_msg_send_rcv(priv, tx_msg);
+ if (ret < 0)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ priv->rx_msg->header,
+ ELE_GET_INFO_REQ,
+ ELE_GET_INFO_RSP_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_GET_INFO_REQ, status);
+ ret = -1;
+ }
+
+ s_info->imem_state = (get_info_data[ELE_IMEM_STATE_WORD]
+ & ELE_IMEM_STATE_MASK) >> 16;
+ s_info->major_ver = (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
+ & SOC_VER_MASK) >> 24;
+ s_info->minor_ver = ((get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
+ & SOC_VER_MASK) >> 16) & 0xFF;
+ s_info->soc_rev = (get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
+ & SOC_VER_MASK) >> 16;
+ s_info->soc_id = get_info_data[GET_INFO_SOC_INFO_WORD_OFFSET]
+ & SOC_ID_MASK;
+ s_info->serial_num
+ = (u64)get_info_data[GET_INFO_SL_NUM_MSB_WORD_OFF] << 32
+ | get_info_data[GET_INFO_SL_NUM_LSB_WORD_OFF];
+exit:
+ if (get_info_addr) {
+ if (priv->mem_pool_name)
+ free_phybuf_mem_pool(dev, priv->mem_pool_name,
+ get_info_data, ELE_GET_INFO_BUFF_SZ);
+ else
+ dmam_free_coherent(dev,
+ ELE_GET_INFO_BUFF_SZ,
+ get_info_data,
+ get_info_addr);
+ }
+
+ return ret;
+}
+
+int ele_ping(struct device *dev)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ struct se_api_msg *tx_msg __free(kfree);
+ struct se_api_msg *rx_msg __free(kfree);
+ u32 status;
+ int ret;
+
+ tx_msg = kzalloc(ELE_PING_REQ_SZ << 2, GFP_KERNEL);
+ if (!tx_msg) {
+ ret = -ENOMEM;
+ return ret;
+ }
+
+ rx_msg = kzalloc(ELE_PING_RSP_SZ << 2, GFP_KERNEL);
+ if (!rx_msg) {
+ ret = -ENOMEM;
+ return ret;
+ }
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct se_msg_hdr *)&tx_msg->header,
+ ELE_PING_REQ, ELE_PING_REQ_SZ,
+ true);
+ if (ret) {
+ dev_err(dev, "Error: plat_fill_cmd_msg_hdr failed.\n");
+ goto exit;
+ }
+
+ priv->rx_msg = rx_msg;
+ ret = imx_ele_msg_send_rcv(priv, tx_msg);
+ if (ret)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ priv->rx_msg->header,
+ ELE_PING_REQ,
+ ELE_PING_RSP_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_PING_REQ, status);
+ ret = -1;
+ }
+exit:
+ return ret;
+}
+
+int ele_service_swap(struct device *dev,
+ phys_addr_t addr,
+ u32 addr_size, u16 flag)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ struct se_api_msg *tx_msg __free(kfree);
+ struct se_api_msg *rx_msg __free(kfree);
+ u32 status;
+ int ret;
+
+ tx_msg = kzalloc(ELE_SERVICE_SWAP_REQ_MSG_SZ << 2, GFP_KERNEL);
+ if (!tx_msg) {
+ ret = -ENOMEM;
+ return ret;
+ }
+
+ rx_msg = kzalloc(ELE_SERVICE_SWAP_RSP_MSG_SZ << 2, GFP_KERNEL);
+ if (!rx_msg) {
+ ret = -ENOMEM;
+ return ret;
+ }
+
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct se_msg_hdr *)&tx_msg->header,
+ ELE_SERVICE_SWAP_REQ,
+ ELE_SERVICE_SWAP_REQ_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ tx_msg->data[0] = flag;
+ tx_msg->data[1] = addr_size;
+ tx_msg->data[2] = ELE_NONE_VAL;
+ tx_msg->data[3] = lower_32_bits(addr);
+ tx_msg->data[4] = plat_add_msg_crc((uint32_t *)&tx_msg[0],
+ ELE_SERVICE_SWAP_REQ_MSG_SZ);
+ priv->rx_msg = rx_msg;
+ ret = imx_ele_msg_send_rcv(priv, tx_msg);
+ if (ret < 0)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ priv->rx_msg->header,
+ ELE_SERVICE_SWAP_REQ,
+ ELE_SERVICE_SWAP_RSP_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_SERVICE_SWAP_REQ, status);
+ ret = -1;
+ } else {
+ if (flag == ELE_IMEM_EXPORT)
+ ret = priv->rx_msg->data[1];
+ else
+ ret = 0;
+ }
+exit:
+
+ return ret;
+}
+
+int ele_fw_authenticate(struct device *dev, phys_addr_t addr)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ struct se_api_msg *tx_msg __free(kfree);
+ struct se_api_msg *rx_msg __free(kfree);
+ u32 status;
+ int ret;
+
+ tx_msg = kzalloc(ELE_FW_AUTH_REQ_SZ << 2, GFP_KERNEL);
+ if (!tx_msg) {
+ ret = -ENOMEM;
+ return ret;
+ }
+
+ rx_msg = kzalloc(ELE_FW_AUTH_RSP_MSG_SZ << 2, GFP_KERNEL);
+ if (!rx_msg) {
+ ret = -ENOMEM;
+ return ret;
+ }
+ ret = plat_fill_cmd_msg_hdr(priv,
+ (struct se_msg_hdr *)&tx_msg->header,
+ ELE_FW_AUTH_REQ,
+ ELE_FW_AUTH_REQ_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ tx_msg->data[0] = addr;
+ tx_msg->data[1] = 0x0;
+ tx_msg->data[2] = addr;
+
+ priv->rx_msg = rx_msg;
+ ret = imx_ele_msg_send_rcv(priv, tx_msg);
+ if (ret < 0)
+ goto exit;
+
+ ret = validate_rsp_hdr(priv,
+ priv->rx_msg->header,
+ ELE_FW_AUTH_REQ,
+ ELE_FW_AUTH_RSP_MSG_SZ,
+ true);
+ if (ret)
+ goto exit;
+
+ status = RES_STATUS(priv->rx_msg->data[0]);
+ if (status != priv->success_tag) {
+ dev_err(dev, "Command Id[%d], Response Failure = 0x%x",
+ ELE_FW_AUTH_REQ, status);
+ ret = -1;
+ }
+exit:
+
+ return ret;
+}
diff --git a/drivers/firmware/imx/ele_base_msg.h b/drivers/firmware/imx/ele_base_msg.h
new file mode 100644
index 000000000000..3b3d2bf04a84
--- /dev/null
+++ b/drivers/firmware/imx/ele_base_msg.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ *
+ * Header file for the EdgeLock Enclave Base API(s).
+ */
+
+#ifndef ELE_BASE_MSG_H
+#define ELE_BASE_MSG_H
+
+#include <linux/device.h>
+#include <linux/types.h>
+
+#define WORD_SZ 4
+#define ELE_NONE_VAL 0x0
+
+#define ELE_SUCCESS_IND 0xD6
+
+#define ELE_GET_INFO_REQ 0xDA
+#define ELE_GET_INFO_REQ_MSG_SZ 0x10
+#define ELE_GET_INFO_RSP_MSG_SZ 0x08
+
+#define ELE_GET_INFO_BUFF_SZ 0x100
+#define ELE_GET_INFO_READ_SZ 0xA0
+
+#define DEFAULT_IMX_SOC_VER 0xA0
+#define SOC_VER_MASK 0xFFFF0000
+#define SOC_ID_MASK 0x0000FFFF
+struct soc_info {
+ u32 imem_state;
+ u8 major_ver;
+ u8 minor_ver;
+ u16 soc_id;
+ u16 soc_rev;
+ u64 serial_num;
+};
+
+#define GET_INFO_SOC_INFO_WORD_OFFSET 1
+#define GET_INFO_UUID_WORD_OFFSET 3
+#define GET_INFO_SL_NUM_MSB_WORD_OFF \
+ (GET_INFO_UUID_WORD_OFFSET + 3)
+#define GET_INFO_SL_NUM_LSB_WORD_OFF \
+ (GET_INFO_UUID_WORD_OFFSET + 0)
+
+#define ELE_PING_REQ 0x01
+#define ELE_PING_REQ_SZ 0x04
+#define ELE_PING_RSP_SZ 0x08
+
+#define ELE_SERVICE_SWAP_REQ 0xDF
+#define ELE_SERVICE_SWAP_REQ_MSG_SZ 0x18
+#define ELE_SERVICE_SWAP_RSP_MSG_SZ 0x0C
+#define ELE_IMEM_SIZE 0x10000
+#define ELE_IMEM_STATE_OK 0xCA
+#define ELE_IMEM_STATE_BAD 0xFE
+#define ELE_IMEM_STATE_WORD 0x27
+#define ELE_IMEM_STATE_MASK 0x00ff0000
+#define ELE_IMEM_EXPORT 0x1
+#define ELE_IMEM_IMPORT 0x2
+
+#define ELE_FW_AUTH_REQ 0x02
+#define ELE_FW_AUTH_REQ_SZ 0x10
+#define ELE_FW_AUTH_RSP_MSG_SZ 0x08
+
+int ele_get_info(struct device *dev, struct soc_info *s_info);
+int ele_ping(struct device *dev);
+int ele_service_swap(struct device *dev,
+ phys_addr_t addr,
+ u32 addr_size, u16 flag);
+int ele_fw_authenticate(struct device *dev, phys_addr_t addr);
+#endif
diff --git a/drivers/firmware/imx/ele_common.c b/drivers/firmware/imx/ele_common.c
new file mode 100644
index 000000000000..dcf7f9034653
--- /dev/null
+++ b/drivers/firmware/imx/ele_common.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "ele_base_msg.h"
+#include "ele_common.h"
+
+u32 plat_add_msg_crc(u32 *msg, u32 msg_len)
+{
+ u32 nb_words = msg_len / (u32)sizeof(u32);
+ u32 crc = 0;
+ u32 i;
+
+ for (i = 0; i < nb_words - 1; i++)
+ crc ^= *(msg + i);
+
+ return crc;
+}
+
+int imx_ele_msg_rcv(struct se_if_priv *priv)
+{
+ u32 wait;
+ int err;
+
+ wait = msecs_to_jiffies(1000);
+ if (!wait_for_completion_timeout(&priv->done, wait)) {
+ dev_err(priv->dev,
+ "Error: wait_for_completion timed out.\n");
+ err = -ETIMEDOUT;
+ }
+
+ mutex_unlock(&priv->se_if_cmd_lock);
+ priv->no_dev_ctx_used = false;
+
+ return err;
+}
+
+int imx_ele_msg_send(struct se_if_priv *priv, void *mssg)
+{
+ bool is_cmd_lock_tobe_taken = false;
+ int err;
+
+ if (!priv->waiting_rsp_dev || priv->no_dev_ctx_used) {
+ is_cmd_lock_tobe_taken = true;
+ mutex_lock(&priv->se_if_cmd_lock);
+ }
+ scoped_guard(mutex, &priv->se_if_lock);
+
+ err = mbox_send_message(priv->tx_chan, mssg);
+ if (err < 0) {
+ dev_err(priv->dev, "Error: mbox_send_message failure.\n");
+ if (is_cmd_lock_tobe_taken)
+ mutex_unlock(&priv->se_if_cmd_lock);
+ return err;
+ }
+ err = 0;
+
+ return err;
+}
+
+int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg)
+{
+ int err;
+
+ priv->no_dev_ctx_used = true;
+ err = imx_ele_msg_send(priv, mssg);
+ if (err)
+ goto exit;
+
+ err = imx_ele_msg_rcv(priv);
+
+exit:
+ return err;
+}
+
+int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *dev_ctx)
+{
+ struct se_msg_hdr header = {0};
+ int err;
+
+ err = wait_event_interruptible(dev_ctx->wq, dev_ctx->pending_hdr != 0);
+ if (err)
+ dev_err(dev_ctx->dev,
+ "%s: Err[0x%x]:Interrupted by signal.\n",
+ dev_ctx->miscdev.name, err);
+
+ header = *((struct se_msg_hdr *) (&dev_ctx->temp_resp[0]));
+
+ if (header.tag == dev_ctx->priv->rsp_tag)
+ mutex_unlock(&dev_ctx->priv->se_if_cmd_lock);
+
+ return err;
+}
+
+int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
+ void *tx_msg, int tx_msg_sz)
+{
+ struct se_if_priv *priv = dev_ctx->priv;
+ struct se_msg_hdr header = {0};
+ int err;
+
+ header = *((struct se_msg_hdr *) tx_msg);
+
+ /*
+ * Check that the size passed as argument matches the size
+ * carried in the message.
+ */
+ err = header.size << 2;
+
+ if (err != tx_msg_sz) {
+ err = -EINVAL;
+ dev_err(priv->dev,
+ "%s: User buffer too small\n",
+ dev_ctx->miscdev.name);
+ goto exit;
+ }
+ /* Check the message is valid according to tags */
+ if (header.tag == priv->cmd_tag)
+ priv->waiting_rsp_dev = dev_ctx;
+ else if (header.tag == priv->rsp_tag) {
+ /* Check the device context can send the command */
+ if (dev_ctx != priv->cmd_receiver_dev) {
+ dev_err(priv->dev,
+ "%s: Channel not configured to send resp to FW.",
+ dev_ctx->miscdev.name);
+ err = -EPERM;
+ goto exit;
+ }
+ } else {
+ dev_err(priv->dev,
+ "%s: The message does not have a valid TAG\n",
+ dev_ctx->miscdev.name);
+ err = -EINVAL;
+ goto exit;
+ }
+ err = imx_ele_msg_send(priv, tx_msg);
+exit:
+ return err;
+}
+
+/*
+ * Callback called by mailbox FW, when data is received.
+ */
+void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg)
+{
+ struct device *dev = mbox_cl->dev;
+ struct se_if_device_ctx *dev_ctx;
+ struct se_api_msg *rx_msg;
+ bool is_response = false;
+ struct se_if_priv *priv;
+ struct se_msg_hdr header;
+
+ priv = dev_get_drvdata(dev);
+ if (!priv) {
+ dev_err(dev, "SE-MU Priv data is NULL;");
+ return;
+ }
+
+ /* The function can be called with NULL msg */
+ if (!msg) {
+ dev_err(dev, "Message is invalid\n");
+ return;
+ }
+
+ header.tag = ((u8 *)msg)[TAG_OFFSET];
+ header.command = ((u8 *)msg)[CMD_OFFSET];
+ header.size = ((u8 *)msg)[SZ_OFFSET];
+ header.ver = ((u8 *)msg)[VER_OFFSET];
+
+ /* Incoming command: wake up the receiver if any. */
+ if (header.tag == priv->cmd_tag) {
+ dev_dbg(dev, "Selecting cmd receiver\n");
+ dev_ctx = priv->cmd_receiver_dev;
+ } else if (header.tag == priv->rsp_tag) {
+ if (priv->waiting_rsp_dev) {
+ dev_dbg(dev, "Selecting rsp waiter\n");
+ dev_ctx = priv->waiting_rsp_dev;
+ is_response = true;
+ } else {
+ /*
+ * Reading the EdgeLock Enclave response
+ * to the command, sent by other
+ * linux kernel services.
+ */
+ spin_lock(&priv->lock);
+ memcpy(&priv->rx_msg, msg, header.size << 2);
+
+ complete(&priv->done);
+ spin_unlock(&priv->lock);
+ return;
+ }
+ } else {
+ dev_err(dev, "Failed to select a device for message: %.8x\n",
+ *((u32 *) &header));
+ return;
+ }
+ /* Init reception */
+ rx_msg = kzalloc(header.size << 2, GFP_KERNEL);
+ if (rx_msg)
+ memcpy(rx_msg, msg, header.size << 2);
+
+ dev_ctx->temp_resp = (u32 *)rx_msg;
+ dev_ctx->temp_resp_size = header.size;
+
+ /* Allow user to read */
+ dev_ctx->pending_hdr = 1;
+ wake_up_interruptible(&dev_ctx->wq);
+
+ if (is_response)
+ priv->waiting_rsp_dev = NULL;
+}
+
+int validate_rsp_hdr(struct se_if_priv *priv, u32 header,
+ uint8_t msg_id, uint8_t sz, bool is_base_api)
+{
+ int ret = -EINVAL;
+ u32 size;
+ u32 cmd;
+ u32 tag;
+ u32 ver;
+
+ tag = MSG_TAG(header);
+ cmd = MSG_COMMAND(header);
+ size = MSG_SIZE(header);
+ ver = MSG_VER(header);
+
+ do {
+ if (tag != priv->rsp_tag) {
+ dev_err(priv->dev,
+ "MSG[0x%x] Hdr: Resp tag mismatch. (0x%x != 0x%x)",
+ msg_id, tag, priv->rsp_tag);
+ break;
+ }
+
+ if (cmd != msg_id) {
+ dev_err(priv->dev,
+ "MSG Header: Cmd id mismatch. (0x%x != 0x%x)",
+ cmd, msg_id);
+ break;
+ }
+
+ if (size != (sz >> 2)) {
+ dev_err(priv->dev,
+ "MSG[0x%x] Hdr: Cmd size mismatch. (0x%x != 0x%x)",
+ msg_id, size, (sz >> 2));
+ break;
+ }
+
+ if (is_base_api && (ver != priv->base_api_ver)) {
+ dev_err(priv->dev,
+ "MSG[0x%x] Hdr: Base API Vers mismatch. (0x%x != 0x%x)",
+ msg_id, ver, priv->base_api_ver);
+ break;
+ } else if (!is_base_api && ver != priv->fw_api_ver) {
+ dev_err(priv->dev,
+ "MSG[0x%x] Hdr: FW API Vers mismatch. (0x%x != 0x%x)",
+ msg_id, ver, priv->fw_api_ver);
+ break;
+ }
+
+ ret = 0;
+
+ } while (false);
+
+ return ret;
+}
+
+int se_save_imem_state(struct device *dev)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ int ret;
+
+ /* EXPORT command will save encrypted IMEM to given address,
+ * so later in resume, IMEM can be restored from the given
+ * address.
+ *
+ * Size must be at least 64 kB.
+ */
+ ret = ele_service_swap(dev,
+ priv->imem.phyaddr,
+ ELE_IMEM_SIZE,
+ ELE_IMEM_EXPORT);
+ if (ret < 0)
+ dev_err(dev, "Failed to export IMEM\n");
+ else
+ dev_info(dev,
+ "Exported %d bytes of encrypted IMEM\n",
+ ret);
+
+ return ret;
+}
+
+int se_restore_imem_state(struct device *dev)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ struct soc_info s_info;
+ int ret;
+
+ /* get info from ELE */
+ ret = ele_get_info(dev, &s_info);
+ if (ret) {
+ dev_err(dev, "Failed to get info from ELE.\n");
+ return ret;
+ }
+
+ /* Get IMEM state, if 0xFE then import IMEM */
+ if (s_info.imem_state == ELE_IMEM_STATE_BAD) {
+ /* IMPORT command will restore IMEM from the given
+ * address, here size is the actual size returned by ELE
+ * during the export operation
+ */
+ ret = ele_service_swap(dev,
+ priv->imem.phyaddr,
+ priv->imem.size,
+ ELE_IMEM_IMPORT);
+ if (ret) {
+ dev_err(dev, "Failed to import IMEM\n");
+ goto exit;
+ }
+ } else
+ goto exit;
+
+ /* After importing IMEM, check if IMEM state is equal to 0xCA
+ * to ensure IMEM is fully loaded and
+ * ELE functionality can be used.
+ */
+ ret = ele_get_info(dev, &s_info);
+ if (ret) {
+ dev_err(dev, "Failed to get info from ELE.\n");
+ goto exit;
+ }
+
+ if (s_info.imem_state == ELE_IMEM_STATE_OK)
+ dev_info(dev, "Successfully restored IMEM\n");
+ else
+ dev_err(dev, "Failed to restore IMEM\n");
+
+exit:
+ return ret;
+}
diff --git a/drivers/firmware/imx/ele_common.h b/drivers/firmware/imx/ele_common.h
new file mode 100644
index 000000000000..6e3a2114bb56
--- /dev/null
+++ b/drivers/firmware/imx/ele_common.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+
+#ifndef __ELE_COMMON_H__
+#define __ELE_COMMON_H__
+
+#include "se_ctrl.h"
+
+#define IMX_ELE_FW_DIR "imx/ele/"
+
+uint32_t plat_add_msg_crc(uint32_t *msg, uint32_t msg_len);
+int imx_ele_miscdev_msg_rcv(struct se_if_device_ctx *priv);
+int imx_ele_miscdev_msg_send(struct se_if_device_ctx *dev_ctx,
+ void *tx_msg, int tx_msg_sz);
+int imx_ele_msg_rcv(struct se_if_priv *priv);
+int imx_ele_msg_send(struct se_if_priv *priv, void *mssg);
+int imx_ele_msg_send_rcv(struct se_if_priv *priv, void *mssg);
+void se_if_rx_callback(struct mbox_client *mbox_cl, void *msg);
+int validate_rsp_hdr(struct se_if_priv *priv, unsigned int header,
+ u8 msg_id, u8 sz, bool is_base_api);
+
+/* Fill a command message header with a given command ID and length in bytes. */
+static inline int plat_fill_cmd_msg_hdr(struct se_if_priv *priv,
+ struct se_msg_hdr *hdr,
+ u8 cmd,
+ u32 len,
+ bool is_base_api)
+{
+ hdr->tag = priv->cmd_tag;
+ hdr->ver = (is_base_api) ? priv->base_api_ver : priv->fw_api_ver;
+ hdr->command = cmd;
+ hdr->size = len >> 2;
+
+ return 0;
+}
+
+int se_save_imem_state(struct device *dev);
+int se_restore_imem_state(struct device *dev);
+
+#endif /*__ELE_COMMON_H__ */
diff --git a/drivers/firmware/imx/se_ctrl.c b/drivers/firmware/imx/se_ctrl.c
new file mode 100644
index 000000000000..11c5eaa7353f
--- /dev/null
+++ b/drivers/firmware/imx/se_ctrl.c
@@ -0,0 +1,1339 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/dev_printk.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <linux/export.h>
+#include <linux/firmware.h>
+#include <linux/firmware/imx/se_api.h>
+#include <linux/genalloc.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/miscdevice.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/sys_soc.h>
+#include <uapi/linux/se_ioctl.h>
+
+#include "ele_base_msg.h"
+#include "ele_common.h"
+#include "se_ctrl.h"
+
+#define RESERVED_DMA_POOL BIT(1)
+
+struct imx_se_node_info {
+ u8 se_if_id;
+ u8 se_if_did;
+ u8 max_dev_ctx;
+ u8 cmd_tag;
+ u8 rsp_tag;
+ u8 success_tag;
+ u8 base_api_ver;
+ u8 fw_api_ver;
+ u8 *se_name;
+ u8 *mbox_tx_name;
+ u8 *mbox_rx_name;
+ u8 *pool_name;
+ u8 *fw_name_in_rfs;
+ bool soc_register;
+ bool reserved_dma_ranges;
+ bool imem_mgmt;
+};
+
+struct imx_se_node_info_list {
+ u8 num_mu;
+ u16 soc_id;
+ u16 soc_rev;
+ struct imx_se_node_info info[];
+};
+
+static const struct imx_se_node_info_list imx8ulp_info = {
+ .num_mu = 1,
+ .soc_id = SOC_ID_OF_IMX8ULP,
+ .info = {
+ {
+ .se_if_id = 2,
+ .se_if_did = 7,
+ .max_dev_ctx = 4,
+ .cmd_tag = 0x17,
+ .rsp_tag = 0xe1,
+ .success_tag = 0xd6,
+ .base_api_ver = MESSAGING_VERSION_6,
+ .fw_api_ver = MESSAGING_VERSION_7,
+ .se_name = "hsm1",
+ .mbox_tx_name = "tx",
+ .mbox_rx_name = "rx",
+ .pool_name = "sram",
+ .fw_name_in_rfs = IMX_ELE_FW_DIR\
+ "mx8ulpa2ext-ahab-container.img",
+ .soc_register = true,
+ .reserved_dma_ranges = true,
+ .imem_mgmt = true,
+ },
+ },
+};
+
+static const struct imx_se_node_info_list imx93_info = {
+ .num_mu = 1,
+ .soc_id = SOC_ID_OF_IMX93,
+ .info = {
+ {
+ .se_if_id = 2,
+ .se_if_did = 3,
+ .max_dev_ctx = 4,
+ .cmd_tag = 0x17,
+ .rsp_tag = 0xe1,
+ .success_tag = 0xd6,
+ .base_api_ver = MESSAGING_VERSION_6,
+ .fw_api_ver = MESSAGING_VERSION_7,
+ .se_name = "hsm1",
+ .mbox_tx_name = "tx",
+ .mbox_rx_name = "rx",
+ .reserved_dma_ranges = true,
+ .imem_mgmt = true,
+ .soc_register = true,
+ },
+ },
+};
+
+static const struct of_device_id se_match[] = {
+ { .compatible = "fsl,imx8ulp-ele", .data = (void *)&imx8ulp_info},
+ { .compatible = "fsl,imx93-ele", .data = (void *)&imx93_info},
+ {},
+};
+
+static struct imx_se_node_info
+ *get_imx_se_node_info(struct imx_se_node_info_list *info_list,
+ const u32 idx)
+{
+ if (idx < 0 || idx > info_list->num_mu)
+ return NULL;
+
+ return &info_list->info[idx];
+}
+
+void *get_phy_buf_mem_pool(struct device *dev,
+ u8 *mem_pool_name,
+ dma_addr_t *buf,
+ u32 size)
+{
+ struct device_node *of_node = dev->of_node;
+ struct gen_pool *mem_pool;
+
+ mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
+ if (!mem_pool) {
+ dev_err(dev,
+ "Unable to get sram pool = %s\n",
+ mem_pool_name);
+ return 0;
+ }
+
+ return gen_pool_dma_alloc(mem_pool, size, buf);
+}
+
+void free_phybuf_mem_pool(struct device *dev,
+ u8 *mem_pool_name,
+ u32 *buf,
+ u32 size)
+{
+ struct device_node *of_node = dev->of_node;
+ struct gen_pool *mem_pool;
+
+ mem_pool = of_gen_pool_get(of_node, mem_pool_name, 0);
+ if (!mem_pool)
+ dev_err(dev,
+ "%s: Failed: Unable to get sram pool.\n",
+ __func__);
+
+ gen_pool_free(mem_pool, (u64)buf, size);
+}
+
+static int imx_fetch_soc_info(struct device *dev)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ struct imx_se_node_info_list *info_list;
+ const struct imx_se_node_info *info;
+ struct soc_device_attribute *attr;
+ struct soc_device *sdev;
+ struct soc_info s_info;
+ int err = 0;
+
+ info = priv->info;
+ info_list = (struct imx_se_node_info_list *)
+ device_get_match_data(dev->parent);
+ if (info_list->soc_rev)
+ return err;
+
+ err = ele_get_info(dev, &s_info);
+ if (err)
+ s_info.major_ver = DEFAULT_IMX_SOC_VER;
+
+ info_list->soc_rev = s_info.soc_rev;
+
+ if (!info->soc_register)
+ return 0;
+
+ attr = devm_kzalloc(dev, sizeof(*attr), GFP_KERNEL);
+ if (!attr)
+ return -ENOMEM;
+
+ if (s_info.minor_ver)
+ attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x.%x",
+ s_info.major_ver,
+ s_info.minor_ver);
+ else
+ attr->revision = devm_kasprintf(dev, GFP_KERNEL, "%x",
+ s_info.major_ver);
+
+ switch (s_info.soc_id) {
+ case SOC_ID_OF_IMX8ULP:
+ attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
+ "i.MX8ULP");
+ break;
+ case SOC_ID_OF_IMX93:
+ attr->soc_id = devm_kasprintf(dev, GFP_KERNEL,
+ "i.MX93");
+ break;
+ }
+
+ err = of_property_read_string(of_root, "model",
+ &attr->machine);
+ if (err) {
+ devm_kfree(dev, attr);
+ return -EINVAL;
+ }
+ attr->family = devm_kasprintf(dev, GFP_KERNEL, "Freescale i.MX");
+
+ attr->serial_number
+ = devm_kasprintf(dev, GFP_KERNEL, "%016llX", s_info.serial_num);
+
+ sdev = soc_device_register(attr);
+ if (IS_ERR(sdev)) {
+ devm_kfree(dev, attr->soc_id);
+ devm_kfree(dev, attr->serial_number);
+ devm_kfree(dev, attr->revision);
+ devm_kfree(dev, attr->family);
+ devm_kfree(dev, attr->machine);
+ devm_kfree(dev, attr);
+ return PTR_ERR(sdev);
+ }
+
+ return 0;
+}
+
+/*
+ * File operations for user-space
+ */
+
+/* Write a message to the MU. */
+static ssize_t se_if_fops_write(struct file *fp, const char __user *buf,
+ size_t size, loff_t *ppos)
+{
+ struct se_api_msg *tx_msg __free(kfree);
+ struct se_if_device_ctx *dev_ctx;
+ struct se_if_priv *priv;
+ int err;
+
+ dev_ctx = container_of(fp->private_data,
+ struct se_if_device_ctx,
+ miscdev);
+ priv = dev_ctx->priv;
+ dev_dbg(priv->dev,
+ "%s: write from buf (%p)%zu, ppos=%lld\n",
+ dev_ctx->miscdev.name,
+ buf, size, ((ppos) ? *ppos : 0));
+
+ if (down_interruptible(&dev_ctx->fops_lock))
+ return -EBUSY;
+
+ if (dev_ctx->status != MU_OPENED) {
+ err = -EINVAL;
+ goto exit;
+ }
+
+ if (size < SE_MU_HDR_SZ) {
+ dev_err(priv->dev,
+ "%s: User buffer too small(%zu < %d)\n",
+ dev_ctx->miscdev.name,
+ size, SE_MU_HDR_SZ);
+ err = -ENOSPC;
+ goto exit;
+ }
+
+ tx_msg = memdup_user((void __user *)ppos, size);
+ if (!tx_msg) {
+ err = -ENOMEM;
+ goto exit;
+ }
+
+ /* Copy data to buffer */
+ if (copy_from_user(tx_msg, buf, size)) {
+ err = -EFAULT;
+ dev_err(priv->dev,
+ "%s: Fail copy message from user\n",
+ dev_ctx->miscdev.name);
+ goto exit;
+ }
+
+ print_hex_dump_debug("from user ", DUMP_PREFIX_OFFSET, 4, 4,
+ tx_msg, size, false);
+
+ err = imx_ele_miscdev_msg_send(dev_ctx, tx_msg, size);
+
+exit:
+ up(&dev_ctx->fops_lock);
+ return err;
+}
+
+/*
+ * Read a message from the MU.
+ * Blocking until a message is available.
+ */
+static ssize_t se_if_fops_read(struct file *fp, char __user *buf,
+ size_t size, loff_t *ppos)
+{
+ struct se_if_device_ctx *dev_ctx;
+ struct se_buf_desc *b_desc;
+ struct se_if_priv *priv;
+ u32 size_to_copy;
+ int err;
+
+ dev_ctx = container_of(fp->private_data,
+ struct se_if_device_ctx,
+ miscdev);
+ priv = dev_ctx->priv;
+ dev_dbg(priv->dev,
+ "%s: read to buf %p(%zu), ppos=%lld\n",
+ dev_ctx->miscdev.name,
+ buf, size, ((ppos) ? *ppos : 0));
+
+ if (down_interruptible(&dev_ctx->fops_lock))
+ return -EBUSY;
+
+ if (dev_ctx->status != MU_OPENED) {
+ err = -EINVAL;
+ goto exit;
+ }
+
+ err = imx_ele_miscdev_msg_rcv(dev_ctx);
+ if (err)
+ goto exit;
+
+ /* Buffer containing the message from FW, is
+ * allocated in callback function.
+ * Check if buffer allocation failed.
+ */
+ if (!dev_ctx->temp_resp) {
+ err = -ENOMEM;
+ goto exit;
+ }
+
+ dev_dbg(priv->dev,
+ "%s: %s %s\n",
+ dev_ctx->miscdev.name,
+ __func__,
+ "message received, start transmit to user");
+
+ /*
+ * Check that the size passed as argument is larger than
+ * the one carried in the message.
+ */
+ size_to_copy = dev_ctx->temp_resp_size << 2;
+ if (size_to_copy > size) {
+ dev_dbg(priv->dev,
+ "%s: User buffer too small (%zu < %d)\n",
+ dev_ctx->miscdev.name,
+ size, size_to_copy);
+ size_to_copy = size;
+ }
+
+ /*
+ * We may need to copy the output data to user before
+ * delivering the completion message.
+ */
+ while (!list_empty(&dev_ctx->pending_out)) {
+ b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
+ struct se_buf_desc,
+ link);
+ if (!b_desc)
+ continue;
+
+ if (b_desc->usr_buf_ptr && b_desc->shared_buf_ptr) {
+
+ dev_dbg(priv->dev,
+ "%s: Copy output data to user\n",
+ dev_ctx->miscdev.name);
+ if (copy_to_user(b_desc->usr_buf_ptr,
+ b_desc->shared_buf_ptr,
+ b_desc->size)) {
+ dev_err(priv->dev,
+ "%s: Failure copying output data to user.",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+ }
+
+ if (b_desc->shared_buf_ptr)
+ memset(b_desc->shared_buf_ptr, 0, b_desc->size);
+
+ __list_del_entry(&b_desc->link);
+ kfree(b_desc);
+ }
+
+ /* Copy data from the buffer */
+ print_hex_dump_debug("to user ", DUMP_PREFIX_OFFSET, 4, 4,
+ dev_ctx->temp_resp, size_to_copy, false);
+ if (copy_to_user(buf, dev_ctx->temp_resp, size_to_copy)) {
+ dev_err(priv->dev,
+ "%s: Failed to copy to user\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+
+ err = size_to_copy;
+ kfree(dev_ctx->temp_resp);
+
+ /* free memory allocated on the shared buffers. */
+ dev_ctx->secure_mem.pos = 0;
+ dev_ctx->non_secure_mem.pos = 0;
+
+ dev_ctx->pending_hdr = 0;
+
+exit:
+ /*
+ * Clean the used Shared Memory space,
+ * whether its Input Data copied from user buffers, or
+ * Data received from FW.
+ */
+ while (!list_empty(&dev_ctx->pending_in) ||
+ !list_empty(&dev_ctx->pending_out)) {
+ if (!list_empty(&dev_ctx->pending_in))
+ b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
+ struct se_buf_desc,
+ link);
+ else
+ b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
+ struct se_buf_desc,
+ link);
+
+ if (!b_desc)
+ continue;
+
+ if (b_desc->shared_buf_ptr)
+ memset(b_desc->shared_buf_ptr, 0, b_desc->size);
+
+ __list_del_entry(&b_desc->link);
+ kfree(b_desc);
+ }
+
+ up(&dev_ctx->fops_lock);
+ return err;
+}
+
+/* Give access to EdgeLock Enclave, to the memory we want to share */
+static int se_if_setup_se_mem_access(struct se_if_device_ctx *dev_ctx,
+ u64 addr, u32 len)
+{
+ /* Assuming EdgeLock Enclave has access to all the memory regions */
+ int ret = 0;
+
+ if (ret) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Fail find memreg\n", dev_ctx->miscdev.name);
+ goto exit;
+ }
+
+ if (ret) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Fail set permission for resource\n",
+ dev_ctx->miscdev.name);
+ goto exit;
+ }
+
+exit:
+ return ret;
+}
+
+static int se_ioctl_get_mu_info(struct se_if_device_ctx *dev_ctx,
+ u64 arg)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev_ctx->dev);
+ struct imx_se_node_info *if_node_info;
+ struct se_ioctl_get_if_info info;
+ int err = 0;
+
+ if_node_info = (struct imx_se_node_info *)priv->info;
+
+ info.se_if_id = if_node_info->se_if_id;
+ info.interrupt_idx = 0;
+ info.tz = 0;
+ info.did = if_node_info->se_if_did;
+ info.cmd_tag = if_node_info->cmd_tag;
+ info.rsp_tag = if_node_info->rsp_tag;
+ info.success_tag = if_node_info->success_tag;
+ info.base_api_ver = if_node_info->base_api_ver;
+ info.fw_api_ver = if_node_info->fw_api_ver;
+
+ dev_dbg(priv->dev,
+ "%s: info [se_if_id: %d, irq_idx: %d, tz: 0x%x, did: 0x%x]\n",
+ dev_ctx->miscdev.name,
+ info.se_if_id, info.interrupt_idx, info.tz, info.did);
+
+ if (copy_to_user((u8 *)arg, &info, sizeof(info))) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed to copy mu info to user\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+
+exit:
+ return err;
+}
+
+/*
+ * Copy a buffer of data to/from the user and return the address to use in
+ * messages
+ */
+static int se_ioctl_setup_iobuf_handler(struct se_if_device_ctx *dev_ctx,
+ u64 arg)
+{
+ struct se_ioctl_setup_iobuf io = {0};
+ struct se_shared_mem *shared_mem;
+ struct se_buf_desc *b_desc;
+ int err = 0;
+ u32 pos;
+
+ if (copy_from_user(&io, (u8 *)arg, sizeof(io))) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed copy iobuf config from user\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+
+ dev_dbg(dev_ctx->priv->dev,
+ "%s: io [buf: %p(%d) flag: %x]\n",
+ dev_ctx->miscdev.name,
+ io.user_buf, io.length, io.flags);
+
+ if (io.length == 0 || !io.user_buf) {
+ /*
+ * Accept NULL pointers since some buffers are optional
+ * in FW commands. In this case we should return 0 as
+ * pointer to be embedded into the message.
+ * Skip all data copy part of code below.
+ */
+ io.ele_addr = 0;
+ goto copy;
+ }
+
+ /* Select the shared memory to be used for this buffer. */
+ if (io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) {
+ /* App requires to use secure memory for this buffer.*/
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed allocate SEC MEM memory\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ } else {
+ /* No specific requirement for this buffer. */
+ shared_mem = &dev_ctx->non_secure_mem;
+ }
+
+ /* Check there is enough space in the shared memory. */
+ if (shared_mem->size < shared_mem->pos
+ || io.length >= shared_mem->size - shared_mem->pos) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Not enough space in shared memory\n",
+ dev_ctx->miscdev.name);
+ err = -ENOMEM;
+ goto exit;
+ }
+
+ /* Allocate space in shared memory. 8 bytes aligned. */
+ pos = shared_mem->pos;
+ shared_mem->pos += round_up(io.length, 8u);
+ io.ele_addr = (u64)shared_mem->dma_addr + pos;
+
+ if ((io.flags & SE_MU_IO_FLAGS_USE_SEC_MEM) &&
+ !(io.flags & SE_MU_IO_FLAGS_USE_SHORT_ADDR)) {
+ /*Add base address to get full address.*/
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed allocate SEC MEM memory\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+
+ memset(shared_mem->ptr + pos, 0, io.length);
+ if ((io.flags & SE_IO_BUF_FLAGS_IS_INPUT) ||
+ (io.flags & SE_IO_BUF_FLAGS_IS_IN_OUT)) {
+ /*
+ * buffer is input:
+ * copy data from user space to this allocated buffer.
+ */
+ if (copy_from_user(shared_mem->ptr + pos, io.user_buf,
+ io.length)) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed copy data to shared memory\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+ }
+
+ b_desc = kzalloc(sizeof(*b_desc), GFP_KERNEL);
+ if (!b_desc) {
+ err = -ENOMEM;
+ goto exit;
+ }
+
+copy:
+ /* Provide the EdgeLock Enclave address to user space only if success.*/
+ if (copy_to_user((u8 *)arg, &io, sizeof(io))) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed to copy iobuff setup to user\n",
+ dev_ctx->miscdev.name);
+ kfree(b_desc);
+ err = -EFAULT;
+ goto exit;
+ }
+
+ if (b_desc) {
+ b_desc->shared_buf_ptr = shared_mem->ptr + pos;
+ b_desc->usr_buf_ptr = io.user_buf;
+ b_desc->size = io.length;
+
+ if (io.flags & SE_IO_BUF_FLAGS_IS_INPUT) {
+ /*
+ * buffer is input:
+ * add an entry in the "pending input buffers" list so
+ * that copied data can be cleaned from shared memory
+ * later.
+ */
+ list_add_tail(&b_desc->link, &dev_ctx->pending_in);
+ } else {
+ /*
+ * buffer is output:
+ * add an entry in the "pending out buffers" list so data
+ * can be copied to user space when receiving Secure-Enclave
+ * response.
+ */
+ list_add_tail(&b_desc->link, &dev_ctx->pending_out);
+ }
+ }
+
+exit:
+ return err;
+}
+
+/* IOCTL to provide SoC information */
+static int se_ioctl_get_soc_info_handler(struct se_if_device_ctx *dev_ctx,
+ u64 arg)
+{
+ struct imx_se_node_info_list *info_list;
+ struct se_ioctl_get_soc_info soc_info;
+ int err = -EINVAL;
+
+ info_list = (struct imx_se_node_info_list *)
+ device_get_match_data(dev_ctx->priv->dev->parent);
+ if (!info_list)
+ goto exit;
+
+ soc_info.soc_id = info_list->soc_id;
+ soc_info.soc_rev = info_list->soc_rev;
+
+ err = (int)copy_to_user((u8 *)arg, (u8 *)(&soc_info), sizeof(soc_info));
+ if (err) {
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed to copy soc info to user\n",
+ dev_ctx->miscdev.name);
+ err = -EFAULT;
+ goto exit;
+ }
+
+exit:
+ return err;
+}
+
+/* Open a character device. */
+static int se_if_fops_open(struct inode *nd, struct file *fp)
+{
+ struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
+ struct se_if_device_ctx,
+ miscdev);
+ int err;
+
+ /* Avoid race if opened at the same time */
+ if (down_trylock(&dev_ctx->fops_lock))
+ return -EBUSY;
+
+ /* Authorize only 1 instance. */
+ if (dev_ctx->status != MU_FREE) {
+ err = -EBUSY;
+ goto exit;
+ }
+
+ /*
+ * Allocate some memory for data exchanges with S40x.
+ * This will be used for data not requiring secure memory.
+ */
+ dev_ctx->non_secure_mem.ptr = dmam_alloc_coherent(dev_ctx->dev,
+ MAX_DATA_SIZE_PER_USER,
+ &dev_ctx->non_secure_mem.dma_addr,
+ GFP_KERNEL);
+ if (!dev_ctx->non_secure_mem.ptr) {
+ err = -ENOMEM;
+ goto exit;
+ }
+
+ err = se_if_setup_se_mem_access(dev_ctx,
+ dev_ctx->non_secure_mem.dma_addr,
+ MAX_DATA_SIZE_PER_USER);
+ if (err) {
+ err = -EPERM;
+ dev_err(dev_ctx->priv->dev,
+ "%s: Failed to share access to shared memory\n",
+ dev_ctx->miscdev.name);
+ goto free_coherent;
+ }
+
+ dev_ctx->non_secure_mem.size = MAX_DATA_SIZE_PER_USER;
+ dev_ctx->non_secure_mem.pos = 0;
+ dev_ctx->status = MU_OPENED;
+
+ dev_ctx->pending_hdr = 0;
+
+ goto exit;
+
+free_coherent:
+ dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
+ dev_ctx->non_secure_mem.ptr,
+ dev_ctx->non_secure_mem.dma_addr);
+
+exit:
+ up(&dev_ctx->fops_lock);
+ return err;
+}
+
+/* Close a character device. */
+static int se_if_fops_close(struct inode *nd, struct file *fp)
+{
+ struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
+ struct se_if_device_ctx,
+ miscdev);
+ struct se_if_priv *priv = dev_ctx->priv;
+ struct se_buf_desc *b_desc;
+
+ /* Avoid race if closed at the same time */
+ if (down_trylock(&dev_ctx->fops_lock))
+ return -EBUSY;
+
+ /* The device context has not been opened */
+ if (dev_ctx->status != MU_OPENED)
+ goto exit;
+
+ /* check if this device was registered as command receiver. */
+ if (priv->cmd_receiver_dev == dev_ctx)
+ priv->cmd_receiver_dev = NULL;
+
+ /* check if this device was registered as waiting response. */
+ if (priv->waiting_rsp_dev == dev_ctx) {
+ priv->waiting_rsp_dev = NULL;
+ mutex_unlock(&priv->se_if_cmd_lock);
+ }
+
+ /* Unmap secure memory shared buffer. */
+ if (dev_ctx->secure_mem.ptr)
+ devm_iounmap(dev_ctx->dev, dev_ctx->secure_mem.ptr);
+
+ dev_ctx->secure_mem.ptr = NULL;
+ dev_ctx->secure_mem.dma_addr = 0;
+ dev_ctx->secure_mem.size = 0;
+ dev_ctx->secure_mem.pos = 0;
+
+ /* Free non-secure shared buffer. */
+ dmam_free_coherent(dev_ctx->priv->dev, MAX_DATA_SIZE_PER_USER,
+ dev_ctx->non_secure_mem.ptr,
+ dev_ctx->non_secure_mem.dma_addr);
+
+ dev_ctx->non_secure_mem.ptr = NULL;
+ dev_ctx->non_secure_mem.dma_addr = 0;
+ dev_ctx->non_secure_mem.size = 0;
+ dev_ctx->non_secure_mem.pos = 0;
+
+ while (!list_empty(&dev_ctx->pending_in) ||
+ !list_empty(&dev_ctx->pending_out)) {
+ if (!list_empty(&dev_ctx->pending_in))
+ b_desc = list_first_entry_or_null(&dev_ctx->pending_in,
+ struct se_buf_desc,
+ link);
+ else
+ b_desc = list_first_entry_or_null(&dev_ctx->pending_out,
+ struct se_buf_desc,
+ link);
+
+ if (!b_desc)
+ continue;
+
+ if (b_desc->shared_buf_ptr)
+ memset(b_desc->shared_buf_ptr, 0, b_desc->size);
+
+ __list_del_entry(&b_desc->link);
+ devm_kfree(dev_ctx->dev, b_desc);
+ }
+
+ dev_ctx->status = MU_FREE;
+
+exit:
+ up(&dev_ctx->fops_lock);
+ return 0;
+}
+
+/* IOCTL entry point of a character device */
+static long se_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
+//static long se_ioctl(struct file *fp, u32 cmd, u64 arg)
+{
+ struct se_if_device_ctx *dev_ctx = container_of(fp->private_data,
+ struct se_if_device_ctx,
+ miscdev);
+ struct se_if_priv *se_if_priv = dev_ctx->priv;
+ int err = -EINVAL;
+
+ /* Prevent race during change of device context */
+ if (down_interruptible(&dev_ctx->fops_lock))
+ return -EBUSY;
+
+ switch (cmd) {
+ case SE_IOCTL_ENABLE_CMD_RCV:
+ if (!se_if_priv->cmd_receiver_dev) {
+ se_if_priv->cmd_receiver_dev = dev_ctx;
+ err = 0;
+ }
+ break;
+ case SE_IOCTL_GET_MU_INFO:
+ err = se_ioctl_get_mu_info(dev_ctx, arg);
+ break;
+ case SE_IOCTL_SETUP_IOBUF:
+ err = se_ioctl_setup_iobuf_handler(dev_ctx, arg);
+ break;
+ case SE_IOCTL_GET_SOC_INFO:
+ err = se_ioctl_get_soc_info_handler(dev_ctx, arg);
+ break;
+
+ default:
+ err = -EINVAL;
+ dev_dbg(se_if_priv->dev,
+ "%s: IOCTL %.8x not supported\n",
+ dev_ctx->miscdev.name,
+ cmd);
+ }
+
+ up(&dev_ctx->fops_lock);
+ return (long)err;
+}
+
+/* Char driver setup */
+static const struct file_operations se_if_fops = {
+ .open = se_if_fops_open,
+ .owner = THIS_MODULE,
+ .release = se_if_fops_close,
+ .unlocked_ioctl = se_ioctl,
+ .read = se_if_fops_read,
+ .write = se_if_fops_write,
+};
+
+/* interface for managed res to free a mailbox channel */
+static void if_mbox_free_channel(void *mbox_chan)
+{
+ mbox_free_channel(mbox_chan);
+}
+
+/* interface for managed res to unregister a character device */
+static void if_misc_deregister(void *miscdevice)
+{
+ misc_deregister(miscdevice);
+}
+
+static int se_if_request_channel(struct device *dev,
+ struct mbox_chan **chan,
+ struct mbox_client *cl,
+ const u8 *name)
+{
+ struct mbox_chan *t_chan;
+ int ret = 0;
+
+ t_chan = mbox_request_channel_byname(cl, name);
+ if (IS_ERR(t_chan)) {
+ ret = PTR_ERR(t_chan);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev,
+ "Failed to request chan %s ret %d\n", name,
+ ret);
+ goto exit;
+ }
+
+ ret = devm_add_action(dev, if_mbox_free_channel, t_chan);
+ if (ret) {
+ dev_err(dev, "failed to add devm removal of mbox %s\n", name);
+ goto exit;
+ }
+
+ *chan = t_chan;
+
+exit:
+ return ret;
+}
+
+static int se_probe_if_cleanup(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct se_if_priv *priv;
+ int ret = 0;
+ int i;
+
+ priv = dev_get_drvdata(dev);
+ if (!priv) {
+ ret = 0;
+ dev_dbg(dev, "SE-MU Priv data is NULL;");
+ return ret;
+ }
+
+ if (priv->tx_chan)
+ mbox_free_channel(priv->tx_chan);
+ if (priv->rx_chan)
+ mbox_free_channel(priv->rx_chan);
+
+ /* free the buffer in se remove, previously allocated
+ * in se probe to store encrypted IMEM
+ */
+ if (priv->imem.buf) {
+ dmam_free_coherent(dev,
+ ELE_IMEM_SIZE,
+ priv->imem.buf,
+ priv->imem.phyaddr);
+ priv->imem.buf = NULL;
+ }
+
+ if (priv->ctxs) {
+ for (i = 0; i < priv->max_dev_ctx; i++) {
+ if (priv->ctxs[i]) {
+ devm_remove_action(dev,
+ if_misc_deregister,
+ &priv->ctxs[i]->miscdev);
+ misc_deregister(&priv->ctxs[i]->miscdev);
+ devm_kfree(dev, priv->ctxs[i]);
+ }
+ }
+ devm_kfree(dev, priv->ctxs);
+ }
+
+ if (priv->flags & RESERVED_DMA_POOL) {
+ of_reserved_mem_device_release(dev);
+ priv->flags &= (~RESERVED_DMA_POOL);
+ }
+
+ devm_kfree(dev, priv);
+ of_node_put(dev->of_node);
+ of_platform_device_destroy(dev, NULL);
+
+ return ret;
+}
+
+static int se_probe_cleanup(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *if_dn;
+
+ /* Enumerate se-interface device nodes. */
+ for_each_child_of_node(dev->of_node, if_dn) {
+ struct platform_device *if_pdev
+ = of_find_device_by_node(if_dn);
+ if (se_probe_if_cleanup(if_pdev))
+ dev_err(dev,
+ "Failed to clean-up child node probe.\n");
+ }
+
+ return 0;
+}
+
+static int init_device_context(struct device *dev)
+{
+ const struct imx_se_node_info *info;
+ struct se_if_device_ctx *dev_ctx;
+ struct se_if_priv *priv;
+ u8 *devname;
+ int ret = 0;
+ int i;
+
+ priv = dev_get_drvdata(dev);
+
+ if (!priv) {
+ ret = -EINVAL;
+ dev_err(dev, "Invalid SE-MU Priv data");
+ return ret;
+ }
+ info = priv->info;
+
+ priv->ctxs = devm_kzalloc(dev, sizeof(dev_ctx) * priv->max_dev_ctx,
+ GFP_KERNEL);
+
+ if (!priv->ctxs) {
+ ret = -ENOMEM;
+ return ret;
+ }
+
+ /* Create users */
+ for (i = 0; i < priv->max_dev_ctx; i++) {
+ dev_ctx = devm_kzalloc(dev, sizeof(*dev_ctx), GFP_KERNEL);
+ if (!dev_ctx) {
+ ret = -ENOMEM;
+ return ret;
+ }
+
+ dev_ctx->dev = dev;
+ dev_ctx->status = MU_FREE;
+ dev_ctx->priv = priv;
+
+ priv->ctxs[i] = dev_ctx;
+
+ /* Default value invalid for an header. */
+ init_waitqueue_head(&dev_ctx->wq);
+
+ INIT_LIST_HEAD(&dev_ctx->pending_out);
+ INIT_LIST_HEAD(&dev_ctx->pending_in);
+ sema_init(&dev_ctx->fops_lock, 1);
+
+ devname = devm_kasprintf(dev, GFP_KERNEL, "%s_ch%d",
+ info->se_name, i);
+ if (!devname) {
+ ret = -ENOMEM;
+ return ret;
+ }
+
+ dev_ctx->miscdev.name = devname;
+ dev_ctx->miscdev.minor = MISC_DYNAMIC_MINOR;
+ dev_ctx->miscdev.fops = &se_if_fops;
+ dev_ctx->miscdev.parent = dev;
+ ret = misc_register(&dev_ctx->miscdev);
+ if (ret) {
+ dev_err(dev, "failed to register misc device %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = devm_add_action(dev, if_misc_deregister,
+ &dev_ctx->miscdev);
+ if (ret) {
+ dev_err(dev,
+ "failed[%d] to add action to the misc-dev\n",
+ ret);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static void se_load_firmware(const struct firmware *fw, void *context)
+{
+ struct se_if_priv *priv = (struct se_if_priv *) context;
+ const struct imx_se_node_info *info = priv->info;
+ const u8 *se_fw_name = info->fw_name_in_rfs;
+ phys_addr_t se_fw_phyaddr;
+ u8 *se_fw_buf;
+
+ if (!fw) {
+ if (priv->fw_fail > MAX_FW_LOAD_RETRIES)
+ dev_dbg(priv->dev,
+ "External FW not found, using ROM FW.\n");
+ else {
+ /*add a bit delay to wait for firmware priv released */
+ msleep(20);
+
+ /* Load firmware one more time if timeout */
+ request_firmware_nowait(THIS_MODULE,
+ FW_ACTION_UEVENT, info->fw_name_in_rfs,
+ priv->dev, GFP_KERNEL, priv,
+ se_load_firmware);
+ priv->fw_fail++;
+ dev_dbg(priv->dev, "Value of retries = 0x%x.\n",
+ priv->fw_fail);
+ }
+
+ return;
+ }
+
+ /* allocate buffer to store the SE FW */
+ se_fw_buf = dmam_alloc_coherent(priv->dev, fw->size,
+ &se_fw_phyaddr,
+ GFP_KERNEL);
+ if (!se_fw_buf) {
+ dev_err(priv->dev, "Failed to alloc SE fw buffer memory\n");
+ goto exit;
+ }
+
+ memcpy(se_fw_buf, fw->data, fw->size);
+
+ if (ele_fw_authenticate(priv->dev, se_fw_phyaddr))
+ dev_err(priv->dev,
+ "Failed to authenticate & load SE firmware %s.\n",
+ se_fw_name);
+
+exit:
+ dmam_free_coherent(priv->dev,
+ fw->size,
+ se_fw_buf,
+ se_fw_phyaddr);
+
+ release_firmware(fw);
+}
+
+static int se_if_probe(struct platform_device *pdev)
+{
+ struct imx_se_node_info_list *info_list;
+ struct device *dev = &pdev->dev;
+ struct imx_se_node_info *info;
+ struct se_if_priv *priv;
+ u32 idx;
+ int ret;
+
+ if (of_property_read_u32(dev->of_node, "reg", &idx)) {
+ ret = -EINVAL;
+ goto exit;
+ }
+
+ info_list = (struct imx_se_node_info_list *)
+ device_get_match_data(dev->parent);
+ info = get_imx_se_node_info(info_list, idx);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ dev_set_drvdata(dev, priv);
+
+ /* Mailbox client configuration */
+ priv->se_mb_cl.dev = dev;
+ priv->se_mb_cl.tx_block = false;
+ priv->se_mb_cl.knows_txdone = true;
+ priv->se_mb_cl.rx_callback = se_if_rx_callback;
+
+ ret = se_if_request_channel(dev, &priv->tx_chan,
+ &priv->se_mb_cl, info->mbox_tx_name);
+ if (ret) {
+ if (ret == -EPROBE_DEFER)
+ dev_err(dev, "Mailbox tx channel, is not ready.\n");
+ else
+ dev_err(dev, "Failed to request tx channel\n");
+
+ goto exit;
+ }
+
+ ret = se_if_request_channel(dev, &priv->rx_chan,
+ &priv->se_mb_cl, info->mbox_rx_name);
+ if (ret) {
+ if (ret == -EPROBE_DEFER)
+ dev_err(dev, "Mailbox rx channel, is not ready.\n");
+ else
+ dev_dbg(dev, "Failed to request rx channel\n");
+
+ goto exit;
+ }
+
+ priv->dev = dev;
+ priv->info = info;
+
+ /* Initialize the mutex. */
+ mutex_init(&priv->se_if_lock);
+ mutex_init(&priv->se_if_cmd_lock);
+
+ priv->cmd_receiver_dev = NULL;
+ priv->waiting_rsp_dev = NULL;
+ priv->max_dev_ctx = info->max_dev_ctx;
+ priv->cmd_tag = info->cmd_tag;
+ priv->rsp_tag = info->rsp_tag;
+ priv->mem_pool_name = info->pool_name;
+ priv->success_tag = info->success_tag;
+ priv->base_api_ver = info->base_api_ver;
+ priv->fw_api_ver = info->fw_api_ver;
+
+ init_completion(&priv->done);
+ spin_lock_init(&priv->lock);
+
+ if (info->reserved_dma_ranges) {
+ ret = of_reserved_mem_device_init(dev);
+ if (ret) {
+ dev_err(dev,
+ "failed to init reserved memory region %d\n",
+ ret);
+ priv->flags &= (~RESERVED_DMA_POOL);
+ goto exit;
+ }
+ priv->flags |= RESERVED_DMA_POOL;
+ }
+
+ if (info->fw_name_in_rfs) {
+ ret = request_firmware_nowait(THIS_MODULE,
+ FW_ACTION_UEVENT,
+ info->fw_name_in_rfs,
+ dev, GFP_KERNEL, priv,
+ se_load_firmware);
+ if (ret)
+ dev_warn(dev, "Failed to get firmware [%s].\n",
+ info->fw_name_in_rfs);
+ }
+
+ ret = imx_fetch_soc_info(dev);
+ if (ret) {
+ dev_err(dev,
+ "failed[%d] to fetch SoC Info\n", ret);
+ goto exit;
+ }
+
+ if (info->imem_mgmt) {
+ /* allocate buffer where SE store encrypted IMEM */
+ priv->imem.buf = dmam_alloc_coherent(dev, ELE_IMEM_SIZE,
+ &priv->imem.phyaddr,
+ GFP_KERNEL);
+ if (!priv->imem.buf) {
+ dev_err(dev,
+ "dmam-alloc-failed: To store encr-IMEM.\n");
+ ret = -ENOMEM;
+ goto exit;
+ }
+ }
+
+ if (info->max_dev_ctx) {
+ ret = init_device_context(dev);
+ if (ret) {
+ dev_err(dev,
+ "Failed[0x%x] to create device contexts.\n",
+ ret);
+ goto exit;
+ }
+ }
+
+ dev_info(dev, "i.MX secure-enclave: %s interface to firmware, configured.\n",
+ info->se_name);
+ return devm_of_platform_populate(dev);
+
+exit:
+ /* if execution control reaches here, if probe fails.
+ * hence doing the cleanup
+ */
+ if (se_probe_if_cleanup(pdev))
+ dev_err(dev,
+ "Failed to clean-up the child node probe.\n");
+
+ return ret;
+}
+
+static int se_probe(struct platform_device *pdev)
+{
+ struct device_node *enum_dev_node;
+ struct device *dev = &pdev->dev;
+ int enum_count;
+ int ret;
+
+ enum_count = of_get_child_count(dev->of_node);
+ if (!enum_count) {
+ ret = -EINVAL;
+ dev_err(dev, "Zero Tx/Rx path MU nodes.\n");
+ return ret;
+ }
+
+ for_each_child_of_node(dev->of_node, enum_dev_node) {
+ struct platform_device *enum_plat_dev __maybe_unused;
+
+ if (!of_device_is_available(enum_dev_node))
+ continue;
+
+ enum_plat_dev = of_platform_device_create(enum_dev_node,
+ NULL,
+ dev);
+ if (!enum_plat_dev) {
+ ret = -EINVAL;
+ of_node_put(enum_dev_node);
+ dev_err(dev,
+ "Failed to create enumerated platform device.");
+ break;
+ }
+
+ ret = se_if_probe(enum_plat_dev);
+ }
+ return ret;
+}
+
+static int se_remove(struct platform_device *pdev)
+{
+ if (se_probe_cleanup(pdev))
+ dev_err(&pdev->dev,
+ "i.MX Secure Enclave is not cleanly un-probed.");
+
+ return 0;
+}
+
+static int se_suspend(struct device *dev)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ const struct imx_se_node_info *info
+ = priv->info;
+
+ if (info && info->imem_mgmt)
+ priv->imem.size = se_save_imem_state(dev);
+
+ return 0;
+}
+
+static int se_resume(struct device *dev)
+{
+ struct se_if_priv *priv = dev_get_drvdata(dev);
+ const struct imx_se_node_info *info
+ = priv->info;
+ int i;
+
+ for (i = 0; i < priv->max_dev_ctx; i++)
+ wake_up_interruptible(&priv->ctxs[i]->wq);
+
+ if (info && info->imem_mgmt)
+ se_restore_imem_state(dev);
+
+ return 0;
+}
+
+static const struct dev_pm_ops se_pm = {
+ RUNTIME_PM_OPS(se_suspend, se_resume, NULL)
+};
+
+static struct platform_driver se_driver = {
+ .driver = {
+ .name = "fsl-se-fw",
+ .of_match_table = se_match,
+ .pm = &se_pm,
+ },
+ .probe = se_probe,
+ .remove = se_remove,
+};
+MODULE_DEVICE_TABLE(of, se_match);
+
+module_platform_driver(se_driver);
+
+MODULE_AUTHOR("Pankaj Gupta <pankaj.gupta@nxp.com>");
+MODULE_DESCRIPTION("iMX Secure Enclave Driver.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/firmware/imx/se_ctrl.h b/drivers/firmware/imx/se_ctrl.h
new file mode 100644
index 000000000000..76e1ce77c52f
--- /dev/null
+++ b/drivers/firmware/imx/se_ctrl.h
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef SE_MU_H
+#define SE_MU_H
+
+#include <linux/miscdevice.h>
+#include <linux/semaphore.h>
+#include <linux/mailbox_client.h>
+
+#define MAX_FW_LOAD_RETRIES 50
+
+#define MSG_TAG(x) (((x) & 0xff000000) >> 24)
+#define MSG_COMMAND(x) (((x) & 0x00ff0000) >> 16)
+#define MSG_SIZE(x) (((x) & 0x0000ff00) >> 8)
+#define MSG_VER(x) ((x) & 0x000000ff)
+#define RES_STATUS(x) ((x) & 0x000000ff)
+#define MAX_DATA_SIZE_PER_USER (65 * 1024)
+#define S4_DEFAULT_MUAP_INDEX (2)
+#define S4_MUAP_DEFAULT_MAX_USERS (4)
+#define MESSAGING_VERSION_6 0x6
+#define MESSAGING_VERSION_7 0x7
+
+#define DEFAULT_MESSAGING_TAG_COMMAND (0x17u)
+#define DEFAULT_MESSAGING_TAG_RESPONSE (0xe1u)
+
+#define SE_MU_IO_FLAGS_USE_SEC_MEM (0x02u)
+#define SE_MU_IO_FLAGS_USE_SHORT_ADDR (0x04u)
+
+struct se_imem_buf {
+ u8 *buf;
+ phys_addr_t phyaddr;
+ u32 size;
+};
+
+struct se_buf_desc {
+ u8 *shared_buf_ptr;
+ u8 *usr_buf_ptr;
+ u32 size;
+ struct list_head link;
+};
+
+/* Status of a char device */
+enum se_if_dev_ctx_status_t {
+ MU_FREE,
+ MU_OPENED
+};
+
+struct se_shared_mem {
+ dma_addr_t dma_addr;
+ u32 size;
+ u32 pos;
+ u8 *ptr;
+};
+
+/* Private struct for each char device instance. */
+struct se_if_device_ctx {
+ struct device *dev;
+ struct se_if_priv *priv;
+ struct miscdevice miscdev;
+
+ enum se_if_dev_ctx_status_t status;
+ wait_queue_head_t wq;
+ struct semaphore fops_lock;
+
+ u32 pending_hdr;
+ struct list_head pending_in;
+ struct list_head pending_out;
+
+ struct se_shared_mem secure_mem;
+ struct se_shared_mem non_secure_mem;
+
+ u32 *temp_resp;
+ u32 temp_resp_size;
+ struct notifier_block se_notify;
+};
+
+/* Header of the messages exchange with the EdgeLock Enclave */
+struct se_msg_hdr {
+ u8 ver;
+ u8 size;
+ u8 command;
+ u8 tag;
+} __packed;
+
+#define SE_MU_HDR_SZ 4
+#define TAG_OFFSET (SE_MU_HDR_SZ - 1)
+#define CMD_OFFSET (SE_MU_HDR_SZ - 2)
+#define SZ_OFFSET (SE_MU_HDR_SZ - 3)
+#define VER_OFFSET (SE_MU_HDR_SZ - 4)
+
+struct se_api_msg {
+ u32 header; /* u8 Tag; u8 Command; u8 Size; u8 Ver; */
+ u32 *data;
+};
+
+struct se_if_priv {
+ struct se_if_device_ctx *cmd_receiver_dev;
+ struct se_if_device_ctx *waiting_rsp_dev;
+ bool no_dev_ctx_used;
+ /*
+ * prevent parallel access to the se interface registers
+ * e.g. a user trying to send a command while the other one is
+ * sending a response.
+ */
+ struct mutex se_if_lock;
+ /*
+ * prevent a command to be sent on the se interface while another one is
+ * still processing. (response to a command is allowed)
+ */
+ struct mutex se_if_cmd_lock;
+ struct device *dev;
+ u8 *mem_pool_name;
+ u8 cmd_tag;
+ u8 rsp_tag;
+ u8 success_tag;
+ u8 base_api_ver;
+ u8 fw_api_ver;
+ u32 fw_fail;
+ const void *info;
+
+ struct mbox_client se_mb_cl;
+ struct mbox_chan *tx_chan, *rx_chan;
+ struct se_api_msg *rx_msg;
+ struct completion done;
+ spinlock_t lock;
+ /*
+ * Flag to retain the state of initialization done at
+ * the time of se-mu probe.
+ */
+ uint32_t flags;
+ u8 max_dev_ctx;
+ struct se_if_device_ctx **ctxs;
+ struct se_imem_buf imem;
+};
+
+void *get_phy_buf_mem_pool(struct device *dev,
+ u8 *mem_pool_name,
+ dma_addr_t *buf,
+ u32 size);
+phys_addr_t get_phy_buf_mem_pool1(struct device *dev,
+ u8 *mem_pool_name,
+ u32 **buf,
+ u32 size);
+void free_phybuf_mem_pool(struct device *dev,
+ u8 *mem_pool_name,
+ u32 *buf,
+ u32 size);
+#endif
diff --git a/include/linux/firmware/imx/se_api.h b/include/linux/firmware/imx/se_api.h
new file mode 100644
index 000000000000..c47f84906837
--- /dev/null
+++ b/include/linux/firmware/imx/se_api.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __SE_API_H__
+#define __SE_API_H__
+
+#include <linux/types.h>
+
+#define SOC_ID_OF_IMX8ULP 0x084D
+#define SOC_ID_OF_IMX93 0x9300
+
+#endif /* __SE_API_H__ */
diff --git a/include/uapi/linux/se_ioctl.h b/include/uapi/linux/se_ioctl.h
new file mode 100644
index 000000000000..f68a36e9da2c
--- /dev/null
+++ b/include/uapi/linux/se_ioctl.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause*/
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef SE_IOCTL_H
+#define SE_IOCTL_H
+
+/* IOCTL definitions. */
+
+struct se_ioctl_setup_iobuf {
+ u8 *user_buf;
+ u32 length;
+ u32 flags;
+ u64 ele_addr;
+};
+
+struct se_ioctl_shared_mem_cfg {
+ u32 base_offset;
+ u32 size;
+};
+
+struct se_ioctl_get_if_info {
+ u8 se_if_id;
+ u8 interrupt_idx;
+ u8 tz;
+ u8 did;
+ u8 cmd_tag;
+ u8 rsp_tag;
+ u8 success_tag;
+ u8 base_api_ver;
+ u8 fw_api_ver;
+};
+
+struct se_ioctl_signed_message {
+ u8 *message;
+ u32 msg_size;
+ u32 error_code;
+};
+
+struct se_ioctl_get_soc_info {
+ u16 soc_id;
+ u16 soc_rev;
+};
+
+/* IO Buffer Flags */
+#define SE_IO_BUF_FLAGS_IS_OUTPUT (0x00u)
+#define SE_IO_BUF_FLAGS_IS_INPUT (0x01u)
+#define SE_IO_BUF_FLAGS_USE_SEC_MEM (0x02u)
+#define SE_IO_BUF_FLAGS_USE_SHORT_ADDR (0x04u)
+#define SE_IO_BUF_FLAGS_IS_IN_OUT (0x10u)
+
+/* IOCTLS */
+#define SE_IOCTL 0x0A /* like MISC_MAJOR. */
+
+/*
+ * ioctl to designated the current fd as logical-reciever.
+ * This is ioctl is send when the nvm-daemon, a slave to the
+ * firmware is started by the user.
+ */
+#define SE_IOCTL_ENABLE_CMD_RCV _IO(SE_IOCTL, 0x01)
+
+/*
+ * ioctl to get the buffer allocated from the memory, which is shared
+ * between kernel and FW.
+ * Post allocation, the kernel tagged the allocated memory with:
+ * Output
+ * Input
+ * Input-Output
+ * Short address
+ * Secure-memory
+ */
+#define SE_IOCTL_SETUP_IOBUF _IOWR(SE_IOCTL, 0x03, \
+ struct se_ioctl_setup_iobuf)
+
+/*
+ * ioctl to get the mu information, that is used to exchange message
+ * with FW, from user-spaced.
+ */
+#define SE_IOCTL_GET_MU_INFO _IOR(SE_IOCTL, 0x04, \
+ struct se_ioctl_get_if_info)
+/*
+ * ioctl to get SoC Info from user-space.
+ */
+#define SE_IOCTL_GET_SOC_INFO _IOR(SE_IOCTL, 0x06, \
+ struct se_ioctl_get_soc_info)
+
+#endif
--
2.34.1
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^ permalink raw reply related [relevance 2%]
* [PATCH 3/3] soc: ti: pm33xx: do device_node auto cleanup
@ 2024-05-10 7:13 10% ` Kousik Sanagavarapu
0 siblings, 0 replies; 200+ results
From: Kousik Sanagavarapu @ 2024-05-10 7:13 UTC (permalink / raw)
To: Nishanth Menon, Santosh Shilimkar, Julia Lawall
Cc: Shuah Khan, Javier Carrasco, linux-kernel, linux-arm-kernel,
Kousik Sanagavarapu
Use scope based cleanup instead of manual of_node_put() calls, hence
simplifying the handling of error paths.
Suggested-by: Julia Lawall <julia.lawall@inria.fr>
Signed-off-by: Kousik Sanagavarapu <five231003@gmail.com>
---
drivers/soc/ti/pm33xx.c | 20 +++++++-------------
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/drivers/soc/ti/pm33xx.c b/drivers/soc/ti/pm33xx.c
index 8e983c3c4e03..40988c45ed00 100644
--- a/drivers/soc/ti/pm33xx.c
+++ b/drivers/soc/ti/pm33xx.c
@@ -383,10 +383,9 @@ static void am33xx_pm_free_sram(void)
*/
static int am33xx_pm_alloc_sram(void)
{
- struct device_node *np;
- int ret = 0;
+ struct device_node *np __free(device_node) =
+ of_find_compatible_node(NULL, NULL, "ti,omap3-mpu");
- np = of_find_compatible_node(NULL, NULL, "ti,omap3-mpu");
if (!np) {
np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
if (!np) {
@@ -400,24 +399,21 @@ static int am33xx_pm_alloc_sram(void)
if (!sram_pool) {
dev_err(pm33xx_dev, "PM: %s: Unable to get sram pool for ocmcram\n",
__func__);
- ret = -ENODEV;
- goto mpu_put_node;
+ return -ENODEV;
}
sram_pool_data = of_gen_pool_get(np, "pm-sram", 1);
if (!sram_pool_data) {
dev_err(pm33xx_dev, "PM: %s: Unable to get sram data pool for ocmcram\n",
__func__);
- ret = -ENODEV;
- goto mpu_put_node;
+ return -ENODEV;
}
ocmcram_location = gen_pool_alloc(sram_pool, *pm_sram->do_wfi_sz);
if (!ocmcram_location) {
dev_err(pm33xx_dev, "PM: %s: Unable to allocate memory from ocmcram\n",
__func__);
- ret = -ENOMEM;
- goto mpu_put_node;
+ return -ENOMEM;
}
ocmcram_location_data = gen_pool_alloc(sram_pool_data,
@@ -425,12 +421,10 @@ static int am33xx_pm_alloc_sram(void)
if (!ocmcram_location_data) {
dev_err(pm33xx_dev, "PM: Unable to allocate memory from ocmcram\n");
gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
- ret = -ENOMEM;
+ return -ENOMEM;
}
-mpu_put_node:
- of_node_put(np);
- return ret;
+ return 0;
}
static int am33xx_pm_rtc_setup(void)
--
2.45.0.rc1.8.ge326e52010
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^ permalink raw reply related [relevance 10%]
* Re: [PATCH rc] iommu/arm-smmu: Use the correct type in nvidia_smmu_context_fault()
2024-05-09 19:26 0% ` Jerry Snitselaar
@ 2024-05-09 19:30 0% ` Jerry Snitselaar
0 siblings, 0 replies; 200+ results
From: Jerry Snitselaar @ 2024-05-09 19:30 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: iommu, Joerg Roedel, linux-arm-kernel, linux-tegra, Robin Murphy,
Thierry Reding, Krishna Reddy, patches, Will Deacon
On Thu, May 09, 2024 at 12:26:36PM GMT, Jerry Snitselaar wrote:
> On Thu, May 09, 2024 at 11:51:55AM GMT, Jerry Snitselaar wrote:
> > On Thu, May 09, 2024 at 02:45:51PM GMT, Jason Gunthorpe wrote:
> > > This was missed because of the function pointer indirection.
> > >
> > > nvidia_smmu_context_fault() is also installed as a irq function, and the
> > > 'void *' was changed to a struct arm_smmu_domain. Since the iommu_domain
> > > is embedded at a non-zero offset this causes nvidia_smmu_context_fault()
> > > to miscompute the offset. Fixup the types.
> > >
> > > Unable to handle kernel NULL pointer dereference at virtual address 0000000000000120
> > > Mem abort info:
> > > ESR = 0x0000000096000004
> > > EC = 0x25: DABT (current EL), IL = 32 bits
> > > SET = 0, FnV = 0
> > > EA = 0, S1PTW = 0
> > > FSC = 0x04: level 0 translation fault
> > > Data abort info:
> > > ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
> > > CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> > > GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> > > user pgtable: 4k pages, 48-bit VAs, pgdp=0000000107c9f000
> > > [0000000000000120] pgd=0000000000000000, p4d=0000000000000000
> > > Internal error: Oops: 0000000096000004 [#1] SMP
> > > Modules linked in:
> > > CPU: 1 PID: 47 Comm: kworker/u25:0 Not tainted 6.9.0-0.rc7.58.eln136.aarch64 #1
> > > Hardware name: Unknown NVIDIA Jetson Orin NX/NVIDIA Jetson Orin NX, BIOS 3.1-32827747 03/19/2023
> > > Workqueue: events_unbound deferred_probe_work_func
> > > pstate: 604000c9 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> > > pc : nvidia_smmu_context_fault+0x1c/0x158
> > > lr : __free_irq+0x1d4/0x2e8
> > > sp : ffff80008044b6f0
> > > x29: ffff80008044b6f0 x28: ffff000080a60b18 x27: ffffd32b5172e970
> > > x26: 0000000000000000 x25: ffff0000802f5aac x24: ffff0000802f5a30
> > > x23: ffff0000802f5b60 x22: 0000000000000057 x21: 0000000000000000
> > > x20: ffff0000802f5a00 x19: ffff000087d4cd80 x18: ffffffffffffffff
> > > x17: 6234362066666666 x16: 6630303078302d30 x15: ffff00008156d888
> > > x14: 0000000000000000 x13: ffff0000801db910 x12: ffff00008156d6d0
> > > x11: 0000000000000003 x10: ffff0000801db918 x9 : ffffd32b50f94d9c
> > > x8 : 1fffe0001032fda1 x7 : ffff00008197ed00 x6 : 000000000000000f
> > > x5 : 000000000000010e x4 : 000000000000010e x3 : 0000000000000000
> > > x2 : ffffd32b51720cd8 x1 : ffff000087e6f700 x0 : 0000000000000057
> > > Call trace:
> > > nvidia_smmu_context_fault+0x1c/0x158
> > > __free_irq+0x1d4/0x2e8
> > > free_irq+0x3c/0x80
> > > devm_free_irq+0x64/0xa8
> > > arm_smmu_domain_free+0xc4/0x158
> > > iommu_domain_free+0x44/0xa0
> > > iommu_deinit_device+0xd0/0xf8
> > > __iommu_group_remove_device+0xcc/0xe0
> > > iommu_bus_notifier+0x64/0xa8
> > > notifier_call_chain+0x78/0x148
> > > blocking_notifier_call_chain+0x4c/0x90
> > > bus_notify+0x44/0x70
> > > device_del+0x264/0x3e8
> > > pci_remove_bus_device+0x84/0x120
> > > pci_remove_root_bus+0x5c/0xc0
> > > dw_pcie_host_deinit+0x38/0xe0
> > > tegra_pcie_config_rp+0xc0/0x1f0
> > > tegra_pcie_dw_probe+0x34c/0x700
> > > platform_probe+0x70/0xe8
> > > really_probe+0xc8/0x3a0
> > > __driver_probe_device+0x84/0x160
> > > driver_probe_device+0x44/0x130
> > > __device_attach_driver+0xc4/0x170
> > > bus_for_each_drv+0x90/0x100
> > > __device_attach+0xa8/0x1c8
> > > device_initial_probe+0x1c/0x30
> > > bus_probe_device+0xb0/0xc0
> > > deferred_probe_work_func+0xbc/0x120
> > > process_one_work+0x194/0x490
> > > worker_thread+0x284/0x3b0
> > > kthread+0xf4/0x108
> > > ret_from_fork+0x10/0x20
> > > Code: a9b97bfd 910003fd a9025bf5 f85a0035 (b94122a1)
> > >
> > > Cc: stable@vger.kernel.org
> > > Fixes: e0976331ad11 ("iommu/arm-smmu: Pass arm_smmu_domain to internal functions")
> > > Reported-by: Jerry Snitselaar <jsnitsel@redhat.com>
> > > Closes: https://lore.kernel.org/all/jto5e3ili4auk6sbzpnojdvhppgwuegir7mpd755anfhwcbkfz@2u5gh7bxb4iv
> > > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
> >
> > Tested-by: Jerry Snitselaar <jsnitsel@redhat.com>
> > Acked-by: Jerry Snitselaar <jsnitsel@redhat.com>
>
> Actually looking at it again, does arm_smmu_context_fault need to be
> updated as well? The devm_request_irq call is getting passed the
> smmu_domain whether context_fault is arm_smmu_context_fault or
> nvidia_smmu_context_fault.
>
Never mind. I can't read today.
> >
> > > ---
> > > drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 4 +---
> > > 1 file changed, 1 insertion(+), 3 deletions(-)
> > >
> > > Joerg, once Jerry ack's this you should grab it for this cycle.
> > >
> > > Thanks,
> > > Jason
> > >
> > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> > > index 87bf522b9d2eec..957d988b6d832f 100644
> > > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> > > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> > > @@ -221,11 +221,9 @@ static irqreturn_t nvidia_smmu_context_fault(int irq, void *dev)
> > > unsigned int inst;
> > > irqreturn_t ret = IRQ_NONE;
> > > struct arm_smmu_device *smmu;
> > > - struct iommu_domain *domain = dev;
> > > - struct arm_smmu_domain *smmu_domain;
> > > + struct arm_smmu_domain *smmu_domain = dev;
> > > struct nvidia_smmu *nvidia;
> > >
> > > - smmu_domain = container_of(domain, struct arm_smmu_domain, domain);
> > > smmu = smmu_domain->smmu;
> > > nvidia = to_nvidia_smmu(smmu);
> > >
> > >
> > > base-commit: dff9180946cc45d90a77e1c8645989cdcfd31437
> > > --
> > > 2.43.2
> > >
> >
>
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* Re: [PATCH rc] iommu/arm-smmu: Use the correct type in nvidia_smmu_context_fault()
2024-05-09 18:51 0% ` Jerry Snitselaar
@ 2024-05-09 19:26 0% ` Jerry Snitselaar
2024-05-09 19:30 0% ` Jerry Snitselaar
0 siblings, 1 reply; 200+ results
From: Jerry Snitselaar @ 2024-05-09 19:26 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: iommu, Joerg Roedel, linux-arm-kernel, linux-tegra, Robin Murphy,
Thierry Reding, Krishna Reddy, patches, Will Deacon
On Thu, May 09, 2024 at 11:51:55AM GMT, Jerry Snitselaar wrote:
> On Thu, May 09, 2024 at 02:45:51PM GMT, Jason Gunthorpe wrote:
> > This was missed because of the function pointer indirection.
> >
> > nvidia_smmu_context_fault() is also installed as a irq function, and the
> > 'void *' was changed to a struct arm_smmu_domain. Since the iommu_domain
> > is embedded at a non-zero offset this causes nvidia_smmu_context_fault()
> > to miscompute the offset. Fixup the types.
> >
> > Unable to handle kernel NULL pointer dereference at virtual address 0000000000000120
> > Mem abort info:
> > ESR = 0x0000000096000004
> > EC = 0x25: DABT (current EL), IL = 32 bits
> > SET = 0, FnV = 0
> > EA = 0, S1PTW = 0
> > FSC = 0x04: level 0 translation fault
> > Data abort info:
> > ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
> > CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> > GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> > user pgtable: 4k pages, 48-bit VAs, pgdp=0000000107c9f000
> > [0000000000000120] pgd=0000000000000000, p4d=0000000000000000
> > Internal error: Oops: 0000000096000004 [#1] SMP
> > Modules linked in:
> > CPU: 1 PID: 47 Comm: kworker/u25:0 Not tainted 6.9.0-0.rc7.58.eln136.aarch64 #1
> > Hardware name: Unknown NVIDIA Jetson Orin NX/NVIDIA Jetson Orin NX, BIOS 3.1-32827747 03/19/2023
> > Workqueue: events_unbound deferred_probe_work_func
> > pstate: 604000c9 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> > pc : nvidia_smmu_context_fault+0x1c/0x158
> > lr : __free_irq+0x1d4/0x2e8
> > sp : ffff80008044b6f0
> > x29: ffff80008044b6f0 x28: ffff000080a60b18 x27: ffffd32b5172e970
> > x26: 0000000000000000 x25: ffff0000802f5aac x24: ffff0000802f5a30
> > x23: ffff0000802f5b60 x22: 0000000000000057 x21: 0000000000000000
> > x20: ffff0000802f5a00 x19: ffff000087d4cd80 x18: ffffffffffffffff
> > x17: 6234362066666666 x16: 6630303078302d30 x15: ffff00008156d888
> > x14: 0000000000000000 x13: ffff0000801db910 x12: ffff00008156d6d0
> > x11: 0000000000000003 x10: ffff0000801db918 x9 : ffffd32b50f94d9c
> > x8 : 1fffe0001032fda1 x7 : ffff00008197ed00 x6 : 000000000000000f
> > x5 : 000000000000010e x4 : 000000000000010e x3 : 0000000000000000
> > x2 : ffffd32b51720cd8 x1 : ffff000087e6f700 x0 : 0000000000000057
> > Call trace:
> > nvidia_smmu_context_fault+0x1c/0x158
> > __free_irq+0x1d4/0x2e8
> > free_irq+0x3c/0x80
> > devm_free_irq+0x64/0xa8
> > arm_smmu_domain_free+0xc4/0x158
> > iommu_domain_free+0x44/0xa0
> > iommu_deinit_device+0xd0/0xf8
> > __iommu_group_remove_device+0xcc/0xe0
> > iommu_bus_notifier+0x64/0xa8
> > notifier_call_chain+0x78/0x148
> > blocking_notifier_call_chain+0x4c/0x90
> > bus_notify+0x44/0x70
> > device_del+0x264/0x3e8
> > pci_remove_bus_device+0x84/0x120
> > pci_remove_root_bus+0x5c/0xc0
> > dw_pcie_host_deinit+0x38/0xe0
> > tegra_pcie_config_rp+0xc0/0x1f0
> > tegra_pcie_dw_probe+0x34c/0x700
> > platform_probe+0x70/0xe8
> > really_probe+0xc8/0x3a0
> > __driver_probe_device+0x84/0x160
> > driver_probe_device+0x44/0x130
> > __device_attach_driver+0xc4/0x170
> > bus_for_each_drv+0x90/0x100
> > __device_attach+0xa8/0x1c8
> > device_initial_probe+0x1c/0x30
> > bus_probe_device+0xb0/0xc0
> > deferred_probe_work_func+0xbc/0x120
> > process_one_work+0x194/0x490
> > worker_thread+0x284/0x3b0
> > kthread+0xf4/0x108
> > ret_from_fork+0x10/0x20
> > Code: a9b97bfd 910003fd a9025bf5 f85a0035 (b94122a1)
> >
> > Cc: stable@vger.kernel.org
> > Fixes: e0976331ad11 ("iommu/arm-smmu: Pass arm_smmu_domain to internal functions")
> > Reported-by: Jerry Snitselaar <jsnitsel@redhat.com>
> > Closes: https://lore.kernel.org/all/jto5e3ili4auk6sbzpnojdvhppgwuegir7mpd755anfhwcbkfz@2u5gh7bxb4iv
> > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
>
> Tested-by: Jerry Snitselaar <jsnitsel@redhat.com>
> Acked-by: Jerry Snitselaar <jsnitsel@redhat.com>
Actually looking at it again, does arm_smmu_context_fault need to be
updated as well? The devm_request_irq call is getting passed the
smmu_domain whether context_fault is arm_smmu_context_fault or
nvidia_smmu_context_fault.
>
> > ---
> > drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 4 +---
> > 1 file changed, 1 insertion(+), 3 deletions(-)
> >
> > Joerg, once Jerry ack's this you should grab it for this cycle.
> >
> > Thanks,
> > Jason
> >
> > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> > index 87bf522b9d2eec..957d988b6d832f 100644
> > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> > @@ -221,11 +221,9 @@ static irqreturn_t nvidia_smmu_context_fault(int irq, void *dev)
> > unsigned int inst;
> > irqreturn_t ret = IRQ_NONE;
> > struct arm_smmu_device *smmu;
> > - struct iommu_domain *domain = dev;
> > - struct arm_smmu_domain *smmu_domain;
> > + struct arm_smmu_domain *smmu_domain = dev;
> > struct nvidia_smmu *nvidia;
> >
> > - smmu_domain = container_of(domain, struct arm_smmu_domain, domain);
> > smmu = smmu_domain->smmu;
> > nvidia = to_nvidia_smmu(smmu);
> >
> >
> > base-commit: dff9180946cc45d90a77e1c8645989cdcfd31437
> > --
> > 2.43.2
> >
>
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* Re: [PATCH rc] iommu/arm-smmu: Use the correct type in nvidia_smmu_context_fault()
2024-05-09 17:45 5% [PATCH rc] iommu/arm-smmu: Use the correct type in nvidia_smmu_context_fault() Jason Gunthorpe
@ 2024-05-09 18:51 0% ` Jerry Snitselaar
2024-05-09 19:26 0% ` Jerry Snitselaar
0 siblings, 1 reply; 200+ results
From: Jerry Snitselaar @ 2024-05-09 18:51 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: iommu, Joerg Roedel, linux-arm-kernel, linux-tegra, Robin Murphy,
Thierry Reding, Krishna Reddy, patches, Will Deacon
On Thu, May 09, 2024 at 02:45:51PM GMT, Jason Gunthorpe wrote:
> This was missed because of the function pointer indirection.
>
> nvidia_smmu_context_fault() is also installed as a irq function, and the
> 'void *' was changed to a struct arm_smmu_domain. Since the iommu_domain
> is embedded at a non-zero offset this causes nvidia_smmu_context_fault()
> to miscompute the offset. Fixup the types.
>
> Unable to handle kernel NULL pointer dereference at virtual address 0000000000000120
> Mem abort info:
> ESR = 0x0000000096000004
> EC = 0x25: DABT (current EL), IL = 32 bits
> SET = 0, FnV = 0
> EA = 0, S1PTW = 0
> FSC = 0x04: level 0 translation fault
> Data abort info:
> ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
> CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> user pgtable: 4k pages, 48-bit VAs, pgdp=0000000107c9f000
> [0000000000000120] pgd=0000000000000000, p4d=0000000000000000
> Internal error: Oops: 0000000096000004 [#1] SMP
> Modules linked in:
> CPU: 1 PID: 47 Comm: kworker/u25:0 Not tainted 6.9.0-0.rc7.58.eln136.aarch64 #1
> Hardware name: Unknown NVIDIA Jetson Orin NX/NVIDIA Jetson Orin NX, BIOS 3.1-32827747 03/19/2023
> Workqueue: events_unbound deferred_probe_work_func
> pstate: 604000c9 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> pc : nvidia_smmu_context_fault+0x1c/0x158
> lr : __free_irq+0x1d4/0x2e8
> sp : ffff80008044b6f0
> x29: ffff80008044b6f0 x28: ffff000080a60b18 x27: ffffd32b5172e970
> x26: 0000000000000000 x25: ffff0000802f5aac x24: ffff0000802f5a30
> x23: ffff0000802f5b60 x22: 0000000000000057 x21: 0000000000000000
> x20: ffff0000802f5a00 x19: ffff000087d4cd80 x18: ffffffffffffffff
> x17: 6234362066666666 x16: 6630303078302d30 x15: ffff00008156d888
> x14: 0000000000000000 x13: ffff0000801db910 x12: ffff00008156d6d0
> x11: 0000000000000003 x10: ffff0000801db918 x9 : ffffd32b50f94d9c
> x8 : 1fffe0001032fda1 x7 : ffff00008197ed00 x6 : 000000000000000f
> x5 : 000000000000010e x4 : 000000000000010e x3 : 0000000000000000
> x2 : ffffd32b51720cd8 x1 : ffff000087e6f700 x0 : 0000000000000057
> Call trace:
> nvidia_smmu_context_fault+0x1c/0x158
> __free_irq+0x1d4/0x2e8
> free_irq+0x3c/0x80
> devm_free_irq+0x64/0xa8
> arm_smmu_domain_free+0xc4/0x158
> iommu_domain_free+0x44/0xa0
> iommu_deinit_device+0xd0/0xf8
> __iommu_group_remove_device+0xcc/0xe0
> iommu_bus_notifier+0x64/0xa8
> notifier_call_chain+0x78/0x148
> blocking_notifier_call_chain+0x4c/0x90
> bus_notify+0x44/0x70
> device_del+0x264/0x3e8
> pci_remove_bus_device+0x84/0x120
> pci_remove_root_bus+0x5c/0xc0
> dw_pcie_host_deinit+0x38/0xe0
> tegra_pcie_config_rp+0xc0/0x1f0
> tegra_pcie_dw_probe+0x34c/0x700
> platform_probe+0x70/0xe8
> really_probe+0xc8/0x3a0
> __driver_probe_device+0x84/0x160
> driver_probe_device+0x44/0x130
> __device_attach_driver+0xc4/0x170
> bus_for_each_drv+0x90/0x100
> __device_attach+0xa8/0x1c8
> device_initial_probe+0x1c/0x30
> bus_probe_device+0xb0/0xc0
> deferred_probe_work_func+0xbc/0x120
> process_one_work+0x194/0x490
> worker_thread+0x284/0x3b0
> kthread+0xf4/0x108
> ret_from_fork+0x10/0x20
> Code: a9b97bfd 910003fd a9025bf5 f85a0035 (b94122a1)
>
> Cc: stable@vger.kernel.org
> Fixes: e0976331ad11 ("iommu/arm-smmu: Pass arm_smmu_domain to internal functions")
> Reported-by: Jerry Snitselaar <jsnitsel@redhat.com>
> Closes: https://lore.kernel.org/all/jto5e3ili4auk6sbzpnojdvhppgwuegir7mpd755anfhwcbkfz@2u5gh7bxb4iv
> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Tested-by: Jerry Snitselaar <jsnitsel@redhat.com>
Acked-by: Jerry Snitselaar <jsnitsel@redhat.com>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> Joerg, once Jerry ack's this you should grab it for this cycle.
>
> Thanks,
> Jason
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> index 87bf522b9d2eec..957d988b6d832f 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
> @@ -221,11 +221,9 @@ static irqreturn_t nvidia_smmu_context_fault(int irq, void *dev)
> unsigned int inst;
> irqreturn_t ret = IRQ_NONE;
> struct arm_smmu_device *smmu;
> - struct iommu_domain *domain = dev;
> - struct arm_smmu_domain *smmu_domain;
> + struct arm_smmu_domain *smmu_domain = dev;
> struct nvidia_smmu *nvidia;
>
> - smmu_domain = container_of(domain, struct arm_smmu_domain, domain);
> smmu = smmu_domain->smmu;
> nvidia = to_nvidia_smmu(smmu);
>
>
> base-commit: dff9180946cc45d90a77e1c8645989cdcfd31437
> --
> 2.43.2
>
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* [PATCH v5 1/2] mm: allow dynamic vmalloc range restrictions
@ 2024-05-09 18:25 5% Maxwell Bland
0 siblings, 0 replies; 200+ results
From: Maxwell Bland @ 2024-05-09 18:25 UTC (permalink / raw)
To: linux-mm
Cc: Catalin Marinas, Will Deacon, Alexei Starovoitov,
Daniel Borkmann, Andrii Nakryiko, Martin KaFai Lau,
Eduard Zingerman, Song Liu, Yonghong Song, John Fastabend,
KP Singh, Stanislav Fomichev, Hao Luo, Jiri Olsa, Zi Shen Lim,
Andrew Morton, Uladzislau Rezki, Christoph Hellwig,
Lorenzo Stoakes, Mark Rutland, Ard Biesheuvel, Maxwell Bland,
Russell King, Masami Hiramatsu, Shaoqin Huang, Ryo Takakura,
James Morse, Ryan Roberts, linux-arm-kernel, linux-kernel, bpf
Add an API to the vmalloc infrastructure, create_vmalloc_range_check,
which allows for the creation of restricted sub-ranges of vmalloc memory
during the init process, which can only be allocated from via vmalloc
requests with vaddr start addresses explicitly matching the range's
start addresses. Calls to this API can split up to two nodes in the
red-black tree.
create_vmalloc_range_check restricts vmalloc requests not matching the
range's start address to all other locations in the standard vmalloc
range, i.e. users of the interface are responsible for requesting only
correct and appropriate reservations. The primary intention of this API
is supporting ASLR module region allocation regions while not
undermining existing security mechanisms by necessitating interleaved
code and data pages.
To perform range allocation at the appropriate, earliest time, provide a
callback arch_init_checked_vmap_ranges rather than maintaining a linked
list outside of the vmalloc infrastructure, ensuring all vmap management
is still owned by vmalloc.c.
Considering some alternatives, i.e. a large change to the vmalloc
infrastructure to provide true support for a module code dynamic
allocation region, this smaller vstart-based opt-in seems preferable.
These changes may need to wait/be rebased on Mike Rapoport's patches
at 20240505160628.2323363-11-rppt@kernel.org , but this version is
submitted to account for the justification for unrestricted BPF/kprobe
code allocations and squashes some bugs the last version created in the
bpf selftests.
Changes from v4:
20240423095843.446565600-1-mbland@motorola.com
- Fix the corruption because of backslash created by SMTP mailer
- Add config to permit the reduction of BPF memory to 128MB, i.e. fix
issue with the arm64 side of this change implicitly breaking
1636131046-5982-2-git-send-email-alan.maguire@oracle.com "128MB of
JIT memory can be quickly exhausted"
- Expand modules_alloc region used on arm64 to support larger BPF
allocations present in the selftests.
Changes from v3:
20240416122254.868007168-1-mbland@motorola.com
- Added callbacks into arch-specific code to dynamically partition
red-black tree
(The freedom of architectures to determine vm area allocation was deemed
dangerous since there was no possibility of enforcing that areas were
correctly managed.)
Changes from v2:
20240220203256.31153-1-mbland@motorola.com
- No longer depends on reducing the size of the vmalloc region
- Attempted to implement change by allowing architectures to override
most abstract public vmalloc interface
(Overrides on vmalloc methods were deemed undesirable.)
Changes from v1:
CAP5Mv+ydhk=Ob4b40ZahGMgT-5+-VEHxtmA=-LkJiEOOU+K6hw@mail.gmail.com
- Statically reduced the range of the vmalloc region to support
parititoned code ranges
(The trade off between space reduction and security was deemed
unnecessary.)
Signed-off-by: Maxwell Bland <mbland@motorola.com>
---
Thanks again to the maintainers for their review, apologies for the
mailer and BPF selftest errors on the previous version. This version
will still be incompatible with BPF allocation limit stress tests, for
clear reasons. I plan to rebase this same exact code on top of Mike
Rapoport's recent patchset, but this version is compatible with the
current linus upstream.
include/linux/vmalloc.h | 14 ++++++
mm/vmalloc.c | 102 ++++++++++++++++++++++++++++++++++++++--
2 files changed, 113 insertions(+), 3 deletions(-)
diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h
index 98ea90e90439..ece8879ab060 100644
--- a/include/linux/vmalloc.h
+++ b/include/linux/vmalloc.h
@@ -81,6 +81,12 @@ struct vmap_area {
unsigned long flags; /* mark type of vm_map_ram area */
};
+struct checked_vmap_range {
+ unsigned long va_start;
+ unsigned long va_end;
+ struct list_head list;
+};
+
/* archs that select HAVE_ARCH_HUGE_VMAP should override one or more of these */
#ifndef arch_vmap_p4d_supported
static inline bool arch_vmap_p4d_supported(pgprot_t prot)
@@ -125,6 +131,12 @@ static inline pgprot_t arch_vmap_pgprot_tagged(pgprot_t prot)
}
#endif
+#ifndef arch_init_checked_vmap_ranges
+inline void __init arch_init_checked_vmap_ranges(void)
+{
+}
+#endif
+
/*
* Highlevel APIs for driver use
*/
@@ -211,6 +223,8 @@ extern struct vm_struct *__get_vm_area_caller(unsigned long size,
unsigned long flags,
unsigned long start, unsigned long end,
const void *caller);
+int __init create_vmalloc_range_check(unsigned long start_vaddr,
+ unsigned long end_vaddr);
void free_vm_area(struct vm_struct *area);
extern struct vm_struct *remove_vm_area(const void *addr);
extern struct vm_struct *find_vm_area(const void *addr);
diff --git a/mm/vmalloc.c b/mm/vmalloc.c
index 68fa001648cc..8f382b6c31de 100644
--- a/mm/vmalloc.c
+++ b/mm/vmalloc.c
@@ -817,6 +817,16 @@ static struct kmem_cache *vmap_area_cachep;
*/
static LIST_HEAD(free_vmap_area_list);
+static struct kmem_cache *vmap_checked_range_cachep;
+
+/*
+ * This linked list is used to record ranges of the vmalloc
+ * region which are checked at allocation time to ensure they
+ * are only allocated within when an explicit allocation
+ * request to that range is made.
+ */
+static LIST_HEAD(checked_range_list);
+
/*
* This augment red-black tree represents the free vmap space.
* All vmap_area objects in this tree are sorted by va->va_start
@@ -1454,6 +1464,23 @@ merge_or_add_vmap_area_augment(struct vmap_area *va,
return va;
}
+static __always_inline bool
+va_is_range_restricted(struct vmap_area *va, unsigned long vstart)
+{
+ struct checked_vmap_range *range, *tmp;
+
+ if (list_empty(&checked_range_list))
+ return false;
+
+ list_for_each_entry_safe(range, tmp, &checked_range_list, list)
+ if (va->va_start >= range->va_start &&
+ va->va_end <= range->va_end &&
+ vstart != range->va_start)
+ return true;
+
+ return false;
+}
+
static __always_inline bool
is_within_this_va(struct vmap_area *va, unsigned long size,
unsigned long align, unsigned long vstart)
@@ -1501,7 +1528,8 @@ find_vmap_lowest_match(struct rb_root *root, unsigned long size,
vstart < va->va_start) {
node = node->rb_left;
} else {
- if (is_within_this_va(va, size, align, vstart))
+ if (!va_is_range_restricted(va, vstart) &&
+ is_within_this_va(va, size, align, vstart))
return va;
/*
@@ -1522,7 +1550,8 @@ find_vmap_lowest_match(struct rb_root *root, unsigned long size,
*/
while ((node = rb_parent(node))) {
va = rb_entry(node, struct vmap_area, rb_node);
- if (is_within_this_va(va, size, align, vstart))
+ if (!va_is_range_restricted(va, vstart) &&
+ is_within_this_va(va, size, align, vstart))
return va;
if (get_subtree_max_size(node->rb_right) >= length &&
@@ -1554,7 +1583,8 @@ find_vmap_lowest_linear_match(struct list_head *head, unsigned long size,
struct vmap_area *va;
list_for_each_entry(va, head, list) {
- if (!is_within_this_va(va, size, align, vstart))
+ if (va_is_range_restricted(va, vstart) ||
+ !is_within_this_va(va, size, align, vstart))
continue;
return va;
@@ -1717,6 +1747,36 @@ va_clip(struct rb_root *root, struct list_head *head,
return 0;
}
+static inline int
+split_and_alloc_va(struct rb_root *root, struct list_head *head, unsigned long addr)
+{
+ struct vmap_area *va;
+ int ret;
+ struct vmap_area *lva = NULL;
+
+ va = __find_vmap_area(addr, root);
+ if (!va) {
+ pr_err("%s: could not find vmap\n", __func__);
+ return -1;
+ }
+
+ lva = kmem_cache_alloc(vmap_area_cachep, GFP_NOWAIT);
+ if (!lva) {
+ pr_err("%s: unable to allocate va for range\n", __func__);
+ return -1;
+ }
+ lva->va_start = addr;
+ lva->va_end = va->va_end;
+ ret = va_clip(root, head, va, addr, va->va_end - addr);
+ if (WARN_ON_ONCE(ret)) {
+ pr_err("%s: unable to clip code base region\n", __func__);
+ kmem_cache_free(vmap_area_cachep, lva);
+ return -1;
+ }
+ insert_vmap_area_augment(lva, NULL, root, head);
+ return 0;
+}
+
static unsigned long
va_alloc(struct vmap_area *va,
struct rb_root *root, struct list_head *head,
@@ -4424,6 +4484,35 @@ int remap_vmalloc_range(struct vm_area_struct *vma, void *addr,
}
EXPORT_SYMBOL(remap_vmalloc_range);
+/**
+ * create_vmalloc_range_check - create a checked range of vmalloc memory
+ * @start_vaddr: The starting vaddr of the code range
+ * @end_vaddr: The ending vaddr of the code range
+ *
+ * Returns: 0 for success, -1 on failure
+ *
+ * This function marks regions within or overlapping the vmalloc region for
+ * requested range checking during allocation. When requesting virtual memory,
+ * if the requested starting vaddr does not explicitly match the starting vaddr
+ * of this range, this range will not be allocated from.
+ */
+int __init create_vmalloc_range_check(unsigned long start_vaddr,
+ unsigned long end_vaddr)
+{
+ struct checked_vmap_range *range;
+
+ range = kmem_cache_alloc(vmap_checked_range_cachep, GFP_NOWAIT);
+ if (split_and_alloc_va(&free_vmap_area_root, &free_vmap_area_list, start_vaddr) ||
+ split_and_alloc_va(&free_vmap_area_root, &free_vmap_area_list, end_vaddr))
+ return -1;
+
+ range->va_start = start_vaddr;
+ range->va_end = end_vaddr;
+
+ list_add(&range->list, &checked_range_list);
+ return 0;
+}
+
void free_vm_area(struct vm_struct *area)
{
struct vm_struct *ret;
@@ -5082,6 +5171,11 @@ void __init vmalloc_init(void)
*/
vmap_area_cachep = KMEM_CACHE(vmap_area, SLAB_PANIC);
+ /*
+ * Create the cache for checked vmap ranges.
+ */
+ vmap_checked_range_cachep = KMEM_CACHE(checked_vmap_range, SLAB_PANIC);
+
for_each_possible_cpu(i) {
struct vmap_block_queue *vbq;
struct vfree_deferred *p;
@@ -5129,4 +5223,6 @@ void __init vmalloc_init(void)
vmap_node_shrinker->count_objects = vmap_node_shrink_count;
vmap_node_shrinker->scan_objects = vmap_node_shrink_scan;
shrinker_register(vmap_node_shrinker);
+
+ arch_init_checked_vmap_ranges();
}
base-commit: ee5b455b0adae9ecafb38b174c648c48f2a3c1a5
--
2.34.1
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^ permalink raw reply related [relevance 5%]
* [PATCH rc] iommu/arm-smmu: Use the correct type in nvidia_smmu_context_fault()
@ 2024-05-09 17:45 5% Jason Gunthorpe
2024-05-09 18:51 0% ` Jerry Snitselaar
0 siblings, 1 reply; 200+ results
From: Jason Gunthorpe @ 2024-05-09 17:45 UTC (permalink / raw)
To: iommu, Joerg Roedel, linux-arm-kernel, linux-tegra, Robin Murphy,
Thierry Reding, Krishna Reddy
Cc: Jerry Snitselaar, patches, Will Deacon
This was missed because of the function pointer indirection.
nvidia_smmu_context_fault() is also installed as a irq function, and the
'void *' was changed to a struct arm_smmu_domain. Since the iommu_domain
is embedded at a non-zero offset this causes nvidia_smmu_context_fault()
to miscompute the offset. Fixup the types.
Unable to handle kernel NULL pointer dereference at virtual address 0000000000000120
Mem abort info:
ESR = 0x0000000096000004
EC = 0x25: DABT (current EL), IL = 32 bits
SET = 0, FnV = 0
EA = 0, S1PTW = 0
FSC = 0x04: level 0 translation fault
Data abort info:
ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
CM = 0, WnR = 0, TnD = 0, TagAccess = 0
GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
user pgtable: 4k pages, 48-bit VAs, pgdp=0000000107c9f000
[0000000000000120] pgd=0000000000000000, p4d=0000000000000000
Internal error: Oops: 0000000096000004 [#1] SMP
Modules linked in:
CPU: 1 PID: 47 Comm: kworker/u25:0 Not tainted 6.9.0-0.rc7.58.eln136.aarch64 #1
Hardware name: Unknown NVIDIA Jetson Orin NX/NVIDIA Jetson Orin NX, BIOS 3.1-32827747 03/19/2023
Workqueue: events_unbound deferred_probe_work_func
pstate: 604000c9 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : nvidia_smmu_context_fault+0x1c/0x158
lr : __free_irq+0x1d4/0x2e8
sp : ffff80008044b6f0
x29: ffff80008044b6f0 x28: ffff000080a60b18 x27: ffffd32b5172e970
x26: 0000000000000000 x25: ffff0000802f5aac x24: ffff0000802f5a30
x23: ffff0000802f5b60 x22: 0000000000000057 x21: 0000000000000000
x20: ffff0000802f5a00 x19: ffff000087d4cd80 x18: ffffffffffffffff
x17: 6234362066666666 x16: 6630303078302d30 x15: ffff00008156d888
x14: 0000000000000000 x13: ffff0000801db910 x12: ffff00008156d6d0
x11: 0000000000000003 x10: ffff0000801db918 x9 : ffffd32b50f94d9c
x8 : 1fffe0001032fda1 x7 : ffff00008197ed00 x6 : 000000000000000f
x5 : 000000000000010e x4 : 000000000000010e x3 : 0000000000000000
x2 : ffffd32b51720cd8 x1 : ffff000087e6f700 x0 : 0000000000000057
Call trace:
nvidia_smmu_context_fault+0x1c/0x158
__free_irq+0x1d4/0x2e8
free_irq+0x3c/0x80
devm_free_irq+0x64/0xa8
arm_smmu_domain_free+0xc4/0x158
iommu_domain_free+0x44/0xa0
iommu_deinit_device+0xd0/0xf8
__iommu_group_remove_device+0xcc/0xe0
iommu_bus_notifier+0x64/0xa8
notifier_call_chain+0x78/0x148
blocking_notifier_call_chain+0x4c/0x90
bus_notify+0x44/0x70
device_del+0x264/0x3e8
pci_remove_bus_device+0x84/0x120
pci_remove_root_bus+0x5c/0xc0
dw_pcie_host_deinit+0x38/0xe0
tegra_pcie_config_rp+0xc0/0x1f0
tegra_pcie_dw_probe+0x34c/0x700
platform_probe+0x70/0xe8
really_probe+0xc8/0x3a0
__driver_probe_device+0x84/0x160
driver_probe_device+0x44/0x130
__device_attach_driver+0xc4/0x170
bus_for_each_drv+0x90/0x100
__device_attach+0xa8/0x1c8
device_initial_probe+0x1c/0x30
bus_probe_device+0xb0/0xc0
deferred_probe_work_func+0xbc/0x120
process_one_work+0x194/0x490
worker_thread+0x284/0x3b0
kthread+0xf4/0x108
ret_from_fork+0x10/0x20
Code: a9b97bfd 910003fd a9025bf5 f85a0035 (b94122a1)
Cc: stable@vger.kernel.org
Fixes: e0976331ad11 ("iommu/arm-smmu: Pass arm_smmu_domain to internal functions")
Reported-by: Jerry Snitselaar <jsnitsel@redhat.com>
Closes: https://lore.kernel.org/all/jto5e3ili4auk6sbzpnojdvhppgwuegir7mpd755anfhwcbkfz@2u5gh7bxb4iv
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
---
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
Joerg, once Jerry ack's this you should grab it for this cycle.
Thanks,
Jason
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
index 87bf522b9d2eec..957d988b6d832f 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
@@ -221,11 +221,9 @@ static irqreturn_t nvidia_smmu_context_fault(int irq, void *dev)
unsigned int inst;
irqreturn_t ret = IRQ_NONE;
struct arm_smmu_device *smmu;
- struct iommu_domain *domain = dev;
- struct arm_smmu_domain *smmu_domain;
+ struct arm_smmu_domain *smmu_domain = dev;
struct nvidia_smmu *nvidia;
- smmu_domain = container_of(domain, struct arm_smmu_domain, domain);
smmu = smmu_domain->smmu;
nvidia = to_nvidia_smmu(smmu);
base-commit: dff9180946cc45d90a77e1c8645989cdcfd31437
--
2.43.2
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* Re: [PATCH v4 3/3] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support
2024-05-09 5:56 6% ` [PATCH v4 3/3] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support Richard Zhu
@ 2024-05-09 14:44 0% ` Frank Li
0 siblings, 0 replies; 200+ results
From: Frank Li @ 2024-05-09 14:44 UTC (permalink / raw)
To: Richard Zhu
Cc: conor, vkoul, kishon, robh+dt, krzysztof.kozlowski+dt, conor+dt,
linux-phy, devicetree, linux-arm-kernel, linux-kernel, kernel,
imx
On Thu, May 09, 2024 at 01:56:21PM +0800, Richard Zhu wrote:
> Add i.MX8QM HSIO PHY driver support.
>
> i.MX8QM HSIO has three lane PHY instances, and can be bound to the
> following controllers in the different use cases listed in below table.
> - two lanes capable PCIEA controller.
> - one lane PCIEB controller.
> - AHCI SATA controller.
>
> i.MX8QM HSIO PHYs support the following use cases.
> +----------------------------------------------------+
> | | Lane0| Lane1| Lane2|
> |-------------------------------|------|------|------|
> | use case 1: PCIEAX2SATA | PCIEA| PCIEA| SATA |
> |-------------------------------|------|------|------|
> | use case 2: PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB|
> |-------------------------------|------|------|------|
> | use case 3: PCIEAPCIEBSATA | PCIEA| PCIEB| SATA |
> +----------------------------------------------------+
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
> drivers/phy/freescale/Kconfig | 8 +
> drivers/phy/freescale/Makefile | 1 +
> drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 598 ++++++++++++++++++++
> 3 files changed, 607 insertions(+)
> create mode 100644 drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
>
> diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
> index 853958fb2c06..c9ee48aeea9e 100644
> --- a/drivers/phy/freescale/Kconfig
> +++ b/drivers/phy/freescale/Kconfig
> @@ -35,6 +35,14 @@ config PHY_FSL_IMX8M_PCIE
> Enable this to add support for the PCIE PHY as found on
> i.MX8M family of SOCs.
>
> +config PHY_FSL_IMX8QM_HSIO
> + tristate "Freescale i.MX8QM HSIO PHY"
> + depends on OF && HAS_IOMEM
> + select GENERIC_PHY
> + help
> + Enable this to add support for the HSIO PHY as found on
> + i.MX8QM family of SOCs.
> +
> endif
>
> config PHY_FSL_LYNX_28G
> diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
> index cedb328bc4d2..b56b4d5c18ea 100644
> --- a/drivers/phy/freescale/Makefile
> +++ b/drivers/phy/freescale/Makefile
> @@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
> obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
> obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
> obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
> +obj-$(CONFIG_PHY_FSL_IMX8QM_HSIO) += phy-fsl-imx8qm-hsio.o
> obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
> diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> new file mode 100644
> index 000000000000..90b57a6893c9
> --- /dev/null
> +++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> @@ -0,0 +1,598 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/pci_regs.h>
> +#include <linux/phy/phy.h>
> +#include <linux/phy/pcie.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/phy/phy-imx8-pcie.h>
> +
> +#define MAX_NUM_LANE 3
> +#define LANE_NUM_CLKS 5
> +
> +/* Parameters for the waiting for PCIe PHY PLL to lock */
> +#define PHY_INIT_WAIT_USLEEP_MAX 10
> +#define PHY_INIT_WAIT_TIMEOUT (1000 * PHY_INIT_WAIT_USLEEP_MAX)
> +
> +/* i.MX8Q HSIO registers */
> +#define HSIO_CTRL0 0x0
> +#define HSIO_APB_RSTN_0 BIT(0)
> +#define HSIO_APB_RSTN_1 BIT(1)
> +#define HSIO_PIPE_RSTN_0_MASK GENMASK(25, 24)
> +#define HSIO_PIPE_RSTN_1_MASK GENMASK(27, 26)
> +#define HSIO_MODE_MASK GENMASK(20, 17)
> +#define HSIO_MODE_PCIE 0x0
> +#define HSIO_MODE_SATA 0x4
> +#define HSIO_DEVICE_TYPE_MASK GENMASK(27, 24)
> +#define HSIO_EPCS_TXDEEMP BIT(5)
> +#define HSIO_EPCS_TXDEEMP_SEL BIT(6)
> +#define HSIO_EPCS_PHYRESET_N BIT(7)
> +#define HSIO_RESET_N BIT(12)
> +
> +#define HSIO_IOB_RXENA BIT(0)
> +#define HSIO_IOB_TXENA BIT(1)
> +#define HSIO_IOB_A_0_TXOE BIT(2)
> +#define HSIO_IOB_A_0_M1M0_2 BIT(4)
> +#define HSIO_IOB_A_0_M1M0_MASK GENMASK(4, 3)
> +#define HSIO_PHYX1_EPCS_SEL BIT(12)
> +#define HSIO_PCIE_AB_SELECT BIT(13)
> +
> +#define HSIO_PHY_STS0 0x4
> +#define HSIO_LANE0_TX_PLL_LOCK BIT(4)
> +#define HSIO_LANE1_TX_PLL_LOCK BIT(12)
> +
> +#define HSIO_CTRL2 0x8
> +#define HSIO_LTSSM_ENABLE BIT(4)
> +#define HSIO_BUTTON_RST_N BIT(21)
> +#define HSIO_PERST_N BIT(22)
> +#define HSIO_POWER_UP_RST_N BIT(23)
> +
> +#define HSIO_PCIE_STS0 0xc
> +#define HSIO_PM_REQ_CORE_RST BIT(19)
> +
> +#define HSIO_REG48_PMA_STATUS 0x30
> +#define HSIO_REG48_PMA_RDY BIT(7)
> +
> +struct imx_hsio_drvdata {
> + int lane_num;
> +};
> +
> +struct imx_hsio_lane {
> + u32 ctrl_index;
> + u32 ctrl_off;
> + u32 idx;
> + u32 phy_off;
> + u32 phy_type;
> + const char * const *clk_names;
> + struct clk_bulk_data clks[LANE_NUM_CLKS];
> + struct imx_hsio_priv *priv;
> + struct phy *phy;
> + enum phy_mode phy_mode;
> +};
> +
> +struct imx_hsio_priv {
> + void __iomem *base;
> + struct device *dev;
> + atomic_t open_cnt;
> + const char *refclk_pad;
> + u32 hsio_cfg;
> + struct regmap *phy;
> + struct regmap *ctrl;
> + struct regmap *misc;
> + const struct imx_hsio_drvdata *drvdata;
> + struct imx_hsio_lane lane[MAX_NUM_LANE];
> +};
> +
> +static const char * const lan0_pcie_clks[] = {"apb_pclk0", "pclk0", "ctl0_crr",
> + "phy0_crr", "misc_crr"};
> +static const char * const lan1_pciea_clks[] = {"apb_pclk1", "pclk1", "ctl0_crr",
> + "phy0_crr", "misc_crr"};
> +static const char * const lan1_pcieb_clks[] = {"apb_pclk1", "pclk1", "ctl1_crr",
> + "phy0_crr", "misc_crr"};
> +static const char * const lan2_pcieb_clks[] = {"apb_pclk2", "pclk2", "ctl1_crr",
> + "phy1_crr", "misc_crr"};
> +static const char * const lan2_sata_clks[] = {"pclk2", "epcs_tx", "epcs_rx",
> + "phy1_crr", "misc_crr"};
> +
> +static const struct regmap_config regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +static int imx_hsio_init(struct phy *phy)
> +{
> + int ret, i;
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> + struct device *dev = priv->dev;
> +
> + /* Assign clocks refer to different modes */
> + switch (lane->phy_type) {
> + case PHY_TYPE_PCIE:
> + lane->phy_mode = PHY_MODE_PCIE;
> + if (lane->ctrl_index == 0) { /* PCIEA */
> + lane->ctrl_off = 0;
> + lane->phy_off = 0;
> +
> + for (i = 0; i < LANE_NUM_CLKS; i++) {
> + if (lane->idx == 0)
> + lane->clks[i].id = lan0_pcie_clks[i];
> + else
> + lane->clks[i].id = lan1_pciea_clks[i];
> + }
> + } else { /* PCIEB */
> + if (lane->idx == 0) { /* i.MX8QXP */
> + lane->ctrl_off = 0;
> + lane->phy_off = 0;
> + } else {
> + /*
> + * On i.MX8QM, only second or third lane can be
> + * bound to PCIEB.
> + */
> + lane->ctrl_off = SZ_64K;
> + if (lane->idx == 1)
> + lane->phy_off = 0;
> + else /* the third lane is bound to PCIEB */
> + lane->phy_off = SZ_64K;
> + }
> +
> + for (i = 0; i < LANE_NUM_CLKS; i++) {
> + if (lane->idx == 1)
> + lane->clks[i].id = lan1_pcieb_clks[i];
> + else if (lane->idx == 2)
> + lane->clks[i].id = lan2_pcieb_clks[i];
> + else /* i.MX8QXP only has PCIEB, idx is 0 */
> + lane->clks[i].id = lan0_pcie_clks[i];
> + }
> + }
> + break;
> + case PHY_TYPE_SATA:
> + /* On i.MX8QM, only the third lane can be bound to SATA */
> + lane->phy_mode = PHY_MODE_SATA;
> + lane->ctrl_off = SZ_128K;
> + lane->phy_off = SZ_64K;
> +
> + for (i = 0; i < LANE_NUM_CLKS; i++)
> + lane->clks[i].id = lan2_sata_clks[i];
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + /* Fetch clocks and enable them */
> + ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, lane->clks);
> + if (ret)
> + return ret;
> + ret = clk_bulk_prepare_enable(LANE_NUM_CLKS, lane->clks);
> + if (ret)
> + return ret;
> +
> + /* allow the clocks to stabilize */
> + usleep_range(200, 500);
> + return 0;
> +}
> +
> +static int imx_hsio_exit(struct phy *phy)
> +{
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> +
> + clk_bulk_disable_unprepare(LANE_NUM_CLKS, lane->clks);
> +
> + return 0;
> +}
> +
> +static void imx_hsio_pcie_phy_resets(struct phy *phy)
> +{
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_BUTTON_RST_N);
> + regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_PERST_N);
> + regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_POWER_UP_RST_N);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_BUTTON_RST_N);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_PERST_N);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_POWER_UP_RST_N);
> +
> + if (lane->idx == 1) {
> + regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_1);
> + regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_PIPE_RSTN_1_MASK);
> + } else {
> + regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_0);
> + regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_PIPE_RSTN_0_MASK);
> + }
> +}
> +
> +static void imx_hsio_sata_phy_resets(struct phy *phy)
> +{
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + /* clear PHY RST, then set it */
> + regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_PHYRESET_N);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_PHYRESET_N);
> +
> + /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
> + udelay(1);
> + regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
> + HSIO_RESET_N);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
> +}
> +
> +static void imx_hsio_configure_clk_pad(struct phy *phy)
> +{
> + bool pll = false;
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + if (strncmp(priv->refclk_pad, "output", 6) == 0) {
> + pll = true;
> + regmap_update_bits(priv->misc, HSIO_CTRL0,
> + HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
> + HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_2);
> + } else {
> + regmap_update_bits(priv->misc, HSIO_CTRL0,
> + HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
> + 0);
> + }
> +
> + regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_RXENA,
> + pll ? 0 : HSIO_IOB_RXENA);
> + regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_TXENA,
> + pll ? HSIO_IOB_TXENA : 0);
> +}
> +
> +static void imx_hsio_pre_set(struct phy *phy)
> +{
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + atomic_set(&priv->open_cnt, 1);
> + if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2PCIEB)
> + regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
> + if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2SATA)
> + regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
> +
> + imx_hsio_configure_clk_pad(phy);
> +}
> +
> +static int imx_hsio_pcie_power_on(struct phy *phy)
> +{
> + int ret;
> + u32 val, addr, cond;
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + imx_hsio_pcie_phy_resets(phy);
> +
> + /* Toggle apb_pclk to make sure PM_REQ_CORE_RST is cleared. */
> + clk_disable_unprepare(lane->clks[0].clk);
> + mdelay(1);
> + ret = clk_prepare_enable(lane->clks[0].clk);
> + if (ret) {
> + dev_err(priv->dev, "unable to enable phy apb_pclk\n");
> + return ret;
> + }
> +
> + addr = lane->ctrl_off + HSIO_PCIE_STS0;
> + cond = HSIO_PM_REQ_CORE_RST;
> + ret = regmap_read_poll_timeout(priv->ctrl, addr, val,
> + (val & cond) == 0,
> + PHY_INIT_WAIT_USLEEP_MAX,
> + PHY_INIT_WAIT_TIMEOUT);
> + if (ret)
> + dev_err(priv->dev, "HSIO_PM_REQ_CORE_RST is set\n");
> + return ret;
> +}
> +
> +static int imx_hsio_sata_power_on(struct phy *phy)
> +{
> + int ret;
> + u32 val, cond;
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0, HSIO_APB_RSTN_0);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_TXDEEMP);
> + regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_TXDEEMP_SEL);
> +
> + imx_hsio_sata_phy_resets(phy);
> +
> + cond = HSIO_REG48_PMA_RDY;
> + ret = read_poll_timeout(readb, val, ((val & cond) == cond),
> + PHY_INIT_WAIT_USLEEP_MAX,
> + PHY_INIT_WAIT_TIMEOUT, false,
> + priv->base + HSIO_REG48_PMA_STATUS);
> + if (ret)
> + dev_err(priv->dev, "PHY calibration is timeout\n");
> + else
> + dev_dbg(priv->dev, "PHY calibration is done\n");
> +
> + return ret;
> +}
> +
> +static int imx_hsio_power_on(struct phy *phy)
> +{
> + int ret;
> + u32 val, cond;
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + if (atomic_inc_and_test(&priv->open_cnt))
> + imx_hsio_pre_set(phy);
when multi client try power_on at the same time, it need wait first
imx_hsio_pre_set(phy) finish. So atomic is not enough here.
scope_guard(mutex, &priv->lock) {
if (!priv->open_cnt)
imx_hsio_pre_set(phy);
priv->open_cnt ++
}
in power_off function
scope_gard(mutex, &priv->lock) {
priv->open_cnt --;
}
> +
> + if (lane->phy_mode == PHY_MODE_PCIE)
> + ret = imx_hsio_pcie_power_on(phy);
> + else /* SATA */
> + ret = imx_hsio_sata_power_on(phy);
> + if (ret)
> + return ret;
> +
> + /* Polling to check the PHY is ready or not. */
> + if (lane->idx == 1)
> + cond = HSIO_LANE1_TX_PLL_LOCK;
> + else
> + /*
> + * Except the phy_off, the bit-offset of lane2 is same to lane0.
> + * Merge the lane0 and lane2 bit-operations together.
> + */
> + cond = HSIO_LANE0_TX_PLL_LOCK;
> +
> + ret = regmap_read_poll_timeout(priv->phy, lane->phy_off + HSIO_PHY_STS0,
> + val, ((val & cond) == cond),
> + PHY_INIT_WAIT_USLEEP_MAX,
> + PHY_INIT_WAIT_TIMEOUT);
> + if (ret) {
> + dev_err(priv->dev, "IMX8Q PHY%d PLL lock timeout\n", lane->idx);
> + return ret;
> + }
> + dev_dbg(priv->dev, "IMX8Q PHY%d PLL is locked\n", lane->idx);
> +
> + return ret;
> +}
> +
> +static int imx_hsio_power_off(struct phy *phy)
> +{
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + if (atomic_dec_and_test(&priv->open_cnt)) {
> + atomic_set(&priv->open_cnt, -1);
> + regmap_clear_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
> + regmap_clear_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
> +
> + if (lane->phy_mode == PHY_MODE_PCIE) {
> + regmap_clear_bits(priv->ctrl,
> + lane->ctrl_off + HSIO_CTRL2,
> + HSIO_BUTTON_RST_N);
> + regmap_clear_bits(priv->ctrl,
> + lane->ctrl_off + HSIO_CTRL2,
> + HSIO_PERST_N);
> + regmap_clear_bits(priv->ctrl,
> + lane->ctrl_off + HSIO_CTRL2,
> + HSIO_POWER_UP_RST_N);
> + } else {
> + regmap_clear_bits(priv->ctrl,
> + lane->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_TXDEEMP);
> + regmap_clear_bits(priv->ctrl,
> + lane->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_TXDEEMP_SEL);
> + regmap_clear_bits(priv->ctrl,
> + lane->ctrl_off + HSIO_CTRL0,
> + HSIO_RESET_N);
> + }
> +
> + if (lane->idx == 1) {
> + regmap_clear_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_1);
> + regmap_clear_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_PIPE_RSTN_1_MASK);
> + } else {
> + /*
> + * Except the phy_off, the bit-offset of lane2 is same
> + * to lane0. Merge the lane0 and lane2 bit-operations
> + * together.
> + */
> + regmap_clear_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_0);
> + regmap_clear_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_PIPE_RSTN_0_MASK);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int imx_hsio_set_mode(struct phy *phy, enum phy_mode mode,
> + int submode)
> +{
> + u32 val;
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + if (lane->phy_mode != mode)
> + return -EINVAL;
> +
> + val = (mode == PHY_MODE_PCIE) ? HSIO_MODE_PCIE : HSIO_MODE_SATA;
> + val = FIELD_PREP(HSIO_MODE_MASK, val);
> + regmap_update_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
> + HSIO_MODE_MASK, val);
> +
> + switch (submode) {
> + case PHY_MODE_PCIE_RC:
> + val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
> + break;
> + case PHY_MODE_PCIE_EP:
> + val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ENDPOINT);
> + break;
> + default: /* Support only PCIe EP and RC now. */
> + return 0;
> + }
> + if (submode)
> + regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
> + HSIO_DEVICE_TYPE_MASK, val);
> +
> + return 0;
> +}
> +
> +static int imx_hsio_set_speed(struct phy *phy, int speed)
> +{
> + struct imx_hsio_lane *lane = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = lane->priv;
> +
> + regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
> + HSIO_LTSSM_ENABLE,
> + speed ? HSIO_LTSSM_ENABLE : 0);
> + return 0;
> +}
> +
> +static const struct phy_ops imx_hsio_ops = {
> + .init = imx_hsio_init,
> + .exit = imx_hsio_exit,
> + .power_on = imx_hsio_power_on,
> + .power_off = imx_hsio_power_off,
> + .set_mode = imx_hsio_set_mode,
> + .set_speed = imx_hsio_set_speed,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct imx_hsio_drvdata imx8qxp_hsio_drvdata = {
> + .lane_num = 0x1,
> +};
> +
> +static const struct imx_hsio_drvdata imx_hsio_drvdata = {
> + .lane_num = 0x3,
> +};
> +
> +static const struct of_device_id imx_hsio_of_match[] = {
> + {.compatible = "fsl,imx8qm-hsio", .data = &imx_hsio_drvdata},
> + {.compatible = "fsl,imx8qxp-hsio", .data = &imx8qxp_hsio_drvdata},
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, imx_hsio_of_match);
> +
> +static struct phy *imx_hsio_xlate(struct device *dev,
> + const struct of_phandle_args *args)
> +{
> + struct imx_hsio_priv *priv = dev_get_drvdata(dev);
> + int idx = args->args[0];
> + int phy_type = args->args[1];
> + int ctrl_index = args->args[2];
> +
> + if (idx < 0 || idx >= priv->drvdata->lane_num)
> + return ERR_PTR(-EINVAL);
> + priv->lane[idx].idx = idx;
> + priv->lane[idx].phy_type = phy_type;
> + priv->lane[idx].ctrl_index = ctrl_index;
> +
> + return priv->lane[idx].phy;
> +}
> +
> +static int imx_hsio_probe(struct platform_device *pdev)
> +{
> + int i;
> + void __iomem *off;
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct imx_hsio_priv *priv;
> + struct phy_provider *provider;
> +
> + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> + priv->dev = &pdev->dev;
> + priv->drvdata = of_device_get_match_data(dev);
> + atomic_set(&priv->open_cnt, -1);
> +
> + /* Get HSIO configuration mode */
> + if (of_property_read_u32(np, "fsl,hsio-cfg", &priv->hsio_cfg))
> + priv->hsio_cfg = 0;
> + /* Get PHY refclk pad mode */
> + if (of_property_read_string(np, "fsl,refclk-pad-mode",
> + &priv->refclk_pad))
> + priv->refclk_pad = NULL;
> +
> + priv->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(priv->base))
> + return PTR_ERR(priv->base);
> +
> + off = devm_platform_ioremap_resource_byname(pdev, "phy");
> + priv->phy = devm_regmap_init_mmio(dev, off, ®map_config);
> + if (IS_ERR(priv->phy))
> + return dev_err_probe(dev, PTR_ERR(priv->phy),
> + "unable to find phy csr registers\n");
> +
> + off = devm_platform_ioremap_resource_byname(pdev, "ctrl");
> + priv->ctrl = devm_regmap_init_mmio(dev, off, ®map_config);
> + if (IS_ERR(priv->ctrl))
> + return dev_err_probe(dev, PTR_ERR(priv->ctrl),
> + "unable to find ctrl csr registers\n");
> +
> + off = devm_platform_ioremap_resource_byname(pdev, "misc");
> + priv->misc = devm_regmap_init_mmio(dev, off, ®map_config);
> + if (IS_ERR(priv->misc))
> + return dev_err_probe(dev, PTR_ERR(priv->misc),
> + "unable to find misc csr registers\n");
> +
> + for (i = 0; i < priv->drvdata->lane_num; i++) {
> + struct imx_hsio_lane *lane = &priv->lane[i];
> + struct phy *phy;
> +
> + memset(lane, 0, sizeof(*lane));
> +
> + phy = devm_phy_create(&pdev->dev, NULL, &imx_hsio_ops);
> + if (IS_ERR(phy))
> + return PTR_ERR(phy);
> +
> + lane->priv = priv;
> + lane->phy = phy;
> + lane->idx = i;
> + phy_set_drvdata(phy, lane);
> + }
> +
> + dev_set_drvdata(dev, priv);
> + dev_set_drvdata(&pdev->dev, priv);
> +
> + provider = devm_of_phy_provider_register(&pdev->dev, imx_hsio_xlate);
> +
> + return PTR_ERR_OR_ZERO(provider);
> +}
> +
> +static struct platform_driver imx_hsio_driver = {
> + .probe = imx_hsio_probe,
> + .driver = {
> + .name = "imx8qm-hsio-phy",
> + .of_match_table = imx_hsio_of_match,
> + }
> +};
> +module_platform_driver(imx_hsio_driver);
> +
> +MODULE_DESCRIPTION("FSL IMX8QM HSIO SERDES PHY driver");
> +MODULE_LICENSE("GPL");
> --
> 2.37.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* [PATCH v2 4/7] drm/rockchip: dsi: Support optional AHB clock
@ 2024-05-09 12:07 12% ` Alex Bee
0 siblings, 0 replies; 200+ results
From: Alex Bee @ 2024-05-09 12:07 UTC (permalink / raw)
To: Sandy Huang, Heiko Stübner, Andy Yan, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Daniel Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Michael Turquette, Stephen Boyd
Cc: dri-devel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, linux-clk, Alex Bee
Some integrations of the IP additionally have an AHB clock which has to be
enabled before accessing the registers is possible.
Add support for it as an optional clock.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
changes since v1:
- new patch
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 4cc8ed8f4fbd..6ed64cc35275 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -265,6 +265,7 @@ struct dw_mipi_dsi_rockchip {
struct clk *pllref_clk;
struct clk *grf_clk;
struct clk *phy_cfg_clk;
+ struct clk *ahb_clk;
/* dual-channel */
bool is_slave;
@@ -1153,7 +1154,15 @@ static int dw_mipi_dsi_dphy_init(struct phy *phy)
goto err_init;
}
+ ret = clk_prepare_enable(dsi->ahb_clk);
+ if (ret) {
+ clk_disable_unprepare(dsi->grf_clk);
+ clk_disable_unprepare(dsi->pclk);
+ goto err_init;
+ }
+
ret = dsi->cdata->dphy_rx_init(phy);
+ clk_disable_unprepare(dsi->ahb_clk);
clk_disable_unprepare(dsi->grf_clk);
clk_disable_unprepare(dsi->pclk);
if (ret < 0)
@@ -1240,6 +1249,12 @@ static int dw_mipi_dsi_dphy_power_on(struct phy *phy)
goto err_phy_cfg_clk;
}
+ ret = clk_prepare_enable(dsi->ahb_clk);
+ if (ret) {
+ DRM_DEV_ERROR(dsi->dev, "Failed to enable ahb_clk: %d\n", ret);
+ goto err_ahb_clk;
+ }
+
/* do soc-variant specific init */
if (dsi->cdata->dphy_rx_power_on) {
ret = dsi->cdata->dphy_rx_power_on(phy);
@@ -1269,6 +1284,8 @@ static int dw_mipi_dsi_dphy_power_on(struct phy *phy)
return ret;
err_pwr_on:
+ clk_disable_unprepare(dsi->ahb_clk);
+err_ahb_clk:
clk_disable_unprepare(dsi->phy_cfg_clk);
err_phy_cfg_clk:
clk_disable_unprepare(dsi->grf_clk);
@@ -1296,6 +1313,7 @@ static int dw_mipi_dsi_dphy_power_off(struct phy *phy)
DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret);
}
+ clk_disable_unprepare(dsi->ahb_clk);
clk_disable_unprepare(dsi->grf_clk);
clk_disable_unprepare(dsi->pclk);
@@ -1429,6 +1447,13 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
}
}
+ dsi->ahb_clk = devm_clk_get_optional(dev, "ahb");
+ if (IS_ERR(dsi->ahb_clk)) {
+ ret = PTR_ERR(dsi->ahb_clk);
+ DRM_DEV_ERROR(dev, "Unable to get ahb_clk: %d\n", ret);
+ return ret;
+ }
+
dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
if (IS_ERR(dsi->grf_regmap)) {
DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n");
--
2.43.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 12%]
* [PATCH v4 3/3] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support
@ 2024-05-09 5:56 6% ` Richard Zhu
2024-05-09 14:44 0% ` Frank Li
0 siblings, 1 reply; 200+ results
From: Richard Zhu @ 2024-05-09 5:56 UTC (permalink / raw)
To: conor, vkoul, kishon, robh+dt, krzysztof.kozlowski+dt, frank.li,
conor+dt
Cc: hongxing.zhu, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, kernel, imx
Add i.MX8QM HSIO PHY driver support.
i.MX8QM HSIO has three lane PHY instances, and can be bound to the
following controllers in the different use cases listed in below table.
- two lanes capable PCIEA controller.
- one lane PCIEB controller.
- AHCI SATA controller.
i.MX8QM HSIO PHYs support the following use cases.
+----------------------------------------------------+
| | Lane0| Lane1| Lane2|
|-------------------------------|------|------|------|
| use case 1: PCIEAX2SATA | PCIEA| PCIEA| SATA |
|-------------------------------|------|------|------|
| use case 2: PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB|
|-------------------------------|------|------|------|
| use case 3: PCIEAPCIEBSATA | PCIEA| PCIEB| SATA |
+----------------------------------------------------+
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/phy/freescale/Kconfig | 8 +
drivers/phy/freescale/Makefile | 1 +
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 598 ++++++++++++++++++++
3 files changed, 607 insertions(+)
create mode 100644 drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index 853958fb2c06..c9ee48aeea9e 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -35,6 +35,14 @@ config PHY_FSL_IMX8M_PCIE
Enable this to add support for the PCIE PHY as found on
i.MX8M family of SOCs.
+config PHY_FSL_IMX8QM_HSIO
+ tristate "Freescale i.MX8QM HSIO PHY"
+ depends on OF && HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Enable this to add support for the HSIO PHY as found on
+ i.MX8QM family of SOCs.
+
endif
config PHY_FSL_LYNX_28G
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index cedb328bc4d2..b56b4d5c18ea 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
+obj-$(CONFIG_PHY_FSL_IMX8QM_HSIO) += phy-fsl-imx8qm-hsio.o
obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
new file mode 100644
index 000000000000..90b57a6893c9
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
@@ -0,0 +1,598 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pci_regs.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/pcie.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#define MAX_NUM_LANE 3
+#define LANE_NUM_CLKS 5
+
+/* Parameters for the waiting for PCIe PHY PLL to lock */
+#define PHY_INIT_WAIT_USLEEP_MAX 10
+#define PHY_INIT_WAIT_TIMEOUT (1000 * PHY_INIT_WAIT_USLEEP_MAX)
+
+/* i.MX8Q HSIO registers */
+#define HSIO_CTRL0 0x0
+#define HSIO_APB_RSTN_0 BIT(0)
+#define HSIO_APB_RSTN_1 BIT(1)
+#define HSIO_PIPE_RSTN_0_MASK GENMASK(25, 24)
+#define HSIO_PIPE_RSTN_1_MASK GENMASK(27, 26)
+#define HSIO_MODE_MASK GENMASK(20, 17)
+#define HSIO_MODE_PCIE 0x0
+#define HSIO_MODE_SATA 0x4
+#define HSIO_DEVICE_TYPE_MASK GENMASK(27, 24)
+#define HSIO_EPCS_TXDEEMP BIT(5)
+#define HSIO_EPCS_TXDEEMP_SEL BIT(6)
+#define HSIO_EPCS_PHYRESET_N BIT(7)
+#define HSIO_RESET_N BIT(12)
+
+#define HSIO_IOB_RXENA BIT(0)
+#define HSIO_IOB_TXENA BIT(1)
+#define HSIO_IOB_A_0_TXOE BIT(2)
+#define HSIO_IOB_A_0_M1M0_2 BIT(4)
+#define HSIO_IOB_A_0_M1M0_MASK GENMASK(4, 3)
+#define HSIO_PHYX1_EPCS_SEL BIT(12)
+#define HSIO_PCIE_AB_SELECT BIT(13)
+
+#define HSIO_PHY_STS0 0x4
+#define HSIO_LANE0_TX_PLL_LOCK BIT(4)
+#define HSIO_LANE1_TX_PLL_LOCK BIT(12)
+
+#define HSIO_CTRL2 0x8
+#define HSIO_LTSSM_ENABLE BIT(4)
+#define HSIO_BUTTON_RST_N BIT(21)
+#define HSIO_PERST_N BIT(22)
+#define HSIO_POWER_UP_RST_N BIT(23)
+
+#define HSIO_PCIE_STS0 0xc
+#define HSIO_PM_REQ_CORE_RST BIT(19)
+
+#define HSIO_REG48_PMA_STATUS 0x30
+#define HSIO_REG48_PMA_RDY BIT(7)
+
+struct imx_hsio_drvdata {
+ int lane_num;
+};
+
+struct imx_hsio_lane {
+ u32 ctrl_index;
+ u32 ctrl_off;
+ u32 idx;
+ u32 phy_off;
+ u32 phy_type;
+ const char * const *clk_names;
+ struct clk_bulk_data clks[LANE_NUM_CLKS];
+ struct imx_hsio_priv *priv;
+ struct phy *phy;
+ enum phy_mode phy_mode;
+};
+
+struct imx_hsio_priv {
+ void __iomem *base;
+ struct device *dev;
+ atomic_t open_cnt;
+ const char *refclk_pad;
+ u32 hsio_cfg;
+ struct regmap *phy;
+ struct regmap *ctrl;
+ struct regmap *misc;
+ const struct imx_hsio_drvdata *drvdata;
+ struct imx_hsio_lane lane[MAX_NUM_LANE];
+};
+
+static const char * const lan0_pcie_clks[] = {"apb_pclk0", "pclk0", "ctl0_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan1_pciea_clks[] = {"apb_pclk1", "pclk1", "ctl0_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan1_pcieb_clks[] = {"apb_pclk1", "pclk1", "ctl1_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan2_pcieb_clks[] = {"apb_pclk2", "pclk2", "ctl1_crr",
+ "phy1_crr", "misc_crr"};
+static const char * const lan2_sata_clks[] = {"pclk2", "epcs_tx", "epcs_rx",
+ "phy1_crr", "misc_crr"};
+
+static const struct regmap_config regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int imx_hsio_init(struct phy *phy)
+{
+ int ret, i;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+ struct device *dev = priv->dev;
+
+ /* Assign clocks refer to different modes */
+ switch (lane->phy_type) {
+ case PHY_TYPE_PCIE:
+ lane->phy_mode = PHY_MODE_PCIE;
+ if (lane->ctrl_index == 0) { /* PCIEA */
+ lane->ctrl_off = 0;
+ lane->phy_off = 0;
+
+ for (i = 0; i < LANE_NUM_CLKS; i++) {
+ if (lane->idx == 0)
+ lane->clks[i].id = lan0_pcie_clks[i];
+ else
+ lane->clks[i].id = lan1_pciea_clks[i];
+ }
+ } else { /* PCIEB */
+ if (lane->idx == 0) { /* i.MX8QXP */
+ lane->ctrl_off = 0;
+ lane->phy_off = 0;
+ } else {
+ /*
+ * On i.MX8QM, only second or third lane can be
+ * bound to PCIEB.
+ */
+ lane->ctrl_off = SZ_64K;
+ if (lane->idx == 1)
+ lane->phy_off = 0;
+ else /* the third lane is bound to PCIEB */
+ lane->phy_off = SZ_64K;
+ }
+
+ for (i = 0; i < LANE_NUM_CLKS; i++) {
+ if (lane->idx == 1)
+ lane->clks[i].id = lan1_pcieb_clks[i];
+ else if (lane->idx == 2)
+ lane->clks[i].id = lan2_pcieb_clks[i];
+ else /* i.MX8QXP only has PCIEB, idx is 0 */
+ lane->clks[i].id = lan0_pcie_clks[i];
+ }
+ }
+ break;
+ case PHY_TYPE_SATA:
+ /* On i.MX8QM, only the third lane can be bound to SATA */
+ lane->phy_mode = PHY_MODE_SATA;
+ lane->ctrl_off = SZ_128K;
+ lane->phy_off = SZ_64K;
+
+ for (i = 0; i < LANE_NUM_CLKS; i++)
+ lane->clks[i].id = lan2_sata_clks[i];
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Fetch clocks and enable them */
+ ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, lane->clks);
+ if (ret)
+ return ret;
+ ret = clk_bulk_prepare_enable(LANE_NUM_CLKS, lane->clks);
+ if (ret)
+ return ret;
+
+ /* allow the clocks to stabilize */
+ usleep_range(200, 500);
+ return 0;
+}
+
+static int imx_hsio_exit(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+
+ clk_bulk_disable_unprepare(LANE_NUM_CLKS, lane->clks);
+
+ return 0;
+}
+
+static void imx_hsio_pcie_phy_resets(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+
+ if (lane->idx == 1) {
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_1);
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_1_MASK);
+ } else {
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_0);
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_0_MASK);
+ }
+}
+
+static void imx_hsio_sata_phy_resets(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ /* clear PHY RST, then set it */
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_PHYRESET_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_PHYRESET_N);
+
+ /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
+ udelay(1);
+ regmap_clear_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_RESET_N);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
+}
+
+static void imx_hsio_configure_clk_pad(struct phy *phy)
+{
+ bool pll = false;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (strncmp(priv->refclk_pad, "output", 6) == 0) {
+ pll = true;
+ regmap_update_bits(priv->misc, HSIO_CTRL0,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_2);
+ } else {
+ regmap_update_bits(priv->misc, HSIO_CTRL0,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
+ 0);
+ }
+
+ regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_RXENA,
+ pll ? 0 : HSIO_IOB_RXENA);
+ regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_TXENA,
+ pll ? HSIO_IOB_TXENA : 0);
+}
+
+static void imx_hsio_pre_set(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ atomic_set(&priv->open_cnt, 1);
+ if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2PCIEB)
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
+ if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2SATA)
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
+
+ imx_hsio_configure_clk_pad(phy);
+}
+
+static int imx_hsio_pcie_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, addr, cond;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ imx_hsio_pcie_phy_resets(phy);
+
+ /* Toggle apb_pclk to make sure PM_REQ_CORE_RST is cleared. */
+ clk_disable_unprepare(lane->clks[0].clk);
+ mdelay(1);
+ ret = clk_prepare_enable(lane->clks[0].clk);
+ if (ret) {
+ dev_err(priv->dev, "unable to enable phy apb_pclk\n");
+ return ret;
+ }
+
+ addr = lane->ctrl_off + HSIO_PCIE_STS0;
+ cond = HSIO_PM_REQ_CORE_RST;
+ ret = regmap_read_poll_timeout(priv->ctrl, addr, val,
+ (val & cond) == 0,
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT);
+ if (ret)
+ dev_err(priv->dev, "HSIO_PM_REQ_CORE_RST is set\n");
+ return ret;
+}
+
+static int imx_hsio_sata_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, cond;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ regmap_set_bits(priv->phy, lane->phy_off + HSIO_CTRL0, HSIO_APB_RSTN_0);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP);
+ regmap_set_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP_SEL);
+
+ imx_hsio_sata_phy_resets(phy);
+
+ cond = HSIO_REG48_PMA_RDY;
+ ret = read_poll_timeout(readb, val, ((val & cond) == cond),
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT, false,
+ priv->base + HSIO_REG48_PMA_STATUS);
+ if (ret)
+ dev_err(priv->dev, "PHY calibration is timeout\n");
+ else
+ dev_dbg(priv->dev, "PHY calibration is done\n");
+
+ return ret;
+}
+
+static int imx_hsio_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, cond;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (atomic_inc_and_test(&priv->open_cnt))
+ imx_hsio_pre_set(phy);
+
+ if (lane->phy_mode == PHY_MODE_PCIE)
+ ret = imx_hsio_pcie_power_on(phy);
+ else /* SATA */
+ ret = imx_hsio_sata_power_on(phy);
+ if (ret)
+ return ret;
+
+ /* Polling to check the PHY is ready or not. */
+ if (lane->idx == 1)
+ cond = HSIO_LANE1_TX_PLL_LOCK;
+ else
+ /*
+ * Except the phy_off, the bit-offset of lane2 is same to lane0.
+ * Merge the lane0 and lane2 bit-operations together.
+ */
+ cond = HSIO_LANE0_TX_PLL_LOCK;
+
+ ret = regmap_read_poll_timeout(priv->phy, lane->phy_off + HSIO_PHY_STS0,
+ val, ((val & cond) == cond),
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT);
+ if (ret) {
+ dev_err(priv->dev, "IMX8Q PHY%d PLL lock timeout\n", lane->idx);
+ return ret;
+ }
+ dev_dbg(priv->dev, "IMX8Q PHY%d PLL is locked\n", lane->idx);
+
+ return ret;
+}
+
+static int imx_hsio_power_off(struct phy *phy)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (atomic_dec_and_test(&priv->open_cnt)) {
+ atomic_set(&priv->open_cnt, -1);
+ regmap_clear_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
+ regmap_clear_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
+
+ if (lane->phy_mode == PHY_MODE_PCIE) {
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+ } else {
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP_SEL);
+ regmap_clear_bits(priv->ctrl,
+ lane->ctrl_off + HSIO_CTRL0,
+ HSIO_RESET_N);
+ }
+
+ if (lane->idx == 1) {
+ regmap_clear_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_1);
+ regmap_clear_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_1_MASK);
+ } else {
+ /*
+ * Except the phy_off, the bit-offset of lane2 is same
+ * to lane0. Merge the lane0 and lane2 bit-operations
+ * together.
+ */
+ regmap_clear_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_0);
+ regmap_clear_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_0_MASK);
+ }
+ }
+
+ return 0;
+}
+
+static int imx_hsio_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ u32 val;
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ if (lane->phy_mode != mode)
+ return -EINVAL;
+
+ val = (mode == PHY_MODE_PCIE) ? HSIO_MODE_PCIE : HSIO_MODE_SATA;
+ val = FIELD_PREP(HSIO_MODE_MASK, val);
+ regmap_update_bits(priv->phy, lane->phy_off + HSIO_CTRL0,
+ HSIO_MODE_MASK, val);
+
+ switch (submode) {
+ case PHY_MODE_PCIE_RC:
+ val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
+ break;
+ case PHY_MODE_PCIE_EP:
+ val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ENDPOINT);
+ break;
+ default: /* Support only PCIe EP and RC now. */
+ return 0;
+ }
+ if (submode)
+ regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL0,
+ HSIO_DEVICE_TYPE_MASK, val);
+
+ return 0;
+}
+
+static int imx_hsio_set_speed(struct phy *phy, int speed)
+{
+ struct imx_hsio_lane *lane = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = lane->priv;
+
+ regmap_update_bits(priv->ctrl, lane->ctrl_off + HSIO_CTRL2,
+ HSIO_LTSSM_ENABLE,
+ speed ? HSIO_LTSSM_ENABLE : 0);
+ return 0;
+}
+
+static const struct phy_ops imx_hsio_ops = {
+ .init = imx_hsio_init,
+ .exit = imx_hsio_exit,
+ .power_on = imx_hsio_power_on,
+ .power_off = imx_hsio_power_off,
+ .set_mode = imx_hsio_set_mode,
+ .set_speed = imx_hsio_set_speed,
+ .owner = THIS_MODULE,
+};
+
+static const struct imx_hsio_drvdata imx8qxp_hsio_drvdata = {
+ .lane_num = 0x1,
+};
+
+static const struct imx_hsio_drvdata imx_hsio_drvdata = {
+ .lane_num = 0x3,
+};
+
+static const struct of_device_id imx_hsio_of_match[] = {
+ {.compatible = "fsl,imx8qm-hsio", .data = &imx_hsio_drvdata},
+ {.compatible = "fsl,imx8qxp-hsio", .data = &imx8qxp_hsio_drvdata},
+ { },
+};
+MODULE_DEVICE_TABLE(of, imx_hsio_of_match);
+
+static struct phy *imx_hsio_xlate(struct device *dev,
+ const struct of_phandle_args *args)
+{
+ struct imx_hsio_priv *priv = dev_get_drvdata(dev);
+ int idx = args->args[0];
+ int phy_type = args->args[1];
+ int ctrl_index = args->args[2];
+
+ if (idx < 0 || idx >= priv->drvdata->lane_num)
+ return ERR_PTR(-EINVAL);
+ priv->lane[idx].idx = idx;
+ priv->lane[idx].phy_type = phy_type;
+ priv->lane[idx].ctrl_index = ctrl_index;
+
+ return priv->lane[idx].phy;
+}
+
+static int imx_hsio_probe(struct platform_device *pdev)
+{
+ int i;
+ void __iomem *off;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct imx_hsio_priv *priv;
+ struct phy_provider *provider;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ priv->dev = &pdev->dev;
+ priv->drvdata = of_device_get_match_data(dev);
+ atomic_set(&priv->open_cnt, -1);
+
+ /* Get HSIO configuration mode */
+ if (of_property_read_u32(np, "fsl,hsio-cfg", &priv->hsio_cfg))
+ priv->hsio_cfg = 0;
+ /* Get PHY refclk pad mode */
+ if (of_property_read_string(np, "fsl,refclk-pad-mode",
+ &priv->refclk_pad))
+ priv->refclk_pad = NULL;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ off = devm_platform_ioremap_resource_byname(pdev, "phy");
+ priv->phy = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->phy))
+ return dev_err_probe(dev, PTR_ERR(priv->phy),
+ "unable to find phy csr registers\n");
+
+ off = devm_platform_ioremap_resource_byname(pdev, "ctrl");
+ priv->ctrl = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->ctrl))
+ return dev_err_probe(dev, PTR_ERR(priv->ctrl),
+ "unable to find ctrl csr registers\n");
+
+ off = devm_platform_ioremap_resource_byname(pdev, "misc");
+ priv->misc = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->misc))
+ return dev_err_probe(dev, PTR_ERR(priv->misc),
+ "unable to find misc csr registers\n");
+
+ for (i = 0; i < priv->drvdata->lane_num; i++) {
+ struct imx_hsio_lane *lane = &priv->lane[i];
+ struct phy *phy;
+
+ memset(lane, 0, sizeof(*lane));
+
+ phy = devm_phy_create(&pdev->dev, NULL, &imx_hsio_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ lane->priv = priv;
+ lane->phy = phy;
+ lane->idx = i;
+ phy_set_drvdata(phy, lane);
+ }
+
+ dev_set_drvdata(dev, priv);
+ dev_set_drvdata(&pdev->dev, priv);
+
+ provider = devm_of_phy_provider_register(&pdev->dev, imx_hsio_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver imx_hsio_driver = {
+ .probe = imx_hsio_probe,
+ .driver = {
+ .name = "imx8qm-hsio-phy",
+ .of_match_table = imx_hsio_of_match,
+ }
+};
+module_platform_driver(imx_hsio_driver);
+
+MODULE_DESCRIPTION("FSL IMX8QM HSIO SERDES PHY driver");
+MODULE_LICENSE("GPL");
--
2.37.1
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^ permalink raw reply related [relevance 6%]
* [PATCH v2 RESEND] soc: xilinx: Add cb event for subsystem restart
@ 2024-05-09 4:56 10% Jay Buddhabhatti
0 siblings, 0 replies; 200+ results
From: Jay Buddhabhatti @ 2024-05-09 4:56 UTC (permalink / raw)
To: michal.simek; +Cc: linux-arm-kernel, linux-kernel, Jay Buddhabhatti
Add support to register subsystem restart events from firmware for Versal
and Versal NET platforms. This event is received when firmware requests
for subsystem restart. After receiving this event, the kernel needs to be
restarted.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
---
V1: https://lore.kernel.org/lkml/20240424095937.2448-1-jay.buddhabhatti@amd.com/
V1->V2: Updated copyright header in xlnx-event-manager.h
---
drivers/soc/xilinx/zynqmp_power.c | 151 +++++++++++++++++---
include/linux/firmware/xlnx-event-manager.h | 10 ++
2 files changed, 141 insertions(+), 20 deletions(-)
diff --git a/drivers/soc/xilinx/zynqmp_power.c b/drivers/soc/xilinx/zynqmp_power.c
index 965b1143936a..fced6bedca43 100644
--- a/drivers/soc/xilinx/zynqmp_power.c
+++ b/drivers/soc/xilinx/zynqmp_power.c
@@ -30,9 +30,27 @@ struct zynqmp_pm_work_struct {
u32 args[CB_ARG_CNT];
};
-static struct zynqmp_pm_work_struct *zynqmp_pm_init_suspend_work;
+/**
+ * struct zynqmp_pm_event_info - event related information
+ * @cb_fun: Function pointer to store the callback function.
+ * @cb_type: Type of callback from pm_api_cb_id,
+ * PM_NOTIFY_CB - for Error Events,
+ * PM_INIT_SUSPEND_CB - for suspend callback.
+ * @node_id: Node-Id related to event.
+ * @event: Event Mask for the Error Event.
+ * @wake: Flag specifying whether the subsystem should be woken upon
+ * event notification.
+ */
+struct zynqmp_pm_event_info {
+ event_cb_func_t cb_fun;
+ enum pm_api_cb_id cb_type;
+ u32 node_id;
+ u32 event;
+ bool wake;
+};
+
+static struct zynqmp_pm_work_struct *zynqmp_pm_init_suspend_work, *zynqmp_pm_init_restart_work;
static struct mbox_chan *rx_chan;
-static bool event_registered;
enum pm_suspend_mode {
PM_SUSPEND_MODE_FIRST = 0,
@@ -54,6 +72,19 @@ static void zynqmp_pm_get_callback_data(u32 *buf)
zynqmp_pm_invoke_fn(GET_CALLBACK_DATA, buf, 0);
}
+static void subsystem_restart_event_callback(const u32 *payload, void *data)
+{
+ /* First element is callback API ID, others are callback arguments */
+ if (work_pending(&zynqmp_pm_init_restart_work->callback_work))
+ return;
+
+ /* Copy callback arguments into work's structure */
+ memcpy(zynqmp_pm_init_restart_work->args, &payload[0],
+ sizeof(zynqmp_pm_init_restart_work->args));
+
+ queue_work(system_unbound_wq, &zynqmp_pm_init_restart_work->callback_work);
+}
+
static void suspend_event_callback(const u32 *payload, void *data)
{
/* First element is callback API ID, others are callback arguments */
@@ -119,6 +150,37 @@ static void ipi_receive_callback(struct mbox_client *cl, void *data)
}
}
+/**
+ * zynqmp_pm_subsystem_restart_work_fn - Initiate Subsystem restart
+ * @work: Pointer to work_struct
+ *
+ * Bottom-half of PM callback IRQ handler.
+ */
+static void zynqmp_pm_subsystem_restart_work_fn(struct work_struct *work)
+{
+ int ret;
+ struct zynqmp_pm_work_struct *pm_work = container_of(work, struct zynqmp_pm_work_struct,
+ callback_work);
+
+ /* First element is callback API ID, others are callback arguments */
+ if (pm_work->args[0] == PM_NOTIFY_CB) {
+ if (pm_work->args[2] == EVENT_SUBSYSTEM_RESTART) {
+ ret = zynqmp_pm_system_shutdown(ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY,
+ ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM);
+ if (ret) {
+ pr_err("unable to set shutdown scope\n");
+ return;
+ }
+
+ kernel_restart(NULL);
+ } else {
+ pr_err("%s Unsupported Event - %d\n", __func__, pm_work->args[2]);
+ }
+ } else {
+ pr_err("%s() Unsupported Callback %d\n", __func__, pm_work->args[0]);
+ }
+}
+
/**
* zynqmp_pm_init_suspend_work_fn - Initialize suspend
* @work: Pointer to work_struct
@@ -184,10 +246,46 @@ static ssize_t suspend_mode_store(struct device *dev,
static DEVICE_ATTR_RW(suspend_mode);
+static void unregister_event(struct device *dev, void *res)
+{
+ struct zynqmp_pm_event_info *event_info = res;
+
+ xlnx_unregister_event(event_info->cb_type, event_info->node_id,
+ event_info->event, event_info->cb_fun, NULL);
+}
+
+static int register_event(struct device *dev, const enum pm_api_cb_id cb_type, const u32 node_id,
+ const u32 event, const bool wake, event_cb_func_t cb_fun)
+{
+ int ret;
+ struct zynqmp_pm_event_info *event_info;
+
+ event_info = devres_alloc(unregister_event, sizeof(struct zynqmp_pm_event_info),
+ GFP_KERNEL);
+ if (!event_info)
+ return -ENOMEM;
+
+ event_info->cb_type = cb_type;
+ event_info->node_id = node_id;
+ event_info->event = event;
+ event_info->wake = wake;
+ event_info->cb_fun = cb_fun;
+
+ ret = xlnx_register_event(event_info->cb_type, event_info->node_id,
+ event_info->event, event_info->wake, event_info->cb_fun, NULL);
+ if (ret) {
+ devres_free(event_info);
+ return ret;
+ }
+
+ devres_add(dev, event_info);
+ return 0;
+}
+
static int zynqmp_pm_probe(struct platform_device *pdev)
{
int ret, irq;
- u32 pm_api_version;
+ u32 pm_api_version, pm_family_code, pm_sub_family_code, node_id;
struct mbox_client *client;
zynqmp_pm_get_api_version(&pm_api_version);
@@ -203,21 +301,43 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
* is not available to use) or -ENODEV(Xilinx Event Manager not compiled),
* then use ipi-mailbox or interrupt method.
*/
- ret = xlnx_register_event(PM_INIT_SUSPEND_CB, 0, 0, false,
- suspend_event_callback, NULL);
+ ret = register_event(&pdev->dev, PM_INIT_SUSPEND_CB, 0, 0, false,
+ suspend_event_callback);
if (!ret) {
zynqmp_pm_init_suspend_work = devm_kzalloc(&pdev->dev,
sizeof(struct zynqmp_pm_work_struct),
GFP_KERNEL);
- if (!zynqmp_pm_init_suspend_work) {
- xlnx_unregister_event(PM_INIT_SUSPEND_CB, 0, 0,
- suspend_event_callback, NULL);
+ if (!zynqmp_pm_init_suspend_work)
return -ENOMEM;
- }
- event_registered = true;
INIT_WORK(&zynqmp_pm_init_suspend_work->callback_work,
zynqmp_pm_init_suspend_work_fn);
+
+ ret = zynqmp_pm_get_family_info(&pm_family_code, &pm_sub_family_code);
+ if (ret < 0)
+ return ret;
+
+ if (pm_sub_family_code == VERSALNET_SUB_FAMILY_CODE)
+ node_id = PM_DEV_ACPU_0_0;
+ else
+ node_id = PM_DEV_ACPU_0;
+
+ ret = register_event(&pdev->dev, PM_NOTIFY_CB, node_id, EVENT_SUBSYSTEM_RESTART,
+ false, subsystem_restart_event_callback);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to Register with Xilinx Event manager %d\n",
+ ret);
+ return ret;
+ }
+
+ zynqmp_pm_init_restart_work = devm_kzalloc(&pdev->dev,
+ sizeof(struct zynqmp_pm_work_struct),
+ GFP_KERNEL);
+ if (!zynqmp_pm_init_restart_work)
+ return -ENOMEM;
+
+ INIT_WORK(&zynqmp_pm_init_restart_work->callback_work,
+ zynqmp_pm_subsystem_restart_work_fn);
} else if (ret != -EACCES && ret != -ENODEV) {
dev_err(&pdev->dev, "Failed to Register with Xilinx Event manager %d\n", ret);
return ret;
@@ -264,15 +384,8 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
}
ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_suspend_mode.attr);
- if (ret) {
- if (event_registered) {
- xlnx_unregister_event(PM_INIT_SUSPEND_CB, 0, 0, suspend_event_callback,
- NULL);
- event_registered = false;
- }
- dev_err(&pdev->dev, "unable to create sysfs interface\n");
+ if (ret)
return ret;
- }
return 0;
}
@@ -280,8 +393,6 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
static void zynqmp_pm_remove(struct platform_device *pdev)
{
sysfs_remove_file(&pdev->dev.kobj, &dev_attr_suspend_mode.attr);
- if (event_registered)
- xlnx_unregister_event(PM_INIT_SUSPEND_CB, 0, 0, suspend_event_callback, NULL);
if (!rx_chan)
mbox_free_channel(rx_chan);
diff --git a/include/linux/firmware/xlnx-event-manager.h b/include/linux/firmware/xlnx-event-manager.h
index 82e8254b0f80..645dd34155e6 100644
--- a/include/linux/firmware/xlnx-event-manager.h
+++ b/include/linux/firmware/xlnx-event-manager.h
@@ -1,4 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx Event Management Driver
+ *
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ */
#ifndef _FIRMWARE_XLNX_EVENT_MANAGER_H_
#define _FIRMWARE_XLNX_EVENT_MANAGER_H_
@@ -7,6 +12,11 @@
#define CB_MAX_PAYLOAD_SIZE (4U) /*In payload maximum 32bytes */
+#define EVENT_SUBSYSTEM_RESTART (4U)
+
+#define PM_DEV_ACPU_0_0 (0x1810c0afU)
+#define PM_DEV_ACPU_0 (0x1810c003U)
+
/************************** Exported Function *****************************/
typedef void (*event_cb_func_t)(const u32 *payload, void *data);
--
2.17.1
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^ permalink raw reply related [relevance 10%]
* Re: [PATCH v4 4/5] PCI: imx6: Convert to agnostic GPIO API
2024-05-09 1:24 0% ` Hongxing Zhu
@ 2024-05-09 4:24 0% ` Andy Shevchenko
0 siblings, 0 replies; 200+ results
From: Andy Shevchenko @ 2024-05-09 4:24 UTC (permalink / raw)
To: Hongxing Zhu
Cc: Andy Shevchenko, Manivannan Sadhasivam, Frank Li,
Krzysztof Wilczy��ski, linux-omap, linux-pci,
linux-arm-kernel, linux-kernel, imx, linux-amlogic,
linux-arm-msm, linux-tegra, Vignesh Raghavendra,
Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczy��ski, Rob Herring, Bjorn Helgaas,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Yue Wang, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl, Xiaowei Song, Binghui Wang,
Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár, Linus Walleij
Thu, May 09, 2024 at 01:24:45AM +0000, Hongxing Zhu kirjoitti:
> > -----Original Message-----
> > From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Sent: 2024年5月6日 22:21
...
> > - imx6_pcie->gpio_active_high = of_property_read_bool(node,
> > - "reset-gpio-active-high");
> > - if (gpio_is_valid(imx6_pcie->reset_gpio)) {
> > - ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
> > - imx6_pcie->gpio_active_high ?
> > - GPIOF_OUT_INIT_HIGH :
> > - GPIOF_OUT_INIT_LOW,
> > - "PCIe reset");
> > - if (ret) {
> > - dev_err(dev, "unable to get reset gpio\n");
> > - return ret;
> > - }
> > - } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
> > - return imx6_pcie->reset_gpio;
> > - }
> Please correct me if my understand is wrong.
> The "reset-gpio-active-high" property is added for some buggy board designs.
> On these buggy boards, the reset gpio is active high.
This is my understanding too.
> In the other words, the PERST# is active and remote endpoint device would
> be in reset stat when this gpio is high on these buggy boards.
Yes.
> I'm afraid that the PCIe would be broken on these boards, If these codes
> are removed totally,
No. Linus W. explained in the previous version review round how it's supposed
to work.
> and toggle the reset GPIO pin like below.
> ...
> gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0);
> msleep(100);
> gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1);
> ...
It's not the code that this patch adds. I'm not sure if I understand starting
from here what you mean.
> By the way, this reset GPIO pin should be high at end in
> imx6_pcie_deassert_core_reset() if the imx6_pcie->gpio_active_high is zero.
This seems a terminology mixup. You probably meant "inactive".
And this is exactly the case with this patch.
If you start thinking in terms of "active"/"inactive" you will see that there
is no contradiction and no behaviour change. The quirk itself is located in
gpiolib-of.c..
--
With Best Regards,
Andy Shevchenko
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* RE: [PATCH v4 4/5] PCI: imx6: Convert to agnostic GPIO API
2024-05-06 14:20 11% ` [PATCH v4 4/5] PCI: imx6: Convert " Andy Shevchenko
2024-05-07 19:22 0% ` Frank Li
@ 2024-05-09 1:24 0% ` Hongxing Zhu
2024-05-09 4:24 0% ` Andy Shevchenko
1 sibling, 1 reply; 200+ results
From: Hongxing Zhu @ 2024-05-09 1:24 UTC (permalink / raw)
To: Andy Shevchenko, Manivannan Sadhasivam, Frank Li,
Krzysztof Wilczy��ski, linux-omap, linux-pci,
linux-arm-kernel, linux-kernel, imx, linux-amlogic,
linux-arm-msm, linux-tegra
Cc: Vignesh Raghavendra, Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczy��ski, Rob Herring, Bjorn Helgaas,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Yue Wang, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl, Xiaowei Song, Binghui Wang,
Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár, Linus Walleij
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="gb2312", Size: 6093 bytes --]
> -----Original Message-----
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Sent: 2024Äê5ÔÂ6ÈÕ 22:21
> To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>; Frank Li
> <frank.li@nxp.com>; Krzysztof Wilczy¨½ski <kwilczynski@kernel.org>; Andy
> Shevchenko <andriy.shevchenko@linux.intel.com>; linux-omap@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; imx@lists.linux.dev;
> linux-amlogic@lists.infradead.org; linux-arm-msm@vger.kernel.org;
> linux-tegra@vger.kernel.org
> Cc: Vignesh Raghavendra <vigneshr@ti.com>; Siddharth Vadapalli
> <s-vadapalli@ti.com>; Lorenzo Pieralisi <lpieralisi@kernel.org>; Krzysztof
> Wilczy¨½ski <kw@linux.com>; Rob Herring <robh@kernel.org>; Bjorn Helgaas
> <bhelgaas@google.com>; Hongxing Zhu <hongxing.zhu@nxp.com>; Lucas Stach
> <l.stach@pengutronix.de>; Shawn Guo <shawnguo@kernel.org>; Sascha Hauer
> <s.hauer@pengutronix.de>; Pengutronix Kernel Team <kernel@pengutronix.de>;
> Fabio Estevam <festevam@gmail.com>; Yue Wang <yue.wang@Amlogic.com>;
> Neil Armstrong <neil.armstrong@linaro.org>; Kevin Hilman
> <khilman@baylibre.com>; Jerome Brunet <jbrunet@baylibre.com>; Martin
> Blumenstingl <martin.blumenstingl@googlemail.com>; Xiaowei Song
> <songxiaowei@hisilicon.com>; Binghui Wang <wangbinghui@hisilicon.com>;
> Thierry Reding <thierry.reding@gmail.com>; Jonathan Hunter
> <jonathanh@nvidia.com>; Thomas Petazzoni <thomas.petazzoni@bootlin.com>;
> Pali Roh¨¢r <pali@kernel.org>; Linus Walleij <linus.walleij@linaro.org>
> Subject: [PATCH v4 4/5] PCI: imx6: Convert to agnostic GPIO API
>
> The of_gpio.h is going to be removed. In preparation of that convert the driver to
> the agnostic API.
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 36 ++++++++-------------------
> 1 file changed, 10 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> b/drivers/pci/controller/dwc/pci-imx6.c
> index 917c69edee1d..62a4994c5501 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -11,14 +11,13 @@
> #include <linux/bitfield.h>
> #include <linux/clk.h>
> #include <linux/delay.h>
> -#include <linux/gpio.h>
> +#include <linux/gpio/consumer.h>
> #include <linux/kernel.h>
> #include <linux/mfd/syscon.h>
> #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
> #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> #include <linux/module.h>
> #include <linux/of.h>
> -#include <linux/of_gpio.h>
> #include <linux/of_address.h>
> #include <linux/pci.h>
> #include <linux/platform_device.h>
> @@ -107,8 +106,7 @@ struct imx6_pcie_drvdata {
>
> struct imx6_pcie {
> struct dw_pcie *pci;
> - int reset_gpio;
> - bool gpio_active_high;
> + struct gpio_desc *reset_gpiod;
> bool link_is_up;
> struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS];
> struct regmap *iomuxc_gpr;
> @@ -721,9 +719,7 @@ static void imx6_pcie_assert_core_reset(struct
> imx6_pcie *imx6_pcie)
> }
>
> /* Some boards don't have PCIe reset GPIO. */
> - if (gpio_is_valid(imx6_pcie->reset_gpio))
> - gpio_set_value_cansleep(imx6_pcie->reset_gpio,
> - imx6_pcie->gpio_active_high);
> + gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 1);
> }
>
> static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) @@
> -771,10 +767,9 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie
> *imx6_pcie)
> }
>
> /* Some boards don't have PCIe reset GPIO. */
> - if (gpio_is_valid(imx6_pcie->reset_gpio)) {
> + if (imx6_pcie->reset_gpiod) {
> msleep(100);
> - gpio_set_value_cansleep(imx6_pcie->reset_gpio,
> - !imx6_pcie->gpio_active_high);
> + gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 0);
> /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
> msleep(100);
> }
> @@ -1285,22 +1280,11 @@ static int imx6_pcie_probe(struct platform_device
> *pdev)
> return PTR_ERR(pci->dbi_base);
>
> /* Fetch GPIOs */
> - imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
> - imx6_pcie->gpio_active_high = of_property_read_bool(node,
> - "reset-gpio-active-high");
> - if (gpio_is_valid(imx6_pcie->reset_gpio)) {
> - ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
> - imx6_pcie->gpio_active_high ?
> - GPIOF_OUT_INIT_HIGH :
> - GPIOF_OUT_INIT_LOW,
> - "PCIe reset");
> - if (ret) {
> - dev_err(dev, "unable to get reset gpio\n");
> - return ret;
> - }
> - } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
> - return imx6_pcie->reset_gpio;
> - }
Hi Andy:
Please correct me if my understand is wrong.
The "reset-gpio-active-high" property is added for some buggy board designs.
On these buggy boards, the reset gpio is active high.
In the other words, the PERST# is active and remote endpoint device would
be in reset stat when this gpio is high on these buggy boards.
I'm afraid that the PCIe would be broken on these boards, If these codes
are removed totally, and toggle the reset GPIO pin like below.
...
gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0);
msleep(100);
gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1);
...
By the way, this reset GPIO pin should be high at end in
imx6_pcie_deassert_core_reset() if the imx6_pcie->gpio_active_high is zero.
Best Regards
Richard Zhu
> + imx6_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset",
> GPIOD_OUT_HIGH);
> + if (IS_ERR(imx6_pcie->reset_gpiod))
> + return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod),
> + "unable to get reset gpio\n");
> + gpiod_set_consumer_name(imx6_pcie->reset_gpiod, "PCIe reset");
>
> if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS)
> return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
> --
> 2.43.0.rc1.1336.g36b5255a03ac
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply [relevance 0%]
* Re: clkdev: report over-sized strings when creating clkdev entries
@ 2024-05-08 21:07 5% ` Sam Protsenko
0 siblings, 0 replies; 200+ results
From: Sam Protsenko @ 2024-05-08 21:07 UTC (permalink / raw)
To: Stephen Boyd
Cc: Arnd Bergmann, Linux ARM, Naresh Kamboju, linux-clk, lkft-triage,
open list, Russell King, Anders Roxell, Dan Carpenter,
Michael Turquette, Marek Szyprowski
On Tue, May 7, 2024 at 3:26 PM Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Arnd Bergmann (2024-05-07 00:44:15)
> > On Tue, May 7, 2024, at 09:20, Naresh Kamboju wrote:
> > > The WinLink E850-96 board boot failed with Linux next-20240506 but there
> > > is no kernel crash log on the serial [1].
> > >
> > > Anders bisection results pointing to this commit,
> > > # first bad commit:
> > > [4d11c62ca8d77cb1f79054844b598e0f4e92dabe]
> > > clkdev: report over-sized strings when creating clkdev entrie
> > >
> > > After reverting the above patch the boot test passed [2].
> > >
> > > Reported-by: Linux Kernel Functional Testing <lkft@linaro.org>
> > >
>
> There are two fixes on the list: [1] and [2]. Perhaps one of those
> resolves this?
>
> [1] https://lore.kernel.org/r/20240507065317.3214186-1-m.szyprowski@samsung.com
> [2] https://lore.kernel.org/r/20240507064434.3213933-1-m.szyprowski@samsung.com
>
Late to the party, but FWIW here is my two cents. E850-96 board
crashes on boot when running next-20240508. Enabling earlycon reveals
the details. Here is the relevant excerpt from the backtrace:
8<-------------------------------------------------------------------->8
Unable to handle kernel NULL pointer dereference
at virtual address 0000000000000000
Call trace:
vsnprintf+0x64/0x724
...
_printk+0x60/0x84
vclkdev_alloc+0x118/0x13c
clkdev_hw_create+0x64/0x9c
do_clk_register_clkdev+0x58/0x7c
clk_hw_register_clkdev+0x30/0x54
samsung_clk_register_fixed_rate+0xac/0x104
samsung_cmu_register_clocks+0x78/0xb0
samsung_cmu_register_one+0x48/0xa4
exynos_arm64_register_cmu+0x3c/0x70
exynos850_cmu_probe+0x2c/0x40
...
8<-------------------------------------------------------------------->8
'addr2line' points at the end of vclkdev_alloc():
pr_err("%pV:%s: %s ID is greater than %zu\n",
&fmt, con_id, failure, max_size);
Applying the forementioned patch [2] ("clkdev: fix potential NULL
pointer dereference") fixes the boot for me.
I can also observe a couple of warnings like these in the kernel log:
samsung_clk_register_fixed_rate: failed to register clock lookup
for clk_rco_i3c_pmic
samsung_clk_register_fixed_rate: failed to register clock lookup
for clk_rco_apm__alv
...
The patch [1] ("clk: samsung: Don't register clkdev lookup for the
fixed rate clocks") fixes those. I think both have to be applied ASAP.
In case of E850-96, I guess [1] is more critical.
Thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 5%]
* Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H616
2024-05-08 11:05 0% ` Andre Przywara
@ 2024-05-08 11:15 0% ` Dragan Simic
0 siblings, 0 replies; 200+ results
From: Dragan Simic @ 2024-05-08 11:15 UTC (permalink / raw)
To: Andre Przywara
Cc: linux-sunxi, wens, jernej.skrabec, samuel, linux-arm-kernel,
devicetree, robh, krzk+dt, conor+dt, linux-kernel
Hello Andre,
On 2024-05-08 13:05, Andre Przywara wrote:
> On Fri, 3 May 2024 11:09:41 +0200
> Dragan Simic <dsimic@manjaro.org> wrote:
>
>> Add missing cache information to the Allwinner H616 SoC dtsi, to allow
>> the userspace, which includes lscpu(1) that uses the virtual files
>> provided
>> by the kernel under the /sys/devices/system/cpu directory, to display
>> the
>> proper H616 cache information.
>>
>> Adding the cache information to the H616 SoC dtsi also makes the
>> following
>> warning message in the kernel log go away:
>>
>> cacheinfo: Unable to detect cache hierarchy for CPU 0
>>
>> Rather conspicuously, almost no cache-related information is available
>> in
>> the publicly available Allwinner H616 datasheet (version 1.0) and H616
>> user
>> manual (version 1.0). Thus, the cache parameters for the H616 SoC
>> dtsi were
>> obtained and derived by hand from the cache size and layout
>> specifications
>> found in the following technical reference manual, and from the cache
>> size
>> and die revision hints available from the following community-provided
>> data
>> and memory subsystem benchmarks:
>>
>> - ARM Cortex-A53 revision r0p4 TRM, version J
>> - Summary of the two available H616 die revisions and their
>> differences
>> in cache sizes observed from the CSSIDR_EL1 register readouts,
>> provided
>> by Andre Przywara [1][2]
>> - Tinymembench benchmark results of the H616-based OrangePi Zero 2
>> SBC,
>> provided by Thomas Kaiser [3]
>>
>> For future reference, here's a brief summary of the available
>> documentation
>> and the community-provided data and memory subsystem benchmarks:
>>
>> - All caches employ the 64-byte cache line length
>> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative
>> instruction
>> cache and 32 KB of L1 4-way, set-associative data cache
>> - The size of the L2 cache depends on the actual H616 die revision
>> (there
>> are two die revisions), so the entire SoC can have either 256 KB
>> or 1 MB
>> of unified L2 16-way, set-associative cache [1]
>>
>> Also for future reference, here's the relevant excerpt from the
>> community-
>> provided H616 memory subsystem benchmark, [3] which confirms that 32
>> KB and
>> 256 KB are the L1 data and L2 cache sizes, respectively:
>>
>> block size : single random read / dual random read
>> 1024 : 0.0 ns / 0.0 ns
>> 2048 : 0.0 ns / 0.0 ns
>> 4096 : 0.0 ns / 0.0 ns
>> 8192 : 0.0 ns / 0.0 ns
>> 16384 : 0.0 ns / 0.0 ns
>> 32768 : 0.0 ns / 0.0 ns
>> 65536 : 4.3 ns / 7.3 ns
>> 131072 : 6.6 ns / 10.5 ns
>> 262144 : 9.8 ns / 15.2 ns
>> 524288 : 91.8 ns / 142.9 ns
>> 1048576 : 138.6 ns / 188.3 ns
>> 2097152 : 163.0 ns / 204.8 ns
>> 4194304 : 178.8 ns / 213.5 ns
>> 8388608 : 187.1 ns / 217.9 ns
>> 16777216 : 192.2 ns / 220.9 ns
>> 33554432 : 196.5 ns / 224.0 ns
>> 67108864 : 215.7 ns / 259.5 ns
>
> Thanks for dumping the elaborate information here!
You're welcome! :) I like when patch descriptions provide as much
relevant information as possible, so I always try to do that myself.
>> The changes introduced to the H616 SoC dtsi by this patch specify 256
>> KB as
>> the L2 cache size. As outlined by Andre Przywara, [2] a follow-up
>> TF-A patch
>> will perform runtime adjustment of the device tree data, making the
>> correct
>> L2 cache size of 1 MB present in the device tree for the boards based
>> on the
>> revision of H616 that actually provides 1 MB of L2 cache.
>
> I pushed that TF-A patch for review now:
> https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/28694/1
> On my OrangePi Zero3 (with an 1MB H618 SoC) the size and number of sets
> get adjusted to describe 1MB:
> => fdt list /cpus/l2-cache
> l2-cache {
> compatible = "cache";
> cache-level = <0x00000002>;
> cache-unified;
> cache-size = <0x00100000>;
> cache-line-size = <0x00000040>;
> cache-sets = <0x00000400>;
> phandle = <0x00000003>;
> };
Awesome, thanks for the follow-up TF-A patch! I'll keep an eye
on your TF-A patch submission.
>> [1]
>> https://lore.kernel.org/linux-sunxi/20240430114627.0cfcd14a@donnerap.manchester.arm.com/
>> [2]
>> https://lore.kernel.org/linux-sunxi/20240501103059.10a8f7de@donnerap.manchester.arm.com/
>> [3]
>> https://raw.githubusercontent.com/ThomasKaiser/sbc-bench/master/results/4knM.txt
>>
>> Suggested-by: Andre Przywara <andre.przywara@arm.com>
>> Helped-by: Andre Przywara <andre.przywara@arm.com>
>> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
>
> So I can confirm that the information above is correct, and also
> matches
> the DT properties added below.
>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Thanks!
>> ---
>> .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 37
>> +++++++++++++++++++
>> 1 file changed, 37 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
>> index b2e85e52d1a1..4faed88d8909 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
>> @@ -26,30 +26,67 @@ cpu0: cpu@0 {
>> reg = <0>;
>> enable-method = "psci";
>> clocks = <&ccu CLK_CPUX>;
>> + i-cache-size = <0x8000>;
>> + i-cache-line-size = <64>;
>> + i-cache-sets = <256>;
>> + d-cache-size = <0x8000>;
>> + d-cache-line-size = <64>;
>> + d-cache-sets = <128>;
>> + next-level-cache = <&l2_cache>;
>> };
>>
>> cpu1: cpu@1 {
>> compatible = "arm,cortex-a53";
>> device_type = "cpu";
>> reg = <1>;
>> enable-method = "psci";
>> clocks = <&ccu CLK_CPUX>;
>> + i-cache-size = <0x8000>;
>> + i-cache-line-size = <64>;
>> + i-cache-sets = <256>;
>> + d-cache-size = <0x8000>;
>> + d-cache-line-size = <64>;
>> + d-cache-sets = <128>;
>> + next-level-cache = <&l2_cache>;
>> };
>>
>> cpu2: cpu@2 {
>> compatible = "arm,cortex-a53";
>> device_type = "cpu";
>> reg = <2>;
>> enable-method = "psci";
>> clocks = <&ccu CLK_CPUX>;
>> + i-cache-size = <0x8000>;
>> + i-cache-line-size = <64>;
>> + i-cache-sets = <256>;
>> + d-cache-size = <0x8000>;
>> + d-cache-line-size = <64>;
>> + d-cache-sets = <128>;
>> + next-level-cache = <&l2_cache>;
>> };
>>
>> cpu3: cpu@3 {
>> compatible = "arm,cortex-a53";
>> device_type = "cpu";
>> reg = <3>;
>> enable-method = "psci";
>> clocks = <&ccu CLK_CPUX>;
>> + i-cache-size = <0x8000>;
>> + i-cache-line-size = <64>;
>> + i-cache-sets = <256>;
>> + d-cache-size = <0x8000>;
>> + d-cache-line-size = <64>;
>> + d-cache-sets = <128>;
>> + next-level-cache = <&l2_cache>;
>> + };
>> +
>> + l2_cache: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + cache-size = <0x40000>;
>> + cache-line-size = <64>;
>> + cache-sets = <256>;
>> };
>> };
>>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H616
2024-05-03 9:09 4% [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H616 Dragan Simic
@ 2024-05-08 11:05 0% ` Andre Przywara
2024-05-08 11:15 0% ` Dragan Simic
2024-05-28 16:08 0% ` Chen-Yu Tsai
1 sibling, 1 reply; 200+ results
From: Andre Przywara @ 2024-05-08 11:05 UTC (permalink / raw)
To: Dragan Simic
Cc: linux-sunxi, wens, jernej.skrabec, samuel, linux-arm-kernel,
devicetree, robh, krzk+dt, conor+dt, linux-kernel
On Fri, 3 May 2024 11:09:41 +0200
Dragan Simic <dsimic@manjaro.org> wrote:
> Add missing cache information to the Allwinner H616 SoC dtsi, to allow
> the userspace, which includes lscpu(1) that uses the virtual files provided
> by the kernel under the /sys/devices/system/cpu directory, to display the
> proper H616 cache information.
>
> Adding the cache information to the H616 SoC dtsi also makes the following
> warning message in the kernel log go away:
>
> cacheinfo: Unable to detect cache hierarchy for CPU 0
>
> Rather conspicuously, almost no cache-related information is available in
> the publicly available Allwinner H616 datasheet (version 1.0) and H616 user
> manual (version 1.0). Thus, the cache parameters for the H616 SoC dtsi were
> obtained and derived by hand from the cache size and layout specifications
> found in the following technical reference manual, and from the cache size
> and die revision hints available from the following community-provided data
> and memory subsystem benchmarks:
>
> - ARM Cortex-A53 revision r0p4 TRM, version J
> - Summary of the two available H616 die revisions and their differences
> in cache sizes observed from the CSSIDR_EL1 register readouts, provided
> by Andre Przywara [1][2]
> - Tinymembench benchmark results of the H616-based OrangePi Zero 2 SBC,
> provided by Thomas Kaiser [3]
>
> For future reference, here's a brief summary of the available documentation
> and the community-provided data and memory subsystem benchmarks:
>
> - All caches employ the 64-byte cache line length
> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction
> cache and 32 KB of L1 4-way, set-associative data cache
> - The size of the L2 cache depends on the actual H616 die revision (there
> are two die revisions), so the entire SoC can have either 256 KB or 1 MB
> of unified L2 16-way, set-associative cache [1]
>
> Also for future reference, here's the relevant excerpt from the community-
> provided H616 memory subsystem benchmark, [3] which confirms that 32 KB and
> 256 KB are the L1 data and L2 cache sizes, respectively:
>
> block size : single random read / dual random read
> 1024 : 0.0 ns / 0.0 ns
> 2048 : 0.0 ns / 0.0 ns
> 4096 : 0.0 ns / 0.0 ns
> 8192 : 0.0 ns / 0.0 ns
> 16384 : 0.0 ns / 0.0 ns
> 32768 : 0.0 ns / 0.0 ns
> 65536 : 4.3 ns / 7.3 ns
> 131072 : 6.6 ns / 10.5 ns
> 262144 : 9.8 ns / 15.2 ns
> 524288 : 91.8 ns / 142.9 ns
> 1048576 : 138.6 ns / 188.3 ns
> 2097152 : 163.0 ns / 204.8 ns
> 4194304 : 178.8 ns / 213.5 ns
> 8388608 : 187.1 ns / 217.9 ns
> 16777216 : 192.2 ns / 220.9 ns
> 33554432 : 196.5 ns / 224.0 ns
> 67108864 : 215.7 ns / 259.5 ns
Thanks for dumping the elaborate information here!
> The changes introduced to the H616 SoC dtsi by this patch specify 256 KB as
> the L2 cache size. As outlined by Andre Przywara, [2] a follow-up TF-A patch
> will perform runtime adjustment of the device tree data, making the correct
> L2 cache size of 1 MB present in the device tree for the boards based on the
> revision of H616 that actually provides 1 MB of L2 cache.
I pushed that TF-A patch for review now:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/28694/1
On my OrangePi Zero3 (with an 1MB H618 SoC) the size and number of sets
get adjusted to describe 1MB:
=> fdt list /cpus/l2-cache
l2-cache {
compatible = "cache";
cache-level = <0x00000002>;
cache-unified;
cache-size = <0x00100000>;
cache-line-size = <0x00000040>;
cache-sets = <0x00000400>;
phandle = <0x00000003>;
};
> [1] https://lore.kernel.org/linux-sunxi/20240430114627.0cfcd14a@donnerap.manchester.arm.com/
> [2] https://lore.kernel.org/linux-sunxi/20240501103059.10a8f7de@donnerap.manchester.arm.com/
> [3] https://raw.githubusercontent.com/ThomasKaiser/sbc-bench/master/results/4knM.txt
>
> Suggested-by: Andre Przywara <andre.przywara@arm.com>
> Helped-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
So I can confirm that the information above is correct, and also matches
the DT properties added below.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Thanks!
Andre
> ---
> .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 37 +++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> index b2e85e52d1a1..4faed88d8909 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> @@ -26,30 +26,67 @@ cpu0: cpu@0 {
> reg = <0>;
> enable-method = "psci";
> clocks = <&ccu CLK_CPUX>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_cache>;
> };
>
> cpu1: cpu@1 {
> compatible = "arm,cortex-a53";
> device_type = "cpu";
> reg = <1>;
> enable-method = "psci";
> clocks = <&ccu CLK_CPUX>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_cache>;
> };
>
> cpu2: cpu@2 {
> compatible = "arm,cortex-a53";
> device_type = "cpu";
> reg = <2>;
> enable-method = "psci";
> clocks = <&ccu CLK_CPUX>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_cache>;
> };
>
> cpu3: cpu@3 {
> compatible = "arm,cortex-a53";
> device_type = "cpu";
> reg = <3>;
> enable-method = "psci";
> clocks = <&ccu CLK_CPUX>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_cache>;
> + };
> +
> + l2_cache: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + cache-size = <0x40000>;
> + cache-line-size = <64>;
> + cache-sets = <256>;
> };
> };
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH 16/17] mfd: Add support for LAN966x PCI device
2024-04-30 8:37 5% ` [PATCH 16/17] mfd: Add support for LAN966x PCI device Herve Codina
@ 2024-05-08 8:20 0% ` Steen.Hegelund
2024-05-14 12:55 0% ` Herve Codina
0 siblings, 1 reply; 200+ results
From: Steen.Hegelund @ 2024-05-08 8:20 UTC (permalink / raw)
To: herve.codina, tglx, robh, krzk+dt, conor+dt, davem, edumazet,
kuba, pabeni, lee, arnd, Horatiu.Vultur, UNGLinuxDriver, andrew,
hkallweit1, linux, saravanak, bhelgaas, p.zabel, Lars.Povlsen,
Steen.Hegelund, Daniel.Machon, alexandre.belloni
Cc: linux-kernel, devicetree, netdev, linux-pci, linux-arm-kernel,
Allan.Nielsen, luca.ceresoli, thomas.petazzoni
Hi Herve,
On Tue Apr 30, 2024 at 10:37 AM CEST, Herve Codina wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add a PCI driver that handles the LAN966x PCI device using a device-tree
> overlay. This overlay is applied to the PCI device DT node and allows to
> describe components that are present in the device.
>
> The memory from the device-tree is remapped to the BAR memory thanks to
> "ranges" properties computed at runtime by the PCI core during the PCI
> enumeration.
> The PCI device itself acts as an interrupt controller and is used as the
> parent of the internal LAN966x interrupt controller to route the
> interrupts to the assigned PCI INTx interrupt.
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
> drivers/mfd/Kconfig | 24 ++++
> drivers/mfd/Makefile | 4 +
> drivers/mfd/lan966x_pci.c | 229 +++++++++++++++++++++++++++++++++++
> drivers/mfd/lan966x_pci.dtso | 167 +++++++++++++++++++++++++
> drivers/pci/quirks.c | 1 +
> 5 files changed, 425 insertions(+)
> create mode 100644 drivers/mfd/lan966x_pci.c
> create mode 100644 drivers/mfd/lan966x_pci.dtso
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 4b023ee229cf..e5f5d2986dd3 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -144,6 +144,30 @@ config MFD_ATMEL_FLEXCOM
> by the probe function of this MFD driver according to a device tree
> property.
>
> +config MFD_LAN966X_PCI
> + tristate "Microchip LAN966x PCIe Support"
> + depends on PCI
> + select OF
> + select OF_OVERLAY
> + select IRQ_DOMAIN
> + help
> + This enables the support for the LAN966x PCIe device.
> + This is used to drive the LAN966x PCIe device from the host system
> + to which it is connected.
> +
> + This driver uses an overlay to load other drivers to support for
> + LAN966x internal components.
> + Even if this driver does not depend on these other drivers, in order
> + to have a fully functional board, the following drivers are needed:
> + - fixed-clock (COMMON_CLK)
> + - lan966x-oic (LAN966X_OIC)
> + - lan966x-cpu-syscon (MFD_SYSCON)
> + - lan966x-switch-reset (RESET_MCHP_SPARX5)
> + - lan966x-pinctrl (PINCTRL_OCELOT)
> + - lan966x-serdes (PHY_LAN966X_SERDES)
> + - lan966x-miim (MDIO_MSCC_MIIM)
> + - lan966x-switch (LAN966X_SWITCH)
> +
> config MFD_ATMEL_HLCDC
> tristate "Atmel HLCDC (High-end LCD Controller)"
> select MFD_CORE
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index c66f07edcd0e..165a9674ff48 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -284,3 +284,7 @@ rsmu-i2c-objs := rsmu_core.o rsmu_i2c.o
> rsmu-spi-objs := rsmu_core.o rsmu_spi.o
> obj-$(CONFIG_MFD_RSMU_I2C) += rsmu-i2c.o
> obj-$(CONFIG_MFD_RSMU_SPI) += rsmu-spi.o
> +
> +lan966x-pci-objs := lan966x_pci.o
> +lan966x-pci-objs += lan966x_pci.dtbo.o
> +obj-$(CONFIG_MFD_LAN966X_PCI) += lan966x-pci.o
> diff --git a/drivers/mfd/lan966x_pci.c b/drivers/mfd/lan966x_pci.c
> new file mode 100644
> index 000000000000..d9d886a1948f
> --- /dev/null
> +++ b/drivers/mfd/lan966x_pci.c
> @@ -0,0 +1,229 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Microchip LAN966x PCI driver
> + *
> + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
> + *
> + * Authors:
> + * Clément Léger <clement.leger@bootlin.com>
> + * Hervé Codina <herve.codina@bootlin.com>
> + */
> +
> +#include <linux/irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/pci.h>
> +#include <linux/slab.h>
> +
> +/* Embedded dtbo symbols created by cmd_wrap_S_dtb in scripts/Makefile.lib */
> +extern char __dtbo_lan966x_pci_begin[];
> +extern char __dtbo_lan966x_pci_end[];
> +
> +struct pci_dev_intr_ctrl {
> + struct pci_dev *pci_dev;
> + struct irq_domain *irq_domain;
> + int irq;
> +};
> +
> +static int pci_dev_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw)
> +{
> + irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_simple_irq);
> + return 0;
> +}
> +
> +static const struct irq_domain_ops pci_dev_irq_domain_ops = {
> + .map = pci_dev_irq_domain_map,
> + .xlate = irq_domain_xlate_onecell,
> +};
> +
> +static irqreturn_t pci_dev_irq_handler(int irq, void *data)
> +{
> + struct pci_dev_intr_ctrl *intr_ctrl = data;
> + int ret;
> +
> + ret = generic_handle_domain_irq(intr_ctrl->irq_domain, 0);
> + return ret ? IRQ_NONE : IRQ_HANDLED;
> +}
> +
> +static struct pci_dev_intr_ctrl *pci_dev_create_intr_ctrl(struct pci_dev *pdev)
> +{
> + struct pci_dev_intr_ctrl *intr_ctrl;
> + struct fwnode_handle *fwnode;
> + int ret;
> +
> + if (!pdev->irq)
> + return ERR_PTR(-EOPNOTSUPP);
> +
> + fwnode = dev_fwnode(&pdev->dev);
> + if (!fwnode)
> + return ERR_PTR(-ENODEV);
> +
> + intr_ctrl = kmalloc(sizeof(*intr_ctrl), GFP_KERNEL);
> + if (!intr_ctrl)
> + return ERR_PTR(-ENOMEM);
> +
> + intr_ctrl->pci_dev = pdev;
> +
> + intr_ctrl->irq_domain = irq_domain_create_linear(fwnode, 1, &pci_dev_irq_domain_ops,
> + intr_ctrl);
> + if (!intr_ctrl->irq_domain) {
> + pci_err(pdev, "Failed to create irqdomain\n");
> + ret = -ENOMEM;
> + goto err_free_intr_ctrl;
> + }
> +
> + ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
> + if (ret < 0) {
> + pci_err(pdev, "Unable alloc irq vector (%d)\n", ret);
> + goto err_remove_domain;
> + }
> + intr_ctrl->irq = pci_irq_vector(pdev, 0);
> + ret = request_irq(intr_ctrl->irq, pci_dev_irq_handler, IRQF_SHARED,
> + dev_name(&pdev->dev), intr_ctrl);
> + if (ret) {
> + pci_err(pdev, "Unable to request irq %d (%d)\n", intr_ctrl->irq, ret);
> + goto err_free_irq_vector;
> + }
> +
> + return intr_ctrl;
> +
> +err_free_irq_vector:
> + pci_free_irq_vectors(pdev);
> +err_remove_domain:
> + irq_domain_remove(intr_ctrl->irq_domain);
> +err_free_intr_ctrl:
> + kfree(intr_ctrl);
> + return ERR_PTR(ret);
> +}
> +
> +static void pci_dev_remove_intr_ctrl(struct pci_dev_intr_ctrl *intr_ctrl)
> +{
> + free_irq(intr_ctrl->irq, intr_ctrl);
> + pci_free_irq_vectors(intr_ctrl->pci_dev);
> + irq_dispose_mapping(irq_find_mapping(intr_ctrl->irq_domain, 0));
> + irq_domain_remove(intr_ctrl->irq_domain);
> + kfree(intr_ctrl);
> +}
> +
It looks like the two functions below (and their helper functions) are so
generic that they could be part of the pci driver core support.
Any plans for that?
> +static void devm_pci_dev_remove_intr_ctrl(void *data)
> +{
> + struct pci_dev_intr_ctrl *intr_ctrl = data;
> +
> + pci_dev_remove_intr_ctrl(intr_ctrl);
> +}
> +
> +static int devm_pci_dev_create_intr_ctrl(struct pci_dev *pdev)
> +{
> + struct pci_dev_intr_ctrl *intr_ctrl;
> +
> + intr_ctrl = pci_dev_create_intr_ctrl(pdev);
> +
> + if (IS_ERR(intr_ctrl))
> + return PTR_ERR(intr_ctrl);
> +
> + return devm_add_action_or_reset(&pdev->dev, devm_pci_dev_remove_intr_ctrl, intr_ctrl);
> +}
> +
...
[snip]
...
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index eff7f5df08e2..9933f245b781 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -6241,6 +6241,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
> +DECLARE_PCI_FIXUP_FINAL(0x1055, 0x9660, of_pci_make_dev_node);
>
> /*
> * Devices known to require a longer delay before first config space access
> --
> 2.44.0
Best Regards
Steen
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* [PATCH v8 3/3] pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driver
@ 2024-05-08 6:51 1% ` Jacky Huang
0 siblings, 0 replies; 200+ results
From: Jacky Huang @ 2024-05-08 6:51 UTC (permalink / raw)
To: linus.walleij, robh+dt, krzysztof.kozlowski+dt, conor+dt,
p.zabel, j.neuschaefer
Cc: linux-arm-kernel, linux-gpio, devicetree, linux-kernel, ychuang3, schung
From: Jacky Huang <ychuang3@nuvoton.com>
Add common pinctrl and GPIO driver for Nuvoton MA35 series SoC, and
add support for ma35d1 pinctrl.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
drivers/pinctrl/nuvoton/Kconfig | 19 +
drivers/pinctrl/nuvoton/Makefile | 2 +
drivers/pinctrl/nuvoton/pinctrl-ma35.c | 1197 ++++++++++++++
drivers/pinctrl/nuvoton/pinctrl-ma35.h | 52 +
drivers/pinctrl/nuvoton/pinctrl-ma35d1.c | 1799 ++++++++++++++++++++++
5 files changed, 3069 insertions(+)
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35.c
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35.h
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
index 2abbfcec1fae..7eadaaf48d6e 100644
--- a/drivers/pinctrl/nuvoton/Kconfig
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -45,3 +45,22 @@ config PINCTRL_NPCM8XX
Say Y or M here to enable pin controller and GPIO support for
the Nuvoton NPCM8XX SoC. This is strongly recommended when
building a kernel that will run on this chip.
+
+config PINCTRL_MA35
+ bool
+ depends on (ARCH_MA35 || COMPILE_TEST) && OF
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ select GPIOLIB
+ select GPIO_GENERIC
+ select GPIOLIB_IRQCHIP
+ select MFD_SYSCON
+
+config PINCTRL_MA35D1
+ bool "Pinctrl and GPIO driver for Nuvoton MA35D1"
+ depends on (ARCH_MA35 || COMPILE_TEST) && OF
+ select PINCTRL_MA35
+ help
+ Say Y here to enable pin controller and GPIO support
+ for Nuvoton MA35D1 SoC.
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
index 08031eab0af6..346c5082bc60 100644
--- a/drivers/pinctrl/nuvoton/Makefile
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -4,3 +4,5 @@
obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o
obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o
obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o
+obj-$(CONFIG_PINCTRL_MA35) += pinctrl-ma35.o
+obj-$(CONFIG_PINCTRL_MA35D1) += pinctrl-ma35d1.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c
new file mode 100644
index 000000000000..e17670246316
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c
@@ -0,0 +1,1197 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Nuvoton Technology Corp.
+ *
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ * * Jacky Huang <ychuang3@nuvoton.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/cleanup.h>
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "../core.h"
+#include "../pinconf.h"
+#include "pinctrl-ma35.h"
+
+#define MA35_MFP_REG_BASE 0x80
+#define MA35_MFP_REG_SZ_PER_BANK 8
+#define MA35_MFP_BITS_PER_PORT 4
+
+#define MA35_GPIO_BANK_MAX 14
+#define MA35_GPIO_PORT_MAX 16
+
+/* GPIO control registers */
+#define MA35_GP_REG_MODE 0x00
+#define MA35_GP_REG_DINOFF 0x04
+#define MA35_GP_REG_DOUT 0x08
+#define MA35_GP_REG_DATMSK 0x0c
+#define MA35_GP_REG_PIN 0x10
+#define MA35_GP_REG_DBEN 0x14
+#define MA35_GP_REG_INTTYPE 0x18
+#define MA35_GP_REG_INTEN 0x1c
+#define MA35_GP_REG_INTSRC 0x20
+#define MA35_GP_REG_SMTEN 0x24
+#define MA35_GP_REG_SLEWCTL 0x28
+#define MA35_GP_REG_SPW 0x2c
+#define MA35_GP_REG_PUSEL 0x30
+#define MA35_GP_REG_DSL 0x38
+#define MA35_GP_REG_DSH 0x3c
+
+/* GPIO mode control */
+#define MA35_GP_MODE_INPUT 0x0
+#define MA35_GP_MODE_OUTPUT 0x1
+#define MA35_GP_MODE_OPEN_DRAIN 0x2
+#define MA35_GP_MODE_QUASI 0x3
+#define MA35_GP_MODE_MASK(n) GENMASK(n * 2 + 1, n * 2)
+
+#define MA35_GP_SLEWCTL_MASK(n) GENMASK(n * 2 + 1, n * 2)
+
+/* GPIO pull-up and pull-down selection control */
+#define MA35_GP_PUSEL_DISABLE 0x0
+#define MA35_GP_PUSEL_PULL_UP 0x1
+#define MA35_GP_PUSEL_PULL_DOWN 0x2
+#define MA35_GP_PUSEL_MASK(n) GENMASK(n * 2 + 1, n * 2)
+
+/*
+ * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
+ * while bits 16 ~ 31 control high-level or rising edge trigger.
+ */
+#define MA35_GP_INTEN_L(n) BIT(n)
+#define MA35_GP_INTEN_H(n) BIT(n + 16)
+#define MA35_GP_INTEN_BOTH(n) (MA35_GP_INTEN_H(n) | MA35_GP_INTEN_L(n))
+
+/*
+ * The MA35_GP_REG_DSL register controls ports 0 to 7, while the MA35_GP_REG_DSH
+ * register controls ports 8 to 15. Each port occupies a width of 4 bits, with 3
+ * bits being effective.
+ */
+#define MA35_GP_DS_REG(n) (n < 8 ? MA35_GP_REG_DSL : MA35_GP_REG_DSH)
+#define MA35_GP_DS_MASK(n) GENMASK((n % 8) * 4 + 3, (n % 8) * 4)
+
+#define MVOLT_1800 0
+#define MVOLT_3300 1
+
+/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
+#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
+#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
+
+static const char * const gpio_group_name[] = {
+ "gpioa", "gpiob", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog",
+ "gpioh", "gpioi", "gpioj", "gpiok", "gpiol", "gpiom", "gpion",
+};
+
+static const u32 ds_1800mv_tbl[] = {
+ 2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000,
+};
+
+static const u32 ds_3300mv_tbl[] = {
+ 17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000,
+};
+
+struct ma35_pin_func {
+ const char *name;
+ const char **groups;
+ u32 ngroups;
+};
+
+struct ma35_pin_setting {
+ u32 offset;
+ u32 shift;
+ u32 muxval;
+ unsigned long *configs;
+ unsigned int nconfigs;
+};
+
+struct ma35_pin_group {
+ const char *name;
+ unsigned int npins;
+ unsigned int *pins;
+ struct ma35_pin_setting *settings;
+};
+
+struct ma35_pin_bank {
+ void __iomem *reg_base;
+ struct clk *clk;
+ int irq;
+ u8 bank_num;
+ u8 nr_pins;
+ bool valid;
+ const char *name;
+ struct fwnode_handle *fwnode;
+ struct gpio_chip chip;
+ u32 irqtype;
+ u32 irqinten;
+ struct regmap *regmap;
+ struct device *dev;
+};
+
+struct ma35_pin_ctrl {
+ struct ma35_pin_bank *pin_banks;
+ u32 nr_banks;
+ u32 nr_pins;
+};
+
+struct ma35_pinctrl {
+ struct device *dev;
+ struct ma35_pin_ctrl *ctrl;
+ struct pinctrl_dev *pctl;
+ const struct ma35_pinctrl_soc_info *info;
+ struct regmap *regmap;
+ struct ma35_pin_group *groups;
+ unsigned int ngroups;
+ struct ma35_pin_func *functions;
+ unsigned int nfunctions;
+};
+
+static DEFINE_RAW_SPINLOCK(ma35_lock);
+
+static int ma35_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return npctl->ngroups;
+}
+
+static const char *ma35_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return npctl->groups[selector].name;
+}
+
+static int ma35_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
+ const unsigned int **pins, unsigned int *npins)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+ if (selector >= npctl->ngroups)
+ return -EINVAL;
+
+ *pins = npctl->groups[selector].pins;
+ *npins = npctl->groups[selector].npins;
+
+ return 0;
+}
+
+static struct ma35_pin_group *ma35_pinctrl_find_group_by_name(
+ const struct ma35_pinctrl *npctl, const char *name)
+{
+ int i;
+
+ for (i = 0; i < npctl->ngroups; i++) {
+ if (!strcmp(npctl->groups[i].name, name))
+ return &npctl->groups[i];
+ }
+ return NULL;
+}
+
+static int ma35_pinctrl_dt_node_to_map_func(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map,
+ unsigned int *num_maps)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+ struct ma35_pin_group *grp;
+ struct pinctrl_map *new_map;
+ struct device_node *parent;
+ int map_num = 1;
+ int i;
+
+ /*
+ * first find the group of this node and check if we need create
+ * config maps for pins
+ */
+ grp = ma35_pinctrl_find_group_by_name(npctl, np->name);
+ if (!grp) {
+ dev_err(npctl->dev, "unable to find group for node %s\n", np->name);
+ return -EINVAL;
+ }
+
+ map_num += grp->npins;
+ new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), GFP_KERNEL);
+ if (!new_map)
+ return -ENOMEM;
+
+ *map = new_map;
+ *num_maps = map_num;
+ /* create mux map */
+ parent = of_get_parent(np);
+ if (!parent)
+ return -EINVAL;
+
+ new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+ new_map[0].data.mux.function = parent->name;
+ new_map[0].data.mux.group = np->name;
+ of_node_put(parent);
+
+ new_map++;
+ for (i = 0; i < grp->npins; i++) {
+ new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->pins[i]);
+ new_map[i].data.configs.configs = grp->settings[i].configs;
+ new_map[i].data.configs.num_configs = grp->settings[i].nconfigs;
+ }
+ dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+ (*map)->data.mux.function, (*map)->data.mux.group, map_num);
+
+ return 0;
+}
+
+static const struct pinctrl_ops ma35_pctrl_ops = {
+ .get_groups_count = ma35_get_groups_count,
+ .get_group_name = ma35_get_group_name,
+ .get_group_pins = ma35_get_group_pins,
+ .dt_node_to_map = ma35_pinctrl_dt_node_to_map_func,
+ .dt_free_map = pinconf_generic_dt_free_map,
+};
+
+static int ma35_pinmux_get_func_count(struct pinctrl_dev *pctldev)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return npctl->nfunctions;
+}
+
+static const char *ma35_pinmux_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return npctl->functions[selector].name;
+}
+
+static int ma35_pinmux_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ const char *const **groups,
+ unsigned int *const num_groups)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = npctl->functions[function].groups;
+ *num_groups = npctl->functions[function].ngroups;
+
+ return 0;
+}
+
+static int ma35_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
+ unsigned int group)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+ struct ma35_pin_group *grp = &npctl->groups[group];
+ struct ma35_pin_setting *setting = grp->settings;
+ u32 i, regval;
+
+ dev_dbg(npctl->dev, "enable function %s group %s\n",
+ npctl->functions[selector].name, npctl->groups[group].name);
+
+ for (i = 0; i < grp->npins; i++) {
+ regmap_read(npctl->regmap, setting->offset, ®val);
+ regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1,
+ setting->shift);
+ regval |= setting->muxval << setting->shift;
+ regmap_write(npctl->regmap, setting->offset, regval);
+ setting++;
+ }
+ return 0;
+}
+
+static const struct pinmux_ops ma35_pmx_ops = {
+ .get_functions_count = ma35_pinmux_get_func_count,
+ .get_function_name = ma35_pinmux_get_func_name,
+ .get_function_groups = ma35_pinmux_get_func_groups,
+ .set_mux = ma35_pinmux_set_mux,
+ .strict = true,
+};
+
+static void ma35_gpio_set_mode(void __iomem *reg_mode, unsigned int gpio, u32 mode)
+{
+ u32 regval = readl(reg_mode);
+
+ regval &= ~MA35_GP_MODE_MASK(gpio);
+ regval |= field_prep(MA35_GP_MODE_MASK(gpio), mode);
+
+ writel(regval, reg_mode);
+}
+
+static u32 ma35_gpio_get_mode(void __iomem *reg_mode, unsigned int gpio)
+{
+ u32 regval = readl(reg_mode);
+
+ return field_get(MA35_GP_MODE_MASK(gpio), regval);
+}
+
+static int ma35_gpio_core_direction_in(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+ void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
+
+ guard(raw_spinlock_irqsave)(&ma35_lock);
+
+ ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_INPUT);
+
+ return 0;
+}
+
+static int ma35_gpio_core_direction_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+ void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
+ void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
+ unsigned int regval;
+
+ guard(raw_spinlock_irqsave)(&ma35_lock);
+
+ regval = readl(reg_dout);
+ if (val)
+ regval |= BIT(gpio);
+ else
+ regval &= ~BIT(gpio);
+ writel(regval, reg_dout);
+
+ ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_OUTPUT);
+
+ return 0;
+}
+
+static int ma35_gpio_core_get(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+ void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN;
+
+ return !!(readl(reg_pin) & BIT(gpio));
+}
+
+static void ma35_gpio_core_set(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+ void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
+ u32 regval;
+
+ if (val)
+ regval = readl(reg_dout) | BIT(gpio);
+ else
+ regval = readl(reg_dout) & ~BIT(gpio);
+
+ writel(regval, reg_dout);
+}
+
+static int ma35_gpio_core_to_request(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(gc);
+ u32 reg_offs, bit_offs, regval;
+
+ if (gpio < 8) {
+ /* The MFP low register controls port 0 ~ 7 */
+ reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK;
+ bit_offs = gpio * MA35_MFP_BITS_PER_PORT;
+ } else {
+ /* The MFP high register controls port 8 ~ 15 */
+ reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK + 4;
+ bit_offs = (gpio - 8) * MA35_MFP_BITS_PER_PORT;
+ }
+
+ regmap_read(bank->regmap, MA35_MFP_REG_BASE + reg_offs, ®val);
+ regval &= ~GENMASK(bit_offs + MA35_MFP_BITS_PER_PORT - 1, bit_offs);
+ regmap_write(bank->regmap, MA35_MFP_REG_BASE + reg_offs, regval);
+
+ return 0;
+}
+
+static void ma35_irq_gpio_ack(struct irq_data *d)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ void __iomem *reg_intsrc = bank->reg_base + MA35_GP_REG_INTSRC;
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+
+ writel(BIT(hwirq), reg_intsrc);
+}
+
+static void ma35_irq_gpio_mask(struct irq_data *d)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+ u32 regval;
+
+ regval = readl(reg_ien);
+
+ regval &= ~MA35_GP_INTEN_BOTH(hwirq);
+
+ writel(regval, reg_ien);
+}
+
+static void ma35_irq_gpio_unmask(struct irq_data *d)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ void __iomem *reg_itype = bank->reg_base + MA35_GP_REG_INTTYPE;
+ void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+ u32 bval, regval;
+
+ bval = bank->irqtype & BIT(hwirq);
+ regval = readl(reg_itype);
+ regval &= ~BIT(hwirq);
+ writel(regval | bval, reg_itype);
+
+ bval = bank->irqinten & MA35_GP_INTEN_BOTH(hwirq);
+ regval = readl(reg_ien);
+ regval &= ~MA35_GP_INTEN_BOTH(hwirq);
+ writel(regval | bval, reg_ien);
+}
+
+static int ma35_irq_irqtype(struct irq_data *d, unsigned int type)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_BOTH:
+ irq_set_handler_locked(d, handle_edge_irq);
+ bank->irqtype &= ~BIT(hwirq);
+ bank->irqinten |= MA35_GP_INTEN_BOTH(hwirq);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ case IRQ_TYPE_LEVEL_HIGH:
+ irq_set_handler_locked(d, handle_edge_irq);
+ bank->irqtype &= ~BIT(hwirq);
+ bank->irqinten |= MA35_GP_INTEN_H(hwirq);
+ bank->irqinten &= ~MA35_GP_INTEN_L(hwirq);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ case IRQ_TYPE_LEVEL_LOW:
+ irq_set_handler_locked(d, handle_edge_irq);
+ bank->irqtype &= ~BIT(hwirq);
+ bank->irqinten |= MA35_GP_INTEN_L(hwirq);
+ bank->irqinten &= ~MA35_GP_INTEN_H(hwirq);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ writel(bank->irqtype, bank->reg_base + MA35_GP_REG_INTTYPE);
+ writel(bank->irqinten, bank->reg_base + MA35_GP_REG_INTEN);
+
+ return 0;
+}
+
+static struct irq_chip ma35_gpio_irqchip = {
+ .name = "MA35-GPIO-IRQ",
+ .irq_disable = ma35_irq_gpio_mask,
+ .irq_enable = ma35_irq_gpio_unmask,
+ .irq_ack = ma35_irq_gpio_ack,
+ .irq_mask = ma35_irq_gpio_mask,
+ .irq_unmask = ma35_irq_gpio_unmask,
+ .irq_set_type = ma35_irq_irqtype,
+ .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
+ GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static void ma35_irq_demux_intgroup(struct irq_desc *desc)
+{
+ struct ma35_pin_bank *bank = gpiochip_get_data(irq_desc_get_handler_data(desc));
+ struct irq_domain *irqdomain = bank->chip.irq.domain;
+ struct irq_chip *irqchip = irq_desc_get_chip(desc);
+ unsigned long isr;
+ int offset;
+
+ chained_irq_enter(irqchip, desc);
+
+ isr = readl(bank->reg_base + MA35_GP_REG_INTSRC);
+
+ for_each_set_bit(offset, &isr, bank->nr_pins)
+ generic_handle_irq(irq_find_mapping(irqdomain, offset));
+
+ chained_irq_exit(irqchip, desc);
+}
+
+static int ma35_gpiolib_register(struct platform_device *pdev, struct ma35_pinctrl *npctl)
+{
+ struct ma35_pin_ctrl *ctrl = npctl->ctrl;
+ struct ma35_pin_bank *bank = ctrl->pin_banks;
+ int ret;
+ int i;
+
+ for (i = 0; i < ctrl->nr_banks; i++, bank++) {
+ if (!bank->valid) {
+ dev_warn(&pdev->dev, "%pfw: bank is not valid\n", bank->fwnode);
+ continue;
+ }
+ bank->irqtype = 0;
+ bank->irqinten = 0;
+ bank->chip.label = bank->name;
+ bank->chip.of_gpio_n_cells = 2;
+ bank->chip.parent = &pdev->dev;
+ bank->chip.request = ma35_gpio_core_to_request;
+ bank->chip.direction_input = ma35_gpio_core_direction_in;
+ bank->chip.direction_output = ma35_gpio_core_direction_out;
+ bank->chip.get = ma35_gpio_core_get;
+ bank->chip.set = ma35_gpio_core_set;
+ bank->chip.base = -1;
+ bank->chip.ngpio = bank->nr_pins;
+ bank->chip.can_sleep = false;
+
+ if (bank->irq > 0) {
+ struct gpio_irq_chip *girq;
+
+ girq = &bank->chip.irq;
+ gpio_irq_chip_set_chip(girq, &ma35_gpio_irqchip);
+ girq->parent_handler = ma35_irq_demux_intgroup;
+ girq->num_parents = 1;
+
+ girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
+ sizeof(*girq->parents), GFP_KERNEL);
+ if (!girq->parents) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ girq->parents[0] = bank->irq;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_bad_irq;
+ }
+
+ ret = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
+ bank->chip.label, ret);
+ goto fail;
+ }
+ }
+ return 0;
+
+fail:
+ while (i--) {
+ bank--;
+ if (!bank->valid)
+ continue;
+ gpiochip_remove(&bank->chip);
+ }
+ return ret;
+}
+
+static int ma35_get_bank_data(struct ma35_pin_bank *bank)
+{
+ bank->reg_base = fwnode_iomap(bank->fwnode, 0);
+ if (IS_ERR(bank->reg_base))
+ return PTR_ERR(bank->reg_base);
+
+ bank->irq = fwnode_irq_get(bank->fwnode, 0);
+
+ bank->nr_pins = MA35_GPIO_PORT_MAX;
+
+ bank->clk = of_clk_get(to_of_node(bank->fwnode), 0);
+ if (IS_ERR(bank->clk))
+ return PTR_ERR(bank->clk);
+
+ return clk_prepare_enable(bank->clk);
+}
+
+static int ma35_pinctrl_get_soc_data(struct ma35_pinctrl *pctl, struct platform_device *pdev)
+{
+ struct fwnode_handle *child;
+ struct ma35_pin_ctrl *ctrl;
+ struct ma35_pin_bank *bank;
+ int i, id = 0;
+
+ ctrl = pctl->ctrl;
+ ctrl->nr_banks = MA35_GPIO_BANK_MAX;
+
+ ctrl->pin_banks = devm_kcalloc(&pdev->dev, ctrl->nr_banks,
+ sizeof(*ctrl->pin_banks), GFP_KERNEL);
+ if (!ctrl->pin_banks)
+ return -ENOMEM;
+
+ for (i = 0; i < ctrl->nr_banks; i++) {
+ ctrl->pin_banks[i].bank_num = i;
+ ctrl->pin_banks[i].name = gpio_group_name[i];
+ }
+
+ for_each_gpiochip_node(&pdev->dev, child) {
+ bank = &ctrl->pin_banks[id];
+ bank->fwnode = child;
+ bank->regmap = pctl->regmap;
+ bank->dev = &pdev->dev;
+ if (!ma35_get_bank_data(bank))
+ bank->valid = true;
+ id++;
+ }
+ return 0;
+}
+
+static void ma35_gpio_cla_port(unsigned int gpio_num, unsigned int *group,
+ unsigned int *num)
+{
+ *group = gpio_num / MA35_GPIO_PORT_MAX;
+ *num = gpio_num % MA35_GPIO_PORT_MAX;
+}
+
+static int ma35_pinconf_set_pull(struct ma35_pinctrl *npctl, unsigned int pin,
+ int pull_up)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval, pull_sel;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_PUSEL);
+ regval &= ~MA35_GP_PUSEL_MASK(port);
+
+ switch (pull_up) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ pull_sel = MA35_GP_PUSEL_PULL_UP;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ pull_sel = MA35_GP_PUSEL_PULL_DOWN;
+ break;
+
+ case PIN_CONFIG_BIAS_DISABLE:
+ pull_sel = MA35_GP_PUSEL_DISABLE;
+ break;
+ }
+
+ regval |= field_prep(MA35_GP_PUSEL_MASK(port), pull_sel);
+ writel(regval, base + MA35_GP_REG_PUSEL);
+
+ return 0;
+}
+
+static int ma35_pinconf_get_output(struct ma35_pinctrl *npctl, unsigned int pin)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 mode;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ mode = ma35_gpio_get_mode(base + MA35_GP_REG_MODE, port);
+ if (mode == MA35_GP_MODE_OUTPUT)
+ return 1;
+
+ return 0;
+}
+
+static int ma35_pinconf_get_pull(struct ma35_pinctrl *npctl, unsigned int pin)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval, pull_sel;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_PUSEL);
+
+ pull_sel = field_get(MA35_GP_PUSEL_MASK(port), regval);
+
+ switch (pull_sel) {
+ case MA35_GP_PUSEL_PULL_UP:
+ return PIN_CONFIG_BIAS_PULL_UP;
+
+ case MA35_GP_PUSEL_PULL_DOWN:
+ return PIN_CONFIG_BIAS_PULL_DOWN;
+
+ case MA35_GP_PUSEL_DISABLE:
+ return PIN_CONFIG_BIAS_DISABLE;
+ }
+
+ return PIN_CONFIG_BIAS_DISABLE;
+}
+
+static int ma35_pinconf_set_output(struct ma35_pinctrl *npctl, unsigned int pin, bool out)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ ma35_gpio_set_mode(base + MA35_GP_REG_MODE, port, MA35_GP_MODE_OUTPUT);
+
+ return 0;
+}
+
+static int ma35_pinconf_get_power_source(struct ma35_pinctrl *npctl, unsigned int pin)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_SPW);
+
+ if (regval & BIT(port))
+ return MVOLT_3300;
+ else
+ return MVOLT_1800;
+}
+
+static int ma35_pinconf_set_power_source(struct ma35_pinctrl *npctl,
+ unsigned int pin, int arg)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval;
+
+ if ((arg != MVOLT_1800) && (arg != MVOLT_3300))
+ return -EINVAL;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_SPW);
+
+ if (arg == MVOLT_1800)
+ regval &= ~BIT(port);
+ else
+ regval |= BIT(port);
+
+ writel(regval, base + MA35_GP_REG_SPW);
+
+ return 0;
+}
+
+static int ma35_pinconf_get_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin,
+ u32 *strength)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval, ds_val;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_DS_REG(port));
+ ds_val = field_get(MA35_GP_DS_MASK(port), regval);
+
+ if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800)
+ *strength = ds_1800mv_tbl[ds_val];
+ else
+ *strength = ds_3300mv_tbl[ds_val];
+
+ return 0;
+}
+
+static int ma35_pinconf_set_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin,
+ int strength)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ int i, ds_val = -1;
+ u32 regval;
+
+ if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800) {
+ for (i = 0; i < ARRAY_SIZE(ds_1800mv_tbl); i++) {
+ if (ds_1800mv_tbl[i] == strength) {
+ ds_val = i;
+ break;
+ }
+ }
+ } else {
+ for (i = 0; i < ARRAY_SIZE(ds_3300mv_tbl); i++) {
+ if (ds_3300mv_tbl[i] == strength) {
+ ds_val = i;
+ continue;
+ }
+ }
+ }
+ if (ds_val == -1)
+ return -EINVAL;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_DS_REG(port));
+ regval &= ~MA35_GP_DS_MASK(port);
+ regval |= field_prep(MA35_GP_DS_MASK(port), ds_val);
+
+ writel(regval, base + MA35_GP_DS_REG(port));
+
+ return 0;
+}
+
+static int ma35_pinconf_get_schmitt_enable(struct ma35_pinctrl *npctl, unsigned int pin)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_SMTEN);
+
+ return !!(regval & BIT(port));
+}
+
+static int ma35_pinconf_set_schmitt(struct ma35_pinctrl *npctl, unsigned int pin, int enable)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_SMTEN);
+
+ if (enable)
+ regval |= BIT(port);
+ else
+ regval &= ~BIT(port);
+
+ writel(regval, base + MA35_GP_REG_SMTEN);
+
+ return 0;
+}
+
+static int ma35_pinconf_get_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_SLEWCTL);
+
+ return field_get(MA35_GP_SLEWCTL_MASK(port), regval);
+}
+
+static int ma35_pinconf_set_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin, int rate)
+{
+ unsigned int port, group_num;
+ void __iomem *base;
+ u32 regval;
+
+ ma35_gpio_cla_port(pin, &group_num, &port);
+ base = npctl->ctrl->pin_banks[group_num].reg_base;
+
+ regval = readl(base + MA35_GP_REG_SLEWCTL);
+ regval &= ~MA35_GP_SLEWCTL_MASK(port);
+ regval |= field_prep(MA35_GP_SLEWCTL_MASK(port), rate);
+
+ writel(regval, base + MA35_GP_REG_SLEWCTL);
+
+ return 0;
+}
+
+static int ma35_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ u32 arg;
+ int ret;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (ma35_pinconf_get_pull(npctl, pin) != param)
+ return -EINVAL;
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ ret = ma35_pinconf_get_drive_strength(npctl, pin, &arg);
+ if (ret)
+ return ret;
+ break;
+
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ arg = ma35_pinconf_get_schmitt_enable(npctl, pin);
+ break;
+
+ case PIN_CONFIG_SLEW_RATE:
+ arg = ma35_pinconf_get_slew_rate(npctl, pin);
+ break;
+
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ arg = ma35_pinconf_get_output(npctl, pin);
+ break;
+
+ case PIN_CONFIG_POWER_SOURCE:
+ arg = ma35_pinconf_get_power_source(npctl, pin);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ *config = pinconf_to_config_packed(param, arg);
+
+ return 0;
+}
+
+static int ma35_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param;
+ unsigned int arg = 0;
+ int i, ret = 0;
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ ret = ma35_pinconf_set_pull(npctl, pin, param);
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ ret = ma35_pinconf_set_drive_strength(npctl, pin, arg);
+ break;
+
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ ret = ma35_pinconf_set_schmitt(npctl, pin, 1);
+ break;
+
+ case PIN_CONFIG_INPUT_SCHMITT:
+ ret = ma35_pinconf_set_schmitt(npctl, pin, arg);
+ break;
+
+ case PIN_CONFIG_SLEW_RATE:
+ ret = ma35_pinconf_set_slew_rate(npctl, pin, arg);
+ break;
+
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ ret = ma35_pinconf_set_output(npctl, pin, arg);
+ break;
+
+ case PIN_CONFIG_POWER_SOURCE:
+ ret = ma35_pinconf_set_power_source(npctl, pin, arg);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ if (ret)
+ break;
+ }
+ return ret;
+}
+
+static const struct pinconf_ops ma35_pinconf_ops = {
+ .pin_config_get = ma35_pinconf_get,
+ .pin_config_set = ma35_pinconf_set,
+ .is_generic = true,
+};
+
+static int ma35_pinctrl_parse_groups(struct device_node *np, struct ma35_pin_group *grp,
+ struct ma35_pinctrl *npctl, u32 index)
+{
+ struct ma35_pin_setting *pin;
+ unsigned long *configs;
+ unsigned int nconfigs;
+ int i, j, count, ret;
+ u32 *elems;
+
+ grp->name = np->name;
+
+ ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &nconfigs);
+ if (ret)
+ return ret;
+
+ count = of_property_count_elems_of_size(np, "nuvoton,pins", sizeof(u32));
+ if (!count || count % 3)
+ return -EINVAL;
+
+ elems = devm_kmalloc_array(npctl->dev, count, sizeof(u32), GFP_KERNEL);
+ if (!elems)
+ return -ENOMEM;
+
+ ret = of_property_read_u32_array(np, "nuvoton,pins", elems, count);
+ if (ret)
+ return -EINVAL;
+
+ grp->npins = count / 3;
+
+ grp->pins = devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
+ if (!grp->pins)
+ return -ENOMEM;
+
+ grp->settings = devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->settings), GFP_KERNEL);
+ if (!grp->settings)
+ return -ENOMEM;
+
+ pin = grp->settings;
+
+ for (i = 0, j = 0; i < count; i += 3, j++) {
+ pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE;
+ pin->shift = (elems[i + 1] * MA35_MFP_BITS_PER_PORT) % 32;
+ pin->muxval = elems[i + 2];
+ pin->configs = configs;
+ pin->nconfigs = nconfigs;
+ grp->pins[j] = npctl->info->get_pin_num(pin->offset, pin->shift);
+ pin++;
+ }
+ return 0;
+}
+
+static int ma35_pinctrl_parse_functions(struct device_node *np, struct ma35_pinctrl *npctl,
+ u32 index)
+{
+ struct device_node *child;
+ struct ma35_pin_func *func;
+ struct ma35_pin_group *grp;
+ static u32 grp_index;
+ u32 ret, i = 0;
+
+ dev_dbg(npctl->dev, "parse function(%d): %s\n", index, np->name);
+
+ func = &npctl->functions[index];
+ func->name = np->name;
+ func->ngroups = of_get_child_count(np);
+
+ if (func->ngroups <= 0)
+ return 0;
+
+ func->groups = devm_kcalloc(npctl->dev, func->ngroups, sizeof(char *), GFP_KERNEL);
+ if (!func->groups)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ func->groups[i] = child->name;
+ grp = &npctl->groups[grp_index++];
+ ret = ma35_pinctrl_parse_groups(child, grp, npctl, i++);
+ if (ret) {
+ of_node_put(child);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinctrl *npctl)
+{
+ struct fwnode_handle *child;
+ u32 idx = 0;
+ int ret;
+
+ device_for_each_child_node(&pdev->dev, child) {
+ if (fwnode_property_present(child, "gpio-controller"))
+ continue;
+ npctl->nfunctions++;
+ npctl->ngroups += of_get_child_count(to_of_node(child));
+ }
+
+ if (!npctl->nfunctions)
+ return -EINVAL;
+
+ npctl->functions = devm_kcalloc(&pdev->dev, npctl->nfunctions,
+ sizeof(*npctl->functions), GFP_KERNEL);
+ if (!npctl->functions)
+ return -ENOMEM;
+
+ npctl->groups = devm_kcalloc(&pdev->dev, npctl->ngroups,
+ sizeof(*npctl->groups), GFP_KERNEL);
+ if (!npctl->groups)
+ return -ENOMEM;
+
+ device_for_each_child_node(&pdev->dev, child) {
+ if (fwnode_property_present(child, "gpio-controller"))
+ continue;
+
+ ret = ma35_pinctrl_parse_functions(to_of_node(child), npctl, idx++);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to parse function\n");
+ return ret;
+ }
+ }
+ return 0;
+}
+
+int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_soc_info *info)
+{
+ struct pinctrl_desc *ma35_pinctrl_desc;
+ struct device *dev = &pdev->dev;
+ struct ma35_pinctrl *npctl;
+ int ret;
+
+ if (!info || !info->pins || !info->npins) {
+ dev_err(&pdev->dev, "wrong pinctrl info\n");
+ return -EINVAL;
+ }
+
+ npctl = devm_kzalloc(&pdev->dev, sizeof(*npctl), GFP_KERNEL);
+ if (!npctl)
+ return -ENOMEM;
+
+ ma35_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ma35_pinctrl_desc), GFP_KERNEL);
+ if (!ma35_pinctrl_desc)
+ return -ENOMEM;
+
+ npctl->ctrl = devm_kzalloc(&pdev->dev, sizeof(*npctl->ctrl), GFP_KERNEL);
+ if (!npctl->ctrl)
+ return -ENOMEM;
+
+ ma35_pinctrl_desc->name = dev_name(&pdev->dev);
+ ma35_pinctrl_desc->pins = info->pins;
+ ma35_pinctrl_desc->npins = info->npins;
+ ma35_pinctrl_desc->pctlops = &ma35_pctrl_ops;
+ ma35_pinctrl_desc->pmxops = &ma35_pmx_ops;
+ ma35_pinctrl_desc->confops = &ma35_pinconf_ops;
+ ma35_pinctrl_desc->owner = THIS_MODULE;
+
+ npctl->info = info;
+ npctl->dev = &pdev->dev;
+
+ npctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "nuvoton,sys");
+ if (IS_ERR(npctl->regmap))
+ return dev_err_probe(&pdev->dev, PTR_ERR(npctl->regmap),
+ "No syscfg phandle specified\n");
+
+ ret = ma35_pinctrl_get_soc_data(npctl, pdev);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "fail to get soc data\n");
+
+ platform_set_drvdata(pdev, npctl);
+
+ ret = ma35_pinctrl_probe_dt(pdev, npctl);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "fail to probe MA35 pinctrl dt\n");
+
+ ret = devm_pinctrl_register_and_init(dev, ma35_pinctrl_desc, npctl, &npctl->pctl);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "fail to register MA35 pinctrl\n");
+
+ ret = pinctrl_enable(npctl->pctl);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "fail to enable MA35 pinctrl\n");
+
+ return ma35_gpiolib_register(pdev, npctl);
+}
+
+int ma35_pinctrl_suspend(struct device *dev)
+{
+ struct ma35_pinctrl *npctl = dev_get_drvdata(dev);
+
+ return pinctrl_force_sleep(npctl->pctl);
+}
+
+int ma35_pinctrl_resume(struct device *dev)
+{
+ struct ma35_pinctrl *npctl = dev_get_drvdata(dev);
+
+ return pinctrl_force_default(npctl->pctl);
+}
diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.h b/drivers/pinctrl/nuvoton/pinctrl-ma35.h
new file mode 100644
index 000000000000..218084100541
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Nuvoton Technology Corp.
+ *
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ * * Jacky Huang <ychuang3@nuvoton.com>
+ */
+#ifndef __PINCTRL_MA35_H
+#define __PINCTRL_MA35_H
+
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+
+struct ma35_mux_desc {
+ const char *name;
+ u32 muxval;
+};
+
+struct ma35_pin_data {
+ u32 offset;
+ u32 shift;
+ struct ma35_mux_desc *muxes;
+};
+
+struct ma35_pinctrl_soc_info {
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ int (*get_pin_num)(int offset, int shift);
+};
+
+#define MA35_PIN(num, n, o, s, ...) { \
+ .number = num, \
+ .name = #n, \
+ .drv_data = &(struct ma35_pin_data) { \
+ .offset = o, \
+ .shift = s, \
+ .muxes = (struct ma35_mux_desc[]) { \
+ __VA_ARGS__, { } }, \
+ }, \
+}
+
+#define MA35_MUX(_val, _name) { \
+ .name = _name, \
+ .muxval = _val, \
+}
+
+int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_soc_info *info);
+int ma35_pinctrl_suspend(struct device *dev);
+int ma35_pinctrl_resume(struct device *dev);
+
+#endif /* __PINCTRL_MA35_H */
diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c b/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
new file mode 100644
index 000000000000..8bb9a5a35954
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
@@ -0,0 +1,1799 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Nuvoton Technology Corp.
+ *
+ * Author: Shan-Chun Hung <schung@nuvoton.com>
+ * * Jacky Huang <ychuang3@nuvoton.com>
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-ma35.h"
+
+static const struct pinctrl_pin_desc ma35d1_pins[] = {
+ MA35_PIN(0, PA0, 0x80, 0x0,
+ MA35_MUX(0x0, "GPA0"),
+ MA35_MUX(0x2, "UART1_nCTS"),
+ MA35_MUX(0x3, "UART16_RXD"),
+ MA35_MUX(0x6, "NAND_DATA0"),
+ MA35_MUX(0x7, "EBI_AD0"),
+ MA35_MUX(0x9, "EBI_ADR0")),
+ MA35_PIN(1, PA1, 0x80, 0x4,
+ MA35_MUX(0x0, "GPA1"),
+ MA35_MUX(0x2, "UART1_nRTS"),
+ MA35_MUX(0x3, "UART16_TXD"),
+ MA35_MUX(0x6, "NAND_DATA1"),
+ MA35_MUX(0x7, "EBI_AD1"),
+ MA35_MUX(0x9, "EBI_ADR1")),
+ MA35_PIN(2, PA2, 0x80, 0x8,
+ MA35_MUX(0x0, "GPA2"),
+ MA35_MUX(0x2, "UART1_RXD"),
+ MA35_MUX(0x6, "NAND_DATA2"),
+ MA35_MUX(0x7, "EBI_AD2"),
+ MA35_MUX(0x9, "EBI_ADR2")),
+ MA35_PIN(3, PA3, 0x80, 0xc,
+ MA35_MUX(0x0, "GPA3"),
+ MA35_MUX(0x2, "UART1_TXD"),
+ MA35_MUX(0x6, "NAND_DATA3"),
+ MA35_MUX(0x7, "EBI_AD3"),
+ MA35_MUX(0x9, "EBI_ADR3")),
+ MA35_PIN(4, PA4, 0x80, 0x10,
+ MA35_MUX(0x0, "GPA4"),
+ MA35_MUX(0x2, "UART3_nCTS"),
+ MA35_MUX(0x3, "UART2_RXD"),
+ MA35_MUX(0x6, "NAND_DATA4"),
+ MA35_MUX(0x7, "EBI_AD4"),
+ MA35_MUX(0x9, "EBI_ADR4")),
+ MA35_PIN(5, PA5, 0x80, 0x14,
+ MA35_MUX(0x0, "GPA5"),
+ MA35_MUX(0x2, "UART3_nRTS"),
+ MA35_MUX(0x3, "UART2_TXD"),
+ MA35_MUX(0x6, "NAND_DATA5"),
+ MA35_MUX(0x7, "EBI_AD5"),
+ MA35_MUX(0x9, "EBI_ADR5")),
+ MA35_PIN(6, PA6, 0x80, 0x18,
+ MA35_MUX(0x0, "GPA6"),
+ MA35_MUX(0x2, "UART3_RXD"),
+ MA35_MUX(0x6, "NAND_DATA6"),
+ MA35_MUX(0x7, "EBI_AD6"),
+ MA35_MUX(0x9, "EBI_ADR6")),
+ MA35_PIN(7, PA7, 0x80, 0x1c,
+ MA35_MUX(0x0, "GPA7"),
+ MA35_MUX(0x2, "UART3_TXD"),
+ MA35_MUX(0x6, "NAND_DATA7"),
+ MA35_MUX(0x7, "EBI_AD7"),
+ MA35_MUX(0x9, "EBI_ADR7")),
+ MA35_PIN(8, PA8, 0x84, 0x0,
+ MA35_MUX(0x0, "GPA8"),
+ MA35_MUX(0x2, "UART5_nCTS"),
+ MA35_MUX(0x3, "UART4_RXD"),
+ MA35_MUX(0x6, "NAND_RDY0"),
+ MA35_MUX(0x7, "EBI_AD8"),
+ MA35_MUX(0x9, "EBI_ADR8")),
+ MA35_PIN(9, PA9, 0x84, 0x4,
+ MA35_MUX(0x0, "GPA9"),
+ MA35_MUX(0x2, "UART5_nRTS"),
+ MA35_MUX(0x3, "UART4_TXD"),
+ MA35_MUX(0x6, "NAND_nRE"),
+ MA35_MUX(0x7, "EBI_AD9"),
+ MA35_MUX(0x9, "EBI_ADR9")),
+ MA35_PIN(10, PA10, 0x84, 0x8,
+ MA35_MUX(0x0, "GPA10"),
+ MA35_MUX(0x2, "UART5_RXD"),
+ MA35_MUX(0x6, "NAND_nWE"),
+ MA35_MUX(0x7, "EBI_AD10"),
+ MA35_MUX(0x9, "EBI_ADR10")),
+ MA35_PIN(11, PA11, 0x84, 0xc,
+ MA35_MUX(0x0, "GPA11"),
+ MA35_MUX(0x2, "UART5_TXD"),
+ MA35_MUX(0x6, "NAND_CLE"),
+ MA35_MUX(0x7, "EBI_AD11"),
+ MA35_MUX(0x9, "EBI_ADR11")),
+ MA35_PIN(12, PA12, 0x84, 0x10,
+ MA35_MUX(0x0, "GPA12"),
+ MA35_MUX(0x2, "UART7_nCTS"),
+ MA35_MUX(0x3, "UART8_RXD"),
+ MA35_MUX(0x6, "NAND_ALE"),
+ MA35_MUX(0x7, "EBI_AD12"),
+ MA35_MUX(0x9, "EBI_ADR12")),
+ MA35_PIN(13, PA13, 0x84, 0x14,
+ MA35_MUX(0x0, "GPA13"),
+ MA35_MUX(0x2, "UART7_nRTS"),
+ MA35_MUX(0x3, "UART8_TXD"),
+ MA35_MUX(0x6, "NAND_nCS0"),
+ MA35_MUX(0x7, "EBI_AD13"),
+ MA35_MUX(0x9, "EBI_ADR13")),
+ MA35_PIN(14, PA14, 0x84, 0x18,
+ MA35_MUX(0x0, "GPA14"),
+ MA35_MUX(0x2, "UART7_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x6, "NAND_nWP"),
+ MA35_MUX(0x7, "EBI_AD14"),
+ MA35_MUX(0x9, "EBI_ADR14")),
+ MA35_PIN(15, PA15, 0x84, 0x1c,
+ MA35_MUX(0x0, "GPA15"),
+ MA35_MUX(0x1, "EPWM0_CH2"),
+ MA35_MUX(0x2, "UART9_nCTS"),
+ MA35_MUX(0x3, "UART6_RXD"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x5, "CAN2_RXD"),
+ MA35_MUX(0x7, "EBI_ALE"),
+ MA35_MUX(0x9, "QEI0_A"),
+ MA35_MUX(0xb, "TM1"),
+ MA35_MUX(0xe, "RGMII0_PPS"),
+ MA35_MUX(0xf, "RMII0_PPS")),
+ MA35_PIN(16, PB0, 0x88, 0x0,
+ MA35_MUX(0x0, "GPB0"),
+ MA35_MUX(0x8, "EADC0_CH0")),
+ MA35_PIN(17, PB1, 0x88, 0x4,
+ MA35_MUX(0x0, "GPB1"),
+ MA35_MUX(0x8, "EADC0_CH1")),
+ MA35_PIN(18, PB2, 0x88, 0x8,
+ MA35_MUX(0x0, "GPB2"),
+ MA35_MUX(0x8, "EADC0_CH2")),
+ MA35_PIN(19, PB3, 0x88, 0xc,
+ MA35_MUX(0x0, "GPB3"),
+ MA35_MUX(0x8, "EADC0_CH3")),
+ MA35_PIN(20, PB4, 0x88, 0x10,
+ MA35_MUX(0x0, "GPB4"),
+ MA35_MUX(0x8, "EADC0_CH4")),
+ MA35_PIN(21, PB5, 0x88, 0x14,
+ MA35_MUX(0x0, "GPB5"),
+ MA35_MUX(0x8, "EADC0_CH5")),
+ MA35_PIN(22, PB6, 0x88, 0x18,
+ MA35_MUX(0x0, "GPB6"),
+ MA35_MUX(0x8, "EADC0_CH6")),
+ MA35_PIN(23, PB7, 0x88, 0x1c,
+ MA35_MUX(0x0, "GPB7"),
+ MA35_MUX(0x8, "EADC0_CH7")),
+ MA35_PIN(24, PB8, 0x8c, 0x0,
+ MA35_MUX(0x0, "GPB8"),
+ MA35_MUX(0x1, "EPWM2_BRAKE0"),
+ MA35_MUX(0x2, "UART2_nCTS"),
+ MA35_MUX(0x3, "UART1_RXD"),
+ MA35_MUX(0x4, "I2C2_SDA"),
+ MA35_MUX(0x5, "SPI0_SS1"),
+ MA35_MUX(0x6, "SPI0_I2SMCLK"),
+ MA35_MUX(0x8, "ADC0_CH0"),
+ MA35_MUX(0x9, "EBI_nCS0"),
+ MA35_MUX(0xb, "TM4"),
+ MA35_MUX(0xe, "QEI2_INDEX"),
+ MA35_MUX(0xf, "KPI_ROW6")),
+ MA35_PIN(25, PB9, 0x8c, 0x4,
+ MA35_MUX(0x0, "GPB9"),
+ MA35_MUX(0x1, "EPWM2_CH4"),
+ MA35_MUX(0x2, "UART2_nRTS"),
+ MA35_MUX(0x3, "UART1_TXD"),
+ MA35_MUX(0x4, "I2C2_SCL"),
+ MA35_MUX(0x5, "SPI0_CLK"),
+ MA35_MUX(0x6, "I2S0_MCLK"),
+ MA35_MUX(0x7, "CCAP1_HSYNC"),
+ MA35_MUX(0x8, "ADC0_CH1"),
+ MA35_MUX(0x9, "EBI_ALE"),
+ MA35_MUX(0xa, "EBI_AD13"),
+ MA35_MUX(0xb, "TM0_EXT"),
+ MA35_MUX(0xc, "I2S1_MCLK"),
+ MA35_MUX(0xd, "SC0_nCD"),
+ MA35_MUX(0xe, "QEI2_A"),
+ MA35_MUX(0xf, "KPI_ROW7")),
+ MA35_PIN(26, PB10, 0x8c, 0x8,
+ MA35_MUX(0x0, "GPB10"),
+ MA35_MUX(0x1, "EPWM2_CH5"),
+ MA35_MUX(0x2, "UART2_RXD"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x5, "SPI0_MOSI"),
+ MA35_MUX(0x6, "EBI_MCLK"),
+ MA35_MUX(0x7, "CCAP1_VSYNC"),
+ MA35_MUX(0x8, "ADC0_CH2"),
+ MA35_MUX(0x9, "EBI_ADR15"),
+ MA35_MUX(0xa, "EBI_AD14"),
+ MA35_MUX(0xb, "TM5"),
+ MA35_MUX(0xc, "I2C1_SDA"),
+ MA35_MUX(0xd, "INT1"),
+ MA35_MUX(0xe, "QEI2_B")),
+ MA35_PIN(27, PB11, 0x8c, 0xc,
+ MA35_MUX(0x0, "GPB11"),
+ MA35_MUX(0x1, "EPWM2_BRAKE1"),
+ MA35_MUX(0x2, "UART2_TXD"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x5, "SPI0_MISO"),
+ MA35_MUX(0x6, "I2S1_MCLK"),
+ MA35_MUX(0x7, "CCAP1_SFIELD"),
+ MA35_MUX(0x8, "ADC0_CH3"),
+ MA35_MUX(0x9, "EBI_nCS2"),
+ MA35_MUX(0xa, "EBI_ALE"),
+ MA35_MUX(0xb, "TM5_EXT"),
+ MA35_MUX(0xc, "I2C1_SCL"),
+ MA35_MUX(0xd, "INT2"),
+ MA35_MUX(0xe, "QEI2_INDEX")),
+ MA35_PIN(28, PB12, 0x8c, 0x10,
+ MA35_MUX(0x0, "GPB12"),
+ MA35_MUX(0x1, "EPWM2_CH0"),
+ MA35_MUX(0x2, "UART4_nCTS"),
+ MA35_MUX(0x3, "UART3_RXD"),
+ MA35_MUX(0x4, "I2C3_SDA"),
+ MA35_MUX(0x5, "CAN2_RXD"),
+ MA35_MUX(0x6, "I2S1_LRCK"),
+ MA35_MUX(0x8, "ADC0_CH4"),
+ MA35_MUX(0x9, "EBI_ADR16"),
+ MA35_MUX(0xe, "ECAP2_IC0")),
+ MA35_PIN(29, PB13, 0x8c, 0x14,
+ MA35_MUX(0x0, "GPB13"),
+ MA35_MUX(0x1, "EPWM2_CH1"),
+ MA35_MUX(0x2, "UART4_nRTS"),
+ MA35_MUX(0x3, "UART3_TXD"),
+ MA35_MUX(0x4, "I2C3_SCL"),
+ MA35_MUX(0x5, "CAN2_TXD"),
+ MA35_MUX(0x6, "I2S1_BCLK"),
+ MA35_MUX(0x8, "ADC0_CH5"),
+ MA35_MUX(0x9, "EBI_ADR17"),
+ MA35_MUX(0xe, "ECAP2_IC1")),
+ MA35_PIN(30, PB14, 0x8c, 0x18,
+ MA35_MUX(0x0, "GPB14"),
+ MA35_MUX(0x1, "EPWM2_CH2"),
+ MA35_MUX(0x2, "UART4_RXD"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x5, "I2C4_SDA"),
+ MA35_MUX(0x6, "I2S1_DI"),
+ MA35_MUX(0x8, "ADC0_CH6"),
+ MA35_MUX(0x9, "EBI_ADR18"),
+ MA35_MUX(0xe, "ECAP2_IC2")),
+ MA35_PIN(31, PB15, 0x8c, 0x1c,
+ MA35_MUX(0x0, "GPB15"),
+ MA35_MUX(0x1, "EPWM2_CH3"),
+ MA35_MUX(0x2, "UART4_TXD"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x5, "I2C4_SCL"),
+ MA35_MUX(0x6, "I2S1_DO"),
+ MA35_MUX(0x8, "ADC0_CH7"),
+ MA35_MUX(0x9, "EBI_ADR19")),
+ MA35_PIN(32, PC0, 0x90, 0x0,
+ MA35_MUX(0x0, "GPC0"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x6, "SD0_CMD/eMMC0_CMD")),
+ MA35_PIN(33, PC1, 0x90, 0x4,
+ MA35_MUX(0x0, "GPC1"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x6, "SD0_CLK/eMMC0_CLK")),
+ MA35_PIN(34, PC2, 0x90, 0x8,
+ MA35_MUX(0x0, "GPC2"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x6, "SD0_DAT0/eMMC0_DAT0")),
+ MA35_PIN(35, PC3, 0x90, 0xc,
+ MA35_MUX(0x0, "GPC3"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x6, "SD0_DAT1/eMMC0_DAT1")),
+ MA35_PIN(36, PC4, 0x90, 0x10,
+ MA35_MUX(0x0, "GPC4"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x6, "SD0_DAT2/eMMC0_DAT2")),
+ MA35_PIN(37, PC5, 0x90, 0x14,
+ MA35_MUX(0x0, "GPC5"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x6, "SD0_DAT3/eMMC0_DAT3")),
+ MA35_PIN(38, PC6, 0x90, 0x18,
+ MA35_MUX(0x0, "GPC6"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x6, "SD0_nCD")),
+ MA35_PIN(39, PC7, 0x90, 0x1c,
+ MA35_MUX(0x0, "GPC7"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x6, "SD0_WP")),
+ MA35_PIN(40, PC12, 0x94, 0x10,
+ MA35_MUX(0x0, "GPC12"),
+ MA35_MUX(0x2, "UART12_nCTS"),
+ MA35_MUX(0x3, "UART11_RXD"),
+ MA35_MUX(0x6, "LCM_DATA16")),
+ MA35_PIN(41, PC13, 0x94, 0x14,
+ MA35_MUX(0x0, "GPC13"),
+ MA35_MUX(0x2, "UART12_nRTS"),
+ MA35_MUX(0x3, "UART11_TXD"),
+ MA35_MUX(0x6, "LCM_DATA17")),
+ MA35_PIN(42, PC14, 0x94, 0x18,
+ MA35_MUX(0x0, "GPC14"),
+ MA35_MUX(0x2, "UART12_RXD"),
+ MA35_MUX(0x6, "LCM_DATA18")),
+ MA35_PIN(43, PC15, 0x94, 0x1c,
+ MA35_MUX(0x0, "GPC15"),
+ MA35_MUX(0x2, "UART12_TXD"),
+ MA35_MUX(0x6, "LCM_DATA19"),
+ MA35_MUX(0x7, "LCM_MPU_TE"),
+ MA35_MUX(0x8, "LCM_MPU_VSYNC")),
+ MA35_PIN(44, PD0, 0x98, 0x0,
+ MA35_MUX(0x0, "GPD0"),
+ MA35_MUX(0x2, "UART3_nCTS"),
+ MA35_MUX(0x3, "UART4_RXD"),
+ MA35_MUX(0x5, "QSPI0_SS0")),
+ MA35_PIN(45, PD1, 0x98, 0x4,
+ MA35_MUX(0x0, "GPD1"),
+ MA35_MUX(0x2, "UART3_nRTS"),
+ MA35_MUX(0x3, "UART4_TXD"),
+ MA35_MUX(0x5, "QSPI0_CLK")),
+ MA35_PIN(46, PD2, 0x98, 0x8,
+ MA35_MUX(0x0, "GPD2"),
+ MA35_MUX(0x2, "UART3_RXD"),
+ MA35_MUX(0x5, "QSPI0_MOSI0")),
+ MA35_PIN(47, PD3, 0x98, 0xc,
+ MA35_MUX(0x0, "GPD3"),
+ MA35_MUX(0x2, "UART3_TXD"),
+ MA35_MUX(0x5, "QSPI0_MISO0")),
+ MA35_PIN(48, PD4, 0x98, 0x10,
+ MA35_MUX(0x0, "GPD4"),
+ MA35_MUX(0x2, "UART1_nCTS"),
+ MA35_MUX(0x3, "UART2_RXD"),
+ MA35_MUX(0x4, "I2C2_SDA"),
+ MA35_MUX(0x5, "QSPI0_MOSI1")),
+ MA35_PIN(49, PD5, 0x98, 0x14,
+ MA35_MUX(0x0, "GPD5"),
+ MA35_MUX(0x2, "UART1_nRTS"),
+ MA35_MUX(0x3, "UART2_TXD"),
+ MA35_MUX(0x4, "I2C2_SCL"),
+ MA35_MUX(0x5, "QSPI0_MISO1")),
+ MA35_PIN(50, PD6, 0x98, 0x18,
+ MA35_MUX(0x0, "GPD6"),
+ MA35_MUX(0x1, "EPWM0_SYNC_IN"),
+ MA35_MUX(0x2, "UART1_RXD"),
+ MA35_MUX(0x5, "QSPI1_MOSI1"),
+ MA35_MUX(0x6, "I2C0_SDA"),
+ MA35_MUX(0x7, "I2S0_MCLK"),
+ MA35_MUX(0x8, "EPWM0_CH0"),
+ MA35_MUX(0x9, "EBI_AD5"),
+ MA35_MUX(0xa, "SPI3_SS1"),
+ MA35_MUX(0xb, "TRACE_CLK")),
+ MA35_PIN(51, PD7, 0x98, 0x1c,
+ MA35_MUX(0x0, "GPD7"),
+ MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
+ MA35_MUX(0x2, "UART1_TXD"),
+ MA35_MUX(0x5, "QSPI1_MISO1"),
+ MA35_MUX(0x6, "I2C0_SCL"),
+ MA35_MUX(0x7, "I2S1_MCLK"),
+ MA35_MUX(0x8, "EPWM0_CH1"),
+ MA35_MUX(0x9, "EBI_AD6"),
+ MA35_MUX(0xa, "SC1_nCD"),
+ MA35_MUX(0xb, "EADC0_ST")),
+ MA35_PIN(52, PD8, 0x9c, 0x0,
+ MA35_MUX(0x0, "GPD8"),
+ MA35_MUX(0x1, "EPWM0_BRAKE0"),
+ MA35_MUX(0x2, "UART16_nCTS"),
+ MA35_MUX(0x3, "UART15_RXD"),
+ MA35_MUX(0x5, "QSPI1_SS0"),
+ MA35_MUX(0x7, "I2S1_LRCK"),
+ MA35_MUX(0x8, "EPWM0_CH2"),
+ MA35_MUX(0x9, "EBI_AD7"),
+ MA35_MUX(0xa, "SC1_CLK"),
+ MA35_MUX(0xb, "TM0")),
+ MA35_PIN(53, PD9, 0x9c, 0x4,
+ MA35_MUX(0x0, "GPD9"),
+ MA35_MUX(0x1, "EPWM0_BRAKE1"),
+ MA35_MUX(0x2, "UART16_nRTS"),
+ MA35_MUX(0x3, "UART15_TXD"),
+ MA35_MUX(0x5, "QSPI1_CLK"),
+ MA35_MUX(0x7, "I2S1_BCLK"),
+ MA35_MUX(0x8, "EPWM0_CH3"),
+ MA35_MUX(0x9, "EBI_AD8"),
+ MA35_MUX(0xa, "SC1_DAT"),
+ MA35_MUX(0xb, "TM0_EXT")),
+ MA35_PIN(54, PD10, 0x9c, 0x8,
+ MA35_MUX(0x0, "GPD10"),
+ MA35_MUX(0x1, "EPWM1_BRAKE0"),
+ MA35_MUX(0x2, "UART16_RXD"),
+ MA35_MUX(0x5, "QSPI1_MOSI0"),
+ MA35_MUX(0x7, "I2S1_DI"),
+ MA35_MUX(0x8, "EPWM0_CH4"),
+ MA35_MUX(0x9, "EBI_AD9"),
+ MA35_MUX(0xa, "SC1_RST"),
+ MA35_MUX(0xb, "TM2")),
+ MA35_PIN(55, PD11, 0x9c, 0xc,
+ MA35_MUX(0x0, "GPD11"),
+ MA35_MUX(0x1, "EPWM1_BRAKE1"),
+ MA35_MUX(0x2, "UART16_TXD"),
+ MA35_MUX(0x5, "QSPI1_MISO0"),
+ MA35_MUX(0x7, "I2S1_DO"),
+ MA35_MUX(0x8, "EPWM0_CH5"),
+ MA35_MUX(0x9, "EBI_AD10"),
+ MA35_MUX(0xa, "SC1_PWR"),
+ MA35_MUX(0xb, "TM2_EXT")),
+ MA35_PIN(56, PD12, 0x9c, 0x10,
+ MA35_MUX(0x0, "GPD12"),
+ MA35_MUX(0x1, "EPWM0_BRAKE0"),
+ MA35_MUX(0x2, "UART11_TXD"),
+ MA35_MUX(0x3, "UART10_RXD"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x6, "TRACE_DATA0"),
+ MA35_MUX(0x7, "EBI_nCS1"),
+ MA35_MUX(0x8, "EBI_AD4"),
+ MA35_MUX(0x9, "QEI0_INDEX"),
+ MA35_MUX(0xb, "TM5"),
+ MA35_MUX(0xc, "I2S1_LRCK"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(57, PD13, 0x9c, 0x14,
+ MA35_MUX(0x0, "GPD13"),
+ MA35_MUX(0x1, "EPWM0_BRAKE1"),
+ MA35_MUX(0x2, "UART11_RXD"),
+ MA35_MUX(0x3, "UART10_TXD"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x6, "TRACE_DATA1"),
+ MA35_MUX(0x7, "EBI_nCS2"),
+ MA35_MUX(0x8, "EBI_AD5"),
+ MA35_MUX(0x9, "ECAP0_IC0"),
+ MA35_MUX(0xb, "TM5_EXT"),
+ MA35_MUX(0xc, "I2S1_BCLK")),
+ MA35_PIN(58, PD14, 0x9c, 0x18,
+ MA35_MUX(0x0, "GPD14"),
+ MA35_MUX(0x1, "EPWM0_SYNC_IN"),
+ MA35_MUX(0x2, "UART11_nCTS"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x6, "TRACE_DATA2"),
+ MA35_MUX(0x7, "EBI_MCLK"),
+ MA35_MUX(0x8, "EBI_AD6"),
+ MA35_MUX(0x9, "ECAP0_IC1"),
+ MA35_MUX(0xb, "TM6"),
+ MA35_MUX(0xc, "I2S1_DI"),
+ MA35_MUX(0xd, "INT3")),
+ MA35_PIN(59, PD15, 0x9c, 0x1c,
+ MA35_MUX(0x0, "GPD15"),
+ MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
+ MA35_MUX(0x2, "UART11_nRTS"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x6, "TRACE_DATA3"),
+ MA35_MUX(0x7, "EBI_ALE"),
+ MA35_MUX(0x8, "EBI_AD7"),
+ MA35_MUX(0x9, "ECAP0_IC2"),
+ MA35_MUX(0xb, "TM6_EXT"),
+ MA35_MUX(0xc, "I2S1_DO")),
+ MA35_PIN(60, PE0, 0xa0, 0x0,
+ MA35_MUX(0x0, "GPE0"),
+ MA35_MUX(0x2, "UART9_nCTS"),
+ MA35_MUX(0x3, "UART8_RXD"),
+ MA35_MUX(0x7, "CCAP1_DATA0"),
+ MA35_MUX(0x8, "RGMII0_MDC"),
+ MA35_MUX(0x9, "RMII0_MDC")),
+ MA35_PIN(61, PE1, 0xa0, 0x4,
+ MA35_MUX(0x0, "GPE1"),
+ MA35_MUX(0x2, "UART9_nRTS"),
+ MA35_MUX(0x3, "UART8_TXD"),
+ MA35_MUX(0x7, "CCAP1_DATA1"),
+ MA35_MUX(0x8, "RGMII0_MDIO"),
+ MA35_MUX(0x9, "RMII0_MDIO")),
+ MA35_PIN(62, PE2, 0xa0, 0x8,
+ MA35_MUX(0x0, "GPE2"),
+ MA35_MUX(0x2, "UART9_RXD"),
+ MA35_MUX(0x7, "CCAP1_DATA2"),
+ MA35_MUX(0x8, "RGMII0_TXCTL"),
+ MA35_MUX(0x9, "RMII0_TXEN")),
+ MA35_PIN(63, PE3, 0xa0, 0xc,
+ MA35_MUX(0x0, "GPE3"),
+ MA35_MUX(0x2, "UART9_TXD"),
+ MA35_MUX(0x7, "CCAP1_DATA3"),
+ MA35_MUX(0x8, "RGMII0_TXD0"),
+ MA35_MUX(0x9, "RMII0_TXD0")),
+ MA35_PIN(64, PE4, 0xa0, 0x10,
+ MA35_MUX(0x0, "GPE4"),
+ MA35_MUX(0x2, "UART4_nCTS"),
+ MA35_MUX(0x3, "UART3_RXD"),
+ MA35_MUX(0x7, "CCAP1_DATA4"),
+ MA35_MUX(0x8, "RGMII0_TXD1"),
+ MA35_MUX(0x9, "RMII0_TXD1")),
+ MA35_PIN(65, PE5, 0xa0, 0x14,
+ MA35_MUX(0x0, "GPE5"),
+ MA35_MUX(0x2, "UART4_nRTS"),
+ MA35_MUX(0x3, "UART3_TXD"),
+ MA35_MUX(0x7, "CCAP1_DATA5"),
+ MA35_MUX(0x8, "RGMII0_RXCLK"),
+ MA35_MUX(0x9, "RMII0_REFCLK")),
+ MA35_PIN(66, PE6, 0xa0, 0x18,
+ MA35_MUX(0x0, "GPE6"),
+ MA35_MUX(0x2, "UART4_RXD"),
+ MA35_MUX(0x7, "CCAP1_DATA6"),
+ MA35_MUX(0x8, "RGMII0_RXCTL"),
+ MA35_MUX(0x9, "RMII0_CRSDV")),
+ MA35_PIN(67, PE7, 0xa0, 0x1c,
+ MA35_MUX(0x0, "GPE7"),
+ MA35_MUX(0x2, "UART4_TXD"),
+ MA35_MUX(0x7, "CCAP1_DATA7"),
+ MA35_MUX(0x8, "RGMII0_RXD0"),
+ MA35_MUX(0x9, "RMII0_RXD0")),
+ MA35_PIN(68, PE8, 0xa4, 0x0,
+ MA35_MUX(0x0, "GPE8"),
+ MA35_MUX(0x2, "UART13_nCTS"),
+ MA35_MUX(0x3, "UART12_RXD"),
+ MA35_MUX(0x7, "CCAP1_SCLK"),
+ MA35_MUX(0x8, "RGMII0_RXD1"),
+ MA35_MUX(0x9, "RMII0_RXD1")),
+ MA35_PIN(69, PE9, 0xa4, 0x4,
+ MA35_MUX(0x0, "GPE9"),
+ MA35_MUX(0x2, "UART13_nRTS"),
+ MA35_MUX(0x3, "UART12_TXD"),
+ MA35_MUX(0x7, "CCAP1_PIXCLK"),
+ MA35_MUX(0x8, "RGMII0_RXD2"),
+ MA35_MUX(0x9, "RMII0_RXERR")),
+ MA35_PIN(70, PE10, 0xa4, 0x8,
+ MA35_MUX(0x0, "GPE10"),
+ MA35_MUX(0x2, "UART15_nCTS"),
+ MA35_MUX(0x3, "UART14_RXD"),
+ MA35_MUX(0x5, "SPI1_SS0"),
+ MA35_MUX(0x7, "CCAP1_HSYNC"),
+ MA35_MUX(0x8, "RGMII0_RXD3")),
+ MA35_PIN(71, PE11, 0xa4, 0xc,
+ MA35_MUX(0x0, "GPE11"),
+ MA35_MUX(0x2, "UART15_nRTS"),
+ MA35_MUX(0x3, "UART14_TXD"),
+ MA35_MUX(0x5, "SPI1_CLK"),
+ MA35_MUX(0x7, "CCAP1_VSYNC"),
+ MA35_MUX(0x8, "RGMII0_TXCLK")),
+ MA35_PIN(72, PE12, 0xa4, 0x10,
+ MA35_MUX(0x0, "GPE12"),
+ MA35_MUX(0x2, "UART15_RXD"),
+ MA35_MUX(0x5, "SPI1_MOSI"),
+ MA35_MUX(0x7, "CCAP1_DATA8"),
+ MA35_MUX(0x8, "RGMII0_TXD2")),
+ MA35_PIN(73, PE13, 0xa4, 0x14,
+ MA35_MUX(0x0, "GPE13"),
+ MA35_MUX(0x2, "UART15_TXD"),
+ MA35_MUX(0x5, "SPI1_MISO"),
+ MA35_MUX(0x7, "CCAP1_DATA9"),
+ MA35_MUX(0x8, "RGMII0_TXD3")),
+ MA35_PIN(74, PE14, 0xa4, 0x18,
+ MA35_MUX(0x0, "GPE14"),
+ MA35_MUX(0x1, "UART0_TXD")),
+ MA35_PIN(75, PE15, 0xa4, 0x1c,
+ MA35_MUX(0x0, "GPE15"),
+ MA35_MUX(0x1, "UART0_RXD")),
+ MA35_PIN(76, PF0, 0xa8, 0x0,
+ MA35_MUX(0x0, "GPF0"),
+ MA35_MUX(0x2, "UART2_nCTS"),
+ MA35_MUX(0x3, "UART1_RXD"),
+ MA35_MUX(0x6, "RGMII0_RXD3"),
+ MA35_MUX(0x8, "RGMII1_MDC"),
+ MA35_MUX(0x9, "RMII1_MDC"),
+ MA35_MUX(0xe, "KPI_COL0")),
+ MA35_PIN(77, PF1, 0xa8, 0x4,
+ MA35_MUX(0x0, "GPF1"),
+ MA35_MUX(0x2, "UART2_nRTS"),
+ MA35_MUX(0x3, "UART1_TXD"),
+ MA35_MUX(0x6, "RGMII0_TXCLK"),
+ MA35_MUX(0x8, "RGMII1_MDIO"),
+ MA35_MUX(0x9, "RMII1_MDIO"),
+ MA35_MUX(0xe, "KPI_COL1")),
+ MA35_PIN(78, PF2, 0xa8, 0x8,
+ MA35_MUX(0x0, "GPF2"),
+ MA35_MUX(0x2, "UART2_RXD"),
+ MA35_MUX(0x6, "RGMII0_TXD2"),
+ MA35_MUX(0x8, "RGMII1_TXCTL"),
+ MA35_MUX(0x9, "RMII1_TXEN"),
+ MA35_MUX(0xe, "KPI_COL2")),
+ MA35_PIN(79, PF3, 0xa8, 0xc,
+ MA35_MUX(0x0, "GPF3"),
+ MA35_MUX(0x2, "UART2_TXD"),
+ MA35_MUX(0x6, "RGMII0_TXD3"),
+ MA35_MUX(0x8, "RGMII1_TXD0"),
+ MA35_MUX(0x9, "RMII1_TXD0"),
+ MA35_MUX(0xe, "KPI_COL3")),
+ MA35_PIN(80, PF4, 0xa8, 0x10,
+ MA35_MUX(0x0, "GPF4"),
+ MA35_MUX(0x2, "UART11_nCTS"),
+ MA35_MUX(0x3, "UART10_RXD"),
+ MA35_MUX(0x4, "I2S0_LRCK"),
+ MA35_MUX(0x5, "SPI1_SS0"),
+ MA35_MUX(0x8, "RGMII1_TXD1"),
+ MA35_MUX(0x9, "RMII1_TXD1"),
+ MA35_MUX(0xd, "CAN2_RXD"),
+ MA35_MUX(0xe, "KPI_ROW0")),
+ MA35_PIN(81, PF5, 0xa8, 0x14,
+ MA35_MUX(0x0, "GPF5"),
+ MA35_MUX(0x2, "UART11_nRTS"),
+ MA35_MUX(0x3, "UART10_TXD"),
+ MA35_MUX(0x4, "I2S0_BCLK"),
+ MA35_MUX(0x5, "SPI1_CLK"),
+ MA35_MUX(0x8, "RGMII1_RXCLK"),
+ MA35_MUX(0x9, "RMII1_REFCLK"),
+ MA35_MUX(0xd, "CAN2_TXD"),
+ MA35_MUX(0xe, "KPI_ROW1")),
+ MA35_PIN(82, PF6, 0xa8, 0x18,
+ MA35_MUX(0x0, "GPF6"),
+ MA35_MUX(0x2, "UART11_RXD"),
+ MA35_MUX(0x4, "I2S0_DI"),
+ MA35_MUX(0x5, "SPI1_MOSI"),
+ MA35_MUX(0x8, "RGMII1_RXCTL"),
+ MA35_MUX(0x9, "RMII1_CRSDV"),
+ MA35_MUX(0xa, "I2C4_SDA"),
+ MA35_MUX(0xd, "SC0_CLK"),
+ MA35_MUX(0xe, "KPI_ROW2")),
+ MA35_PIN(83, PF7, 0xa8, 0x1c,
+ MA35_MUX(0x0, "GPF7"),
+ MA35_MUX(0x2, "UART11_TXD"),
+ MA35_MUX(0x4, "I2S0_DO"),
+ MA35_MUX(0x5, "SPI1_MISO"),
+ MA35_MUX(0x8, "RGMII1_RXD0"),
+ MA35_MUX(0x9, "RMII1_RXD0"),
+ MA35_MUX(0xa, "I2C4_SCL"),
+ MA35_MUX(0xd, "SC0_DAT"),
+ MA35_MUX(0xe, "KPI_ROW3")),
+ MA35_PIN(84, PF8, 0xac, 0x0,
+ MA35_MUX(0x0, "GPF8"),
+ MA35_MUX(0x2, "UART13_RXD"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x5, "SPI0_SS0"),
+ MA35_MUX(0x8, "RGMII1_RXD1"),
+ MA35_MUX(0x9, "RMII1_RXD1"),
+ MA35_MUX(0xd, "SC0_RST"),
+ MA35_MUX(0xe, "KPI_COL4")),
+ MA35_PIN(85, PF9, 0xac, 0x4,
+ MA35_MUX(0x0, "GPF9"),
+ MA35_MUX(0x2, "UART13_TXD"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x5, "SPI0_SS1"),
+ MA35_MUX(0x8, "RGMII1_RXD2"),
+ MA35_MUX(0x9, "RMII1_RXERR"),
+ MA35_MUX(0xd, "SC0_PWR"),
+ MA35_MUX(0xe, "KPI_COL5")),
+ MA35_PIN(86, PF10, 0xac, 0x8,
+ MA35_MUX(0x0, "GPF10"),
+ MA35_MUX(0x2, "UART13_nCTS"),
+ MA35_MUX(0x5, "I2S0_LRCK"),
+ MA35_MUX(0x6, "SPI1_SS0"),
+ MA35_MUX(0x8, "RGMII1_RXD3"),
+ MA35_MUX(0x9, "SC0_CLK"),
+ MA35_MUX(0xe, "KPI_COL6")),
+ MA35_PIN(87, PF11, 0xac, 0xc,
+ MA35_MUX(0x0, "GPF11"),
+ MA35_MUX(0x2, "UART13_nRTS"),
+ MA35_MUX(0x5, "I2S0_BCLK"),
+ MA35_MUX(0x6, "SPI1_CLK"),
+ MA35_MUX(0x8, "RGMII1_TXCLK"),
+ MA35_MUX(0x9, "SC0_DAT"),
+ MA35_MUX(0xe, "KPI_COL7")),
+ MA35_PIN(88, PF12, 0xac, 0x10,
+ MA35_MUX(0x0, "GPF12"),
+ MA35_MUX(0x5, "I2S0_DI"),
+ MA35_MUX(0x6, "SPI1_MOSI"),
+ MA35_MUX(0x8, "RGMII1_TXD2"),
+ MA35_MUX(0x9, "SC0_RST"),
+ MA35_MUX(0xe, "KPI_ROW4")),
+ MA35_PIN(89, PF13, 0xac, 0x14,
+ MA35_MUX(0x0, "GPF13"),
+ MA35_MUX(0x5, "I2S0_DO"),
+ MA35_MUX(0x6, "SPI1_MISO"),
+ MA35_MUX(0x8, "RGMII1_TXD3"),
+ MA35_MUX(0x9, "SC0_PWR"),
+ MA35_MUX(0xe, "KPI_ROW5")),
+ MA35_PIN(90, PF14, 0xac, 0x18,
+ MA35_MUX(0x0, "GPF14"),
+ MA35_MUX(0x1, "EPWM2_BRAKE0"),
+ MA35_MUX(0x2, "EADC0_ST"),
+ MA35_MUX(0x3, "RGMII1_PPS"),
+ MA35_MUX(0x4, "RMII1_PPS"),
+ MA35_MUX(0x5, "SPI0_I2SMCLK"),
+ MA35_MUX(0x6, "SPI1_I2SMCLK"),
+ MA35_MUX(0x7, "CCAP1_SFIELD"),
+ MA35_MUX(0x8, "RGMII0_PPS"),
+ MA35_MUX(0x9, "RMII0_PPS"),
+ MA35_MUX(0xb, "TM0"),
+ MA35_MUX(0xc, "INT0"),
+ MA35_MUX(0xd, "SPI1_SS1"),
+ MA35_MUX(0xe, "QEI2_INDEX"),
+ MA35_MUX(0xf, "I2S0_MCLK")),
+ MA35_PIN(91, PF15, 0xac, 0x1c,
+ MA35_MUX(0x0, "GPF15"),
+ MA35_MUX(0x1, "HSUSB0_VBUSVLD")),
+ MA35_PIN(92, PG0, 0xb0, 0x0,
+ MA35_MUX(0x0, "GPG0"),
+ MA35_MUX(0x1, "EPWM0_CH0"),
+ MA35_MUX(0x2, "UART7_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "SPI0_SS0"),
+ MA35_MUX(0x6, "EADC0_ST"),
+ MA35_MUX(0x7, "EBI_AD15"),
+ MA35_MUX(0x9, "I2S1_MCLK"),
+ MA35_MUX(0xa, "QEI0_INDEX"),
+ MA35_MUX(0xb, "TM1"),
+ MA35_MUX(0xc, "CLKO"),
+ MA35_MUX(0xd, "INT0"),
+ MA35_MUX(0xf, "EBI_ADR15")),
+ MA35_PIN(93, PG1, 0xb0, 0x4,
+ MA35_MUX(0x0, "GPG1"),
+ MA35_MUX(0x1, "EPWM0_CH3"),
+ MA35_MUX(0x2, "UART9_nRTS"),
+ MA35_MUX(0x3, "UART6_TXD"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x5, "CAN2_TXD"),
+ MA35_MUX(0x7, "EBI_nCS0"),
+ MA35_MUX(0x9, "QEI0_B"),
+ MA35_MUX(0xb, "TM1_EXT"),
+ MA35_MUX(0xe, "RGMII1_PPS"),
+ MA35_MUX(0xf, "RMII1_PPS")),
+ MA35_PIN(94, PG2, 0xb0, 0x8,
+ MA35_MUX(0x0, "GPG2"),
+ MA35_MUX(0x1, "EPWM0_CH4"),
+ MA35_MUX(0x2, "UART9_RXD"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x5, "SPI0_SS1"),
+ MA35_MUX(0x7, "EBI_ADR16"),
+ MA35_MUX(0x8, "EBI_nCS2"),
+ MA35_MUX(0xa, "QEI0_A"),
+ MA35_MUX(0xb, "TM3"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(95, PG3, 0xb0, 0xc,
+ MA35_MUX(0x0, "GPG3"),
+ MA35_MUX(0x1, "EPWM0_CH5"),
+ MA35_MUX(0x2, "UART9_TXD"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x5, "SPI0_I2SMCLK"),
+ MA35_MUX(0x7, "EBI_ADR17"),
+ MA35_MUX(0x8, "EBI_nCS1"),
+ MA35_MUX(0x9, "EBI_MCLK"),
+ MA35_MUX(0xa, "QEI0_B"),
+ MA35_MUX(0xb, "TM3_EXT"),
+ MA35_MUX(0xc, "I2S1_MCLK")),
+ MA35_PIN(96, PG4, 0xb0, 0x10,
+ MA35_MUX(0x0, "GPG4"),
+ MA35_MUX(0x1, "EPWM1_CH0"),
+ MA35_MUX(0x2, "UART5_nCTS"),
+ MA35_MUX(0x3, "UART6_RXD"),
+ MA35_MUX(0x5, "SPI3_SS0"),
+ MA35_MUX(0x6, "QEI1_INDEX"),
+ MA35_MUX(0x7, "EBI_ADR18"),
+ MA35_MUX(0x8, "EBI_nCS0"),
+ MA35_MUX(0x9, "I2S1_DO"),
+ MA35_MUX(0xa, "SC1_CLK"),
+ MA35_MUX(0xb, "TM4"),
+ MA35_MUX(0xd, "INT2"),
+ MA35_MUX(0xe, "ECAP1_IC2")),
+ MA35_PIN(97, PG5, 0xb0, 0x14,
+ MA35_MUX(0x0, "GPG5"),
+ MA35_MUX(0x1, "EPWM1_CH1"),
+ MA35_MUX(0x2, "UART5_nRTS"),
+ MA35_MUX(0x3, "UART6_TXD"),
+ MA35_MUX(0x5, "SPI3_CLK"),
+ MA35_MUX(0x6, "ECAP0_IC0"),
+ MA35_MUX(0x7, "EBI_ADR19"),
+ MA35_MUX(0x8, "EBI_ALE"),
+ MA35_MUX(0x9, "I2S1_DI"),
+ MA35_MUX(0xa, "SC1_DAT"),
+ MA35_MUX(0xb, "TM4_EXT")),
+ MA35_PIN(98, PG6, 0xb0, 0x18,
+ MA35_MUX(0x0, "GPG6"),
+ MA35_MUX(0x1, "EPWM1_CH2"),
+ MA35_MUX(0x2, "UART5_RXD"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x5, "SPI3_MOSI"),
+ MA35_MUX(0x6, "ECAP0_IC1"),
+ MA35_MUX(0x7, "EBI_nRD"),
+ MA35_MUX(0x9, "I2S1_BCLK"),
+ MA35_MUX(0xa, "SC1_RST"),
+ MA35_MUX(0xb, "TM7"),
+ MA35_MUX(0xd, "INT3")),
+ MA35_PIN(99, PG7, 0xb0, 0x1c,
+ MA35_MUX(0x0, "GPG7"),
+ MA35_MUX(0x1, "EPWM1_CH3"),
+ MA35_MUX(0x2, "UART5_TXD"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x5, "SPI3_MISO"),
+ MA35_MUX(0x6, "ECAP0_IC2"),
+ MA35_MUX(0x7, "EBI_nWR"),
+ MA35_MUX(0x9, "I2S1_LRCK"),
+ MA35_MUX(0xa, "SC1_PWR"),
+ MA35_MUX(0xb, "TM7_EXT")),
+ MA35_PIN(100, PG8, 0xb4, 0x0,
+ MA35_MUX(0x0, "GPG8"),
+ MA35_MUX(0x1, "EPWM1_CH4"),
+ MA35_MUX(0x2, "UART12_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x5, "SPI2_SS0"),
+ MA35_MUX(0x6, "LCM_VSYNC"),
+ MA35_MUX(0x7, "I2C3_SDA"),
+ MA35_MUX(0xc, "EBI_AD7"),
+ MA35_MUX(0xd, "EBI_nCS0")),
+ MA35_PIN(101, PG9, 0xb4, 0x4,
+ MA35_MUX(0x0, "GPG9"),
+ MA35_MUX(0x1, "EPWM1_CH5"),
+ MA35_MUX(0x2, "UART12_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "SPI2_CLK"),
+ MA35_MUX(0x6, "LCM_HSYNC"),
+ MA35_MUX(0x7, "I2C3_SCL"),
+ MA35_MUX(0xc, "EBI_AD8"),
+ MA35_MUX(0xd, "EBI_nCS1")),
+ MA35_PIN(102, PG10, 0xb4, 0x8,
+ MA35_MUX(0x0, "GPG10"),
+ MA35_MUX(0x2, "UART12_nRTS"),
+ MA35_MUX(0x3, "UART13_TXD"),
+ MA35_MUX(0x5, "SPI2_MOSI"),
+ MA35_MUX(0x6, "LCM_CLK"),
+ MA35_MUX(0xc, "EBI_AD9"),
+ MA35_MUX(0xd, "EBI_nWRH")),
+ MA35_PIN(103, PG11, 0xb4, 0xc,
+ MA35_MUX(0x0, "GPG11"),
+ MA35_MUX(0x3, "JTAG_TDO"),
+ MA35_MUX(0x5, "I2S0_MCLK"),
+ MA35_MUX(0x6, "NAND_RDY1"),
+ MA35_MUX(0x7, "EBI_nWRH"),
+ MA35_MUX(0x8, "EBI_nCS1"),
+ MA35_MUX(0xa, "EBI_AD0")),
+ MA35_PIN(104, PG12, 0xb4, 0x10,
+ MA35_MUX(0x0, "GPG12"),
+ MA35_MUX(0x3, "JTAG_TCK/SW_CLK"),
+ MA35_MUX(0x5, "I2S0_LRCK"),
+ MA35_MUX(0x7, "EBI_nWRL"),
+ MA35_MUX(0xa, "EBI_AD1")),
+ MA35_PIN(105, PG13, 0xb4, 0x14,
+ MA35_MUX(0x0, "GPG13"),
+ MA35_MUX(0x3, "JTAG_TMS/SW_DIO"),
+ MA35_MUX(0x5, "I2S0_BCLK"),
+ MA35_MUX(0x7, "EBI_MCLK"),
+ MA35_MUX(0xa, "EBI_AD2")),
+ MA35_PIN(106, PG14, 0xb4, 0x18,
+ MA35_MUX(0x0, "GPG14"),
+ MA35_MUX(0x3, "JTAG_TDI"),
+ MA35_MUX(0x5, "I2S0_DI"),
+ MA35_MUX(0x6, "NAND_nCS1"),
+ MA35_MUX(0x7, "EBI_ALE"),
+ MA35_MUX(0xa, "EBI_AD3")),
+ MA35_PIN(107, PG15, 0xb4, 0x1c,
+ MA35_MUX(0x0, "GPG15"),
+ MA35_MUX(0x3, "JTAG_nTRST"),
+ MA35_MUX(0x5, "I2S0_DO"),
+ MA35_MUX(0x7, "EBI_nCS0"),
+ MA35_MUX(0xa, "EBI_AD4")),
+ MA35_PIN(108, PH0, 0xb8, 0x0,
+ MA35_MUX(0x0, "GPH0"),
+ MA35_MUX(0x2, "UART8_nCTS"),
+ MA35_MUX(0x3, "UART7_RXD"),
+ MA35_MUX(0x6, "LCM_DATA8")),
+ MA35_PIN(109, PH1, 0xb8, 0x4,
+ MA35_MUX(0x0, "GPH1"),
+ MA35_MUX(0x2, "UART8_nRTS"),
+ MA35_MUX(0x3, "UART7_TXD"),
+ MA35_MUX(0x6, "LCM_DATA9")),
+ MA35_PIN(110, PH2, 0xb8, 0x8,
+ MA35_MUX(0x0, "GPH2"),
+ MA35_MUX(0x2, "UART8_RXD"),
+ MA35_MUX(0x6, "LCM_DATA10")),
+ MA35_PIN(111, PH3, 0xb8, 0xc,
+ MA35_MUX(0x0, "GPH3"),
+ MA35_MUX(0x2, "UART8_TXD"),
+ MA35_MUX(0x6, "LCM_DATA11")),
+ MA35_PIN(112, PH4, 0xb8, 0x10,
+ MA35_MUX(0x0, "GPH4"),
+ MA35_MUX(0x2, "UART10_nCTS"),
+ MA35_MUX(0x3, "UART9_RXD"),
+ MA35_MUX(0x6, "LCM_DATA12")),
+ MA35_PIN(113, PH5, 0xb8, 0x14,
+ MA35_MUX(0x0, "GPH5"),
+ MA35_MUX(0x2, "UART10_nRTS"),
+ MA35_MUX(0x3, "UART9_TXD"),
+ MA35_MUX(0x6, "LCM_DATA13")),
+ MA35_PIN(114, PH6, 0xb8, 0x18,
+ MA35_MUX(0x0, "GPH6"),
+ MA35_MUX(0x2, "UART10_RXD"),
+ MA35_MUX(0x6, "LCM_DATA14")),
+ MA35_PIN(115, PH7, 0xb8, 0x1c,
+ MA35_MUX(0x0, "GPH7"),
+ MA35_MUX(0x2, "UART10_TXD"),
+ MA35_MUX(0x6, "LCM_DATA15")),
+ MA35_PIN(116, PH8, 0xbc, 0x0,
+ MA35_MUX(0x0, "GPH8"),
+ MA35_MUX(0x6, "TAMPER0")),
+ MA35_PIN(117, PH9, 0xbc, 0x4,
+ MA35_MUX(0x0, "GPH9"),
+ MA35_MUX(0x4, "CLK_32KOUT"),
+ MA35_MUX(0x6, "TAMPER1")),
+ MA35_PIN(118, PH12, 0xbc, 0x10,
+ MA35_MUX(0x0, "GPH12"),
+ MA35_MUX(0x2, "UART14_nCTS"),
+ MA35_MUX(0x3, "UART13_RXD"),
+ MA35_MUX(0x6, "LCM_DATA20")),
+ MA35_PIN(119, PH13, 0xbc, 0x14,
+ MA35_MUX(0x0, "GPH13"),
+ MA35_MUX(0x2, "UART14_nRTS"),
+ MA35_MUX(0x3, "UART13_TXD"),
+ MA35_MUX(0x6, "LCM_DATA21")),
+ MA35_PIN(120, PH14, 0xbc, 0x18,
+ MA35_MUX(0x0, "GPH14"),
+ MA35_MUX(0x2, "UART14_RXD"),
+ MA35_MUX(0x6, "LCM_DATA22")),
+ MA35_PIN(121, PH15, 0xbc, 0x1c,
+ MA35_MUX(0x0, "GPH15"),
+ MA35_MUX(0x2, "UART14_TXD"),
+ MA35_MUX(0x6, "LCM_DATA23")),
+ MA35_PIN(122, PI0, 0xc0, 0x0,
+ MA35_MUX(0x0, "GPI0"),
+ MA35_MUX(0x1, "EPWM0_CH0"),
+ MA35_MUX(0x2, "UART12_nCTS"),
+ MA35_MUX(0x3, "UART11_RXD"),
+ MA35_MUX(0x4, "I2C2_SDA"),
+ MA35_MUX(0x5, "SPI3_SS0"),
+ MA35_MUX(0x7, "SC0_nCD"),
+ MA35_MUX(0x8, "EBI_ADR0"),
+ MA35_MUX(0xb, "TM0"),
+ MA35_MUX(0xc, "ECAP1_IC0")),
+ MA35_PIN(123, PI1, 0xc0, 0x4,
+ MA35_MUX(0x0, "GPI1"),
+ MA35_MUX(0x1, "EPWM0_CH1"),
+ MA35_MUX(0x2, "UART12_nRTS"),
+ MA35_MUX(0x3, "UART11_TXD"),
+ MA35_MUX(0x4, "I2C2_SCL"),
+ MA35_MUX(0x5, "SPI3_CLK"),
+ MA35_MUX(0x7, "SC0_CLK"),
+ MA35_MUX(0x8, "EBI_ADR1"),
+ MA35_MUX(0xb, "TM0_EXT"),
+ MA35_MUX(0xc, "ECAP1_IC1")),
+ MA35_PIN(124, PI2, 0xc0, 0x8,
+ MA35_MUX(0x0, "GPI2"),
+ MA35_MUX(0x1, "EPWM0_CH2"),
+ MA35_MUX(0x2, "UART12_RXD"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x5, "SPI3_MOSI"),
+ MA35_MUX(0x7, "SC0_DAT"),
+ MA35_MUX(0x8, "EBI_ADR2"),
+ MA35_MUX(0xb, "TM1"),
+ MA35_MUX(0xc, "ECAP1_IC2")),
+ MA35_PIN(125, PI3, 0xc0, 0xc,
+ MA35_MUX(0x0, "GPI3"),
+ MA35_MUX(0x1, "EPWM0_CH3"),
+ MA35_MUX(0x2, "UART12_TXD"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x5, "SPI3_MISO"),
+ MA35_MUX(0x7, "SC0_RST"),
+ MA35_MUX(0x8, "EBI_ADR3"),
+ MA35_MUX(0xb, "TM1_EXT")),
+ MA35_PIN(126, PI4, 0xc0, 0x10,
+ MA35_MUX(0x0, "GPI4"),
+ MA35_MUX(0x1, "EPWM0_CH4"),
+ MA35_MUX(0x2, "UART14_nCTS"),
+ MA35_MUX(0x3, "UART13_RXD"),
+ MA35_MUX(0x4, "I2C3_SDA"),
+ MA35_MUX(0x5, "SPI2_SS1"),
+ MA35_MUX(0x6, "I2S1_LRCK"),
+ MA35_MUX(0x8, "EBI_ADR4"),
+ MA35_MUX(0xd, "INT0")),
+ MA35_PIN(127, PI5, 0xc0, 0x14,
+ MA35_MUX(0x0, "GPI5"),
+ MA35_MUX(0x1, "EPWM0_CH5"),
+ MA35_MUX(0x2, "UART14_nRTS"),
+ MA35_MUX(0x3, "UART13_TXD"),
+ MA35_MUX(0x4, "I2C3_SCL"),
+ MA35_MUX(0x6, "I2S1_BCLK"),
+ MA35_MUX(0x8, "EBI_ADR5"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(128, PI6, 0xc0, 0x18,
+ MA35_MUX(0x0, "GPI6"),
+ MA35_MUX(0x1, "EPWM0_BRAKE0"),
+ MA35_MUX(0x2, "UART14_RXD"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x6, "I2S1_DI"),
+ MA35_MUX(0x8, "EBI_ADR6"),
+ MA35_MUX(0xc, "QEI1_INDEX"),
+ MA35_MUX(0xd, "INT2")),
+ MA35_PIN(129, PI7, 0xc0, 0x1c,
+ MA35_MUX(0x0, "GPI7"),
+ MA35_MUX(0x1, "EPWM0_BRAKE1"),
+ MA35_MUX(0x2, "UART14_TXD"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x6, "I2S1_DO"),
+ MA35_MUX(0x8, "EBI_ADR7"),
+ MA35_MUX(0xc, "ECAP0_IC0"),
+ MA35_MUX(0xd, "INT3")),
+ MA35_PIN(130, PI8, 0xc4, 0x0,
+ MA35_MUX(0x0, "GPI8"),
+ MA35_MUX(0x2, "UART4_nCTS"),
+ MA35_MUX(0x3, "UART3_RXD"),
+ MA35_MUX(0x6, "LCM_DATA0"),
+ MA35_MUX(0xc, "EBI_AD11")),
+ MA35_PIN(131, PI9, 0xc4, 0x4,
+ MA35_MUX(0x0, "GPI9"),
+ MA35_MUX(0x2, "UART4_nRTS"),
+ MA35_MUX(0x3, "UART3_TXD"),
+ MA35_MUX(0x6, "LCM_DATA1"),
+ MA35_MUX(0xc, "EBI_AD12")),
+ MA35_PIN(132, PI10, 0xc4, 0x8,
+ MA35_MUX(0x0, "GPI10"),
+ MA35_MUX(0x2, "UART4_RXD"),
+ MA35_MUX(0x6, "LCM_DATA2"),
+ MA35_MUX(0xc, "EBI_AD13")),
+ MA35_PIN(133, PI11, 0xC4, 0xc,
+ MA35_MUX(0x0, "GPI11"),
+ MA35_MUX(0x2, "UART4_TXD"),
+ MA35_MUX(0x6, "LCM_DATA3"),
+ MA35_MUX(0xc, "EBI_AD14")),
+ MA35_PIN(134, PI12, 0xc4, 0x10,
+ MA35_MUX(0x0, "GPI12"),
+ MA35_MUX(0x2, "UART6_nCTS"),
+ MA35_MUX(0x3, "UART5_RXD"),
+ MA35_MUX(0x6, "LCM_DATA4")),
+ MA35_PIN(135, PI13, 0xc4, 0x14,
+ MA35_MUX(0x0, "GPI13"),
+ MA35_MUX(0x2, "UART6_nRTS"),
+ MA35_MUX(0x3, "UART5_TXD"),
+ MA35_MUX(0x6, "LCM_DATA5")),
+ MA35_PIN(136, PI14, 0xc4, 0x18,
+ MA35_MUX(0x0, "GPI14"),
+ MA35_MUX(0x2, "UART6_RXD"),
+ MA35_MUX(0x6, "LCM_DATA6")),
+ MA35_PIN(137, PI15, 0xc4, 0x1c,
+ MA35_MUX(0x0, "GPI15"),
+ MA35_MUX(0x2, "UART6_TXD"),
+ MA35_MUX(0x6, "LCM_DATA7")),
+ MA35_PIN(138, PJ0, 0xc8, 0x0,
+ MA35_MUX(0x0, "GPJ0"),
+ MA35_MUX(0x1, "EPWM1_BRAKE0"),
+ MA35_MUX(0x2, "UART8_nCTS"),
+ MA35_MUX(0x3, "UART7_RXD"),
+ MA35_MUX(0x4, "I2C2_SDA"),
+ MA35_MUX(0x5, "SPI2_SS0"),
+ MA35_MUX(0x6, "eMMC1_DAT4"),
+ MA35_MUX(0x7, "I2S0_LRCK"),
+ MA35_MUX(0x8, "SC0_CLK"),
+ MA35_MUX(0x9, "EBI_AD11"),
+ MA35_MUX(0xa, "EBI_ADR16"),
+ MA35_MUX(0xb, "EBI_nCS0"),
+ MA35_MUX(0xc, "EBI_AD7")),
+ MA35_PIN(139, PJ1, 0xc8, 0x4,
+ MA35_MUX(0x0, "GPJ1"),
+ MA35_MUX(0x1, "EPWM1_BRAKE1"),
+ MA35_MUX(0x2, "UART8_nRTS"),
+ MA35_MUX(0x3, "UART7_TXD"),
+ MA35_MUX(0x4, "I2C2_SCL"),
+ MA35_MUX(0x5, "SPI2_CLK"),
+ MA35_MUX(0x6, "eMMC1_DAT5"),
+ MA35_MUX(0x7, "I2S0_BCLK"),
+ MA35_MUX(0x8, "SC0_DAT"),
+ MA35_MUX(0x9, "EBI_AD12"),
+ MA35_MUX(0xa, "EBI_ADR17"),
+ MA35_MUX(0xb, "EBI_nCS1"),
+ MA35_MUX(0xc, "EBI_AD8")),
+ MA35_PIN(140, PJ2, 0xc8, 0x8,
+ MA35_MUX(0x0, "GPJ2"),
+ MA35_MUX(0x1, "EPWM1_CH4"),
+ MA35_MUX(0x2, "UART8_RXD"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x5, "SPI2_MOSI"),
+ MA35_MUX(0x6, "eMMC1_DAT6"),
+ MA35_MUX(0x7, "I2S0_DI"),
+ MA35_MUX(0x8, "SC0_RST"),
+ MA35_MUX(0x9, "EBI_AD13"),
+ MA35_MUX(0xa, "EBI_ADR18"),
+ MA35_MUX(0xb, "EBI_nWRH"),
+ MA35_MUX(0xc, "EBI_AD9")),
+ MA35_PIN(141, PJ3, 0xc8, 0xc,
+ MA35_MUX(0x0, "GPJ3"),
+ MA35_MUX(0x1, "EPWM1_CH5"),
+ MA35_MUX(0x2, "UART8_TXD"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x5, "SPI2_MISO"),
+ MA35_MUX(0x6, "eMMC1_DAT7"),
+ MA35_MUX(0x7, "I2S0_DO"),
+ MA35_MUX(0x8, "SC0_PWR"),
+ MA35_MUX(0x9, "EBI_AD14"),
+ MA35_MUX(0xa, "EBI_ADR19"),
+ MA35_MUX(0xb, "EBI_nWRL"),
+ MA35_MUX(0xc, "EBI_AD10")),
+ MA35_PIN(142, PJ4, 0xc8, 0x10,
+ MA35_MUX(0x0, "GPJ4"),
+ MA35_MUX(0x4, "I2C3_SDA"),
+ MA35_MUX(0x6, "SD1_WP")),
+ MA35_PIN(143, PJ5, 0xc8, 0x14,
+ MA35_MUX(0x0, "GPJ5"),
+ MA35_MUX(0x4, "I2C3_SCL"),
+ MA35_MUX(0x6, "SD1_nCD")),
+ MA35_PIN(144, PJ6, 0xc8, 0x18,
+ MA35_MUX(0x0, "GPJ6"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x6, "SD1_CMD/eMMC1_CMD")),
+ MA35_PIN(145, PJ7, 0xc8, 0x1c,
+ MA35_MUX(0x0, "GPJ7"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x6, "SD1_CLK/eMMC1_CLK")),
+ MA35_PIN(146, PJ8, 0xcc, 0x0,
+ MA35_MUX(0x0, "GPJ8"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x6, "SD1_DAT0/eMMC1_DAT0")),
+ MA35_PIN(147, PJ9, 0xcc, 0x4,
+ MA35_MUX(0x0, "GPJ9"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x6, "SD1_DAT1/eMMC1_DAT1")),
+ MA35_PIN(148, PJ10, 0xcc, 0x8,
+ MA35_MUX(0x0, "GPJ10"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x6, "SD1_DAT2/eMMC1_DAT2")),
+ MA35_PIN(149, PJ11, 0xcc, 0xc,
+ MA35_MUX(0x0, "GPJ11"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x6, "SD1_DAT3/eMMC1_DAT3")),
+ MA35_PIN(150, PJ12, 0xcc, 0x10,
+ MA35_MUX(0x0, "GPJ12"),
+ MA35_MUX(0x1, "EPWM1_CH2"),
+ MA35_MUX(0x2, "UART2_nCTS"),
+ MA35_MUX(0x3, "UART1_RXD"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x5, "SPI3_SS0"),
+ MA35_MUX(0x7, "SC1_CLK"),
+ MA35_MUX(0x8, "EBI_ADR12"),
+ MA35_MUX(0xb, "TM2"),
+ MA35_MUX(0xc, "QEI0_INDEX")),
+ MA35_PIN(151, PJ13, 0xcc, 0x14,
+ MA35_MUX(0x0, "GPJ13"),
+ MA35_MUX(0x1, "EPWM1_CH3"),
+ MA35_MUX(0x2, "UART2_nRTS"),
+ MA35_MUX(0x3, "UART1_TXD"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x5, "SPI3_MOSI"),
+ MA35_MUX(0x7, "SC1_DAT"),
+ MA35_MUX(0x8, "EBI_ADR13"),
+ MA35_MUX(0xb, "TM2_EXT")),
+ MA35_PIN(152, PJ14, 0xcc, 0x18,
+ MA35_MUX(0x0, "GPJ14"),
+ MA35_MUX(0x1, "EPWM1_CH4"),
+ MA35_MUX(0x2, "UART2_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x5, "SPI3_MISO"),
+ MA35_MUX(0x7, "SC1_RST"),
+ MA35_MUX(0x8, "EBI_ADR14"),
+ MA35_MUX(0xb, "TM3")),
+ MA35_PIN(153, PJ15, 0xcc, 0x1c,
+ MA35_MUX(0x0, "GPJ15"),
+ MA35_MUX(0x1, "EPWM1_CH5"),
+ MA35_MUX(0x2, "UART2_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "SPI3_CLK"),
+ MA35_MUX(0x6, "EADC0_ST"),
+ MA35_MUX(0x7, "SC1_PWR"),
+ MA35_MUX(0x8, "EBI_ADR15"),
+ MA35_MUX(0xb, "TM3_EXT"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(154, PK0, 0xd0, 0x0,
+ MA35_MUX(0x0, "GPK0"),
+ MA35_MUX(0x1, "EPWM0_SYNC_IN"),
+ MA35_MUX(0x2, "UART16_nCTS"),
+ MA35_MUX(0x3, "UART15_RXD"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x6, "I2S1_MCLK"),
+ MA35_MUX(0x8, "EBI_ADR8"),
+ MA35_MUX(0xb, "TM7"),
+ MA35_MUX(0xc, "ECAP0_IC1")),
+ MA35_PIN(155, PK1, 0xd0, 0x4,
+ MA35_MUX(0x0, "GPK1"),
+ MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
+ MA35_MUX(0x2, "UART16_nRTS"),
+ MA35_MUX(0x3, "UART15_TXD"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x6, "EADC0_ST"),
+ MA35_MUX(0x8, "EBI_ADR9"),
+ MA35_MUX(0xb, "TM7_EXT"),
+ MA35_MUX(0xc, "ECAP0_IC2")),
+ MA35_PIN(156, PK2, 0xd0, 0x8,
+ MA35_MUX(0x0, "GPK2"),
+ MA35_MUX(0x1, "EPWM1_CH0"),
+ MA35_MUX(0x2, "UART16_RXD"),
+ MA35_MUX(0x3, "CAN2_RXD"),
+ MA35_MUX(0x5, "SPI3_I2SMCLK"),
+ MA35_MUX(0x7, "SC0_PWR"),
+ MA35_MUX(0x8, "EBI_ADR10"),
+ MA35_MUX(0xc, "QEI0_A")),
+ MA35_PIN(157, PK3, 0xd0, 0xc,
+ MA35_MUX(0x0, "GPK3"),
+ MA35_MUX(0x1, "EPWM1_CH1"),
+ MA35_MUX(0x2, "UART16_TXD"),
+ MA35_MUX(0x3, "CAN2_TXD"),
+ MA35_MUX(0x5, "SPI3_SS1"),
+ MA35_MUX(0x7, "SC1_nCD"),
+ MA35_MUX(0x8, "EBI_ADR11"),
+ MA35_MUX(0xc, "QEI0_B")),
+ MA35_PIN(158, PK4, 0xd0, 0x10,
+ MA35_MUX(0x0, "GPK4"),
+ MA35_MUX(0x2, "UART12_nCTS"),
+ MA35_MUX(0x3, "UART13_RXD"),
+ MA35_MUX(0x5, "SPI2_MISO"),
+ MA35_MUX(0x6, "LCM_DEN"),
+ MA35_MUX(0xc, "EBI_AD10"),
+ MA35_MUX(0xd, "EBI_nWRL")),
+ MA35_PIN(159, PK5, 0xd0, 0x14,
+ MA35_MUX(0x0, "GPK5"),
+ MA35_MUX(0x1, "EPWM1_CH1"),
+ MA35_MUX(0x2, "UART12_nRTS"),
+ MA35_MUX(0x3, "UART13_TXD"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x5, "SPI2_CLK"),
+ MA35_MUX(0x7, "I2S1_DI"),
+ MA35_MUX(0x8, "SC0_DAT"),
+ MA35_MUX(0x9, "EADC0_ST"),
+ MA35_MUX(0xb, "TM8_EXT"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(160, PK6, 0xd0, 0x18,
+ MA35_MUX(0x0, "GPK6"),
+ MA35_MUX(0x1, "EPWM1_CH2"),
+ MA35_MUX(0x2, "UART12_RXD"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x5, "SPI2_MOSI"),
+ MA35_MUX(0x7, "I2S1_BCLK"),
+ MA35_MUX(0x8, "SC0_RST"),
+ MA35_MUX(0xb, "TM6"),
+ MA35_MUX(0xd, "INT2")),
+ MA35_PIN(161, PK7, 0xd0, 0x1c,
+ MA35_MUX(0x0, "GPK7"),
+ MA35_MUX(0x1, "EPWM1_CH3"),
+ MA35_MUX(0x2, "UART12_TXD"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x5, "SPI2_MISO"),
+ MA35_MUX(0x7, "I2S1_LRCK"),
+ MA35_MUX(0x8, "SC0_PWR"),
+ MA35_MUX(0x9, "CLKO"),
+ MA35_MUX(0xb, "TM6_EXT"),
+ MA35_MUX(0xd, "INT3")),
+ MA35_PIN(162, PK8, 0xd4, 0x0,
+ MA35_MUX(0x0, "GPK8"),
+ MA35_MUX(0x1, "EPWM1_CH0"),
+ MA35_MUX(0x4, "I2C3_SDA"),
+ MA35_MUX(0x5, "SPI3_CLK"),
+ MA35_MUX(0x7, "EADC0_ST"),
+ MA35_MUX(0x8, "EBI_AD15"),
+ MA35_MUX(0x9, "EBI_MCLK"),
+ MA35_MUX(0xa, "EBI_ADR15"),
+ MA35_MUX(0xb, "TM8"),
+ MA35_MUX(0xc, "QEI1_INDEX")),
+ MA35_PIN(163, PK9, 0xd4, 0x4,
+ MA35_MUX(0x0, "GPK9"),
+ MA35_MUX(0x4, "I2C3_SCL"),
+ MA35_MUX(0x6, "CCAP0_SCLK"),
+ MA35_MUX(0x8, "EBI_AD0"),
+ MA35_MUX(0xa, "EBI_ADR0")),
+ MA35_PIN(164, PK10, 0xd4, 0x8,
+ MA35_MUX(0x0, "GPK10"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x6, "CCAP0_PIXCLK"),
+ MA35_MUX(0x8, "EBI_AD1"),
+ MA35_MUX(0xa, "EBI_ADR1")),
+ MA35_PIN(165, PK11, 0xd4, 0xc,
+ MA35_MUX(0x0, "GPK11"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x6, "CCAP0_HSYNC"),
+ MA35_MUX(0x8, "EBI_AD2"),
+ MA35_MUX(0xa, "EBI_ADR2")),
+ MA35_PIN(166, PK12, 0xd4, 0x10,
+ MA35_MUX(0x0, "GPK12"),
+ MA35_MUX(0x1, "EPWM2_CH0"),
+ MA35_MUX(0x2, "UART1_nCTS"),
+ MA35_MUX(0x3, "UART13_RXD"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x5, "I2S0_LRCK"),
+ MA35_MUX(0x6, "SPI1_SS0"),
+ MA35_MUX(0x8, "SC0_CLK"),
+ MA35_MUX(0xb, "TM10"),
+ MA35_MUX(0xd, "INT2")),
+ MA35_PIN(167, PK13, 0xd4, 0x14,
+ MA35_MUX(0x0, "GPK13"),
+ MA35_MUX(0x1, "EPWM2_CH1"),
+ MA35_MUX(0x2, "UART1_nRTS"),
+ MA35_MUX(0x3, "UART13_TXD"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x5, "I2S0_BCLK"),
+ MA35_MUX(0x6, "SPI1_CLK"),
+ MA35_MUX(0x8, "SC0_DAT"),
+ MA35_MUX(0xb, "TM10_EXT")),
+ MA35_PIN(168, PK14, 0xd4, 0x18,
+ MA35_MUX(0x0, "GPK14"),
+ MA35_MUX(0x1, "EPWM2_CH2"),
+ MA35_MUX(0x2, "UART1_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x5, "I2S0_DI"),
+ MA35_MUX(0x6, "SPI1_MOSI"),
+ MA35_MUX(0x8, "SC0_RST"),
+ MA35_MUX(0xa, "I2C5_SDA"),
+ MA35_MUX(0xb, "TM11"),
+ MA35_MUX(0xd, "INT3")),
+ MA35_PIN(169, PK15, 0xd4, 0x1c,
+ MA35_MUX(0x0, "GPK15"),
+ MA35_MUX(0x1, "EPWM2_CH3"),
+ MA35_MUX(0x2, "UART1_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "I2S0_DO"),
+ MA35_MUX(0x6, "SPI1_MISO"),
+ MA35_MUX(0x8, "SC0_PWR"),
+ MA35_MUX(0xa, "I2C5_SCL"),
+ MA35_MUX(0xb, "TM11_EXT")),
+ MA35_PIN(170, PL0, 0xd8, 0x0,
+ MA35_MUX(0x0, "GPL0"),
+ MA35_MUX(0x1, "EPWM1_CH0"),
+ MA35_MUX(0x2, "UART11_nCTS"),
+ MA35_MUX(0x3, "UART10_RXD"),
+ MA35_MUX(0x4, "I2C3_SDA"),
+ MA35_MUX(0x5, "SPI2_MOSI"),
+ MA35_MUX(0x6, "QSPI1_MOSI1"),
+ MA35_MUX(0x7, "I2S0_LRCK"),
+ MA35_MUX(0x8, "EBI_AD11"),
+ MA35_MUX(0x9, "SC1_CLK"),
+ MA35_MUX(0xb, "TM5"),
+ MA35_MUX(0xc, "QEI1_A")),
+ MA35_PIN(171, PL1, 0xd8, 0x4,
+ MA35_MUX(0x0, "GPL1"),
+ MA35_MUX(0x1, "EPWM1_CH1"),
+ MA35_MUX(0x2, "UART11_nRTS"),
+ MA35_MUX(0x3, "UART10_TXD"),
+ MA35_MUX(0x4, "I2C3_SCL"),
+ MA35_MUX(0x5, "SPI2_MISO"),
+ MA35_MUX(0x6, "QSPI1_MISO1"),
+ MA35_MUX(0x7, "I2S0_BCLK"),
+ MA35_MUX(0x8, "EBI_AD12"),
+ MA35_MUX(0x9, "SC1_DAT"),
+ MA35_MUX(0xb, "TM5_EXT"),
+ MA35_MUX(0xc, "QEI1_B")),
+ MA35_PIN(172, PL2, 0xd8, 0x8,
+ MA35_MUX(0x0, "GPL2"),
+ MA35_MUX(0x1, "EPWM1_CH2"),
+ MA35_MUX(0x2, "UART11_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x5, "SPI2_SS0"),
+ MA35_MUX(0x6, "QSPI1_SS1"),
+ MA35_MUX(0x7, "I2S0_DI"),
+ MA35_MUX(0x8, "EBI_AD13"),
+ MA35_MUX(0x9, "SC1_RST"),
+ MA35_MUX(0xb, "TM7"),
+ MA35_MUX(0xc, "QEI1_INDEX")),
+ MA35_PIN(173, PL3, 0xd8, 0xc,
+ MA35_MUX(0x0, "GPL3"),
+ MA35_MUX(0x1, "EPWM1_CH3"),
+ MA35_MUX(0x2, "UART11_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "SPI2_CLK"),
+ MA35_MUX(0x6, "QSPI1_CLK"),
+ MA35_MUX(0x7, "I2S0_DO"),
+ MA35_MUX(0x8, "EBI_AD14"),
+ MA35_MUX(0x9, "SC1_PWR"),
+ MA35_MUX(0xb, "TM7_EXT"),
+ MA35_MUX(0xc, "ECAP0_IC0")),
+ MA35_PIN(174, PL4, 0xd8, 0x10,
+ MA35_MUX(0x0, "GPL4"),
+ MA35_MUX(0x1, "EPWM1_CH4"),
+ MA35_MUX(0x2, "UART2_nCTS"),
+ MA35_MUX(0x3, "UART1_RXD"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x5, "SPI3_MOSI"),
+ MA35_MUX(0x6, "QSPI1_MOSI0"),
+ MA35_MUX(0x7, "I2S0_MCLK"),
+ MA35_MUX(0x8, "EBI_nRD"),
+ MA35_MUX(0x9, "SC1_nCD"),
+ MA35_MUX(0xb, "TM9"),
+ MA35_MUX(0xc, "ECAP0_IC1")),
+ MA35_PIN(175, PL5, 0xd8, 0x14,
+ MA35_MUX(0x0, "GPL5"),
+ MA35_MUX(0x1, "EPWM1_CH5"),
+ MA35_MUX(0x2, "UART2_nRTS"),
+ MA35_MUX(0x3, "UART1_TXD"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x5, "SPI3_MISO"),
+ MA35_MUX(0x6, "QSPI1_MISO0"),
+ MA35_MUX(0x7, "I2S1_MCLK"),
+ MA35_MUX(0x8, "EBI_nWR"),
+ MA35_MUX(0x9, "SC0_nCD"),
+ MA35_MUX(0xb, "TM9_EXT"),
+ MA35_MUX(0xc, "ECAP0_IC2")),
+ MA35_PIN(176, PL6, 0xd8, 0x18,
+ MA35_MUX(0x0, "GPL6"),
+ MA35_MUX(0x1, "EPWM0_CH0"),
+ MA35_MUX(0x2, "UART2_RXD"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x6, "QSPI1_MOSI1"),
+ MA35_MUX(0x7, "TRACE_CLK"),
+ MA35_MUX(0x8, "EBI_AD5"),
+ MA35_MUX(0xb, "TM3"),
+ MA35_MUX(0xc, "ECAP1_IC0"),
+ MA35_MUX(0xd, "INT0")),
+ MA35_PIN(177, PL7, 0xd8, 0x1c,
+ MA35_MUX(0x0, "GPL7"),
+ MA35_MUX(0x1, "EPWM0_CH1"),
+ MA35_MUX(0x2, "UART2_TXD"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x6, "QSPI1_MISO1"),
+ MA35_MUX(0x8, "EBI_AD6"),
+ MA35_MUX(0xb, "TM3_EXT"),
+ MA35_MUX(0xc, "ECAP1_IC1"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(178, PL8, 0xdc, 0x0,
+ MA35_MUX(0x0, "GPL8"),
+ MA35_MUX(0x1, "EPWM0_CH2"),
+ MA35_MUX(0x2, "UART14_nCTS"),
+ MA35_MUX(0x3, "UART13_RXD"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x5, "SPI3_SS0"),
+ MA35_MUX(0x6, "EPWM0_CH4"),
+ MA35_MUX(0x7, "I2S1_LRCK"),
+ MA35_MUX(0x8, "EBI_AD7"),
+ MA35_MUX(0x9, "SC0_CLK"),
+ MA35_MUX(0xb, "TM4"),
+ MA35_MUX(0xc, "ECAP1_IC2"),
+ MA35_MUX(0xd, "INT2")),
+ MA35_PIN(179, PL9, 0xdc, 0x4,
+ MA35_MUX(0x0, "GPL9"),
+ MA35_MUX(0x1, "EPWM0_CH3"),
+ MA35_MUX(0x2, "UART14_nRTS"),
+ MA35_MUX(0x3, "UART13_TXD"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x5, "SPI3_CLK"),
+ MA35_MUX(0x6, "EPWM1_CH4"),
+ MA35_MUX(0x7, "I2S1_BCLK"),
+ MA35_MUX(0x8, "EBI_AD8"),
+ MA35_MUX(0x9, "SC0_DAT"),
+ MA35_MUX(0xb, "TM4_EXT"),
+ MA35_MUX(0xc, "QEI0_A"),
+ MA35_MUX(0xd, "INT3")),
+ MA35_PIN(180, PL10, 0xdc, 0x8,
+ MA35_MUX(0x0, "GPL10"),
+ MA35_MUX(0x1, "EPWM0_CH4"),
+ MA35_MUX(0x2, "UART14_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x5, "SPI3_MOSI"),
+ MA35_MUX(0x6, "EPWM0_CH5"),
+ MA35_MUX(0x7, "I2S1_DI"),
+ MA35_MUX(0x8, "EBI_AD9"),
+ MA35_MUX(0x9, "SC0_RST"),
+ MA35_MUX(0xb, "EBI_nWRH"),
+ MA35_MUX(0xc, "QEI0_B")),
+ MA35_PIN(181, PL11, 0xdc, 0xc,
+ MA35_MUX(0x0, "GPL11"),
+ MA35_MUX(0x1, "EPWM0_CH5"),
+ MA35_MUX(0x2, "UART14_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "SPI3_MISO"),
+ MA35_MUX(0x6, "EPWM1_CH5"),
+ MA35_MUX(0x7, "I2S1_DO"),
+ MA35_MUX(0x8, "EBI_AD10"),
+ MA35_MUX(0x9, "SC0_PWR"),
+ MA35_MUX(0xb, "EBI_nWRL"),
+ MA35_MUX(0xc, "QEI0_INDEX")),
+ MA35_PIN(182, PL12, 0xdc, 0x10,
+ MA35_MUX(0x0, "GPL12"),
+ MA35_MUX(0x1, "EPWM0_SYNC_IN"),
+ MA35_MUX(0x2, "UART7_nCTS"),
+ MA35_MUX(0x3, "ECAP1_IC0"),
+ MA35_MUX(0x4, "UART14_RXD"),
+ MA35_MUX(0x5, "SPI0_SS0"),
+ MA35_MUX(0x6, "I2S1_LRCK"),
+ MA35_MUX(0x7, "SC1_CLK"),
+ MA35_MUX(0x8, "EBI_AD0"),
+ MA35_MUX(0x9, "HSUSBH_PWREN"),
+ MA35_MUX(0xa, "I2C2_SDA"),
+ MA35_MUX(0xb, "TM0"),
+ MA35_MUX(0xc, "EPWM0_CH2"),
+ MA35_MUX(0xd, "EBI_AD11"),
+ MA35_MUX(0xe, "RGMII0_PPS"),
+ MA35_MUX(0xf, "RMII0_PPS")),
+ MA35_PIN(183, PL13, 0xdc, 0x14,
+ MA35_MUX(0x0, "GPL13"),
+ MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
+ MA35_MUX(0x2, "UART7_nRTS"),
+ MA35_MUX(0x3, "ECAP1_IC1"),
+ MA35_MUX(0x4, "UART14_TXD"),
+ MA35_MUX(0x5, "SPI0_CLK"),
+ MA35_MUX(0x6, "I2S1_BCLK"),
+ MA35_MUX(0x7, "SC1_DAT"),
+ MA35_MUX(0x8, "EBI_AD1"),
+ MA35_MUX(0x9, "HSUSBH_OVC"),
+ MA35_MUX(0xa, "I2C2_SCL"),
+ MA35_MUX(0xb, "TM0_EXT"),
+ MA35_MUX(0xc, "EPWM0_CH3"),
+ MA35_MUX(0xd, "EBI_AD12"),
+ MA35_MUX(0xe, "RGMII1_PPS"),
+ MA35_MUX(0xf, "RMII1_PPS")),
+ MA35_PIN(184, PL14, 0xdc, 0x18,
+ MA35_MUX(0x0, "GPL14"),
+ MA35_MUX(0x1, "EPWM0_CH2"),
+ MA35_MUX(0x2, "UART7_RXD"),
+ MA35_MUX(0x4, "CAN1_RXD"),
+ MA35_MUX(0x5, "SPI0_MOSI"),
+ MA35_MUX(0x6, "I2S1_DI"),
+ MA35_MUX(0x7, "SC1_RST"),
+ MA35_MUX(0x8, "EBI_AD2"),
+ MA35_MUX(0xb, "TM2"),
+ MA35_MUX(0xc, "INT0"),
+ MA35_MUX(0xd, "EBI_AD13")),
+ MA35_PIN(185, PL15, 0xdc, 0x1c,
+ MA35_MUX(0x0, "GPL15"),
+ MA35_MUX(0x1, "EPWM0_CH1"),
+ MA35_MUX(0x2, "UART7_TXD"),
+ MA35_MUX(0x3, "TRACE_CLK"),
+ MA35_MUX(0x4, "CAN1_TXD"),
+ MA35_MUX(0x5, "SPI0_MISO"),
+ MA35_MUX(0x6, "I2S1_DO"),
+ MA35_MUX(0x7, "SC1_PWR"),
+ MA35_MUX(0x8, "EBI_AD3"),
+ MA35_MUX(0xb, "TM2_EXT"),
+ MA35_MUX(0xc, "INT2"),
+ MA35_MUX(0xd, "EBI_AD14")),
+ MA35_PIN(186, PM0, 0xe0, 0x0,
+ MA35_MUX(0x0, "GPM0"),
+ MA35_MUX(0x4, "I2C4_SDA"),
+ MA35_MUX(0x6, "CCAP0_VSYNC"),
+ MA35_MUX(0x8, "EBI_AD3"),
+ MA35_MUX(0xa, "EBI_ADR3")),
+ MA35_PIN(187, PM1, 0xe0, 0x4,
+ MA35_MUX(0x0, "GPM1"),
+ MA35_MUX(0x4, "I2C4_SCL"),
+ MA35_MUX(0x5, "SPI3_I2SMCLK"),
+ MA35_MUX(0x6, "CCAP0_SFIELD"),
+ MA35_MUX(0x8, "EBI_AD4"),
+ MA35_MUX(0xa, "EBI_ADR4")),
+ MA35_PIN(188, PM2, 0xe0, 0x8,
+ MA35_MUX(0x0, "GPM2"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x6, "CCAP0_DATA0"),
+ MA35_MUX(0x8, "EBI_AD5"),
+ MA35_MUX(0xa, "EBI_ADR5")),
+ MA35_PIN(189, PM3, 0xe0, 0xc,
+ MA35_MUX(0x0, "GPM3"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x6, "CCAP0_DATA1"),
+ MA35_MUX(0x8, "EBI_AD6"),
+ MA35_MUX(0xa, "EBI_ADR6")),
+ MA35_PIN(190, PM4, 0xe0, 0x10,
+ MA35_MUX(0x0, "GPM4"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x6, "CCAP0_DATA2"),
+ MA35_MUX(0x8, "EBI_AD7"),
+ MA35_MUX(0xa, "EBI_ADR7")),
+ MA35_PIN(191, PM5, 0xe0, 0x14,
+ MA35_MUX(0x0, "GPM5"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x6, "CCAP0_DATA3"),
+ MA35_MUX(0x8, "EBI_AD8"),
+ MA35_MUX(0xa, "EBI_ADR8")),
+ MA35_PIN(192, PM6, 0xe0, 0x18,
+ MA35_MUX(0x0, "GPM6"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x6, "CCAP0_DATA4"),
+ MA35_MUX(0x8, "EBI_AD9"),
+ MA35_MUX(0xa, "EBI_ADR9")),
+ MA35_PIN(193, PM7, 0xe0, 0x1c,
+ MA35_MUX(0x0, "GPM7"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x6, "CCAP0_DATA5"),
+ MA35_MUX(0x8, "EBI_AD10"),
+ MA35_MUX(0xa, "EBI_ADR10")),
+ MA35_PIN(194, PM8, 0xe4, 0x0,
+ MA35_MUX(0x0, "GPM8"),
+ MA35_MUX(0x4, "I2C0_SDA"),
+ MA35_MUX(0x6, "CCAP0_DATA6"),
+ MA35_MUX(0x8, "EBI_AD11"),
+ MA35_MUX(0xa, "EBI_ADR11")),
+ MA35_PIN(195, PM9, 0xe4, 0x4,
+ MA35_MUX(0x0, "GPM9"),
+ MA35_MUX(0x4, "I2C0_SCL"),
+ MA35_MUX(0x6, "CCAP0_DATA7"),
+ MA35_MUX(0x8, "EBI_AD12"),
+ MA35_MUX(0xa, "EBI_ADR12")),
+ MA35_PIN(196, PM10, 0xe4, 0x8,
+ MA35_MUX(0x0, "GPM10"),
+ MA35_MUX(0x1, "EPWM1_CH2"),
+ MA35_MUX(0x3, "CAN2_RXD"),
+ MA35_MUX(0x5, "SPI3_SS0"),
+ MA35_MUX(0x6, "CCAP0_DATA8"),
+ MA35_MUX(0x7, "SPI2_I2SMCLK"),
+ MA35_MUX(0x8, "EBI_AD13"),
+ MA35_MUX(0xa, "EBI_ADR13")),
+ MA35_PIN(197, PM11, 0xe4, 0xc,
+ MA35_MUX(0x0, "GPM11"),
+ MA35_MUX(0x1, "EPWM1_CH3"),
+ MA35_MUX(0x3, "CAN2_TXD"),
+ MA35_MUX(0x5, "SPI3_SS1"),
+ MA35_MUX(0x6, "CCAP0_DATA9"),
+ MA35_MUX(0x7, "SPI2_SS1"),
+ MA35_MUX(0x8, "EBI_AD14"),
+ MA35_MUX(0xa, "EBI_ADR14")),
+ MA35_PIN(198, PM12, 0xe4, 0x10,
+ MA35_MUX(0x0, "GPM12"),
+ MA35_MUX(0x1, "EPWM1_CH4"),
+ MA35_MUX(0x2, "UART10_nCTS"),
+ MA35_MUX(0x3, "TRACE_DATA0"),
+ MA35_MUX(0x4, "UART11_RXD"),
+ MA35_MUX(0x5, "I2C2_SDA"),
+ MA35_MUX(0x7, "SC1_nCD"),
+ MA35_MUX(0x8, "EBI_AD8"),
+ MA35_MUX(0x9, "I2S1_MCLK"),
+ MA35_MUX(0xb, "TM8")),
+ MA35_PIN(199, PM13, 0xe4, 0x14,
+ MA35_MUX(0x0, "GPM13"),
+ MA35_MUX(0x1, "EPWM1_CH5"),
+ MA35_MUX(0x2, "UART10_nRTS"),
+ MA35_MUX(0x3, "TRACE_DATA1"),
+ MA35_MUX(0x4, "UART11_TXD"),
+ MA35_MUX(0x5, "I2C2_SCL"),
+ MA35_MUX(0x8, "EBI_AD9"),
+ MA35_MUX(0x9, "ECAP1_IC0"),
+ MA35_MUX(0xb, "TM8_EXT")),
+ MA35_PIN(200, PM14, 0xe4, 0x18,
+ MA35_MUX(0x0, "GPM14"),
+ MA35_MUX(0x1, "EPWM1_BRAKE0"),
+ MA35_MUX(0x2, "UART10_RXD"),
+ MA35_MUX(0x3, "TRACE_DATA2"),
+ MA35_MUX(0x4, "CAN2_RXD"),
+ MA35_MUX(0x6, "I2C3_SDA"),
+ MA35_MUX(0x8, "EBI_AD10"),
+ MA35_MUX(0x9, "ECAP1_IC1"),
+ MA35_MUX(0xb, "TM10"),
+ MA35_MUX(0xd, "INT1")),
+ MA35_PIN(201, PM15, 0xe4, 0x1c,
+ MA35_MUX(0x0, "GPM15"),
+ MA35_MUX(0x1, "EPWM1_BRAKE1"),
+ MA35_MUX(0x2, "UART10_TXD"),
+ MA35_MUX(0x3, "TRACE_DATA3"),
+ MA35_MUX(0x4, "CAN2_TXD"),
+ MA35_MUX(0x6, "I2C3_SCL"),
+ MA35_MUX(0x8, "EBI_AD11"),
+ MA35_MUX(0x9, "ECAP1_IC2"),
+ MA35_MUX(0xb, "TM10_EXT"),
+ MA35_MUX(0xd, "INT2")),
+ MA35_PIN(202, PN0, 0xe8, 0x0,
+ MA35_MUX(0x0, "GPN0"),
+ MA35_MUX(0x4, "I2C2_SDA"),
+ MA35_MUX(0x6, "CCAP1_DATA0")),
+ MA35_PIN(203, PN1, 0xe8, 0x4,
+ MA35_MUX(0x0, "GPN1"),
+ MA35_MUX(0x4, "I2C2_SCL"),
+ MA35_MUX(0x6, "CCAP1_DATA1")),
+ MA35_PIN(204, PN2, 0xe8, 0x8,
+ MA35_MUX(0x0, "GPN2"),
+ MA35_MUX(0x3, "CAN0_RXD"),
+ MA35_MUX(0x6, "CCAP1_DATA2")),
+ MA35_PIN(205, PN3, 0xe8, 0xc,
+ MA35_MUX(0x0, "GPN3"),
+ MA35_MUX(0x3, "CAN0_TXD"),
+ MA35_MUX(0x6, "CCAP1_DATA3")),
+ MA35_PIN(206, PN4, 0xe8, 0x10,
+ MA35_MUX(0x0, "GPN4"),
+ MA35_MUX(0x4, "I2C1_SDA"),
+ MA35_MUX(0x6, "CCAP1_DATA4")),
+ MA35_PIN(207, PN5, 0xe8, 0x14,
+ MA35_MUX(0x0, "GPN5"),
+ MA35_MUX(0x4, "I2C1_SCL"),
+ MA35_MUX(0x6, "CCAP1_DATA5")),
+ MA35_PIN(208, PN6, 0xe8, 0x18,
+ MA35_MUX(0x0, "GPN6"),
+ MA35_MUX(0x3, "CAN1_RXD"),
+ MA35_MUX(0x6, "CCAP1_DATA6")),
+ MA35_PIN(209, PN7, 0xe8, 0x1c,
+ MA35_MUX(0x0, "GPN7"),
+ MA35_MUX(0x3, "CAN1_TXD"),
+ MA35_MUX(0x6, "CCAP1_DATA7")),
+ MA35_PIN(210, PN10, 0xec, 0x8,
+ MA35_MUX(0x0, "GPN10"),
+ MA35_MUX(0x3, "CAN2_RXD"),
+ MA35_MUX(0x6, "CCAP1_SCLK")),
+ MA35_PIN(211, PN11, 0xec, 0xc,
+ MA35_MUX(0x0, "GPN11"),
+ MA35_MUX(0x3, "CAN2_TXD"),
+ MA35_MUX(0x6, "CCAP1_PIXCLK")),
+ MA35_PIN(212, PN12, 0xec, 0x10,
+ MA35_MUX(0x0, "GPN12"),
+ MA35_MUX(0x2, "UART6_nCTS"),
+ MA35_MUX(0x3, "UART12_RXD"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x6, "CCAP1_HSYNC")),
+ MA35_PIN(213, PN13, 0xec, 0x14,
+ MA35_MUX(0x0, "GPN13"),
+ MA35_MUX(0x2, "UART6_nRTS"),
+ MA35_MUX(0x3, "UART12_TXD"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x6, "CCAP1_VSYNC")),
+ MA35_PIN(214, PN14, 0xec, 0x18,
+ MA35_MUX(0x0, "GPN14"),
+ MA35_MUX(0x2, "UART6_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x5, "SPI1_SS1"),
+ MA35_MUX(0x6, "CCAP1_SFIELD"),
+ MA35_MUX(0x7, "SPI1_I2SMCLK")),
+ MA35_PIN(215, PN15, 0xec, 0x1c,
+ MA35_MUX(0x0, "GPN15"),
+ MA35_MUX(0x1, "EPWM2_CH4"),
+ MA35_MUX(0x2, "UART6_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x5, "I2S0_MCLK"),
+ MA35_MUX(0x6, "SPI1_SS1"),
+ MA35_MUX(0x7, "SPI1_I2SMCLK"),
+ MA35_MUX(0x8, "SC0_nCD"),
+ MA35_MUX(0x9, "EADC0_ST"),
+ MA35_MUX(0xa, "CLKO"),
+ MA35_MUX(0xb, "TM6")),
+ MA35_PIN(216, PN8, 0xec, 0x0,
+ MA35_MUX(0x0, "GPN8"),
+ MA35_MUX(0x1, "EPWM2_CH4"),
+ MA35_MUX(0x4, "I2C0_SDA"),
+ MA35_MUX(0x5, "SPI2_I2SMCLK"),
+ MA35_MUX(0x6, "CCAP1_DATA8")),
+ MA35_PIN(217, PN9, 0xec, 0x4,
+ MA35_MUX(0x0, "GPN9"),
+ MA35_MUX(0x1, "EPWM2_CH5"),
+ MA35_MUX(0x4, "I2C0_SCL"),
+ MA35_MUX(0x5, "SPI1_I2SMCLK"),
+ MA35_MUX(0x6, "CCAP1_DATA9")),
+ MA35_PIN(218, PN10, 0xec, 0x8,
+ MA35_MUX(0x0, "GPN10"),
+ MA35_MUX(0x3, "CAN2_RXD"),
+ MA35_MUX(0x4, "USBHL2_DM"),
+ MA35_MUX(0x6, "CCAP1_SCLK")),
+ MA35_PIN(219, PN11, 0xec, 0xc,
+ MA35_MUX(0x0, "GPN11"),
+ MA35_MUX(0x3, "CAN2_TXD"),
+ MA35_MUX(0x4, "USBHL2_DP"),
+ MA35_MUX(0x6, "CCAP1_PIXCLK")),
+ MA35_PIN(220, PN12, 0xec, 0x10,
+ MA35_MUX(0x0, "GPN12"),
+ MA35_MUX(0x2, "UART6_nCTS"),
+ MA35_MUX(0x3, "UART12_RXD"),
+ MA35_MUX(0x4, "I2C5_SDA"),
+ MA35_MUX(0x6, "CCAP1_HSYNC")),
+ MA35_PIN(221, PN13, 0xec, 0x14,
+ MA35_MUX(0x0, "GPN13"),
+ MA35_MUX(0x2, "UART6_nRTS"),
+ MA35_MUX(0x3, "UART12_TXD"),
+ MA35_MUX(0x4, "I2C5_SCL"),
+ MA35_MUX(0x6, "CCAP1_VSYNC")),
+ MA35_PIN(222, PN14, 0xec, 0x18,
+ MA35_MUX(0x0, "GPN14"),
+ MA35_MUX(0x2, "UART6_RXD"),
+ MA35_MUX(0x3, "CAN3_RXD"),
+ MA35_MUX(0x4, "USBHL3_DM"),
+ MA35_MUX(0x5, "SPI1_SS1"),
+ MA35_MUX(0x6, "CCAP1_SFIELD"),
+ MA35_MUX(0x7, "SPI1_I2SMCLK")),
+ MA35_PIN(223, PN15, 0xec, 0x1c,
+ MA35_MUX(0x0, "GPN15"),
+ MA35_MUX(0x1, "EPWM2_CH4"),
+ MA35_MUX(0x2, "UART6_TXD"),
+ MA35_MUX(0x3, "CAN3_TXD"),
+ MA35_MUX(0x4, "USBHL3_DP"),
+ MA35_MUX(0x5, "I2S0_MCLK"),
+ MA35_MUX(0x6, "SPI1_SS1"),
+ MA35_MUX(0x7, "SPI1_I2SMCLK"),
+ MA35_MUX(0x8, "SC0_nCD"),
+ MA35_MUX(0x9, "EADC0_ST"),
+ MA35_MUX(0xa, "CLKO"),
+ MA35_MUX(0xb, "TM6")),
+};
+
+static int ma35d1_get_pin_num(int offset, int shift)
+{
+ return (offset - 0x80) * 2 + shift / 4;
+}
+
+static struct ma35_pinctrl_soc_info ma35d1_pinctrl_info = {
+ .pins = ma35d1_pins,
+ .npins = ARRAY_SIZE(ma35d1_pins),
+ .get_pin_num = ma35d1_get_pin_num,
+};
+
+static DEFINE_NOIRQ_DEV_PM_OPS(ma35_pinctrl_pm_ops, ma35_pinctrl_suspend, ma35_pinctrl_resume);
+
+static int ma35d1_pinctrl_probe(struct platform_device *pdev)
+{
+ return ma35_pinctrl_probe(pdev, &ma35d1_pinctrl_info);
+}
+
+static const struct of_device_id ma35d1_pinctrl_of_match[] = {
+ { .compatible = "nuvoton,ma35d1-pinctrl" },
+ { },
+};
+
+static struct platform_driver ma35d1_pinctrl_driver = {
+ .probe = ma35d1_pinctrl_probe,
+ .driver = {
+ .name = "ma35d1-pinctrl",
+ .pm = pm_sleep_ptr(&ma35_pinctrl_pm_ops),
+ .of_match_table = ma35d1_pinctrl_of_match,
+ },
+};
+
+static int __init ma35d1_pinctrl_init(void)
+{
+ return platform_driver_register(&ma35d1_pinctrl_driver);
+}
+arch_initcall(ma35d1_pinctrl_init);
+
+MODULE_AUTHOR("schung@nuvoton.com");
+MODULE_DESCRIPTION("Nuvoton MA35D1 pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.34.1
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^ permalink raw reply related [relevance 1%]
* Re: [PATCH v4 4/5] PCI: imx6: Convert to agnostic GPIO API
2024-05-06 14:20 11% ` [PATCH v4 4/5] PCI: imx6: Convert " Andy Shevchenko
@ 2024-05-07 19:22 0% ` Frank Li
2024-05-09 1:24 0% ` Hongxing Zhu
1 sibling, 0 replies; 200+ results
From: Frank Li @ 2024-05-07 19:22 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Manivannan Sadhasivam, Krzysztof Wilczyński, linux-omap,
linux-pci, linux-arm-kernel, linux-kernel, imx, linux-amlogic,
linux-arm-msm, linux-tegra, Vignesh Raghavendra,
Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár, Linus Walleij
On Mon, May 06, 2024 at 05:20:40PM +0300, Andy Shevchenko wrote:
> The of_gpio.h is going to be removed. In preparation of that convert
> the driver to the agnostic API.
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
Can I include your patch in my imx6 pci improvement patches
https://lore.kernel.org/linux-pci/20240507-pci2_upstream-v4-0-e8c80d874057@nxp.com/T/#t
There is patch, which rename function from imx6 -> imx. That will avoid
conflict.
Frank Li
> drivers/pci/controller/dwc/pci-imx6.c | 36 ++++++++-------------------
> 1 file changed, 10 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 917c69edee1d..62a4994c5501 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -11,14 +11,13 @@
> #include <linux/bitfield.h>
> #include <linux/clk.h>
> #include <linux/delay.h>
> -#include <linux/gpio.h>
> +#include <linux/gpio/consumer.h>
> #include <linux/kernel.h>
> #include <linux/mfd/syscon.h>
> #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
> #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> #include <linux/module.h>
> #include <linux/of.h>
> -#include <linux/of_gpio.h>
> #include <linux/of_address.h>
> #include <linux/pci.h>
> #include <linux/platform_device.h>
> @@ -107,8 +106,7 @@ struct imx6_pcie_drvdata {
>
> struct imx6_pcie {
> struct dw_pcie *pci;
> - int reset_gpio;
> - bool gpio_active_high;
> + struct gpio_desc *reset_gpiod;
> bool link_is_up;
> struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS];
> struct regmap *iomuxc_gpr;
> @@ -721,9 +719,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
> }
>
> /* Some boards don't have PCIe reset GPIO. */
> - if (gpio_is_valid(imx6_pcie->reset_gpio))
> - gpio_set_value_cansleep(imx6_pcie->reset_gpio,
> - imx6_pcie->gpio_active_high);
> + gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 1);
> }
>
> static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> @@ -771,10 +767,9 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> }
>
> /* Some boards don't have PCIe reset GPIO. */
> - if (gpio_is_valid(imx6_pcie->reset_gpio)) {
> + if (imx6_pcie->reset_gpiod) {
> msleep(100);
> - gpio_set_value_cansleep(imx6_pcie->reset_gpio,
> - !imx6_pcie->gpio_active_high);
> + gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 0);
> /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
> msleep(100);
> }
> @@ -1285,22 +1280,11 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> return PTR_ERR(pci->dbi_base);
>
> /* Fetch GPIOs */
> - imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
> - imx6_pcie->gpio_active_high = of_property_read_bool(node,
> - "reset-gpio-active-high");
> - if (gpio_is_valid(imx6_pcie->reset_gpio)) {
> - ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
> - imx6_pcie->gpio_active_high ?
> - GPIOF_OUT_INIT_HIGH :
> - GPIOF_OUT_INIT_LOW,
> - "PCIe reset");
> - if (ret) {
> - dev_err(dev, "unable to get reset gpio\n");
> - return ret;
> - }
> - } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
> - return imx6_pcie->reset_gpio;
> - }
> + imx6_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
> + if (IS_ERR(imx6_pcie->reset_gpiod))
> + return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod),
> + "unable to get reset gpio\n");
> + gpiod_set_consumer_name(imx6_pcie->reset_gpiod, "PCIe reset");
>
> if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS)
> return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
> --
> 2.43.0.rc1.1336.g36b5255a03ac
>
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^ permalink raw reply [relevance 0%]
* [PATCH v4 11/12] PCI: imx6: Call: Common PHY API to set mode, speed, and submode
` (2 preceding siblings ...)
2024-05-07 18:45 10% ` [PATCH v4 05/12] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li
@ 2024-05-07 18:45 5% ` Frank Li
3 siblings, 0 replies; 200+ results
From: Frank Li @ 2024-05-07 18:45 UTC (permalink / raw)
To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley
Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree,
Frank Li
Invoke the common PHY API to configure mode, speed, and submode. While
these functions are optional in the PHY interface, they are necessary for
certain PHY drivers. Lack of support for these functions in a PHY driver
does not cause harm.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 9d53b545540c6..df623977d8fe6 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -30,6 +30,7 @@
#include <linux/interrupt.h>
#include <linux/reset.h>
#include <linux/phy/phy.h>
+#include <linux/phy/pcie.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
@@ -308,6 +309,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
id = imx_pcie->controller_id;
+ /* If mode_mask[0] is 0, means use phy driver to set mode */
+ if (!drvdata->mode_mask[0])
+ return;
+
/* If mode_mask[id] is zero, means each controller have its individual gpr */
if (!drvdata->mode_mask[id])
id = 0;
@@ -887,6 +892,7 @@ static void imx_pcie_ltssm_enable(struct device *dev)
struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
+ phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB);
if (drvdata->ltssm_mask)
regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
drvdata->ltssm_mask);
@@ -899,6 +905,7 @@ static void imx_pcie_ltssm_disable(struct device *dev)
struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
+ phy_set_speed(imx_pcie->phy, 0);
if (drvdata->ltssm_mask)
regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
drvdata->ltssm_mask, 0);
@@ -1034,6 +1041,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
goto err_clk_disable;
}
+ ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
+ if (ret) {
+ dev_err(dev, "unable to set pcie PHY mode\n");
+ goto err_phy_off;
+ }
+
ret = phy_power_on(imx_pcie->phy);
if (ret) {
dev_err(dev, "waiting for PHY ready timeout!\n");
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* [PATCH v4 04/12] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
2024-05-07 18:45 7% ` [PATCH v4 03/12] PCI: imx6: Rename imx6_* with imx_* Frank Li
@ 2024-05-07 18:45 5% ` Frank Li
2024-05-07 18:45 10% ` [PATCH v4 05/12] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li
2024-05-07 18:45 5% ` [PATCH v4 11/12] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Frank Li
3 siblings, 0 replies; 200+ results
From: Frank Li @ 2024-05-07 18:45 UTC (permalink / raw)
To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley
Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree,
Frank Li
Instead of using the switch case statement to enable/disable the reference
clock handled by this driver itself, let's introduce a new callback
set_ref_clk() and define it for platforms that require it. This simplifies
the code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 112 ++++++++++++++++------------------
1 file changed, 52 insertions(+), 60 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index e93070d60df52..cf1b487b3f625 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -103,6 +103,7 @@ struct imx_pcie_drvdata {
const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
const struct pci_epc_features *epc_features;
int (*init_phy)(struct imx_pcie *pcie);
+ int (*set_ref_clk)(struct imx_pcie *pcie, bool enable);
};
struct imx_pcie {
@@ -585,21 +586,19 @@ static int imx_pcie_attach_pd(struct device *dev)
return 0;
}
-static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
+static int imx6sx_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
{
- unsigned int offset;
- int ret = 0;
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
+ enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
- switch (imx_pcie->drvdata->variant) {
- case IMX6SX:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
- IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
- break;
- case IMX6QP:
- case IMX6Q:
+ return 0;
+}
+
+static int imx6q_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
+{
+ if (enable) {
/* power up core phy and enable ref clock */
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0);
/*
* the async reset input need ref clock to sync internally,
* when the ref clock comes after reset, internal synced
@@ -608,54 +607,34 @@ static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
*/
usleep_range(10, 100);
regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
- break;
- case IMX7D:
- case IMX95:
- case IMX95_EP:
- break;
- case IMX8MM:
- case IMX8MM_EP:
- case IMX8MQ:
- case IMX8MQ_EP:
- case IMX8MP:
- case IMX8MP_EP:
- offset = imx_pcie_grp_offset(imx_pcie);
- /*
- * Set the over ride low and enabled
- * make sure that REF_CLK is turned on.
- */
- regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
- IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
- 0);
- regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
- IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
- IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
- break;
+ IMX6Q_GPR1_PCIE_REF_CLK_EN, IMX6Q_GPR1_PCIE_REF_CLK_EN);
+ } else {
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD);
}
- return ret;
+ return 0;
}
-static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie)
+static int imx8mm_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
{
- switch (imx_pcie->drvdata->variant) {
- case IMX6QP:
- case IMX6Q:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_TEST_PD,
- IMX6Q_GPR1_PCIE_TEST_PD);
- break;
- case IMX7D:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
- IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
- IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
- break;
- default:
- break;
- }
+ int offset = imx_pcie_grp_offset(imx_pcie);
+
+ /* Set the over ride low and enabled make sure that REF_CLK is turned on.*/
+ regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
+ enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
+ enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0);
+ return 0;
+}
+
+static int imx7d_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
+{
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
+ enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
+ return 0;
}
static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
@@ -668,10 +647,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
if (ret)
return ret;
- ret = imx_pcie_enable_ref_clk(imx_pcie);
- if (ret) {
- dev_err(dev, "unable to enable pcie ref clock\n");
- goto err_ref_clk;
+ if (imx_pcie->drvdata->set_ref_clk) {
+ ret = imx_pcie->drvdata->set_ref_clk(imx_pcie, true);
+ if (ret) {
+ dev_err(dev, "Failed to enable PCIe REFCLK\n");
+ goto err_ref_clk;
+ }
}
/* allow the clocks to stabilize */
@@ -686,7 +667,8 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
{
- imx_pcie_disable_ref_clk(imx_pcie);
+ if (imx_pcie->drvdata->set_ref_clk)
+ imx_pcie->drvdata->set_ref_clk(imx_pcie, false);
clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
}
@@ -1465,6 +1447,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx_pcie_init_phy,
+ .set_ref_clk = imx6q_pcie_set_ref_clk,
},
[IMX6SX] = {
.variant = IMX6SX,
@@ -1479,6 +1462,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx6sx_pcie_init_phy,
+ .set_ref_clk = imx6sx_pcie_set_ref_clk,
},
[IMX6QP] = {
.variant = IMX6QP,
@@ -1494,6 +1478,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx_pcie_init_phy,
+ .set_ref_clk = imx6q_pcie_set_ref_clk,
},
[IMX7D] = {
.variant = IMX7D,
@@ -1506,6 +1491,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx7d_pcie_init_phy,
+ .set_ref_clk = imx7d_pcie_set_ref_clk,
},
[IMX8MQ] = {
.variant = IMX8MQ,
@@ -1519,6 +1505,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[1] = IOMUXC_GPR12,
.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
.init_phy = imx8mq_pcie_init_phy,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX8MM] = {
.variant = IMX8MM,
@@ -1530,6 +1517,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX8MP] = {
.variant = IMX8MP,
@@ -1541,6 +1529,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX95] = {
.variant = IMX95,
@@ -1567,6 +1556,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
.epc_features = &imx8m_pcie_epc_features,
.init_phy = imx8mq_pcie_init_phy,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX8MM_EP] = {
.variant = IMX8MM_EP,
@@ -1579,6 +1569,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.epc_features = &imx8m_pcie_epc_features,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX8MP_EP] = {
.variant = IMX8MP_EP,
@@ -1591,6 +1582,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.epc_features = &imx8m_pcie_epc_features,
+ .set_ref_clk = imx8mm_pcie_set_ref_clk,
},
[IMX95_EP] = {
.variant = IMX95_EP,
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* [PATCH v4 03/12] PCI: imx6: Rename imx6_* with imx_*
@ 2024-05-07 18:45 7% ` Frank Li
2024-05-07 18:45 5% ` [PATCH v4 04/12] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li
` (2 subsequent siblings)
3 siblings, 0 replies; 200+ results
From: Frank Li @ 2024-05-07 18:45 UTC (permalink / raw)
To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley
Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree,
Frank Li
Since this driver has evolved to support other i.MX SoCs such as i.MX7/8/9,
let's rename the 'imx6' prefix to 'imx' to avoid confusion. But the driver
name is left unchanged to avoid breaking userspace scripts
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 760 +++++++++++++++++-----------------
1 file changed, 380 insertions(+), 380 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 6c4d25b92225e..e93070d60df52 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -55,9 +55,9 @@
#define IMX95_PE0_GEN_CTRL_3 0x1058
#define IMX95_PCIE_LTSSM_EN BIT(0)
-#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
+#define to_imx_pcie(x) dev_get_drvdata((x)->dev)
-enum imx6_pcie_variants {
+enum imx_pcie_variants {
IMX6Q,
IMX6SX,
IMX6QP,
@@ -72,25 +72,25 @@ enum imx6_pcie_variants {
IMX95_EP,
};
-#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
-#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
-#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
-#define IMX6_PCIE_FLAG_HAS_PHYDRV BIT(3)
-#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4)
-#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5)
-#define IMX6_PCIE_FLAG_HAS_SERDES BIT(6)
-#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7)
+#define IMX_PCIE_FLAG_IMX_PHY BIT(0)
+#define IMX_PCIE_FLAG_IMX_SPEED_CHANGE BIT(1)
+#define IMX_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
+#define IMX_PCIE_FLAG_HAS_PHYDRV BIT(3)
+#define IMX_PCIE_FLAG_HAS_APP_RESET BIT(4)
+#define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5)
+#define IMX_PCIE_FLAG_HAS_SERDES BIT(6)
+#define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7)
-#define imx6_check_flag(pci, val) (pci->drvdata->flags & val)
+#define imx_check_flag(pci, val) (pci->drvdata->flags & val)
-#define IMX6_PCIE_MAX_CLKS 6
+#define IMX_PCIE_MAX_CLKS 6
-#define IMX6_PCIE_MAX_INSTANCES 2
+#define IMX_PCIE_MAX_INSTANCES 2
-struct imx6_pcie;
+struct imx_pcie;
-struct imx6_pcie_drvdata {
- enum imx6_pcie_variants variant;
+struct imx_pcie_drvdata {
+ enum imx_pcie_variants variant;
enum dw_pcie_device_mode mode;
u32 flags;
int dbi_length;
@@ -99,18 +99,18 @@ struct imx6_pcie_drvdata {
const u32 clks_cnt;
const u32 ltssm_off;
const u32 ltssm_mask;
- const u32 mode_off[IMX6_PCIE_MAX_INSTANCES];
- const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES];
+ const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
+ const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
const struct pci_epc_features *epc_features;
- int (*init_phy)(struct imx6_pcie *pcie);
+ int (*init_phy)(struct imx_pcie *pcie);
};
-struct imx6_pcie {
+struct imx_pcie {
struct dw_pcie *pci;
int reset_gpio;
bool gpio_active_high;
bool link_is_up;
- struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS];
+ struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS];
struct regmap *iomuxc_gpr;
u16 msi_ctrl;
u32 controller_id;
@@ -131,7 +131,7 @@ struct imx6_pcie {
/* power domain for pcie phy */
struct device *pd_pcie_phy;
struct phy *phy;
- const struct imx6_pcie_drvdata *drvdata;
+ const struct imx_pcie_drvdata *drvdata;
};
/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
@@ -186,28 +186,28 @@ struct imx6_pcie {
#define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5)
#define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3)
-static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
+static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
{
- WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
- imx6_pcie->drvdata->variant != IMX8MQ_EP &&
- imx6_pcie->drvdata->variant != IMX8MM &&
- imx6_pcie->drvdata->variant != IMX8MM_EP &&
- imx6_pcie->drvdata->variant != IMX8MP &&
- imx6_pcie->drvdata->variant != IMX8MP_EP);
- return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
+ WARN_ON(imx_pcie->drvdata->variant != IMX8MQ &&
+ imx_pcie->drvdata->variant != IMX8MQ_EP &&
+ imx_pcie->drvdata->variant != IMX8MM &&
+ imx_pcie->drvdata->variant != IMX8MM_EP &&
+ imx_pcie->drvdata->variant != IMX8MP &&
+ imx_pcie->drvdata->variant != IMX8MP_EP);
+ return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
}
-static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
{
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX95_PCIE_SS_RW_REG_0,
IMX95_PCIE_PHY_CR_PARA_SEL,
IMX95_PCIE_PHY_CR_PARA_SEL);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX95_PCIE_PHY_GEN_CTRL,
IMX95_PCIE_REF_USE_PAD, 0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX95_PCIE_SS_RW_REG_0,
IMX95_PCIE_REF_CLKEN,
IMX95_PCIE_REF_CLKEN);
@@ -215,9 +215,9 @@ static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie)
return 0;
}
-static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
{
- const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
+ const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
unsigned int mask, val, mode, id;
if (drvdata->mode == DW_PCIE_EP_TYPE)
@@ -225,7 +225,7 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
else
mode = PCI_EXP_TYPE_ROOT_PORT;
- id = imx6_pcie->controller_id;
+ id = imx_pcie->controller_id;
/* If mode_mask[id] is zero, means each controller have its individual gpr */
if (!drvdata->mode_mask[id])
@@ -234,12 +234,12 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
mask = drvdata->mode_mask[id];
val = mode << (ffs(mask) - 1);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
}
-static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
+static int pcie_phy_poll_ack(struct imx_pcie *imx_pcie, bool exp_val)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
bool val;
u32 max_iterations = 10;
u32 wait_counter = 0;
@@ -258,9 +258,9 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
return -ETIMEDOUT;
}
-static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
+static int pcie_phy_wait_ack(struct imx_pcie *imx_pcie, int addr)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
u32 val;
int ret;
@@ -270,24 +270,24 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
val |= PCIE_PHY_CTRL_CAP_ADR;
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
- ret = pcie_phy_poll_ack(imx6_pcie, true);
+ ret = pcie_phy_poll_ack(imx_pcie, true);
if (ret)
return ret;
val = PCIE_PHY_CTRL_DATA(addr);
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
- return pcie_phy_poll_ack(imx6_pcie, false);
+ return pcie_phy_poll_ack(imx_pcie, false);
}
/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
-static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
+static int pcie_phy_read(struct imx_pcie *imx_pcie, int addr, u16 *data)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
u32 phy_ctl;
int ret;
- ret = pcie_phy_wait_ack(imx6_pcie, addr);
+ ret = pcie_phy_wait_ack(imx_pcie, addr);
if (ret)
return ret;
@@ -295,7 +295,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
phy_ctl = PCIE_PHY_CTRL_RD;
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
- ret = pcie_phy_poll_ack(imx6_pcie, true);
+ ret = pcie_phy_poll_ack(imx_pcie, true);
if (ret)
return ret;
@@ -304,18 +304,18 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
/* deassert Read signal */
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
- return pcie_phy_poll_ack(imx6_pcie, false);
+ return pcie_phy_poll_ack(imx_pcie, false);
}
-static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
+static int pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
u32 var;
int ret;
/* write addr */
/* cap addr */
- ret = pcie_phy_wait_ack(imx6_pcie, addr);
+ ret = pcie_phy_wait_ack(imx_pcie, addr);
if (ret)
return ret;
@@ -326,7 +326,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
var |= PCIE_PHY_CTRL_CAP_DAT;
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
- ret = pcie_phy_poll_ack(imx6_pcie, true);
+ ret = pcie_phy_poll_ack(imx_pcie, true);
if (ret)
return ret;
@@ -335,7 +335,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
/* wait for ack de-assertion */
- ret = pcie_phy_poll_ack(imx6_pcie, false);
+ ret = pcie_phy_poll_ack(imx_pcie, false);
if (ret)
return ret;
@@ -344,7 +344,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
/* wait for ack */
- ret = pcie_phy_poll_ack(imx6_pcie, true);
+ ret = pcie_phy_poll_ack(imx_pcie, true);
if (ret)
return ret;
@@ -353,7 +353,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
/* wait for ack de-assertion */
- ret = pcie_phy_poll_ack(imx6_pcie, false);
+ ret = pcie_phy_poll_ack(imx_pcie, false);
if (ret)
return ret;
@@ -362,74 +362,74 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
return 0;
}
-static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie)
{
/* TODO: Currently this code assumes external oscillator is being used */
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
- imx6_pcie_grp_offset(imx6_pcie),
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
+ imx_pcie_grp_offset(imx_pcie),
IMX8MQ_GPR_PCIE_REF_USE_PAD,
IMX8MQ_GPR_PCIE_REF_USE_PAD);
/*
* Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is
* supplied by 3.3V, the VREG_BYPASS should be cleared to zero.
*/
- if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000)
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
- imx6_pcie_grp_offset(imx6_pcie),
+ if (imx_pcie->vph && regulator_get_voltage(imx_pcie->vph) > 3000000)
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
+ imx_pcie_grp_offset(imx_pcie),
IMX8MQ_GPR_PCIE_VREG_BYPASS,
0);
return 0;
}
-static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie)
{
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
return 0;
}
-static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_init_phy(struct imx_pcie *imx_pcie)
{
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
/* configure constant input signal to the pcie ctrl and phy */
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_DEEMPH_GEN1,
- imx6_pcie->tx_deemph_gen1 << 0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ imx_pcie->tx_deemph_gen1 << 0);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
- imx6_pcie->tx_deemph_gen2_3p5db << 6);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ imx_pcie->tx_deemph_gen2_3p5db << 6);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
- imx6_pcie->tx_deemph_gen2_6db << 12);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ imx_pcie->tx_deemph_gen2_6db << 12);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_SWING_FULL,
- imx6_pcie->tx_swing_full << 18);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ imx_pcie->tx_swing_full << 18);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_SWING_LOW,
- imx6_pcie->tx_swing_low << 25);
+ imx_pcie->tx_swing_low << 25);
return 0;
}
-static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+static int imx6sx_pcie_init_phy(struct imx_pcie *imx_pcie)
{
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2);
- return imx6_pcie_init_phy(imx6_pcie);
+ return imx_pcie_init_phy(imx_pcie);
}
-static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
+static void imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
{
u32 val;
- struct device *dev = imx6_pcie->pci->dev;
+ struct device *dev = imx_pcie->pci->dev;
- if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
+ if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
IOMUXC_GPR22, val,
val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
PHY_PLL_LOCK_WAIT_USLEEP_MAX,
@@ -437,19 +437,19 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
dev_err(dev, "PCIe PLL lock timeout\n");
}
-static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
+static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie)
{
unsigned long phy_rate = 0;
int mult, div;
u16 val;
int i;
- if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
+ if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY))
return 0;
- for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++)
- if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0)
- phy_rate = clk_get_rate(imx6_pcie->clks[i].clk);
+ for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++)
+ if (strncmp(imx_pcie->clks[i].id, "pcie_phy", 8) == 0)
+ phy_rate = clk_get_rate(imx_pcie->clks[i].clk);
switch (phy_rate) {
case 125000000:
@@ -467,46 +467,46 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
div = 1;
break;
default:
- dev_err(imx6_pcie->pci->dev,
+ dev_err(imx_pcie->pci->dev,
"Unsupported PHY reference clock rate %lu\n", phy_rate);
return -EINVAL;
}
- pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
+ pcie_phy_read(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
- pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
+ pcie_phy_write(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
- pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
+ pcie_phy_read(imx_pcie, PCIE_PHY_ATEOVRD, &val);
val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
val |= PCIE_PHY_ATEOVRD_EN;
- pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
+ pcie_phy_write(imx_pcie, PCIE_PHY_ATEOVRD, val);
return 0;
}
-static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_reset_phy(struct imx_pcie *imx_pcie)
{
u16 tmp;
- if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
+ if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY))
return;
- pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
+ pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp);
tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
PHY_RX_OVRD_IN_LO_RX_PLL_EN);
- pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
+ pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp);
usleep_range(2000, 3000);
- pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
+ pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp);
tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
PHY_RX_OVRD_IN_LO_RX_PLL_EN);
- pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
+ pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp);
}
#ifdef CONFIG_ARM
@@ -545,22 +545,22 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
}
#endif
-static int imx6_pcie_attach_pd(struct device *dev)
+static int imx_pcie_attach_pd(struct device *dev)
{
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
struct device_link *link;
/* Do nothing when in a single power domain */
if (dev->pm_domain)
return 0;
- imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
- if (IS_ERR(imx6_pcie->pd_pcie))
- return PTR_ERR(imx6_pcie->pd_pcie);
+ imx_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
+ if (IS_ERR(imx_pcie->pd_pcie))
+ return PTR_ERR(imx_pcie->pd_pcie);
/* Do nothing when power domain missing */
- if (!imx6_pcie->pd_pcie)
+ if (!imx_pcie->pd_pcie)
return 0;
- link = device_link_add(dev, imx6_pcie->pd_pcie,
+ link = device_link_add(dev, imx_pcie->pd_pcie,
DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME |
DL_FLAG_RPM_ACTIVE);
@@ -569,11 +569,11 @@ static int imx6_pcie_attach_pd(struct device *dev)
return -EINVAL;
}
- imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
- if (IS_ERR(imx6_pcie->pd_pcie_phy))
- return PTR_ERR(imx6_pcie->pd_pcie_phy);
+ imx_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
+ if (IS_ERR(imx_pcie->pd_pcie_phy))
+ return PTR_ERR(imx_pcie->pd_pcie_phy);
- link = device_link_add(dev, imx6_pcie->pd_pcie_phy,
+ link = device_link_add(dev, imx_pcie->pd_pcie_phy,
DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME |
DL_FLAG_RPM_ACTIVE);
@@ -585,20 +585,20 @@ static int imx6_pcie_attach_pd(struct device *dev)
return 0;
}
-static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
{
unsigned int offset;
int ret = 0;
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX6SX:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
break;
case IMX6QP:
case IMX6Q:
/* power up core phy and enable ref clock */
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
/*
* the async reset input need ref clock to sync internally,
@@ -607,7 +607,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
* add one ~10us delay here.
*/
usleep_range(10, 100);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
break;
case IMX7D:
@@ -620,15 +620,15 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
case IMX8MQ_EP:
case IMX8MP:
case IMX8MP_EP:
- offset = imx6_pcie_grp_offset(imx6_pcie);
+ offset = imx_pcie_grp_offset(imx_pcie);
/*
* Set the over ride low and enabled
* make sure that REF_CLK is turned on.
*/
- regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
break;
@@ -637,19 +637,19 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
return ret;
}
-static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie)
{
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX6QP:
case IMX6Q:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD,
IMX6Q_GPR1_PCIE_TEST_PD);
break;
case IMX7D:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
break;
@@ -658,17 +658,17 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
}
}
-static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
struct device *dev = pci->dev;
int ret;
- ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
+ ret = clk_bulk_prepare_enable(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
if (ret)
return ret;
- ret = imx6_pcie_enable_ref_clk(imx6_pcie);
+ ret = imx_pcie_enable_ref_clk(imx_pcie);
if (ret) {
dev_err(dev, "unable to enable pcie ref clock\n");
goto err_ref_clk;
@@ -679,41 +679,41 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
return 0;
err_ref_clk:
- clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
+ clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
return ret;
}
-static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
{
- imx6_pcie_disable_ref_clk(imx6_pcie);
- clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
+ imx_pcie_disable_ref_clk(imx_pcie);
+ clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
}
-static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
{
- reset_control_assert(imx6_pcie->pciephy_reset);
- reset_control_assert(imx6_pcie->apps_reset);
+ reset_control_assert(imx_pcie->pciephy_reset);
+ reset_control_assert(imx_pcie->apps_reset);
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX6SX:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
/* Force PCIe PHY reset */
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
IMX6SX_GPR5_PCIE_BTNRST_RESET,
IMX6SX_GPR5_PCIE_BTNRST_RESET);
break;
case IMX6QP:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_SW_RST,
IMX6Q_GPR1_PCIE_SW_RST);
break;
case IMX6Q:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
break;
default:
@@ -721,47 +721,47 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
}
/* Some boards don't have PCIe reset GPIO. */
- if (gpio_is_valid(imx6_pcie->reset_gpio))
- gpio_set_value_cansleep(imx6_pcie->reset_gpio,
- imx6_pcie->gpio_active_high);
+ if (gpio_is_valid(imx_pcie->reset_gpio))
+ gpio_set_value_cansleep(imx_pcie->reset_gpio,
+ imx_pcie->gpio_active_high);
}
-static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
struct device *dev = pci->dev;
- reset_control_deassert(imx6_pcie->pciephy_reset);
+ reset_control_deassert(imx_pcie->pciephy_reset);
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX7D:
/* Workaround for ERR010728, failure of PCI-e PLL VCO to
* oscillate, especially when cold. This turns off "Duty-cycle
* Corrector" and other mysterious undocumented things.
*/
- if (likely(imx6_pcie->phy_base)) {
+ if (likely(imx_pcie->phy_base)) {
/* De-assert DCC_FB_EN */
writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
- imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
+ imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
/* Assert RX_EQS and RX_EQS_SEL */
writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
| PCIE_PHY_CMN_REG24_RX_EQ,
- imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
+ imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
/* Assert ATT_MODE */
writel(PCIE_PHY_CMN_REG26_ATT_MODE,
- imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
+ imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
} else {
dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
}
- imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
+ imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
break;
case IMX6SX:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
break;
case IMX6QP:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_SW_RST, 0);
usleep_range(200, 500);
@@ -771,10 +771,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
}
/* Some boards don't have PCIe reset GPIO. */
- if (gpio_is_valid(imx6_pcie->reset_gpio)) {
+ if (gpio_is_valid(imx_pcie->reset_gpio)) {
msleep(100);
- gpio_set_value_cansleep(imx6_pcie->reset_gpio,
- !imx6_pcie->gpio_active_high);
+ gpio_set_value_cansleep(imx_pcie->reset_gpio,
+ !imx_pcie->gpio_active_high);
/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
msleep(100);
}
@@ -782,9 +782,9 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
return 0;
}
-static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_wait_for_speed_change(struct imx_pcie *imx_pcie)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
struct device *dev = pci->dev;
u32 tmp;
unsigned int retries;
@@ -801,33 +801,33 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
return -ETIMEDOUT;
}
-static void imx6_pcie_ltssm_enable(struct device *dev)
+static void imx_pcie_ltssm_enable(struct device *dev)
{
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
if (drvdata->ltssm_mask)
- regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
drvdata->ltssm_mask);
- reset_control_deassert(imx6_pcie->apps_reset);
+ reset_control_deassert(imx_pcie->apps_reset);
}
-static void imx6_pcie_ltssm_disable(struct device *dev)
+static void imx_pcie_ltssm_disable(struct device *dev)
{
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
if (drvdata->ltssm_mask)
- regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
drvdata->ltssm_mask, 0);
- reset_control_assert(imx6_pcie->apps_reset);
+ reset_control_assert(imx_pcie->apps_reset);
}
-static int imx6_pcie_start_link(struct dw_pcie *pci)
+static int imx_pcie_start_link(struct dw_pcie *pci)
{
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pci);
struct device *dev = pci->dev;
u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
u32 tmp;
@@ -846,7 +846,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
dw_pcie_dbi_ro_wr_dis(pci);
/* Start LTSSM. */
- imx6_pcie_ltssm_enable(dev);
+ imx_pcie_ltssm_enable(dev);
ret = dw_pcie_wait_for_link(pci);
if (ret)
@@ -869,8 +869,8 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
dw_pcie_dbi_ro_wr_dis(pci);
- if (imx6_pcie->drvdata->flags &
- IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
+ if (imx_pcie->drvdata->flags &
+ IMX_PCIE_FLAG_IMX_SPEED_CHANGE) {
/*
* On i.MX7, DIRECT_SPEED_CHANGE behaves differently
* from i.MX6 family when no link speed transition
@@ -880,7 +880,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
* failure.
*/
- ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
+ ret = imx_pcie_wait_for_speed_change(imx_pcie);
if (ret) {
dev_err(dev, "Failed to bring link up!\n");
goto err_reset_phy;
@@ -895,37 +895,37 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
dev_info(dev, "Link: Only Gen1 is enabled\n");
}
- imx6_pcie->link_is_up = true;
+ imx_pcie->link_is_up = true;
tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
return 0;
err_reset_phy:
- imx6_pcie->link_is_up = false;
+ imx_pcie->link_is_up = false;
dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
- imx6_pcie_reset_phy(imx6_pcie);
+ imx_pcie_reset_phy(imx_pcie);
return 0;
}
-static void imx6_pcie_stop_link(struct dw_pcie *pci)
+static void imx_pcie_stop_link(struct dw_pcie *pci)
{
struct device *dev = pci->dev;
/* Turn off PCIe LTSSM */
- imx6_pcie_ltssm_disable(dev);
+ imx_pcie_ltssm_disable(dev);
}
-static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
+static int imx_pcie_host_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct device *dev = pci->dev;
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pci);
int ret;
- if (imx6_pcie->vpcie) {
- ret = regulator_enable(imx6_pcie->vpcie);
+ if (imx_pcie->vpcie) {
+ ret = regulator_enable(imx_pcie->vpcie);
if (ret) {
dev_err(dev, "failed to enable vpcie regulator: %d\n",
ret);
@@ -933,83 +933,83 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
}
}
- imx6_pcie_assert_core_reset(imx6_pcie);
+ imx_pcie_assert_core_reset(imx_pcie);
- if (imx6_pcie->drvdata->init_phy)
- imx6_pcie->drvdata->init_phy(imx6_pcie);
+ if (imx_pcie->drvdata->init_phy)
+ imx_pcie->drvdata->init_phy(imx_pcie);
- imx6_pcie_configure_type(imx6_pcie);
+ imx_pcie_configure_type(imx_pcie);
- ret = imx6_pcie_clk_enable(imx6_pcie);
+ ret = imx_pcie_clk_enable(imx_pcie);
if (ret) {
dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
goto err_reg_disable;
}
- if (imx6_pcie->phy) {
- ret = phy_init(imx6_pcie->phy);
+ if (imx_pcie->phy) {
+ ret = phy_init(imx_pcie->phy);
if (ret) {
dev_err(dev, "pcie PHY power up failed\n");
goto err_clk_disable;
}
}
- if (imx6_pcie->phy) {
- ret = phy_power_on(imx6_pcie->phy);
+ if (imx_pcie->phy) {
+ ret = phy_power_on(imx_pcie->phy);
if (ret) {
dev_err(dev, "waiting for PHY ready timeout!\n");
goto err_phy_off;
}
}
- ret = imx6_pcie_deassert_core_reset(imx6_pcie);
+ ret = imx_pcie_deassert_core_reset(imx_pcie);
if (ret < 0) {
dev_err(dev, "pcie deassert core reset failed: %d\n", ret);
goto err_phy_off;
}
- imx6_setup_phy_mpll(imx6_pcie);
+ imx_setup_phy_mpll(imx_pcie);
return 0;
err_phy_off:
- if (imx6_pcie->phy)
- phy_exit(imx6_pcie->phy);
+ if (imx_pcie->phy)
+ phy_exit(imx_pcie->phy);
err_clk_disable:
- imx6_pcie_clk_disable(imx6_pcie);
+ imx_pcie_clk_disable(imx_pcie);
err_reg_disable:
- if (imx6_pcie->vpcie)
- regulator_disable(imx6_pcie->vpcie);
+ if (imx_pcie->vpcie)
+ regulator_disable(imx_pcie->vpcie);
return ret;
}
-static void imx6_pcie_host_exit(struct dw_pcie_rp *pp)
+static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pci);
- if (imx6_pcie->phy) {
- if (phy_power_off(imx6_pcie->phy))
+ if (imx_pcie->phy) {
+ if (phy_power_off(imx_pcie->phy))
dev_err(pci->dev, "unable to power off PHY\n");
- phy_exit(imx6_pcie->phy);
+ phy_exit(imx_pcie->phy);
}
- imx6_pcie_clk_disable(imx6_pcie);
+ imx_pcie_clk_disable(imx_pcie);
- if (imx6_pcie->vpcie)
- regulator_disable(imx6_pcie->vpcie);
+ if (imx_pcie->vpcie)
+ regulator_disable(imx_pcie->vpcie);
}
-static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
- .init = imx6_pcie_host_init,
- .deinit = imx6_pcie_host_exit,
+static const struct dw_pcie_host_ops imx_pcie_host_ops = {
+ .init = imx_pcie_host_init,
+ .deinit = imx_pcie_host_exit,
};
static const struct dw_pcie_ops dw_pcie_ops = {
- .start_link = imx6_pcie_start_link,
- .stop_link = imx6_pcie_stop_link,
+ .start_link = imx_pcie_start_link,
+ .stop_link = imx_pcie_stop_link,
};
-static void imx6_pcie_ep_init(struct dw_pcie_ep *ep)
+static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
{
enum pci_barno bar;
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -1018,7 +1018,7 @@ static void imx6_pcie_ep_init(struct dw_pcie_ep *ep)
dw_pcie_ep_reset_bar(pci, bar);
}
-static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
+static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
unsigned int type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -1065,35 +1065,35 @@ static const struct pci_epc_features imx95_pcie_epc_features = {
};
static const struct pci_epc_features*
-imx6_pcie_ep_get_features(struct dw_pcie_ep *ep)
+imx_pcie_ep_get_features(struct dw_pcie_ep *ep)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pci);
- return imx6_pcie->drvdata->epc_features;
+ return imx_pcie->drvdata->epc_features;
}
static const struct dw_pcie_ep_ops pcie_ep_ops = {
- .init = imx6_pcie_ep_init,
- .raise_irq = imx6_pcie_ep_raise_irq,
- .get_features = imx6_pcie_ep_get_features,
+ .init = imx_pcie_ep_init,
+ .raise_irq = imx_pcie_ep_raise_irq,
+ .get_features = imx_pcie_ep_get_features,
};
-static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
+static int imx_add_pcie_ep(struct imx_pcie *imx_pcie,
struct platform_device *pdev)
{
int ret;
unsigned int pcie_dbi2_offset;
struct dw_pcie_ep *ep;
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
struct dw_pcie_rp *pp = &pci->pp;
struct device *dev = pci->dev;
- imx6_pcie_host_init(pp);
+ imx_pcie_host_init(pp);
ep = &pci->ep;
ep->ops = &pcie_ep_ops;
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX8MQ_EP:
case IMX8MM_EP:
case IMX8MP_EP:
@@ -1115,10 +1115,10 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
if (device_property_match_string(dev, "reg-names", "dbi2") >= 0)
pci->dbi_base2 = NULL;
- if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT))
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_SUPPORT_64BIT))
dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
- ep->page_size = imx6_pcie->drvdata->epc_features->align;
+ ep->page_size = imx_pcie->drvdata->epc_features->align;
ret = dw_pcie_ep_init(ep);
if (ret) {
@@ -1126,30 +1126,30 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
return ret;
}
/* Start LTSSM. */
- imx6_pcie_ltssm_enable(dev);
+ imx_pcie_ltssm_enable(dev);
return 0;
}
-static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_pm_turnoff(struct imx_pcie *imx_pcie)
{
- struct device *dev = imx6_pcie->pci->dev;
+ struct device *dev = imx_pcie->pci->dev;
/* Some variants have a turnoff reset in DT */
- if (imx6_pcie->turnoff_reset) {
- reset_control_assert(imx6_pcie->turnoff_reset);
- reset_control_deassert(imx6_pcie->turnoff_reset);
+ if (imx_pcie->turnoff_reset) {
+ reset_control_assert(imx_pcie->turnoff_reset);
+ reset_control_deassert(imx_pcie->turnoff_reset);
goto pm_turnoff_sleep;
}
/* Others poke directly at IOMUXC registers */
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX6SX:
case IMX6QP:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_PM_TURN_OFF,
IMX6SX_GPR12_PCIE_PM_TURN_OFF);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
break;
default:
@@ -1168,73 +1168,73 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
usleep_range(1000, 10000);
}
-static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save)
+static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save)
{
u8 offset;
u16 val;
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie *pci = imx_pcie->pci;
if (pci_msi_enabled()) {
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
if (save) {
val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
- imx6_pcie->msi_ctrl = val;
+ imx_pcie->msi_ctrl = val;
} else {
dw_pcie_dbi_ro_wr_en(pci);
- val = imx6_pcie->msi_ctrl;
+ val = imx_pcie->msi_ctrl;
dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
dw_pcie_dbi_ro_wr_dis(pci);
}
}
}
-static int imx6_pcie_suspend_noirq(struct device *dev)
+static int imx_pcie_suspend_noirq(struct device *dev)
{
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ struct dw_pcie_rp *pp = &imx_pcie->pci->pp;
- if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
+ if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND))
return 0;
- imx6_pcie_msi_save_restore(imx6_pcie, true);
- imx6_pcie_pm_turnoff(imx6_pcie);
- imx6_pcie_stop_link(imx6_pcie->pci);
- imx6_pcie_host_exit(pp);
+ imx_pcie_msi_save_restore(imx_pcie, true);
+ imx_pcie_pm_turnoff(imx_pcie);
+ imx_pcie_stop_link(imx_pcie->pci);
+ imx_pcie_host_exit(pp);
return 0;
}
-static int imx6_pcie_resume_noirq(struct device *dev)
+static int imx_pcie_resume_noirq(struct device *dev)
{
int ret;
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ struct dw_pcie_rp *pp = &imx_pcie->pci->pp;
- if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
+ if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND))
return 0;
- ret = imx6_pcie_host_init(pp);
+ ret = imx_pcie_host_init(pp);
if (ret)
return ret;
- imx6_pcie_msi_save_restore(imx6_pcie, false);
+ imx_pcie_msi_save_restore(imx_pcie, false);
dw_pcie_setup_rc(pp);
- if (imx6_pcie->link_is_up)
- imx6_pcie_start_link(imx6_pcie->pci);
+ if (imx_pcie->link_is_up)
+ imx_pcie_start_link(imx_pcie->pci);
return 0;
}
-static const struct dev_pm_ops imx6_pcie_pm_ops = {
- NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
- imx6_pcie_resume_noirq)
+static const struct dev_pm_ops imx_pcie_pm_ops = {
+ NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_pcie_suspend_noirq,
+ imx_pcie_resume_noirq)
};
-static int imx6_pcie_probe(struct platform_device *pdev)
+static int imx_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct dw_pcie *pci;
- struct imx6_pcie *imx6_pcie;
+ struct imx_pcie *imx_pcie;
struct device_node *np;
struct resource *dbi_base;
struct device_node *node = dev->of_node;
@@ -1242,8 +1242,8 @@ static int imx6_pcie_probe(struct platform_device *pdev)
u16 val;
int i;
- imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
- if (!imx6_pcie)
+ imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
+ if (!imx_pcie)
return -ENOMEM;
pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
@@ -1252,10 +1252,10 @@ static int imx6_pcie_probe(struct platform_device *pdev)
pci->dev = dev;
pci->ops = &dw_pcie_ops;
- pci->pp.ops = &imx6_pcie_host_ops;
+ pci->pp.ops = &imx_pcie_host_ops;
- imx6_pcie->pci = pci;
- imx6_pcie->drvdata = of_device_get_match_data(dev);
+ imx_pcie->pci = pci;
+ imx_pcie->drvdata = of_device_get_match_data(dev);
/* Find the PHY if one is defined, only imx7d uses it */
np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
@@ -1267,9 +1267,9 @@ static int imx6_pcie_probe(struct platform_device *pdev)
dev_err(dev, "Unable to map PCIe PHY\n");
return ret;
}
- imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
- if (IS_ERR(imx6_pcie->phy_base))
- return PTR_ERR(imx6_pcie->phy_base);
+ imx_pcie->phy_base = devm_ioremap_resource(dev, &res);
+ if (IS_ERR(imx_pcie->phy_base))
+ return PTR_ERR(imx_pcie->phy_base);
}
pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base);
@@ -1277,12 +1277,12 @@ static int imx6_pcie_probe(struct platform_device *pdev)
return PTR_ERR(pci->dbi_base);
/* Fetch GPIOs */
- imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
- imx6_pcie->gpio_active_high = of_property_read_bool(node,
+ imx_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
+ imx_pcie->gpio_active_high = of_property_read_bool(node,
"reset-gpio-active-high");
- if (gpio_is_valid(imx6_pcie->reset_gpio)) {
- ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
- imx6_pcie->gpio_active_high ?
+ if (gpio_is_valid(imx_pcie->reset_gpio)) {
+ ret = devm_gpio_request_one(dev, imx_pcie->reset_gpio,
+ imx_pcie->gpio_active_high ?
GPIOF_OUT_INIT_HIGH :
GPIOF_OUT_INIT_LOW,
"PCIe reset");
@@ -1290,70 +1290,70 @@ static int imx6_pcie_probe(struct platform_device *pdev)
dev_err(dev, "unable to get reset gpio\n");
return ret;
}
- } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
- return imx6_pcie->reset_gpio;
+ } else if (imx_pcie->reset_gpio == -EPROBE_DEFER) {
+ return imx_pcie->reset_gpio;
}
- if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS)
+ if (imx_pcie->drvdata->clks_cnt >= IMX_PCIE_MAX_CLKS)
return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
- for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++)
- imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i];
+ for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++)
+ imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i];
/* Fetch clocks */
- ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
+ ret = devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
if (ret)
return ret;
- if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHYDRV)) {
- imx6_pcie->phy = devm_phy_get(dev, "pcie-phy");
- if (IS_ERR(imx6_pcie->phy))
- return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy),
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
+ imx_pcie->phy = devm_phy_get(dev, "pcie-phy");
+ if (IS_ERR(imx_pcie->phy))
+ return dev_err_probe(dev, PTR_ERR(imx_pcie->phy),
"failed to get pcie phy\n");
}
- if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) {
- imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps");
- if (IS_ERR(imx6_pcie->apps_reset))
- return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset),
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_APP_RESET)) {
+ imx_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps");
+ if (IS_ERR(imx_pcie->apps_reset))
+ return dev_err_probe(dev, PTR_ERR(imx_pcie->apps_reset),
"failed to get pcie apps reset control\n");
}
- if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) {
- imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy");
- if (IS_ERR(imx6_pcie->pciephy_reset))
- return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset),
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHY_RESET)) {
+ imx_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy");
+ if (IS_ERR(imx_pcie->pciephy_reset))
+ return dev_err_probe(dev, PTR_ERR(imx_pcie->pciephy_reset),
"Failed to get PCIEPHY reset control\n");
}
- switch (imx6_pcie->drvdata->variant) {
+ switch (imx_pcie->drvdata->variant) {
case IMX8MQ:
case IMX8MQ_EP:
case IMX7D:
if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
- imx6_pcie->controller_id = 1;
+ imx_pcie->controller_id = 1;
break;
default:
break;
}
/* Grab turnoff reset */
- imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
- if (IS_ERR(imx6_pcie->turnoff_reset)) {
+ imx_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
+ if (IS_ERR(imx_pcie->turnoff_reset)) {
dev_err(dev, "Failed to get TURNOFF reset control\n");
- return PTR_ERR(imx6_pcie->turnoff_reset);
+ return PTR_ERR(imx_pcie->turnoff_reset);
}
- if (imx6_pcie->drvdata->gpr) {
+ if (imx_pcie->drvdata->gpr) {
/* Grab GPR config register range */
- imx6_pcie->iomuxc_gpr =
- syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
- if (IS_ERR(imx6_pcie->iomuxc_gpr))
- return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
+ imx_pcie->iomuxc_gpr =
+ syscon_regmap_lookup_by_compatible(imx_pcie->drvdata->gpr);
+ if (IS_ERR(imx_pcie->iomuxc_gpr))
+ return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr),
"unable to find iomuxc registers\n");
}
- if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) {
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_SERDES)) {
void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app");
if (IS_ERR(off))
@@ -1366,59 +1366,59 @@ static int imx6_pcie_probe(struct platform_device *pdev)
.reg_stride = 4,
};
- imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config);
- if (IS_ERR(imx6_pcie->iomuxc_gpr))
- return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
+ imx_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(imx_pcie->iomuxc_gpr))
+ return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr),
"unable to find iomuxc registers\n");
}
/* Grab PCIe PHY Tx Settings */
if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
- &imx6_pcie->tx_deemph_gen1))
- imx6_pcie->tx_deemph_gen1 = 0;
+ &imx_pcie->tx_deemph_gen1))
+ imx_pcie->tx_deemph_gen1 = 0;
if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
- &imx6_pcie->tx_deemph_gen2_3p5db))
- imx6_pcie->tx_deemph_gen2_3p5db = 0;
+ &imx_pcie->tx_deemph_gen2_3p5db))
+ imx_pcie->tx_deemph_gen2_3p5db = 0;
if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
- &imx6_pcie->tx_deemph_gen2_6db))
- imx6_pcie->tx_deemph_gen2_6db = 20;
+ &imx_pcie->tx_deemph_gen2_6db))
+ imx_pcie->tx_deemph_gen2_6db = 20;
if (of_property_read_u32(node, "fsl,tx-swing-full",
- &imx6_pcie->tx_swing_full))
- imx6_pcie->tx_swing_full = 127;
+ &imx_pcie->tx_swing_full))
+ imx_pcie->tx_swing_full = 127;
if (of_property_read_u32(node, "fsl,tx-swing-low",
- &imx6_pcie->tx_swing_low))
- imx6_pcie->tx_swing_low = 127;
+ &imx_pcie->tx_swing_low))
+ imx_pcie->tx_swing_low = 127;
/* Limit link speed */
pci->link_gen = 1;
of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
- imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
- if (IS_ERR(imx6_pcie->vpcie)) {
- if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
- return PTR_ERR(imx6_pcie->vpcie);
- imx6_pcie->vpcie = NULL;
+ imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
+ if (IS_ERR(imx_pcie->vpcie)) {
+ if (PTR_ERR(imx_pcie->vpcie) != -ENODEV)
+ return PTR_ERR(imx_pcie->vpcie);
+ imx_pcie->vpcie = NULL;
}
- imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
- if (IS_ERR(imx6_pcie->vph)) {
- if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
- return PTR_ERR(imx6_pcie->vph);
- imx6_pcie->vph = NULL;
+ imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
+ if (IS_ERR(imx_pcie->vph)) {
+ if (PTR_ERR(imx_pcie->vph) != -ENODEV)
+ return PTR_ERR(imx_pcie->vph);
+ imx_pcie->vph = NULL;
}
- platform_set_drvdata(pdev, imx6_pcie);
+ platform_set_drvdata(pdev, imx_pcie);
- ret = imx6_pcie_attach_pd(dev);
+ ret = imx_pcie_attach_pd(dev);
if (ret)
return ret;
- if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
- ret = imx6_add_pcie_ep(imx6_pcie, pdev);
+ if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
+ ret = imx_add_pcie_ep(imx_pcie, pdev);
if (ret < 0)
return ret;
} else {
@@ -1438,12 +1438,12 @@ static int imx6_pcie_probe(struct platform_device *pdev)
return 0;
}
-static void imx6_pcie_shutdown(struct platform_device *pdev)
+static void imx_pcie_shutdown(struct platform_device *pdev)
{
- struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
+ struct imx_pcie *imx_pcie = platform_get_drvdata(pdev);
/* bring down link, so bootloader gets clean state in case of reboot */
- imx6_pcie_assert_core_reset(imx6_pcie);
+ imx_pcie_assert_core_reset(imx_pcie);
}
static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"};
@@ -1451,11 +1451,11 @@ static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"};
static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
-static const struct imx6_pcie_drvdata drvdata[] = {
+static const struct imx_pcie_drvdata drvdata[] = {
[IMX6Q] = {
.variant = IMX6Q,
- .flags = IMX6_PCIE_FLAG_IMX6_PHY |
- IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
+ .flags = IMX_PCIE_FLAG_IMX_PHY |
+ IMX_PCIE_FLAG_IMX_SPEED_CHANGE,
.dbi_length = 0x200,
.gpr = "fsl,imx6q-iomuxc-gpr",
.clk_names = imx6q_clks,
@@ -1464,13 +1464,13 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
- .init_phy = imx6_pcie_init_phy,
+ .init_phy = imx_pcie_init_phy,
},
[IMX6SX] = {
.variant = IMX6SX,
- .flags = IMX6_PCIE_FLAG_IMX6_PHY |
- IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
- IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
+ .flags = IMX_PCIE_FLAG_IMX_PHY |
+ IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
+ IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
.gpr = "fsl,imx6q-iomuxc-gpr",
.clk_names = imx6sx_clks,
.clks_cnt = ARRAY_SIZE(imx6sx_clks),
@@ -1482,9 +1482,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX6QP] = {
.variant = IMX6QP,
- .flags = IMX6_PCIE_FLAG_IMX6_PHY |
- IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
- IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
+ .flags = IMX_PCIE_FLAG_IMX_PHY |
+ IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
+ IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
.dbi_length = 0x200,
.gpr = "fsl,imx6q-iomuxc-gpr",
.clk_names = imx6q_clks,
@@ -1493,13 +1493,13 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
.mode_off[0] = IOMUXC_GPR12,
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
- .init_phy = imx6_pcie_init_phy,
+ .init_phy = imx_pcie_init_phy,
},
[IMX7D] = {
.variant = IMX7D,
- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
- IMX6_PCIE_FLAG_HAS_APP_RESET |
- IMX6_PCIE_FLAG_HAS_PHY_RESET,
+ .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
+ IMX_PCIE_FLAG_HAS_APP_RESET |
+ IMX_PCIE_FLAG_HAS_PHY_RESET,
.gpr = "fsl,imx7d-iomuxc-gpr",
.clk_names = imx6q_clks,
.clks_cnt = ARRAY_SIZE(imx6q_clks),
@@ -1509,8 +1509,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MQ] = {
.variant = IMX8MQ,
- .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
- IMX6_PCIE_FLAG_HAS_PHY_RESET,
+ .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
+ IMX_PCIE_FLAG_HAS_PHY_RESET,
.gpr = "fsl,imx8mq-iomuxc-gpr",
.clk_names = imx8mq_clks,
.clks_cnt = ARRAY_SIZE(imx8mq_clks),
@@ -1522,9 +1522,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MM] = {
.variant = IMX8MM,
- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
- IMX6_PCIE_FLAG_HAS_PHYDRV |
- IMX6_PCIE_FLAG_HAS_APP_RESET,
+ .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
+ IMX_PCIE_FLAG_HAS_PHYDRV |
+ IMX_PCIE_FLAG_HAS_APP_RESET,
.gpr = "fsl,imx8mm-iomuxc-gpr",
.clk_names = imx8mm_clks,
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
@@ -1533,9 +1533,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MP] = {
.variant = IMX8MP,
- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
- IMX6_PCIE_FLAG_HAS_PHYDRV |
- IMX6_PCIE_FLAG_HAS_APP_RESET,
+ .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
+ IMX_PCIE_FLAG_HAS_PHYDRV |
+ IMX_PCIE_FLAG_HAS_APP_RESET,
.gpr = "fsl,imx8mp-iomuxc-gpr",
.clk_names = imx8mm_clks,
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
@@ -1544,7 +1544,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX95] = {
.variant = IMX95,
- .flags = IMX6_PCIE_FLAG_HAS_SERDES,
+ .flags = IMX_PCIE_FLAG_HAS_SERDES,
.clk_names = imx8mq_clks,
.clks_cnt = ARRAY_SIZE(imx8mq_clks),
.ltssm_off = IMX95_PE0_GEN_CTRL_3,
@@ -1555,8 +1555,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MQ_EP] = {
.variant = IMX8MQ_EP,
- .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
- IMX6_PCIE_FLAG_HAS_PHY_RESET,
+ .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
+ IMX_PCIE_FLAG_HAS_PHY_RESET,
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mq-iomuxc-gpr",
.clk_names = imx8mq_clks,
@@ -1570,8 +1570,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MM_EP] = {
.variant = IMX8MM_EP,
- .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
- IMX6_PCIE_FLAG_HAS_PHYDRV,
+ .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
+ IMX_PCIE_FLAG_HAS_PHYDRV,
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mm-iomuxc-gpr",
.clk_names = imx8mm_clks,
@@ -1582,8 +1582,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX8MP_EP] = {
.variant = IMX8MP_EP,
- .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
- IMX6_PCIE_FLAG_HAS_PHYDRV,
+ .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
+ IMX_PCIE_FLAG_HAS_PHYDRV,
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mp-iomuxc-gpr",
.clk_names = imx8mm_clks,
@@ -1594,8 +1594,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
[IMX95_EP] = {
.variant = IMX95_EP,
- .flags = IMX6_PCIE_FLAG_HAS_SERDES |
- IMX6_PCIE_FLAG_SUPPORT_64BIT,
+ .flags = IMX_PCIE_FLAG_HAS_SERDES |
+ IMX_PCIE_FLAG_SUPPORT_64BIT,
.clk_names = imx8mq_clks,
.clks_cnt = ARRAY_SIZE(imx8mq_clks),
.ltssm_off = IMX95_PE0_GEN_CTRL_3,
@@ -1608,7 +1608,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
},
};
-static const struct of_device_id imx6_pcie_of_match[] = {
+static const struct of_device_id imx_pcie_of_match[] = {
{ .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
{ .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
@@ -1624,19 +1624,19 @@ static const struct of_device_id imx6_pcie_of_match[] = {
{},
};
-static struct platform_driver imx6_pcie_driver = {
+static struct platform_driver imx_pcie_driver = {
.driver = {
.name = "imx6q-pcie",
- .of_match_table = imx6_pcie_of_match,
+ .of_match_table = imx_pcie_of_match,
.suppress_bind_attrs = true,
- .pm = &imx6_pcie_pm_ops,
+ .pm = &imx_pcie_pm_ops,
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
- .probe = imx6_pcie_probe,
- .shutdown = imx6_pcie_shutdown,
+ .probe = imx_pcie_probe,
+ .shutdown = imx_pcie_shutdown,
};
-static void imx6_pcie_quirk(struct pci_dev *dev)
+static void imx_pcie_quirk(struct pci_dev *dev)
{
struct pci_bus *bus = dev->bus;
struct dw_pcie_rp *pp = bus->sysdata;
@@ -1646,33 +1646,33 @@ static void imx6_pcie_quirk(struct pci_dev *dev)
return;
/* Make sure we only quirk devices associated with this driver */
- if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver)
+ if (bus->dev.parent->parent->driver != &imx_pcie_driver.driver)
return;
if (pci_is_root_bus(bus)) {
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pci);
/*
* Limit config length to avoid the kernel reading beyond
* the register set and causing an abort on i.MX 6Quad
*/
- if (imx6_pcie->drvdata->dbi_length) {
- dev->cfg_size = imx6_pcie->drvdata->dbi_length;
+ if (imx_pcie->drvdata->dbi_length) {
+ dev->cfg_size = imx_pcie->drvdata->dbi_length;
dev_info(&dev->dev, "Limiting cfg_size to %d\n",
dev->cfg_size);
}
}
}
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd,
- PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk);
+ PCI_CLASS_BRIDGE_PCI, 8, imx_pcie_quirk);
-static int __init imx6_pcie_init(void)
+static int __init imx_pcie_init(void)
{
#ifdef CONFIG_ARM
struct device_node *np;
- np = of_find_matching_node(NULL, imx6_pcie_of_match);
+ np = of_find_matching_node(NULL, imx_pcie_of_match);
if (!np)
return -ENODEV;
of_node_put(np);
@@ -1688,6 +1688,6 @@ static int __init imx6_pcie_init(void)
"external abort on non-linefetch");
#endif
- return platform_driver_register(&imx6_pcie_driver);
+ return platform_driver_register(&imx_pcie_driver);
}
-device_initcall(imx6_pcie_init);
+device_initcall(imx_pcie_init);
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 7%]
* [PATCH v4 05/12] PCI: imx6: Simplify switch-case logic by involve core_reset callback
2024-05-07 18:45 7% ` [PATCH v4 03/12] PCI: imx6: Rename imx6_* with imx_* Frank Li
2024-05-07 18:45 5% ` [PATCH v4 04/12] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li
@ 2024-05-07 18:45 10% ` Frank Li
2024-05-07 18:45 5% ` [PATCH v4 11/12] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Frank Li
3 siblings, 0 replies; 200+ results
From: Frank Li @ 2024-05-07 18:45 UTC (permalink / raw)
To: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley
Cc: linux-pci, imx, linux-arm-kernel, linux-kernel, bpf, devicetree,
Frank Li
Instead of using the switch case statement to assert/dassert the core reset
handled by this driver itself, let's introduce a new callback core_reset()
and define it for platforms that require it. This simplifies the code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 134 ++++++++++++++++++----------------
1 file changed, 71 insertions(+), 63 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index cf1b487b3f625..7396f0d51119a 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -104,6 +104,7 @@ struct imx_pcie_drvdata {
const struct pci_epc_features *epc_features;
int (*init_phy)(struct imx_pcie *pcie);
int (*set_ref_clk)(struct imx_pcie *pcie, bool enable);
+ int (*core_reset)(struct imx_pcie *pcie, bool assert);
};
struct imx_pcie {
@@ -672,35 +673,75 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
}
+static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+ if (assert)
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
+
+ /* Force PCIe PHY reset */
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET,
+ assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0);
+ return 0;
+}
+
+static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST,
+ assert ? IMX6Q_GPR1_PCIE_SW_RST : 0);
+ if (!assert)
+ usleep_range(200, 500);
+
+ return 0;
+}
+
+static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+ if (!assert)
+ return 0;
+
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD);
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN);
+
+ return 0;
+}
+
+static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+ struct dw_pcie *pci = imx_pcie->pci;
+ struct device *dev = pci->dev;
+
+ if (assert)
+ return 0;
+
+ /*
+ * Workaround for ERR010728, failure of PCI-e PLL VCO to
+ * oscillate, especially when cold. This turns off "Duty-cycle
+ * Corrector" and other mysterious undocumented things.
+ */
+
+ if (likely(imx_pcie->phy_base)) {
+ /* De-assert DCC_FB_EN */
+ writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
+ /* Assert RX_EQS and RX_EQS_SEL */
+ writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ,
+ imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
+ /* Assert ATT_MODE */
+ writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
+ } else {
+ dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
+ }
+ imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
+ return 0;
+}
+
static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
{
reset_control_assert(imx_pcie->pciephy_reset);
reset_control_assert(imx_pcie->apps_reset);
- switch (imx_pcie->drvdata->variant) {
- case IMX6SX:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
- IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
- IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
- /* Force PCIe PHY reset */
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
- IMX6SX_GPR5_PCIE_BTNRST_RESET,
- IMX6SX_GPR5_PCIE_BTNRST_RESET);
- break;
- case IMX6QP:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_SW_RST,
- IMX6Q_GPR1_PCIE_SW_RST);
- break;
- case IMX6Q:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
- break;
- default:
- break;
- }
+ if (imx_pcie->drvdata->core_reset)
+ imx_pcie->drvdata->core_reset(imx_pcie, true);
/* Some boards don't have PCIe reset GPIO. */
if (gpio_is_valid(imx_pcie->reset_gpio))
@@ -710,47 +751,10 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
{
- struct dw_pcie *pci = imx_pcie->pci;
- struct device *dev = pci->dev;
-
reset_control_deassert(imx_pcie->pciephy_reset);
- switch (imx_pcie->drvdata->variant) {
- case IMX7D:
- /* Workaround for ERR010728, failure of PCI-e PLL VCO to
- * oscillate, especially when cold. This turns off "Duty-cycle
- * Corrector" and other mysterious undocumented things.
- */
- if (likely(imx_pcie->phy_base)) {
- /* De-assert DCC_FB_EN */
- writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
- imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
- /* Assert RX_EQS and RX_EQS_SEL */
- writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
- | PCIE_PHY_CMN_REG24_RX_EQ,
- imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
- /* Assert ATT_MODE */
- writel(PCIE_PHY_CMN_REG26_ATT_MODE,
- imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
- } else {
- dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
- }
-
- imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
- break;
- case IMX6SX:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
- IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
- break;
- case IMX6QP:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_SW_RST, 0);
-
- usleep_range(200, 500);
- break;
- default:
- break;
- }
+ if (imx_pcie->drvdata->core_reset)
+ imx_pcie->drvdata->core_reset(imx_pcie, false);
/* Some boards don't have PCIe reset GPIO. */
if (gpio_is_valid(imx_pcie->reset_gpio)) {
@@ -1448,6 +1452,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx_pcie_init_phy,
.set_ref_clk = imx6q_pcie_set_ref_clk,
+ .core_reset = imx6q_pcie_core_reset,
},
[IMX6SX] = {
.variant = IMX6SX,
@@ -1463,6 +1468,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx6sx_pcie_init_phy,
.set_ref_clk = imx6sx_pcie_set_ref_clk,
+ .core_reset = imx6sx_pcie_core_reset,
},
[IMX6QP] = {
.variant = IMX6QP,
@@ -1479,6 +1485,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx_pcie_init_phy,
.set_ref_clk = imx6q_pcie_set_ref_clk,
+ .core_reset = imx6qp_pcie_core_reset,
},
[IMX7D] = {
.variant = IMX7D,
@@ -1492,6 +1499,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx7d_pcie_init_phy,
.set_ref_clk = imx7d_pcie_set_ref_clk,
+ .core_reset = imx7d_pcie_core_reset,
},
[IMX8MQ] = {
.variant = IMX8MQ,
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 10%]
* [PATCH v2 4/8] irqchip/stm32-exti: split MCU and MPU code
@ 2024-05-07 13:10 2% ` Antonio Borneo
0 siblings, 0 replies; 200+ results
From: Antonio Borneo @ 2024-05-07 13:10 UTC (permalink / raw)
To: Russell King, Maxime Coquelin, Alexandre Torgue, Catalin Marinas,
Will Deacon, Thomas Gleixner
Cc: Antonio Borneo, linux-arm-kernel, linux-stm32, linux-kernel
Keep in stm32-exti only the code for ARMv7m STM32 MCUs and split
out in stm32mp-exti the code for ARMv7a & ARMv8a STM32MPxxx MPUs.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
drivers/irqchip/Kconfig | 3 +-
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-stm32-exti.c | 670 +-----------------
.../{irq-stm32-exti.c => irq-stm32mp-exti.c} | 345 +--------
4 files changed, 10 insertions(+), 1009 deletions(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 798bd50f8ab23..486022fb7806e 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -394,7 +394,8 @@ config PARTITION_PERCPU
config STM32MP_EXTI
bool
- select STM32_EXTI
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
config STM32_EXTI
bool
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index d9dc3d99aaa86..8dffb6efbc070 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o
+obj-$(CONFIG_STM32MP_EXTI) += irq-stm32mp-exti.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 2cc9f3b7d6690..7c6a0080c3303 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -1,45 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Maxime Coquelin 2015
- * Copyright (C) STMicroelectronics 2017
+ * Copyright (C) STMicroelectronics 2017-2024
* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
*/
#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/hwspinlock.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
-#include <linux/mod_devicetable.h>
-#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
-#include <linux/platform_device.h>
-#include <linux/pm.h>
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
#define IRQS_PER_BANK 32
-#define HWSPNLCK_TIMEOUT 1000 /* usec */
-
-#define EXTI_EnCIDCFGR(n) (0x180 + (n) * 4)
-#define EXTI_HWCFGR1 0x3f0
-
-/* Register: EXTI_EnCIDCFGR(n) */
-#define EXTI_CIDCFGR_CFEN_MASK BIT(0)
-#define EXTI_CIDCFGR_CID_MASK GENMASK(6, 4)
-#define EXTI_CIDCFGR_CID_SHIFT 4
-
-/* Register: EXTI_HWCFGR1 */
-#define EXTI_HWCFGR1_CIDWIDTH_MASK GENMASK(27, 24)
-
-#define EXTI_CID1 1
-
struct stm32_exti_bank {
u32 imr_ofst;
u32 emr_ofst;
@@ -47,13 +24,8 @@ struct stm32_exti_bank {
u32 ftsr_ofst;
u32 swier_ofst;
u32 rpr_ofst;
- u32 fpr_ofst;
- u32 trg_ofst;
- u32 seccfgr_ofst;
};
-#define UNDEF_REG ~0
-
struct stm32_exti_drv_data {
const struct stm32_exti_bank **exti_banks;
const u8 *desc_irqs;
@@ -63,7 +35,6 @@ struct stm32_exti_drv_data {
struct stm32_exti_chip_data {
struct stm32_exti_host_data *host_data;
const struct stm32_exti_bank *reg_bank;
- struct raw_spinlock rlock;
u32 wake_active;
u32 mask_cache;
u32 rtsr_cache;
@@ -76,8 +47,6 @@ struct stm32_exti_host_data {
struct device *dev;
struct stm32_exti_chip_data *chips_data;
const struct stm32_exti_drv_data *drv_data;
- struct hwspinlock *hwlock;
- bool dt_has_irqs_desc; /* skip internal desc_irqs array and get it from DT */
};
static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
@@ -87,9 +56,6 @@ static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
.ftsr_ofst = 0x0C,
.swier_ofst = 0x10,
.rpr_ofst = 0x14,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
};
static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
@@ -108,9 +74,6 @@ static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
.ftsr_ofst = 0x04,
.swier_ofst = 0x08,
.rpr_ofst = 0x88,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
};
static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
@@ -120,9 +83,6 @@ static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
.ftsr_ofst = 0x24,
.swier_ofst = 0x28,
.rpr_ofst = 0x98,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
};
static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
@@ -132,9 +92,6 @@ static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
.ftsr_ofst = 0x44,
.swier_ofst = 0x48,
.rpr_ofst = 0xA8,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
};
static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
@@ -148,183 +105,12 @@ static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
.bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
};
-static const struct stm32_exti_bank stm32mp1_exti_b1 = {
- .imr_ofst = 0x80,
- .emr_ofst = UNDEF_REG,
- .rtsr_ofst = 0x00,
- .ftsr_ofst = 0x04,
- .swier_ofst = 0x08,
- .rpr_ofst = 0x0C,
- .fpr_ofst = 0x10,
- .trg_ofst = 0x3EC,
- .seccfgr_ofst = 0x14,
-};
-
-static const struct stm32_exti_bank stm32mp1_exti_b2 = {
- .imr_ofst = 0x90,
- .emr_ofst = UNDEF_REG,
- .rtsr_ofst = 0x20,
- .ftsr_ofst = 0x24,
- .swier_ofst = 0x28,
- .rpr_ofst = 0x2C,
- .fpr_ofst = 0x30,
- .trg_ofst = 0x3E8,
- .seccfgr_ofst = 0x34,
-};
-
-static const struct stm32_exti_bank stm32mp1_exti_b3 = {
- .imr_ofst = 0xA0,
- .emr_ofst = UNDEF_REG,
- .rtsr_ofst = 0x40,
- .ftsr_ofst = 0x44,
- .swier_ofst = 0x48,
- .rpr_ofst = 0x4C,
- .fpr_ofst = 0x50,
- .trg_ofst = 0x3E4,
- .seccfgr_ofst = 0x54,
-};
-
-static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
- &stm32mp1_exti_b1,
- &stm32mp1_exti_b2,
- &stm32mp1_exti_b3,
-};
-
-static struct irq_chip stm32_exti_h_chip;
-static struct irq_chip stm32_exti_h_chip_direct;
-
-#define EXTI_INVALID_IRQ U8_MAX
-#define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER_BANK)
-
-/*
- * Use some intentionally tricky logic here to initialize the whole array to
- * EXTI_INVALID_IRQ, but then override certain fields, requiring us to indicate
- * that we "know" that there are overrides in this structure, and we'll need to
- * disable that warning from W=1 builds.
- */
-__diag_push();
-__diag_ignore_all("-Woverride-init",
- "logic to initialize all and then override some is OK");
-
-static const u8 stm32mp1_desc_irq[] = {
- /* default value */
- [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
-
- [0] = 6,
- [1] = 7,
- [2] = 8,
- [3] = 9,
- [4] = 10,
- [5] = 23,
- [6] = 64,
- [7] = 65,
- [8] = 66,
- [9] = 67,
- [10] = 40,
- [11] = 42,
- [12] = 76,
- [13] = 77,
- [14] = 121,
- [15] = 127,
- [16] = 1,
- [19] = 3,
- [21] = 31,
- [22] = 33,
- [23] = 72,
- [24] = 95,
- [25] = 107,
- [26] = 37,
- [27] = 38,
- [28] = 39,
- [29] = 71,
- [30] = 52,
- [31] = 53,
- [32] = 82,
- [33] = 83,
- [46] = 151,
- [47] = 93,
- [48] = 138,
- [50] = 139,
- [52] = 140,
- [53] = 141,
- [54] = 135,
- [61] = 100,
- [65] = 144,
- [68] = 143,
- [70] = 62,
- [73] = 129,
-};
-
-static const u8 stm32mp13_desc_irq[] = {
- /* default value */
- [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
-
- [0] = 6,
- [1] = 7,
- [2] = 8,
- [3] = 9,
- [4] = 10,
- [5] = 24,
- [6] = 65,
- [7] = 66,
- [8] = 67,
- [9] = 68,
- [10] = 41,
- [11] = 43,
- [12] = 77,
- [13] = 78,
- [14] = 106,
- [15] = 109,
- [16] = 1,
- [19] = 3,
- [21] = 32,
- [22] = 34,
- [23] = 73,
- [24] = 93,
- [25] = 114,
- [26] = 38,
- [27] = 39,
- [28] = 40,
- [29] = 72,
- [30] = 53,
- [31] = 54,
- [32] = 83,
- [33] = 84,
- [44] = 96,
- [47] = 92,
- [48] = 116,
- [50] = 117,
- [52] = 118,
- [53] = 119,
- [68] = 63,
- [70] = 98,
-};
-
-__diag_pop();
-
-static const struct stm32_exti_drv_data stm32mp1_drv_data = {
- .exti_banks = stm32mp1_exti_banks,
- .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
- .desc_irqs = stm32mp1_desc_irq,
-};
-
-static const struct stm32_exti_drv_data stm32mp13_drv_data = {
- .exti_banks = stm32mp1_exti_banks,
- .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
- .desc_irqs = stm32mp13_desc_irq,
-};
-
static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
{
struct stm32_exti_chip_data *chip_data = gc->private;
const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
- unsigned long pending;
- pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
- if (stm32_bank->fpr_ofst != UNDEF_REG)
- pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
-
- return pending;
+ return irq_reg_readl(gc, stm32_bank->rpr_ofst);
}
static void stm32_irq_handler(struct irq_desc *desc)
@@ -380,33 +166,21 @@ static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct stm32_exti_chip_data *chip_data = gc->private;
const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
- struct hwspinlock *hwlock = chip_data->host_data->hwlock;
u32 rtsr, ftsr;
int err;
irq_gc_lock(gc);
- if (hwlock) {
- err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
- if (err) {
- pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
- goto unlock;
- }
- }
-
rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
if (err)
- goto unspinlock;
+ goto unlock;
irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
-unspinlock:
- if (hwlock)
- hwspin_unlock_in_atomic(hwlock);
unlock:
irq_gc_unlock(gc);
@@ -494,287 +268,10 @@ static void stm32_irq_ack(struct irq_data *d)
irq_gc_lock(gc);
irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
- if (stm32_bank->fpr_ofst != UNDEF_REG)
- irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
irq_gc_unlock(gc);
}
-/* directly set the target bit without reading first. */
-static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- void __iomem *base = chip_data->host_data->base;
- u32 val = BIT(d->hwirq % IRQS_PER_BANK);
-
- writel_relaxed(val, base + reg);
-}
-
-static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- void __iomem *base = chip_data->host_data->base;
- u32 val;
-
- val = readl_relaxed(base + reg);
- val |= BIT(d->hwirq % IRQS_PER_BANK);
- writel_relaxed(val, base + reg);
-
- return val;
-}
-
-static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- void __iomem *base = chip_data->host_data->base;
- u32 val;
-
- val = readl_relaxed(base + reg);
- val &= ~BIT(d->hwirq % IRQS_PER_BANK);
- writel_relaxed(val, base + reg);
-
- return val;
-}
-
-static void stm32_exti_h_eoi(struct irq_data *d)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
-
- raw_spin_lock(&chip_data->rlock);
-
- stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
- if (stm32_bank->fpr_ofst != UNDEF_REG)
- stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
-
- raw_spin_unlock(&chip_data->rlock);
-
- if (d->parent_data->chip)
- irq_chip_eoi_parent(d);
-}
-
-static void stm32_exti_h_mask(struct irq_data *d)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
-
- raw_spin_lock(&chip_data->rlock);
- chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
- raw_spin_unlock(&chip_data->rlock);
-
- if (d->parent_data->chip)
- irq_chip_mask_parent(d);
-}
-
-static void stm32_exti_h_unmask(struct irq_data *d)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
-
- raw_spin_lock(&chip_data->rlock);
- chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
- raw_spin_unlock(&chip_data->rlock);
-
- if (d->parent_data->chip)
- irq_chip_unmask_parent(d);
-}
-
-static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
- struct hwspinlock *hwlock = chip_data->host_data->hwlock;
- void __iomem *base = chip_data->host_data->base;
- u32 rtsr, ftsr;
- int err;
-
- raw_spin_lock(&chip_data->rlock);
-
- if (hwlock) {
- err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
- if (err) {
- pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
- goto unlock;
- }
- }
-
- rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
- ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
-
- err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
- if (err)
- goto unspinlock;
-
- writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
- writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
-
-unspinlock:
- if (hwlock)
- hwspin_unlock_in_atomic(hwlock);
-unlock:
- raw_spin_unlock(&chip_data->rlock);
-
- return err;
-}
-
-static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
-
- raw_spin_lock(&chip_data->rlock);
-
- if (on)
- chip_data->wake_active |= mask;
- else
- chip_data->wake_active &= ~mask;
-
- raw_spin_unlock(&chip_data->rlock);
-
- return 0;
-}
-
-static int stm32_exti_h_set_affinity(struct irq_data *d,
- const struct cpumask *dest, bool force)
-{
- if (d->parent_data->chip)
- return irq_chip_set_affinity_parent(d, dest, force);
-
- return IRQ_SET_MASK_OK_DONE;
-}
-
-static int stm32_exti_h_suspend(struct device *dev)
-{
- struct stm32_exti_host_data *host_data = dev_get_drvdata(dev);
- struct stm32_exti_chip_data *chip_data;
- int i;
-
- for (i = 0; i < host_data->drv_data->bank_nr; i++) {
- chip_data = &host_data->chips_data[i];
- stm32_chip_suspend(chip_data, chip_data->wake_active);
- }
-
- return 0;
-}
-
-static int stm32_exti_h_resume(struct device *dev)
-{
- struct stm32_exti_host_data *host_data = dev_get_drvdata(dev);
- struct stm32_exti_chip_data *chip_data;
- int i;
-
- for (i = 0; i < host_data->drv_data->bank_nr; i++) {
- chip_data = &host_data->chips_data[i];
- stm32_chip_resume(chip_data, chip_data->mask_cache);
- }
-
- return 0;
-}
-
-static int stm32_exti_h_retrigger(struct irq_data *d)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
- void __iomem *base = chip_data->host_data->base;
- u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
-
- writel_relaxed(mask, base + stm32_bank->swier_ofst);
-
- return 0;
-}
-
-static struct irq_chip stm32_exti_h_chip = {
- .name = "stm32-exti-h",
- .irq_eoi = stm32_exti_h_eoi,
- .irq_mask = stm32_exti_h_mask,
- .irq_unmask = stm32_exti_h_unmask,
- .irq_retrigger = stm32_exti_h_retrigger,
- .irq_set_type = stm32_exti_h_set_type,
- .irq_set_wake = stm32_exti_h_set_wake,
- .flags = IRQCHIP_MASK_ON_SUSPEND,
- .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
-};
-
-static struct irq_chip stm32_exti_h_chip_direct = {
- .name = "stm32-exti-h-direct",
- .irq_eoi = irq_chip_eoi_parent,
- .irq_ack = irq_chip_ack_parent,
- .irq_mask = stm32_exti_h_mask,
- .irq_unmask = stm32_exti_h_unmask,
- .irq_retrigger = irq_chip_retrigger_hierarchy,
- .irq_set_type = irq_chip_set_type_parent,
- .irq_set_wake = stm32_exti_h_set_wake,
- .flags = IRQCHIP_MASK_ON_SUSPEND,
- .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
-};
-
-static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
- unsigned int virq,
- unsigned int nr_irqs, void *data)
-{
- struct stm32_exti_host_data *host_data = dm->host_data;
- struct stm32_exti_chip_data *chip_data;
- u8 desc_irq;
- struct irq_fwspec *fwspec = data;
- struct irq_fwspec p_fwspec;
- irq_hw_number_t hwirq;
- int bank;
- u32 event_trg;
- struct irq_chip *chip;
-
- hwirq = fwspec->param[0];
- if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK)
- return -EINVAL;
-
- bank = hwirq / IRQS_PER_BANK;
- chip_data = &host_data->chips_data[bank];
-
- /* Check if event is reserved (Secure) */
- if (chip_data->event_reserved & BIT(hwirq % IRQS_PER_BANK)) {
- dev_err(host_data->dev, "event %lu is reserved, secure\n", hwirq);
- return -EPERM;
- }
-
- event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst);
- chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ?
- &stm32_exti_h_chip : &stm32_exti_h_chip_direct;
-
- irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
-
- if (host_data->dt_has_irqs_desc) {
- struct of_phandle_args out_irq;
- int ret;
-
- ret = of_irq_parse_one(host_data->dev->of_node, hwirq, &out_irq);
- if (ret)
- return ret;
- /* we only support one parent, so far */
- if (of_node_to_fwnode(out_irq.np) != dm->parent->fwnode)
- return -EINVAL;
-
- of_phandle_args_to_fwspec(out_irq.np, out_irq.args,
- out_irq.args_count, &p_fwspec);
-
- return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
- }
-
- if (!host_data->drv_data->desc_irqs)
- return -EINVAL;
-
- desc_irq = host_data->drv_data->desc_irqs[hwirq];
- if (desc_irq != EXTI_INVALID_IRQ) {
- p_fwspec.fwnode = dm->parent->fwnode;
- p_fwspec.param_count = 3;
- p_fwspec.param[0] = GIC_SPI;
- p_fwspec.param[1] = desc_irq;
- p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
-
- return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
- }
-
- return 0;
-}
-
static struct
stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
struct device_node *node)
@@ -822,19 +319,12 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
chip_data->host_data = h_data;
chip_data->reg_bank = stm32_bank;
- raw_spin_lock_init(&chip_data->rlock);
-
/*
* This IP has no reset, so after hot reboot we should
* clear registers to avoid residue
*/
writel_relaxed(0, base + stm32_bank->imr_ofst);
- if (stm32_bank->emr_ofst != UNDEF_REG)
- writel_relaxed(0, base + stm32_bank->emr_ofst);
-
- /* reserve Secure events */
- if (stm32_bank->seccfgr_ofst != UNDEF_REG)
- chip_data->event_reserved = readl_relaxed(base + stm32_bank->seccfgr_ofst);
+ writel_relaxed(0, base + stm32_bank->emr_ofst);
pr_info("%pOF: bank%d\n", node, bank_idx);
@@ -914,158 +404,6 @@ static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
return ret;
}
-static const struct irq_domain_ops stm32_exti_h_domain_ops = {
- .alloc = stm32_exti_h_domain_alloc,
- .free = irq_domain_free_irqs_common,
- .xlate = irq_domain_xlate_twocell,
-};
-
-static void stm32_exti_check_rif(struct stm32_exti_host_data *host_data)
-{
- unsigned int bank, i, event;
- u32 cid, cidcfgr, hwcfgr1;
-
- /* quit on CID not supported */
- hwcfgr1 = readl_relaxed(host_data->base + EXTI_HWCFGR1);
- if ((hwcfgr1 & EXTI_HWCFGR1_CIDWIDTH_MASK) == 0)
- return;
-
- for (bank = 0; bank < host_data->drv_data->bank_nr; bank++) {
- for (i = 0; i < IRQS_PER_BANK; i++) {
- event = bank * IRQS_PER_BANK + i;
- cidcfgr = readl_relaxed(host_data->base + EXTI_EnCIDCFGR(event));
- cid = (cidcfgr & EXTI_CIDCFGR_CID_MASK) >> EXTI_CIDCFGR_CID_SHIFT;
- if ((cidcfgr & EXTI_CIDCFGR_CFEN_MASK) && cid != EXTI_CID1)
- host_data->chips_data[bank].event_reserved |= BIT(i);
- }
- }
-}
-
-static void stm32_exti_remove_irq(void *data)
-{
- struct irq_domain *domain = data;
-
- irq_domain_remove(domain);
-}
-
-static int stm32_exti_probe(struct platform_device *pdev)
-{
- int ret, i;
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- struct irq_domain *parent_domain, *domain;
- struct stm32_exti_host_data *host_data;
- const struct stm32_exti_drv_data *drv_data;
-
- host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
- if (!host_data)
- return -ENOMEM;
-
- dev_set_drvdata(dev, host_data);
- host_data->dev = dev;
-
- /* check for optional hwspinlock which may be not available yet */
- ret = of_hwspin_lock_get_id(np, 0);
- if (ret == -EPROBE_DEFER)
- /* hwspinlock framework not yet ready */
- return ret;
-
- if (ret >= 0) {
- host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
- if (!host_data->hwlock) {
- dev_err(dev, "Failed to request hwspinlock\n");
- return -EINVAL;
- }
- } else if (ret != -ENOENT) {
- /* note: ENOENT is a valid case (means 'no hwspinlock') */
- dev_err(dev, "Failed to get hwspinlock\n");
- return ret;
- }
-
- /* initialize host_data */
- drv_data = of_device_get_match_data(dev);
- if (!drv_data) {
- dev_err(dev, "no of match data\n");
- return -ENODEV;
- }
- host_data->drv_data = drv_data;
-
- host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
- sizeof(*host_data->chips_data),
- GFP_KERNEL);
- if (!host_data->chips_data)
- return -ENOMEM;
-
- host_data->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(host_data->base))
- return PTR_ERR(host_data->base);
-
- for (i = 0; i < drv_data->bank_nr; i++)
- stm32_exti_chip_init(host_data, i, np);
-
- stm32_exti_check_rif(host_data);
-
- parent_domain = irq_find_host(of_irq_find_parent(np));
- if (!parent_domain) {
- dev_err(dev, "GIC interrupt-parent not found\n");
- return -EINVAL;
- }
-
- domain = irq_domain_add_hierarchy(parent_domain, 0,
- drv_data->bank_nr * IRQS_PER_BANK,
- np, &stm32_exti_h_domain_ops,
- host_data);
-
- if (!domain) {
- dev_err(dev, "Could not register exti domain\n");
- return -ENOMEM;
- }
-
- ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
- if (ret)
- return ret;
-
- if (of_property_read_bool(np, "interrupts-extended"))
- host_data->dt_has_irqs_desc = true;
-
- return 0;
-}
-
-/* platform driver only for MP1 */
-static const struct of_device_id stm32_exti_ids[] = {
- { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
- { .compatible = "st,stm32mp13-exti", .data = &stm32mp13_drv_data},
- {},
-};
-MODULE_DEVICE_TABLE(of, stm32_exti_ids);
-
-static const struct dev_pm_ops stm32_exti_dev_pm_ops = {
- NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_exti_h_suspend, stm32_exti_h_resume)
-};
-
-static struct platform_driver stm32_exti_driver = {
- .probe = stm32_exti_probe,
- .driver = {
- .name = "stm32_exti",
- .of_match_table = stm32_exti_ids,
- .pm = &stm32_exti_dev_pm_ops,
- },
-};
-
-static int __init stm32_exti_arch_init(void)
-{
- return platform_driver_register(&stm32_exti_driver);
-}
-
-static void __exit stm32_exti_arch_exit(void)
-{
- return platform_driver_unregister(&stm32_exti_driver);
-}
-
-arch_initcall(stm32_exti_arch_init);
-module_exit(stm32_exti_arch_exit);
-
-/* no platform driver for F4 and H7 */
static int __init stm32f4_exti_of_init(struct device_node *np,
struct device_node *parent)
{
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32mp-exti.c
similarity index 67%
copy from drivers/irqchip/irq-stm32-exti.c
copy to drivers/irqchip/irq-stm32mp-exti.c
index 2cc9f3b7d6690..8a45ece2e198f 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32mp-exti.c
@@ -1,18 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Maxime Coquelin 2015
- * Copyright (C) STMicroelectronics 2017
+ * Copyright (C) STMicroelectronics 2017-2024
* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
*/
#include <linux/bitops.h>
-#include <linux/delay.h>
#include <linux/hwspinlock.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
-#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
@@ -42,7 +40,6 @@
struct stm32_exti_bank {
u32 imr_ofst;
- u32 emr_ofst;
u32 rtsr_ofst;
u32 ftsr_ofst;
u32 swier_ofst;
@@ -52,8 +49,6 @@ struct stm32_exti_bank {
u32 seccfgr_ofst;
};
-#define UNDEF_REG ~0
-
struct stm32_exti_drv_data {
const struct stm32_exti_bank **exti_banks;
const u8 *desc_irqs;
@@ -80,77 +75,8 @@ struct stm32_exti_host_data {
bool dt_has_irqs_desc; /* skip internal desc_irqs array and get it from DT */
};
-static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
- .imr_ofst = 0x00,
- .emr_ofst = 0x04,
- .rtsr_ofst = 0x08,
- .ftsr_ofst = 0x0C,
- .swier_ofst = 0x10,
- .rpr_ofst = 0x14,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
-};
-
-static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
- &stm32f4xx_exti_b1,
-};
-
-static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
- .exti_banks = stm32f4xx_exti_banks,
- .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
-};
-
-static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
- .imr_ofst = 0x80,
- .emr_ofst = 0x84,
- .rtsr_ofst = 0x00,
- .ftsr_ofst = 0x04,
- .swier_ofst = 0x08,
- .rpr_ofst = 0x88,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
-};
-
-static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
- .imr_ofst = 0x90,
- .emr_ofst = 0x94,
- .rtsr_ofst = 0x20,
- .ftsr_ofst = 0x24,
- .swier_ofst = 0x28,
- .rpr_ofst = 0x98,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
-};
-
-static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
- .imr_ofst = 0xA0,
- .emr_ofst = 0xA4,
- .rtsr_ofst = 0x40,
- .ftsr_ofst = 0x44,
- .swier_ofst = 0x48,
- .rpr_ofst = 0xA8,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
-};
-
-static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
- &stm32h7xx_exti_b1,
- &stm32h7xx_exti_b2,
- &stm32h7xx_exti_b3,
-};
-
-static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
- .exti_banks = stm32h7xx_exti_banks,
- .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
-};
-
static const struct stm32_exti_bank stm32mp1_exti_b1 = {
.imr_ofst = 0x80,
- .emr_ofst = UNDEF_REG,
.rtsr_ofst = 0x00,
.ftsr_ofst = 0x04,
.swier_ofst = 0x08,
@@ -162,7 +88,6 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 = {
static const struct stm32_exti_bank stm32mp1_exti_b2 = {
.imr_ofst = 0x90,
- .emr_ofst = UNDEF_REG,
.rtsr_ofst = 0x20,
.ftsr_ofst = 0x24,
.swier_ofst = 0x28,
@@ -174,7 +99,6 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 = {
static const struct stm32_exti_bank stm32mp1_exti_b3 = {
.imr_ofst = 0xA0,
- .emr_ofst = UNDEF_REG,
.rtsr_ofst = 0x40,
.ftsr_ofst = 0x44,
.swier_ofst = 0x48,
@@ -314,42 +238,6 @@ static const struct stm32_exti_drv_data stm32mp13_drv_data = {
.desc_irqs = stm32mp13_desc_irq,
};
-static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
-{
- struct stm32_exti_chip_data *chip_data = gc->private;
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
- unsigned long pending;
-
- pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
- if (stm32_bank->fpr_ofst != UNDEF_REG)
- pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
-
- return pending;
-}
-
-static void stm32_irq_handler(struct irq_desc *desc)
-{
- struct irq_domain *domain = irq_desc_get_handler_data(desc);
- struct irq_chip *chip = irq_desc_get_chip(desc);
- unsigned int nbanks = domain->gc->num_chips;
- struct irq_chip_generic *gc;
- unsigned long pending;
- int n, i, irq_base = 0;
-
- chained_irq_enter(chip, desc);
-
- for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
- gc = irq_get_domain_generic_chip(domain, irq_base);
-
- while ((pending = stm32_exti_pending(gc))) {
- for_each_set_bit(n, &pending, IRQS_PER_BANK)
- generic_handle_domain_irq(domain, irq_base + n);
- }
- }
-
- chained_irq_exit(chip, desc);
-}
-
static int stm32_exti_set_type(struct irq_data *d,
unsigned int type, u32 *rtsr, u32 *ftsr)
{
@@ -375,44 +263,6 @@ static int stm32_exti_set_type(struct irq_data *d,
return 0;
}
-static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
-{
- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- struct stm32_exti_chip_data *chip_data = gc->private;
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
- struct hwspinlock *hwlock = chip_data->host_data->hwlock;
- u32 rtsr, ftsr;
- int err;
-
- irq_gc_lock(gc);
-
- if (hwlock) {
- err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
- if (err) {
- pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
- goto unlock;
- }
- }
-
- rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
- ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
-
- err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
- if (err)
- goto unspinlock;
-
- irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
- irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
-
-unspinlock:
- if (hwlock)
- hwspin_unlock_in_atomic(hwlock);
-unlock:
- irq_gc_unlock(gc);
-
- return err;
-}
-
static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
u32 wake_active)
{
@@ -439,67 +289,6 @@ static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
}
-static void stm32_irq_suspend(struct irq_chip_generic *gc)
-{
- struct stm32_exti_chip_data *chip_data = gc->private;
-
- irq_gc_lock(gc);
- stm32_chip_suspend(chip_data, gc->wake_active);
- irq_gc_unlock(gc);
-}
-
-static void stm32_irq_resume(struct irq_chip_generic *gc)
-{
- struct stm32_exti_chip_data *chip_data = gc->private;
-
- irq_gc_lock(gc);
- stm32_chip_resume(chip_data, gc->mask_cache);
- irq_gc_unlock(gc);
-}
-
-static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
- unsigned int nr_irqs, void *data)
-{
- struct irq_fwspec *fwspec = data;
- irq_hw_number_t hwirq;
-
- hwirq = fwspec->param[0];
-
- irq_map_generic_chip(d, virq, hwirq);
-
- return 0;
-}
-
-static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
- unsigned int nr_irqs)
-{
- struct irq_data *data = irq_domain_get_irq_data(d, virq);
-
- irq_domain_reset_irq_data(data);
-}
-
-static const struct irq_domain_ops irq_exti_domain_ops = {
- .map = irq_map_generic_chip,
- .alloc = stm32_exti_alloc,
- .free = stm32_exti_free,
- .xlate = irq_domain_xlate_twocell,
-};
-
-static void stm32_irq_ack(struct irq_data *d)
-{
- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- struct stm32_exti_chip_data *chip_data = gc->private;
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
-
- irq_gc_lock(gc);
-
- irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
- if (stm32_bank->fpr_ofst != UNDEF_REG)
- irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
-
- irq_gc_unlock(gc);
-}
-
/* directly set the target bit without reading first. */
static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
{
@@ -544,8 +333,7 @@ static void stm32_exti_h_eoi(struct irq_data *d)
raw_spin_lock(&chip_data->rlock);
stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
- if (stm32_bank->fpr_ofst != UNDEF_REG)
- stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
+ stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
raw_spin_unlock(&chip_data->rlock);
@@ -775,39 +563,6 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
return 0;
}
-static struct
-stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
- struct device_node *node)
-{
- struct stm32_exti_host_data *host_data;
-
- host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
- if (!host_data)
- return NULL;
-
- host_data->drv_data = dd;
- host_data->chips_data = kcalloc(dd->bank_nr,
- sizeof(struct stm32_exti_chip_data),
- GFP_KERNEL);
- if (!host_data->chips_data)
- goto free_host_data;
-
- host_data->base = of_iomap(node, 0);
- if (!host_data->base) {
- pr_err("%pOF: Unable to map registers\n", node);
- goto free_chips_data;
- }
-
- return host_data;
-
-free_chips_data:
- kfree(host_data->chips_data);
-free_host_data:
- kfree(host_data);
-
- return NULL;
-}
-
static struct
stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
u32 bank_idx,
@@ -829,91 +584,15 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
* clear registers to avoid residue
*/
writel_relaxed(0, base + stm32_bank->imr_ofst);
- if (stm32_bank->emr_ofst != UNDEF_REG)
- writel_relaxed(0, base + stm32_bank->emr_ofst);
/* reserve Secure events */
- if (stm32_bank->seccfgr_ofst != UNDEF_REG)
- chip_data->event_reserved = readl_relaxed(base + stm32_bank->seccfgr_ofst);
+ chip_data->event_reserved = readl_relaxed(base + stm32_bank->seccfgr_ofst);
pr_info("%pOF: bank%d\n", node, bank_idx);
return chip_data;
}
-static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
- struct device_node *node)
-{
- struct stm32_exti_host_data *host_data;
- unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
- int nr_irqs, ret, i;
- struct irq_chip_generic *gc;
- struct irq_domain *domain;
-
- host_data = stm32_exti_host_init(drv_data, node);
- if (!host_data)
- return -ENOMEM;
-
- domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
- &irq_exti_domain_ops, NULL);
- if (!domain) {
- pr_err("%pOFn: Could not register interrupt domain.\n",
- node);
- ret = -ENOMEM;
- goto out_unmap;
- }
-
- ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
- handle_edge_irq, clr, 0, 0);
- if (ret) {
- pr_err("%pOF: Could not allocate generic interrupt chip.\n",
- node);
- goto out_free_domain;
- }
-
- for (i = 0; i < drv_data->bank_nr; i++) {
- const struct stm32_exti_bank *stm32_bank;
- struct stm32_exti_chip_data *chip_data;
-
- stm32_bank = drv_data->exti_banks[i];
- chip_data = stm32_exti_chip_init(host_data, i, node);
-
- gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
-
- gc->reg_base = host_data->base;
- gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
- gc->chip_types->chip.irq_ack = stm32_irq_ack;
- gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
- gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
- gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
- gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
- gc->suspend = stm32_irq_suspend;
- gc->resume = stm32_irq_resume;
- gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
-
- gc->chip_types->regs.mask = stm32_bank->imr_ofst;
- gc->private = (void *)chip_data;
- }
-
- nr_irqs = of_irq_count(node);
- for (i = 0; i < nr_irqs; i++) {
- unsigned int irq = irq_of_parse_and_map(node, i);
-
- irq_set_handler_data(irq, domain);
- irq_set_chained_handler(irq, stm32_irq_handler);
- }
-
- return 0;
-
-out_free_domain:
- irq_domain_remove(domain);
-out_unmap:
- iounmap(host_data->base);
- kfree(host_data->chips_data);
- kfree(host_data);
- return ret;
-}
-
static const struct irq_domain_ops stm32_exti_h_domain_ops = {
.alloc = stm32_exti_h_domain_alloc,
.free = irq_domain_free_irqs_common,
@@ -1031,7 +710,6 @@ static int stm32_exti_probe(struct platform_device *pdev)
return 0;
}
-/* platform driver only for MP1 */
static const struct of_device_id stm32_exti_ids[] = {
{ .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
{ .compatible = "st,stm32mp13-exti", .data = &stm32mp13_drv_data},
@@ -1064,20 +742,3 @@ static void __exit stm32_exti_arch_exit(void)
arch_initcall(stm32_exti_arch_init);
module_exit(stm32_exti_arch_exit);
-
-/* no platform driver for F4 and H7 */
-static int __init stm32f4_exti_of_init(struct device_node *np,
- struct device_node *parent)
-{
- return stm32_exti_init(&stm32f4xx_drv_data, np);
-}
-
-IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
-
-static int __init stm32h7_exti_of_init(struct device_node *np,
- struct device_node *parent)
-{
- return stm32_exti_init(&stm32h7xx_drv_data, np);
-}
-
-IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 2%]
* [PATCH] clkdev: fix potential NULL pointer dereference
[not found] <CGME20240507064445eucas1p1bfc17da4f824ef46567774634482f12f@eucas1p1.samsung.com>
@ 2024-05-07 6:44 5% ` Marek Szyprowski
0 siblings, 0 replies; 200+ results
From: Marek Szyprowski @ 2024-05-07 6:44 UTC (permalink / raw)
To: linux-clk, linux-arm-kernel, linux-kernel
Cc: Marek Szyprowski, Russell King, Michael Turquette, Stephen Boyd
dev_fmt argument is optional, so avoid dereferencing it unconditionally.
Fixes: 4d11c62ca8d7 ("clkdev: report over-sized strings when creating clkdev entries")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
This fixes the following kernel panic observed on Samsung Exynos542x
SoCs family:
8<--- cut here ---
Unable to handle kernel NULL pointer dereference at virtual address 00000000 when read
[00000000] *pgd=00000000
Internal error: Oops: 5 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.8.0-00001-g4d11c62ca8d7 #14975
Hardware name: Samsung Exynos (Flattened Device Tree)
PC is at vsnprintf+0x4c/0x3c8
LR is at init_stack+0x1dd6/0x2000
pc : [<c0c09d3c>] lr : [<c1301dd6>] psr: 800000d3
...
Flags: Nzcv IRQs off FIQs off Mode SVC_32 ISA ARM Segment none
Control: 10c5387d Table: 4000406a DAC: 00000051
...
Process swapper/0 (pid: 0, stack limit = 0x(ptrval))
Stack: (0xc1301c70 to 0xc1302000)
...
vsnprintf from va_format.constprop.0+0x70/0x160
va_format.constprop.0 from pointer+0x454/0x670
pointer from vsnprintf+0x228/0x3c8
vsnprintf from vprintk_store+0x100/0x428
vprintk_store from vprintk_emit+0x6c/0x328
vprintk_emit from vprintk_default+0x24/0x2c
vprintk_default from _printk+0x28/0x4c
_printk from vclkdev_alloc+0xf0/0x110
vclkdev_alloc from clkdev_hw_create+0x28/0x88
clkdev_hw_create from clk_hw_register_clkdev+0x38/0x3c
clk_hw_register_clkdev from samsung_clk_register_fixed_rate+0xa4/0xd4
samsung_clk_register_fixed_rate from exynos5x_clk_init+0xf0/0x2b0
exynos5x_clk_init from of_clk_init+0x15c/0x228
of_clk_init from time_init+0x24/0x30
time_init from start_kernel+0x4b8/0x620
start_kernel from 0x0
Code: e09e9001 e1a05002 e28da01c 2a000086 (e5d50000)
---[ end trace 0000000000000000 ]---
Kernel panic - not syncing: Attempted to kill the idle task!
---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---
Best regards
Marek Szyprowski, PhD
Samsung R&D Institute Poland
---
drivers/clk/clkdev.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index ddacab7863d0..d2801ae70e34 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -194,10 +194,12 @@ vclkdev_alloc(struct clk_hw *hw, const char *con_id, const char *dev_fmt,
return &cla->cl;
fail:
- fmt.fmt = dev_fmt;
- fmt.va = &ap_copy;
- pr_err("%pV:%s: %s ID is greater than %zu\n",
- &fmt, con_id, failure, max_size);
+ if (dev_fmt) {
+ fmt.fmt = dev_fmt;
+ fmt.va = &ap_copy;
+ pr_err("%pV:%s: %s ID is greater than %zu\n",
+ &fmt, con_id, failure, max_size);
+ }
va_end(ap_copy);
kfree(cla);
return NULL;
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* Re: [PATCH v2 1/2] media: bcm2835-unicam: Do not replace IRQ retcode during probe
2024-05-06 19:24 7% ` [PATCH v2 1/2] media: bcm2835-unicam: Do not replace IRQ retcode " Ricardo Ribalda
@ 2024-05-07 6:08 0% ` Laurent Pinchart
0 siblings, 0 replies; 200+ results
From: Laurent Pinchart @ 2024-05-07 6:08 UTC (permalink / raw)
To: Ricardo Ribalda
Cc: Mauro Carvalho Chehab, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
linux-media, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Hans Verkuil
Hi Ricardo,
Thank you for the patch.
On Mon, May 06, 2024 at 07:24:46PM +0000, Ricardo Ribalda wrote:
> platform_get_irq() cannot return the value 0. It will either return a non-zero
> irq or a errcode.
>
> If a errcode is returned, we need to populate the error code upwards. It will
> give a more accurate reason of why it failed to the caller, who might decide
> to retry later.
>
> Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Aren't git commit messages supposed to be wrapped at 72 columns ?
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> drivers/media/platform/broadcom/bcm2835-unicam.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/media/platform/broadcom/bcm2835-unicam.c b/drivers/media/platform/broadcom/bcm2835-unicam.c
> index bd2bbb53070e..60c0fe956c58 100644
> --- a/drivers/media/platform/broadcom/bcm2835-unicam.c
> +++ b/drivers/media/platform/broadcom/bcm2835-unicam.c
> @@ -2660,9 +2660,8 @@ static int unicam_probe(struct platform_device *pdev)
> }
>
> ret = platform_get_irq(pdev, 0);
> - if (ret <= 0) {
> + if (ret < 0) {
> dev_err(&pdev->dev, "No IRQ resource\n");
> - ret = -EINVAL;
> goto err_unicam_put;
> }
>
> @@ -2670,7 +2669,6 @@ static int unicam_probe(struct platform_device *pdev)
> "unicam_capture0", unicam);
> if (ret) {
> dev_err(&pdev->dev, "Unable to request interrupt\n");
> - ret = -EINVAL;
> goto err_unicam_put;
> }
>
--
Regards,
Laurent Pinchart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* [PATCH v2 1/2] media: bcm2835-unicam: Do not replace IRQ retcode during probe
@ 2024-05-06 19:24 7% ` Ricardo Ribalda
2024-05-07 6:08 0% ` Laurent Pinchart
0 siblings, 1 reply; 200+ results
From: Ricardo Ribalda @ 2024-05-06 19:24 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden
Cc: linux-media, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Hans Verkuil, Ricardo Ribalda
platform_get_irq() cannot return the value 0. It will either return a non-zero
irq or a errcode.
If a errcode is returned, we need to populate the error code upwards. It will
give a more accurate reason of why it failed to the caller, who might decide
to retry later.
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
---
drivers/media/platform/broadcom/bcm2835-unicam.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/media/platform/broadcom/bcm2835-unicam.c b/drivers/media/platform/broadcom/bcm2835-unicam.c
index bd2bbb53070e..60c0fe956c58 100644
--- a/drivers/media/platform/broadcom/bcm2835-unicam.c
+++ b/drivers/media/platform/broadcom/bcm2835-unicam.c
@@ -2660,9 +2660,8 @@ static int unicam_probe(struct platform_device *pdev)
}
ret = platform_get_irq(pdev, 0);
- if (ret <= 0) {
+ if (ret < 0) {
dev_err(&pdev->dev, "No IRQ resource\n");
- ret = -EINVAL;
goto err_unicam_put;
}
@@ -2670,7 +2669,6 @@ static int unicam_probe(struct platform_device *pdev)
"unicam_capture0", unicam);
if (ret) {
dev_err(&pdev->dev, "Unable to request interrupt\n");
- ret = -EINVAL;
goto err_unicam_put;
}
--
2.45.0.rc1.225.g2a3ae87e7f-goog
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 7%]
* Re: [PATCH 3/3] media: bcm2835-unicam: Do not replace IRQ retcode during probe
2024-04-30 7:51 7% ` [PATCH 3/3] media: bcm2835-unicam: Do not replace IRQ retcode " Ricardo Ribalda
@ 2024-05-06 18:03 0% ` Laurent Pinchart
0 siblings, 0 replies; 200+ results
From: Laurent Pinchart @ 2024-05-06 18:03 UTC (permalink / raw)
To: Ricardo Ribalda
Cc: Mauro Carvalho Chehab, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
linux-media, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Hans Verkuil
Hi Ricardo,
Thank you for the patch.
On Tue, Apr 30, 2024 at 07:51:28AM +0000, Ricardo Ribalda wrote:
> Use the error code generated by platform_get_irq() and
> devm_request_irq() as the error code of probe().
>
> It will give a more accurate reason of why it failed.
>
> Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
> ---
> drivers/media/platform/broadcom/bcm2835-unicam.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/media/platform/broadcom/bcm2835-unicam.c b/drivers/media/platform/broadcom/bcm2835-unicam.c
> index b2b23d24da19..0b2729bf4a36 100644
> --- a/drivers/media/platform/broadcom/bcm2835-unicam.c
> +++ b/drivers/media/platform/broadcom/bcm2835-unicam.c
> @@ -2660,17 +2660,13 @@ static int unicam_probe(struct platform_device *pdev)
> }
>
> ret = platform_get_irq(pdev, 0);
> - if (ret < 0) {
> - if (ret != -EPROBE_DEFER)
> - ret = -EINVAL;
> + if (ret < 0)
> goto err_unicam_put;
> - }
I think you can squash the whole patch with 1/3.
>
> ret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,
> "unicam_capture0", unicam);
> if (ret) {
> dev_err(&pdev->dev, "Unable to request interrupt\n");
> - ret = -EINVAL;
> goto err_unicam_put;
> }
>
--
Regards,
Laurent Pinchart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [BUG] drm: zynqmp_dp: Lockup in zynqmp_dp_bridge_detect when device is unbound
@ 2024-05-06 14:46 4% ` Sean Anderson
0 siblings, 0 replies; 200+ results
From: Sean Anderson @ 2024-05-06 14:46 UTC (permalink / raw)
To: Tomi Valkeinen, Laurent Pinchart
Cc: Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
David Airlie, Daniel Vetter, Michal Simek, dri-devel,
linux-arm-kernel, linux-kernel
On 5/6/24 07:16, Tomi Valkeinen wrote:
> Hi,
>
> On 04/05/2024 00:54, Sean Anderson wrote:
>> Hi,
>>
>> I have discovered a bug in the displayport driver on drm-misc-next. To
>> trigger it, run
>>
>> echo fd4a0000.display > /sys/bus/platform/drivers/zynqmp-dpsub/unbind
>>
>> The system will become unresponsive and (after a bit) splat with a hard
>> LOCKUP. One core will be unresponsive at the first zynqmp_dp_read in
>> zynqmp_dp_bridge_detect.
>>
>> I believe the issue is due the registers being unmapped and the block
>> put into reset in zynqmp_dp_remove instead of zynqmp_dpsub_release. This
>> could be resolved by deferring things until zynqmp_dpsub_release
>> (requiring us to skip devm_*), or by adding a flag to struct zynqmp_dp
>> and checking it before each callback. A subsystem-level implementation
>> might be better for the latter.
>>
>> For a better traceback, try applying the below patch and running the
>> following commands before triggering the lockup:
>>
>> echo 4 > /sys/module/drm/parameters/debug
>> echo 8 > /proc/sys/kernel/printk
>
> I wasn't able to reproduce. Where does the detect call come in your case? Looking at the code, afaics, it shouldn't happen.
# echo fd4a0000.display > /sys/bus/platform/drivers/zynqmp-dpsub/unbind
[234105.917005] Console: switching to colour dummy device 80x25
[234105.962474] zynqmp-dpsub fd4a0000.display: [drm:drm_client_release] fbdev
[234105.970397] zynqmp-dpsub fd4a0000.display: [drm:drm_sysfs_connector_remove] [CONNECTOR:41:DP-1] removing connector from sysfs
[234105.991669] zynqmp-dpsub fd4a0000.display: [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:41:DP-1]
[234106.001833] ------------[ cut here ]------------
[234106.006570] WARNING: CPU: 2 PID: 527 at drivers/gpu/drm/xlnx/zynqmp_dp.c:1537 zynqmp_dp_bridge_detect (drivers/gpu/drm/xlnx/zynqmp_dp.c:1537 (discriminator 1))
[234106.016960] Modules linked in:
[234106.021306] CPU: 2 PID: 527 Comm: Xorg Not tainted 6.9.0-rc6+ #34
[234106.027858] Hardware name: xlnx,zynqmp (DT)
[234106.032146] pstate: a0000005 (NzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[234106.039219] pc : zynqmp_dp_bridge_detect (drivers/gpu/drm/xlnx/zynqmp_dp.c:1537 (discriminator 1))
[234106.044297] lr : drm_bridge_connector_detect (drivers/gpu/drm/drm_bridge_connector.c:176)
[234106.049548] sp : ffffffc0895bb980
[234106.052968] x29: ffffffc0895bb980 x28: ffffff8805fe1000 x27: ffffffc0818ff000
[234106.060251] x26: 0000000000000001 x25: 0000000000000050 x24: 0000000000001000
[234106.067534] x23: 0000000000001000 x22: ffffff8805fe0030 x21: ffffff8805fe1000
[234106.074816] x20: ffffffc0895bbae8 x19: ffffff8805fe1000 x18: 0000000000005550
[234106.082099] x17: 6e6e6f635f656c67 x16: 6e69735f65626f72 x15: 705f7265706c6568
[234106.089382] x14: 5f6d72643a6d7264 x13: 0000000000000000 x12: 0000000000000000
[234106.096664] x11: 00000000000002c5 x10: 00000000000002c5 x9 : 00000000000402c5
[234106.103947] x8 : 0000000095d72cee x7 : 00000000f1c4be6a x6 : ffffffc082707b78
[234106.111229] x5 : 0000000000000000 x4 : ffffff8801f20000 x3 : 0000000000000000
[234106.118512] x2 : ffffffc080a5a2bc x1 : 0123456789abcdef x0 : deadbeefdeadbeef
[234106.125795] Call trace:
[234106.128347] zynqmp_dp_bridge_detect (drivers/gpu/drm/xlnx/zynqmp_dp.c:1537 (discriminator 1))
[234106.133077] drm_bridge_connector_detect (drivers/gpu/drm/drm_bridge_connector.c:176)
[234106.137981] drm_helper_probe_detect (drivers/gpu/drm/drm_probe_helper.c:407)
[234106.142538] drm_helper_probe_single_connector_modes (drivers/gpu/drm/drm_probe_helper.c:596)
[234106.148658] drm_mode_getconnector (drivers/gpu/drm/drm_connector.c:2947)
[234106.153215] drm_ioctl_kernel (drivers/gpu/drm/drm_ioctl.c:744 (discriminator 1))
[234106.157251] drm_ioctl (drivers/gpu/drm/drm_ioctl.c:841)
[234106.160767] __arm64_sys_ioctl (fs/ioctl.c:52 fs/ioctl.c:904 fs/ioctl.c:890 fs/ioctl.c:890)
[234106.164803] invoke_syscall (arch/arm64/include/asm/current.h:19 arch/arm64/kernel/syscall.c:53)
[234106.168665] el0_svc_common.constprop.0 (arch/arm64/kernel/syscall.c:140)
[234106.173483] do_el0_svc (arch/arm64/kernel/syscall.c:153)
[234106.176911] el0_svc (arch/arm64/include/asm/irqflags.h:83 arch/arm64/include/asm/irqflags.h:124 arch/arm64/include/asm/irqflags.h:137 arch/arm64/kernel/entry-common.c:165 arch/arm64/kernel/entry-common.c:178 arch/arm64/kernel/entry-common.c:713)
[234106.180166] el0t_64_sync_handler (arch/arm64/kernel/entry-common.c:731)
[234106.184637] el0t_64_sync (arch/arm64/kernel/entry.S:598)
[234106.188413] irq event stamp: 348036
[234106.192006] hardirqs last enabled at (348035): console_unlock (arch/arm64/include/asm/irqflags.h:83 arch/arm64/include/asm/irqflags.h:124 arch/arm64/include/asm/irqflags.h:137 kernel/printk/printk.c:341 kernel/printk/printk.c:2731 kernel/printk/printk.c:3050)
[234106.200816] hardirqs last disabled at (348036): el1_dbg (arch/arm64/kernel/entry-common.c:371 (discriminator 4) arch/arm64/kernel/entry-common.c:471 (discriminator 4))
[234106.208845] softirqs last enabled at (348030): __do_softirq (arch/arm64/include/asm/current.h:19 arch/arm64/include/asm/preempt.h:13 kernel/softirq.c:401 kernel/softirq.c:583)
[234106.217482] softirqs last disabled at (348023): ____do_softirq (arch/arm64/kernel/irq.c:82)
[234106.226119] ---[ end trace 0000000000000000 ]---
[234106.230974] Unable to handle kernel paging request at virtual address ffffffc08562d130
[234106.239055] Mem abort info:
[234106.242008] ESR = 0x0000000096000007
[234106.245872] EC = 0x25: DABT (current EL), IL = 32 bits
[234106.251375] SET = 0, FnV = 0
[234106.254584] EA = 0, S1PTW = 0
[234106.257841] FSC = 0x07: level 3 translation fault
[234106.262874] Data abort info:
[234106.265870] ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000
[234106.271548] CM = 0, WnR = 0, TnD = 0, TagAccess = 0
[234106.276763] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
[234106.282240] swapper pgtable: 4k pages, 39-bit VAs, pgdp=0000000001a8d000
[234106.289107] [ffffffc08562d130] pgd=10000000033d8003, p4d=10000000033d8003, pud=10000000033d8003, pmd=10000008038ce003, pte=0000000000000000
[234106.302368] Internal error: Oops: 0000000096000007 [#1] SMP
[234106.308029] Modules linked in:
[234106.311169] CPU: 2 PID: 527 Comm: Xorg Tainted: G W 6.9.0-rc6+ #34
[234106.319170] Hardware name: xlnx,zynqmp (DT)
[234106.323433] pstate: a0000005 (NzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[234106.330480] pc : zynqmp_dp_bridge_detect (arch/arm64/include/asm/io.h:79 include/asm-generic/io.h:223 drivers/gpu/drm/xlnx/zynqmp_dp.c:335 drivers/gpu/drm/xlnx/zynqmp_dp.c:1544)
[234106.335455] lr : drm_bridge_connector_detect (drivers/gpu/drm/drm_bridge_connector.c:176)
[234106.340679] sp : ffffffc0895bb980
[234106.344073] x29: ffffffc0895bb980 x28: ffffff8805fe1000 x27: ffffffc0818ff000
[234106.351304] x26: 0000000000000001 x25: 0000000000000050 x24: 0000000000001000
[234106.358534] x23: 0000000000001000 x22: ffffff8805fe0030 x21: ffffff8805fe0000
[234106.365765] x20: ffffffc0895bbae8 x19: 000000000000000a x18: 0000000000005550
[234106.372995] x17: 6e6e6f635f656c67 x16: 6e69735f65626f72 x15: 705f7265706c6568
[234106.380226] x14: 5f6d72643a6d7264 x13: 0000000000000000 x12: 0000000000000000
[234106.387456] x11: 00000000000002c5 x10: 00000000000002c5 x9 : 00000000000402c5
[234106.394687] x8 : 0000000095d72cee x7 : 00000000f1c4be6a x6 : ffffffc082707b78
[234106.401917] x5 : 0000000000000000 x4 : ffffff8801f20000 x3 : 0000000000000000
[234106.409148] x2 : ffffffc080a5a2bc x1 : ffffffc08562d130 x0 : deadbeefdeadbeef
[234106.416379] Call trace:
[234106.418904] zynqmp_dp_bridge_detect (arch/arm64/include/asm/io.h:79 include/asm-generic/io.h:223 drivers/gpu/drm/xlnx/zynqmp_dp.c:335 drivers/gpu/drm/xlnx/zynqmp_dp.c:1544)
[234106.423522] drm_bridge_connector_detect (drivers/gpu/drm/drm_bridge_connector.c:176)
[234106.428400] drm_helper_probe_detect (drivers/gpu/drm/drm_probe_helper.c:407)
[234106.432931] drm_helper_probe_single_connector_modes (drivers/gpu/drm/drm_probe_helper.c:596)
[234106.439025] drm_mode_getconnector (drivers/gpu/drm/drm_connector.c:2947)
[234106.443556] drm_ioctl_kernel (drivers/gpu/drm/drm_ioctl.c:744 (discriminator 1))
[234106.447566] drm_ioctl (drivers/gpu/drm/drm_ioctl.c:841)
[234106.451055] __arm64_sys_ioctl (fs/ioctl.c:52 fs/ioctl.c:904 fs/ioctl.c:890 fs/ioctl.c:890)
[234106.455066] invoke_syscall (arch/arm64/include/asm/current.h:19 arch/arm64/kernel/syscall.c:53)
[234106.458902] el0_svc_common.constprop.0 (arch/arm64/kernel/syscall.c:140)
[234106.463693] do_el0_svc (arch/arm64/kernel/syscall.c:153)
[234106.467096] el0_svc (arch/arm64/include/asm/irqflags.h:83 arch/arm64/include/asm/irqflags.h:124 arch/arm64/include/asm/irqflags.h:137 arch/arm64/kernel/entry-common.c:165 arch/arm64/kernel/entry-common.c:178 arch/arm64/kernel/entry-common.c:713)
[234106.470325] el0t_64_sync_handler (arch/arm64/kernel/entry-common.c:731)
[234106.474769] el0t_64_sync (arch/arm64/kernel/entry.S:598)
[234106.478524] Code: d100c2d5 52800153 f9400ea1 9104c021 (b9400021)
All code
========
0: d100c2d5 sub x21, x22, #0x30
4: 52800153 mov w19, #0xa // #10
8: f9400ea1 ldr x1, [x21, #24]
c: 9104c021 add x1, x1, #0x130
10:* b9400021 ldr w1, [x1] <-- trapping instruction
Code starting with the faulting instruction
===========================================
0: b9400021 ldr w1, [x1]
[234106.484704] ---[ end trace 0000000000000000 ]---
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [relevance 4%]
* [PATCH v4 5/5] PCI: kirin: Convert to agnostic GPIO API
2024-05-06 14:20 11% ` [PATCH v4 4/5] PCI: imx6: Convert " Andy Shevchenko
@ 2024-05-06 14:20 16% ` Andy Shevchenko
1 sibling, 0 replies; 200+ results
From: Andy Shevchenko @ 2024-05-06 14:20 UTC (permalink / raw)
To: Manivannan Sadhasivam, Frank Li, Krzysztof Wilczyński,
Andy Shevchenko, linux-omap, linux-pci, linux-arm-kernel,
linux-kernel, imx, linux-amlogic, linux-arm-msm, linux-tegra
Cc: Vignesh Raghavendra, Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár, Linus Walleij
The of_gpio.h is going to be removed. In preparation of that convert
the driver to the agnostic API.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pci/controller/dwc/pcie-kirin.c | 105 ++++++++----------------
1 file changed, 35 insertions(+), 70 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
index d5523f302102..d1f54f188e71 100644
--- a/drivers/pci/controller/dwc/pcie-kirin.c
+++ b/drivers/pci/controller/dwc/pcie-kirin.c
@@ -12,12 +12,10 @@
#include <linux/compiler.h>
#include <linux/delay.h>
#include <linux/err.h>
-#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
-#include <linux/of_gpio.h>
#include <linux/of_pci.h>
#include <linux/phy/phy.h>
#include <linux/pci.h>
@@ -78,16 +76,16 @@ struct kirin_pcie {
void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */
/* DWC PERST# */
- int gpio_id_dwc_perst;
+ struct gpio_desc *id_dwc_perst_gpio;
/* Per-slot PERST# */
int num_slots;
- int gpio_id_reset[MAX_PCI_SLOTS];
+ struct gpio_desc *id_reset_gpio[MAX_PCI_SLOTS];
const char *reset_names[MAX_PCI_SLOTS];
/* Per-slot clkreq */
int n_gpio_clkreq;
- int gpio_id_clkreq[MAX_PCI_SLOTS];
+ struct gpio_desc *id_clkreq_gpio[MAX_PCI_SLOTS];
const char *clkreq_names[MAX_PCI_SLOTS];
};
@@ -381,15 +379,20 @@ static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie,
pcie->n_gpio_clkreq = ret;
for (i = 0; i < pcie->n_gpio_clkreq; i++) {
- pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node,
- "hisilicon,clken-gpios", i);
- if (pcie->gpio_id_clkreq[i] < 0)
- return pcie->gpio_id_clkreq[i];
+ pcie->id_clkreq_gpio[i] = devm_gpiod_get_index(dev,
+ "hisilicon,clken", i,
+ GPIOD_OUT_LOW);
+ if (IS_ERR(pcie->id_clkreq_gpio[i]))
+ return dev_err_probe(dev, PTR_ERR(pcie->id_clkreq_gpio[i]),
+ "unable to get a valid clken gpio\n");
pcie->clkreq_names[i] = devm_kasprintf(dev, GFP_KERNEL,
"pcie_clkreq_%d", i);
if (!pcie->clkreq_names[i])
return -ENOMEM;
+
+ gpiod_set_consumer_name(pcie->id_clkreq_gpio[i],
+ pcie->clkreq_names[i]);
}
return 0;
@@ -407,10 +410,16 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
for_each_available_child_of_node(parent, child) {
i = pcie->num_slots;
- pcie->gpio_id_reset[i] = of_get_named_gpio(child,
- "reset-gpios", 0);
- if (pcie->gpio_id_reset[i] < 0)
- continue;
+ pcie->id_reset_gpio[i] = devm_fwnode_gpiod_get_index(dev,
+ of_fwnode_handle(child),
+ "reset", 0, GPIOD_OUT_LOW,
+ NULL);
+ if (IS_ERR(pcie->id_reset_gpio[i])) {
+ if (PTR_ERR(pcie->id_reset_gpio[i]) == -ENOENT)
+ continue;
+ return dev_err_probe(dev, PTR_ERR(pcie->id_reset_gpio[i]),
+ "unable to get a valid reset gpio\n");
+ }
pcie->num_slots++;
if (pcie->num_slots > MAX_PCI_SLOTS) {
@@ -434,6 +443,9 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
ret = -ENOMEM;
goto put_node;
}
+
+ gpiod_set_consumer_name(pcie->id_reset_gpio[i],
+ pcie->reset_names[i]);
}
}
@@ -463,14 +475,11 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
return PTR_ERR(kirin_pcie->apb);
/* pcie internal PERST# gpio */
- kirin_pcie->gpio_id_dwc_perst = of_get_named_gpio(dev->of_node,
- "reset-gpios", 0);
- if (kirin_pcie->gpio_id_dwc_perst == -EPROBE_DEFER) {
- return -EPROBE_DEFER;
- } else if (!gpio_is_valid(kirin_pcie->gpio_id_dwc_perst)) {
- dev_err(dev, "unable to get a valid gpio pin\n");
- return -ENODEV;
- }
+ kirin_pcie->id_dwc_perst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(kirin_pcie->id_dwc_perst_gpio))
+ return dev_err_probe(dev, PTR_ERR(kirin_pcie->id_dwc_perst_gpio),
+ "unable to get a valid gpio pin\n");
+ gpiod_set_consumer_name(kirin_pcie->id_dwc_perst_gpio, "pcie_perst_bridge");
ret = kirin_pcie_get_gpio_enable(kirin_pcie, pdev);
if (ret)
@@ -553,7 +562,7 @@ static int kirin_pcie_add_bus(struct pci_bus *bus)
/* Send PERST# to each slot */
for (i = 0; i < kirin_pcie->num_slots; i++) {
- ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1);
+ ret = gpiod_direction_output_raw(kirin_pcie->id_reset_gpio[i], 1);
if (ret) {
dev_err(pci->dev, "PERST# %s error: %d\n",
kirin_pcie->reset_names[i], ret);
@@ -623,44 +632,6 @@ static int kirin_pcie_host_init(struct dw_pcie_rp *pp)
return 0;
}
-static int kirin_pcie_gpio_request(struct kirin_pcie *kirin_pcie,
- struct device *dev)
-{
- int ret, i;
-
- for (i = 0; i < kirin_pcie->num_slots; i++) {
- if (!gpio_is_valid(kirin_pcie->gpio_id_reset[i])) {
- dev_err(dev, "unable to get a valid %s gpio\n",
- kirin_pcie->reset_names[i]);
- return -ENODEV;
- }
-
- ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i],
- kirin_pcie->reset_names[i]);
- if (ret)
- return ret;
- }
-
- for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) {
- if (!gpio_is_valid(kirin_pcie->gpio_id_clkreq[i])) {
- dev_err(dev, "unable to get a valid %s gpio\n",
- kirin_pcie->clkreq_names[i]);
- return -ENODEV;
- }
-
- ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i],
- kirin_pcie->clkreq_names[i]);
- if (ret)
- return ret;
-
- ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
static const struct dw_pcie_ops kirin_dw_pcie_ops = {
.read_dbi = kirin_pcie_read_dbi,
.write_dbi = kirin_pcie_write_dbi,
@@ -680,7 +651,7 @@ static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie)
return hi3660_pcie_phy_power_off(kirin_pcie);
for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++)
- gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 1);
+ gpiod_direction_output_raw(kirin_pcie->id_clkreq_gpio[i], 1);
phy_power_off(kirin_pcie->phy);
phy_exit(kirin_pcie->phy);
@@ -707,10 +678,6 @@ static int kirin_pcie_power_on(struct platform_device *pdev,
if (IS_ERR(kirin_pcie->phy))
return PTR_ERR(kirin_pcie->phy);
- ret = kirin_pcie_gpio_request(kirin_pcie, dev);
- if (ret)
- return ret;
-
ret = phy_init(kirin_pcie->phy);
if (ret)
goto err;
@@ -723,11 +690,9 @@ static int kirin_pcie_power_on(struct platform_device *pdev,
/* perst assert Endpoint */
usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
- if (!gpio_request(kirin_pcie->gpio_id_dwc_perst, "pcie_perst_bridge")) {
- ret = gpio_direction_output(kirin_pcie->gpio_id_dwc_perst, 1);
- if (ret)
- goto err;
- }
+ ret = gpiod_direction_output_raw(kirin_pcie->id_dwc_perst_gpio, 1);
+ if (ret)
+ goto err;
usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
--
2.43.0.rc1.1336.g36b5255a03ac
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 16%]
* [PATCH v4 4/5] PCI: imx6: Convert to agnostic GPIO API
@ 2024-05-06 14:20 11% ` Andy Shevchenko
2024-05-07 19:22 0% ` Frank Li
2024-05-09 1:24 0% ` Hongxing Zhu
2024-05-06 14:20 16% ` [PATCH v4 5/5] PCI: kirin: " Andy Shevchenko
1 sibling, 2 replies; 200+ results
From: Andy Shevchenko @ 2024-05-06 14:20 UTC (permalink / raw)
To: Manivannan Sadhasivam, Frank Li, Krzysztof Wilczyński,
Andy Shevchenko, linux-omap, linux-pci, linux-arm-kernel,
linux-kernel, imx, linux-amlogic, linux-arm-msm, linux-tegra
Cc: Vignesh Raghavendra, Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár, Linus Walleij
The of_gpio.h is going to be removed. In preparation of that convert
the driver to the agnostic API.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 36 ++++++++-------------------
1 file changed, 10 insertions(+), 26 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 917c69edee1d..62a4994c5501 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -11,14 +11,13 @@
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_gpio.h>
#include <linux/of_address.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
@@ -107,8 +106,7 @@ struct imx6_pcie_drvdata {
struct imx6_pcie {
struct dw_pcie *pci;
- int reset_gpio;
- bool gpio_active_high;
+ struct gpio_desc *reset_gpiod;
bool link_is_up;
struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS];
struct regmap *iomuxc_gpr;
@@ -721,9 +719,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
}
/* Some boards don't have PCIe reset GPIO. */
- if (gpio_is_valid(imx6_pcie->reset_gpio))
- gpio_set_value_cansleep(imx6_pcie->reset_gpio,
- imx6_pcie->gpio_active_high);
+ gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 1);
}
static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
@@ -771,10 +767,9 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
}
/* Some boards don't have PCIe reset GPIO. */
- if (gpio_is_valid(imx6_pcie->reset_gpio)) {
+ if (imx6_pcie->reset_gpiod) {
msleep(100);
- gpio_set_value_cansleep(imx6_pcie->reset_gpio,
- !imx6_pcie->gpio_active_high);
+ gpiod_set_value_cansleep(imx6_pcie->reset_gpiod, 0);
/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
msleep(100);
}
@@ -1285,22 +1280,11 @@ static int imx6_pcie_probe(struct platform_device *pdev)
return PTR_ERR(pci->dbi_base);
/* Fetch GPIOs */
- imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
- imx6_pcie->gpio_active_high = of_property_read_bool(node,
- "reset-gpio-active-high");
- if (gpio_is_valid(imx6_pcie->reset_gpio)) {
- ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
- imx6_pcie->gpio_active_high ?
- GPIOF_OUT_INIT_HIGH :
- GPIOF_OUT_INIT_LOW,
- "PCIe reset");
- if (ret) {
- dev_err(dev, "unable to get reset gpio\n");
- return ret;
- }
- } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
- return imx6_pcie->reset_gpio;
- }
+ imx6_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(imx6_pcie->reset_gpiod))
+ return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod),
+ "unable to get reset gpio\n");
+ gpiod_set_consumer_name(imx6_pcie->reset_gpiod, "PCIe reset");
if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS)
return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
--
2.43.0.rc1.1336.g36b5255a03ac
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 11%]
* [PATCH 4/8] irqchip/stm32-exti: split MCU and MPU code
@ 2024-05-06 13:32 2% ` Antonio Borneo
0 siblings, 0 replies; 200+ results
From: Antonio Borneo @ 2024-05-06 13:32 UTC (permalink / raw)
To: Russell King, Maxime Coquelin, Alexandre Torgue, Catalin Marinas,
Will Deacon, Thomas Gleixner
Cc: Antonio Borneo, linux-arm-kernel, linux-stm32, linux-kernel
Keep in stm32-exti only the code for ARMv7m STM32 MCUs and split
out in stm32mp-exti the code for ARMv7a & ARMv8a STM32MPxxx MPUs.
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
---
drivers/irqchip/Kconfig | 3 +-
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-stm32-exti.c | 670 +-----------------
.../{irq-stm32-exti.c => irq-stm32mp-exti.c} | 345 +--------
4 files changed, 10 insertions(+), 1009 deletions(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 798bd50f8ab23..486022fb7806e 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -394,7 +394,8 @@ config PARTITION_PERCPU
config STM32MP_EXTI
bool
- select STM32_EXTI
+ select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
config STM32_EXTI
bool
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index d9dc3d99aaa86..8dffb6efbc070 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o
+obj-$(CONFIG_STM32MP_EXTI) += irq-stm32mp-exti.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 2cc9f3b7d6690..7c6a0080c3303 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -1,45 +1,22 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Maxime Coquelin 2015
- * Copyright (C) STMicroelectronics 2017
+ * Copyright (C) STMicroelectronics 2017-2024
* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
*/
#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/hwspinlock.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
-#include <linux/mod_devicetable.h>
-#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
-#include <linux/platform_device.h>
-#include <linux/pm.h>
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
#define IRQS_PER_BANK 32
-#define HWSPNLCK_TIMEOUT 1000 /* usec */
-
-#define EXTI_EnCIDCFGR(n) (0x180 + (n) * 4)
-#define EXTI_HWCFGR1 0x3f0
-
-/* Register: EXTI_EnCIDCFGR(n) */
-#define EXTI_CIDCFGR_CFEN_MASK BIT(0)
-#define EXTI_CIDCFGR_CID_MASK GENMASK(6, 4)
-#define EXTI_CIDCFGR_CID_SHIFT 4
-
-/* Register: EXTI_HWCFGR1 */
-#define EXTI_HWCFGR1_CIDWIDTH_MASK GENMASK(27, 24)
-
-#define EXTI_CID1 1
-
struct stm32_exti_bank {
u32 imr_ofst;
u32 emr_ofst;
@@ -47,13 +24,8 @@ struct stm32_exti_bank {
u32 ftsr_ofst;
u32 swier_ofst;
u32 rpr_ofst;
- u32 fpr_ofst;
- u32 trg_ofst;
- u32 seccfgr_ofst;
};
-#define UNDEF_REG ~0
-
struct stm32_exti_drv_data {
const struct stm32_exti_bank **exti_banks;
const u8 *desc_irqs;
@@ -63,7 +35,6 @@ struct stm32_exti_drv_data {
struct stm32_exti_chip_data {
struct stm32_exti_host_data *host_data;
const struct stm32_exti_bank *reg_bank;
- struct raw_spinlock rlock;
u32 wake_active;
u32 mask_cache;
u32 rtsr_cache;
@@ -76,8 +47,6 @@ struct stm32_exti_host_data {
struct device *dev;
struct stm32_exti_chip_data *chips_data;
const struct stm32_exti_drv_data *drv_data;
- struct hwspinlock *hwlock;
- bool dt_has_irqs_desc; /* skip internal desc_irqs array and get it from DT */
};
static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
@@ -87,9 +56,6 @@ static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
.ftsr_ofst = 0x0C,
.swier_ofst = 0x10,
.rpr_ofst = 0x14,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
};
static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
@@ -108,9 +74,6 @@ static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
.ftsr_ofst = 0x04,
.swier_ofst = 0x08,
.rpr_ofst = 0x88,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
};
static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
@@ -120,9 +83,6 @@ static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
.ftsr_ofst = 0x24,
.swier_ofst = 0x28,
.rpr_ofst = 0x98,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
};
static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
@@ -132,9 +92,6 @@ static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
.ftsr_ofst = 0x44,
.swier_ofst = 0x48,
.rpr_ofst = 0xA8,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
};
static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
@@ -148,183 +105,12 @@ static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
.bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
};
-static const struct stm32_exti_bank stm32mp1_exti_b1 = {
- .imr_ofst = 0x80,
- .emr_ofst = UNDEF_REG,
- .rtsr_ofst = 0x00,
- .ftsr_ofst = 0x04,
- .swier_ofst = 0x08,
- .rpr_ofst = 0x0C,
- .fpr_ofst = 0x10,
- .trg_ofst = 0x3EC,
- .seccfgr_ofst = 0x14,
-};
-
-static const struct stm32_exti_bank stm32mp1_exti_b2 = {
- .imr_ofst = 0x90,
- .emr_ofst = UNDEF_REG,
- .rtsr_ofst = 0x20,
- .ftsr_ofst = 0x24,
- .swier_ofst = 0x28,
- .rpr_ofst = 0x2C,
- .fpr_ofst = 0x30,
- .trg_ofst = 0x3E8,
- .seccfgr_ofst = 0x34,
-};
-
-static const struct stm32_exti_bank stm32mp1_exti_b3 = {
- .imr_ofst = 0xA0,
- .emr_ofst = UNDEF_REG,
- .rtsr_ofst = 0x40,
- .ftsr_ofst = 0x44,
- .swier_ofst = 0x48,
- .rpr_ofst = 0x4C,
- .fpr_ofst = 0x50,
- .trg_ofst = 0x3E4,
- .seccfgr_ofst = 0x54,
-};
-
-static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
- &stm32mp1_exti_b1,
- &stm32mp1_exti_b2,
- &stm32mp1_exti_b3,
-};
-
-static struct irq_chip stm32_exti_h_chip;
-static struct irq_chip stm32_exti_h_chip_direct;
-
-#define EXTI_INVALID_IRQ U8_MAX
-#define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER_BANK)
-
-/*
- * Use some intentionally tricky logic here to initialize the whole array to
- * EXTI_INVALID_IRQ, but then override certain fields, requiring us to indicate
- * that we "know" that there are overrides in this structure, and we'll need to
- * disable that warning from W=1 builds.
- */
-__diag_push();
-__diag_ignore_all("-Woverride-init",
- "logic to initialize all and then override some is OK");
-
-static const u8 stm32mp1_desc_irq[] = {
- /* default value */
- [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
-
- [0] = 6,
- [1] = 7,
- [2] = 8,
- [3] = 9,
- [4] = 10,
- [5] = 23,
- [6] = 64,
- [7] = 65,
- [8] = 66,
- [9] = 67,
- [10] = 40,
- [11] = 42,
- [12] = 76,
- [13] = 77,
- [14] = 121,
- [15] = 127,
- [16] = 1,
- [19] = 3,
- [21] = 31,
- [22] = 33,
- [23] = 72,
- [24] = 95,
- [25] = 107,
- [26] = 37,
- [27] = 38,
- [28] = 39,
- [29] = 71,
- [30] = 52,
- [31] = 53,
- [32] = 82,
- [33] = 83,
- [46] = 151,
- [47] = 93,
- [48] = 138,
- [50] = 139,
- [52] = 140,
- [53] = 141,
- [54] = 135,
- [61] = 100,
- [65] = 144,
- [68] = 143,
- [70] = 62,
- [73] = 129,
-};
-
-static const u8 stm32mp13_desc_irq[] = {
- /* default value */
- [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
-
- [0] = 6,
- [1] = 7,
- [2] = 8,
- [3] = 9,
- [4] = 10,
- [5] = 24,
- [6] = 65,
- [7] = 66,
- [8] = 67,
- [9] = 68,
- [10] = 41,
- [11] = 43,
- [12] = 77,
- [13] = 78,
- [14] = 106,
- [15] = 109,
- [16] = 1,
- [19] = 3,
- [21] = 32,
- [22] = 34,
- [23] = 73,
- [24] = 93,
- [25] = 114,
- [26] = 38,
- [27] = 39,
- [28] = 40,
- [29] = 72,
- [30] = 53,
- [31] = 54,
- [32] = 83,
- [33] = 84,
- [44] = 96,
- [47] = 92,
- [48] = 116,
- [50] = 117,
- [52] = 118,
- [53] = 119,
- [68] = 63,
- [70] = 98,
-};
-
-__diag_pop();
-
-static const struct stm32_exti_drv_data stm32mp1_drv_data = {
- .exti_banks = stm32mp1_exti_banks,
- .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
- .desc_irqs = stm32mp1_desc_irq,
-};
-
-static const struct stm32_exti_drv_data stm32mp13_drv_data = {
- .exti_banks = stm32mp1_exti_banks,
- .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
- .desc_irqs = stm32mp13_desc_irq,
-};
-
static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
{
struct stm32_exti_chip_data *chip_data = gc->private;
const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
- unsigned long pending;
- pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
- if (stm32_bank->fpr_ofst != UNDEF_REG)
- pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
-
- return pending;
+ return irq_reg_readl(gc, stm32_bank->rpr_ofst);
}
static void stm32_irq_handler(struct irq_desc *desc)
@@ -380,33 +166,21 @@ static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct stm32_exti_chip_data *chip_data = gc->private;
const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
- struct hwspinlock *hwlock = chip_data->host_data->hwlock;
u32 rtsr, ftsr;
int err;
irq_gc_lock(gc);
- if (hwlock) {
- err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
- if (err) {
- pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
- goto unlock;
- }
- }
-
rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
if (err)
- goto unspinlock;
+ goto unlock;
irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
-unspinlock:
- if (hwlock)
- hwspin_unlock_in_atomic(hwlock);
unlock:
irq_gc_unlock(gc);
@@ -494,287 +268,10 @@ static void stm32_irq_ack(struct irq_data *d)
irq_gc_lock(gc);
irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
- if (stm32_bank->fpr_ofst != UNDEF_REG)
- irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
irq_gc_unlock(gc);
}
-/* directly set the target bit without reading first. */
-static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- void __iomem *base = chip_data->host_data->base;
- u32 val = BIT(d->hwirq % IRQS_PER_BANK);
-
- writel_relaxed(val, base + reg);
-}
-
-static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- void __iomem *base = chip_data->host_data->base;
- u32 val;
-
- val = readl_relaxed(base + reg);
- val |= BIT(d->hwirq % IRQS_PER_BANK);
- writel_relaxed(val, base + reg);
-
- return val;
-}
-
-static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- void __iomem *base = chip_data->host_data->base;
- u32 val;
-
- val = readl_relaxed(base + reg);
- val &= ~BIT(d->hwirq % IRQS_PER_BANK);
- writel_relaxed(val, base + reg);
-
- return val;
-}
-
-static void stm32_exti_h_eoi(struct irq_data *d)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
-
- raw_spin_lock(&chip_data->rlock);
-
- stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
- if (stm32_bank->fpr_ofst != UNDEF_REG)
- stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
-
- raw_spin_unlock(&chip_data->rlock);
-
- if (d->parent_data->chip)
- irq_chip_eoi_parent(d);
-}
-
-static void stm32_exti_h_mask(struct irq_data *d)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
-
- raw_spin_lock(&chip_data->rlock);
- chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
- raw_spin_unlock(&chip_data->rlock);
-
- if (d->parent_data->chip)
- irq_chip_mask_parent(d);
-}
-
-static void stm32_exti_h_unmask(struct irq_data *d)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
-
- raw_spin_lock(&chip_data->rlock);
- chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
- raw_spin_unlock(&chip_data->rlock);
-
- if (d->parent_data->chip)
- irq_chip_unmask_parent(d);
-}
-
-static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
- struct hwspinlock *hwlock = chip_data->host_data->hwlock;
- void __iomem *base = chip_data->host_data->base;
- u32 rtsr, ftsr;
- int err;
-
- raw_spin_lock(&chip_data->rlock);
-
- if (hwlock) {
- err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
- if (err) {
- pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
- goto unlock;
- }
- }
-
- rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
- ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
-
- err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
- if (err)
- goto unspinlock;
-
- writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
- writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
-
-unspinlock:
- if (hwlock)
- hwspin_unlock_in_atomic(hwlock);
-unlock:
- raw_spin_unlock(&chip_data->rlock);
-
- return err;
-}
-
-static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
-
- raw_spin_lock(&chip_data->rlock);
-
- if (on)
- chip_data->wake_active |= mask;
- else
- chip_data->wake_active &= ~mask;
-
- raw_spin_unlock(&chip_data->rlock);
-
- return 0;
-}
-
-static int stm32_exti_h_set_affinity(struct irq_data *d,
- const struct cpumask *dest, bool force)
-{
- if (d->parent_data->chip)
- return irq_chip_set_affinity_parent(d, dest, force);
-
- return IRQ_SET_MASK_OK_DONE;
-}
-
-static int stm32_exti_h_suspend(struct device *dev)
-{
- struct stm32_exti_host_data *host_data = dev_get_drvdata(dev);
- struct stm32_exti_chip_data *chip_data;
- int i;
-
- for (i = 0; i < host_data->drv_data->bank_nr; i++) {
- chip_data = &host_data->chips_data[i];
- stm32_chip_suspend(chip_data, chip_data->wake_active);
- }
-
- return 0;
-}
-
-static int stm32_exti_h_resume(struct device *dev)
-{
- struct stm32_exti_host_data *host_data = dev_get_drvdata(dev);
- struct stm32_exti_chip_data *chip_data;
- int i;
-
- for (i = 0; i < host_data->drv_data->bank_nr; i++) {
- chip_data = &host_data->chips_data[i];
- stm32_chip_resume(chip_data, chip_data->mask_cache);
- }
-
- return 0;
-}
-
-static int stm32_exti_h_retrigger(struct irq_data *d)
-{
- struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
- void __iomem *base = chip_data->host_data->base;
- u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
-
- writel_relaxed(mask, base + stm32_bank->swier_ofst);
-
- return 0;
-}
-
-static struct irq_chip stm32_exti_h_chip = {
- .name = "stm32-exti-h",
- .irq_eoi = stm32_exti_h_eoi,
- .irq_mask = stm32_exti_h_mask,
- .irq_unmask = stm32_exti_h_unmask,
- .irq_retrigger = stm32_exti_h_retrigger,
- .irq_set_type = stm32_exti_h_set_type,
- .irq_set_wake = stm32_exti_h_set_wake,
- .flags = IRQCHIP_MASK_ON_SUSPEND,
- .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
-};
-
-static struct irq_chip stm32_exti_h_chip_direct = {
- .name = "stm32-exti-h-direct",
- .irq_eoi = irq_chip_eoi_parent,
- .irq_ack = irq_chip_ack_parent,
- .irq_mask = stm32_exti_h_mask,
- .irq_unmask = stm32_exti_h_unmask,
- .irq_retrigger = irq_chip_retrigger_hierarchy,
- .irq_set_type = irq_chip_set_type_parent,
- .irq_set_wake = stm32_exti_h_set_wake,
- .flags = IRQCHIP_MASK_ON_SUSPEND,
- .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
-};
-
-static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
- unsigned int virq,
- unsigned int nr_irqs, void *data)
-{
- struct stm32_exti_host_data *host_data = dm->host_data;
- struct stm32_exti_chip_data *chip_data;
- u8 desc_irq;
- struct irq_fwspec *fwspec = data;
- struct irq_fwspec p_fwspec;
- irq_hw_number_t hwirq;
- int bank;
- u32 event_trg;
- struct irq_chip *chip;
-
- hwirq = fwspec->param[0];
- if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK)
- return -EINVAL;
-
- bank = hwirq / IRQS_PER_BANK;
- chip_data = &host_data->chips_data[bank];
-
- /* Check if event is reserved (Secure) */
- if (chip_data->event_reserved & BIT(hwirq % IRQS_PER_BANK)) {
- dev_err(host_data->dev, "event %lu is reserved, secure\n", hwirq);
- return -EPERM;
- }
-
- event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst);
- chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ?
- &stm32_exti_h_chip : &stm32_exti_h_chip_direct;
-
- irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
-
- if (host_data->dt_has_irqs_desc) {
- struct of_phandle_args out_irq;
- int ret;
-
- ret = of_irq_parse_one(host_data->dev->of_node, hwirq, &out_irq);
- if (ret)
- return ret;
- /* we only support one parent, so far */
- if (of_node_to_fwnode(out_irq.np) != dm->parent->fwnode)
- return -EINVAL;
-
- of_phandle_args_to_fwspec(out_irq.np, out_irq.args,
- out_irq.args_count, &p_fwspec);
-
- return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
- }
-
- if (!host_data->drv_data->desc_irqs)
- return -EINVAL;
-
- desc_irq = host_data->drv_data->desc_irqs[hwirq];
- if (desc_irq != EXTI_INVALID_IRQ) {
- p_fwspec.fwnode = dm->parent->fwnode;
- p_fwspec.param_count = 3;
- p_fwspec.param[0] = GIC_SPI;
- p_fwspec.param[1] = desc_irq;
- p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
-
- return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
- }
-
- return 0;
-}
-
static struct
stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
struct device_node *node)
@@ -822,19 +319,12 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
chip_data->host_data = h_data;
chip_data->reg_bank = stm32_bank;
- raw_spin_lock_init(&chip_data->rlock);
-
/*
* This IP has no reset, so after hot reboot we should
* clear registers to avoid residue
*/
writel_relaxed(0, base + stm32_bank->imr_ofst);
- if (stm32_bank->emr_ofst != UNDEF_REG)
- writel_relaxed(0, base + stm32_bank->emr_ofst);
-
- /* reserve Secure events */
- if (stm32_bank->seccfgr_ofst != UNDEF_REG)
- chip_data->event_reserved = readl_relaxed(base + stm32_bank->seccfgr_ofst);
+ writel_relaxed(0, base + stm32_bank->emr_ofst);
pr_info("%pOF: bank%d\n", node, bank_idx);
@@ -914,158 +404,6 @@ static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
return ret;
}
-static const struct irq_domain_ops stm32_exti_h_domain_ops = {
- .alloc = stm32_exti_h_domain_alloc,
- .free = irq_domain_free_irqs_common,
- .xlate = irq_domain_xlate_twocell,
-};
-
-static void stm32_exti_check_rif(struct stm32_exti_host_data *host_data)
-{
- unsigned int bank, i, event;
- u32 cid, cidcfgr, hwcfgr1;
-
- /* quit on CID not supported */
- hwcfgr1 = readl_relaxed(host_data->base + EXTI_HWCFGR1);
- if ((hwcfgr1 & EXTI_HWCFGR1_CIDWIDTH_MASK) == 0)
- return;
-
- for (bank = 0; bank < host_data->drv_data->bank_nr; bank++) {
- for (i = 0; i < IRQS_PER_BANK; i++) {
- event = bank * IRQS_PER_BANK + i;
- cidcfgr = readl_relaxed(host_data->base + EXTI_EnCIDCFGR(event));
- cid = (cidcfgr & EXTI_CIDCFGR_CID_MASK) >> EXTI_CIDCFGR_CID_SHIFT;
- if ((cidcfgr & EXTI_CIDCFGR_CFEN_MASK) && cid != EXTI_CID1)
- host_data->chips_data[bank].event_reserved |= BIT(i);
- }
- }
-}
-
-static void stm32_exti_remove_irq(void *data)
-{
- struct irq_domain *domain = data;
-
- irq_domain_remove(domain);
-}
-
-static int stm32_exti_probe(struct platform_device *pdev)
-{
- int ret, i;
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- struct irq_domain *parent_domain, *domain;
- struct stm32_exti_host_data *host_data;
- const struct stm32_exti_drv_data *drv_data;
-
- host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
- if (!host_data)
- return -ENOMEM;
-
- dev_set_drvdata(dev, host_data);
- host_data->dev = dev;
-
- /* check for optional hwspinlock which may be not available yet */
- ret = of_hwspin_lock_get_id(np, 0);
- if (ret == -EPROBE_DEFER)
- /* hwspinlock framework not yet ready */
- return ret;
-
- if (ret >= 0) {
- host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
- if (!host_data->hwlock) {
- dev_err(dev, "Failed to request hwspinlock\n");
- return -EINVAL;
- }
- } else if (ret != -ENOENT) {
- /* note: ENOENT is a valid case (means 'no hwspinlock') */
- dev_err(dev, "Failed to get hwspinlock\n");
- return ret;
- }
-
- /* initialize host_data */
- drv_data = of_device_get_match_data(dev);
- if (!drv_data) {
- dev_err(dev, "no of match data\n");
- return -ENODEV;
- }
- host_data->drv_data = drv_data;
-
- host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
- sizeof(*host_data->chips_data),
- GFP_KERNEL);
- if (!host_data->chips_data)
- return -ENOMEM;
-
- host_data->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(host_data->base))
- return PTR_ERR(host_data->base);
-
- for (i = 0; i < drv_data->bank_nr; i++)
- stm32_exti_chip_init(host_data, i, np);
-
- stm32_exti_check_rif(host_data);
-
- parent_domain = irq_find_host(of_irq_find_parent(np));
- if (!parent_domain) {
- dev_err(dev, "GIC interrupt-parent not found\n");
- return -EINVAL;
- }
-
- domain = irq_domain_add_hierarchy(parent_domain, 0,
- drv_data->bank_nr * IRQS_PER_BANK,
- np, &stm32_exti_h_domain_ops,
- host_data);
-
- if (!domain) {
- dev_err(dev, "Could not register exti domain\n");
- return -ENOMEM;
- }
-
- ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
- if (ret)
- return ret;
-
- if (of_property_read_bool(np, "interrupts-extended"))
- host_data->dt_has_irqs_desc = true;
-
- return 0;
-}
-
-/* platform driver only for MP1 */
-static const struct of_device_id stm32_exti_ids[] = {
- { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
- { .compatible = "st,stm32mp13-exti", .data = &stm32mp13_drv_data},
- {},
-};
-MODULE_DEVICE_TABLE(of, stm32_exti_ids);
-
-static const struct dev_pm_ops stm32_exti_dev_pm_ops = {
- NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_exti_h_suspend, stm32_exti_h_resume)
-};
-
-static struct platform_driver stm32_exti_driver = {
- .probe = stm32_exti_probe,
- .driver = {
- .name = "stm32_exti",
- .of_match_table = stm32_exti_ids,
- .pm = &stm32_exti_dev_pm_ops,
- },
-};
-
-static int __init stm32_exti_arch_init(void)
-{
- return platform_driver_register(&stm32_exti_driver);
-}
-
-static void __exit stm32_exti_arch_exit(void)
-{
- return platform_driver_unregister(&stm32_exti_driver);
-}
-
-arch_initcall(stm32_exti_arch_init);
-module_exit(stm32_exti_arch_exit);
-
-/* no platform driver for F4 and H7 */
static int __init stm32f4_exti_of_init(struct device_node *np,
struct device_node *parent)
{
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32mp-exti.c
similarity index 67%
copy from drivers/irqchip/irq-stm32-exti.c
copy to drivers/irqchip/irq-stm32mp-exti.c
index 2cc9f3b7d6690..8a45ece2e198f 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32mp-exti.c
@@ -1,18 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Maxime Coquelin 2015
- * Copyright (C) STMicroelectronics 2017
+ * Copyright (C) STMicroelectronics 2017-2024
* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
*/
#include <linux/bitops.h>
-#include <linux/delay.h>
#include <linux/hwspinlock.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
-#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
@@ -42,7 +40,6 @@
struct stm32_exti_bank {
u32 imr_ofst;
- u32 emr_ofst;
u32 rtsr_ofst;
u32 ftsr_ofst;
u32 swier_ofst;
@@ -52,8 +49,6 @@ struct stm32_exti_bank {
u32 seccfgr_ofst;
};
-#define UNDEF_REG ~0
-
struct stm32_exti_drv_data {
const struct stm32_exti_bank **exti_banks;
const u8 *desc_irqs;
@@ -80,77 +75,8 @@ struct stm32_exti_host_data {
bool dt_has_irqs_desc; /* skip internal desc_irqs array and get it from DT */
};
-static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
- .imr_ofst = 0x00,
- .emr_ofst = 0x04,
- .rtsr_ofst = 0x08,
- .ftsr_ofst = 0x0C,
- .swier_ofst = 0x10,
- .rpr_ofst = 0x14,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
-};
-
-static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
- &stm32f4xx_exti_b1,
-};
-
-static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
- .exti_banks = stm32f4xx_exti_banks,
- .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
-};
-
-static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
- .imr_ofst = 0x80,
- .emr_ofst = 0x84,
- .rtsr_ofst = 0x00,
- .ftsr_ofst = 0x04,
- .swier_ofst = 0x08,
- .rpr_ofst = 0x88,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
-};
-
-static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
- .imr_ofst = 0x90,
- .emr_ofst = 0x94,
- .rtsr_ofst = 0x20,
- .ftsr_ofst = 0x24,
- .swier_ofst = 0x28,
- .rpr_ofst = 0x98,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
-};
-
-static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
- .imr_ofst = 0xA0,
- .emr_ofst = 0xA4,
- .rtsr_ofst = 0x40,
- .ftsr_ofst = 0x44,
- .swier_ofst = 0x48,
- .rpr_ofst = 0xA8,
- .fpr_ofst = UNDEF_REG,
- .trg_ofst = UNDEF_REG,
- .seccfgr_ofst = UNDEF_REG,
-};
-
-static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
- &stm32h7xx_exti_b1,
- &stm32h7xx_exti_b2,
- &stm32h7xx_exti_b3,
-};
-
-static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
- .exti_banks = stm32h7xx_exti_banks,
- .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
-};
-
static const struct stm32_exti_bank stm32mp1_exti_b1 = {
.imr_ofst = 0x80,
- .emr_ofst = UNDEF_REG,
.rtsr_ofst = 0x00,
.ftsr_ofst = 0x04,
.swier_ofst = 0x08,
@@ -162,7 +88,6 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 = {
static const struct stm32_exti_bank stm32mp1_exti_b2 = {
.imr_ofst = 0x90,
- .emr_ofst = UNDEF_REG,
.rtsr_ofst = 0x20,
.ftsr_ofst = 0x24,
.swier_ofst = 0x28,
@@ -174,7 +99,6 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 = {
static const struct stm32_exti_bank stm32mp1_exti_b3 = {
.imr_ofst = 0xA0,
- .emr_ofst = UNDEF_REG,
.rtsr_ofst = 0x40,
.ftsr_ofst = 0x44,
.swier_ofst = 0x48,
@@ -314,42 +238,6 @@ static const struct stm32_exti_drv_data stm32mp13_drv_data = {
.desc_irqs = stm32mp13_desc_irq,
};
-static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
-{
- struct stm32_exti_chip_data *chip_data = gc->private;
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
- unsigned long pending;
-
- pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
- if (stm32_bank->fpr_ofst != UNDEF_REG)
- pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
-
- return pending;
-}
-
-static void stm32_irq_handler(struct irq_desc *desc)
-{
- struct irq_domain *domain = irq_desc_get_handler_data(desc);
- struct irq_chip *chip = irq_desc_get_chip(desc);
- unsigned int nbanks = domain->gc->num_chips;
- struct irq_chip_generic *gc;
- unsigned long pending;
- int n, i, irq_base = 0;
-
- chained_irq_enter(chip, desc);
-
- for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
- gc = irq_get_domain_generic_chip(domain, irq_base);
-
- while ((pending = stm32_exti_pending(gc))) {
- for_each_set_bit(n, &pending, IRQS_PER_BANK)
- generic_handle_domain_irq(domain, irq_base + n);
- }
- }
-
- chained_irq_exit(chip, desc);
-}
-
static int stm32_exti_set_type(struct irq_data *d,
unsigned int type, u32 *rtsr, u32 *ftsr)
{
@@ -375,44 +263,6 @@ static int stm32_exti_set_type(struct irq_data *d,
return 0;
}
-static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
-{
- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- struct stm32_exti_chip_data *chip_data = gc->private;
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
- struct hwspinlock *hwlock = chip_data->host_data->hwlock;
- u32 rtsr, ftsr;
- int err;
-
- irq_gc_lock(gc);
-
- if (hwlock) {
- err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
- if (err) {
- pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
- goto unlock;
- }
- }
-
- rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
- ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
-
- err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
- if (err)
- goto unspinlock;
-
- irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
- irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
-
-unspinlock:
- if (hwlock)
- hwspin_unlock_in_atomic(hwlock);
-unlock:
- irq_gc_unlock(gc);
-
- return err;
-}
-
static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
u32 wake_active)
{
@@ -439,67 +289,6 @@ static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
}
-static void stm32_irq_suspend(struct irq_chip_generic *gc)
-{
- struct stm32_exti_chip_data *chip_data = gc->private;
-
- irq_gc_lock(gc);
- stm32_chip_suspend(chip_data, gc->wake_active);
- irq_gc_unlock(gc);
-}
-
-static void stm32_irq_resume(struct irq_chip_generic *gc)
-{
- struct stm32_exti_chip_data *chip_data = gc->private;
-
- irq_gc_lock(gc);
- stm32_chip_resume(chip_data, gc->mask_cache);
- irq_gc_unlock(gc);
-}
-
-static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
- unsigned int nr_irqs, void *data)
-{
- struct irq_fwspec *fwspec = data;
- irq_hw_number_t hwirq;
-
- hwirq = fwspec->param[0];
-
- irq_map_generic_chip(d, virq, hwirq);
-
- return 0;
-}
-
-static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
- unsigned int nr_irqs)
-{
- struct irq_data *data = irq_domain_get_irq_data(d, virq);
-
- irq_domain_reset_irq_data(data);
-}
-
-static const struct irq_domain_ops irq_exti_domain_ops = {
- .map = irq_map_generic_chip,
- .alloc = stm32_exti_alloc,
- .free = stm32_exti_free,
- .xlate = irq_domain_xlate_twocell,
-};
-
-static void stm32_irq_ack(struct irq_data *d)
-{
- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- struct stm32_exti_chip_data *chip_data = gc->private;
- const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
-
- irq_gc_lock(gc);
-
- irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
- if (stm32_bank->fpr_ofst != UNDEF_REG)
- irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
-
- irq_gc_unlock(gc);
-}
-
/* directly set the target bit without reading first. */
static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
{
@@ -544,8 +333,7 @@ static void stm32_exti_h_eoi(struct irq_data *d)
raw_spin_lock(&chip_data->rlock);
stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
- if (stm32_bank->fpr_ofst != UNDEF_REG)
- stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
+ stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
raw_spin_unlock(&chip_data->rlock);
@@ -775,39 +563,6 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
return 0;
}
-static struct
-stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
- struct device_node *node)
-{
- struct stm32_exti_host_data *host_data;
-
- host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
- if (!host_data)
- return NULL;
-
- host_data->drv_data = dd;
- host_data->chips_data = kcalloc(dd->bank_nr,
- sizeof(struct stm32_exti_chip_data),
- GFP_KERNEL);
- if (!host_data->chips_data)
- goto free_host_data;
-
- host_data->base = of_iomap(node, 0);
- if (!host_data->base) {
- pr_err("%pOF: Unable to map registers\n", node);
- goto free_chips_data;
- }
-
- return host_data;
-
-free_chips_data:
- kfree(host_data->chips_data);
-free_host_data:
- kfree(host_data);
-
- return NULL;
-}
-
static struct
stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
u32 bank_idx,
@@ -829,91 +584,15 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
* clear registers to avoid residue
*/
writel_relaxed(0, base + stm32_bank->imr_ofst);
- if (stm32_bank->emr_ofst != UNDEF_REG)
- writel_relaxed(0, base + stm32_bank->emr_ofst);
/* reserve Secure events */
- if (stm32_bank->seccfgr_ofst != UNDEF_REG)
- chip_data->event_reserved = readl_relaxed(base + stm32_bank->seccfgr_ofst);
+ chip_data->event_reserved = readl_relaxed(base + stm32_bank->seccfgr_ofst);
pr_info("%pOF: bank%d\n", node, bank_idx);
return chip_data;
}
-static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
- struct device_node *node)
-{
- struct stm32_exti_host_data *host_data;
- unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
- int nr_irqs, ret, i;
- struct irq_chip_generic *gc;
- struct irq_domain *domain;
-
- host_data = stm32_exti_host_init(drv_data, node);
- if (!host_data)
- return -ENOMEM;
-
- domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
- &irq_exti_domain_ops, NULL);
- if (!domain) {
- pr_err("%pOFn: Could not register interrupt domain.\n",
- node);
- ret = -ENOMEM;
- goto out_unmap;
- }
-
- ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
- handle_edge_irq, clr, 0, 0);
- if (ret) {
- pr_err("%pOF: Could not allocate generic interrupt chip.\n",
- node);
- goto out_free_domain;
- }
-
- for (i = 0; i < drv_data->bank_nr; i++) {
- const struct stm32_exti_bank *stm32_bank;
- struct stm32_exti_chip_data *chip_data;
-
- stm32_bank = drv_data->exti_banks[i];
- chip_data = stm32_exti_chip_init(host_data, i, node);
-
- gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
-
- gc->reg_base = host_data->base;
- gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
- gc->chip_types->chip.irq_ack = stm32_irq_ack;
- gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
- gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
- gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
- gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
- gc->suspend = stm32_irq_suspend;
- gc->resume = stm32_irq_resume;
- gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
-
- gc->chip_types->regs.mask = stm32_bank->imr_ofst;
- gc->private = (void *)chip_data;
- }
-
- nr_irqs = of_irq_count(node);
- for (i = 0; i < nr_irqs; i++) {
- unsigned int irq = irq_of_parse_and_map(node, i);
-
- irq_set_handler_data(irq, domain);
- irq_set_chained_handler(irq, stm32_irq_handler);
- }
-
- return 0;
-
-out_free_domain:
- irq_domain_remove(domain);
-out_unmap:
- iounmap(host_data->base);
- kfree(host_data->chips_data);
- kfree(host_data);
- return ret;
-}
-
static const struct irq_domain_ops stm32_exti_h_domain_ops = {
.alloc = stm32_exti_h_domain_alloc,
.free = irq_domain_free_irqs_common,
@@ -1031,7 +710,6 @@ static int stm32_exti_probe(struct platform_device *pdev)
return 0;
}
-/* platform driver only for MP1 */
static const struct of_device_id stm32_exti_ids[] = {
{ .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
{ .compatible = "st,stm32mp13-exti", .data = &stm32mp13_drv_data},
@@ -1064,20 +742,3 @@ static void __exit stm32_exti_arch_exit(void)
arch_initcall(stm32_exti_arch_init);
module_exit(stm32_exti_arch_exit);
-
-/* no platform driver for F4 and H7 */
-static int __init stm32f4_exti_of_init(struct device_node *np,
- struct device_node *parent)
-{
- return stm32_exti_init(&stm32f4xx_drv_data, np);
-}
-
-IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
-
-static int __init stm32h7_exti_of_init(struct device_node *np,
- struct device_node *parent)
-{
- return stm32_exti_init(&stm32h7xx_drv_data, np);
-}
-
-IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
--
2.34.1
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^ permalink raw reply related [relevance 2%]
* [PATCH 2/2] phy: rockchip: Add Samsung CSI/DSI Combo DCPHY driver
@ 2024-05-06 12:48 1% ` Heiko Stuebner
0 siblings, 0 replies; 200+ results
From: Heiko Stuebner @ 2024-05-06 12:48 UTC (permalink / raw)
To: vkoul, kishon, robh, krzk+dt, conor+dt
Cc: quentin.schulz, heiko, linux-phy, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel
Add phy driver needed to drive either a MIPI DSI output to a DSI display
or MIPI CSI input from a camera on rk3588.
Right now only the DSI portion is implemented as the whole camera part
needs more work in general.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/phy/rockchip/Kconfig | 12 +
drivers/phy/rockchip/Makefile | 1 +
.../phy/rockchip/phy-rockchip-samsung-dcphy.c | 1609 +++++++++++++++++
3 files changed, 1622 insertions(+)
create mode 100644 drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 08b0f43457606..f7dac676f2061 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -83,6 +83,18 @@ config PHY_ROCKCHIP_PCIE
help
Enable this to support the Rockchip PCIe PHY.
+config PHY_ROCKCHIP_SAMSUNG_DCPHY
+ tristate "Rockchip Samsung MIPI DCPHY driver"
+ depends on (ARCH_ROCKCHIP || COMPILE_TEST)
+ select GENERIC_PHY
+ select GENERIC_PHY_MIPI_DPHY
+ help
+ Enable this to support the Rockchip MIPI DCPHY with
+ Samsung IP block.
+
+ To compile this driver as a module, choose M here: the module
+ will be called phy-rockchip-samsung-dcphy
+
config PHY_ROCKCHIP_SAMSUNG_HDPTX
tristate "Rockchip Samsung HDMI/eDP Combo PHY driver"
depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 010a824e32ce0..117aaffd037d8 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
+obj-$(CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY) += phy-rockchip-samsung-dcphy.o
obj-$(CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX) += phy-rockchip-samsung-hdptx.o
obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
new file mode 100644
index 0000000000000..b897ecc5e1917
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
@@ -0,0 +1,1609 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Rockchip Electronics Co.Ltd
+ * Author:
+ * Guochun Huang <hero.huang@rock-chips.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
+#define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16))
+
+#define BIAS_CON0 0x0000
+#define BIAS_CON1 0x0004
+#define BIAS_CON2 0x0008
+#define BIAS_CON4 0x0010
+#define I_MUX_SEL_MASK GENMASK(6, 5)
+#define I_MUX_SEL(x) UPDATE(x, 6, 5)
+#define I_MUX_SEL_400MV I_MUX_SEL(0)
+#define I_MUX_SEL_200MV I_MUX_SEL(1)
+#define I_MUX_SEL_530MV I_MUX_SEL(2)
+
+#define PLL_CON0 0x0100
+#define PLL_EN BIT(12)
+#define S_MASK GENMASK(10, 8)
+#define S(x) UPDATE(x, 10, 8)
+#define P_MASK GENMASK(5, 0)
+#define P(x) UPDATE(x, 5, 0)
+#define PLL_CON1 0x0104
+#define PLL_CON2 0x0108
+#define M_MASK GENMASK(9, 0)
+#define M(x) UPDATE(x, 9, 0)
+#define PLL_CON3 0x010c
+#define MRR_MASK GENMASK(13, 8)
+#define MRR(x) UPDATE(x, 13, 8)
+#define MFR_MASK GENMASK(7, 0)
+#define MFR(x) UPDATE(x, 7, 0)
+#define PLL_CON4 0x0110
+#define SSCG_EN BIT(11)
+#define PLL_CON5 0x0114
+#define RESET_N_SEL BIT(10)
+#define PLL_ENABLE_SEL BIT(8)
+#define PLL_CON6 0x0118
+#define PLL_CON7 0x011c
+#define PLL_LOCK_CNT(x) UPDATE(x, 15, 0)
+#define PLL_CON8 0x0120
+#define PLL_STB_CNT(x) UPDATE(x, 15, 0)
+#define PLL_STAT0 0x0140
+#define PLL_LOCK BIT(0)
+
+#define DPHY_MC_GNR_CON0 0x0300
+#define PHY_READY BIT(1)
+#define PHY_ENABLE BIT(0)
+#define DPHY_MC_GNR_CON1 0x0304
+#define T_PHY_READY(x) UPDATE(x, 15, 0)
+#define DPHY_MC_ANA_CON0 0x0308
+#define DPHY_MC_ANA_CON1 0x030c
+#define DPHY_MC_ANA_CON2 0x0310
+#define HS_VREG_AMP_ICON(x) UPDATE(x, 1, 0)
+#define DPHY_MC_TIME_CON0 0x0330
+#define HSTX_CLK_SEL BIT(12)
+#define T_LPX(x) UPDATE(x, 11, 4)
+#define DPHY_MC_TIME_CON1 0x0334
+#define T_CLK_ZERO(x) UPDATE(x, 15, 8)
+#define T_CLK_PREPARE(x) UPDATE(x, 7, 0)
+#define DPHY_MC_TIME_CON2 0x0338
+#define T_HS_EXIT(x) UPDATE(x, 15, 8)
+#define T_CLK_TRAIL(x) UPDATE(x, 7, 0)
+#define DPHY_MC_TIME_CON3 0x033c
+#define T_CLK_POST(x) UPDATE(x, 7, 0)
+#define DPHY_MC_TIME_CON4 0x0340
+#define T_ULPS_EXIT(x) UPDATE(x, 9, 0)
+#define DPHY_MC_DESKEW_CON0 0x0350
+#define SKEW_CAL_RUN_TIME(x) UPDATE(x, 15, 12)
+
+#define SKEW_CAL_INIT_RUN_TIME(x) UPDATE(x, 11, 8)
+#define SKEW_CAL_INIT_WAIT_TIME(x) UPDATE(x, 7, 4)
+#define SKEW_CAL_EN BIT(0)
+
+#define COMBO_MD0_GNR_CON0 0x0400
+#define COMBO_MD0_GNR_CON1 0x0404
+#define COMBO_MD0_ANA_CON0 0x0408
+#define COMBO_MD0_ANA_CON1 0x040C
+#define COMBO_MD0_ANA_CON2 0x0410
+
+#define COMBO_MD0_TIME_CON0 0x0430
+#define COMBO_MD0_TIME_CON1 0x0434
+#define COMBO_MD0_TIME_CON2 0x0438
+#define COMBO_MD0_TIME_CON3 0x043C
+#define COMBO_MD0_TIME_CON4 0x0440
+#define COMBO_MD0_DATA_CON0 0x0444
+
+#define COMBO_MD1_GNR_CON0 0x0500
+#define COMBO_MD1_GNR_CON1 0x0504
+#define COMBO_MD1_ANA_CON0 0x0508
+#define COMBO_MD1_ANA_CON1 0x050c
+#define COMBO_MD1_ANA_CON2 0x0510
+#define COMBO_MD1_TIME_CON0 0x0530
+#define COMBO_MD1_TIME_CON1 0x0534
+#define COMBO_MD1_TIME_CON2 0x0538
+#define COMBO_MD1_TIME_CON3 0x053C
+#define COMBO_MD1_TIME_CON4 0x0540
+#define COMBO_MD1_DATA_CON0 0x0544
+
+#define COMBO_MD2_GNR_CON0 0x0600
+#define COMBO_MD2_GNR_CON1 0x0604
+#define COMBO_MD2_ANA_CON0 0X0608
+#define COMBO_MD2_ANA_CON1 0X060C
+#define COMBO_MD2_ANA_CON2 0X0610
+#define COMBO_MD2_TIME_CON0 0x0630
+#define COMBO_MD2_TIME_CON1 0x0634
+#define COMBO_MD2_TIME_CON2 0x0638
+#define COMBO_MD2_TIME_CON3 0x063C
+#define COMBO_MD2_TIME_CON4 0x0640
+#define COMBO_MD2_DATA_CON0 0x0644
+
+#define DPHY_MD3_GNR_CON0 0x0700
+#define DPHY_MD3_GNR_CON1 0x0704
+#define DPHY_MD3_ANA_CON0 0X0708
+#define DPHY_MD3_ANA_CON1 0X070C
+#define DPHY_MD3_ANA_CON2 0X0710
+#define DPHY_MD3_TIME_CON0 0x0730
+#define DPHY_MD3_TIME_CON1 0x0734
+#define DPHY_MD3_TIME_CON2 0x0738
+#define DPHY_MD3_TIME_CON3 0x073C
+#define DPHY_MD3_TIME_CON4 0x0740
+#define DPHY_MD3_DATA_CON0 0x0744
+
+#define T_LP_EXIT_SKEW(x) UPDATE(x, 3, 2)
+#define T_LP_ENTRY_SKEW(x) UPDATE(x, 1, 0)
+#define T_HS_ZERO(x) UPDATE(x, 15, 8)
+#define T_HS_PREPARE(x) UPDATE(x, 7, 0)
+#define T_HS_EXIT(x) UPDATE(x, 15, 8)
+#define T_HS_TRAIL(x) UPDATE(x, 7, 0)
+#define T_TA_GET(x) UPDATE(x, 7, 4)
+#define T_TA_GO(x) UPDATE(x, 3, 0)
+
+/* MIPICDPHY_GRF registers */
+#define MIPICDPHY_GRF_CON0 0x0000
+#define S_CPHY_MODE HIWORD_UPDATE(1, 3, 3)
+#define M_CPHY_MODE HIWORD_UPDATE(1, 0, 0)
+
+#define MAX_DPHY_BW 4500000L
+#define MAX_CPHY_BW 2000000L
+
+#define RX_CLK_THS_SETTLE (0xb30)
+#define RX_LANE0_THS_SETTLE (0xC30)
+#define RX_LANE0_ERR_SOT_SYNC (0xC34)
+#define RX_LANE1_THS_SETTLE (0xD30)
+#define RX_LANE1_ERR_SOT_SYNC (0xD34)
+#define RX_LANE2_THS_SETTLE (0xE30)
+#define RX_LANE2_ERR_SOT_SYNC (0xE34)
+#define RX_LANE3_THS_SETTLE (0xF30)
+#define RX_LANE3_ERR_SOT_SYNC (0xF34)
+#define RX_CLK_LANE_ENABLE (0xB00)
+#define RX_DATA_LANE0_ENABLE (0xC00)
+#define RX_DATA_LANE1_ENABLE (0xD00)
+#define RX_DATA_LANE2_ENABLE (0xE00)
+#define RX_DATA_LANE3_ENABLE (0xF00)
+
+#define RX_S0C_GNR_CON1 (0xB04)
+#define RX_S0C_ANA_CON1 (0xB0c)
+#define RX_S0C_ANA_CON2 (0xB10)
+#define RX_S0C_ANA_CON3 (0xB14)
+#define RX_COMBO_S0D0_GNR_CON1 (0xC04)
+#define RX_COMBO_S0D0_ANA_CON1 (0xC0c)
+#define RX_COMBO_S0D0_ANA_CON2 (0xC10)
+#define RX_COMBO_S0D0_ANA_CON3 (0xC14)
+#define RX_COMBO_S0D0_ANA_CON6 (0xC20)
+#define RX_COMBO_S0D0_ANA_CON7 (0xC24)
+#define RX_COMBO_S0D0_DESKEW_CON0 (0xC40)
+#define RX_COMBO_S0D0_DESKEW_CON2 (0xC48)
+#define RX_COMBO_S0D0_DESKEW_CON4 (0xC50)
+#define RX_COMBO_S0D0_CRC_CON1 (0xC64)
+#define RX_COMBO_S0D0_CRC_CON2 (0xC68)
+#define RX_COMBO_S0D1_GNR_CON1 (0xD04)
+#define RX_COMBO_S0D1_ANA_CON1 (0xD0c)
+#define RX_COMBO_S0D1_ANA_CON2 (0xD10)
+#define RX_COMBO_S0D1_ANA_CON3 (0xD14)
+#define RX_COMBO_S0D1_ANA_CON6 (0xD20)
+#define RX_COMBO_S0D1_ANA_CON7 (0xD24)
+#define RX_COMBO_S0D1_DESKEW_CON0 (0xD40)
+#define RX_COMBO_S0D1_DESKEW_CON2 (0xD48)
+#define RX_COMBO_S0D1_DESKEW_CON4 (0xD50)
+#define RX_COMBO_S0D1_CRC_CON1 (0xD64)
+#define RX_COMBO_S0D1_CRC_CON2 (0xD68)
+#define RX_COMBO_S0D2_GNR_CON1 (0xE04)
+#define RX_COMBO_S0D2_ANA_CON1 (0xE0c)
+#define RX_COMBO_S0D2_ANA_CON2 (0xE10)
+#define RX_COMBO_S0D2_ANA_CON3 (0xE14)
+#define RX_COMBO_S0D2_ANA_CON6 (0xE20)
+#define RX_COMBO_S0D2_ANA_CON7 (0xE24)
+#define RX_COMBO_S0D2_DESKEW_CON0 (0xE40)
+#define RX_COMBO_S0D2_DESKEW_CON2 (0xE48)
+#define RX_COMBO_S0D2_DESKEW_CON4 (0xE50)
+#define RX_COMBO_S0D2_CRC_CON1 (0xE64)
+#define RX_COMBO_S0D2_CRC_CON2 (0xE68)
+#define RX_S0D3_GNR_CON1 (0xF04)
+#define RX_S0D3_ANA_CON1 (0xF0c)
+#define RX_S0D3_ANA_CON2 (0xF10)
+#define RX_S0D3_ANA_CON3 (0xF14)
+#define RX_S0D3_DESKEW_CON0 (0xF40)
+#define RX_S0D3_DESKEW_CON2 (0xF48)
+#define RX_S0D3_DESKEW_CON4 (0xF50)
+
+struct samsung_mipi_dcphy {
+ struct device *dev;
+ struct clk *ref_clk;
+ struct clk *pclk;
+ struct regmap *regmap;
+ struct regmap *grf_regmap;
+ struct reset_control *m_phy_rst;
+ struct reset_control *s_phy_rst;
+ struct reset_control *apb_rst;
+ struct reset_control *grf_apb_rst;
+ unsigned int lanes;
+
+ struct {
+ unsigned long long rate;
+ u8 prediv;
+ u16 fbdiv;
+ long dsm;
+ u8 scaler;
+
+ bool ssc_en;
+ u8 mfr;
+ u8 mrr;
+ } pll;
+};
+
+struct samsung_mipi_dphy_timing {
+ unsigned int max_lane_mbps;
+ u8 clk_prepare;
+ u8 clk_zero;
+ u8 clk_post;
+ u8 clk_trail_eot;
+ u8 hs_prepare;
+ u8 hs_zero;
+ u8 hs_trail_eot;
+ u8 lpx;
+ u8 hs_exit;
+ u8 hs_settle;
+};
+
+static const
+struct samsung_mipi_dphy_timing samsung_mipi_dphy_timing_table[] = {
+ {6500, 32, 117, 31, 28, 30, 56, 27, 24, 44, 37},
+ {6490, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37},
+ {6480, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37},
+ {6470, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37},
+ {6460, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37},
+ {6450, 32, 115, 31, 28, 30, 56, 27, 24, 44, 37},
+ {6440, 32, 115, 31, 28, 30, 56, 27, 24, 44, 37},
+ {6430, 31, 116, 31, 28, 30, 55, 27, 24, 44, 37},
+ {6420, 31, 116, 31, 28, 30, 55, 27, 24, 44, 37},
+ {6410, 31, 116, 31, 27, 30, 55, 27, 24, 44, 37},
+ {6400, 31, 115, 30, 27, 30, 55, 27, 23, 43, 36},
+ {6390, 31, 115, 30, 27, 30, 55, 27, 23, 43, 36},
+ {6380, 31, 115, 30, 27, 30, 55, 27, 23, 43, 36},
+ {6370, 31, 115, 30, 27, 30, 55, 26, 23, 43, 36},
+ {6360, 31, 114, 30, 27, 30, 54, 26, 23, 43, 36},
+ {6350, 31, 114, 30, 27, 30, 54, 26, 23, 43, 36},
+ {6340, 31, 114, 30, 27, 30, 54, 26, 23, 43, 36},
+ {6330, 31, 114, 30, 27, 30, 54, 26, 23, 43, 36},
+ {6320, 31, 113, 30, 27, 30, 54, 26, 23, 43, 36},
+ {6310, 31, 113, 30, 27, 30, 54, 26, 23, 43, 36},
+ {6300, 31, 113, 30, 27, 30, 54, 26, 23, 43, 36},
+ {6290, 31, 113, 30, 27, 29, 54, 26, 23, 43, 36},
+ {6280, 31, 112, 30, 27, 29, 54, 26, 23, 43, 36},
+ {6270, 31, 112, 30, 27, 29, 54, 26, 23, 43, 36},
+ {6260, 31, 112, 30, 27, 29, 54, 26, 23, 43, 36},
+ {6250, 31, 112, 30, 27, 29, 54, 26, 23, 42, 36},
+ {6240, 30, 113, 30, 27, 29, 54, 26, 23, 42, 36},
+ {6230, 30, 112, 30, 27, 29, 54, 26, 23, 42, 35},
+ {6220, 30, 112, 30, 27, 29, 53, 26, 23, 42, 35},
+ {6210, 30, 112, 30, 27, 29, 53, 26, 23, 42, 35},
+ {6200, 30, 112, 29, 27, 29, 53, 26, 23, 42, 35},
+ {6190, 30, 111, 29, 27, 29, 53, 26, 23, 42, 35},
+ {6180, 30, 111, 29, 27, 29, 53, 26, 23, 42, 35},
+ {6170, 30, 111, 29, 26, 29, 53, 26, 23, 42, 35},
+ {6160, 30, 111, 29, 26, 29, 53, 26, 23, 42, 35},
+ {6150, 30, 110, 29, 26, 29, 53, 26, 23, 42, 35},
+ {6140, 30, 110, 29, 26, 29, 52, 26, 23, 42, 35},
+ {6130, 30, 110, 29, 26, 29, 52, 25, 22, 42, 35},
+ {6120, 30, 110, 29, 26, 29, 52, 25, 22, 42, 35},
+ {6110, 30, 110, 29, 26, 29, 52, 25, 22, 42, 35},
+ {6100, 30, 109, 29, 26, 29, 52, 25, 22, 41, 35},
+ {6090, 30, 109, 29, 26, 29, 52, 25, 22, 41, 35},
+ {6080, 30, 109, 29, 26, 28, 53, 25, 22, 41, 35},
+ {6070, 30, 109, 29, 26, 28, 52, 25, 22, 41, 34},
+ {6060, 30, 108, 29, 26, 28, 52, 25, 22, 41, 34},
+ {6050, 30, 108, 29, 26, 28, 52, 25, 22, 41, 34},
+ {6040, 29, 109, 29, 26, 28, 52, 25, 22, 41, 34},
+ {6030, 29, 109, 29, 26, 28, 52, 25, 22, 41, 34},
+ {6020, 29, 108, 29, 26, 28, 52, 25, 22, 41, 34},
+ {6010, 29, 108, 29, 26, 28, 52, 25, 22, 41, 34},
+ {6000, 29, 108, 28, 26, 28, 51, 25, 22, 41, 34},
+ {5990, 29, 108, 28, 26, 28, 51, 25, 22, 41, 34},
+ {5980, 29, 107, 28, 26, 28, 51, 25, 22, 41, 34},
+ {5970, 29, 107, 28, 26, 28, 51, 25, 22, 41, 34},
+ {5960, 29, 107, 28, 26, 28, 51, 25, 22, 40, 34},
+ {5950, 29, 107, 28, 26, 28, 51, 25, 22, 40, 34},
+ {5940, 29, 107, 28, 25, 28, 51, 25, 22, 40, 34},
+ {5930, 29, 106, 28, 25, 28, 50, 25, 22, 40, 34},
+ {5920, 29, 106, 28, 25, 28, 50, 25, 22, 40, 34},
+ {5910, 29, 106, 28, 25, 28, 50, 25, 22, 40, 34},
+ {5900, 29, 106, 28, 25, 28, 50, 24, 22, 40, 33},
+ {5890, 29, 105, 28, 25, 28, 50, 24, 22, 40, 33},
+ {5880, 29, 105, 28, 25, 28, 50, 24, 22, 40, 33},
+ {5870, 29, 105, 28, 25, 27, 51, 24, 22, 40, 33},
+ {5860, 29, 105, 28, 25, 27, 51, 24, 21, 40, 33},
+ {5850, 29, 104, 28, 25, 27, 50, 24, 21, 40, 33},
+ {5840, 28, 105, 28, 25, 27, 50, 24, 21, 40, 33},
+ {5830, 28, 105, 28, 25, 27, 50, 24, 21, 40, 33},
+ {5820, 28, 105, 28, 25, 27, 50, 24, 21, 40, 33},
+ {5810, 28, 104, 28, 25, 27, 50, 24, 21, 39, 33},
+ {5800, 28, 104, 27, 25, 27, 50, 24, 21, 39, 33},
+ {5790, 28, 104, 27, 25, 27, 50, 24, 21, 39, 33},
+ {5780, 28, 104, 27, 25, 27, 49, 24, 21, 39, 33},
+ {5770, 28, 104, 27, 25, 27, 49, 24, 21, 39, 33},
+ {5760, 28, 103, 27, 25, 27, 49, 24, 21, 39, 33},
+ {5750, 28, 103, 27, 25, 27, 49, 24, 21, 39, 33},
+ {5740, 28, 103, 27, 25, 27, 49, 24, 21, 39, 33},
+ {5730, 28, 103, 27, 25, 27, 49, 24, 21, 39, 32},
+ {5720, 28, 102, 27, 25, 27, 49, 24, 21, 39, 32},
+ {5710, 28, 102, 27, 25, 27, 48, 24, 21, 39, 32},
+ {5700, 28, 102, 27, 24, 27, 48, 24, 21, 39, 32},
+ {5690, 28, 102, 27, 24, 27, 48, 24, 21, 39, 32},
+ {5680, 28, 101, 27, 24, 27, 48, 24, 21, 39, 32},
+ {5670, 28, 101, 27, 24, 27, 48, 23, 21, 38, 32},
+ {5660, 28, 101, 27, 24, 26, 49, 23, 21, 38, 32},
+ {5650, 28, 101, 27, 24, 26, 49, 23, 21, 38, 32},
+ {5640, 27, 101, 27, 24, 26, 48, 23, 21, 38, 32},
+ {5630, 27, 101, 27, 24, 26, 48, 23, 21, 38, 32},
+ {5620, 27, 101, 27, 24, 26, 48, 23, 21, 38, 32},
+ {5610, 27, 101, 27, 24, 26, 48, 23, 21, 38, 32},
+ {5600, 27, 101, 26, 24, 26, 48, 23, 20, 38, 32},
+ {5590, 27, 100, 26, 24, 26, 48, 23, 20, 38, 32},
+ {5580, 27, 100, 26, 24, 26, 48, 23, 20, 38, 32},
+ {5570, 27, 100, 26, 24, 26, 48, 23, 20, 38, 31},
+ {5560, 27, 100, 26, 24, 26, 47, 23, 20, 38, 31},
+ {5550, 27, 99, 26, 24, 26, 47, 23, 20, 38, 31},
+ {5540, 27, 99, 26, 24, 26, 47, 23, 20, 38, 31},
+ {5530, 27, 99, 26, 24, 26, 47, 23, 20, 38, 31},
+ {5520, 27, 99, 26, 24, 26, 47, 23, 20, 37, 31},
+ {5510, 27, 98, 26, 24, 26, 47, 23, 20, 37, 31},
+ {5500, 27, 98, 26, 24, 26, 47, 23, 20, 37, 31},
+ {5490, 27, 98, 26, 24, 26, 46, 23, 20, 37, 31},
+ {5480, 27, 98, 26, 24, 26, 46, 23, 20, 37, 31},
+ {5470, 27, 97, 26, 23, 26, 46, 23, 20, 37, 31},
+ {5460, 27, 97, 26, 23, 26, 46, 23, 20, 37, 31},
+ {5450, 27, 97, 26, 23, 25, 47, 23, 20, 37, 31},
+ {5440, 26, 98, 26, 23, 25, 47, 23, 20, 37, 31},
+ {5430, 26, 98, 26, 23, 25, 47, 22, 20, 37, 31},
+ {5420, 26, 97, 26, 23, 25, 46, 22, 20, 37, 31},
+ {5410, 26, 97, 26, 23, 25, 46, 22, 20, 37, 31},
+ {5400, 26, 97, 25, 23, 25, 46, 22, 20, 37, 30},
+ {5390, 26, 97, 25, 23, 25, 46, 22, 20, 37, 30},
+ {5380, 26, 96, 25, 23, 25, 46, 22, 20, 36, 30},
+ {5370, 26, 96, 25, 23, 25, 46, 22, 20, 36, 30},
+ {5360, 26, 96, 25, 23, 25, 46, 22, 20, 36, 30},
+ {5350, 26, 96, 25, 23, 25, 46, 22, 20, 36, 30},
+ {5340, 26, 95, 25, 23, 25, 45, 22, 20, 36, 30},
+ {5330, 26, 95, 25, 23, 25, 45, 22, 19, 36, 30},
+ {5320, 26, 95, 25, 23, 25, 45, 22, 19, 36, 30},
+ {5310, 26, 95, 25, 23, 25, 45, 22, 19, 36, 30},
+ {5300, 26, 95, 25, 23, 25, 45, 22, 19, 36, 30},
+ {5290, 26, 94, 25, 23, 25, 45, 22, 19, 36, 30},
+ {5280, 26, 94, 25, 23, 25, 45, 22, 19, 36, 30},
+ {5270, 26, 94, 25, 23, 25, 44, 22, 19, 36, 30},
+ {5260, 26, 94, 25, 23, 25, 44, 22, 19, 36, 30},
+ {5250, 25, 94, 25, 23, 24, 45, 22, 19, 36, 30},
+ {5240, 25, 94, 25, 23, 24, 45, 22, 19, 36, 29},
+ {5230, 25, 94, 25, 22, 24, 45, 22, 19, 35, 29},
+ {5220, 25, 94, 25, 22, 24, 45, 22, 19, 35, 29},
+ {5210, 25, 93, 25, 22, 24, 45, 22, 19, 35, 29},
+ {5200, 25, 93, 24, 22, 24, 44, 21, 19, 35, 29},
+ {5190, 25, 93, 24, 22, 24, 44, 21, 19, 35, 29},
+ {5180, 25, 93, 24, 22, 24, 44, 21, 19, 35, 29},
+ {5170, 25, 92, 24, 22, 24, 44, 21, 19, 35, 29},
+ {5160, 25, 92, 24, 22, 24, 44, 21, 19, 35, 29},
+ {5150, 25, 92, 24, 22, 24, 44, 21, 19, 35, 29},
+ {5140, 25, 92, 24, 22, 24, 44, 21, 19, 35, 29},
+ {5130, 25, 92, 24, 22, 24, 43, 21, 19, 35, 29},
+ {5120, 25, 91, 24, 22, 24, 43, 21, 19, 35, 29},
+ {5110, 25, 91, 24, 22, 24, 43, 21, 19, 35, 29},
+ {5100, 25, 91, 24, 22, 24, 43, 21, 19, 35, 29},
+ {5090, 25, 91, 24, 22, 24, 43, 21, 19, 34, 29},
+ {5080, 25, 90, 24, 22, 24, 43, 21, 19, 34, 29},
+ {5070, 25, 90, 24, 22, 24, 43, 21, 19, 34, 28},
+ {5060, 25, 90, 24, 22, 24, 43, 21, 18, 34, 28},
+ {5050, 24, 91, 24, 22, 24, 42, 21, 18, 34, 28},
+ {5040, 24, 90, 24, 22, 23, 43, 21, 18, 34, 28},
+ {5030, 24, 90, 24, 22, 23, 43, 21, 18, 34, 28},
+ {5020, 24, 90, 24, 22, 23, 43, 21, 18, 34, 28},
+ {5010, 24, 90, 24, 22, 23, 43, 21, 18, 34, 28},
+ {5000, 24, 89, 23, 21, 23, 43, 21, 18, 34, 28},
+ {4990, 24, 89, 23, 21, 23, 43, 21, 18, 34, 28},
+ {4980, 24, 89, 23, 21, 23, 42, 21, 18, 34, 28},
+ {4970, 24, 89, 23, 21, 23, 42, 21, 18, 34, 28},
+ {4960, 24, 89, 23, 21, 23, 42, 20, 18, 34, 28},
+ {4950, 24, 88, 23, 21, 23, 42, 20, 18, 34, 28},
+ {4940, 24, 88, 23, 21, 23, 42, 20, 18, 33, 28},
+ {4930, 24, 88, 23, 21, 23, 42, 20, 18, 33, 28},
+ {4920, 24, 88, 23, 21, 23, 42, 20, 18, 33, 28},
+ {4910, 24, 87, 23, 21, 23, 41, 20, 18, 33, 28},
+ {4900, 24, 87, 23, 21, 23, 41, 20, 18, 33, 27},
+ {4890, 24, 87, 23, 21, 23, 41, 20, 18, 33, 27},
+ {4880, 24, 87, 23, 21, 23, 41, 20, 18, 33, 27},
+ {4870, 24, 86, 23, 21, 23, 41, 20, 18, 33, 27},
+ {4860, 24, 86, 23, 21, 23, 41, 20, 18, 33, 27},
+ {4850, 23, 87, 23, 21, 23, 41, 20, 18, 33, 27},
+ {4840, 23, 87, 23, 21, 23, 40, 20, 18, 33, 27},
+ {4830, 23, 86, 23, 21, 22, 41, 20, 18, 33, 27},
+ {4820, 23, 86, 23, 21, 22, 41, 20, 18, 33, 27},
+ {4810, 23, 86, 23, 21, 22, 41, 20, 18, 33, 27},
+ {4800, 23, 86, 22, 21, 22, 41, 20, 17, 32, 27},
+ {4790, 23, 86, 22, 21, 22, 41, 20, 17, 32, 27},
+ {4780, 23, 85, 22, 21, 22, 41, 20, 17, 32, 27},
+ {4770, 23, 85, 22, 21, 22, 41, 20, 17, 32, 27},
+ {4760, 23, 85, 22, 20, 22, 40, 20, 17, 32, 27},
+ {4750, 23, 85, 22, 20, 22, 40, 20, 17, 32, 27},
+ {4740, 23, 84, 22, 20, 22, 40, 20, 17, 32, 26},
+ {4730, 23, 84, 22, 20, 22, 40, 19, 17, 32, 26},
+ {4720, 23, 84, 22, 20, 22, 40, 19, 17, 32, 26},
+ {4710, 23, 84, 22, 20, 22, 40, 19, 17, 32, 26},
+ {4700, 23, 83, 22, 20, 22, 40, 19, 17, 32, 26},
+ {4690, 23, 83, 22, 20, 22, 39, 19, 17, 32, 26},
+ {4680, 23, 83, 22, 20, 22, 39, 19, 17, 32, 26},
+ {4670, 23, 83, 22, 20, 22, 39, 19, 17, 32, 26},
+ {4660, 23, 82, 22, 20, 22, 39, 19, 17, 32, 26},
+ {4650, 22, 83, 22, 20, 22, 39, 19, 17, 31, 26},
+ {4640, 22, 83, 22, 20, 22, 39, 19, 17, 31, 26},
+ {4630, 22, 83, 22, 20, 22, 39, 19, 17, 31, 26},
+ {4620, 22, 83, 22, 20, 21, 39, 19, 17, 31, 26},
+ {4610, 22, 82, 22, 20, 21, 39, 19, 17, 31, 26},
+ {4600, 22, 82, 21, 20, 21, 39, 19, 17, 31, 26},
+ {4590, 22, 82, 21, 20, 21, 39, 19, 17, 31, 26},
+ {4580, 22, 82, 21, 20, 21, 39, 19, 17, 31, 26},
+ {4570, 22, 81, 21, 20, 21, 39, 19, 17, 31, 25},
+ {4560, 22, 81, 21, 20, 21, 39, 19, 17, 31, 25},
+ {4550, 22, 81, 21, 20, 21, 38, 19, 17, 31, 25},
+ {4540, 22, 81, 21, 20, 21, 38, 19, 17, 31, 25},
+ {4530, 22, 80, 21, 19, 21, 38, 19, 16, 31, 25},
+ {4520, 22, 80, 21, 19, 21, 38, 19, 16, 31, 25},
+ {4510, 22, 80, 21, 19, 21, 38, 19, 16, 31, 25},
+ {4500, 22, 80, 21, 19, 21, 38, 19, 16, 30, 25},
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+ {1490, 59, 25, 6, 77, 59, 10, 70, 44, 9, 73},
+ {1480, 59, 24, 6, 76, 58, 10, 70, 44, 9, 73},
+ {1470, 58, 24, 6, 76, 58, 10, 69, 44, 9, 72},
+ {1460, 58, 24, 6, 76, 58, 10, 69, 43, 9, 72},
+ {1450, 58, 24, 6, 75, 57, 10, 68, 43, 9, 71},
+ {1440, 57, 24, 6, 75, 57, 10, 68, 43, 9, 71},
+ {1430, 57, 23, 6, 75, 57, 10, 68, 43, 8, 70},
+ {1420, 56, 23, 6, 74, 57, 9, 67, 43, 8, 70},
+ {1410, 56, 23, 6, 74, 57, 9, 67, 43, 8, 69},
+ {1400, 56, 23, 5, 74, 55, 9, 67, 41, 8, 69},
+ {1390, 55, 23, 5, 73, 55, 9, 66, 41, 8, 68},
+ {1380, 55, 23, 5, 73, 54, 9, 66, 41, 8, 68},
+ {1370, 54, 22, 5, 72, 54, 9, 66, 41, 8, 67},
+ {1360, 54, 22, 5, 72, 54, 9, 65, 40, 8, 67},
+ {1350, 54, 22, 5, 72, 53, 9, 65, 40, 8, 66},
+ {1340, 53, 22, 5, 71, 53, 9, 65, 40, 8, 66},
+ {1330, 53, 22, 5, 71, 53, 9, 64, 39, 8, 65},
+ {1320, 52, 22, 5, 71, 53, 8, 64, 40, 8, 65},
+ {1310, 52, 21, 5, 70, 53, 8, 64, 40, 8, 64},
+ {1300, 51, 21, 5, 70, 51, 8, 63, 38, 8, 64},
+ {1290, 51, 21, 5, 70, 51, 8, 63, 38, 7, 64},
+ {1280, 51, 21, 5, 69, 51, 8, 63, 38, 7, 63},
+ {1270, 50, 21, 5, 69, 50, 8, 62, 38, 7, 63},
+ {1260, 50, 20, 5, 69, 50, 8, 62, 37, 7, 62},
+ {1250, 49, 20, 5, 68, 49, 8, 62, 37, 7, 62},
+ {1240, 49, 20, 5, 68, 49, 8, 61, 37, 7, 61},
+ {1230, 49, 20, 5, 68, 49, 8, 61, 36, 7, 61},
+ {1220, 48, 20, 5, 67, 48, 8, 61, 36, 7, 60},
+ {1210, 48, 19, 5, 67, 48, 7, 60, 36, 7, 60},
+ {1200, 49, 19, 4, 67, 49, 7, 60, 36, 7, 59},
+ {1190, 48, 19, 4, 66, 48, 7, 60, 36, 7, 59},
+ {1180, 48, 19, 4, 66, 48, 7, 59, 36, 7, 58},
+ {1170, 46, 19, 4, 66, 46, 7, 59, 35, 7, 58},
+ {1160, 46, 18, 4, 65, 46, 7, 59, 34, 7, 57},
+ {1150, 45, 18, 4, 65, 46, 7, 58, 34, 7, 57},
+ {1140, 45, 18, 4, 65, 45, 7, 58, 34, 6, 56},
+ {1130, 45, 18, 4, 64, 45, 7, 58, 33, 6, 56},
+ {1120, 44, 18, 4, 64, 44, 7, 57, 33, 6, 55},
+ {1110, 44, 18, 4, 64, 44, 7, 57, 33, 6, 55},
+ {1100, 43, 17, 4, 63, 44, 6, 57, 32, 6, 54},
+ {1090, 43, 17, 4, 63, 44, 6, 56, 33, 6, 54},
+ {1080, 43, 17, 4, 63, 44, 6, 56, 33, 6, 53},
+ {1070, 42, 17, 4, 62, 44, 6, 56, 33, 6, 53},
+ {1060, 42, 17, 4, 62, 42, 6, 55, 31, 6, 52},
+ {1050, 41, 17, 4, 62, 42, 6, 55, 31, 6, 52},
+ {1040, 41, 16, 4, 61, 41, 6, 54, 31, 6, 52},
+ {1030, 41, 16, 4, 61, 41, 6, 54, 30, 6, 51},
+ {1020, 40, 16, 4, 61, 41, 6, 54, 30, 6, 51},
+ {1010, 40, 16, 4, 60, 40, 6, 53, 30, 6, 50},
+ {1000, 39, 16, 3, 60, 40, 6, 53, 29, 5, 50},
+ { 990, 39, 15, 3, 60, 39, 6, 53, 29, 5, 49},
+ { 980, 39, 15, 3, 59, 39, 5, 52, 29, 5, 49},
+ { 970, 38, 15, 3, 59, 39, 5, 52, 29, 5, 48},
+ { 960, 38, 15, 3, 59, 39, 5, 52, 29, 5, 48},
+ { 950, 37, 15, 3, 58, 39, 5, 51, 29, 5, 47},
+ { 940, 37, 14, 3, 58, 39, 5, 51, 29, 5, 47},
+ { 930, 37, 14, 3, 57, 37, 5, 51, 27, 5, 46},
+ { 920, 36, 14, 3, 57, 37, 5, 50, 27, 5, 46},
+ { 910, 36, 14, 3, 57, 36, 5, 50, 27, 5, 45},
+ { 900, 35, 14, 3, 56, 36, 5, 50, 26, 5, 45},
+ { 890, 35, 14, 3, 56, 36, 5, 49, 26, 5, 44},
+ { 880, 35, 13, 3, 56, 35, 5, 49, 26, 5, 44},
+ { 870, 34, 13, 3, 55, 35, 4, 49, 26, 5, 43},
+ { 860, 34, 13, 3, 55, 35, 4, 48, 25, 5, 43},
+ { 850, 33, 13, 3, 55, 35, 4, 48, 26, 4, 42},
+ { 840, 33, 13, 3, 54, 35, 4, 48, 26, 4, 42},
+ { 830, 33, 12, 3, 54, 33, 4, 47, 24, 4, 41},
+ { 820, 32, 12, 3, 54, 33, 4, 47, 24, 4, 41},
+ { 810, 32, 12, 3, 53, 33, 4, 47, 24, 4, 40},
+ { 800, 31, 12, 2, 53, 32, 4, 46, 23, 4, 40},
+ { 790, 31, 12, 2, 53, 32, 4, 46, 23, 4, 39},
+ { 780, 30, 12, 2, 52, 31, 4, 46, 23, 4, 39},
+ { 770, 30, 11, 2, 52, 31, 4, 45, 23, 4, 39},
+ { 760, 30, 11, 2, 52, 31, 3, 45, 22, 4, 38},
+ { 750, 29, 11, 2, 51, 30, 3, 45, 22, 4, 38},
+ { 740, 29, 11, 2, 51, 30, 3, 44, 22, 4, 37},
+ { 730, 28, 11, 2, 51, 31, 3, 44, 22, 4, 37},
+ { 720, 28, 10, 2, 50, 30, 3, 44, 22, 4, 36},
+ { 710, 28, 10, 2, 50, 30, 3, 43, 22, 4, 36},
+ { 700, 27, 10, 2, 50, 28, 3, 43, 20, 3, 35},
+ { 690, 27, 10, 2, 49, 28, 3, 43, 20, 3, 35},
+ { 680, 26, 10, 2, 49, 28, 3, 42, 20, 3, 34},
+ { 670, 26, 10, 2, 49, 27, 3, 42, 20, 3, 34},
+ { 660, 26, 9, 2, 48, 27, 3, 42, 19, 3, 33},
+ { 650, 25, 9, 2, 48, 26, 3, 41, 19, 3, 33},
+ { 640, 25, 9, 2, 48, 26, 2, 41, 19, 3, 32},
+ { 630, 24, 9, 2, 47, 26, 2, 40, 18, 3, 32},
+ { 620, 24, 9, 2, 47, 26, 2, 40, 19, 3, 31},
+ { 610, 24, 8, 2, 47, 26, 2, 40, 19, 3, 31},
+ { 600, 23, 8, 1, 46, 26, 2, 39, 18, 3, 30},
+ { 590, 23, 8, 1, 46, 24, 2, 39, 17, 3, 30},
+ { 580, 22, 8, 1, 46, 24, 2, 39, 17, 3, 29},
+ { 570, 22, 8, 1, 45, 23, 2, 38, 17, 3, 29},
+ { 560, 22, 7, 1, 45, 23, 2, 38, 16, 2, 28},
+ { 550, 21, 7, 1, 45, 23, 2, 38, 16, 2, 28},
+ { 540, 21, 7, 1, 44, 22, 2, 37, 16, 2, 27},
+ { 530, 20, 7, 1, 44, 22, 1, 37, 15, 2, 27},
+ { 520, 20, 7, 1, 43, 21, 1, 37, 15, 2, 27},
+ { 510, 20, 6, 1, 43, 21, 1, 36, 15, 2, 26},
+ { 500, 19, 6, 1, 43, 22, 1, 36, 15, 2, 26},
+ { 490, 19, 6, 1, 42, 21, 1, 36, 15, 2, 25},
+ { 480, 18, 6, 1, 42, 21, 1, 35, 15, 2, 25},
+ { 470, 18, 6, 1, 42, 21, 1, 35, 15, 2, 24},
+ { 460, 18, 6, 1, 41, 19, 1, 35, 13, 2, 24},
+ { 450, 17, 5, 1, 41, 19, 1, 34, 13, 2, 23},
+ { 440, 17, 5, 1, 41, 18, 1, 34, 13, 2, 23},
+ { 430, 16, 5, 1, 40, 18, 0, 34, 12, 2, 22},
+ { 420, 16, 5, 1, 40, 18, 0, 33, 12, 2, 22},
+ { 410, 16, 5, 1, 40, 17, 0, 33, 12, 1, 21},
+ { 400, 15, 5, 0, 39, 17, 0, 33, 11, 1, 21},
+ { 390, 15, 4, 0, 39, 17, 0, 32, 12, 1, 20},
+ { 380, 14, 4, 0, 39, 17, 0, 32, 12, 1, 20},
+ { 370, 14, 4, 0, 38, 17, 0, 32, 12, 1, 19},
+ { 360, 14, 4, 0, 38, 15, 0, 31, 10, 1, 19},
+ { 350, 13, 4, 0, 38, 15, 0, 31, 10, 1, 18},
+ { 340, 13, 3, 0, 37, 15, 0, 31, 10, 1, 18},
+ { 330, 12, 3, 0, 37, 14, 0, 30, 9, 1, 17},
+ { 320, 12, 3, 0, 37, 14, 0, 30, 9, 1, 17},
+ { 310, 12, 3, 0, 36, 13, 0, 30, 9, 1, 16},
+ { 300, 11, 3, 0, 36, 13, 0, 29, 8, 1, 16},
+ { 290, 11, 2, 0, 36, 13, 0, 29, 8, 1, 15},
+ { 280, 10, 2, 0, 35, 12, 0, 29, 8, 1, 15},
+ { 270, 10, 2, 0, 35, 12, 0, 28, 8, 0, 14},
+ { 260, 9, 2, 0, 35, 12, 0, 28, 8, 0, 14},
+ { 250, 9, 2, 0, 34, 12, 0, 28, 8, 0, 14},
+ { 240, 9, 2, 0, 34, 12, 0, 27, 8, 0, 13},
+ { 230, 8, 1, 0, 34, 10, 0, 27, 6, 0, 13},
+ { 220, 8, 1, 0, 33, 10, 0, 27, 6, 0, 12},
+ { 210, 7, 1, 0, 33, 10, 0, 26, 6, 0, 12},
+ { 200, 7, 1, 0, 33, 9, 0, 26, 5, 0, 11},
+ { 190, 7, 1, 0, 32, 9, 0, 25, 5, 0, 11},
+ { 180, 6, 1, 0, 32, 8, 0, 25, 5, 0, 10},
+ { 170, 6, 0, 0, 32, 8, 0, 25, 5, 0, 10},
+ { 160, 5, 0, 0, 31, 8, 0, 24, 4, 0, 9},
+ { 150, 5, 0, 0, 31, 8, 0, 24, 5, 0, 9},
+ { 140, 5, 0, 0, 31, 8, 0, 24, 5, 0, 8},
+ { 130, 4, 0, 0, 30, 6, 0, 23, 3, 0, 8},
+ { 120, 4, 0, 0, 30, 6, 0, 23, 3, 0, 7},
+ { 110, 3, 0, 0, 30, 6, 0, 23, 3, 0, 7},
+ { 100, 3, 0, 0, 29, 5, 0, 22, 2, 0, 6},
+ { 90, 3, 0, 0, 29, 5, 0, 22, 2, 0, 6},
+ { 80, 2, 0, 0, 28, 5, 0, 22, 2, 0, 5},
+};
+
+struct hsfreq_range {
+ u32 range_h;
+ u16 cfg_bit;
+};
+
+/* These tables must be sorted by .range_h ascending. */
+static const struct hsfreq_range samsung_dphy_rx_hsfreq_ranges[] = {
+ { 80, 0x105}, { 100, 0x106}, { 120, 0x107}, { 140, 0x108},
+ { 160, 0x109}, { 180, 0x10a}, { 200, 0x10b}, { 220, 0x10c},
+ { 240, 0x10d}, { 270, 0x10e}, { 290, 0x10f}, { 310, 0x110},
+ { 330, 0x111}, { 350, 0x112}, { 370, 0x113}, { 390, 0x114},
+ { 410, 0x115}, { 430, 0x116}, { 450, 0x117}, { 470, 0x118},
+ { 490, 0x119}, { 510, 0x11a}, { 540, 0x11b}, { 560, 0x11c},
+ { 580, 0x11d}, { 600, 0x11e}, { 620, 0x11f}, { 640, 0x120},
+ { 660, 0x121}, { 680, 0x122}, { 700, 0x123}, { 720, 0x124},
+ { 740, 0x125}, { 760, 0x126}, { 790, 0x127}, { 810, 0x128},
+ { 830, 0x129}, { 850, 0x12a}, { 870, 0x12b}, { 890, 0x12c},
+ { 910, 0x12d}, { 930, 0x12e}, { 950, 0x12f}, { 970, 0x130},
+ { 990, 0x131}, {1010, 0x132}, {1030, 0x133}, {1060, 0x134},
+ {1080, 0x135}, {1100, 0x136}, {1120, 0x137}, {1140, 0x138},
+ {1160, 0x139}, {1180, 0x13a}, {1200, 0x13b}, {1220, 0x13c},
+ {1240, 0x13d}, {1260, 0x13e}, {1280, 0x13f}, {1310, 0x140},
+ {1330, 0x141}, {1350, 0x142}, {1370, 0x143}, {1390, 0x144},
+ {1410, 0x145}, {1430, 0x146}, {1450, 0x147}, {1470, 0x148},
+ {1490, 0x149}, {1580, 0x007}, {1740, 0x008}, {1910, 0x009},
+ {2070, 0x00a}, {2240, 0x00b}, {2410, 0x00c}, {2570, 0x00d},
+ {2740, 0x00e}, {2910, 0x00f}, {3070, 0x010}, {3240, 0x011},
+ {3410, 0x012}, {3570, 0x013}, {3740, 0x014}, {3890, 0x015},
+ {4070, 0x016}, {4240, 0x017}, {4400, 0x018}, {4500, 0x019},
+};
+
+static void samsung_mipi_dcphy_bias_block_enable(struct samsung_mipi_dcphy *samsung)
+{
+ u32 bias_con2 = 0x3223;
+
+ regmap_write(samsung->regmap, BIAS_CON0, 0x0010);
+ regmap_write(samsung->regmap, BIAS_CON1, 0x0110);
+ regmap_write(samsung->regmap, BIAS_CON2, bias_con2);
+
+ /* output voltage, 400mV for DPHY, 530mV for CPHY */
+ regmap_update_bits(samsung->regmap, BIAS_CON4,
+ I_MUX_SEL_MASK, I_MUX_SEL_400MV);
+}
+
+static void samsung_mipi_dcphy_bias_block_disable(struct samsung_mipi_dcphy *samsung)
+{
+}
+
+static void samsung_mipi_dphy_lane_enable(struct samsung_mipi_dcphy *samsung)
+{
+ regmap_write(samsung->regmap, DPHY_MC_GNR_CON1, T_PHY_READY(0x2000));
+ regmap_update_bits(samsung->regmap, DPHY_MC_GNR_CON0,
+ PHY_ENABLE, PHY_ENABLE);
+
+ switch (samsung->lanes) {
+ case 4:
+ regmap_write(samsung->regmap, DPHY_MD3_GNR_CON1,
+ T_PHY_READY(0x2000));
+ regmap_update_bits(samsung->regmap, DPHY_MD3_GNR_CON0,
+ PHY_ENABLE, PHY_ENABLE);
+ fallthrough;
+ case 3:
+ regmap_write(samsung->regmap, COMBO_MD2_GNR_CON1,
+ T_PHY_READY(0x2000));
+ regmap_update_bits(samsung->regmap, COMBO_MD2_GNR_CON0,
+ PHY_ENABLE, PHY_ENABLE);
+ fallthrough;
+ case 2:
+ regmap_write(samsung->regmap, COMBO_MD1_GNR_CON1,
+ T_PHY_READY(0x2000));
+ regmap_update_bits(samsung->regmap, COMBO_MD1_GNR_CON0,
+ PHY_ENABLE, PHY_ENABLE);
+ fallthrough;
+ case 1:
+ default:
+ regmap_write(samsung->regmap, COMBO_MD0_GNR_CON1,
+ T_PHY_READY(0x2000));
+ regmap_update_bits(samsung->regmap, COMBO_MD0_GNR_CON0,
+ PHY_ENABLE, PHY_ENABLE);
+ break;
+ }
+}
+
+static void samsung_mipi_dphy_lane_disable(struct samsung_mipi_dcphy *samsung)
+{
+ regmap_update_bits(samsung->regmap, DPHY_MC_GNR_CON0, PHY_ENABLE, 0);
+ regmap_update_bits(samsung->regmap, COMBO_MD0_GNR_CON0, PHY_ENABLE, 0);
+ regmap_update_bits(samsung->regmap, COMBO_MD1_GNR_CON0, PHY_ENABLE, 0);
+ regmap_update_bits(samsung->regmap, COMBO_MD2_GNR_CON0, PHY_ENABLE, 0);
+ regmap_update_bits(samsung->regmap, DPHY_MD3_GNR_CON0, PHY_ENABLE, 0);
+}
+
+static void samsung_mipi_dcphy_pll_configure(struct samsung_mipi_dcphy *samsung)
+{
+ regmap_update_bits(samsung->regmap, PLL_CON0, S_MASK | P_MASK,
+ S(samsung->pll.scaler) | P(samsung->pll.prediv));
+
+ if (samsung->pll.dsm < 0) {
+ u16 dsm_tmp;
+
+ /* Using opposite number subtraction to find complement */
+ dsm_tmp = abs(samsung->pll.dsm);
+ dsm_tmp = dsm_tmp - 1;
+ dsm_tmp ^= 0xffff;
+ regmap_write(samsung->regmap, PLL_CON1, dsm_tmp);
+ } else {
+ regmap_write(samsung->regmap, PLL_CON1, samsung->pll.dsm);
+ }
+
+ regmap_update_bits(samsung->regmap, PLL_CON2,
+ M_MASK, M(samsung->pll.fbdiv));
+
+ if (samsung->pll.ssc_en) {
+ regmap_write(samsung->regmap, PLL_CON3,
+ MRR(samsung->pll.mrr) | MFR(samsung->pll.mfr));
+ regmap_update_bits(samsung->regmap, PLL_CON4, SSCG_EN, SSCG_EN);
+ }
+
+ regmap_write(samsung->regmap, PLL_CON5, RESET_N_SEL | PLL_ENABLE_SEL);
+ regmap_write(samsung->regmap, PLL_CON7, PLL_LOCK_CNT(0xf000));
+ regmap_write(samsung->regmap, PLL_CON8, PLL_STB_CNT(0xf000));
+}
+
+static int samsung_mipi_dcphy_pll_enable(struct samsung_mipi_dcphy *samsung)
+{
+ u32 sts;
+ int ret;
+
+ regmap_update_bits(samsung->regmap, PLL_CON0, PLL_EN, PLL_EN);
+
+ ret = regmap_read_poll_timeout(samsung->regmap, PLL_STAT0,
+ sts, (sts & PLL_LOCK), 1000, 20000);
+ if (ret < 0)
+ dev_err(samsung->dev, "DC-PHY pll failed to lock\n");
+
+ return ret;
+}
+
+static void samsung_mipi_dcphy_pll_disable(struct samsung_mipi_dcphy *samsung)
+{
+ regmap_update_bits(samsung->regmap, PLL_CON0, PLL_EN, 0);
+}
+
+static const struct samsung_mipi_dphy_timing *
+samsung_mipi_dphy_get_timing(struct samsung_mipi_dcphy *samsung)
+{
+ const struct samsung_mipi_dphy_timing *timings;
+ unsigned int num_timings;
+ unsigned int lane_mbps = div64_ul(samsung->pll.rate, USEC_PER_SEC);
+ unsigned int i;
+
+ timings = samsung_mipi_dphy_timing_table;
+ num_timings = ARRAY_SIZE(samsung_mipi_dphy_timing_table);
+
+ for (i = num_timings; i > 0; i--)
+ if (lane_mbps <= timings[i - 1].max_lane_mbps)
+ break;
+
+ if (i == 0)
+ ++i;
+
+ return &timings[i - 1];
+}
+
+static unsigned long
+samsung_mipi_dcphy_pll_round_rate(struct samsung_mipi_dcphy *samsung,
+ unsigned long prate, unsigned long rate,
+ u8 *prediv, u16 *fbdiv, int *dsm, u8 *scaler)
+{
+ u64 max_fout = MAX_DPHY_BW;
+ u64 best_freq = 0;
+ u64 fin, fvco, fout;
+ u8 min_prediv, max_prediv;
+ u8 _prediv, best_prediv = 1;
+ u16 _fbdiv, best_fbdiv = 1;
+ u8 _scaler, best_scaler = 0;
+ u32 min_delta = UINT_MAX;
+ long _dsm, best_dsm = 0;
+
+ /*
+ * The PLL output frequency can be calculated using a simple formula:
+ * Fvco = ((m+k/65536) x 2 x Fin) / p
+ * Fout = ((m+k/65536) x 2 x Fin) / (p x 2^s)
+ */
+ fin = div64_ul(prate, MSEC_PER_SEC);
+
+ while (!best_freq) {
+ fout = div64_ul(rate, MSEC_PER_SEC);
+ if (fout > max_fout)
+ fout = max_fout;
+
+ /* 0 ≤ S[2:0] ≤ 6 */
+ for (_scaler = 0; _scaler < 7; _scaler++) {
+ fvco = fout << _scaler;
+
+ /*
+ * 2600MHz ≤ FVCO ≤ 6600MHz
+ */
+ if (fvco < 2600 * MSEC_PER_SEC || fvco > 6600 * MSEC_PER_SEC)
+ continue;
+
+ /* 6MHz ≤ Fref(Fin / p) ≤ 30MHz */
+ min_prediv = DIV_ROUND_UP_ULL(fin, 30 * MSEC_PER_SEC);
+ max_prediv = DIV_ROUND_CLOSEST_ULL(fin, 6 * MSEC_PER_SEC);
+
+ for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
+ u64 delta, tmp;
+
+ _fbdiv = DIV_ROUND_CLOSEST_ULL(fvco * _prediv, 2 * fin);
+
+ /* 64 ≤ M[9:0] ≤ 1023 */
+ if (_fbdiv < 64 || _fbdiv > 1023)
+ continue;
+
+ /* -32767 ≤ K[15:0] ≤ 32767 */
+ _dsm = ((_prediv * fvco) - (2 * _fbdiv * fin));
+ _dsm = DIV_ROUND_UP_ULL(_dsm << 15, fin);
+ if (abs(_dsm) > 32767)
+ continue;
+
+ tmp = DIV_ROUND_CLOSEST_ULL((_fbdiv * fin * 2 * 1000), _prediv);
+ tmp += DIV_ROUND_CLOSEST_ULL((_dsm * fin * 1000), _prediv << 15);
+
+ delta = abs(fvco * MSEC_PER_SEC - tmp);
+ if (delta < min_delta) {
+ best_prediv = _prediv;
+ best_fbdiv = _fbdiv;
+ best_dsm = _dsm;
+ best_scaler = _scaler;
+ min_delta = delta;
+ best_freq = DIV_ROUND_CLOSEST_ULL(tmp, 1000) * MSEC_PER_SEC;
+ }
+ }
+ }
+
+ rate += 100 * MSEC_PER_SEC;
+ }
+
+ *prediv = best_prediv;
+ *fbdiv = best_fbdiv;
+ *dsm = (int)best_dsm & 0xffff;
+ *scaler = best_scaler;
+ dev_dbg(samsung->dev, "p: %d, m: %d, dsm:%ld, scaler: %d\n",
+ best_prediv, best_fbdiv, best_dsm, best_scaler);
+
+ return best_freq >> best_scaler;
+}
+
+static void
+samsung_mipi_dphy_clk_lane_timing_init(struct samsung_mipi_dcphy *samsung)
+{
+ const struct samsung_mipi_dphy_timing *timing;
+ unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC);
+ u32 val = 0;
+
+ timing = samsung_mipi_dphy_get_timing(samsung);
+ regmap_write(samsung->regmap, DPHY_MC_GNR_CON0, 0xf000);
+ regmap_write(samsung->regmap, DPHY_MC_ANA_CON0, 0x7133);
+
+ if (lane_hs_rate >= 4500)
+ regmap_write(samsung->regmap, DPHY_MC_ANA_CON1, 0x0001);
+
+ /*
+ * Divide-by-2 Clock from Serial Clock. Use this when data rate is under
+ * 1500Mbps, otherwise divide-by-16 Clock from Serial Clock
+ */
+ if (lane_hs_rate < 1500)
+ val = HSTX_CLK_SEL;
+
+ val |= T_LPX(timing->lpx);
+ /* T_LP_EXIT_SKEW/T_LP_ENTRY_SKEW unconfig */
+ regmap_write(samsung->regmap, DPHY_MC_TIME_CON0, val);
+
+ val = T_CLK_ZERO(timing->clk_zero) | T_CLK_PREPARE(timing->clk_prepare);
+ regmap_write(samsung->regmap, DPHY_MC_TIME_CON1, val);
+
+ val = T_HS_EXIT(timing->hs_exit) | T_CLK_TRAIL(timing->clk_trail_eot);
+ regmap_write(samsung->regmap, DPHY_MC_TIME_CON2, val);
+
+ val = T_CLK_POST(timing->clk_post);
+ regmap_write(samsung->regmap, DPHY_MC_TIME_CON3, val);
+
+ /* Escape Clock is 20.00MHz */
+ regmap_write(samsung->regmap, DPHY_MC_TIME_CON4, 0x1f4);
+
+ /*
+ * skew calibration should be off, if the operation data rate is
+ * under 1.5Gbps or equal to 1.5Gbps.
+ */
+ if (lane_hs_rate > 1500)
+ regmap_write(samsung->regmap, DPHY_MC_DESKEW_CON0, 0x9cb1);
+}
+
+static void
+samsung_mipi_dphy_data_lane_timing_init(struct samsung_mipi_dcphy *samsung)
+{
+ const struct samsung_mipi_dphy_timing *timing;
+ unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC);
+ u32 val = 0;
+
+ timing = samsung_mipi_dphy_get_timing(samsung);
+
+ regmap_write(samsung->regmap, COMBO_MD0_ANA_CON0, 0x7133);
+ regmap_write(samsung->regmap, COMBO_MD1_ANA_CON0, 0x7133);
+ regmap_write(samsung->regmap, COMBO_MD2_ANA_CON0, 0x7133);
+ regmap_write(samsung->regmap, DPHY_MD3_ANA_CON0, 0x7133);
+
+ if (lane_hs_rate >= 4500) {
+ regmap_write(samsung->regmap, COMBO_MD0_ANA_CON1, 0x0001);
+ regmap_write(samsung->regmap, COMBO_MD1_ANA_CON1, 0x0001);
+ regmap_write(samsung->regmap, COMBO_MD2_ANA_CON1, 0x0001);
+ regmap_write(samsung->regmap, DPHY_MD3_ANA_CON1, 0x0001);
+ }
+
+ /*
+ * Divide-by-2 Clock from Serial Clock. Use this when data rate is under
+ * 1500Mbps, otherwise divide-by-16 Clock from Serial Clock
+ */
+ if (lane_hs_rate < 1500)
+ val = HSTX_CLK_SEL;
+
+ val |= T_LPX(timing->lpx);
+ /* T_LP_EXIT_SKEW/T_LP_ENTRY_SKEW unconfig */
+ regmap_write(samsung->regmap, COMBO_MD0_TIME_CON0, val);
+ regmap_write(samsung->regmap, COMBO_MD1_TIME_CON0, val);
+ regmap_write(samsung->regmap, COMBO_MD2_TIME_CON0, val);
+ regmap_write(samsung->regmap, DPHY_MD3_TIME_CON0, val);
+
+ val = T_HS_ZERO(timing->hs_zero) | T_HS_PREPARE(timing->hs_prepare);
+ regmap_write(samsung->regmap, COMBO_MD0_TIME_CON1, val);
+ regmap_write(samsung->regmap, COMBO_MD1_TIME_CON1, val);
+ regmap_write(samsung->regmap, COMBO_MD2_TIME_CON1, val);
+ regmap_write(samsung->regmap, DPHY_MD3_TIME_CON1, val);
+
+ val = T_HS_EXIT(timing->hs_exit) | T_HS_TRAIL(timing->hs_trail_eot);
+ regmap_write(samsung->regmap, COMBO_MD0_TIME_CON2, val);
+ regmap_write(samsung->regmap, COMBO_MD1_TIME_CON2, val);
+ regmap_write(samsung->regmap, COMBO_MD2_TIME_CON2, val);
+ regmap_write(samsung->regmap, DPHY_MD3_TIME_CON2, val);
+
+ /* TTA-GET/TTA-GO Timing Counter register use default value */
+ val = T_TA_GET(0x3) | T_TA_GO(0x0);
+ regmap_write(samsung->regmap, COMBO_MD0_TIME_CON3, val);
+ regmap_write(samsung->regmap, COMBO_MD1_TIME_CON3, val);
+ regmap_write(samsung->regmap, COMBO_MD2_TIME_CON3, val);
+ regmap_write(samsung->regmap, DPHY_MD3_TIME_CON3, val);
+
+ /* Escape Clock is 20.00MHz */
+ regmap_write(samsung->regmap, COMBO_MD0_TIME_CON4, 0x1f4);
+ regmap_write(samsung->regmap, COMBO_MD1_TIME_CON4, 0x1f4);
+ regmap_write(samsung->regmap, COMBO_MD2_TIME_CON4, 0x1f4);
+ regmap_write(samsung->regmap, DPHY_MD3_TIME_CON4, 0x1f4);
+}
+
+static int samsung_mipi_dphy_power_on(struct samsung_mipi_dcphy *samsung)
+{
+ int ret;
+
+ reset_control_assert(samsung->m_phy_rst);
+
+ samsung_mipi_dcphy_bias_block_enable(samsung);
+ samsung_mipi_dcphy_pll_configure(samsung);
+ samsung_mipi_dphy_clk_lane_timing_init(samsung);
+ samsung_mipi_dphy_data_lane_timing_init(samsung);
+ ret = samsung_mipi_dcphy_pll_enable(samsung);
+ if (ret < 0) {
+ samsung_mipi_dcphy_bias_block_disable(samsung);
+ return ret;
+ }
+
+ samsung_mipi_dphy_lane_enable(samsung);
+
+ reset_control_deassert(samsung->m_phy_rst);
+
+ /* The TSKEWCAL maximum is 100 µsec
+ * at initial calibration.
+ */
+ usleep_range(100, 110);
+
+ return 0;
+}
+
+static int samsung_mipi_dcphy_power_on(struct phy *phy)
+{
+ struct samsung_mipi_dcphy *samsung = phy_get_drvdata(phy);
+ enum phy_mode mode = phy_get_mode(phy);
+
+ pm_runtime_get_sync(samsung->dev);
+ reset_control_assert(samsung->apb_rst);
+ udelay(1);
+ reset_control_deassert(samsung->apb_rst);
+
+ switch (mode) {
+ case PHY_MODE_MIPI_DPHY:
+ return samsung_mipi_dphy_power_on(samsung);
+ default:
+ /* CSI cphy part to be implemented later */
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+
+static int samsung_mipi_dcphy_power_off(struct phy *phy)
+{
+ struct samsung_mipi_dcphy *samsung = phy_get_drvdata(phy);
+ enum phy_mode mode = phy_get_mode(phy);
+
+ switch (mode) {
+ case PHY_MODE_MIPI_DPHY:
+ samsung_mipi_dphy_lane_disable(samsung);
+ break;
+ default:
+ /* CSI cphy part to be implemented later */
+ return -EOPNOTSUPP;
+ }
+
+ samsung_mipi_dcphy_pll_disable(samsung);
+ samsung_mipi_dcphy_bias_block_disable(samsung);
+
+ pm_runtime_put(samsung->dev);
+
+ return 0;
+}
+
+static int samsung_mipi_dcphy_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ return 0;
+}
+
+static int
+samsung_mipi_dcphy_pll_ssc_modulation_calc(struct samsung_mipi_dcphy *samsung,
+ u8 *mfr, u8 *mrr)
+{
+ unsigned long fin = div64_ul(clk_get_rate(samsung->ref_clk), MSEC_PER_SEC);
+ u16 prediv = samsung->pll.prediv;
+ u16 fbdiv = samsung->pll.fbdiv;
+ u16 min_mfr, max_mfr;
+ u16 _mfr, best_mfr = 0;
+ u16 mr, _mrr, best_mrr = 0;
+
+ /* 20KHz ≤ MF ≤ 150KHz */
+ max_mfr = DIV_ROUND_UP(fin, (20 * prediv) << 5);
+ min_mfr = div64_ul(fin, ((150 * prediv) << 5));
+ /*0 ≤ mfr ≤ 255 */
+ if (max_mfr > 256)
+ max_mfr = 256;
+
+ for (_mfr = min_mfr; _mfr < max_mfr; _mfr++) {
+ /* 1 ≤ mrr ≤ 31 */
+ for (_mrr = 1; _mrr < 32; _mrr++) {
+ mr = DIV_ROUND_UP(_mfr * _mrr * 100, fbdiv << 6);
+ /* 0 ≤ MR ≤ 5% */
+ if (mr > 5)
+ continue;
+
+ if (_mfr * _mrr < 513) {
+ best_mfr = _mfr;
+ best_mrr = _mrr;
+ break;
+ }
+ }
+ }
+
+ if (best_mrr) {
+ *mfr = best_mfr & 0xff;
+ *mrr = best_mrr & 0x3f;
+ } else {
+ dev_err(samsung->dev, "failed to calc ssc parameter mfr and mrr\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void
+samsung_mipi_dcphy_pll_calc_rate(struct samsung_mipi_dcphy *samsung,
+ unsigned long long rate)
+{
+ unsigned long prate = clk_get_rate(samsung->ref_clk);
+ unsigned long fout;
+ u8 scaler = 0, mfr = 0, mrr = 0;
+ u16 fbdiv = 1;
+ u8 prediv = 1;
+ int dsm = 0;
+ int ret;
+
+ fout = samsung_mipi_dcphy_pll_round_rate(samsung, prate, rate,
+ &prediv, &fbdiv, &dsm,
+ &scaler);
+
+ dev_dbg(samsung->dev, "%s: fin=%lu, req_rate=%llu\n",
+ __func__, prate, rate);
+ dev_dbg(samsung->dev, "%s: fout=%lu, prediv=%u, fbdiv=%u\n",
+ __func__, fout, prediv, fbdiv);
+
+ samsung->pll.prediv = prediv;
+ samsung->pll.fbdiv = fbdiv;
+ samsung->pll.dsm = dsm;
+ samsung->pll.scaler = scaler;
+ samsung->pll.rate = fout;
+
+ /*
+ * All DPHY 2.0 compliant Transmitters shall support SSC operating above
+ * 2.5 Gbps
+ */
+ if (fout > 2500000000LL) {
+ ret = samsung_mipi_dcphy_pll_ssc_modulation_calc(samsung,
+ &mfr, &mrr);
+ if (!ret) {
+ samsung->pll.ssc_en = true;
+ samsung->pll.mfr = mfr;
+ samsung->pll.mrr = mrr;
+ }
+ }
+}
+
+static int samsung_mipi_dcphy_configure(struct phy *phy,
+ union phy_configure_opts *opts)
+{
+ struct samsung_mipi_dcphy *samsung = phy_get_drvdata(phy);
+ unsigned long long target_rate = opts->mipi_dphy.hs_clk_rate;
+
+ samsung->lanes = opts->mipi_dphy.lanes > 4 ? 4 : opts->mipi_dphy.lanes;
+
+ samsung_mipi_dcphy_pll_calc_rate(samsung, target_rate);
+ opts->mipi_dphy.hs_clk_rate = samsung->pll.rate;
+
+ return 0;
+}
+
+static int samsung_mipi_dcphy_init(struct phy *phy)
+{
+ struct samsung_mipi_dcphy *samsung = phy_get_drvdata(phy);
+
+ pm_runtime_get_sync(samsung->dev);
+
+ return 0;
+}
+
+static int samsung_mipi_dcphy_exit(struct phy *phy)
+{
+ struct samsung_mipi_dcphy *samsung = phy_get_drvdata(phy);
+
+ pm_runtime_put(samsung->dev);
+
+ return 0;
+}
+
+static const struct phy_ops samsung_mipi_dcphy_ops = {
+ .configure = samsung_mipi_dcphy_configure,
+ .set_mode = samsung_mipi_dcphy_set_mode,
+ .power_on = samsung_mipi_dcphy_power_on,
+ .power_off = samsung_mipi_dcphy_power_off,
+ .init = samsung_mipi_dcphy_init,
+ .exit = samsung_mipi_dcphy_exit,
+ .owner = THIS_MODULE,
+};
+
+static const struct regmap_config samsung_mipi_dcphy_regmap_config = {
+ .name = "dcphy",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0x10000,
+};
+
+static int samsung_mipi_dcphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct samsung_mipi_dcphy *samsung;
+ struct phy_provider *phy_provider;
+ struct phy *phy;
+ struct resource *res;
+ void __iomem *regs;
+ int ret;
+
+ samsung = devm_kzalloc(dev, sizeof(*samsung), GFP_KERNEL);
+ if (!samsung)
+ return -ENOMEM;
+
+ samsung->dev = dev;
+ platform_set_drvdata(pdev, samsung);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ samsung->regmap = devm_regmap_init_mmio(dev, regs,
+ &samsung_mipi_dcphy_regmap_config);
+ if (IS_ERR(samsung->regmap)) {
+ ret = PTR_ERR(samsung->regmap);
+ dev_err(dev, "failed to init regmap: %d\n", ret);
+ return ret;
+ }
+
+ samsung->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(samsung->grf_regmap)) {
+ dev_err(dev, "Unable to get rockchip,grf\n");
+ return PTR_ERR(samsung->grf_regmap);
+ }
+
+ samsung->ref_clk = devm_clk_get(dev, "ref");
+ if (IS_ERR(samsung->ref_clk)) {
+ dev_err(dev, "failed to get reference clock\n");
+ return PTR_ERR(samsung->ref_clk);
+ }
+
+ samsung->pclk = devm_clk_get(dev, "pclk");
+ if (IS_ERR(samsung->pclk)) {
+ dev_err(dev, "failed to get pclk\n");
+ return PTR_ERR(samsung->pclk);
+ }
+
+ samsung->m_phy_rst = devm_reset_control_get(dev, "m_phy");
+ if (IS_ERR(samsung->m_phy_rst)) {
+ dev_err(dev, "failed to get system m_phy_rst control\n");
+ return PTR_ERR(samsung->m_phy_rst);
+ }
+
+ samsung->s_phy_rst = devm_reset_control_get(dev, "s_phy");
+ if (IS_ERR(samsung->s_phy_rst)) {
+ dev_err(dev, "failed to get system s_phy_rst control\n");
+ return PTR_ERR(samsung->s_phy_rst);
+ }
+
+ samsung->apb_rst = devm_reset_control_get(dev, "apb");
+ if (IS_ERR(samsung->apb_rst)) {
+ dev_err(dev, "failed to get system apb_rst control\n");
+ return PTR_ERR(samsung->apb_rst);
+ }
+
+ samsung->grf_apb_rst = devm_reset_control_get(dev, "grf");
+ if (IS_ERR(samsung->grf_apb_rst)) {
+ dev_err(dev, "failed to get system grf_apb_rst control\n");
+ return PTR_ERR(samsung->grf_apb_rst);
+ }
+
+ phy = devm_phy_create(dev, NULL, &samsung_mipi_dcphy_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create MIPI Dc-PHY\n");
+ return PTR_ERR(phy);
+ }
+
+ phy_set_drvdata(phy, samsung);
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider)) {
+ dev_err(dev, "failed to register phy provider\n");
+ return PTR_ERR(phy_provider);
+ }
+
+ return 0;
+}
+
+static __maybe_unused int samsung_mipi_dcphy_runtime_suspend(struct device *dev)
+{
+ struct samsung_mipi_dcphy *samsung = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(samsung->pclk);
+ clk_disable_unprepare(samsung->ref_clk);
+
+ return 0;
+}
+
+static __maybe_unused int samsung_mipi_dcphy_runtime_resume(struct device *dev)
+{
+ struct samsung_mipi_dcphy *samsung = dev_get_drvdata(dev);
+
+ clk_prepare_enable(samsung->pclk);
+ clk_prepare_enable(samsung->ref_clk);
+
+ return 0;
+}
+
+static const struct dev_pm_ops samsung_mipi_dcphy_pm_ops = {
+ RUNTIME_PM_OPS(samsung_mipi_dcphy_runtime_suspend,
+ samsung_mipi_dcphy_runtime_resume, NULL)
+};
+
+static const struct of_device_id samsung_mipi_dcphy_of_match[] = {
+ {
+ .compatible = "rockchip,rk3588-mipi-dcphy",
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, samsung_mipi_dcphy_of_match);
+
+static struct platform_driver samsung_mipi_dcphy_driver = {
+ .driver = {
+ .name = "samsung-mipi-dcphy",
+ .of_match_table = of_match_ptr(samsung_mipi_dcphy_of_match),
+ .pm = &samsung_mipi_dcphy_pm_ops,
+ },
+ .probe = samsung_mipi_dcphy_probe,
+};
+module_platform_driver(samsung_mipi_dcphy_driver);
+
+MODULE_AUTHOR("Guochun Huang<hero.huang@rock-chips.com>");
+MODULE_DESCRIPTION("Samsung MIPI DCPHY Driver");
+MODULE_LICENSE("GPL");
--
2.39.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 1%]
* Re: [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: Fix wrong lvts_ctrl index
2024-05-03 15:35 5% ` [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: " Julien Panis
2024-05-03 15:45 0% ` Nicolas Pitre
@ 2024-05-06 7:52 0% ` AngeloGioacchino Del Regno
1 sibling, 0 replies; 200+ results
From: AngeloGioacchino Del Regno @ 2024-05-06 7:52 UTC (permalink / raw)
To: Julien Panis, Rafael J. Wysocki, Daniel Lezcano, Zhang Rui,
Lukasz Luba, Matthias Brugger, Nicolas Pitre
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek
Il 03/05/24 17:35, Julien Panis ha scritto:
> In 'lvts_should_update_thresh()' and 'lvts_ctrl_start()' functions,
> the parameter passed to 'lvts_for_each_valid_sensor()' macro is always
> 'lvts_ctrl->lvts_data->lvts_ctrl'. In other words, the array index 0
> is systematically passed as 'struct lvts_ctrl_data' type item, even
> when another item should be consumed instead.
>
> Hence, the 'valid_sensor_mask' value which is selected can be wrong
> because unrelated to the 'struct lvts_ctrl_data' type item that should
> be used. Hence, some thermal zone can be registered for a sensor 'i'
> that does not actually exist. Because of the invalid address used
> as 'lvts_sensor[i].msr', this situation ends up with a crash in
> 'lvts_get_temp()' function, where this 'msr' pointer is passed to
> 'readl_poll_timeout()' function. The following message is output:
> "Unable to handle kernel NULL pointer dereference at virtual
> address <msr>", with <msr> = 0.
>
> This patch fixes the issue.
>
> Fixes: 11e6f4c31447 ("thermal/drivers/mediatek/lvts_thermal: Allow early empty sensor slots")
> Signed-off-by: Julien Panis <jpanis@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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^ permalink raw reply [relevance 0%]
* [PATCH RESEND v8 08/16] mm/execmem, arch: convert remaining overrides of module_alloc to execmem
@ 2024-05-05 16:06 6% ` Mike Rapoport
0 siblings, 0 replies; 200+ results
From: Mike Rapoport @ 2024-05-05 16:06 UTC (permalink / raw)
To: linux-kernel
Cc: Alexandre Ghiti, Andrew Morton, Björn Töpel,
Catalin Marinas, Christophe Leroy, David S. Miller, Dinh Nguyen,
Donald Dutile, Eric Chanudet, Heiko Carstens, Helge Deller,
Huacai Chen, Kent Overstreet, Liviu Dudau, Luis Chamberlain,
Mark Rutland, Masami Hiramatsu, Michael Ellerman, Mike Rapoport,
Nadav Amit, Palmer Dabbelt, Peter Zijlstra,
Philippe Mathieu-Daudé,
Rick Edgecombe, Russell King, Sam Ravnborg, Song Liu,
Steven Rostedt, Thomas Bogendoerfer, Thomas Gleixner,
Will Deacon, bpf, linux-arch, linux-arm-kernel, linux-mips,
linux-mm, linux-modules, linux-parisc, linux-riscv, linux-s390,
linux-trace-kernel, linuxppc-dev, loongarch, netdev, sparclinux,
x86
From: "Mike Rapoport (IBM)" <rppt@kernel.org>
Extend execmem parameters to accommodate more complex overrides of
module_alloc() by architectures.
This includes specification of a fallback range required by arm, arm64
and powerpc, EXECMEM_MODULE_DATA type required by powerpc, support for
allocation of KASAN shadow required by s390 and x86 and support for
late initialization of execmem required by arm64.
The core implementation of execmem_alloc() takes care of suppressing
warnings when the initial allocation fails but there is a fallback range
defined.
Signed-off-by: Mike Rapoport (IBM) <rppt@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Song Liu <song@kernel.org>
Tested-by: Liviu Dudau <liviu@dudau.co.uk>
---
arch/Kconfig | 8 ++++
arch/arm/kernel/module.c | 41 ++++++++++++--------
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/module.c | 55 +++++++++++++++------------
arch/powerpc/kernel/module.c | 60 +++++++++++++++++++----------
arch/s390/kernel/module.c | 54 +++++++++++---------------
arch/x86/kernel/module.c | 70 +++++++++++-----------------------
include/linux/execmem.h | 30 ++++++++++++++-
include/linux/moduleloader.h | 12 ------
kernel/module/main.c | 26 +++----------
mm/execmem.c | 74 ++++++++++++++++++++++++++++++------
11 files changed, 246 insertions(+), 185 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index 65afb1de48b3..4fd0daa54e6c 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -960,6 +960,14 @@ config ARCH_WANTS_MODULES_DATA_IN_VMALLOC
For architectures like powerpc/32 which have constraints on module
allocation and need to allocate module data outside of module area.
+config ARCH_WANTS_EXECMEM_LATE
+ bool
+ help
+ For architectures that do not allocate executable memory early on
+ boot, but rather require its initialization late when there is
+ enough entropy for module space randomization, for instance
+ arm64.
+
config HAVE_IRQ_EXIT_ON_IRQ_STACK
bool
help
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index e74d84f58b77..a98fdf6ff26c 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -16,6 +16,7 @@
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/gfp.h>
+#include <linux/execmem.h>
#include <asm/sections.h>
#include <asm/smp_plat.h>
@@ -34,23 +35,31 @@
#endif
#ifdef CONFIG_MMU
-void *module_alloc(unsigned long size)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- /* Silence the initial allocation */
- if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS))
- gfp_mask |= __GFP_NOWARN;
-
- p = __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
- gfp_mask, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- if (!IS_ENABLED(CONFIG_ARM_MODULE_PLTS) || p)
- return p;
- return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
+ unsigned long fallback_start = 0, fallback_end = 0;
+
+ if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS)) {
+ fallback_start = VMALLOC_START;
+ fallback_end = VMALLOC_END;
+ }
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = MODULES_VADDR,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL_EXEC,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#endif
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7b11c98b3e84..74b34a78b7ac 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -105,6 +105,7 @@ config ARM64
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
select ARCH_WANT_LD_ORPHAN_WARN
+ select ARCH_WANTS_EXECMEM_LATE if EXECMEM
select ARCH_WANTS_NO_INSTR
select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
select ARCH_HAS_UBSAN
diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c
index e92da4da1b2a..b7a7a23f9f8f 100644
--- a/arch/arm64/kernel/module.c
+++ b/arch/arm64/kernel/module.c
@@ -20,6 +20,7 @@
#include <linux/random.h>
#include <linux/scs.h>
#include <linux/vmalloc.h>
+#include <linux/execmem.h>
#include <asm/alternative.h>
#include <asm/insn.h>
@@ -108,41 +109,47 @@ static int __init module_init_limits(void)
return 0;
}
-subsys_initcall(module_init_limits);
-void *module_alloc(unsigned long size)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- void *p = NULL;
+ unsigned long fallback_start = 0, fallback_end = 0;
+ unsigned long start = 0, end = 0;
+
+ module_init_limits();
/*
* Where possible, prefer to allocate within direct branch range of the
* kernel such that no PLTs are necessary.
*/
if (module_direct_base) {
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- module_direct_base,
- module_direct_base + SZ_128M,
- GFP_KERNEL | __GFP_NOWARN,
- PAGE_KERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- }
+ start = module_direct_base;
+ end = module_direct_base + SZ_128M;
- if (!p && module_plt_base) {
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- module_plt_base,
- module_plt_base + SZ_2G,
- GFP_KERNEL | __GFP_NOWARN,
- PAGE_KERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- }
-
- if (!p) {
- pr_warn_ratelimited("%s: unable to allocate memory\n",
- __func__);
+ if (module_plt_base) {
+ fallback_start = module_plt_base;
+ fallback_end = module_plt_base + SZ_2G;
+ }
+ } else if (module_plt_base) {
+ start = module_plt_base;
+ end = module_plt_base + SZ_2G;
}
- /* Memory is intended to be executable, reset the pointer tag. */
- return kasan_reset_tag(p);
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = start,
+ .end = end,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ },
+ };
+
+ return &execmem_info;
}
enum aarch64_reloc_op {
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index f6d6ae0a1692..ac80559015a3 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -10,6 +10,7 @@
#include <linux/vmalloc.h>
#include <linux/mm.h>
#include <linux/bug.h>
+#include <linux/execmem.h>
#include <asm/module.h>
#include <linux/uaccess.h>
#include <asm/firmware.h>
@@ -89,39 +90,56 @@ int module_finalize(const Elf_Ehdr *hdr,
return 0;
}
-static __always_inline void *
-__module_alloc(unsigned long size, unsigned long start, unsigned long end, bool nowarn)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
pgprot_t prot = strict_module_rwx_enabled() ? PAGE_KERNEL : PAGE_KERNEL_EXEC;
- gfp_t gfp = GFP_KERNEL | (nowarn ? __GFP_NOWARN : 0);
+ unsigned long fallback_start = 0, fallback_end = 0;
+ unsigned long start, end;
/*
- * Don't do huge page allocations for modules yet until more testing
- * is done. STRICT_MODULE_RWX may require extra work to support this
- * too.
+ * BOOK3S_32 and 8xx define MODULES_VADDR for text allocations and
+ * allow allocating data in the entire vmalloc space
*/
- return __vmalloc_node_range(size, 1, start, end, gfp, prot,
- VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
-void *module_alloc(unsigned long size)
-{
#ifdef MODULES_VADDR
unsigned long limit = (unsigned long)_etext - SZ_32M;
- void *ptr = NULL;
BUILD_BUG_ON(TASK_SIZE > MODULES_VADDR);
/* First try within 32M limit from _etext to avoid branch trampolines */
- if (MODULES_VADDR < PAGE_OFFSET && MODULES_END > limit)
- ptr = __module_alloc(size, limit, MODULES_END, true);
-
- if (!ptr)
- ptr = __module_alloc(size, MODULES_VADDR, MODULES_END, false);
+ if (MODULES_VADDR < PAGE_OFFSET && MODULES_END > limit) {
+ start = limit;
+ fallback_start = MODULES_VADDR;
+ fallback_end = MODULES_END;
+ } else {
+ start = MODULES_VADDR;
+ }
- return ptr;
+ end = MODULES_END;
#else
- return __module_alloc(size, VMALLOC_START, VMALLOC_END, false);
+ start = VMALLOC_START;
+ end = VMALLOC_END;
#endif
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = start,
+ .end = end,
+ .pgprot = prot,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ [EXECMEM_MODULE_DATA] = {
+ .start = VMALLOC_START,
+ .end = VMALLOC_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ },
+ },
+ };
+
+ return &execmem_info;
}
diff --git a/arch/s390/kernel/module.c b/arch/s390/kernel/module.c
index ac97a905e8cd..7fee64fdc1bb 100644
--- a/arch/s390/kernel/module.c
+++ b/arch/s390/kernel/module.c
@@ -37,41 +37,31 @@
#define PLT_ENTRY_SIZE 22
-static unsigned long get_module_load_offset(void)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- static DEFINE_MUTEX(module_kaslr_mutex);
- static unsigned long module_load_offset;
-
- if (!kaslr_enabled())
- return 0;
- /*
- * Calculate the module_load_offset the first time this code
- * is called. Once calculated it stays the same until reboot.
- */
- mutex_lock(&module_kaslr_mutex);
- if (!module_load_offset)
+ unsigned long module_load_offset = 0;
+ unsigned long start;
+
+ if (kaslr_enabled())
module_load_offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
- mutex_unlock(&module_kaslr_mutex);
- return module_load_offset;
-}
-void *module_alloc(unsigned long size)
-{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- if (PAGE_ALIGN(size) > MODULES_LEN)
- return NULL;
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- MODULES_VADDR + get_module_load_offset(),
- MODULES_END, gfp_mask, PAGE_KERNEL,
- VM_FLUSH_RESET_PERMS | VM_DEFER_KMEMLEAK,
- NUMA_NO_NODE, __builtin_return_address(0));
- if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) {
- vfree(p);
- return NULL;
- }
- return p;
+ start = MODULES_VADDR + module_load_offset;
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .flags = EXECMEM_KASAN_SHADOW,
+ .start = start,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = MODULE_ALIGN,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#ifdef CONFIG_FUNCTION_TRACER
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index e18914c0e38a..45b1a7c03379 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -19,6 +19,7 @@
#include <linux/jump_label.h>
#include <linux/random.h>
#include <linux/memory.h>
+#include <linux/execmem.h>
#include <asm/text-patching.h>
#include <asm/page.h>
@@ -36,55 +37,30 @@ do { \
} while (0)
#endif
-#ifdef CONFIG_RANDOMIZE_BASE
-static unsigned long module_load_offset;
+static struct execmem_info execmem_info __ro_after_init;
-/* Mutex protects the module_load_offset. */
-static DEFINE_MUTEX(module_kaslr_mutex);
-
-static unsigned long int get_module_load_offset(void)
-{
- if (kaslr_enabled()) {
- mutex_lock(&module_kaslr_mutex);
- /*
- * Calculate the module_load_offset the first time this
- * code is called. Once calculated it stays the same until
- * reboot.
- */
- if (module_load_offset == 0)
- module_load_offset =
- get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
- mutex_unlock(&module_kaslr_mutex);
- }
- return module_load_offset;
-}
-#else
-static unsigned long int get_module_load_offset(void)
+struct execmem_info __init *execmem_arch_setup(void)
{
- return 0;
-}
-#endif
-
-void *module_alloc(unsigned long size)
-{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- if (PAGE_ALIGN(size) > MODULES_LEN)
- return NULL;
-
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- MODULES_VADDR + get_module_load_offset(),
- MODULES_END, gfp_mask, PAGE_KERNEL,
- VM_FLUSH_RESET_PERMS | VM_DEFER_KMEMLEAK,
- NUMA_NO_NODE, __builtin_return_address(0));
-
- if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) {
- vfree(p);
- return NULL;
- }
-
- return p;
+ unsigned long start, offset = 0;
+
+ if (kaslr_enabled())
+ offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
+
+ start = MODULES_VADDR + offset;
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .flags = EXECMEM_KASAN_SHADOW,
+ .start = start,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = MODULE_ALIGN,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#ifdef CONFIG_X86_32
diff --git a/include/linux/execmem.h b/include/linux/execmem.h
index 96fc59258467..32cef1144117 100644
--- a/include/linux/execmem.h
+++ b/include/linux/execmem.h
@@ -5,6 +5,14 @@
#include <linux/types.h>
#include <linux/moduleloader.h>
+#if (defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)) && \
+ !defined(CONFIG_KASAN_VMALLOC)
+#include <linux/kasan.h>
+#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
+#else
+#define MODULE_ALIGN PAGE_SIZE
+#endif
+
/**
* enum execmem_type - types of executable memory ranges
*
@@ -22,6 +30,7 @@
* @EXECMEM_KPROBES: parameters for kprobes
* @EXECMEM_FTRACE: parameters for ftrace
* @EXECMEM_BPF: parameters for BPF
+ * @EXECMEM_MODULE_DATA: parameters for module data sections
* @EXECMEM_TYPE_MAX:
*/
enum execmem_type {
@@ -30,22 +39,38 @@ enum execmem_type {
EXECMEM_KPROBES,
EXECMEM_FTRACE,
EXECMEM_BPF,
+ EXECMEM_MODULE_DATA,
EXECMEM_TYPE_MAX,
};
+/**
+ * enum execmem_range_flags - options for executable memory allocations
+ * @EXECMEM_KASAN_SHADOW: allocate kasan shadow
+ */
+enum execmem_range_flags {
+ EXECMEM_KASAN_SHADOW = (1 << 0),
+};
+
/**
* struct execmem_range - definition of an address space suitable for code and
* related data allocations
* @start: address space start
* @end: address space end (inclusive)
+ * @fallback_start: start of the secondary address space range for fallback
+ * allocations on architectures that require it
+ * @fallback_end: start of the secondary address space (inclusive)
* @pgprot: permissions for memory in this address space
* @alignment: alignment required for text allocations
+ * @flags: options for memory allocations for this range
*/
struct execmem_range {
unsigned long start;
unsigned long end;
+ unsigned long fallback_start;
+ unsigned long fallback_end;
pgprot_t pgprot;
unsigned int alignment;
+ enum execmem_range_flags flags;
};
/**
@@ -82,6 +107,9 @@ struct execmem_info *execmem_arch_setup(void);
* Allocates memory that will contain executable code, either generated or
* loaded from kernel modules.
*
+ * Allocates memory that will contain data coupled with executable code,
+ * like data sections in kernel modules.
+ *
* The memory will have protections defined by architecture for executable
* region of the @type.
*
@@ -95,7 +123,7 @@ void *execmem_alloc(enum execmem_type type, size_t size);
*/
void execmem_free(void *ptr);
-#ifdef CONFIG_EXECMEM
+#if defined(CONFIG_EXECMEM) && !defined(CONFIG_ARCH_WANTS_EXECMEM_LATE)
void execmem_init(void);
#else
static inline void execmem_init(void) {}
diff --git a/include/linux/moduleloader.h b/include/linux/moduleloader.h
index a3b8caee9405..e395461d59e5 100644
--- a/include/linux/moduleloader.h
+++ b/include/linux/moduleloader.h
@@ -25,10 +25,6 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
/* Additional bytes needed by arch in front of individual sections */
unsigned int arch_mod_section_prepend(struct module *mod, unsigned int section);
-/* Allocator used for allocating struct module, core sections and init
- sections. Returns NULL on failure. */
-void *module_alloc(unsigned long size);
-
/* Determines if the section name is an init section (that is only used during
* module loading).
*/
@@ -126,12 +122,4 @@ void module_arch_cleanup(struct module *mod);
/* Any cleanup before freeing mod->module_init */
void module_arch_freeing_init(struct module *mod);
-#if (defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)) && \
- !defined(CONFIG_KASAN_VMALLOC)
-#include <linux/kasan.h>
-#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
-#else
-#define MODULE_ALIGN PAGE_SIZE
-#endif
-
#endif
diff --git a/kernel/module/main.c b/kernel/module/main.c
index d56b7df0cbb6..91e185607d4b 100644
--- a/kernel/module/main.c
+++ b/kernel/module/main.c
@@ -1188,24 +1188,20 @@ void __weak module_arch_freeing_init(struct module *mod)
{
}
-static bool mod_mem_use_vmalloc(enum mod_mem_type type)
-{
- return IS_ENABLED(CONFIG_ARCH_WANTS_MODULES_DATA_IN_VMALLOC) &&
- mod_mem_type_is_core_data(type);
-}
-
static int module_memory_alloc(struct module *mod, enum mod_mem_type type)
{
unsigned int size = PAGE_ALIGN(mod->mem[type].size);
+ enum execmem_type execmem_type;
void *ptr;
mod->mem[type].size = size;
- if (mod_mem_use_vmalloc(type))
- ptr = vmalloc(size);
+ if (mod_mem_type_is_data(type))
+ execmem_type = EXECMEM_MODULE_DATA;
else
- ptr = execmem_alloc(EXECMEM_MODULE_TEXT, size);
+ execmem_type = EXECMEM_MODULE_TEXT;
+ ptr = execmem_alloc(execmem_type, size);
if (!ptr)
return -ENOMEM;
@@ -1232,10 +1228,7 @@ static void module_memory_free(struct module *mod, enum mod_mem_type type)
{
void *ptr = mod->mem[type].base;
- if (mod_mem_use_vmalloc(type))
- vfree(ptr);
- else
- execmem_free(ptr);
+ execmem_free(ptr);
}
static void free_mod_mem(struct module *mod)
@@ -1630,13 +1623,6 @@ static void free_modinfo(struct module *mod)
}
}
-void * __weak module_alloc(unsigned long size)
-{
- return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_EXEC, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
bool __weak module_init_section(const char *name)
{
return strstarts(name, ".init");
diff --git a/mm/execmem.c b/mm/execmem.c
index 80e61c1e7319..0c4b36bc6d10 100644
--- a/mm/execmem.c
+++ b/mm/execmem.c
@@ -12,27 +12,49 @@
#include <linux/moduleloader.h>
static struct execmem_info *execmem_info __ro_after_init;
+static struct execmem_info default_execmem_info __ro_after_init;
static void *__execmem_alloc(struct execmem_range *range, size_t size)
{
+ bool kasan = range->flags & EXECMEM_KASAN_SHADOW;
+ unsigned long vm_flags = VM_FLUSH_RESET_PERMS;
+ gfp_t gfp_flags = GFP_KERNEL | __GFP_NOWARN;
unsigned long start = range->start;
unsigned long end = range->end;
unsigned int align = range->alignment;
pgprot_t pgprot = range->pgprot;
+ void *p;
+
+ if (kasan)
+ vm_flags |= VM_DEFER_KMEMLEAK;
+
+ p = __vmalloc_node_range(size, align, start, end, gfp_flags,
+ pgprot, vm_flags, NUMA_NO_NODE,
+ __builtin_return_address(0));
+ if (!p && range->fallback_start) {
+ start = range->fallback_start;
+ end = range->fallback_end;
+ p = __vmalloc_node_range(size, align, start, end, gfp_flags,
+ pgprot, vm_flags, NUMA_NO_NODE,
+ __builtin_return_address(0));
+ }
+
+ if (!p) {
+ pr_warn_ratelimited("execmem: unable to allocate memory\n");
+ return NULL;
+ }
+
+ if (kasan && (kasan_alloc_module_shadow(p, size, GFP_KERNEL) < 0)) {
+ vfree(p);
+ return NULL;
+ }
- return __vmalloc_node_range(size, align, start, end,
- GFP_KERNEL, pgprot, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
+ return kasan_reset_tag(p);
}
void *execmem_alloc(enum execmem_type type, size_t size)
{
- struct execmem_range *range;
-
- if (!execmem_info)
- return module_alloc(size);
-
- range = &execmem_info->ranges[type];
+ struct execmem_range *range = &execmem_info->ranges[type];
return __execmem_alloc(range, size);
}
@@ -67,10 +89,16 @@ static void execmem_init_missing(struct execmem_info *info)
struct execmem_range *r = &info->ranges[i];
if (!r->start) {
- r->pgprot = default_range->pgprot;
+ if (i == EXECMEM_MODULE_DATA)
+ r->pgprot = PAGE_KERNEL;
+ else
+ r->pgprot = default_range->pgprot;
r->alignment = default_range->alignment;
r->start = default_range->start;
r->end = default_range->end;
+ r->flags = default_range->flags;
+ r->fallback_start = default_range->fallback_start;
+ r->fallback_end = default_range->fallback_end;
}
}
}
@@ -80,14 +108,36 @@ struct execmem_info * __weak execmem_arch_setup(void)
return NULL;
}
-void __init execmem_init(void)
+static void __init __execmem_init(void)
{
struct execmem_info *info = execmem_arch_setup();
- if (!info || !execmem_validate(info))
+ if (!info) {
+ info = execmem_info = &default_execmem_info;
+ info->ranges[EXECMEM_DEFAULT].start = VMALLOC_START;
+ info->ranges[EXECMEM_DEFAULT].end = VMALLOC_END;
+ info->ranges[EXECMEM_DEFAULT].pgprot = PAGE_KERNEL_EXEC;
+ info->ranges[EXECMEM_DEFAULT].alignment = 1;
+ }
+
+ if (!execmem_validate(info))
return;
execmem_init_missing(info);
execmem_info = info;
}
+
+#ifdef CONFIG_ARCH_WANTS_EXECMEM_LATE
+static int __init execmem_late_init(void)
+{
+ __execmem_init();
+ return 0;
+}
+core_initcall(execmem_late_init);
+#else
+void __init execmem_init(void)
+{
+ __execmem_init();
+}
+#endif
--
2.43.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 6%]
* [PATCH v8 08/17] mm/execmem, arch: convert remaining overrides of module_alloc to execmem
@ 2024-05-05 14:25 6% ` Mike Rapoport
0 siblings, 0 replies; 200+ results
From: Mike Rapoport @ 2024-05-05 14:25 UTC (permalink / raw)
To: linux-kernel
Cc: Alexandre Ghiti, Andrew Morton, Björn Töpel,
Catalin Marinas, Christophe Leroy, David S. Miller, Dinh Nguyen,
Donald Dutile, Eric Chanudet, Heiko Carstens, Helge Deller,
Huacai Chen, Kent Overstreet, Liviu Dudau, Luis Chamberlain,
Mark Rutland, Masami Hiramatsu, Michael Ellerman, Mike Rapoport,
Nadav Amit, Palmer Dabbelt, Peter Zijlstra,
Philippe Mathieu-Daudé,
Rick Edgecombe, Russell King, Sam Ravnborg, Song Liu,
Steven Rostedt, Thomas Bogendoerfer, Thomas Gleixner,
Will Deacon, bpf, linux-arch, linux-arm-kernel, linux-mips,
linux-mm, linux-modules, linux-parisc, linux-riscv, linux-s390,
linux-trace-kernel, linuxppc-dev, loongarch, netdev, sparclinux,
x86
From: "Mike Rapoport (IBM)" <rppt@kernel.org>
Extend execmem parameters to accommodate more complex overrides of
module_alloc() by architectures.
This includes specification of a fallback range required by arm, arm64
and powerpc, EXECMEM_MODULE_DATA type required by powerpc, support for
allocation of KASAN shadow required by s390 and x86 and support for
late initialization of execmem required by arm64.
The core implementation of execmem_alloc() takes care of suppressing
warnings when the initial allocation fails but there is a fallback range
defined.
Signed-off-by: Mike Rapoport (IBM) <rppt@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Song Liu <song@kernel.org>
Tested-by: Liviu Dudau <liviu@dudau.co.uk>
---
arch/Kconfig | 8 ++++
arch/arm/kernel/module.c | 41 ++++++++++++--------
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/module.c | 55 ++++++++++++++------------
arch/powerpc/kernel/module.c | 60 +++++++++++++++++++----------
arch/s390/kernel/module.c | 54 +++++++++++---------------
arch/x86/kernel/module.c | 70 +++++++++++----------------------
include/linux/execmem.h | 30 ++++++++++++++-
include/linux/moduleloader.h | 12 ------
kernel/module/main.c | 26 +++----------
mm/execmem.c | 75 ++++++++++++++++++++++++++++++------
11 files changed, 247 insertions(+), 185 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index 65afb1de48b3..4fd0daa54e6c 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -960,6 +960,14 @@ config ARCH_WANTS_MODULES_DATA_IN_VMALLOC
For architectures like powerpc/32 which have constraints on module
allocation and need to allocate module data outside of module area.
+config ARCH_WANTS_EXECMEM_LATE
+ bool
+ help
+ For architectures that do not allocate executable memory early on
+ boot, but rather require its initialization late when there is
+ enough entropy for module space randomization, for instance
+ arm64.
+
config HAVE_IRQ_EXIT_ON_IRQ_STACK
bool
help
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index e74d84f58b77..a98fdf6ff26c 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -16,6 +16,7 @@
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/gfp.h>
+#include <linux/execmem.h>
#include <asm/sections.h>
#include <asm/smp_plat.h>
@@ -34,23 +35,31 @@
#endif
#ifdef CONFIG_MMU
-void *module_alloc(unsigned long size)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- /* Silence the initial allocation */
- if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS))
- gfp_mask |= __GFP_NOWARN;
-
- p = __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
- gfp_mask, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- if (!IS_ENABLED(CONFIG_ARM_MODULE_PLTS) || p)
- return p;
- return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
+ unsigned long fallback_start = 0, fallback_end = 0;
+
+ if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS)) {
+ fallback_start = VMALLOC_START;
+ fallback_end = VMALLOC_END;
+ }
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = MODULES_VADDR,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL_EXEC,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#endif
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7b11c98b3e84..74b34a78b7ac 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -105,6 +105,7 @@ config ARM64
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
select ARCH_WANT_LD_ORPHAN_WARN
+ select ARCH_WANTS_EXECMEM_LATE if EXECMEM
select ARCH_WANTS_NO_INSTR
select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
select ARCH_HAS_UBSAN
diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c
index e92da4da1b2a..b7a7a23f9f8f 100644
--- a/arch/arm64/kernel/module.c
+++ b/arch/arm64/kernel/module.c
@@ -20,6 +20,7 @@
#include <linux/random.h>
#include <linux/scs.h>
#include <linux/vmalloc.h>
+#include <linux/execmem.h>
#include <asm/alternative.h>
#include <asm/insn.h>
@@ -108,41 +109,47 @@ static int __init module_init_limits(void)
return 0;
}
-subsys_initcall(module_init_limits);
-void *module_alloc(unsigned long size)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- void *p = NULL;
+ unsigned long fallback_start = 0, fallback_end = 0;
+ unsigned long start = 0, end = 0;
+
+ module_init_limits();
/*
* Where possible, prefer to allocate within direct branch range of the
* kernel such that no PLTs are necessary.
*/
if (module_direct_base) {
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- module_direct_base,
- module_direct_base + SZ_128M,
- GFP_KERNEL | __GFP_NOWARN,
- PAGE_KERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- }
+ start = module_direct_base;
+ end = module_direct_base + SZ_128M;
- if (!p && module_plt_base) {
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- module_plt_base,
- module_plt_base + SZ_2G,
- GFP_KERNEL | __GFP_NOWARN,
- PAGE_KERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- }
-
- if (!p) {
- pr_warn_ratelimited("%s: unable to allocate memory\n",
- __func__);
+ if (module_plt_base) {
+ fallback_start = module_plt_base;
+ fallback_end = module_plt_base + SZ_2G;
+ }
+ } else if (module_plt_base) {
+ start = module_plt_base;
+ end = module_plt_base + SZ_2G;
}
- /* Memory is intended to be executable, reset the pointer tag. */
- return kasan_reset_tag(p);
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = start,
+ .end = end,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ },
+ };
+
+ return &execmem_info;
}
enum aarch64_reloc_op {
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index f6d6ae0a1692..ac80559015a3 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -10,6 +10,7 @@
#include <linux/vmalloc.h>
#include <linux/mm.h>
#include <linux/bug.h>
+#include <linux/execmem.h>
#include <asm/module.h>
#include <linux/uaccess.h>
#include <asm/firmware.h>
@@ -89,39 +90,56 @@ int module_finalize(const Elf_Ehdr *hdr,
return 0;
}
-static __always_inline void *
-__module_alloc(unsigned long size, unsigned long start, unsigned long end, bool nowarn)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
pgprot_t prot = strict_module_rwx_enabled() ? PAGE_KERNEL : PAGE_KERNEL_EXEC;
- gfp_t gfp = GFP_KERNEL | (nowarn ? __GFP_NOWARN : 0);
+ unsigned long fallback_start = 0, fallback_end = 0;
+ unsigned long start, end;
/*
- * Don't do huge page allocations for modules yet until more testing
- * is done. STRICT_MODULE_RWX may require extra work to support this
- * too.
+ * BOOK3S_32 and 8xx define MODULES_VADDR for text allocations and
+ * allow allocating data in the entire vmalloc space
*/
- return __vmalloc_node_range(size, 1, start, end, gfp, prot,
- VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
-void *module_alloc(unsigned long size)
-{
#ifdef MODULES_VADDR
unsigned long limit = (unsigned long)_etext - SZ_32M;
- void *ptr = NULL;
BUILD_BUG_ON(TASK_SIZE > MODULES_VADDR);
/* First try within 32M limit from _etext to avoid branch trampolines */
- if (MODULES_VADDR < PAGE_OFFSET && MODULES_END > limit)
- ptr = __module_alloc(size, limit, MODULES_END, true);
-
- if (!ptr)
- ptr = __module_alloc(size, MODULES_VADDR, MODULES_END, false);
+ if (MODULES_VADDR < PAGE_OFFSET && MODULES_END > limit) {
+ start = limit;
+ fallback_start = MODULES_VADDR;
+ fallback_end = MODULES_END;
+ } else {
+ start = MODULES_VADDR;
+ }
- return ptr;
+ end = MODULES_END;
#else
- return __module_alloc(size, VMALLOC_START, VMALLOC_END, false);
+ start = VMALLOC_START;
+ end = VMALLOC_END;
#endif
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = start,
+ .end = end,
+ .pgprot = prot,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ [EXECMEM_MODULE_DATA] = {
+ .start = VMALLOC_START,
+ .end = VMALLOC_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ },
+ },
+ };
+
+ return &execmem_info;
}
diff --git a/arch/s390/kernel/module.c b/arch/s390/kernel/module.c
index ac97a905e8cd..7fee64fdc1bb 100644
--- a/arch/s390/kernel/module.c
+++ b/arch/s390/kernel/module.c
@@ -37,41 +37,31 @@
#define PLT_ENTRY_SIZE 22
-static unsigned long get_module_load_offset(void)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- static DEFINE_MUTEX(module_kaslr_mutex);
- static unsigned long module_load_offset;
-
- if (!kaslr_enabled())
- return 0;
- /*
- * Calculate the module_load_offset the first time this code
- * is called. Once calculated it stays the same until reboot.
- */
- mutex_lock(&module_kaslr_mutex);
- if (!module_load_offset)
+ unsigned long module_load_offset = 0;
+ unsigned long start;
+
+ if (kaslr_enabled())
module_load_offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
- mutex_unlock(&module_kaslr_mutex);
- return module_load_offset;
-}
-void *module_alloc(unsigned long size)
-{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- if (PAGE_ALIGN(size) > MODULES_LEN)
- return NULL;
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- MODULES_VADDR + get_module_load_offset(),
- MODULES_END, gfp_mask, PAGE_KERNEL,
- VM_FLUSH_RESET_PERMS | VM_DEFER_KMEMLEAK,
- NUMA_NO_NODE, __builtin_return_address(0));
- if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) {
- vfree(p);
- return NULL;
- }
- return p;
+ start = MODULES_VADDR + module_load_offset;
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .flags = EXECMEM_KASAN_SHADOW,
+ .start = start,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = MODULE_ALIGN,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#ifdef CONFIG_FUNCTION_TRACER
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index e18914c0e38a..45b1a7c03379 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -19,6 +19,7 @@
#include <linux/jump_label.h>
#include <linux/random.h>
#include <linux/memory.h>
+#include <linux/execmem.h>
#include <asm/text-patching.h>
#include <asm/page.h>
@@ -36,55 +37,30 @@ do { \
} while (0)
#endif
-#ifdef CONFIG_RANDOMIZE_BASE
-static unsigned long module_load_offset;
+static struct execmem_info execmem_info __ro_after_init;
-/* Mutex protects the module_load_offset. */
-static DEFINE_MUTEX(module_kaslr_mutex);
-
-static unsigned long int get_module_load_offset(void)
-{
- if (kaslr_enabled()) {
- mutex_lock(&module_kaslr_mutex);
- /*
- * Calculate the module_load_offset the first time this
- * code is called. Once calculated it stays the same until
- * reboot.
- */
- if (module_load_offset == 0)
- module_load_offset =
- get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
- mutex_unlock(&module_kaslr_mutex);
- }
- return module_load_offset;
-}
-#else
-static unsigned long int get_module_load_offset(void)
+struct execmem_info __init *execmem_arch_setup(void)
{
- return 0;
-}
-#endif
-
-void *module_alloc(unsigned long size)
-{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- if (PAGE_ALIGN(size) > MODULES_LEN)
- return NULL;
-
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- MODULES_VADDR + get_module_load_offset(),
- MODULES_END, gfp_mask, PAGE_KERNEL,
- VM_FLUSH_RESET_PERMS | VM_DEFER_KMEMLEAK,
- NUMA_NO_NODE, __builtin_return_address(0));
-
- if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) {
- vfree(p);
- return NULL;
- }
-
- return p;
+ unsigned long start, offset = 0;
+
+ if (kaslr_enabled())
+ offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
+
+ start = MODULES_VADDR + offset;
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .flags = EXECMEM_KASAN_SHADOW,
+ .start = start,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = MODULE_ALIGN,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#ifdef CONFIG_X86_32
diff --git a/include/linux/execmem.h b/include/linux/execmem.h
index 96fc59258467..32cef1144117 100644
--- a/include/linux/execmem.h
+++ b/include/linux/execmem.h
@@ -5,6 +5,14 @@
#include <linux/types.h>
#include <linux/moduleloader.h>
+#if (defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)) && \
+ !defined(CONFIG_KASAN_VMALLOC)
+#include <linux/kasan.h>
+#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
+#else
+#define MODULE_ALIGN PAGE_SIZE
+#endif
+
/**
* enum execmem_type - types of executable memory ranges
*
@@ -22,6 +30,7 @@
* @EXECMEM_KPROBES: parameters for kprobes
* @EXECMEM_FTRACE: parameters for ftrace
* @EXECMEM_BPF: parameters for BPF
+ * @EXECMEM_MODULE_DATA: parameters for module data sections
* @EXECMEM_TYPE_MAX:
*/
enum execmem_type {
@@ -30,22 +39,38 @@ enum execmem_type {
EXECMEM_KPROBES,
EXECMEM_FTRACE,
EXECMEM_BPF,
+ EXECMEM_MODULE_DATA,
EXECMEM_TYPE_MAX,
};
+/**
+ * enum execmem_range_flags - options for executable memory allocations
+ * @EXECMEM_KASAN_SHADOW: allocate kasan shadow
+ */
+enum execmem_range_flags {
+ EXECMEM_KASAN_SHADOW = (1 << 0),
+};
+
/**
* struct execmem_range - definition of an address space suitable for code and
* related data allocations
* @start: address space start
* @end: address space end (inclusive)
+ * @fallback_start: start of the secondary address space range for fallback
+ * allocations on architectures that require it
+ * @fallback_end: start of the secondary address space (inclusive)
* @pgprot: permissions for memory in this address space
* @alignment: alignment required for text allocations
+ * @flags: options for memory allocations for this range
*/
struct execmem_range {
unsigned long start;
unsigned long end;
+ unsigned long fallback_start;
+ unsigned long fallback_end;
pgprot_t pgprot;
unsigned int alignment;
+ enum execmem_range_flags flags;
};
/**
@@ -82,6 +107,9 @@ struct execmem_info *execmem_arch_setup(void);
* Allocates memory that will contain executable code, either generated or
* loaded from kernel modules.
*
+ * Allocates memory that will contain data coupled with executable code,
+ * like data sections in kernel modules.
+ *
* The memory will have protections defined by architecture for executable
* region of the @type.
*
@@ -95,7 +123,7 @@ void *execmem_alloc(enum execmem_type type, size_t size);
*/
void execmem_free(void *ptr);
-#ifdef CONFIG_EXECMEM
+#if defined(CONFIG_EXECMEM) && !defined(CONFIG_ARCH_WANTS_EXECMEM_LATE)
void execmem_init(void);
#else
static inline void execmem_init(void) {}
diff --git a/include/linux/moduleloader.h b/include/linux/moduleloader.h
index a3b8caee9405..e395461d59e5 100644
--- a/include/linux/moduleloader.h
+++ b/include/linux/moduleloader.h
@@ -25,10 +25,6 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
/* Additional bytes needed by arch in front of individual sections */
unsigned int arch_mod_section_prepend(struct module *mod, unsigned int section);
-/* Allocator used for allocating struct module, core sections and init
- sections. Returns NULL on failure. */
-void *module_alloc(unsigned long size);
-
/* Determines if the section name is an init section (that is only used during
* module loading).
*/
@@ -126,12 +122,4 @@ void module_arch_cleanup(struct module *mod);
/* Any cleanup before freeing mod->module_init */
void module_arch_freeing_init(struct module *mod);
-#if (defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)) && \
- !defined(CONFIG_KASAN_VMALLOC)
-#include <linux/kasan.h>
-#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
-#else
-#define MODULE_ALIGN PAGE_SIZE
-#endif
-
#endif
diff --git a/kernel/module/main.c b/kernel/module/main.c
index d56b7df0cbb6..91e185607d4b 100644
--- a/kernel/module/main.c
+++ b/kernel/module/main.c
@@ -1188,24 +1188,20 @@ void __weak module_arch_freeing_init(struct module *mod)
{
}
-static bool mod_mem_use_vmalloc(enum mod_mem_type type)
-{
- return IS_ENABLED(CONFIG_ARCH_WANTS_MODULES_DATA_IN_VMALLOC) &&
- mod_mem_type_is_core_data(type);
-}
-
static int module_memory_alloc(struct module *mod, enum mod_mem_type type)
{
unsigned int size = PAGE_ALIGN(mod->mem[type].size);
+ enum execmem_type execmem_type;
void *ptr;
mod->mem[type].size = size;
- if (mod_mem_use_vmalloc(type))
- ptr = vmalloc(size);
+ if (mod_mem_type_is_data(type))
+ execmem_type = EXECMEM_MODULE_DATA;
else
- ptr = execmem_alloc(EXECMEM_MODULE_TEXT, size);
+ execmem_type = EXECMEM_MODULE_TEXT;
+ ptr = execmem_alloc(execmem_type, size);
if (!ptr)
return -ENOMEM;
@@ -1232,10 +1228,7 @@ static void module_memory_free(struct module *mod, enum mod_mem_type type)
{
void *ptr = mod->mem[type].base;
- if (mod_mem_use_vmalloc(type))
- vfree(ptr);
- else
- execmem_free(ptr);
+ execmem_free(ptr);
}
static void free_mod_mem(struct module *mod)
@@ -1630,13 +1623,6 @@ static void free_modinfo(struct module *mod)
}
}
-void * __weak module_alloc(unsigned long size)
-{
- return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_EXEC, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
bool __weak module_init_section(const char *name)
{
return strstarts(name, ".init");
diff --git a/mm/execmem.c b/mm/execmem.c
index 80e61c1e7319..f6dc3fabc1ca 100644
--- a/mm/execmem.c
+++ b/mm/execmem.c
@@ -12,27 +12,49 @@
#include <linux/moduleloader.h>
static struct execmem_info *execmem_info __ro_after_init;
+static struct execmem_info default_execmem_info __ro_after_init;
static void *__execmem_alloc(struct execmem_range *range, size_t size)
{
+ bool kasan = range->flags & EXECMEM_KASAN_SHADOW;
+ unsigned long vm_flags = VM_FLUSH_RESET_PERMS;
+ gfp_t gfp_flags = GFP_KERNEL | __GFP_NOWARN;
unsigned long start = range->start;
unsigned long end = range->end;
unsigned int align = range->alignment;
pgprot_t pgprot = range->pgprot;
+ void *p;
+
+ if (kasan)
+ vm_flags |= VM_DEFER_KMEMLEAK;
+
+ p = __vmalloc_node_range(size, align, start, end, gfp_flags,
+ pgprot, vm_flags, NUMA_NO_NODE,
+ __builtin_return_address(0));
+ if (!p && range->fallback_start) {
+ start = range->fallback_start;
+ end = range->fallback_end;
+ p = __vmalloc_node_range(size, align, start, end, gfp_flags,
+ pgprot, vm_flags, NUMA_NO_NODE,
+ __builtin_return_address(0));
+ }
+
+ if (!p) {
+ pr_warn_ratelimited("execmem: unable to allocate memory\n");
+ return NULL;
+ }
+
+ if (kasan && (kasan_alloc_module_shadow(p, size, GFP_KERNEL) < 0)) {
+ vfree(p);
+ return NULL;
+ }
- return __vmalloc_node_range(size, align, start, end,
- GFP_KERNEL, pgprot, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
+ return kasan_reset_tag(p);
}
void *execmem_alloc(enum execmem_type type, size_t size)
{
- struct execmem_range *range;
-
- if (!execmem_info)
- return module_alloc(size);
-
- range = &execmem_info->ranges[type];
+ struct execmem_range *range = &execmem_info->ranges[type];
return __execmem_alloc(range, size);
}
@@ -67,10 +89,16 @@ static void execmem_init_missing(struct execmem_info *info)
struct execmem_range *r = &info->ranges[i];
if (!r->start) {
- r->pgprot = default_range->pgprot;
+ if (i == EXECMEM_MODULE_DATA)
+ r->pgprot = PAGE_KERNEL;
+ else
+ r->pgprot = default_range->pgprot;
r->alignment = default_range->alignment;
r->start = default_range->start;
r->end = default_range->end;
+ r->flags = default_range->flags;
+ r->fallback_start = default_range->fallback_start;
+ r->fallback_end = default_range->fallback_end;
}
}
}
@@ -80,14 +108,37 @@ struct execmem_info * __weak execmem_arch_setup(void)
return NULL;
}
-void __init execmem_init(void)
+static void __init __execmem_init(void)
{
struct execmem_info *info = execmem_arch_setup();
- if (!info || !execmem_validate(info))
+ if (!info) {
+ info = execmem_info = &default_execmem_info;
+ info->ranges[EXECMEM_DEFAULT].start = VMALLOC_START;
+ info->ranges[EXECMEM_DEFAULT].end = VMALLOC_END;
+ info->ranges[EXECMEM_DEFAULT].pgprot = PAGE_KERNEL_EXEC;
+ info->ranges[EXECMEM_DEFAULT].alignment = 1;
+ return;
+ }
+
+ if (!execmem_validate(info))
return;
execmem_init_missing(info);
execmem_info = info;
}
+
+#ifdef CONFIG_ARCH_WANTS_EXECMEM_LATE
+static int __init execmem_late_init(void)
+{
+ __execmem_init();
+ return 0;
+}
+core_initcall(execmem_late_init);
+#else
+void __init execmem_init(void)
+{
+ __execmem_init();
+}
+#endif
--
2.43.0
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 6%]
* Re: [PATCH] ARM: multi_v7_defconfig: Select CONFIG_USB_ONBOARD_DEV as built-in
2024-05-02 22:58 5% ` Fabio Estevam
2024-05-03 17:16 0% ` Matthias Kaehlcke
@ 2024-05-03 20:11 0% ` Matthias Kaehlcke
1 sibling, 0 replies; 200+ results
From: Matthias Kaehlcke @ 2024-05-03 20:11 UTC (permalink / raw)
To: Fabio Estevam
Cc: Arnd Bergmann, Alexander Stein, Fabio Estevam, linux-arm-kernel,
Mark Brown, javier.carrasco
On Thu, May 02, 2024 at 07:58:57PM -0300, Fabio Estevam wrote:
> Hi Matthias,
>
> On Thu, May 2, 2024 at 6:45 PM Matthias Kaehlcke <mka@chromium.org> wrote:
>
> > It is also not clear to me why things would be broken with
> > CONFIG_USB=y CONFIG_USB_ONBOARD_DEV=m, but not with CONFIG_USB=m. It
> > doesn't seem to be an universal issue, I can't repro it locally.
>
> This issue happens on an imx6q-udoo board.
>
> multi_v7_defconfig has CONFIG_USB=y and CONFIG_USB_ONBOARD_DEV=m:
> https://storage.kernelci.org/next/master/next-20240502/arm/multi_v7_defconfig+CONFIG_THUMB2_KERNEL=y/gcc-10/lab-broonie/baseline-imx6q-udoo.html
>
> usb 1-1: device descriptor read/64, error -71
> usb 1-1: device descriptor read/64, error -71
> usb 1-1: new full-speed USB device number 3 using ci_hdrc
> usb 1-1: device descriptor read/64, error -71
> usb 1-1: device descriptor read/64, error -71
> usb usb1-port1: attempt power cycle
> usb 1-1: new full-speed USB device number 4 using ci_hdrc
> usb 1-1: device not accepting address 4, error -71
> usb 1-1: new full-speed USB device number 5 using ci_hdrc
> usb 1-1: device not accepting address 5, error -71
> usb usb1-port1: unable to enumerate USB device
>
> imx_v6_v7_defconfig has CONFIG_USB=y and CONFIG_USB_ONBOARD_DEV=y:
> https://storage.kernelci.org/next/master/next-20240502/arm/imx_v6_v7_defconfig/gcc-10/lab-broonie/baseline-imx6q-udoo.html
>
> In this case, the USB Wifi chip connected to the USB2514 hub is
> correctly detected:
>
> usb 1-1.3: new high-speed USB device number 3 using ci_hdrc
> usb 1-1.3: New USB device found, idVendor=148f, idProduct=5370, bcdDevice= 1.01
> usb 1-1.3: New USB device strings: Mfr=1, Product=2, SerialNumber=3
> usb 1-1.3: Product: 802.11 n WLAN
> usb 1-1.3: Manufacturer: Ralink
> usb 1-1.3: SerialNumber: 1.0
Here are some debug logs from my side with CONFIG_USB_ONBOARD_DEV=m:
[ 0.755965] DBG: hub_probe: adding onboard pdevs
[ 0.756204] DBG: hub_probe: done
[ 0.756618] DBG: hub_probe: adding onboard pdevs
[ 0.756621] DBG: hub_probe: done
[ 8.094539] DBG: onboard_dev_init
[ 9.141729] DBG: onboard_dev_probe
[ 9.142237] DBG: onboard_dev_probe (done)
[ 9.142428] DBG: onboard_dev_init (done)
The root hub adds the onboard pdev at 0.75..., but the onboard_dev
module is only loaded more than 7s later (and probed even later). In
the meantime there are no errors of failed enumerations as seen on
the imx6q-udoo.
I wonder if the problem could be that the sense resistors of the hub
on the imx6q-udoo are always active and not only when the hub is
powered, indicating the controller the presence of a device, which
results in an attempt to enumerate it.
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^ permalink raw reply [relevance 0%]
* [PATCH v6 03/17] riscv: vector: Use vlenb from DT
@ 2024-05-03 18:18 5% ` Charlie Jenkins
2024-05-16 13:11 0% ` Andy Chiu
2024-05-16 14:00 0% ` Andy Chiu
0 siblings, 2 replies; 200+ results
From: Charlie Jenkins @ 2024-05-03 18:18 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Guo Ren, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Conor Dooley, Evan Green,
Clément Léger, Jonathan Corbet, Shuah Khan
Cc: linux-riscv, devicetree, linux-kernel, Palmer Dabbelt,
linux-arm-kernel, linux-sunxi, linux-doc, linux-kselftest,
Charlie Jenkins
If vlenb is provided in the device tree, prefer that over reading the
vlenb csr.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
arch/riscv/include/asm/cpufeature.h | 2 ++
arch/riscv/kernel/cpufeature.c | 47 +++++++++++++++++++++++++++++++++++++
arch/riscv/kernel/vector.c | 12 +++++++++-
3 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 347805446151..0c4f08577015 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
/* Per-cpu ISA extensions. */
extern struct riscv_isainfo hart_isa[NR_CPUS];
+extern u32 riscv_vlenb_of;
+
void riscv_user_isa_enable(void);
#if defined(CONFIG_RISCV_MISALIGNED)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3ed2359eae35..6c143ea9592b 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
/* Per-cpu ISA extensions. */
struct riscv_isainfo hart_isa[NR_CPUS];
+u32 riscv_vlenb_of;
+
/**
* riscv_isa_extension_base() - Get base extension word
*
@@ -648,6 +650,46 @@ static int __init riscv_isa_fallback_setup(char *__unused)
early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
#endif
+static int has_riscv_homogeneous_vlenb(void)
+{
+ int cpu;
+ u32 prev_vlenb = 0;
+ u32 vlenb;
+
+ /* Ignore vlenb if vector is not enabled in the kernel */
+ if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
+ return 0;
+
+ for_each_possible_cpu(cpu) {
+ struct device_node *cpu_node;
+
+ cpu_node = of_cpu_device_node_get(cpu);
+ if (!cpu_node) {
+ pr_warn("Unable to find cpu node\n");
+ return -ENOENT;
+ }
+
+ if (of_property_read_u32(cpu_node, "riscv,vlenb", &vlenb)) {
+ of_node_put(cpu_node);
+
+ if (prev_vlenb)
+ return -ENOENT;
+ continue;
+ }
+
+ if (prev_vlenb && vlenb != prev_vlenb) {
+ of_node_put(cpu_node);
+ return -ENOENT;
+ }
+
+ prev_vlenb = vlenb;
+ of_node_put(cpu_node);
+ }
+
+ riscv_vlenb_of = vlenb;
+ return 0;
+}
+
void __init riscv_fill_hwcap(void)
{
char print_str[NUM_ALPHA_EXTS + 1];
@@ -671,6 +713,11 @@ void __init riscv_fill_hwcap(void)
pr_info("Falling back to deprecated \"riscv,isa\"\n");
riscv_fill_hwcap_from_isa_string(isa2hwcap);
}
+
+ if (elf_hwcap & COMPAT_HWCAP_ISA_V && has_riscv_homogeneous_vlenb() < 0) {
+ pr_warn("Unsupported heterogeneous vlen detected, vector extension disabled.\n");
+ elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
+ }
}
/*
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index 6727d1d3b8f2..e04586cdb7f0 100644
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void)
{
unsigned long this_vsize;
- /* There are 32 vector registers with vlenb length. */
+ /*
+ * There are 32 vector registers with vlenb length.
+ *
+ * If the riscv,vlenb property was provided by the firmware, use that
+ * instead of probing the CSRs.
+ */
+ if (riscv_vlenb_of) {
+ this_vsize = riscv_vlenb_of * 32;
+ return 0;
+ }
+
riscv_v_enable();
this_vsize = csr_read(CSR_VLENB) * 32;
riscv_v_disable();
--
2.44.0
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* Re: [PATCH] ARM: multi_v7_defconfig: Select CONFIG_USB_ONBOARD_DEV as built-in
2024-05-02 22:58 5% ` Fabio Estevam
@ 2024-05-03 17:16 0% ` Matthias Kaehlcke
2024-05-03 20:11 0% ` Matthias Kaehlcke
1 sibling, 0 replies; 200+ results
From: Matthias Kaehlcke @ 2024-05-03 17:16 UTC (permalink / raw)
To: Fabio Estevam
Cc: Arnd Bergmann, Alexander Stein, Fabio Estevam, linux-arm-kernel,
Mark Brown, javier.carrasco
On Thu, May 2, 2024 at 3:59 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Matthias,
>
> On Thu, May 2, 2024 at 6:45 PM Matthias Kaehlcke <mka@chromium.org> wrote:
>
> > It is also not clear to me why things would be broken with
> > CONFIG_USB=y CONFIG_USB_ONBOARD_DEV=m, but not with CONFIG_USB=m. It
> > doesn't seem to be an universal issue, I can't repro it locally.
>
> This issue happens on an imx6q-udoo board.
>
> multi_v7_defconfig has CONFIG_USB=y and CONFIG_USB_ONBOARD_DEV=m:
> https://storage.kernelci.org/next/master/next-20240502/arm/multi_v7_defconfig+CONFIG_THUMB2_KERNEL=y/gcc-10/lab-broonie/baseline-imx6q-udoo.html
>
> usb 1-1: device descriptor read/64, error -71
> usb 1-1: device descriptor read/64, error -71
> usb 1-1: new full-speed USB device number 3 using ci_hdrc
> usb 1-1: device descriptor read/64, error -71
> usb 1-1: device descriptor read/64, error -71
> usb usb1-port1: attempt power cycle
> usb 1-1: new full-speed USB device number 4 using ci_hdrc
> usb 1-1: device not accepting address 4, error -71
> usb 1-1: new full-speed USB device number 5 using ci_hdrc
> usb 1-1: device not accepting address 5, error -71
> usb usb1-port1: unable to enumerate USB device
>
> imx_v6_v7_defconfig has CONFIG_USB=y and CONFIG_USB_ONBOARD_DEV=y:
> https://storage.kernelci.org/next/master/next-20240502/arm/imx_v6_v7_defconfig/gcc-10/lab-broonie/baseline-imx6q-udoo.html
>
> In this case, the USB Wifi chip connected to the USB2514 hub is
> correctly detected:
>
> usb 1-1.3: new high-speed USB device number 3 using ci_hdrc
> usb 1-1.3: New USB device found, idVendor=148f, idProduct=5370, bcdDevice= 1.01
> usb 1-1.3: New USB device strings: Mfr=1, Product=2, SerialNumber=3
> usb 1-1.3: Product: 802.11 n WLAN
> usb 1-1.3: Manufacturer: Ralink
> usb 1-1.3: SerialNumber: 1.0
Ah, from the discussion my impression was that CONFIG_USB=y and
CONFIG_USB_ONBOARD_DEV=m works, but not CONFIG_USB=m and
CONFIG_USB_ONBOARD_DEV=m, good we clarified that.
Is the rootfs by chance on a USB device and that prevents the
onboard_usb_dev module from being loaded?
You could add debug logs to hub_probe(), onboard_dev_init() and
onboard_dev_probe() to get more information.
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 03/17] riscv: vector: Use vlenb from DT
2024-05-03 16:59 0% ` Conor Dooley
@ 2024-05-03 17:15 0% ` Charlie Jenkins
0 siblings, 0 replies; 200+ results
From: Charlie Jenkins @ 2024-05-03 17:15 UTC (permalink / raw)
To: Conor Dooley
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Guo Ren, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Conor Dooley, Evan Green,
Clément Léger, Jonathan Corbet, Shuah Khan,
linux-riscv, devicetree, linux-kernel, Palmer Dabbelt,
linux-arm-kernel, linux-sunxi, linux-doc, linux-kselftest
On Fri, May 03, 2024 at 05:59:33PM +0100, Conor Dooley wrote:
> On Thu, May 02, 2024 at 09:46:38PM -0700, Charlie Jenkins wrote:
> > If vlenb is provided in the device tree, prefer that over reading the
> > vlenb csr.
> >
> > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > ---
> > arch/riscv/include/asm/cpufeature.h | 2 ++
> > arch/riscv/kernel/cpufeature.c | 43 +++++++++++++++++++++++++++++++++++++
> > arch/riscv/kernel/vector.c | 12 ++++++++++-
> > 3 files changed, 56 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> > index 347805446151..0c4f08577015 100644
> > --- a/arch/riscv/include/asm/cpufeature.h
> > +++ b/arch/riscv/include/asm/cpufeature.h
> > @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
> > /* Per-cpu ISA extensions. */
> > extern struct riscv_isainfo hart_isa[NR_CPUS];
> >
> > +extern u32 riscv_vlenb_of;
> > +
> > void riscv_user_isa_enable(void);
> >
> > #if defined(CONFIG_RISCV_MISALIGNED)
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 3ed2359eae35..12c79db0b0bb 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
> > /* Per-cpu ISA extensions. */
> > struct riscv_isainfo hart_isa[NR_CPUS];
> >
> > +u32 riscv_vlenb_of;
> > +
> > /**
> > * riscv_isa_extension_base() - Get base extension word
> > *
> > @@ -648,6 +650,42 @@ static int __init riscv_isa_fallback_setup(char *__unused)
> > early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
> > #endif
> >
> > +static int has_riscv_homogeneous_vlenb(void)
> > +{
> > + int cpu;
> > + u32 prev_vlenb = 0;
> > + u32 vlenb;
> > +
> > + for_each_possible_cpu(cpu) {
> > + struct device_node *cpu_node;
> > +
> > + cpu_node = of_cpu_device_node_get(cpu);
> > + if (!cpu_node) {
> > + pr_warn("Unable to find cpu node\n");
> > + return -ENOENT;
> > + }
> > +
> > + if (of_property_read_u32(cpu_node, "riscv,vlenb", &vlenb)) {
> > + of_node_put(cpu_node);
> > +
> > + if (prev_vlenb)
> > + return -ENOENT;
> > + continue;
> > + }
> > +
> > + if (prev_vlenb && vlenb != prev_vlenb) {
> > + of_node_put(cpu_node);
> > + return -ENOENT;
> > + }
> > +
> > + prev_vlenb = vlenb;
> > + of_node_put(cpu_node);
> > + }
> > +
> > + riscv_vlenb_of = vlenb;
> > + return 0;
> > +}
> > +
> > void __init riscv_fill_hwcap(void)
> > {
> > char print_str[NUM_ALPHA_EXTS + 1];
> > @@ -671,6 +709,11 @@ void __init riscv_fill_hwcap(void)
> > pr_info("Falling back to deprecated \"riscv,isa\"\n");
> > riscv_fill_hwcap_from_isa_string(isa2hwcap);
> > }
> > +
> > + if (elf_hwcap & COMPAT_HWCAP_ISA_V && has_riscv_homogeneous_vlenb() < 0) {
>
> I still think this isn't quite right, as it will emit a warning when
> RISCV_ISA_V is disabled. The simplest thing to do probably is just
> add an `if (IS_ENABLED(CONFIG_RISCV_ISA_V) return 0` shortcut the to
> function? It'll get disabled a few lines later so I think a zero is
> safe.
That seems like a good idea. It is weird to throw a warning about this
even when they have V disabled in the kernel. The DT is improperly
formatted since it has heterogeneous vlenb entries and has V enabled,
but since the user disabled V in the kernel skipping the warning is
reasonable.
- Charlie
>
> > + pr_warn("Unsupported heterogeneous vlen detected, vector extension disabled.\n");
> > + elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
> > + }
> > }
> >
> > /*
> > diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> > index 6727d1d3b8f2..e04586cdb7f0 100644
> > --- a/arch/riscv/kernel/vector.c
> > +++ b/arch/riscv/kernel/vector.c
> > @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void)
> > {
> > unsigned long this_vsize;
> >
> > - /* There are 32 vector registers with vlenb length. */
> > + /*
> > + * There are 32 vector registers with vlenb length.
> > + *
> > + * If the riscv,vlenb property was provided by the firmware, use that
> > + * instead of probing the CSRs.
> > + */
> > + if (riscv_vlenb_of) {
> > + this_vsize = riscv_vlenb_of * 32;
> > + return 0;
> > + }
> > +
> > riscv_v_enable();
> > this_vsize = csr_read(CSR_VLENB) * 32;
> > riscv_v_disable();
> >
> > --
> > 2.44.0
> >
_______________________________________________
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 03/17] riscv: vector: Use vlenb from DT
2024-05-03 4:46 5% ` [PATCH v5 03/17] riscv: vector: Use vlenb from DT Charlie Jenkins
@ 2024-05-03 16:59 0% ` Conor Dooley
2024-05-03 17:15 0% ` Charlie Jenkins
0 siblings, 1 reply; 200+ results
From: Conor Dooley @ 2024-05-03 16:59 UTC (permalink / raw)
To: Charlie Jenkins
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Guo Ren, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Conor Dooley, Evan Green,
Clément Léger, Jonathan Corbet, Shuah Khan,
linux-riscv, devicetree, linux-kernel, Palmer Dabbelt,
linux-arm-kernel, linux-sunxi, linux-doc, linux-kselftest
[-- Attachment #1.1: Type: text/plain, Size: 3915 bytes --]
On Thu, May 02, 2024 at 09:46:38PM -0700, Charlie Jenkins wrote:
> If vlenb is provided in the device tree, prefer that over reading the
> vlenb csr.
>
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> ---
> arch/riscv/include/asm/cpufeature.h | 2 ++
> arch/riscv/kernel/cpufeature.c | 43 +++++++++++++++++++++++++++++++++++++
> arch/riscv/kernel/vector.c | 12 ++++++++++-
> 3 files changed, 56 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 347805446151..0c4f08577015 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
> /* Per-cpu ISA extensions. */
> extern struct riscv_isainfo hart_isa[NR_CPUS];
>
> +extern u32 riscv_vlenb_of;
> +
> void riscv_user_isa_enable(void);
>
> #if defined(CONFIG_RISCV_MISALIGNED)
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 3ed2359eae35..12c79db0b0bb 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
> /* Per-cpu ISA extensions. */
> struct riscv_isainfo hart_isa[NR_CPUS];
>
> +u32 riscv_vlenb_of;
> +
> /**
> * riscv_isa_extension_base() - Get base extension word
> *
> @@ -648,6 +650,42 @@ static int __init riscv_isa_fallback_setup(char *__unused)
> early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
> #endif
>
> +static int has_riscv_homogeneous_vlenb(void)
> +{
> + int cpu;
> + u32 prev_vlenb = 0;
> + u32 vlenb;
> +
> + for_each_possible_cpu(cpu) {
> + struct device_node *cpu_node;
> +
> + cpu_node = of_cpu_device_node_get(cpu);
> + if (!cpu_node) {
> + pr_warn("Unable to find cpu node\n");
> + return -ENOENT;
> + }
> +
> + if (of_property_read_u32(cpu_node, "riscv,vlenb", &vlenb)) {
> + of_node_put(cpu_node);
> +
> + if (prev_vlenb)
> + return -ENOENT;
> + continue;
> + }
> +
> + if (prev_vlenb && vlenb != prev_vlenb) {
> + of_node_put(cpu_node);
> + return -ENOENT;
> + }
> +
> + prev_vlenb = vlenb;
> + of_node_put(cpu_node);
> + }
> +
> + riscv_vlenb_of = vlenb;
> + return 0;
> +}
> +
> void __init riscv_fill_hwcap(void)
> {
> char print_str[NUM_ALPHA_EXTS + 1];
> @@ -671,6 +709,11 @@ void __init riscv_fill_hwcap(void)
> pr_info("Falling back to deprecated \"riscv,isa\"\n");
> riscv_fill_hwcap_from_isa_string(isa2hwcap);
> }
> +
> + if (elf_hwcap & COMPAT_HWCAP_ISA_V && has_riscv_homogeneous_vlenb() < 0) {
I still think this isn't quite right, as it will emit a warning when
RISCV_ISA_V is disabled. The simplest thing to do probably is just
add an `if (IS_ENABLED(CONFIG_RISCV_ISA_V) return 0` shortcut the to
function? It'll get disabled a few lines later so I think a zero is
safe.
> + pr_warn("Unsupported heterogeneous vlen detected, vector extension disabled.\n");
> + elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
> + }
> }
>
> /*
> diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> index 6727d1d3b8f2..e04586cdb7f0 100644
> --- a/arch/riscv/kernel/vector.c
> +++ b/arch/riscv/kernel/vector.c
> @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void)
> {
> unsigned long this_vsize;
>
> - /* There are 32 vector registers with vlenb length. */
> + /*
> + * There are 32 vector registers with vlenb length.
> + *
> + * If the riscv,vlenb property was provided by the firmware, use that
> + * instead of probing the CSRs.
> + */
> + if (riscv_vlenb_of) {
> + this_vsize = riscv_vlenb_of * 32;
> + return 0;
> + }
> +
> riscv_v_enable();
> this_vsize = csr_read(CSR_VLENB) * 32;
> riscv_v_disable();
>
> --
> 2.44.0
>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply [relevance 0%]
* Re: [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: Fix wrong lvts_ctrl index
2024-05-03 15:35 5% ` [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: " Julien Panis
@ 2024-05-03 15:45 0% ` Nicolas Pitre
2024-05-06 7:52 0% ` AngeloGioacchino Del Regno
1 sibling, 0 replies; 200+ results
From: Nicolas Pitre @ 2024-05-03 15:45 UTC (permalink / raw)
To: Julien Panis
Cc: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Matthias Brugger, AngeloGioacchino Del Regno, linux-pm,
linux-kernel, linux-arm-kernel, linux-mediatek
On Fri, 3 May 2024, Julien Panis wrote:
> In 'lvts_should_update_thresh()' and 'lvts_ctrl_start()' functions,
> the parameter passed to 'lvts_for_each_valid_sensor()' macro is always
> 'lvts_ctrl->lvts_data->lvts_ctrl'. In other words, the array index 0
> is systematically passed as 'struct lvts_ctrl_data' type item, even
> when another item should be consumed instead.
>
> Hence, the 'valid_sensor_mask' value which is selected can be wrong
> because unrelated to the 'struct lvts_ctrl_data' type item that should
> be used. Hence, some thermal zone can be registered for a sensor 'i'
> that does not actually exist. Because of the invalid address used
> as 'lvts_sensor[i].msr', this situation ends up with a crash in
> 'lvts_get_temp()' function, where this 'msr' pointer is passed to
> 'readl_poll_timeout()' function. The following message is output:
> "Unable to handle kernel NULL pointer dereference at virtual
> address <msr>", with <msr> = 0.
>
> This patch fixes the issue.
>
> Fixes: 11e6f4c31447 ("thermal/drivers/mediatek/lvts_thermal: Allow early empty sensor slots")
> Signed-off-by: Julien Panis <jpanis@baylibre.com>
Reviewed-by: Nicolas Pitre <npitre@baylibre.com>
> ---
> drivers/thermal/mediatek/lvts_thermal.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
> index 18a796386cd0..d7df6f09938b 100644
> --- a/drivers/thermal/mediatek/lvts_thermal.c
> +++ b/drivers/thermal/mediatek/lvts_thermal.c
> @@ -116,9 +116,9 @@ struct lvts_ctrl_data {
> ((s2) ? BIT(2) : 0) | \
> ((s3) ? BIT(3) : 0))
>
> -#define lvts_for_each_valid_sensor(i, lvts_ctrl_data) \
> +#define lvts_for_each_valid_sensor(i, lvts_ctrl) \
> for ((i) = 0; (i) < LVTS_SENSOR_MAX; (i)++) \
> - if (!((lvts_ctrl_data)->valid_sensor_mask & BIT(i))) \
> + if (!((lvts_ctrl)->valid_sensor_mask & BIT(i))) \
> continue; \
> else
>
> @@ -145,6 +145,7 @@ struct lvts_ctrl {
> const struct lvts_data *lvts_data;
> u32 calibration[LVTS_SENSOR_MAX];
> u32 hw_tshut_raw_temp;
> + u8 valid_sensor_mask;
> int mode;
> void __iomem *base;
> int low_thresh;
> @@ -356,7 +357,7 @@ static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high)
> if (high > lvts_ctrl->high_thresh)
> return true;
>
> - lvts_for_each_valid_sensor(i, lvts_ctrl->lvts_data->lvts_ctrl)
> + lvts_for_each_valid_sensor(i, lvts_ctrl)
> if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
> && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
> return false;
> @@ -617,6 +618,8 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
> lvts_sensor[i].high_thresh = INT_MIN;
> };
>
> + lvts_ctrl->valid_sensor_mask = lvts_ctrl_data->valid_sensor_mask;
> +
> return 0;
> }
>
> @@ -1112,7 +1115,7 @@ static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl)
> u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ?
> sensor_imm_bitmap : sensor_filt_bitmap;
>
> - lvts_for_each_valid_sensor(i, lvts_ctrl->lvts_data->lvts_ctrl) {
> + lvts_for_each_valid_sensor(i, lvts_ctrl) {
>
> int dt_id = lvts_sensors[i].dt_id;
>
>
> --
> 2.37.3
>
>
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^ permalink raw reply [relevance 0%]
* [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: Fix wrong lvts_ctrl index
@ 2024-05-03 15:35 5% ` Julien Panis
2024-05-03 15:45 0% ` Nicolas Pitre
2024-05-06 7:52 0% ` AngeloGioacchino Del Regno
0 siblings, 2 replies; 200+ results
From: Julien Panis @ 2024-05-03 15:35 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Matthias Brugger, AngeloGioacchino Del Regno, Nicolas Pitre
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek, Julien Panis
In 'lvts_should_update_thresh()' and 'lvts_ctrl_start()' functions,
the parameter passed to 'lvts_for_each_valid_sensor()' macro is always
'lvts_ctrl->lvts_data->lvts_ctrl'. In other words, the array index 0
is systematically passed as 'struct lvts_ctrl_data' type item, even
when another item should be consumed instead.
Hence, the 'valid_sensor_mask' value which is selected can be wrong
because unrelated to the 'struct lvts_ctrl_data' type item that should
be used. Hence, some thermal zone can be registered for a sensor 'i'
that does not actually exist. Because of the invalid address used
as 'lvts_sensor[i].msr', this situation ends up with a crash in
'lvts_get_temp()' function, where this 'msr' pointer is passed to
'readl_poll_timeout()' function. The following message is output:
"Unable to handle kernel NULL pointer dereference at virtual
address <msr>", with <msr> = 0.
This patch fixes the issue.
Fixes: 11e6f4c31447 ("thermal/drivers/mediatek/lvts_thermal: Allow early empty sensor slots")
Signed-off-by: Julien Panis <jpanis@baylibre.com>
---
drivers/thermal/mediatek/lvts_thermal.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index 18a796386cd0..d7df6f09938b 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -116,9 +116,9 @@ struct lvts_ctrl_data {
((s2) ? BIT(2) : 0) | \
((s3) ? BIT(3) : 0))
-#define lvts_for_each_valid_sensor(i, lvts_ctrl_data) \
+#define lvts_for_each_valid_sensor(i, lvts_ctrl) \
for ((i) = 0; (i) < LVTS_SENSOR_MAX; (i)++) \
- if (!((lvts_ctrl_data)->valid_sensor_mask & BIT(i))) \
+ if (!((lvts_ctrl)->valid_sensor_mask & BIT(i))) \
continue; \
else
@@ -145,6 +145,7 @@ struct lvts_ctrl {
const struct lvts_data *lvts_data;
u32 calibration[LVTS_SENSOR_MAX];
u32 hw_tshut_raw_temp;
+ u8 valid_sensor_mask;
int mode;
void __iomem *base;
int low_thresh;
@@ -356,7 +357,7 @@ static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high)
if (high > lvts_ctrl->high_thresh)
return true;
- lvts_for_each_valid_sensor(i, lvts_ctrl->lvts_data->lvts_ctrl)
+ lvts_for_each_valid_sensor(i, lvts_ctrl)
if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
&& lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
return false;
@@ -617,6 +618,8 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
lvts_sensor[i].high_thresh = INT_MIN;
};
+ lvts_ctrl->valid_sensor_mask = lvts_ctrl_data->valid_sensor_mask;
+
return 0;
}
@@ -1112,7 +1115,7 @@ static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl)
u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ?
sensor_imm_bitmap : sensor_filt_bitmap;
- lvts_for_each_valid_sensor(i, lvts_ctrl->lvts_data->lvts_ctrl) {
+ lvts_for_each_valid_sensor(i, lvts_ctrl) {
int dt_id = lvts_sensors[i].dt_id;
--
2.37.3
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^ permalink raw reply related [relevance 5%]
* Re: [PATCH v7 00/16] mm: jit/text allocator
2024-05-03 6:28 0% ` Mike Rapoport
@ 2024-05-03 10:40 0% ` Liviu Dudau
0 siblings, 0 replies; 200+ results
From: Liviu Dudau @ 2024-05-03 10:40 UTC (permalink / raw)
To: Mike Rapoport
Cc: Luis Chamberlain, linux-kernel, Alexandre Ghiti, Andrew Morton,
Björn Töpel, Catalin Marinas, Christophe Leroy,
David S. Miller, Dinh Nguyen, Donald Dutile, Eric Chanudet,
Heiko Carstens, Helge Deller, Huacai Chen, Kent Overstreet,
Mark Rutland, Masami Hiramatsu, Michael Ellerman, Nadav Amit,
Palmer Dabbelt, Peter Zijlstra, Philippe Mathieu-Daudé,
Rick Edgecombe, Russell King, Sam Ravnborg, Song Liu,
Steven Rostedt, Thomas Bogendoerfer, Thomas Gleixner,
Will Deacon, bpf, linux-arch, linux-arm-kernel, linux-mips,
linux-mm, linux-modules, linux-parisc, linux-riscv, linux-s390,
linux-trace-kernel, linuxppc-dev, loongarch, netdev, sparclinux,
x86
On Fri, May 03, 2024 at 09:28:25AM +0300, Mike Rapoport wrote:
> On Fri, May 03, 2024 at 01:23:30AM +0100, Liviu Dudau wrote:
> > On Thu, May 02, 2024 at 04:07:05PM -0700, Luis Chamberlain wrote:
> > > On Thu, May 02, 2024 at 11:50:36PM +0100, Liviu Dudau wrote:
> > > > On Mon, Apr 29, 2024 at 09:29:20AM -0700, Luis Chamberlain wrote:
> > > > > On Mon, Apr 29, 2024 at 03:16:04PM +0300, Mike Rapoport wrote:
> > > > > > From: "Mike Rapoport (IBM)" <rppt@kernel.org>
> > > > > >
> > > > > > Hi,
> > > > > >
> > > > > > The patches are also available in git:
> > > > > > https://git.kernel.org/pub/scm/linux/kernel/git/rppt/linux.git/log/?h=execmem/v7
> > > > > >
> > > > > > v7 changes:
> > > > > > * define MODULE_{VADDR,END} for riscv32 to fix the build and avoid
> > > > > > #ifdefs in a function body
> > > > > > * add Acks, thanks everybody
> > > > >
> > > > > Thanks, I've pushed this to modules-next for further exposure / testing.
> > > > > Given the status of testing so far with prior revisions, in that only a
> > > > > few issues were found and that those were fixed, and the status of
> > > > > reviews, this just might be ripe for v6.10.
> > > >
> > > > Looks like there is still some work needed. I've picked up next-20240501
> > > > and on arch/mips with CONFIG_MODULE_COMPRESS_XZ=y and CONFIG_MODULE_DECOMPRESS=y
> > > > I fail to load any module:
> > > >
> > > > # modprobe rfkill
> > > > [11746.539090] Invalid ELF header magic: != ELF
> > > > [11746.587149] execmem: unable to allocate memory
> > > > modprobe: can't load module rfkill (kernel/net/rfkill/rfkill.ko.xz): Out of memory
> > > >
> > > > The (hopefully) relevant parts of my .config:
> > >
> > > Thanks for the report! Any chance we can get you to try a bisection? I
> > > think it should take 2-3 test boots. To help reduce scope you try modules-next:
> > >
> > > https://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git/log/?h=modules-next
> > >
> > > Then can you check by resetting your tree to commmit 3fbe6c2f820a76 (mm:
> > > introduce execmem_alloc() and execmem_free()"). I suspect that should
> > > boot, so your bad commit would be the tip 3c2c250cb3a5fbb ("bpf: remove
> > > CONFIG_BPF_JIT dependency on CONFIG_MODULES of").
> > >
> > > That gives us only a few commits to bisect:
> > >
> > > git log --oneline 3fbe6c2f820a76bc36d5546bda85832f57c8fce2..
> > > 3c2c250cb3a5 (HEAD -> modules-next, korg/modules-next) bpf: remove CONFIG_BPF_JIT dependency on CONFIG_MODULES of
> > > 11e8e65cce5c kprobes: remove dependency on CONFIG_MODULES
> > > e10cbc38697b powerpc: use CONFIG_EXECMEM instead of CONFIG_MODULES where appropriate
> > > 4da3d38f24c5 x86/ftrace: enable dynamic ftrace without CONFIG_MODULES
> > > 13ae3d74ee70 arch: make execmem setup available regardless of CONFIG_MODULES
> > > 460bbbc70a47 powerpc: extend execmem_params for kprobes allocations
> > > e1a14069b5b4 arm64: extend execmem_info for generated code allocations
> > > 971e181c6585 riscv: extend execmem_params for generated code allocations
> > > 0fa276f26721 mm/execmem, arch: convert remaining overrides of module_alloc to execmem
> > > 022cef244287 mm/execmem, arch: convert simple overrides of module_alloc to execmem
> > >
> > > With 2-3 boots we should be to tell which is the bad commit.
> >
> > Looks like 0fa276f26721 is the first bad commit.
> >
> > $ git bisect log
> > # bad: [3c2c250cb3a5fbbccc4a4ff4c9354c54af91f02c] bpf: remove CONFIG_BPF_JIT dependency on CONFIG_MODULES of
> > # good: [3fbe6c2f820a76bc36d5546bda85832f57c8fce2] mm: introduce execmem_alloc() and execmem_free()
> > git bisect start '3c2c250cb3a5' '3fbe6c2f820a76'
> > # bad: [460bbbc70a47e929b1936ca68979f3b79f168fc6] powerpc: extend execmem_params for kprobes allocations
> > git bisect bad 460bbbc70a47e929b1936ca68979f3b79f168fc6
> > # bad: [0fa276f26721e0ffc2ae9c7cf67dcc005b43c67e] mm/execmem, arch: convert remaining overrides of module_alloc to execmem
> > git bisect bad 0fa276f26721e0ffc2ae9c7cf67dcc005b43c67e
> > # good: [022cef2442870db738a366d3b7a636040c081859] mm/execmem, arch: convert simple overrides of module_alloc to execmem
> > git bisect good 022cef2442870db738a366d3b7a636040c081859
> > # first bad commit: [0fa276f26721e0ffc2ae9c7cf67dcc005b43c67e] mm/execmem, arch: convert remaining overrides of module_alloc to execmem
> >
> > Maybe MIPS also needs a ARCH_WANTS_EXECMEM_LATE?
>
> I don't think so. It rather seems there's a bug in the initialization of
> the defaults in execmem. This should fix it:
>
> diff --git a/mm/execmem.c b/mm/execmem.c
> index f6dc3fabc1ca..0c4b36bc6d10 100644
> --- a/mm/execmem.c
> +++ b/mm/execmem.c
> @@ -118,7 +118,6 @@ static void __init __execmem_init(void)
> info->ranges[EXECMEM_DEFAULT].end = VMALLOC_END;
> info->ranges[EXECMEM_DEFAULT].pgprot = PAGE_KERNEL_EXEC;
> info->ranges[EXECMEM_DEFAULT].alignment = 1;
> - return;
> }
>
> if (!execmem_validate(info))
>
That does, indeed, fix the issue!
You can add my Tested-by when you submit the patch.
Best regards,
Liviu
>
> --
> Sincerely yours,
> Mike.
>
--
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
-- John D. Clark, Ignition!
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 2/2] pinctrl: samsung: support a bus clock
2024-05-02 10:41 0% ` André Draszik
@ 2024-05-03 9:13 0% ` Krzysztof Kozlowski
0 siblings, 0 replies; 200+ results
From: Krzysztof Kozlowski @ 2024-05-03 9:13 UTC (permalink / raw)
To: André Draszik, Tudor Ambarus, Sylwester Nawrocki,
Alim Akhtar, Linus Walleij, Rob Herring, Conor Dooley,
Tomasz Figa, Peter Griffin
Cc: Will McVicker, Sam Protsenko, kernel-team, linux-arm-kernel,
linux-samsung-soc, linux-gpio, devicetree, linux-kernel
On 02/05/2024 12:41, André Draszik wrote:
> On Thu, 2024-05-02 at 09:46 +0200, Krzysztof Kozlowski wrote:
>> On 02/05/2024 09:41, Tudor Ambarus wrote:
>>>>
>>>> @@ -223,6 +268,13 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
>>>> shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
>>>> mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
>>>>
>>>> + if (clk_enable(bank->drvdata->pclk)) {
>>>> + dev_err(bank->gpio_chip.parent,
>>>> + "unable to enable clock for deconfiguring pin %s-%lu\n",
>>>> + bank->name, irqd->hwirq);
>>>> + return;
>>>
>>> but here we just print an error. I guess that for consistency reasons it
>>> would be good to follow up with a patch and change the return types of
>>> these methods and return the error too when the clock enable fails.
>>
>> That's a release, so usually void callback. The true issue is that we
>> expect release to always succeed, I think.
>>
>> This points to issue with this patchset: looks like some patchwork all
>> around the places having register accesses. But how do you even expect
>> interrupts and pins to work if entire pinctrl block is clock gated?
>
> I was initially thinking the same, but the clock seems to be required for
> register access only, interrupts are still being received and triggered
> with pclk turned off as per my testing.
Probably we could simplify this all and keep the clock enabled always,
when device is not suspended. Toggling clock on/off for every pin change
is also an overhead. Anyway, I merged the patches for now, because it
addresses real problem and seems like one of reasonable solutions.
Best regards,
Krzysztof
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^ permalink raw reply [relevance 0%]
* [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H616
@ 2024-05-03 9:09 4% Dragan Simic
2024-05-08 11:05 0% ` Andre Przywara
2024-05-28 16:08 0% ` Chen-Yu Tsai
0 siblings, 2 replies; 200+ results
From: Dragan Simic @ 2024-05-03 9:09 UTC (permalink / raw)
To: linux-sunxi
Cc: wens, jernej.skrabec, samuel, linux-arm-kernel, devicetree, robh,
krzk+dt, conor+dt, linux-kernel, Andre Przywara
Add missing cache information to the Allwinner H616 SoC dtsi, to allow
the userspace, which includes lscpu(1) that uses the virtual files provided
by the kernel under the /sys/devices/system/cpu directory, to display the
proper H616 cache information.
Adding the cache information to the H616 SoC dtsi also makes the following
warning message in the kernel log go away:
cacheinfo: Unable to detect cache hierarchy for CPU 0
Rather conspicuously, almost no cache-related information is available in
the publicly available Allwinner H616 datasheet (version 1.0) and H616 user
manual (version 1.0). Thus, the cache parameters for the H616 SoC dtsi were
obtained and derived by hand from the cache size and layout specifications
found in the following technical reference manual, and from the cache size
and die revision hints available from the following community-provided data
and memory subsystem benchmarks:
- ARM Cortex-A53 revision r0p4 TRM, version J
- Summary of the two available H616 die revisions and their differences
in cache sizes observed from the CSSIDR_EL1 register readouts, provided
by Andre Przywara [1][2]
- Tinymembench benchmark results of the H616-based OrangePi Zero 2 SBC,
provided by Thomas Kaiser [3]
For future reference, here's a brief summary of the available documentation
and the community-provided data and memory subsystem benchmarks:
- All caches employ the 64-byte cache line length
- Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction
cache and 32 KB of L1 4-way, set-associative data cache
- The size of the L2 cache depends on the actual H616 die revision (there
are two die revisions), so the entire SoC can have either 256 KB or 1 MB
of unified L2 16-way, set-associative cache [1]
Also for future reference, here's the relevant excerpt from the community-
provided H616 memory subsystem benchmark, [3] which confirms that 32 KB and
256 KB are the L1 data and L2 cache sizes, respectively:
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.3 ns / 7.3 ns
131072 : 6.6 ns / 10.5 ns
262144 : 9.8 ns / 15.2 ns
524288 : 91.8 ns / 142.9 ns
1048576 : 138.6 ns / 188.3 ns
2097152 : 163.0 ns / 204.8 ns
4194304 : 178.8 ns / 213.5 ns
8388608 : 187.1 ns / 217.9 ns
16777216 : 192.2 ns / 220.9 ns
33554432 : 196.5 ns / 224.0 ns
67108864 : 215.7 ns / 259.5 ns
The changes introduced to the H616 SoC dtsi by this patch specify 256 KB as
the L2 cache size. As outlined by Andre Przywara, [2] a follow-up TF-A patch
will perform runtime adjustment of the device tree data, making the correct
L2 cache size of 1 MB present in the device tree for the boards based on the
revision of H616 that actually provides 1 MB of L2 cache.
[1] https://lore.kernel.org/linux-sunxi/20240430114627.0cfcd14a@donnerap.manchester.arm.com/
[2] https://lore.kernel.org/linux-sunxi/20240501103059.10a8f7de@donnerap.manchester.arm.com/
[3] https://raw.githubusercontent.com/ThomasKaiser/sbc-bench/master/results/4knM.txt
Suggested-by: Andre Przywara <andre.przywara@arm.com>
Helped-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index b2e85e52d1a1..4faed88d8909 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -26,30 +26,67 @@ cpu0: cpu@0 {
reg = <0>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
};
};
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^ permalink raw reply related [relevance 4%]
* Re: [PATCH v7 00/16] mm: jit/text allocator
2024-05-03 0:23 0% ` Liviu Dudau
@ 2024-05-03 6:28 0% ` Mike Rapoport
2024-05-03 10:40 0% ` Liviu Dudau
0 siblings, 1 reply; 200+ results
From: Mike Rapoport @ 2024-05-03 6:28 UTC (permalink / raw)
To: Liviu Dudau
Cc: Luis Chamberlain, linux-kernel, Alexandre Ghiti, Andrew Morton,
Björn Töpel, Catalin Marinas, Christophe Leroy,
David S. Miller, Dinh Nguyen, Donald Dutile, Eric Chanudet,
Heiko Carstens, Helge Deller, Huacai Chen, Kent Overstreet,
Mark Rutland, Masami Hiramatsu, Michael Ellerman, Nadav Amit,
Palmer Dabbelt, Peter Zijlstra, Philippe Mathieu-Daudé,
Rick Edgecombe, Russell King, Sam Ravnborg, Song Liu,
Steven Rostedt, Thomas Bogendoerfer, Thomas Gleixner,
Will Deacon, bpf, linux-arch, linux-arm-kernel, linux-mips,
linux-mm, linux-modules, linux-parisc, linux-riscv, linux-s390,
linux-trace-kernel, linuxppc-dev, loongarch, netdev, sparclinux,
x86
On Fri, May 03, 2024 at 01:23:30AM +0100, Liviu Dudau wrote:
> On Thu, May 02, 2024 at 04:07:05PM -0700, Luis Chamberlain wrote:
> > On Thu, May 02, 2024 at 11:50:36PM +0100, Liviu Dudau wrote:
> > > On Mon, Apr 29, 2024 at 09:29:20AM -0700, Luis Chamberlain wrote:
> > > > On Mon, Apr 29, 2024 at 03:16:04PM +0300, Mike Rapoport wrote:
> > > > > From: "Mike Rapoport (IBM)" <rppt@kernel.org>
> > > > >
> > > > > Hi,
> > > > >
> > > > > The patches are also available in git:
> > > > > https://git.kernel.org/pub/scm/linux/kernel/git/rppt/linux.git/log/?h=execmem/v7
> > > > >
> > > > > v7 changes:
> > > > > * define MODULE_{VADDR,END} for riscv32 to fix the build and avoid
> > > > > #ifdefs in a function body
> > > > > * add Acks, thanks everybody
> > > >
> > > > Thanks, I've pushed this to modules-next for further exposure / testing.
> > > > Given the status of testing so far with prior revisions, in that only a
> > > > few issues were found and that those were fixed, and the status of
> > > > reviews, this just might be ripe for v6.10.
> > >
> > > Looks like there is still some work needed. I've picked up next-20240501
> > > and on arch/mips with CONFIG_MODULE_COMPRESS_XZ=y and CONFIG_MODULE_DECOMPRESS=y
> > > I fail to load any module:
> > >
> > > # modprobe rfkill
> > > [11746.539090] Invalid ELF header magic: != ELF
> > > [11746.587149] execmem: unable to allocate memory
> > > modprobe: can't load module rfkill (kernel/net/rfkill/rfkill.ko.xz): Out of memory
> > >
> > > The (hopefully) relevant parts of my .config:
> >
> > Thanks for the report! Any chance we can get you to try a bisection? I
> > think it should take 2-3 test boots. To help reduce scope you try modules-next:
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git/log/?h=modules-next
> >
> > Then can you check by resetting your tree to commmit 3fbe6c2f820a76 (mm:
> > introduce execmem_alloc() and execmem_free()"). I suspect that should
> > boot, so your bad commit would be the tip 3c2c250cb3a5fbb ("bpf: remove
> > CONFIG_BPF_JIT dependency on CONFIG_MODULES of").
> >
> > That gives us only a few commits to bisect:
> >
> > git log --oneline 3fbe6c2f820a76bc36d5546bda85832f57c8fce2..
> > 3c2c250cb3a5 (HEAD -> modules-next, korg/modules-next) bpf: remove CONFIG_BPF_JIT dependency on CONFIG_MODULES of
> > 11e8e65cce5c kprobes: remove dependency on CONFIG_MODULES
> > e10cbc38697b powerpc: use CONFIG_EXECMEM instead of CONFIG_MODULES where appropriate
> > 4da3d38f24c5 x86/ftrace: enable dynamic ftrace without CONFIG_MODULES
> > 13ae3d74ee70 arch: make execmem setup available regardless of CONFIG_MODULES
> > 460bbbc70a47 powerpc: extend execmem_params for kprobes allocations
> > e1a14069b5b4 arm64: extend execmem_info for generated code allocations
> > 971e181c6585 riscv: extend execmem_params for generated code allocations
> > 0fa276f26721 mm/execmem, arch: convert remaining overrides of module_alloc to execmem
> > 022cef244287 mm/execmem, arch: convert simple overrides of module_alloc to execmem
> >
> > With 2-3 boots we should be to tell which is the bad commit.
>
> Looks like 0fa276f26721 is the first bad commit.
>
> $ git bisect log
> # bad: [3c2c250cb3a5fbbccc4a4ff4c9354c54af91f02c] bpf: remove CONFIG_BPF_JIT dependency on CONFIG_MODULES of
> # good: [3fbe6c2f820a76bc36d5546bda85832f57c8fce2] mm: introduce execmem_alloc() and execmem_free()
> git bisect start '3c2c250cb3a5' '3fbe6c2f820a76'
> # bad: [460bbbc70a47e929b1936ca68979f3b79f168fc6] powerpc: extend execmem_params for kprobes allocations
> git bisect bad 460bbbc70a47e929b1936ca68979f3b79f168fc6
> # bad: [0fa276f26721e0ffc2ae9c7cf67dcc005b43c67e] mm/execmem, arch: convert remaining overrides of module_alloc to execmem
> git bisect bad 0fa276f26721e0ffc2ae9c7cf67dcc005b43c67e
> # good: [022cef2442870db738a366d3b7a636040c081859] mm/execmem, arch: convert simple overrides of module_alloc to execmem
> git bisect good 022cef2442870db738a366d3b7a636040c081859
> # first bad commit: [0fa276f26721e0ffc2ae9c7cf67dcc005b43c67e] mm/execmem, arch: convert remaining overrides of module_alloc to execmem
>
> Maybe MIPS also needs a ARCH_WANTS_EXECMEM_LATE?
I don't think so. It rather seems there's a bug in the initialization of
the defaults in execmem. This should fix it:
diff --git a/mm/execmem.c b/mm/execmem.c
index f6dc3fabc1ca..0c4b36bc6d10 100644
--- a/mm/execmem.c
+++ b/mm/execmem.c
@@ -118,7 +118,6 @@ static void __init __execmem_init(void)
info->ranges[EXECMEM_DEFAULT].end = VMALLOC_END;
info->ranges[EXECMEM_DEFAULT].pgprot = PAGE_KERNEL_EXEC;
info->ranges[EXECMEM_DEFAULT].alignment = 1;
- return;
}
if (!execmem_validate(info))
> Best regards,
> Liviu
--
Sincerely yours,
Mike.
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 0%]
* [PATCH v5 03/17] riscv: vector: Use vlenb from DT
@ 2024-05-03 4:46 5% ` Charlie Jenkins
2024-05-03 16:59 0% ` Conor Dooley
0 siblings, 1 reply; 200+ results
From: Charlie Jenkins @ 2024-05-03 4:46 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Guo Ren, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Conor Dooley, Evan Green,
Clément Léger, Jonathan Corbet, Shuah Khan
Cc: linux-riscv, devicetree, linux-kernel, Palmer Dabbelt,
linux-arm-kernel, linux-sunxi, linux-doc, linux-kselftest,
Charlie Jenkins
If vlenb is provided in the device tree, prefer that over reading the
vlenb csr.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
arch/riscv/include/asm/cpufeature.h | 2 ++
arch/riscv/kernel/cpufeature.c | 43 +++++++++++++++++++++++++++++++++++++
arch/riscv/kernel/vector.c | 12 ++++++++++-
3 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 347805446151..0c4f08577015 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
/* Per-cpu ISA extensions. */
extern struct riscv_isainfo hart_isa[NR_CPUS];
+extern u32 riscv_vlenb_of;
+
void riscv_user_isa_enable(void);
#if defined(CONFIG_RISCV_MISALIGNED)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3ed2359eae35..12c79db0b0bb 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
/* Per-cpu ISA extensions. */
struct riscv_isainfo hart_isa[NR_CPUS];
+u32 riscv_vlenb_of;
+
/**
* riscv_isa_extension_base() - Get base extension word
*
@@ -648,6 +650,42 @@ static int __init riscv_isa_fallback_setup(char *__unused)
early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
#endif
+static int has_riscv_homogeneous_vlenb(void)
+{
+ int cpu;
+ u32 prev_vlenb = 0;
+ u32 vlenb;
+
+ for_each_possible_cpu(cpu) {
+ struct device_node *cpu_node;
+
+ cpu_node = of_cpu_device_node_get(cpu);
+ if (!cpu_node) {
+ pr_warn("Unable to find cpu node\n");
+ return -ENOENT;
+ }
+
+ if (of_property_read_u32(cpu_node, "riscv,vlenb", &vlenb)) {
+ of_node_put(cpu_node);
+
+ if (prev_vlenb)
+ return -ENOENT;
+ continue;
+ }
+
+ if (prev_vlenb && vlenb != prev_vlenb) {
+ of_node_put(cpu_node);
+ return -ENOENT;
+ }
+
+ prev_vlenb = vlenb;
+ of_node_put(cpu_node);
+ }
+
+ riscv_vlenb_of = vlenb;
+ return 0;
+}
+
void __init riscv_fill_hwcap(void)
{
char print_str[NUM_ALPHA_EXTS + 1];
@@ -671,6 +709,11 @@ void __init riscv_fill_hwcap(void)
pr_info("Falling back to deprecated \"riscv,isa\"\n");
riscv_fill_hwcap_from_isa_string(isa2hwcap);
}
+
+ if (elf_hwcap & COMPAT_HWCAP_ISA_V && has_riscv_homogeneous_vlenb() < 0) {
+ pr_warn("Unsupported heterogeneous vlen detected, vector extension disabled.\n");
+ elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
+ }
}
/*
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index 6727d1d3b8f2..e04586cdb7f0 100644
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void)
{
unsigned long this_vsize;
- /* There are 32 vector registers with vlenb length. */
+ /*
+ * There are 32 vector registers with vlenb length.
+ *
+ * If the riscv,vlenb property was provided by the firmware, use that
+ * instead of probing the CSRs.
+ */
+ if (riscv_vlenb_of) {
+ this_vsize = riscv_vlenb_of * 32;
+ return 0;
+ }
+
riscv_v_enable();
this_vsize = csr_read(CSR_VLENB) * 32;
riscv_v_disable();
--
2.44.0
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^ permalink raw reply related [relevance 5%]
* Re: [PATCH v7 00/16] mm: jit/text allocator
2024-05-02 23:07 0% ` Luis Chamberlain
@ 2024-05-03 0:23 0% ` Liviu Dudau
2024-05-03 6:28 0% ` Mike Rapoport
0 siblings, 1 reply; 200+ results
From: Liviu Dudau @ 2024-05-03 0:23 UTC (permalink / raw)
To: Luis Chamberlain
Cc: Mike Rapoport, linux-kernel, Alexandre Ghiti, Andrew Morton,
Björn Töpel, Catalin Marinas, Christophe Leroy,
David S. Miller, Dinh Nguyen, Donald Dutile, Eric Chanudet,
Heiko Carstens, Helge Deller, Huacai Chen, Kent Overstreet,
Mark Rutland, Masami Hiramatsu, Michael Ellerman, Nadav Amit,
Palmer Dabbelt, Peter Zijlstra, Philippe Mathieu-Daudé,
Rick Edgecombe, Russell King, Sam Ravnborg, Song Liu,
Steven Rostedt, Thomas Bogendoerfer, Thomas Gleixner,
Will Deacon, bpf, linux-arch, linux-arm-kernel, linux-mips,
linux-mm, linux-modules, linux-parisc, linux-riscv, linux-s390,
linux-trace-kernel, linuxppc-dev, loongarch, netdev, sparclinux,
x86
On Thu, May 02, 2024 at 04:07:05PM -0700, Luis Chamberlain wrote:
> On Thu, May 02, 2024 at 11:50:36PM +0100, Liviu Dudau wrote:
> > On Mon, Apr 29, 2024 at 09:29:20AM -0700, Luis Chamberlain wrote:
> > > On Mon, Apr 29, 2024 at 03:16:04PM +0300, Mike Rapoport wrote:
> > > > From: "Mike Rapoport (IBM)" <rppt@kernel.org>
> > > >
> > > > Hi,
> > > >
> > > > The patches are also available in git:
> > > > https://git.kernel.org/pub/scm/linux/kernel/git/rppt/linux.git/log/?h=execmem/v7
> > > >
> > > > v7 changes:
> > > > * define MODULE_{VADDR,END} for riscv32 to fix the build and avoid
> > > > #ifdefs in a function body
> > > > * add Acks, thanks everybody
> > >
> > > Thanks, I've pushed this to modules-next for further exposure / testing.
> > > Given the status of testing so far with prior revisions, in that only a
> > > few issues were found and that those were fixed, and the status of
> > > reviews, this just might be ripe for v6.10.
> >
> > Looks like there is still some work needed. I've picked up next-20240501
> > and on arch/mips with CONFIG_MODULE_COMPRESS_XZ=y and CONFIG_MODULE_DECOMPRESS=y
> > I fail to load any module:
> >
> > # modprobe rfkill
> > [11746.539090] Invalid ELF header magic: != ELF
> > [11746.587149] execmem: unable to allocate memory
> > modprobe: can't load module rfkill (kernel/net/rfkill/rfkill.ko.xz): Out of memory
> >
> > The (hopefully) relevant parts of my .config:
>
> Thanks for the report! Any chance we can get you to try a bisection? I
> think it should take 2-3 test boots. To help reduce scope you try modules-next:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git/log/?h=modules-next
>
> Then can you check by resetting your tree to commmit 3fbe6c2f820a76 (mm:
> introduce execmem_alloc() and execmem_free()"). I suspect that should
> boot, so your bad commit would be the tip 3c2c250cb3a5fbb ("bpf: remove
> CONFIG_BPF_JIT dependency on CONFIG_MODULES of").
>
> That gives us only a few commits to bisect:
>
> git log --oneline 3fbe6c2f820a76bc36d5546bda85832f57c8fce2..
> 3c2c250cb3a5 (HEAD -> modules-next, korg/modules-next) bpf: remove CONFIG_BPF_JIT dependency on CONFIG_MODULES of
> 11e8e65cce5c kprobes: remove dependency on CONFIG_MODULES
> e10cbc38697b powerpc: use CONFIG_EXECMEM instead of CONFIG_MODULES where appropriate
> 4da3d38f24c5 x86/ftrace: enable dynamic ftrace without CONFIG_MODULES
> 13ae3d74ee70 arch: make execmem setup available regardless of CONFIG_MODULES
> 460bbbc70a47 powerpc: extend execmem_params for kprobes allocations
> e1a14069b5b4 arm64: extend execmem_info for generated code allocations
> 971e181c6585 riscv: extend execmem_params for generated code allocations
> 0fa276f26721 mm/execmem, arch: convert remaining overrides of module_alloc to execmem
> 022cef244287 mm/execmem, arch: convert simple overrides of module_alloc to execmem
>
> With 2-3 boots we should be to tell which is the bad commit.
Looks like 0fa276f26721 is the first bad commit.
$ git bisect log
# bad: [3c2c250cb3a5fbbccc4a4ff4c9354c54af91f02c] bpf: remove CONFIG_BPF_JIT dependency on CONFIG_MODULES of
# good: [3fbe6c2f820a76bc36d5546bda85832f57c8fce2] mm: introduce execmem_alloc() and execmem_free()
git bisect start '3c2c250cb3a5' '3fbe6c2f820a76'
# bad: [460bbbc70a47e929b1936ca68979f3b79f168fc6] powerpc: extend execmem_params for kprobes allocations
git bisect bad 460bbbc70a47e929b1936ca68979f3b79f168fc6
# bad: [0fa276f26721e0ffc2ae9c7cf67dcc005b43c67e] mm/execmem, arch: convert remaining overrides of module_alloc to execmem
git bisect bad 0fa276f26721e0ffc2ae9c7cf67dcc005b43c67e
# good: [022cef2442870db738a366d3b7a636040c081859] mm/execmem, arch: convert simple overrides of module_alloc to execmem
git bisect good 022cef2442870db738a366d3b7a636040c081859
# first bad commit: [0fa276f26721e0ffc2ae9c7cf67dcc005b43c67e] mm/execmem, arch: convert remaining overrides of module_alloc to execmem
Maybe MIPS also needs a ARCH_WANTS_EXECMEM_LATE?
Best regards,
Liviu
>
> Luis
>
--
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
-- John D. Clark, Ignition!
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v7 00/16] mm: jit/text allocator
2024-05-02 22:50 5% ` Liviu Dudau
@ 2024-05-02 23:07 0% ` Luis Chamberlain
2024-05-03 0:23 0% ` Liviu Dudau
0 siblings, 1 reply; 200+ results
From: Luis Chamberlain @ 2024-05-02 23:07 UTC (permalink / raw)
To: Liviu Dudau
Cc: Mike Rapoport, linux-kernel, Alexandre Ghiti, Andrew Morton,
Björn Töpel, Catalin Marinas, Christophe Leroy,
David S. Miller, Dinh Nguyen, Donald Dutile, Eric Chanudet,
Heiko Carstens, Helge Deller, Huacai Chen, Kent Overstreet,
Mark Rutland, Masami Hiramatsu, Michael Ellerman, Nadav Amit,
Palmer Dabbelt, Peter Zijlstra, Philippe Mathieu-Daudé,
Rick Edgecombe, Russell King, Sam Ravnborg, Song Liu,
Steven Rostedt, Thomas Bogendoerfer, Thomas Gleixner,
Will Deacon, bpf, linux-arch, linux-arm-kernel, linux-mips,
linux-mm, linux-modules, linux-parisc, linux-riscv, linux-s390,
linux-trace-kernel, linuxppc-dev, loongarch, netdev, sparclinux,
x86
On Thu, May 02, 2024 at 11:50:36PM +0100, Liviu Dudau wrote:
> On Mon, Apr 29, 2024 at 09:29:20AM -0700, Luis Chamberlain wrote:
> > On Mon, Apr 29, 2024 at 03:16:04PM +0300, Mike Rapoport wrote:
> > > From: "Mike Rapoport (IBM)" <rppt@kernel.org>
> > >
> > > Hi,
> > >
> > > The patches are also available in git:
> > > https://git.kernel.org/pub/scm/linux/kernel/git/rppt/linux.git/log/?h=execmem/v7
> > >
> > > v7 changes:
> > > * define MODULE_{VADDR,END} for riscv32 to fix the build and avoid
> > > #ifdefs in a function body
> > > * add Acks, thanks everybody
> >
> > Thanks, I've pushed this to modules-next for further exposure / testing.
> > Given the status of testing so far with prior revisions, in that only a
> > few issues were found and that those were fixed, and the status of
> > reviews, this just might be ripe for v6.10.
>
> Looks like there is still some work needed. I've picked up next-20240501
> and on arch/mips with CONFIG_MODULE_COMPRESS_XZ=y and CONFIG_MODULE_DECOMPRESS=y
> I fail to load any module:
>
> # modprobe rfkill
> [11746.539090] Invalid ELF header magic: != ELF
> [11746.587149] execmem: unable to allocate memory
> modprobe: can't load module rfkill (kernel/net/rfkill/rfkill.ko.xz): Out of memory
>
> The (hopefully) relevant parts of my .config:
Thanks for the report! Any chance we can get you to try a bisection? I
think it should take 2-3 test boots. To help reduce scope you try modules-next:
https://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/linux.git/log/?h=modules-next
Then can you check by resetting your tree to commmit 3fbe6c2f820a76 (mm:
introduce execmem_alloc() and execmem_free()"). I suspect that should
boot, so your bad commit would be the tip 3c2c250cb3a5fbb ("bpf: remove
CONFIG_BPF_JIT dependency on CONFIG_MODULES of").
That gives us only a few commits to bisect:
git log --oneline 3fbe6c2f820a76bc36d5546bda85832f57c8fce2..
3c2c250cb3a5 (HEAD -> modules-next, korg/modules-next) bpf: remove CONFIG_BPF_JIT dependency on CONFIG_MODULES of
11e8e65cce5c kprobes: remove dependency on CONFIG_MODULES
e10cbc38697b powerpc: use CONFIG_EXECMEM instead of CONFIG_MODULES where appropriate
4da3d38f24c5 x86/ftrace: enable dynamic ftrace without CONFIG_MODULES
13ae3d74ee70 arch: make execmem setup available regardless of CONFIG_MODULES
460bbbc70a47 powerpc: extend execmem_params for kprobes allocations
e1a14069b5b4 arm64: extend execmem_info for generated code allocations
971e181c6585 riscv: extend execmem_params for generated code allocations
0fa276f26721 mm/execmem, arch: convert remaining overrides of module_alloc to execmem
022cef244287 mm/execmem, arch: convert simple overrides of module_alloc to execmem
With 2-3 boots we should be to tell which is the bad commit.
Luis
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^ permalink raw reply [relevance 0%]
* Re: [PATCH] ARM: multi_v7_defconfig: Select CONFIG_USB_ONBOARD_DEV as built-in
@ 2024-05-02 22:58 5% ` Fabio Estevam
2024-05-03 17:16 0% ` Matthias Kaehlcke
2024-05-03 20:11 0% ` Matthias Kaehlcke
0 siblings, 2 replies; 200+ results
From: Fabio Estevam @ 2024-05-02 22:58 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: Arnd Bergmann, Alexander Stein, Fabio Estevam, linux-arm-kernel,
Mark Brown, javier.carrasco
Hi Matthias,
On Thu, May 2, 2024 at 6:45 PM Matthias Kaehlcke <mka@chromium.org> wrote:
> It is also not clear to me why things would be broken with
> CONFIG_USB=y CONFIG_USB_ONBOARD_DEV=m, but not with CONFIG_USB=m. It
> doesn't seem to be an universal issue, I can't repro it locally.
This issue happens on an imx6q-udoo board.
multi_v7_defconfig has CONFIG_USB=y and CONFIG_USB_ONBOARD_DEV=m:
https://storage.kernelci.org/next/master/next-20240502/arm/multi_v7_defconfig+CONFIG_THUMB2_KERNEL=y/gcc-10/lab-broonie/baseline-imx6q-udoo.html
usb 1-1: device descriptor read/64, error -71
usb 1-1: device descriptor read/64, error -71
usb 1-1: new full-speed USB device number 3 using ci_hdrc
usb 1-1: device descriptor read/64, error -71
usb 1-1: device descriptor read/64, error -71
usb usb1-port1: attempt power cycle
usb 1-1: new full-speed USB device number 4 using ci_hdrc
usb 1-1: device not accepting address 4, error -71
usb 1-1: new full-speed USB device number 5 using ci_hdrc
usb 1-1: device not accepting address 5, error -71
usb usb1-port1: unable to enumerate USB device
imx_v6_v7_defconfig has CONFIG_USB=y and CONFIG_USB_ONBOARD_DEV=y:
https://storage.kernelci.org/next/master/next-20240502/arm/imx_v6_v7_defconfig/gcc-10/lab-broonie/baseline-imx6q-udoo.html
In this case, the USB Wifi chip connected to the USB2514 hub is
correctly detected:
usb 1-1.3: new high-speed USB device number 3 using ci_hdrc
usb 1-1.3: New USB device found, idVendor=148f, idProduct=5370, bcdDevice= 1.01
usb 1-1.3: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 1-1.3: Product: 802.11 n WLAN
usb 1-1.3: Manufacturer: Ralink
usb 1-1.3: SerialNumber: 1.0
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^ permalink raw reply [relevance 5%]
* Re: [PATCH v7 00/16] mm: jit/text allocator
@ 2024-05-02 22:50 5% ` Liviu Dudau
2024-05-02 23:07 0% ` Luis Chamberlain
0 siblings, 1 reply; 200+ results
From: Liviu Dudau @ 2024-05-02 22:50 UTC (permalink / raw)
To: Luis Chamberlain
Cc: Mike Rapoport, linux-kernel, Alexandre Ghiti, Andrew Morton,
Björn Töpel, Catalin Marinas, Christophe Leroy,
David S. Miller, Dinh Nguyen, Donald Dutile, Eric Chanudet,
Heiko Carstens, Helge Deller, Huacai Chen, Kent Overstreet,
Mark Rutland, Masami Hiramatsu, Michael Ellerman, Nadav Amit,
Palmer Dabbelt, Peter Zijlstra, Philippe Mathieu-Daudé,
Rick Edgecombe, Russell King, Sam Ravnborg, Song Liu,
Steven Rostedt, Thomas Bogendoerfer, Thomas Gleixner,
Will Deacon, bpf, linux-arch, linux-arm-kernel, linux-mips,
linux-mm, linux-modules, linux-parisc, linux-riscv, linux-s390,
linux-trace-kernel, linuxppc-dev, loongarch, netdev, sparclinux,
x86
On Mon, Apr 29, 2024 at 09:29:20AM -0700, Luis Chamberlain wrote:
> On Mon, Apr 29, 2024 at 03:16:04PM +0300, Mike Rapoport wrote:
> > From: "Mike Rapoport (IBM)" <rppt@kernel.org>
> >
> > Hi,
> >
> > The patches are also available in git:
> > https://git.kernel.org/pub/scm/linux/kernel/git/rppt/linux.git/log/?h=execmem/v7
> >
> > v7 changes:
> > * define MODULE_{VADDR,END} for riscv32 to fix the build and avoid
> > #ifdefs in a function body
> > * add Acks, thanks everybody
>
> Thanks, I've pushed this to modules-next for further exposure / testing.
> Given the status of testing so far with prior revisions, in that only a
> few issues were found and that those were fixed, and the status of
> reviews, this just might be ripe for v6.10.
Looks like there is still some work needed. I've picked up next-20240501
and on arch/mips with CONFIG_MODULE_COMPRESS_XZ=y and CONFIG_MODULE_DECOMPRESS=y
I fail to load any module:
# modprobe rfkill
[11746.539090] Invalid ELF header magic: != ELF
[11746.587149] execmem: unable to allocate memory
modprobe: can't load module rfkill (kernel/net/rfkill/rfkill.ko.xz): Out of memory
The (hopefully) relevant parts of my .config:
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_MIPS=y
CONFIG_RALINK=y
CONFIG_SOC_MT7621=y
CONFIG_EXECMEM=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MODULES=y
# CONFIG_MODULE_DEBUG is not set
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS_NONE is not set
# CONFIG_MODULE_COMPRESS_GZIP is not set
CONFIG_MODULE_COMPRESS_XZ=y
# CONFIG_MODULE_COMPRESS_ZSTD is not set
CONFIG_MODULE_DECOMPRESS=y
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODULES_TREE_LOOKUP=y
Best regards,
Liviu
>
> Luis
>
--
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
-- John D. Clark, Ignition!
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^ permalink raw reply [relevance 5%]
* Re: [PATCH v3 2/2] pinctrl: samsung: support a bus clock
2024-05-02 7:46 0% ` Krzysztof Kozlowski
@ 2024-05-02 10:41 0% ` André Draszik
2024-05-03 9:13 0% ` Krzysztof Kozlowski
0 siblings, 1 reply; 200+ results
From: André Draszik @ 2024-05-02 10:41 UTC (permalink / raw)
To: Krzysztof Kozlowski, Tudor Ambarus, Sylwester Nawrocki,
Alim Akhtar, Linus Walleij, Rob Herring, Conor Dooley,
Tomasz Figa, Peter Griffin
Cc: Will McVicker, Sam Protsenko, kernel-team, linux-arm-kernel,
linux-samsung-soc, linux-gpio, devicetree, linux-kernel
On Thu, 2024-05-02 at 09:46 +0200, Krzysztof Kozlowski wrote:
> On 02/05/2024 09:41, Tudor Ambarus wrote:
> > >
> > > @@ -223,6 +268,13 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
> > > shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
> > > mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
> > >
> > > + if (clk_enable(bank->drvdata->pclk)) {
> > > + dev_err(bank->gpio_chip.parent,
> > > + "unable to enable clock for deconfiguring pin %s-%lu\n",
> > > + bank->name, irqd->hwirq);
> > > + return;
> >
> > but here we just print an error. I guess that for consistency reasons it
> > would be good to follow up with a patch and change the return types of
> > these methods and return the error too when the clock enable fails.
>
> That's a release, so usually void callback. The true issue is that we
> expect release to always succeed, I think.
>
> This points to issue with this patchset: looks like some patchwork all
> around the places having register accesses. But how do you even expect
> interrupts and pins to work if entire pinctrl block is clock gated?
I was initially thinking the same, but the clock seems to be required for
register access only, interrupts are still being received and triggered
with pclk turned off as per my testing.
Cheers,
Andre'
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 08/17] ACPI: pci_link: Clear the dependencies after probe
2024-05-02 9:25 0% ` Andy Shevchenko
@ 2024-05-02 9:32 0% ` Sunil V L
0 siblings, 0 replies; 200+ results
From: Sunil V L @ 2024-05-02 9:32 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Bjorn Helgaas, linux-arm-kernel, linux-kernel, linux-riscv,
linux-acpi, linux-pci, linux-serial, acpica-devel,
Catalin Marinas, Will Deacon, Paul Walmsley, Albert Ou,
Rafael J . Wysocki, Len Brown, Bjorn Helgaas, Anup Patel,
Thomas Gleixner, Samuel Holland, Greg Kroah-Hartman, Jiri Slaby,
Robert Moore, Conor Dooley, Andrew Jones, Marc Zyngier,
Atish Kumar Patra, Andrei Warkentin, Haibo1 Xu,
Björn Töpel
On Thu, May 02, 2024 at 12:25:35PM +0300, Andy Shevchenko wrote:
> On Wed, May 01, 2024 at 11:56:15AM -0500, Bjorn Helgaas wrote:
> > On Wed, May 01, 2024 at 05:47:33PM +0530, Sunil V L wrote:
> > > RISC-V platforms need to use dependencies between PCI host bridge, Link
> > > devices and the interrupt controllers to ensure probe order. The
> > > dependency is like below.
> > >
> > > Interrupt controller <-- Link Device <-- PCI Host bridge.
> > >
> > > If there is no dependency added between Link device and PCI Host Bridge,
> > > then the PCI end points can get probed prior to link device, unable to
> > > get mapping for INTx.
> > >
> > > So, add the link device's HID to dependency honor list and also clear it
> > > after its probe.
> > >
> > > Since this is required only for architectures like RISC-V, enable this
> > > code under a new config option and set this only in RISC-V.
>
> ...
>
> > > + if (IS_ENABLED(CONFIG_ARCH_ACPI_DEFERRED_GSI))
> > > + acpi_dev_clear_dependencies(device);
> >
> > This is really a question for Rafael, but it doesn't seem right that
> > this completely depends on a config option.
>
> +1 here, fells like a hack and looks like a hack.
>
I can remove the config option. I just thought this would probably never
required to be called on other architectures.
Unless there is an objection, I will remove it in next version.
Thanks!
Sunil
> > Is there a reason this wouldn't work for all architectures, i.e., what
> > would happen if you just called acpi_dev_clear_dependencies()
> > unconditionally?
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 08/17] ACPI: pci_link: Clear the dependencies after probe
2024-05-01 16:56 0% ` Bjorn Helgaas
@ 2024-05-02 9:25 0% ` Andy Shevchenko
2024-05-02 9:32 0% ` Sunil V L
0 siblings, 1 reply; 200+ results
From: Andy Shevchenko @ 2024-05-02 9:25 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Sunil V L, linux-arm-kernel, linux-kernel, linux-riscv,
linux-acpi, linux-pci, linux-serial, acpica-devel,
Catalin Marinas, Will Deacon, Paul Walmsley, Albert Ou,
Rafael J . Wysocki, Len Brown, Bjorn Helgaas, Anup Patel,
Thomas Gleixner, Samuel Holland, Greg Kroah-Hartman, Jiri Slaby,
Robert Moore, Conor Dooley, Andrew Jones, Marc Zyngier,
Atish Kumar Patra, Andrei Warkentin, Haibo1 Xu,
Björn Töpel
On Wed, May 01, 2024 at 11:56:15AM -0500, Bjorn Helgaas wrote:
> On Wed, May 01, 2024 at 05:47:33PM +0530, Sunil V L wrote:
> > RISC-V platforms need to use dependencies between PCI host bridge, Link
> > devices and the interrupt controllers to ensure probe order. The
> > dependency is like below.
> >
> > Interrupt controller <-- Link Device <-- PCI Host bridge.
> >
> > If there is no dependency added between Link device and PCI Host Bridge,
> > then the PCI end points can get probed prior to link device, unable to
> > get mapping for INTx.
> >
> > So, add the link device's HID to dependency honor list and also clear it
> > after its probe.
> >
> > Since this is required only for architectures like RISC-V, enable this
> > code under a new config option and set this only in RISC-V.
...
> > + if (IS_ENABLED(CONFIG_ARCH_ACPI_DEFERRED_GSI))
> > + acpi_dev_clear_dependencies(device);
>
> This is really a question for Rafael, but it doesn't seem right that
> this completely depends on a config option.
+1 here, fells like a hack and looks like a hack.
> Is there a reason this wouldn't work for all architectures, i.e., what
> would happen if you just called acpi_dev_clear_dependencies()
> unconditionally?
--
With Best Regards,
Andy Shevchenko
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 2/2] pinctrl: samsung: support a bus clock
2024-05-02 7:41 0% ` Tudor Ambarus
@ 2024-05-02 7:46 0% ` Krzysztof Kozlowski
2024-05-02 10:41 0% ` André Draszik
0 siblings, 1 reply; 200+ results
From: Krzysztof Kozlowski @ 2024-05-02 7:46 UTC (permalink / raw)
To: Tudor Ambarus, André Draszik, Sylwester Nawrocki,
Alim Akhtar, Linus Walleij, Rob Herring, Conor Dooley,
Tomasz Figa, Peter Griffin
Cc: Will McVicker, Sam Protsenko, kernel-team, linux-arm-kernel,
linux-samsung-soc, linux-gpio, devicetree, linux-kernel
On 02/05/2024 09:41, Tudor Ambarus wrote:
>>
>> @@ -223,6 +268,13 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
>> shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
>> mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
>>
>> + if (clk_enable(bank->drvdata->pclk)) {
>> + dev_err(bank->gpio_chip.parent,
>> + "unable to enable clock for deconfiguring pin %s-%lu\n",
>> + bank->name, irqd->hwirq);
>> + return;
>
> but here we just print an error. I guess that for consistency reasons it
> would be good to follow up with a patch and change the return types of
> these methods and return the error too when the clock enable fails.
That's a release, so usually void callback. The true issue is that we
expect release to always succeed, I think.
This points to issue with this patchset: looks like some patchwork all
around the places having register accesses. But how do you even expect
interrupts and pins to work if entire pinctrl block is clock gated?
Best regards,
Krzysztof
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 2/2] pinctrl: samsung: support a bus clock
2024-04-26 13:25 9% ` [PATCH v3 2/2] pinctrl: samsung: support a bus clock André Draszik
@ 2024-05-02 7:41 0% ` Tudor Ambarus
2024-05-02 7:46 0% ` Krzysztof Kozlowski
0 siblings, 1 reply; 200+ results
From: Tudor Ambarus @ 2024-05-02 7:41 UTC (permalink / raw)
To: André Draszik, Krzysztof Kozlowski, Sylwester Nawrocki,
Alim Akhtar, Linus Walleij, Rob Herring, Conor Dooley,
Tomasz Figa, Peter Griffin
Cc: Will McVicker, Sam Protsenko, kernel-team, linux-arm-kernel,
linux-samsung-soc, linux-gpio, devicetree, linux-kernel
Hi, André!
On 4/26/24 14:25, André Draszik wrote:
> @@ -200,6 +235,14 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
> shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
> mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
>
> + ret = clk_enable(bank->drvdata->pclk);
> + if (ret) {
> + dev_err(bank->gpio_chip.parent,
> + "unable to enable clock for configuring pin %s-%lu\n",
> + bank->name, irqd->hwirq);
> + return ret;
here we return an error
> + }
> +
> raw_spin_lock_irqsave(&bank->slock, flags);
>
> con = readl(bank->pctl_base + reg_con);
> @@ -209,6 +252,8 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
>
> raw_spin_unlock_irqrestore(&bank->slock, flags);
>
> + clk_disable(bank->drvdata->pclk);
> +
> return 0;
> }
>
> @@ -223,6 +268,13 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
> shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
> mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
>
> + if (clk_enable(bank->drvdata->pclk)) {
> + dev_err(bank->gpio_chip.parent,
> + "unable to enable clock for deconfiguring pin %s-%lu\n",
> + bank->name, irqd->hwirq);
> + return;
but here we just print an error. I guess that for consistency reasons it
would be good to follow up with a patch and change the return types of
these methods and return the error too when the clock enable fails.
Cheers,
ta
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v5 08/17] ACPI: pci_link: Clear the dependencies after probe
2024-05-01 12:17 5% ` [PATCH v5 08/17] ACPI: pci_link: Clear the dependencies after probe Sunil V L
@ 2024-05-01 16:56 0% ` Bjorn Helgaas
2024-05-02 9:25 0% ` Andy Shevchenko
0 siblings, 1 reply; 200+ results
From: Bjorn Helgaas @ 2024-05-01 16:56 UTC (permalink / raw)
To: Sunil V L
Cc: linux-arm-kernel, linux-kernel, linux-riscv, linux-acpi,
linux-pci, linux-serial, acpica-devel, Catalin Marinas,
Will Deacon, Paul Walmsley, Albert Ou, Rafael J . Wysocki,
Len Brown, Bjorn Helgaas, Anup Patel, Thomas Gleixner,
Samuel Holland, Greg Kroah-Hartman, Jiri Slaby, Robert Moore,
Conor Dooley, Andrew Jones, Andy Shevchenko, Marc Zyngier,
Atish Kumar Patra, Andrei Warkentin, Haibo1 Xu,
Björn Töpel
On Wed, May 01, 2024 at 05:47:33PM +0530, Sunil V L wrote:
> RISC-V platforms need to use dependencies between PCI host bridge, Link
> devices and the interrupt controllers to ensure probe order. The
> dependency is like below.
>
> Interrupt controller <-- Link Device <-- PCI Host bridge.
>
> If there is no dependency added between Link device and PCI Host Bridge,
> then the PCI end points can get probed prior to link device, unable to
> get mapping for INTx.
>
> So, add the link device's HID to dependency honor list and also clear it
> after its probe.
>
> Since this is required only for architectures like RISC-V, enable this
> code under a new config option and set this only in RISC-V.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
> arch/riscv/Kconfig | 1 +
> drivers/acpi/Kconfig | 3 +++
> drivers/acpi/pci_link.c | 3 +++
> drivers/acpi/scan.c | 1 +
> 4 files changed, 8 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index f961449ca077..f7a36d79ff1a 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -14,6 +14,7 @@ config RISCV
> def_bool y
> select ACPI_GENERIC_GSI if ACPI
> select ACPI_REDUCED_HARDWARE_ONLY if ACPI
> + select ARCH_ACPI_DEFERRED_GSI if ACPI
> select ARCH_DMA_DEFAULT_COHERENT
> select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
> select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
> diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
> index e3a7c2aedd5f..ebec1707f662 100644
> --- a/drivers/acpi/Kconfig
> +++ b/drivers/acpi/Kconfig
> @@ -587,6 +587,9 @@ config ACPI_PRMT
> substantially increase computational overhead related to the
> initialization of some server systems.
>
> +config ARCH_ACPI_DEFERRED_GSI
> + bool
> +
> endif # ACPI
>
> config X86_PM_TIMER
> diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c
> index aa1038b8aec4..48cdcedafad6 100644
> --- a/drivers/acpi/pci_link.c
> +++ b/drivers/acpi/pci_link.c
> @@ -748,6 +748,9 @@ static int acpi_pci_link_add(struct acpi_device *device,
> if (result)
> kfree(link);
>
> + if (IS_ENABLED(CONFIG_ARCH_ACPI_DEFERRED_GSI))
> + acpi_dev_clear_dependencies(device);
This is really a question for Rafael, but it doesn't seem right that
this completely depends on a config option.
Is there a reason this wouldn't work for all architectures, i.e., what
would happen if you just called acpi_dev_clear_dependencies()
unconditionally?
> +
> return result < 0 ? result : 1;
> }
>
> diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
> index 3eeb4ce39fcc..67677a6ff8e3 100644
> --- a/drivers/acpi/scan.c
> +++ b/drivers/acpi/scan.c
> @@ -834,6 +834,7 @@ static const char * const acpi_honor_dep_ids[] = {
> "INTC10CF", /* IVSC (MTL) driver must be loaded to allow i2c access to camera sensors */
> "RSCV0001", /* RISC-V PLIC */
> "RSCV0002", /* RISC-V APLIC */
> + "PNP0C0F", /* PCI Link Device */
> NULL
> };
>
> --
> 2.40.1
>
>
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 03/16] riscv: vector: Use vlenb from DT
2024-05-01 10:31 0% ` Conor Dooley
@ 2024-05-01 16:46 0% ` Charlie Jenkins
0 siblings, 0 replies; 200+ results
From: Charlie Jenkins @ 2024-05-01 16:46 UTC (permalink / raw)
To: Conor Dooley
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Guo Ren, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Conor Dooley, Evan Green,
Clément Léger, Jonathan Corbet, Shuah Khan,
linux-riscv, devicetree, linux-kernel, Palmer Dabbelt,
linux-arm-kernel, linux-sunxi, linux-doc, linux-kselftest
On Wed, May 01, 2024 at 11:31:45AM +0100, Conor Dooley wrote:
> On Fri, Apr 26, 2024 at 02:29:17PM -0700, Charlie Jenkins wrote:
> > If vlenb is provided in the device tree, prefer that over reading the
> > vlenb csr.
> >
> > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > ---
> > arch/riscv/include/asm/cpufeature.h | 2 ++
> > arch/riscv/kernel/cpufeature.c | 43 +++++++++++++++++++++++++++++++++++++
> > arch/riscv/kernel/vector.c | 12 ++++++++++-
> > 3 files changed, 56 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> > index 347805446151..0c4f08577015 100644
> > --- a/arch/riscv/include/asm/cpufeature.h
> > +++ b/arch/riscv/include/asm/cpufeature.h
> > @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
> > /* Per-cpu ISA extensions. */
> > extern struct riscv_isainfo hart_isa[NR_CPUS];
> >
> > +extern u32 riscv_vlenb_of;
> > +
> > void riscv_user_isa_enable(void);
> >
> > #if defined(CONFIG_RISCV_MISALIGNED)
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 3ed2359eae35..8158f34c3e36 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
> > /* Per-cpu ISA extensions. */
> > struct riscv_isainfo hart_isa[NR_CPUS];
> >
> > +u32 riscv_vlenb_of;
> > +
> > /**
> > * riscv_isa_extension_base() - Get base extension word
> > *
> > @@ -648,6 +650,42 @@ static int __init riscv_isa_fallback_setup(char *__unused)
> > early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
> > #endif
> >
> > +static int riscv_homogeneous_vlenb(void)
>
> Without a verb, this function name is rather odd.
>
Maybe has_riscv_homogeneous_vlenb() is better.
> > +{
> > + int cpu;
> > + u32 prev_vlenb = 0;
> > + u32 vlenb;
> > +
> > + for_each_possible_cpu(cpu) {
> > + struct device_node *cpu_node;
> > +
> > + cpu_node = of_cpu_device_node_get(cpu);
> > + if (!cpu_node) {
> > + pr_warn("Unable to find cpu node\n");
> > + continue;
>
> Hmm, if we fail to find the cpu node, then shouldn't we be returning an
> error?
Yes, I will change that.
>
> > + }
> > +
> > + if (of_property_read_u32(cpu_node, "riscv,vlenb", &vlenb)) {
> > + of_node_put(cpu_node);
> > +
> > + if (prev_vlenb)
> > + return -1;
>
> Can you return an errno here and below please?
>
Sounds good.
> > + continue;
> > + }
> > +
> > + if (prev_vlenb && vlenb != prev_vlenb) {
> > + of_node_put(cpu_node);
> > + return -1;
> > + }
> > +
> > + prev_vlenb = vlenb;
> > + of_node_put(cpu_node);
> > + }
> > +
> > + riscv_vlenb_of = vlenb;
> > + return 0;
> > +}
> > +
> > void __init riscv_fill_hwcap(void)
> > {
> > char print_str[NUM_ALPHA_EXTS + 1];
> > @@ -671,6 +709,11 @@ void __init riscv_fill_hwcap(void)
> > pr_info("Falling back to deprecated \"riscv,isa\"\n");
> > riscv_fill_hwcap_from_isa_string(isa2hwcap);
> > }
> > +
> > + if (riscv_homogeneous_vlenb() < 0) {
> > + pr_warn("RISCV_ISA_V only supports one vlenb on SMP systems. Please ensure that the riscv,vlenb devicetree property is the same across all CPUs. Either all CPUs must have the riscv,vlenb property, or none. If no CPUs in the devicetree use riscv,vlenb then vlenb will be probed from the vlenb CSR. Disabling vector.\n");
>
> Oh dear, that's a bit unwieldy... I think you could get away with a far
> more basic message - and you should be able to break this over lines,
> adjacent string literals should get concatenated.
> I'd probably say something like "unsupported heterogeneous vlen detected,
> vector extension disabled", however we should actually check that the
> vector extension has been detected on all CPUs and that kernel support
> for vector is enabled before emitting a warning for this.
Haha yeah I wanted to provide as much information as possible, but I
will shorten it.
I can add an if-statement to only run this code if check if V is
contained in elf_hwcap.
- Charlie
>
> Cheers,
> Conor.
>
> > + elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
> > + }
> > }
> >
> > /*
> > diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> > index 6727d1d3b8f2..e04586cdb7f0 100644
> > --- a/arch/riscv/kernel/vector.c
> > +++ b/arch/riscv/kernel/vector.c
> > @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void)
> > {
> > unsigned long this_vsize;
> >
> > - /* There are 32 vector registers with vlenb length. */
> > + /*
> > + * There are 32 vector registers with vlenb length.
> > + *
> > + * If the riscv,vlenb property was provided by the firmware, use that
> > + * instead of probing the CSRs.
> > + */
> > + if (riscv_vlenb_of) {
> > + this_vsize = riscv_vlenb_of * 32;
> > + return 0;
> > + }
> > +
> > riscv_v_enable();
> > this_vsize = csr_read(CSR_VLENB) * 32;
> > riscv_v_disable();
> >
> > --
> > 2.44.0
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* [PATCH v6 3/3] spi: airoha: Add spi-nand flash controller driver
@ 2024-05-01 14:06 2% ` Lorenzo Bianconi
0 siblings, 0 replies; 200+ results
From: Lorenzo Bianconi @ 2024-05-01 14:06 UTC (permalink / raw)
To: linux-spi
Cc: broonie, conor, lorenzo.bianconi83, linux-arm-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, nbd, john, dd,
catalin.marinas, will, upstream, angelogioacchino.delregno,
andy.shevchenko
Introduce support for spi-nand driver of the Airoha NAND Flash Interface
found on Airoha ARM SoCs.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Tested-by: Rajeev Kumar <Rajeev.Kumar@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
MAINTAINERS | 9 +
drivers/spi/Kconfig | 10 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-airoha-snfi.c | 1124 +++++++++++++++++++++++++++++++++
4 files changed, 1144 insertions(+)
create mode 100644 drivers/spi/spi-airoha-snfi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index aa3b947fb080..ce9fac46f741 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -653,6 +653,15 @@ S: Supported
F: fs/aio.c
F: include/linux/*aio*.h
+AIROHA SPI SNFI DRIVER
+M: Lorenzo Bianconi <lorenzo@kernel.org>
+M: Ray Liu <ray.liu@airoha.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-spi@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/spi/airoha,en7581-snand.yaml
+F: drivers/spi/spi-airoha.c
+
AIRSPY MEDIA DRIVER
L: linux-media@vger.kernel.org
S: Orphan
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bc7021da2fe9..6fa91775f334 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -57,6 +57,16 @@ config SPI_MEM
comment "SPI Master Controller Drivers"
+config SPI_AIROHA_SNFI
+ tristate "Airoha SPI NAND Flash Interface"
+ depends on ARCH_AIROHA || COMPILE_TEST
+ depends on SPI_MASTER
+ select REGMAP_MMIO
+ help
+ This enables support for SPI-NAND mode on the Airoha NAND
+ Flash Interface found on Airoha ARM SoCs. This controller
+ is implemented as a SPI-MEM controller.
+
config SPI_ALTERA
tristate "Altera SPI Controller platform driver"
select SPI_ALTERA_CORE
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4ff8d725ba5e..e694254dec04 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_SPIDEV) += spidev.o
obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
# SPI master controller drivers (bus)
+obj-$(CONFIG_SPI_AIROHA_SNFI) += spi-airoha-snfi.o
obj-$(CONFIG_SPI_ALTERA) += spi-altera-platform.o
obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o
obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o
diff --git a/drivers/spi/spi-airoha-snfi.c b/drivers/spi/spi-airoha-snfi.c
new file mode 100644
index 000000000000..7fc3be6d4a6a
--- /dev/null
+++ b/drivers/spi/spi-airoha-snfi.c
@@ -0,0 +1,1124 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Ray Liu <ray.liu@airoha.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <linux/limits.h>
+#include <linux/math.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/sizes.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+#include <linux/types.h>
+#include <asm/unaligned.h>
+
+/* SPI */
+#define REG_SPI_CTRL_BASE 0x1FA10000
+
+#define REG_SPI_CTRL_READ_MODE 0x0000
+#define REG_SPI_CTRL_READ_IDLE_EN 0x0004
+#define REG_SPI_CTRL_SIDLY 0x0008
+#define REG_SPI_CTRL_CSHEXT 0x000c
+#define REG_SPI_CTRL_CSLEXT 0x0010
+
+#define REG_SPI_CTRL_MTX_MODE_TOG 0x0014
+#define SPI_CTRL_MTX_MODE_TOG GENMASK(3, 0)
+
+#define REG_SPI_CTRL_RDCTL_FSM 0x0018
+#define SPI_CTRL_RDCTL_FSM GENMASK(3, 0)
+
+#define REG_SPI_CTRL_MACMUX_SEL 0x001c
+
+#define REG_SPI_CTRL_MANUAL_EN 0x0020
+#define SPI_CTRL_MANUAL_EN BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_EMPTY 0x0024
+#define SPI_CTRL_OPFIFO_EMPTY BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_WDATA 0x0028
+#define SPI_CTRL_OPFIFO_LEN GENMASK(8, 0)
+#define SPI_CTRL_OPFIFO_OP GENMASK(13, 9)
+
+#define REG_SPI_CTRL_OPFIFO_FULL 0x002c
+#define SPI_CTRL_OPFIFO_FULL BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_WR 0x0030
+#define SPI_CTRL_OPFIFO_WR BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_FULL 0x0034
+#define SPI_CTRL_DFIFO_FULL BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_WDATA 0x0038
+#define SPI_CTRL_DFIFO_WDATA GENMASK(7, 0)
+
+#define REG_SPI_CTRL_DFIFO_EMPTY 0x003c
+#define SPI_CTRL_DFIFO_EMPTY BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_RD 0x0040
+#define SPI_CTRL_DFIFO_RD BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_RDATA 0x0044
+#define SPI_CTRL_DFIFO_RDATA GENMASK(7, 0)
+
+#define REG_SPI_CTRL_DUMMY 0x0080
+#define SPI_CTRL_CTRL_DUMMY GENMASK(3, 0)
+
+#define REG_SPI_CTRL_PROBE_SEL 0x0088
+#define REG_SPI_CTRL_INTERRUPT 0x0090
+#define REG_SPI_CTRL_INTERRUPT_EN 0x0094
+#define REG_SPI_CTRL_SI_CK_SEL 0x009c
+#define REG_SPI_CTRL_SW_CFGNANDADDR_VAL 0x010c
+#define REG_SPI_CTRL_SW_CFGNANDADDR_EN 0x0110
+#define REG_SPI_CTRL_SFC_STRAP 0x0114
+
+#define REG_SPI_CTRL_NFI2SPI_EN 0x0130
+#define SPI_CTRL_NFI2SPI_EN BIT(0)
+
+/* NFI2SPI */
+#define REG_SPI_NFI_CNFG 0x0000
+#define SPI_NFI_DMA_MODE BIT(0)
+#define SPI_NFI_READ_MODE BIT(1)
+#define SPI_NFI_DMA_BURST_EN BIT(2)
+#define SPI_NFI_HW_ECC_EN BIT(8)
+#define SPI_NFI_AUTO_FDM_EN BIT(9)
+#define SPI_NFI_OPMODE GENMASK(14, 12)
+
+#define REG_SPI_NFI_PAGEFMT 0x0004
+#define SPI_NFI_PAGE_SIZE GENMASK(1, 0)
+#define SPI_NFI_SPARE_SIZE GENMASK(5, 4)
+
+#define REG_SPI_NFI_CON 0x0008
+#define SPI_NFI_FIFO_FLUSH BIT(0)
+#define SPI_NFI_RST BIT(1)
+#define SPI_NFI_RD_TRIG BIT(8)
+#define SPI_NFI_WR_TRIG BIT(9)
+#define SPI_NFI_SEC_NUM GENMASK(15, 12)
+
+#define REG_SPI_NFI_INTR_EN 0x0010
+#define SPI_NFI_RD_DONE_EN BIT(0)
+#define SPI_NFI_WR_DONE_EN BIT(1)
+#define SPI_NFI_RST_DONE_EN BIT(2)
+#define SPI_NFI_ERASE_DONE_EN BIT(3)
+#define SPI_NFI_BUSY_RETURN_EN BIT(4)
+#define SPI_NFI_ACCESS_LOCK_EN BIT(5)
+#define SPI_NFI_AHB_DONE_EN BIT(6)
+#define SPI_NFI_ALL_IRQ_EN \
+ (SPI_NFI_RD_DONE_EN | SPI_NFI_WR_DONE_EN | \
+ SPI_NFI_RST_DONE_EN | SPI_NFI_ERASE_DONE_EN | \
+ SPI_NFI_BUSY_RETURN_EN | SPI_NFI_ACCESS_LOCK_EN | \
+ SPI_NFI_AHB_DONE_EN)
+
+#define REG_SPI_NFI_INTR 0x0014
+#define SPI_NFI_AHB_DONE BIT(6)
+
+#define REG_SPI_NFI_CMD 0x0020
+
+#define REG_SPI_NFI_ADDR_NOB 0x0030
+#define SPI_NFI_ROW_ADDR_NOB GENMASK(6, 4)
+
+#define REG_SPI_NFI_STA 0x0060
+#define REG_SPI_NFI_FIFOSTA 0x0064
+#define REG_SPI_NFI_STRADDR 0x0080
+#define REG_SPI_NFI_FDM0L 0x00a0
+#define REG_SPI_NFI_FDM0M 0x00a4
+#define REG_SPI_NFI_FDM7L 0x00d8
+#define REG_SPI_NFI_FDM7M 0x00dc
+#define REG_SPI_NFI_FIFODATA0 0x0190
+#define REG_SPI_NFI_FIFODATA1 0x0194
+#define REG_SPI_NFI_FIFODATA2 0x0198
+#define REG_SPI_NFI_FIFODATA3 0x019c
+#define REG_SPI_NFI_MASTERSTA 0x0224
+
+#define REG_SPI_NFI_SECCUS_SIZE 0x022c
+#define SPI_NFI_CUS_SEC_SIZE GENMASK(12, 0)
+#define SPI_NFI_CUS_SEC_SIZE_EN BIT(16)
+
+#define REG_SPI_NFI_RD_CTL2 0x0510
+#define REG_SPI_NFI_RD_CTL3 0x0514
+
+#define REG_SPI_NFI_PG_CTL1 0x0524
+#define SPI_NFI_PG_LOAD_CMD GENMASK(15, 8)
+
+#define REG_SPI_NFI_PG_CTL2 0x0528
+#define REG_SPI_NFI_NOR_PROG_ADDR 0x052c
+#define REG_SPI_NFI_NOR_RD_ADDR 0x0534
+
+#define REG_SPI_NFI_SNF_MISC_CTL 0x0538
+#define SPI_NFI_DATA_READ_WR_MODE GENMASK(18, 16)
+
+#define REG_SPI_NFI_SNF_MISC_CTL2 0x053c
+#define SPI_NFI_READ_DATA_BYTE_NUM GENMASK(12, 0)
+#define SPI_NFI_PROG_LOAD_BYTE_NUM GENMASK(28, 16)
+
+#define REG_SPI_NFI_SNF_STA_CTL1 0x0550
+#define SPI_NFI_READ_FROM_CACHE_DONE BIT(25)
+#define SPI_NFI_LOAD_TO_CACHE_DONE BIT(26)
+
+#define REG_SPI_NFI_SNF_STA_CTL2 0x0554
+
+#define REG_SPI_NFI_SNF_NFI_CNFG 0x055c
+#define SPI_NFI_SPI_MODE BIT(0)
+
+/* SPI NAND Protocol OP */
+#define SPI_NAND_OP_GET_FEATURE 0x0f
+#define SPI_NAND_OP_SET_FEATURE 0x1f
+#define SPI_NAND_OP_PAGE_READ 0x13
+#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE 0x03
+#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST 0x0b
+#define SPI_NAND_OP_READ_FROM_CACHE_DUAL 0x3b
+#define SPI_NAND_OP_READ_FROM_CACHE_QUAD 0x6b
+#define SPI_NAND_OP_WRITE_ENABLE 0x06
+#define SPI_NAND_OP_WRITE_DISABLE 0x04
+#define SPI_NAND_OP_PROGRAM_LOAD_SINGLE 0x02
+#define SPI_NAND_OP_PROGRAM_LOAD_QUAD 0x32
+#define SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE 0x84
+#define SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD 0x34
+#define SPI_NAND_OP_PROGRAM_EXECUTE 0x10
+#define SPI_NAND_OP_READ_ID 0x9f
+#define SPI_NAND_OP_BLOCK_ERASE 0xd8
+#define SPI_NAND_OP_RESET 0xff
+#define SPI_NAND_OP_DIE_SELECT 0xc2
+
+#define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256)
+#define SPI_MAX_TRANSFER_SIZE 511
+
+enum airoha_snand_mode {
+ SPI_MODE_AUTO,
+ SPI_MODE_MANUAL,
+ SPI_MODE_DMA,
+};
+
+enum airoha_snand_cs {
+ SPI_CHIP_SEL_HIGH,
+ SPI_CHIP_SEL_LOW,
+};
+
+struct airoha_snand_dev {
+ size_t buf_len;
+
+ u8 *txrx_buf;
+ dma_addr_t dma_addr;
+
+ u64 cur_page_num;
+ bool data_need_update;
+};
+
+struct airoha_snand_ctrl {
+ struct device *dev;
+ struct regmap *regmap_ctrl;
+ struct regmap *regmap_nfi;
+ struct clk *spi_clk;
+
+ struct {
+ size_t page_size;
+ size_t sec_size;
+ u8 sec_num;
+ u8 spare_size;
+ } nfi_cfg;
+};
+
+static int airoha_snand_set_fifo_op(struct airoha_snand_ctrl *as_ctrl,
+ u8 op_cmd, int op_len)
+{
+ int err;
+ u32 val;
+
+ err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WDATA,
+ FIELD_PREP(SPI_CTRL_OPFIFO_LEN, op_len) |
+ FIELD_PREP(SPI_CTRL_OPFIFO_OP, op_cmd));
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_OPFIFO_FULL,
+ val, !(val & SPI_CTRL_OPFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WR,
+ SPI_CTRL_OPFIFO_WR);
+ if (err)
+ return err;
+
+ return regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_OPFIFO_EMPTY,
+ val, (val & SPI_CTRL_OPFIFO_EMPTY),
+ 0, 250 * USEC_PER_MSEC);
+}
+
+static int airoha_snand_set_cs(struct airoha_snand_ctrl *as_ctrl, u8 cs)
+{
+ return airoha_snand_set_fifo_op(as_ctrl, cs, sizeof(cs));
+}
+
+static int airoha_snand_write_data_to_fifo(struct airoha_snand_ctrl *as_ctrl,
+ const u8 *data, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ int err;
+ u32 val;
+
+ /* 1. Wait until dfifo is not full */
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_FULL, val,
+ !(val & SPI_CTRL_DFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ /* 2. Write data to register DFIFO_WDATA */
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_WDATA,
+ FIELD_PREP(SPI_CTRL_DFIFO_WDATA, data[i]));
+ if (err)
+ return err;
+
+ /* 3. Wait until dfifo is not full */
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_FULL, val,
+ !(val & SPI_CTRL_DFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_read_data_from_fifo(struct airoha_snand_ctrl *as_ctrl,
+ u8 *ptr, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ int err;
+ u32 val;
+
+ /* 1. wait until dfifo is not empty */
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_EMPTY, val,
+ !(val & SPI_CTRL_DFIFO_EMPTY),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ /* 2. read from dfifo to register DFIFO_RDATA */
+ err = regmap_read(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_RDATA, &val);
+ if (err)
+ return err;
+
+ ptr[i] = FIELD_GET(SPI_CTRL_DFIFO_RDATA, val);
+ /* 3. enable register DFIFO_RD to read next byte */
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_RD, SPI_CTRL_DFIFO_RD);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_set_mode(struct airoha_snand_ctrl *as_ctrl,
+ enum airoha_snand_mode mode)
+{
+ int err;
+
+ switch (mode) {
+ case SPI_MODE_MANUAL: {
+ u32 val;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_NFI2SPI_EN, 0);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_READ_IDLE_EN, 0);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_RDCTL_FSM, val,
+ !(val & SPI_CTRL_RDCTL_FSM),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MTX_MODE_TOG, 9);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MANUAL_EN, SPI_CTRL_MANUAL_EN);
+ if (err)
+ return err;
+ break;
+ }
+ case SPI_MODE_DMA:
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_NFI2SPI_EN,
+ SPI_CTRL_MANUAL_EN);
+ if (err < 0)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MTX_MODE_TOG, 0x0);
+ if (err < 0)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MANUAL_EN, 0x0);
+ if (err < 0)
+ return err;
+ break;
+ case SPI_MODE_AUTO:
+ default:
+ break;
+ }
+
+ return regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
+}
+
+static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd,
+ const u8 *data, int len)
+{
+ int i, data_len;
+
+ for (i = 0; i < len; i += data_len) {
+ int err;
+
+ data_len = min(len, SPI_MAX_TRANSFER_SIZE);
+ err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
+ if (err)
+ return err;
+
+ err = airoha_snand_write_data_to_fifo(as_ctrl, &data[i],
+ data_len);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data,
+ int len)
+{
+ int i, data_len;
+
+ for (i = 0; i < len; i += data_len) {
+ int err;
+
+ data_len = min(len, SPI_MAX_TRANSFER_SIZE);
+ err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len);
+ if (err)
+ return err;
+
+ err = airoha_snand_read_data_from_fifo(as_ctrl, &data[i],
+ data_len);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_nfi_init(struct airoha_snand_ctrl *as_ctrl)
+{
+ int err;
+
+ /* switch to SNFI mode */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_NFI_CNFG,
+ SPI_NFI_SPI_MODE);
+ if (err)
+ return err;
+
+ /* Enable DMA */
+ return regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR_EN,
+ SPI_NFI_ALL_IRQ_EN, SPI_NFI_AHB_DONE_EN);
+}
+
+static int airoha_snand_nfi_config(struct airoha_snand_ctrl *as_ctrl)
+{
+ int err;
+ u32 val;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
+ if (err)
+ return err;
+
+ /* auto FDM */
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_AUTO_FDM_EN);
+ if (err)
+ return err;
+
+ /* HW ECC */
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_HW_ECC_EN);
+ if (err)
+ return err;
+
+ /* DMA Burst */
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_DMA_BURST_EN);
+ if (err)
+ return err;
+
+ /* page format */
+ switch (as_ctrl->nfi_cfg.spare_size) {
+ case 26:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1);
+ break;
+ case 27:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x2);
+ break;
+ case 28:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x3);
+ break;
+ default:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x0);
+ break;
+ }
+
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
+ SPI_NFI_SPARE_SIZE, val);
+ if (err)
+ return err;
+
+ switch (as_ctrl->nfi_cfg.page_size) {
+ case 2048:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1);
+ break;
+ case 4096:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x2);
+ break;
+ default:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x0);
+ break;
+ }
+
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
+ SPI_NFI_PAGE_SIZE, val);
+ if (err)
+ return err;
+
+ /* sec num */
+ val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_SEC_NUM, val);
+ if (err)
+ return err;
+
+ /* enable cust sec size */
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
+ SPI_NFI_CUS_SEC_SIZE_EN);
+ if (err)
+ return err;
+
+ /* set cust sec size */
+ val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, as_ctrl->nfi_cfg.sec_size);
+ return regmap_update_bits(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SECCUS_SIZE,
+ SPI_NFI_CUS_SEC_SIZE, val);
+}
+
+static bool airoha_snand_is_page_ops(const struct spi_mem_op *op)
+{
+ if (op->addr.nbytes != 2)
+ return false;
+
+ if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
+ op->addr.buswidth != 4)
+ return false;
+
+ switch (op->data.dir) {
+ case SPI_MEM_DATA_IN:
+ if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > 0xf)
+ return false;
+
+ /* quad in / quad out */
+ if (op->addr.buswidth == 4)
+ return op->data.buswidth == 4;
+
+ if (op->addr.buswidth == 2)
+ return op->data.buswidth == 2;
+
+ /* standard spi */
+ return op->data.buswidth == 4 || op->data.buswidth == 2 ||
+ op->data.buswidth == 1;
+ case SPI_MEM_DATA_OUT:
+ return !op->dummy.nbytes && op->addr.buswidth == 1 &&
+ (op->data.buswidth == 4 || op->data.buswidth == 1);
+ default:
+ return false;
+ }
+}
+
+static int airoha_snand_adjust_op_size(struct spi_mem *mem,
+ struct spi_mem_op *op)
+{
+ size_t max_len;
+
+ if (airoha_snand_is_page_ops(op)) {
+ struct airoha_snand_ctrl *as_ctrl;
+
+ as_ctrl = spi_controller_get_devdata(mem->spi->controller);
+ max_len = as_ctrl->nfi_cfg.sec_size;
+ max_len += as_ctrl->nfi_cfg.spare_size;
+ max_len *= as_ctrl->nfi_cfg.sec_num;
+
+ if (op->data.nbytes > max_len)
+ op->data.nbytes = max_len;
+ } else {
+ max_len = 1 + op->addr.nbytes + op->dummy.nbytes;
+ if (max_len >= 160)
+ return -EOPNOTSUPP;
+
+ if (op->data.nbytes > 160 - max_len)
+ op->data.nbytes = 160 - max_len;
+ }
+
+ return 0;
+}
+
+static bool airoha_snand_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ if (!spi_mem_default_supports_op(mem, op))
+ return false;
+
+ if (op->cmd.buswidth != 1)
+ return false;
+
+ if (airoha_snand_is_page_ops(op))
+ return true;
+
+ return (!op->addr.nbytes || op->addr.buswidth == 1) &&
+ (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
+ (!op->data.nbytes || op->data.buswidth == 1);
+}
+
+static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(desc->mem->spi);
+
+ if (!as_dev->txrx_buf)
+ return -EINVAL;
+
+ if (desc->info.offset + desc->info.length > U32_MAX)
+ return -EINVAL;
+
+ if (!airoha_snand_supports_op(desc->mem, &desc->info.op_tmpl))
+ return -EOPNOTSUPP;
+
+ return 0;
+}
+
+static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, void *buf)
+{
+ struct spi_device *spi = desc->mem->spi;
+ struct airoha_snand_ctrl *as_ctrl = spi_controller_get_devdata(spi->controller);
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ struct spi_mem_op *op = &desc->info.op_tmpl;
+ u32 val, rd_mode;
+ int err;
+
+ if (!as_dev->data_need_update)
+ return len;
+
+ as_dev->data_need_update = false;
+
+ switch (op->cmd.opcode) {
+ case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
+ rd_mode = 1;
+ break;
+ case SPI_NAND_OP_READ_FROM_CACHE_QUAD:
+ rd_mode = 2;
+ break;
+ default:
+ rd_mode = 0;
+ break;
+ }
+
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_nfi_config(as_ctrl);
+ if (err)
+ return err;
+
+ dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+
+ /* set dma addr */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
+ as_dev->dma_addr);
+ if (err)
+ return err;
+
+ /* set cust sec size */
+ val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
+ val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
+ err = regmap_update_bits(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_MISC_CTL2,
+ SPI_NFI_READ_DATA_BYTE_NUM, val);
+ if (err)
+ return err;
+
+ /* set read command */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL2,
+ op->cmd.opcode);
+ if (err)
+ return err;
+
+ /* set read mode */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
+ FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, rd_mode));
+ if (err)
+ return err;
+
+ /* set read addr */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 0x0);
+ if (err)
+ return err;
+
+ /* set nfi read */
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_OPMODE,
+ FIELD_PREP(SPI_NFI_OPMODE, 6));
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
+ if (err)
+ return err;
+
+ /* trigger dma start read */
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_RD_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_RD_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_STA_CTL1, val,
+ (val & SPI_NFI_READ_FROM_CACHE_DONE),
+ 0, 1 * USEC_PER_SEC);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
+ SPI_NFI_READ_FROM_CACHE_DONE);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
+ val, (val & SPI_NFI_AHB_DONE), 0,
+ 1 * USEC_PER_SEC);
+ if (err)
+ return err;
+
+ /* DMA read need delay for data ready from controller to DRAM */
+ udelay(1);
+
+ dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ memcpy(buf, as_dev->txrx_buf + offs, len);
+
+ return len;
+}
+
+static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, const void *buf)
+{
+ struct spi_device *spi = desc->mem->spi;
+ struct airoha_snand_ctrl *as_ctrl = spi_controller_get_devdata(spi->controller);
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ struct spi_mem_op *op = &desc->info.op_tmpl;
+ u32 wr_mode, val;
+ int err;
+
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ memcpy(as_dev->txrx_buf + offs, buf, len);
+ dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_nfi_config(as_ctrl);
+ if (err)
+ return err;
+
+ if (op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_QUAD ||
+ op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD)
+ wr_mode = BIT(1);
+ else
+ wr_mode = 0;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
+ as_dev->dma_addr);
+ if (err)
+ return err;
+
+ val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM,
+ as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num);
+ err = regmap_update_bits(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_MISC_CTL2,
+ SPI_NFI_PROG_LOAD_BYTE_NUM, val);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL1,
+ FIELD_PREP(SPI_NFI_PG_LOAD_CMD,
+ op->cmd.opcode));
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
+ FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, wr_mode));
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 0x0);
+ if (err)
+ return err;
+
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_READ_MODE);
+ if (err)
+ return err;
+
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_OPMODE,
+ FIELD_PREP(SPI_NFI_OPMODE, 3));
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_DMA_MODE);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
+ if (err)
+ return err;
+
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_WR_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_WR_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
+ val, (val & SPI_NFI_AHB_DONE), 0,
+ 1 * USEC_PER_SEC);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_STA_CTL1, val,
+ (val & SPI_NFI_LOAD_TO_CACHE_DONE),
+ 0, 1 * USEC_PER_SEC);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
+ SPI_NFI_LOAD_TO_CACHE_DONE);
+ if (err)
+ return err;
+
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ return len;
+}
+
+static int airoha_snand_exec_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ struct spi_device *spi = mem->spi;
+ struct airoha_snand_ctrl *as_ctrl = spi_controller_get_devdata(spi->controller);
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ u8 data[8], cmd, opcode = op->cmd.opcode;
+ int i, err;
+
+ if (opcode == SPI_NAND_OP_PROGRAM_EXECUTE &&
+ op->addr.val == as_dev->cur_page_num) {
+ as_dev->data_need_update = true;
+ } else if (opcode == SPI_NAND_OP_PAGE_READ) {
+ if (!as_dev->data_need_update &&
+ op->addr.val == as_dev->cur_page_num)
+ return 0;
+
+ as_dev->data_need_update = true;
+ as_dev->cur_page_num = op->addr.val;
+ }
+
+ /* switch to manual mode */
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_LOW);
+ if (err < 0)
+ return err;
+
+ /* opcode */
+ err = airoha_snand_write_data(as_ctrl, 0x8, &opcode, sizeof(opcode));
+ if (err)
+ return err;
+
+ /* addr part */
+ cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
+ put_unaligned_be64(op->addr.val, data);
+
+ for (i = ARRAY_SIZE(data) - op->addr.nbytes;
+ i < ARRAY_SIZE(data); i++) {
+ err = airoha_snand_write_data(as_ctrl, cmd, &data[i],
+ sizeof(data[0]));
+ if (err)
+ return err;
+ }
+
+ /* dummy */
+ data[0] = 0xff;
+ for (i = 0; i < op->dummy.nbytes; i++) {
+ err = airoha_snand_write_data(as_ctrl, 0x8, &data[0],
+ sizeof(data[0]));
+ if (err)
+ return err;
+ }
+
+ /* data */
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ err = airoha_snand_read_data(as_ctrl, op->data.buf.in,
+ op->data.nbytes);
+ if (err)
+ return err;
+ } else {
+ err = airoha_snand_write_data(as_ctrl, 0x8, op->data.buf.out,
+ op->data.nbytes);
+ if (err)
+ return err;
+ }
+
+ return airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_HIGH);
+}
+
+static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
+ .adjust_op_size = airoha_snand_adjust_op_size,
+ .supports_op = airoha_snand_supports_op,
+ .exec_op = airoha_snand_exec_op,
+ .dirmap_create = airoha_snand_dirmap_create,
+ .dirmap_read = airoha_snand_dirmap_read,
+ .dirmap_write = airoha_snand_dirmap_write,
+};
+
+static int airoha_snand_setup(struct spi_device *spi)
+{
+ struct airoha_snand_ctrl *as_ctrl = spi_controller_get_devdata(spi->controller);
+ struct airoha_snand_dev *as_dev;
+
+ as_dev = devm_kzalloc(as_ctrl->dev, sizeof(*as_dev), GFP_KERNEL);
+ if (!as_dev)
+ return -ENOMEM;
+
+ /* prepare device buffer */
+ as_dev->buf_len = SPI_NAND_CACHE_SIZE;
+ as_dev->txrx_buf = devm_kzalloc(as_ctrl->dev, as_dev->buf_len,
+ GFP_KERNEL);
+ if (!as_dev->txrx_buf)
+ return -ENOMEM;
+
+ as_dev->dma_addr = dma_map_single(as_ctrl->dev, as_dev->txrx_buf,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ if (dma_mapping_error(as_ctrl->dev, as_dev->dma_addr))
+ return -ENOMEM;
+
+ as_dev->data_need_update = true;
+ spi_set_ctldata(spi, as_dev);
+
+ return 0;
+}
+
+static void airoha_snand_cleanup(struct spi_device *spi)
+{
+ struct airoha_snand_ctrl *as_ctrl = spi_controller_get_devdata(spi->controller);
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+
+ dma_unmap_single(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ spi_set_ctldata(spi, NULL);
+}
+
+static int airoha_snand_nfi_setup(struct airoha_snand_ctrl *as_ctrl)
+{
+ u32 val, sec_size, sec_num;
+ int err;
+
+ err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, &val);
+ if (err)
+ return err;
+
+ sec_num = FIELD_GET(SPI_NFI_SEC_NUM, val);
+
+ err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE, &val);
+ if (err)
+ return err;
+
+ sec_size = FIELD_GET(SPI_NFI_CUS_SEC_SIZE, val);
+
+ /* init default value */
+ as_ctrl->nfi_cfg.sec_size = sec_size;
+ as_ctrl->nfi_cfg.sec_num = sec_num;
+ as_ctrl->nfi_cfg.page_size = round_down(sec_size * sec_num, 1024);
+ as_ctrl->nfi_cfg.spare_size = 16;
+
+ err = airoha_snand_nfi_init(as_ctrl);
+ if (err)
+ return err;
+
+ return airoha_snand_nfi_config(as_ctrl);
+}
+
+static const struct regmap_config spi_ctrl_regmap_config = {
+ .name = "ctrl",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = REG_SPI_CTRL_NFI2SPI_EN,
+};
+
+static const struct regmap_config spi_nfi_regmap_config = {
+ .name = "nfi",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = REG_SPI_NFI_SNF_NFI_CNFG,
+};
+
+static int airoha_snand_probe(struct platform_device *pdev)
+{
+ struct airoha_snand_ctrl *as_ctrl;
+ struct device *dev = &pdev->dev;
+ struct spi_controller *ctrl;
+ void __iomem *base;
+ int err;
+
+ ctrl = devm_spi_alloc_host(dev, sizeof(*as_ctrl));
+ if (!ctrl)
+ return -ENOMEM;
+
+ as_ctrl = spi_controller_get_devdata(ctrl);
+ as_ctrl->dev = dev;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ as_ctrl->regmap_ctrl = devm_regmap_init_mmio(dev, base,
+ &spi_ctrl_regmap_config);
+ if (IS_ERR(as_ctrl->regmap_ctrl))
+ return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_ctrl),
+ "failed to init spi ctrl regmap\n");
+
+ base = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ as_ctrl->regmap_nfi = devm_regmap_init_mmio(dev, base,
+ &spi_nfi_regmap_config);
+ if (IS_ERR(as_ctrl->regmap_nfi))
+ return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_nfi),
+ "failed to init spi nfi regmap\n");
+
+ as_ctrl->spi_clk = devm_clk_get_enabled(dev, "spi");
+ if (IS_ERR(as_ctrl->spi_clk))
+ return dev_err_probe(dev, PTR_ERR(as_ctrl->spi_clk),
+ "unable to get spi clk\n");
+
+ err = dma_set_mask(as_ctrl->dev, DMA_BIT_MASK(32));
+ if (err)
+ return err;
+
+ ctrl->num_chipselect = 2;
+ ctrl->mem_ops = &airoha_snand_mem_ops;
+ ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
+ ctrl->mode_bits = SPI_RX_DUAL;
+ ctrl->setup = airoha_snand_setup;
+ ctrl->cleanup = airoha_snand_cleanup;
+ device_set_node(&ctrl->dev, dev_fwnode(dev));
+
+ err = airoha_snand_nfi_setup(as_ctrl);
+ if (err)
+ return err;
+
+ return devm_spi_register_controller(dev, ctrl);
+}
+
+static const struct of_device_id airoha_snand_ids[] = {
+ { .compatible = "airoha,en7581-snand" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_snand_ids);
+
+static struct platform_driver airoha_snand_driver = {
+ .driver = {
+ .name = "airoha-spi",
+ .of_match_table = airoha_snand_ids,
+ },
+ .probe = airoha_snand_probe,
+};
+module_platform_driver(airoha_snand_driver);
+
+MODULE_DESCRIPTION("Airoha SPI-NAND Flash Controller Driver");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Ray Liu <ray.liu@airoha.com>");
+MODULE_LICENSE("GPL");
--
2.44.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 2%]
* [PATCH v5 08/17] ACPI: pci_link: Clear the dependencies after probe
@ 2024-05-01 12:17 5% ` Sunil V L
2024-05-01 16:56 0% ` Bjorn Helgaas
2024-05-01 12:17 3% ` [PATCH v5 14/17] irqchip/riscv-imsic: Add ACPI support Sunil V L
1 sibling, 1 reply; 200+ results
From: Sunil V L @ 2024-05-01 12:17 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-riscv, linux-acpi,
linux-pci, linux-serial, acpica-devel
Cc: Catalin Marinas, Will Deacon, Paul Walmsley, Albert Ou,
Rafael J . Wysocki, Len Brown, Bjorn Helgaas, Anup Patel,
Thomas Gleixner, Samuel Holland, Greg Kroah-Hartman, Jiri Slaby,
Robert Moore, Conor Dooley, Andrew Jones, Andy Shevchenko,
Marc Zyngier, Atish Kumar Patra, Andrei Warkentin, Haibo1 Xu,
Björn Töpel, Sunil V L
RISC-V platforms need to use dependencies between PCI host bridge, Link
devices and the interrupt controllers to ensure probe order. The
dependency is like below.
Interrupt controller <-- Link Device <-- PCI Host bridge.
If there is no dependency added between Link device and PCI Host Bridge,
then the PCI end points can get probed prior to link device, unable to
get mapping for INTx.
So, add the link device's HID to dependency honor list and also clear it
after its probe.
Since this is required only for architectures like RISC-V, enable this
code under a new config option and set this only in RISC-V.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
arch/riscv/Kconfig | 1 +
drivers/acpi/Kconfig | 3 +++
drivers/acpi/pci_link.c | 3 +++
drivers/acpi/scan.c | 1 +
4 files changed, 8 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f961449ca077..f7a36d79ff1a 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,6 +14,7 @@ config RISCV
def_bool y
select ACPI_GENERIC_GSI if ACPI
select ACPI_REDUCED_HARDWARE_ONLY if ACPI
+ select ARCH_ACPI_DEFERRED_GSI if ACPI
select ARCH_DMA_DEFAULT_COHERENT
select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index e3a7c2aedd5f..ebec1707f662 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -587,6 +587,9 @@ config ACPI_PRMT
substantially increase computational overhead related to the
initialization of some server systems.
+config ARCH_ACPI_DEFERRED_GSI
+ bool
+
endif # ACPI
config X86_PM_TIMER
diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c
index aa1038b8aec4..48cdcedafad6 100644
--- a/drivers/acpi/pci_link.c
+++ b/drivers/acpi/pci_link.c
@@ -748,6 +748,9 @@ static int acpi_pci_link_add(struct acpi_device *device,
if (result)
kfree(link);
+ if (IS_ENABLED(CONFIG_ARCH_ACPI_DEFERRED_GSI))
+ acpi_dev_clear_dependencies(device);
+
return result < 0 ? result : 1;
}
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 3eeb4ce39fcc..67677a6ff8e3 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -834,6 +834,7 @@ static const char * const acpi_honor_dep_ids[] = {
"INTC10CF", /* IVSC (MTL) driver must be loaded to allow i2c access to camera sensors */
"RSCV0001", /* RISC-V PLIC */
"RSCV0002", /* RISC-V APLIC */
+ "PNP0C0F", /* PCI Link Device */
NULL
};
--
2.40.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* [PATCH v5 14/17] irqchip/riscv-imsic: Add ACPI support
2024-05-01 12:17 5% ` [PATCH v5 08/17] ACPI: pci_link: Clear the dependencies after probe Sunil V L
@ 2024-05-01 12:17 3% ` Sunil V L
2024-05-23 22:00 0% ` Thomas Gleixner
1 sibling, 1 reply; 200+ results
From: Sunil V L @ 2024-05-01 12:17 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, linux-riscv, linux-acpi,
linux-pci, linux-serial, acpica-devel
Cc: Catalin Marinas, Will Deacon, Paul Walmsley, Albert Ou,
Rafael J . Wysocki, Len Brown, Bjorn Helgaas, Anup Patel,
Thomas Gleixner, Samuel Holland, Greg Kroah-Hartman, Jiri Slaby,
Robert Moore, Conor Dooley, Andrew Jones, Andy Shevchenko,
Marc Zyngier, Atish Kumar Patra, Andrei Warkentin, Haibo1 Xu,
Björn Töpel, Sunil V L
RISC-V IMSIC interrupt controller provides IPI and MSI support.
Currently, DT based drivers setup the IPI feature early during boot but
defer setting up the MSI functionality. However, in ACPI systems, ACPI,
both IPI and MSI features need to be initialized early itself.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
drivers/irqchip/irq-riscv-imsic-early.c | 52 +++++++++-
drivers/irqchip/irq-riscv-imsic-platform.c | 32 ++++--
drivers/irqchip/irq-riscv-imsic-state.c | 115 ++++++++++-----------
drivers/irqchip/irq-riscv-imsic-state.h | 2 +-
include/linux/irqchip/riscv-imsic.h | 10 ++
5 files changed, 144 insertions(+), 67 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c
index 886418ec06cb..d8161243791d 100644
--- a/drivers/irqchip/irq-riscv-imsic-early.c
+++ b/drivers/irqchip/irq-riscv-imsic-early.c
@@ -5,13 +5,16 @@
*/
#define pr_fmt(fmt) "riscv-imsic: " fmt
+#include <linux/acpi.h>
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
+#include <linux/irqchip/riscv-imsic.h>
#include <linux/module.h>
+#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
@@ -182,7 +185,7 @@ static int __init imsic_early_dt_init(struct device_node *node, struct device_no
int rc;
/* Setup IMSIC state */
- rc = imsic_setup_state(fwnode);
+ rc = imsic_setup_state(fwnode, NULL);
if (rc) {
pr_err("%pfwP: failed to setup state (error %d)\n", fwnode, rc);
return rc;
@@ -199,3 +202,50 @@ static int __init imsic_early_dt_init(struct device_node *node, struct device_no
}
IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init);
+
+#ifdef CONFIG_ACPI
+
+static struct fwnode_handle *imsic_acpi_fwnode;
+
+struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev)
+{
+ return imsic_acpi_fwnode;
+}
+
+static int __init imsic_early_acpi_init(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_madt_imsic *imsic = (struct acpi_madt_imsic *)header;
+ int rc;
+
+ imsic_acpi_fwnode = irq_domain_alloc_named_fwnode("imsic");
+ if (!imsic_acpi_fwnode) {
+ pr_err("unable to allocate IMSIC FW node\n");
+ return -ENOMEM;
+ }
+
+ /* Setup IMSIC state */
+ rc = imsic_setup_state(imsic_acpi_fwnode, (void *)imsic);
+ if (rc) {
+ pr_err("%pfwP: failed to setup state (error %d)\n", imsic_acpi_fwnode, rc);
+ return rc;
+ }
+
+ /* Do early setup of IMSIC state and IPIs */
+ rc = imsic_early_probe(imsic_acpi_fwnode);
+ if (rc)
+ return rc;
+
+ rc = imsic_platform_acpi_probe(imsic_acpi_fwnode);
+
+#ifdef CONFIG_PCI
+ if (!rc)
+ pci_msi_register_fwnode_provider(&imsic_acpi_get_fwnode);
+#endif
+
+ return rc;
+}
+
+IRQCHIP_ACPI_DECLARE(riscv_imsic, ACPI_MADT_TYPE_IMSIC, NULL,
+ 1, imsic_early_acpi_init);
+#endif
diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c
index 11723a763c10..64905e6f52d7 100644
--- a/drivers/irqchip/irq-riscv-imsic-platform.c
+++ b/drivers/irqchip/irq-riscv-imsic-platform.c
@@ -5,6 +5,7 @@
*/
#define pr_fmt(fmt) "riscv-imsic: " fmt
+#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <linux/cpu.h>
#include <linux/interrupt.h>
@@ -348,18 +349,37 @@ int imsic_irqdomain_init(void)
return 0;
}
-static int imsic_platform_probe(struct platform_device *pdev)
+static int imsic_platform_probe_common(struct fwnode_handle *fwnode)
{
- struct device *dev = &pdev->dev;
-
- if (imsic && imsic->fwnode != dev->fwnode) {
- dev_err(dev, "fwnode mismatch\n");
+ if (imsic && imsic->fwnode != fwnode) {
+ pr_err("%pfwP: fwnode mismatch\n", fwnode);
return -ENODEV;
}
return imsic_irqdomain_init();
}
+static int imsic_platform_dt_probe(struct platform_device *pdev)
+{
+ return imsic_platform_probe_common(pdev->dev.fwnode);
+}
+
+#ifdef CONFIG_ACPI
+
+/*
+ * On ACPI based systems, PCI enumeration happens early during boot in
+ * acpi_scan_init(). PCI enumeration expects MSI domain setup before
+ * it calls pci_set_msi_domain(). Hence, unlike in DT where
+ * imsic-platform drive probe happens late during boot, ACPI based
+ * systems need to setup the MSI domain early.
+ */
+int imsic_platform_acpi_probe(struct fwnode_handle *fwnode)
+{
+ return imsic_platform_probe_common(fwnode);
+}
+
+#endif
+
static const struct of_device_id imsic_platform_match[] = {
{ .compatible = "riscv,imsics" },
{}
@@ -370,6 +390,6 @@ static struct platform_driver imsic_platform_driver = {
.name = "riscv-imsic",
.of_match_table = imsic_platform_match,
},
- .probe = imsic_platform_probe,
+ .probe = imsic_platform_dt_probe,
};
builtin_platform_driver(imsic_platform_driver);
diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c
index 5479f872e62b..608b87dd0784 100644
--- a/drivers/irqchip/irq-riscv-imsic-state.c
+++ b/drivers/irqchip/irq-riscv-imsic-state.c
@@ -5,6 +5,7 @@
*/
#define pr_fmt(fmt) "riscv-imsic: " fmt
+#include <linux/acpi.h>
#include <linux/cpu.h>
#include <linux/bitmap.h>
#include <linux/interrupt.h>
@@ -516,12 +517,8 @@ static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode,
struct of_phandle_args parent;
int rc;
- /*
- * Currently, only OF fwnode is supported so extend this
- * function for ACPI support.
- */
if (!is_of_node(fwnode))
- return -EINVAL;
+ return acpi_get_intc_index_hartid(index, hartid);
rc = of_irq_parse_one(to_of_node(fwnode), index, &parent);
if (rc)
@@ -540,12 +537,8 @@ static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode,
static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode,
u32 index, struct resource *res)
{
- /*
- * Currently, only OF fwnode is supported so extend this
- * function for ACPI support.
- */
if (!is_of_node(fwnode))
- return -EINVAL;
+ return acpi_get_imsic_mmio_info(index, res);
return of_address_to_resource(to_of_node(fwnode), index, res);
}
@@ -553,20 +546,15 @@ static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode,
static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode,
struct imsic_global_config *global,
u32 *nr_parent_irqs,
- u32 *nr_mmios)
+ u32 *nr_mmios,
+ void *opaque)
{
+ struct acpi_madt_imsic *imsic = (struct acpi_madt_imsic *)opaque;
unsigned long hartid;
struct resource res;
int rc;
u32 i;
- /*
- * Currently, only OF fwnode is supported so extend this
- * function for ACPI support.
- */
- if (!is_of_node(fwnode))
- return -EINVAL;
-
*nr_parent_irqs = 0;
*nr_mmios = 0;
@@ -578,51 +566,60 @@ static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode,
return -EINVAL;
}
- /* Find number of guest index bits in MSI address */
- rc = of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits",
- &global->guest_index_bits);
- if (rc)
- global->guest_index_bits = 0;
+ if (is_of_node(fwnode)) {
+ /* Find number of guest index bits in MSI address */
+ rc = of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits",
+ &global->guest_index_bits);
+ if (rc)
+ global->guest_index_bits = 0;
- /* Find number of HART index bits */
- rc = of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits",
- &global->hart_index_bits);
- if (rc) {
- /* Assume default value */
- global->hart_index_bits = __fls(*nr_parent_irqs);
- if (BIT(global->hart_index_bits) < *nr_parent_irqs)
- global->hart_index_bits++;
- }
+ /* Find number of HART index bits */
+ rc = of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits",
+ &global->hart_index_bits);
+ if (rc) {
+ /* Assume default value */
+ global->hart_index_bits = __fls(*nr_parent_irqs);
+ if (BIT(global->hart_index_bits) < *nr_parent_irqs)
+ global->hart_index_bits++;
+ }
- /* Find number of group index bits */
- rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits",
- &global->group_index_bits);
- if (rc)
- global->group_index_bits = 0;
+ /* Find number of group index bits */
+ rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits",
+ &global->group_index_bits);
+ if (rc)
+ global->group_index_bits = 0;
- /*
- * Find first bit position of group index.
- * If not specified assumed the default APLIC-IMSIC configuration.
- */
- rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift",
- &global->group_index_shift);
- if (rc)
- global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2;
+ /*
+ * Find first bit position of group index.
+ * If not specified assumed the default APLIC-IMSIC configuration.
+ */
+ rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift",
+ &global->group_index_shift);
+ if (rc)
+ global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2;
+
+ /* Find number of interrupt identities */
+ rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids",
+ &global->nr_ids);
+ if (rc) {
+ pr_err("%pfwP: number of interrupt identities not found\n", fwnode);
+ return rc;
+ }
- /* Find number of interrupt identities */
- rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids",
- &global->nr_ids);
- if (rc) {
- pr_err("%pfwP: number of interrupt identities not found\n", fwnode);
- return rc;
+ /* Find number of guest interrupt identities */
+ rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids",
+ &global->nr_guest_ids);
+ if (rc)
+ global->nr_guest_ids = global->nr_ids;
+ } else {
+ global->guest_index_bits = imsic->guest_index_bits;
+ global->hart_index_bits = imsic->hart_index_bits;
+ global->group_index_bits = imsic->group_index_bits;
+ global->group_index_shift = imsic->group_index_shift;
+ global->nr_ids = imsic->num_ids;
+ global->nr_guest_ids = imsic->num_guest_ids;
}
- /* Find number of guest interrupt identities */
- rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids",
- &global->nr_guest_ids);
- if (rc)
- global->nr_guest_ids = global->nr_ids;
-
/* Sanity check guest index bits */
i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT;
if (i < global->guest_index_bits) {
@@ -688,7 +685,7 @@ static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode,
return 0;
}
-int __init imsic_setup_state(struct fwnode_handle *fwnode)
+int __init imsic_setup_state(struct fwnode_handle *fwnode, void *opaque)
{
u32 i, j, index, nr_parent_irqs, nr_mmios, nr_handlers = 0;
struct imsic_global_config *global;
@@ -729,7 +726,7 @@ int __init imsic_setup_state(struct fwnode_handle *fwnode)
}
/* Parse IMSIC fwnode */
- rc = imsic_parse_fwnode(fwnode, global, &nr_parent_irqs, &nr_mmios);
+ rc = imsic_parse_fwnode(fwnode, global, &nr_parent_irqs, &nr_mmios, opaque);
if (rc)
goto out_free_local;
diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h
index 5ae2f69b035b..391e44280827 100644
--- a/drivers/irqchip/irq-riscv-imsic-state.h
+++ b/drivers/irqchip/irq-riscv-imsic-state.h
@@ -102,7 +102,7 @@ void imsic_vector_debug_show_summary(struct seq_file *m, int ind);
void imsic_state_online(void);
void imsic_state_offline(void);
-int imsic_setup_state(struct fwnode_handle *fwnode);
+int imsic_setup_state(struct fwnode_handle *fwnode, void *opaque);
int imsic_irqdomain_init(void);
#endif
diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/riscv-imsic.h
index faf0b800b1b0..e08680b1932b 100644
--- a/include/linux/irqchip/riscv-imsic.h
+++ b/include/linux/irqchip/riscv-imsic.h
@@ -84,4 +84,14 @@ static inline const struct imsic_global_config *imsic_get_global_config(void)
#endif
+#ifdef CONFIG_ACPI
+int imsic_platform_acpi_probe(struct fwnode_handle *fwnode);
+struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev);
+#else
+static inline struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev)
+{
+ return NULL;
+}
+#endif
+
#endif
--
2.40.1
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^ permalink raw reply related [relevance 3%]
* Re: [PATCH v9 19/19] cpumask: Add enabled cpumask for present CPUs that can be brought online
2024-04-30 14:24 4% ` [PATCH v9 19/19] cpumask: Add enabled cpumask for present CPUs that can be brought online Jonathan Cameron
@ 2024-05-01 11:14 0% ` Gavin Shan
0 siblings, 0 replies; 200+ results
From: Gavin Shan @ 2024-05-01 11:14 UTC (permalink / raw)
To: Jonathan Cameron, Thomas Gleixner, Peter Zijlstra, linux-pm,
loongarch, linux-acpi, linux-arch, linux-kernel,
linux-arm-kernel, kvmarm, x86, Russell King, Rafael J . Wysocki,
Miguel Luis, James Morse, Salil Mehta, Jean-Philippe Brucker,
Catalin Marinas, Will Deacon, Marc Zyngier, Hanjun Guo
Cc: Ingo Molnar, Borislav Petkov, Dave Hansen, linuxarm, justin.he,
jianyong.wu
On 5/1/24 00:24, Jonathan Cameron wrote:
> From: James Morse <james.morse@arm.com>
>
> The 'offline' file in sysfs shows all offline CPUs, including those
> that aren't present. User-space is expected to remove not-present CPUs
> from this list to learn which CPUs could be brought online.
>
> CPUs can be present but not-enabled. These CPUs can't be brought online
> until the firmware policy changes, which comes with an ACPI notification
> that will register the CPUs.
>
> With only the offline and present files, user-space is unable to
> determine which CPUs it can try to bring online. Add a new CPU mask
> that shows this based on all the registered CPUs.
>
> Signed-off-by: James Morse <james.morse@arm.com>
> Tested-by: Miguel Luis <miguel.luis@oracle.com>
> Tested-by: Vishnu Pajjuri <vishnu@os.amperecomputing.com>
> Tested-by: Jianyong Wu <jianyong.wu@arm.com>
> Acked-by: Thomas Gleixner <tglx@linutronix.de>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ---
> v9: No change
> ---
> .../ABI/testing/sysfs-devices-system-cpu | 6 +++++
> drivers/base/cpu.c | 10 ++++++++
> include/linux/cpumask.h | 25 +++++++++++++++++++
> kernel/cpu.c | 3 +++
> 4 files changed, 44 insertions(+)
>
Reviewed-by: Gavin Shan <gshan@redhat.com>
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v4 03/16] riscv: vector: Use vlenb from DT
2024-04-26 21:29 5% ` [PATCH v4 03/16] riscv: vector: Use vlenb from DT Charlie Jenkins
@ 2024-05-01 10:31 0% ` Conor Dooley
2024-05-01 16:46 0% ` Charlie Jenkins
0 siblings, 1 reply; 200+ results
From: Conor Dooley @ 2024-05-01 10:31 UTC (permalink / raw)
To: Charlie Jenkins
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Guo Ren, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Conor Dooley, Evan Green,
Clément Léger, Jonathan Corbet, Shuah Khan,
linux-riscv, devicetree, linux-kernel, Palmer Dabbelt,
linux-arm-kernel, linux-sunxi, linux-doc, linux-kselftest
[-- Attachment #1.1: Type: text/plain, Size: 4494 bytes --]
On Fri, Apr 26, 2024 at 02:29:17PM -0700, Charlie Jenkins wrote:
> If vlenb is provided in the device tree, prefer that over reading the
> vlenb csr.
>
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> ---
> arch/riscv/include/asm/cpufeature.h | 2 ++
> arch/riscv/kernel/cpufeature.c | 43 +++++++++++++++++++++++++++++++++++++
> arch/riscv/kernel/vector.c | 12 ++++++++++-
> 3 files changed, 56 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 347805446151..0c4f08577015 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
> /* Per-cpu ISA extensions. */
> extern struct riscv_isainfo hart_isa[NR_CPUS];
>
> +extern u32 riscv_vlenb_of;
> +
> void riscv_user_isa_enable(void);
>
> #if defined(CONFIG_RISCV_MISALIGNED)
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 3ed2359eae35..8158f34c3e36 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
> /* Per-cpu ISA extensions. */
> struct riscv_isainfo hart_isa[NR_CPUS];
>
> +u32 riscv_vlenb_of;
> +
> /**
> * riscv_isa_extension_base() - Get base extension word
> *
> @@ -648,6 +650,42 @@ static int __init riscv_isa_fallback_setup(char *__unused)
> early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
> #endif
>
> +static int riscv_homogeneous_vlenb(void)
Without a verb, this function name is rather odd.
> +{
> + int cpu;
> + u32 prev_vlenb = 0;
> + u32 vlenb;
> +
> + for_each_possible_cpu(cpu) {
> + struct device_node *cpu_node;
> +
> + cpu_node = of_cpu_device_node_get(cpu);
> + if (!cpu_node) {
> + pr_warn("Unable to find cpu node\n");
> + continue;
Hmm, if we fail to find the cpu node, then shouldn't we be returning an
error?
> + }
> +
> + if (of_property_read_u32(cpu_node, "riscv,vlenb", &vlenb)) {
> + of_node_put(cpu_node);
> +
> + if (prev_vlenb)
> + return -1;
Can you return an errno here and below please?
> + continue;
> + }
> +
> + if (prev_vlenb && vlenb != prev_vlenb) {
> + of_node_put(cpu_node);
> + return -1;
> + }
> +
> + prev_vlenb = vlenb;
> + of_node_put(cpu_node);
> + }
> +
> + riscv_vlenb_of = vlenb;
> + return 0;
> +}
> +
> void __init riscv_fill_hwcap(void)
> {
> char print_str[NUM_ALPHA_EXTS + 1];
> @@ -671,6 +709,11 @@ void __init riscv_fill_hwcap(void)
> pr_info("Falling back to deprecated \"riscv,isa\"\n");
> riscv_fill_hwcap_from_isa_string(isa2hwcap);
> }
> +
> + if (riscv_homogeneous_vlenb() < 0) {
> + pr_warn("RISCV_ISA_V only supports one vlenb on SMP systems. Please ensure that the riscv,vlenb devicetree property is the same across all CPUs. Either all CPUs must have the riscv,vlenb property, or none. If no CPUs in the devicetree use riscv,vlenb then vlenb will be probed from the vlenb CSR. Disabling vector.\n");
Oh dear, that's a bit unwieldy... I think you could get away with a far
more basic message - and you should be able to break this over lines,
adjacent string literals should get concatenated.
I'd probably say something like "unsupported heterogeneous vlen detected,
vector extension disabled", however we should actually check that the
vector extension has been detected on all CPUs and that kernel support
for vector is enabled before emitting a warning for this.
Cheers,
Conor.
> + elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
> + }
> }
>
> /*
> diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> index 6727d1d3b8f2..e04586cdb7f0 100644
> --- a/arch/riscv/kernel/vector.c
> +++ b/arch/riscv/kernel/vector.c
> @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void)
> {
> unsigned long this_vsize;
>
> - /* There are 32 vector registers with vlenb length. */
> + /*
> + * There are 32 vector registers with vlenb length.
> + *
> + * If the riscv,vlenb property was provided by the firmware, use that
> + * instead of probing the CSRs.
> + */
> + if (riscv_vlenb_of) {
> + this_vsize = riscv_vlenb_of * 32;
> + return 0;
> + }
> +
> riscv_v_enable();
> this_vsize = csr_read(CSR_VLENB) * 32;
> riscv_v_disable();
>
> --
> 2.44.0
>
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply [relevance 0%]
* Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6
2024-04-30 11:10 0% ` Dragan Simic
@ 2024-05-01 9:30 0% ` Andre Przywara
0 siblings, 0 replies; 200+ results
From: Andre Przywara @ 2024-05-01 9:30 UTC (permalink / raw)
To: Dragan Simic
Cc: linux-sunxi, wens, jernej.skrabec, samuel, linux-arm-kernel,
devicetree, robh, krzk+dt, conor+dt, linux-kernel
On Tue, 30 Apr 2024 13:10:41 +0200
Dragan Simic <dsimic@manjaro.org> wrote:
> Hello Andre,
>
> On 2024-04-30 12:46, Andre Przywara wrote:
> > On Tue, 30 Apr 2024 02:01:42 +0200
> > Dragan Simic <dsimic@manjaro.org> wrote:
> >> On 2024-04-30 01:10, Andre Przywara wrote:
> >> > On Sun, 28 Apr 2024 13:40:36 +0200
> >> > Dragan Simic <dsimic@manjaro.org> wrote:
> >> >
> >> >> Add missing cache information to the Allwinner H6 SoC dtsi, to allow
> >> >> the userspace, which includes lscpu(1) that uses the virtual files
> >> >> provided
> >> >> by the kernel under the /sys/devices/system/cpu directory, to display
> >> >> the
> >> >> proper H6 cache information.
> >> >>
> >> >> Adding the cache information to the H6 SoC dtsi also makes the
> >> >> following
> >> >> warning message in the kernel log go away:
> >> >>
> >> >> cacheinfo: Unable to detect cache hierarchy for CPU 0
> >> >>
> >> >> The cache parameters for the H6 dtsi were obtained and partially
> >> >> derived
> >> >> by hand from the cache size and layout specifications found in the
> >> >> following
> >> >> datasheets and technical reference manuals:
> >> >>
> >> >> - Allwinner H6 V200 datasheet, version 1.1
> >> >> - ARM Cortex-A53 revision r0p3 TRM, version E
> >> >>
> >> >> For future reference, here's a brief summary of the documentation:
> >> >>
> >> >> - All caches employ the 64-byte cache line length
> >> >> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative
> >> >> instruction
> >> >> cache and 32 KB of L1 4-way, set-associative data cache
> >> >> - The entire SoC has 512 KB of unified L2 16-way, set-associative
> >> >> cache
> >> >>
> >> >> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
> >> >
> >> > I can confirm that the data below matches the manuals, but also the
> >> > decoding of the architectural cache type registers (CCSIDR_EL1):
> >> > L1D: 32 KB: 128 sets, 4 way associative, 64 bytes/line
> >> > L1I: 32 KB: 256 sets, 2 way associative, 64 bytes/line
> >> > L2: 512 KB: 512 sets, 16 way associative, 64 bytes/line
> >>
> >> Thank you very much for reviewing my patch in such a detailed way!
> >> It's good to know that the values in the Allwinner datasheets match
> >> with the observed reality, so to speak. :)
> >
> > YW, and yes, I like to double check things when it comes to Allwinner
> > documentation ;-) And it was comparably easy for this problem.
>
> Double checking is always good, IMHO. :)
>
> > Out of curiosity: what triggered that patch? Trying to get rid of false
> > warning/error messages?
>
> Yes, one of the motivators was to get rid of the false kernel warning,
> and the other was to have the cache information nicely available through
> lscpu(1). I already did the same for a few Rockchip SoCs, [1][2][3] so
> a couple of Allwinner SoCs were the next on my mental TODO list. :)
Thanks for doing this!
> > And do you plan to address the H616 as well? It's a bit more tricky
> > there,
> > since there are two die revisions out: one with 256(?)KB of L2, one
> > with
> > 1MB(!). We know how to tell them apart, so I could provide some TF-A
> > code
> > to patch that up in the DT. The kernel DT copy could go with 256KB
> > then.
>
> I have no boards based on the Allwinner H616, so it wasn't on my radar.
> Though, I'd be happy to prepare and submit a similar kernel patch for
> the H616, if you'd then take it further and submit a TF-A patch that
> fixes the DT according to the detected die revision? Did I understand
> the plan right?
Yes, that was the idea. I have a working version of that TF-A patch now,
just need to figure out some details about the best way to only build this
for the H616 port.
Neither the data sheet nor the user manual mention the cache sizes for the
H616, but I checked the CSSIDR_EL1 register readouts on both an old H616
and a new H618, and they confirm that the former has 256 KB L2, and the
latter 1MB. Also I ran tinymembench on two boards to confirm this,
community benchmarks results are available here:
https://github.com/ThomasKaiser/sbc-bench/blob/master/Results.md
The OrangePi Zero2 and OrangePi Zero3 are good examples, respectively.
Associativity and cache line size are dictated by the Arm Cortex cores,
and the L1I & L1D sizes are the same as in the other SoCs.
Cheers,
Andre
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=67a6a98575974416834c2294853b3814376a7ce7
> [2]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=8612169a05c5e979af033868b7a9b177e0f9fcdf
> [3]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=b72633ba5cfa932405832de25d0f0a11716903b4
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^ permalink raw reply [relevance 0%]
* [PATCH v9 19/19] cpumask: Add enabled cpumask for present CPUs that can be brought online
2024-04-30 14:24 5% ` [PATCH v9 17/19] arm64: Kconfig: Enable hotplug CPU on arm64 if ACPI_PROCESSOR is enabled Jonathan Cameron
@ 2024-04-30 14:24 4% ` Jonathan Cameron
2024-05-01 11:14 0% ` Gavin Shan
1 sibling, 1 reply; 200+ results
From: Jonathan Cameron @ 2024-04-30 14:24 UTC (permalink / raw)
To: Thomas Gleixner, Peter Zijlstra, linux-pm, loongarch, linux-acpi,
linux-arch, linux-kernel, linux-arm-kernel, kvmarm, x86,
Russell King, Rafael J . Wysocki, Miguel Luis, James Morse,
Salil Mehta, Jean-Philippe Brucker, Catalin Marinas, Will Deacon,
Marc Zyngier, Hanjun Guo, Gavin Shan
Cc: Ingo Molnar, Borislav Petkov, Dave Hansen, linuxarm, justin.he,
jianyong.wu
From: James Morse <james.morse@arm.com>
The 'offline' file in sysfs shows all offline CPUs, including those
that aren't present. User-space is expected to remove not-present CPUs
from this list to learn which CPUs could be brought online.
CPUs can be present but not-enabled. These CPUs can't be brought online
until the firmware policy changes, which comes with an ACPI notification
that will register the CPUs.
With only the offline and present files, user-space is unable to
determine which CPUs it can try to bring online. Add a new CPU mask
that shows this based on all the registered CPUs.
Signed-off-by: James Morse <james.morse@arm.com>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
Tested-by: Vishnu Pajjuri <vishnu@os.amperecomputing.com>
Tested-by: Jianyong Wu <jianyong.wu@arm.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v9: No change
---
.../ABI/testing/sysfs-devices-system-cpu | 6 +++++
drivers/base/cpu.c | 10 ++++++++
include/linux/cpumask.h | 25 +++++++++++++++++++
kernel/cpu.c | 3 +++
4 files changed, 44 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
index 710d47be11e0..808efb5b860a 100644
--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
@@ -694,3 +694,9 @@ Description:
(RO) indicates whether or not the kernel directly supports
modifying the crash elfcorehdr for CPU hot un/plug and/or
on/offline changes.
+
+What: /sys/devices/system/cpu/enabled
+Date: Nov 2022
+Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
+Description:
+ (RO) the list of CPUs that can be brought online.
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index 7b83e9c87d7c..353ee39a5cbe 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -95,6 +95,7 @@ void unregister_cpu(struct cpu *cpu)
{
int logical_cpu = cpu->dev.id;
+ set_cpu_enabled(logical_cpu, false);
unregister_cpu_under_node(logical_cpu, cpu_to_node(logical_cpu));
device_unregister(&cpu->dev);
@@ -273,6 +274,13 @@ static ssize_t print_cpus_offline(struct device *dev,
}
static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL);
+static ssize_t print_cpus_enabled(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(cpu_enabled_mask));
+}
+static DEVICE_ATTR(enabled, 0444, print_cpus_enabled, NULL);
+
static ssize_t print_cpus_isolated(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -413,6 +421,7 @@ int register_cpu(struct cpu *cpu, int num)
register_cpu_under_node(num, cpu_to_node(num));
dev_pm_qos_expose_latency_limit(&cpu->dev,
PM_QOS_RESUME_LATENCY_NO_CONSTRAINT);
+ set_cpu_enabled(num, true);
return 0;
}
@@ -494,6 +503,7 @@ static struct attribute *cpu_root_attrs[] = {
&cpu_attrs[2].attr.attr,
&dev_attr_kernel_max.attr,
&dev_attr_offline.attr,
+ &dev_attr_enabled.attr,
&dev_attr_isolated.attr,
#ifdef CONFIG_NO_HZ_FULL
&dev_attr_nohz_full.attr,
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index 1c29947db848..4b202b94c97a 100644
--- a/include/linux/cpumask.h
+++ b/include/linux/cpumask.h
@@ -93,6 +93,7 @@ static inline void set_nr_cpu_ids(unsigned int nr)
*
* cpu_possible_mask- has bit 'cpu' set iff cpu is populatable
* cpu_present_mask - has bit 'cpu' set iff cpu is populated
+ * cpu_enabled_mask - has bit 'cpu' set iff cpu can be brought online
* cpu_online_mask - has bit 'cpu' set iff cpu available to scheduler
* cpu_active_mask - has bit 'cpu' set iff cpu available to migration
*
@@ -125,11 +126,13 @@ static inline void set_nr_cpu_ids(unsigned int nr)
extern struct cpumask __cpu_possible_mask;
extern struct cpumask __cpu_online_mask;
+extern struct cpumask __cpu_enabled_mask;
extern struct cpumask __cpu_present_mask;
extern struct cpumask __cpu_active_mask;
extern struct cpumask __cpu_dying_mask;
#define cpu_possible_mask ((const struct cpumask *)&__cpu_possible_mask)
#define cpu_online_mask ((const struct cpumask *)&__cpu_online_mask)
+#define cpu_enabled_mask ((const struct cpumask *)&__cpu_enabled_mask)
#define cpu_present_mask ((const struct cpumask *)&__cpu_present_mask)
#define cpu_active_mask ((const struct cpumask *)&__cpu_active_mask)
#define cpu_dying_mask ((const struct cpumask *)&__cpu_dying_mask)
@@ -1009,6 +1012,7 @@ extern const DECLARE_BITMAP(cpu_all_bits, NR_CPUS);
#else
#define for_each_possible_cpu(cpu) for_each_cpu((cpu), cpu_possible_mask)
#define for_each_online_cpu(cpu) for_each_cpu((cpu), cpu_online_mask)
+#define for_each_enabled_cpu(cpu) for_each_cpu((cpu), cpu_enabled_mask)
#define for_each_present_cpu(cpu) for_each_cpu((cpu), cpu_present_mask)
#endif
@@ -1031,6 +1035,15 @@ set_cpu_possible(unsigned int cpu, bool possible)
cpumask_clear_cpu(cpu, &__cpu_possible_mask);
}
+static inline void
+set_cpu_enabled(unsigned int cpu, bool can_be_onlined)
+{
+ if (can_be_onlined)
+ cpumask_set_cpu(cpu, &__cpu_enabled_mask);
+ else
+ cpumask_clear_cpu(cpu, &__cpu_enabled_mask);
+}
+
static inline void
set_cpu_present(unsigned int cpu, bool present)
{
@@ -1112,6 +1125,7 @@ static __always_inline unsigned int num_online_cpus(void)
return raw_atomic_read(&__num_online_cpus);
}
#define num_possible_cpus() cpumask_weight(cpu_possible_mask)
+#define num_enabled_cpus() cpumask_weight(cpu_enabled_mask)
#define num_present_cpus() cpumask_weight(cpu_present_mask)
#define num_active_cpus() cpumask_weight(cpu_active_mask)
@@ -1120,6 +1134,11 @@ static inline bool cpu_online(unsigned int cpu)
return cpumask_test_cpu(cpu, cpu_online_mask);
}
+static inline bool cpu_enabled(unsigned int cpu)
+{
+ return cpumask_test_cpu(cpu, cpu_enabled_mask);
+}
+
static inline bool cpu_possible(unsigned int cpu)
{
return cpumask_test_cpu(cpu, cpu_possible_mask);
@@ -1144,6 +1163,7 @@ static inline bool cpu_dying(unsigned int cpu)
#define num_online_cpus() 1U
#define num_possible_cpus() 1U
+#define num_enabled_cpus() 1U
#define num_present_cpus() 1U
#define num_active_cpus() 1U
@@ -1157,6 +1177,11 @@ static inline bool cpu_possible(unsigned int cpu)
return cpu == 0;
}
+static inline bool cpu_enabled(unsigned int cpu)
+{
+ return cpu == 0;
+}
+
static inline bool cpu_present(unsigned int cpu)
{
return cpu == 0;
diff --git a/kernel/cpu.c b/kernel/cpu.c
index 8f6affd051f7..537099bf5d02 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -3117,6 +3117,9 @@ EXPORT_SYMBOL(__cpu_possible_mask);
struct cpumask __cpu_online_mask __read_mostly;
EXPORT_SYMBOL(__cpu_online_mask);
+struct cpumask __cpu_enabled_mask __read_mostly;
+EXPORT_SYMBOL(__cpu_enabled_mask);
+
struct cpumask __cpu_present_mask __read_mostly;
EXPORT_SYMBOL(__cpu_present_mask);
--
2.39.2
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^ permalink raw reply related [relevance 4%]
* [PATCH v9 17/19] arm64: Kconfig: Enable hotplug CPU on arm64 if ACPI_PROCESSOR is enabled.
@ 2024-04-30 14:24 5% ` Jonathan Cameron
2024-04-30 14:24 4% ` [PATCH v9 19/19] cpumask: Add enabled cpumask for present CPUs that can be brought online Jonathan Cameron
1 sibling, 0 replies; 200+ results
From: Jonathan Cameron @ 2024-04-30 14:24 UTC (permalink / raw)
To: Thomas Gleixner, Peter Zijlstra, linux-pm, loongarch, linux-acpi,
linux-arch, linux-kernel, linux-arm-kernel, kvmarm, x86,
Russell King, Rafael J . Wysocki, Miguel Luis, James Morse,
Salil Mehta, Jean-Philippe Brucker, Catalin Marinas, Will Deacon,
Marc Zyngier, Hanjun Guo, Gavin Shan
Cc: Ingo Molnar, Borislav Petkov, Dave Hansen, linuxarm, justin.he,
jianyong.wu
In order to move arch_register_cpu() to be called via the same path
for initially present CPUs described by ACPI and hotplugged CPUs
ACPI_HOTPLUG_CPU needs to be enabled.
The protection against invalid IDs in acpi_map_cpu() is needed as
at least one production BIOS is in the wild which reports entries
in DSDT (with no _STA method, so assumed enabled and present)
that don't match MADT.
Tested-by: Miguel Luis <miguel.luis@oracle.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
V9: No change.
---
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/acpi.c | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7b11c98b3e84..fed7d0d54179 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -5,6 +5,7 @@ config ARM64
select ACPI_CCA_REQUIRED if ACPI
select ACPI_GENERIC_GSI if ACPI
select ACPI_GTDT if ACPI
+ select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR
select ACPI_IORT if ACPI
select ACPI_REDUCED_HARDWARE_ONLY if ACPI
select ACPI_MCFG if (ACPI && PCI)
diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index dba8fcec7f33..fb9368197c74 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -29,6 +29,7 @@
#include <linux/pgtable.h>
#include <acpi/ghes.h>
+#include <acpi/processor.h>
#include <asm/cputype.h>
#include <asm/cpu_ops.h>
#include <asm/daifflags.h>
@@ -413,6 +414,27 @@ void arch_reserve_mem_area(acpi_physical_address addr, size_t size)
memblock_mark_nomap(addr, size);
}
+#ifdef CONFIG_ACPI_HOTPLUG_CPU
+int acpi_map_cpu(acpi_handle handle, phys_cpuid_t physid, u32 apci_id,
+ int *pcpu)
+{
+ /* If an error code is passed in this stub can't fix it */
+ if (*pcpu < 0) {
+ pr_warn_once("Unable to map CPU to valid ID\n");
+ return *pcpu;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(acpi_map_cpu);
+
+int acpi_unmap_cpu(int cpu)
+{
+ return 0;
+}
+EXPORT_SYMBOL(acpi_unmap_cpu);
+#endif /* CONFIG_ACPI_HOTPLUG_CPU */
+
#ifdef CONFIG_ACPI_FFH
/*
* Implements ARM64 specific callbacks to support ACPI FFH Operation Region as
--
2.39.2
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^ permalink raw reply related [relevance 5%]
* Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6
2024-04-30 10:46 0% ` Andre Przywara
@ 2024-04-30 11:10 0% ` Dragan Simic
2024-05-01 9:30 0% ` Andre Przywara
0 siblings, 1 reply; 200+ results
From: Dragan Simic @ 2024-04-30 11:10 UTC (permalink / raw)
To: Andre Przywara
Cc: linux-sunxi, wens, jernej.skrabec, samuel, linux-arm-kernel,
devicetree, robh, krzk+dt, conor+dt, linux-kernel
Hello Andre,
On 2024-04-30 12:46, Andre Przywara wrote:
> On Tue, 30 Apr 2024 02:01:42 +0200
> Dragan Simic <dsimic@manjaro.org> wrote:
>> On 2024-04-30 01:10, Andre Przywara wrote:
>> > On Sun, 28 Apr 2024 13:40:36 +0200
>> > Dragan Simic <dsimic@manjaro.org> wrote:
>> >
>> >> Add missing cache information to the Allwinner H6 SoC dtsi, to allow
>> >> the userspace, which includes lscpu(1) that uses the virtual files
>> >> provided
>> >> by the kernel under the /sys/devices/system/cpu directory, to display
>> >> the
>> >> proper H6 cache information.
>> >>
>> >> Adding the cache information to the H6 SoC dtsi also makes the
>> >> following
>> >> warning message in the kernel log go away:
>> >>
>> >> cacheinfo: Unable to detect cache hierarchy for CPU 0
>> >>
>> >> The cache parameters for the H6 dtsi were obtained and partially
>> >> derived
>> >> by hand from the cache size and layout specifications found in the
>> >> following
>> >> datasheets and technical reference manuals:
>> >>
>> >> - Allwinner H6 V200 datasheet, version 1.1
>> >> - ARM Cortex-A53 revision r0p3 TRM, version E
>> >>
>> >> For future reference, here's a brief summary of the documentation:
>> >>
>> >> - All caches employ the 64-byte cache line length
>> >> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative
>> >> instruction
>> >> cache and 32 KB of L1 4-way, set-associative data cache
>> >> - The entire SoC has 512 KB of unified L2 16-way, set-associative
>> >> cache
>> >>
>> >> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
>> >
>> > I can confirm that the data below matches the manuals, but also the
>> > decoding of the architectural cache type registers (CCSIDR_EL1):
>> > L1D: 32 KB: 128 sets, 4 way associative, 64 bytes/line
>> > L1I: 32 KB: 256 sets, 2 way associative, 64 bytes/line
>> > L2: 512 KB: 512 sets, 16 way associative, 64 bytes/line
>>
>> Thank you very much for reviewing my patch in such a detailed way!
>> It's good to know that the values in the Allwinner datasheets match
>> with the observed reality, so to speak. :)
>
> YW, and yes, I like to double check things when it comes to Allwinner
> documentation ;-) And it was comparably easy for this problem.
Double checking is always good, IMHO. :)
> Out of curiosity: what triggered that patch? Trying to get rid of false
> warning/error messages?
Yes, one of the motivators was to get rid of the false kernel warning,
and the other was to have the cache information nicely available through
lscpu(1). I already did the same for a few Rockchip SoCs, [1][2][3] so
a couple of Allwinner SoCs were the next on my mental TODO list. :)
> And do you plan to address the H616 as well? It's a bit more tricky
> there,
> since there are two die revisions out: one with 256(?)KB of L2, one
> with
> 1MB(!). We know how to tell them apart, so I could provide some TF-A
> code
> to patch that up in the DT. The kernel DT copy could go with 256KB
> then.
I have no boards based on the Allwinner H616, so it wasn't on my radar.
Though, I'd be happy to prepare and submit a similar kernel patch for
the H616, if you'd then take it further and submit a TF-A patch that
fixes the DT according to the detected die revision? Did I understand
the plan right?
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=67a6a98575974416834c2294853b3814376a7ce7
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=8612169a05c5e979af033868b7a9b177e0f9fcdf
[3]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=b72633ba5cfa932405832de25d0f0a11716903b4
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^ permalink raw reply [relevance 0%]
* [PATCH 16/17] mfd: Add support for LAN966x PCI device
@ 2024-04-30 8:37 5% ` Herve Codina
2024-05-08 8:20 0% ` Steen.Hegelund
0 siblings, 1 reply; 200+ results
From: Herve Codina @ 2024-04-30 8:37 UTC (permalink / raw)
To: Herve Codina, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Lee Jones, Arnd Bergmann, Horatiu Vultur,
UNGLinuxDriver, Andrew Lunn, Heiner Kallweit, Russell King,
Saravana Kannan, Bjorn Helgaas, Philipp Zabel, Lars Povlsen,
Steen Hegelund, Daniel Machon, Alexandre Belloni
Cc: linux-kernel, devicetree, netdev, linux-pci, linux-arm-kernel,
Allan Nielsen, Steen Hegelund, Luca Ceresoli, Thomas Petazzoni
Add a PCI driver that handles the LAN966x PCI device using a device-tree
overlay. This overlay is applied to the PCI device DT node and allows to
describe components that are present in the device.
The memory from the device-tree is remapped to the BAR memory thanks to
"ranges" properties computed at runtime by the PCI core during the PCI
enumeration.
The PCI device itself acts as an interrupt controller and is used as the
parent of the internal LAN966x interrupt controller to route the
interrupts to the assigned PCI INTx interrupt.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
drivers/mfd/Kconfig | 24 ++++
drivers/mfd/Makefile | 4 +
drivers/mfd/lan966x_pci.c | 229 +++++++++++++++++++++++++++++++++++
drivers/mfd/lan966x_pci.dtso | 167 +++++++++++++++++++++++++
drivers/pci/quirks.c | 1 +
5 files changed, 425 insertions(+)
create mode 100644 drivers/mfd/lan966x_pci.c
create mode 100644 drivers/mfd/lan966x_pci.dtso
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4b023ee229cf..e5f5d2986dd3 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -144,6 +144,30 @@ config MFD_ATMEL_FLEXCOM
by the probe function of this MFD driver according to a device tree
property.
+config MFD_LAN966X_PCI
+ tristate "Microchip LAN966x PCIe Support"
+ depends on PCI
+ select OF
+ select OF_OVERLAY
+ select IRQ_DOMAIN
+ help
+ This enables the support for the LAN966x PCIe device.
+ This is used to drive the LAN966x PCIe device from the host system
+ to which it is connected.
+
+ This driver uses an overlay to load other drivers to support for
+ LAN966x internal components.
+ Even if this driver does not depend on these other drivers, in order
+ to have a fully functional board, the following drivers are needed:
+ - fixed-clock (COMMON_CLK)
+ - lan966x-oic (LAN966X_OIC)
+ - lan966x-cpu-syscon (MFD_SYSCON)
+ - lan966x-switch-reset (RESET_MCHP_SPARX5)
+ - lan966x-pinctrl (PINCTRL_OCELOT)
+ - lan966x-serdes (PHY_LAN966X_SERDES)
+ - lan966x-miim (MDIO_MSCC_MIIM)
+ - lan966x-switch (LAN966X_SWITCH)
+
config MFD_ATMEL_HLCDC
tristate "Atmel HLCDC (High-end LCD Controller)"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index c66f07edcd0e..165a9674ff48 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -284,3 +284,7 @@ rsmu-i2c-objs := rsmu_core.o rsmu_i2c.o
rsmu-spi-objs := rsmu_core.o rsmu_spi.o
obj-$(CONFIG_MFD_RSMU_I2C) += rsmu-i2c.o
obj-$(CONFIG_MFD_RSMU_SPI) += rsmu-spi.o
+
+lan966x-pci-objs := lan966x_pci.o
+lan966x-pci-objs += lan966x_pci.dtbo.o
+obj-$(CONFIG_MFD_LAN966X_PCI) += lan966x-pci.o
diff --git a/drivers/mfd/lan966x_pci.c b/drivers/mfd/lan966x_pci.c
new file mode 100644
index 000000000000..d9d886a1948f
--- /dev/null
+++ b/drivers/mfd/lan966x_pci.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Microchip LAN966x PCI driver
+ *
+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
+ *
+ * Authors:
+ * Clément Léger <clement.leger@bootlin.com>
+ * Hervé Codina <herve.codina@bootlin.com>
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+
+/* Embedded dtbo symbols created by cmd_wrap_S_dtb in scripts/Makefile.lib */
+extern char __dtbo_lan966x_pci_begin[];
+extern char __dtbo_lan966x_pci_end[];
+
+struct pci_dev_intr_ctrl {
+ struct pci_dev *pci_dev;
+ struct irq_domain *irq_domain;
+ int irq;
+};
+
+static int pci_dev_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw)
+{
+ irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_simple_irq);
+ return 0;
+}
+
+static const struct irq_domain_ops pci_dev_irq_domain_ops = {
+ .map = pci_dev_irq_domain_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static irqreturn_t pci_dev_irq_handler(int irq, void *data)
+{
+ struct pci_dev_intr_ctrl *intr_ctrl = data;
+ int ret;
+
+ ret = generic_handle_domain_irq(intr_ctrl->irq_domain, 0);
+ return ret ? IRQ_NONE : IRQ_HANDLED;
+}
+
+static struct pci_dev_intr_ctrl *pci_dev_create_intr_ctrl(struct pci_dev *pdev)
+{
+ struct pci_dev_intr_ctrl *intr_ctrl;
+ struct fwnode_handle *fwnode;
+ int ret;
+
+ if (!pdev->irq)
+ return ERR_PTR(-EOPNOTSUPP);
+
+ fwnode = dev_fwnode(&pdev->dev);
+ if (!fwnode)
+ return ERR_PTR(-ENODEV);
+
+ intr_ctrl = kmalloc(sizeof(*intr_ctrl), GFP_KERNEL);
+ if (!intr_ctrl)
+ return ERR_PTR(-ENOMEM);
+
+ intr_ctrl->pci_dev = pdev;
+
+ intr_ctrl->irq_domain = irq_domain_create_linear(fwnode, 1, &pci_dev_irq_domain_ops,
+ intr_ctrl);
+ if (!intr_ctrl->irq_domain) {
+ pci_err(pdev, "Failed to create irqdomain\n");
+ ret = -ENOMEM;
+ goto err_free_intr_ctrl;
+ }
+
+ ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
+ if (ret < 0) {
+ pci_err(pdev, "Unable alloc irq vector (%d)\n", ret);
+ goto err_remove_domain;
+ }
+ intr_ctrl->irq = pci_irq_vector(pdev, 0);
+ ret = request_irq(intr_ctrl->irq, pci_dev_irq_handler, IRQF_SHARED,
+ dev_name(&pdev->dev), intr_ctrl);
+ if (ret) {
+ pci_err(pdev, "Unable to request irq %d (%d)\n", intr_ctrl->irq, ret);
+ goto err_free_irq_vector;
+ }
+
+ return intr_ctrl;
+
+err_free_irq_vector:
+ pci_free_irq_vectors(pdev);
+err_remove_domain:
+ irq_domain_remove(intr_ctrl->irq_domain);
+err_free_intr_ctrl:
+ kfree(intr_ctrl);
+ return ERR_PTR(ret);
+}
+
+static void pci_dev_remove_intr_ctrl(struct pci_dev_intr_ctrl *intr_ctrl)
+{
+ free_irq(intr_ctrl->irq, intr_ctrl);
+ pci_free_irq_vectors(intr_ctrl->pci_dev);
+ irq_dispose_mapping(irq_find_mapping(intr_ctrl->irq_domain, 0));
+ irq_domain_remove(intr_ctrl->irq_domain);
+ kfree(intr_ctrl);
+}
+
+static void devm_pci_dev_remove_intr_ctrl(void *data)
+{
+ struct pci_dev_intr_ctrl *intr_ctrl = data;
+
+ pci_dev_remove_intr_ctrl(intr_ctrl);
+}
+
+static int devm_pci_dev_create_intr_ctrl(struct pci_dev *pdev)
+{
+ struct pci_dev_intr_ctrl *intr_ctrl;
+
+ intr_ctrl = pci_dev_create_intr_ctrl(pdev);
+
+ if (IS_ERR(intr_ctrl))
+ return PTR_ERR(intr_ctrl);
+
+ return devm_add_action_or_reset(&pdev->dev, devm_pci_dev_remove_intr_ctrl, intr_ctrl);
+}
+
+struct lan966x_pci {
+ struct device *dev;
+ struct pci_dev *pci_dev;
+ int ovcs_id;
+};
+
+static int lan966x_pci_load_overlay(struct lan966x_pci *data)
+{
+ u32 dtbo_size = __dtbo_lan966x_pci_end - __dtbo_lan966x_pci_begin;
+ void *dtbo_start = __dtbo_lan966x_pci_begin;
+ int ret;
+
+ ret = of_overlay_fdt_apply(dtbo_start, dtbo_size, &data->ovcs_id, data->dev->of_node);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void lan966x_pci_unload_overlay(struct lan966x_pci *data)
+{
+ of_overlay_remove(&data->ovcs_id);
+}
+
+static int lan966x_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct device *dev = &pdev->dev;
+ struct lan966x_pci *data;
+ int ret;
+
+ if (!dev->of_node) {
+ dev_err(dev, "Missing of_node for device\n");
+ return -EINVAL;
+ }
+
+ /* Need to be done before devm_pci_dev_create_intr_ctrl.
+ * It allocates an IRQ and so pdev->irq is updated
+ */
+ ret = pcim_enable_device(pdev);
+ if (ret)
+ return ret;
+
+ ret = devm_pci_dev_create_intr_ctrl(pdev);
+ if (ret)
+ return ret;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, data);
+ data->dev = dev;
+ data->pci_dev = pdev;
+
+ ret = lan966x_pci_load_overlay(data);
+ if (ret)
+ return ret;
+
+ pci_set_master(pdev);
+
+ ret = of_platform_default_populate(dev->of_node, NULL, dev);
+ if (ret)
+ goto err_unload_overlay;
+
+ return 0;
+
+err_unload_overlay:
+ lan966x_pci_unload_overlay(data);
+ return ret;
+}
+
+static void lan966x_pci_remove(struct pci_dev *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct lan966x_pci *data = dev_get_drvdata(dev);
+
+ of_platform_depopulate(dev);
+
+ lan966x_pci_unload_overlay(data);
+
+ pci_clear_master(pdev);
+}
+
+static struct pci_device_id lan966x_pci_ids[] = {
+ { PCI_DEVICE(0x1055, 0x9660) },
+ { 0, }
+};
+MODULE_DEVICE_TABLE(pci, lan966x_pci_ids);
+
+static struct pci_driver lan966x_pci_driver = {
+ .name = "mchp_lan966x_pci",
+ .id_table = lan966x_pci_ids,
+ .probe = lan966x_pci_probe,
+ .remove = lan966x_pci_remove,
+};
+module_pci_driver(lan966x_pci_driver);
+
+MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
+MODULE_DESCRIPTION("Microchip LAN966x PCI driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/lan966x_pci.dtso b/drivers/mfd/lan966x_pci.dtso
new file mode 100644
index 000000000000..041f4319e4cd
--- /dev/null
+++ b/drivers/mfd/lan966x_pci.dtso
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Microchip UNG
+ */
+
+#include <dt-bindings/clock/microchip,lan966x.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/phy/phy-lan966x-serdes.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target-path="";
+ __overlay__ {
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pci-ep-bus@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * map @0xe2000000 (32MB) to BAR0 (CPU)
+ * map @0xe0000000 (16MB) to BAR1 (AMBA)
+ */
+ ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
+ 0xe0000000 0x01 0x00 0x00 0x1000000>;
+
+ oic: oic@e00c0120 {
+ compatible = "microchip,lan966x-oic";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <0>; /* PCI INTx assigned interrupt */
+ reg = <0xe00c0120 0x190>;
+ };
+
+ cpu_clk: cpu_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>; // CPU clock = 600MHz
+ };
+
+ ddr_clk: ddr_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>; // Fabric clock = 30MHz
+ };
+
+ sys_clk: sys_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <15625000>; // System clock = 15.625MHz
+ };
+
+ cpu_ctrl: syscon@e00c0000 {
+ compatible = "microchip,lan966x-cpu-syscon", "syscon";
+ reg = <0xe00c0000 0xa8>;
+ };
+
+ reset: reset@e200400c {
+ compatible = "microchip,lan966x-switch-reset";
+ reg = <0xe200400c 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
+ };
+
+ gpio: pinctrl@e2004064 {
+ compatible = "microchip,lan966x-pinctrl";
+ reg = <0xe2004064 0xb4>,
+ <0xe2010024 0x138>;
+ resets = <&reset 0>;
+ reset-names = "switch";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 78>;
+ interrupt-parent = <&oic>;
+ interrupt-controller;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+
+ tod_pins: tod_pins {
+ pins = "GPIO_36";
+ function = "ptpsync_1";
+ };
+
+ fc0_a_pins: fcb4-i2c-pins {
+ /* RXD, TXD */
+ pins = "GPIO_9", "GPIO_10";
+ function = "fc0_a";
+ };
+
+ };
+
+ serdes: serdes@e202c000 {
+ compatible = "microchip,lan966x-serdes";
+ reg = <0xe202c000 0x9c>,
+ <0xe2004010 0x4>;
+ #phy-cells = <2>;
+ };
+
+ mdio1: mdio@e200413c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "microchip,lan966x-miim";
+ reg = <0xe200413c 0x24>,
+ <0xe2010020 0x4>;
+
+ resets = <&reset 0>;
+ reset-names = "switch";
+
+ lan966x_phy0: ethernet-lan966x_phy@1 {
+ reg = <1>;
+ };
+
+ lan966x_phy1: ethernet-lan966x_phy@2 {
+ reg = <2>;
+ };
+ };
+
+ switch: switch@e0000000 {
+ compatible = "microchip,lan966x-switch";
+ reg = <0xe0000000 0x0100000>,
+ <0xe2000000 0x0800000>;
+ reg-names = "cpu", "gcb";
+
+ interrupt-parent = <&oic>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+ <9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "xtr", "ana";
+
+ resets = <&reset 0>;
+ reset-names = "switch";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tod_pins>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ phy-handle = <&lan966x_phy0>;
+
+ reg = <0>;
+ phy-mode = "gmii";
+ phys = <&serdes 0 CU(0)>;
+ };
+
+ port1: port@1 {
+ phy-handle = <&lan966x_phy1>;
+
+ reg = <1>;
+ phy-mode = "gmii";
+ phys = <&serdes 1 CU(1)>;
+ };
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index eff7f5df08e2..9933f245b781 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -6241,6 +6241,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
+DECLARE_PCI_FIXUP_FINAL(0x1055, 0x9660, of_pci_make_dev_node);
/*
* Devices known to require a longer delay before first config space access
--
2.44.0
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^ permalink raw reply related [relevance 5%]
* Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6
2024-04-30 0:01 0% ` Dragan Simic
@ 2024-04-30 10:46 0% ` Andre Przywara
2024-04-30 11:10 0% ` Dragan Simic
0 siblings, 1 reply; 200+ results
From: Andre Przywara @ 2024-04-30 10:46 UTC (permalink / raw)
To: Dragan Simic
Cc: linux-sunxi, wens, jernej.skrabec, samuel, linux-arm-kernel,
devicetree, robh, krzk+dt, conor+dt, linux-kernel
On Tue, 30 Apr 2024 02:01:42 +0200
Dragan Simic <dsimic@manjaro.org> wrote:
Hi Dragan,
> Hello Andre,
>
> On 2024-04-30 01:10, Andre Przywara wrote:
> > On Sun, 28 Apr 2024 13:40:36 +0200
> > Dragan Simic <dsimic@manjaro.org> wrote:
> >
> >> Add missing cache information to the Allwinner H6 SoC dtsi, to allow
> >> the userspace, which includes lscpu(1) that uses the virtual files
> >> provided
> >> by the kernel under the /sys/devices/system/cpu directory, to display
> >> the
> >> proper H6 cache information.
> >>
> >> Adding the cache information to the H6 SoC dtsi also makes the
> >> following
> >> warning message in the kernel log go away:
> >>
> >> cacheinfo: Unable to detect cache hierarchy for CPU 0
> >>
> >> The cache parameters for the H6 dtsi were obtained and partially
> >> derived
> >> by hand from the cache size and layout specifications found in the
> >> following
> >> datasheets and technical reference manuals:
> >>
> >> - Allwinner H6 V200 datasheet, version 1.1
> >> - ARM Cortex-A53 revision r0p3 TRM, version E
> >>
> >> For future reference, here's a brief summary of the documentation:
> >>
> >> - All caches employ the 64-byte cache line length
> >> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative
> >> instruction
> >> cache and 32 KB of L1 4-way, set-associative data cache
> >> - The entire SoC has 512 KB of unified L2 16-way, set-associative
> >> cache
> >>
> >> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
> >
> > I can confirm that the data below matches the manuals, but also the
> > decoding of the architectural cache type registers (CCSIDR_EL1):
> > L1D: 32 KB: 128 sets, 4 way associative, 64 bytes/line
> > L1I: 32 KB: 256 sets, 2 way associative, 64 bytes/line
> > L2: 512 KB: 512 sets, 16 way associative, 64 bytes/line
>
> Thank you very much for reviewing my patch in such a detailed way!
> It's good to know that the values in the Allwinner datasheets match
> with the observed reality, so to speak. :)
YW, and yes, I like to double check things when it comes to Allwinner
documentation ;-) And it was comparably easy for this problem.
Out of curiosity: what triggered that patch? Trying to get rid of false
warning/error messages?
And do you plan to address the H616 as well? It's a bit more tricky there,
since there are two die revisions out: one with 256(?)KB of L2, one with
1MB(!). We know how to tell them apart, so I could provide some TF-A code
to patch that up in the DT. The kernel DT copy could go with 256KB then.
Cheers,
Andre.
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v7 0/2] modify Signed-off-by field
[not found] ` <CAK=2Bxt=WK4AdktNZDN2iXjk3ga9WRqUm9JQHoNjRnrW8hVt0Q@mail.gmail.com>
@ 2024-04-30 10:21 0% ` Paul Menzel
0 siblings, 0 replies; 200+ results
From: Paul Menzel @ 2024-04-30 10:21 UTC (permalink / raw)
To: Chia Li Hung
Cc: robh+dt, devicetree, conor+dt, linux-aspeed, openbmc,
linux-kernel, Kelly Hung, joel, krzysztof.kozlowski+dt,
Allenyy_Hsu, linux-arm-kernel
Dear Chia,
Thank you for your reply. I am sorry, this causes so much trouble.
Am 30.04.24 um 12:04 schrieb Chia Li Hung:
> Paul Menzel 於 2024年4月30日 週二 下午2:48寫道：
>> Am 30.04.24 um 06:58 schrieb Kelly Hung:
>>> For the warning message:
>>> From: Kelly Hung '<ppighouse@gmail.com>' != 'Signed-off-by: Kelly Hung <Kelly_Hung@asus.com>'
>>>
>>> I replaced Kelly_Hung@asus.com with my private Gmail account.
>>>
>>> Due to a security issue with ASUS's mail server, I am unable to use
>>> ASUS's mail system to send patches out from my build server.
>>> So I executed git send-email using my private gmail account.
>>
>> To put light on ASUS’ upstream work, using your company address would be
>> nice in my opinion. Do you have it configured everything in git
>> (`~/.gitconfig`)?
>>
>> git config --global user.name "Kelly Hung"
>> git config --global user.email Kelly_Hung@asus.com
> Below is my git configuration.
> [user]
> name = Kelly Hung
> email = Kelly_Hung@asus.com
> [sendemail]
> smtpserver = smtp.gmail.com
> smtpEncryption = tls
> smtpUser = ppighouse@gmail.com
> smtpServerPort = 587
>
> I made sure the "From" value after executing git format-patch was my ASUS
> email address.
>
> From: Kelly Hung <Kelly_Hung@asus.com>
> Date: Thu, 29 Feb 2024 16:45:02 +0800
> Subject: [PATCH v7 1/2] dt-bindings: arm: aspeed: add ASUS X4TF board
>
> Since my smtp server is Gmail, when I run send-gmail it replaces my "From"
> value with the Gmail account. I asked ASUS IT for assistance today and
> tried to get an SMTP acount.
*A thing you should know if you are using multiple email accounts with
`git send-email`* [1] says to use
git send-email --from ppighouse@gmail.com 000*.patch
Kind regards,
Paul
[1]: https://sjp38.github.io/post/git_send_email_multiple_email_caution/
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^ permalink raw reply [relevance 0%]
* Re: [PATCH] ARM: multi_v7_defconfig: Select CONFIG_USB_ONBOARD_DEV as built-in
2024-04-30 6:28 0% ` Alexander Stein
@ 2024-04-30 7:52 0% ` Arnd Bergmann
0 siblings, 1 reply; 200+ results
From: Arnd Bergmann @ 2024-04-30 7:52 UTC (permalink / raw)
To: Alexander Stein, Fabio Estevam
Cc: linux-arm-kernel, Mark Brown, javier.carrasco, Fabio Estevam
On Tue, Apr 30, 2024, at 08:28, Alexander Stein wrote:
> Am Dienstag, 30. April 2024, 00:09:52 CEST schrieb Fabio Estevam:
>> Hi Arnd,
>>
>> On Mon, Apr 8, 2024 at 11:03 AM Fabio Estevam <festevam@gmail.com> wrote:
>> >
>> > From: Fabio Estevam <festevam@denx.de>
>> >
>> > Selecting CONFIG_USB_ONBOARD_DEV as a module may cause the following
>> > run-time error when probing a USB2514 hub on a imx6q-udoo board:
>> >
>> > usb 1-1: device not accepting address 5, error -71
>> > usb usb1-port1: unable to enumerate USB device
>> >
>> > Fix this issue by selecting CONFIG_USB_ONBOARD_DEV as built-in so
>> > that the USB hub reset line and clock can be activated earlier.
>> >
>> > Signed-off-by: Fabio Estevam <festevam@denx.de>
>> > ---
>> > Here is the imx6q-udoo boot log from Mark's farm that shows the problem:
>> >
>> > https://storage.kernelci.org/next/master/next-20240408/arm/multi_v7_defconfig/gcc-10/lab-broonie/baseline-imx6dl-udoo.html
>
> Despite the change to the defconfig. If this driver causes problems when
> being built as module, shouldn't it be bool instead of tristate then?
It does sound like this is something the kernel should be able to
get to work properly in some form, but I don't think making it
a 'bool' symbol is the correct answer here: if CONFIG_USB is
set to =m, it would be impossible to include USB_ONBOARD_DEV
in this case.
Fabio, can you explain how making it built-in addresses the
problem here? I assume this is related to probe order, so I
wonder if it's just a matter of making the usb hub driver
properly handle -EPROBE_DEFER until the onboard dev has been
initialized.
Arnd
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^ permalink raw reply [relevance 0%]
* [PATCH 3/3] media: bcm2835-unicam: Do not replace IRQ retcode during probe
@ 2024-04-30 7:51 7% ` Ricardo Ribalda
2024-05-06 18:03 0% ` Laurent Pinchart
0 siblings, 1 reply; 200+ results
From: Ricardo Ribalda @ 2024-04-30 7:51 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden
Cc: linux-media, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Hans Verkuil, Ricardo Ribalda
Use the error code generated by platform_get_irq() and
devm_request_irq() as the error code of probe().
It will give a more accurate reason of why it failed.
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
---
drivers/media/platform/broadcom/bcm2835-unicam.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/media/platform/broadcom/bcm2835-unicam.c b/drivers/media/platform/broadcom/bcm2835-unicam.c
index b2b23d24da19..0b2729bf4a36 100644
--- a/drivers/media/platform/broadcom/bcm2835-unicam.c
+++ b/drivers/media/platform/broadcom/bcm2835-unicam.c
@@ -2660,17 +2660,13 @@ static int unicam_probe(struct platform_device *pdev)
}
ret = platform_get_irq(pdev, 0);
- if (ret < 0) {
- if (ret != -EPROBE_DEFER)
- ret = -EINVAL;
+ if (ret < 0)
goto err_unicam_put;
- }
ret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,
"unicam_capture0", unicam);
if (ret) {
dev_err(&pdev->dev, "Unable to request interrupt\n");
- ret = -EINVAL;
goto err_unicam_put;
}
--
2.44.0.769.g3c40516874-goog
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^ permalink raw reply related [relevance 7%]
* [syzbot] Monthly arm report (Apr 2024)
@ 2024-04-30 7:12 5% syzbot
0 siblings, 0 replies; 200+ results
From: syzbot @ 2024-04-30 7:12 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, syzkaller-bugs
Hello arm maintainers/developers,
This is a 31-day syzbot report for the arm subsystem.
All related reports/information can be found at:
https://syzkaller.appspot.com/upstream/s/arm
During the period, 2 new issues were detected and 0 were fixed.
In total, 7 issues are still open and 4 have been fixed so far.
Some of the still happening issues:
Ref Crashes Repro Title
<1> 1634 Yes BUG: bad usercopy in fpa_set
https://syzkaller.appspot.com/bug?extid=cb76c2983557a07cdb14
<2> 350 Yes INFO: task hung in lookup_slow (3)
https://syzkaller.appspot.com/bug?extid=7cfc6a4f6b025f710423
<3> 37 No WARNING in delayed_work_timer_fn
https://syzkaller.appspot.com/bug?extid=e13e654d315d4da1277c
<4> 18 Yes BUG: unable to handle kernel paging request in trans_pgd_create_copy
https://syzkaller.appspot.com/bug?extid=2d1f5a94167d430a3bd7
<5> 9 No WARNING in do_sve_acc
https://syzkaller.appspot.com/bug?extid=95ffb6a83b20ea7f4f55
---
This report is generated by a bot. It may contain errors.
See https://goo.gl/tpsmEJ for more information about syzbot.
syzbot engineers can be reached at syzkaller@googlegroups.com.
To disable reminders for individual bugs, reply with the following command:
#syz set <Ref> no-reminders
To change bug's subsystems, reply with:
#syz set <Ref> subsystems: new-subsystem
You may send multiple commands in a single email message.
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^ permalink raw reply [relevance 5%]
* Re: [PATCH v7 0/2] modify Signed-off-by field
2024-04-30 4:58 6% [PATCH v7 0/2] modify Signed-off-by field Kelly Hung
@ 2024-04-30 6:48 0% ` Paul Menzel
[not found] ` <CAK=2Bxt=WK4AdktNZDN2iXjk3ga9WRqUm9JQHoNjRnrW8hVt0Q@mail.gmail.com>
0 siblings, 1 reply; 200+ results
From: Paul Menzel @ 2024-04-30 6:48 UTC (permalink / raw)
To: Kelly Hung
Cc: robh+dt, devicetree, conor+dt, linux-aspeed, openbmc,
linux-kernel, Kelly Hung, joel, krzysztof.kozlowski+dt,
Allenyy_Hsu, linux-arm-kernel
Dear Kelly,
Am 30.04.24 um 06:58 schrieb Kelly Hung:
> For the warning message:
> From: Kelly Hung '<ppighouse@gmail.com>' != 'Signed-off-by: Kelly Hung <Kelly_Hung@asus.com>'
>
> I replaced Kelly_Hung@asus.com with my private Gmail account.
>
> Due to a security issue with ASUS's mail server, I am unable to use
> ASUS's mail system to send patches out from my build server.
> So I executed git send-email using my private gmail account.
To put light on ASUS’ upstream work, using your company address would be
nice in my opinion. Do you have it configured everything in git
(`~/.gitconfig`)?
git config --global user.name "Kelly Hung"
git config --global user.email Kelly_Hung@asus.com
Then `git format-patch` and `git send-email` should put
From: Kelly Hung <Kelly_Hung@asus.com>
at the top of the message.
Kind regards,
Paul
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^ permalink raw reply [relevance 0%]
* Re: [PATCH] ARM: multi_v7_defconfig: Select CONFIG_USB_ONBOARD_DEV as built-in
2024-04-29 22:09 0% ` Fabio Estevam
@ 2024-04-30 6:28 0% ` Alexander Stein
2024-04-30 7:52 0% ` Arnd Bergmann
0 siblings, 1 reply; 200+ results
From: Alexander Stein @ 2024-04-30 6:28 UTC (permalink / raw)
To: Fabio Estevam
Cc: arnd, linux-arm-kernel, broonie, javier.carrasco,
linux-arm-kernel, Fabio Estevam
Hi,
Am Dienstag, 30. April 2024, 00:09:52 CEST schrieb Fabio Estevam:
> Hi Arnd,
>
> On Mon, Apr 8, 2024 at 11:03 AM Fabio Estevam <festevam@gmail.com> wrote:
> >
> > From: Fabio Estevam <festevam@denx.de>
> >
> > Selecting CONFIG_USB_ONBOARD_DEV as a module may cause the following
> > run-time error when probing a USB2514 hub on a imx6q-udoo board:
> >
> > usb 1-1: device not accepting address 5, error -71
> > usb usb1-port1: unable to enumerate USB device
> >
> > Fix this issue by selecting CONFIG_USB_ONBOARD_DEV as built-in so
> > that the USB hub reset line and clock can be activated earlier.
> >
> > Signed-off-by: Fabio Estevam <festevam@denx.de>
> > ---
> > Here is the imx6q-udoo boot log from Mark's farm that shows the problem:
> >
> > https://storage.kernelci.org/next/master/next-20240408/arm/multi_v7_defconfig/gcc-10/lab-broonie/baseline-imx6dl-udoo.html
>
> A gentle ping.
Despite the change to the defconfig. If this driver causes problems when
being built as module, shouldn't it be bool instead of tristate then?
Best regards,
Alexander
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 5/5] PCI: kirin: Convert to agnostic GPIO API
2024-04-29 10:23 16% ` [PATCH v3 5/5] PCI: kirin: " Andy Shevchenko
@ 2024-04-30 5:16 0% ` Manivannan Sadhasivam
0 siblings, 0 replies; 200+ results
From: Manivannan Sadhasivam @ 2024-04-30 5:16 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Frank Li, Krzysztof Wilczyński, Uwe Kleine-König,
linux-omap, linux-pci, linux-arm-kernel, linux-kernel, imx,
linux-amlogic, linux-arm-msm, linux-tegra, Vignesh Raghavendra,
Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár
On Mon, Apr 29, 2024 at 01:23:22PM +0300, Andy Shevchenko wrote:
> The of_gpio.h is going to be removed. In preparation of that convert
> the driver to the agnostic API.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> drivers/pci/controller/dwc/pcie-kirin.c | 105 ++++++++----------------
> 1 file changed, 35 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
> index d5523f302102..d1f54f188e71 100644
> --- a/drivers/pci/controller/dwc/pcie-kirin.c
> +++ b/drivers/pci/controller/dwc/pcie-kirin.c
> @@ -12,12 +12,10 @@
> #include <linux/compiler.h>
> #include <linux/delay.h>
> #include <linux/err.h>
> -#include <linux/gpio.h>
> #include <linux/gpio/consumer.h>
> #include <linux/interrupt.h>
> #include <linux/mfd/syscon.h>
> #include <linux/of.h>
> -#include <linux/of_gpio.h>
> #include <linux/of_pci.h>
> #include <linux/phy/phy.h>
> #include <linux/pci.h>
> @@ -78,16 +76,16 @@ struct kirin_pcie {
> void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */
>
> /* DWC PERST# */
> - int gpio_id_dwc_perst;
> + struct gpio_desc *id_dwc_perst_gpio;
>
> /* Per-slot PERST# */
> int num_slots;
> - int gpio_id_reset[MAX_PCI_SLOTS];
> + struct gpio_desc *id_reset_gpio[MAX_PCI_SLOTS];
> const char *reset_names[MAX_PCI_SLOTS];
>
> /* Per-slot clkreq */
> int n_gpio_clkreq;
> - int gpio_id_clkreq[MAX_PCI_SLOTS];
> + struct gpio_desc *id_clkreq_gpio[MAX_PCI_SLOTS];
> const char *clkreq_names[MAX_PCI_SLOTS];
> };
>
> @@ -381,15 +379,20 @@ static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie,
> pcie->n_gpio_clkreq = ret;
>
> for (i = 0; i < pcie->n_gpio_clkreq; i++) {
> - pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node,
> - "hisilicon,clken-gpios", i);
> - if (pcie->gpio_id_clkreq[i] < 0)
> - return pcie->gpio_id_clkreq[i];
> + pcie->id_clkreq_gpio[i] = devm_gpiod_get_index(dev,
> + "hisilicon,clken", i,
> + GPIOD_OUT_LOW);
> + if (IS_ERR(pcie->id_clkreq_gpio[i]))
> + return dev_err_probe(dev, PTR_ERR(pcie->id_clkreq_gpio[i]),
> + "unable to get a valid clken gpio\n");
>
> pcie->clkreq_names[i] = devm_kasprintf(dev, GFP_KERNEL,
> "pcie_clkreq_%d", i);
> if (!pcie->clkreq_names[i])
> return -ENOMEM;
> +
> + gpiod_set_consumer_name(pcie->id_clkreq_gpio[i],
> + pcie->clkreq_names[i]);
> }
>
> return 0;
> @@ -407,10 +410,16 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
> for_each_available_child_of_node(parent, child) {
> i = pcie->num_slots;
>
> - pcie->gpio_id_reset[i] = of_get_named_gpio(child,
> - "reset-gpios", 0);
> - if (pcie->gpio_id_reset[i] < 0)
> - continue;
> + pcie->id_reset_gpio[i] = devm_fwnode_gpiod_get_index(dev,
> + of_fwnode_handle(child),
> + "reset", 0, GPIOD_OUT_LOW,
> + NULL);
> + if (IS_ERR(pcie->id_reset_gpio[i])) {
> + if (PTR_ERR(pcie->id_reset_gpio[i]) == -ENOENT)
> + continue;
> + return dev_err_probe(dev, PTR_ERR(pcie->id_reset_gpio[i]),
> + "unable to get a valid reset gpio\n");
> + }
>
> pcie->num_slots++;
> if (pcie->num_slots > MAX_PCI_SLOTS) {
> @@ -434,6 +443,9 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
> ret = -ENOMEM;
> goto put_node;
> }
> +
> + gpiod_set_consumer_name(pcie->id_reset_gpio[i],
> + pcie->reset_names[i]);
> }
> }
>
> @@ -463,14 +475,11 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
> return PTR_ERR(kirin_pcie->apb);
>
> /* pcie internal PERST# gpio */
> - kirin_pcie->gpio_id_dwc_perst = of_get_named_gpio(dev->of_node,
> - "reset-gpios", 0);
> - if (kirin_pcie->gpio_id_dwc_perst == -EPROBE_DEFER) {
> - return -EPROBE_DEFER;
> - } else if (!gpio_is_valid(kirin_pcie->gpio_id_dwc_perst)) {
> - dev_err(dev, "unable to get a valid gpio pin\n");
> - return -ENODEV;
> - }
> + kirin_pcie->id_dwc_perst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
> + if (IS_ERR(kirin_pcie->id_dwc_perst_gpio))
> + return dev_err_probe(dev, PTR_ERR(kirin_pcie->id_dwc_perst_gpio),
> + "unable to get a valid gpio pin\n");
> + gpiod_set_consumer_name(kirin_pcie->id_dwc_perst_gpio, "pcie_perst_bridge");
>
> ret = kirin_pcie_get_gpio_enable(kirin_pcie, pdev);
> if (ret)
> @@ -553,7 +562,7 @@ static int kirin_pcie_add_bus(struct pci_bus *bus)
>
> /* Send PERST# to each slot */
> for (i = 0; i < kirin_pcie->num_slots; i++) {
> - ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1);
> + ret = gpiod_direction_output_raw(kirin_pcie->id_reset_gpio[i], 1);
> if (ret) {
> dev_err(pci->dev, "PERST# %s error: %d\n",
> kirin_pcie->reset_names[i], ret);
> @@ -623,44 +632,6 @@ static int kirin_pcie_host_init(struct dw_pcie_rp *pp)
> return 0;
> }
>
> -static int kirin_pcie_gpio_request(struct kirin_pcie *kirin_pcie,
> - struct device *dev)
> -{
> - int ret, i;
> -
> - for (i = 0; i < kirin_pcie->num_slots; i++) {
> - if (!gpio_is_valid(kirin_pcie->gpio_id_reset[i])) {
> - dev_err(dev, "unable to get a valid %s gpio\n",
> - kirin_pcie->reset_names[i]);
> - return -ENODEV;
> - }
> -
> - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i],
> - kirin_pcie->reset_names[i]);
> - if (ret)
> - return ret;
> - }
> -
> - for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) {
> - if (!gpio_is_valid(kirin_pcie->gpio_id_clkreq[i])) {
> - dev_err(dev, "unable to get a valid %s gpio\n",
> - kirin_pcie->clkreq_names[i]);
> - return -ENODEV;
> - }
> -
> - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i],
> - kirin_pcie->clkreq_names[i]);
> - if (ret)
> - return ret;
> -
> - ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0);
> - if (ret)
> - return ret;
> - }
> -
> - return 0;
> -}
> -
> static const struct dw_pcie_ops kirin_dw_pcie_ops = {
> .read_dbi = kirin_pcie_read_dbi,
> .write_dbi = kirin_pcie_write_dbi,
> @@ -680,7 +651,7 @@ static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie)
> return hi3660_pcie_phy_power_off(kirin_pcie);
>
> for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++)
> - gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 1);
> + gpiod_direction_output_raw(kirin_pcie->id_clkreq_gpio[i], 1);
>
> phy_power_off(kirin_pcie->phy);
> phy_exit(kirin_pcie->phy);
> @@ -707,10 +678,6 @@ static int kirin_pcie_power_on(struct platform_device *pdev,
> if (IS_ERR(kirin_pcie->phy))
> return PTR_ERR(kirin_pcie->phy);
>
> - ret = kirin_pcie_gpio_request(kirin_pcie, dev);
> - if (ret)
> - return ret;
> -
> ret = phy_init(kirin_pcie->phy);
> if (ret)
> goto err;
> @@ -723,11 +690,9 @@ static int kirin_pcie_power_on(struct platform_device *pdev,
> /* perst assert Endpoint */
> usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
>
> - if (!gpio_request(kirin_pcie->gpio_id_dwc_perst, "pcie_perst_bridge")) {
> - ret = gpio_direction_output(kirin_pcie->gpio_id_dwc_perst, 1);
> - if (ret)
> - goto err;
> - }
> + ret = gpiod_direction_output_raw(kirin_pcie->id_dwc_perst_gpio, 1);
> + if (ret)
> + goto err;
>
> usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
>
> --
> 2.43.0.rc1.1336.g36b5255a03ac
>
--
மணிவண்ணன் சதாசிவம்
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^ permalink raw reply [relevance 0%]
* [PATCH v7 0/2] modify Signed-off-by field
@ 2024-04-30 4:58 6% Kelly Hung
2024-04-30 6:48 0% ` Paul Menzel
0 siblings, 1 reply; 200+ results
From: Kelly Hung @ 2024-04-30 4:58 UTC (permalink / raw)
To: robh+dt
Cc: krzysztof.kozlowski+dt, conor+dt, joel, andrew, devicetree,
linux-arm-kernel, linux-aspeed, linux-kernel, openbmc,
kelly_hung, Allenyy_Hsu, Kelly Hung
For the warning message:
From: Kelly Hung '<ppighouse@gmail.com>' != 'Signed-off-by: Kelly Hung
<Kelly_Hung@asus.com>'
I replaced Kelly_Hung@asus.com with my private Gmail account.
Due to a security issue with ASUS's mail server, I am unable to use
ASUS's mail system to send patches out from my build server.
So I executed git send-email using my private gmail accoutt.
Kelly Hung (2):
dt-bindings: arm: aspeed: add ASUS X4TF board
ARM: dts: aspeed: x4tf: Add dts for asus x4tf project
.../bindings/arm/aspeed/aspeed.yaml | 1 +
arch/arm/boot/dts/aspeed/Makefile | 1 +
.../boot/dts/aspeed/aspeed-bmc-asus-x4tf.dts | 581 ++++++++++++++++++
3 files changed, 583 insertions(+)
create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asus-x4tf.dts
--
2.25.1
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^ permalink raw reply [relevance 6%]
* Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6
2024-04-29 23:10 0% ` Andre Przywara
@ 2024-04-30 0:01 0% ` Dragan Simic
2024-04-30 10:46 0% ` Andre Przywara
0 siblings, 1 reply; 200+ results
From: Dragan Simic @ 2024-04-30 0:01 UTC (permalink / raw)
To: Andre Przywara
Cc: linux-sunxi, wens, jernej.skrabec, samuel, linux-arm-kernel,
devicetree, robh, krzk+dt, conor+dt, linux-kernel
Hello Andre,
On 2024-04-30 01:10, Andre Przywara wrote:
> On Sun, 28 Apr 2024 13:40:36 +0200
> Dragan Simic <dsimic@manjaro.org> wrote:
>
>> Add missing cache information to the Allwinner H6 SoC dtsi, to allow
>> the userspace, which includes lscpu(1) that uses the virtual files
>> provided
>> by the kernel under the /sys/devices/system/cpu directory, to display
>> the
>> proper H6 cache information.
>>
>> Adding the cache information to the H6 SoC dtsi also makes the
>> following
>> warning message in the kernel log go away:
>>
>> cacheinfo: Unable to detect cache hierarchy for CPU 0
>>
>> The cache parameters for the H6 dtsi were obtained and partially
>> derived
>> by hand from the cache size and layout specifications found in the
>> following
>> datasheets and technical reference manuals:
>>
>> - Allwinner H6 V200 datasheet, version 1.1
>> - ARM Cortex-A53 revision r0p3 TRM, version E
>>
>> For future reference, here's a brief summary of the documentation:
>>
>> - All caches employ the 64-byte cache line length
>> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative
>> instruction
>> cache and 32 KB of L1 4-way, set-associative data cache
>> - The entire SoC has 512 KB of unified L2 16-way, set-associative
>> cache
>>
>> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
>
> I can confirm that the data below matches the manuals, but also the
> decoding of the architectural cache type registers (CCSIDR_EL1):
> L1D: 32 KB: 128 sets, 4 way associative, 64 bytes/line
> L1I: 32 KB: 256 sets, 2 way associative, 64 bytes/line
> L2: 512 KB: 512 sets, 16 way associative, 64 bytes/line
Thank you very much for reviewing my patch in such a detailed way!
It's good to know that the values in the Allwinner datasheets match
with the observed reality, so to speak. :)
> tinymembench results for the H6 are available here:
> https://github.com/ThomasKaiser/sbc-bench/blob/master/results/26Ph.txt
> and confirm the theory. Also ran it locally with similar results.
Here's a quick copy & paste of the most important benchmark results
from the link above, as a quick reference for anyone reading this
thread in the future, or as a data source in case the link above
becomes inaccessible at some point in the future:
==========================================================================
== Memory latency test
==
==
==
== Average time is measured for random memory accesses in the buffers
==
== of different sizes. The larger is the buffer, the more significant
==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM
==
== accesses. For extremely large buffer sizes we are expecting to see
==
== page table walk with several requests to SDRAM for almost every
==
== memory access (though 64MiB is not nearly large enough to experience
==
== this effect to its fullest).
==
==
==
== Note 1: All the numbers are representing extra time, which needs to
==
== be added to L1 cache latency. The cycle timings for L1 cache
==
== latency can be usually found in the processor documentation.
==
== Note 2: Dual random read means that we are simultaneously performing
==
== two independent memory accesses at a time. In the case if
==
== the memory subsystem can't handle multiple outstanding
==
== requests, dual random read has the same timings as two
==
== single reads performed one after another.
==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 3.8 ns / 6.5 ns
131072 : 5.8 ns / 9.1 ns
262144 : 6.9 ns / 10.2 ns
524288 : 7.8 ns / 11.2 ns
1048576 : 74.3 ns / 114.5 ns
2097152 : 110.5 ns / 148.1 ns
4194304 : 132.6 ns / 164.5 ns
8388608 : 144.0 ns / 172.3 ns
16777216 : 151.5 ns / 177.3 ns
33554432 : 156.3 ns / 180.7 ns
67108864 : 158.7 ns / 182.9 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 3.8 ns / 6.5 ns
131072 : 5.8 ns / 9.1 ns
262144 : 6.9 ns / 10.2 ns
524288 : 7.8 ns / 11.2 ns
1048576 : 74.3 ns / 114.5 ns
2097152 : 110.0 ns / 147.5 ns
4194304 : 127.6 ns / 158.3 ns
8388608 : 136.4 ns / 162.2 ns
16777216 : 141.2 ns / 165.6 ns
33554432 : 143.7 ns / 168.4 ns
67108864 : 144.9 ns / 168.9 ns
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Thanks!
>> ---
>> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 37
>> ++++++++++++++++++++
>> 1 file changed, 37 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> index d11e5041bae9..1a63066396e8 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> @@ -29,36 +29,73 @@ cpu0: cpu@0 {
>> clocks = <&ccu CLK_CPUX>;
>> clock-latency-ns = <244144>; /* 8 32k periods */
>> #cooling-cells = <2>;
>> + i-cache-size = <0x8000>;
>> + i-cache-line-size = <64>;
>> + i-cache-sets = <256>;
>> + d-cache-size = <0x8000>;
>> + d-cache-line-size = <64>;
>> + d-cache-sets = <128>;
>> + next-level-cache = <&l2_cache>;
>> };
>>
>> cpu1: cpu@1 {
>> compatible = "arm,cortex-a53";
>> device_type = "cpu";
>> reg = <1>;
>> enable-method = "psci";
>> clocks = <&ccu CLK_CPUX>;
>> clock-latency-ns = <244144>; /* 8 32k periods */
>> #cooling-cells = <2>;
>> + i-cache-size = <0x8000>;
>> + i-cache-line-size = <64>;
>> + i-cache-sets = <256>;
>> + d-cache-size = <0x8000>;
>> + d-cache-line-size = <64>;
>> + d-cache-sets = <128>;
>> + next-level-cache = <&l2_cache>;
>> };
>>
>> cpu2: cpu@2 {
>> compatible = "arm,cortex-a53";
>> device_type = "cpu";
>> reg = <2>;
>> enable-method = "psci";
>> clocks = <&ccu CLK_CPUX>;
>> clock-latency-ns = <244144>; /* 8 32k periods */
>> #cooling-cells = <2>;
>> + i-cache-size = <0x8000>;
>> + i-cache-line-size = <64>;
>> + i-cache-sets = <256>;
>> + d-cache-size = <0x8000>;
>> + d-cache-line-size = <64>;
>> + d-cache-sets = <128>;
>> + next-level-cache = <&l2_cache>;
>> };
>>
>> cpu3: cpu@3 {
>> compatible = "arm,cortex-a53";
>> device_type = "cpu";
>> reg = <3>;
>> enable-method = "psci";
>> clocks = <&ccu CLK_CPUX>;
>> clock-latency-ns = <244144>; /* 8 32k periods */
>> #cooling-cells = <2>;
>> + i-cache-size = <0x8000>;
>> + i-cache-line-size = <64>;
>> + i-cache-sets = <256>;
>> + d-cache-size = <0x8000>;
>> + d-cache-line-size = <64>;
>> + d-cache-sets = <128>;
>> + next-level-cache = <&l2_cache>;
>> + };
>> +
>> + l2_cache: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + cache-size = <0x80000>;
>> + cache-line-size = <64>;
>> + cache-sets = <512>;
>> };
>> };
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6
2024-04-28 11:40 5% ` [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6 Dragan Simic
2024-04-28 16:21 0% ` Jernej Škrabec
@ 2024-04-29 23:10 0% ` Andre Przywara
2024-04-30 0:01 0% ` Dragan Simic
1 sibling, 1 reply; 200+ results
From: Andre Przywara @ 2024-04-29 23:10 UTC (permalink / raw)
To: Dragan Simic
Cc: linux-sunxi, wens, jernej.skrabec, samuel, linux-arm-kernel,
devicetree, robh, krzk+dt, conor+dt, linux-kernel
On Sun, 28 Apr 2024 13:40:36 +0200
Dragan Simic <dsimic@manjaro.org> wrote:
> Add missing cache information to the Allwinner H6 SoC dtsi, to allow
> the userspace, which includes lscpu(1) that uses the virtual files provided
> by the kernel under the /sys/devices/system/cpu directory, to display the
> proper H6 cache information.
>
> Adding the cache information to the H6 SoC dtsi also makes the following
> warning message in the kernel log go away:
>
> cacheinfo: Unable to detect cache hierarchy for CPU 0
>
> The cache parameters for the H6 dtsi were obtained and partially derived
> by hand from the cache size and layout specifications found in the following
> datasheets and technical reference manuals:
>
> - Allwinner H6 V200 datasheet, version 1.1
> - ARM Cortex-A53 revision r0p3 TRM, version E
>
> For future reference, here's a brief summary of the documentation:
>
> - All caches employ the 64-byte cache line length
> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction
> cache and 32 KB of L1 4-way, set-associative data cache
> - The entire SoC has 512 KB of unified L2 16-way, set-associative cache
>
> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
I can confirm that the data below matches the manuals, but also the
decoding of the architectural cache type registers (CCSIDR_EL1):
L1D: 32 KB: 128 sets, 4 way associative, 64 bytes/line
L1I: 32 KB: 256 sets, 2 way associative, 64 bytes/line
L2: 512 KB: 512 sets, 16 way associative, 64 bytes/line
tinymembench results for the H6 are available here:
https://github.com/ThomasKaiser/sbc-bench/blob/master/results/26Ph.txt
and confirm the theory. Also ran it locally with similar results.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Thanks,
Andre
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 37 ++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index d11e5041bae9..1a63066396e8 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -29,36 +29,73 @@ cpu0: cpu@0 {
> clocks = <&ccu CLK_CPUX>;
> clock-latency-ns = <244144>; /* 8 32k periods */
> #cooling-cells = <2>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_cache>;
> };
>
> cpu1: cpu@1 {
> compatible = "arm,cortex-a53";
> device_type = "cpu";
> reg = <1>;
> enable-method = "psci";
> clocks = <&ccu CLK_CPUX>;
> clock-latency-ns = <244144>; /* 8 32k periods */
> #cooling-cells = <2>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_cache>;
> };
>
> cpu2: cpu@2 {
> compatible = "arm,cortex-a53";
> device_type = "cpu";
> reg = <2>;
> enable-method = "psci";
> clocks = <&ccu CLK_CPUX>;
> clock-latency-ns = <244144>; /* 8 32k periods */
> #cooling-cells = <2>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_cache>;
> };
>
> cpu3: cpu@3 {
> compatible = "arm,cortex-a53";
> device_type = "cpu";
> reg = <3>;
> enable-method = "psci";
> clocks = <&ccu CLK_CPUX>;
> clock-latency-ns = <244144>; /* 8 32k periods */
> #cooling-cells = <2>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_cache>;
> + };
> +
> + l2_cache: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + cache-size = <0x80000>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> };
> };
>
>
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^ permalink raw reply [relevance 0%]
* Re: [PATCH] ARM: multi_v7_defconfig: Select CONFIG_USB_ONBOARD_DEV as built-in
@ 2024-04-29 22:09 0% ` Fabio Estevam
2024-04-30 6:28 0% ` Alexander Stein
0 siblings, 1 reply; 200+ results
From: Fabio Estevam @ 2024-04-29 22:09 UTC (permalink / raw)
To: arnd; +Cc: broonie, javier.carrasco, linux-arm-kernel, Fabio Estevam
Hi Arnd,
On Mon, Apr 8, 2024 at 11:03 AM Fabio Estevam <festevam@gmail.com> wrote:
>
> From: Fabio Estevam <festevam@denx.de>
>
> Selecting CONFIG_USB_ONBOARD_DEV as a module may cause the following
> run-time error when probing a USB2514 hub on a imx6q-udoo board:
>
> usb 1-1: device not accepting address 5, error -71
> usb usb1-port1: unable to enumerate USB device
>
> Fix this issue by selecting CONFIG_USB_ONBOARD_DEV as built-in so
> that the USB hub reset line and clock can be activated earlier.
>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
> ---
> Here is the imx6q-udoo boot log from Mark's farm that shows the problem:
>
> https://storage.kernelci.org/next/master/next-20240408/arm/multi_v7_defconfig/gcc-10/lab-broonie/baseline-imx6dl-udoo.html
A gentle ping.
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 11/11] PCI: imx6: Add i.MX8Q PCIe support
2024-04-27 11:47 0% ` Manivannan Sadhasivam
@ 2024-04-29 17:56 0% ` Frank Li
0 siblings, 0 replies; 200+ results
From: Frank Li @ 2024-04-29 17:56 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Krzysztof Kozlowski, Conor Dooley, linux-pci, imx,
linux-arm-kernel, linux-kernel, bpf, devicetree
On Sat, Apr 27, 2024 at 05:17:36PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Apr 02, 2024 at 10:33:47AM -0400, Frank Li wrote:
> > From: Richard Zhu <hongxing.zhu@nxp.com>
> >
> > Add i.MX8Q (i.MX8QM, i.MX8QXP and i.MX8DXL) PCIe support.
> >
>
> Add some info like IP version, PCIe Gen, how different the code support
> comparted to previous SoCs etc...
>
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > drivers/pci/controller/dwc/pcie-imx.c | 54 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 54 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c
> > index 378808262d16b..af7c79e869e70 100644
> > --- a/drivers/pci/controller/dwc/pcie-imx.c
> > +++ b/drivers/pci/controller/dwc/pcie-imx.c
> > @@ -30,6 +30,7 @@
> > #include <linux/interrupt.h>
> > #include <linux/reset.h>
> > #include <linux/phy/phy.h>
> > +#include <linux/phy/pcie.h>
> > #include <linux/pm_domain.h>
> > #include <linux/pm_runtime.h>
> >
> > @@ -81,6 +82,7 @@ enum imx_pcie_variants {
> > IMX8MQ,
> > IMX8MM,
> > IMX8MP,
> > + IMX8Q,
> > IMX95,
> > IMX8MQ_EP,
> > IMX8MM_EP,
> > @@ -96,6 +98,7 @@ enum imx_pcie_variants {
> > #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5)
> > #define IMX_PCIE_FLAG_HAS_SERDES BIT(6)
> > #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7)
> > +#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8)
> >
> > #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
> >
> > @@ -132,6 +135,7 @@ struct imx_pcie {
> > struct regmap *iomuxc_gpr;
> > u16 msi_ctrl;
> > u32 controller_id;
> > + u32 local_addr;
> > struct reset_control *pciephy_reset;
> > struct reset_control *apps_reset;
> > struct reset_control *turnoff_reset;
> > @@ -402,6 +406,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
> > if (!drvdata->mode_mask[id])
> > id = 0;
> >
> > + /* If mode_mask is 0, means use phy driver to set mode */
> > + if (!drvdata->mode_mask[id])
> > + return;
>
> There is already a check above for 0 mode_mask. Please consolidate.
>
> > +
> > mask = drvdata->mode_mask[id];
> > val = mode << (ffs(mask) - 1);
> >
> > @@ -957,6 +965,7 @@ static void imx_pcie_ltssm_enable(struct device *dev)
> > struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> > const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
> >
> > + phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB);
> > if (drvdata->ltssm_mask)
> > regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
> > drvdata->ltssm_mask);
> > @@ -969,6 +978,7 @@ static void imx_pcie_ltssm_disable(struct device *dev)
> > struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> > const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
> >
> > + phy_set_speed(imx_pcie->phy, 0);
> > if (drvdata->ltssm_mask)
> > regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
> > drvdata->ltssm_mask, 0);
> > @@ -1104,6 +1114,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
> > goto err_clk_disable;
> > }
> >
> > + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
> > + if (ret) {
> > + dev_err(dev, "unable to set pcie PHY mode\n");
> > + goto err_phy_off;
> > + }
>
> This is not i.MX8Q specific. Please add it in a separate patch.
>
> > +
> > ret = phy_power_on(imx_pcie->phy);
> > if (ret) {
> > dev_err(dev, "waiting for PHY ready timeout!\n");
> > @@ -1154,6 +1170,28 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
> > regulator_disable(imx_pcie->vpcie);
> > }
> >
> > +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr)
> > +{
> > + struct imx_pcie *imx_pcie = to_imx_pcie(pcie);
> > + struct dw_pcie_ep *ep = &pcie->ep;
> > + struct dw_pcie_rp *pp = &pcie->pp;
> > + struct resource_entry *entry;
> > + unsigned int offset;
> > +
> > + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP))
>
> This flag should be documented in the commit message.
>
> > + return cpu_addr;
> > +
> > + if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
> > + offset = ep->phys_base;
> > + } else {
> > + entry = resource_list_first_type(&pp->bridge->windows,
> > + IORESOURCE_MEM);
>
> Check for NULL entry.
>
> > + offset = entry->res->start;
> > + }
> > +
> > + return (cpu_addr + imx_pcie->local_addr - offset);
> > +}
> > +
> > static const struct dw_pcie_host_ops imx_pcie_host_ops = {
> > .init = imx_pcie_host_init,
> > .deinit = imx_pcie_host_exit,
> > @@ -1162,6 +1200,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = {
> > static const struct dw_pcie_ops dw_pcie_ops = {
> > .start_link = imx_pcie_start_link,
> > .stop_link = imx_pcie_stop_link,
> > + .cpu_addr_fixup = imx_pcie_cpu_addr_fixup,
> > };
> >
> > static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
> > @@ -1481,6 +1520,12 @@ static int imx_pcie_probe(struct platform_device *pdev)
> > "Failed to get PCIEPHY reset control\n");
> > }
> >
> > + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) {
> > + ret = of_property_read_u32(node, "fsl,local-address", &imx_pcie->local_addr);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to get local-address");
>
> Is it OK to continue?
No, if no "fsl,local-address" for iMX8QM/QXP, address map will be wrong.
Frank
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 07/11] PCI: imx: Simplify switch-case logic by involve core_reset callback
2024-04-27 10:19 0% ` Manivannan Sadhasivam
@ 2024-04-29 16:38 0% ` Frank Li
0 siblings, 0 replies; 200+ results
From: Frank Li @ 2024-04-29 16:38 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Krzysztof Kozlowski, Conor Dooley, linux-pci, imx,
linux-arm-kernel, linux-kernel, bpf, devicetree
On Sat, Apr 27, 2024 at 03:49:50PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Apr 02, 2024 at 10:33:43AM -0400, Frank Li wrote:
> > Instead of using the switch case statement to assert/dassert the core reset
> > handled by this driver itself, let's introduce a new callback core_reset()
> > and define it for platforms that require it. This simplifies the code.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > drivers/pci/controller/dwc/pcie-imx.c | 131 ++++++++++++++++++----------------
> > 1 file changed, 68 insertions(+), 63 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c
> > index 77dae5c3f7057..af0f960f28757 100644
> > --- a/drivers/pci/controller/dwc/pcie-imx.c
> > +++ b/drivers/pci/controller/dwc/pcie-imx.c
> > @@ -104,6 +104,7 @@ struct imx_pcie_drvdata {
> > const struct pci_epc_features *epc_features;
> > int (*init_phy)(struct imx_pcie *pcie);
> > int (*set_ref_clk)(struct imx_pcie *pcie, bool enable);
> > + int (*core_reset)(struct imx_pcie *pcie, bool assert);
> > };
> >
> > struct imx_pcie {
> > @@ -671,35 +672,72 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
> > clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
> > }
> >
> > +static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> > +{
> > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
> > + assert ? IMX6SX_GPR12_PCIE_TEST_POWERDOWN : 0);
>
> Earlier, this register was not cleared during deassert. Is if fine?
Just missed power off cycle, it is functional. But I think it's better
to match old logic to let review easily.
>
> > + /* Force PCIe PHY reset */
> > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET,
> > + assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0);
> > + return 0;
> > +}
> > +
> > +static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> > +{
> > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST,
> > + assert ? IMX6Q_GPR1_PCIE_SW_RST : 0);
> > + if (!assert)
> > + usleep_range(200, 500);
> > +
> > + return 0;
> > +}
> > +
> > +static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> > +{
> > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD,
> > + assert ? IMX6Q_GPR1_PCIE_TEST_PD : 0);
> > +
> > + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN,
> > + assert ? 0 : IMX6Q_GPR1_PCIE_REF_CLK_EN);
> > +
>
> Same comment as above.
>
> > + return 0;
> > +}
> > +
> > +static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> > +{
> > + struct dw_pcie *pci = imx_pcie->pci;
> > + struct device *dev = pci->dev;
> > +
> > + if (assert)
> > + return 0;
> > +
> > + /*
> > + * Workaround for ERR010728, failure of PCI-e PLL VCO to oscillate, especially when cold.
>
> What does 'especially when cold' means? I know it is an old comment, but still
> it is not very clear.
>
> > + * This turns off "Duty-cycle Corrector" and other mysterious undocumented things.
>
> Same comment as previous patch.
It is copy from old comments. How about keep the same here. And improve at
difference patch? I copied key content from formal errata.
/*
Workaround for ERR010728 (IMX7DS_2N09P, Rev. 1.1, 4/2023):
PCIe: PLL may fail to lock under corner conditions
Initial VCO oscillation may fail under corner conditions such as cold
temperature which will cause the PCIe PLL fail to lock in the
initialization phase.
The Duty-cycle Corrector calibration must be disabled
1. De-assert the G_RST signal by clearing SRC_PCIEPHY_RCR[PCIEPHY_G_RST].
2. De-assert DCC_FB_EN by writing data “0x29” to the register address 0x306d0014.
3. Assert RX_EQS, RX_EQ_SEL by writing data “0x48” to the register address 0x306d0090.
4. Assert ATT_MODE by writing data “0xbc” to the register address 0x306d0098.
5. De-assert the CMN_RST signal by clearing register bit SRC_PCIEPHY_RCR[PCIEPHY_BTN]
*/
>
> > + */
> > +
> > + if (likely(imx_pcie->phy_base)) {
> > + /* De-assert DCC_FB_EN */
> > + writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
> > + /* Assert RX_EQS and RX_EQS_SEL */
> > + writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ,
> > + imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
> > + /* Assert ATT_MODE */
> > + writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
>
> Why does this workaround a part of core_reset handling? This function doesn't
> look like performing reset at all.
According to errata document, it should be step 2,3,4.
>
> - Mani
>
> > + } else {
> > + dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
> > + }
> > + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
> > + return 0;
> > +}
> > +
> > static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
> > {
> > reset_control_assert(imx_pcie->pciephy_reset);
> > reset_control_assert(imx_pcie->apps_reset);
> >
> > - switch (imx_pcie->drvdata->variant) {
> > - case IMX6SX:
> > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> > - IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
> > - IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
> > - /* Force PCIe PHY reset */
> > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
> > - IMX6SX_GPR5_PCIE_BTNRST_RESET,
> > - IMX6SX_GPR5_PCIE_BTNRST_RESET);
> > - break;
> > - case IMX6QP:
> > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> > - IMX6Q_GPR1_PCIE_SW_RST,
> > - IMX6Q_GPR1_PCIE_SW_RST);
> > - break;
> > - case IMX6Q:
> > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> > - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
> > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> > - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
> > - break;
> > - default:
> > - break;
> > - }
> > + if (imx_pcie->drvdata->core_reset)
> > + imx_pcie->drvdata->core_reset(imx_pcie, true);
> >
> > /* Some boards don't have PCIe reset GPIO. */
> > if (gpio_is_valid(imx_pcie->reset_gpio))
> > @@ -709,47 +747,10 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
> >
> > static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
> > {
> > - struct dw_pcie *pci = imx_pcie->pci;
> > - struct device *dev = pci->dev;
> > -
> > reset_control_deassert(imx_pcie->pciephy_reset);
> >
> > - switch (imx_pcie->drvdata->variant) {
> > - case IMX7D:
> > - /* Workaround for ERR010728, failure of PCI-e PLL VCO to
> > - * oscillate, especially when cold. This turns off "Duty-cycle
> > - * Corrector" and other mysterious undocumented things.
> > - */
> > - if (likely(imx_pcie->phy_base)) {
> > - /* De-assert DCC_FB_EN */
> > - writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
> > - imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
> > - /* Assert RX_EQS and RX_EQS_SEL */
> > - writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
> > - | PCIE_PHY_CMN_REG24_RX_EQ,
> > - imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
> > - /* Assert ATT_MODE */
> > - writel(PCIE_PHY_CMN_REG26_ATT_MODE,
> > - imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
> > - } else {
> > - dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
> > - }
> > -
> > - imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
> > - break;
> > - case IMX6SX:
> > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
> > - IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
> > - break;
> > - case IMX6QP:
> > - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> > - IMX6Q_GPR1_PCIE_SW_RST, 0);
> > -
> > - usleep_range(200, 500);
> > - break;
> > - default:
> > - break;
> > - }
> > + if (imx_pcie->drvdata->core_reset)
> > + imx_pcie->drvdata->core_reset(imx_pcie, false);
> >
> > /* Some boards don't have PCIe reset GPIO. */
> > if (gpio_is_valid(imx_pcie->reset_gpio)) {
> > @@ -1447,6 +1448,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > .init_phy = imx_pcie_init_phy,
> > .set_ref_clk = imx6q_pcie_set_ref_clk,
> > + .core_reset = imx6q_pcie_core_reset,
> > },
> > [IMX6SX] = {
> > .variant = IMX6SX,
> > @@ -1462,6 +1464,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > .init_phy = imx6sx_pcie_init_phy,
> > .set_ref_clk = imx6sx_pcie_set_ref_clk,
> > + .core_reset = imx6sx_pcie_core_reset,
> > },
> > [IMX6QP] = {
> > .variant = IMX6QP,
> > @@ -1478,6 +1481,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > .init_phy = imx_pcie_init_phy,
> > .set_ref_clk = imx6q_pcie_set_ref_clk,
> > + .core_reset = imx6qp_pcie_core_reset,
> > },
> > [IMX7D] = {
> > .variant = IMX7D,
> > @@ -1491,6 +1495,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > .init_phy = imx7d_pcie_init_phy,
> > .set_ref_clk = imx7d_pcie_set_ref_clk,
> > + .core_reset = imx7d_pcie_core_reset,
> > },
> > [IMX8MQ] = {
> > .variant = IMX8MQ,
> >
> > --
> > 2.34.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* [PATCH v7 08/16] mm/execmem, arch: convert remaining overrides of module_alloc to execmem
@ 2024-04-29 12:16 6% ` Mike Rapoport
1 sibling, 0 replies; 200+ results
From: Mike Rapoport @ 2024-04-29 12:16 UTC (permalink / raw)
To: linux-kernel
Cc: Alexandre Ghiti, Andrew Morton, Björn Töpel,
Catalin Marinas, Christophe Leroy, David S. Miller, Dinh Nguyen,
Donald Dutile, Eric Chanudet, Heiko Carstens, Helge Deller,
Huacai Chen, Kent Overstreet, Luis Chamberlain, Mark Rutland,
Masami Hiramatsu, Michael Ellerman, Mike Rapoport, Nadav Amit,
Palmer Dabbelt, Peter Zijlstra, Philippe Mathieu-Daudé,
Rick Edgecombe, Russell King, Sam Ravnborg, Song Liu,
Steven Rostedt, Thomas Bogendoerfer, Thomas Gleixner,
Will Deacon, bpf, linux-arch, linux-arm-kernel, linux-mips,
linux-mm, linux-modules, linux-parisc, linux-riscv, linux-s390,
linux-trace-kernel, linuxppc-dev, loongarch, netdev, sparclinux,
x86
From: "Mike Rapoport (IBM)" <rppt@kernel.org>
Extend execmem parameters to accommodate more complex overrides of
module_alloc() by architectures.
This includes specification of a fallback range required by arm, arm64
and powerpc, EXECMEM_MODULE_DATA type required by powerpc, support for
allocation of KASAN shadow required by s390 and x86 and support for
late initialization of execmem required by arm64.
The core implementation of execmem_alloc() takes care of suppressing
warnings when the initial allocation fails but there is a fallback range
defined.
Signed-off-by: Mike Rapoport (IBM) <rppt@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Song Liu <song@kernel.org>
---
arch/Kconfig | 8 ++++
arch/arm/kernel/module.c | 41 ++++++++++++--------
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/module.c | 55 ++++++++++++++------------
arch/powerpc/kernel/module.c | 60 +++++++++++++++++++----------
arch/s390/kernel/module.c | 54 +++++++++++---------------
arch/x86/kernel/module.c | 70 +++++++++++----------------------
include/linux/execmem.h | 30 ++++++++++++++-
include/linux/moduleloader.h | 12 ------
kernel/module/main.c | 26 +++----------
mm/execmem.c | 75 ++++++++++++++++++++++++++++++------
11 files changed, 247 insertions(+), 185 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index 65afb1de48b3..4fd0daa54e6c 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -960,6 +960,14 @@ config ARCH_WANTS_MODULES_DATA_IN_VMALLOC
For architectures like powerpc/32 which have constraints on module
allocation and need to allocate module data outside of module area.
+config ARCH_WANTS_EXECMEM_LATE
+ bool
+ help
+ For architectures that do not allocate executable memory early on
+ boot, but rather require its initialization late when there is
+ enough entropy for module space randomization, for instance
+ arm64.
+
config HAVE_IRQ_EXIT_ON_IRQ_STACK
bool
help
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index e74d84f58b77..a98fdf6ff26c 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -16,6 +16,7 @@
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/gfp.h>
+#include <linux/execmem.h>
#include <asm/sections.h>
#include <asm/smp_plat.h>
@@ -34,23 +35,31 @@
#endif
#ifdef CONFIG_MMU
-void *module_alloc(unsigned long size)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- /* Silence the initial allocation */
- if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS))
- gfp_mask |= __GFP_NOWARN;
-
- p = __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
- gfp_mask, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- if (!IS_ENABLED(CONFIG_ARM_MODULE_PLTS) || p)
- return p;
- return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
+ unsigned long fallback_start = 0, fallback_end = 0;
+
+ if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS)) {
+ fallback_start = VMALLOC_START;
+ fallback_end = VMALLOC_END;
+ }
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = MODULES_VADDR,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL_EXEC,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#endif
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7b11c98b3e84..74b34a78b7ac 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -105,6 +105,7 @@ config ARM64
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
select ARCH_WANT_LD_ORPHAN_WARN
+ select ARCH_WANTS_EXECMEM_LATE if EXECMEM
select ARCH_WANTS_NO_INSTR
select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
select ARCH_HAS_UBSAN
diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c
index e92da4da1b2a..b7a7a23f9f8f 100644
--- a/arch/arm64/kernel/module.c
+++ b/arch/arm64/kernel/module.c
@@ -20,6 +20,7 @@
#include <linux/random.h>
#include <linux/scs.h>
#include <linux/vmalloc.h>
+#include <linux/execmem.h>
#include <asm/alternative.h>
#include <asm/insn.h>
@@ -108,41 +109,47 @@ static int __init module_init_limits(void)
return 0;
}
-subsys_initcall(module_init_limits);
-void *module_alloc(unsigned long size)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- void *p = NULL;
+ unsigned long fallback_start = 0, fallback_end = 0;
+ unsigned long start = 0, end = 0;
+
+ module_init_limits();
/*
* Where possible, prefer to allocate within direct branch range of the
* kernel such that no PLTs are necessary.
*/
if (module_direct_base) {
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- module_direct_base,
- module_direct_base + SZ_128M,
- GFP_KERNEL | __GFP_NOWARN,
- PAGE_KERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- }
+ start = module_direct_base;
+ end = module_direct_base + SZ_128M;
- if (!p && module_plt_base) {
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- module_plt_base,
- module_plt_base + SZ_2G,
- GFP_KERNEL | __GFP_NOWARN,
- PAGE_KERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- }
-
- if (!p) {
- pr_warn_ratelimited("%s: unable to allocate memory\n",
- __func__);
+ if (module_plt_base) {
+ fallback_start = module_plt_base;
+ fallback_end = module_plt_base + SZ_2G;
+ }
+ } else if (module_plt_base) {
+ start = module_plt_base;
+ end = module_plt_base + SZ_2G;
}
- /* Memory is intended to be executable, reset the pointer tag. */
- return kasan_reset_tag(p);
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = start,
+ .end = end,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ },
+ };
+
+ return &execmem_info;
}
enum aarch64_reloc_op {
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index f6d6ae0a1692..ac80559015a3 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -10,6 +10,7 @@
#include <linux/vmalloc.h>
#include <linux/mm.h>
#include <linux/bug.h>
+#include <linux/execmem.h>
#include <asm/module.h>
#include <linux/uaccess.h>
#include <asm/firmware.h>
@@ -89,39 +90,56 @@ int module_finalize(const Elf_Ehdr *hdr,
return 0;
}
-static __always_inline void *
-__module_alloc(unsigned long size, unsigned long start, unsigned long end, bool nowarn)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
pgprot_t prot = strict_module_rwx_enabled() ? PAGE_KERNEL : PAGE_KERNEL_EXEC;
- gfp_t gfp = GFP_KERNEL | (nowarn ? __GFP_NOWARN : 0);
+ unsigned long fallback_start = 0, fallback_end = 0;
+ unsigned long start, end;
/*
- * Don't do huge page allocations for modules yet until more testing
- * is done. STRICT_MODULE_RWX may require extra work to support this
- * too.
+ * BOOK3S_32 and 8xx define MODULES_VADDR for text allocations and
+ * allow allocating data in the entire vmalloc space
*/
- return __vmalloc_node_range(size, 1, start, end, gfp, prot,
- VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
-void *module_alloc(unsigned long size)
-{
#ifdef MODULES_VADDR
unsigned long limit = (unsigned long)_etext - SZ_32M;
- void *ptr = NULL;
BUILD_BUG_ON(TASK_SIZE > MODULES_VADDR);
/* First try within 32M limit from _etext to avoid branch trampolines */
- if (MODULES_VADDR < PAGE_OFFSET && MODULES_END > limit)
- ptr = __module_alloc(size, limit, MODULES_END, true);
-
- if (!ptr)
- ptr = __module_alloc(size, MODULES_VADDR, MODULES_END, false);
+ if (MODULES_VADDR < PAGE_OFFSET && MODULES_END > limit) {
+ start = limit;
+ fallback_start = MODULES_VADDR;
+ fallback_end = MODULES_END;
+ } else {
+ start = MODULES_VADDR;
+ }
- return ptr;
+ end = MODULES_END;
#else
- return __module_alloc(size, VMALLOC_START, VMALLOC_END, false);
+ start = VMALLOC_START;
+ end = VMALLOC_END;
#endif
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = start,
+ .end = end,
+ .pgprot = prot,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ [EXECMEM_MODULE_DATA] = {
+ .start = VMALLOC_START,
+ .end = VMALLOC_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ },
+ },
+ };
+
+ return &execmem_info;
}
diff --git a/arch/s390/kernel/module.c b/arch/s390/kernel/module.c
index ac97a905e8cd..7fee64fdc1bb 100644
--- a/arch/s390/kernel/module.c
+++ b/arch/s390/kernel/module.c
@@ -37,41 +37,31 @@
#define PLT_ENTRY_SIZE 22
-static unsigned long get_module_load_offset(void)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- static DEFINE_MUTEX(module_kaslr_mutex);
- static unsigned long module_load_offset;
-
- if (!kaslr_enabled())
- return 0;
- /*
- * Calculate the module_load_offset the first time this code
- * is called. Once calculated it stays the same until reboot.
- */
- mutex_lock(&module_kaslr_mutex);
- if (!module_load_offset)
+ unsigned long module_load_offset = 0;
+ unsigned long start;
+
+ if (kaslr_enabled())
module_load_offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
- mutex_unlock(&module_kaslr_mutex);
- return module_load_offset;
-}
-void *module_alloc(unsigned long size)
-{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- if (PAGE_ALIGN(size) > MODULES_LEN)
- return NULL;
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- MODULES_VADDR + get_module_load_offset(),
- MODULES_END, gfp_mask, PAGE_KERNEL,
- VM_FLUSH_RESET_PERMS | VM_DEFER_KMEMLEAK,
- NUMA_NO_NODE, __builtin_return_address(0));
- if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) {
- vfree(p);
- return NULL;
- }
- return p;
+ start = MODULES_VADDR + module_load_offset;
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .flags = EXECMEM_KASAN_SHADOW,
+ .start = start,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = MODULE_ALIGN,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#ifdef CONFIG_FUNCTION_TRACER
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index e18914c0e38a..45b1a7c03379 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -19,6 +19,7 @@
#include <linux/jump_label.h>
#include <linux/random.h>
#include <linux/memory.h>
+#include <linux/execmem.h>
#include <asm/text-patching.h>
#include <asm/page.h>
@@ -36,55 +37,30 @@ do { \
} while (0)
#endif
-#ifdef CONFIG_RANDOMIZE_BASE
-static unsigned long module_load_offset;
+static struct execmem_info execmem_info __ro_after_init;
-/* Mutex protects the module_load_offset. */
-static DEFINE_MUTEX(module_kaslr_mutex);
-
-static unsigned long int get_module_load_offset(void)
-{
- if (kaslr_enabled()) {
- mutex_lock(&module_kaslr_mutex);
- /*
- * Calculate the module_load_offset the first time this
- * code is called. Once calculated it stays the same until
- * reboot.
- */
- if (module_load_offset == 0)
- module_load_offset =
- get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
- mutex_unlock(&module_kaslr_mutex);
- }
- return module_load_offset;
-}
-#else
-static unsigned long int get_module_load_offset(void)
+struct execmem_info __init *execmem_arch_setup(void)
{
- return 0;
-}
-#endif
-
-void *module_alloc(unsigned long size)
-{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- if (PAGE_ALIGN(size) > MODULES_LEN)
- return NULL;
-
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- MODULES_VADDR + get_module_load_offset(),
- MODULES_END, gfp_mask, PAGE_KERNEL,
- VM_FLUSH_RESET_PERMS | VM_DEFER_KMEMLEAK,
- NUMA_NO_NODE, __builtin_return_address(0));
-
- if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) {
- vfree(p);
- return NULL;
- }
-
- return p;
+ unsigned long start, offset = 0;
+
+ if (kaslr_enabled())
+ offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
+
+ start = MODULES_VADDR + offset;
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .flags = EXECMEM_KASAN_SHADOW,
+ .start = start,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = MODULE_ALIGN,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#ifdef CONFIG_X86_32
diff --git a/include/linux/execmem.h b/include/linux/execmem.h
index 96fc59258467..32cef1144117 100644
--- a/include/linux/execmem.h
+++ b/include/linux/execmem.h
@@ -5,6 +5,14 @@
#include <linux/types.h>
#include <linux/moduleloader.h>
+#if (defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)) && \
+ !defined(CONFIG_KASAN_VMALLOC)
+#include <linux/kasan.h>
+#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
+#else
+#define MODULE_ALIGN PAGE_SIZE
+#endif
+
/**
* enum execmem_type - types of executable memory ranges
*
@@ -22,6 +30,7 @@
* @EXECMEM_KPROBES: parameters for kprobes
* @EXECMEM_FTRACE: parameters for ftrace
* @EXECMEM_BPF: parameters for BPF
+ * @EXECMEM_MODULE_DATA: parameters for module data sections
* @EXECMEM_TYPE_MAX:
*/
enum execmem_type {
@@ -30,22 +39,38 @@ enum execmem_type {
EXECMEM_KPROBES,
EXECMEM_FTRACE,
EXECMEM_BPF,
+ EXECMEM_MODULE_DATA,
EXECMEM_TYPE_MAX,
};
+/**
+ * enum execmem_range_flags - options for executable memory allocations
+ * @EXECMEM_KASAN_SHADOW: allocate kasan shadow
+ */
+enum execmem_range_flags {
+ EXECMEM_KASAN_SHADOW = (1 << 0),
+};
+
/**
* struct execmem_range - definition of an address space suitable for code and
* related data allocations
* @start: address space start
* @end: address space end (inclusive)
+ * @fallback_start: start of the secondary address space range for fallback
+ * allocations on architectures that require it
+ * @fallback_end: start of the secondary address space (inclusive)
* @pgprot: permissions for memory in this address space
* @alignment: alignment required for text allocations
+ * @flags: options for memory allocations for this range
*/
struct execmem_range {
unsigned long start;
unsigned long end;
+ unsigned long fallback_start;
+ unsigned long fallback_end;
pgprot_t pgprot;
unsigned int alignment;
+ enum execmem_range_flags flags;
};
/**
@@ -82,6 +107,9 @@ struct execmem_info *execmem_arch_setup(void);
* Allocates memory that will contain executable code, either generated or
* loaded from kernel modules.
*
+ * Allocates memory that will contain data coupled with executable code,
+ * like data sections in kernel modules.
+ *
* The memory will have protections defined by architecture for executable
* region of the @type.
*
@@ -95,7 +123,7 @@ void *execmem_alloc(enum execmem_type type, size_t size);
*/
void execmem_free(void *ptr);
-#ifdef CONFIG_EXECMEM
+#if defined(CONFIG_EXECMEM) && !defined(CONFIG_ARCH_WANTS_EXECMEM_LATE)
void execmem_init(void);
#else
static inline void execmem_init(void) {}
diff --git a/include/linux/moduleloader.h b/include/linux/moduleloader.h
index a3b8caee9405..e395461d59e5 100644
--- a/include/linux/moduleloader.h
+++ b/include/linux/moduleloader.h
@@ -25,10 +25,6 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
/* Additional bytes needed by arch in front of individual sections */
unsigned int arch_mod_section_prepend(struct module *mod, unsigned int section);
-/* Allocator used for allocating struct module, core sections and init
- sections. Returns NULL on failure. */
-void *module_alloc(unsigned long size);
-
/* Determines if the section name is an init section (that is only used during
* module loading).
*/
@@ -126,12 +122,4 @@ void module_arch_cleanup(struct module *mod);
/* Any cleanup before freeing mod->module_init */
void module_arch_freeing_init(struct module *mod);
-#if (defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)) && \
- !defined(CONFIG_KASAN_VMALLOC)
-#include <linux/kasan.h>
-#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
-#else
-#define MODULE_ALIGN PAGE_SIZE
-#endif
-
#endif
diff --git a/kernel/module/main.c b/kernel/module/main.c
index d56b7df0cbb6..91e185607d4b 100644
--- a/kernel/module/main.c
+++ b/kernel/module/main.c
@@ -1188,24 +1188,20 @@ void __weak module_arch_freeing_init(struct module *mod)
{
}
-static bool mod_mem_use_vmalloc(enum mod_mem_type type)
-{
- return IS_ENABLED(CONFIG_ARCH_WANTS_MODULES_DATA_IN_VMALLOC) &&
- mod_mem_type_is_core_data(type);
-}
-
static int module_memory_alloc(struct module *mod, enum mod_mem_type type)
{
unsigned int size = PAGE_ALIGN(mod->mem[type].size);
+ enum execmem_type execmem_type;
void *ptr;
mod->mem[type].size = size;
- if (mod_mem_use_vmalloc(type))
- ptr = vmalloc(size);
+ if (mod_mem_type_is_data(type))
+ execmem_type = EXECMEM_MODULE_DATA;
else
- ptr = execmem_alloc(EXECMEM_MODULE_TEXT, size);
+ execmem_type = EXECMEM_MODULE_TEXT;
+ ptr = execmem_alloc(execmem_type, size);
if (!ptr)
return -ENOMEM;
@@ -1232,10 +1228,7 @@ static void module_memory_free(struct module *mod, enum mod_mem_type type)
{
void *ptr = mod->mem[type].base;
- if (mod_mem_use_vmalloc(type))
- vfree(ptr);
- else
- execmem_free(ptr);
+ execmem_free(ptr);
}
static void free_mod_mem(struct module *mod)
@@ -1630,13 +1623,6 @@ static void free_modinfo(struct module *mod)
}
}
-void * __weak module_alloc(unsigned long size)
-{
- return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_EXEC, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
bool __weak module_init_section(const char *name)
{
return strstarts(name, ".init");
diff --git a/mm/execmem.c b/mm/execmem.c
index 80e61c1e7319..f6dc3fabc1ca 100644
--- a/mm/execmem.c
+++ b/mm/execmem.c
@@ -12,27 +12,49 @@
#include <linux/moduleloader.h>
static struct execmem_info *execmem_info __ro_after_init;
+static struct execmem_info default_execmem_info __ro_after_init;
static void *__execmem_alloc(struct execmem_range *range, size_t size)
{
+ bool kasan = range->flags & EXECMEM_KASAN_SHADOW;
+ unsigned long vm_flags = VM_FLUSH_RESET_PERMS;
+ gfp_t gfp_flags = GFP_KERNEL | __GFP_NOWARN;
unsigned long start = range->start;
unsigned long end = range->end;
unsigned int align = range->alignment;
pgprot_t pgprot = range->pgprot;
+ void *p;
+
+ if (kasan)
+ vm_flags |= VM_DEFER_KMEMLEAK;
+
+ p = __vmalloc_node_range(size, align, start, end, gfp_flags,
+ pgprot, vm_flags, NUMA_NO_NODE,
+ __builtin_return_address(0));
+ if (!p && range->fallback_start) {
+ start = range->fallback_start;
+ end = range->fallback_end;
+ p = __vmalloc_node_range(size, align, start, end, gfp_flags,
+ pgprot, vm_flags, NUMA_NO_NODE,
+ __builtin_return_address(0));
+ }
+
+ if (!p) {
+ pr_warn_ratelimited("execmem: unable to allocate memory\n");
+ return NULL;
+ }
+
+ if (kasan && (kasan_alloc_module_shadow(p, size, GFP_KERNEL) < 0)) {
+ vfree(p);
+ return NULL;
+ }
- return __vmalloc_node_range(size, align, start, end,
- GFP_KERNEL, pgprot, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
+ return kasan_reset_tag(p);
}
void *execmem_alloc(enum execmem_type type, size_t size)
{
- struct execmem_range *range;
-
- if (!execmem_info)
- return module_alloc(size);
-
- range = &execmem_info->ranges[type];
+ struct execmem_range *range = &execmem_info->ranges[type];
return __execmem_alloc(range, size);
}
@@ -67,10 +89,16 @@ static void execmem_init_missing(struct execmem_info *info)
struct execmem_range *r = &info->ranges[i];
if (!r->start) {
- r->pgprot = default_range->pgprot;
+ if (i == EXECMEM_MODULE_DATA)
+ r->pgprot = PAGE_KERNEL;
+ else
+ r->pgprot = default_range->pgprot;
r->alignment = default_range->alignment;
r->start = default_range->start;
r->end = default_range->end;
+ r->flags = default_range->flags;
+ r->fallback_start = default_range->fallback_start;
+ r->fallback_end = default_range->fallback_end;
}
}
}
@@ -80,14 +108,37 @@ struct execmem_info * __weak execmem_arch_setup(void)
return NULL;
}
-void __init execmem_init(void)
+static void __init __execmem_init(void)
{
struct execmem_info *info = execmem_arch_setup();
- if (!info || !execmem_validate(info))
+ if (!info) {
+ info = execmem_info = &default_execmem_info;
+ info->ranges[EXECMEM_DEFAULT].start = VMALLOC_START;
+ info->ranges[EXECMEM_DEFAULT].end = VMALLOC_END;
+ info->ranges[EXECMEM_DEFAULT].pgprot = PAGE_KERNEL_EXEC;
+ info->ranges[EXECMEM_DEFAULT].alignment = 1;
+ return;
+ }
+
+ if (!execmem_validate(info))
return;
execmem_init_missing(info);
execmem_info = info;
}
+
+#ifdef CONFIG_ARCH_WANTS_EXECMEM_LATE
+static int __init execmem_late_init(void)
+{
+ __execmem_init();
+ return 0;
+}
+core_initcall(execmem_late_init);
+#else
+void __init execmem_init(void)
+{
+ __execmem_init();
+}
+#endif
--
2.43.0
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* [PATCH v3 5/5] PCI: kirin: Convert to agnostic GPIO API
2024-04-29 10:23 11% ` [PATCH v3 4/5] PCI: imx6: Convert " Andy Shevchenko
@ 2024-04-29 10:23 16% ` Andy Shevchenko
2024-04-30 5:16 0% ` Manivannan Sadhasivam
1 sibling, 1 reply; 200+ results
From: Andy Shevchenko @ 2024-04-29 10:23 UTC (permalink / raw)
To: Manivannan Sadhasivam, Frank Li, Krzysztof Wilczyński,
Andy Shevchenko, Uwe Kleine-König, linux-omap, linux-pci,
linux-arm-kernel, linux-kernel, imx, linux-amlogic,
linux-arm-msm, linux-tegra
Cc: Vignesh Raghavendra, Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár
The of_gpio.h is going to be removed. In preparation of that convert
the driver to the agnostic API.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pci/controller/dwc/pcie-kirin.c | 105 ++++++++----------------
1 file changed, 35 insertions(+), 70 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
index d5523f302102..d1f54f188e71 100644
--- a/drivers/pci/controller/dwc/pcie-kirin.c
+++ b/drivers/pci/controller/dwc/pcie-kirin.c
@@ -12,12 +12,10 @@
#include <linux/compiler.h>
#include <linux/delay.h>
#include <linux/err.h>
-#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
-#include <linux/of_gpio.h>
#include <linux/of_pci.h>
#include <linux/phy/phy.h>
#include <linux/pci.h>
@@ -78,16 +76,16 @@ struct kirin_pcie {
void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */
/* DWC PERST# */
- int gpio_id_dwc_perst;
+ struct gpio_desc *id_dwc_perst_gpio;
/* Per-slot PERST# */
int num_slots;
- int gpio_id_reset[MAX_PCI_SLOTS];
+ struct gpio_desc *id_reset_gpio[MAX_PCI_SLOTS];
const char *reset_names[MAX_PCI_SLOTS];
/* Per-slot clkreq */
int n_gpio_clkreq;
- int gpio_id_clkreq[MAX_PCI_SLOTS];
+ struct gpio_desc *id_clkreq_gpio[MAX_PCI_SLOTS];
const char *clkreq_names[MAX_PCI_SLOTS];
};
@@ -381,15 +379,20 @@ static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie,
pcie->n_gpio_clkreq = ret;
for (i = 0; i < pcie->n_gpio_clkreq; i++) {
- pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node,
- "hisilicon,clken-gpios", i);
- if (pcie->gpio_id_clkreq[i] < 0)
- return pcie->gpio_id_clkreq[i];
+ pcie->id_clkreq_gpio[i] = devm_gpiod_get_index(dev,
+ "hisilicon,clken", i,
+ GPIOD_OUT_LOW);
+ if (IS_ERR(pcie->id_clkreq_gpio[i]))
+ return dev_err_probe(dev, PTR_ERR(pcie->id_clkreq_gpio[i]),
+ "unable to get a valid clken gpio\n");
pcie->clkreq_names[i] = devm_kasprintf(dev, GFP_KERNEL,
"pcie_clkreq_%d", i);
if (!pcie->clkreq_names[i])
return -ENOMEM;
+
+ gpiod_set_consumer_name(pcie->id_clkreq_gpio[i],
+ pcie->clkreq_names[i]);
}
return 0;
@@ -407,10 +410,16 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
for_each_available_child_of_node(parent, child) {
i = pcie->num_slots;
- pcie->gpio_id_reset[i] = of_get_named_gpio(child,
- "reset-gpios", 0);
- if (pcie->gpio_id_reset[i] < 0)
- continue;
+ pcie->id_reset_gpio[i] = devm_fwnode_gpiod_get_index(dev,
+ of_fwnode_handle(child),
+ "reset", 0, GPIOD_OUT_LOW,
+ NULL);
+ if (IS_ERR(pcie->id_reset_gpio[i])) {
+ if (PTR_ERR(pcie->id_reset_gpio[i]) == -ENOENT)
+ continue;
+ return dev_err_probe(dev, PTR_ERR(pcie->id_reset_gpio[i]),
+ "unable to get a valid reset gpio\n");
+ }
pcie->num_slots++;
if (pcie->num_slots > MAX_PCI_SLOTS) {
@@ -434,6 +443,9 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
ret = -ENOMEM;
goto put_node;
}
+
+ gpiod_set_consumer_name(pcie->id_reset_gpio[i],
+ pcie->reset_names[i]);
}
}
@@ -463,14 +475,11 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
return PTR_ERR(kirin_pcie->apb);
/* pcie internal PERST# gpio */
- kirin_pcie->gpio_id_dwc_perst = of_get_named_gpio(dev->of_node,
- "reset-gpios", 0);
- if (kirin_pcie->gpio_id_dwc_perst == -EPROBE_DEFER) {
- return -EPROBE_DEFER;
- } else if (!gpio_is_valid(kirin_pcie->gpio_id_dwc_perst)) {
- dev_err(dev, "unable to get a valid gpio pin\n");
- return -ENODEV;
- }
+ kirin_pcie->id_dwc_perst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(kirin_pcie->id_dwc_perst_gpio))
+ return dev_err_probe(dev, PTR_ERR(kirin_pcie->id_dwc_perst_gpio),
+ "unable to get a valid gpio pin\n");
+ gpiod_set_consumer_name(kirin_pcie->id_dwc_perst_gpio, "pcie_perst_bridge");
ret = kirin_pcie_get_gpio_enable(kirin_pcie, pdev);
if (ret)
@@ -553,7 +562,7 @@ static int kirin_pcie_add_bus(struct pci_bus *bus)
/* Send PERST# to each slot */
for (i = 0; i < kirin_pcie->num_slots; i++) {
- ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1);
+ ret = gpiod_direction_output_raw(kirin_pcie->id_reset_gpio[i], 1);
if (ret) {
dev_err(pci->dev, "PERST# %s error: %d\n",
kirin_pcie->reset_names[i], ret);
@@ -623,44 +632,6 @@ static int kirin_pcie_host_init(struct dw_pcie_rp *pp)
return 0;
}
-static int kirin_pcie_gpio_request(struct kirin_pcie *kirin_pcie,
- struct device *dev)
-{
- int ret, i;
-
- for (i = 0; i < kirin_pcie->num_slots; i++) {
- if (!gpio_is_valid(kirin_pcie->gpio_id_reset[i])) {
- dev_err(dev, "unable to get a valid %s gpio\n",
- kirin_pcie->reset_names[i]);
- return -ENODEV;
- }
-
- ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i],
- kirin_pcie->reset_names[i]);
- if (ret)
- return ret;
- }
-
- for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) {
- if (!gpio_is_valid(kirin_pcie->gpio_id_clkreq[i])) {
- dev_err(dev, "unable to get a valid %s gpio\n",
- kirin_pcie->clkreq_names[i]);
- return -ENODEV;
- }
-
- ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i],
- kirin_pcie->clkreq_names[i]);
- if (ret)
- return ret;
-
- ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
static const struct dw_pcie_ops kirin_dw_pcie_ops = {
.read_dbi = kirin_pcie_read_dbi,
.write_dbi = kirin_pcie_write_dbi,
@@ -680,7 +651,7 @@ static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie)
return hi3660_pcie_phy_power_off(kirin_pcie);
for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++)
- gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 1);
+ gpiod_direction_output_raw(kirin_pcie->id_clkreq_gpio[i], 1);
phy_power_off(kirin_pcie->phy);
phy_exit(kirin_pcie->phy);
@@ -707,10 +678,6 @@ static int kirin_pcie_power_on(struct platform_device *pdev,
if (IS_ERR(kirin_pcie->phy))
return PTR_ERR(kirin_pcie->phy);
- ret = kirin_pcie_gpio_request(kirin_pcie, dev);
- if (ret)
- return ret;
-
ret = phy_init(kirin_pcie->phy);
if (ret)
goto err;
@@ -723,11 +690,9 @@ static int kirin_pcie_power_on(struct platform_device *pdev,
/* perst assert Endpoint */
usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
- if (!gpio_request(kirin_pcie->gpio_id_dwc_perst, "pcie_perst_bridge")) {
- ret = gpio_direction_output(kirin_pcie->gpio_id_dwc_perst, 1);
- if (ret)
- goto err;
- }
+ ret = gpiod_direction_output_raw(kirin_pcie->id_dwc_perst_gpio, 1);
+ if (ret)
+ goto err;
usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
--
2.43.0.rc1.1336.g36b5255a03ac
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 16%]
* [PATCH v3 4/5] PCI: imx6: Convert to agnostic GPIO API
@ 2024-04-29 10:23 11% ` Andy Shevchenko
2024-04-29 10:23 16% ` [PATCH v3 5/5] PCI: kirin: " Andy Shevchenko
1 sibling, 0 replies; 200+ results
From: Andy Shevchenko @ 2024-04-29 10:23 UTC (permalink / raw)
To: Manivannan Sadhasivam, Frank Li, Krzysztof Wilczyński,
Andy Shevchenko, Uwe Kleine-König, linux-omap, linux-pci,
linux-arm-kernel, linux-kernel, imx, linux-amlogic,
linux-arm-msm, linux-tegra
Cc: Vignesh Raghavendra, Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár
The of_gpio.h is going to be removed. In preparation of that convert
the driver to the agnostic API.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 37 ++++++++++-----------------
1 file changed, 14 insertions(+), 23 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 917c69edee1d..d620f1e1a43c 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -11,14 +11,13 @@
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_gpio.h>
#include <linux/of_address.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
@@ -107,7 +106,7 @@ struct imx6_pcie_drvdata {
struct imx6_pcie {
struct dw_pcie *pci;
- int reset_gpio;
+ struct gpio_desc *reset_gpiod;
bool gpio_active_high;
bool link_is_up;
struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS];
@@ -721,9 +720,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
}
/* Some boards don't have PCIe reset GPIO. */
- if (gpio_is_valid(imx6_pcie->reset_gpio))
- gpio_set_value_cansleep(imx6_pcie->reset_gpio,
- imx6_pcie->gpio_active_high);
+ gpiod_set_raw_value_cansleep(imx6_pcie->reset_gpiod,
+ imx6_pcie->gpio_active_high);
}
static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
@@ -771,10 +769,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
}
/* Some boards don't have PCIe reset GPIO. */
- if (gpio_is_valid(imx6_pcie->reset_gpio)) {
+ if (imx6_pcie->reset_gpiod) {
msleep(100);
- gpio_set_value_cansleep(imx6_pcie->reset_gpio,
- !imx6_pcie->gpio_active_high);
+ gpiod_set_raw_value_cansleep(imx6_pcie->reset_gpiod,
+ !imx6_pcie->gpio_active_high);
/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
msleep(100);
}
@@ -1285,22 +1283,15 @@ static int imx6_pcie_probe(struct platform_device *pdev)
return PTR_ERR(pci->dbi_base);
/* Fetch GPIOs */
- imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
imx6_pcie->gpio_active_high = of_property_read_bool(node,
"reset-gpio-active-high");
- if (gpio_is_valid(imx6_pcie->reset_gpio)) {
- ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
- imx6_pcie->gpio_active_high ?
- GPIOF_OUT_INIT_HIGH :
- GPIOF_OUT_INIT_LOW,
- "PCIe reset");
- if (ret) {
- dev_err(dev, "unable to get reset gpio\n");
- return ret;
- }
- } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
- return imx6_pcie->reset_gpio;
- }
+ imx6_pcie->reset_gpiod =
+ devm_gpiod_get_optional(dev, "reset",
+ imx6_pcie->gpio_active_high ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW);
+ if (IS_ERR(imx6_pcie->reset_gpiod))
+ return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod),
+ "unable to get reset gpio\n");
+ gpiod_set_consumer_name(imx6_pcie->reset_gpiod, "PCIe reset");
if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS)
return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
--
2.43.0.rc1.1336.g36b5255a03ac
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 11%]
* [PATCH v5 3/3] spi: airoha: add SPI-NAND Flash controller driver
@ 2024-04-29 8:13 2% ` Lorenzo Bianconi
0 siblings, 0 replies; 200+ results
From: Lorenzo Bianconi @ 2024-04-29 8:13 UTC (permalink / raw)
To: linux-spi
Cc: conor, broonie, lorenzo.bianconi83, linux-arm-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, nbd, john, dd,
catalin.marinas, will, upstream, angelogioacchino.delregno,
andy.shevchenko
Introduce support for SPI-NAND driver of the Airoha NAND Flash Interface
found on Airoha ARM SoCs.
Tested-by: Rajeev Kumar <Rajeev.Kumar@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
MAINTAINERS | 9 +
drivers/spi/Kconfig | 10 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-airoha-snfi.c | 1129 +++++++++++++++++++++++++++++++++
4 files changed, 1149 insertions(+)
create mode 100644 drivers/spi/spi-airoha-snfi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index aa3b947fb080..ce9fac46f741 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -653,6 +653,15 @@ S: Supported
F: fs/aio.c
F: include/linux/*aio*.h
+AIROHA SPI SNFI DRIVER
+M: Lorenzo Bianconi <lorenzo@kernel.org>
+M: Ray Liu <ray.liu@airoha.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-spi@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/spi/airoha,en7581-snand.yaml
+F: drivers/spi/spi-airoha.c
+
AIRSPY MEDIA DRIVER
L: linux-media@vger.kernel.org
S: Orphan
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bc7021da2fe9..6fa91775f334 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -57,6 +57,16 @@ config SPI_MEM
comment "SPI Master Controller Drivers"
+config SPI_AIROHA_SNFI
+ tristate "Airoha SPI NAND Flash Interface"
+ depends on ARCH_AIROHA || COMPILE_TEST
+ depends on SPI_MASTER
+ select REGMAP_MMIO
+ help
+ This enables support for SPI-NAND mode on the Airoha NAND
+ Flash Interface found on Airoha ARM SoCs. This controller
+ is implemented as a SPI-MEM controller.
+
config SPI_ALTERA
tristate "Altera SPI Controller platform driver"
select SPI_ALTERA_CORE
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4ff8d725ba5e..e694254dec04 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_SPIDEV) += spidev.o
obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
# SPI master controller drivers (bus)
+obj-$(CONFIG_SPI_AIROHA_SNFI) += spi-airoha-snfi.o
obj-$(CONFIG_SPI_ALTERA) += spi-altera-platform.o
obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o
obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o
diff --git a/drivers/spi/spi-airoha-snfi.c b/drivers/spi/spi-airoha-snfi.c
new file mode 100644
index 000000000000..9d97ec98881c
--- /dev/null
+++ b/drivers/spi/spi-airoha-snfi.c
@@ -0,0 +1,1129 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Ray Liu <ray.liu@airoha.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <linux/limits.h>
+#include <linux/math.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/sizes.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+#include <linux/types.h>
+#include <asm/unaligned.h>
+
+/* SPI */
+#define REG_SPI_CTRL_BASE 0x1FA10000
+
+#define REG_SPI_CTRL_READ_MODE 0x0000
+#define REG_SPI_CTRL_READ_IDLE_EN 0x0004
+#define REG_SPI_CTRL_SIDLY 0x0008
+#define REG_SPI_CTRL_CSHEXT 0x000c
+#define REG_SPI_CTRL_CSLEXT 0x0010
+
+#define REG_SPI_CTRL_MTX_MODE_TOG 0x0014
+#define SPI_CTRL_MTX_MODE_TOG GENMASK(3, 0)
+
+#define REG_SPI_CTRL_RDCTL_FSM 0x0018
+#define SPI_CTRL_RDCTL_FSM GENMASK(3, 0)
+
+#define REG_SPI_CTRL_MACMUX_SEL 0x001c
+
+#define REG_SPI_CTRL_MANUAL_EN 0x0020
+#define SPI_CTRL_MANUAL_EN BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_EMPTY 0x0024
+#define SPI_CTRL_OPFIFO_EMPTY BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_WDATA 0x0028
+#define SPI_CTRL_OPFIFO_LEN GENMASK(8, 0)
+#define SPI_CTRL_OPFIFO_OP GENMASK(13, 9)
+
+#define REG_SPI_CTRL_OPFIFO_FULL 0x002c
+#define SPI_CTRL_OPFIFO_FULL BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_WR 0x0030
+#define SPI_CTRL_OPFIFO_WR BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_FULL 0x0034
+#define SPI_CTRL_DFIFO_FULL BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_WDATA 0x0038
+#define SPI_CTRL_DFIFO_WDATA GENMASK(7, 0)
+
+#define REG_SPI_CTRL_DFIFO_EMPTY 0x003c
+#define SPI_CTRL_DFIFO_EMPTY BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_RD 0x0040
+#define SPI_CTRL_DFIFO_RD BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_RDATA 0x0044
+#define SPI_CTRL_DFIFO_RDATA GENMASK(7, 0)
+
+#define REG_SPI_CTRL_DUMMY 0x0080
+#define SPI_CTRL_CTRL_DUMMY GENMASK(3, 0)
+
+#define REG_SPI_CTRL_PROBE_SEL 0x0088
+#define REG_SPI_CTRL_INTERRUPT 0x0090
+#define REG_SPI_CTRL_INTERRUPT_EN 0x0094
+#define REG_SPI_CTRL_SI_CK_SEL 0x009c
+#define REG_SPI_CTRL_SW_CFGNANDADDR_VAL 0x010c
+#define REG_SPI_CTRL_SW_CFGNANDADDR_EN 0x0110
+#define REG_SPI_CTRL_SFC_STRAP 0x0114
+
+#define REG_SPI_CTRL_NFI2SPI_EN 0x0130
+#define SPI_CTRL_NFI2SPI_EN BIT(0)
+
+/* NFI2SPI */
+#define REG_SPI_NFI_CNFG 0x0000
+#define SPI_NFI_DMA_MODE BIT(0)
+#define SPI_NFI_READ_MODE BIT(1)
+#define SPI_NFI_DMA_BURST_EN BIT(2)
+#define SPI_NFI_HW_ECC_EN BIT(8)
+#define SPI_NFI_AUTO_FDM_EN BIT(9)
+#define SPI_NFI_OPMODE GENMASK(14, 12)
+
+#define REG_SPI_NFI_PAGEFMT 0x0004
+#define SPI_NFI_PAGE_SIZE GENMASK(1, 0)
+#define SPI_NFI_SPARE_SIZE GENMASK(5, 4)
+
+#define REG_SPI_NFI_CON 0x0008
+#define SPI_NFI_FIFO_FLUSH BIT(0)
+#define SPI_NFI_RST BIT(1)
+#define SPI_NFI_RD_TRIG BIT(8)
+#define SPI_NFI_WR_TRIG BIT(9)
+#define SPI_NFI_SEC_NUM GENMASK(15, 12)
+
+#define REG_SPI_NFI_INTR_EN 0x0010
+#define SPI_NFI_RD_DONE_EN BIT(0)
+#define SPI_NFI_WR_DONE_EN BIT(1)
+#define SPI_NFI_RST_DONE_EN BIT(2)
+#define SPI_NFI_ERASE_DONE_EN BIT(3)
+#define SPI_NFI_BUSY_RETURN_EN BIT(4)
+#define SPI_NFI_ACCESS_LOCK_EN BIT(5)
+#define SPI_NFI_AHB_DONE_EN BIT(6)
+#define SPI_NFI_ALL_IRQ_EN \
+ (SPI_NFI_RD_DONE_EN | SPI_NFI_WR_DONE_EN | \
+ SPI_NFI_RST_DONE_EN | SPI_NFI_ERASE_DONE_EN | \
+ SPI_NFI_BUSY_RETURN_EN | SPI_NFI_ACCESS_LOCK_EN | \
+ SPI_NFI_AHB_DONE_EN)
+
+#define REG_SPI_NFI_INTR 0x0014
+#define SPI_NFI_AHB_DONE BIT(6)
+
+#define REG_SPI_NFI_CMD 0x0020
+
+#define REG_SPI_NFI_ADDR_NOB 0x0030
+#define SPI_NFI_ROW_ADDR_NOB GENMASK(6, 4)
+
+#define REG_SPI_NFI_STA 0x0060
+#define REG_SPI_NFI_FIFOSTA 0x0064
+#define REG_SPI_NFI_STRADDR 0x0080
+#define REG_SPI_NFI_FDM0L 0x00a0
+#define REG_SPI_NFI_FDM0M 0x00a4
+#define REG_SPI_NFI_FDM7L 0x00d8
+#define REG_SPI_NFI_FDM7M 0x00dc
+#define REG_SPI_NFI_FIFODATA0 0x0190
+#define REG_SPI_NFI_FIFODATA1 0x0194
+#define REG_SPI_NFI_FIFODATA2 0x0198
+#define REG_SPI_NFI_FIFODATA3 0x019c
+#define REG_SPI_NFI_MASTERSTA 0x0224
+
+#define REG_SPI_NFI_SECCUS_SIZE 0x022c
+#define SPI_NFI_CUS_SEC_SIZE GENMASK(12, 0)
+#define SPI_NFI_CUS_SEC_SIZE_EN BIT(16)
+
+#define REG_SPI_NFI_RD_CTL2 0x0510
+#define REG_SPI_NFI_RD_CTL3 0x0514
+
+#define REG_SPI_NFI_PG_CTL1 0x0524
+#define SPI_NFI_PG_LOAD_CMD GENMASK(15, 8)
+
+#define REG_SPI_NFI_PG_CTL2 0x0528
+#define REG_SPI_NFI_NOR_PROG_ADDR 0x052c
+#define REG_SPI_NFI_NOR_RD_ADDR 0x0534
+
+#define REG_SPI_NFI_SNF_MISC_CTL 0x0538
+#define SPI_NFI_DATA_READ_WR_MODE GENMASK(18, 16)
+
+#define REG_SPI_NFI_SNF_MISC_CTL2 0x053c
+#define SPI_NFI_READ_DATA_BYTE_NUM GENMASK(12, 0)
+#define SPI_NFI_PROG_LOAD_BYTE_NUM GENMASK(28, 16)
+
+#define REG_SPI_NFI_SNF_STA_CTL1 0x0550
+#define SPI_NFI_READ_FROM_CACHE_DONE BIT(25)
+#define SPI_NFI_LOAD_TO_CACHE_DONE BIT(26)
+
+#define REG_SPI_NFI_SNF_STA_CTL2 0x0554
+
+#define REG_SPI_NFI_SNF_NFI_CNFG 0x055c
+#define SPI_NFI_SPI_MODE BIT(0)
+
+/* SPI NAND Protocol OP */
+#define SPI_NAND_OP_GET_FEATURE 0x0f
+#define SPI_NAND_OP_SET_FEATURE 0x1f
+#define SPI_NAND_OP_PAGE_READ 0x13
+#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE 0x03
+#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST 0x0b
+#define SPI_NAND_OP_READ_FROM_CACHE_DUAL 0x3b
+#define SPI_NAND_OP_READ_FROM_CACHE_QUAD 0x6b
+#define SPI_NAND_OP_WRITE_ENABLE 0x06
+#define SPI_NAND_OP_WRITE_DISABLE 0x04
+#define SPI_NAND_OP_PROGRAM_LOAD_SINGLE 0x02
+#define SPI_NAND_OP_PROGRAM_LOAD_QUAD 0x32
+#define SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE 0x84
+#define SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD 0x34
+#define SPI_NAND_OP_PROGRAM_EXECUTE 0x10
+#define SPI_NAND_OP_READ_ID 0x9f
+#define SPI_NAND_OP_BLOCK_ERASE 0xd8
+#define SPI_NAND_OP_RESET 0xff
+#define SPI_NAND_OP_DIE_SELECT 0xc2
+
+#define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256)
+#define SPI_MAX_TRANSFER_SIZE 511
+
+enum airoha_snand_mode {
+ SPI_MODE_AUTO,
+ SPI_MODE_MANUAL,
+ SPI_MODE_DMA,
+};
+
+enum airoha_snand_cs {
+ SPI_CHIP_SEL_HIGH,
+ SPI_CHIP_SEL_LOW,
+};
+
+struct airoha_snand_dev {
+ size_t buf_len;
+
+ u8 *txrx_buf;
+ dma_addr_t dma_addr;
+
+ u64 cur_page_num;
+ bool data_need_update;
+};
+
+struct airoha_snand_ctrl {
+ struct device *dev;
+ struct regmap *regmap_ctrl;
+ struct regmap *regmap_nfi;
+ struct clk *spi_clk;
+
+ struct {
+ size_t page_size;
+ size_t sec_size;
+ u8 sec_num;
+ u8 spare_size;
+ } nfi_cfg;
+};
+
+static int airoha_snand_set_fifo_op(struct airoha_snand_ctrl *as_ctrl,
+ u8 op_cmd, int op_len)
+{
+ int err;
+ u32 val;
+
+ err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WDATA,
+ FIELD_PREP(SPI_CTRL_OPFIFO_LEN, op_len) |
+ FIELD_PREP(SPI_CTRL_OPFIFO_OP, op_cmd));
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_OPFIFO_FULL,
+ val, !(val & SPI_CTRL_OPFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WR,
+ SPI_CTRL_OPFIFO_WR);
+ if (err)
+ return err;
+
+ return regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_OPFIFO_EMPTY,
+ val, (val & SPI_CTRL_OPFIFO_EMPTY),
+ 0, 250 * USEC_PER_MSEC);
+}
+
+static int airoha_snand_set_cs(struct airoha_snand_ctrl *as_ctrl, u8 cs)
+{
+ return airoha_snand_set_fifo_op(as_ctrl, cs, sizeof(cs));
+}
+
+static int airoha_snand_write_data_to_fifo(struct airoha_snand_ctrl *as_ctrl,
+ const u8 *data, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ int err;
+ u32 val;
+
+ /* 1. Wait until dfifo is not full */
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_FULL, val,
+ !(val & SPI_CTRL_DFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ /* 2. Write data to register DFIFO_WDATA */
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_WDATA,
+ FIELD_PREP(SPI_CTRL_DFIFO_WDATA, data[i]));
+ if (err)
+ return err;
+
+ /* 3. Wait until dfifo is not full */
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_FULL, val,
+ !(val & SPI_CTRL_DFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_read_data_from_fifo(struct airoha_snand_ctrl *as_ctrl,
+ u8 *ptr, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ int err;
+ u32 val;
+
+ /* 1. wait until dfifo is not empty */
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_EMPTY, val,
+ !(val & SPI_CTRL_DFIFO_EMPTY),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ /* 2. read from dfifo to register DFIFO_RDATA */
+ err = regmap_read(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_RDATA, &val);
+ if (err)
+ return err;
+
+ ptr[i] = FIELD_GET(SPI_CTRL_DFIFO_RDATA, val);
+ /* 3. enable register DFIFO_RD to read next byte */
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_RD, SPI_CTRL_DFIFO_RD);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_set_mode(struct airoha_snand_ctrl *as_ctrl,
+ enum airoha_snand_mode mode)
+{
+ int err;
+
+ switch (mode) {
+ case SPI_MODE_MANUAL: {
+ u32 val;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_NFI2SPI_EN, 0);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_READ_IDLE_EN, 0);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_RDCTL_FSM, val,
+ !(val & SPI_CTRL_RDCTL_FSM),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MTX_MODE_TOG, 9);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MANUAL_EN, SPI_CTRL_MANUAL_EN);
+ if (err)
+ return err;
+ break;
+ }
+ case SPI_MODE_DMA:
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_NFI2SPI_EN,
+ SPI_CTRL_MANUAL_EN);
+ if (err < 0)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MTX_MODE_TOG, 0x0);
+ if (err < 0)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MANUAL_EN, 0x0);
+ if (err < 0)
+ return err;
+ break;
+ case SPI_MODE_AUTO:
+ default:
+ break;
+ }
+
+ return regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
+}
+
+static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd,
+ const u8 *data, int len)
+{
+ int i, data_len;
+
+ for (i = 0; i < len; i += data_len) {
+ int err;
+
+ data_len = min(len, SPI_MAX_TRANSFER_SIZE);
+ err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
+ if (err)
+ return err;
+
+ err = airoha_snand_write_data_to_fifo(as_ctrl, &data[i],
+ data_len);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data,
+ int len)
+{
+ int i, data_len;
+
+ for (i = 0; i < len; i += data_len) {
+ int err;
+
+ data_len = min(len, SPI_MAX_TRANSFER_SIZE);
+ err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len);
+ if (err)
+ return err;
+
+ err = airoha_snand_read_data_from_fifo(as_ctrl, &data[i],
+ data_len);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_nfi_init(struct airoha_snand_ctrl *as_ctrl)
+{
+ int err;
+
+ /* switch to SNFI mode */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_NFI_CNFG,
+ SPI_NFI_SPI_MODE);
+ if (err)
+ return err;
+
+ /* Enable DMA */
+ return regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR_EN,
+ SPI_NFI_ALL_IRQ_EN, SPI_NFI_AHB_DONE_EN);
+}
+
+static int airoha_snand_nfi_config(struct airoha_snand_ctrl *as_ctrl)
+{
+ int err;
+ u32 val;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
+ if (err)
+ return err;
+
+ /* auto FDM */
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_AUTO_FDM_EN);
+ if (err)
+ return err;
+
+ /* HW ECC */
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_HW_ECC_EN);
+ if (err)
+ return err;
+
+ /* DMA Burst */
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_DMA_BURST_EN);
+ if (err)
+ return err;
+
+ /* page format */
+ switch (as_ctrl->nfi_cfg.spare_size) {
+ case 26:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1);
+ break;
+ case 27:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x2);
+ break;
+ case 28:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x3);
+ break;
+ default:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x0);
+ break;
+ }
+
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
+ SPI_NFI_SPARE_SIZE, val);
+ if (err)
+ return err;
+
+ switch (as_ctrl->nfi_cfg.page_size) {
+ case 2048:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1);
+ break;
+ case 4096:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x2);
+ break;
+ default:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x0);
+ break;
+ }
+
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
+ SPI_NFI_PAGE_SIZE, val);
+ if (err)
+ return err;
+
+ /* sec num */
+ val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_SEC_NUM, val);
+ if (err)
+ return err;
+
+ /* enable cust sec size */
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
+ SPI_NFI_CUS_SEC_SIZE_EN);
+ if (err)
+ return err;
+
+ /* set cust sec size */
+ val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, as_ctrl->nfi_cfg.sec_size);
+ return regmap_update_bits(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SECCUS_SIZE,
+ SPI_NFI_CUS_SEC_SIZE, val);
+}
+
+static bool airoha_snand_is_page_ops(const struct spi_mem_op *op)
+{
+ if (op->addr.nbytes != 2)
+ return false;
+
+ if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
+ op->addr.buswidth != 4)
+ return false;
+
+ switch (op->data.dir) {
+ case SPI_MEM_DATA_IN:
+ if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > 0xf)
+ return false;
+
+ /* quad in / quad out */
+ if (op->addr.buswidth == 4)
+ return op->data.buswidth == 4;
+
+ if (op->addr.buswidth == 2)
+ return op->data.buswidth == 2;
+
+ /* standard spi */
+ return op->data.buswidth == 4 || op->data.buswidth == 2 ||
+ op->data.buswidth == 1;
+ case SPI_MEM_DATA_OUT:
+ return !op->dummy.nbytes && op->addr.buswidth == 1 &&
+ (op->data.buswidth == 4 || op->data.buswidth == 1);
+ default:
+ return false;
+ }
+}
+
+static int airoha_snand_adjust_op_size(struct spi_mem *mem,
+ struct spi_mem_op *op)
+{
+ size_t max_len;
+
+ if (airoha_snand_is_page_ops(op)) {
+ struct airoha_snand_ctrl *as_ctrl;
+
+ as_ctrl = spi_controller_get_devdata(mem->spi->controller);
+ max_len = as_ctrl->nfi_cfg.sec_size;
+ max_len += as_ctrl->nfi_cfg.spare_size;
+ max_len *= as_ctrl->nfi_cfg.sec_num;
+
+ if (op->data.nbytes > max_len)
+ op->data.nbytes = max_len;
+ } else {
+ max_len = 1 + op->addr.nbytes + op->dummy.nbytes;
+ if (max_len >= 160)
+ return -EOPNOTSUPP;
+
+ if (op->data.nbytes > 160 - max_len)
+ op->data.nbytes = 160 - max_len;
+ }
+
+ return 0;
+}
+
+static bool airoha_snand_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ if (!spi_mem_default_supports_op(mem, op))
+ return false;
+
+ if (op->cmd.buswidth != 1)
+ return false;
+
+ if (airoha_snand_is_page_ops(op))
+ return true;
+
+ return (!op->addr.nbytes || op->addr.buswidth == 1) &&
+ (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
+ (!op->data.nbytes || op->data.buswidth == 1);
+}
+
+static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(desc->mem->spi);
+
+ if (!as_dev->txrx_buf)
+ return -EINVAL;
+
+ if (desc->info.offset + desc->info.length > U32_MAX)
+ return -EINVAL;
+
+ if (!airoha_snand_supports_op(desc->mem, &desc->info.op_tmpl))
+ return -EOPNOTSUPP;
+
+ return 0;
+}
+
+static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, void *buf)
+{
+ struct spi_device *spi = desc->mem->spi;
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ struct spi_mem_op *op = &desc->info.op_tmpl;
+ struct airoha_snand_ctrl *as_ctrl;
+ u32 val, rd_mode;
+ int err;
+
+ if (!as_dev->data_need_update)
+ return len;
+
+ as_dev->data_need_update = false;
+
+ switch (op->cmd.opcode) {
+ case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
+ rd_mode = 1;
+ break;
+ case SPI_NAND_OP_READ_FROM_CACHE_QUAD:
+ rd_mode = 2;
+ break;
+ default:
+ rd_mode = 0;
+ break;
+ }
+
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_nfi_config(as_ctrl);
+ if (err)
+ return err;
+
+ dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+
+ /* set dma addr */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
+ as_dev->dma_addr);
+ if (err)
+ return err;
+
+ /* set cust sec size */
+ val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
+ val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
+ err = regmap_update_bits(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_MISC_CTL2,
+ SPI_NFI_READ_DATA_BYTE_NUM, val);
+ if (err)
+ return err;
+
+ /* set read command */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL2,
+ op->cmd.opcode);
+ if (err)
+ return err;
+
+ /* set read mode */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
+ FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, rd_mode));
+ if (err)
+ return err;
+
+ /* set read addr */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 0x0);
+ if (err)
+ return err;
+
+ /* set nfi read */
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_OPMODE,
+ FIELD_PREP(SPI_NFI_OPMODE, 6));
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
+ if (err)
+ return err;
+
+ /* trigger dma start read */
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_RD_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_RD_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_STA_CTL1, val,
+ (val & SPI_NFI_READ_FROM_CACHE_DONE),
+ 0, 1 * USEC_PER_SEC);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
+ SPI_NFI_READ_FROM_CACHE_DONE);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
+ val, (val & SPI_NFI_AHB_DONE), 0,
+ 1 * USEC_PER_SEC);
+ if (err)
+ return err;
+
+ /* DMA read need delay for data ready from controller to DRAM */
+ udelay(1);
+
+ dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ memcpy(buf, as_dev->txrx_buf + offs, len);
+
+ return len;
+}
+
+static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, const void *buf)
+{
+ struct spi_device *spi = desc->mem->spi;
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ struct spi_mem_op *op = &desc->info.op_tmpl;
+ struct airoha_snand_ctrl *as_ctrl;
+ u32 wr_mode, val;
+ int err;
+
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ memcpy(as_dev->txrx_buf + offs, buf, len);
+ dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_nfi_config(as_ctrl);
+ if (err)
+ return err;
+
+ if (op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_QUAD ||
+ op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD)
+ wr_mode = BIT(1);
+ else
+ wr_mode = 0;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
+ as_dev->dma_addr);
+ if (err)
+ return err;
+
+ val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM,
+ as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num);
+ err = regmap_update_bits(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_MISC_CTL2,
+ SPI_NFI_PROG_LOAD_BYTE_NUM, val);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL1,
+ FIELD_PREP(SPI_NFI_PG_LOAD_CMD,
+ op->cmd.opcode));
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
+ FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, wr_mode));
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 0x0);
+ if (err)
+ return err;
+
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_READ_MODE);
+ if (err)
+ return err;
+
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_OPMODE,
+ FIELD_PREP(SPI_NFI_OPMODE, 3));
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_DMA_MODE);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
+ if (err)
+ return err;
+
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_WR_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_WR_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
+ val, (val & SPI_NFI_AHB_DONE), 0,
+ 1 * USEC_PER_SEC);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_STA_CTL1, val,
+ (val & SPI_NFI_LOAD_TO_CACHE_DONE),
+ 0, 1 * USEC_PER_SEC);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
+ SPI_NFI_LOAD_TO_CACHE_DONE);
+ if (err)
+ return err;
+
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ return len;
+}
+
+static int airoha_snand_exec_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(mem->spi);
+ u8 data[8], cmd, opcode = op->cmd.opcode;
+ struct airoha_snand_ctrl *as_ctrl;
+ int i, err;
+
+ as_ctrl = spi_controller_get_devdata(mem->spi->controller);
+ if (opcode == SPI_NAND_OP_PROGRAM_EXECUTE &&
+ op->addr.val == as_dev->cur_page_num) {
+ as_dev->data_need_update = true;
+ } else if (opcode == SPI_NAND_OP_PAGE_READ) {
+ if (!as_dev->data_need_update &&
+ op->addr.val == as_dev->cur_page_num)
+ return 0;
+
+ as_dev->data_need_update = true;
+ as_dev->cur_page_num = op->addr.val;
+ }
+
+ /* switch to manual mode */
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_LOW);
+ if (err < 0)
+ return err;
+
+ /* opcode */
+ err = airoha_snand_write_data(as_ctrl, 0x8, &opcode, sizeof(opcode));
+ if (err)
+ return err;
+
+ /* addr part */
+ cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
+ put_unaligned_be64(op->addr.val, data);
+
+ for (i = ARRAY_SIZE(data) - op->addr.nbytes;
+ i < ARRAY_SIZE(data); i++) {
+ err = airoha_snand_write_data(as_ctrl, cmd, &data[i],
+ sizeof(data[0]));
+ if (err)
+ return err;
+ }
+
+ /* dummy */
+ data[0] = 0xff;
+ for (i = 0; i < op->dummy.nbytes; i++) {
+ err = airoha_snand_write_data(as_ctrl, 0x8, &data[0],
+ sizeof(data[0]));
+ if (err)
+ return err;
+ }
+
+ /* data */
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ err = airoha_snand_read_data(as_ctrl, op->data.buf.in,
+ op->data.nbytes);
+ if (err)
+ return err;
+ } else {
+ err = airoha_snand_write_data(as_ctrl, 0x8, op->data.buf.out,
+ op->data.nbytes);
+ if (err)
+ return err;
+ }
+
+ return airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_HIGH);
+}
+
+static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
+ .adjust_op_size = airoha_snand_adjust_op_size,
+ .supports_op = airoha_snand_supports_op,
+ .exec_op = airoha_snand_exec_op,
+ .dirmap_create = airoha_snand_dirmap_create,
+ .dirmap_read = airoha_snand_dirmap_read,
+ .dirmap_write = airoha_snand_dirmap_write,
+};
+
+static int airoha_snand_setup(struct spi_device *spi)
+{
+ struct airoha_snand_ctrl *as_ctrl;
+ struct airoha_snand_dev *as_dev;
+
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+
+ as_dev = devm_kzalloc(as_ctrl->dev, sizeof(*as_dev), GFP_KERNEL);
+ if (!as_dev)
+ return -ENOMEM;
+
+ /* prepare device buffer */
+ as_dev->buf_len = SPI_NAND_CACHE_SIZE;
+ as_dev->txrx_buf = devm_kzalloc(as_ctrl->dev, as_dev->buf_len,
+ GFP_KERNEL);
+ if (!as_dev->txrx_buf)
+ return -ENOMEM;
+
+ as_dev->dma_addr = dma_map_single(as_ctrl->dev, as_dev->txrx_buf,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ if (dma_mapping_error(as_ctrl->dev, as_dev->dma_addr))
+ return -ENOMEM;
+
+ as_dev->data_need_update = true;
+ spi_set_ctldata(spi, as_dev);
+
+ return 0;
+}
+
+static void airoha_snand_cleanup(struct spi_device *spi)
+{
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ struct airoha_snand_ctrl *as_ctrl;
+
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+ dma_unmap_single(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ spi_set_ctldata(spi, NULL);
+}
+
+static int airoha_snand_nfi_setup(struct airoha_snand_ctrl *as_ctrl)
+{
+ u32 val, sec_size, sec_num;
+ int err;
+
+ err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, &val);
+ if (err)
+ return err;
+
+ sec_num = FIELD_GET(SPI_NFI_SEC_NUM, val);
+
+ err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE, &val);
+ if (err)
+ return err;
+
+ sec_size = FIELD_GET(SPI_NFI_CUS_SEC_SIZE, val);
+
+ /* init default value */
+ as_ctrl->nfi_cfg.sec_size = sec_size;
+ as_ctrl->nfi_cfg.sec_num = sec_num;
+ as_ctrl->nfi_cfg.page_size = round_down(sec_size * sec_num, 1024);
+ as_ctrl->nfi_cfg.spare_size = 16;
+
+ err = airoha_snand_nfi_init(as_ctrl);
+ if (err)
+ return err;
+
+ return airoha_snand_nfi_config(as_ctrl);
+}
+
+static const struct regmap_config spi_ctrl_regmap_config = {
+ .name = "ctrl",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = REG_SPI_CTRL_NFI2SPI_EN,
+};
+
+static const struct regmap_config spi_nfi_regmap_config = {
+ .name = "nfi",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = REG_SPI_NFI_SNF_NFI_CNFG,
+};
+
+static const struct of_device_id airoha_snand_ids[] = {
+ { .compatible = "airoha,en7581-snand" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_snand_ids);
+
+static int airoha_snand_probe(struct platform_device *pdev)
+{
+ struct airoha_snand_ctrl *as_ctrl;
+ struct device *dev = &pdev->dev;
+ struct spi_controller *ctrl;
+ void __iomem *base;
+ int err;
+
+ ctrl = devm_spi_alloc_host(dev, sizeof(*as_ctrl));
+ if (!ctrl)
+ return -ENOMEM;
+
+ as_ctrl = spi_controller_get_devdata(ctrl);
+ as_ctrl->dev = dev;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ as_ctrl->regmap_ctrl = devm_regmap_init_mmio(dev, base,
+ &spi_ctrl_regmap_config);
+ if (IS_ERR(as_ctrl->regmap_ctrl))
+ return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_ctrl),
+ "failed to init spi ctrl regmap\n");
+
+ base = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ as_ctrl->regmap_nfi = devm_regmap_init_mmio(dev, base,
+ &spi_nfi_regmap_config);
+ if (IS_ERR(as_ctrl->regmap_nfi))
+ return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_nfi),
+ "failed to init spi nfi regmap\n");
+
+ as_ctrl->spi_clk = devm_clk_get_enabled(dev, "spi");
+ if (IS_ERR(as_ctrl->spi_clk))
+ return dev_err_probe(dev, PTR_ERR(as_ctrl->spi_clk),
+ "unable to get spi clk\n");
+
+ err = dma_set_mask(as_ctrl->dev, DMA_BIT_MASK(32));
+ if (err)
+ return err;
+
+ ctrl->num_chipselect = 2;
+ ctrl->mem_ops = &airoha_snand_mem_ops;
+ ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
+ ctrl->mode_bits = SPI_RX_DUAL;
+ ctrl->setup = airoha_snand_setup;
+ ctrl->cleanup = airoha_snand_cleanup;
+ device_set_node(&ctrl->dev, dev_fwnode(dev));
+
+ err = airoha_snand_nfi_setup(as_ctrl);
+ if (err)
+ return err;
+
+ return devm_spi_register_controller(dev, ctrl);
+}
+
+static struct platform_driver airoha_snand_driver = {
+ .driver = {
+ .name = "airoha-spi",
+ .of_match_table = airoha_snand_ids,
+ },
+ .probe = airoha_snand_probe,
+};
+module_platform_driver(airoha_snand_driver);
+
+MODULE_DESCRIPTION("Airoha SPI-NAND Flash Controller Driver");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Ray Liu <ray.liu@airoha.com>");
+MODULE_LICENSE("GPL");
--
2.44.0
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^ permalink raw reply related [relevance 2%]
* [PATCH] dmaengine: bcm2835-dma: Add check for dma_set_max_seg_size
@ 2024-04-29 4:13 6% Chen Ni
0 siblings, 0 replies; 200+ results
From: Chen Ni @ 2024-04-29 4:13 UTC (permalink / raw)
To: vkoul, florian.fainelli, rjui, sbranden
Cc: bcm-kernel-feedback-list, dmaengine, linux-rpi-kernel,
linux-arm-kernel, linux-kernel, Chen Ni
Add check for the return value of dma_set_max_seg_size() and return
the error if it fails in order to catch the error.
Signed-off-by: Chen Ni <nichen@iscas.ac.cn>
---
drivers/dma/bcm2835-dma.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index 9d74fe97452e..d1e775a2f6b3 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -899,7 +899,11 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
if (!od)
return -ENOMEM;
- dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
+ rc = dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
+ if (rc) {
+ dev_err(&pdev->dev, "Unable to set dma device segment size\n");
+ return rc;
+ }
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
--
2.25.1
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^ permalink raw reply related [relevance 6%]
* Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6
2024-04-28 11:40 5% ` [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6 Dragan Simic
@ 2024-04-28 16:21 0% ` Jernej Škrabec
2024-04-29 23:10 0% ` Andre Przywara
1 sibling, 0 replies; 200+ results
From: Jernej Škrabec @ 2024-04-28 16:21 UTC (permalink / raw)
To: linux-sunxi, Dragan Simic
Cc: wens, samuel, linux-arm-kernel, devicetree, robh, krzk+dt,
conor+dt, linux-kernel
Dne nedelja, 28. april 2024 ob 13:40:36 GMT +2 je Dragan Simic napisal(a):
> Add missing cache information to the Allwinner H6 SoC dtsi, to allow
> the userspace, which includes lscpu(1) that uses the virtual files provided
> by the kernel under the /sys/devices/system/cpu directory, to display the
> proper H6 cache information.
>
> Adding the cache information to the H6 SoC dtsi also makes the following
> warning message in the kernel log go away:
>
> cacheinfo: Unable to detect cache hierarchy for CPU 0
>
> The cache parameters for the H6 dtsi were obtained and partially derived
> by hand from the cache size and layout specifications found in the following
> datasheets and technical reference manuals:
>
> - Allwinner H6 V200 datasheet, version 1.1
> - ARM Cortex-A53 revision r0p3 TRM, version E
>
> For future reference, here's a brief summary of the documentation:
>
> - All caches employ the 64-byte cache line length
> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction
> cache and 32 KB of L1 4-way, set-associative data cache
> - The entire SoC has 512 KB of unified L2 16-way, set-associative cache
>
> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
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^ permalink raw reply [relevance 0%]
* [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6
@ 2024-04-28 11:40 5% ` Dragan Simic
2024-04-28 16:21 0% ` Jernej Škrabec
2024-04-29 23:10 0% ` Andre Przywara
0 siblings, 2 replies; 200+ results
From: Dragan Simic @ 2024-04-28 11:40 UTC (permalink / raw)
To: linux-sunxi
Cc: wens, jernej.skrabec, samuel, linux-arm-kernel, devicetree, robh,
krzk+dt, conor+dt, linux-kernel
Add missing cache information to the Allwinner H6 SoC dtsi, to allow
the userspace, which includes lscpu(1) that uses the virtual files provided
by the kernel under the /sys/devices/system/cpu directory, to display the
proper H6 cache information.
Adding the cache information to the H6 SoC dtsi also makes the following
warning message in the kernel log go away:
cacheinfo: Unable to detect cache hierarchy for CPU 0
The cache parameters for the H6 dtsi were obtained and partially derived
by hand from the cache size and layout specifications found in the following
datasheets and technical reference manuals:
- Allwinner H6 V200 datasheet, version 1.1
- ARM Cortex-A53 revision r0p3 TRM, version E
For future reference, here's a brief summary of the documentation:
- All caches employ the 64-byte cache line length
- Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction
cache and 32 KB of L1 4-way, set-associative data cache
- The entire SoC has 512 KB of unified L2 16-way, set-associative cache
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 37 ++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index d11e5041bae9..1a63066396e8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -29,36 +29,73 @@ cpu0: cpu@0 {
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* [PATCH v3 2/6] pinctrl: scmi: move pinctrl_ops to scmi_pinctrl
@ 2024-04-28 5:07 5% ` Peng Fan (OSS)
0 siblings, 0 replies; 200+ results
From: Peng Fan (OSS) @ 2024-04-28 5:07 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Linus Walleij, Dong Aisheng, Jacky Bai
Cc: linux-arm-kernel, devicetree, linux-kernel, imx, linux-gpio, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Make pinctrl_ops a global variable not able to support multiple
protocol@19 nodes, so make it per scmi_pinctrl.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/pinctrl/pinctrl-scmi.c | 35 ++++++++++++++++++-----------------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c
index 036bc1e3fc6c..682ff595c3c7 100644
--- a/drivers/pinctrl/pinctrl-scmi.c
+++ b/drivers/pinctrl/pinctrl-scmi.c
@@ -30,8 +30,6 @@
/* Define num configs, if not large than 4 use stack, else use kcalloc() */
#define SCMI_NUM_CONFIGS 4
-static const struct scmi_pinctrl_proto_ops *pinctrl_ops;
-
struct scmi_pinctrl {
struct device *dev;
struct scmi_protocol_handle *ph;
@@ -41,13 +39,14 @@ struct scmi_pinctrl {
unsigned int nr_functions;
struct pinctrl_pin_desc *pins;
unsigned int nr_pins;
+ const struct scmi_pinctrl_proto_ops *ops;
};
static int pinctrl_scmi_get_groups_count(struct pinctrl_dev *pctldev)
{
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- return pinctrl_ops->count_get(pmx->ph, GROUP_TYPE);
+ return pmx->ops->count_get(pmx->ph, GROUP_TYPE);
}
static const char *pinctrl_scmi_get_group_name(struct pinctrl_dev *pctldev,
@@ -57,7 +56,7 @@ static const char *pinctrl_scmi_get_group_name(struct pinctrl_dev *pctldev,
const char *name;
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- ret = pinctrl_ops->name_get(pmx->ph, selector, GROUP_TYPE, &name);
+ ret = pmx->ops->name_get(pmx->ph, selector, GROUP_TYPE, &name);
if (ret) {
dev_err(pmx->dev, "get name failed with err %d", ret);
return NULL;
@@ -73,7 +72,7 @@ static int pinctrl_scmi_get_group_pins(struct pinctrl_dev *pctldev,
{
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- return pinctrl_ops->group_pins_get(pmx->ph, selector, pins, num_pins);
+ return pmx->ops->group_pins_get(pmx->ph, selector, pins, num_pins);
}
static const struct pinctrl_ops pinctrl_scmi_pinctrl_ops = {
@@ -90,7 +89,7 @@ static int pinctrl_scmi_get_functions_count(struct pinctrl_dev *pctldev)
{
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- return pinctrl_ops->count_get(pmx->ph, FUNCTION_TYPE);
+ return pmx->ops->count_get(pmx->ph, FUNCTION_TYPE);
}
static const char *pinctrl_scmi_get_function_name(struct pinctrl_dev *pctldev,
@@ -100,7 +99,7 @@ static const char *pinctrl_scmi_get_function_name(struct pinctrl_dev *pctldev,
const char *name;
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- ret = pinctrl_ops->name_get(pmx->ph, selector, FUNCTION_TYPE, &name);
+ ret = pmx->ops->name_get(pmx->ph, selector, FUNCTION_TYPE, &name);
if (ret) {
dev_err(pmx->dev, "get name failed with err %d", ret);
return NULL;
@@ -131,7 +130,7 @@ static int pinctrl_scmi_get_function_groups(struct pinctrl_dev *pctldev,
if (func->ngroups)
goto done;
- ret = pinctrl_ops->function_groups_get(pmx->ph, selector, &num_groups,
+ ret = pmx->ops->function_groups_get(pmx->ph, selector, &num_groups,
&group_ids);
if (ret) {
dev_err(pmx->dev, "Unable to get function groups, err %d", ret);
@@ -171,7 +170,7 @@ static int pinctrl_scmi_func_set_mux(struct pinctrl_dev *pctldev,
{
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- return pinctrl_ops->mux_set(pmx->ph, selector, group);
+ return pmx->ops->mux_set(pmx->ph, selector, group);
}
static int pinctrl_scmi_request(struct pinctrl_dev *pctldev,
@@ -179,14 +178,14 @@ static int pinctrl_scmi_request(struct pinctrl_dev *pctldev,
{
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- return pinctrl_ops->pin_request(pmx->ph, offset);
+ return pmx->ops->pin_request(pmx->ph, offset);
}
static int pinctrl_scmi_free(struct pinctrl_dev *pctldev, unsigned int offset)
{
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
- return pinctrl_ops->pin_free(pmx->ph, offset);
+ return pmx->ops->pin_free(pmx->ph, offset);
}
static const struct pinmux_ops pinctrl_scmi_pinmux_ops = {
@@ -295,7 +294,7 @@ static int pinctrl_scmi_pinconf_get(struct pinctrl_dev *pctldev,
if (ret)
return ret;
- ret = pinctrl_ops->settings_get_one(pmx->ph, pin, PIN_TYPE, type,
+ ret = pmx->ops->settings_get_one(pmx->ph, pin, PIN_TYPE, type,
&config_value);
/* Convert SCMI error code to PINCTRL expected error code */
if (ret == -EOPNOTSUPP)
@@ -372,7 +371,7 @@ static int pinctrl_scmi_pinconf_set(struct pinctrl_dev *pctldev,
p_config_value[i] = pinconf_to_config_argument(configs[i]);
}
- ret = pinctrl_ops->settings_conf(pmx->ph, pin, PIN_TYPE, num_configs,
+ ret = pmx->ops->settings_conf(pmx->ph, pin, PIN_TYPE, num_configs,
p_config_type, p_config_value);
if (ret)
dev_err(pmx->dev, "Error parsing config %d\n", ret);
@@ -415,7 +414,7 @@ static int pinctrl_scmi_pinconf_group_set(struct pinctrl_dev *pctldev,
p_config_value[i] = pinconf_to_config_argument(configs[i]);
}
- ret = pinctrl_ops->settings_conf(pmx->ph, group, GROUP_TYPE,
+ ret = pmx->ops->settings_conf(pmx->ph, group, GROUP_TYPE,
num_configs, p_config_type,
p_config_value);
if (ret)
@@ -447,7 +446,7 @@ static int pinctrl_scmi_pinconf_group_get(struct pinctrl_dev *pctldev,
return ret;
}
- ret = pinctrl_ops->settings_get_one(pmx->ph, group, GROUP_TYPE, type,
+ ret = pmx->ops->settings_get_one(pmx->ph, group, GROUP_TYPE, type,
&config_value);
/* Convert SCMI error code to PINCTRL expected error code */
if (ret == -EOPNOTSUPP)
@@ -476,7 +475,7 @@ static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx,
unsigned int npins;
int ret, i;
- npins = pinctrl_ops->count_get(pmx->ph, PIN_TYPE);
+ npins = pmx->ops->count_get(pmx->ph, PIN_TYPE);
/*
* npins will never be zero, the scmi pinctrl driver has bailed out
* if npins is zero.
@@ -491,7 +490,7 @@ static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx,
* The memory for name is handled by the scmi firmware driver,
* no need free here
*/
- ret = pinctrl_ops->name_get(pmx->ph, i, PIN_TYPE, &pins[i].name);
+ ret = pmx->ops->name_get(pmx->ph, i, PIN_TYPE, &pins[i].name);
if (ret)
return dev_err_probe(pmx->dev, ret,
"Can't get name for pin %d", i);
@@ -511,6 +510,7 @@ static int scmi_pinctrl_probe(struct scmi_device *sdev)
struct scmi_pinctrl *pmx;
const struct scmi_handle *handle;
struct scmi_protocol_handle *ph;
+ const struct scmi_pinctrl_proto_ops *pinctrl_ops;
if (!sdev->handle)
return -EINVAL;
@@ -526,6 +526,7 @@ static int scmi_pinctrl_probe(struct scmi_device *sdev)
return -ENOMEM;
pmx->ph = ph;
+ pmx->ops = pinctrl_ops;
pmx->dev = dev;
pmx->pctl_desc.name = DRV_NAME;
--
2.37.1
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^ permalink raw reply related [relevance 5%]
* Re: [PATCH v3 11/11] PCI: imx6: Add i.MX8Q PCIe support
@ 2024-04-27 11:47 0% ` Manivannan Sadhasivam
2024-04-29 17:56 0% ` Frank Li
0 siblings, 1 reply; 200+ results
From: Manivannan Sadhasivam @ 2024-04-27 11:47 UTC (permalink / raw)
To: Frank Li
Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Krzysztof Kozlowski, Conor Dooley, linux-pci, imx,
linux-arm-kernel, linux-kernel, bpf, devicetree
On Tue, Apr 02, 2024 at 10:33:47AM -0400, Frank Li wrote:
> From: Richard Zhu <hongxing.zhu@nxp.com>
>
> Add i.MX8Q (i.MX8QM, i.MX8QXP and i.MX8DXL) PCIe support.
>
Add some info like IP version, PCIe Gen, how different the code support
comparted to previous SoCs etc...
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> drivers/pci/controller/dwc/pcie-imx.c | 54 +++++++++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c
> index 378808262d16b..af7c79e869e70 100644
> --- a/drivers/pci/controller/dwc/pcie-imx.c
> +++ b/drivers/pci/controller/dwc/pcie-imx.c
> @@ -30,6 +30,7 @@
> #include <linux/interrupt.h>
> #include <linux/reset.h>
> #include <linux/phy/phy.h>
> +#include <linux/phy/pcie.h>
> #include <linux/pm_domain.h>
> #include <linux/pm_runtime.h>
>
> @@ -81,6 +82,7 @@ enum imx_pcie_variants {
> IMX8MQ,
> IMX8MM,
> IMX8MP,
> + IMX8Q,
> IMX95,
> IMX8MQ_EP,
> IMX8MM_EP,
> @@ -96,6 +98,7 @@ enum imx_pcie_variants {
> #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5)
> #define IMX_PCIE_FLAG_HAS_SERDES BIT(6)
> #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7)
> +#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8)
>
> #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
>
> @@ -132,6 +135,7 @@ struct imx_pcie {
> struct regmap *iomuxc_gpr;
> u16 msi_ctrl;
> u32 controller_id;
> + u32 local_addr;
> struct reset_control *pciephy_reset;
> struct reset_control *apps_reset;
> struct reset_control *turnoff_reset;
> @@ -402,6 +406,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
> if (!drvdata->mode_mask[id])
> id = 0;
>
> + /* If mode_mask is 0, means use phy driver to set mode */
> + if (!drvdata->mode_mask[id])
> + return;
There is already a check above for 0 mode_mask. Please consolidate.
> +
> mask = drvdata->mode_mask[id];
> val = mode << (ffs(mask) - 1);
>
> @@ -957,6 +965,7 @@ static void imx_pcie_ltssm_enable(struct device *dev)
> struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
>
> + phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB);
> if (drvdata->ltssm_mask)
> regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
> drvdata->ltssm_mask);
> @@ -969,6 +978,7 @@ static void imx_pcie_ltssm_disable(struct device *dev)
> struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
>
> + phy_set_speed(imx_pcie->phy, 0);
> if (drvdata->ltssm_mask)
> regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
> drvdata->ltssm_mask, 0);
> @@ -1104,6 +1114,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
> goto err_clk_disable;
> }
>
> + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
> + if (ret) {
> + dev_err(dev, "unable to set pcie PHY mode\n");
> + goto err_phy_off;
> + }
This is not i.MX8Q specific. Please add it in a separate patch.
> +
> ret = phy_power_on(imx_pcie->phy);
> if (ret) {
> dev_err(dev, "waiting for PHY ready timeout!\n");
> @@ -1154,6 +1170,28 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
> regulator_disable(imx_pcie->vpcie);
> }
>
> +static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr)
> +{
> + struct imx_pcie *imx_pcie = to_imx_pcie(pcie);
> + struct dw_pcie_ep *ep = &pcie->ep;
> + struct dw_pcie_rp *pp = &pcie->pp;
> + struct resource_entry *entry;
> + unsigned int offset;
> +
> + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP))
This flag should be documented in the commit message.
> + return cpu_addr;
> +
> + if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
> + offset = ep->phys_base;
> + } else {
> + entry = resource_list_first_type(&pp->bridge->windows,
> + IORESOURCE_MEM);
Check for NULL entry.
> + offset = entry->res->start;
> + }
> +
> + return (cpu_addr + imx_pcie->local_addr - offset);
> +}
> +
> static const struct dw_pcie_host_ops imx_pcie_host_ops = {
> .init = imx_pcie_host_init,
> .deinit = imx_pcie_host_exit,
> @@ -1162,6 +1200,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = {
> static const struct dw_pcie_ops dw_pcie_ops = {
> .start_link = imx_pcie_start_link,
> .stop_link = imx_pcie_stop_link,
> + .cpu_addr_fixup = imx_pcie_cpu_addr_fixup,
> };
>
> static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
> @@ -1481,6 +1520,12 @@ static int imx_pcie_probe(struct platform_device *pdev)
> "Failed to get PCIEPHY reset control\n");
> }
>
> + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) {
> + ret = of_property_read_u32(node, "fsl,local-address", &imx_pcie->local_addr);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to get local-address");
Is it OK to continue?
- Mani
--
மணிவண்ணன் சதாசிவம்
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 07/11] PCI: imx: Simplify switch-case logic by involve core_reset callback
@ 2024-04-27 10:19 0% ` Manivannan Sadhasivam
2024-04-29 16:38 0% ` Frank Li
0 siblings, 1 reply; 200+ results
From: Manivannan Sadhasivam @ 2024-04-27 10:19 UTC (permalink / raw)
To: Frank Li
Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Krzysztof Kozlowski, Conor Dooley, linux-pci, imx,
linux-arm-kernel, linux-kernel, bpf, devicetree
On Tue, Apr 02, 2024 at 10:33:43AM -0400, Frank Li wrote:
> Instead of using the switch case statement to assert/dassert the core reset
> handled by this driver itself, let's introduce a new callback core_reset()
> and define it for platforms that require it. This simplifies the code.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> drivers/pci/controller/dwc/pcie-imx.c | 131 ++++++++++++++++++----------------
> 1 file changed, 68 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c
> index 77dae5c3f7057..af0f960f28757 100644
> --- a/drivers/pci/controller/dwc/pcie-imx.c
> +++ b/drivers/pci/controller/dwc/pcie-imx.c
> @@ -104,6 +104,7 @@ struct imx_pcie_drvdata {
> const struct pci_epc_features *epc_features;
> int (*init_phy)(struct imx_pcie *pcie);
> int (*set_ref_clk)(struct imx_pcie *pcie, bool enable);
> + int (*core_reset)(struct imx_pcie *pcie, bool assert);
> };
>
> struct imx_pcie {
> @@ -671,35 +672,72 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
> clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
> }
>
> +static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> +{
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
> + assert ? IMX6SX_GPR12_PCIE_TEST_POWERDOWN : 0);
Earlier, this register was not cleared during deassert. Is if fine?
> + /* Force PCIe PHY reset */
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET,
> + assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0);
> + return 0;
> +}
> +
> +static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> +{
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST,
> + assert ? IMX6Q_GPR1_PCIE_SW_RST : 0);
> + if (!assert)
> + usleep_range(200, 500);
> +
> + return 0;
> +}
> +
> +static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> +{
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD,
> + assert ? IMX6Q_GPR1_PCIE_TEST_PD : 0);
> +
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN,
> + assert ? 0 : IMX6Q_GPR1_PCIE_REF_CLK_EN);
> +
Same comment as above.
> + return 0;
> +}
> +
> +static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> +{
> + struct dw_pcie *pci = imx_pcie->pci;
> + struct device *dev = pci->dev;
> +
> + if (assert)
> + return 0;
> +
> + /*
> + * Workaround for ERR010728, failure of PCI-e PLL VCO to oscillate, especially when cold.
What does 'especially when cold' means? I know it is an old comment, but still
it is not very clear.
> + * This turns off "Duty-cycle Corrector" and other mysterious undocumented things.
Same comment as previous patch.
> + */
> +
> + if (likely(imx_pcie->phy_base)) {
> + /* De-assert DCC_FB_EN */
> + writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
> + /* Assert RX_EQS and RX_EQS_SEL */
> + writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ,
> + imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
> + /* Assert ATT_MODE */
> + writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
Why does this workaround a part of core_reset handling? This function doesn't
look like performing reset at all.
- Mani
> + } else {
> + dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
> + }
> + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
> + return 0;
> +}
> +
> static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
> {
> reset_control_assert(imx_pcie->pciephy_reset);
> reset_control_assert(imx_pcie->apps_reset);
>
> - switch (imx_pcie->drvdata->variant) {
> - case IMX6SX:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> - IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
> - IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
> - /* Force PCIe PHY reset */
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
> - IMX6SX_GPR5_PCIE_BTNRST_RESET,
> - IMX6SX_GPR5_PCIE_BTNRST_RESET);
> - break;
> - case IMX6QP:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_SW_RST,
> - IMX6Q_GPR1_PCIE_SW_RST);
> - break;
> - case IMX6Q:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
> - break;
> - default:
> - break;
> - }
> + if (imx_pcie->drvdata->core_reset)
> + imx_pcie->drvdata->core_reset(imx_pcie, true);
>
> /* Some boards don't have PCIe reset GPIO. */
> if (gpio_is_valid(imx_pcie->reset_gpio))
> @@ -709,47 +747,10 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
>
> static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
> {
> - struct dw_pcie *pci = imx_pcie->pci;
> - struct device *dev = pci->dev;
> -
> reset_control_deassert(imx_pcie->pciephy_reset);
>
> - switch (imx_pcie->drvdata->variant) {
> - case IMX7D:
> - /* Workaround for ERR010728, failure of PCI-e PLL VCO to
> - * oscillate, especially when cold. This turns off "Duty-cycle
> - * Corrector" and other mysterious undocumented things.
> - */
> - if (likely(imx_pcie->phy_base)) {
> - /* De-assert DCC_FB_EN */
> - writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
> - imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
> - /* Assert RX_EQS and RX_EQS_SEL */
> - writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
> - | PCIE_PHY_CMN_REG24_RX_EQ,
> - imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
> - /* Assert ATT_MODE */
> - writel(PCIE_PHY_CMN_REG26_ATT_MODE,
> - imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
> - } else {
> - dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
> - }
> -
> - imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
> - break;
> - case IMX6SX:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
> - IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
> - break;
> - case IMX6QP:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_SW_RST, 0);
> -
> - usleep_range(200, 500);
> - break;
> - default:
> - break;
> - }
> + if (imx_pcie->drvdata->core_reset)
> + imx_pcie->drvdata->core_reset(imx_pcie, false);
>
> /* Some boards don't have PCIe reset GPIO. */
> if (gpio_is_valid(imx_pcie->reset_gpio)) {
> @@ -1447,6 +1448,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> .init_phy = imx_pcie_init_phy,
> .set_ref_clk = imx6q_pcie_set_ref_clk,
> + .core_reset = imx6q_pcie_core_reset,
> },
> [IMX6SX] = {
> .variant = IMX6SX,
> @@ -1462,6 +1464,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> .init_phy = imx6sx_pcie_init_phy,
> .set_ref_clk = imx6sx_pcie_set_ref_clk,
> + .core_reset = imx6sx_pcie_core_reset,
> },
> [IMX6QP] = {
> .variant = IMX6QP,
> @@ -1478,6 +1481,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> .init_phy = imx_pcie_init_phy,
> .set_ref_clk = imx6q_pcie_set_ref_clk,
> + .core_reset = imx6qp_pcie_core_reset,
> },
> [IMX7D] = {
> .variant = IMX7D,
> @@ -1491,6 +1495,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> .init_phy = imx7d_pcie_init_phy,
> .set_ref_clk = imx7d_pcie_set_ref_clk,
> + .core_reset = imx7d_pcie_core_reset,
> },
> [IMX8MQ] = {
> .variant = IMX8MQ,
>
> --
> 2.34.1
>
--
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 06/11] PCI: imx: Simplify switch-case logic by involve set_ref_clk callback
@ 2024-04-27 9:54 0% ` Manivannan Sadhasivam
0 siblings, 0 replies; 200+ results
From: Manivannan Sadhasivam @ 2024-04-27 9:54 UTC (permalink / raw)
To: Frank Li
Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Krzysztof Kozlowski, Conor Dooley, linux-pci, imx,
linux-arm-kernel, linux-kernel, bpf, devicetree
On Tue, Apr 02, 2024 at 10:33:42AM -0400, Frank Li wrote:
PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
> Instead of using the switch case statement to enable/disable the reference
> clock handled by this driver itself, let's introduce a new callback
> set_ref_clk() and define it for platforms that require it. This simplifies
> the code.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> drivers/pci/controller/dwc/pcie-imx.c | 119 ++++++++++++++++------------------
> 1 file changed, 55 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c
> index e93070d60df52..77dae5c3f7057 100644
> --- a/drivers/pci/controller/dwc/pcie-imx.c
> +++ b/drivers/pci/controller/dwc/pcie-imx.c
> @@ -103,6 +103,7 @@ struct imx_pcie_drvdata {
> const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
> const struct pci_epc_features *epc_features;
> int (*init_phy)(struct imx_pcie *pcie);
> + int (*set_ref_clk)(struct imx_pcie *pcie, bool enable);
> };
>
> struct imx_pcie {
> @@ -585,77 +586,54 @@ static int imx_pcie_attach_pd(struct device *dev)
> return 0;
> }
>
> -static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
> +static int imx6sx_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> {
> - unsigned int offset;
> - int ret = 0;
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
> + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
>
> - switch (imx_pcie->drvdata->variant) {
> - case IMX6SX:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
> - break;
> - case IMX6QP:
> - case IMX6Q:
> + return 0;
> +}
> +
> +static int imx6q_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> +{
> + if (enable) {
> /* power up core phy and enable ref clock */
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0);
> /*
> - * the async reset input need ref clock to sync internally,
> - * when the ref clock comes after reset, internal synced
> - * reset time is too short, cannot meet the requirement.
> - * add one ~10us delay here.
> + * the async reset input need ref clock to sync internally, when the ref clock comes
> + * after reset, internal synced reset time is too short, cannot meet the
> + * requirement.add one ~10us delay here.
Please wrap the comments to 80 column width.
> */
> usleep_range(10, 100);
> regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
> - break;
> - case IMX7D:
> - case IMX95:
> - case IMX95_EP:
> - break;
> - case IMX8MM:
> - case IMX8MM_EP:
> - case IMX8MQ:
> - case IMX8MQ_EP:
> - case IMX8MP:
> - case IMX8MP_EP:
> - offset = imx_pcie_grp_offset(imx_pcie);
> - /*
> - * Set the over ride low and enabled
> - * make sure that REF_CLK is turned on.
> - */
> - regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
> - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
> - 0);
> - regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
> - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
> - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
> - break;
> + IMX6Q_GPR1_PCIE_REF_CLK_EN, IMX6Q_GPR1_PCIE_REF_CLK_EN);
> + } else {
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD);
> }
>
> - return ret;
> + return 0;
> }
>
> -static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie)
> +static int imx8mm_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> {
> - switch (imx_pcie->drvdata->variant) {
> - case IMX6QP:
> - case IMX6Q:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> - IMX6Q_GPR1_PCIE_TEST_PD,
> - IMX6Q_GPR1_PCIE_TEST_PD);
> - break;
> - case IMX7D:
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
> - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
> - break;
> - default:
> - break;
> - }
> + int offset = imx_pcie_grp_offset(imx_pcie);
> +
> + /* Set the over ride low and enabled make sure that REF_CLK is turned on.*/
> + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
> + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
> + enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0);
Extra space after :
> + return 0;
> +}
> +
> +static int imx7d_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> +{
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
> + enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
> + return 0;
> }
>
> static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
> @@ -668,10 +646,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
> if (ret)
> return ret;
>
> - ret = imx_pcie_enable_ref_clk(imx_pcie);
> - if (ret) {
> - dev_err(dev, "unable to enable pcie ref clock\n");
> - goto err_ref_clk;
> + if (imx_pcie->drvdata->set_ref_clk) {
> + ret = imx_pcie->drvdata->set_ref_clk(imx_pcie, true);
> + if (ret) {
> + dev_err(dev, "unable to enable pcie ref clock\n");
'Failed to enable PCIe REFCLK'
- Mani
--
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 03/11] PCI: imx6: Rename imx6_* with imx_*
@ 2024-04-27 9:29 0% ` Manivannan Sadhasivam
0 siblings, 0 replies; 200+ results
From: Manivannan Sadhasivam @ 2024-04-27 9:29 UTC (permalink / raw)
To: Frank Li
Cc: Richard Zhu, Lucas Stach, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Philipp Zabel, Liam Girdwood, Mark Brown,
Krzysztof Kozlowski, Conor Dooley, linux-pci, imx,
linux-arm-kernel, linux-kernel, bpf, devicetree
On Tue, Apr 02, 2024 at 10:33:39AM -0400, Frank Li wrote:
PCI: imx6: Rename 'imx6' prefix to 'imx'
> imx6_* actually mean for all imx chips (imx6x, imx7x, imx8x and imx9x).
> Rename imx6_* with imx_* to avoid confuse.
>
'Since this driver has evolved to support other i.MX SoCs such as i.MX7/8/9,
let's rename the 'imx6' prefix to 'imx' to avoid confusion. But the driver name
is left unchanged to avoid breaking userspace scripts.'
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
With above changes,
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 760 +++++++++++++++++-----------------
> 1 file changed, 380 insertions(+), 380 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 6c4d25b92225e..e93070d60df52 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -55,9 +55,9 @@
> #define IMX95_PE0_GEN_CTRL_3 0x1058
> #define IMX95_PCIE_LTSSM_EN BIT(0)
>
> -#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
> +#define to_imx_pcie(x) dev_get_drvdata((x)->dev)
>
> -enum imx6_pcie_variants {
> +enum imx_pcie_variants {
> IMX6Q,
> IMX6SX,
> IMX6QP,
> @@ -72,25 +72,25 @@ enum imx6_pcie_variants {
> IMX95_EP,
> };
>
> -#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
> -#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
> -#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
> -#define IMX6_PCIE_FLAG_HAS_PHYDRV BIT(3)
> -#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4)
> -#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5)
> -#define IMX6_PCIE_FLAG_HAS_SERDES BIT(6)
> -#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7)
> +#define IMX_PCIE_FLAG_IMX_PHY BIT(0)
> +#define IMX_PCIE_FLAG_IMX_SPEED_CHANGE BIT(1)
> +#define IMX_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
> +#define IMX_PCIE_FLAG_HAS_PHYDRV BIT(3)
> +#define IMX_PCIE_FLAG_HAS_APP_RESET BIT(4)
> +#define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5)
> +#define IMX_PCIE_FLAG_HAS_SERDES BIT(6)
> +#define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7)
>
> -#define imx6_check_flag(pci, val) (pci->drvdata->flags & val)
> +#define imx_check_flag(pci, val) (pci->drvdata->flags & val)
>
> -#define IMX6_PCIE_MAX_CLKS 6
> +#define IMX_PCIE_MAX_CLKS 6
>
> -#define IMX6_PCIE_MAX_INSTANCES 2
> +#define IMX_PCIE_MAX_INSTANCES 2
>
> -struct imx6_pcie;
> +struct imx_pcie;
>
> -struct imx6_pcie_drvdata {
> - enum imx6_pcie_variants variant;
> +struct imx_pcie_drvdata {
> + enum imx_pcie_variants variant;
> enum dw_pcie_device_mode mode;
> u32 flags;
> int dbi_length;
> @@ -99,18 +99,18 @@ struct imx6_pcie_drvdata {
> const u32 clks_cnt;
> const u32 ltssm_off;
> const u32 ltssm_mask;
> - const u32 mode_off[IMX6_PCIE_MAX_INSTANCES];
> - const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES];
> + const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
> + const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
> const struct pci_epc_features *epc_features;
> - int (*init_phy)(struct imx6_pcie *pcie);
> + int (*init_phy)(struct imx_pcie *pcie);
> };
>
> -struct imx6_pcie {
> +struct imx_pcie {
> struct dw_pcie *pci;
> int reset_gpio;
> bool gpio_active_high;
> bool link_is_up;
> - struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS];
> + struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS];
> struct regmap *iomuxc_gpr;
> u16 msi_ctrl;
> u32 controller_id;
> @@ -131,7 +131,7 @@ struct imx6_pcie {
> /* power domain for pcie phy */
> struct device *pd_pcie_phy;
> struct phy *phy;
> - const struct imx6_pcie_drvdata *drvdata;
> + const struct imx_pcie_drvdata *drvdata;
> };
>
> /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
> @@ -186,28 +186,28 @@ struct imx6_pcie {
> #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5)
> #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3)
>
> -static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
> +static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
> {
> - WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
> - imx6_pcie->drvdata->variant != IMX8MQ_EP &&
> - imx6_pcie->drvdata->variant != IMX8MM &&
> - imx6_pcie->drvdata->variant != IMX8MM_EP &&
> - imx6_pcie->drvdata->variant != IMX8MP &&
> - imx6_pcie->drvdata->variant != IMX8MP_EP);
> - return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
> + WARN_ON(imx_pcie->drvdata->variant != IMX8MQ &&
> + imx_pcie->drvdata->variant != IMX8MQ_EP &&
> + imx_pcie->drvdata->variant != IMX8MM &&
> + imx_pcie->drvdata->variant != IMX8MM_EP &&
> + imx_pcie->drvdata->variant != IMX8MP &&
> + imx_pcie->drvdata->variant != IMX8MP_EP);
> + return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
> }
>
> -static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> +static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
> {
> - regmap_update_bits(imx6_pcie->iomuxc_gpr,
> + regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_SS_RW_REG_0,
> IMX95_PCIE_PHY_CR_PARA_SEL,
> IMX95_PCIE_PHY_CR_PARA_SEL);
>
> - regmap_update_bits(imx6_pcie->iomuxc_gpr,
> + regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_PHY_GEN_CTRL,
> IMX95_PCIE_REF_USE_PAD, 0);
> - regmap_update_bits(imx6_pcie->iomuxc_gpr,
> + regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_SS_RW_REG_0,
> IMX95_PCIE_REF_CLKEN,
> IMX95_PCIE_REF_CLKEN);
> @@ -215,9 +215,9 @@ static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> return 0;
> }
>
> -static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
> +static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
> {
> - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
> + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
> unsigned int mask, val, mode, id;
>
> if (drvdata->mode == DW_PCIE_EP_TYPE)
> @@ -225,7 +225,7 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
> else
> mode = PCI_EXP_TYPE_ROOT_PORT;
>
> - id = imx6_pcie->controller_id;
> + id = imx_pcie->controller_id;
>
> /* If mode_mask[id] is zero, means each controller have its individual gpr */
> if (!drvdata->mode_mask[id])
> @@ -234,12 +234,12 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
> mask = drvdata->mode_mask[id];
> val = mode << (ffs(mask) - 1);
>
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val);
> }
>
> -static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
> +static int pcie_phy_poll_ack(struct imx_pcie *imx_pcie, bool exp_val)
> {
> - struct dw_pcie *pci = imx6_pcie->pci;
> + struct dw_pcie *pci = imx_pcie->pci;
> bool val;
> u32 max_iterations = 10;
> u32 wait_counter = 0;
> @@ -258,9 +258,9 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
> return -ETIMEDOUT;
> }
>
> -static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
> +static int pcie_phy_wait_ack(struct imx_pcie *imx_pcie, int addr)
> {
> - struct dw_pcie *pci = imx6_pcie->pci;
> + struct dw_pcie *pci = imx_pcie->pci;
> u32 val;
> int ret;
>
> @@ -270,24 +270,24 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
> val |= PCIE_PHY_CTRL_CAP_ADR;
> dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
>
> - ret = pcie_phy_poll_ack(imx6_pcie, true);
> + ret = pcie_phy_poll_ack(imx_pcie, true);
> if (ret)
> return ret;
>
> val = PCIE_PHY_CTRL_DATA(addr);
> dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
>
> - return pcie_phy_poll_ack(imx6_pcie, false);
> + return pcie_phy_poll_ack(imx_pcie, false);
> }
>
> /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
> -static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
> +static int pcie_phy_read(struct imx_pcie *imx_pcie, int addr, u16 *data)
> {
> - struct dw_pcie *pci = imx6_pcie->pci;
> + struct dw_pcie *pci = imx_pcie->pci;
> u32 phy_ctl;
> int ret;
>
> - ret = pcie_phy_wait_ack(imx6_pcie, addr);
> + ret = pcie_phy_wait_ack(imx_pcie, addr);
> if (ret)
> return ret;
>
> @@ -295,7 +295,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
> phy_ctl = PCIE_PHY_CTRL_RD;
> dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
>
> - ret = pcie_phy_poll_ack(imx6_pcie, true);
> + ret = pcie_phy_poll_ack(imx_pcie, true);
> if (ret)
> return ret;
>
> @@ -304,18 +304,18 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
> /* deassert Read signal */
> dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
>
> - return pcie_phy_poll_ack(imx6_pcie, false);
> + return pcie_phy_poll_ack(imx_pcie, false);
> }
>
> -static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
> +static int pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data)
> {
> - struct dw_pcie *pci = imx6_pcie->pci;
> + struct dw_pcie *pci = imx_pcie->pci;
> u32 var;
> int ret;
>
> /* write addr */
> /* cap addr */
> - ret = pcie_phy_wait_ack(imx6_pcie, addr);
> + ret = pcie_phy_wait_ack(imx_pcie, addr);
> if (ret)
> return ret;
>
> @@ -326,7 +326,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
> var |= PCIE_PHY_CTRL_CAP_DAT;
> dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
>
> - ret = pcie_phy_poll_ack(imx6_pcie, true);
> + ret = pcie_phy_poll_ack(imx_pcie, true);
> if (ret)
> return ret;
>
> @@ -335,7 +335,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
> dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
>
> /* wait for ack de-assertion */
> - ret = pcie_phy_poll_ack(imx6_pcie, false);
> + ret = pcie_phy_poll_ack(imx_pcie, false);
> if (ret)
> return ret;
>
> @@ -344,7 +344,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
> dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
>
> /* wait for ack */
> - ret = pcie_phy_poll_ack(imx6_pcie, true);
> + ret = pcie_phy_poll_ack(imx_pcie, true);
> if (ret)
> return ret;
>
> @@ -353,7 +353,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
> dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
>
> /* wait for ack de-assertion */
> - ret = pcie_phy_poll_ack(imx6_pcie, false);
> + ret = pcie_phy_poll_ack(imx_pcie, false);
> if (ret)
> return ret;
>
> @@ -362,74 +362,74 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
> return 0;
> }
>
> -static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> +static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie)
> {
> /* TODO: Currently this code assumes external oscillator is being used */
> - regmap_update_bits(imx6_pcie->iomuxc_gpr,
> - imx6_pcie_grp_offset(imx6_pcie),
> + regmap_update_bits(imx_pcie->iomuxc_gpr,
> + imx_pcie_grp_offset(imx_pcie),
> IMX8MQ_GPR_PCIE_REF_USE_PAD,
> IMX8MQ_GPR_PCIE_REF_USE_PAD);
> /*
> * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is
> * supplied by 3.3V, the VREG_BYPASS should be cleared to zero.
> */
> - if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000)
> - regmap_update_bits(imx6_pcie->iomuxc_gpr,
> - imx6_pcie_grp_offset(imx6_pcie),
> + if (imx_pcie->vph && regulator_get_voltage(imx_pcie->vph) > 3000000)
> + regmap_update_bits(imx_pcie->iomuxc_gpr,
> + imx_pcie_grp_offset(imx_pcie),
> IMX8MQ_GPR_PCIE_VREG_BYPASS,
> 0);
>
> return 0;
> }
>
> -static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> +static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie)
> {
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
>
> return 0;
> }
>
> -static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> +static int imx_pcie_init_phy(struct imx_pcie *imx_pcie)
> {
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
>
> /* configure constant input signal to the pcie ctrl and phy */
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
>
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
> IMX6Q_GPR8_TX_DEEMPH_GEN1,
> - imx6_pcie->tx_deemph_gen1 << 0);
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
> + imx_pcie->tx_deemph_gen1 << 0);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
> IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
> - imx6_pcie->tx_deemph_gen2_3p5db << 6);
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
> + imx_pcie->tx_deemph_gen2_3p5db << 6);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
> IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
> - imx6_pcie->tx_deemph_gen2_6db << 12);
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
> + imx_pcie->tx_deemph_gen2_6db << 12);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
> IMX6Q_GPR8_TX_SWING_FULL,
> - imx6_pcie->tx_swing_full << 18);
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
> + imx_pcie->tx_swing_full << 18);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
> IMX6Q_GPR8_TX_SWING_LOW,
> - imx6_pcie->tx_swing_low << 25);
> + imx_pcie->tx_swing_low << 25);
> return 0;
> }
>
> -static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> +static int imx6sx_pcie_init_phy(struct imx_pcie *imx_pcie)
> {
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2);
>
> - return imx6_pcie_init_phy(imx6_pcie);
> + return imx_pcie_init_phy(imx_pcie);
> }
>
> -static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
> +static void imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
> {
> u32 val;
> - struct device *dev = imx6_pcie->pci->dev;
> + struct device *dev = imx_pcie->pci->dev;
>
> - if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
> + if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
> IOMUXC_GPR22, val,
> val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
> PHY_PLL_LOCK_WAIT_USLEEP_MAX,
> @@ -437,19 +437,19 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
> dev_err(dev, "PCIe PLL lock timeout\n");
> }
>
> -static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
> +static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie)
> {
> unsigned long phy_rate = 0;
> int mult, div;
> u16 val;
> int i;
>
> - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
> + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY))
> return 0;
>
> - for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++)
> - if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0)
> - phy_rate = clk_get_rate(imx6_pcie->clks[i].clk);
> + for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++)
> + if (strncmp(imx_pcie->clks[i].id, "pcie_phy", 8) == 0)
> + phy_rate = clk_get_rate(imx_pcie->clks[i].clk);
>
> switch (phy_rate) {
> case 125000000:
> @@ -467,46 +467,46 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
> div = 1;
> break;
> default:
> - dev_err(imx6_pcie->pci->dev,
> + dev_err(imx_pcie->pci->dev,
> "Unsupported PHY reference clock rate %lu\n", phy_rate);
> return -EINVAL;
> }
>
> - pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
> + pcie_phy_read(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
> val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
> PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
> val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
> val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
> - pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
> + pcie_phy_write(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
>
> - pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
> + pcie_phy_read(imx_pcie, PCIE_PHY_ATEOVRD, &val);
> val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
> PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
> val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
> val |= PCIE_PHY_ATEOVRD_EN;
> - pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
> + pcie_phy_write(imx_pcie, PCIE_PHY_ATEOVRD, val);
>
> return 0;
> }
>
> -static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
> +static void imx_pcie_reset_phy(struct imx_pcie *imx_pcie)
> {
> u16 tmp;
>
> - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
> + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY))
> return;
>
> - pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
> + pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp);
> tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
> PHY_RX_OVRD_IN_LO_RX_PLL_EN);
> - pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
> + pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp);
>
> usleep_range(2000, 3000);
>
> - pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
> + pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp);
> tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
> PHY_RX_OVRD_IN_LO_RX_PLL_EN);
> - pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
> + pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp);
> }
>
> #ifdef CONFIG_ARM
> @@ -545,22 +545,22 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
> }
> #endif
>
> -static int imx6_pcie_attach_pd(struct device *dev)
> +static int imx_pcie_attach_pd(struct device *dev)
> {
> - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
> + struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> struct device_link *link;
>
> /* Do nothing when in a single power domain */
> if (dev->pm_domain)
> return 0;
>
> - imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
> - if (IS_ERR(imx6_pcie->pd_pcie))
> - return PTR_ERR(imx6_pcie->pd_pcie);
> + imx_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
> + if (IS_ERR(imx_pcie->pd_pcie))
> + return PTR_ERR(imx_pcie->pd_pcie);
> /* Do nothing when power domain missing */
> - if (!imx6_pcie->pd_pcie)
> + if (!imx_pcie->pd_pcie)
> return 0;
> - link = device_link_add(dev, imx6_pcie->pd_pcie,
> + link = device_link_add(dev, imx_pcie->pd_pcie,
> DL_FLAG_STATELESS |
> DL_FLAG_PM_RUNTIME |
> DL_FLAG_RPM_ACTIVE);
> @@ -569,11 +569,11 @@ static int imx6_pcie_attach_pd(struct device *dev)
> return -EINVAL;
> }
>
> - imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
> - if (IS_ERR(imx6_pcie->pd_pcie_phy))
> - return PTR_ERR(imx6_pcie->pd_pcie_phy);
> + imx_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
> + if (IS_ERR(imx_pcie->pd_pcie_phy))
> + return PTR_ERR(imx_pcie->pd_pcie_phy);
>
> - link = device_link_add(dev, imx6_pcie->pd_pcie_phy,
> + link = device_link_add(dev, imx_pcie->pd_pcie_phy,
> DL_FLAG_STATELESS |
> DL_FLAG_PM_RUNTIME |
> DL_FLAG_RPM_ACTIVE);
> @@ -585,20 +585,20 @@ static int imx6_pcie_attach_pd(struct device *dev)
> return 0;
> }
>
> -static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
> +static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
> {
> unsigned int offset;
> int ret = 0;
>
> - switch (imx6_pcie->drvdata->variant) {
> + switch (imx_pcie->drvdata->variant) {
> case IMX6SX:
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
> break;
> case IMX6QP:
> case IMX6Q:
> /* power up core phy and enable ref clock */
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
> /*
> * the async reset input need ref clock to sync internally,
> @@ -607,7 +607,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
> * add one ~10us delay here.
> */
> usleep_range(10, 100);
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
> break;
> case IMX7D:
> @@ -620,15 +620,15 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
> case IMX8MQ_EP:
> case IMX8MP:
> case IMX8MP_EP:
> - offset = imx6_pcie_grp_offset(imx6_pcie);
> + offset = imx_pcie_grp_offset(imx_pcie);
> /*
> * Set the over ride low and enabled
> * make sure that REF_CLK is turned on.
> */
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
> IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
> 0);
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
> IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
> IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
> break;
> @@ -637,19 +637,19 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
> return ret;
> }
>
> -static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
> +static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie)
> {
> - switch (imx6_pcie->drvdata->variant) {
> + switch (imx_pcie->drvdata->variant) {
> case IMX6QP:
> case IMX6Q:
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_TEST_PD,
> IMX6Q_GPR1_PCIE_TEST_PD);
> break;
> case IMX7D:
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
> IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
> break;
> @@ -658,17 +658,17 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
> }
> }
>
> -static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
> +static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
> {
> - struct dw_pcie *pci = imx6_pcie->pci;
> + struct dw_pcie *pci = imx_pcie->pci;
> struct device *dev = pci->dev;
> int ret;
>
> - ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
> + ret = clk_bulk_prepare_enable(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
> if (ret)
> return ret;
>
> - ret = imx6_pcie_enable_ref_clk(imx6_pcie);
> + ret = imx_pcie_enable_ref_clk(imx_pcie);
> if (ret) {
> dev_err(dev, "unable to enable pcie ref clock\n");
> goto err_ref_clk;
> @@ -679,41 +679,41 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
> return 0;
>
> err_ref_clk:
> - clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
> + clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
>
> return ret;
> }
>
> -static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
> +static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
> {
> - imx6_pcie_disable_ref_clk(imx6_pcie);
> - clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
> + imx_pcie_disable_ref_clk(imx_pcie);
> + clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
> }
>
> -static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
> +static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
> {
> - reset_control_assert(imx6_pcie->pciephy_reset);
> - reset_control_assert(imx6_pcie->apps_reset);
> + reset_control_assert(imx_pcie->pciephy_reset);
> + reset_control_assert(imx_pcie->apps_reset);
>
> - switch (imx6_pcie->drvdata->variant) {
> + switch (imx_pcie->drvdata->variant) {
> case IMX6SX:
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
> IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
> /* Force PCIe PHY reset */
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
> IMX6SX_GPR5_PCIE_BTNRST_RESET,
> IMX6SX_GPR5_PCIE_BTNRST_RESET);
> break;
> case IMX6QP:
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_SW_RST,
> IMX6Q_GPR1_PCIE_SW_RST);
> break;
> case IMX6Q:
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
> break;
> default:
> @@ -721,47 +721,47 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
> }
>
> /* Some boards don't have PCIe reset GPIO. */
> - if (gpio_is_valid(imx6_pcie->reset_gpio))
> - gpio_set_value_cansleep(imx6_pcie->reset_gpio,
> - imx6_pcie->gpio_active_high);
> + if (gpio_is_valid(imx_pcie->reset_gpio))
> + gpio_set_value_cansleep(imx_pcie->reset_gpio,
> + imx_pcie->gpio_active_high);
> }
>
> -static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> +static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
> {
> - struct dw_pcie *pci = imx6_pcie->pci;
> + struct dw_pcie *pci = imx_pcie->pci;
> struct device *dev = pci->dev;
>
> - reset_control_deassert(imx6_pcie->pciephy_reset);
> + reset_control_deassert(imx_pcie->pciephy_reset);
>
> - switch (imx6_pcie->drvdata->variant) {
> + switch (imx_pcie->drvdata->variant) {
> case IMX7D:
> /* Workaround for ERR010728, failure of PCI-e PLL VCO to
> * oscillate, especially when cold. This turns off "Duty-cycle
> * Corrector" and other mysterious undocumented things.
> */
> - if (likely(imx6_pcie->phy_base)) {
> + if (likely(imx_pcie->phy_base)) {
> /* De-assert DCC_FB_EN */
> writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
> - imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
> + imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
> /* Assert RX_EQS and RX_EQS_SEL */
> writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
> | PCIE_PHY_CMN_REG24_RX_EQ,
> - imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
> + imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
> /* Assert ATT_MODE */
> writel(PCIE_PHY_CMN_REG26_ATT_MODE,
> - imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
> + imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
> } else {
> dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
> }
>
> - imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
> + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
> break;
> case IMX6SX:
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
> IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
> break;
> case IMX6QP:
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_SW_RST, 0);
>
> usleep_range(200, 500);
> @@ -771,10 +771,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> }
>
> /* Some boards don't have PCIe reset GPIO. */
> - if (gpio_is_valid(imx6_pcie->reset_gpio)) {
> + if (gpio_is_valid(imx_pcie->reset_gpio)) {
> msleep(100);
> - gpio_set_value_cansleep(imx6_pcie->reset_gpio,
> - !imx6_pcie->gpio_active_high);
> + gpio_set_value_cansleep(imx_pcie->reset_gpio,
> + !imx_pcie->gpio_active_high);
> /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
> msleep(100);
> }
> @@ -782,9 +782,9 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> return 0;
> }
>
> -static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
> +static int imx_pcie_wait_for_speed_change(struct imx_pcie *imx_pcie)
> {
> - struct dw_pcie *pci = imx6_pcie->pci;
> + struct dw_pcie *pci = imx_pcie->pci;
> struct device *dev = pci->dev;
> u32 tmp;
> unsigned int retries;
> @@ -801,33 +801,33 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
> return -ETIMEDOUT;
> }
>
> -static void imx6_pcie_ltssm_enable(struct device *dev)
> +static void imx_pcie_ltssm_enable(struct device *dev)
> {
> - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
> - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
> + struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
>
> if (drvdata->ltssm_mask)
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
> drvdata->ltssm_mask);
>
> - reset_control_deassert(imx6_pcie->apps_reset);
> + reset_control_deassert(imx_pcie->apps_reset);
> }
>
> -static void imx6_pcie_ltssm_disable(struct device *dev)
> +static void imx_pcie_ltssm_disable(struct device *dev)
> {
> - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
> - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata;
> + struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
>
> if (drvdata->ltssm_mask)
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
> drvdata->ltssm_mask, 0);
>
> - reset_control_assert(imx6_pcie->apps_reset);
> + reset_control_assert(imx_pcie->apps_reset);
> }
>
> -static int imx6_pcie_start_link(struct dw_pcie *pci)
> +static int imx_pcie_start_link(struct dw_pcie *pci)
> {
> - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
> + struct imx_pcie *imx_pcie = to_imx_pcie(pci);
> struct device *dev = pci->dev;
> u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> u32 tmp;
> @@ -846,7 +846,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
> dw_pcie_dbi_ro_wr_dis(pci);
>
> /* Start LTSSM. */
> - imx6_pcie_ltssm_enable(dev);
> + imx_pcie_ltssm_enable(dev);
>
> ret = dw_pcie_wait_for_link(pci);
> if (ret)
> @@ -869,8 +869,8 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
> dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
> dw_pcie_dbi_ro_wr_dis(pci);
>
> - if (imx6_pcie->drvdata->flags &
> - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
> + if (imx_pcie->drvdata->flags &
> + IMX_PCIE_FLAG_IMX_SPEED_CHANGE) {
> /*
> * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
> * from i.MX6 family when no link speed transition
> @@ -880,7 +880,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
> * failure.
> */
>
> - ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
> + ret = imx_pcie_wait_for_speed_change(imx_pcie);
> if (ret) {
> dev_err(dev, "Failed to bring link up!\n");
> goto err_reset_phy;
> @@ -895,37 +895,37 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
> dev_info(dev, "Link: Only Gen1 is enabled\n");
> }
>
> - imx6_pcie->link_is_up = true;
> + imx_pcie->link_is_up = true;
> tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
> dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
> return 0;
>
> err_reset_phy:
> - imx6_pcie->link_is_up = false;
> + imx_pcie->link_is_up = false;
> dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
> dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
> dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
> - imx6_pcie_reset_phy(imx6_pcie);
> + imx_pcie_reset_phy(imx_pcie);
> return 0;
> }
>
> -static void imx6_pcie_stop_link(struct dw_pcie *pci)
> +static void imx_pcie_stop_link(struct dw_pcie *pci)
> {
> struct device *dev = pci->dev;
>
> /* Turn off PCIe LTSSM */
> - imx6_pcie_ltssm_disable(dev);
> + imx_pcie_ltssm_disable(dev);
> }
>
> -static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
> +static int imx_pcie_host_init(struct dw_pcie_rp *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> struct device *dev = pci->dev;
> - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
> + struct imx_pcie *imx_pcie = to_imx_pcie(pci);
> int ret;
>
> - if (imx6_pcie->vpcie) {
> - ret = regulator_enable(imx6_pcie->vpcie);
> + if (imx_pcie->vpcie) {
> + ret = regulator_enable(imx_pcie->vpcie);
> if (ret) {
> dev_err(dev, "failed to enable vpcie regulator: %d\n",
> ret);
> @@ -933,83 +933,83 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
> }
> }
>
> - imx6_pcie_assert_core_reset(imx6_pcie);
> + imx_pcie_assert_core_reset(imx_pcie);
>
> - if (imx6_pcie->drvdata->init_phy)
> - imx6_pcie->drvdata->init_phy(imx6_pcie);
> + if (imx_pcie->drvdata->init_phy)
> + imx_pcie->drvdata->init_phy(imx_pcie);
>
> - imx6_pcie_configure_type(imx6_pcie);
> + imx_pcie_configure_type(imx_pcie);
>
> - ret = imx6_pcie_clk_enable(imx6_pcie);
> + ret = imx_pcie_clk_enable(imx_pcie);
> if (ret) {
> dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
> goto err_reg_disable;
> }
>
> - if (imx6_pcie->phy) {
> - ret = phy_init(imx6_pcie->phy);
> + if (imx_pcie->phy) {
> + ret = phy_init(imx_pcie->phy);
> if (ret) {
> dev_err(dev, "pcie PHY power up failed\n");
> goto err_clk_disable;
> }
> }
>
> - if (imx6_pcie->phy) {
> - ret = phy_power_on(imx6_pcie->phy);
> + if (imx_pcie->phy) {
> + ret = phy_power_on(imx_pcie->phy);
> if (ret) {
> dev_err(dev, "waiting for PHY ready timeout!\n");
> goto err_phy_off;
> }
> }
>
> - ret = imx6_pcie_deassert_core_reset(imx6_pcie);
> + ret = imx_pcie_deassert_core_reset(imx_pcie);
> if (ret < 0) {
> dev_err(dev, "pcie deassert core reset failed: %d\n", ret);
> goto err_phy_off;
> }
>
> - imx6_setup_phy_mpll(imx6_pcie);
> + imx_setup_phy_mpll(imx_pcie);
>
> return 0;
>
> err_phy_off:
> - if (imx6_pcie->phy)
> - phy_exit(imx6_pcie->phy);
> + if (imx_pcie->phy)
> + phy_exit(imx_pcie->phy);
> err_clk_disable:
> - imx6_pcie_clk_disable(imx6_pcie);
> + imx_pcie_clk_disable(imx_pcie);
> err_reg_disable:
> - if (imx6_pcie->vpcie)
> - regulator_disable(imx6_pcie->vpcie);
> + if (imx_pcie->vpcie)
> + regulator_disable(imx_pcie->vpcie);
> return ret;
> }
>
> -static void imx6_pcie_host_exit(struct dw_pcie_rp *pp)
> +static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
> + struct imx_pcie *imx_pcie = to_imx_pcie(pci);
>
> - if (imx6_pcie->phy) {
> - if (phy_power_off(imx6_pcie->phy))
> + if (imx_pcie->phy) {
> + if (phy_power_off(imx_pcie->phy))
> dev_err(pci->dev, "unable to power off PHY\n");
> - phy_exit(imx6_pcie->phy);
> + phy_exit(imx_pcie->phy);
> }
> - imx6_pcie_clk_disable(imx6_pcie);
> + imx_pcie_clk_disable(imx_pcie);
>
> - if (imx6_pcie->vpcie)
> - regulator_disable(imx6_pcie->vpcie);
> + if (imx_pcie->vpcie)
> + regulator_disable(imx_pcie->vpcie);
> }
>
> -static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
> - .init = imx6_pcie_host_init,
> - .deinit = imx6_pcie_host_exit,
> +static const struct dw_pcie_host_ops imx_pcie_host_ops = {
> + .init = imx_pcie_host_init,
> + .deinit = imx_pcie_host_exit,
> };
>
> static const struct dw_pcie_ops dw_pcie_ops = {
> - .start_link = imx6_pcie_start_link,
> - .stop_link = imx6_pcie_stop_link,
> + .start_link = imx_pcie_start_link,
> + .stop_link = imx_pcie_stop_link,
> };
>
> -static void imx6_pcie_ep_init(struct dw_pcie_ep *ep)
> +static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
> {
> enum pci_barno bar;
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> @@ -1018,7 +1018,7 @@ static void imx6_pcie_ep_init(struct dw_pcie_ep *ep)
> dw_pcie_ep_reset_bar(pci, bar);
> }
>
> -static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> +static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> unsigned int type, u16 interrupt_num)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> @@ -1065,35 +1065,35 @@ static const struct pci_epc_features imx95_pcie_epc_features = {
> };
>
> static const struct pci_epc_features*
> -imx6_pcie_ep_get_features(struct dw_pcie_ep *ep)
> +imx_pcie_ep_get_features(struct dw_pcie_ep *ep)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
> + struct imx_pcie *imx_pcie = to_imx_pcie(pci);
>
> - return imx6_pcie->drvdata->epc_features;
> + return imx_pcie->drvdata->epc_features;
> }
>
> static const struct dw_pcie_ep_ops pcie_ep_ops = {
> - .init = imx6_pcie_ep_init,
> - .raise_irq = imx6_pcie_ep_raise_irq,
> - .get_features = imx6_pcie_ep_get_features,
> + .init = imx_pcie_ep_init,
> + .raise_irq = imx_pcie_ep_raise_irq,
> + .get_features = imx_pcie_ep_get_features,
> };
>
> -static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
> +static int imx_add_pcie_ep(struct imx_pcie *imx_pcie,
> struct platform_device *pdev)
> {
> int ret;
> unsigned int pcie_dbi2_offset;
> struct dw_pcie_ep *ep;
> - struct dw_pcie *pci = imx6_pcie->pci;
> + struct dw_pcie *pci = imx_pcie->pci;
> struct dw_pcie_rp *pp = &pci->pp;
> struct device *dev = pci->dev;
>
> - imx6_pcie_host_init(pp);
> + imx_pcie_host_init(pp);
> ep = &pci->ep;
> ep->ops = &pcie_ep_ops;
>
> - switch (imx6_pcie->drvdata->variant) {
> + switch (imx_pcie->drvdata->variant) {
> case IMX8MQ_EP:
> case IMX8MM_EP:
> case IMX8MP_EP:
> @@ -1115,10 +1115,10 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
> if (device_property_match_string(dev, "reg-names", "dbi2") >= 0)
> pci->dbi_base2 = NULL;
>
> - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT))
> + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_SUPPORT_64BIT))
> dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
>
> - ep->page_size = imx6_pcie->drvdata->epc_features->align;
> + ep->page_size = imx_pcie->drvdata->epc_features->align;
>
> ret = dw_pcie_ep_init(ep);
> if (ret) {
> @@ -1126,30 +1126,30 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
> return ret;
> }
> /* Start LTSSM. */
> - imx6_pcie_ltssm_enable(dev);
> + imx_pcie_ltssm_enable(dev);
>
> return 0;
> }
>
> -static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
> +static void imx_pcie_pm_turnoff(struct imx_pcie *imx_pcie)
> {
> - struct device *dev = imx6_pcie->pci->dev;
> + struct device *dev = imx_pcie->pci->dev;
>
> /* Some variants have a turnoff reset in DT */
> - if (imx6_pcie->turnoff_reset) {
> - reset_control_assert(imx6_pcie->turnoff_reset);
> - reset_control_deassert(imx6_pcie->turnoff_reset);
> + if (imx_pcie->turnoff_reset) {
> + reset_control_assert(imx_pcie->turnoff_reset);
> + reset_control_deassert(imx_pcie->turnoff_reset);
> goto pm_turnoff_sleep;
> }
>
> /* Others poke directly at IOMUXC registers */
> - switch (imx6_pcie->drvdata->variant) {
> + switch (imx_pcie->drvdata->variant) {
> case IMX6SX:
> case IMX6QP:
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX6SX_GPR12_PCIE_PM_TURN_OFF,
> IMX6SX_GPR12_PCIE_PM_TURN_OFF);
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
> break;
> default:
> @@ -1168,73 +1168,73 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
> usleep_range(1000, 10000);
> }
>
> -static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save)
> +static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save)
> {
> u8 offset;
> u16 val;
> - struct dw_pcie *pci = imx6_pcie->pci;
> + struct dw_pcie *pci = imx_pcie->pci;
>
> if (pci_msi_enabled()) {
> offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
> if (save) {
> val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
> - imx6_pcie->msi_ctrl = val;
> + imx_pcie->msi_ctrl = val;
> } else {
> dw_pcie_dbi_ro_wr_en(pci);
> - val = imx6_pcie->msi_ctrl;
> + val = imx_pcie->msi_ctrl;
> dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
> dw_pcie_dbi_ro_wr_dis(pci);
> }
> }
> }
>
> -static int imx6_pcie_suspend_noirq(struct device *dev)
> +static int imx_pcie_suspend_noirq(struct device *dev)
> {
> - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
> - struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
> + struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> + struct dw_pcie_rp *pp = &imx_pcie->pci->pp;
>
> - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
> + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND))
> return 0;
>
> - imx6_pcie_msi_save_restore(imx6_pcie, true);
> - imx6_pcie_pm_turnoff(imx6_pcie);
> - imx6_pcie_stop_link(imx6_pcie->pci);
> - imx6_pcie_host_exit(pp);
> + imx_pcie_msi_save_restore(imx_pcie, true);
> + imx_pcie_pm_turnoff(imx_pcie);
> + imx_pcie_stop_link(imx_pcie->pci);
> + imx_pcie_host_exit(pp);
>
> return 0;
> }
>
> -static int imx6_pcie_resume_noirq(struct device *dev)
> +static int imx_pcie_resume_noirq(struct device *dev)
> {
> int ret;
> - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
> - struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
> + struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
> + struct dw_pcie_rp *pp = &imx_pcie->pci->pp;
>
> - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
> + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND))
> return 0;
>
> - ret = imx6_pcie_host_init(pp);
> + ret = imx_pcie_host_init(pp);
> if (ret)
> return ret;
> - imx6_pcie_msi_save_restore(imx6_pcie, false);
> + imx_pcie_msi_save_restore(imx_pcie, false);
> dw_pcie_setup_rc(pp);
>
> - if (imx6_pcie->link_is_up)
> - imx6_pcie_start_link(imx6_pcie->pci);
> + if (imx_pcie->link_is_up)
> + imx_pcie_start_link(imx_pcie->pci);
>
> return 0;
> }
>
> -static const struct dev_pm_ops imx6_pcie_pm_ops = {
> - NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
> - imx6_pcie_resume_noirq)
> +static const struct dev_pm_ops imx_pcie_pm_ops = {
> + NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_pcie_suspend_noirq,
> + imx_pcie_resume_noirq)
> };
>
> -static int imx6_pcie_probe(struct platform_device *pdev)
> +static int imx_pcie_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct dw_pcie *pci;
> - struct imx6_pcie *imx6_pcie;
> + struct imx_pcie *imx_pcie;
> struct device_node *np;
> struct resource *dbi_base;
> struct device_node *node = dev->of_node;
> @@ -1242,8 +1242,8 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> u16 val;
> int i;
>
> - imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
> - if (!imx6_pcie)
> + imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
> + if (!imx_pcie)
> return -ENOMEM;
>
> pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> @@ -1252,10 +1252,10 @@ static int imx6_pcie_probe(struct platform_device *pdev)
>
> pci->dev = dev;
> pci->ops = &dw_pcie_ops;
> - pci->pp.ops = &imx6_pcie_host_ops;
> + pci->pp.ops = &imx_pcie_host_ops;
>
> - imx6_pcie->pci = pci;
> - imx6_pcie->drvdata = of_device_get_match_data(dev);
> + imx_pcie->pci = pci;
> + imx_pcie->drvdata = of_device_get_match_data(dev);
>
> /* Find the PHY if one is defined, only imx7d uses it */
> np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
> @@ -1267,9 +1267,9 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> dev_err(dev, "Unable to map PCIe PHY\n");
> return ret;
> }
> - imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
> - if (IS_ERR(imx6_pcie->phy_base))
> - return PTR_ERR(imx6_pcie->phy_base);
> + imx_pcie->phy_base = devm_ioremap_resource(dev, &res);
> + if (IS_ERR(imx_pcie->phy_base))
> + return PTR_ERR(imx_pcie->phy_base);
> }
>
> pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base);
> @@ -1277,12 +1277,12 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> return PTR_ERR(pci->dbi_base);
>
> /* Fetch GPIOs */
> - imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
> - imx6_pcie->gpio_active_high = of_property_read_bool(node,
> + imx_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
> + imx_pcie->gpio_active_high = of_property_read_bool(node,
> "reset-gpio-active-high");
> - if (gpio_is_valid(imx6_pcie->reset_gpio)) {
> - ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
> - imx6_pcie->gpio_active_high ?
> + if (gpio_is_valid(imx_pcie->reset_gpio)) {
> + ret = devm_gpio_request_one(dev, imx_pcie->reset_gpio,
> + imx_pcie->gpio_active_high ?
> GPIOF_OUT_INIT_HIGH :
> GPIOF_OUT_INIT_LOW,
> "PCIe reset");
> @@ -1290,70 +1290,70 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> dev_err(dev, "unable to get reset gpio\n");
> return ret;
> }
> - } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
> - return imx6_pcie->reset_gpio;
> + } else if (imx_pcie->reset_gpio == -EPROBE_DEFER) {
> + return imx_pcie->reset_gpio;
> }
>
> - if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS)
> + if (imx_pcie->drvdata->clks_cnt >= IMX_PCIE_MAX_CLKS)
> return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
>
> - for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++)
> - imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i];
> + for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++)
> + imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i];
>
> /* Fetch clocks */
> - ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
> + ret = devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
> if (ret)
> return ret;
>
> - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHYDRV)) {
> - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy");
> - if (IS_ERR(imx6_pcie->phy))
> - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy),
> + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
> + imx_pcie->phy = devm_phy_get(dev, "pcie-phy");
> + if (IS_ERR(imx_pcie->phy))
> + return dev_err_probe(dev, PTR_ERR(imx_pcie->phy),
> "failed to get pcie phy\n");
> }
>
> - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) {
> - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps");
> - if (IS_ERR(imx6_pcie->apps_reset))
> - return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset),
> + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_APP_RESET)) {
> + imx_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps");
> + if (IS_ERR(imx_pcie->apps_reset))
> + return dev_err_probe(dev, PTR_ERR(imx_pcie->apps_reset),
> "failed to get pcie apps reset control\n");
> }
>
> - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) {
> - imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy");
> - if (IS_ERR(imx6_pcie->pciephy_reset))
> - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset),
> + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHY_RESET)) {
> + imx_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy");
> + if (IS_ERR(imx_pcie->pciephy_reset))
> + return dev_err_probe(dev, PTR_ERR(imx_pcie->pciephy_reset),
> "Failed to get PCIEPHY reset control\n");
> }
>
> - switch (imx6_pcie->drvdata->variant) {
> + switch (imx_pcie->drvdata->variant) {
> case IMX8MQ:
> case IMX8MQ_EP:
> case IMX7D:
> if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
> - imx6_pcie->controller_id = 1;
> + imx_pcie->controller_id = 1;
> break;
> default:
> break;
> }
>
> /* Grab turnoff reset */
> - imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
> - if (IS_ERR(imx6_pcie->turnoff_reset)) {
> + imx_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
> + if (IS_ERR(imx_pcie->turnoff_reset)) {
> dev_err(dev, "Failed to get TURNOFF reset control\n");
> - return PTR_ERR(imx6_pcie->turnoff_reset);
> + return PTR_ERR(imx_pcie->turnoff_reset);
> }
>
> - if (imx6_pcie->drvdata->gpr) {
> + if (imx_pcie->drvdata->gpr) {
> /* Grab GPR config register range */
> - imx6_pcie->iomuxc_gpr =
> - syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
> - if (IS_ERR(imx6_pcie->iomuxc_gpr))
> - return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
> + imx_pcie->iomuxc_gpr =
> + syscon_regmap_lookup_by_compatible(imx_pcie->drvdata->gpr);
> + if (IS_ERR(imx_pcie->iomuxc_gpr))
> + return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr),
> "unable to find iomuxc registers\n");
> }
>
> - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) {
> + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_SERDES)) {
> void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app");
>
> if (IS_ERR(off))
> @@ -1366,59 +1366,59 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> .reg_stride = 4,
> };
>
> - imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config);
> - if (IS_ERR(imx6_pcie->iomuxc_gpr))
> - return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr),
> + imx_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config);
> + if (IS_ERR(imx_pcie->iomuxc_gpr))
> + return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr),
> "unable to find iomuxc registers\n");
> }
>
> /* Grab PCIe PHY Tx Settings */
> if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
> - &imx6_pcie->tx_deemph_gen1))
> - imx6_pcie->tx_deemph_gen1 = 0;
> + &imx_pcie->tx_deemph_gen1))
> + imx_pcie->tx_deemph_gen1 = 0;
>
> if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
> - &imx6_pcie->tx_deemph_gen2_3p5db))
> - imx6_pcie->tx_deemph_gen2_3p5db = 0;
> + &imx_pcie->tx_deemph_gen2_3p5db))
> + imx_pcie->tx_deemph_gen2_3p5db = 0;
>
> if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
> - &imx6_pcie->tx_deemph_gen2_6db))
> - imx6_pcie->tx_deemph_gen2_6db = 20;
> + &imx_pcie->tx_deemph_gen2_6db))
> + imx_pcie->tx_deemph_gen2_6db = 20;
>
> if (of_property_read_u32(node, "fsl,tx-swing-full",
> - &imx6_pcie->tx_swing_full))
> - imx6_pcie->tx_swing_full = 127;
> + &imx_pcie->tx_swing_full))
> + imx_pcie->tx_swing_full = 127;
>
> if (of_property_read_u32(node, "fsl,tx-swing-low",
> - &imx6_pcie->tx_swing_low))
> - imx6_pcie->tx_swing_low = 127;
> + &imx_pcie->tx_swing_low))
> + imx_pcie->tx_swing_low = 127;
>
> /* Limit link speed */
> pci->link_gen = 1;
> of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
>
> - imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
> - if (IS_ERR(imx6_pcie->vpcie)) {
> - if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
> - return PTR_ERR(imx6_pcie->vpcie);
> - imx6_pcie->vpcie = NULL;
> + imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
> + if (IS_ERR(imx_pcie->vpcie)) {
> + if (PTR_ERR(imx_pcie->vpcie) != -ENODEV)
> + return PTR_ERR(imx_pcie->vpcie);
> + imx_pcie->vpcie = NULL;
> }
>
> - imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
> - if (IS_ERR(imx6_pcie->vph)) {
> - if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
> - return PTR_ERR(imx6_pcie->vph);
> - imx6_pcie->vph = NULL;
> + imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
> + if (IS_ERR(imx_pcie->vph)) {
> + if (PTR_ERR(imx_pcie->vph) != -ENODEV)
> + return PTR_ERR(imx_pcie->vph);
> + imx_pcie->vph = NULL;
> }
>
> - platform_set_drvdata(pdev, imx6_pcie);
> + platform_set_drvdata(pdev, imx_pcie);
>
> - ret = imx6_pcie_attach_pd(dev);
> + ret = imx_pcie_attach_pd(dev);
> if (ret)
> return ret;
>
> - if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
> - ret = imx6_add_pcie_ep(imx6_pcie, pdev);
> + if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
> + ret = imx_add_pcie_ep(imx_pcie, pdev);
> if (ret < 0)
> return ret;
> } else {
> @@ -1438,12 +1438,12 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> return 0;
> }
>
> -static void imx6_pcie_shutdown(struct platform_device *pdev)
> +static void imx_pcie_shutdown(struct platform_device *pdev)
> {
> - struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
> + struct imx_pcie *imx_pcie = platform_get_drvdata(pdev);
>
> /* bring down link, so bootloader gets clean state in case of reboot */
> - imx6_pcie_assert_core_reset(imx6_pcie);
> + imx_pcie_assert_core_reset(imx_pcie);
> }
>
> static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"};
> @@ -1451,11 +1451,11 @@ static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"};
> static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
> static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
>
> -static const struct imx6_pcie_drvdata drvdata[] = {
> +static const struct imx_pcie_drvdata drvdata[] = {
> [IMX6Q] = {
> .variant = IMX6Q,
> - .flags = IMX6_PCIE_FLAG_IMX6_PHY |
> - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
> + .flags = IMX_PCIE_FLAG_IMX_PHY |
> + IMX_PCIE_FLAG_IMX_SPEED_CHANGE,
> .dbi_length = 0x200,
> .gpr = "fsl,imx6q-iomuxc-gpr",
> .clk_names = imx6q_clks,
> @@ -1464,13 +1464,13 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> - .init_phy = imx6_pcie_init_phy,
> + .init_phy = imx_pcie_init_phy,
> },
> [IMX6SX] = {
> .variant = IMX6SX,
> - .flags = IMX6_PCIE_FLAG_IMX6_PHY |
> - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
> - IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
> + .flags = IMX_PCIE_FLAG_IMX_PHY |
> + IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
> + IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
> .gpr = "fsl,imx6q-iomuxc-gpr",
> .clk_names = imx6sx_clks,
> .clks_cnt = ARRAY_SIZE(imx6sx_clks),
> @@ -1482,9 +1482,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> },
> [IMX6QP] = {
> .variant = IMX6QP,
> - .flags = IMX6_PCIE_FLAG_IMX6_PHY |
> - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
> - IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
> + .flags = IMX_PCIE_FLAG_IMX_PHY |
> + IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
> + IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
> .dbi_length = 0x200,
> .gpr = "fsl,imx6q-iomuxc-gpr",
> .clk_names = imx6q_clks,
> @@ -1493,13 +1493,13 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2,
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> - .init_phy = imx6_pcie_init_phy,
> + .init_phy = imx_pcie_init_phy,
> },
> [IMX7D] = {
> .variant = IMX7D,
> - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
> - IMX6_PCIE_FLAG_HAS_APP_RESET |
> - IMX6_PCIE_FLAG_HAS_PHY_RESET,
> + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
> + IMX_PCIE_FLAG_HAS_APP_RESET |
> + IMX_PCIE_FLAG_HAS_PHY_RESET,
> .gpr = "fsl,imx7d-iomuxc-gpr",
> .clk_names = imx6q_clks,
> .clks_cnt = ARRAY_SIZE(imx6q_clks),
> @@ -1509,8 +1509,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> },
> [IMX8MQ] = {
> .variant = IMX8MQ,
> - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
> - IMX6_PCIE_FLAG_HAS_PHY_RESET,
> + .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
> + IMX_PCIE_FLAG_HAS_PHY_RESET,
> .gpr = "fsl,imx8mq-iomuxc-gpr",
> .clk_names = imx8mq_clks,
> .clks_cnt = ARRAY_SIZE(imx8mq_clks),
> @@ -1522,9 +1522,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> },
> [IMX8MM] = {
> .variant = IMX8MM,
> - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
> - IMX6_PCIE_FLAG_HAS_PHYDRV |
> - IMX6_PCIE_FLAG_HAS_APP_RESET,
> + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
> + IMX_PCIE_FLAG_HAS_PHYDRV |
> + IMX_PCIE_FLAG_HAS_APP_RESET,
> .gpr = "fsl,imx8mm-iomuxc-gpr",
> .clk_names = imx8mm_clks,
> .clks_cnt = ARRAY_SIZE(imx8mm_clks),
> @@ -1533,9 +1533,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> },
> [IMX8MP] = {
> .variant = IMX8MP,
> - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
> - IMX6_PCIE_FLAG_HAS_PHYDRV |
> - IMX6_PCIE_FLAG_HAS_APP_RESET,
> + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
> + IMX_PCIE_FLAG_HAS_PHYDRV |
> + IMX_PCIE_FLAG_HAS_APP_RESET,
> .gpr = "fsl,imx8mp-iomuxc-gpr",
> .clk_names = imx8mm_clks,
> .clks_cnt = ARRAY_SIZE(imx8mm_clks),
> @@ -1544,7 +1544,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> },
> [IMX95] = {
> .variant = IMX95,
> - .flags = IMX6_PCIE_FLAG_HAS_SERDES,
> + .flags = IMX_PCIE_FLAG_HAS_SERDES,
> .clk_names = imx8mq_clks,
> .clks_cnt = ARRAY_SIZE(imx8mq_clks),
> .ltssm_off = IMX95_PE0_GEN_CTRL_3,
> @@ -1555,8 +1555,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> },
> [IMX8MQ_EP] = {
> .variant = IMX8MQ_EP,
> - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
> - IMX6_PCIE_FLAG_HAS_PHY_RESET,
> + .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
> + IMX_PCIE_FLAG_HAS_PHY_RESET,
> .mode = DW_PCIE_EP_TYPE,
> .gpr = "fsl,imx8mq-iomuxc-gpr",
> .clk_names = imx8mq_clks,
> @@ -1570,8 +1570,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> },
> [IMX8MM_EP] = {
> .variant = IMX8MM_EP,
> - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
> - IMX6_PCIE_FLAG_HAS_PHYDRV,
> + .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
> + IMX_PCIE_FLAG_HAS_PHYDRV,
> .mode = DW_PCIE_EP_TYPE,
> .gpr = "fsl,imx8mm-iomuxc-gpr",
> .clk_names = imx8mm_clks,
> @@ -1582,8 +1582,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> },
> [IMX8MP_EP] = {
> .variant = IMX8MP_EP,
> - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET |
> - IMX6_PCIE_FLAG_HAS_PHYDRV,
> + .flags = IMX_PCIE_FLAG_HAS_APP_RESET |
> + IMX_PCIE_FLAG_HAS_PHYDRV,
> .mode = DW_PCIE_EP_TYPE,
> .gpr = "fsl,imx8mp-iomuxc-gpr",
> .clk_names = imx8mm_clks,
> @@ -1594,8 +1594,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> },
> [IMX95_EP] = {
> .variant = IMX95_EP,
> - .flags = IMX6_PCIE_FLAG_HAS_SERDES |
> - IMX6_PCIE_FLAG_SUPPORT_64BIT,
> + .flags = IMX_PCIE_FLAG_HAS_SERDES |
> + IMX_PCIE_FLAG_SUPPORT_64BIT,
> .clk_names = imx8mq_clks,
> .clks_cnt = ARRAY_SIZE(imx8mq_clks),
> .ltssm_off = IMX95_PE0_GEN_CTRL_3,
> @@ -1608,7 +1608,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> },
> };
>
> -static const struct of_device_id imx6_pcie_of_match[] = {
> +static const struct of_device_id imx_pcie_of_match[] = {
> { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
> { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
> { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
> @@ -1624,19 +1624,19 @@ static const struct of_device_id imx6_pcie_of_match[] = {
> {},
> };
>
> -static struct platform_driver imx6_pcie_driver = {
> +static struct platform_driver imx_pcie_driver = {
> .driver = {
> .name = "imx6q-pcie",
> - .of_match_table = imx6_pcie_of_match,
> + .of_match_table = imx_pcie_of_match,
> .suppress_bind_attrs = true,
> - .pm = &imx6_pcie_pm_ops,
> + .pm = &imx_pcie_pm_ops,
> .probe_type = PROBE_PREFER_ASYNCHRONOUS,
> },
> - .probe = imx6_pcie_probe,
> - .shutdown = imx6_pcie_shutdown,
> + .probe = imx_pcie_probe,
> + .shutdown = imx_pcie_shutdown,
> };
>
> -static void imx6_pcie_quirk(struct pci_dev *dev)
> +static void imx_pcie_quirk(struct pci_dev *dev)
> {
> struct pci_bus *bus = dev->bus;
> struct dw_pcie_rp *pp = bus->sysdata;
> @@ -1646,33 +1646,33 @@ static void imx6_pcie_quirk(struct pci_dev *dev)
> return;
>
> /* Make sure we only quirk devices associated with this driver */
> - if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver)
> + if (bus->dev.parent->parent->driver != &imx_pcie_driver.driver)
> return;
>
> if (pci_is_root_bus(bus)) {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
> + struct imx_pcie *imx_pcie = to_imx_pcie(pci);
>
> /*
> * Limit config length to avoid the kernel reading beyond
> * the register set and causing an abort on i.MX 6Quad
> */
> - if (imx6_pcie->drvdata->dbi_length) {
> - dev->cfg_size = imx6_pcie->drvdata->dbi_length;
> + if (imx_pcie->drvdata->dbi_length) {
> + dev->cfg_size = imx_pcie->drvdata->dbi_length;
> dev_info(&dev->dev, "Limiting cfg_size to %d\n",
> dev->cfg_size);
> }
> }
> }
> DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd,
> - PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk);
> + PCI_CLASS_BRIDGE_PCI, 8, imx_pcie_quirk);
>
> -static int __init imx6_pcie_init(void)
> +static int __init imx_pcie_init(void)
> {
> #ifdef CONFIG_ARM
> struct device_node *np;
>
> - np = of_find_matching_node(NULL, imx6_pcie_of_match);
> + np = of_find_matching_node(NULL, imx_pcie_of_match);
> if (!np)
> return -ENODEV;
> of_node_put(np);
> @@ -1688,6 +1688,6 @@ static int __init imx6_pcie_init(void)
> "external abort on non-linefetch");
> #endif
>
> - return platform_driver_register(&imx6_pcie_driver);
> + return platform_driver_register(&imx_pcie_driver);
> }
> -device_initcall(imx6_pcie_init);
> +device_initcall(imx_pcie_init);
>
> --
> 2.34.1
>
--
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v2 4/4] PCI: kirin: Convert to agnostic GPIO API
2024-04-23 17:19 16% ` [PATCH v2 4/4] PCI: kirin: " Andy Shevchenko
@ 2024-04-27 7:23 0% ` Manivannan Sadhasivam
0 siblings, 0 replies; 200+ results
From: Manivannan Sadhasivam @ 2024-04-27 7:23 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Frank Li, Krzysztof Wilczyński, Uwe Kleine-König,
linux-omap, linux-pci, linux-arm-kernel, linux-kernel, imx,
linux-amlogic, linux-arm-msm, linux-tegra, Vignesh Raghavendra,
Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár
On Tue, Apr 23, 2024 at 08:19:07PM +0300, Andy Shevchenko wrote:
> The of_gpio.h is going to be removed. In preparation of that convert
> the driver to the agnostic API.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> drivers/pci/controller/dwc/pcie-kirin.c | 105 ++++++++----------------
> 1 file changed, 35 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
> index d5523f302102..1753ab63a541 100644
> --- a/drivers/pci/controller/dwc/pcie-kirin.c
> +++ b/drivers/pci/controller/dwc/pcie-kirin.c
> @@ -12,12 +12,10 @@
> #include <linux/compiler.h>
> #include <linux/delay.h>
> #include <linux/err.h>
> -#include <linux/gpio.h>
> #include <linux/gpio/consumer.h>
> #include <linux/interrupt.h>
> #include <linux/mfd/syscon.h>
> #include <linux/of.h>
> -#include <linux/of_gpio.h>
> #include <linux/of_pci.h>
> #include <linux/phy/phy.h>
> #include <linux/pci.h>
> @@ -78,16 +76,16 @@ struct kirin_pcie {
> void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */
>
> /* DWC PERST# */
> - int gpio_id_dwc_perst;
> + struct gpio_desc *id_dwc_perst_gpio;
>
> /* Per-slot PERST# */
> int num_slots;
> - int gpio_id_reset[MAX_PCI_SLOTS];
> + struct gpio_desc *id_reset_gpio[MAX_PCI_SLOTS];
> const char *reset_names[MAX_PCI_SLOTS];
>
> /* Per-slot clkreq */
> int n_gpio_clkreq;
> - int gpio_id_clkreq[MAX_PCI_SLOTS];
> + struct gpio_desc *id_clkreq_gpio[MAX_PCI_SLOTS];
> const char *clkreq_names[MAX_PCI_SLOTS];
> };
>
> @@ -381,15 +379,20 @@ static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie,
> pcie->n_gpio_clkreq = ret;
>
> for (i = 0; i < pcie->n_gpio_clkreq; i++) {
> - pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node,
> - "hisilicon,clken-gpios", i);
> - if (pcie->gpio_id_clkreq[i] < 0)
> - return pcie->gpio_id_clkreq[i];
> + pcie->id_clkreq_gpio[i] = devm_gpiod_get_index(dev,
> + "hisilicon,clken", i,
> + GPIOD_ASIS);
Please don't use GPIOD_ASIS even if the old code was using it.
For all 3 GPIOs in this driver, GPIOD_OUT_LOW flag should be used as the default
state is assert (considering the fact that the DT uses GPIO_ACTIVE_HIGH).
- Mani
> + if (IS_ERR(pcie->id_clkreq_gpio[i]))
> + return dev_err_probe(dev, PTR_ERR(pcie->id_clkreq_gpio[i]),
> + "unable to get a valid clken gpio\n");
>
> pcie->clkreq_names[i] = devm_kasprintf(dev, GFP_KERNEL,
> "pcie_clkreq_%d", i);
> if (!pcie->clkreq_names[i])
> return -ENOMEM;
> +
> + gpiod_set_consumer_name(pcie->id_clkreq_gpio[i],
> + pcie->clkreq_names[i]);
> }
>
> return 0;
> @@ -407,10 +410,16 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
> for_each_available_child_of_node(parent, child) {
> i = pcie->num_slots;
>
> - pcie->gpio_id_reset[i] = of_get_named_gpio(child,
> - "reset-gpios", 0);
> - if (pcie->gpio_id_reset[i] < 0)
> - continue;
> + pcie->id_reset_gpio[i] = devm_fwnode_gpiod_get_index(dev,
> + of_fwnode_handle(child),
> + "reset", 0, GPIOD_ASIS,
> + NULL);
> + if (IS_ERR(pcie->id_reset_gpio[i])) {
> + if (PTR_ERR(pcie->id_reset_gpio[i]) == -ENOENT)
> + continue;
> + return dev_err_probe(dev, PTR_ERR(pcie->id_reset_gpio[i]),
> + "unable to get a valid reset gpio\n");
> + }
>
> pcie->num_slots++;
> if (pcie->num_slots > MAX_PCI_SLOTS) {
> @@ -434,6 +443,9 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
> ret = -ENOMEM;
> goto put_node;
> }
> +
> + gpiod_set_consumer_name(pcie->id_reset_gpio[i],
> + pcie->reset_names[i]);
> }
> }
>
> @@ -463,14 +475,11 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
> return PTR_ERR(kirin_pcie->apb);
>
> /* pcie internal PERST# gpio */
> - kirin_pcie->gpio_id_dwc_perst = of_get_named_gpio(dev->of_node,
> - "reset-gpios", 0);
> - if (kirin_pcie->gpio_id_dwc_perst == -EPROBE_DEFER) {
> - return -EPROBE_DEFER;
> - } else if (!gpio_is_valid(kirin_pcie->gpio_id_dwc_perst)) {
> - dev_err(dev, "unable to get a valid gpio pin\n");
> - return -ENODEV;
> - }
> + kirin_pcie->id_dwc_perst_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
> + if (IS_ERR(kirin_pcie->id_dwc_perst_gpio))
> + return dev_err_probe(dev, PTR_ERR(kirin_pcie->id_dwc_perst_gpio),
> + "unable to get a valid gpio pin\n");
> + gpiod_set_consumer_name(kirin_pcie->id_dwc_perst_gpio, "pcie_perst_bridge");
>
> ret = kirin_pcie_get_gpio_enable(kirin_pcie, pdev);
> if (ret)
> @@ -553,7 +562,7 @@ static int kirin_pcie_add_bus(struct pci_bus *bus)
>
> /* Send PERST# to each slot */
> for (i = 0; i < kirin_pcie->num_slots; i++) {
> - ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1);
> + ret = gpiod_direction_output_raw(kirin_pcie->id_reset_gpio[i], 1);
> if (ret) {
> dev_err(pci->dev, "PERST# %s error: %d\n",
> kirin_pcie->reset_names[i], ret);
> @@ -623,44 +632,6 @@ static int kirin_pcie_host_init(struct dw_pcie_rp *pp)
> return 0;
> }
>
> -static int kirin_pcie_gpio_request(struct kirin_pcie *kirin_pcie,
> - struct device *dev)
> -{
> - int ret, i;
> -
> - for (i = 0; i < kirin_pcie->num_slots; i++) {
> - if (!gpio_is_valid(kirin_pcie->gpio_id_reset[i])) {
> - dev_err(dev, "unable to get a valid %s gpio\n",
> - kirin_pcie->reset_names[i]);
> - return -ENODEV;
> - }
> -
> - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i],
> - kirin_pcie->reset_names[i]);
> - if (ret)
> - return ret;
> - }
> -
> - for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) {
> - if (!gpio_is_valid(kirin_pcie->gpio_id_clkreq[i])) {
> - dev_err(dev, "unable to get a valid %s gpio\n",
> - kirin_pcie->clkreq_names[i]);
> - return -ENODEV;
> - }
> -
> - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i],
> - kirin_pcie->clkreq_names[i]);
> - if (ret)
> - return ret;
> -
> - ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0);
> - if (ret)
> - return ret;
> - }
> -
> - return 0;
> -}
> -
> static const struct dw_pcie_ops kirin_dw_pcie_ops = {
> .read_dbi = kirin_pcie_read_dbi,
> .write_dbi = kirin_pcie_write_dbi,
> @@ -680,7 +651,7 @@ static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie)
> return hi3660_pcie_phy_power_off(kirin_pcie);
>
> for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++)
> - gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 1);
> + gpiod_direction_output_raw(kirin_pcie->id_clkreq_gpio[i], 1);
>
> phy_power_off(kirin_pcie->phy);
> phy_exit(kirin_pcie->phy);
> @@ -707,10 +678,6 @@ static int kirin_pcie_power_on(struct platform_device *pdev,
> if (IS_ERR(kirin_pcie->phy))
> return PTR_ERR(kirin_pcie->phy);
>
> - ret = kirin_pcie_gpio_request(kirin_pcie, dev);
> - if (ret)
> - return ret;
> -
> ret = phy_init(kirin_pcie->phy);
> if (ret)
> goto err;
> @@ -723,11 +690,9 @@ static int kirin_pcie_power_on(struct platform_device *pdev,
> /* perst assert Endpoint */
> usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
>
> - if (!gpio_request(kirin_pcie->gpio_id_dwc_perst, "pcie_perst_bridge")) {
> - ret = gpio_direction_output(kirin_pcie->gpio_id_dwc_perst, 1);
> - if (ret)
> - goto err;
> - }
> + ret = gpiod_direction_output_raw(kirin_pcie->id_dwc_perst_gpio, 1);
> + if (ret)
> + goto err;
>
> usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
>
> --
> 2.43.0.rc1.1336.g36b5255a03ac
>
--
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v2 3/4] PCI: imx6: Convert to agnostic GPIO API
2024-04-23 17:19 11% ` [PATCH v2 3/4] PCI: imx6: Convert " Andy Shevchenko
2024-04-23 19:56 5% ` Frank Li
@ 2024-04-27 6:43 0% ` Manivannan Sadhasivam
1 sibling, 0 replies; 200+ results
From: Manivannan Sadhasivam @ 2024-04-27 6:43 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Frank Li, Krzysztof Wilczyński, Uwe Kleine-König,
linux-omap, linux-pci, linux-arm-kernel, linux-kernel, imx,
linux-amlogic, linux-arm-msm, linux-tegra, Vignesh Raghavendra,
Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár
On Tue, Apr 23, 2024 at 08:19:06PM +0300, Andy Shevchenko wrote:
> The of_gpio.h is going to be removed. In preparation of that convert
> the driver to the agnostic API.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 37 ++++++++++-----------------
> 1 file changed, 14 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 917c69edee1d..d620f1e1a43c 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -11,14 +11,13 @@
> #include <linux/bitfield.h>
> #include <linux/clk.h>
> #include <linux/delay.h>
> -#include <linux/gpio.h>
> +#include <linux/gpio/consumer.h>
> #include <linux/kernel.h>
> #include <linux/mfd/syscon.h>
> #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
> #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> #include <linux/module.h>
> #include <linux/of.h>
> -#include <linux/of_gpio.h>
> #include <linux/of_address.h>
> #include <linux/pci.h>
> #include <linux/platform_device.h>
> @@ -107,7 +106,7 @@ struct imx6_pcie_drvdata {
>
> struct imx6_pcie {
> struct dw_pcie *pci;
> - int reset_gpio;
> + struct gpio_desc *reset_gpiod;
> bool gpio_active_high;
> bool link_is_up;
> struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS];
> @@ -721,9 +720,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
> }
>
> /* Some boards don't have PCIe reset GPIO. */
> - if (gpio_is_valid(imx6_pcie->reset_gpio))
> - gpio_set_value_cansleep(imx6_pcie->reset_gpio,
> - imx6_pcie->gpio_active_high);
> + gpiod_set_raw_value_cansleep(imx6_pcie->reset_gpiod,
> + imx6_pcie->gpio_active_high);
> }
>
> static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> @@ -771,10 +769,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> }
>
> /* Some boards don't have PCIe reset GPIO. */
> - if (gpio_is_valid(imx6_pcie->reset_gpio)) {
> + if (imx6_pcie->reset_gpiod) {
> msleep(100);
> - gpio_set_value_cansleep(imx6_pcie->reset_gpio,
> - !imx6_pcie->gpio_active_high);
> + gpiod_set_raw_value_cansleep(imx6_pcie->reset_gpiod,
> + !imx6_pcie->gpio_active_high);
> /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
> msleep(100);
> }
> @@ -1285,22 +1283,15 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> return PTR_ERR(pci->dbi_base);
>
> /* Fetch GPIOs */
> - imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
> imx6_pcie->gpio_active_high = of_property_read_bool(node,
> "reset-gpio-active-high");
> - if (gpio_is_valid(imx6_pcie->reset_gpio)) {
> - ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
> - imx6_pcie->gpio_active_high ?
> - GPIOF_OUT_INIT_HIGH :
> - GPIOF_OUT_INIT_LOW,
> - "PCIe reset");
> - if (ret) {
> - dev_err(dev, "unable to get reset gpio\n");
> - return ret;
> - }
> - } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
> - return imx6_pcie->reset_gpio;
> - }
> + imx6_pcie->reset_gpiod =
> + devm_gpiod_get_optional(dev, "reset",
> + imx6_pcie->gpio_active_high ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW);
> + if (IS_ERR(imx6_pcie->reset_gpiod))
> + return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod),
> + "unable to get reset gpio\n");
> + gpiod_set_consumer_name(imx6_pcie->reset_gpiod, "PCIe reset");
>
> if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS)
> return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
> --
> 2.43.0.rc1.1336.g36b5255a03ac
>
>
--
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* [PATCH v4 03/16] riscv: vector: Use vlenb from DT
@ 2024-04-26 21:29 5% ` Charlie Jenkins
2024-05-01 10:31 0% ` Conor Dooley
0 siblings, 1 reply; 200+ results
From: Charlie Jenkins @ 2024-04-26 21:29 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Guo Ren, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Conor Dooley, Evan Green,
Clément Léger, Jonathan Corbet, Shuah Khan
Cc: linux-riscv, devicetree, linux-kernel, Palmer Dabbelt,
linux-arm-kernel, linux-sunxi, linux-doc, linux-kselftest,
Charlie Jenkins
If vlenb is provided in the device tree, prefer that over reading the
vlenb csr.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
arch/riscv/include/asm/cpufeature.h | 2 ++
arch/riscv/kernel/cpufeature.c | 43 +++++++++++++++++++++++++++++++++++++
arch/riscv/kernel/vector.c | 12 ++++++++++-
3 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 347805446151..0c4f08577015 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
/* Per-cpu ISA extensions. */
extern struct riscv_isainfo hart_isa[NR_CPUS];
+extern u32 riscv_vlenb_of;
+
void riscv_user_isa_enable(void);
#if defined(CONFIG_RISCV_MISALIGNED)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3ed2359eae35..8158f34c3e36 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
/* Per-cpu ISA extensions. */
struct riscv_isainfo hart_isa[NR_CPUS];
+u32 riscv_vlenb_of;
+
/**
* riscv_isa_extension_base() - Get base extension word
*
@@ -648,6 +650,42 @@ static int __init riscv_isa_fallback_setup(char *__unused)
early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
#endif
+static int riscv_homogeneous_vlenb(void)
+{
+ int cpu;
+ u32 prev_vlenb = 0;
+ u32 vlenb;
+
+ for_each_possible_cpu(cpu) {
+ struct device_node *cpu_node;
+
+ cpu_node = of_cpu_device_node_get(cpu);
+ if (!cpu_node) {
+ pr_warn("Unable to find cpu node\n");
+ continue;
+ }
+
+ if (of_property_read_u32(cpu_node, "riscv,vlenb", &vlenb)) {
+ of_node_put(cpu_node);
+
+ if (prev_vlenb)
+ return -1;
+ continue;
+ }
+
+ if (prev_vlenb && vlenb != prev_vlenb) {
+ of_node_put(cpu_node);
+ return -1;
+ }
+
+ prev_vlenb = vlenb;
+ of_node_put(cpu_node);
+ }
+
+ riscv_vlenb_of = vlenb;
+ return 0;
+}
+
void __init riscv_fill_hwcap(void)
{
char print_str[NUM_ALPHA_EXTS + 1];
@@ -671,6 +709,11 @@ void __init riscv_fill_hwcap(void)
pr_info("Falling back to deprecated \"riscv,isa\"\n");
riscv_fill_hwcap_from_isa_string(isa2hwcap);
}
+
+ if (riscv_homogeneous_vlenb() < 0) {
+ pr_warn("RISCV_ISA_V only supports one vlenb on SMP systems. Please ensure that the riscv,vlenb devicetree property is the same across all CPUs. Either all CPUs must have the riscv,vlenb property, or none. If no CPUs in the devicetree use riscv,vlenb then vlenb will be probed from the vlenb CSR. Disabling vector.\n");
+ elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
+ }
}
/*
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index 6727d1d3b8f2..e04586cdb7f0 100644
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void)
{
unsigned long this_vsize;
- /* There are 32 vector registers with vlenb length. */
+ /*
+ * There are 32 vector registers with vlenb length.
+ *
+ * If the riscv,vlenb property was provided by the firmware, use that
+ * instead of probing the CSRs.
+ */
+ if (riscv_vlenb_of) {
+ this_vsize = riscv_vlenb_of * 32;
+ return 0;
+ }
+
riscv_v_enable();
this_vsize = csr_read(CSR_VLENB) * 32;
riscv_v_disable();
--
2.44.0
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^ permalink raw reply related [relevance 5%]
* Re: [PATCH v3 04/17] riscv: vector: Use vlenb from DT
2024-04-26 16:21 0% ` Conor Dooley
@ 2024-04-26 17:03 0% ` Charlie Jenkins
0 siblings, 0 replies; 200+ results
From: Charlie Jenkins @ 2024-04-26 17:03 UTC (permalink / raw)
To: Conor Dooley
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Guo Ren, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Conor Dooley, Evan Green,
Clément Léger, Jonathan Corbet, Shuah Khan,
linux-riscv, devicetree, linux-kernel, Palmer Dabbelt,
linux-arm-kernel, linux-sunxi, linux-doc, linux-kselftest
On Fri, Apr 26, 2024 at 05:21:16PM +0100, Conor Dooley wrote:
> On Fri, Apr 26, 2024 at 04:17:52PM +0100, Conor Dooley wrote:
> > On Sat, Apr 20, 2024 at 06:04:36PM -0700, Charlie Jenkins wrote:
> > > If vlenb is provided in the device tree, prefer that over reading the
> > > vlenb csr.
> > >
> > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > > ---
> > > arch/riscv/include/asm/cpufeature.h | 2 ++
> > > arch/riscv/kernel/cpufeature.c | 26 ++++++++++++++++++++++++++
> > > arch/riscv/kernel/vector.c | 13 +++++++++----
> > > 3 files changed, 37 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> > > index 347805446151..809f61ffb667 100644
> > > --- a/arch/riscv/include/asm/cpufeature.h
> > > +++ b/arch/riscv/include/asm/cpufeature.h
> > > @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
> > > /* Per-cpu ISA extensions. */
> > > extern struct riscv_isainfo hart_isa[NR_CPUS];
> > >
> > > +extern u32 riscv_vlenb_dt[NR_CPUS];
> > > +
> > > void riscv_user_isa_enable(void);
> > >
> > > #if defined(CONFIG_RISCV_MISALIGNED)
> > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > index c6e27b45e192..48874aac4871 100644
> > > --- a/arch/riscv/kernel/cpufeature.c
> > > +++ b/arch/riscv/kernel/cpufeature.c
> > > @@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
> > > /* Per-cpu ISA extensions. */
> > > struct riscv_isainfo hart_isa[NR_CPUS];
> > >
> > > +u32 riscv_vlenb_dt[NR_CPUS];
> > > +
> > > /**
> > > * riscv_isa_extension_base() - Get base extension word
> > > *
> > > @@ -656,6 +658,28 @@ static int __init riscv_isa_fallback_setup(char *__unused)
> > > early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
> > > #endif
> > >
> > > +static void riscv_set_vlenb_from_dt(void)
> >
> > I'd expect to see a name here that had "of" in it, not "dt".
>
> Also, "set" - I think "get" is more suitable here given that this
> doesn't actually set the vlen, we only do any setting later on in
> riscv_v_set_vsize().
>
> >
> > > +{
> > > + int cpu;
> > > +
> > > + for_each_possible_cpu(cpu) {
> > > + struct device_node *cpu_node;
> > > +
> > > + cpu_node = of_cpu_device_node_get(cpu);
> > > + if (!cpu_node) {
> > > + pr_warn("Unable to find cpu node\n");
> > > + continue;
> > > + }
> > > +
> > > + if (!of_property_read_u32(cpu_node, "riscv,vlenb", &riscv_vlenb_dt[cpu])) {
> > > + of_node_put(cpu_node);
> > > + continue;
> > > + }
> > > +
> > > + of_node_put(cpu_node);
> > > + }
> > > +}
> > > +
> > > void __init riscv_fill_hwcap(void)
> > > {
> > > char print_str[NUM_ALPHA_EXTS + 1];
> > > @@ -675,6 +699,8 @@ void __init riscv_fill_hwcap(void)
> > > } else {
> > > int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap);
> > >
> > > + riscv_set_vlenb_from_dt();
> >
> > Hmm, I think we can go a step further here. We know all of the CPUs
> > widths by the time we get to the first call to riscv_v_setup_vsize(), can
> > we examine the whole list and decide not to enable vector if they do
> > not match, rather than continuing and failing to online CPUs that having
> > the mismatched size?
> >
> > I guess that can go into the `if (elf_hwcap & COMPAT_HWCAP_ISA_V)`
> > condition we already have, and would require clearing the bit from the
> > mask we have at the moment.
Good point, thank you. Since this is not supported with ACPI, I will
clear the COMPAT_HWCAP_ISA_V bit from elf_hwcap if
riscv_set_vlenb_from_dt() (which will be renamed) determines that the
the riscv,vlenb field changes between CPU entries.
- Charlie
> >
> > Cheers,
> > Conor.
> >
> > > +
> > > if (ret && riscv_isa_fallback) {
> > > pr_info("Falling back to deprecated \"riscv,isa\"\n");
> > > riscv_fill_hwcap_from_isa_string(isa2hwcap);
> > > diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> > > index 6727d1d3b8f2..fb7f3ca80d9e 100644
> > > --- a/arch/riscv/kernel/vector.c
> > > +++ b/arch/riscv/kernel/vector.c
> > > @@ -32,11 +32,16 @@ EXPORT_SYMBOL_GPL(riscv_v_vsize);
> > > int riscv_v_setup_vsize(void)
> > > {
> > > unsigned long this_vsize;
> > > + int cpu = smp_processor_id();
> > >
> > > - /* There are 32 vector registers with vlenb length. */
> > > - riscv_v_enable();
> > > - this_vsize = csr_read(CSR_VLENB) * 32;
> > > - riscv_v_disable();
> > > + if (riscv_vlenb_dt[cpu]) {
> > > + this_vsize = riscv_vlenb_dt[cpu];
> >
> > > + } else {
> > > + /* There are 32 vector registers with vlenb length. */
> > > + riscv_v_enable();
> > > + this_vsize = csr_read(CSR_VLENB) * 32;
> > > + riscv_v_disable();
> > > + }
> > >
> > > if (!riscv_v_vsize) {
> > > riscv_v_vsize = this_vsize;
> > >
> > > --
> > > 2.44.0
> > >
>
>
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 04/17] riscv: vector: Use vlenb from DT
2024-04-26 15:17 0% ` Conor Dooley
@ 2024-04-26 16:21 0% ` Conor Dooley
2024-04-26 17:03 0% ` Charlie Jenkins
0 siblings, 1 reply; 200+ results
From: Conor Dooley @ 2024-04-26 16:21 UTC (permalink / raw)
To: Charlie Jenkins
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Guo Ren, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Conor Dooley, Evan Green,
Clément Léger, Jonathan Corbet, Shuah Khan,
linux-riscv, devicetree, linux-kernel, Palmer Dabbelt,
linux-arm-kernel, linux-sunxi, linux-doc, linux-kselftest
[-- Attachment #1.1: Type: text/plain, Size: 4406 bytes --]
On Fri, Apr 26, 2024 at 04:17:52PM +0100, Conor Dooley wrote:
> On Sat, Apr 20, 2024 at 06:04:36PM -0700, Charlie Jenkins wrote:
> > If vlenb is provided in the device tree, prefer that over reading the
> > vlenb csr.
> >
> > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > ---
> > arch/riscv/include/asm/cpufeature.h | 2 ++
> > arch/riscv/kernel/cpufeature.c | 26 ++++++++++++++++++++++++++
> > arch/riscv/kernel/vector.c | 13 +++++++++----
> > 3 files changed, 37 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> > index 347805446151..809f61ffb667 100644
> > --- a/arch/riscv/include/asm/cpufeature.h
> > +++ b/arch/riscv/include/asm/cpufeature.h
> > @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
> > /* Per-cpu ISA extensions. */
> > extern struct riscv_isainfo hart_isa[NR_CPUS];
> >
> > +extern u32 riscv_vlenb_dt[NR_CPUS];
> > +
> > void riscv_user_isa_enable(void);
> >
> > #if defined(CONFIG_RISCV_MISALIGNED)
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index c6e27b45e192..48874aac4871 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
> > /* Per-cpu ISA extensions. */
> > struct riscv_isainfo hart_isa[NR_CPUS];
> >
> > +u32 riscv_vlenb_dt[NR_CPUS];
> > +
> > /**
> > * riscv_isa_extension_base() - Get base extension word
> > *
> > @@ -656,6 +658,28 @@ static int __init riscv_isa_fallback_setup(char *__unused)
> > early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
> > #endif
> >
> > +static void riscv_set_vlenb_from_dt(void)
>
> I'd expect to see a name here that had "of" in it, not "dt".
Also, "set" - I think "get" is more suitable here given that this
doesn't actually set the vlen, we only do any setting later on in
riscv_v_set_vsize().
>
> > +{
> > + int cpu;
> > +
> > + for_each_possible_cpu(cpu) {
> > + struct device_node *cpu_node;
> > +
> > + cpu_node = of_cpu_device_node_get(cpu);
> > + if (!cpu_node) {
> > + pr_warn("Unable to find cpu node\n");
> > + continue;
> > + }
> > +
> > + if (!of_property_read_u32(cpu_node, "riscv,vlenb", &riscv_vlenb_dt[cpu])) {
> > + of_node_put(cpu_node);
> > + continue;
> > + }
> > +
> > + of_node_put(cpu_node);
> > + }
> > +}
> > +
> > void __init riscv_fill_hwcap(void)
> > {
> > char print_str[NUM_ALPHA_EXTS + 1];
> > @@ -675,6 +699,8 @@ void __init riscv_fill_hwcap(void)
> > } else {
> > int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap);
> >
> > + riscv_set_vlenb_from_dt();
>
> Hmm, I think we can go a step further here. We know all of the CPUs
> widths by the time we get to the first call to riscv_v_setup_vsize(), can
> we examine the whole list and decide not to enable vector if they do
> not match, rather than continuing and failing to online CPUs that having
> the mismatched size?
>
> I guess that can go into the `if (elf_hwcap & COMPAT_HWCAP_ISA_V)`
> condition we already have, and would require clearing the bit from the
> mask we have at the moment.
>
> Cheers,
> Conor.
>
> > +
> > if (ret && riscv_isa_fallback) {
> > pr_info("Falling back to deprecated \"riscv,isa\"\n");
> > riscv_fill_hwcap_from_isa_string(isa2hwcap);
> > diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> > index 6727d1d3b8f2..fb7f3ca80d9e 100644
> > --- a/arch/riscv/kernel/vector.c
> > +++ b/arch/riscv/kernel/vector.c
> > @@ -32,11 +32,16 @@ EXPORT_SYMBOL_GPL(riscv_v_vsize);
> > int riscv_v_setup_vsize(void)
> > {
> > unsigned long this_vsize;
> > + int cpu = smp_processor_id();
> >
> > - /* There are 32 vector registers with vlenb length. */
> > - riscv_v_enable();
> > - this_vsize = csr_read(CSR_VLENB) * 32;
> > - riscv_v_disable();
> > + if (riscv_vlenb_dt[cpu]) {
> > + this_vsize = riscv_vlenb_dt[cpu];
>
> > + } else {
> > + /* There are 32 vector registers with vlenb length. */
> > + riscv_v_enable();
> > + this_vsize = csr_read(CSR_VLENB) * 32;
> > + riscv_v_disable();
> > + }
> >
> > if (!riscv_v_vsize) {
> > riscv_v_vsize = this_vsize;
> >
> > --
> > 2.44.0
> >
[-- Attachment #1.2: signature.asc --]
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v3 04/17] riscv: vector: Use vlenb from DT
@ 2024-04-26 15:17 0% ` Conor Dooley
2024-04-26 16:21 0% ` Conor Dooley
0 siblings, 1 reply; 200+ results
From: Conor Dooley @ 2024-04-26 15:17 UTC (permalink / raw)
To: Charlie Jenkins
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Guo Ren, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Conor Dooley, Evan Green,
Clément Léger, Jonathan Corbet, Shuah Khan,
linux-riscv, devicetree, linux-kernel, Palmer Dabbelt,
linux-arm-kernel, linux-sunxi, linux-doc, linux-kselftest
[-- Attachment #1.1: Type: text/plain, Size: 3935 bytes --]
On Sat, Apr 20, 2024 at 06:04:36PM -0700, Charlie Jenkins wrote:
> If vlenb is provided in the device tree, prefer that over reading the
> vlenb csr.
>
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> ---
> arch/riscv/include/asm/cpufeature.h | 2 ++
> arch/riscv/kernel/cpufeature.c | 26 ++++++++++++++++++++++++++
> arch/riscv/kernel/vector.c | 13 +++++++++----
> 3 files changed, 37 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 347805446151..809f61ffb667 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
> /* Per-cpu ISA extensions. */
> extern struct riscv_isainfo hart_isa[NR_CPUS];
>
> +extern u32 riscv_vlenb_dt[NR_CPUS];
> +
> void riscv_user_isa_enable(void);
>
> #if defined(CONFIG_RISCV_MISALIGNED)
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index c6e27b45e192..48874aac4871 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
> /* Per-cpu ISA extensions. */
> struct riscv_isainfo hart_isa[NR_CPUS];
>
> +u32 riscv_vlenb_dt[NR_CPUS];
> +
> /**
> * riscv_isa_extension_base() - Get base extension word
> *
> @@ -656,6 +658,28 @@ static int __init riscv_isa_fallback_setup(char *__unused)
> early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
> #endif
>
> +static void riscv_set_vlenb_from_dt(void)
I'd expect to see a name here that had "of" in it, not "dt".
> +{
> + int cpu;
> +
> + for_each_possible_cpu(cpu) {
> + struct device_node *cpu_node;
> +
> + cpu_node = of_cpu_device_node_get(cpu);
> + if (!cpu_node) {
> + pr_warn("Unable to find cpu node\n");
> + continue;
> + }
> +
> + if (!of_property_read_u32(cpu_node, "riscv,vlenb", &riscv_vlenb_dt[cpu])) {
> + of_node_put(cpu_node);
> + continue;
> + }
> +
> + of_node_put(cpu_node);
> + }
> +}
> +
> void __init riscv_fill_hwcap(void)
> {
> char print_str[NUM_ALPHA_EXTS + 1];
> @@ -675,6 +699,8 @@ void __init riscv_fill_hwcap(void)
> } else {
> int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap);
>
> + riscv_set_vlenb_from_dt();
Hmm, I think we can go a step further here. We know all of the CPUs
widths by the time we get to the first call to riscv_v_setup_vsize(), can
we examine the whole list and decide not to enable vector if they do
not match, rather than continuing and failing to online CPUs that having
the mismatched size?
I guess that can go into the `if (elf_hwcap & COMPAT_HWCAP_ISA_V)`
condition we already have, and would require clearing the bit from the
mask we have at the moment.
Cheers,
Conor.
> +
> if (ret && riscv_isa_fallback) {
> pr_info("Falling back to deprecated \"riscv,isa\"\n");
> riscv_fill_hwcap_from_isa_string(isa2hwcap);
> diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> index 6727d1d3b8f2..fb7f3ca80d9e 100644
> --- a/arch/riscv/kernel/vector.c
> +++ b/arch/riscv/kernel/vector.c
> @@ -32,11 +32,16 @@ EXPORT_SYMBOL_GPL(riscv_v_vsize);
> int riscv_v_setup_vsize(void)
> {
> unsigned long this_vsize;
> + int cpu = smp_processor_id();
>
> - /* There are 32 vector registers with vlenb length. */
> - riscv_v_enable();
> - this_vsize = csr_read(CSR_VLENB) * 32;
> - riscv_v_disable();
> + if (riscv_vlenb_dt[cpu]) {
> + this_vsize = riscv_vlenb_dt[cpu];
> + } else {
> + /* There are 32 vector registers with vlenb length. */
> + riscv_v_enable();
> + this_vsize = csr_read(CSR_VLENB) * 32;
> + riscv_v_disable();
> + }
>
> if (!riscv_v_vsize) {
> riscv_v_vsize = this_vsize;
>
> --
> 2.44.0
>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply [relevance 0%]
* [PATCH v8 16/16] cpumask: Add enabled cpumask for present CPUs that can be brought online
2024-04-26 13:51 5% ` [PATCH v8 14/16] arm64: Kconfig: Enable hotplug CPU on arm64 if ACPI_PROCESSOR is enabled Jonathan Cameron
@ 2024-04-26 13:51 4% ` Jonathan Cameron
1 sibling, 0 replies; 200+ results
From: Jonathan Cameron @ 2024-04-26 13:51 UTC (permalink / raw)
To: Thomas Gleixner, Peter Zijlstra, linux-pm, loongarch, linux-acpi,
linux-arch, linux-kernel, linux-arm-kernel, kvmarm, x86,
Russell King, Rafael J . Wysocki, Miguel Luis, James Morse,
Salil Mehta, Jean-Philippe Brucker, Catalin Marinas, Will Deacon,
Marc Zyngier, Hanjun Guo
Cc: Ingo Molnar, Borislav Petkov, Dave Hansen, linuxarm, justin.he,
jianyong.wu, Lorenzo Pieralisi, Sudeep Holla
From: James Morse <james.morse@arm.com>
The 'offline' file in sysfs shows all offline CPUs, including those
that aren't present. User-space is expected to remove not-present CPUs
from this list to learn which CPUs could be brought online.
CPUs can be present but not-enabled. These CPUs can't be brought online
until the firmware policy changes, which comes with an ACPI notification
that will register the CPUs.
With only the offline and present files, user-space is unable to
determine which CPUs it can try to bring online. Add a new CPU mask
that shows this based on all the registered CPUs.
Signed-off-by: James Morse <james.morse@arm.com>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
Tested-by: Vishnu Pajjuri <vishnu@os.amperecomputing.com>
Tested-by: Jianyong Wu <jianyong.wu@arm.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
.../ABI/testing/sysfs-devices-system-cpu | 6 +++++
drivers/base/cpu.c | 10 ++++++++
include/linux/cpumask.h | 25 +++++++++++++++++++
kernel/cpu.c | 3 +++
4 files changed, 44 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
index 710d47be11e0..808efb5b860a 100644
--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
@@ -694,3 +694,9 @@ Description:
(RO) indicates whether or not the kernel directly supports
modifying the crash elfcorehdr for CPU hot un/plug and/or
on/offline changes.
+
+What: /sys/devices/system/cpu/enabled
+Date: Nov 2022
+Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
+Description:
+ (RO) the list of CPUs that can be brought online.
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index 7b83e9c87d7c..353ee39a5cbe 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -95,6 +95,7 @@ void unregister_cpu(struct cpu *cpu)
{
int logical_cpu = cpu->dev.id;
+ set_cpu_enabled(logical_cpu, false);
unregister_cpu_under_node(logical_cpu, cpu_to_node(logical_cpu));
device_unregister(&cpu->dev);
@@ -273,6 +274,13 @@ static ssize_t print_cpus_offline(struct device *dev,
}
static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL);
+static ssize_t print_cpus_enabled(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(cpu_enabled_mask));
+}
+static DEVICE_ATTR(enabled, 0444, print_cpus_enabled, NULL);
+
static ssize_t print_cpus_isolated(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -413,6 +421,7 @@ int register_cpu(struct cpu *cpu, int num)
register_cpu_under_node(num, cpu_to_node(num));
dev_pm_qos_expose_latency_limit(&cpu->dev,
PM_QOS_RESUME_LATENCY_NO_CONSTRAINT);
+ set_cpu_enabled(num, true);
return 0;
}
@@ -494,6 +503,7 @@ static struct attribute *cpu_root_attrs[] = {
&cpu_attrs[2].attr.attr,
&dev_attr_kernel_max.attr,
&dev_attr_offline.attr,
+ &dev_attr_enabled.attr,
&dev_attr_isolated.attr,
#ifdef CONFIG_NO_HZ_FULL
&dev_attr_nohz_full.attr,
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index 1c29947db848..4b202b94c97a 100644
--- a/include/linux/cpumask.h
+++ b/include/linux/cpumask.h
@@ -93,6 +93,7 @@ static inline void set_nr_cpu_ids(unsigned int nr)
*
* cpu_possible_mask- has bit 'cpu' set iff cpu is populatable
* cpu_present_mask - has bit 'cpu' set iff cpu is populated
+ * cpu_enabled_mask - has bit 'cpu' set iff cpu can be brought online
* cpu_online_mask - has bit 'cpu' set iff cpu available to scheduler
* cpu_active_mask - has bit 'cpu' set iff cpu available to migration
*
@@ -125,11 +126,13 @@ static inline void set_nr_cpu_ids(unsigned int nr)
extern struct cpumask __cpu_possible_mask;
extern struct cpumask __cpu_online_mask;
+extern struct cpumask __cpu_enabled_mask;
extern struct cpumask __cpu_present_mask;
extern struct cpumask __cpu_active_mask;
extern struct cpumask __cpu_dying_mask;
#define cpu_possible_mask ((const struct cpumask *)&__cpu_possible_mask)
#define cpu_online_mask ((const struct cpumask *)&__cpu_online_mask)
+#define cpu_enabled_mask ((const struct cpumask *)&__cpu_enabled_mask)
#define cpu_present_mask ((const struct cpumask *)&__cpu_present_mask)
#define cpu_active_mask ((const struct cpumask *)&__cpu_active_mask)
#define cpu_dying_mask ((const struct cpumask *)&__cpu_dying_mask)
@@ -1009,6 +1012,7 @@ extern const DECLARE_BITMAP(cpu_all_bits, NR_CPUS);
#else
#define for_each_possible_cpu(cpu) for_each_cpu((cpu), cpu_possible_mask)
#define for_each_online_cpu(cpu) for_each_cpu((cpu), cpu_online_mask)
+#define for_each_enabled_cpu(cpu) for_each_cpu((cpu), cpu_enabled_mask)
#define for_each_present_cpu(cpu) for_each_cpu((cpu), cpu_present_mask)
#endif
@@ -1031,6 +1035,15 @@ set_cpu_possible(unsigned int cpu, bool possible)
cpumask_clear_cpu(cpu, &__cpu_possible_mask);
}
+static inline void
+set_cpu_enabled(unsigned int cpu, bool can_be_onlined)
+{
+ if (can_be_onlined)
+ cpumask_set_cpu(cpu, &__cpu_enabled_mask);
+ else
+ cpumask_clear_cpu(cpu, &__cpu_enabled_mask);
+}
+
static inline void
set_cpu_present(unsigned int cpu, bool present)
{
@@ -1112,6 +1125,7 @@ static __always_inline unsigned int num_online_cpus(void)
return raw_atomic_read(&__num_online_cpus);
}
#define num_possible_cpus() cpumask_weight(cpu_possible_mask)
+#define num_enabled_cpus() cpumask_weight(cpu_enabled_mask)
#define num_present_cpus() cpumask_weight(cpu_present_mask)
#define num_active_cpus() cpumask_weight(cpu_active_mask)
@@ -1120,6 +1134,11 @@ static inline bool cpu_online(unsigned int cpu)
return cpumask_test_cpu(cpu, cpu_online_mask);
}
+static inline bool cpu_enabled(unsigned int cpu)
+{
+ return cpumask_test_cpu(cpu, cpu_enabled_mask);
+}
+
static inline bool cpu_possible(unsigned int cpu)
{
return cpumask_test_cpu(cpu, cpu_possible_mask);
@@ -1144,6 +1163,7 @@ static inline bool cpu_dying(unsigned int cpu)
#define num_online_cpus() 1U
#define num_possible_cpus() 1U
+#define num_enabled_cpus() 1U
#define num_present_cpus() 1U
#define num_active_cpus() 1U
@@ -1157,6 +1177,11 @@ static inline bool cpu_possible(unsigned int cpu)
return cpu == 0;
}
+static inline bool cpu_enabled(unsigned int cpu)
+{
+ return cpu == 0;
+}
+
static inline bool cpu_present(unsigned int cpu)
{
return cpu == 0;
diff --git a/kernel/cpu.c b/kernel/cpu.c
index 8f6affd051f7..537099bf5d02 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -3117,6 +3117,9 @@ EXPORT_SYMBOL(__cpu_possible_mask);
struct cpumask __cpu_online_mask __read_mostly;
EXPORT_SYMBOL(__cpu_online_mask);
+struct cpumask __cpu_enabled_mask __read_mostly;
+EXPORT_SYMBOL(__cpu_enabled_mask);
+
struct cpumask __cpu_present_mask __read_mostly;
EXPORT_SYMBOL(__cpu_present_mask);
--
2.39.2
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^ permalink raw reply related [relevance 4%]
* [PATCH v8 14/16] arm64: Kconfig: Enable hotplug CPU on arm64 if ACPI_PROCESSOR is enabled.
@ 2024-04-26 13:51 5% ` Jonathan Cameron
2024-04-26 13:51 4% ` [PATCH v8 16/16] cpumask: Add enabled cpumask for present CPUs that can be brought online Jonathan Cameron
1 sibling, 0 replies; 200+ results
From: Jonathan Cameron @ 2024-04-26 13:51 UTC (permalink / raw)
To: Thomas Gleixner, Peter Zijlstra, linux-pm, loongarch, linux-acpi,
linux-arch, linux-kernel, linux-arm-kernel, kvmarm, x86,
Russell King, Rafael J . Wysocki, Miguel Luis, James Morse,
Salil Mehta, Jean-Philippe Brucker, Catalin Marinas, Will Deacon,
Marc Zyngier, Hanjun Guo
Cc: Ingo Molnar, Borislav Petkov, Dave Hansen, linuxarm, justin.he,
jianyong.wu, Lorenzo Pieralisi, Sudeep Holla
In order to move arch_register_cpu() to be called via the same path
for initially present CPUs described by ACPI and hotplugged CPUs
ACPI_HOTPLUG_CPU needs to be enabled.
The protection against invalid IDs in acpi_map_cpu() is needed as
at least one production BIOS is in the wild which reports entries
in DSDT (with no _STA method, so assumed enabled and present)
that don't match MADT.
Tested-by: Miguel Luis <miguel.luis@oracle.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v8: If acpi_map_cpu() stub is passed an error code as pcpu, don't
pretend it worked.
Note that x86 relies on passing an invalid error code in here
to indicate a CPU ID needs to be allocated, on ARM64 if we
don't get something valid there is nothing we can do about it.
---
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/acpi.c | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7b11c98b3e84..fed7d0d54179 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -5,6 +5,7 @@ config ARM64
select ACPI_CCA_REQUIRED if ACPI
select ACPI_GENERIC_GSI if ACPI
select ACPI_GTDT if ACPI
+ select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR
select ACPI_IORT if ACPI
select ACPI_REDUCED_HARDWARE_ONLY if ACPI
select ACPI_MCFG if (ACPI && PCI)
diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index dba8fcec7f33..fb9368197c74 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -29,6 +29,7 @@
#include <linux/pgtable.h>
#include <acpi/ghes.h>
+#include <acpi/processor.h>
#include <asm/cputype.h>
#include <asm/cpu_ops.h>
#include <asm/daifflags.h>
@@ -413,6 +414,27 @@ void arch_reserve_mem_area(acpi_physical_address addr, size_t size)
memblock_mark_nomap(addr, size);
}
+#ifdef CONFIG_ACPI_HOTPLUG_CPU
+int acpi_map_cpu(acpi_handle handle, phys_cpuid_t physid, u32 apci_id,
+ int *pcpu)
+{
+ /* If an error code is passed in this stub can't fix it */
+ if (*pcpu < 0) {
+ pr_warn_once("Unable to map CPU to valid ID\n");
+ return *pcpu;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(acpi_map_cpu);
+
+int acpi_unmap_cpu(int cpu)
+{
+ return 0;
+}
+EXPORT_SYMBOL(acpi_unmap_cpu);
+#endif /* CONFIG_ACPI_HOTPLUG_CPU */
+
#ifdef CONFIG_ACPI_FFH
/*
* Implements ARM64 specific callbacks to support ACPI FFH Operation Region as
--
2.39.2
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^ permalink raw reply related [relevance 5%]
* [PATCH v3 2/2] pinctrl: samsung: support a bus clock
@ 2024-04-26 13:25 9% ` André Draszik
2024-05-02 7:41 0% ` Tudor Ambarus
0 siblings, 1 reply; 200+ results
From: André Draszik @ 2024-04-26 13:25 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Alim Akhtar,
Linus Walleij, Rob Herring, Conor Dooley, Tomasz Figa,
Peter Griffin
Cc: Tudor Ambarus, Will McVicker, Sam Protsenko, kernel-team,
linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree,
linux-kernel, André Draszik
On some Samsung-based SoCs there are separate bus clocks / gates each
for each pinctrl instance. To be able to access each pinctrl instance's
registers, this bus clock needs to be running, otherwise register
access will hang. Google Tensor gs101 is one example for such an
implementation.
Update the driver to handle this optional bus clock:
* handle an optional bus clock from DT
* prepare it during driver probe
* enclose all relevant register accesses with a clock enable & disable
Signed-off-by: André Draszik <andre.draszik@linaro.org>
---
v2:
- propagate clk_enable() errors in samsung_pinmux_setup(), i.e.
struct pinmux_ops::set_mux()
- move clk_enable()/disable() outside bank->slock lock, to avoid
possible deadlocks due to locking inversion
- fix some comments
- use 'ret' instead of 'i' in samsung_pinctrl_resume()
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 112 ++++++++++++++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 95 ++++++++++++++++++++++++-
drivers/pinctrl/samsung/pinctrl-samsung.h | 2 +
3 files changed, 206 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 871c1eb46ddf..ce5e6783b5b9 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -13,6 +13,7 @@
// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
// external gpio and wakeup interrupt support.
+#include <linux/clk.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
@@ -61,6 +62,12 @@ static void exynos_irq_mask(struct irq_data *irqd)
else
reg_mask = our_chip->eint_mask + bank->eint_offset;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for masking IRQ\n");
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
mask = readl(bank->eint_base + reg_mask);
@@ -68,6 +75,8 @@ static void exynos_irq_mask(struct irq_data *irqd)
writel(mask, bank->eint_base + reg_mask);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(bank->drvdata->pclk);
}
static void exynos_irq_ack(struct irq_data *irqd)
@@ -82,7 +91,15 @@ static void exynos_irq_ack(struct irq_data *irqd)
else
reg_pend = our_chip->eint_pend + bank->eint_offset;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock to ack IRQ\n");
+ return;
+ }
+
writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
+
+ clk_disable(bank->drvdata->pclk);
}
static void exynos_irq_unmask(struct irq_data *irqd)
@@ -110,6 +127,12 @@ static void exynos_irq_unmask(struct irq_data *irqd)
else
reg_mask = our_chip->eint_mask + bank->eint_offset;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for unmasking IRQ\n");
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
mask = readl(bank->eint_base + reg_mask);
@@ -117,6 +140,8 @@ static void exynos_irq_unmask(struct irq_data *irqd)
writel(mask, bank->eint_base + reg_mask);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(bank->drvdata->pclk);
}
static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
@@ -127,6 +152,7 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
unsigned int con, trig_type;
unsigned long reg_con;
+ int ret;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
@@ -159,11 +185,20 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
else
reg_con = our_chip->eint_con + bank->eint_offset;
+ ret = clk_enable(bank->drvdata->pclk);
+ if (ret) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for configuring IRQ type\n");
+ return ret;
+ }
+
con = readl(bank->eint_base + reg_con);
con &= ~(EXYNOS_EINT_CON_MASK << shift);
con |= trig_type << shift;
writel(con, bank->eint_base + reg_con);
+ clk_disable(bank->drvdata->pclk);
+
return 0;
}
@@ -200,6 +235,14 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
+ ret = clk_enable(bank->drvdata->pclk);
+ if (ret) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for configuring pin %s-%lu\n",
+ bank->name, irqd->hwirq);
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->pctl_base + reg_con);
@@ -209,6 +252,8 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(bank->drvdata->pclk);
+
return 0;
}
@@ -223,6 +268,13 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for deconfiguring pin %s-%lu\n",
+ bank->name, irqd->hwirq);
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->pctl_base + reg_con);
@@ -232,6 +284,8 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(bank->drvdata->pclk);
+
gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
}
@@ -281,10 +335,19 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
unsigned int svc, group, pin;
int ret;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for handling IRQ\n");
+ return IRQ_NONE;
+ }
+
if (bank->eint_con_offset)
svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);
else
svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
+
+ clk_disable(bank->drvdata->pclk);
+
group = EXYNOS_SVC_GROUP(svc);
pin = svc & EXYNOS_SVC_NUM_MASK;
@@ -563,6 +626,20 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
chained_irq_enter(chip, desc);
+ /*
+ * just enable the clock once here, to avoid an enable/disable dance for
+ * each bank.
+ */
+ if (eintd->nr_banks) {
+ struct samsung_pin_bank *b = eintd->banks[0];
+
+ if (clk_enable(b->drvdata->pclk)) {
+ dev_err(b->gpio_chip.parent,
+ "unable to enable clock for pending IRQs\n");
+ return;
+ }
+ }
+
for (i = 0; i < eintd->nr_banks; ++i) {
struct samsung_pin_bank *b = eintd->banks[i];
pend = readl(b->eint_base + b->irq_chip->eint_pend
@@ -572,6 +649,9 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
}
+ if (eintd->nr_banks)
+ clk_disable(eintd->banks[0]->drvdata->pclk);
+
chained_irq_exit(chip, desc);
}
@@ -695,6 +775,12 @@ static void exynos_pinctrl_suspend_bank(
struct exynos_eint_gpio_save *save = bank->soc_priv;
const void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for saving state\n");
+ return;
+ }
+
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset);
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
@@ -704,6 +790,8 @@ static void exynos_pinctrl_suspend_bank(
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
+ bank->eint_offset);
+ clk_disable(bank->drvdata->pclk);
+
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
@@ -716,9 +804,17 @@ static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data *drv
struct exynos_eint_gpio_save *save = bank->soc_priv;
const void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for saving state\n");
+ return;
+ }
+
save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
+ clk_disable(bank->drvdata->pclk);
+
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
}
@@ -753,6 +849,12 @@ static void exynos_pinctrl_resume_bank(
struct exynos_eint_gpio_save *save = bank->soc_priv;
void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for restoring state\n");
+ return;
+ }
+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
readl(regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset), save->eint_con);
@@ -774,6 +876,8 @@ static void exynos_pinctrl_resume_bank(
+ 2 * bank->eint_offset + 4);
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
+ bank->eint_offset);
+
+ clk_disable(bank->drvdata->pclk);
}
static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata,
@@ -782,6 +886,12 @@ static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvd
struct exynos_eint_gpio_save *save = bank->soc_priv;
void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for restoring state\n");
+ return;
+ }
+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
@@ -789,6 +899,8 @@ static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvd
writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
+
+ clk_disable(bank->drvdata->pclk);
}
void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index ed07e23e0912..acde42983934 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -15,6 +15,7 @@
// but provides extensions to which platform specific implementation of the gpio
// and wakeup interrupts can be hooked to.
+#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
@@ -371,7 +372,7 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
}
/* enable or disable a pinmux function */
-static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
+static int samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct samsung_pinctrl_drv_data *drvdata;
@@ -382,6 +383,7 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
unsigned long flags;
const struct samsung_pmx_func *func;
const struct samsung_pin_group *grp;
+ int ret;
drvdata = pinctrl_dev_get_drvdata(pctldev);
func = &drvdata->pmx_functions[selector];
@@ -397,6 +399,12 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
reg += 4;
}
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(pctldev->dev, "failed to enable clock for setup\n");
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
@@ -405,6 +413,10 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(drvdata->pclk);
+
+ return 0;
}
/* enable a specified pinmux by writing to registers */
@@ -412,8 +424,7 @@ static int samsung_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned selector,
unsigned group)
{
- samsung_pinmux_setup(pctldev, selector, group);
- return 0;
+ return samsung_pinmux_setup(pctldev, selector, group);
}
/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
@@ -436,6 +447,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
u32 data, width, pin_offset, mask, shift;
u32 cfg_value, cfg_reg;
unsigned long flags;
+ int ret;
drvdata = pinctrl_dev_get_drvdata(pctldev);
pin_to_reg_bank(drvdata, pin, ®_base, &pin_offset, &bank);
@@ -447,6 +459,12 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
width = type->fld_width[cfg_type];
cfg_reg = type->reg_offset[cfg_type];
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
mask = (1 << width) - 1;
@@ -466,6 +484,8 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(drvdata->pclk);
+
return 0;
}
@@ -555,11 +575,19 @@ static void samsung_gpio_set_value(struct gpio_chip *gc,
static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
{
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
+ struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
unsigned long flags;
+ if (clk_enable(drvdata->pclk)) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
samsung_gpio_set_value(gc, offset, value);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(drvdata->pclk);
}
/* gpiolib gpio_get callback function */
@@ -569,12 +597,23 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
u32 data;
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
const struct samsung_pin_bank_type *type = bank->type;
+ struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
+ int ret;
reg = bank->pctl_base + bank->pctl_offset;
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
data >>= offset;
data &= 1;
+
+ clk_disable(drvdata->pclk);
+
return data;
}
@@ -591,9 +630,11 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
struct samsung_pin_bank *bank;
void __iomem *reg;
u32 data, mask, shift;
+ struct samsung_pinctrl_drv_data *drvdata;
bank = gpiochip_get_data(gc);
type = bank->type;
+ drvdata = bank->drvdata;
reg = bank->pctl_base + bank->pctl_offset
+ type->reg_offset[PINCFG_TYPE_FUNC];
@@ -619,12 +660,22 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
{
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
+ struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
unsigned long flags;
int ret;
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
ret = samsung_gpio_set_direction(gc, offset, true);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(drvdata->pclk);
+
return ret;
}
@@ -633,14 +684,23 @@ static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
+ struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
unsigned long flags;
int ret;
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
samsung_gpio_set_value(gc, offset, value);
ret = samsung_gpio_set_direction(gc, offset, false);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(drvdata->pclk);
+
return ret;
}
@@ -1164,6 +1224,12 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
}
}
+ drvdata->pclk = devm_clk_get_optional_prepared(dev, "pclk");
+ if (IS_ERR(drvdata->pclk)) {
+ ret = PTR_ERR(drvdata->pclk);
+ goto err_put_banks;
+ }
+
ret = samsung_pinctrl_register(pdev, drvdata);
if (ret)
goto err_put_banks;
@@ -1202,6 +1268,13 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
int i;
+ i = clk_enable(drvdata->pclk);
+ if (i) {
+ dev_err(drvdata->dev,
+ "failed to enable clock for saving state\n");
+ return i;
+ }
+
for (i = 0; i < drvdata->nr_banks; i++) {
struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
const void __iomem *reg = bank->pctl_base + bank->pctl_offset;
@@ -1231,6 +1304,8 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
}
}
+ clk_disable(drvdata->pclk);
+
if (drvdata->suspend)
drvdata->suspend(drvdata);
if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable)
@@ -1250,8 +1325,20 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
{
struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
+ int ret;
int i;
+ /*
+ * enable clock before the callback, as we don't want to have to deal
+ * with callback cleanup on clock failures.
+ */
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev,
+ "failed to enable clock for restoring state\n");
+ return ret;
+ }
+
if (drvdata->resume)
drvdata->resume(drvdata);
@@ -1286,6 +1373,8 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
writel(bank->pm_save[type], reg + offs[type]);
}
+ clk_disable(drvdata->pclk);
+
if (drvdata->retention_ctrl && drvdata->retention_ctrl->disable)
drvdata->retention_ctrl->disable(drvdata);
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index ab791afaabf5..d50ba6f07d5d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -274,6 +274,7 @@ struct samsung_pin_ctrl {
* through samsung_pinctrl_drv_data, not samsung_pin_bank).
* @dev: device instance representing the controller.
* @irq: interrpt number used by the controller to notify gpio interrupts.
+ * @pclk: optional bus clock if required for accessing registers
* @ctrl: pin controller instance managed by the driver.
* @pctl: pin controller descriptor registered with the pinctrl subsystem.
* @pctl_dev: cookie representing pinctrl device instance.
@@ -293,6 +294,7 @@ struct samsung_pinctrl_drv_data {
void __iomem *virt_base;
struct device *dev;
int irq;
+ struct clk *pclk;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
--
2.44.0.769.g3c40516874-goog
_______________________________________________
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^ permalink raw reply related [relevance 9%]
* [PATCH v2 2/2] pinctrl: samsung: support a bus clock
@ 2024-04-26 13:10 9% ` André Draszik
0 siblings, 0 replies; 200+ results
From: André Draszik @ 2024-04-26 13:10 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Alim Akhtar,
Linus Walleij, Rob Herring, Conor Dooley, Tomasz Figa,
Peter Griffin
Cc: Tudor Ambarus, Will McVicker, Sam Protsenko, kernel-team,
linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree,
linux-kernel, André Draszik
On some Samsung-based SoCs there are separate bus clocks / gates each
for each pinctrl instance. To be able to access each pinctrl instance's
registers, this bus clock needs to be running, otherwise register
access will hang. Google Tensor gs101 is one example for such an
implementation.
Update the driver to handle this optional bus clock:
* handle an optional bus clock from DT
* prepare it during driver probe
* enclose all relevant register accesses with a clock enable & disable
Signed-off-by: André Draszik <andre.draszik@linaro.org>
---
v2:
- propagate clk_enable() errors in samsung_pinmux_setup(), i.e.
struct pinmux_ops::set_mux()
- move clk_enable()/disable() outside bank->slock lock, to avoid
possible deadlocks due to locking inversion
- fix some comments
- use 'ret' instead of 'i' in samsung_pinctrl_resume()
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 112 ++++++++++++++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 95 ++++++++++++++++++++++++-
drivers/pinctrl/samsung/pinctrl-samsung.h | 2 +
3 files changed, 206 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 871c1eb46ddf..ce5e6783b5b9 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -13,6 +13,7 @@
// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
// external gpio and wakeup interrupt support.
+#include <linux/clk.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
@@ -61,6 +62,12 @@ static void exynos_irq_mask(struct irq_data *irqd)
else
reg_mask = our_chip->eint_mask + bank->eint_offset;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for masking IRQ\n");
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
mask = readl(bank->eint_base + reg_mask);
@@ -68,6 +75,8 @@ static void exynos_irq_mask(struct irq_data *irqd)
writel(mask, bank->eint_base + reg_mask);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(bank->drvdata->pclk);
}
static void exynos_irq_ack(struct irq_data *irqd)
@@ -82,7 +91,15 @@ static void exynos_irq_ack(struct irq_data *irqd)
else
reg_pend = our_chip->eint_pend + bank->eint_offset;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock to ack IRQ\n");
+ return;
+ }
+
writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
+
+ clk_disable(bank->drvdata->pclk);
}
static void exynos_irq_unmask(struct irq_data *irqd)
@@ -110,6 +127,12 @@ static void exynos_irq_unmask(struct irq_data *irqd)
else
reg_mask = our_chip->eint_mask + bank->eint_offset;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for unmasking IRQ\n");
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
mask = readl(bank->eint_base + reg_mask);
@@ -117,6 +140,8 @@ static void exynos_irq_unmask(struct irq_data *irqd)
writel(mask, bank->eint_base + reg_mask);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(bank->drvdata->pclk);
}
static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
@@ -127,6 +152,7 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
unsigned int con, trig_type;
unsigned long reg_con;
+ int ret;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
@@ -159,11 +185,20 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
else
reg_con = our_chip->eint_con + bank->eint_offset;
+ ret = clk_enable(bank->drvdata->pclk);
+ if (ret) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for configuring IRQ type\n");
+ return ret;
+ }
+
con = readl(bank->eint_base + reg_con);
con &= ~(EXYNOS_EINT_CON_MASK << shift);
con |= trig_type << shift;
writel(con, bank->eint_base + reg_con);
+ clk_disable(bank->drvdata->pclk);
+
return 0;
}
@@ -200,6 +235,14 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
+ ret = clk_enable(bank->drvdata->pclk);
+ if (ret) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for configuring pin %s-%lu\n",
+ bank->name, irqd->hwirq);
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->pctl_base + reg_con);
@@ -209,6 +252,8 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(bank->drvdata->pclk);
+
return 0;
}
@@ -223,6 +268,13 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for deconfiguring pin %s-%lu\n",
+ bank->name, irqd->hwirq);
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->pctl_base + reg_con);
@@ -232,6 +284,8 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(bank->drvdata->pclk);
+
gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
}
@@ -281,10 +335,19 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
unsigned int svc, group, pin;
int ret;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for handling IRQ\n");
+ return IRQ_NONE;
+ }
+
if (bank->eint_con_offset)
svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);
else
svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
+
+ clk_disable(bank->drvdata->pclk);
+
group = EXYNOS_SVC_GROUP(svc);
pin = svc & EXYNOS_SVC_NUM_MASK;
@@ -563,6 +626,20 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
chained_irq_enter(chip, desc);
+ /*
+ * just enable the clock once here, to avoid an enable/disable dance for
+ * each bank.
+ */
+ if (eintd->nr_banks) {
+ struct samsung_pin_bank *b = eintd->banks[0];
+
+ if (clk_enable(b->drvdata->pclk)) {
+ dev_err(b->gpio_chip.parent,
+ "unable to enable clock for pending IRQs\n");
+ return;
+ }
+ }
+
for (i = 0; i < eintd->nr_banks; ++i) {
struct samsung_pin_bank *b = eintd->banks[i];
pend = readl(b->eint_base + b->irq_chip->eint_pend
@@ -572,6 +649,9 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
}
+ if (eintd->nr_banks)
+ clk_disable(eintd->banks[0]->drvdata->pclk);
+
chained_irq_exit(chip, desc);
}
@@ -695,6 +775,12 @@ static void exynos_pinctrl_suspend_bank(
struct exynos_eint_gpio_save *save = bank->soc_priv;
const void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for saving state\n");
+ return;
+ }
+
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset);
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
@@ -704,6 +790,8 @@ static void exynos_pinctrl_suspend_bank(
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
+ bank->eint_offset);
+ clk_disable(bank->drvdata->pclk);
+
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
@@ -716,9 +804,17 @@ static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data *drv
struct exynos_eint_gpio_save *save = bank->soc_priv;
const void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for saving state\n");
+ return;
+ }
+
save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
+ clk_disable(bank->drvdata->pclk);
+
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
}
@@ -753,6 +849,12 @@ static void exynos_pinctrl_resume_bank(
struct exynos_eint_gpio_save *save = bank->soc_priv;
void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for restoring state\n");
+ return;
+ }
+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
readl(regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset), save->eint_con);
@@ -774,6 +876,8 @@ static void exynos_pinctrl_resume_bank(
+ 2 * bank->eint_offset + 4);
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
+ bank->eint_offset);
+
+ clk_disable(bank->drvdata->pclk);
}
static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata,
@@ -782,6 +886,12 @@ static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvd
struct exynos_eint_gpio_save *save = bank->soc_priv;
void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for restoring state\n");
+ return;
+ }
+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
@@ -789,6 +899,8 @@ static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvd
writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
+
+ clk_disable(bank->drvdata->pclk);
}
void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index ed07e23e0912..acde42983934 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -15,6 +15,7 @@
// but provides extensions to which platform specific implementation of the gpio
// and wakeup interrupts can be hooked to.
+#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
@@ -371,7 +372,7 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
}
/* enable or disable a pinmux function */
-static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
+static int samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct samsung_pinctrl_drv_data *drvdata;
@@ -382,6 +383,7 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
unsigned long flags;
const struct samsung_pmx_func *func;
const struct samsung_pin_group *grp;
+ int ret;
drvdata = pinctrl_dev_get_drvdata(pctldev);
func = &drvdata->pmx_functions[selector];
@@ -397,6 +399,12 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
reg += 4;
}
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(pctldev->dev, "failed to enable clock for setup\n");
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
@@ -405,6 +413,10 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(drvdata->pclk);
+
+ return 0;
}
/* enable a specified pinmux by writing to registers */
@@ -412,8 +424,7 @@ static int samsung_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned selector,
unsigned group)
{
- samsung_pinmux_setup(pctldev, selector, group);
- return 0;
+ return samsung_pinmux_setup(pctldev, selector, group);
}
/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
@@ -436,6 +447,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
u32 data, width, pin_offset, mask, shift;
u32 cfg_value, cfg_reg;
unsigned long flags;
+ int ret;
drvdata = pinctrl_dev_get_drvdata(pctldev);
pin_to_reg_bank(drvdata, pin, ®_base, &pin_offset, &bank);
@@ -447,6 +459,12 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
width = type->fld_width[cfg_type];
cfg_reg = type->reg_offset[cfg_type];
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
mask = (1 << width) - 1;
@@ -466,6 +484,8 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(drvdata->pclk);
+
return 0;
}
@@ -555,11 +575,19 @@ static void samsung_gpio_set_value(struct gpio_chip *gc,
static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
{
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
+ struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
unsigned long flags;
+ if (clk_enable(drvdata->pclk)) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
samsung_gpio_set_value(gc, offset, value);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(drvdata->pclk);
}
/* gpiolib gpio_get callback function */
@@ -569,12 +597,23 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
u32 data;
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
const struct samsung_pin_bank_type *type = bank->type;
+ struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
+ int ret;
reg = bank->pctl_base + bank->pctl_offset;
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
data >>= offset;
data &= 1;
+
+ clk_disable(drvdata->pclk);
+
return data;
}
@@ -591,9 +630,11 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
struct samsung_pin_bank *bank;
void __iomem *reg;
u32 data, mask, shift;
+ struct samsung_pinctrl_drv_data *drvdata;
bank = gpiochip_get_data(gc);
type = bank->type;
+ drvdata = bank->drvdata;
reg = bank->pctl_base + bank->pctl_offset
+ type->reg_offset[PINCFG_TYPE_FUNC];
@@ -619,12 +660,22 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
{
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
+ struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
unsigned long flags;
int ret;
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
ret = samsung_gpio_set_direction(gc, offset, true);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(drvdata->pclk);
+
return ret;
}
@@ -633,14 +684,23 @@ static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
+ struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
unsigned long flags;
int ret;
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
samsung_gpio_set_value(gc, offset, value);
ret = samsung_gpio_set_direction(gc, offset, false);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(drvdata->pclk);
+
return ret;
}
@@ -1164,6 +1224,12 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
}
}
+ drvdata->pclk = devm_clk_get_optional_prepared(dev, "pclk");
+ if (IS_ERR(drvdata->pclk)) {
+ ret = PTR_ERR(drvdata->pclk);
+ goto err_put_banks;
+ }
+
ret = samsung_pinctrl_register(pdev, drvdata);
if (ret)
goto err_put_banks;
@@ -1202,6 +1268,13 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
int i;
+ i = clk_enable(drvdata->pclk);
+ if (i) {
+ dev_err(drvdata->dev,
+ "failed to enable clock for saving state\n");
+ return i;
+ }
+
for (i = 0; i < drvdata->nr_banks; i++) {
struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
const void __iomem *reg = bank->pctl_base + bank->pctl_offset;
@@ -1231,6 +1304,8 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
}
}
+ clk_disable(drvdata->pclk);
+
if (drvdata->suspend)
drvdata->suspend(drvdata);
if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable)
@@ -1250,8 +1325,20 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
{
struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
+ int ret;
int i;
+ /*
+ * enable clock before the callback, as we don't want to have to deal
+ * with callback cleanup on clock failures.
+ */
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev,
+ "failed to enable clock for restoring state\n");
+ return ret;
+ }
+
if (drvdata->resume)
drvdata->resume(drvdata);
@@ -1286,6 +1373,8 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
writel(bank->pm_save[type], reg + offs[type]);
}
+ clk_disable(drvdata->pclk);
+
if (drvdata->retention_ctrl && drvdata->retention_ctrl->disable)
drvdata->retention_ctrl->disable(drvdata);
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index ab791afaabf5..d50ba6f07d5d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -274,6 +274,7 @@ struct samsung_pin_ctrl {
* through samsung_pinctrl_drv_data, not samsung_pin_bank).
* @dev: device instance representing the controller.
* @irq: interrpt number used by the controller to notify gpio interrupts.
+ * @pclk: optional bus clock if required for accessing registers
* @ctrl: pin controller instance managed by the driver.
* @pctl: pin controller descriptor registered with the pinctrl subsystem.
* @pctl_dev: cookie representing pinctrl device instance.
@@ -293,6 +294,7 @@ struct samsung_pinctrl_drv_data {
void __iomem *virt_base;
struct device *dev;
int irq;
+ struct clk *pclk;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
--
2.44.0.769.g3c40516874-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 9%]
* [PATCH v4 3/3] spi: airoha: add SPI-NAND Flash controller driver
@ 2024-04-26 8:30 2% ` Lorenzo Bianconi
0 siblings, 0 replies; 200+ results
From: Lorenzo Bianconi @ 2024-04-26 8:30 UTC (permalink / raw)
To: linux-spi
Cc: conor, broonie, lorenzo.bianconi83, linux-arm-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, nbd, john, dd,
catalin.marinas, will, upstream, angelogioacchino.delregno,
andy.shevchenko
Introduce support for SPI-NAND driver of the Airoha NAND Flash Interface
found on Airoha ARM SoCs.
Tested-by: Rajeev Kumar <Rajeev.Kumar@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
MAINTAINERS | 9 +
drivers/spi/Kconfig | 10 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-airoha-snfi.c | 1140 +++++++++++++++++++++++++++++++++
4 files changed, 1160 insertions(+)
create mode 100644 drivers/spi/spi-airoha-snfi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index aa3b947fb080..ce9fac46f741 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -653,6 +653,15 @@ S: Supported
F: fs/aio.c
F: include/linux/*aio*.h
+AIROHA SPI SNFI DRIVER
+M: Lorenzo Bianconi <lorenzo@kernel.org>
+M: Ray Liu <ray.liu@airoha.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-spi@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/spi/airoha,en7581-snand.yaml
+F: drivers/spi/spi-airoha.c
+
AIRSPY MEDIA DRIVER
L: linux-media@vger.kernel.org
S: Orphan
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bc7021da2fe9..6fa91775f334 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -57,6 +57,16 @@ config SPI_MEM
comment "SPI Master Controller Drivers"
+config SPI_AIROHA_SNFI
+ tristate "Airoha SPI NAND Flash Interface"
+ depends on ARCH_AIROHA || COMPILE_TEST
+ depends on SPI_MASTER
+ select REGMAP_MMIO
+ help
+ This enables support for SPI-NAND mode on the Airoha NAND
+ Flash Interface found on Airoha ARM SoCs. This controller
+ is implemented as a SPI-MEM controller.
+
config SPI_ALTERA
tristate "Altera SPI Controller platform driver"
select SPI_ALTERA_CORE
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4ff8d725ba5e..e694254dec04 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_SPIDEV) += spidev.o
obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
# SPI master controller drivers (bus)
+obj-$(CONFIG_SPI_AIROHA_SNFI) += spi-airoha-snfi.o
obj-$(CONFIG_SPI_ALTERA) += spi-altera-platform.o
obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o
obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o
diff --git a/drivers/spi/spi-airoha-snfi.c b/drivers/spi/spi-airoha-snfi.c
new file mode 100644
index 000000000000..bb4360a2ca30
--- /dev/null
+++ b/drivers/spi/spi-airoha-snfi.c
@@ -0,0 +1,1140 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Ray Liu <ray.liu@airoha.com>
+ */
+
+#include <asm-generic/unaligned.h>
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/types.h>
+#include <linux/math.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/sizes.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+/* SPI */
+#define REG_SPI_CTRL_BASE 0x1FA10000
+
+#define REG_SPI_CTRL_READ_MODE 0x0000
+#define REG_SPI_CTRL_READ_IDLE_EN 0x0004
+#define REG_SPI_CTRL_SIDLY 0x0008
+#define REG_SPI_CTRL_CSHEXT 0x000c
+#define REG_SPI_CTRL_CSLEXT 0x0010
+
+#define REG_SPI_CTRL_MTX_MODE_TOG 0x0014
+#define SPI_CTRL_MTX_MODE_TOG GENMASK(3, 0)
+
+#define REG_SPI_CTRL_RDCTL_FSM 0x0018
+#define SPI_CTRL_RDCTL_FSM GENMASK(3, 0)
+
+#define REG_SPI_CTRL_MACMUX_SEL 0x001c
+
+#define REG_SPI_CTRL_MANUAL_EN 0x0020
+#define SPI_CTRL_MANUAL_EN BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_EMPTY 0x0024
+#define SPI_CTRL_OPFIFO_EMPTY BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_WDATA 0x0028
+#define SPI_CTRL_OPFIFO_LEN GENMASK(8, 0)
+#define SPI_CTRL_OPFIFO_OP GENMASK(13, 9)
+
+#define REG_SPI_CTRL_OPFIFO_FULL 0x002c
+#define SPI_CTRL_OPFIFO_FULL BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_WR 0x0030
+#define SPI_CTRL_OPFIFO_WR BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_FULL 0x0034
+#define SPI_CTRL_DFIFO_FULL BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_WDATA 0x0038
+#define SPI_CTRL_DFIFO_WDATA GENMASK(7, 0)
+
+#define REG_SPI_CTRL_DFIFO_EMPTY 0x003c
+#define SPI_CTRL_DFIFO_EMPTY BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_RD 0x0040
+#define SPI_CTRL_DFIFO_RD BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_RDATA 0x0044
+#define SPI_CTRL_DFIFO_RDATA GENMASK(7, 0)
+
+#define REG_SPI_CTRL_DUMMY 0x0080
+#define SPI_CTRL_CTRL_DUMMY GENMASK(3, 0)
+
+#define REG_SPI_CTRL_PROBE_SEL 0x0088
+#define REG_SPI_CTRL_INTERRUPT 0x0090
+#define REG_SPI_CTRL_INTERRUPT_EN 0x0094
+#define REG_SPI_CTRL_SI_CK_SEL 0x009c
+#define REG_SPI_CTRL_SW_CFGNANDADDR_VAL 0x010c
+#define REG_SPI_CTRL_SW_CFGNANDADDR_EN 0x0110
+#define REG_SPI_CTRL_SFC_STRAP 0x0114
+
+#define REG_SPI_CTRL_NFI2SPI_EN 0x0130
+#define SPI_CTRL_NFI2SPI_EN BIT(0)
+
+/* NFI2SPI */
+#define REG_SPI_NFI_CNFG 0x0000
+#define SPI_NFI_DMA_MODE BIT(0)
+#define SPI_NFI_READ_MODE BIT(1)
+#define SPI_NFI_DMA_BURST_EN BIT(2)
+#define SPI_NFI_HW_ECC_EN BIT(8)
+#define SPI_NFI_AUTO_FDM_EN BIT(9)
+#define SPI_NFI_OPMODE GENMASK(14, 12)
+
+#define REG_SPI_NFI_PAGEFMT 0x0004
+#define SPI_NFI_PAGE_SIZE GENMASK(1, 0)
+#define SPI_NFI_SPARE_SIZE GENMASK(5, 4)
+
+#define REG_SPI_NFI_CON 0x0008
+#define SPI_NFI_FIFO_FLUSH BIT(0)
+#define SPI_NFI_RST BIT(1)
+#define SPI_NFI_RD_TRIG BIT(8)
+#define SPI_NFI_WR_TRIG BIT(9)
+#define SPI_NFI_SEC_NUM GENMASK(15, 12)
+
+#define REG_SPI_NFI_INTR_EN 0x0010
+#define SPI_NFI_RD_DONE_EN BIT(0)
+#define SPI_NFI_WR_DONE_EN BIT(1)
+#define SPI_NFI_RST_DONE_EN BIT(2)
+#define SPI_NFI_ERASE_DONE_EN BIT(3)
+#define SPI_NFI_BUSY_RETURN_EN BIT(4)
+#define SPI_NFI_ACCESS_LOCK_EN BIT(5)
+#define SPI_NFI_AHB_DONE_EN BIT(6)
+#define SPI_NFI_ALL_IRQ_EN \
+ (SPI_NFI_RD_DONE_EN | SPI_NFI_WR_DONE_EN | \
+ SPI_NFI_RST_DONE_EN | SPI_NFI_ERASE_DONE_EN | \
+ SPI_NFI_BUSY_RETURN_EN | SPI_NFI_ACCESS_LOCK_EN | \
+ SPI_NFI_AHB_DONE_EN)
+
+#define REG_SPI_NFI_INTR 0x0014
+#define SPI_NFI_AHB_DONE BIT(6)
+
+#define REG_SPI_NFI_CMD 0x0020
+
+#define REG_SPI_NFI_ADDR_NOB 0x0030
+#define SPI_NFI_ROW_ADDR_NOB GENMASK(6, 4)
+
+#define REG_SPI_NFI_STA 0x0060
+#define REG_SPI_NFI_FIFOSTA 0x0064
+#define REG_SPI_NFI_STRADDR 0x0080
+#define REG_SPI_NFI_FDM0L 0x00a0
+#define REG_SPI_NFI_FDM0M 0x00a4
+#define REG_SPI_NFI_FDM7L 0x00d8
+#define REG_SPI_NFI_FDM7M 0x00dc
+#define REG_SPI_NFI_FIFODATA0 0x0190
+#define REG_SPI_NFI_FIFODATA1 0x0194
+#define REG_SPI_NFI_FIFODATA2 0x0198
+#define REG_SPI_NFI_FIFODATA3 0x019c
+#define REG_SPI_NFI_MASTERSTA 0x0224
+
+#define REG_SPI_NFI_SECCUS_SIZE 0x022c
+#define SPI_NFI_CUS_SEC_SIZE GENMASK(12, 0)
+#define SPI_NFI_CUS_SEC_SIZE_EN BIT(16)
+
+#define REG_SPI_NFI_RD_CTL2 0x0510
+#define REG_SPI_NFI_RD_CTL3 0x0514
+
+#define REG_SPI_NFI_PG_CTL1 0x0524
+#define SPI_NFI_PG_LOAD_CMD GENMASK(15, 8)
+
+#define REG_SPI_NFI_PG_CTL2 0x0528
+#define REG_SPI_NFI_NOR_PROG_ADDR 0x052c
+#define REG_SPI_NFI_NOR_RD_ADDR 0x0534
+
+#define REG_SPI_NFI_SNF_MISC_CTL 0x0538
+#define SPI_NFI_DATA_READ_WR_MODE GENMASK(18, 16)
+
+#define REG_SPI_NFI_SNF_MISC_CTL2 0x053c
+#define SPI_NFI_READ_DATA_BYTE_NUM GENMASK(12, 0)
+#define SPI_NFI_PROG_LOAD_BYTE_NUM GENMASK(28, 16)
+
+#define REG_SPI_NFI_SNF_STA_CTL1 0x0550
+#define SPI_NFI_READ_FROM_CACHE_DONE BIT(25)
+#define SPI_NFI_LOAD_TO_CACHE_DONE BIT(26)
+
+#define REG_SPI_NFI_SNF_STA_CTL2 0x0554
+
+#define REG_SPI_NFI_SNF_NFI_CNFG 0x055c
+#define SPI_NFI_SPI_MODE BIT(0)
+
+/* SPI NAND Protocol OP */
+#define SPI_NAND_OP_GET_FEATURE 0x0f
+#define SPI_NAND_OP_SET_FEATURE 0x1f
+#define SPI_NAND_OP_PAGE_READ 0x13
+#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE 0x03
+#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST 0x0b
+#define SPI_NAND_OP_READ_FROM_CACHE_DUAL 0x3b
+#define SPI_NAND_OP_READ_FROM_CACHE_QUAD 0x6b
+#define SPI_NAND_OP_WRITE_ENABLE 0x06
+#define SPI_NAND_OP_WRITE_DISABLE 0x04
+#define SPI_NAND_OP_PROGRAM_LOAD_SINGLE 0x02
+#define SPI_NAND_OP_PROGRAM_LOAD_QUAD 0x32
+#define SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE 0x84
+#define SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD 0x34
+#define SPI_NAND_OP_PROGRAM_EXECUTE 0x10
+#define SPI_NAND_OP_READ_ID 0x9f
+#define SPI_NAND_OP_BLOCK_ERASE 0xd8
+#define SPI_NAND_OP_RESET 0xff
+#define SPI_NAND_OP_DIE_SELECT 0xc2
+
+#define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256)
+#define SPI_MAX_TRANSFER_SIZE 511
+
+enum airoha_snand_mode {
+ SPI_MODE_AUTO,
+ SPI_MODE_MANUAL,
+ SPI_MODE_DMA,
+};
+
+enum airoha_snand_cs {
+ SPI_CHIP_SEL_HIGH,
+ SPI_CHIP_SEL_LOW,
+};
+
+struct airoha_snand_dev {
+ size_t buf_len;
+
+ u8 *txrx_buf;
+ dma_addr_t dma_addr;
+
+ u64 cur_page_num;
+ bool data_need_update;
+};
+
+struct airoha_snand_ctrl {
+ struct device *dev;
+ struct regmap *regmap_ctrl;
+ struct regmap *regmap_nfi;
+ struct clk *spi_clk;
+
+ struct {
+ size_t page_size;
+ size_t sec_size;
+ u8 sec_num;
+ u8 spare_size;
+ } nfi_cfg;
+};
+
+static int airoha_snand_set_fifo_op(struct airoha_snand_ctrl *as_ctrl,
+ u8 op_cmd, int op_len)
+{
+ int err;
+ u32 val;
+
+ err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WDATA,
+ FIELD_PREP(SPI_CTRL_OPFIFO_LEN, op_len) |
+ FIELD_PREP(SPI_CTRL_OPFIFO_OP, op_cmd));
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_OPFIFO_FULL,
+ val, !(val & SPI_CTRL_OPFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WR,
+ SPI_CTRL_OPFIFO_WR);
+ if (err)
+ return err;
+
+ return regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_OPFIFO_EMPTY,
+ val, (val & SPI_CTRL_OPFIFO_EMPTY),
+ 0, 250 * USEC_PER_MSEC);
+}
+
+static int airoha_snand_set_cs(struct airoha_snand_ctrl *as_ctrl, u8 cs)
+{
+ return airoha_snand_set_fifo_op(as_ctrl, cs, sizeof(cs));
+}
+
+static int airoha_snand_write_data_to_fifo(struct airoha_snand_ctrl *as_ctrl,
+ const u8 *data, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ int err;
+ u32 val;
+
+ /* 1. Wait until dfifo is not full */
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_FULL, val,
+ !(val & SPI_CTRL_DFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ /* 2. Write data to register DFIFO_WDATA */
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_WDATA,
+ FIELD_PREP(SPI_CTRL_DFIFO_WDATA, data[i]));
+ if (err)
+ return err;
+
+ /* 3. Wait until dfifo is not full */
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_FULL, val,
+ !(val & SPI_CTRL_DFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_read_data_from_fifo(struct airoha_snand_ctrl *as_ctrl,
+ u8 *ptr, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ int err;
+ u32 val;
+
+ /* 1. wait until dfifo is not empty */
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_EMPTY, val,
+ !(val & SPI_CTRL_DFIFO_EMPTY),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ /* 2. read from dfifo to register DFIFO_RDATA */
+ err = regmap_read(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_RDATA, &val);
+ if (err)
+ return err;
+
+ ptr[i] = FIELD_GET(SPI_CTRL_DFIFO_RDATA, val);
+ /* 3. enable register DFIFO_RD to read next byte */
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_RD, SPI_CTRL_DFIFO_RD);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_set_mode(struct airoha_snand_ctrl *as_ctrl,
+ enum airoha_snand_mode mode)
+{
+ int err;
+
+ switch (mode) {
+ case SPI_MODE_MANUAL: {
+ u32 val;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_NFI2SPI_EN, 0);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_READ_IDLE_EN, 0);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_RDCTL_FSM, val,
+ !(val & SPI_CTRL_RDCTL_FSM),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MTX_MODE_TOG, 9);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MANUAL_EN, SPI_CTRL_MANUAL_EN);
+ if (err)
+ return err;
+ break;
+ }
+ case SPI_MODE_DMA:
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_NFI2SPI_EN,
+ SPI_CTRL_MANUAL_EN);
+ if (err < 0)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MTX_MODE_TOG, 0x0);
+ if (err < 0)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MANUAL_EN, 0x0);
+ if (err < 0)
+ return err;
+ break;
+ case SPI_MODE_AUTO:
+ default:
+ break;
+ }
+
+ return regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
+}
+
+static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd,
+ const u8 *data, int len)
+{
+ int i, data_len;
+
+ for (i = 0; i < len; i += data_len) {
+ int err;
+
+ data_len = min(len, SPI_MAX_TRANSFER_SIZE);
+ err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
+ if (err)
+ return err;
+
+ err = airoha_snand_write_data_to_fifo(as_ctrl, &data[i],
+ data_len);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data,
+ int len)
+{
+ int i, data_len;
+
+ for (i = 0; i < len; i += data_len) {
+ int err;
+
+ data_len = min(len, SPI_MAX_TRANSFER_SIZE);
+ err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len);
+ if (err)
+ return err;
+
+ err = airoha_snand_read_data_from_fifo(as_ctrl, &data[i],
+ data_len);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_nfi_init(struct airoha_snand_ctrl *as_ctrl)
+{
+ int err;
+
+ /* switch to SNFI mode */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_NFI_CNFG,
+ SPI_NFI_SPI_MODE);
+ if (err)
+ return err;
+
+ /* Enable DMA */
+ return regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR_EN,
+ SPI_NFI_ALL_IRQ_EN, SPI_NFI_AHB_DONE_EN);
+}
+
+static int airoha_snand_nfi_config(struct airoha_snand_ctrl *as_ctrl)
+{
+ int err;
+ u32 val;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
+ if (err)
+ return err;
+
+ /* auto FDM */
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_AUTO_FDM_EN);
+ if (err)
+ return err;
+
+ /* HW ECC */
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_HW_ECC_EN);
+ if (err)
+ return err;
+
+ /* DMA Burst */
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_DMA_BURST_EN);
+ if (err)
+ return err;
+
+ /* page format */
+ switch (as_ctrl->nfi_cfg.spare_size) {
+ case 26:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1);
+ break;
+ case 27:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x2);
+ break;
+ case 28:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x3);
+ break;
+ default:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x0);
+ break;
+ }
+
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
+ SPI_NFI_SPARE_SIZE, val);
+ if (err)
+ return err;
+
+ switch (as_ctrl->nfi_cfg.page_size) {
+ case 2048:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1);
+ break;
+ case 4096:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x2);
+ break;
+ default:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x0);
+ break;
+ }
+
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
+ SPI_NFI_PAGE_SIZE, val);
+ if (err)
+ return err;
+
+ /* sec num */
+ val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_SEC_NUM, val);
+ if (err)
+ return err;
+
+ /* enable cust sec size */
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
+ SPI_NFI_CUS_SEC_SIZE_EN);
+ if (err)
+ return err;
+
+ /* set cust sec size */
+ val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, as_ctrl->nfi_cfg.sec_size);
+ return regmap_update_bits(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SECCUS_SIZE,
+ SPI_NFI_CUS_SEC_SIZE, val);
+}
+
+static bool airoha_snand_is_page_ops(const struct spi_mem_op *op)
+{
+ if (op->addr.nbytes != 2)
+ return false;
+
+ if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
+ op->addr.buswidth != 4)
+ return false;
+
+ switch (op->data.dir) {
+ case SPI_MEM_DATA_IN:
+ /* check dummy cycle first */
+ if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > 0xf)
+ return false;
+
+ /* quad io / quad out */
+ if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) &&
+ op->data.buswidth == 4)
+ return true;
+
+ /* dual io / dual out */
+ if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) &&
+ op->data.buswidth == 2)
+ return true;
+
+ /* standard spi */
+ if (op->addr.buswidth == 1 && op->data.buswidth == 1)
+ return true;
+ break;
+ case SPI_MEM_DATA_OUT:
+ /* check dummy cycle first */
+ if (op->dummy.nbytes)
+ return false;
+
+ /* program load quad out */
+ if (op->addr.buswidth == 1 && op->data.buswidth == 4)
+ return true;
+
+ /* standard spi */
+ if (op->addr.buswidth == 1 && op->data.buswidth == 1)
+ return true;
+ default:
+ break;
+ }
+
+ return false;
+}
+
+static int airoha_snand_adjust_op_size(struct spi_mem *mem,
+ struct spi_mem_op *op)
+{
+ struct airoha_snand_ctrl *as_ctrl;
+ size_t len;
+
+ as_ctrl = spi_controller_get_devdata(mem->spi->controller);
+ if (airoha_snand_is_page_ops(op)) {
+ len = as_ctrl->nfi_cfg.sec_size;
+ len += as_ctrl->nfi_cfg.spare_size;
+ len *= as_ctrl->nfi_cfg.sec_num;
+ op->data.nbytes = min_t(size_t, op->data.nbytes, len);
+ } else {
+ len = 1 + op->addr.nbytes + op->dummy.nbytes;
+ if (len >= 160)
+ return -EOPNOTSUPP;
+
+ op->data.nbytes = min_t(size_t, op->data.nbytes, 160 - len);
+ }
+
+ return 0;
+}
+
+static bool airoha_snand_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ if (!spi_mem_default_supports_op(mem, op))
+ return false;
+
+ if (op->cmd.buswidth != 1)
+ return false;
+
+ if (airoha_snand_is_page_ops(op))
+ return true;
+
+ return (!op->addr.nbytes || op->addr.buswidth == 1) &&
+ (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
+ (!op->data.nbytes || op->data.buswidth == 1);
+}
+
+static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(desc->mem->spi);
+
+ if (!as_dev->txrx_buf)
+ return -EINVAL;
+
+ if (desc->info.offset + desc->info.length > U32_MAX)
+ return -EINVAL;
+
+ if (!airoha_snand_supports_op(desc->mem, &desc->info.op_tmpl))
+ return -EOPNOTSUPP;
+
+ return 0;
+}
+
+static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, void *buf)
+{
+ struct spi_device *spi = desc->mem->spi;
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ struct spi_mem_op *op = &desc->info.op_tmpl;
+ struct airoha_snand_ctrl *as_ctrl;
+ u32 val, rd_mode;
+ int err;
+
+ if (!as_dev->data_need_update)
+ return len;
+
+ as_dev->data_need_update = false;
+
+ switch (op->cmd.opcode) {
+ case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
+ rd_mode = 1;
+ break;
+ case SPI_NAND_OP_READ_FROM_CACHE_QUAD:
+ rd_mode = 2;
+ break;
+ default:
+ rd_mode = 0;
+ break;
+ }
+
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_nfi_config(as_ctrl);
+ if (err)
+ return err;
+
+ dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+
+ /* set dma addr */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
+ as_dev->dma_addr);
+ if (err)
+ return err;
+
+ /* set cust sec size */
+ val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
+ val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
+ err = regmap_update_bits(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_MISC_CTL2,
+ SPI_NFI_READ_DATA_BYTE_NUM, val);
+ if (err)
+ return err;
+
+ /* set read command */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL2,
+ op->cmd.opcode);
+ if (err)
+ return err;
+
+ /* set read mode */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
+ FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, rd_mode));
+ if (err)
+ return err;
+
+ /* set read addr */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 0x0);
+ if (err)
+ return err;
+
+ /* set nfi read */
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_OPMODE,
+ FIELD_PREP(SPI_NFI_OPMODE, 6));
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
+ if (err)
+ return err;
+
+ /* trigger dma start read */
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_RD_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_RD_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_STA_CTL1, val,
+ (val & SPI_NFI_READ_FROM_CACHE_DONE),
+ 0, USEC_PER_SEC);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
+ SPI_NFI_READ_FROM_CACHE_DONE);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
+ val, (val & SPI_NFI_AHB_DONE), 0,
+ USEC_PER_SEC);
+ if (err)
+ return err;
+
+ /* DMA read need delay for data ready from controller to DRAM */
+ udelay(1);
+
+ dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ memcpy(buf, as_dev->txrx_buf + offs, len);
+
+ return len;
+}
+
+static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, const void *buf)
+{
+ struct spi_device *spi = desc->mem->spi;
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ struct spi_mem_op *op = &desc->info.op_tmpl;
+ struct airoha_snand_ctrl *as_ctrl;
+ u32 wr_mode, val;
+ int err;
+
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ memcpy(as_dev->txrx_buf + offs, buf, len);
+ dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_nfi_config(as_ctrl);
+ if (err)
+ return err;
+
+ if (op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_QUAD ||
+ op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD)
+ wr_mode = BIT(1);
+ else
+ wr_mode = 0;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
+ as_dev->dma_addr);
+ if (err)
+ return err;
+
+ val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM,
+ as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num);
+ err = regmap_update_bits(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_MISC_CTL2,
+ SPI_NFI_PROG_LOAD_BYTE_NUM, val);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL1,
+ FIELD_PREP(SPI_NFI_PG_LOAD_CMD,
+ op->cmd.opcode));
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
+ FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, wr_mode));
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 0x0);
+ if (err)
+ return err;
+
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_READ_MODE);
+ if (err)
+ return err;
+
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_OPMODE,
+ FIELD_PREP(SPI_NFI_OPMODE, 3));
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_DMA_MODE);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
+ if (err)
+ return err;
+
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_WR_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_WR_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
+ val, (val & SPI_NFI_AHB_DONE), 0,
+ USEC_PER_SEC);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_STA_CTL1, val,
+ (val & SPI_NFI_LOAD_TO_CACHE_DONE),
+ 0, USEC_PER_SEC);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
+ SPI_NFI_LOAD_TO_CACHE_DONE);
+ if (err)
+ return err;
+
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ return len;
+}
+
+static int airoha_snand_exec_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(mem->spi);
+ u8 data[8], cmd, opcode = op->cmd.opcode;
+ struct airoha_snand_ctrl *as_ctrl;
+ int i, err;
+
+ as_ctrl = spi_controller_get_devdata(mem->spi->controller);
+ if (opcode == SPI_NAND_OP_PROGRAM_EXECUTE &&
+ op->addr.val == as_dev->cur_page_num) {
+ as_dev->data_need_update = true;
+ } else if (opcode == SPI_NAND_OP_PAGE_READ) {
+ if (!as_dev->data_need_update &&
+ op->addr.val == as_dev->cur_page_num)
+ return 0;
+
+ as_dev->data_need_update = true;
+ as_dev->cur_page_num = op->addr.val;
+ }
+
+ /* switch to manual mode */
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_LOW);
+ if (err < 0)
+ return err;
+
+ /* opcode */
+ err = airoha_snand_write_data(as_ctrl, 0x8, &opcode, sizeof(opcode));
+ if (err)
+ return err;
+
+ /* addr part */
+ cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
+ put_unaligned_be64(op->addr.val, data);
+
+ for (i = 0; i < op->addr.nbytes; i++) {
+ err = airoha_snand_write_data(as_ctrl, cmd,
+ &data[8 - op->addr.nbytes + i],
+ sizeof(data[0]));
+ if (err)
+ return err;
+ }
+
+ /* dummy */
+ data[0] = 0xff;
+ for (i = 0; i < op->dummy.nbytes; i++) {
+ err = airoha_snand_write_data(as_ctrl, 0x8, &data[0],
+ sizeof(data[0]));
+ if (err)
+ return err;
+ }
+
+ /* data */
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ err = airoha_snand_read_data(as_ctrl, op->data.buf.in,
+ op->data.nbytes);
+ if (err)
+ return err;
+ } else {
+ err = airoha_snand_write_data(as_ctrl, 0x8, op->data.buf.out,
+ op->data.nbytes);
+ if (err)
+ return err;
+ }
+
+ return airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_HIGH);
+}
+
+static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
+ .adjust_op_size = airoha_snand_adjust_op_size,
+ .supports_op = airoha_snand_supports_op,
+ .exec_op = airoha_snand_exec_op,
+ .dirmap_create = airoha_snand_dirmap_create,
+ .dirmap_read = airoha_snand_dirmap_read,
+ .dirmap_write = airoha_snand_dirmap_write,
+};
+
+static int airoha_snand_setup(struct spi_device *spi)
+{
+ struct airoha_snand_ctrl *as_ctrl;
+ struct airoha_snand_dev *as_dev;
+
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+
+ as_dev = devm_kzalloc(as_ctrl->dev, sizeof(*as_dev), GFP_KERNEL);
+ if (!as_dev)
+ return -ENOMEM;
+
+ /* prepare device buffer */
+ as_dev->buf_len = SPI_NAND_CACHE_SIZE;
+ as_dev->txrx_buf = devm_kzalloc(as_ctrl->dev, as_dev->buf_len,
+ GFP_KERNEL);
+ if (!as_dev->txrx_buf)
+ return -ENOMEM;
+
+ as_dev->dma_addr = dma_map_single(as_ctrl->dev, as_dev->txrx_buf,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ if (dma_mapping_error(as_ctrl->dev, as_dev->dma_addr))
+ return -ENOMEM;
+
+ as_dev->data_need_update = true;
+ spi_set_ctldata(spi, as_dev);
+
+ return 0;
+}
+
+static void airoha_snand_cleanup(struct spi_device *spi)
+{
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ struct airoha_snand_ctrl *as_ctrl;
+
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+ dma_unmap_single(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ devm_kfree(as_ctrl->dev, as_dev->txrx_buf);
+ devm_kfree(as_ctrl->dev, as_dev);
+
+ spi_set_ctldata(spi, NULL);
+}
+
+static int airoha_snand_nfi_setup(struct airoha_snand_ctrl *as_ctrl)
+{
+ u32 val, sec_size, sec_num;
+ int err;
+
+ err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, &val);
+ if (err)
+ return err;
+
+ sec_num = FIELD_GET(SPI_NFI_SEC_NUM, val);
+
+ err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE, &val);
+ if (err)
+ return err;
+
+ sec_size = FIELD_GET(SPI_NFI_CUS_SEC_SIZE, val);
+
+ /* init default value */
+ as_ctrl->nfi_cfg.sec_size = sec_size;
+ as_ctrl->nfi_cfg.sec_num = sec_num;
+ as_ctrl->nfi_cfg.page_size = round_down(sec_size * sec_num, 1024);
+ as_ctrl->nfi_cfg.spare_size = 16;
+
+ err = airoha_snand_nfi_init(as_ctrl);
+ if (err)
+ return err;
+
+ return airoha_snand_nfi_config(as_ctrl);
+}
+
+static const struct regmap_config spi_ctrl_regmap_config = {
+ .name = "ctrl",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = REG_SPI_CTRL_NFI2SPI_EN,
+};
+
+static const struct regmap_config spi_nfi_regmap_config = {
+ .name = "nfi",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = REG_SPI_NFI_SNF_NFI_CNFG,
+};
+
+static const struct of_device_id airoha_snand_ids[] = {
+ { .compatible = "airoha,en7581-snand" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_snand_ids);
+
+static int airoha_snand_probe(struct platform_device *pdev)
+{
+ struct airoha_snand_ctrl *as_ctrl;
+ struct device *dev = &pdev->dev;
+ struct spi_controller *ctrl;
+ struct resource *res;
+ void __iomem *base;
+ int err;
+
+ ctrl = devm_spi_alloc_host(dev, sizeof(*as_ctrl));
+ if (!ctrl)
+ return -ENOMEM;
+
+ as_ctrl = spi_controller_get_devdata(ctrl);
+ as_ctrl->dev = dev;
+
+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ as_ctrl->regmap_ctrl = devm_regmap_init_mmio(dev, base,
+ &spi_ctrl_regmap_config);
+ if (IS_ERR(as_ctrl->regmap_ctrl))
+ return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_ctrl),
+ "failed to init spi ctrl regmap\n");
+
+ base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ as_ctrl->regmap_nfi = devm_regmap_init_mmio(dev, base,
+ &spi_nfi_regmap_config);
+ if (IS_ERR(as_ctrl->regmap_nfi))
+ return dev_err_probe(dev, PTR_ERR(as_ctrl->regmap_nfi),
+ "failed to init spi nfi regmap\n");
+
+ as_ctrl->spi_clk = devm_clk_get_enabled(dev, "spi");
+ if (IS_ERR(as_ctrl->spi_clk))
+ return dev_err_probe(dev, PTR_ERR(as_ctrl->spi_clk),
+ "unable to get spi clk\n");
+
+ err = dma_set_mask(as_ctrl->dev, DMA_BIT_MASK(32));
+ if (err)
+ return err;
+
+ ctrl->num_chipselect = 2;
+ ctrl->mem_ops = &airoha_snand_mem_ops;
+ ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
+ ctrl->mode_bits = SPI_RX_DUAL;
+ ctrl->dev.of_node = dev->of_node;
+ ctrl->setup = airoha_snand_setup;
+ ctrl->cleanup = airoha_snand_cleanup;
+
+ err = airoha_snand_nfi_setup(as_ctrl);
+ if (err)
+ return err;
+
+ return devm_spi_register_controller(dev, ctrl);
+}
+
+static struct platform_driver airoha_snand_driver = {
+ .driver = {
+ .name = "airoha-spi",
+ .of_match_table = airoha_snand_ids,
+ },
+ .probe = airoha_snand_probe,
+};
+module_platform_driver(airoha_snand_driver);
+
+MODULE_DESCRIPTION("Airoha SPI-NAND Flash Controller Driver");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Ray Liu <ray.liu@airoha.com>");
+MODULE_LICENSE("GPL");
--
2.44.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 2%]
* [PATCH v6 08/16] mm/execmem, arch: convert remaining overrides of module_alloc to execmem
@ 2024-04-26 8:28 6% ` Mike Rapoport
0 siblings, 0 replies; 200+ results
From: Mike Rapoport @ 2024-04-26 8:28 UTC (permalink / raw)
To: linux-kernel
Cc: Alexandre Ghiti, Andrew Morton, Björn Töpel,
Catalin Marinas, Christophe Leroy, David S. Miller, Dinh Nguyen,
Donald Dutile, Eric Chanudet, Heiko Carstens, Helge Deller,
Huacai Chen, Kent Overstreet, Luis Chamberlain, Mark Rutland,
Masami Hiramatsu, Michael Ellerman, Mike Rapoport, Nadav Amit,
Palmer Dabbelt, Peter Zijlstra, Rick Edgecombe, Russell King,
Sam Ravnborg, Song Liu, Steven Rostedt, Thomas Bogendoerfer,
Thomas Gleixner, Will Deacon, bpf, linux-arch, linux-arm-kernel,
linux-mips, linux-mm, linux-modules, linux-parisc, linux-riscv,
linux-s390, linux-trace-kernel, linuxppc-dev, loongarch, netdev,
sparclinux, x86
From: "Mike Rapoport (IBM)" <rppt@kernel.org>
Extend execmem parameters to accommodate more complex overrides of
module_alloc() by architectures.
This includes specification of a fallback range required by arm, arm64
and powerpc, EXECMEM_MODULE_DATA type required by powerpc, support for
allocation of KASAN shadow required by s390 and x86 and support for
late initialization of execmem required by arm64.
The core implementation of execmem_alloc() takes care of suppressing
warnings when the initial allocation fails but there is a fallback range
defined.
Signed-off-by: Mike Rapoport (IBM) <rppt@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
---
arch/Kconfig | 8 ++++
arch/arm/kernel/module.c | 41 ++++++++++++--------
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/module.c | 55 ++++++++++++++------------
arch/powerpc/kernel/module.c | 60 +++++++++++++++++++----------
arch/s390/kernel/module.c | 54 +++++++++++---------------
arch/x86/kernel/module.c | 70 +++++++++++----------------------
include/linux/execmem.h | 30 ++++++++++++++-
include/linux/moduleloader.h | 12 ------
kernel/module/main.c | 26 +++----------
mm/execmem.c | 75 ++++++++++++++++++++++++++++++------
11 files changed, 247 insertions(+), 185 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index 65afb1de48b3..4fd0daa54e6c 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -960,6 +960,14 @@ config ARCH_WANTS_MODULES_DATA_IN_VMALLOC
For architectures like powerpc/32 which have constraints on module
allocation and need to allocate module data outside of module area.
+config ARCH_WANTS_EXECMEM_LATE
+ bool
+ help
+ For architectures that do not allocate executable memory early on
+ boot, but rather require its initialization late when there is
+ enough entropy for module space randomization, for instance
+ arm64.
+
config HAVE_IRQ_EXIT_ON_IRQ_STACK
bool
help
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index e74d84f58b77..a98fdf6ff26c 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -16,6 +16,7 @@
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/gfp.h>
+#include <linux/execmem.h>
#include <asm/sections.h>
#include <asm/smp_plat.h>
@@ -34,23 +35,31 @@
#endif
#ifdef CONFIG_MMU
-void *module_alloc(unsigned long size)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- /* Silence the initial allocation */
- if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS))
- gfp_mask |= __GFP_NOWARN;
-
- p = __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
- gfp_mask, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- if (!IS_ENABLED(CONFIG_ARM_MODULE_PLTS) || p)
- return p;
- return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
+ unsigned long fallback_start = 0, fallback_end = 0;
+
+ if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS)) {
+ fallback_start = VMALLOC_START;
+ fallback_end = VMALLOC_END;
+ }
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = MODULES_VADDR,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL_EXEC,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#endif
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7b11c98b3e84..74b34a78b7ac 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -105,6 +105,7 @@ config ARM64
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
select ARCH_WANT_LD_ORPHAN_WARN
+ select ARCH_WANTS_EXECMEM_LATE if EXECMEM
select ARCH_WANTS_NO_INSTR
select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
select ARCH_HAS_UBSAN
diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c
index e92da4da1b2a..b7a7a23f9f8f 100644
--- a/arch/arm64/kernel/module.c
+++ b/arch/arm64/kernel/module.c
@@ -20,6 +20,7 @@
#include <linux/random.h>
#include <linux/scs.h>
#include <linux/vmalloc.h>
+#include <linux/execmem.h>
#include <asm/alternative.h>
#include <asm/insn.h>
@@ -108,41 +109,47 @@ static int __init module_init_limits(void)
return 0;
}
-subsys_initcall(module_init_limits);
-void *module_alloc(unsigned long size)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- void *p = NULL;
+ unsigned long fallback_start = 0, fallback_end = 0;
+ unsigned long start = 0, end = 0;
+
+ module_init_limits();
/*
* Where possible, prefer to allocate within direct branch range of the
* kernel such that no PLTs are necessary.
*/
if (module_direct_base) {
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- module_direct_base,
- module_direct_base + SZ_128M,
- GFP_KERNEL | __GFP_NOWARN,
- PAGE_KERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- }
+ start = module_direct_base;
+ end = module_direct_base + SZ_128M;
- if (!p && module_plt_base) {
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- module_plt_base,
- module_plt_base + SZ_2G,
- GFP_KERNEL | __GFP_NOWARN,
- PAGE_KERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- }
-
- if (!p) {
- pr_warn_ratelimited("%s: unable to allocate memory\n",
- __func__);
+ if (module_plt_base) {
+ fallback_start = module_plt_base;
+ fallback_end = module_plt_base + SZ_2G;
+ }
+ } else if (module_plt_base) {
+ start = module_plt_base;
+ end = module_plt_base + SZ_2G;
}
- /* Memory is intended to be executable, reset the pointer tag. */
- return kasan_reset_tag(p);
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = start,
+ .end = end,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ },
+ };
+
+ return &execmem_info;
}
enum aarch64_reloc_op {
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index f6d6ae0a1692..ac80559015a3 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -10,6 +10,7 @@
#include <linux/vmalloc.h>
#include <linux/mm.h>
#include <linux/bug.h>
+#include <linux/execmem.h>
#include <asm/module.h>
#include <linux/uaccess.h>
#include <asm/firmware.h>
@@ -89,39 +90,56 @@ int module_finalize(const Elf_Ehdr *hdr,
return 0;
}
-static __always_inline void *
-__module_alloc(unsigned long size, unsigned long start, unsigned long end, bool nowarn)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
pgprot_t prot = strict_module_rwx_enabled() ? PAGE_KERNEL : PAGE_KERNEL_EXEC;
- gfp_t gfp = GFP_KERNEL | (nowarn ? __GFP_NOWARN : 0);
+ unsigned long fallback_start = 0, fallback_end = 0;
+ unsigned long start, end;
/*
- * Don't do huge page allocations for modules yet until more testing
- * is done. STRICT_MODULE_RWX may require extra work to support this
- * too.
+ * BOOK3S_32 and 8xx define MODULES_VADDR for text allocations and
+ * allow allocating data in the entire vmalloc space
*/
- return __vmalloc_node_range(size, 1, start, end, gfp, prot,
- VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
-void *module_alloc(unsigned long size)
-{
#ifdef MODULES_VADDR
unsigned long limit = (unsigned long)_etext - SZ_32M;
- void *ptr = NULL;
BUILD_BUG_ON(TASK_SIZE > MODULES_VADDR);
/* First try within 32M limit from _etext to avoid branch trampolines */
- if (MODULES_VADDR < PAGE_OFFSET && MODULES_END > limit)
- ptr = __module_alloc(size, limit, MODULES_END, true);
-
- if (!ptr)
- ptr = __module_alloc(size, MODULES_VADDR, MODULES_END, false);
+ if (MODULES_VADDR < PAGE_OFFSET && MODULES_END > limit) {
+ start = limit;
+ fallback_start = MODULES_VADDR;
+ fallback_end = MODULES_END;
+ } else {
+ start = MODULES_VADDR;
+ }
- return ptr;
+ end = MODULES_END;
#else
- return __module_alloc(size, VMALLOC_START, VMALLOC_END, false);
+ start = VMALLOC_START;
+ end = VMALLOC_END;
#endif
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = start,
+ .end = end,
+ .pgprot = prot,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ [EXECMEM_MODULE_DATA] = {
+ .start = VMALLOC_START,
+ .end = VMALLOC_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ },
+ },
+ };
+
+ return &execmem_info;
}
diff --git a/arch/s390/kernel/module.c b/arch/s390/kernel/module.c
index ac97a905e8cd..7fee64fdc1bb 100644
--- a/arch/s390/kernel/module.c
+++ b/arch/s390/kernel/module.c
@@ -37,41 +37,31 @@
#define PLT_ENTRY_SIZE 22
-static unsigned long get_module_load_offset(void)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- static DEFINE_MUTEX(module_kaslr_mutex);
- static unsigned long module_load_offset;
-
- if (!kaslr_enabled())
- return 0;
- /*
- * Calculate the module_load_offset the first time this code
- * is called. Once calculated it stays the same until reboot.
- */
- mutex_lock(&module_kaslr_mutex);
- if (!module_load_offset)
+ unsigned long module_load_offset = 0;
+ unsigned long start;
+
+ if (kaslr_enabled())
module_load_offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
- mutex_unlock(&module_kaslr_mutex);
- return module_load_offset;
-}
-void *module_alloc(unsigned long size)
-{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- if (PAGE_ALIGN(size) > MODULES_LEN)
- return NULL;
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- MODULES_VADDR + get_module_load_offset(),
- MODULES_END, gfp_mask, PAGE_KERNEL,
- VM_FLUSH_RESET_PERMS | VM_DEFER_KMEMLEAK,
- NUMA_NO_NODE, __builtin_return_address(0));
- if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) {
- vfree(p);
- return NULL;
- }
- return p;
+ start = MODULES_VADDR + module_load_offset;
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .flags = EXECMEM_KASAN_SHADOW,
+ .start = start,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = MODULE_ALIGN,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#ifdef CONFIG_FUNCTION_TRACER
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index e18914c0e38a..45b1a7c03379 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -19,6 +19,7 @@
#include <linux/jump_label.h>
#include <linux/random.h>
#include <linux/memory.h>
+#include <linux/execmem.h>
#include <asm/text-patching.h>
#include <asm/page.h>
@@ -36,55 +37,30 @@ do { \
} while (0)
#endif
-#ifdef CONFIG_RANDOMIZE_BASE
-static unsigned long module_load_offset;
+static struct execmem_info execmem_info __ro_after_init;
-/* Mutex protects the module_load_offset. */
-static DEFINE_MUTEX(module_kaslr_mutex);
-
-static unsigned long int get_module_load_offset(void)
-{
- if (kaslr_enabled()) {
- mutex_lock(&module_kaslr_mutex);
- /*
- * Calculate the module_load_offset the first time this
- * code is called. Once calculated it stays the same until
- * reboot.
- */
- if (module_load_offset == 0)
- module_load_offset =
- get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
- mutex_unlock(&module_kaslr_mutex);
- }
- return module_load_offset;
-}
-#else
-static unsigned long int get_module_load_offset(void)
+struct execmem_info __init *execmem_arch_setup(void)
{
- return 0;
-}
-#endif
-
-void *module_alloc(unsigned long size)
-{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- if (PAGE_ALIGN(size) > MODULES_LEN)
- return NULL;
-
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- MODULES_VADDR + get_module_load_offset(),
- MODULES_END, gfp_mask, PAGE_KERNEL,
- VM_FLUSH_RESET_PERMS | VM_DEFER_KMEMLEAK,
- NUMA_NO_NODE, __builtin_return_address(0));
-
- if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) {
- vfree(p);
- return NULL;
- }
-
- return p;
+ unsigned long start, offset = 0;
+
+ if (kaslr_enabled())
+ offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
+
+ start = MODULES_VADDR + offset;
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .flags = EXECMEM_KASAN_SHADOW,
+ .start = start,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = MODULE_ALIGN,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#ifdef CONFIG_X86_32
diff --git a/include/linux/execmem.h b/include/linux/execmem.h
index 96fc59258467..32cef1144117 100644
--- a/include/linux/execmem.h
+++ b/include/linux/execmem.h
@@ -5,6 +5,14 @@
#include <linux/types.h>
#include <linux/moduleloader.h>
+#if (defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)) && \
+ !defined(CONFIG_KASAN_VMALLOC)
+#include <linux/kasan.h>
+#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
+#else
+#define MODULE_ALIGN PAGE_SIZE
+#endif
+
/**
* enum execmem_type - types of executable memory ranges
*
@@ -22,6 +30,7 @@
* @EXECMEM_KPROBES: parameters for kprobes
* @EXECMEM_FTRACE: parameters for ftrace
* @EXECMEM_BPF: parameters for BPF
+ * @EXECMEM_MODULE_DATA: parameters for module data sections
* @EXECMEM_TYPE_MAX:
*/
enum execmem_type {
@@ -30,22 +39,38 @@ enum execmem_type {
EXECMEM_KPROBES,
EXECMEM_FTRACE,
EXECMEM_BPF,
+ EXECMEM_MODULE_DATA,
EXECMEM_TYPE_MAX,
};
+/**
+ * enum execmem_range_flags - options for executable memory allocations
+ * @EXECMEM_KASAN_SHADOW: allocate kasan shadow
+ */
+enum execmem_range_flags {
+ EXECMEM_KASAN_SHADOW = (1 << 0),
+};
+
/**
* struct execmem_range - definition of an address space suitable for code and
* related data allocations
* @start: address space start
* @end: address space end (inclusive)
+ * @fallback_start: start of the secondary address space range for fallback
+ * allocations on architectures that require it
+ * @fallback_end: start of the secondary address space (inclusive)
* @pgprot: permissions for memory in this address space
* @alignment: alignment required for text allocations
+ * @flags: options for memory allocations for this range
*/
struct execmem_range {
unsigned long start;
unsigned long end;
+ unsigned long fallback_start;
+ unsigned long fallback_end;
pgprot_t pgprot;
unsigned int alignment;
+ enum execmem_range_flags flags;
};
/**
@@ -82,6 +107,9 @@ struct execmem_info *execmem_arch_setup(void);
* Allocates memory that will contain executable code, either generated or
* loaded from kernel modules.
*
+ * Allocates memory that will contain data coupled with executable code,
+ * like data sections in kernel modules.
+ *
* The memory will have protections defined by architecture for executable
* region of the @type.
*
@@ -95,7 +123,7 @@ void *execmem_alloc(enum execmem_type type, size_t size);
*/
void execmem_free(void *ptr);
-#ifdef CONFIG_EXECMEM
+#if defined(CONFIG_EXECMEM) && !defined(CONFIG_ARCH_WANTS_EXECMEM_LATE)
void execmem_init(void);
#else
static inline void execmem_init(void) {}
diff --git a/include/linux/moduleloader.h b/include/linux/moduleloader.h
index a3b8caee9405..e395461d59e5 100644
--- a/include/linux/moduleloader.h
+++ b/include/linux/moduleloader.h
@@ -25,10 +25,6 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
/* Additional bytes needed by arch in front of individual sections */
unsigned int arch_mod_section_prepend(struct module *mod, unsigned int section);
-/* Allocator used for allocating struct module, core sections and init
- sections. Returns NULL on failure. */
-void *module_alloc(unsigned long size);
-
/* Determines if the section name is an init section (that is only used during
* module loading).
*/
@@ -126,12 +122,4 @@ void module_arch_cleanup(struct module *mod);
/* Any cleanup before freeing mod->module_init */
void module_arch_freeing_init(struct module *mod);
-#if (defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)) && \
- !defined(CONFIG_KASAN_VMALLOC)
-#include <linux/kasan.h>
-#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
-#else
-#define MODULE_ALIGN PAGE_SIZE
-#endif
-
#endif
diff --git a/kernel/module/main.c b/kernel/module/main.c
index d56b7df0cbb6..91e185607d4b 100644
--- a/kernel/module/main.c
+++ b/kernel/module/main.c
@@ -1188,24 +1188,20 @@ void __weak module_arch_freeing_init(struct module *mod)
{
}
-static bool mod_mem_use_vmalloc(enum mod_mem_type type)
-{
- return IS_ENABLED(CONFIG_ARCH_WANTS_MODULES_DATA_IN_VMALLOC) &&
- mod_mem_type_is_core_data(type);
-}
-
static int module_memory_alloc(struct module *mod, enum mod_mem_type type)
{
unsigned int size = PAGE_ALIGN(mod->mem[type].size);
+ enum execmem_type execmem_type;
void *ptr;
mod->mem[type].size = size;
- if (mod_mem_use_vmalloc(type))
- ptr = vmalloc(size);
+ if (mod_mem_type_is_data(type))
+ execmem_type = EXECMEM_MODULE_DATA;
else
- ptr = execmem_alloc(EXECMEM_MODULE_TEXT, size);
+ execmem_type = EXECMEM_MODULE_TEXT;
+ ptr = execmem_alloc(execmem_type, size);
if (!ptr)
return -ENOMEM;
@@ -1232,10 +1228,7 @@ static void module_memory_free(struct module *mod, enum mod_mem_type type)
{
void *ptr = mod->mem[type].base;
- if (mod_mem_use_vmalloc(type))
- vfree(ptr);
- else
- execmem_free(ptr);
+ execmem_free(ptr);
}
static void free_mod_mem(struct module *mod)
@@ -1630,13 +1623,6 @@ static void free_modinfo(struct module *mod)
}
}
-void * __weak module_alloc(unsigned long size)
-{
- return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_EXEC, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
bool __weak module_init_section(const char *name)
{
return strstarts(name, ".init");
diff --git a/mm/execmem.c b/mm/execmem.c
index 80e61c1e7319..f6dc3fabc1ca 100644
--- a/mm/execmem.c
+++ b/mm/execmem.c
@@ -12,27 +12,49 @@
#include <linux/moduleloader.h>
static struct execmem_info *execmem_info __ro_after_init;
+static struct execmem_info default_execmem_info __ro_after_init;
static void *__execmem_alloc(struct execmem_range *range, size_t size)
{
+ bool kasan = range->flags & EXECMEM_KASAN_SHADOW;
+ unsigned long vm_flags = VM_FLUSH_RESET_PERMS;
+ gfp_t gfp_flags = GFP_KERNEL | __GFP_NOWARN;
unsigned long start = range->start;
unsigned long end = range->end;
unsigned int align = range->alignment;
pgprot_t pgprot = range->pgprot;
+ void *p;
+
+ if (kasan)
+ vm_flags |= VM_DEFER_KMEMLEAK;
+
+ p = __vmalloc_node_range(size, align, start, end, gfp_flags,
+ pgprot, vm_flags, NUMA_NO_NODE,
+ __builtin_return_address(0));
+ if (!p && range->fallback_start) {
+ start = range->fallback_start;
+ end = range->fallback_end;
+ p = __vmalloc_node_range(size, align, start, end, gfp_flags,
+ pgprot, vm_flags, NUMA_NO_NODE,
+ __builtin_return_address(0));
+ }
+
+ if (!p) {
+ pr_warn_ratelimited("execmem: unable to allocate memory\n");
+ return NULL;
+ }
+
+ if (kasan && (kasan_alloc_module_shadow(p, size, GFP_KERNEL) < 0)) {
+ vfree(p);
+ return NULL;
+ }
- return __vmalloc_node_range(size, align, start, end,
- GFP_KERNEL, pgprot, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
+ return kasan_reset_tag(p);
}
void *execmem_alloc(enum execmem_type type, size_t size)
{
- struct execmem_range *range;
-
- if (!execmem_info)
- return module_alloc(size);
-
- range = &execmem_info->ranges[type];
+ struct execmem_range *range = &execmem_info->ranges[type];
return __execmem_alloc(range, size);
}
@@ -67,10 +89,16 @@ static void execmem_init_missing(struct execmem_info *info)
struct execmem_range *r = &info->ranges[i];
if (!r->start) {
- r->pgprot = default_range->pgprot;
+ if (i == EXECMEM_MODULE_DATA)
+ r->pgprot = PAGE_KERNEL;
+ else
+ r->pgprot = default_range->pgprot;
r->alignment = default_range->alignment;
r->start = default_range->start;
r->end = default_range->end;
+ r->flags = default_range->flags;
+ r->fallback_start = default_range->fallback_start;
+ r->fallback_end = default_range->fallback_end;
}
}
}
@@ -80,14 +108,37 @@ struct execmem_info * __weak execmem_arch_setup(void)
return NULL;
}
-void __init execmem_init(void)
+static void __init __execmem_init(void)
{
struct execmem_info *info = execmem_arch_setup();
- if (!info || !execmem_validate(info))
+ if (!info) {
+ info = execmem_info = &default_execmem_info;
+ info->ranges[EXECMEM_DEFAULT].start = VMALLOC_START;
+ info->ranges[EXECMEM_DEFAULT].end = VMALLOC_END;
+ info->ranges[EXECMEM_DEFAULT].pgprot = PAGE_KERNEL_EXEC;
+ info->ranges[EXECMEM_DEFAULT].alignment = 1;
+ return;
+ }
+
+ if (!execmem_validate(info))
return;
execmem_init_missing(info);
execmem_info = info;
}
+
+#ifdef CONFIG_ARCH_WANTS_EXECMEM_LATE
+static int __init execmem_late_init(void)
+{
+ __execmem_init();
+ return 0;
+}
+core_initcall(execmem_late_init);
+#else
+void __init execmem_init(void)
+{
+ __execmem_init();
+}
+#endif
--
2.43.0
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 6%]
* Re: [PATCH v2 0/2] thermal: amlogic: introduce A1 SoC family Thermal Sensor controller
@ 2024-04-26 7:31 0% ` Dmitry Rokosov
0 siblings, 0 replies; 200+ results
From: Dmitry Rokosov @ 2024-04-26 7:31 UTC (permalink / raw)
To: Daniel Lezcano, neil.armstrong
Cc: jbrunet, mturquette, khilman, martin.blumenstingl, glaroque,
rafael, rui.zhang, lukasz.luba, robh+dt, krzysztof.kozlowski+dt,
conor+dt, kernel, rockosov, linux-amlogic, linux-pm,
linux-kernel, devicetree, linux-arm-kernel
Hello Neil,
I hope you're doing well. I was wondering if you could assist me with
below problem.
I'm a bit confused about which kernel repository the series was applied
to. I asked Daniel about it, but unfortunately, I didn't receive any
feedback from him. Could you provide some clarification on this matter?
Thank you in advance for your help.
On Wed, Apr 17, 2024 at 11:40:07AM +0300, Dmitry Rokosov wrote:
> Hello Daniel,
>
> Could you please let me know in which repository you have applied this
> change? I am trying to cherry-pick the original applied commit and apply
> it to our internal mainline branch instead of the internal commit.
> However, I am unable to find the applied series in any of the
> repositories on git.kernel.org.
>
> On Thu, Apr 04, 2024 at 02:23:21PM +0200, Daniel Lezcano wrote:
> > On 28/03/2024 20:13, Dmitry Rokosov wrote:
> > > It is primarily based on the G12A thermal controller, with only a slight
> > > variation in the offset value of the efuse parameters. Therefore, this
> > > patch series provides appropriate platform data and dt-bindings to
> > > ensure proper support.
> >
> >
> > Applied, thanks
>
--
Thank you,
Dmitry
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* [PATCH v3 3/3] pwm: meson: Use mul_u64_u64_div_u64() for frequency calculating
@ 2024-04-25 17:12 7% ` George Stark
0 siblings, 0 replies; 200+ results
From: George Stark @ 2024-04-25 17:12 UTC (permalink / raw)
To: u.kleine-koenig, neil.armstrong, khilman, jbrunet,
martin.blumenstingl, thierry.reding, hkallweit1
Cc: linux-pwm, linux-amlogic, linux-arm-kernel, linux-kernel, kernel,
George Stark
While calculating frequency for the given period u64 numbers are
multiplied before division what can lead to overflow in theory so use
secure mul_u64_u64_div_u64() which handles overflow correctly.
Fixes: 329db102a26d ("pwm: meson: make full use of common clock framework")
Suggested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: George Stark <gnstark@salutedevices.com>
---
drivers/pwm/pwm-meson.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 4a652d500dfc..b2f97dfb01bb 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -176,7 +176,7 @@ static int meson_pwm_calc(struct pwm_chip *chip, struct pwm_device *pwm,
dev_dbg(pwmchip_parent(chip), "fin_freq: %ld Hz\n", fin_freq);
- cnt = div_u64(fin_freq * period, NSEC_PER_SEC);
+ cnt = mul_u64_u64_div_u64(fin_freq, period, NSEC_PER_SEC);
if (cnt > 0xffff) {
dev_err(pwmchip_parent(chip), "unable to get period cnt\n");
return -EINVAL;
@@ -191,7 +191,7 @@ static int meson_pwm_calc(struct pwm_chip *chip, struct pwm_device *pwm,
channel->hi = 0;
channel->lo = cnt;
} else {
- duty_cnt = div_u64(fin_freq * duty, NSEC_PER_SEC);
+ duty_cnt = mul_u64_u64_div_u64(fin_freq, duty, NSEC_PER_SEC);
dev_dbg(pwmchip_parent(chip), "duty=%llu duty_cnt=%u\n", duty, duty_cnt);
--
2.25.1
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^ permalink raw reply related [relevance 7%]
* Re: [PATCH v2 09/14] arm64: Enable memory encrypt for Realms
2024-04-25 13:42 0% ` Suzuki K Poulose
@ 2024-04-25 16:29 0% ` Suzuki K Poulose
0 siblings, 0 replies; 200+ results
From: Suzuki K Poulose @ 2024-04-25 16:29 UTC (permalink / raw)
To: kernel test robot, Steven Price, kvm, kvmarm
Cc: llvm, oe-kbuild-all, Catalin Marinas, Marc Zyngier, Will Deacon,
James Morse, Oliver Upton, Zenghui Yu, linux-arm-kernel,
linux-kernel, Joey Gouly, Alexandru Elisei, Christoffer Dall,
Fuad Tabba, linux-coco, Ganapatrao Kulkarni, Emanuele.Rocca
On 25/04/2024 14:42, Suzuki K Poulose wrote:
> On 15/04/2024 04:13, kernel test robot wrote:
>> Hi Steven,
>>
>> kernel test robot noticed the following build errors:
>>
>> [auto build test ERROR on arm64/for-next/core]
>> [also build test ERROR on kvmarm/next efi/next tip/irq/core
>> linus/master v6.9-rc3 next-20240412]
>> [cannot apply to arnd-asm-generic/master]
>> [If your patch is applied to the wrong git tree, kindly drop us a note.
>> And when submitting patch, we suggest to use '--base' as documented in
>> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>>
>> url:
>> https://github.com/intel-lab-lkp/linux/commits/Steven-Price/arm64-rsi-Add-RSI-definitions/20240412-164852
>> base:
>> https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
>> for-next/core
>> patch link:
>> https://lore.kernel.org/r/20240412084213.1733764-10-steven.price%40arm.com
>> patch subject: [PATCH v2 09/14] arm64: Enable memory encrypt for Realms
>> config: arm64-allyesconfig
>> (https://download.01.org/0day-ci/archive/20240415/202404151003.vkNApJiS-lkp@intel.com/config)
>> compiler: clang version 19.0.0git
>> (https://github.com/llvm/llvm-project
>> 8b3b4a92adee40483c27f26c478a384cd69c6f05)
>> reproduce (this is a W=1 build):
>> (https://download.01.org/0day-ci/archive/20240415/202404151003.vkNApJiS-lkp@intel.com/reproduce)
>>
>> If you fix the issue in a separate patch/commit (i.e. not just a new
>> version of
>> the same patch/commit), kindly add following tags
>> | Reported-by: kernel test robot <lkp@intel.com>
>> | Closes:
>> https://lore.kernel.org/oe-kbuild-all/202404151003.vkNApJiS-lkp@intel.com/
>>
>> All errors (new ones prefixed by >>):
>>
>> In file included from drivers/hv/hv.c:13:
>> In file included from include/linux/mm.h:2208:
>> include/linux/vmstat.h:508:43: warning: arithmetic between
>> different enumeration types ('enum zone_stat_item' and 'enum
>> numa_stat_item') [-Wenum-enum-conversion]
>> 508 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~ ^
>> 509 | item];
>> | ~~~~
>> include/linux/vmstat.h:515:43: warning: arithmetic between
>> different enumeration types ('enum zone_stat_item' and 'enum
>> numa_stat_item') [-Wenum-enum-conversion]
>> 515 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~ ^
>> 516 | NR_VM_NUMA_EVENT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~~
>> include/linux/vmstat.h:522:36: warning: arithmetic between
>> different enumeration types ('enum node_stat_item' and 'enum
>> lru_list') [-Wenum-enum-conversion]
>> 522 | return node_stat_name(NR_LRU_BASE + lru) + 3; //
>> skip "nr_"
>> | ~~~~~~~~~~~ ^ ~~~
>> include/linux/vmstat.h:527:43: warning: arithmetic between
>> different enumeration types ('enum zone_stat_item' and 'enum
>> numa_stat_item') [-Wenum-enum-conversion]
>> 527 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~ ^
>> 528 | NR_VM_NUMA_EVENT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~~
>> include/linux/vmstat.h:536:43: warning: arithmetic between
>> different enumeration types ('enum zone_stat_item' and 'enum
>> numa_stat_item') [-Wenum-enum-conversion]
>> 536 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~ ^
>> 537 | NR_VM_NUMA_EVENT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~~
>>>> drivers/hv/hv.c:132:10: error: call to undeclared function
>>>> 'set_memory_decrypted'; ISO C99 and later do not support implicit
>>>> function declarations [-Wimplicit-function-declaration]
>> 132 | ret =
>> set_memory_decrypted((unsigned long)hv_cpu->post_msg_page, 1);
>> | ^
>> drivers/hv/hv.c:168:10: error: call to undeclared function
>> 'set_memory_decrypted'; ISO C99 and later do not support implicit
>> function declarations [-Wimplicit-function-declaration]
>> 168 | ret =
>> set_memory_decrypted((unsigned long)
>> | ^
>>>> drivers/hv/hv.c:218:11: error: call to undeclared function
>>>> 'set_memory_encrypted'; ISO C99 and later do not support implicit
>>>> function declarations [-Wimplicit-function-declaration]
>> 218 | ret =
>> set_memory_encrypted((unsigned long)
>> | ^
>> drivers/hv/hv.c:230:11: error: call to undeclared function
>> 'set_memory_encrypted'; ISO C99 and later do not support implicit
>> function declarations [-Wimplicit-function-declaration]
>> 230 | ret =
>> set_memory_encrypted((unsigned long)
>> | ^
>> drivers/hv/hv.c:239:11: error: call to undeclared function
>> 'set_memory_encrypted'; ISO C99 and later do not support implicit
>> function declarations [-Wimplicit-function-declaration]
>> 239 | ret =
>> set_memory_encrypted((unsigned long)
>> | ^
>> 5 warnings and 5 errors generated.
>> --
>> In file included from drivers/hv/connection.c:16:
>> In file included from include/linux/mm.h:2208:
>> include/linux/vmstat.h:508:43: warning: arithmetic between
>> different enumeration types ('enum zone_stat_item' and 'enum
>> numa_stat_item') [-Wenum-enum-conversion]
>> 508 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~ ^
>> 509 | item];
>> | ~~~~
>> include/linux/vmstat.h:515:43: warning: arithmetic between
>> different enumeration types ('enum zone_stat_item' and 'enum
>> numa_stat_item') [-Wenum-enum-conversion]
>> 515 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~ ^
>> 516 | NR_VM_NUMA_EVENT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~~
>> include/linux/vmstat.h:522:36: warning: arithmetic between
>> different enumeration types ('enum node_stat_item' and 'enum
>> lru_list') [-Wenum-enum-conversion]
>> 522 | return node_stat_name(NR_LRU_BASE + lru) + 3; //
>> skip "nr_"
>> | ~~~~~~~~~~~ ^ ~~~
>> include/linux/vmstat.h:527:43: warning: arithmetic between
>> different enumeration types ('enum zone_stat_item' and 'enum
>> numa_stat_item') [-Wenum-enum-conversion]
>> 527 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~ ^
>> 528 | NR_VM_NUMA_EVENT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~~
>> include/linux/vmstat.h:536:43: warning: arithmetic between
>> different enumeration types ('enum zone_stat_item' and 'enum
>> numa_stat_item') [-Wenum-enum-conversion]
>> 536 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~ ^
>> 537 | NR_VM_NUMA_EVENT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~~
>>>> drivers/hv/connection.c:236:8: error: call to undeclared function
>>>> 'set_memory_decrypted'; ISO C99 and later do not support implicit
>>>> function declarations [-Wimplicit-function-declaration]
>> 236 | ret = set_memory_decrypted((unsigned long)
>> | ^
>>>> drivers/hv/connection.c:340:2: error: call to undeclared function
>>>> 'set_memory_encrypted'; ISO C99 and later do not support implicit
>>>> function declarations [-Wimplicit-function-declaration]
>> 340 | set_memory_encrypted((unsigned
>> long)vmbus_connection.monitor_pages[0], 1);
>> | ^
>> 5 warnings and 2 errors generated.
>> --
>> In file included from drivers/hv/channel.c:14:
>> In file included from include/linux/mm.h:2208:
>> include/linux/vmstat.h:508:43: warning: arithmetic between
>> different enumeration types ('enum zone_stat_item' and 'enum
>> numa_stat_item') [-Wenum-enum-conversion]
>> 508 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~ ^
>> 509 | item];
>> | ~~~~
>> include/linux/vmstat.h:515:43: warning: arithmetic between
>> different enumeration types ('enum zone_stat_item' and 'enum
>> numa_stat_item') [-Wenum-enum-conversion]
>> 515 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~ ^
>> 516 | NR_VM_NUMA_EVENT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~~
>> include/linux/vmstat.h:522:36: warning: arithmetic between
>> different enumeration types ('enum node_stat_item' and 'enum
>> lru_list') [-Wenum-enum-conversion]
>> 522 | return node_stat_name(NR_LRU_BASE + lru) + 3; //
>> skip "nr_"
>> | ~~~~~~~~~~~ ^ ~~~
>> include/linux/vmstat.h:527:43: warning: arithmetic between
>> different enumeration types ('enum zone_stat_item' and 'enum
>> numa_stat_item') [-Wenum-enum-conversion]
>> 527 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~ ^
>> 528 | NR_VM_NUMA_EVENT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~~
>> include/linux/vmstat.h:536:43: warning: arithmetic between
>> different enumeration types ('enum zone_stat_item' and 'enum
>> numa_stat_item') [-Wenum-enum-conversion]
>> 536 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~ ^
>> 537 | NR_VM_NUMA_EVENT_ITEMS +
>> | ~~~~~~~~~~~~~~~~~~~~~~
>>>> drivers/hv/channel.c:442:8: error: call to undeclared function
>>>> 'set_memory_decrypted'; ISO C99 and later do not support implicit
>>>> function declarations [-Wimplicit-function-declaration]
>> 442 | ret = set_memory_decrypted((unsigned long)kbuffer,
>> | ^
>>>> drivers/hv/channel.c:531:3: error: call to undeclared function
>>>> 'set_memory_encrypted'; ISO C99 and later do not support implicit
>>>> function declarations [-Wimplicit-function-declaration]
>> 531 | set_memory_encrypted((unsigned long)kbuffer,
>> | ^
>> drivers/hv/channel.c:848:8: error: call to undeclared function
>> 'set_memory_encrypted'; ISO C99 and later do not support implicit
>> function declarations [-Wimplicit-function-declaration]
>> 848 | ret = set_memory_encrypted((unsigned
>> long)gpadl->buffer,
>> | ^
>> 5 warnings and 3 errors generated.
>
> Thats my mistake. The correct place for declaring set_memory_*crypted()
> is asm/set_memory.h not asm/mem_encrypt.h.
>
> Steven, please could you fold this patch below :
>
>
> diff --git a/arch/arm64/include/asm/mem_encrypt.h
> b/arch/arm64/include/asm/mem_encrypt.h
> index 7381f9585321..e47265cd180a 100644
> --- a/arch/arm64/include/asm/mem_encrypt.h
> +++ b/arch/arm64/include/asm/mem_encrypt.h
> @@ -14,6 +14,4 @@ static inline bool force_dma_unencrypted(struct device
> *dev)
> return is_realm_world();
> }
>
> -int set_memory_encrypted(unsigned long addr, int numpages);
> -int set_memory_decrypted(unsigned long addr, int numpages);
> #endif
> diff --git a/arch/arm64/include/asm/set_memory.h
> b/arch/arm64/include/asm/set_memory.h
> index 0f740b781187..9561b90fb43c 100644
> --- a/arch/arm64/include/asm/set_memory.h
> +++ b/arch/arm64/include/asm/set_memory.h
> @@ -14,4 +14,6 @@ int set_direct_map_invalid_noflush(struct page *page);
> int set_direct_map_default_noflush(struct page *page);
> bool kernel_page_present(struct page *page);
>
> +int set_memory_encrypted(unsigned long addr, int numpages);
> +int set_memory_decrypted(unsigned long addr, int numpages);
>
>
Emmanuele reports that these need to be exported as well, something
like:
diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c
index 229b6d9990f5..de3843ce2aea 100644
--- a/arch/arm64/mm/pageattr.c
+++ b/arch/arm64/mm/pageattr.c
@@ -228,11 +228,13 @@ int set_memory_encrypted(unsigned long addr, int
numpages)
{
return __set_memory_encrypted(addr, numpages, true);
}
+EXPORT_SYMBOL_GPL(set_memory_encrypted);
int set_memory_decrypted(unsigned long addr, int numpages)
{
return __set_memory_encrypted(addr, numpages, false);
}
+EXPORT_SYMBOL_GPL(set_memory_decrypted);
#ifdef CONFIG_DEBUG_PAGEALLOC
void __kernel_map_pages(struct page *page, int numpages, int enable
>
> Suzuki
>>
>>
>> vim +/set_memory_decrypted +132 drivers/hv/hv.c
>>
>> 3e7ee4902fe699 drivers/staging/hv/Hv.c Hank Janssen 2009-07-13 96
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 97 int hv_synic_alloc(void)
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 98 {
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 99 int cpu, ret = -ENOMEM;
>> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10
>> 100 struct hv_per_cpu_context *hv_cpu;
>> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 101
>> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10
>> 102 /*
>> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10
>> 103 * First, zero all per-cpu memory areas so hv_synic_free() can
>> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10
>> 104 * detect what memory has been allocated and cleanup properly
>> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10
>> 105 * after any failures.
>> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10
>> 106 */
>> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10
>> 107 for_each_present_cpu(cpu) {
>> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10
>> 108 hv_cpu = per_cpu_ptr(hv_context.cpu_context, cpu);
>> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10
>> 109 memset(hv_cpu, 0, sizeof(*hv_cpu));
>> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10
>> 110 }
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 111
>> 6396bb221514d2 drivers/hv/hv.c Kees Cook 2018-06-12
>> 112 hv_context.hv_numa_map = kcalloc(nr_node_ids, sizeof(struct
>> cpumask),
>> 597ff72f3de850 drivers/hv/hv.c Jia-Ju Bai 2018-03-04
>> 113 GFP_KERNEL);
>> 9f01ec53458d9e drivers/hv/hv.c K. Y. Srinivasan 2015-08-05
>> 114 if (hv_context.hv_numa_map == NULL) {
>> 9f01ec53458d9e drivers/hv/hv.c K. Y. Srinivasan 2015-08-05
>> 115 pr_err("Unable to allocate NUMA map\n");
>> 9f01ec53458d9e drivers/hv/hv.c K. Y. Srinivasan 2015-08-05
>> 116 goto err;
>> 9f01ec53458d9e drivers/hv/hv.c K. Y. Srinivasan 2015-08-05
>> 117 }
>> 9f01ec53458d9e drivers/hv/hv.c K. Y. Srinivasan 2015-08-05 118
>> 421b8f20d3c381 drivers/hv/hv.c Vitaly Kuznetsov 2016-12-07
>> 119 for_each_present_cpu(cpu) {
>> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10
>> 120 hv_cpu = per_cpu_ptr(hv_context.cpu_context, cpu);
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 121
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11
>> 122 tasklet_init(&hv_cpu->msg_dpc,
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11
>> 123 vmbus_on_msg_dpc, (unsigned long) hv_cpu);
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 124
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 125 if (ms_hyperv.paravisor_present &&
>> hv_isolation_type_tdx()) {
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 126 hv_cpu->post_msg_page = (void
>> *)get_zeroed_page(GFP_ATOMIC);
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 127 if (hv_cpu->post_msg_page == NULL) {
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 128 pr_err("Unable to allocate post msg page\n");
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 129 goto err;
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 130 }
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 131
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> @132 ret = set_memory_decrypted((unsigned
>> long)hv_cpu->post_msg_page, 1);
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 133 if (ret) {
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 134 pr_err("Failed to decrypt post msg page: %d\n",
>> ret);
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 135 /* Just leak the page, as it's unsafe to free the
>> page. */
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 136 hv_cpu->post_msg_page = NULL;
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 137 goto err;
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 138 }
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 139
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 140 memset(hv_cpu->post_msg_page, 0, PAGE_SIZE);
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 141 }
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 142
>> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25
>> 143 /*
>> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25
>> 144 * Synic message and event pages are allocated by paravisor.
>> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25
>> 145 * Skip these pages allocation here.
>> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25
>> 146 */
>> d3a9d7e49d1531 drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 147 if (!ms_hyperv.paravisor_present && !hv_root_partition) {
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11
>> 148 hv_cpu->synic_message_page =
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 149 (void *)get_zeroed_page(GFP_ATOMIC);
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11
>> 150 if (hv_cpu->synic_message_page == NULL) {
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 151 pr_err("Unable to allocate SYNIC message page\n");
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 152 goto err;
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 153 }
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 154
>> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25
>> 155 hv_cpu->synic_event_page =
>> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25
>> 156 (void *)get_zeroed_page(GFP_ATOMIC);
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11
>> 157 if (hv_cpu->synic_event_page == NULL) {
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 158 pr_err("Unable to allocate SYNIC event page\n");
>> 68f2f2bc163d44 drivers/hv/hv.c Dexuan Cui 2023-08-24 159
>> 68f2f2bc163d44 drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 160 free_page((unsigned
>> long)hv_cpu->synic_message_page);
>> 68f2f2bc163d44 drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 161 hv_cpu->synic_message_page = NULL;
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 162 goto err;
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 163 }
>> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25
>> 164 }
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 165
>> 68f2f2bc163d44 drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 166 if (!ms_hyperv.paravisor_present &&
>> e3131f1c81448a drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 167 (hv_isolation_type_snp() || hv_isolation_type_tdx())) {
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 168 ret = set_memory_decrypted((unsigned long)
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 169 hv_cpu->synic_message_page, 1);
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 170 if (ret) {
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 171 pr_err("Failed to decrypt SYNIC msg page: %d\n",
>> ret);
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 172 hv_cpu->synic_message_page = NULL;
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 173
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 174 /*
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 175 * Free the event page here so that hv_synic_free()
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 176 * won't later try to re-encrypt it.
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 177 */
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 178 free_page((unsigned long)hv_cpu->synic_event_page);
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 179 hv_cpu->synic_event_page = NULL;
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 180 goto err;
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 181 }
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 182
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 183 ret = set_memory_decrypted((unsigned long)
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 184 hv_cpu->synic_event_page, 1);
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 185 if (ret) {
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 186 pr_err("Failed to decrypt SYNIC event page:
>> %d\n", ret);
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 187 hv_cpu->synic_event_page = NULL;
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 188 goto err;
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 189 }
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 190
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 191 memset(hv_cpu->synic_message_page, 0, PAGE_SIZE);
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 192 memset(hv_cpu->synic_event_page, 0, PAGE_SIZE);
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 193 }
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 194 }
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 195
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 196 return 0;
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 197
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 198 err:
>> 572086325ce9a9 drivers/hv/hv.c Michael Kelley 2018-08-02
>> 199 /*
>> 572086325ce9a9 drivers/hv/hv.c Michael Kelley 2018-08-02
>> 200 * Any memory allocations that succeeded will be freed when
>> 572086325ce9a9 drivers/hv/hv.c Michael Kelley 2018-08-02
>> 201 * the caller cleans up by calling hv_synic_free()
>> 572086325ce9a9 drivers/hv/hv.c Michael Kelley 2018-08-02
>> 202 */
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 203 return ret;
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 204 }
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 205
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 206
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 207 void hv_synic_free(void)
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 208 {
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 209 int cpu, ret;
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 210
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11
>> 211 for_each_present_cpu(cpu) {
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11
>> 212 struct hv_per_cpu_context *hv_cpu
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11
>> 213 = per_cpu_ptr(hv_context.cpu_context, cpu);
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 214
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 215 /* It's better to leak the page if the encryption fails. */
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 216 if (ms_hyperv.paravisor_present &&
>> hv_isolation_type_tdx()) {
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 217 if (hv_cpu->post_msg_page) {
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> @218 ret = set_memory_encrypted((unsigned long)
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 219 hv_cpu->post_msg_page, 1);
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 220 if (ret) {
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 221 pr_err("Failed to encrypt post msg page:
>> %d\n", ret);
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 222 hv_cpu->post_msg_page = NULL;
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 223 }
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 224 }
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 225 }
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 226
>> 68f2f2bc163d44 drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 227 if (!ms_hyperv.paravisor_present &&
>> e3131f1c81448a drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 228 (hv_isolation_type_snp() || hv_isolation_type_tdx())) {
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 229 if (hv_cpu->synic_message_page) {
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 230 ret = set_memory_encrypted((unsigned long)
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 231 hv_cpu->synic_message_page, 1);
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 232 if (ret) {
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 233 pr_err("Failed to encrypt SYNIC msg page:
>> %d\n", ret);
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 234 hv_cpu->synic_message_page = NULL;
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 235 }
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 236 }
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 237
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 238 if (hv_cpu->synic_event_page) {
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 239 ret = set_memory_encrypted((unsigned long)
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 240 hv_cpu->synic_event_page, 1);
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 241 if (ret) {
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 242 pr_err("Failed to encrypt SYNIC event page:
>> %d\n", ret);
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 243 hv_cpu->synic_event_page = NULL;
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 244 }
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 245 }
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18
>> 246 }
>> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 247
>> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24
>> 248 free_page((unsigned long)hv_cpu->post_msg_page);
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11
>> 249 free_page((unsigned long)hv_cpu->synic_event_page);
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11
>> 250 free_page((unsigned long)hv_cpu->synic_message_page);
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11
>> 251 }
>> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 252
>> 9f01ec53458d9e drivers/hv/hv.c K. Y. Srinivasan 2015-08-05
>> 253 kfree(hv_context.hv_numa_map);
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19
>> 254 }
>> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 255
>>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 0%]
* [PATCH 2/2] pinctrl: samsung: support a bus clock
@ 2024-04-25 16:03 9% ` André Draszik
0 siblings, 0 replies; 200+ results
From: André Draszik @ 2024-04-25 16:03 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Alim Akhtar,
Linus Walleij, Rob Herring, Conor Dooley, Tomasz Figa,
Peter Griffin
Cc: Tudor Ambarus, Will McVicker, kernel-team, linux-arm-kernel,
linux-samsung-soc, linux-gpio, devicetree, linux-kernel,
André Draszik
On some Samsung-based SoCs there are separate bus clocks / gates each
for each pinctrl instance. To be able to access each pinctrl instance's
registers, this bus clock needs to be running, otherwise register
access will hang. Google Tensor gs101 is one example for such an
implementation.
Update the driver to handle this optional bus clock:
* handle an optional bus clock from DT
* prepare it during driver probe
* enclose all relevant register accesses with a clock enable & disable
Signed-off-by: André Draszik <andre.draszik@linaro.org>
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 111 ++++++++++++++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 74 ++++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.h | 2 +
3 files changed, 187 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 871c1eb46ddf..857d631132f9 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -13,6 +13,7 @@
// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
// external gpio and wakeup interrupt support.
+#include <linux/clk.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
@@ -61,6 +62,12 @@ static void exynos_irq_mask(struct irq_data *irqd)
else
reg_mask = our_chip->eint_mask + bank->eint_offset;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for masking IRQ\n");
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
mask = readl(bank->eint_base + reg_mask);
@@ -68,6 +75,8 @@ static void exynos_irq_mask(struct irq_data *irqd)
writel(mask, bank->eint_base + reg_mask);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(bank->drvdata->pclk);
}
static void exynos_irq_ack(struct irq_data *irqd)
@@ -82,7 +91,15 @@ static void exynos_irq_ack(struct irq_data *irqd)
else
reg_pend = our_chip->eint_pend + bank->eint_offset;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock to ack IRQ\n");
+ return;
+ }
+
writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
+
+ clk_disable(bank->drvdata->pclk);
}
static void exynos_irq_unmask(struct irq_data *irqd)
@@ -110,6 +127,12 @@ static void exynos_irq_unmask(struct irq_data *irqd)
else
reg_mask = our_chip->eint_mask + bank->eint_offset;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for unmasking IRQ\n");
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
mask = readl(bank->eint_base + reg_mask);
@@ -117,6 +140,8 @@ static void exynos_irq_unmask(struct irq_data *irqd)
writel(mask, bank->eint_base + reg_mask);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(bank->drvdata->pclk);
}
static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
@@ -127,6 +152,7 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
unsigned int con, trig_type;
unsigned long reg_con;
+ int ret;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
@@ -159,11 +185,20 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
else
reg_con = our_chip->eint_con + bank->eint_offset;
+ ret = clk_enable(bank->drvdata->pclk);
+ if (ret) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for configuring IRQ type\n");
+ return ret;
+ }
+
con = readl(bank->eint_base + reg_con);
con &= ~(EXYNOS_EINT_CON_MASK << shift);
con |= trig_type << shift;
writel(con, bank->eint_base + reg_con);
+ clk_disable(bank->drvdata->pclk);
+
return 0;
}
@@ -200,6 +235,14 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
+ ret = clk_enable(bank->drvdata->pclk);
+ if (ret) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for configuring pin %s-%lu\n",
+ bank->name, irqd->hwirq);
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->pctl_base + reg_con);
@@ -209,6 +252,8 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(bank->drvdata->pclk);
+
return 0;
}
@@ -223,6 +268,13 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for deconfiguring pin %s-%lu\n",
+ bank->name, irqd->hwirq);
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->pctl_base + reg_con);
@@ -232,6 +284,8 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(bank->drvdata->pclk);
+
gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
}
@@ -281,10 +335,19 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
unsigned int svc, group, pin;
int ret;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for handling IRQ\n");
+ return IRQ_NONE;
+ }
+
if (bank->eint_con_offset)
svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);
else
svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
+
+ clk_disable(bank->drvdata->pclk);
+
group = EXYNOS_SVC_GROUP(svc);
pin = svc & EXYNOS_SVC_NUM_MASK;
@@ -563,6 +626,19 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
chained_irq_enter(chip, desc);
+ /* just enable the clock once here, to avoid an enable/disable dance for
+ * each bank.
+ */
+ if (eintd->nr_banks) {
+ struct samsung_pin_bank *b = eintd->banks[0];
+
+ if (clk_enable(b->drvdata->pclk)) {
+ dev_err(b->gpio_chip.parent,
+ "unable to enable clock for pending IRQs\n");
+ return;
+ }
+ }
+
for (i = 0; i < eintd->nr_banks; ++i) {
struct samsung_pin_bank *b = eintd->banks[i];
pend = readl(b->eint_base + b->irq_chip->eint_pend
@@ -572,6 +648,9 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
}
+ if (eintd->nr_banks)
+ clk_disable(eintd->banks[0]->drvdata->pclk);
+
chained_irq_exit(chip, desc);
}
@@ -695,6 +774,12 @@ static void exynos_pinctrl_suspend_bank(
struct exynos_eint_gpio_save *save = bank->soc_priv;
const void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for saving state\n");
+ return;
+ }
+
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset);
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
@@ -704,6 +789,8 @@ static void exynos_pinctrl_suspend_bank(
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
+ bank->eint_offset);
+ clk_disable(bank->drvdata->pclk);
+
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
@@ -716,9 +803,17 @@ static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data *drv
struct exynos_eint_gpio_save *save = bank->soc_priv;
const void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for saving state\n");
+ return;
+ }
+
save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
+ clk_disable(bank->drvdata->pclk);
+
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
}
@@ -753,6 +848,12 @@ static void exynos_pinctrl_resume_bank(
struct exynos_eint_gpio_save *save = bank->soc_priv;
void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for restoring state\n");
+ return;
+ }
+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
readl(regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset), save->eint_con);
@@ -774,6 +875,8 @@ static void exynos_pinctrl_resume_bank(
+ 2 * bank->eint_offset + 4);
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
+ bank->eint_offset);
+
+ clk_disable(bank->drvdata->pclk);
}
static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata,
@@ -782,6 +885,12 @@ static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvd
struct exynos_eint_gpio_save *save = bank->soc_priv;
void __iomem *regs = bank->eint_base;
+ if (clk_enable(bank->drvdata->pclk)) {
+ dev_err(bank->gpio_chip.parent,
+ "unable to enable clock for restoring state\n");
+ return;
+ }
+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
@@ -789,6 +898,8 @@ static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvd
writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
+
+ clk_disable(bank->drvdata->pclk);
}
void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index ed07e23e0912..8e4742d3655c 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -15,6 +15,7 @@
// but provides extensions to which platform specific implementation of the gpio
// and wakeup interrupts can be hooked to.
+#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
@@ -397,6 +398,11 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
reg += 4;
}
+ if (clk_enable(drvdata->pclk)) {
+ dev_err(pctldev->dev, "failed to enable clock for setup\n");
+ return;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
@@ -405,6 +411,8 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
raw_spin_unlock_irqrestore(&bank->slock, flags);
+
+ clk_disable(drvdata->pclk);
}
/* enable a specified pinmux by writing to registers */
@@ -436,6 +444,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
u32 data, width, pin_offset, mask, shift;
u32 cfg_value, cfg_reg;
unsigned long flags;
+ int ret;
drvdata = pinctrl_dev_get_drvdata(pctldev);
pin_to_reg_bank(drvdata, pin, ®_base, &pin_offset, &bank);
@@ -447,6 +456,12 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
width = type->fld_width[cfg_type];
cfg_reg = type->reg_offset[cfg_type];
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
raw_spin_lock_irqsave(&bank->slock, flags);
mask = (1 << width) - 1;
@@ -466,6 +481,8 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
raw_spin_unlock_irqrestore(&bank->slock, flags);
+ clk_disable(drvdata->pclk);
+
return 0;
}
@@ -539,16 +556,24 @@ static void samsung_gpio_set_value(struct gpio_chip *gc,
{
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
const struct samsung_pin_bank_type *type = bank->type;
+ struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
void __iomem *reg;
u32 data;
reg = bank->pctl_base + bank->pctl_offset;
+ if (clk_enable(drvdata->pclk)) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return;
+ }
+
data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
data &= ~(1 << offset);
if (value)
data |= 1 << offset;
writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]);
+
+ clk_disable(drvdata->pclk);
}
/* gpiolib gpio_set callback function */
@@ -569,12 +594,23 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
u32 data;
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
const struct samsung_pin_bank_type *type = bank->type;
+ struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
+ int ret;
reg = bank->pctl_base + bank->pctl_offset;
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
data >>= offset;
data &= 1;
+
+ clk_disable(drvdata->pclk);
+
return data;
}
@@ -591,9 +627,12 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
struct samsung_pin_bank *bank;
void __iomem *reg;
u32 data, mask, shift;
+ struct samsung_pinctrl_drv_data *drvdata;
+ int ret;
bank = gpiochip_get_data(gc);
type = bank->type;
+ drvdata = bank->drvdata;
reg = bank->pctl_base + bank->pctl_offset
+ type->reg_offset[PINCFG_TYPE_FUNC];
@@ -606,12 +645,20 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
reg += 4;
}
+ ret = clk_enable(drvdata->pclk);
+ if (ret) {
+ dev_err(drvdata->dev, "failed to enable clock\n");
+ return ret;
+ }
+
data = readl(reg);
data &= ~(mask << shift);
if (!input)
data |= PIN_CON_FUNC_OUTPUT << shift;
writel(data, reg);
+ clk_disable(drvdata->pclk);
+
return 0;
}
@@ -1164,6 +1211,12 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
}
}
+ drvdata->pclk = devm_clk_get_optional_prepared(dev, "pclk");
+ if (IS_ERR(drvdata->pclk)) {
+ ret = PTR_ERR(drvdata->pclk);
+ goto err_put_banks;
+ }
+
ret = samsung_pinctrl_register(pdev, drvdata);
if (ret)
goto err_put_banks;
@@ -1202,6 +1255,13 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
int i;
+ i = clk_enable(drvdata->pclk);
+ if (i) {
+ dev_err(drvdata->dev,
+ "failed to enable clock for saving state\n");
+ return i;
+ }
+
for (i = 0; i < drvdata->nr_banks; i++) {
struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
const void __iomem *reg = bank->pctl_base + bank->pctl_offset;
@@ -1231,6 +1291,8 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
}
}
+ clk_disable(drvdata->pclk);
+
if (drvdata->suspend)
drvdata->suspend(drvdata);
if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable)
@@ -1252,6 +1314,16 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
int i;
+ /* enable clock before the callback, as we don't want to have to deal
+ * with callback cleanup on clock failures.
+ */
+ i = clk_enable(drvdata->pclk);
+ if (i) {
+ dev_err(drvdata->dev,
+ "failed to enable clock for restoring state\n");
+ return i;
+ }
+
if (drvdata->resume)
drvdata->resume(drvdata);
@@ -1286,6 +1358,8 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
writel(bank->pm_save[type], reg + offs[type]);
}
+ clk_disable(drvdata->pclk);
+
if (drvdata->retention_ctrl && drvdata->retention_ctrl->disable)
drvdata->retention_ctrl->disable(drvdata);
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index ab791afaabf5..d50ba6f07d5d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -274,6 +274,7 @@ struct samsung_pin_ctrl {
* through samsung_pinctrl_drv_data, not samsung_pin_bank).
* @dev: device instance representing the controller.
* @irq: interrpt number used by the controller to notify gpio interrupts.
+ * @pclk: optional bus clock if required for accessing registers
* @ctrl: pin controller instance managed by the driver.
* @pctl: pin controller descriptor registered with the pinctrl subsystem.
* @pctl_dev: cookie representing pinctrl device instance.
@@ -293,6 +294,7 @@ struct samsung_pinctrl_drv_data {
void __iomem *virt_base;
struct device *dev;
int irq;
+ struct clk *pclk;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
--
2.44.0.769.g3c40516874-goog
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 9%]
* Re: [PATCH v2 09/14] arm64: Enable memory encrypt for Realms
@ 2024-04-25 13:42 0% ` Suzuki K Poulose
2024-04-25 16:29 0% ` Suzuki K Poulose
0 siblings, 1 reply; 200+ results
From: Suzuki K Poulose @ 2024-04-25 13:42 UTC (permalink / raw)
To: kernel test robot, Steven Price, kvm, kvmarm
Cc: llvm, oe-kbuild-all, Catalin Marinas, Marc Zyngier, Will Deacon,
James Morse, Oliver Upton, Zenghui Yu, linux-arm-kernel,
linux-kernel, Joey Gouly, Alexandru Elisei, Christoffer Dall,
Fuad Tabba, linux-coco, Ganapatrao Kulkarni, Emanuele.Rocca
On 15/04/2024 04:13, kernel test robot wrote:
> Hi Steven,
>
> kernel test robot noticed the following build errors:
>
> [auto build test ERROR on arm64/for-next/core]
> [also build test ERROR on kvmarm/next efi/next tip/irq/core linus/master v6.9-rc3 next-20240412]
> [cannot apply to arnd-asm-generic/master]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Steven-Price/arm64-rsi-Add-RSI-definitions/20240412-164852
> base: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
> patch link: https://lore.kernel.org/r/20240412084213.1733764-10-steven.price%40arm.com
> patch subject: [PATCH v2 09/14] arm64: Enable memory encrypt for Realms
> config: arm64-allyesconfig (https://download.01.org/0day-ci/archive/20240415/202404151003.vkNApJiS-lkp@intel.com/config)
> compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project 8b3b4a92adee40483c27f26c478a384cd69c6f05)
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240415/202404151003.vkNApJiS-lkp@intel.com/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202404151003.vkNApJiS-lkp@intel.com/
>
> All errors (new ones prefixed by >>):
>
> In file included from drivers/hv/hv.c:13:
> In file included from include/linux/mm.h:2208:
> include/linux/vmstat.h:508:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
> 508 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~ ^
> 509 | item];
> | ~~~~
> include/linux/vmstat.h:515:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
> 515 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~ ^
> 516 | NR_VM_NUMA_EVENT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~~
> include/linux/vmstat.h:522:36: warning: arithmetic between different enumeration types ('enum node_stat_item' and 'enum lru_list') [-Wenum-enum-conversion]
> 522 | return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_"
> | ~~~~~~~~~~~ ^ ~~~
> include/linux/vmstat.h:527:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
> 527 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~ ^
> 528 | NR_VM_NUMA_EVENT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~~
> include/linux/vmstat.h:536:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
> 536 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~ ^
> 537 | NR_VM_NUMA_EVENT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~~
>>> drivers/hv/hv.c:132:10: error: call to undeclared function 'set_memory_decrypted'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
> 132 | ret = set_memory_decrypted((unsigned long)hv_cpu->post_msg_page, 1);
> | ^
> drivers/hv/hv.c:168:10: error: call to undeclared function 'set_memory_decrypted'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
> 168 | ret = set_memory_decrypted((unsigned long)
> | ^
>>> drivers/hv/hv.c:218:11: error: call to undeclared function 'set_memory_encrypted'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
> 218 | ret = set_memory_encrypted((unsigned long)
> | ^
> drivers/hv/hv.c:230:11: error: call to undeclared function 'set_memory_encrypted'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
> 230 | ret = set_memory_encrypted((unsigned long)
> | ^
> drivers/hv/hv.c:239:11: error: call to undeclared function 'set_memory_encrypted'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
> 239 | ret = set_memory_encrypted((unsigned long)
> | ^
> 5 warnings and 5 errors generated.
> --
> In file included from drivers/hv/connection.c:16:
> In file included from include/linux/mm.h:2208:
> include/linux/vmstat.h:508:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
> 508 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~ ^
> 509 | item];
> | ~~~~
> include/linux/vmstat.h:515:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
> 515 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~ ^
> 516 | NR_VM_NUMA_EVENT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~~
> include/linux/vmstat.h:522:36: warning: arithmetic between different enumeration types ('enum node_stat_item' and 'enum lru_list') [-Wenum-enum-conversion]
> 522 | return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_"
> | ~~~~~~~~~~~ ^ ~~~
> include/linux/vmstat.h:527:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
> 527 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~ ^
> 528 | NR_VM_NUMA_EVENT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~~
> include/linux/vmstat.h:536:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
> 536 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~ ^
> 537 | NR_VM_NUMA_EVENT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~~
>>> drivers/hv/connection.c:236:8: error: call to undeclared function 'set_memory_decrypted'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
> 236 | ret = set_memory_decrypted((unsigned long)
> | ^
>>> drivers/hv/connection.c:340:2: error: call to undeclared function 'set_memory_encrypted'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
> 340 | set_memory_encrypted((unsigned long)vmbus_connection.monitor_pages[0], 1);
> | ^
> 5 warnings and 2 errors generated.
> --
> In file included from drivers/hv/channel.c:14:
> In file included from include/linux/mm.h:2208:
> include/linux/vmstat.h:508:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
> 508 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~ ^
> 509 | item];
> | ~~~~
> include/linux/vmstat.h:515:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
> 515 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~ ^
> 516 | NR_VM_NUMA_EVENT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~~
> include/linux/vmstat.h:522:36: warning: arithmetic between different enumeration types ('enum node_stat_item' and 'enum lru_list') [-Wenum-enum-conversion]
> 522 | return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_"
> | ~~~~~~~~~~~ ^ ~~~
> include/linux/vmstat.h:527:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
> 527 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~ ^
> 528 | NR_VM_NUMA_EVENT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~~
> include/linux/vmstat.h:536:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
> 536 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~ ^
> 537 | NR_VM_NUMA_EVENT_ITEMS +
> | ~~~~~~~~~~~~~~~~~~~~~~
>>> drivers/hv/channel.c:442:8: error: call to undeclared function 'set_memory_decrypted'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
> 442 | ret = set_memory_decrypted((unsigned long)kbuffer,
> | ^
>>> drivers/hv/channel.c:531:3: error: call to undeclared function 'set_memory_encrypted'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
> 531 | set_memory_encrypted((unsigned long)kbuffer,
> | ^
> drivers/hv/channel.c:848:8: error: call to undeclared function 'set_memory_encrypted'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
> 848 | ret = set_memory_encrypted((unsigned long)gpadl->buffer,
> | ^
> 5 warnings and 3 errors generated.
Thats my mistake. The correct place for declaring set_memory_*crypted()
is asm/set_memory.h not asm/mem_encrypt.h.
Steven, please could you fold this patch below :
diff --git a/arch/arm64/include/asm/mem_encrypt.h
b/arch/arm64/include/asm/mem_encrypt.h
index 7381f9585321..e47265cd180a 100644
--- a/arch/arm64/include/asm/mem_encrypt.h
+++ b/arch/arm64/include/asm/mem_encrypt.h
@@ -14,6 +14,4 @@ static inline bool force_dma_unencrypted(struct device
*dev)
return is_realm_world();
}
-int set_memory_encrypted(unsigned long addr, int numpages);
-int set_memory_decrypted(unsigned long addr, int numpages);
#endif
diff --git a/arch/arm64/include/asm/set_memory.h
b/arch/arm64/include/asm/set_memory.h
index 0f740b781187..9561b90fb43c 100644
--- a/arch/arm64/include/asm/set_memory.h
+++ b/arch/arm64/include/asm/set_memory.h
@@ -14,4 +14,6 @@ int set_direct_map_invalid_noflush(struct page *page);
int set_direct_map_default_noflush(struct page *page);
bool kernel_page_present(struct page *page);
+int set_memory_encrypted(unsigned long addr, int numpages);
+int set_memory_decrypted(unsigned long addr, int numpages);
Suzuki
>
>
> vim +/set_memory_decrypted +132 drivers/hv/hv.c
>
> 3e7ee4902fe699 drivers/staging/hv/Hv.c Hank Janssen 2009-07-13 96
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 97 int hv_synic_alloc(void)
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 98 {
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 99 int cpu, ret = -ENOMEM;
> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 100 struct hv_per_cpu_context *hv_cpu;
> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 101
> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 102 /*
> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 103 * First, zero all per-cpu memory areas so hv_synic_free() can
> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 104 * detect what memory has been allocated and cleanup properly
> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 105 * after any failures.
> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 106 */
> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 107 for_each_present_cpu(cpu) {
> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 108 hv_cpu = per_cpu_ptr(hv_context.cpu_context, cpu);
> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 109 memset(hv_cpu, 0, sizeof(*hv_cpu));
> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 110 }
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 111
> 6396bb221514d2 drivers/hv/hv.c Kees Cook 2018-06-12 112 hv_context.hv_numa_map = kcalloc(nr_node_ids, sizeof(struct cpumask),
> 597ff72f3de850 drivers/hv/hv.c Jia-Ju Bai 2018-03-04 113 GFP_KERNEL);
> 9f01ec53458d9e drivers/hv/hv.c K. Y. Srinivasan 2015-08-05 114 if (hv_context.hv_numa_map == NULL) {
> 9f01ec53458d9e drivers/hv/hv.c K. Y. Srinivasan 2015-08-05 115 pr_err("Unable to allocate NUMA map\n");
> 9f01ec53458d9e drivers/hv/hv.c K. Y. Srinivasan 2015-08-05 116 goto err;
> 9f01ec53458d9e drivers/hv/hv.c K. Y. Srinivasan 2015-08-05 117 }
> 9f01ec53458d9e drivers/hv/hv.c K. Y. Srinivasan 2015-08-05 118
> 421b8f20d3c381 drivers/hv/hv.c Vitaly Kuznetsov 2016-12-07 119 for_each_present_cpu(cpu) {
> f25a7ece08bdb1 drivers/hv/hv.c Michael Kelley 2018-08-10 120 hv_cpu = per_cpu_ptr(hv_context.cpu_context, cpu);
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 121
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 122 tasklet_init(&hv_cpu->msg_dpc,
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 123 vmbus_on_msg_dpc, (unsigned long) hv_cpu);
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 124
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 125 if (ms_hyperv.paravisor_present && hv_isolation_type_tdx()) {
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 126 hv_cpu->post_msg_page = (void *)get_zeroed_page(GFP_ATOMIC);
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 127 if (hv_cpu->post_msg_page == NULL) {
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 128 pr_err("Unable to allocate post msg page\n");
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 129 goto err;
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 130 }
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 131
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 @132 ret = set_memory_decrypted((unsigned long)hv_cpu->post_msg_page, 1);
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 133 if (ret) {
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 134 pr_err("Failed to decrypt post msg page: %d\n", ret);
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 135 /* Just leak the page, as it's unsafe to free the page. */
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 136 hv_cpu->post_msg_page = NULL;
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 137 goto err;
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 138 }
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 139
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 140 memset(hv_cpu->post_msg_page, 0, PAGE_SIZE);
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 141 }
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 142
> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25 143 /*
> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25 144 * Synic message and event pages are allocated by paravisor.
> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25 145 * Skip these pages allocation here.
> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25 146 */
> d3a9d7e49d1531 drivers/hv/hv.c Dexuan Cui 2023-08-24 147 if (!ms_hyperv.paravisor_present && !hv_root_partition) {
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 148 hv_cpu->synic_message_page =
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 149 (void *)get_zeroed_page(GFP_ATOMIC);
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 150 if (hv_cpu->synic_message_page == NULL) {
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 151 pr_err("Unable to allocate SYNIC message page\n");
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 152 goto err;
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 153 }
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 154
> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25 155 hv_cpu->synic_event_page =
> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25 156 (void *)get_zeroed_page(GFP_ATOMIC);
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 157 if (hv_cpu->synic_event_page == NULL) {
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 158 pr_err("Unable to allocate SYNIC event page\n");
> 68f2f2bc163d44 drivers/hv/hv.c Dexuan Cui 2023-08-24 159
> 68f2f2bc163d44 drivers/hv/hv.c Dexuan Cui 2023-08-24 160 free_page((unsigned long)hv_cpu->synic_message_page);
> 68f2f2bc163d44 drivers/hv/hv.c Dexuan Cui 2023-08-24 161 hv_cpu->synic_message_page = NULL;
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 162 goto err;
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 163 }
> faff44069ff538 drivers/hv/hv.c Tianyu Lan 2021-10-25 164 }
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 165
> 68f2f2bc163d44 drivers/hv/hv.c Dexuan Cui 2023-08-24 166 if (!ms_hyperv.paravisor_present &&
> e3131f1c81448a drivers/hv/hv.c Dexuan Cui 2023-08-24 167 (hv_isolation_type_snp() || hv_isolation_type_tdx())) {
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 168 ret = set_memory_decrypted((unsigned long)
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 169 hv_cpu->synic_message_page, 1);
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 170 if (ret) {
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 171 pr_err("Failed to decrypt SYNIC msg page: %d\n", ret);
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 172 hv_cpu->synic_message_page = NULL;
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 173
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 174 /*
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 175 * Free the event page here so that hv_synic_free()
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 176 * won't later try to re-encrypt it.
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 177 */
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 178 free_page((unsigned long)hv_cpu->synic_event_page);
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 179 hv_cpu->synic_event_page = NULL;
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 180 goto err;
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 181 }
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 182
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 183 ret = set_memory_decrypted((unsigned long)
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 184 hv_cpu->synic_event_page, 1);
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 185 if (ret) {
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 186 pr_err("Failed to decrypt SYNIC event page: %d\n", ret);
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 187 hv_cpu->synic_event_page = NULL;
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 188 goto err;
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 189 }
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 190
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 191 memset(hv_cpu->synic_message_page, 0, PAGE_SIZE);
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 192 memset(hv_cpu->synic_event_page, 0, PAGE_SIZE);
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 193 }
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 194 }
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 195
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 196 return 0;
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 197
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 198 err:
> 572086325ce9a9 drivers/hv/hv.c Michael Kelley 2018-08-02 199 /*
> 572086325ce9a9 drivers/hv/hv.c Michael Kelley 2018-08-02 200 * Any memory allocations that succeeded will be freed when
> 572086325ce9a9 drivers/hv/hv.c Michael Kelley 2018-08-02 201 * the caller cleans up by calling hv_synic_free()
> 572086325ce9a9 drivers/hv/hv.c Michael Kelley 2018-08-02 202 */
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 203 return ret;
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 204 }
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 205
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 206
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 207 void hv_synic_free(void)
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 208 {
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 209 int cpu, ret;
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 210
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 211 for_each_present_cpu(cpu) {
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 212 struct hv_per_cpu_context *hv_cpu
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 213 = per_cpu_ptr(hv_context.cpu_context, cpu);
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 214
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 215 /* It's better to leak the page if the encryption fails. */
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 216 if (ms_hyperv.paravisor_present && hv_isolation_type_tdx()) {
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 217 if (hv_cpu->post_msg_page) {
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 @218 ret = set_memory_encrypted((unsigned long)
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 219 hv_cpu->post_msg_page, 1);
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 220 if (ret) {
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 221 pr_err("Failed to encrypt post msg page: %d\n", ret);
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 222 hv_cpu->post_msg_page = NULL;
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 223 }
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 224 }
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 225 }
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 226
> 68f2f2bc163d44 drivers/hv/hv.c Dexuan Cui 2023-08-24 227 if (!ms_hyperv.paravisor_present &&
> e3131f1c81448a drivers/hv/hv.c Dexuan Cui 2023-08-24 228 (hv_isolation_type_snp() || hv_isolation_type_tdx())) {
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 229 if (hv_cpu->synic_message_page) {
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 230 ret = set_memory_encrypted((unsigned long)
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 231 hv_cpu->synic_message_page, 1);
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 232 if (ret) {
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 233 pr_err("Failed to encrypt SYNIC msg page: %d\n", ret);
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 234 hv_cpu->synic_message_page = NULL;
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 235 }
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 236 }
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 237
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 238 if (hv_cpu->synic_event_page) {
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 239 ret = set_memory_encrypted((unsigned long)
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 240 hv_cpu->synic_event_page, 1);
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 241 if (ret) {
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 242 pr_err("Failed to encrypt SYNIC event page: %d\n", ret);
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 243 hv_cpu->synic_event_page = NULL;
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 244 }
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 245 }
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 246 }
> 193061ea0a50c1 drivers/hv/hv.c Tianyu Lan 2023-08-18 247
> 23378295042a4b drivers/hv/hv.c Dexuan Cui 2023-08-24 248 free_page((unsigned long)hv_cpu->post_msg_page);
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 249 free_page((unsigned long)hv_cpu->synic_event_page);
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 250 free_page((unsigned long)hv_cpu->synic_message_page);
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 251 }
> 37cdd991fac810 drivers/hv/hv.c Stephen Hemminger 2017-02-11 252
> 9f01ec53458d9e drivers/hv/hv.c K. Y. Srinivasan 2015-08-05 253 kfree(hv_context.hv_numa_map);
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 254 }
> 2608fb65310341 drivers/hv/hv.c Jason Wang 2013-06-19 255
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 0%]
* RE: [PATCH v3 3/3] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support
2024-04-24 21:50 0% ` Rob Herring
@ 2024-04-25 8:36 0% ` Hongxing Zhu
0 siblings, 0 replies; 200+ results
From: Hongxing Zhu @ 2024-04-25 8:36 UTC (permalink / raw)
To: Rob Herring
Cc: conor, vkoul, kishon, krzysztof.kozlowski+dt, Frank Li, conor+dt,
linux-phy, devicetree, linux-arm-kernel, linux-kernel, kernel,
imx
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 2024年4月25日 5:51
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: conor@kernel.org; vkoul@kernel.org; kishon@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; Frank Li <frank.li@nxp.com>;
> conor+dt@kernel.org; linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; imx@lists.linux.dev
> Subject: Re: [PATCH v3 3/3] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO
> PHY driver support
>
> On Wed, Apr 24, 2024 at 02:21:23PM +0800, Richard Zhu wrote:
> > Add i.MX8QM HSIO PHY driver support.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> > drivers/phy/freescale/Kconfig | 8 +
> > drivers/phy/freescale/Makefile | 1 +
> > drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 607
> > ++++++++++++++++++++
> > 3 files changed, 616 insertions(+)
> > create mode 100644 drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> >
> > diff --git a/drivers/phy/freescale/Kconfig
> > b/drivers/phy/freescale/Kconfig index 853958fb2c06..c9ee48aeea9e
> > 100644
> > --- a/drivers/phy/freescale/Kconfig
> > +++ b/drivers/phy/freescale/Kconfig
> > @@ -35,6 +35,14 @@ config PHY_FSL_IMX8M_PCIE
> > Enable this to add support for the PCIE PHY as found on
> > i.MX8M family of SOCs.
> >
> > +config PHY_FSL_IMX8QM_HSIO
> > + tristate "Freescale i.MX8QM HSIO PHY"
> > + depends on OF && HAS_IOMEM
> > + select GENERIC_PHY
> > + help
> > + Enable this to add support for the HSIO PHY as found on
> > + i.MX8QM family of SOCs.
> > +
> > endif
> >
> > config PHY_FSL_LYNX_28G
> > diff --git a/drivers/phy/freescale/Makefile
> > b/drivers/phy/freescale/Makefile index cedb328bc4d2..b56b4d5c18ea
> > 100644
> > --- a/drivers/phy/freescale/Makefile
> > +++ b/drivers/phy/freescale/Makefile
> > @@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) +=
> phy-fsl-imx8mq-usb.o
> > obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
> > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
> > obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
> > +obj-$(CONFIG_PHY_FSL_IMX8QM_HSIO) += phy-fsl-imx8qm-hsio.o
> > obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> > b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> > new file mode 100644
> > index 000000000000..b3e17163e859
> > --- /dev/null
> > +++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> > @@ -0,0 +1,607 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
>
> Check that you are including the right DT includes.
>
> > +#include <linux/pci_regs.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/phy/pcie.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +
> > +#include <dt-bindings/phy/phy.h>
> > +#include <dt-bindings/phy/phy-imx8-pcie.h>
> > +
> > +#define MAX_NUM_PHY_MIXS 4
> > +#define PHY_MIX_MAX_NUM_LANES 2
> > +#define LANE_NUM_CLKS 5
> > +
> > +/* Parameters for the waiting for PCIe PHY PLL to lock */
> > +#define PHY_INIT_WAIT_USLEEP_MAX 10
> > +#define PHY_INIT_WAIT_TIMEOUT (1000 *
> PHY_INIT_WAIT_USLEEP_MAX)
> > +
> > +/* i.MX8Q HSIO registers */
> > +#define HSIO_CTRL0 0x0
> > +#define HSIO_APB_RSTN_0 BIT(0)
> > +#define HSIO_APB_RSTN_1 BIT(1)
> > +#define HSIO_PIPE_RSTN_0_MASK GENMASK(25, 24)
> > +#define HSIO_PIPE_RSTN_1_MASK GENMASK(27, 26)
> > +#define HSIO_MODE_MASK GENMASK(20, 17)
> > +#define HSIO_MODE_PCIE 0x0
> > +#define HSIO_MODE_SATA 0x4
> > +#define HSIO_DEVICE_TYPE_MASK GENMASK(27, 24)
> > +#define HSIO_EPCS_TXDEEMP BIT(5)
> > +#define HSIO_EPCS_TXDEEMP_SEL BIT(6)
> > +#define HSIO_EPCS_PHYRESET_N BIT(7)
> > +#define HSIO_RESET_N BIT(12)
> > +
> > +#define HSIO_IOB_RXENA BIT(0)
> > +#define HSIO_IOB_TXENA BIT(1)
> > +#define HSIO_IOB_A_0_TXOE BIT(2)
> > +#define HSIO_IOB_A_0_M1M0_2 BIT(4)
> > +#define HSIO_IOB_A_0_M1M0_MASK GENMASK(4, 3)
> > +#define HSIO_PHYX1_EPCS_SEL BIT(12)
> > +#define HSIO_PCIE_AB_SELECT BIT(13)
> > +
> > +#define HSIO_PHY_STS0 0x4
> > +#define HSIO_LANE0_TX_PLL_LOCK BIT(4)
> > +#define HSIO_LANE1_TX_PLL_LOCK BIT(12)
> > +
> > +#define HSIO_CTRL2 0x8
> > +#define HSIO_LTSSM_ENABLE BIT(4)
> > +#define HSIO_BUTTON_RST_N BIT(21)
> > +#define HSIO_PERST_N BIT(22)
> > +#define HSIO_POWER_UP_RST_N BIT(23)
> > +
> > +#define HSIO_PCIE_STS0 0xc
> > +#define HSIO_PM_REQ_CORE_RST BIT(19)
> > +
> > +#define HSIO_REG48_PMA_STATUS 0x30
> > +#define HSIO_REG48_PMA_RDY BIT(7)
> > +
> > +/*
> > + * There are three lanes PHY in i.MX8QM HSIO, and can be made up the
> > + * following PHY modes in different use cases.
> > + * +------------------------------------+
> > + * | index | LAN0 | LAN1 | LAN2 |
> > + * |------------------------------------|
> > + * | 0 | PCIEA | | |
> > + * |------------------------------------|
> > + * | 1 | | PCIEB | |
> > + * |------------------------------------|
> > + * | 2 | PCIEA | PCIEA | |
> > + * |------------------------------------|
> > + * | 3 | | | PCIEB/SATA |
> > + * +------------------------------------+
> > + */
> > +enum phy_mode_index {
> > + IMX8Q_HSIO_LANE0_PCIE_PHY,
> > + IMX8Q_HSIO_LANE1_PCIE_PHY,
> > + IMX8Q_HSIO_LANE0_1_PCIE_PHY,
> > + IMX8Q_HSIO_LANE2_PHY
> > +};
> > +
> > +struct imx_hsio_drvdata {
> > + int phy_mix_num;
> > +};
> > +
> > +struct imx_hsio_phy_lane {
> > + const char * const *clk_names;
> > + struct clk_bulk_data clks[LANE_NUM_CLKS]; };
> > +
> > +struct imx_hsio_phy_mix {
> > + u32 ctrl_index;
> > + u32 ctrl_off;
> > + u32 phy_off;
> > + u32 phy_type;
> > + struct imx_hsio_phy_lane lane[PHY_MIX_MAX_NUM_LANES];
> > + struct imx_hsio_priv *priv;
> > + struct phy *phy;
> > + enum phy_mode pmix_mode;
> > + enum phy_mode_index idx;
> > +};
> > +
> > +struct imx_hsio_priv {
> > + void __iomem *base;
> > + struct device *dev;
> > + u32 refclk_pad;
> > + u32 hsio_cfg;
> > + struct regmap *phy;
> > + struct regmap *ctrl;
> > + struct regmap *misc;
> > + const struct imx_hsio_drvdata *drvdata;
> > + struct imx_hsio_phy_mix pmix[MAX_NUM_PHY_MIXS]; };
> > +
> > +static const char * const lan0_pcie_clks[] = {"apb_pclk0", "pclk0", "ctl0_crr",
> > + "phy0_crr", "misc_crr"};
> > +static const char * const lan1_pciea_clks[] = {"apb_pclk1", "pclk1", "ctl0_crr",
> > + "phy0_crr", "misc_crr"};
> > +static const char * const lan1_pcieb_clks[] = {"apb_pclk1", "pclk1", "ctl1_crr",
> > + "phy0_crr", "misc_crr"};
> > +static const char * const lan2_pcieb_clks[] = {"apb_pclk2", "pclk2", "ctl1_crr",
> > + "phy1_crr", "misc_crr"};
> > +static const char * const lan2_sata_clks[] = {"pclk2", "epcs_tx", "epcs_rx",
> > + "phy1_crr", "misc_crr"};
> > +
> > +static const struct regmap_config regmap_config = {
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = 4,
> > +};
> > +
> > +static int imx_hsio_get_idx(int phy_type, int ctrl_index, int
> > +lane_mask) {
> > + int index;
> > +
> > + switch (phy_type) {
> > + case PHY_TYPE_PCIE:
> > + if (ctrl_index) { /* PCIEB */
> > + if (lane_mask == IMX8Q_HSIO_LANE0) /* i.MX8QXP */
> > + index = IMX8Q_HSIO_LANE0_PCIE_PHY;
> > + else if (lane_mask == IMX8Q_HSIO_LANE1) /* i.MX8QM */
> > + index = IMX8Q_HSIO_LANE1_PCIE_PHY;
> > + else if (lane_mask == IMX8Q_HSIO_LANE2) /* i.MX8QM */
> > + index = IMX8Q_HSIO_LANE2_PHY;
> > + else
> > + return -EINVAL;
> > + } else { /* PCIEA */
> > + if (lane_mask == (IMX8Q_HSIO_LANE0 | IMX8Q_HSIO_LANE1))
> > + index = IMX8Q_HSIO_LANE0_1_PCIE_PHY;
> > + else if (lane_mask == IMX8Q_HSIO_LANE0)
> > + index = IMX8Q_HSIO_LANE0_PCIE_PHY;
> > + else
> > + return -EINVAL;
> > + }
> > + break;
> > + case PHY_TYPE_SATA:
> > + index = IMX8Q_HSIO_LANE2_PHY;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + return index;
> > +}
> > +
> > +static int imx_hsio_init(struct phy *phy) {
> > + int ret, i;
> > + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> > + struct imx_hsio_priv *priv = pmix->priv;
> > + struct device *dev = priv->dev;
> > +
> > + /* Assign clocks refer to different modes */
> > + switch (pmix->phy_type) {
> > + case PHY_TYPE_PCIE:
> > + if (pmix->ctrl_index == 0) { /* PCIEA */
> > + pmix->pmix_mode = PHY_MODE_PCIE;
> > + pmix->ctrl_off = 0;
> > + pmix->phy_off = 0;
> > +
> > + for (i = 0; i < LANE_NUM_CLKS; i++) {
> > + if (pmix->idx == IMX8Q_HSIO_LANE0_PCIE_PHY) {
> > + pmix->lane[0].clks[i].id = lan0_pcie_clks[i];
> > + } else { /* 2 lanes are bound to PCIEA */
> > + pmix->lane[0].clks[i].id = lan0_pcie_clks[i];
> > + pmix->lane[1].clks[i].id = lan1_pciea_clks[i];
> > + }
> > + }
> > + } else { /* PCIEB */
> > + pmix->pmix_mode = PHY_MODE_PCIE;
> > + if (pmix->idx == IMX8Q_HSIO_LANE0_PCIE_PHY) {
> > + /* i.MX8QXP */
> > + pmix->ctrl_off = 0;
> > + pmix->phy_off = 0;
> > + } else {
> > + /*
> > + * On i.MX8QM, only second or third lane can be
> > + * bound to PCIEB.
> > + */
> > + pmix->ctrl_off = SZ_64K;
> > + if (pmix->idx == IMX8Q_HSIO_LANE1_PCIE_PHY)
> > + pmix->phy_off = 0;
> > + else /* the third lane is bound to PCIEB */
> > + pmix->phy_off = SZ_64K;
> > + }
> > +
> > + for (i = 0; i < LANE_NUM_CLKS; i++) {
> > + if (pmix->idx == IMX8Q_HSIO_LANE1_PCIE_PHY)
> > + pmix->lane[0].clks[i].id = lan1_pcieb_clks[i];
> > + else if (pmix->idx == IMX8Q_HSIO_LANE2_PHY)
> > + pmix->lane[0].clks[i].id = lan2_pcieb_clks[i];
> > + else /* i.MX8QXP only has PCIEB, idx is 0 */
> > + pmix->lane[0].clks[i].id = lan0_pcie_clks[i];
> > + }
> > + }
> > + break;
> > + case PHY_TYPE_SATA:
> > + /* On i.MX8QM, only the third lane can be bound to SATA */
> > + pmix->ctrl_off = SZ_128K;
> > + pmix->pmix_mode = PHY_MODE_SATA;
> > + pmix->phy_off = SZ_64K;
> > +
> > + for (i = 0; i < LANE_NUM_CLKS; i++)
> > + pmix->lane[0].clks[i].id = lan2_sata_clks[i];
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + /* Fetch clocks and enable them */
> > + ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, pmix->lane[0].clks);
> > + if (ret)
> > + return ret;
> > + if (pmix->idx == IMX8Q_HSIO_LANE0_1_PCIE_PHY) {
> > + ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, pmix->lane[1].clks);
> > + if (ret)
> > + return ret;
> > + }
> > + ret = clk_bulk_prepare_enable(LANE_NUM_CLKS, pmix->lane[0].clks);
> > + if (ret)
> > + return ret;
> > + if (pmix->idx == IMX8Q_HSIO_LANE0_1_PCIE_PHY) {
> > + /* Enable the second lane's clocks */
> > + ret = clk_bulk_prepare_enable(LANE_NUM_CLKS,
> > + pmix->lane[1].clks);
> > + if (ret) {
> > + clk_bulk_disable_unprepare(LANE_NUM_CLKS,
> > + pmix->lane[0].clks);
> > + return ret;
> > + }
> > + }
> > +
> > + /* allow the clocks to stabilize */
> > + usleep_range(200, 500);
> > + return 0;
> > +}
> > +
> > +static int imx_hsio_exit(struct phy *phy) {
> > + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> > +
> > + clk_bulk_disable_unprepare(LANE_NUM_CLKS, pmix->lane[0].clks);
> > + if (pmix->idx == IMX8Q_HSIO_LANE0_1_PCIE_PHY)
> > + /* Disable the clocks used by sencond lane of the PHY */
> > + clk_bulk_disable_unprepare(LANE_NUM_CLKS, pmix->lane[1].clks);
> > +
> > + return 0;
> > +}
> > +
> > +static void imx_hsio_pcie_phy_resets(struct phy *phy) {
> > + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> > + struct imx_hsio_priv *priv = pmix->priv;
> > +
> > + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> > + HSIO_BUTTON_RST_N);
> > + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> > + HSIO_PERST_N);
> > + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> > + HSIO_POWER_UP_RST_N);
> > + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> > + HSIO_BUTTON_RST_N);
> > + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> > + HSIO_PERST_N);
> > + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> > + HSIO_POWER_UP_RST_N);
> > +
> > + if (pmix->idx == IMX8Q_HSIO_LANE0_1_PCIE_PHY) {
> > + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> > + HSIO_APB_RSTN_0);
> > + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> > + HSIO_PIPE_RSTN_0_MASK);
> > + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> > + HSIO_APB_RSTN_1);
> > + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> > + HSIO_PIPE_RSTN_1_MASK);
> > + } else if (pmix->idx == IMX8Q_HSIO_LANE1_PCIE_PHY) {
> > + /* The second pmix */
> > + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> > + HSIO_APB_RSTN_1);
> > + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> > + HSIO_PIPE_RSTN_1_MASK);
> > + } else {
> > + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> > + HSIO_APB_RSTN_0);
> > + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> > + HSIO_PIPE_RSTN_0_MASK);
> > + }
> > +}
> > +
> > +static void imx_hsio_sata_phy_resets(struct phy *phy) {
> > + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> > + struct imx_hsio_priv *priv = pmix->priv;
> > +
> > + /* clear PHY RST, then set it */
> > + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> > + HSIO_EPCS_PHYRESET_N);
> > + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> > + HSIO_EPCS_PHYRESET_N);
> > +
> > + /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
> > + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
> > + udelay(1);
> > + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> > + HSIO_RESET_N);
> > + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> > +HSIO_RESET_N); }
> > +
> > +static void imx_hsio_configure_clk_pad(struct phy *phy) {
> > + bool pll = false;
> > + u32 pad_mode;
> > + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> > + struct imx_hsio_priv *priv = pmix->priv;
> > +
> > + pad_mode = priv->refclk_pad;
> > + if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) {
> > + pll = true;
> > + regmap_update_bits(priv->misc, HSIO_CTRL0,
> > + HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
> > + HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_2);
> > + }
> > +
> > + regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_RXENA,
> > + pll ? 0 : HSIO_IOB_RXENA);
> > + regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_TXENA,
> > + pll ? HSIO_IOB_TXENA : 0);
> > +}
> > +
> > +static int imx_hsio_power_on(struct phy *phy) {
> > + int ret;
> > + u32 val, addr, cond;
> > + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> > + struct imx_hsio_priv *priv = pmix->priv;
> > +
> > + if (pmix->pmix_mode == PHY_MODE_PCIE)
> > + imx_hsio_pcie_phy_resets(phy);
> > + else /* SATA */
> > + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> > + HSIO_APB_RSTN_0);
> > +
> > + if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2PCIEB)
>
> Can't this just be based on lane==2 and mode==pcie?
>
The IMX8Q_HSIO_CFG_# are bit-map definitions.
IMX8Q_HSIO_CFG_PCIEAX2PCIEB means that not only PCIEA is enabled but also
the PCIEB is enabled too.
Thus, the PCIE_AB_SELECT should be asserted to be 1b'1.
> > + regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
> > + if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2SATA)
>
> And this on mode==sata?
IMX8Q_HSIO_CFG_PCIEAX2SATA means that not only PCIEA is enabled but also
the SATA is enabled too.
So, the PHYX1_EPCS_SEL should be asserted to be 1b'1 here.
>
> > + regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
> > +
> > + imx_hsio_configure_clk_pad(phy);
>
> power_on is called per phy, but this appears to be some global state.
>
You're right. The pad setting is global and should be called once.
BTW, the setting of the PCIE_AB_SELECT and PHYX1_EPCS_SEL are global too.
> > +
> > + if (pmix->pmix_mode == PHY_MODE_SATA) {
> > + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> > + HSIO_EPCS_TXDEEMP);
> > + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> > + HSIO_EPCS_TXDEEMP_SEL);
> > +
> > + imx_hsio_sata_phy_resets(phy);
> > + } else {
> > + /* Toggle apb_pclk to make sure PM_REQ_CORE_RST is cleared. */
> > + clk_disable_unprepare(pmix->lane[0].clks[0].clk);
> > + mdelay(1);
> > + ret = clk_prepare_enable(pmix->lane[0].clks[0].clk);
> > + if (ret) {
> > + dev_err(priv->dev, "unable to enable phy apb_pclk\n");
> > + return ret;
> > + }
> > +
> > + addr = pmix->ctrl_off + HSIO_PCIE_STS0;
> > + cond = HSIO_PM_REQ_CORE_RST;
> > + ret = regmap_read_poll_timeout(priv->ctrl, addr, val,
> > + (val & cond) == 0,
> > + PHY_INIT_WAIT_USLEEP_MAX,
> > + PHY_INIT_WAIT_TIMEOUT);
> > + if (ret) {
> > + dev_err(priv->dev, "HSIO_PM_REQ_CORE_RST is set\n");
> > + return ret;
> > + }
> > + }
> > +
> > + /* Polling to check the PHY is ready or not. */
> > + if (pmix->idx == IMX8Q_HSIO_LANE1_PCIE_PHY)
> > + cond = HSIO_LANE1_TX_PLL_LOCK;
> > + else
> > + cond = HSIO_LANE0_TX_PLL_LOCK;
>
> In SATA mode, don't you need LANE2? Or you should have exited above?
>
Except the pmix->phy_off of lane2, the others are same to the setting of lane0.
So, the PLL_LOCK check of lane2 is merged into the check of lane0 here.
>
> > +
> > + ret = regmap_read_poll_timeout(priv->phy, pmix->phy_off +
> HSIO_PHY_STS0,
> > + val, ((val & cond) == cond),
> > + PHY_INIT_WAIT_USLEEP_MAX,
> > + PHY_INIT_WAIT_TIMEOUT);
> > + if (ret) {
> > + dev_err(priv->dev, "IMX8Q PHY%d PLL lock timeout\n", pmix->idx);
> > + return ret;
> > + }
> > + dev_info(priv->dev, "IMX8Q PHY%d PLL is locked\n", pmix->idx);
>
> These info level prints should be debug level IMO.
>
> > +
> > + if (pmix->pmix_mode == PHY_MODE_SATA) {
> > + cond = HSIO_REG48_PMA_RDY;
> > + ret = read_poll_timeout(readb, val, ((val & cond) == cond),
> > + PHY_INIT_WAIT_USLEEP_MAX,
> > + PHY_INIT_WAIT_TIMEOUT, false,
> > + priv->base + HSIO_REG48_PMA_STATUS);
> > + if (ret)
> > + dev_err(priv->dev, "PHY calibration is timeout\n");
> > + else
> > + dev_info(priv->dev, "PHY calibration is done\n");
> > + }
>
> This function is a bunch of 'if SATA' or 'if PCIE' blocks which is hard to follow. I
> think it would be easier to follow if you had a specific power_on function for each
> mode which can then call any common helpers (like polling for PLL lock).
>
> And consider if mode specific stuff can go into set_mode() hook instead.
Good idea.
Thanks.
>
> > +
> > + return ret;
> > +}
> > +
> > +static int imx_hsio_set_mode(struct phy *phy, enum phy_mode mode,
> > + int submode)
> > +{
> > + u32 val;
> > + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> > + struct imx_hsio_priv *priv = pmix->priv;
> > +
> > + if (pmix->pmix_mode != mode)
> > + return -EINVAL;
> > +
> > + val = (mode == PHY_MODE_PCIE) ? HSIO_MODE_PCIE : HSIO_MODE_SATA;
> > + val = FIELD_PREP(HSIO_MODE_MASK, val);
> > + regmap_update_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> > + HSIO_MODE_MASK, val);
> > +
> > + switch (submode) {
> > + case PHY_MODE_PCIE_RC:
> > + val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK,
> PCI_EXP_TYPE_ROOT_PORT);
> > + break;
> > + case PHY_MODE_PCIE_EP:
> > + val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK,
> PCI_EXP_TYPE_ENDPOINT);
> > + break;
> > + default: /* Support only PCIe EP and RC now. */
> > + return 0;
> > + }
> > + if (submode)
> > + regmap_update_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> > + HSIO_DEVICE_TYPE_MASK, val);
> > +
> > + return 0;
> > +}
> > +
> > +static int imx_hsio_set_speed(struct phy *phy, int speed) {
> > + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> > + struct imx_hsio_priv *priv = pmix->priv;
> > +
> > + regmap_update_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> > + HSIO_LTSSM_ENABLE,
> > + speed ? HSIO_LTSSM_ENABLE : 0);
> > + return 0;
> > +}
> > +
> > +static const struct phy_ops imx_hsio_ops = {
> > + .init = imx_hsio_init,
> > + .exit = imx_hsio_exit,
> > + .power_on = imx_hsio_power_on,
> > + .set_mode = imx_hsio_set_mode,
> > + .set_speed = imx_hsio_set_speed,
> > + .owner = THIS_MODULE,
> > +};
> > +
> > +static const struct imx_hsio_drvdata imx8qxp_hsio_drvdata = {
> > + .phy_mix_num = 0x1,
> > +};
> > +
> > +static const struct imx_hsio_drvdata imx_hsio_drvdata = {
> > + .phy_mix_num = 0x4,
> > +};
> > +
> > +static const struct of_device_id imx_hsio_of_match[] = {
> > + {.compatible = "fsl,imx8qm-hsio", .data = &imx_hsio_drvdata},
> > + {.compatible = "fsl,imx8qxp-hsio", .data = &imx8qxp_hsio_drvdata},
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, imx_hsio_of_match);
> > +
> > +static struct phy *imx_hsio_xlate(struct device *dev,
> > + const struct of_phandle_args *args) {
> > + struct imx_hsio_priv *priv = dev_get_drvdata(dev);
> > + int phy_type = args->args[0];
> > + int ctrl_index = args->args[1];
> > + int idx, lane_mask = args->args[2];
> > +
> > + idx = imx_hsio_get_idx(phy_type, ctrl_index, lane_mask);
> > + if (idx < 0 || idx >= priv->drvdata->phy_mix_num)
> > + return ERR_PTR(-EINVAL);
> > + priv->pmix[idx].phy_type = phy_type;
> > + priv->pmix[idx].ctrl_index = ctrl_index;
> > + priv->pmix[idx].idx = idx;
> > +
> > + return priv->pmix[idx].phy;
> > +}
> > +
> > +static int imx_hsio_probe(struct platform_device *pdev) {
> > + int i;
> > + void __iomem *off;
> > + struct device *dev = &pdev->dev;
> > + struct device_node *np = dev->of_node;
> > + const struct of_device_id *of_id;
> > + struct imx_hsio_priv *priv;
> > + struct phy_provider *provider;
> > +
> > + of_id = of_match_device(imx_hsio_of_match, dev);
> > + if (!of_id)
> > + return -EINVAL;
>
> This driver only works with DT. We've entered probe because matching happened.
> How could this fail?
>
You're right.
This check can be removed totally. Thanks.
> > +
> > + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > + priv->dev = &pdev->dev;
> > + priv->drvdata = of_device_get_match_data(dev);
> > +
> > + /* Get HSIO configuration mode */
> > + of_property_read_u32(np, "fsl,hsio-cfg", &priv->hsio_cfg);
> > + /* Get PHY refclk pad mode */
> > + if (of_property_read_u32(np, "fsl,refclk-pad-mode", &priv->refclk_pad))
> > + priv->refclk_pad = IMX8_PCIE_REFCLK_PAD_OUTPUT;
> > +
> > + priv->base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(priv->base))
> > + return PTR_ERR(priv->base);
> > +
> > + off = devm_platform_ioremap_resource_byname(pdev, "phy");
> > + priv->phy = devm_regmap_init_mmio(dev, off, ®map_config);
> > + if (IS_ERR(priv->phy))
> > + return dev_err_probe(dev, PTR_ERR(priv->phy),
> > + "unable to find phy csr registers\n");
> > +
> > + off = devm_platform_ioremap_resource_byname(pdev, "ctrl");
> > + priv->ctrl = devm_regmap_init_mmio(dev, off, ®map_config);
> > + if (IS_ERR(priv->ctrl))
> > + return dev_err_probe(dev, PTR_ERR(priv->ctrl),
> > + "unable to find ctrl csr registers\n");
> > +
> > + off = devm_platform_ioremap_resource_byname(pdev, "misc");
> > + priv->misc = devm_regmap_init_mmio(dev, off, ®map_config);
> > + if (IS_ERR(priv->misc))
> > + return dev_err_probe(dev, PTR_ERR(priv->misc),
> > + "unable to find misc csr registers\n");
> > +
> > + for (i = 0; i < priv->drvdata->phy_mix_num; i++) {
> > + struct imx_hsio_phy_mix *pmix = &priv->pmix[i];
> > + struct phy *phy;
> > +
> > + memset(pmix, 0, sizeof(*pmix));
> > +
> > + phy = devm_phy_create(&pdev->dev, NULL, &imx_hsio_ops);
>
> You have up to 3 phys, why do you register 4?
Based on the 3 hardware lane phy instances, there are four phy combination modes
defined above.
So, 4 abstract phys are register here according to the different phy modes.
Anyway, I consider to drop this method, and following your suggestions
listed below.
PCIEA:
phys = <&hsio_phy 0 PHY_MODE_PCIE>;
or:
phys = <&hsio_phy 0 PHY_MODE_PCIE>, <&hsio_phy 1 PHY_MODE_PCIE>;
PCIEB:
phys = <&hsio_phy 1 PHY_MODE_PCIE>;
or:
phys = <&hsio_phy 2 PHY_MODE_PCIE>;
SATA:
phys = <&hsio_phy 2 PHY_MODE_SATA>;
Richard
Best Regards
>
>
> > + if (IS_ERR(phy))
> > + return PTR_ERR(phy);
> > +
> > + pmix->priv = priv;
> > + pmix->phy = phy;
> > + pmix->idx = i;
> > + phy_set_drvdata(phy, pmix);
> > + }
> > +
> > + dev_set_drvdata(dev, priv);
> > + dev_set_drvdata(&pdev->dev, priv);
> > +
> > + provider = devm_of_phy_provider_register(&pdev->dev,
> > +imx_hsio_xlate);
> > +
> > + return PTR_ERR_OR_ZERO(provider);
> > +}
> > +
> > +static struct platform_driver imx_hsio_driver = {
> > + .probe = imx_hsio_probe,
> > + .driver = {
> > + .name = "imx8qm-hsio-phy",
> > + .of_match_table = imx_hsio_of_match,
> > + }
> > +};
> > +module_platform_driver(imx_hsio_driver);
> > +
> > +MODULE_DESCRIPTION("FSL IMX8QM HSIO SERDES PHY driver");
> > +MODULE_LICENSE("GPL");
> > --
> > 2.37.1
> >
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* [PATCH V3 3/3] tty: serial: uartps: Add support for uartps controller reset
@ 2024-04-25 6:23 6% ` Manikanta Guntupalli
0 siblings, 0 replies; 200+ results
From: Manikanta Guntupalli @ 2024-04-25 6:23 UTC (permalink / raw)
To: git, gregkh, jirislaby, robh, krzk+dt, conor+dt, michal.simek,
p.zabel, laurent.pinchart, radhey.shyam.pandey, parth.gajjar,
u.kleine-koenig, tglx, julien.malik, ruanjinjie, linux-kernel,
linux-serial, devicetree, linux-arm-kernel
Cc: srinivas.goud, shubhrajyoti.datta, manion05gk, Manikanta Guntupalli
Add support for an optional reset for the uartps controller using
the reset driver. If the uartps node contains the "resets" property,
then cdns_uart_startup performs uartps controller non-pulse out of reset
and reset in exit path.
Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
---
Changes for V2:
Remove check for reset_control_deassert, as reset_control_deassert
function internally has NULL check.
Changes for V3:
None.
---
drivers/tty/serial/xilinx_uartps.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
index de3487206bcb..2acfcea403ce 100644
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -25,6 +25,7 @@
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/delay.h>
+#include <linux/reset.h>
#define CDNS_UART_TTY_NAME "ttyPS"
#define CDNS_UART_NAME "xuartps"
@@ -198,6 +199,7 @@ MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
* @gpiod_rts: Pointer to the gpio descriptor
* @rs485_tx_started: RS485 tx state
* @tx_timer: Timer for tx
+ * @rstc: Pointer to the reset control
*/
struct cdns_uart {
struct uart_port *port;
@@ -211,6 +213,7 @@ struct cdns_uart {
struct gpio_desc *gpiod_rts;
bool rs485_tx_started;
struct hrtimer tx_timer;
+ struct reset_control *rstc;
};
struct cdns_platform_data {
u32 quirks;
@@ -948,6 +951,10 @@ static int cdns_uart_startup(struct uart_port *port)
is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
+ ret = reset_control_deassert(cdns_uart->rstc);
+ if (ret)
+ return ret;
+
uart_port_lock_irqsave(port, &flags);
/* Disable the TX and RX */
@@ -1721,6 +1728,13 @@ static int cdns_uart_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
}
+ cdns_uart_data->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(cdns_uart_data->rstc)) {
+ rc = PTR_ERR(cdns_uart_data->rstc);
+ dev_err_probe(&pdev->dev, rc, "Cannot get UART reset\n");
+ goto err_out_unregister_driver;
+ }
+
rc = clk_prepare_enable(cdns_uart_data->pclk);
if (rc) {
dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
@@ -1881,6 +1895,7 @@ static void cdns_uart_remove(struct platform_device *pdev)
if (console_port == port)
console_port = NULL;
#endif
+ reset_control_assert(cdns_uart_data->rstc);
if (!--instances)
uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
--
2.25.1
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^ permalink raw reply related [relevance 6%]
* Re: [PATCH v3 3/3] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support
2024-04-24 6:21 6% ` [PATCH v3 3/3] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support Richard Zhu
@ 2024-04-24 21:50 0% ` Rob Herring
2024-04-25 8:36 0% ` Hongxing Zhu
0 siblings, 1 reply; 200+ results
From: Rob Herring @ 2024-04-24 21:50 UTC (permalink / raw)
To: Richard Zhu
Cc: conor, vkoul, kishon, krzysztof.kozlowski+dt, frank.li, conor+dt,
linux-phy, devicetree, linux-arm-kernel, linux-kernel, kernel,
imx
On Wed, Apr 24, 2024 at 02:21:23PM +0800, Richard Zhu wrote:
> Add i.MX8QM HSIO PHY driver support.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
> drivers/phy/freescale/Kconfig | 8 +
> drivers/phy/freescale/Makefile | 1 +
> drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 607 ++++++++++++++++++++
> 3 files changed, 616 insertions(+)
> create mode 100644 drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
>
> diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
> index 853958fb2c06..c9ee48aeea9e 100644
> --- a/drivers/phy/freescale/Kconfig
> +++ b/drivers/phy/freescale/Kconfig
> @@ -35,6 +35,14 @@ config PHY_FSL_IMX8M_PCIE
> Enable this to add support for the PCIE PHY as found on
> i.MX8M family of SOCs.
>
> +config PHY_FSL_IMX8QM_HSIO
> + tristate "Freescale i.MX8QM HSIO PHY"
> + depends on OF && HAS_IOMEM
> + select GENERIC_PHY
> + help
> + Enable this to add support for the HSIO PHY as found on
> + i.MX8QM family of SOCs.
> +
> endif
>
> config PHY_FSL_LYNX_28G
> diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
> index cedb328bc4d2..b56b4d5c18ea 100644
> --- a/drivers/phy/freescale/Makefile
> +++ b/drivers/phy/freescale/Makefile
> @@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
> obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
> obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
> obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
> +obj-$(CONFIG_PHY_FSL_IMX8QM_HSIO) += phy-fsl-imx8qm-hsio.o
> obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
> diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> new file mode 100644
> index 000000000000..b3e17163e859
> --- /dev/null
> +++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> @@ -0,0 +1,607 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
Check that you are including the right DT includes.
> +#include <linux/pci_regs.h>
> +#include <linux/phy/phy.h>
> +#include <linux/phy/pcie.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/phy/phy-imx8-pcie.h>
> +
> +#define MAX_NUM_PHY_MIXS 4
> +#define PHY_MIX_MAX_NUM_LANES 2
> +#define LANE_NUM_CLKS 5
> +
> +/* Parameters for the waiting for PCIe PHY PLL to lock */
> +#define PHY_INIT_WAIT_USLEEP_MAX 10
> +#define PHY_INIT_WAIT_TIMEOUT (1000 * PHY_INIT_WAIT_USLEEP_MAX)
> +
> +/* i.MX8Q HSIO registers */
> +#define HSIO_CTRL0 0x0
> +#define HSIO_APB_RSTN_0 BIT(0)
> +#define HSIO_APB_RSTN_1 BIT(1)
> +#define HSIO_PIPE_RSTN_0_MASK GENMASK(25, 24)
> +#define HSIO_PIPE_RSTN_1_MASK GENMASK(27, 26)
> +#define HSIO_MODE_MASK GENMASK(20, 17)
> +#define HSIO_MODE_PCIE 0x0
> +#define HSIO_MODE_SATA 0x4
> +#define HSIO_DEVICE_TYPE_MASK GENMASK(27, 24)
> +#define HSIO_EPCS_TXDEEMP BIT(5)
> +#define HSIO_EPCS_TXDEEMP_SEL BIT(6)
> +#define HSIO_EPCS_PHYRESET_N BIT(7)
> +#define HSIO_RESET_N BIT(12)
> +
> +#define HSIO_IOB_RXENA BIT(0)
> +#define HSIO_IOB_TXENA BIT(1)
> +#define HSIO_IOB_A_0_TXOE BIT(2)
> +#define HSIO_IOB_A_0_M1M0_2 BIT(4)
> +#define HSIO_IOB_A_0_M1M0_MASK GENMASK(4, 3)
> +#define HSIO_PHYX1_EPCS_SEL BIT(12)
> +#define HSIO_PCIE_AB_SELECT BIT(13)
> +
> +#define HSIO_PHY_STS0 0x4
> +#define HSIO_LANE0_TX_PLL_LOCK BIT(4)
> +#define HSIO_LANE1_TX_PLL_LOCK BIT(12)
> +
> +#define HSIO_CTRL2 0x8
> +#define HSIO_LTSSM_ENABLE BIT(4)
> +#define HSIO_BUTTON_RST_N BIT(21)
> +#define HSIO_PERST_N BIT(22)
> +#define HSIO_POWER_UP_RST_N BIT(23)
> +
> +#define HSIO_PCIE_STS0 0xc
> +#define HSIO_PM_REQ_CORE_RST BIT(19)
> +
> +#define HSIO_REG48_PMA_STATUS 0x30
> +#define HSIO_REG48_PMA_RDY BIT(7)
> +
> +/*
> + * There are three lanes PHY in i.MX8QM HSIO, and can be made up the
> + * following PHY modes in different use cases.
> + * +------------------------------------+
> + * | index | LAN0 | LAN1 | LAN2 |
> + * |------------------------------------|
> + * | 0 | PCIEA | | |
> + * |------------------------------------|
> + * | 1 | | PCIEB | |
> + * |------------------------------------|
> + * | 2 | PCIEA | PCIEA | |
> + * |------------------------------------|
> + * | 3 | | | PCIEB/SATA |
> + * +------------------------------------+
> + */
> +enum phy_mode_index {
> + IMX8Q_HSIO_LANE0_PCIE_PHY,
> + IMX8Q_HSIO_LANE1_PCIE_PHY,
> + IMX8Q_HSIO_LANE0_1_PCIE_PHY,
> + IMX8Q_HSIO_LANE2_PHY
> +};
> +
> +struct imx_hsio_drvdata {
> + int phy_mix_num;
> +};
> +
> +struct imx_hsio_phy_lane {
> + const char * const *clk_names;
> + struct clk_bulk_data clks[LANE_NUM_CLKS];
> +};
> +
> +struct imx_hsio_phy_mix {
> + u32 ctrl_index;
> + u32 ctrl_off;
> + u32 phy_off;
> + u32 phy_type;
> + struct imx_hsio_phy_lane lane[PHY_MIX_MAX_NUM_LANES];
> + struct imx_hsio_priv *priv;
> + struct phy *phy;
> + enum phy_mode pmix_mode;
> + enum phy_mode_index idx;
> +};
> +
> +struct imx_hsio_priv {
> + void __iomem *base;
> + struct device *dev;
> + u32 refclk_pad;
> + u32 hsio_cfg;
> + struct regmap *phy;
> + struct regmap *ctrl;
> + struct regmap *misc;
> + const struct imx_hsio_drvdata *drvdata;
> + struct imx_hsio_phy_mix pmix[MAX_NUM_PHY_MIXS];
> +};
> +
> +static const char * const lan0_pcie_clks[] = {"apb_pclk0", "pclk0", "ctl0_crr",
> + "phy0_crr", "misc_crr"};
> +static const char * const lan1_pciea_clks[] = {"apb_pclk1", "pclk1", "ctl0_crr",
> + "phy0_crr", "misc_crr"};
> +static const char * const lan1_pcieb_clks[] = {"apb_pclk1", "pclk1", "ctl1_crr",
> + "phy0_crr", "misc_crr"};
> +static const char * const lan2_pcieb_clks[] = {"apb_pclk2", "pclk2", "ctl1_crr",
> + "phy1_crr", "misc_crr"};
> +static const char * const lan2_sata_clks[] = {"pclk2", "epcs_tx", "epcs_rx",
> + "phy1_crr", "misc_crr"};
> +
> +static const struct regmap_config regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +static int imx_hsio_get_idx(int phy_type, int ctrl_index, int lane_mask)
> +{
> + int index;
> +
> + switch (phy_type) {
> + case PHY_TYPE_PCIE:
> + if (ctrl_index) { /* PCIEB */
> + if (lane_mask == IMX8Q_HSIO_LANE0) /* i.MX8QXP */
> + index = IMX8Q_HSIO_LANE0_PCIE_PHY;
> + else if (lane_mask == IMX8Q_HSIO_LANE1) /* i.MX8QM */
> + index = IMX8Q_HSIO_LANE1_PCIE_PHY;
> + else if (lane_mask == IMX8Q_HSIO_LANE2) /* i.MX8QM */
> + index = IMX8Q_HSIO_LANE2_PHY;
> + else
> + return -EINVAL;
> + } else { /* PCIEA */
> + if (lane_mask == (IMX8Q_HSIO_LANE0 | IMX8Q_HSIO_LANE1))
> + index = IMX8Q_HSIO_LANE0_1_PCIE_PHY;
> + else if (lane_mask == IMX8Q_HSIO_LANE0)
> + index = IMX8Q_HSIO_LANE0_PCIE_PHY;
> + else
> + return -EINVAL;
> + }
> + break;
> + case PHY_TYPE_SATA:
> + index = IMX8Q_HSIO_LANE2_PHY;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return index;
> +}
> +
> +static int imx_hsio_init(struct phy *phy)
> +{
> + int ret, i;
> + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = pmix->priv;
> + struct device *dev = priv->dev;
> +
> + /* Assign clocks refer to different modes */
> + switch (pmix->phy_type) {
> + case PHY_TYPE_PCIE:
> + if (pmix->ctrl_index == 0) { /* PCIEA */
> + pmix->pmix_mode = PHY_MODE_PCIE;
> + pmix->ctrl_off = 0;
> + pmix->phy_off = 0;
> +
> + for (i = 0; i < LANE_NUM_CLKS; i++) {
> + if (pmix->idx == IMX8Q_HSIO_LANE0_PCIE_PHY) {
> + pmix->lane[0].clks[i].id = lan0_pcie_clks[i];
> + } else { /* 2 lanes are bound to PCIEA */
> + pmix->lane[0].clks[i].id = lan0_pcie_clks[i];
> + pmix->lane[1].clks[i].id = lan1_pciea_clks[i];
> + }
> + }
> + } else { /* PCIEB */
> + pmix->pmix_mode = PHY_MODE_PCIE;
> + if (pmix->idx == IMX8Q_HSIO_LANE0_PCIE_PHY) {
> + /* i.MX8QXP */
> + pmix->ctrl_off = 0;
> + pmix->phy_off = 0;
> + } else {
> + /*
> + * On i.MX8QM, only second or third lane can be
> + * bound to PCIEB.
> + */
> + pmix->ctrl_off = SZ_64K;
> + if (pmix->idx == IMX8Q_HSIO_LANE1_PCIE_PHY)
> + pmix->phy_off = 0;
> + else /* the third lane is bound to PCIEB */
> + pmix->phy_off = SZ_64K;
> + }
> +
> + for (i = 0; i < LANE_NUM_CLKS; i++) {
> + if (pmix->idx == IMX8Q_HSIO_LANE1_PCIE_PHY)
> + pmix->lane[0].clks[i].id = lan1_pcieb_clks[i];
> + else if (pmix->idx == IMX8Q_HSIO_LANE2_PHY)
> + pmix->lane[0].clks[i].id = lan2_pcieb_clks[i];
> + else /* i.MX8QXP only has PCIEB, idx is 0 */
> + pmix->lane[0].clks[i].id = lan0_pcie_clks[i];
> + }
> + }
> + break;
> + case PHY_TYPE_SATA:
> + /* On i.MX8QM, only the third lane can be bound to SATA */
> + pmix->ctrl_off = SZ_128K;
> + pmix->pmix_mode = PHY_MODE_SATA;
> + pmix->phy_off = SZ_64K;
> +
> + for (i = 0; i < LANE_NUM_CLKS; i++)
> + pmix->lane[0].clks[i].id = lan2_sata_clks[i];
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + /* Fetch clocks and enable them */
> + ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, pmix->lane[0].clks);
> + if (ret)
> + return ret;
> + if (pmix->idx == IMX8Q_HSIO_LANE0_1_PCIE_PHY) {
> + ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, pmix->lane[1].clks);
> + if (ret)
> + return ret;
> + }
> + ret = clk_bulk_prepare_enable(LANE_NUM_CLKS, pmix->lane[0].clks);
> + if (ret)
> + return ret;
> + if (pmix->idx == IMX8Q_HSIO_LANE0_1_PCIE_PHY) {
> + /* Enable the second lane's clocks */
> + ret = clk_bulk_prepare_enable(LANE_NUM_CLKS,
> + pmix->lane[1].clks);
> + if (ret) {
> + clk_bulk_disable_unprepare(LANE_NUM_CLKS,
> + pmix->lane[0].clks);
> + return ret;
> + }
> + }
> +
> + /* allow the clocks to stabilize */
> + usleep_range(200, 500);
> + return 0;
> +}
> +
> +static int imx_hsio_exit(struct phy *phy)
> +{
> + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> +
> + clk_bulk_disable_unprepare(LANE_NUM_CLKS, pmix->lane[0].clks);
> + if (pmix->idx == IMX8Q_HSIO_LANE0_1_PCIE_PHY)
> + /* Disable the clocks used by sencond lane of the PHY */
> + clk_bulk_disable_unprepare(LANE_NUM_CLKS, pmix->lane[1].clks);
> +
> + return 0;
> +}
> +
> +static void imx_hsio_pcie_phy_resets(struct phy *phy)
> +{
> + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = pmix->priv;
> +
> + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> + HSIO_BUTTON_RST_N);
> + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> + HSIO_PERST_N);
> + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> + HSIO_POWER_UP_RST_N);
> + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> + HSIO_BUTTON_RST_N);
> + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> + HSIO_PERST_N);
> + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> + HSIO_POWER_UP_RST_N);
> +
> + if (pmix->idx == IMX8Q_HSIO_LANE0_1_PCIE_PHY) {
> + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_0);
> + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> + HSIO_PIPE_RSTN_0_MASK);
> + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_1);
> + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> + HSIO_PIPE_RSTN_1_MASK);
> + } else if (pmix->idx == IMX8Q_HSIO_LANE1_PCIE_PHY) {
> + /* The second pmix */
> + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_1);
> + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> + HSIO_PIPE_RSTN_1_MASK);
> + } else {
> + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_0);
> + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> + HSIO_PIPE_RSTN_0_MASK);
> + }
> +}
> +
> +static void imx_hsio_sata_phy_resets(struct phy *phy)
> +{
> + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = pmix->priv;
> +
> + /* clear PHY RST, then set it */
> + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_PHYRESET_N);
> + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_PHYRESET_N);
> +
> + /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
> + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
> + udelay(1);
> + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> + HSIO_RESET_N);
> + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
> +}
> +
> +static void imx_hsio_configure_clk_pad(struct phy *phy)
> +{
> + bool pll = false;
> + u32 pad_mode;
> + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = pmix->priv;
> +
> + pad_mode = priv->refclk_pad;
> + if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) {
> + pll = true;
> + regmap_update_bits(priv->misc, HSIO_CTRL0,
> + HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
> + HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_2);
> + }
> +
> + regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_RXENA,
> + pll ? 0 : HSIO_IOB_RXENA);
> + regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_TXENA,
> + pll ? HSIO_IOB_TXENA : 0);
> +}
> +
> +static int imx_hsio_power_on(struct phy *phy)
> +{
> + int ret;
> + u32 val, addr, cond;
> + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = pmix->priv;
> +
> + if (pmix->pmix_mode == PHY_MODE_PCIE)
> + imx_hsio_pcie_phy_resets(phy);
> + else /* SATA */
> + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> + HSIO_APB_RSTN_0);
> +
> + if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2PCIEB)
Can't this just be based on lane==2 and mode==pcie?
> + regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
> + if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2SATA)
And this on mode==sata?
> + regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
> +
> + imx_hsio_configure_clk_pad(phy);
power_on is called per phy, but this appears to be some global state.
> +
> + if (pmix->pmix_mode == PHY_MODE_SATA) {
> + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_TXDEEMP);
> + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> + HSIO_EPCS_TXDEEMP_SEL);
> +
> + imx_hsio_sata_phy_resets(phy);
> + } else {
> + /* Toggle apb_pclk to make sure PM_REQ_CORE_RST is cleared. */
> + clk_disable_unprepare(pmix->lane[0].clks[0].clk);
> + mdelay(1);
> + ret = clk_prepare_enable(pmix->lane[0].clks[0].clk);
> + if (ret) {
> + dev_err(priv->dev, "unable to enable phy apb_pclk\n");
> + return ret;
> + }
> +
> + addr = pmix->ctrl_off + HSIO_PCIE_STS0;
> + cond = HSIO_PM_REQ_CORE_RST;
> + ret = regmap_read_poll_timeout(priv->ctrl, addr, val,
> + (val & cond) == 0,
> + PHY_INIT_WAIT_USLEEP_MAX,
> + PHY_INIT_WAIT_TIMEOUT);
> + if (ret) {
> + dev_err(priv->dev, "HSIO_PM_REQ_CORE_RST is set\n");
> + return ret;
> + }
> + }
> +
> + /* Polling to check the PHY is ready or not. */
> + if (pmix->idx == IMX8Q_HSIO_LANE1_PCIE_PHY)
> + cond = HSIO_LANE1_TX_PLL_LOCK;
> + else
> + cond = HSIO_LANE0_TX_PLL_LOCK;
In SATA mode, don't you need LANE2? Or you should have exited above?
> +
> + ret = regmap_read_poll_timeout(priv->phy, pmix->phy_off + HSIO_PHY_STS0,
> + val, ((val & cond) == cond),
> + PHY_INIT_WAIT_USLEEP_MAX,
> + PHY_INIT_WAIT_TIMEOUT);
> + if (ret) {
> + dev_err(priv->dev, "IMX8Q PHY%d PLL lock timeout\n", pmix->idx);
> + return ret;
> + }
> + dev_info(priv->dev, "IMX8Q PHY%d PLL is locked\n", pmix->idx);
These info level prints should be debug level IMO.
> +
> + if (pmix->pmix_mode == PHY_MODE_SATA) {
> + cond = HSIO_REG48_PMA_RDY;
> + ret = read_poll_timeout(readb, val, ((val & cond) == cond),
> + PHY_INIT_WAIT_USLEEP_MAX,
> + PHY_INIT_WAIT_TIMEOUT, false,
> + priv->base + HSIO_REG48_PMA_STATUS);
> + if (ret)
> + dev_err(priv->dev, "PHY calibration is timeout\n");
> + else
> + dev_info(priv->dev, "PHY calibration is done\n");
> + }
This function is a bunch of 'if SATA' or 'if PCIE' blocks which is hard
to follow. I think it would be easier to follow if you had a specific
power_on function for each mode which can then call any common helpers
(like polling for PLL lock).
And consider if mode specific stuff can go into set_mode() hook instead.
> +
> + return ret;
> +}
> +
> +static int imx_hsio_set_mode(struct phy *phy, enum phy_mode mode,
> + int submode)
> +{
> + u32 val;
> + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = pmix->priv;
> +
> + if (pmix->pmix_mode != mode)
> + return -EINVAL;
> +
> + val = (mode == PHY_MODE_PCIE) ? HSIO_MODE_PCIE : HSIO_MODE_SATA;
> + val = FIELD_PREP(HSIO_MODE_MASK, val);
> + regmap_update_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
> + HSIO_MODE_MASK, val);
> +
> + switch (submode) {
> + case PHY_MODE_PCIE_RC:
> + val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
> + break;
> + case PHY_MODE_PCIE_EP:
> + val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ENDPOINT);
> + break;
> + default: /* Support only PCIe EP and RC now. */
> + return 0;
> + }
> + if (submode)
> + regmap_update_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
> + HSIO_DEVICE_TYPE_MASK, val);
> +
> + return 0;
> +}
> +
> +static int imx_hsio_set_speed(struct phy *phy, int speed)
> +{
> + struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
> + struct imx_hsio_priv *priv = pmix->priv;
> +
> + regmap_update_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
> + HSIO_LTSSM_ENABLE,
> + speed ? HSIO_LTSSM_ENABLE : 0);
> + return 0;
> +}
> +
> +static const struct phy_ops imx_hsio_ops = {
> + .init = imx_hsio_init,
> + .exit = imx_hsio_exit,
> + .power_on = imx_hsio_power_on,
> + .set_mode = imx_hsio_set_mode,
> + .set_speed = imx_hsio_set_speed,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct imx_hsio_drvdata imx8qxp_hsio_drvdata = {
> + .phy_mix_num = 0x1,
> +};
> +
> +static const struct imx_hsio_drvdata imx_hsio_drvdata = {
> + .phy_mix_num = 0x4,
> +};
> +
> +static const struct of_device_id imx_hsio_of_match[] = {
> + {.compatible = "fsl,imx8qm-hsio", .data = &imx_hsio_drvdata},
> + {.compatible = "fsl,imx8qxp-hsio", .data = &imx8qxp_hsio_drvdata},
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, imx_hsio_of_match);
> +
> +static struct phy *imx_hsio_xlate(struct device *dev,
> + const struct of_phandle_args *args)
> +{
> + struct imx_hsio_priv *priv = dev_get_drvdata(dev);
> + int phy_type = args->args[0];
> + int ctrl_index = args->args[1];
> + int idx, lane_mask = args->args[2];
> +
> + idx = imx_hsio_get_idx(phy_type, ctrl_index, lane_mask);
> + if (idx < 0 || idx >= priv->drvdata->phy_mix_num)
> + return ERR_PTR(-EINVAL);
> + priv->pmix[idx].phy_type = phy_type;
> + priv->pmix[idx].ctrl_index = ctrl_index;
> + priv->pmix[idx].idx = idx;
> +
> + return priv->pmix[idx].phy;
> +}
> +
> +static int imx_hsio_probe(struct platform_device *pdev)
> +{
> + int i;
> + void __iomem *off;
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + const struct of_device_id *of_id;
> + struct imx_hsio_priv *priv;
> + struct phy_provider *provider;
> +
> + of_id = of_match_device(imx_hsio_of_match, dev);
> + if (!of_id)
> + return -EINVAL;
This driver only works with DT. We've entered probe because matching
happened. How could this fail?
> +
> + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> + priv->dev = &pdev->dev;
> + priv->drvdata = of_device_get_match_data(dev);
> +
> + /* Get HSIO configuration mode */
> + of_property_read_u32(np, "fsl,hsio-cfg", &priv->hsio_cfg);
> + /* Get PHY refclk pad mode */
> + if (of_property_read_u32(np, "fsl,refclk-pad-mode", &priv->refclk_pad))
> + priv->refclk_pad = IMX8_PCIE_REFCLK_PAD_OUTPUT;
> +
> + priv->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(priv->base))
> + return PTR_ERR(priv->base);
> +
> + off = devm_platform_ioremap_resource_byname(pdev, "phy");
> + priv->phy = devm_regmap_init_mmio(dev, off, ®map_config);
> + if (IS_ERR(priv->phy))
> + return dev_err_probe(dev, PTR_ERR(priv->phy),
> + "unable to find phy csr registers\n");
> +
> + off = devm_platform_ioremap_resource_byname(pdev, "ctrl");
> + priv->ctrl = devm_regmap_init_mmio(dev, off, ®map_config);
> + if (IS_ERR(priv->ctrl))
> + return dev_err_probe(dev, PTR_ERR(priv->ctrl),
> + "unable to find ctrl csr registers\n");
> +
> + off = devm_platform_ioremap_resource_byname(pdev, "misc");
> + priv->misc = devm_regmap_init_mmio(dev, off, ®map_config);
> + if (IS_ERR(priv->misc))
> + return dev_err_probe(dev, PTR_ERR(priv->misc),
> + "unable to find misc csr registers\n");
> +
> + for (i = 0; i < priv->drvdata->phy_mix_num; i++) {
> + struct imx_hsio_phy_mix *pmix = &priv->pmix[i];
> + struct phy *phy;
> +
> + memset(pmix, 0, sizeof(*pmix));
> +
> + phy = devm_phy_create(&pdev->dev, NULL, &imx_hsio_ops);
You have up to 3 phys, why do you register 4?
> + if (IS_ERR(phy))
> + return PTR_ERR(phy);
> +
> + pmix->priv = priv;
> + pmix->phy = phy;
> + pmix->idx = i;
> + phy_set_drvdata(phy, pmix);
> + }
> +
> + dev_set_drvdata(dev, priv);
> + dev_set_drvdata(&pdev->dev, priv);
> +
> + provider = devm_of_phy_provider_register(&pdev->dev, imx_hsio_xlate);
> +
> + return PTR_ERR_OR_ZERO(provider);
> +}
> +
> +static struct platform_driver imx_hsio_driver = {
> + .probe = imx_hsio_probe,
> + .driver = {
> + .name = "imx8qm-hsio-phy",
> + .of_match_table = imx_hsio_of_match,
> + }
> +};
> +module_platform_driver(imx_hsio_driver);
> +
> +MODULE_DESCRIPTION("FSL IMX8QM HSIO SERDES PHY driver");
> +MODULE_LICENSE("GPL");
> --
> 2.37.1
>
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v7 14/16] arm64: Kconfig: Enable hotplug CPU on arm64 if ACPI_PROCESSOR is enabled.
@ 2024-04-24 17:24 5% ` Jonathan Cameron
0 siblings, 0 replies; 200+ results
From: Jonathan Cameron @ 2024-04-24 17:24 UTC (permalink / raw)
To: Thomas Gleixner, Peter Zijlstra, linux-pm, loongarch, linux-acpi,
linux-arch, linux-kernel, linux-arm-kernel, kvmarm, x86,
Russell King, Rafael J . Wysocki, Miguel Luis, James Morse,
Salil Mehta, Jean-Philippe Brucker, Catalin Marinas, Will Deacon,
linuxarm
Cc: Ingo Molnar, Borislav Petkov, Dave Hansen, justin.he, jianyong.wu
On Thu, 18 Apr 2024 14:54:10 +0100
Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
> In order to move arch_register_cpu() to be called via the same path
> for initially present CPUs described by ACPI and hotplugged CPUs
> ACPI_HOTPLUG_CPU needs to be enabled.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> v7: No change.
> ---
> arch/arm64/Kconfig | 1 +
> arch/arm64/kernel/acpi.c | 16 ++++++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 7b11c98b3e84..fed7d0d54179 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -5,6 +5,7 @@ config ARM64
> select ACPI_CCA_REQUIRED if ACPI
> select ACPI_GENERIC_GSI if ACPI
> select ACPI_GTDT if ACPI
> + select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR
> select ACPI_IORT if ACPI
> select ACPI_REDUCED_HARDWARE_ONLY if ACPI
> select ACPI_MCFG if (ACPI && PCI)
> diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
> index dba8fcec7f33..a74e80d58df3 100644
> --- a/arch/arm64/kernel/acpi.c
> +++ b/arch/arm64/kernel/acpi.c
> @@ -29,6 +29,7 @@
> #include <linux/pgtable.h>
>
> #include <acpi/ghes.h>
> +#include <acpi/processor.h>
> #include <asm/cputype.h>
> #include <asm/cpu_ops.h>
> #include <asm/daifflags.h>
> @@ -413,6 +414,21 @@ void arch_reserve_mem_area(acpi_physical_address addr, size_t size)
> memblock_mark_nomap(addr, size);
> }
>
> +#ifdef CONFIG_ACPI_HOTPLUG_CPU
> +int acpi_map_cpu(acpi_handle handle, phys_cpuid_t physid, u32 apci_id,
> + int *pcpu)
> +{
There are shipping firmware's in the wild that have DSDT entries for
way more CPUs than are actually present and don't bother with niceties like
providing _STA() methods.
As such, we need to check somewhere that the pcpu after this call is valid.
Given today this only applies to arm64 (as the x86 code has an implementation
of this function that will replace an invalid ID with a valid one) I'll add
a small catch here.
if (*pcpu < 0) {
pr_warn("Unable to map from CPU ACPI ID to anything useful\n");
return -EINVAL;
}
I'll have an entirely polite discussion with the relevant team at somepoint, but
on the plus side this is a sensible bit of hardening.
Jonathan
p.s. I want all those other cores!!!!
> + return 0;
> +}
> +EXPORT_SYMBOL(acpi_map_cpu); /* check why */
> +
> +int acpi_unmap_cpu(int cpu)
> +{
> + return 0;
> +}
> +EXPORT_SYMBOL(acpi_unmap_cpu);
> +#endif /* CONFIG_ACPI_HOTPLUG_CPU */
> +
> #ifdef CONFIG_ACPI_FFH
> /*
> * Implements ARM64 specific callbacks to support ACPI FFH Operation Region as
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^ permalink raw reply [relevance 5%]
* [PATCH v2] soc: xilinx: Add cb event for subsystem restart
2024-04-24 9:59 10% [PATCH] soc: xilinx: Add cb event for subsystem restart Jay Buddhabhatti
@ 2024-04-24 12:49 10% ` Jay Buddhabhatti
0 siblings, 0 replies; 200+ results
From: Jay Buddhabhatti @ 2024-04-24 12:49 UTC (permalink / raw)
To: michal.simek; +Cc: linux-arm-kernel, linux-kernel, Jay Buddhabhatti
Add support to register subsystem restart events from firmware for Versal
and Versal NET platforms. This event is received when firmware requests
for subsystem restart. After receiving this event, the kernel needs to be
restarted.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
---
V1: https://lore.kernel.org/lkml/20240424095937.2448-1-jay.buddhabhatti@amd.com/
V1->V2: Updated copyright header in xlnx-event-manager.h
---
drivers/soc/xilinx/zynqmp_power.c | 151 +++++++++++++++++---
include/linux/firmware/xlnx-event-manager.h | 10 ++
2 files changed, 141 insertions(+), 20 deletions(-)
diff --git a/drivers/soc/xilinx/zynqmp_power.c b/drivers/soc/xilinx/zynqmp_power.c
index 8570ab1a6857..c193daf04a0a 100644
--- a/drivers/soc/xilinx/zynqmp_power.c
+++ b/drivers/soc/xilinx/zynqmp_power.c
@@ -31,9 +31,27 @@ struct zynqmp_pm_work_struct {
u32 args[CB_ARG_CNT];
};
-static struct zynqmp_pm_work_struct *zynqmp_pm_init_suspend_work;
+/**
+ * struct zynqmp_pm_event_info - event related information
+ * @cb_fun: Function pointer to store the callback function.
+ * @cb_type: Type of callback from pm_api_cb_id,
+ * PM_NOTIFY_CB - for Error Events,
+ * PM_INIT_SUSPEND_CB - for suspend callback.
+ * @node_id: Node-Id related to event.
+ * @event: Event Mask for the Error Event.
+ * @wake: Flag specifying whether the subsystem should be woken upon
+ * event notification.
+ */
+struct zynqmp_pm_event_info {
+ event_cb_func_t cb_fun;
+ enum pm_api_cb_id cb_type;
+ u32 node_id;
+ u32 event;
+ bool wake;
+};
+
+static struct zynqmp_pm_work_struct *zynqmp_pm_init_suspend_work, *zynqmp_pm_init_restart_work;
static struct mbox_chan *rx_chan;
-static bool event_registered;
enum pm_suspend_mode {
PM_SUSPEND_MODE_FIRST = 0,
@@ -55,6 +73,19 @@ static void zynqmp_pm_get_callback_data(u32 *buf)
zynqmp_pm_invoke_fn(GET_CALLBACK_DATA, buf, 0);
}
+static void subsystem_restart_event_callback(const u32 *payload, void *data)
+{
+ /* First element is callback API ID, others are callback arguments */
+ if (work_pending(&zynqmp_pm_init_restart_work->callback_work))
+ return;
+
+ /* Copy callback arguments into work's structure */
+ memcpy(zynqmp_pm_init_restart_work->args, &payload[0],
+ sizeof(zynqmp_pm_init_restart_work->args));
+
+ queue_work(system_unbound_wq, &zynqmp_pm_init_restart_work->callback_work);
+}
+
static void suspend_event_callback(const u32 *payload, void *data)
{
/* First element is callback API ID, others are callback arguments */
@@ -120,6 +151,37 @@ static void ipi_receive_callback(struct mbox_client *cl, void *data)
}
}
+/**
+ * zynqmp_pm_subsystem_restart_work_fn - Initiate Subsystem restart
+ * @work: Pointer to work_struct
+ *
+ * Bottom-half of PM callback IRQ handler.
+ */
+static void zynqmp_pm_subsystem_restart_work_fn(struct work_struct *work)
+{
+ int ret;
+ struct zynqmp_pm_work_struct *pm_work = container_of(work, struct zynqmp_pm_work_struct,
+ callback_work);
+
+ /* First element is callback API ID, others are callback arguments */
+ if (pm_work->args[0] == PM_NOTIFY_CB) {
+ if (pm_work->args[2] == EVENT_SUBSYSTEM_RESTART) {
+ ret = zynqmp_pm_system_shutdown(ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY,
+ ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM);
+ if (ret) {
+ pr_err("unable to set shutdown scope\n");
+ return;
+ }
+
+ kernel_restart(NULL);
+ } else {
+ pr_err("%s Unsupported Event - %d\n", __func__, pm_work->args[2]);
+ }
+ } else {
+ pr_err("%s() Unsupported Callback %d\n", __func__, pm_work->args[0]);
+ }
+}
+
/**
* zynqmp_pm_init_suspend_work_fn - Initialize suspend
* @work: Pointer to work_struct
@@ -185,10 +247,46 @@ static ssize_t suspend_mode_store(struct device *dev,
static DEVICE_ATTR_RW(suspend_mode);
+static void unregister_event(struct device *dev, void *res)
+{
+ struct zynqmp_pm_event_info *event_info = res;
+
+ xlnx_unregister_event(event_info->cb_type, event_info->node_id,
+ event_info->event, event_info->cb_fun, NULL);
+}
+
+static int register_event(struct device *dev, const enum pm_api_cb_id cb_type, const u32 node_id,
+ const u32 event, const bool wake, event_cb_func_t cb_fun)
+{
+ int ret;
+ struct zynqmp_pm_event_info *event_info;
+
+ event_info = devres_alloc(unregister_event, sizeof(struct zynqmp_pm_event_info),
+ GFP_KERNEL);
+ if (!event_info)
+ return -ENOMEM;
+
+ event_info->cb_type = cb_type;
+ event_info->node_id = node_id;
+ event_info->event = event;
+ event_info->wake = wake;
+ event_info->cb_fun = cb_fun;
+
+ ret = xlnx_register_event(event_info->cb_type, event_info->node_id,
+ event_info->event, event_info->wake, event_info->cb_fun, NULL);
+ if (ret) {
+ devres_free(event_info);
+ return ret;
+ }
+
+ devres_add(dev, event_info);
+ return 0;
+}
+
static int zynqmp_pm_probe(struct platform_device *pdev)
{
int ret, irq;
- u32 pm_api_version;
+ u32 pm_api_version, pm_family_code, pm_sub_family_code, node_id;
struct mbox_client *client;
ret = zynqmp_pm_get_api_version(&pm_api_version);
@@ -206,21 +304,43 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
* is not available to use) or -ENODEV(Xilinx Event Manager not compiled),
* then use ipi-mailbox or interrupt method.
*/
- ret = xlnx_register_event(PM_INIT_SUSPEND_CB, 0, 0, false,
- suspend_event_callback, NULL);
+ ret = register_event(&pdev->dev, PM_INIT_SUSPEND_CB, 0, 0, false,
+ suspend_event_callback);
if (!ret) {
zynqmp_pm_init_suspend_work = devm_kzalloc(&pdev->dev,
sizeof(struct zynqmp_pm_work_struct),
GFP_KERNEL);
- if (!zynqmp_pm_init_suspend_work) {
- xlnx_unregister_event(PM_INIT_SUSPEND_CB, 0, 0,
- suspend_event_callback, NULL);
+ if (!zynqmp_pm_init_suspend_work)
return -ENOMEM;
- }
- event_registered = true;
INIT_WORK(&zynqmp_pm_init_suspend_work->callback_work,
zynqmp_pm_init_suspend_work_fn);
+
+ ret = zynqmp_pm_get_family_info(&pm_family_code, &pm_sub_family_code);
+ if (ret < 0)
+ return ret;
+
+ if (pm_sub_family_code == VERSALNET_SUB_FAMILY_CODE)
+ node_id = PM_DEV_ACPU_0_0;
+ else
+ node_id = PM_DEV_ACPU_0;
+
+ ret = register_event(&pdev->dev, PM_NOTIFY_CB, node_id, EVENT_SUBSYSTEM_RESTART,
+ false, subsystem_restart_event_callback);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to Register with Xilinx Event manager %d\n",
+ ret);
+ return ret;
+ }
+
+ zynqmp_pm_init_restart_work = devm_kzalloc(&pdev->dev,
+ sizeof(struct zynqmp_pm_work_struct),
+ GFP_KERNEL);
+ if (!zynqmp_pm_init_restart_work)
+ return -ENOMEM;
+
+ INIT_WORK(&zynqmp_pm_init_restart_work->callback_work,
+ zynqmp_pm_subsystem_restart_work_fn);
} else if (ret != -EACCES && ret != -ENODEV) {
dev_err(&pdev->dev, "Failed to Register with Xilinx Event manager %d\n", ret);
return ret;
@@ -267,15 +387,8 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
}
ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_suspend_mode.attr);
- if (ret) {
- if (event_registered) {
- xlnx_unregister_event(PM_INIT_SUSPEND_CB, 0, 0, suspend_event_callback,
- NULL);
- event_registered = false;
- }
- dev_err(&pdev->dev, "unable to create sysfs interface\n");
+ if (ret)
return ret;
- }
return 0;
}
@@ -283,8 +396,6 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
static void zynqmp_pm_remove(struct platform_device *pdev)
{
sysfs_remove_file(&pdev->dev.kobj, &dev_attr_suspend_mode.attr);
- if (event_registered)
- xlnx_unregister_event(PM_INIT_SUSPEND_CB, 0, 0, suspend_event_callback, NULL);
if (!rx_chan)
mbox_free_channel(rx_chan);
diff --git a/include/linux/firmware/xlnx-event-manager.h b/include/linux/firmware/xlnx-event-manager.h
index 82e8254b0f80..645dd34155e6 100644
--- a/include/linux/firmware/xlnx-event-manager.h
+++ b/include/linux/firmware/xlnx-event-manager.h
@@ -1,4 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx Event Management Driver
+ *
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ */
#ifndef _FIRMWARE_XLNX_EVENT_MANAGER_H_
#define _FIRMWARE_XLNX_EVENT_MANAGER_H_
@@ -7,6 +12,11 @@
#define CB_MAX_PAYLOAD_SIZE (4U) /*In payload maximum 32bytes */
+#define EVENT_SUBSYSTEM_RESTART (4U)
+
+#define PM_DEV_ACPU_0_0 (0x1810c0afU)
+#define PM_DEV_ACPU_0 (0x1810c003U)
+
/************************** Exported Function *****************************/
typedef void (*event_cb_func_t)(const u32 *payload, void *data);
--
2.17.1
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^ permalink raw reply related [relevance 10%]
* [PATCH V2 3/3] tty: serial: uartps: Add support for uartps controller reset
@ 2024-04-24 11:29 6% ` Manikanta Guntupalli
0 siblings, 0 replies; 200+ results
From: Manikanta Guntupalli @ 2024-04-24 11:29 UTC (permalink / raw)
To: git, gregkh, jirislaby, robh, krzk+dt, conor+dt, michal.simek,
p.zabel, laurent.pinchart, radhey.shyam.pandey, parth.gajjar,
u.kleine-koenig, tglx, julien.malik, ruanjinjie, linux-kernel,
linux-serial, devicetree, linux-arm-kernel
Cc: srinivas.goud, shubhrajyoti.datta, manion05gk, Manikanta Guntupalli
Add support for an optional reset for the uartps controller using
the reset driver. If the uartps node contains the "resets" property,
then cdns_uart_startup performs uartps controller non-pulse out of reset
and reset in exit path.
Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
---
Changes for V2:
Remove check for reset_control_deassert, as reset_control_deassert
function internally has NULL check
---
drivers/tty/serial/xilinx_uartps.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
index de3487206bcb..2acfcea403ce 100644
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -25,6 +25,7 @@
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/delay.h>
+#include <linux/reset.h>
#define CDNS_UART_TTY_NAME "ttyPS"
#define CDNS_UART_NAME "xuartps"
@@ -198,6 +199,7 @@ MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
* @gpiod_rts: Pointer to the gpio descriptor
* @rs485_tx_started: RS485 tx state
* @tx_timer: Timer for tx
+ * @rstc: Pointer to the reset control
*/
struct cdns_uart {
struct uart_port *port;
@@ -211,6 +213,7 @@ struct cdns_uart {
struct gpio_desc *gpiod_rts;
bool rs485_tx_started;
struct hrtimer tx_timer;
+ struct reset_control *rstc;
};
struct cdns_platform_data {
u32 quirks;
@@ -948,6 +951,10 @@ static int cdns_uart_startup(struct uart_port *port)
is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
+ ret = reset_control_deassert(cdns_uart->rstc);
+ if (ret)
+ return ret;
+
uart_port_lock_irqsave(port, &flags);
/* Disable the TX and RX */
@@ -1721,6 +1728,13 @@ static int cdns_uart_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
}
+ cdns_uart_data->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(cdns_uart_data->rstc)) {
+ rc = PTR_ERR(cdns_uart_data->rstc);
+ dev_err_probe(&pdev->dev, rc, "Cannot get UART reset\n");
+ goto err_out_unregister_driver;
+ }
+
rc = clk_prepare_enable(cdns_uart_data->pclk);
if (rc) {
dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
@@ -1881,6 +1895,7 @@ static void cdns_uart_remove(struct platform_device *pdev)
if (console_port == port)
console_port = NULL;
#endif
+ reset_control_assert(cdns_uart_data->rstc);
if (!--instances)
uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
--
2.25.1
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^ permalink raw reply related [relevance 6%]
* Re: [PATCH v3 3/3] spi: airoha: add SPI-NAND Flash controller driver
2024-04-23 23:51 0% ` Andy Shevchenko
@ 2024-04-24 10:06 0% ` Lorenzo Bianconi
0 siblings, 0 replies; 200+ results
From: Lorenzo Bianconi @ 2024-04-24 10:06 UTC (permalink / raw)
To: Andy Shevchenko
Cc: linux-spi, conor, broonie, lorenzo.bianconi83, linux-arm-kernel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, devicetree, nbd, john,
dd, catalin.marinas, will, upstream, angelogioacchino.delregno
[-- Attachment #1.1: Type: text/plain, Size: 6683 bytes --]
> Tue, Apr 23, 2024 at 12:16:37PM +0200, Lorenzo Bianconi kirjoitti:
> > Introduce support for SPI-NAND driver of the Airoha NAND Flash Interface
> > found on Airoha ARM SoCs.
>
> ...
>
> > +#include <linux/bitfield.h>
> > +#include <linux/clk.h>
> > +#include <linux/device.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/init.h>
> > +#include <linux/iopoll.h>
>
> > +#include <linux/kernel.h>
>
> Make sure you are using exact headers you need, this one seems "proxy" and not
> really in use here.
>
> (Quite likely you wanted minmax.h, types.h, and possible others.)
ack, I will fix it.
>
> > +#include <linux/module.h>
> > +#include <linux/mutex.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +#include <linux/spi/spi.h>
> > +#include <linux/spi/spi-mem.h>
>
> ...
>
> > +#define SPI_NFI_ALL_IRQ_EN (SPI_NFI_RD_DONE_EN | \
> > + SPI_NFI_WR_DONE_EN | \
> > + SPI_NFI_RST_DONE_EN | \
> > + SPI_NFI_ERASE_DONE_EN | \
> > + SPI_NFI_BUSY_RETURN_EN | \
> > + SPI_NFI_ACCESS_LOCK_EN | \
> > + SPI_NFI_AHB_DONE_EN)
>
> What about writing this as
>
> #define SPI_NFI_ALL_IRQ_EN \
> (SPI_NFI_RD_DONE_EN | SPI_NFI_WR_DONE_EN | \
> SPI_NFI_RST_DONE_EN | SPI_NFI_ERASE_DONE_EN | \
> SPI_NFI_BUSY_RETURN_EN | SPI_NFI_ACCESS_LOCK_EN | \
> SPI_NFI_AHB_DONE_EN)
>
> ?
no strong opinion about it, I will fix it.
>
> ...
>
> > +enum airoha_snand_mode {
> > + SPI_MODE_AUTO,
> > + SPI_MODE_MANUAL,
> > + SPI_MODE_DMA,
> > + SPI_MODE_NO
>
> Is _NO a termination entry? Meaning there always be only 3 modes no matter
> what. If not, leave the trailing comma as it helps to reduce a burden in case
> this list will be expanded.
I think we can get rid of it
>
> > +};
>
> ...
>
> > +struct airoha_snand_dev {
> > + size_t buf_len;
> > +
> > + u8 *txrx_buf;
> > + dma_addr_t dma_addr;
> > +
> > + bool data_need_update;
> > + u64 cur_page_num;
> > +};
>
> Most likely `pahole` shows better layout to save a few bytes in some cases.
ack, I think we can swap data_need_update and cur_page_num.
>
> ...
>
> > +struct airoha_snand_ctrl {
> > + struct device *dev;
> > + struct regmap *regmap_ctrl;
> > + struct regmap *regmap_nfi;
> > + struct clk *spi_clk;
> > +
> > + struct {
> > + size_t page_size;
> > + size_t sec_size;
>
> > + unsigned char sec_num;
> > + unsigned char spare_size;
>
> Hmm... Why not u8 for both of these?
ack, I will fix it.
>
> > + } nfi_cfg;
> > +};
>
> ...
>
> > +static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd,
> > + const u8 *data, int len)
> > +{
> > + int i = 0;
> > +
> > + while (i < len) {
>
> Seems nothing prevents you from using for-loop here as well.
ack, I will fix it.
>
> > + int data_len = min(len, MAX_TRANSFER_SIZE);
> > + int err;
> > +
> > + err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
> > + if (err)
> > + return err;
> > +
> > + err = airoha_snand_write_data_to_fifo(as_ctrl, &data[i],
> > + data_len);
> > + if (err < 0)
> > + return err;
> > +
> > + i += data_len;
> > + }
> > +
> > + return 0;
> > +}
>
> ...
>
> > +static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data,
> > + int len)
>
> As per above.
ack, I will fix it.
>
> ...
>
> > + /* addr part */
> > + for (i = 0; i < op->addr.nbytes; i++) {
> > + u8 cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
> > +
> > + data = op->addr.val >> ((op->addr.nbytes - i - 1) * 8);
>
> Seems like you wanted to have always the same endianess and hence can be done
> outside the loop via cpu_to_xxx()?
sorry, I did not get what you mean here, data value relies on the loop
iteration.
>
> > + err = airoha_snand_write_data(as_ctrl, cmd, &data,
> > + sizeof(data));
> > + if (err)
> > + return err;
> > + }
>
> ...
>
> > +static int airoha_snand_setup(struct spi_device *spi)
> > +{
> > + struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
> > + struct airoha_snand_ctrl *as_ctrl;
> > +
> > + as_dev = kzalloc(sizeof(*as_dev), GFP_KERNEL);
> > + if (!as_dev)
> > + return -ENOMEM;
> > +
> > + spi_set_ctldata(spi, as_dev);
> > + as_dev->data_need_update = true;
> > +
> > + /* prepare device buffer */
> > + as_dev->buf_len = SPI_NAND_CACHE_SIZE;
> > + as_dev->txrx_buf = kzalloc(as_dev->buf_len, GFP_KERNEL);
> > + if (!as_dev->txrx_buf)
> > + goto error_dev_free;
> > +
> > + as_ctrl = spi_controller_get_devdata(spi->controller);
> > + as_dev->dma_addr = dma_map_single(as_ctrl->dev, as_dev->txrx_buf,
> > + as_dev->buf_len, DMA_BIDIRECTIONAL);
> > + if (dma_mapping_error(as_ctrl->dev, as_dev->dma_addr))
> > + goto error_buf_free;
> > +
> > + return 0;
> > +
> > +error_buf_free:
> > + kfree(as_dev->txrx_buf);
> > +error_dev_free:
> > + kfree(as_dev);
>
> Why not utilising cleanup.h? (__free(), no_free_ptr(), etc)
I guess we can just allocate as_dev and as_dev->txrx_buf with devm_kzalloc()
here, agree?
>
> > + return -EINVAL;
> > +}
>
> ...
>
> > + err = regmap_read(as_ctrl->regmap_nfi,
> > + REG_SPI_NFI_SECCUS_SIZE, &val);
>
> One line?
ack, I will fix it.
>
> > + if (err)
> > + return err;
>
> ...
>
> > + as_ctrl->nfi_cfg.page_size = rounddown(sec_size * sec_num, 1024);
>
> round_down() is optimised for power-of-2.
> You would need to include math.h IIRC.
ack, I will fix it.
>
> ...
>
> > + as_ctrl->regmap_ctrl = devm_regmap_init_mmio(&pdev->dev, base,
> > + &spi_ctrl_regmap_config);
>
> With help of
>
> struct device *dev = &pdev->dev;
>
> at the top of the function the entire code will become neater.
ack, I will fix it.
>
> > + if (IS_ERR(as_ctrl->regmap_ctrl)) {
> > + dev_err(&pdev->dev, "failed to init spi ctrl regmap: %ld\n",
> > + PTR_ERR(as_ctrl->regmap_ctrl));
> > + return PTR_ERR(as_ctrl->regmap_ctrl);
>
> return dev_err_probe(...);
>
> > + }
>
> ...
>
> > + dev_err(&pdev->dev, "failed to init spi nfi regmap: %ld\n",
> > + PTR_ERR(as_ctrl->regmap_nfi));
> > + return PTR_ERR(as_ctrl->regmap_nfi);
>
> return dev_err_probe(...);
>
> ...
>
> > + dev_err(&pdev->dev, "unable to get spi clk");
> > + return PTR_ERR(as_ctrl->spi_clk);
>
> Ditto.
>
> ...
>
> > +
>
> Unneeded blank line.
ack, I will fix it.
Regards,
Lorenzo
>
> > +module_platform_driver(airoha_snand_driver);
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply [relevance 0%]
* [PATCH] soc: xilinx: Add cb event for subsystem restart
@ 2024-04-24 9:59 10% Jay Buddhabhatti
2024-04-24 12:49 10% ` [PATCH v2] " Jay Buddhabhatti
0 siblings, 1 reply; 200+ results
From: Jay Buddhabhatti @ 2024-04-24 9:59 UTC (permalink / raw)
To: michal.simek; +Cc: linux-arm-kernel, linux-kernel, Jay Buddhabhatti
Add support to register subsystem restart events from firmware for Versal
and Versal NET platforms. This event is received when firmware requests
for subsystem restart. After receiving this event, the kernel needs to be
restarted.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
---
drivers/soc/xilinx/zynqmp_power.c | 151 +++++++++++++++++---
include/linux/firmware/xlnx-event-manager.h | 12 ++
2 files changed, 143 insertions(+), 20 deletions(-)
diff --git a/drivers/soc/xilinx/zynqmp_power.c b/drivers/soc/xilinx/zynqmp_power.c
index 8570ab1a6857..c193daf04a0a 100644
--- a/drivers/soc/xilinx/zynqmp_power.c
+++ b/drivers/soc/xilinx/zynqmp_power.c
@@ -31,9 +31,27 @@ struct zynqmp_pm_work_struct {
u32 args[CB_ARG_CNT];
};
-static struct zynqmp_pm_work_struct *zynqmp_pm_init_suspend_work;
+/**
+ * struct zynqmp_pm_event_info - event related information
+ * @cb_fun: Function pointer to store the callback function.
+ * @cb_type: Type of callback from pm_api_cb_id,
+ * PM_NOTIFY_CB - for Error Events,
+ * PM_INIT_SUSPEND_CB - for suspend callback.
+ * @node_id: Node-Id related to event.
+ * @event: Event Mask for the Error Event.
+ * @wake: Flag specifying whether the subsystem should be woken upon
+ * event notification.
+ */
+struct zynqmp_pm_event_info {
+ event_cb_func_t cb_fun;
+ enum pm_api_cb_id cb_type;
+ u32 node_id;
+ u32 event;
+ bool wake;
+};
+
+static struct zynqmp_pm_work_struct *zynqmp_pm_init_suspend_work, *zynqmp_pm_init_restart_work;
static struct mbox_chan *rx_chan;
-static bool event_registered;
enum pm_suspend_mode {
PM_SUSPEND_MODE_FIRST = 0,
@@ -55,6 +73,19 @@ static void zynqmp_pm_get_callback_data(u32 *buf)
zynqmp_pm_invoke_fn(GET_CALLBACK_DATA, buf, 0);
}
+static void subsystem_restart_event_callback(const u32 *payload, void *data)
+{
+ /* First element is callback API ID, others are callback arguments */
+ if (work_pending(&zynqmp_pm_init_restart_work->callback_work))
+ return;
+
+ /* Copy callback arguments into work's structure */
+ memcpy(zynqmp_pm_init_restart_work->args, &payload[0],
+ sizeof(zynqmp_pm_init_restart_work->args));
+
+ queue_work(system_unbound_wq, &zynqmp_pm_init_restart_work->callback_work);
+}
+
static void suspend_event_callback(const u32 *payload, void *data)
{
/* First element is callback API ID, others are callback arguments */
@@ -120,6 +151,37 @@ static void ipi_receive_callback(struct mbox_client *cl, void *data)
}
}
+/**
+ * zynqmp_pm_subsystem_restart_work_fn - Initiate Subsystem restart
+ * @work: Pointer to work_struct
+ *
+ * Bottom-half of PM callback IRQ handler.
+ */
+static void zynqmp_pm_subsystem_restart_work_fn(struct work_struct *work)
+{
+ int ret;
+ struct zynqmp_pm_work_struct *pm_work = container_of(work, struct zynqmp_pm_work_struct,
+ callback_work);
+
+ /* First element is callback API ID, others are callback arguments */
+ if (pm_work->args[0] == PM_NOTIFY_CB) {
+ if (pm_work->args[2] == EVENT_SUBSYSTEM_RESTART) {
+ ret = zynqmp_pm_system_shutdown(ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY,
+ ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM);
+ if (ret) {
+ pr_err("unable to set shutdown scope\n");
+ return;
+ }
+
+ kernel_restart(NULL);
+ } else {
+ pr_err("%s Unsupported Event - %d\n", __func__, pm_work->args[2]);
+ }
+ } else {
+ pr_err("%s() Unsupported Callback %d\n", __func__, pm_work->args[0]);
+ }
+}
+
/**
* zynqmp_pm_init_suspend_work_fn - Initialize suspend
* @work: Pointer to work_struct
@@ -185,10 +247,46 @@ static ssize_t suspend_mode_store(struct device *dev,
static DEVICE_ATTR_RW(suspend_mode);
+static void unregister_event(struct device *dev, void *res)
+{
+ struct zynqmp_pm_event_info *event_info = res;
+
+ xlnx_unregister_event(event_info->cb_type, event_info->node_id,
+ event_info->event, event_info->cb_fun, NULL);
+}
+
+static int register_event(struct device *dev, const enum pm_api_cb_id cb_type, const u32 node_id,
+ const u32 event, const bool wake, event_cb_func_t cb_fun)
+{
+ int ret;
+ struct zynqmp_pm_event_info *event_info;
+
+ event_info = devres_alloc(unregister_event, sizeof(struct zynqmp_pm_event_info),
+ GFP_KERNEL);
+ if (!event_info)
+ return -ENOMEM;
+
+ event_info->cb_type = cb_type;
+ event_info->node_id = node_id;
+ event_info->event = event;
+ event_info->wake = wake;
+ event_info->cb_fun = cb_fun;
+
+ ret = xlnx_register_event(event_info->cb_type, event_info->node_id,
+ event_info->event, event_info->wake, event_info->cb_fun, NULL);
+ if (ret) {
+ devres_free(event_info);
+ return ret;
+ }
+
+ devres_add(dev, event_info);
+ return 0;
+}
+
static int zynqmp_pm_probe(struct platform_device *pdev)
{
int ret, irq;
- u32 pm_api_version;
+ u32 pm_api_version, pm_family_code, pm_sub_family_code, node_id;
struct mbox_client *client;
ret = zynqmp_pm_get_api_version(&pm_api_version);
@@ -206,21 +304,43 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
* is not available to use) or -ENODEV(Xilinx Event Manager not compiled),
* then use ipi-mailbox or interrupt method.
*/
- ret = xlnx_register_event(PM_INIT_SUSPEND_CB, 0, 0, false,
- suspend_event_callback, NULL);
+ ret = register_event(&pdev->dev, PM_INIT_SUSPEND_CB, 0, 0, false,
+ suspend_event_callback);
if (!ret) {
zynqmp_pm_init_suspend_work = devm_kzalloc(&pdev->dev,
sizeof(struct zynqmp_pm_work_struct),
GFP_KERNEL);
- if (!zynqmp_pm_init_suspend_work) {
- xlnx_unregister_event(PM_INIT_SUSPEND_CB, 0, 0,
- suspend_event_callback, NULL);
+ if (!zynqmp_pm_init_suspend_work)
return -ENOMEM;
- }
- event_registered = true;
INIT_WORK(&zynqmp_pm_init_suspend_work->callback_work,
zynqmp_pm_init_suspend_work_fn);
+
+ ret = zynqmp_pm_get_family_info(&pm_family_code, &pm_sub_family_code);
+ if (ret < 0)
+ return ret;
+
+ if (pm_sub_family_code == VERSALNET_SUB_FAMILY_CODE)
+ node_id = PM_DEV_ACPU_0_0;
+ else
+ node_id = PM_DEV_ACPU_0;
+
+ ret = register_event(&pdev->dev, PM_NOTIFY_CB, node_id, EVENT_SUBSYSTEM_RESTART,
+ false, subsystem_restart_event_callback);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to Register with Xilinx Event manager %d\n",
+ ret);
+ return ret;
+ }
+
+ zynqmp_pm_init_restart_work = devm_kzalloc(&pdev->dev,
+ sizeof(struct zynqmp_pm_work_struct),
+ GFP_KERNEL);
+ if (!zynqmp_pm_init_restart_work)
+ return -ENOMEM;
+
+ INIT_WORK(&zynqmp_pm_init_restart_work->callback_work,
+ zynqmp_pm_subsystem_restart_work_fn);
} else if (ret != -EACCES && ret != -ENODEV) {
dev_err(&pdev->dev, "Failed to Register with Xilinx Event manager %d\n", ret);
return ret;
@@ -267,15 +387,8 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
}
ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_suspend_mode.attr);
- if (ret) {
- if (event_registered) {
- xlnx_unregister_event(PM_INIT_SUSPEND_CB, 0, 0, suspend_event_callback,
- NULL);
- event_registered = false;
- }
- dev_err(&pdev->dev, "unable to create sysfs interface\n");
+ if (ret)
return ret;
- }
return 0;
}
@@ -283,8 +396,6 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
static void zynqmp_pm_remove(struct platform_device *pdev)
{
sysfs_remove_file(&pdev->dev.kobj, &dev_attr_suspend_mode.attr);
- if (event_registered)
- xlnx_unregister_event(PM_INIT_SUSPEND_CB, 0, 0, suspend_event_callback, NULL);
if (!rx_chan)
mbox_free_channel(rx_chan);
diff --git a/include/linux/firmware/xlnx-event-manager.h b/include/linux/firmware/xlnx-event-manager.h
index 82e8254b0f80..317e51829346 100644
--- a/include/linux/firmware/xlnx-event-manager.h
+++ b/include/linux/firmware/xlnx-event-manager.h
@@ -1,4 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx Event Management Driver
+ *
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
#ifndef _FIRMWARE_XLNX_EVENT_MANAGER_H_
#define _FIRMWARE_XLNX_EVENT_MANAGER_H_
@@ -7,6 +14,11 @@
#define CB_MAX_PAYLOAD_SIZE (4U) /*In payload maximum 32bytes */
+#define EVENT_SUBSYSTEM_RESTART (4U)
+
+#define PM_DEV_ACPU_0_0 (0x1810c0afU)
+#define PM_DEV_ACPU_0 (0x1810c003U)
+
/************************** Exported Function *****************************/
typedef void (*event_cb_func_t)(const u32 *payload, void *data);
--
2.17.1
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^ permalink raw reply related [relevance 10%]
* [PATCH v3 3/3] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support
@ 2024-04-24 6:21 6% ` Richard Zhu
2024-04-24 21:50 0% ` Rob Herring
0 siblings, 1 reply; 200+ results
From: Richard Zhu @ 2024-04-24 6:21 UTC (permalink / raw)
To: conor, vkoul, kishon, robh+dt, krzysztof.kozlowski+dt, frank.li,
conor+dt
Cc: hongxing.zhu, linux-phy, devicetree, linux-arm-kernel,
linux-kernel, kernel, imx
Add i.MX8QM HSIO PHY driver support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/phy/freescale/Kconfig | 8 +
drivers/phy/freescale/Makefile | 1 +
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 607 ++++++++++++++++++++
3 files changed, 616 insertions(+)
create mode 100644 drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index 853958fb2c06..c9ee48aeea9e 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -35,6 +35,14 @@ config PHY_FSL_IMX8M_PCIE
Enable this to add support for the PCIE PHY as found on
i.MX8M family of SOCs.
+config PHY_FSL_IMX8QM_HSIO
+ tristate "Freescale i.MX8QM HSIO PHY"
+ depends on OF && HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Enable this to add support for the HSIO PHY as found on
+ i.MX8QM family of SOCs.
+
endif
config PHY_FSL_LYNX_28G
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index cedb328bc4d2..b56b4d5c18ea 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o
+obj-$(CONFIG_PHY_FSL_IMX8QM_HSIO) += phy-fsl-imx8qm-hsio.o
obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o
diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
new file mode 100644
index 000000000000..b3e17163e859
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
@@ -0,0 +1,607 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/pci_regs.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/pcie.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#define MAX_NUM_PHY_MIXS 4
+#define PHY_MIX_MAX_NUM_LANES 2
+#define LANE_NUM_CLKS 5
+
+/* Parameters for the waiting for PCIe PHY PLL to lock */
+#define PHY_INIT_WAIT_USLEEP_MAX 10
+#define PHY_INIT_WAIT_TIMEOUT (1000 * PHY_INIT_WAIT_USLEEP_MAX)
+
+/* i.MX8Q HSIO registers */
+#define HSIO_CTRL0 0x0
+#define HSIO_APB_RSTN_0 BIT(0)
+#define HSIO_APB_RSTN_1 BIT(1)
+#define HSIO_PIPE_RSTN_0_MASK GENMASK(25, 24)
+#define HSIO_PIPE_RSTN_1_MASK GENMASK(27, 26)
+#define HSIO_MODE_MASK GENMASK(20, 17)
+#define HSIO_MODE_PCIE 0x0
+#define HSIO_MODE_SATA 0x4
+#define HSIO_DEVICE_TYPE_MASK GENMASK(27, 24)
+#define HSIO_EPCS_TXDEEMP BIT(5)
+#define HSIO_EPCS_TXDEEMP_SEL BIT(6)
+#define HSIO_EPCS_PHYRESET_N BIT(7)
+#define HSIO_RESET_N BIT(12)
+
+#define HSIO_IOB_RXENA BIT(0)
+#define HSIO_IOB_TXENA BIT(1)
+#define HSIO_IOB_A_0_TXOE BIT(2)
+#define HSIO_IOB_A_0_M1M0_2 BIT(4)
+#define HSIO_IOB_A_0_M1M0_MASK GENMASK(4, 3)
+#define HSIO_PHYX1_EPCS_SEL BIT(12)
+#define HSIO_PCIE_AB_SELECT BIT(13)
+
+#define HSIO_PHY_STS0 0x4
+#define HSIO_LANE0_TX_PLL_LOCK BIT(4)
+#define HSIO_LANE1_TX_PLL_LOCK BIT(12)
+
+#define HSIO_CTRL2 0x8
+#define HSIO_LTSSM_ENABLE BIT(4)
+#define HSIO_BUTTON_RST_N BIT(21)
+#define HSIO_PERST_N BIT(22)
+#define HSIO_POWER_UP_RST_N BIT(23)
+
+#define HSIO_PCIE_STS0 0xc
+#define HSIO_PM_REQ_CORE_RST BIT(19)
+
+#define HSIO_REG48_PMA_STATUS 0x30
+#define HSIO_REG48_PMA_RDY BIT(7)
+
+/*
+ * There are three lanes PHY in i.MX8QM HSIO, and can be made up the
+ * following PHY modes in different use cases.
+ * +------------------------------------+
+ * | index | LAN0 | LAN1 | LAN2 |
+ * |------------------------------------|
+ * | 0 | PCIEA | | |
+ * |------------------------------------|
+ * | 1 | | PCIEB | |
+ * |------------------------------------|
+ * | 2 | PCIEA | PCIEA | |
+ * |------------------------------------|
+ * | 3 | | | PCIEB/SATA |
+ * +------------------------------------+
+ */
+enum phy_mode_index {
+ IMX8Q_HSIO_LANE0_PCIE_PHY,
+ IMX8Q_HSIO_LANE1_PCIE_PHY,
+ IMX8Q_HSIO_LANE0_1_PCIE_PHY,
+ IMX8Q_HSIO_LANE2_PHY
+};
+
+struct imx_hsio_drvdata {
+ int phy_mix_num;
+};
+
+struct imx_hsio_phy_lane {
+ const char * const *clk_names;
+ struct clk_bulk_data clks[LANE_NUM_CLKS];
+};
+
+struct imx_hsio_phy_mix {
+ u32 ctrl_index;
+ u32 ctrl_off;
+ u32 phy_off;
+ u32 phy_type;
+ struct imx_hsio_phy_lane lane[PHY_MIX_MAX_NUM_LANES];
+ struct imx_hsio_priv *priv;
+ struct phy *phy;
+ enum phy_mode pmix_mode;
+ enum phy_mode_index idx;
+};
+
+struct imx_hsio_priv {
+ void __iomem *base;
+ struct device *dev;
+ u32 refclk_pad;
+ u32 hsio_cfg;
+ struct regmap *phy;
+ struct regmap *ctrl;
+ struct regmap *misc;
+ const struct imx_hsio_drvdata *drvdata;
+ struct imx_hsio_phy_mix pmix[MAX_NUM_PHY_MIXS];
+};
+
+static const char * const lan0_pcie_clks[] = {"apb_pclk0", "pclk0", "ctl0_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan1_pciea_clks[] = {"apb_pclk1", "pclk1", "ctl0_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan1_pcieb_clks[] = {"apb_pclk1", "pclk1", "ctl1_crr",
+ "phy0_crr", "misc_crr"};
+static const char * const lan2_pcieb_clks[] = {"apb_pclk2", "pclk2", "ctl1_crr",
+ "phy1_crr", "misc_crr"};
+static const char * const lan2_sata_clks[] = {"pclk2", "epcs_tx", "epcs_rx",
+ "phy1_crr", "misc_crr"};
+
+static const struct regmap_config regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int imx_hsio_get_idx(int phy_type, int ctrl_index, int lane_mask)
+{
+ int index;
+
+ switch (phy_type) {
+ case PHY_TYPE_PCIE:
+ if (ctrl_index) { /* PCIEB */
+ if (lane_mask == IMX8Q_HSIO_LANE0) /* i.MX8QXP */
+ index = IMX8Q_HSIO_LANE0_PCIE_PHY;
+ else if (lane_mask == IMX8Q_HSIO_LANE1) /* i.MX8QM */
+ index = IMX8Q_HSIO_LANE1_PCIE_PHY;
+ else if (lane_mask == IMX8Q_HSIO_LANE2) /* i.MX8QM */
+ index = IMX8Q_HSIO_LANE2_PHY;
+ else
+ return -EINVAL;
+ } else { /* PCIEA */
+ if (lane_mask == (IMX8Q_HSIO_LANE0 | IMX8Q_HSIO_LANE1))
+ index = IMX8Q_HSIO_LANE0_1_PCIE_PHY;
+ else if (lane_mask == IMX8Q_HSIO_LANE0)
+ index = IMX8Q_HSIO_LANE0_PCIE_PHY;
+ else
+ return -EINVAL;
+ }
+ break;
+ case PHY_TYPE_SATA:
+ index = IMX8Q_HSIO_LANE2_PHY;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return index;
+}
+
+static int imx_hsio_init(struct phy *phy)
+{
+ int ret, i;
+ struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = pmix->priv;
+ struct device *dev = priv->dev;
+
+ /* Assign clocks refer to different modes */
+ switch (pmix->phy_type) {
+ case PHY_TYPE_PCIE:
+ if (pmix->ctrl_index == 0) { /* PCIEA */
+ pmix->pmix_mode = PHY_MODE_PCIE;
+ pmix->ctrl_off = 0;
+ pmix->phy_off = 0;
+
+ for (i = 0; i < LANE_NUM_CLKS; i++) {
+ if (pmix->idx == IMX8Q_HSIO_LANE0_PCIE_PHY) {
+ pmix->lane[0].clks[i].id = lan0_pcie_clks[i];
+ } else { /* 2 lanes are bound to PCIEA */
+ pmix->lane[0].clks[i].id = lan0_pcie_clks[i];
+ pmix->lane[1].clks[i].id = lan1_pciea_clks[i];
+ }
+ }
+ } else { /* PCIEB */
+ pmix->pmix_mode = PHY_MODE_PCIE;
+ if (pmix->idx == IMX8Q_HSIO_LANE0_PCIE_PHY) {
+ /* i.MX8QXP */
+ pmix->ctrl_off = 0;
+ pmix->phy_off = 0;
+ } else {
+ /*
+ * On i.MX8QM, only second or third lane can be
+ * bound to PCIEB.
+ */
+ pmix->ctrl_off = SZ_64K;
+ if (pmix->idx == IMX8Q_HSIO_LANE1_PCIE_PHY)
+ pmix->phy_off = 0;
+ else /* the third lane is bound to PCIEB */
+ pmix->phy_off = SZ_64K;
+ }
+
+ for (i = 0; i < LANE_NUM_CLKS; i++) {
+ if (pmix->idx == IMX8Q_HSIO_LANE1_PCIE_PHY)
+ pmix->lane[0].clks[i].id = lan1_pcieb_clks[i];
+ else if (pmix->idx == IMX8Q_HSIO_LANE2_PHY)
+ pmix->lane[0].clks[i].id = lan2_pcieb_clks[i];
+ else /* i.MX8QXP only has PCIEB, idx is 0 */
+ pmix->lane[0].clks[i].id = lan0_pcie_clks[i];
+ }
+ }
+ break;
+ case PHY_TYPE_SATA:
+ /* On i.MX8QM, only the third lane can be bound to SATA */
+ pmix->ctrl_off = SZ_128K;
+ pmix->pmix_mode = PHY_MODE_SATA;
+ pmix->phy_off = SZ_64K;
+
+ for (i = 0; i < LANE_NUM_CLKS; i++)
+ pmix->lane[0].clks[i].id = lan2_sata_clks[i];
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Fetch clocks and enable them */
+ ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, pmix->lane[0].clks);
+ if (ret)
+ return ret;
+ if (pmix->idx == IMX8Q_HSIO_LANE0_1_PCIE_PHY) {
+ ret = devm_clk_bulk_get(dev, LANE_NUM_CLKS, pmix->lane[1].clks);
+ if (ret)
+ return ret;
+ }
+ ret = clk_bulk_prepare_enable(LANE_NUM_CLKS, pmix->lane[0].clks);
+ if (ret)
+ return ret;
+ if (pmix->idx == IMX8Q_HSIO_LANE0_1_PCIE_PHY) {
+ /* Enable the second lane's clocks */
+ ret = clk_bulk_prepare_enable(LANE_NUM_CLKS,
+ pmix->lane[1].clks);
+ if (ret) {
+ clk_bulk_disable_unprepare(LANE_NUM_CLKS,
+ pmix->lane[0].clks);
+ return ret;
+ }
+ }
+
+ /* allow the clocks to stabilize */
+ usleep_range(200, 500);
+ return 0;
+}
+
+static int imx_hsio_exit(struct phy *phy)
+{
+ struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
+
+ clk_bulk_disable_unprepare(LANE_NUM_CLKS, pmix->lane[0].clks);
+ if (pmix->idx == IMX8Q_HSIO_LANE0_1_PCIE_PHY)
+ /* Disable the clocks used by sencond lane of the PHY */
+ clk_bulk_disable_unprepare(LANE_NUM_CLKS, pmix->lane[1].clks);
+
+ return 0;
+}
+
+static void imx_hsio_pcie_phy_resets(struct phy *phy)
+{
+ struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = pmix->priv;
+
+ regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+ regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
+ HSIO_BUTTON_RST_N);
+ regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
+ HSIO_PERST_N);
+ regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
+ HSIO_POWER_UP_RST_N);
+
+ if (pmix->idx == IMX8Q_HSIO_LANE0_1_PCIE_PHY) {
+ regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_0);
+ regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_0_MASK);
+ regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_1);
+ regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_1_MASK);
+ } else if (pmix->idx == IMX8Q_HSIO_LANE1_PCIE_PHY) {
+ /* The second pmix */
+ regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_1);
+ regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_1_MASK);
+ } else {
+ regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_0);
+ regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
+ HSIO_PIPE_RSTN_0_MASK);
+ }
+}
+
+static void imx_hsio_sata_phy_resets(struct phy *phy)
+{
+ struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = pmix->priv;
+
+ /* clear PHY RST, then set it */
+ regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_PHYRESET_N);
+ regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_PHYRESET_N);
+
+ /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
+ regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
+ udelay(1);
+ regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
+ HSIO_RESET_N);
+ regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, HSIO_RESET_N);
+}
+
+static void imx_hsio_configure_clk_pad(struct phy *phy)
+{
+ bool pll = false;
+ u32 pad_mode;
+ struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = pmix->priv;
+
+ pad_mode = priv->refclk_pad;
+ if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) {
+ pll = true;
+ regmap_update_bits(priv->misc, HSIO_CTRL0,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK,
+ HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_2);
+ }
+
+ regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_RXENA,
+ pll ? 0 : HSIO_IOB_RXENA);
+ regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_TXENA,
+ pll ? HSIO_IOB_TXENA : 0);
+}
+
+static int imx_hsio_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, addr, cond;
+ struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = pmix->priv;
+
+ if (pmix->pmix_mode == PHY_MODE_PCIE)
+ imx_hsio_pcie_phy_resets(phy);
+ else /* SATA */
+ regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
+ HSIO_APB_RSTN_0);
+
+ if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2PCIEB)
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT);
+ if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2SATA)
+ regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL);
+
+ imx_hsio_configure_clk_pad(phy);
+
+ if (pmix->pmix_mode == PHY_MODE_SATA) {
+ regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP);
+ regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
+ HSIO_EPCS_TXDEEMP_SEL);
+
+ imx_hsio_sata_phy_resets(phy);
+ } else {
+ /* Toggle apb_pclk to make sure PM_REQ_CORE_RST is cleared. */
+ clk_disable_unprepare(pmix->lane[0].clks[0].clk);
+ mdelay(1);
+ ret = clk_prepare_enable(pmix->lane[0].clks[0].clk);
+ if (ret) {
+ dev_err(priv->dev, "unable to enable phy apb_pclk\n");
+ return ret;
+ }
+
+ addr = pmix->ctrl_off + HSIO_PCIE_STS0;
+ cond = HSIO_PM_REQ_CORE_RST;
+ ret = regmap_read_poll_timeout(priv->ctrl, addr, val,
+ (val & cond) == 0,
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT);
+ if (ret) {
+ dev_err(priv->dev, "HSIO_PM_REQ_CORE_RST is set\n");
+ return ret;
+ }
+ }
+
+ /* Polling to check the PHY is ready or not. */
+ if (pmix->idx == IMX8Q_HSIO_LANE1_PCIE_PHY)
+ cond = HSIO_LANE1_TX_PLL_LOCK;
+ else
+ cond = HSIO_LANE0_TX_PLL_LOCK;
+
+ ret = regmap_read_poll_timeout(priv->phy, pmix->phy_off + HSIO_PHY_STS0,
+ val, ((val & cond) == cond),
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT);
+ if (ret) {
+ dev_err(priv->dev, "IMX8Q PHY%d PLL lock timeout\n", pmix->idx);
+ return ret;
+ }
+ dev_info(priv->dev, "IMX8Q PHY%d PLL is locked\n", pmix->idx);
+
+ if (pmix->pmix_mode == PHY_MODE_SATA) {
+ cond = HSIO_REG48_PMA_RDY;
+ ret = read_poll_timeout(readb, val, ((val & cond) == cond),
+ PHY_INIT_WAIT_USLEEP_MAX,
+ PHY_INIT_WAIT_TIMEOUT, false,
+ priv->base + HSIO_REG48_PMA_STATUS);
+ if (ret)
+ dev_err(priv->dev, "PHY calibration is timeout\n");
+ else
+ dev_info(priv->dev, "PHY calibration is done\n");
+ }
+
+ return ret;
+}
+
+static int imx_hsio_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ u32 val;
+ struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = pmix->priv;
+
+ if (pmix->pmix_mode != mode)
+ return -EINVAL;
+
+ val = (mode == PHY_MODE_PCIE) ? HSIO_MODE_PCIE : HSIO_MODE_SATA;
+ val = FIELD_PREP(HSIO_MODE_MASK, val);
+ regmap_update_bits(priv->phy, pmix->phy_off + HSIO_CTRL0,
+ HSIO_MODE_MASK, val);
+
+ switch (submode) {
+ case PHY_MODE_PCIE_RC:
+ val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
+ break;
+ case PHY_MODE_PCIE_EP:
+ val = FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ENDPOINT);
+ break;
+ default: /* Support only PCIe EP and RC now. */
+ return 0;
+ }
+ if (submode)
+ regmap_update_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0,
+ HSIO_DEVICE_TYPE_MASK, val);
+
+ return 0;
+}
+
+static int imx_hsio_set_speed(struct phy *phy, int speed)
+{
+ struct imx_hsio_phy_mix *pmix = phy_get_drvdata(phy);
+ struct imx_hsio_priv *priv = pmix->priv;
+
+ regmap_update_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2,
+ HSIO_LTSSM_ENABLE,
+ speed ? HSIO_LTSSM_ENABLE : 0);
+ return 0;
+}
+
+static const struct phy_ops imx_hsio_ops = {
+ .init = imx_hsio_init,
+ .exit = imx_hsio_exit,
+ .power_on = imx_hsio_power_on,
+ .set_mode = imx_hsio_set_mode,
+ .set_speed = imx_hsio_set_speed,
+ .owner = THIS_MODULE,
+};
+
+static const struct imx_hsio_drvdata imx8qxp_hsio_drvdata = {
+ .phy_mix_num = 0x1,
+};
+
+static const struct imx_hsio_drvdata imx_hsio_drvdata = {
+ .phy_mix_num = 0x4,
+};
+
+static const struct of_device_id imx_hsio_of_match[] = {
+ {.compatible = "fsl,imx8qm-hsio", .data = &imx_hsio_drvdata},
+ {.compatible = "fsl,imx8qxp-hsio", .data = &imx8qxp_hsio_drvdata},
+ { },
+};
+MODULE_DEVICE_TABLE(of, imx_hsio_of_match);
+
+static struct phy *imx_hsio_xlate(struct device *dev,
+ const struct of_phandle_args *args)
+{
+ struct imx_hsio_priv *priv = dev_get_drvdata(dev);
+ int phy_type = args->args[0];
+ int ctrl_index = args->args[1];
+ int idx, lane_mask = args->args[2];
+
+ idx = imx_hsio_get_idx(phy_type, ctrl_index, lane_mask);
+ if (idx < 0 || idx >= priv->drvdata->phy_mix_num)
+ return ERR_PTR(-EINVAL);
+ priv->pmix[idx].phy_type = phy_type;
+ priv->pmix[idx].ctrl_index = ctrl_index;
+ priv->pmix[idx].idx = idx;
+
+ return priv->pmix[idx].phy;
+}
+
+static int imx_hsio_probe(struct platform_device *pdev)
+{
+ int i;
+ void __iomem *off;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ const struct of_device_id *of_id;
+ struct imx_hsio_priv *priv;
+ struct phy_provider *provider;
+
+ of_id = of_match_device(imx_hsio_of_match, dev);
+ if (!of_id)
+ return -EINVAL;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ priv->dev = &pdev->dev;
+ priv->drvdata = of_device_get_match_data(dev);
+
+ /* Get HSIO configuration mode */
+ of_property_read_u32(np, "fsl,hsio-cfg", &priv->hsio_cfg);
+ /* Get PHY refclk pad mode */
+ if (of_property_read_u32(np, "fsl,refclk-pad-mode", &priv->refclk_pad))
+ priv->refclk_pad = IMX8_PCIE_REFCLK_PAD_OUTPUT;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ off = devm_platform_ioremap_resource_byname(pdev, "phy");
+ priv->phy = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->phy))
+ return dev_err_probe(dev, PTR_ERR(priv->phy),
+ "unable to find phy csr registers\n");
+
+ off = devm_platform_ioremap_resource_byname(pdev, "ctrl");
+ priv->ctrl = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->ctrl))
+ return dev_err_probe(dev, PTR_ERR(priv->ctrl),
+ "unable to find ctrl csr registers\n");
+
+ off = devm_platform_ioremap_resource_byname(pdev, "misc");
+ priv->misc = devm_regmap_init_mmio(dev, off, ®map_config);
+ if (IS_ERR(priv->misc))
+ return dev_err_probe(dev, PTR_ERR(priv->misc),
+ "unable to find misc csr registers\n");
+
+ for (i = 0; i < priv->drvdata->phy_mix_num; i++) {
+ struct imx_hsio_phy_mix *pmix = &priv->pmix[i];
+ struct phy *phy;
+
+ memset(pmix, 0, sizeof(*pmix));
+
+ phy = devm_phy_create(&pdev->dev, NULL, &imx_hsio_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ pmix->priv = priv;
+ pmix->phy = phy;
+ pmix->idx = i;
+ phy_set_drvdata(phy, pmix);
+ }
+
+ dev_set_drvdata(dev, priv);
+ dev_set_drvdata(&pdev->dev, priv);
+
+ provider = devm_of_phy_provider_register(&pdev->dev, imx_hsio_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver imx_hsio_driver = {
+ .probe = imx_hsio_probe,
+ .driver = {
+ .name = "imx8qm-hsio-phy",
+ .of_match_table = imx_hsio_of_match,
+ }
+};
+module_platform_driver(imx_hsio_driver);
+
+MODULE_DESCRIPTION("FSL IMX8QM HSIO SERDES PHY driver");
+MODULE_LICENSE("GPL");
--
2.37.1
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^ permalink raw reply related [relevance 6%]
* Re: [PATCH v3 3/3] spi: airoha: add SPI-NAND Flash controller driver
2024-04-23 10:16 2% ` [PATCH v3 3/3] spi: airoha: add SPI-NAND Flash controller driver Lorenzo Bianconi
@ 2024-04-23 23:51 0% ` Andy Shevchenko
2024-04-24 10:06 0% ` Lorenzo Bianconi
0 siblings, 1 reply; 200+ results
From: Andy Shevchenko @ 2024-04-23 23:51 UTC (permalink / raw)
To: Lorenzo Bianconi
Cc: linux-spi, conor, broonie, lorenzo.bianconi83, linux-arm-kernel,
robh+dt, krzysztof.kozlowski+dt, conor+dt, devicetree, nbd, john,
dd, catalin.marinas, will, upstream, angelogioacchino.delregno
Tue, Apr 23, 2024 at 12:16:37PM +0200, Lorenzo Bianconi kirjoitti:
> Introduce support for SPI-NAND driver of the Airoha NAND Flash Interface
> found on Airoha ARM SoCs.
...
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/device.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/init.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
Make sure you are using exact headers you need, this one seems "proxy" and not
really in use here.
(Quite likely you wanted minmax.h, types.h, and possible others.)
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/spi/spi.h>
> +#include <linux/spi/spi-mem.h>
...
> +#define SPI_NFI_ALL_IRQ_EN (SPI_NFI_RD_DONE_EN | \
> + SPI_NFI_WR_DONE_EN | \
> + SPI_NFI_RST_DONE_EN | \
> + SPI_NFI_ERASE_DONE_EN | \
> + SPI_NFI_BUSY_RETURN_EN | \
> + SPI_NFI_ACCESS_LOCK_EN | \
> + SPI_NFI_AHB_DONE_EN)
What about writing this as
#define SPI_NFI_ALL_IRQ_EN \
(SPI_NFI_RD_DONE_EN | SPI_NFI_WR_DONE_EN | \
SPI_NFI_RST_DONE_EN | SPI_NFI_ERASE_DONE_EN | \
SPI_NFI_BUSY_RETURN_EN | SPI_NFI_ACCESS_LOCK_EN | \
SPI_NFI_AHB_DONE_EN)
?
...
> +enum airoha_snand_mode {
> + SPI_MODE_AUTO,
> + SPI_MODE_MANUAL,
> + SPI_MODE_DMA,
> + SPI_MODE_NO
Is _NO a termination entry? Meaning there always be only 3 modes no matter
what. If not, leave the trailing comma as it helps to reduce a burden in case
this list will be expanded.
> +};
...
> +struct airoha_snand_dev {
> + size_t buf_len;
> +
> + u8 *txrx_buf;
> + dma_addr_t dma_addr;
> +
> + bool data_need_update;
> + u64 cur_page_num;
> +};
Most likely `pahole` shows better layout to save a few bytes in some cases.
...
> +struct airoha_snand_ctrl {
> + struct device *dev;
> + struct regmap *regmap_ctrl;
> + struct regmap *regmap_nfi;
> + struct clk *spi_clk;
> +
> + struct {
> + size_t page_size;
> + size_t sec_size;
> + unsigned char sec_num;
> + unsigned char spare_size;
Hmm... Why not u8 for both of these?
> + } nfi_cfg;
> +};
...
> +static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd,
> + const u8 *data, int len)
> +{
> + int i = 0;
> +
> + while (i < len) {
Seems nothing prevents you from using for-loop here as well.
> + int data_len = min(len, MAX_TRANSFER_SIZE);
> + int err;
> +
> + err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
> + if (err)
> + return err;
> +
> + err = airoha_snand_write_data_to_fifo(as_ctrl, &data[i],
> + data_len);
> + if (err < 0)
> + return err;
> +
> + i += data_len;
> + }
> +
> + return 0;
> +}
...
> +static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data,
> + int len)
As per above.
...
> + /* addr part */
> + for (i = 0; i < op->addr.nbytes; i++) {
> + u8 cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
> +
> + data = op->addr.val >> ((op->addr.nbytes - i - 1) * 8);
Seems like you wanted to have always the same endianess and hence can be done
outside the loop via cpu_to_xxx()?
> + err = airoha_snand_write_data(as_ctrl, cmd, &data,
> + sizeof(data));
> + if (err)
> + return err;
> + }
...
> +static int airoha_snand_setup(struct spi_device *spi)
> +{
> + struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
> + struct airoha_snand_ctrl *as_ctrl;
> +
> + as_dev = kzalloc(sizeof(*as_dev), GFP_KERNEL);
> + if (!as_dev)
> + return -ENOMEM;
> +
> + spi_set_ctldata(spi, as_dev);
> + as_dev->data_need_update = true;
> +
> + /* prepare device buffer */
> + as_dev->buf_len = SPI_NAND_CACHE_SIZE;
> + as_dev->txrx_buf = kzalloc(as_dev->buf_len, GFP_KERNEL);
> + if (!as_dev->txrx_buf)
> + goto error_dev_free;
> +
> + as_ctrl = spi_controller_get_devdata(spi->controller);
> + as_dev->dma_addr = dma_map_single(as_ctrl->dev, as_dev->txrx_buf,
> + as_dev->buf_len, DMA_BIDIRECTIONAL);
> + if (dma_mapping_error(as_ctrl->dev, as_dev->dma_addr))
> + goto error_buf_free;
> +
> + return 0;
> +
> +error_buf_free:
> + kfree(as_dev->txrx_buf);
> +error_dev_free:
> + kfree(as_dev);
Why not utilising cleanup.h? (__free(), no_free_ptr(), etc)
> + return -EINVAL;
> +}
...
> + err = regmap_read(as_ctrl->regmap_nfi,
> + REG_SPI_NFI_SECCUS_SIZE, &val);
One line?
> + if (err)
> + return err;
...
> + as_ctrl->nfi_cfg.page_size = rounddown(sec_size * sec_num, 1024);
round_down() is optimised for power-of-2.
You would need to include math.h IIRC.
...
> + as_ctrl->regmap_ctrl = devm_regmap_init_mmio(&pdev->dev, base,
> + &spi_ctrl_regmap_config);
With help of
struct device *dev = &pdev->dev;
at the top of the function the entire code will become neater.
> + if (IS_ERR(as_ctrl->regmap_ctrl)) {
> + dev_err(&pdev->dev, "failed to init spi ctrl regmap: %ld\n",
> + PTR_ERR(as_ctrl->regmap_ctrl));
> + return PTR_ERR(as_ctrl->regmap_ctrl);
return dev_err_probe(...);
> + }
...
> + dev_err(&pdev->dev, "failed to init spi nfi regmap: %ld\n",
> + PTR_ERR(as_ctrl->regmap_nfi));
> + return PTR_ERR(as_ctrl->regmap_nfi);
return dev_err_probe(...);
...
> + dev_err(&pdev->dev, "unable to get spi clk");
> + return PTR_ERR(as_ctrl->spi_clk);
Ditto.
...
> +
Unneeded blank line.
> +module_platform_driver(airoha_snand_driver);
--
With Best Regards,
Andy Shevchenko
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v2 3/4] PCI: imx6: Convert to agnostic GPIO API
2024-04-23 20:16 5% ` Frank Li
2024-04-23 20:22 0% ` Fabio Estevam
@ 2024-04-23 20:23 0% ` Frank Li
1 sibling, 0 replies; 200+ results
From: Frank Li @ 2024-04-23 20:23 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Manivannan Sadhasivam, Krzysztof Wilczyński,
Uwe Kleine-König, linux-omap, linux-pci, linux-arm-kernel,
linux-kernel, imx, linux-amlogic, linux-arm-msm, linux-tegra,
Vignesh Raghavendra, Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár
On Tue, Apr 23, 2024 at 04:16:36PM -0400, Frank Li wrote:
> On Tue, Apr 23, 2024 at 11:03:59PM +0300, Andy Shevchenko wrote:
> > On Tue, Apr 23, 2024 at 03:56:56PM -0400, Frank Li wrote:
> > > On Tue, Apr 23, 2024 at 08:19:06PM +0300, Andy Shevchenko wrote:
> >
> > ...
> >
> > > > + imx6_pcie->reset_gpiod =
> > > > + devm_gpiod_get_optional(dev, "reset",
> > > > + imx6_pcie->gpio_active_high ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW);
> > > > + if (IS_ERR(imx6_pcie->reset_gpiod))
> > > > + return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod),
> > > > + "unable to get reset gpio\n");
> > >
> > > Small problem here. err message "unable to get reset gpio\n" will print
> > > when -EPROBE_DEFER happen. EPROBE_DEFER is quite common when use i2c
> > > expand gpio chip.
> >
> > I'm not sure how you come to this conclusion. Can you elaborate, please?
> > P.S> I do not see a problem as described.
>
> If i2c gpio-expander driver have not load when imx6_pcie probe, I supposed
> devm_gpiod_get_optional() will return -EPROBE_DEFER,
>
> if (IS_ERR(imx6_pcie->reset_gpiod)) should be true. then dev_err_probe()
> will run and print "unable to get reset gpio\n" with error code
> -EPROBE_DEFER.
Sorry for that. dev_err_probe() already consider this. Please forget my
comments.
dev_err_probe()
{
if (err != -EPROBE_DEFER) {
dev_err(dev, "error %pe: %pV", ERR_PTR(err), &vaf);
}
}
So:
Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
> driver framework will retry imx6_pcie probe again when a new device appear.
> it may retry sevial times utill i2c gpio-expander driver probe success or
> timeout.
>
> Frank
>
> >
> > --
> > With Best Regards,
> > Andy Shevchenko
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v2 3/4] PCI: imx6: Convert to agnostic GPIO API
2024-04-23 20:16 5% ` Frank Li
@ 2024-04-23 20:22 0% ` Fabio Estevam
2024-04-23 20:23 0% ` Frank Li
1 sibling, 0 replies; 200+ results
From: Fabio Estevam @ 2024-04-23 20:22 UTC (permalink / raw)
To: Frank Li
Cc: Andy Shevchenko, Manivannan Sadhasivam,
Krzysztof Wilczyński, Uwe Kleine-König, linux-omap,
linux-pci, linux-arm-kernel, linux-kernel, imx, linux-amlogic,
linux-arm-msm, linux-tegra, Vignesh Raghavendra,
Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Yue Wang, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl, Xiaowei Song, Binghui Wang,
Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár
On Tue, Apr 23, 2024 at 5:16 PM Frank Li <Frank.li@nxp.com> wrote:
> if (IS_ERR(imx6_pcie->reset_gpiod)) should be true. then dev_err_probe()
> will run and print "unable to get reset gpio\n" with error code
> -EPROBE_DEFER.
dev_err_probe() will not print an error message when the error code is
-EPROBE_DEFER.
That's exactly the point of using dev_err_probe().
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^ permalink raw reply [relevance 0%]
* Re: [PATCH v2 3/4] PCI: imx6: Convert to agnostic GPIO API
2024-04-23 20:03 0% ` Andy Shevchenko
@ 2024-04-23 20:16 5% ` Frank Li
2024-04-23 20:22 0% ` Fabio Estevam
2024-04-23 20:23 0% ` Frank Li
0 siblings, 2 replies; 200+ results
From: Frank Li @ 2024-04-23 20:16 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Manivannan Sadhasivam, Krzysztof Wilczyński,
Uwe Kleine-König, linux-omap, linux-pci, linux-arm-kernel,
linux-kernel, imx, linux-amlogic, linux-arm-msm, linux-tegra,
Vignesh Raghavendra, Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár
On Tue, Apr 23, 2024 at 11:03:59PM +0300, Andy Shevchenko wrote:
> On Tue, Apr 23, 2024 at 03:56:56PM -0400, Frank Li wrote:
> > On Tue, Apr 23, 2024 at 08:19:06PM +0300, Andy Shevchenko wrote:
>
> ...
>
> > > + imx6_pcie->reset_gpiod =
> > > + devm_gpiod_get_optional(dev, "reset",
> > > + imx6_pcie->gpio_active_high ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW);
> > > + if (IS_ERR(imx6_pcie->reset_gpiod))
> > > + return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod),
> > > + "unable to get reset gpio\n");
> >
> > Small problem here. err message "unable to get reset gpio\n" will print
> > when -EPROBE_DEFER happen. EPROBE_DEFER is quite common when use i2c
> > expand gpio chip.
>
> I'm not sure how you come to this conclusion. Can you elaborate, please?
> P.S> I do not see a problem as described.
If i2c gpio-expander driver have not load when imx6_pcie probe, I supposed
devm_gpiod_get_optional() will return -EPROBE_DEFER,
if (IS_ERR(imx6_pcie->reset_gpiod)) should be true. then dev_err_probe()
will run and print "unable to get reset gpio\n" with error code
-EPROBE_DEFER.
driver framework will retry imx6_pcie probe again when a new device appear.
it may retry sevial times utill i2c gpio-expander driver probe success or
timeout.
Frank
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 5%]
* Re: [PATCH v2 3/4] PCI: imx6: Convert to agnostic GPIO API
2024-04-23 19:56 5% ` Frank Li
@ 2024-04-23 20:03 0% ` Andy Shevchenko
2024-04-23 20:16 5% ` Frank Li
0 siblings, 1 reply; 200+ results
From: Andy Shevchenko @ 2024-04-23 20:03 UTC (permalink / raw)
To: Frank Li
Cc: Manivannan Sadhasivam, Krzysztof Wilczyński,
Uwe Kleine-König, linux-omap, linux-pci, linux-arm-kernel,
linux-kernel, imx, linux-amlogic, linux-arm-msm, linux-tegra,
Vignesh Raghavendra, Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár
On Tue, Apr 23, 2024 at 03:56:56PM -0400, Frank Li wrote:
> On Tue, Apr 23, 2024 at 08:19:06PM +0300, Andy Shevchenko wrote:
...
> > + imx6_pcie->reset_gpiod =
> > + devm_gpiod_get_optional(dev, "reset",
> > + imx6_pcie->gpio_active_high ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW);
> > + if (IS_ERR(imx6_pcie->reset_gpiod))
> > + return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod),
> > + "unable to get reset gpio\n");
>
> Small problem here. err message "unable to get reset gpio\n" will print
> when -EPROBE_DEFER happen. EPROBE_DEFER is quite common when use i2c
> expand gpio chip.
I'm not sure how you come to this conclusion. Can you elaborate, please?
P.S> I do not see a problem as described.
--
With Best Regards,
Andy Shevchenko
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [PATCH v2 3/4] PCI: imx6: Convert to agnostic GPIO API
2024-04-23 17:19 11% ` [PATCH v2 3/4] PCI: imx6: Convert " Andy Shevchenko
@ 2024-04-23 19:56 5% ` Frank Li
2024-04-23 20:03 0% ` Andy Shevchenko
2024-04-27 6:43 0% ` Manivannan Sadhasivam
1 sibling, 1 reply; 200+ results
From: Frank Li @ 2024-04-23 19:56 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Manivannan Sadhasivam, Krzysztof Wilczyński,
Uwe Kleine-König, linux-omap, linux-pci, linux-arm-kernel,
linux-kernel, imx, linux-amlogic, linux-arm-msm, linux-tegra,
Vignesh Raghavendra, Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár
On Tue, Apr 23, 2024 at 08:19:06PM +0300, Andy Shevchenko wrote:
> The of_gpio.h is going to be removed. In preparation of that convert
> the driver to the agnostic API.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 37 ++++++++++-----------------
> 1 file changed, 14 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 917c69edee1d..d620f1e1a43c 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -11,14 +11,13 @@
> #include <linux/bitfield.h>
> #include <linux/clk.h>
> #include <linux/delay.h>
> -#include <linux/gpio.h>
> +#include <linux/gpio/consumer.h>
> #include <linux/kernel.h>
> #include <linux/mfd/syscon.h>
> #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
> #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> #include <linux/module.h>
> #include <linux/of.h>
> -#include <linux/of_gpio.h>
> #include <linux/of_address.h>
> #include <linux/pci.h>
> #include <linux/platform_device.h>
> @@ -107,7 +106,7 @@ struct imx6_pcie_drvdata {
>
> struct imx6_pcie {
> struct dw_pcie *pci;
> - int reset_gpio;
> + struct gpio_desc *reset_gpiod;
> bool gpio_active_high;
> bool link_is_up;
> struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS];
> @@ -721,9 +720,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
> }
>
> /* Some boards don't have PCIe reset GPIO. */
> - if (gpio_is_valid(imx6_pcie->reset_gpio))
> - gpio_set_value_cansleep(imx6_pcie->reset_gpio,
> - imx6_pcie->gpio_active_high);
> + gpiod_set_raw_value_cansleep(imx6_pcie->reset_gpiod,
> + imx6_pcie->gpio_active_high);
> }
>
> static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> @@ -771,10 +769,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> }
>
> /* Some boards don't have PCIe reset GPIO. */
> - if (gpio_is_valid(imx6_pcie->reset_gpio)) {
> + if (imx6_pcie->reset_gpiod) {
> msleep(100);
> - gpio_set_value_cansleep(imx6_pcie->reset_gpio,
> - !imx6_pcie->gpio_active_high);
> + gpiod_set_raw_value_cansleep(imx6_pcie->reset_gpiod,
> + !imx6_pcie->gpio_active_high);
> /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
> msleep(100);
> }
> @@ -1285,22 +1283,15 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> return PTR_ERR(pci->dbi_base);
>
> /* Fetch GPIOs */
> - imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
> imx6_pcie->gpio_active_high = of_property_read_bool(node,
> "reset-gpio-active-high");
> - if (gpio_is_valid(imx6_pcie->reset_gpio)) {
> - ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
> - imx6_pcie->gpio_active_high ?
> - GPIOF_OUT_INIT_HIGH :
> - GPIOF_OUT_INIT_LOW,
> - "PCIe reset");
> - if (ret) {
> - dev_err(dev, "unable to get reset gpio\n");
> - return ret;
> - }
> - } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
> - return imx6_pcie->reset_gpio;
> - }
> + imx6_pcie->reset_gpiod =
> + devm_gpiod_get_optional(dev, "reset",
> + imx6_pcie->gpio_active_high ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW);
> + if (IS_ERR(imx6_pcie->reset_gpiod))
> + return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod),
> + "unable to get reset gpio\n");
Small problem here. err message "unable to get reset gpio\n" will print
when -EPROBE_DEFER happen. EPROBE_DEFER is quite common when use i2c
expand gpio chip.
Frank
> + gpiod_set_consumer_name(imx6_pcie->reset_gpiod, "PCIe reset");
>
> if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS)
> return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
> --
> 2.43.0.rc1.1336.g36b5255a03ac
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 5%]
* [PATCH v2 3/4] PCI: imx6: Convert to agnostic GPIO API
@ 2024-04-23 17:19 11% ` Andy Shevchenko
2024-04-23 19:56 5% ` Frank Li
2024-04-27 6:43 0% ` Manivannan Sadhasivam
2024-04-23 17:19 16% ` [PATCH v2 4/4] PCI: kirin: " Andy Shevchenko
1 sibling, 2 replies; 200+ results
From: Andy Shevchenko @ 2024-04-23 17:19 UTC (permalink / raw)
To: Manivannan Sadhasivam, Frank Li, Krzysztof Wilczyński,
Andy Shevchenko, Uwe Kleine-König, linux-omap, linux-pci,
linux-arm-kernel, linux-kernel, imx, linux-amlogic,
linux-arm-msm, linux-tegra
Cc: Vignesh Raghavendra, Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár
The of_gpio.h is going to be removed. In preparation of that convert
the driver to the agnostic API.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 37 ++++++++++-----------------
1 file changed, 14 insertions(+), 23 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 917c69edee1d..d620f1e1a43c 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -11,14 +11,13 @@
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
-#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_gpio.h>
#include <linux/of_address.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
@@ -107,7 +106,7 @@ struct imx6_pcie_drvdata {
struct imx6_pcie {
struct dw_pcie *pci;
- int reset_gpio;
+ struct gpio_desc *reset_gpiod;
bool gpio_active_high;
bool link_is_up;
struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS];
@@ -721,9 +720,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
}
/* Some boards don't have PCIe reset GPIO. */
- if (gpio_is_valid(imx6_pcie->reset_gpio))
- gpio_set_value_cansleep(imx6_pcie->reset_gpio,
- imx6_pcie->gpio_active_high);
+ gpiod_set_raw_value_cansleep(imx6_pcie->reset_gpiod,
+ imx6_pcie->gpio_active_high);
}
static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
@@ -771,10 +769,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
}
/* Some boards don't have PCIe reset GPIO. */
- if (gpio_is_valid(imx6_pcie->reset_gpio)) {
+ if (imx6_pcie->reset_gpiod) {
msleep(100);
- gpio_set_value_cansleep(imx6_pcie->reset_gpio,
- !imx6_pcie->gpio_active_high);
+ gpiod_set_raw_value_cansleep(imx6_pcie->reset_gpiod,
+ !imx6_pcie->gpio_active_high);
/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
msleep(100);
}
@@ -1285,22 +1283,15 @@ static int imx6_pcie_probe(struct platform_device *pdev)
return PTR_ERR(pci->dbi_base);
/* Fetch GPIOs */
- imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
imx6_pcie->gpio_active_high = of_property_read_bool(node,
"reset-gpio-active-high");
- if (gpio_is_valid(imx6_pcie->reset_gpio)) {
- ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
- imx6_pcie->gpio_active_high ?
- GPIOF_OUT_INIT_HIGH :
- GPIOF_OUT_INIT_LOW,
- "PCIe reset");
- if (ret) {
- dev_err(dev, "unable to get reset gpio\n");
- return ret;
- }
- } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
- return imx6_pcie->reset_gpio;
- }
+ imx6_pcie->reset_gpiod =
+ devm_gpiod_get_optional(dev, "reset",
+ imx6_pcie->gpio_active_high ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW);
+ if (IS_ERR(imx6_pcie->reset_gpiod))
+ return dev_err_probe(dev, PTR_ERR(imx6_pcie->reset_gpiod),
+ "unable to get reset gpio\n");
+ gpiod_set_consumer_name(imx6_pcie->reset_gpiod, "PCIe reset");
if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS)
return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
--
2.43.0.rc1.1336.g36b5255a03ac
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 11%]
* [PATCH v2 4/4] PCI: kirin: Convert to agnostic GPIO API
2024-04-23 17:19 11% ` [PATCH v2 3/4] PCI: imx6: Convert " Andy Shevchenko
@ 2024-04-23 17:19 16% ` Andy Shevchenko
2024-04-27 7:23 0% ` Manivannan Sadhasivam
1 sibling, 1 reply; 200+ results
From: Andy Shevchenko @ 2024-04-23 17:19 UTC (permalink / raw)
To: Manivannan Sadhasivam, Frank Li, Krzysztof Wilczyński,
Andy Shevchenko, Uwe Kleine-König, linux-omap, linux-pci,
linux-arm-kernel, linux-kernel, imx, linux-amlogic,
linux-arm-msm, linux-tegra
Cc: Vignesh Raghavendra, Siddharth Vadapalli, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Yue Wang, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Xiaowei Song,
Binghui Wang, Thierry Reding, Jonathan Hunter, Thomas Petazzoni,
Pali Rohár
The of_gpio.h is going to be removed. In preparation of that convert
the driver to the agnostic API.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pcie-kirin.c | 105 ++++++++----------------
1 file changed, 35 insertions(+), 70 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
index d5523f302102..1753ab63a541 100644
--- a/drivers/pci/controller/dwc/pcie-kirin.c
+++ b/drivers/pci/controller/dwc/pcie-kirin.c
@@ -12,12 +12,10 @@
#include <linux/compiler.h>
#include <linux/delay.h>
#include <linux/err.h>
-#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
-#include <linux/of_gpio.h>
#include <linux/of_pci.h>
#include <linux/phy/phy.h>
#include <linux/pci.h>
@@ -78,16 +76,16 @@ struct kirin_pcie {
void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */
/* DWC PERST# */
- int gpio_id_dwc_perst;
+ struct gpio_desc *id_dwc_perst_gpio;
/* Per-slot PERST# */
int num_slots;
- int gpio_id_reset[MAX_PCI_SLOTS];
+ struct gpio_desc *id_reset_gpio[MAX_PCI_SLOTS];
const char *reset_names[MAX_PCI_SLOTS];
/* Per-slot clkreq */
int n_gpio_clkreq;
- int gpio_id_clkreq[MAX_PCI_SLOTS];
+ struct gpio_desc *id_clkreq_gpio[MAX_PCI_SLOTS];
const char *clkreq_names[MAX_PCI_SLOTS];
};
@@ -381,15 +379,20 @@ static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie,
pcie->n_gpio_clkreq = ret;
for (i = 0; i < pcie->n_gpio_clkreq; i++) {
- pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node,
- "hisilicon,clken-gpios", i);
- if (pcie->gpio_id_clkreq[i] < 0)
- return pcie->gpio_id_clkreq[i];
+ pcie->id_clkreq_gpio[i] = devm_gpiod_get_index(dev,
+ "hisilicon,clken", i,
+ GPIOD_ASIS);
+ if (IS_ERR(pcie->id_clkreq_gpio[i]))
+ return dev_err_probe(dev, PTR_ERR(pcie->id_clkreq_gpio[i]),
+ "unable to get a valid clken gpio\n");
pcie->clkreq_names[i] = devm_kasprintf(dev, GFP_KERNEL,
"pcie_clkreq_%d", i);
if (!pcie->clkreq_names[i])
return -ENOMEM;
+
+ gpiod_set_consumer_name(pcie->id_clkreq_gpio[i],
+ pcie->clkreq_names[i]);
}
return 0;
@@ -407,10 +410,16 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
for_each_available_child_of_node(parent, child) {
i = pcie->num_slots;
- pcie->gpio_id_reset[i] = of_get_named_gpio(child,
- "reset-gpios", 0);
- if (pcie->gpio_id_reset[i] < 0)
- continue;
+ pcie->id_reset_gpio[i] = devm_fwnode_gpiod_get_index(dev,
+ of_fwnode_handle(child),
+ "reset", 0, GPIOD_ASIS,
+ NULL);
+ if (IS_ERR(pcie->id_reset_gpio[i])) {
+ if (PTR_ERR(pcie->id_reset_gpio[i]) == -ENOENT)
+ continue;
+ return dev_err_probe(dev, PTR_ERR(pcie->id_reset_gpio[i]),
+ "unable to get a valid reset gpio\n");
+ }
pcie->num_slots++;
if (pcie->num_slots > MAX_PCI_SLOTS) {
@@ -434,6 +443,9 @@ static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
ret = -ENOMEM;
goto put_node;
}
+
+ gpiod_set_consumer_name(pcie->id_reset_gpio[i],
+ pcie->reset_names[i]);
}
}
@@ -463,14 +475,11 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
return PTR_ERR(kirin_pcie->apb);
/* pcie internal PERST# gpio */
- kirin_pcie->gpio_id_dwc_perst = of_get_named_gpio(dev->of_node,
- "reset-gpios", 0);
- if (kirin_pcie->gpio_id_dwc_perst == -EPROBE_DEFER) {
- return -EPROBE_DEFER;
- } else if (!gpio_is_valid(kirin_pcie->gpio_id_dwc_perst)) {
- dev_err(dev, "unable to get a valid gpio pin\n");
- return -ENODEV;
- }
+ kirin_pcie->id_dwc_perst_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
+ if (IS_ERR(kirin_pcie->id_dwc_perst_gpio))
+ return dev_err_probe(dev, PTR_ERR(kirin_pcie->id_dwc_perst_gpio),
+ "unable to get a valid gpio pin\n");
+ gpiod_set_consumer_name(kirin_pcie->id_dwc_perst_gpio, "pcie_perst_bridge");
ret = kirin_pcie_get_gpio_enable(kirin_pcie, pdev);
if (ret)
@@ -553,7 +562,7 @@ static int kirin_pcie_add_bus(struct pci_bus *bus)
/* Send PERST# to each slot */
for (i = 0; i < kirin_pcie->num_slots; i++) {
- ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1);
+ ret = gpiod_direction_output_raw(kirin_pcie->id_reset_gpio[i], 1);
if (ret) {
dev_err(pci->dev, "PERST# %s error: %d\n",
kirin_pcie->reset_names[i], ret);
@@ -623,44 +632,6 @@ static int kirin_pcie_host_init(struct dw_pcie_rp *pp)
return 0;
}
-static int kirin_pcie_gpio_request(struct kirin_pcie *kirin_pcie,
- struct device *dev)
-{
- int ret, i;
-
- for (i = 0; i < kirin_pcie->num_slots; i++) {
- if (!gpio_is_valid(kirin_pcie->gpio_id_reset[i])) {
- dev_err(dev, "unable to get a valid %s gpio\n",
- kirin_pcie->reset_names[i]);
- return -ENODEV;
- }
-
- ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i],
- kirin_pcie->reset_names[i]);
- if (ret)
- return ret;
- }
-
- for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) {
- if (!gpio_is_valid(kirin_pcie->gpio_id_clkreq[i])) {
- dev_err(dev, "unable to get a valid %s gpio\n",
- kirin_pcie->clkreq_names[i]);
- return -ENODEV;
- }
-
- ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i],
- kirin_pcie->clkreq_names[i]);
- if (ret)
- return ret;
-
- ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
static const struct dw_pcie_ops kirin_dw_pcie_ops = {
.read_dbi = kirin_pcie_read_dbi,
.write_dbi = kirin_pcie_write_dbi,
@@ -680,7 +651,7 @@ static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie)
return hi3660_pcie_phy_power_off(kirin_pcie);
for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++)
- gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 1);
+ gpiod_direction_output_raw(kirin_pcie->id_clkreq_gpio[i], 1);
phy_power_off(kirin_pcie->phy);
phy_exit(kirin_pcie->phy);
@@ -707,10 +678,6 @@ static int kirin_pcie_power_on(struct platform_device *pdev,
if (IS_ERR(kirin_pcie->phy))
return PTR_ERR(kirin_pcie->phy);
- ret = kirin_pcie_gpio_request(kirin_pcie, dev);
- if (ret)
- return ret;
-
ret = phy_init(kirin_pcie->phy);
if (ret)
goto err;
@@ -723,11 +690,9 @@ static int kirin_pcie_power_on(struct platform_device *pdev,
/* perst assert Endpoint */
usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
- if (!gpio_request(kirin_pcie->gpio_id_dwc_perst, "pcie_perst_bridge")) {
- ret = gpio_direction_output(kirin_pcie->gpio_id_dwc_perst, 1);
- if (ret)
- goto err;
- }
+ ret = gpiod_direction_output_raw(kirin_pcie->id_dwc_perst_gpio, 1);
+ if (ret)
+ goto err;
usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
--
2.43.0.rc1.1336.g36b5255a03ac
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 16%]
* [PATCH v4 1/2] mm: allow dynamic vmalloc range restrictions
@ 2024-04-23 14:58 5% Maxwell Bland
2024-04-23 15:00 5% ` mbland
0 siblings, 1 reply; 200+ results
From: Maxwell Bland @ 2024-04-23 14:58 UTC (permalink / raw)
To: linux-mm
Cc: Maxwell Bland <mbland@motorola.com> Catalin Marinas,
Will Deacon, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Eduard Zingerman, Song Liu,
Yonghong Song, John Fastabend, KP Singh, Stanislav Fomichev,
Hao Luo, Jiri Olsa, Zi Shen Lim, Andrew Morton, Uladzislau Rezki,
Christoph Hellwig, Lorenzo Stoakes, Mark Rutland, Ard Biesheuvel,
Maxwell Bland, Russell King, Masami Hiramatsu, Shaoqin Huang,
Ryo Takakura, James Morse, Ryan Roberts, linux-arm-kernel,
linux-kernel, bpf
Add an API to the vmalloc infrastructure, create_vmalloc_range_check,
which allows for the creation of restricted sub-ranges of vmalloc memory
during the init process, which can only be allocated from via vmalloc
requests with vaddr start addresses explicitly matching the range's
start addresses. Calls to this API can split up to two nodes in the
red-black tree.
create_vmalloc_range_check restricts vmalloc requests not matching the
range's start address to all other locations in the standard vmalloc
range, i.e. users of the interface are responsible for requesting only
correct and appropriate reservations. The primary intention of this API
is supporting ASLR module region allocation regions while not
undermining existing security mechanisms by necessitating interleaved
code and data pages.
To perform range allocation at the appropriate, earliest time, provide a
callback arch_init_checked_vmap_ranges rather than maintaining a linked
list outside of the vmalloc infrastructure, ensuring all vmap management
is still owned by vmalloc.c.
v3: 20240416122254.868007168-1-mbland@motorola.com
- Added callbacks into arch-specific code to dynamically partition
red-black tree
(The freedom of architectures to determine vm area allocation was deemed
dangerous since there was no possibility of enforcing that areas were
correctly managed.)
v2: 20240220203256.31153-1-mbland@motorola.com
- No longer depends on reducing the size of the vmalloc region
- Attempted to implement change by allowing architectures to override
most abstract public vmalloc interface
(Overrides on vmalloc methods were deemed undesirable.)
v1: CAP5Mv+ydhk=Ob4b40ZahGMgT-5+-VEHxtmA=-LkJiEOOU+K6hw@mail.gmail.com
- Statically reduced the range of the vmalloc region to support
parititoned code ranges
(The trade off between space reduction and security was deemed
unnecessary.)
Signed-off-by: Maxwell Bland <mbland@motorola.com>
---
Hello,
Thank you again to all the maintainers for prior and current reviews of
this patch. The below approach is more pristine and fixes the additional
issues Uladzislau raised last Tuesday.
I have decided to break down the prior patchset into 3-5 parts since the
affected maintainers list is large and the affected portions of the code
are large and discrete.
Regards,
Maxwell Bland
P.S. Clarifying a few technical details from prior reviews:
- Dynamic restricted ranges are adopted in favor over strict (linear)
partitioning, as just restricting vmalloc ranges creates unfavorable and
unnecessary trade-offs between vmalloc region size and security, for
example, ASLR randomization entropy. Restricted ranges are also adopted
in favor over interleaving code and data pages, which prevents an entire
field of work and kernel improvements based on the enforcment of
PMD-level-and-coarser sized code protections or optimizations (e.g.
arm64's PXNTable) dynamically.
- Preventing code and data page interleaving simplifies code focused on
preventing malicious page table updates since we do not need to track
all updates of PTE level descriptors. Many present exploits which
generate write gadgets to kernel data via use-after-free (UAF) and
heap-spray attacks target PTE descriptors to modify the permissions on
critical memory regions. If PTEs are non-interleaved, executable regions
can be marked immutable when outside of specialized code allocation
systems, e.g. BPF's JIT, and data regions can be entirely restricted
from privileged executability at the PMD level.
include/linux/vmalloc.h | 14 ++++++
mm/vmalloc.c | 102 ++++++++++++++++++++++++++++++++++++++--
2 files changed, 113 insertions(+), 3 deletions(-)
diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h
index 98ea90e90439..ece8879ab060 100644
--- a/include/linux/vmalloc.h
+++ b/include/linux/vmalloc.h
@@ -81,6 +81,12 @@ struct vmap_area {
unsigned long flags; /* mark type of vm_map_ram area */
};
+struct checked_vmap_range {
+ unsigned long va_start;
+ unsigned long va_end;
+ struct list_head list;
+};
+
/* archs that select HAVE_ARCH_HUGE_VMAP should override one or more of these */
#ifndef arch_vmap_p4d_supported
static inline bool arch_vmap_p4d_supported(pgprot_t prot)
@@ -125,6 +131,12 @@ static inline pgprot_t arch_vmap_pgprot_tagged(pgprot_t prot)
}
#endif
+#ifndef arch_init_checked_vmap_ranges
+inline void __init arch_init_checked_vmap_ranges(void)
+{
+}
+#endif
+
/*
* Highlevel APIs for driver use
*/
@@ -211,6 +223,8 @@ extern struct vm_struct *__get_vm_area_caller(unsigned long size,
unsigned long flags,
unsigned long start, unsigned long end,
const void *caller);
+int __init create_vmalloc_range_check(unsigned long start_vaddr,
+ unsigned long end_vaddr);
void free_vm_area(struct vm_struct *area);
extern struct vm_struct *remove_vm_area(const void *addr);
extern struct vm_struct *find_vm_area(const void *addr);
diff --git a/mm/vmalloc.c b/mm/vmalloc.c
index 68fa001648cc..8f382b6c31de 100644
--- a/mm/vmalloc.c
+++ b/mm/vmalloc.c
@@ -817,6 +817,16 @@ static struct kmem_cache *vmap_area_cachep;
*/
static LIST_HEAD(free_vmap_area_list);
+static struct kmem_cache *vmap_checked_range_cachep;
+
+/*
+ * This linked list is used to record ranges of the vmalloc
+ * region which are checked at allocation time to ensure they
+ * are only allocated within when an explicit allocation
+ * request to that range is made.
+ */
+static LIST_HEAD(checked_range_list);
+
/*
* This augment red-black tree represents the free vmap space.
* All vmap_area objects in this tree are sorted by va->va_start
@@ -1454,6 +1464,23 @@ merge_or_add_vmap_area_augment(struct vmap_area *va,
return va;
}
+static __always_inline bool
+va_is_range_restricted(struct vmap_area *va, unsigned long vstart)
+{
+ struct checked_vmap_range *range, *tmp;
+
+ if (list_empty(&checked_range_list))
+ return false;
+
+ list_for_each_entry_safe(range, tmp, &checked_range_list, list)
+ if (va->va_start >= range->va_start &&
+ va->va_end <= range->va_end &&
+ vstart != range->va_start)
+ return true;
+
+ return false;
+}
+
static __always_inline bool
is_within_this_va(struct vmap_area *va, unsigned long size,
unsigned long align, unsigned long vstart)
@@ -1501,7 +1528,8 @@ find_vmap_lowest_match(struct rb_root *root, unsigned long size,
vstart < va->va_start) {
node = node->rb_left;
} else {
- if (is_within_this_va(va, size, align, vstart))
+ if (!va_is_range_restricted(va, vstart) &&
+ is_within_this_va(va, size, align, vstart))
return va;
/*
@@ -1522,7 +1550,8 @@ find_vmap_lowest_match(struct rb_root *root, unsigned long size,
*/
while ((node = rb_parent(node))) {
va = rb_entry(node, struct vmap_area, rb_node);
- if (is_within_this_va(va, size, align, vstart))
+ if (!va_is_range_restricted(va, vstart) &&
+ is_within_this_va(va, size, align, vstart))
return va;
if (get_subtree_max_size(node->rb_right) >= length &&
@@ -1554,7 +1583,8 @@ find_vmap_lowest_linear_match(struct list_head *head, unsigned long size,
struct vmap_area *va;
list_for_each_entry(va, head, list) {
- if (!is_within_this_va(va, size, align, vstart))
+ if (va_is_range_restricted(va, vstart) ||
+ !is_within_this_va(va, size, align, vstart))
continue;
return va;
@@ -1717,6 +1747,36 @@ va_clip(struct rb_root *root, struct list_head *head,
return 0;
}
+static inline int
+split_and_alloc_va(struct rb_root *root, struct list_head *head, unsigned long addr)
+{
+ struct vmap_area *va;
+ int ret;
+ struct vmap_area *lva = NULL;
+
+ va = __find_vmap_area(addr, root);
+ if (!va) {
+ pr_err("%s: could not find vmap\n", __func__);
+ return -1;
+ }
+
+ lva = kmem_cache_alloc(vmap_area_cachep, GFP_NOWAIT);
+ if (!lva) {
+ pr_err("%s: unable to allocate va for range\n", __func__);
+ return -1;
+ }
+ lva->va_start = addr;
+ lva->va_end = va->va_end;
+ ret = va_clip(root, head, va, addr, va->va_end - addr);
+ if (WARN_ON_ONCE(ret)) {
+ pr_err("%s: unable to clip code base region\n", __func__);
+ kmem_cache_free(vmap_area_cachep, lva);
+ return -1;
+ }
+ insert_vmap_area_augment(lva, NULL, root, head);
+ return 0;
+}
+
static unsigned long
va_alloc(struct vmap_area *va,
struct rb_root *root, struct list_head *head,
@@ -4424,6 +4484,35 @@ int remap_vmalloc_range(struct vm_area_struct *vma, void *addr,
}
EXPORT_SYMBOL(remap_vmalloc_range);
+/**
+ * create_vmalloc_range_check - create a checked range of vmalloc memory
+ * @start_vaddr: The starting vaddr of the code range
+ * @end_vaddr: The ending vaddr of the code range
+ *
+ * Returns: 0 for success, -1 on failure
+ *
+ * This function marks regions within or overlapping the vmalloc region for
+ * requested range checking during allocation. When requesting virtual memory,
+ * if the requested starting vaddr does not explicitly match the starting vaddr
+ * of this range, this range will not be allocated from.
+ */
+int __init create_vmalloc_range_check(unsigned long start_vaddr,
+ unsigned long end_vaddr)
+{
+ struct checked_vmap_range *range;
+
+ range = kmem_cache_alloc(vmap_checked_range_cachep, GFP_NOWAIT);
+ if (split_and_alloc_va(&free_vmap_area_root, &free_vmap_area_list, start_vaddr) ||
+ split_and_alloc_va(&free_vmap_area_root, &free_vmap_area_list, end_vaddr))
+ return -1;
+
+ range->va_start = start_vaddr;
+ range->va_end = end_vaddr;
+
+ list_add(&range->list, &checked_range_list);
+ return 0;
+}
+
void free_vm_area(struct vm_struct *area)
{
struct vm_struct *ret;
@@ -5082,6 +5171,11 @@ void __init vmalloc_init(void)
*/
vmap_area_cachep = KMEM_CACHE(vmap_area, SLAB_PANIC);
+ /*
+ * Create the cache for checked vmap ranges.
+ */
+ vmap_checked_range_cachep = KMEM_CACHE(checked_vmap_range, SLAB_PANIC);
+
for_each_possible_cpu(i) {
struct vmap_block_queue *vbq;
struct vfree_deferred *p;
@@ -5129,4 +5223,6 @@ void __init vmalloc_init(void)
vmap_node_shrinker->count_objects = vmap_node_shrink_count;
vmap_node_shrinker->scan_objects = vmap_node_shrink_scan;
shrinker_register(vmap_node_shrinker);
+
+ arch_init_checked_vmap_ranges();
}
base-commit: 71b1543c83d65af8215d7558d70fc2ecbee77dcf
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* (no subject)
2024-04-23 14:58 5% [PATCH v4 1/2] mm: allow dynamic vmalloc range restrictions Maxwell Bland
@ 2024-04-23 15:00 5% ` mbland
0 siblings, 0 replies; 200+ results
From: mbland @ 2024-04-23 15:00 UTC (permalink / raw)
To: linux-mm
Cc: Maxwell Bland <mbland@motorola.com> Catalin Marinas,
Will Deacon, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Eduard Zingerman, Song Liu,
Yonghong Song, John Fastabend, KP Singh, Stanislav Fomichev,
Hao Luo, Jiri Olsa, Zi Shen Lim, Andrew Morton, Uladzislau Rezki,
Christoph Hellwig, Lorenzo Stoakes, Mark Rutland, Ard Biesheuvel,
Maxwell Bland, Russell King, Masami Hiramatsu, Shaoqin Huang,
Ryo Takakura, James Morse, Ryan Roberts, linux-arm-kernel,
linux-kernel, bpf
From aef33d1682400c55a1634de8ab44b7a77a776900 Mon Sep 17 00:00:00 2001
From: Maxwell Bland <mbland@motorola.com>
Date: Tue, 23 Apr 2024 09:58:43 -0500
Subject: [PATCH v4 1/2] mm: allow dynamic vmalloc range restrictions
Add an API to the vmalloc infrastructure, create_vmalloc_range_check,
which allows for the creation of restricted sub-ranges of vmalloc memory
during the init process, which can only be allocated from via vmalloc
requests with vaddr start addresses explicitly matching the range's
start addresses. Calls to this API can split up to two nodes in the
red-black tree.
create_vmalloc_range_check restricts vmalloc requests not matching the
range's start address to all other locations in the standard vmalloc
range, i.e. users of the interface are responsible for requesting only
correct and appropriate reservations. The primary intention of this API
is supporting ASLR module region allocation regions while not
undermining existing security mechanisms by necessitating interleaved
code and data pages.
To perform range allocation at the appropriate, earliest time, provide a
callback arch_init_checked_vmap_ranges rather than maintaining a linked
list outside of the vmalloc infrastructure, ensuring all vmap management
is still owned by vmalloc.c.
v3: 20240416122254.868007168-1-mbland@motorola.com
- Added callbacks into arch-specific code to dynamically partition
red-black tree
(The freedom of architectures to determine vm area allocation was deemed
dangerous since there was no possibility of enforcing that areas were
correctly managed.)
v2: 20240220203256.31153-1-mbland@motorola.com
- No longer depends on reducing the size of the vmalloc region
- Attempted to implement change by allowing architectures to override
most abstract public vmalloc interface
(Overrides on vmalloc methods were deemed undesirable.)
v1: CAP5Mv+ydhk=Ob4b40ZahGMgT-5+-VEHxtmA=-LkJiEOOU+K6hw@mail.gmail.com
- Statically reduced the range of the vmalloc region to support
parititoned code ranges
(The trade off between space reduction and security was deemed
unnecessary.)
Signed-off-by: Maxwell Bland <mbland@motorola.com>
---
Hello,
Thank you again to all the maintainers for prior and current reviews of
this patch. The below approach is more pristine and fixes the additional
issues Uladzislau raised last Tuesday.
I have decided to break down the prior patchset into 3-5 parts since the
affected maintainers list is large and the affected portions of the code
are large and discrete.
Regards,
Maxwell Bland
P.S. Clarifying a few technical details from prior reviews:
- Dynamic restricted ranges are adopted in favor over strict (linear)
partitioning, as just restricting vmalloc ranges creates unfavorable and
unnecessary trade-offs between vmalloc region size and security, for
example, ASLR randomization entropy. Restricted ranges are also adopted
in favor over interleaving code and data pages, which prevents an entire
field of work and kernel improvements based on the enforcment of
PMD-level-and-coarser sized code protections or optimizations (e.g.
arm64's PXNTable) dynamically.
- Preventing code and data page interleaving simplifies code focused on
preventing malicious page table updates since we do not need to track
all updates of PTE level descriptors. Many present exploits which
generate write gadgets to kernel data via use-after-free (UAF) and
heap-spray attacks target PTE descriptors to modify the permissions on
critical memory regions. If PTEs are non-interleaved, executable regions
can be marked immutable when outside of specialized code allocation
systems, e.g. BPF's JIT, and data regions can be entirely restricted
from privileged executability at the PMD level.
include/linux/vmalloc.h | 14 ++++++
mm/vmalloc.c | 102 ++++++++++++++++++++++++++++++++++++++--
2 files changed, 113 insertions(+), 3 deletions(-)
diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h
index 98ea90e90439..ece8879ab060 100644
--- a/include/linux/vmalloc.h
+++ b/include/linux/vmalloc.h
@@ -81,6 +81,12 @@ struct vmap_area {
unsigned long flags; /* mark type of vm_map_ram area */
};
+struct checked_vmap_range {
+ unsigned long va_start;
+ unsigned long va_end;
+ struct list_head list;
+};
+
/* archs that select HAVE_ARCH_HUGE_VMAP should override one or more of these */
#ifndef arch_vmap_p4d_supported
static inline bool arch_vmap_p4d_supported(pgprot_t prot)
@@ -125,6 +131,12 @@ static inline pgprot_t arch_vmap_pgprot_tagged(pgprot_t prot)
}
#endif
+#ifndef arch_init_checked_vmap_ranges
+inline void __init arch_init_checked_vmap_ranges(void)
+{
+}
+#endif
+
/*
* Highlevel APIs for driver use
*/
@@ -211,6 +223,8 @@ extern struct vm_struct *__get_vm_area_caller(unsigned long size,
unsigned long flags,
unsigned long start, unsigned long end,
const void *caller);
+int __init create_vmalloc_range_check(unsigned long start_vaddr,
+ unsigned long end_vaddr);
void free_vm_area(struct vm_struct *area);
extern struct vm_struct *remove_vm_area(const void *addr);
extern struct vm_struct *find_vm_area(const void *addr);
diff --git a/mm/vmalloc.c b/mm/vmalloc.c
index 68fa001648cc..8f382b6c31de 100644
--- a/mm/vmalloc.c
+++ b/mm/vmalloc.c
@@ -817,6 +817,16 @@ static struct kmem_cache *vmap_area_cachep;
*/
static LIST_HEAD(free_vmap_area_list);
+static struct kmem_cache *vmap_checked_range_cachep;
+
+/*
+ * This linked list is used to record ranges of the vmalloc
+ * region which are checked at allocation time to ensure they
+ * are only allocated within when an explicit allocation
+ * request to that range is made.
+ */
+static LIST_HEAD(checked_range_list);
+
/*
* This augment red-black tree represents the free vmap space.
* All vmap_area objects in this tree are sorted by va->va_start
@@ -1454,6 +1464,23 @@ merge_or_add_vmap_area_augment(struct vmap_area *va,
return va;
}
+static __always_inline bool
+va_is_range_restricted(struct vmap_area *va, unsigned long vstart)
+{
+ struct checked_vmap_range *range, *tmp;
+
+ if (list_empty(&checked_range_list))
+ return false;
+
+ list_for_each_entry_safe(range, tmp, &checked_range_list, list)
+ if (va->va_start >= range->va_start &&
+ va->va_end <= range->va_end &&
+ vstart != range->va_start)
+ return true;
+
+ return false;
+}
+
static __always_inline bool
is_within_this_va(struct vmap_area *va, unsigned long size,
unsigned long align, unsigned long vstart)
@@ -1501,7 +1528,8 @@ find_vmap_lowest_match(struct rb_root *root, unsigned long size,
vstart < va->va_start) {
node = node->rb_left;
} else {
- if (is_within_this_va(va, size, align, vstart))
+ if (!va_is_range_restricted(va, vstart) &&
+ is_within_this_va(va, size, align, vstart))
return va;
/*
@@ -1522,7 +1550,8 @@ find_vmap_lowest_match(struct rb_root *root, unsigned long size,
*/
while ((node = rb_parent(node))) {
va = rb_entry(node, struct vmap_area, rb_node);
- if (is_within_this_va(va, size, align, vstart))
+ if (!va_is_range_restricted(va, vstart) &&
+ is_within_this_va(va, size, align, vstart))
return va;
if (get_subtree_max_size(node->rb_right) >= length &&
@@ -1554,7 +1583,8 @@ find_vmap_lowest_linear_match(struct list_head *head, unsigned long size,
struct vmap_area *va;
list_for_each_entry(va, head, list) {
- if (!is_within_this_va(va, size, align, vstart))
+ if (va_is_range_restricted(va, vstart) ||
+ !is_within_this_va(va, size, align, vstart))
continue;
return va;
@@ -1717,6 +1747,36 @@ va_clip(struct rb_root *root, struct list_head *head,
return 0;
}
+static inline int
+split_and_alloc_va(struct rb_root *root, struct list_head *head, unsigned long addr)
+{
+ struct vmap_area *va;
+ int ret;
+ struct vmap_area *lva = NULL;
+
+ va = __find_vmap_area(addr, root);
+ if (!va) {
+ pr_err("%s: could not find vmap\n", __func__);
+ return -1;
+ }
+
+ lva = kmem_cache_alloc(vmap_area_cachep, GFP_NOWAIT);
+ if (!lva) {
+ pr_err("%s: unable to allocate va for range\n", __func__);
+ return -1;
+ }
+ lva->va_start = addr;
+ lva->va_end = va->va_end;
+ ret = va_clip(root, head, va, addr, va->va_end - addr);
+ if (WARN_ON_ONCE(ret)) {
+ pr_err("%s: unable to clip code base region\n", __func__);
+ kmem_cache_free(vmap_area_cachep, lva);
+ return -1;
+ }
+ insert_vmap_area_augment(lva, NULL, root, head);
+ return 0;
+}
+
static unsigned long
va_alloc(struct vmap_area *va,
struct rb_root *root, struct list_head *head,
@@ -4424,6 +4484,35 @@ int remap_vmalloc_range(struct vm_area_struct *vma, void *addr,
}
EXPORT_SYMBOL(remap_vmalloc_range);
+/**
+ * create_vmalloc_range_check - create a checked range of vmalloc memory
+ * @start_vaddr: The starting vaddr of the code range
+ * @end_vaddr: The ending vaddr of the code range
+ *
+ * Returns: 0 for success, -1 on failure
+ *
+ * This function marks regions within or overlapping the vmalloc region for
+ * requested range checking during allocation. When requesting virtual memory,
+ * if the requested starting vaddr does not explicitly match the starting vaddr
+ * of this range, this range will not be allocated from.
+ */
+int __init create_vmalloc_range_check(unsigned long start_vaddr,
+ unsigned long end_vaddr)
+{
+ struct checked_vmap_range *range;
+
+ range = kmem_cache_alloc(vmap_checked_range_cachep, GFP_NOWAIT);
+ if (split_and_alloc_va(&free_vmap_area_root, &free_vmap_area_list, start_vaddr) ||
+ split_and_alloc_va(&free_vmap_area_root, &free_vmap_area_list, end_vaddr))
+ return -1;
+
+ range->va_start = start_vaddr;
+ range->va_end = end_vaddr;
+
+ list_add(&range->list, &checked_range_list);
+ return 0;
+}
+
void free_vm_area(struct vm_struct *area)
{
struct vm_struct *ret;
@@ -5082,6 +5171,11 @@ void __init vmalloc_init(void)
*/
vmap_area_cachep = KMEM_CACHE(vmap_area, SLAB_PANIC);
+ /*
+ * Create the cache for checked vmap ranges.
+ */
+ vmap_checked_range_cachep = KMEM_CACHE(checked_vmap_range, SLAB_PANIC);
+
for_each_possible_cpu(i) {
struct vmap_block_queue *vbq;
struct vfree_deferred *p;
@@ -5129,4 +5223,6 @@ void __init vmalloc_init(void)
vmap_node_shrinker->count_objects = vmap_node_shrink_count;
vmap_node_shrinker->scan_objects = vmap_node_shrink_scan;
shrinker_register(vmap_node_shrinker);
+
+ arch_init_checked_vmap_ranges();
}
base-commit: 71b1543c83d65af8215d7558d70fc2ecbee77dcf
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* [PATCH v3 3/3] spi: airoha: add SPI-NAND Flash controller driver
@ 2024-04-23 10:16 2% ` Lorenzo Bianconi
2024-04-23 23:51 0% ` Andy Shevchenko
0 siblings, 1 reply; 200+ results
From: Lorenzo Bianconi @ 2024-04-23 10:16 UTC (permalink / raw)
To: linux-spi
Cc: conor, broonie, lorenzo.bianconi83, linux-arm-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, nbd, john, dd,
catalin.marinas, will, upstream, angelogioacchino.delregno
Introduce support for SPI-NAND driver of the Airoha NAND Flash Interface
found on Airoha ARM SoCs.
Tested-by: Rajeev Kumar <Rajeev.Kumar@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
MAINTAINERS | 9 +
drivers/spi/Kconfig | 10 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-airoha-snfi.c | 1156 +++++++++++++++++++++++++++++++++
4 files changed, 1176 insertions(+)
create mode 100644 drivers/spi/spi-airoha-snfi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index aa3b947fb080..ce9fac46f741 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -653,6 +653,15 @@ S: Supported
F: fs/aio.c
F: include/linux/*aio*.h
+AIROHA SPI SNFI DRIVER
+M: Lorenzo Bianconi <lorenzo@kernel.org>
+M: Ray Liu <ray.liu@airoha.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-spi@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/spi/airoha,en7581-snand.yaml
+F: drivers/spi/spi-airoha.c
+
AIRSPY MEDIA DRIVER
L: linux-media@vger.kernel.org
S: Orphan
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bc7021da2fe9..6fa91775f334 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -57,6 +57,16 @@ config SPI_MEM
comment "SPI Master Controller Drivers"
+config SPI_AIROHA_SNFI
+ tristate "Airoha SPI NAND Flash Interface"
+ depends on ARCH_AIROHA || COMPILE_TEST
+ depends on SPI_MASTER
+ select REGMAP_MMIO
+ help
+ This enables support for SPI-NAND mode on the Airoha NAND
+ Flash Interface found on Airoha ARM SoCs. This controller
+ is implemented as a SPI-MEM controller.
+
config SPI_ALTERA
tristate "Altera SPI Controller platform driver"
select SPI_ALTERA_CORE
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4ff8d725ba5e..e694254dec04 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_SPIDEV) += spidev.o
obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
# SPI master controller drivers (bus)
+obj-$(CONFIG_SPI_AIROHA_SNFI) += spi-airoha-snfi.o
obj-$(CONFIG_SPI_ALTERA) += spi-altera-platform.o
obj-$(CONFIG_SPI_ALTERA_CORE) += spi-altera-core.o
obj-$(CONFIG_SPI_ALTERA_DFL) += spi-altera-dfl.o
diff --git a/drivers/spi/spi-airoha-snfi.c b/drivers/spi/spi-airoha-snfi.c
new file mode 100644
index 000000000000..eacb32d6e28e
--- /dev/null
+++ b/drivers/spi/spi-airoha-snfi.c
@@ -0,0 +1,1156 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Ray Liu <ray.liu@airoha.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+/* SPI */
+#define REG_SPI_CTRL_BASE 0x1FA10000
+
+#define REG_SPI_CTRL_READ_MODE 0x0000
+#define REG_SPI_CTRL_READ_IDLE_EN 0x0004
+#define REG_SPI_CTRL_SIDLY 0x0008
+#define REG_SPI_CTRL_CSHEXT 0x000c
+#define REG_SPI_CTRL_CSLEXT 0x0010
+
+#define REG_SPI_CTRL_MTX_MODE_TOG 0x0014
+#define SPI_CTRL_MTX_MODE_TOG GENMASK(3, 0)
+
+#define REG_SPI_CTRL_RDCTL_FSM 0x0018
+#define SPI_CTRL_RDCTL_FSM GENMASK(3, 0)
+
+#define REG_SPI_CTRL_MACMUX_SEL 0x001c
+
+#define REG_SPI_CTRL_MANUAL_EN 0x0020
+#define SPI_CTRL_MANUAL_EN BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_EMPTY 0x0024
+#define SPI_CTRL_OPFIFO_EMPTY BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_WDATA 0x0028
+#define SPI_CTRL_OPFIFO_LEN GENMASK(8, 0)
+#define SPI_CTRL_OPFIFO_OP GENMASK(13, 9)
+
+#define REG_SPI_CTRL_OPFIFO_FULL 0x002c
+#define SPI_CTRL_OPFIFO_FULL BIT(0)
+
+#define REG_SPI_CTRL_OPFIFO_WR 0x0030
+#define SPI_CTRL_OPFIFO_WR BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_FULL 0x0034
+#define SPI_CTRL_DFIFO_FULL BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_WDATA 0x0038
+#define SPI_CTRL_DFIFO_WDATA GENMASK(7, 0)
+
+#define REG_SPI_CTRL_DFIFO_EMPTY 0x003c
+#define SPI_CTRL_DFIFO_EMPTY BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_RD 0x0040
+#define SPI_CTRL_DFIFO_RD BIT(0)
+
+#define REG_SPI_CTRL_DFIFO_RDATA 0x0044
+#define SPI_CTRL_DFIFO_RDATA GENMASK(7, 0)
+
+#define REG_SPI_CTRL_DUMMY 0x0080
+#define SPI_CTRL_CTRL_DUMMY GENMASK(3, 0)
+
+#define REG_SPI_CTRL_PROBE_SEL 0x0088
+#define REG_SPI_CTRL_INTERRUPT 0x0090
+#define REG_SPI_CTRL_INTERRUPT_EN 0x0094
+#define REG_SPI_CTRL_SI_CK_SEL 0x009c
+#define REG_SPI_CTRL_SW_CFGNANDADDR_VAL 0x010c
+#define REG_SPI_CTRL_SW_CFGNANDADDR_EN 0x0110
+#define REG_SPI_CTRL_SFC_STRAP 0x0114
+
+#define REG_SPI_CTRL_NFI2SPI_EN 0x0130
+#define SPI_CTRL_NFI2SPI_EN BIT(0)
+
+/* NFI2SPI */
+#define REG_SPI_NFI_CNFG 0x0000
+#define SPI_NFI_DMA_MODE BIT(0)
+#define SPI_NFI_READ_MODE BIT(1)
+#define SPI_NFI_DMA_BURST_EN BIT(2)
+#define SPI_NFI_HW_ECC_EN BIT(8)
+#define SPI_NFI_AUTO_FDM_EN BIT(9)
+#define SPI_NFI_OPMODE GENMASK(14, 12)
+
+#define REG_SPI_NFI_PAGEFMT 0x0004
+#define SPI_NFI_PAGE_SIZE GENMASK(1, 0)
+#define SPI_NFI_SPARE_SIZE GENMASK(5, 4)
+
+#define REG_SPI_NFI_CON 0x0008
+#define SPI_NFI_FIFO_FLUSH BIT(0)
+#define SPI_NFI_RST BIT(1)
+#define SPI_NFI_RD_TRIG BIT(8)
+#define SPI_NFI_WR_TRIG BIT(9)
+#define SPI_NFI_SEC_NUM GENMASK(15, 12)
+
+#define REG_SPI_NFI_INTR_EN 0x0010
+#define SPI_NFI_RD_DONE_EN BIT(0)
+#define SPI_NFI_WR_DONE_EN BIT(1)
+#define SPI_NFI_RST_DONE_EN BIT(2)
+#define SPI_NFI_ERASE_DONE_EN BIT(3)
+#define SPI_NFI_BUSY_RETURN_EN BIT(4)
+#define SPI_NFI_ACCESS_LOCK_EN BIT(5)
+#define SPI_NFI_AHB_DONE_EN BIT(6)
+#define SPI_NFI_ALL_IRQ_EN (SPI_NFI_RD_DONE_EN | \
+ SPI_NFI_WR_DONE_EN | \
+ SPI_NFI_RST_DONE_EN | \
+ SPI_NFI_ERASE_DONE_EN | \
+ SPI_NFI_BUSY_RETURN_EN | \
+ SPI_NFI_ACCESS_LOCK_EN | \
+ SPI_NFI_AHB_DONE_EN)
+
+#define REG_SPI_NFI_INTR 0x0014
+#define SPI_NFI_AHB_DONE BIT(6)
+
+#define REG_SPI_NFI_CMD 0x0020
+
+#define REG_SPI_NFI_ADDR_NOB 0x0030
+#define SPI_NFI_ROW_ADDR_NOB GENMASK(6, 4)
+
+#define REG_SPI_NFI_STA 0x0060
+#define REG_SPI_NFI_FIFOSTA 0x0064
+#define REG_SPI_NFI_STRADDR 0x0080
+#define REG_SPI_NFI_FDM0L 0x00a0
+#define REG_SPI_NFI_FDM0M 0x00a4
+#define REG_SPI_NFI_FDM7L 0x00d8
+#define REG_SPI_NFI_FDM7M 0x00dc
+#define REG_SPI_NFI_FIFODATA0 0x0190
+#define REG_SPI_NFI_FIFODATA1 0x0194
+#define REG_SPI_NFI_FIFODATA2 0x0198
+#define REG_SPI_NFI_FIFODATA3 0x019c
+#define REG_SPI_NFI_MASTERSTA 0x0224
+
+#define REG_SPI_NFI_SECCUS_SIZE 0x022c
+#define SPI_NFI_CUS_SEC_SIZE GENMASK(12, 0)
+#define SPI_NFI_CUS_SEC_SIZE_EN BIT(16)
+
+#define REG_SPI_NFI_RD_CTL2 0x0510
+#define REG_SPI_NFI_RD_CTL3 0x0514
+
+#define REG_SPI_NFI_PG_CTL1 0x0524
+#define SPI_NFI_PG_LOAD_CMD GENMASK(15, 8)
+
+#define REG_SPI_NFI_PG_CTL2 0x0528
+#define REG_SPI_NFI_NOR_PROG_ADDR 0x052c
+#define REG_SPI_NFI_NOR_RD_ADDR 0x0534
+
+#define REG_SPI_NFI_SNF_MISC_CTL 0x0538
+#define SPI_NFI_DATA_READ_WR_MODE GENMASK(18, 16)
+
+#define REG_SPI_NFI_SNF_MISC_CTL2 0x053c
+#define SPI_NFI_READ_DATA_BYTE_NUM GENMASK(12, 0)
+#define SPI_NFI_PROG_LOAD_BYTE_NUM GENMASK(28, 16)
+
+#define REG_SPI_NFI_SNF_STA_CTL1 0x0550
+#define SPI_NFI_READ_FROM_CACHE_DONE BIT(25)
+#define SPI_NFI_LOAD_TO_CACHE_DONE BIT(26)
+
+#define REG_SPI_NFI_SNF_STA_CTL2 0x0554
+
+#define REG_SPI_NFI_SNF_NFI_CNFG 0x055c
+#define SPI_NFI_SPI_MODE BIT(0)
+
+/* SPI NAND Protocol OP */
+#define SPI_NAND_OP_GET_FEATURE 0x0f
+#define SPI_NAND_OP_SET_FEATURE 0x1f
+#define SPI_NAND_OP_PAGE_READ 0x13
+#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE 0x03
+#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST 0x0b
+#define SPI_NAND_OP_READ_FROM_CACHE_DUAL 0x3b
+#define SPI_NAND_OP_READ_FROM_CACHE_QUAD 0x6b
+#define SPI_NAND_OP_WRITE_ENABLE 0x06
+#define SPI_NAND_OP_WRITE_DISABLE 0x04
+#define SPI_NAND_OP_PROGRAM_LOAD_SINGLE 0x02
+#define SPI_NAND_OP_PROGRAM_LOAD_QUAD 0x32
+#define SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE 0x84
+#define SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD 0x34
+#define SPI_NAND_OP_PROGRAM_EXECUTE 0x10
+#define SPI_NAND_OP_READ_ID 0x9f
+#define SPI_NAND_OP_BLOCK_ERASE 0xd8
+#define SPI_NAND_OP_RESET 0xff
+#define SPI_NAND_OP_DIE_SELECT 0xc2
+
+enum airoha_snand_mode {
+ SPI_MODE_AUTO,
+ SPI_MODE_MANUAL,
+ SPI_MODE_DMA,
+ SPI_MODE_NO
+};
+
+enum airoha_snand_cs {
+ SPI_CHIP_SEL_HIGH,
+ SPI_CHIP_SEL_LOW,
+};
+
+struct airoha_snand_dev {
+ size_t buf_len;
+
+ u8 *txrx_buf;
+ dma_addr_t dma_addr;
+
+ bool data_need_update;
+ u64 cur_page_num;
+};
+
+struct airoha_snand_ctrl {
+ struct device *dev;
+ struct regmap *regmap_ctrl;
+ struct regmap *regmap_nfi;
+ struct clk *spi_clk;
+
+ struct {
+ size_t page_size;
+ size_t sec_size;
+ unsigned char sec_num;
+ unsigned char spare_size;
+ } nfi_cfg;
+};
+
+static int airoha_snand_set_fifo_op(struct airoha_snand_ctrl *as_ctrl,
+ u8 op_cmd, int op_len)
+{
+ int err;
+ u32 val;
+
+ err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WDATA,
+ FIELD_PREP(SPI_CTRL_OPFIFO_LEN, op_len) |
+ FIELD_PREP(SPI_CTRL_OPFIFO_OP, op_cmd));
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_OPFIFO_FULL,
+ val, !(val & SPI_CTRL_OPFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WR,
+ SPI_CTRL_OPFIFO_WR);
+ if (err)
+ return err;
+
+ return regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_OPFIFO_EMPTY,
+ val, (val & SPI_CTRL_OPFIFO_EMPTY),
+ 0, 250 * USEC_PER_MSEC);
+}
+
+static int airoha_snand_set_cs(struct airoha_snand_ctrl *as_ctrl, u8 cs)
+{
+ return airoha_snand_set_fifo_op(as_ctrl, cs, sizeof(cs));
+}
+
+static int airoha_snand_write_data_to_fifo(struct airoha_snand_ctrl *as_ctrl,
+ const u8 *data, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ int err;
+ u32 val;
+
+ /* 1. Wait until dfifo is not full */
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_FULL, val,
+ !(val & SPI_CTRL_DFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ /* 2. Write data to register DFIFO_WDATA */
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_WDATA,
+ FIELD_PREP(SPI_CTRL_DFIFO_WDATA, data[i]));
+ if (err)
+ return err;
+
+ /* 3. Wait until dfifo is not full */
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_FULL, val,
+ !(val & SPI_CTRL_DFIFO_FULL),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_read_data_from_fifo(struct airoha_snand_ctrl *as_ctrl,
+ u8 *ptr, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ int err;
+ u32 val;
+
+ /* 1. wait until dfifo is not empty */
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_EMPTY, val,
+ !(val & SPI_CTRL_DFIFO_EMPTY),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ /* 2. read from dfifo to register DFIFO_RDATA */
+ err = regmap_read(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_RDATA, &val);
+ if (err)
+ return err;
+
+ ptr[i] = FIELD_GET(SPI_CTRL_DFIFO_RDATA, val);
+ /* 3. enable register DFIFO_RD to read next byte */
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_DFIFO_RD, SPI_CTRL_DFIFO_RD);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_set_mode(struct airoha_snand_ctrl *as_ctrl,
+ enum airoha_snand_mode mode)
+{
+ int err;
+
+ switch (mode) {
+ case SPI_MODE_MANUAL: {
+ u32 val;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_NFI2SPI_EN, 0);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_READ_IDLE_EN, 0);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_RDCTL_FSM, val,
+ !(val & SPI_CTRL_RDCTL_FSM),
+ 0, 250 * USEC_PER_MSEC);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MTX_MODE_TOG, 9);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MANUAL_EN, SPI_CTRL_MANUAL_EN);
+ if (err)
+ return err;
+ break;
+ }
+ case SPI_MODE_DMA:
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_NFI2SPI_EN,
+ SPI_CTRL_MANUAL_EN);
+ if (err < 0)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MTX_MODE_TOG, 0x0);
+ if (err < 0)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_ctrl,
+ REG_SPI_CTRL_MANUAL_EN, 0x0);
+ if (err < 0)
+ return err;
+ break;
+ case SPI_MODE_AUTO:
+ default:
+ break;
+ }
+
+ return regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
+}
+
+#define MAX_TRANSFER_SIZE 511
+static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd,
+ const u8 *data, int len)
+{
+ int i = 0;
+
+ while (i < len) {
+ int data_len = min(len, MAX_TRANSFER_SIZE);
+ int err;
+
+ err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
+ if (err)
+ return err;
+
+ err = airoha_snand_write_data_to_fifo(as_ctrl, &data[i],
+ data_len);
+ if (err < 0)
+ return err;
+
+ i += data_len;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data,
+ int len)
+{
+ int i = 0;
+
+ while (i < len) {
+ int err, data_len = min(len, MAX_TRANSFER_SIZE);
+
+ err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len);
+ if (err)
+ return err;
+
+ err = airoha_snand_read_data_from_fifo(as_ctrl, &data[i],
+ data_len);
+ if (err < 0)
+ return err;
+
+ i += data_len;
+ }
+
+ return 0;
+}
+
+static int airoha_snand_nfi_init(struct airoha_snand_ctrl *as_ctrl)
+{
+ int err;
+
+ /* switch to SNFI mode */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_NFI_CNFG,
+ SPI_NFI_SPI_MODE);
+ if (err)
+ return err;
+
+ /* Enable DMA */
+ return regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR_EN,
+ SPI_NFI_ALL_IRQ_EN, SPI_NFI_AHB_DONE_EN);
+}
+
+static int airoha_snand_nfi_config(struct airoha_snand_ctrl *as_ctrl)
+{
+ int err;
+ u32 val;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
+ if (err)
+ return err;
+
+ /* auto FDM */
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_AUTO_FDM_EN);
+ if (err)
+ return err;
+
+ /* HW ECC */
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_HW_ECC_EN);
+ if (err)
+ return err;
+
+ /* DMA Burst */
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_DMA_BURST_EN);
+ if (err)
+ return err;
+
+ /* page format */
+ switch (as_ctrl->nfi_cfg.spare_size) {
+ case 26:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1);
+ break;
+ case 27:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x2);
+ break;
+ case 28:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x3);
+ break;
+ default:
+ val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x0);
+ break;
+ }
+
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
+ SPI_NFI_SPARE_SIZE, val);
+ if (err)
+ return err;
+
+ switch (as_ctrl->nfi_cfg.page_size) {
+ case 2048:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1);
+ break;
+ case 4096:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x2);
+ break;
+ default:
+ val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x0);
+ break;
+ }
+
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
+ SPI_NFI_PAGE_SIZE, val);
+ if (err)
+ return err;
+
+ /* sec num */
+ val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_SEC_NUM, val);
+ if (err)
+ return err;
+
+ /* enable cust sec size */
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
+ SPI_NFI_CUS_SEC_SIZE_EN);
+ if (err)
+ return err;
+
+ /* set cust sec size */
+ val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, as_ctrl->nfi_cfg.sec_size);
+ return regmap_update_bits(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SECCUS_SIZE,
+ SPI_NFI_CUS_SEC_SIZE, val);
+}
+
+static bool airoha_snand_is_page_ops(const struct spi_mem_op *op)
+{
+ if (op->addr.nbytes != 2)
+ return false;
+
+ if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
+ op->addr.buswidth != 4)
+ return false;
+
+ switch (op->data.dir) {
+ case SPI_MEM_DATA_IN:
+ /* check dummy cycle first */
+ if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > 0xf)
+ return false;
+
+ /* quad io / quad out */
+ if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) &&
+ op->data.buswidth == 4)
+ return true;
+
+ /* dual io / dual out */
+ if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) &&
+ op->data.buswidth == 2)
+ return true;
+
+ /* standard spi */
+ if (op->addr.buswidth == 1 && op->data.buswidth == 1)
+ return true;
+ break;
+ case SPI_MEM_DATA_OUT:
+ /* check dummy cycle first */
+ if (op->dummy.nbytes)
+ return false;
+
+ /* program load quad out */
+ if (op->addr.buswidth == 1 && op->data.buswidth == 4)
+ return true;
+
+ /* standard spi */
+ if (op->addr.buswidth == 1 && op->data.buswidth == 1)
+ return true;
+ default:
+ break;
+ }
+
+ return false;
+}
+
+static int airoha_snand_adjust_op_size(struct spi_mem *mem,
+ struct spi_mem_op *op)
+{
+ struct airoha_snand_ctrl *as_ctrl;
+ size_t len;
+
+ as_ctrl = spi_controller_get_devdata(mem->spi->controller);
+ if (airoha_snand_is_page_ops(op)) {
+ len = as_ctrl->nfi_cfg.sec_size;
+ len += as_ctrl->nfi_cfg.spare_size;
+ len *= as_ctrl->nfi_cfg.sec_num;
+ op->data.nbytes = min_t(size_t, op->data.nbytes, len);
+ } else {
+ len = 1 + op->addr.nbytes + op->dummy.nbytes;
+ if (len >= 160)
+ return -EOPNOTSUPP;
+
+ op->data.nbytes = min_t(size_t, op->data.nbytes, 160 - len);
+ }
+
+ return 0;
+}
+
+static bool airoha_snand_supports_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ if (!spi_mem_default_supports_op(mem, op))
+ return false;
+
+ if (op->cmd.buswidth != 1)
+ return false;
+
+ if (airoha_snand_is_page_ops(op))
+ return true;
+
+ return (!op->addr.nbytes || op->addr.buswidth == 1) &&
+ (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
+ (!op->data.nbytes || op->data.buswidth == 1);
+}
+
+static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(desc->mem->spi);
+
+ if (!as_dev->txrx_buf)
+ return -EINVAL;
+
+ if (desc->info.offset + desc->info.length > U32_MAX)
+ return -EINVAL;
+
+ if (!airoha_snand_supports_op(desc->mem, &desc->info.op_tmpl))
+ return -EOPNOTSUPP;
+
+ return 0;
+}
+
+static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, void *buf)
+{
+ struct spi_device *spi = desc->mem->spi;
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ struct spi_mem_op *op = &desc->info.op_tmpl;
+ struct airoha_snand_ctrl *as_ctrl;
+ u32 val, rd_mode;
+ int err;
+
+ if (!as_dev->data_need_update)
+ return len;
+
+ as_dev->data_need_update = false;
+
+ switch (op->cmd.opcode) {
+ case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
+ rd_mode = 1;
+ break;
+ case SPI_NAND_OP_READ_FROM_CACHE_QUAD:
+ rd_mode = 2;
+ break;
+ default:
+ rd_mode = 0;
+ break;
+ }
+
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_nfi_config(as_ctrl);
+ if (err)
+ return err;
+
+ dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ mb();
+
+ /* set dma addr */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
+ as_dev->dma_addr);
+ if (err)
+ return err;
+
+ /* set cust sec size */
+ val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
+ val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
+ err = regmap_update_bits(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_MISC_CTL2,
+ SPI_NFI_READ_DATA_BYTE_NUM, val);
+ if (err)
+ return err;
+
+ /* set read command */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL2,
+ op->cmd.opcode);
+ if (err)
+ return err;
+
+ /* set read mode */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
+ FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, rd_mode));
+ if (err)
+ return err;
+
+ /* set read addr */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 0x0);
+ if (err)
+ return err;
+
+ /* set nfi read */
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_OPMODE,
+ FIELD_PREP(SPI_NFI_OPMODE, 6));
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
+ if (err)
+ return err;
+
+ /* trigger dma start read */
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_RD_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_RD_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_STA_CTL1, val,
+ (val & SPI_NFI_READ_FROM_CACHE_DONE),
+ 0, USEC_PER_SEC);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
+ SPI_NFI_READ_FROM_CACHE_DONE);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
+ val, (val & SPI_NFI_AHB_DONE), 0,
+ USEC_PER_SEC);
+ if (err)
+ return err;
+
+ /* DMA read need delay for data ready from controller to DRAM */
+ udelay(1);
+
+ dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ memcpy(buf, as_dev->txrx_buf + offs, len);
+
+ return len;
+}
+
+static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, const void *buf)
+{
+ struct spi_device *spi = desc->mem->spi;
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ struct spi_mem_op *op = &desc->info.op_tmpl;
+ struct airoha_snand_ctrl *as_ctrl;
+ u32 wr_mode, val;
+ int err;
+
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ memcpy(as_dev->txrx_buf + offs, buf, len);
+ dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ mb();
+
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_nfi_config(as_ctrl);
+ if (err)
+ return err;
+
+ if (op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_QUAD ||
+ op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD)
+ wr_mode = 2;
+ else
+ wr_mode = 0;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
+ as_dev->dma_addr);
+ if (err)
+ return err;
+
+ val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
+ val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM, val);
+ err = regmap_update_bits(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_MISC_CTL2,
+ SPI_NFI_PROG_LOAD_BYTE_NUM, val);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL1,
+ FIELD_PREP(SPI_NFI_PG_LOAD_CMD,
+ op->cmd.opcode));
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
+ FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, wr_mode));
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 0x0);
+ if (err)
+ return err;
+
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_READ_MODE);
+ if (err)
+ return err;
+
+ err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_OPMODE,
+ FIELD_PREP(SPI_NFI_OPMODE, 3));
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+ SPI_NFI_DMA_MODE);
+ if (err)
+ return err;
+
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
+ if (err)
+ return err;
+
+ err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_WR_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ SPI_NFI_WR_TRIG);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
+ val, (val & SPI_NFI_AHB_DONE), 0,
+ USEC_PER_SEC);
+ if (err)
+ return err;
+
+ err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SNF_STA_CTL1, val,
+ (val & SPI_NFI_LOAD_TO_CACHE_DONE),
+ 0, USEC_PER_SEC);
+ if (err)
+ return err;
+
+ err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
+ SPI_NFI_LOAD_TO_CACHE_DONE);
+ if (err)
+ return err;
+
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ return len;
+}
+
+static int airoha_snand_exec_op(struct spi_mem *mem,
+ const struct spi_mem_op *op)
+{
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(mem->spi);
+ struct airoha_snand_ctrl *as_ctrl;
+ u8 data, opcode = op->cmd.opcode;
+ int i, err;
+
+ as_ctrl = spi_controller_get_devdata(mem->spi->controller);
+ if (opcode == SPI_NAND_OP_PROGRAM_EXECUTE &&
+ op->addr.val == as_dev->cur_page_num) {
+ as_dev->data_need_update = true;
+ } else if (opcode == SPI_NAND_OP_PAGE_READ) {
+ if (!as_dev->data_need_update &&
+ op->addr.val == as_dev->cur_page_num)
+ return 0;
+
+ as_dev->data_need_update = true;
+ as_dev->cur_page_num = op->addr.val;
+ }
+
+ /* switch to manual mode */
+ err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
+ if (err < 0)
+ return err;
+
+ err = airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_LOW);
+ if (err < 0)
+ return err;
+
+ /* opcode */
+ err = airoha_snand_write_data(as_ctrl, 0x8, &opcode, sizeof(opcode));
+ if (err)
+ return err;
+
+ /* addr part */
+ for (i = 0; i < op->addr.nbytes; i++) {
+ u8 cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
+
+ data = op->addr.val >> ((op->addr.nbytes - i - 1) * 8);
+ err = airoha_snand_write_data(as_ctrl, cmd, &data,
+ sizeof(data));
+ if (err)
+ return err;
+ }
+
+ /* dummy */
+ for (i = 0; i < op->dummy.nbytes; i++) {
+ data = 0xff;
+ err = airoha_snand_write_data(as_ctrl, 0x8, &data,
+ sizeof(data));
+ if (err)
+ return err;
+ }
+
+ /* data */
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ err = airoha_snand_read_data(as_ctrl, op->data.buf.in,
+ op->data.nbytes);
+ if (err)
+ return err;
+ } else {
+ err = airoha_snand_write_data(as_ctrl, 0x8, op->data.buf.out,
+ op->data.nbytes);
+ if (err)
+ return err;
+ }
+
+ return airoha_snand_set_cs(as_ctrl, SPI_CHIP_SEL_HIGH);
+}
+
+static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
+ .adjust_op_size = airoha_snand_adjust_op_size,
+ .supports_op = airoha_snand_supports_op,
+ .exec_op = airoha_snand_exec_op,
+ .dirmap_create = airoha_snand_dirmap_create,
+ .dirmap_read = airoha_snand_dirmap_read,
+ .dirmap_write = airoha_snand_dirmap_write,
+};
+
+#define SPI_NAND_CACHE_SIZE (4096 + 256)
+
+static int airoha_snand_setup(struct spi_device *spi)
+{
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ struct airoha_snand_ctrl *as_ctrl;
+
+ as_dev = kzalloc(sizeof(*as_dev), GFP_KERNEL);
+ if (!as_dev)
+ return -ENOMEM;
+
+ spi_set_ctldata(spi, as_dev);
+ as_dev->data_need_update = true;
+
+ /* prepare device buffer */
+ as_dev->buf_len = SPI_NAND_CACHE_SIZE;
+ as_dev->txrx_buf = kzalloc(as_dev->buf_len, GFP_KERNEL);
+ if (!as_dev->txrx_buf)
+ goto error_dev_free;
+
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+ as_dev->dma_addr = dma_map_single(as_ctrl->dev, as_dev->txrx_buf,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ if (dma_mapping_error(as_ctrl->dev, as_dev->dma_addr))
+ goto error_buf_free;
+
+ return 0;
+
+error_buf_free:
+ kfree(as_dev->txrx_buf);
+error_dev_free:
+ kfree(as_dev);
+
+ return -EINVAL;
+}
+
+static void airoha_snand_cleanup(struct spi_device *spi)
+{
+ struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
+ struct airoha_snand_ctrl *as_ctrl;
+
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+ dma_unmap_single(as_ctrl->dev, as_dev->dma_addr,
+ as_dev->buf_len, DMA_BIDIRECTIONAL);
+ kfree(as_dev->txrx_buf);
+
+ spi_set_ctldata(spi, NULL);
+}
+
+static int airoha_snand_nfi_setup(struct airoha_snand_ctrl *as_ctrl)
+{
+ u32 val, sec_size, sec_num;
+ int err;
+
+ err = regmap_read(as_ctrl->regmap_nfi, REG_SPI_NFI_CON, &val);
+ if (err)
+ return err;
+
+ sec_num = FIELD_GET(SPI_NFI_SEC_NUM, val);
+
+ err = regmap_read(as_ctrl->regmap_nfi,
+ REG_SPI_NFI_SECCUS_SIZE, &val);
+ if (err)
+ return err;
+
+ sec_size = FIELD_GET(SPI_NFI_CUS_SEC_SIZE, val);
+
+ /* init default value */
+ as_ctrl->nfi_cfg.sec_size = sec_size;
+ as_ctrl->nfi_cfg.sec_num = sec_num;
+ as_ctrl->nfi_cfg.page_size = rounddown(sec_size * sec_num, 1024);
+ as_ctrl->nfi_cfg.spare_size = 16;
+
+ err = airoha_snand_nfi_init(as_ctrl);
+ if (err)
+ return err;
+
+ return airoha_snand_nfi_config(as_ctrl);
+}
+
+static const struct regmap_config spi_ctrl_regmap_config = {
+ .name = "ctrl",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = REG_SPI_CTRL_NFI2SPI_EN,
+};
+
+static const struct regmap_config spi_nfi_regmap_config = {
+ .name = "nfi",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = REG_SPI_NFI_SNF_NFI_CNFG,
+};
+
+static const struct of_device_id airoha_snand_ids[] = {
+ { .compatible = "airoha,en7581-snand" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, airoha_snand_ids);
+
+static int airoha_snand_probe(struct platform_device *pdev)
+{
+ struct airoha_snand_ctrl *as_ctrl;
+ struct spi_controller *ctrl;
+ struct resource *res;
+ void __iomem *base;
+ int err;
+
+ ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(*as_ctrl));
+ if (!ctrl)
+ return -ENOMEM;
+
+ as_ctrl = spi_controller_get_devdata(ctrl);
+ as_ctrl->dev = &pdev->dev;
+
+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ as_ctrl->regmap_ctrl = devm_regmap_init_mmio(&pdev->dev, base,
+ &spi_ctrl_regmap_config);
+ if (IS_ERR(as_ctrl->regmap_ctrl)) {
+ dev_err(&pdev->dev, "failed to init spi ctrl regmap: %ld\n",
+ PTR_ERR(as_ctrl->regmap_ctrl));
+ return PTR_ERR(as_ctrl->regmap_ctrl);
+ }
+
+ base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ as_ctrl->regmap_nfi = devm_regmap_init_mmio(&pdev->dev, base,
+ &spi_nfi_regmap_config);
+ if (IS_ERR(as_ctrl->regmap_nfi)) {
+ dev_err(&pdev->dev, "failed to init spi nfi regmap: %ld\n",
+ PTR_ERR(as_ctrl->regmap_nfi));
+ return PTR_ERR(as_ctrl->regmap_nfi);
+ }
+
+ as_ctrl->spi_clk = devm_clk_get_enabled(&pdev->dev, "spi");
+ if (IS_ERR(as_ctrl->spi_clk)) {
+ dev_err(&pdev->dev, "unable to get spi clk");
+ return PTR_ERR(as_ctrl->spi_clk);
+ }
+
+ err = dma_set_mask(as_ctrl->dev, DMA_BIT_MASK(32));
+ if (err)
+ return err;
+
+ ctrl->num_chipselect = 2;
+ ctrl->mem_ops = &airoha_snand_mem_ops;
+ ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
+ ctrl->mode_bits = SPI_RX_DUAL;
+ ctrl->dev.of_node = pdev->dev.of_node;
+ ctrl->setup = airoha_snand_setup;
+ ctrl->cleanup = airoha_snand_cleanup;
+
+ err = airoha_snand_nfi_setup(as_ctrl);
+ if (err)
+ return err;
+
+ return devm_spi_register_controller(&pdev->dev, ctrl);
+}
+
+static struct platform_driver airoha_snand_driver = {
+ .driver = {
+ .name = "airoha-spi",
+ .of_match_table = airoha_snand_ids,
+ },
+ .probe = airoha_snand_probe,
+};
+
+module_platform_driver(airoha_snand_driver);
+
+MODULE_DESCRIPTION("Airoha SPI-NAND Flash Controller Driver");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Ray Liu <ray.liu@airoha.com>");
+MODULE_LICENSE("GPL");
--
2.44.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 2%]
* Re: [PATCH v2 09/43] arm64: RME: ioctls to create and configure realms
@ 2024-04-22 16:33 0% ` Steven Price
0 siblings, 0 replies; 200+ results
From: Steven Price @ 2024-04-22 16:33 UTC (permalink / raw)
To: Suzuki K Poulose, kvm, kvmarm
Cc: Catalin Marinas, Marc Zyngier, Will Deacon, James Morse,
Oliver Upton, Zenghui Yu, linux-arm-kernel, linux-kernel,
Joey Gouly, Alexandru Elisei, Christoffer Dall, Fuad Tabba,
linux-coco, Ganapatrao Kulkarni, Jean-Philippe Brucker
On 17/04/2024 10:51, Suzuki K Poulose wrote:
> Hi Steven
>
> On 12/04/2024 09:42, Steven Price wrote:
>> Add the KVM_CAP_ARM_RME_CREATE_FD ioctl to create a realm. This involves
>
> minor nit: s/FD/RD
>
>> delegating pages to the RMM to hold the Realm Descriptor (RD) and for
>> the base level of the Realm Translation Tables (RTT). A VMID also need
>> to be picked, since the RMM has a separate VMID address space a
>> dedicated allocator is added for this purpose.
>>
>> KVM_CAP_ARM_RME_CONFIG_REALM is provided to allow configuring the realm
>> before it is created.
>
> It might be helpful to provide a bit more background on the Realm
> parameters. Something like:
>
> Realm parameters for Realm Descriptor creation could be classified as:
>
> 1. Parameters specific to the Realm stage2 (e.g. IPA Size, vmid, stage2
> entry level, entry level RTTs, number of RTTs in start level, LPA2)
> Most of these are not measured by RMM and comes from KVM book
> keeping.
>
> 2. Parameters controlling "Arm Architecture features for the VM". (e.g.
> SVE VL, PMU counters, number of HW BRPs/WPs), configured by the VMM
> using the "user ID register write" mechanism. These will be
> supported in the later patches.
>
> 3. Parameters are not part of the core Arm architecture but defined
> by the RMM spec (e.g. Hash algorithm for measurement,
> Personalisation value). These are programmed via
> KVM_CAP_ARM_RME_CONFIG_REALM.
>
Thanks, I'll steal that wording ;)
>
> Also it may be a good idea to call out one of the issues that we have
> with the UABI w.r.t the IPA Size. The IPA Size supported by RMM *could*
> be different from the normal IPA Size as supported by KVM. We do not
> expect this to be common, but is not impossible.
>
> If the RMM_IPA_Size < Normal_IPA_Size, we have a problem with
> advertising the "IPA Size" to the VMM. Right now we advertise
> the "normal limit" by KVM_CAP_ARM_VM_IPA_SIZE and the IPA Size
> is configured via vm_type[7:0] in KVM_CREATE_VM. Given we have
> to configure the IPA size for a "Realm VM" at CREATE_VM time too,
> the VMM is unable to choose a valid IPA Size for the Realm. We
> have the following options:
>
> 1. Given IPA Size for a Realm is measured, the user must get
> what they choose. i.e., if the platform cannot support the
> requested size, don't run your Realm VM. In this case, we
> don't need to do anything.
>
> 2. Add KVM_CAP_ARM_VM_RMM_IPA_SIZE to expose the RMM limit
> for the VMM to choose.
>
> 3. VMM to create a Realm VM using the default IPA Size and then
> check the KVM_CAP_ARM_VM_IPA_SIZE on the "kvm" instance (which
> is Realm) and get the RMM IPA limit.
>
> I prefer 2 or 1, in that order of preference. Happy to hear suggestions.
My gut feeling is that we should go for 1, and add 2 if we actually see
a need for it.
I'm struggling to see why the VMM would want to choose the IPA size
dynamically (surely the attestation server doesn't want to deal with
different IPA sizes?). So the IPA size is going to be picked by the
container owner based on actual need and the VMM can attempt to create a
VM and fail if the platform doesn't support that size. In that case
because attestation would fail with a smaller IPA size the correct
response is failure.
I'll stick something in the commit message to record that.
>>
>> Co-developed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Steven Price <steven.price@arm.com>
>> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
>> ---
>> arch/arm64/include/asm/kvm_emulate.h | 5 +
>> arch/arm64/include/asm/kvm_rme.h | 19 ++
>> arch/arm64/kvm/arm.c | 18 ++
>> arch/arm64/kvm/mmu.c | 15 +-
>> arch/arm64/kvm/rme.c | 282 +++++++++++++++++++++++++++
>> 5 files changed, 337 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/kvm_emulate.h
>> b/arch/arm64/include/asm/kvm_emulate.h
>> index 6f08398537e2..c606316f4729 100644
>> --- a/arch/arm64/include/asm/kvm_emulate.h
>> +++ b/arch/arm64/include/asm/kvm_emulate.h
>> @@ -624,6 +624,11 @@ static inline enum realm_state
>> kvm_realm_state(struct kvm *kvm)
>> return READ_ONCE(kvm->arch.realm.state);
>> }
>> +static inline bool kvm_realm_is_created(struct kvm *kvm)
>> +{
>> + return kvm_is_realm(kvm) && kvm_realm_state(kvm) !=
>> REALM_STATE_NONE;
>> +}
>> +
>> static inline bool vcpu_is_rec(struct kvm_vcpu *vcpu)
>> {
>> return false;
>> diff --git a/arch/arm64/include/asm/kvm_rme.h
>> b/arch/arm64/include/asm/kvm_rme.h
>> index 922da3f47227..cf8cc4d30364 100644
>> --- a/arch/arm64/include/asm/kvm_rme.h
>> +++ b/arch/arm64/include/asm/kvm_rme.h
>> @@ -6,6 +6,8 @@
>> #ifndef __ASM_KVM_RME_H
>> #define __ASM_KVM_RME_H
>> +#include <uapi/linux/kvm.h>
>> +
>> /**
>> * enum realm_state - State of a Realm
>> */
>> @@ -46,11 +48,28 @@ enum realm_state {
>> * struct realm - Additional per VM data for a Realm
>> *
>> * @state: The lifetime state machine for the realm
>> + * @rd: Kernel mapping of the Realm Descriptor (RD)
>> + * @params: Parameters for the RMI_REALM_CREATE command
>> + * @num_aux: The number of auxiliary pages required by the RMM
>> + * @vmid: VMID to be used by the RMM for the realm
>> + * @ia_bits: Number of valid Input Address bits in the IPA
>> */
>> struct realm {
>> enum realm_state state;
>> +
>> + void *rd;
>> + struct realm_params *params;
>> +
>> + unsigned long num_aux;
>> + unsigned int vmid;
>> + unsigned int ia_bits;
>> };
>> int kvm_init_rme(void);
>> +u32 kvm_realm_ipa_limit(void);
>> +
>> +int kvm_realm_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap);
>> +int kvm_init_realm_vm(struct kvm *kvm);
>> +void kvm_destroy_realm(struct kvm *kvm);
>> #endif
>> diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
>> index 2056c660c5ee..5729ea430d6d 100644
>> --- a/arch/arm64/kvm/arm.c
>> +++ b/arch/arm64/kvm/arm.c
>> @@ -119,6 +119,13 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
>> }
>> mutex_unlock(&kvm->slots_lock);
>> break;
>> + case KVM_CAP_ARM_RME:
>> + if (!kvm_is_realm(kvm))
>> + return -EINVAL;
>> + mutex_lock(&kvm->lock);
>> + r = kvm_realm_enable_cap(kvm, cap);
>> + mutex_unlock(&kvm->lock);
>> + break;
>> default:
>> r = -EINVAL;
>> break;
>> @@ -179,6 +186,13 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned
>> long type)
>> bitmap_zero(kvm->arch.vcpu_features, KVM_VCPU_MAX_FEATURES);
>> + /* Initialise the realm bits after the generic bits are enabled */
>> + if (kvm_is_realm(kvm)) {
>> + ret = kvm_init_realm_vm(kvm);
>> + if (ret)
>> + goto err_free_cpumask;
>> + }
>> +
>> return 0;
>> err_free_cpumask:
>> @@ -219,6 +233,7 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
>> kvm_unshare_hyp(kvm, kvm + 1);
>> kvm_arm_teardown_hypercalls(kvm);
>> + kvm_destroy_realm(kvm);
>> }
>> int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
>> @@ -328,6 +343,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm,
>> long ext)
>> case KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES:
>> r = BIT(0);
>> break;
>> + case KVM_CAP_ARM_RME:
>> + r = static_key_enabled(&kvm_rme_is_available);
>> + break;
>> default:
>> r = 0;
>> }
>> diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
>> index 18680771cdb0..aae365647b62 100644
>> --- a/arch/arm64/kvm/mmu.c
>> +++ b/arch/arm64/kvm/mmu.c
>> @@ -872,6 +872,10 @@ int kvm_init_stage2_mmu(struct kvm *kvm, struct
>> kvm_s2_mmu *mmu, unsigned long t
>> struct kvm_pgtable *pgt;
>> u64 mmfr0, mmfr1;
>> u32 phys_shift;
>> + u32 ipa_limit = kvm_ipa_limit;
>> +
>> + if (kvm_is_realm(kvm))
>> + ipa_limit = kvm_realm_ipa_limit();
>> if (type & ~KVM_VM_TYPE_ARM_IPA_SIZE_MASK)
>> return -EINVAL;
>> @@ -880,12 +884,12 @@ int kvm_init_stage2_mmu(struct kvm *kvm, struct
>> kvm_s2_mmu *mmu, unsigned long t
>> if (is_protected_kvm_enabled()) {
>> phys_shift = kvm_ipa_limit;
>> } else if (phys_shift) {
>> - if (phys_shift > kvm_ipa_limit ||
>> + if (phys_shift > ipa_limit ||
>> phys_shift < ARM64_MIN_PARANGE_BITS)
>> return -EINVAL;
>> } else {
>> phys_shift = KVM_PHYS_SHIFT;
>> - if (phys_shift > kvm_ipa_limit) {
>> + if (phys_shift > ipa_limit) {
>> pr_warn_once("%s using unsupported default IPA limit,
>> upgrade your VMM\n",
>> current->comm);
>> return -EINVAL;
>> @@ -1014,6 +1018,13 @@ void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu)
>> struct kvm_pgtable *pgt = NULL;
>> write_lock(&kvm->mmu_lock);
>> + if (kvm_is_realm(kvm) &&
>> + (kvm_realm_state(kvm) != REALM_STATE_DEAD &&
>> + kvm_realm_state(kvm) != REALM_STATE_NONE)) {
>> + /* TODO: teardown rtts */
>> + write_unlock(&kvm->mmu_lock);
>> + return;
>> + }
>
> This needs a comment to explain the rationale of deferring the
> Stage2 pgt freeing. Something like :
>
> /*
> * For realms, we can free the entry level RTTs
> * only after :
> * 1. All of the stage2 mappings are torn down.
> * 2. The Realm has been destroyed.
> *
> * So, come back later once the RD has been destroyed.
> */
Actually the 'TODO' is really "this is handled in a future patch". I'll
make that more obvious.
>> pgt = mmu->pgt;
>> if (pgt) {
>> mmu->pgd_phys = 0;
>> diff --git a/arch/arm64/kvm/rme.c b/arch/arm64/kvm/rme.c
>> index 3dbbf9d046bf..658d14e8d87d 100644
>> --- a/arch/arm64/kvm/rme.c
>> +++ b/arch/arm64/kvm/rme.c
>> @@ -5,9 +5,20 @@
>> #include <linux/kvm_host.h>
>> +#include <asm/kvm_emulate.h>
>> +#include <asm/kvm_mmu.h>
>> #include <asm/rmi_cmds.h>
>> #include <asm/virt.h>
>> +#include <asm/kvm_pgtable.h>
>> +
>> +static unsigned long rmm_feat_reg0;
>> +
>> +static bool rme_supports(unsigned long feature)
>> +{
>> + return !!u64_get_bits(rmm_feat_reg0, feature);
>> +}
>> +
>> static int rmi_check_version(void)
>> {
>> struct arm_smccc_res res;
>> @@ -36,8 +47,272 @@ static int rmi_check_version(void)
>> return 0;
>> }
>> +u32 kvm_realm_ipa_limit(void)
>> +{
>> + return u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_S2SZ);
>> +}
>> +
>> +static int get_start_level(struct realm *realm)
>> +{
>> + return 4 - stage2_pgtable_levels(realm->ia_bits);
>> +}
>> +
>> +static int realm_create_rd(struct kvm *kvm)
>> +{
>> + struct realm *realm = &kvm->arch.realm;
>> + struct realm_params *params = realm->params;
>> + void *rd = NULL;
>> + phys_addr_t rd_phys, params_phys;
>> + struct kvm_pgtable *pgt = kvm->arch.mmu.pgt;
>> + int i, r;
>> +
>> + if (WARN_ON(realm->rd) || WARN_ON(!realm->params))
>> + return -EEXIST;
>> +
>> + rd = (void *)__get_free_page(GFP_KERNEL);
>> + if (!rd)
>> + return -ENOMEM;
>> +
>> + rd_phys = virt_to_phys(rd);
>> + if (rmi_granule_delegate(rd_phys)) {
>> + r = -ENXIO;
>> + goto out;
>
> super minor nit: s/out/free_rd/ is a bit more readable. Here "out" is
> only used for error exits and could be confusing.
It's a good point - I'll fix.
>> + }
>> +
>> + for (i = 0; i < pgt->pgd_pages; i++) {
>> + phys_addr_t pgd_phys = kvm->arch.mmu.pgd_phys + i * PAGE_SIZE;
>> +
>> + if (rmi_granule_delegate(pgd_phys)) {
>> + r = -ENXIO;
>> + goto out_undelegate_tables;
>> + }
>> + }
>> +
>> + realm->ia_bits = VTCR_EL2_IPA(kvm->arch.mmu.vtcr);
>> +
>> + params->rtt_level_start = get_start_level(realm);
>> + params->rtt_num_start = pgt->pgd_pages;
>> + params->rtt_base = kvm->arch.mmu.pgd_phys;
>> + params->vmid = realm->vmid;
>> +
>> + params_phys = virt_to_phys(params);
>> +
>> + if (rmi_realm_create(rd_phys, params_phys)) {
>> + r = -ENXIO;
>> + goto out_undelegate_tables;
>> + }
>> +
>> + realm->rd = rd;
>> +
>> + if (WARN_ON(rmi_rec_aux_count(rd_phys, &realm->num_aux))) {
>> + WARN_ON(rmi_realm_destroy(rd_phys));
>> + goto out_undelegate_tables;
>> + }
>> +
>> + return 0;
>> +
>> +out_undelegate_tables:
>> + while (--i >= 0) {
>> + phys_addr_t pgd_phys = kvm->arch.mmu.pgd_phys + i * PAGE_SIZE;
>> +
>> + WARN_ON(rmi_granule_undelegate(pgd_phys));
>> + }
>> + WARN_ON(rmi_granule_undelegate(rd_phys));
>> +out:
>> + free_page((unsigned long)rd);
>> + return r;
>> +}
>> +
>> +/* Protects access to rme_vmid_bitmap */
>> +static DEFINE_SPINLOCK(rme_vmid_lock);
>> +static unsigned long *rme_vmid_bitmap;
>> +
>> +static int rme_vmid_init(void)
>> +{
>> + unsigned int vmid_count = 1 << kvm_get_vmid_bits();
>
> minor nit: RMM has a fixed VMID width of 16bits. Do we need to
> explicitly use that, instead of relying what kvm thinks ? (Though
> in practise, this would only be a problem if the architecture
> evolves to support something more).
I don't think the RMM has a fixed VMID width according to the spec. It says:
The VMID of a Realm is chosen by the Host. The VMID must be within the
range supported by the hardware platform. The RMM ensures that every
Realm on the system has a unique VMID.
It also declares a pseudo-code VmidIsValid function which says:
If the underlying hardware platform does not implement FEAT_VMID16 then
a VMID value with vmid[15:8] != 0 is invalid.
So it would seem from the spec that a VMID width <16 bits is supported.
On the other hand if we ever get >16 bit VMID support in the
architecture then the 16 bit vmid field in RmiRealmParams is clearly
going to trip us up.
At the moment my feeling is that 16 bit VMIDs ought to be enough for
anybody ... ;)
>> +
>> + rme_vmid_bitmap = bitmap_zalloc(vmid_count, GFP_KERNEL);
>> + if (!rme_vmid_bitmap) {
>> + kvm_err("%s: Couldn't allocate rme vmid bitmap\n", __func__);
>> + return -ENOMEM;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int rme_vmid_reserve(void)
>> +{
>> + int ret;
>> + unsigned int vmid_count = 1 << kvm_get_vmid_bits();
>> +
>> + spin_lock(&rme_vmid_lock);
>> + ret = bitmap_find_free_region(rme_vmid_bitmap, vmid_count, 0);
>> + spin_unlock(&rme_vmid_lock);
>> +
>> + return ret;
>> +}
>> +
>> +static void rme_vmid_release(unsigned int vmid)
>> +{
>> + spin_lock(&rme_vmid_lock);
>> + bitmap_release_region(rme_vmid_bitmap, vmid, 0);
>> + spin_unlock(&rme_vmid_lock);
>> +}
>> +
>> +static int kvm_create_realm(struct kvm *kvm)
>> +{
>> + struct realm *realm = &kvm->arch.realm;
>> + int ret;
>> +
>> + if (!kvm_is_realm(kvm) || kvm_realm_is_created(kvm))
>> + return -EEXIST;
>
> Minor nit:
>
> if (!kvm_is_realm(kvm)
> return -EIO or even -EINVAL ?
>
> if (kvm_realm_is_created(kvm))
> return -EEXIST;
Indeed EEXIST is a terrible error code for !realm. My preference is EIO.
>> +
>> + ret = rme_vmid_reserve();
>> + if (ret < 0)
>> + return ret;
>> + realm->vmid = ret;
>> +
>> + ret = realm_create_rd(kvm);
>> + if (ret) {
>> + rme_vmid_release(realm->vmid);
>> + return ret;
>> + }
>> +
>> + WRITE_ONCE(realm->state, REALM_STATE_NEW);
>> +
>> + /* The realm is up, free the parameters. */
>> + free_page((unsigned long)realm->params);
>> + realm->params = NULL;
>> +
>> + return 0;
>> +}
>> +
>> +static int config_realm_hash_algo(struct realm *realm,
>> + struct kvm_cap_arm_rme_config_item *cfg)
>> +{
>> + switch (cfg->hash_algo) {
>> + case KVM_CAP_ARM_RME_MEASUREMENT_ALGO_SHA256:
>> + if (!rme_supports(RMI_FEATURE_REGISTER_0_HASH_SHA_256))
>> + return -EINVAL;
>> + break;
>> + case KVM_CAP_ARM_RME_MEASUREMENT_ALGO_SHA512:
>> + if (!rme_supports(RMI_FEATURE_REGISTER_0_HASH_SHA_512))
>> + return -EINVAL;
>
> Do we need to add a comment here on why we don't expose the supported
> "hash" algo as part of the UABI ? Something like :
>
> /*
> * The hash algorithm for the measurements is a choosen by
> * the Realm owner (since it affects the attestation), we
> * would like the owner to get what they wants.
> */
I'm not really sure here's the right place for such a comment. Clearly
here we're just doing whatever the VMM requested and returning -EINVAL
if it's not supported (by KVM or the RMM).
There is the bigger question on whether discovery of the RMM's feature
set is necessary and easy enough with the current uAPI. As you say there
is a reasonable argument that the VMM doesn't have a choice so there's
no need for discovery. Equally adding an extra CAP ioctl for discovery
later is easy enough.
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> + realm->params->hash_algo = cfg->hash_algo;
>> + return 0;
>> +}
>> +
>> +static int kvm_rme_config_realm(struct kvm *kvm, struct
>> kvm_enable_cap *cap)
>> +{
>> + struct kvm_cap_arm_rme_config_item cfg;
>> + struct realm *realm = &kvm->arch.realm;
>> + int r = 0;
>> +
>> + if (kvm_realm_is_created(kvm))
>> + return -EINVAL;
>
> minor nit: May be return -EEXIST or -EIO rather than, "Invalid
> (parameter)" ?
Yep, although EBUSY seems like the most descriptive to me.
>
>> +
>> + if (copy_from_user(&cfg, (void __user *)cap->args[1], sizeof(cfg)))
>> + return -EFAULT;
>> +
>> + switch (cfg.cfg) {
>> + case KVM_CAP_ARM_RME_CFG_RPV:
>> + memcpy(&realm->params->rpv, &cfg.rpv, sizeof(cfg.rpv));
>> + break;
>> + case KVM_CAP_ARM_RME_CFG_HASH_ALGO:
>> + r = config_realm_hash_algo(realm, &cfg);
>> + break;
>> + default:
>> + r = -EINVAL;
>> + }
>> +
>> + return r;
>> +}
>> +
>> +int kvm_realm_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap)
>> +{
>> + int r = 0;
>> +
>> + if (!kvm_is_realm(kvm))
>> + return -EINVAL;
>> +
>> + switch (cap->args[0]) {
>> + case KVM_CAP_ARM_RME_CONFIG_REALM:
>> + r = kvm_rme_config_realm(kvm, cap);
>> + break;
>> + case KVM_CAP_ARM_RME_CREATE_RD:
>> + r = kvm_create_realm(kvm);
>> + break;
>> + default:
>> + r = -EINVAL;
>> + break;
>> + }
>> +
>> + return r;
>> +}
>> +
>> +void kvm_destroy_realm(struct kvm *kvm)
>> +{
>> + struct realm *realm = &kvm->arch.realm;
>> + struct kvm_pgtable *pgt = kvm->arch.mmu.pgt;
>> + int i;
>> +
>> + if (realm->params) {
>> + free_page((unsigned long)realm->params);
>> + realm->params = NULL;
>> + }
>> +
>> + if (!kvm_realm_is_created(kvm))
>> + return;
>> +
>> + WRITE_ONCE(realm->state, REALM_STATE_DYING);
>> +
>> + if (realm->rd) {
>> + phys_addr_t rd_phys = virt_to_phys(realm->rd);
>> +
>> + if (WARN_ON(rmi_realm_destroy(rd_phys)))
>> + return;
>> + if (WARN_ON(rmi_granule_undelegate(rd_phys)))
>> + return;
>> + free_page((unsigned long)realm->rd);
>> + realm->rd = NULL;
>> + }
>> +
>> + rme_vmid_release(realm->vmid);
>> +
>> + for (i = 0; i < pgt->pgd_pages; i++) {
>> + phys_addr_t pgd_phys = kvm->arch.mmu.pgd_phys + i * PAGE_SIZE;
>> +
>> + if (WARN_ON(rmi_granule_undelegate(pgd_phys)))
>> + return;
>> + }
>> +
>> + WRITE_ONCE(realm->state, REALM_STATE_DEAD);
>> +
>
> May be add in a comment here:
>
> /* Now that the Realm is destroyed, free the entry level RTTs */
>> + kvm_free_stage2_pgd(&kvm->arch.mmu);
>
>
>
>> +}
>> +
>> +int kvm_init_realm_vm(struct kvm *kvm)
>> +{
>> + struct realm_params *params;
>> +
>> + params = (struct realm_params *)get_zeroed_page(GFP_KERNEL);
>> + if (!params)
>> + return -ENOMEM;
>> +
>> + /* Default parameters, not exposed to user space */
>
> This is a bit misleading. The value comes from the userspace and...
>
>> + params->s2sz = VTCR_EL2_IPA(kvm->arch.mmu.vtcr);
>
> (minor nit) we initialise most of the params, including those that come
> from KVM later. So, as such may be a good idea to move it together at
> create_realm, unless we need it.
Indeed I'll move this to create_realm.
Thanks,
Steve
>> + kvm->arch.realm.params = params;
>> + return 0;
>> +}
>> +
>> int kvm_init_rme(void)
>> {
>> + int ret;
>> +
>> if (PAGE_SIZE != SZ_4K)
>> /* Only 4k page size on the host is supported */
>> return 0;
>> @@ -46,6 +321,13 @@ int kvm_init_rme(void)
>> /* Continue without realm support */
>> return 0;
>> + if (WARN_ON(rmi_features(0, &rmm_feat_reg0)))
>> + return 0;
>> +
>> + ret = rme_vmid_init();
>> + if (ret)
>> + return ret;
>> +
>> /* Future patch will enable static branch kvm_rme_is_available */
>> return 0;
>
>
> Suzuki
>
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^ permalink raw reply [relevance 0%]
* Re: [RFC PATCH v3 4/6] dt-bindings: clock: meson: document A1 SoC audio clock controller driver
2024-04-22 14:31 0% ` Jan Dakinevich
@ 2024-04-22 15:38 0% ` Jerome Brunet
2024-04-22 15:43 0% ` Jan Dakinevich
1 sibling, 0 replies; 200+ results
From: Jerome Brunet @ 2024-04-22 15:38 UTC (permalink / raw)
To: Jan Dakinevich
Cc: Jerome Brunet, Krzysztof Kozlowski, Rob Herring, Neil Armstrong,
Michael Turquette, Stephen Boyd, Krzysztof Kozlowski,
Conor Dooley, Kevin Hilman, Martin Blumenstingl, Philipp Zabel,
Jiucheng Xu, linux-amlogic, linux-clk, devicetree, linux-kernel,
linux-arm-kernel
On Mon 22 Apr 2024 at 17:31, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:
> On 4/22/24 10:57, Jerome Brunet wrote:
>>
>> On Mon 22 Apr 2024 at 09:16, Jerome Brunet <jbrunet@baylibre.com> wrote:
>>
>>> On Sun 21 Apr 2024 at 20:14, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>
>>>> On 20/04/2024 18:15, Jan Dakinevich wrote:
>>>>>
>>>>>
>>>>> On 4/20/24 00:09, Rob Herring wrote:
>>>>>> On Fri, Apr 19, 2024 at 03:58:10PM +0300, Jan Dakinevich wrote:
>>>>>>> Add device tree bindings for A1 SoC audio clock and reset controllers.
>>>>>>>
>>>>>>> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>>>>>>> ---
>>>>>>>
>>>>>>> This controller has 6 mandatory and up to 20 optional clocks. To describe
>>>>>>> this, I use 'additionalItems'. It produces correct processed-schema.json:
>>>>>>>
>>>>>>> "clock-names": {
>>>>>>> "maxItems": 26,
>>>>>>> "items": [
>>>>>>> {
>>>>>>> "const": "pclk"
>>>>>>> },
>>>>>>> {
>>>>>>> "const": "dds_in"
>>>>>>> },
>>>>>>> {
>>>>>>> "const": "fclk_div2"
>>>>>>> },
>>>>>>> {
>>>>>>> "const": "fclk_div3"
>>>>>>> },
>>>>>>> {
>>>>>>> "const": "hifi_pll"
>>>>>>> },
>>>>>>> {
>>>>>>> "const": "xtal"
>>>>>>> }
>>>>>>> ],
>>>>>>> "additionalItems": {
>>>>>>> "oneOf": [
>>>>>>> {
>>>>>>> "pattern": "^slv_sclk[0-9]$"
>>>>>>> },
>>>>>>> {
>>>>>>> "pattern": "^slv_lrclk[0-9]$"
>>>>>>> }
>>>>>>> ]
>>>>>>> },
>>>>>>> "type": "array",
>>>>>>> "minItems": 6
>>>>>>> },
>>>>>>>
>>>>>>> and it behaves as expected. However, the checking is followed by
>>>>>>> complaints like this:
>>>>>>>
>>>>>>> Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml: properties:clock-names:additionalItems: {'oneOf': [{'pattern': '^slv_sclk[0-9]$'}, {'pattern': '^slv_lrclk[0-9]$'}]} is not of type 'boolean'
>>>>>>>
>>>>>>> And indeed, 'additionalItems' has boolean type in meta-schema. So, how to
>>>>>>> do it right?
>>>>>>
>>>>>> The meta-schemas are written both to prevent nonsense that json-schema
>>>>>> allows by default (e.g additionalitems (wrong case)) and constraints to
>>>>>> follow the patterns we expect. I'm happy to loosen the latter case if
>>>>>> there's really a need.
>>>>>>
>>>>>> Generally, most bindings shouldn't be using 'additionalItems' at all as
>>>>>> all entries should be defined, but there's a few exceptions. Here, the
>>>>>> only reasoning I see is 26 entries is a lot to write out, but that
>>>>>> wouldn't really justify it.
>>>>>
>>>>> Writing a lot of entries don't scary me too much, but the reason is that
>>>>> the existence of optional clock sources depends on schematics. Also, we
>>>>
>>>> Aren't you documenting SoC component, not a board? So how exactly it
>>>> depends on schematics? SoC is done or not done...
>>>>
>>>>> unable to declare dt-nodes for 'clocks' array in any generic way,
>>>>> because their declaration would depends on that what is actually
>>>>> connected to the SoC (dt-node could be "fixed-clock" with specific rate
>>>>> or something else).
>>>>
>>>> So these are clock inputs to the SoC?
>>>>
>>>
>>> Yes, possibly.
>>> Like an external crystal or a set clocks provided by an external codec
>>> where the codec is the clock master of the link.
>>>
>>> This is same case as the AXG that was discussed here:
>>> https://lore.kernel.org/linux-devicetree/20230808194811.113087-1-alexander.stein@mailbox.org/
>>>
>>> IMO, like the AXG, only the pclk is a required clock.
>>> All the others - master and slave clocks - are optional.
>>> The controller is designed to operate with grounded inputs
>>
>> Looking again at the implementation of the controller, there is a clear
>> indication in patch 3 that the controller interface is the same as the
>> AXG and that the above statement is true.
>> > The AXG had 8 master clocks wired in. The A1 just has 5 - and 3 grounded
>> master clocks. This is why you to had to provide a mux input table to
>> skip the grounded inputs. You would not have to do so if the controller was
>> properly declared with the 8 master clock input, as it actually is.
>>
>
> For simplicity, I could make something like this in device tree:
>
> clocks = <&clk0,
> &clk1,
> &clk2,
> &clk3,
> &clk4,
> 0,
> 0,
> 0>
> clock-names = <"mst_in0",
> "mst_in1",
> "mst_in2"
> "mst_in2"
> "mst_in3"
> "mst_in4"
> "mst_in5"
> "mst_in6"
> "mst_in7">
>
> But I don't see in the doc that the last 3 clocks are grounded to
> anywhere. It will be just community's assumption about internals of the
> controller.
Maybe so. Given how much we know about the amlogic HW, there will always be
assumptions (... and corrections). It is a fare assumption to
make. Looking at definitions for the master clocks or the TDM clocks,
you can see that the HW is same, only what is wired in has changed.
The register definition of the master clocks is still the same.
You may still put a '6' in the register, you just don't know where it
goes. Physically it may exist IMO.
I'll agree only the 5 first mst inputs are documented ATM.
Go ahead with a different interface but at least fix the names please.
>
> Anyway, I still don't understand what to do with external slv_* clocks.
> I can do the same as in example above: list slv_(s|lr)clk[0-9] in
> "clock-names" and fill the rest if "clocks" by "0" phandles.
>
You don't have to put them in the example when there is only <0> to the end.
>> It also shows that it is a bad idea to name input after what is coming
>> in (like you do with "dds_in" or "fclk_div2") instead of what they
>> actually are like in the AXG (mst0, mst1, etc ...)
>>
>
> I agree, these are not the best names.
>
>>>
>>>>>
>>>>> By the way, I don't know any example (neither for A1 SoC nor for other
>>>>> Amlogic's SoCs) where these optional clocks are used, but they are
>>>>> allowed by hw.
>>>
>>> Those scenario exists and have been tested. There is just no dts using
>>> that upstream because they are all mostly copy of the AML ref design.
>>>
>>>>>
>>>>> This is my understanding of this controller. I hope, Jerome Brunet will
>>>>> clarify how it actually works.
>>>>
>>>
>>> I think the simpliest way to deal with this to just list all the clocks
>>> with 'minItems = 1'. It is going be hard to read with a lot of '<0>,' in
>>> the DTS when do need those slave clocks but at least the binding doc
>>> will be simple.
>>>
>>>> Best regards,
>>>> Krzysztof
>>>
>>> If you are going ahead with this, please name the file
>>> amlogic,axg-audio-clkc.yaml because this is really the first controller
>>> of the type and is meant to be documented in the same file.
>>>
>>> You are free to handle the conversion of the AXG at the same time if
>>> you'd like. It would be much appreciated if you do.
>>
>>
--
Jerome
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^ permalink raw reply [relevance 0%]
* Re: [RFC PATCH v3 4/6] dt-bindings: clock: meson: document A1 SoC audio clock controller driver
2024-04-22 14:31 0% ` Jan Dakinevich
2024-04-22 15:38 0% ` Jerome Brunet
@ 2024-04-22 15:43 0% ` Jan Dakinevich
1 sibling, 0 replies; 200+ results
From: Jan Dakinevich @ 2024-04-22 15:43 UTC (permalink / raw)
To: Jerome Brunet
Cc: Krzysztof Kozlowski, Rob Herring, Neil Armstrong,
Michael Turquette, Stephen Boyd, Krzysztof Kozlowski,
Conor Dooley, Kevin Hilman, Martin Blumenstingl, Philipp Zabel,
Jiucheng Xu, linux-amlogic, linux-clk, devicetree, linux-kernel,
linux-arm-kernel
On 4/22/24 17:31, Jan Dakinevich wrote:
>
>
> On 4/22/24 10:57, Jerome Brunet wrote:
>>
>> On Mon 22 Apr 2024 at 09:16, Jerome Brunet <jbrunet@baylibre.com> wrote:
>>
>>> On Sun 21 Apr 2024 at 20:14, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>
>>>> On 20/04/2024 18:15, Jan Dakinevich wrote:
>>>>>
>>>>>
>>>>> On 4/20/24 00:09, Rob Herring wrote:
>>>>>> On Fri, Apr 19, 2024 at 03:58:10PM +0300, Jan Dakinevich wrote:
>>>>>>> Add device tree bindings for A1 SoC audio clock and reset controllers.
>>>>>>>
>>>>>>> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>>>>>>> ---
>>>>>>>
>>>>>>> This controller has 6 mandatory and up to 20 optional clocks. To describe
>>>>>>> this, I use 'additionalItems'. It produces correct processed-schema.json:
>>>>>>>
>>>>>>> "clock-names": {
>>>>>>> "maxItems": 26,
>>>>>>> "items": [
>>>>>>> {
>>>>>>> "const": "pclk"
>>>>>>> },
>>>>>>> {
>>>>>>> "const": "dds_in"
>>>>>>> },
>>>>>>> {
>>>>>>> "const": "fclk_div2"
>>>>>>> },
>>>>>>> {
>>>>>>> "const": "fclk_div3"
>>>>>>> },
>>>>>>> {
>>>>>>> "const": "hifi_pll"
>>>>>>> },
>>>>>>> {
>>>>>>> "const": "xtal"
>>>>>>> }
>>>>>>> ],
>>>>>>> "additionalItems": {
>>>>>>> "oneOf": [
>>>>>>> {
>>>>>>> "pattern": "^slv_sclk[0-9]$"
>>>>>>> },
>>>>>>> {
>>>>>>> "pattern": "^slv_lrclk[0-9]$"
>>>>>>> }
>>>>>>> ]
>>>>>>> },
>>>>>>> "type": "array",
>>>>>>> "minItems": 6
>>>>>>> },
>>>>>>>
>>>>>>> and it behaves as expected. However, the checking is followed by
>>>>>>> complaints like this:
>>>>>>>
>>>>>>> Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml: properties:clock-names:additionalItems: {'oneOf': [{'pattern': '^slv_sclk[0-9]$'}, {'pattern': '^slv_lrclk[0-9]$'}]} is not of type 'boolean'
>>>>>>>
>>>>>>> And indeed, 'additionalItems' has boolean type in meta-schema. So, how to
>>>>>>> do it right?
>>>>>>
>>>>>> The meta-schemas are written both to prevent nonsense that json-schema
>>>>>> allows by default (e.g additionalitems (wrong case)) and constraints to
>>>>>> follow the patterns we expect. I'm happy to loosen the latter case if
>>>>>> there's really a need.
>>>>>>
>>>>>> Generally, most bindings shouldn't be using 'additionalItems' at all as
>>>>>> all entries should be defined, but there's a few exceptions. Here, the
>>>>>> only reasoning I see is 26 entries is a lot to write out, but that
>>>>>> wouldn't really justify it.
>>>>>
>>>>> Writing a lot of entries don't scary me too much, but the reason is that
>>>>> the existence of optional clock sources depends on schematics. Also, we
>>>>
>>>> Aren't you documenting SoC component, not a board? So how exactly it
>>>> depends on schematics? SoC is done or not done...
>>>>
>>>>> unable to declare dt-nodes for 'clocks' array in any generic way,
>>>>> because their declaration would depends on that what is actually
>>>>> connected to the SoC (dt-node could be "fixed-clock" with specific rate
>>>>> or something else).
>>>>
>>>> So these are clock inputs to the SoC?
>>>>
>>>
>>> Yes, possibly.
>>> Like an external crystal or a set clocks provided by an external codec
>>> where the codec is the clock master of the link.
>>>
>>> This is same case as the AXG that was discussed here:
>>> https://lore.kernel.org/linux-devicetree/20230808194811.113087-1-alexander.stein@mailbox.org/
>>>
>>> IMO, like the AXG, only the pclk is a required clock.
>>> All the others - master and slave clocks - are optional.
>>> The controller is designed to operate with grounded inputs
>>
>> Looking again at the implementation of the controller, there is a clear
>> indication in patch 3 that the controller interface is the same as the
>> AXG and that the above statement is true.
>>> The AXG had 8 master clocks wired in. The A1 just has 5 - and 3 grounded
>> master clocks. This is why you to had to provide a mux input table to
>> skip the grounded inputs. You would not have to do so if the controller was
>> properly declared with the 8 master clock input, as it actually is.
>>
>
> For simplicity, I could make something like this in device tree:
>
> clocks = <&clk0,
> &clk1,
> &clk2,
> &clk3,
> &clk4,
> 0,
> 0,
> 0>
> clock-names = <"mst_in0",
> "mst_in1",
> "mst_in2"
> "mst_in2"
> "mst_in3"
> "mst_in4"
> "mst_in5"
> "mst_in6"
> "mst_in7">
>
> But I don't see in the doc that the last 3 clocks are grounded to
> anywhere. It will be just community's assumption about internals of the
> controller.
>
> Anyway, I still don't understand what to do with external slv_* clocks.
> I can do the same as in example above: list slv_(s|lr)clk[0-9] in
> "clock-names" and fill the rest if "clocks" by "0" phandles.
>
Sorry, I missed that you suggested similar thing:
>>> I think the simpliest way to deal with this to just list all the clocks
>>> with 'minItems = 1'. It is going be hard to read with a lot of '<0>,' in
>>> the DTS when do need those slave clocks but at least the binding doc
>>> will be simple.
But, may be it could be better to claim that all clocks are mandatory
and list all of them (including slv_*)? So, 'minItems = 1' can be
omitted. What do you think?
clocks = <&pclk,
&clk0,
&clk1,
&clk2,
&clk3,
&clk4,
0,
0,
0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0>;
clock-names = <"pclk",
"mst_in0",
"mst_in1",
"mst_in2"
"mst_in2"
"mst_in3"
"mst_in4"
"mst_in5"
"mst_in6"
"mst_in7",
"slv_sclk0",
"slv_sclk1",
"slv_sclk2",
"slv_sclk3",
"slv_sclk4",
"slv_sclk5",
"slv_sclk6",
"slv_sclk7",
"slv_sclk8",
"slv_sclk9",
"slv_lrclk0",
"slv_lrclk1",
"slv_lrclk2",
"slv_lrclk3",
"slv_lrclk4",
"slv_lrclk5",
"slv_lrclk6",
"slv_lrclk7",
"slv_lrclk8",
"slv_lrclk9">;
>> It also shows that it is a bad idea to name input after what is coming
>> in (like you do with "dds_in" or "fclk_div2") instead of what they
>> actually are like in the AXG (mst0, mst1, etc ...)
>>
>
> I agree, these are not the best names.
>
>>>
>>>>>
>>>>> By the way, I don't know any example (neither for A1 SoC nor for other
>>>>> Amlogic's SoCs) where these optional clocks are used, but they are
>>>>> allowed by hw.
>>>
>>> Those scenario exists and have been tested. There is just no dts using
>>> that upstream because they are all mostly copy of the AML ref design.
>>>
>>>>>
>>>>> This is my understanding of this controller. I hope, Jerome Brunet will
>>>>> clarify how it actually works.
>>>>
>>>
>>> I think the simpliest way to deal with this to just list all the clocks
>>> with 'minItems = 1'. It is going be hard to read with a lot of '<0>,' in
>>> the DTS when do need those slave clocks but at least the binding doc
>>> will be simple.
>>>
>>>> Best regards,
>>>> Krzysztof
>>>
>>> If you are going ahead with this, please name the file
>>> amlogic,axg-audio-clkc.yaml because this is really the first controller
>>> of the type and is meant to be documented in the same file.
>>>
>>> You are free to handle the conversion of the AXG at the same time if
>>> you'd like. It would be much appreciated if you do.
>>
>>
>
--
Best regards
Jan Dakinevich
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* Re: [RFC PATCH v3 4/6] dt-bindings: clock: meson: document A1 SoC audio clock controller driver
@ 2024-04-22 14:31 0% ` Jan Dakinevich
2024-04-22 15:38 0% ` Jerome Brunet
2024-04-22 15:43 0% ` Jan Dakinevich
0 siblings, 2 replies; 200+ results
From: Jan Dakinevich @ 2024-04-22 14:31 UTC (permalink / raw)
To: Jerome Brunet
Cc: Krzysztof Kozlowski, Rob Herring, Neil Armstrong,
Michael Turquette, Stephen Boyd, Krzysztof Kozlowski,
Conor Dooley, Kevin Hilman, Martin Blumenstingl, Philipp Zabel,
Jiucheng Xu, linux-amlogic, linux-clk, devicetree, linux-kernel,
linux-arm-kernel
On 4/22/24 10:57, Jerome Brunet wrote:
>
> On Mon 22 Apr 2024 at 09:16, Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>> On Sun 21 Apr 2024 at 20:14, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>>> On 20/04/2024 18:15, Jan Dakinevich wrote:
>>>>
>>>>
>>>> On 4/20/24 00:09, Rob Herring wrote:
>>>>> On Fri, Apr 19, 2024 at 03:58:10PM +0300, Jan Dakinevich wrote:
>>>>>> Add device tree bindings for A1 SoC audio clock and reset controllers.
>>>>>>
>>>>>> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>>>>>> ---
>>>>>>
>>>>>> This controller has 6 mandatory and up to 20 optional clocks. To describe
>>>>>> this, I use 'additionalItems'. It produces correct processed-schema.json:
>>>>>>
>>>>>> "clock-names": {
>>>>>> "maxItems": 26,
>>>>>> "items": [
>>>>>> {
>>>>>> "const": "pclk"
>>>>>> },
>>>>>> {
>>>>>> "const": "dds_in"
>>>>>> },
>>>>>> {
>>>>>> "const": "fclk_div2"
>>>>>> },
>>>>>> {
>>>>>> "const": "fclk_div3"
>>>>>> },
>>>>>> {
>>>>>> "const": "hifi_pll"
>>>>>> },
>>>>>> {
>>>>>> "const": "xtal"
>>>>>> }
>>>>>> ],
>>>>>> "additionalItems": {
>>>>>> "oneOf": [
>>>>>> {
>>>>>> "pattern": "^slv_sclk[0-9]$"
>>>>>> },
>>>>>> {
>>>>>> "pattern": "^slv_lrclk[0-9]$"
>>>>>> }
>>>>>> ]
>>>>>> },
>>>>>> "type": "array",
>>>>>> "minItems": 6
>>>>>> },
>>>>>>
>>>>>> and it behaves as expected. However, the checking is followed by
>>>>>> complaints like this:
>>>>>>
>>>>>> Documentation/devicetree/bindings/clock/amlogic,a1-audio-clkc.yaml: properties:clock-names:additionalItems: {'oneOf': [{'pattern': '^slv_sclk[0-9]$'}, {'pattern': '^slv_lrclk[0-9]$'}]} is not of type 'boolean'
>>>>>>
>>>>>> And indeed, 'additionalItems' has boolean type in meta-schema. So, how to
>>>>>> do it right?
>>>>>
>>>>> The meta-schemas are written both to prevent nonsense that json-schema
>>>>> allows by default (e.g additionalitems (wrong case)) and constraints to
>>>>> follow the patterns we expect. I'm happy to loosen the latter case if
>>>>> there's really a need.
>>>>>
>>>>> Generally, most bindings shouldn't be using 'additionalItems' at all as
>>>>> all entries should be defined, but there's a few exceptions. Here, the
>>>>> only reasoning I see is 26 entries is a lot to write out, but that
>>>>> wouldn't really justify it.
>>>>
>>>> Writing a lot of entries don't scary me too much, but the reason is that
>>>> the existence of optional clock sources depends on schematics. Also, we
>>>
>>> Aren't you documenting SoC component, not a board? So how exactly it
>>> depends on schematics? SoC is done or not done...
>>>
>>>> unable to declare dt-nodes for 'clocks' array in any generic way,
>>>> because their declaration would depends on that what is actually
>>>> connected to the SoC (dt-node could be "fixed-clock" with specific rate
>>>> or something else).
>>>
>>> So these are clock inputs to the SoC?
>>>
>>
>> Yes, possibly.
>> Like an external crystal or a set clocks provided by an external codec
>> where the codec is the clock master of the link.
>>
>> This is same case as the AXG that was discussed here:
>> https://lore.kernel.org/linux-devicetree/20230808194811.113087-1-alexander.stein@mailbox.org/
>>
>> IMO, like the AXG, only the pclk is a required clock.
>> All the others - master and slave clocks - are optional.
>> The controller is designed to operate with grounded inputs
>
> Looking again at the implementation of the controller, there is a clear
> indication in patch 3 that the controller interface is the same as the
> AXG and that the above statement is true.
> > The AXG had 8 master clocks wired in. The A1 just has 5 - and 3 grounded
> master clocks. This is why you to had to provide a mux input table to
> skip the grounded inputs. You would not have to do so if the controller was
> properly declared with the 8 master clock input, as it actually is.
>
For simplicity, I could make something like this in device tree:
clocks = <&clk0,
&clk1,
&clk2,
&clk3,
&clk4,
0,
0,
0>
clock-names = <"mst_in0",
"mst_in1",
"mst_in2"
"mst_in2"
"mst_in3"
"mst_in4"
"mst_in5"
"mst_in6"
"mst_in7">
But I don't see in the doc that the last 3 clocks are grounded to
anywhere. It will be just community's assumption about internals of the
controller.
Anyway, I still don't understand what to do with external slv_* clocks.
I can do the same as in example above: list slv_(s|lr)clk[0-9] in
"clock-names" and fill the rest if "clocks" by "0" phandles.
> It also shows that it is a bad idea to name input after what is coming
> in (like you do with "dds_in" or "fclk_div2") instead of what they
> actually are like in the AXG (mst0, mst1, etc ...)
>
I agree, these are not the best names.
>>
>>>>
>>>> By the way, I don't know any example (neither for A1 SoC nor for other
>>>> Amlogic's SoCs) where these optional clocks are used, but they are
>>>> allowed by hw.
>>
>> Those scenario exists and have been tested. There is just no dts using
>> that upstream because they are all mostly copy of the AML ref design.
>>
>>>>
>>>> This is my understanding of this controller. I hope, Jerome Brunet will
>>>> clarify how it actually works.
>>>
>>
>> I think the simpliest way to deal with this to just list all the clocks
>> with 'minItems = 1'. It is going be hard to read with a lot of '<0>,' in
>> the DTS when do need those slave clocks but at least the binding doc
>> will be simple.
>>
>>> Best regards,
>>> Krzysztof
>>
>> If you are going ahead with this, please name the file
>> amlogic,axg-audio-clkc.yaml because this is really the first controller
>> of the type and is meant to be documented in the same file.
>>
>> You are free to handle the conversion of the AXG at the same time if
>> you'd like. It would be much appreciated if you do.
>
>
--
Best regards
Jan Dakinevich
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [relevance 0%]
* [PATCH v5 08/15] mm/execmem, arch: convert remaining overrides of module_alloc to execmem
@ 2024-04-22 9:44 5% ` Mike Rapoport
0 siblings, 0 replies; 200+ results
From: Mike Rapoport @ 2024-04-22 9:44 UTC (permalink / raw)
To: linux-kernel
Cc: Alexandre Ghiti, Andrew Morton, Björn Töpel,
Catalin Marinas, Christophe Leroy, David S. Miller, Dinh Nguyen,
Donald Dutile, Eric Chanudet, Heiko Carstens, Helge Deller,
Huacai Chen, Kent Overstreet, Luis Chamberlain, Mark Rutland,
Masami Hiramatsu, Michael Ellerman, Mike Rapoport, Nadav Amit,
Palmer Dabbelt, Peter Zijlstra, Rick Edgecombe, Russell King,
Sam Ravnborg, Song Liu, Steven Rostedt, Thomas Bogendoerfer,
Thomas Gleixner, Will Deacon, bpf, linux-arch, linux-arm-kernel,
linux-mips, linux-mm, linux-modules, linux-parisc, linux-riscv,
linux-s390, linux-trace-kernel, linuxppc-dev, loongarch, netdev,
sparclinux, x86
From: "Mike Rapoport (IBM)" <rppt@kernel.org>
Extend execmem parameters to accommodate more complex overrides of
module_alloc() by architectures.
This includes specification of a fallback range required by arm, arm64
and powerpc, EXECMEM_MODULE_DATA type required by powerpc, support for
allocation of KASAN shadow required by s390 and x86 and support for
early initialization of execmem required by x86.
The core implementation of execmem_alloc() takes care of suppressing
warnings when the initial allocation fails but there is a fallback range
defined.
Signed-off-by: Mike Rapoport (IBM) <rppt@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
---
arch/Kconfig | 6 +++
arch/arm/kernel/module.c | 41 ++++++++++-------
arch/arm64/kernel/module.c | 67 ++++++++++++++++++----------
arch/arm64/kernel/probes/kprobes.c | 7 ---
arch/arm64/net/bpf_jit_comp.c | 11 -----
arch/powerpc/kernel/module.c | 60 ++++++++++++++++---------
arch/s390/kernel/module.c | 54 ++++++++++-------------
arch/x86/Kconfig | 1 +
arch/x86/kernel/module.c | 70 ++++++++++--------------------
include/linux/execmem.h | 34 +++++++++++++++
include/linux/moduleloader.h | 12 -----
kernel/module/main.c | 26 +++--------
mm/execmem.c | 70 +++++++++++++++++++++++++-----
mm/mm_init.c | 2 +
14 files changed, 259 insertions(+), 202 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index 65afb1de48b3..7006f71f0110 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -960,6 +960,12 @@ config ARCH_WANTS_MODULES_DATA_IN_VMALLOC
For architectures like powerpc/32 which have constraints on module
allocation and need to allocate module data outside of module area.
+config ARCH_WANTS_EXECMEM_EARLY
+ bool
+ help
+ For architectures that might allocate executable memory early on
+ boot, for instance ftrace on x86.
+
config HAVE_IRQ_EXIT_ON_IRQ_STACK
bool
help
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index e74d84f58b77..a98fdf6ff26c 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -16,6 +16,7 @@
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/gfp.h>
+#include <linux/execmem.h>
#include <asm/sections.h>
#include <asm/smp_plat.h>
@@ -34,23 +35,31 @@
#endif
#ifdef CONFIG_MMU
-void *module_alloc(unsigned long size)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- /* Silence the initial allocation */
- if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS))
- gfp_mask |= __GFP_NOWARN;
-
- p = __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
- gfp_mask, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- if (!IS_ENABLED(CONFIG_ARM_MODULE_PLTS) || p)
- return p;
- return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
+ unsigned long fallback_start = 0, fallback_end = 0;
+
+ if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS)) {
+ fallback_start = VMALLOC_START;
+ fallback_end = VMALLOC_END;
+ }
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = MODULES_VADDR,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL_EXEC,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#endif
diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c
index e92da4da1b2a..a52240ea084b 100644
--- a/arch/arm64/kernel/module.c
+++ b/arch/arm64/kernel/module.c
@@ -20,6 +20,7 @@
#include <linux/random.h>
#include <linux/scs.h>
#include <linux/vmalloc.h>
+#include <linux/execmem.h>
#include <asm/alternative.h>
#include <asm/insn.h>
@@ -108,41 +109,59 @@ static int __init module_init_limits(void)
return 0;
}
-subsys_initcall(module_init_limits);
-void *module_alloc(unsigned long size)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- void *p = NULL;
+ unsigned long fallback_start = 0, fallback_end = 0;
+ unsigned long start = 0, end = 0;
+
+ module_init_limits();
/*
* Where possible, prefer to allocate within direct branch range of the
* kernel such that no PLTs are necessary.
*/
if (module_direct_base) {
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- module_direct_base,
- module_direct_base + SZ_128M,
- GFP_KERNEL | __GFP_NOWARN,
- PAGE_KERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- }
+ start = module_direct_base;
+ end = module_direct_base + SZ_128M;
- if (!p && module_plt_base) {
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- module_plt_base,
- module_plt_base + SZ_2G,
- GFP_KERNEL | __GFP_NOWARN,
- PAGE_KERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- }
-
- if (!p) {
- pr_warn_ratelimited("%s: unable to allocate memory\n",
- __func__);
+ if (module_plt_base) {
+ fallback_start = module_plt_base;
+ fallback_end = module_plt_base + SZ_2G;
+ }
+ } else if (module_plt_base) {
+ start = module_plt_base;
+ end = module_plt_base + SZ_2G;
}
- /* Memory is intended to be executable, reset the pointer tag. */
- return kasan_reset_tag(p);
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = start,
+ .end = end,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ [EXECMEM_KPROBES] = {
+ .start = VMALLOC_START,
+ .end = VMALLOC_END,
+ .pgprot = PAGE_KERNEL_ROX,
+ .alignment = 1,
+ },
+ [EXECMEM_BPF] = {
+ .start = VMALLOC_START,
+ .end = VMALLOC_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ },
+ },
+ };
+
+ return &execmem_info;
}
enum aarch64_reloc_op {
diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
index 327855a11df2..4268678d0e86 100644
--- a/arch/arm64/kernel/probes/kprobes.c
+++ b/arch/arm64/kernel/probes/kprobes.c
@@ -129,13 +129,6 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
return 0;
}
-void *alloc_insn_page(void)
-{
- return __vmalloc_node_range(PAGE_SIZE, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_ROX, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
/* arm kprobe: install breakpoint in text */
void __kprobes arch_arm_kprobe(struct kprobe *p)
{
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index 122021f9bdfc..456f5af239fc 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -1793,17 +1793,6 @@ u64 bpf_jit_alloc_exec_limit(void)
return VMALLOC_END - VMALLOC_START;
}
-void *bpf_jit_alloc_exec(unsigned long size)
-{
- /* Memory is intended to be executable, reset the pointer tag. */
- return kasan_reset_tag(vmalloc(size));
-}
-
-void bpf_jit_free_exec(void *addr)
-{
- return vfree(addr);
-}
-
/* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
bool bpf_jit_supports_subprog_tailcalls(void)
{
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index f6d6ae0a1692..ac80559015a3 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -10,6 +10,7 @@
#include <linux/vmalloc.h>
#include <linux/mm.h>
#include <linux/bug.h>
+#include <linux/execmem.h>
#include <asm/module.h>
#include <linux/uaccess.h>
#include <asm/firmware.h>
@@ -89,39 +90,56 @@ int module_finalize(const Elf_Ehdr *hdr,
return 0;
}
-static __always_inline void *
-__module_alloc(unsigned long size, unsigned long start, unsigned long end, bool nowarn)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
pgprot_t prot = strict_module_rwx_enabled() ? PAGE_KERNEL : PAGE_KERNEL_EXEC;
- gfp_t gfp = GFP_KERNEL | (nowarn ? __GFP_NOWARN : 0);
+ unsigned long fallback_start = 0, fallback_end = 0;
+ unsigned long start, end;
/*
- * Don't do huge page allocations for modules yet until more testing
- * is done. STRICT_MODULE_RWX may require extra work to support this
- * too.
+ * BOOK3S_32 and 8xx define MODULES_VADDR for text allocations and
+ * allow allocating data in the entire vmalloc space
*/
- return __vmalloc_node_range(size, 1, start, end, gfp, prot,
- VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
-void *module_alloc(unsigned long size)
-{
#ifdef MODULES_VADDR
unsigned long limit = (unsigned long)_etext - SZ_32M;
- void *ptr = NULL;
BUILD_BUG_ON(TASK_SIZE > MODULES_VADDR);
/* First try within 32M limit from _etext to avoid branch trampolines */
- if (MODULES_VADDR < PAGE_OFFSET && MODULES_END > limit)
- ptr = __module_alloc(size, limit, MODULES_END, true);
-
- if (!ptr)
- ptr = __module_alloc(size, MODULES_VADDR, MODULES_END, false);
+ if (MODULES_VADDR < PAGE_OFFSET && MODULES_END > limit) {
+ start = limit;
+ fallback_start = MODULES_VADDR;
+ fallback_end = MODULES_END;
+ } else {
+ start = MODULES_VADDR;
+ }
- return ptr;
+ end = MODULES_END;
#else
- return __module_alloc(size, VMALLOC_START, VMALLOC_END, false);
+ start = VMALLOC_START;
+ end = VMALLOC_END;
#endif
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = start,
+ .end = end,
+ .pgprot = prot,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ [EXECMEM_MODULE_DATA] = {
+ .start = VMALLOC_START,
+ .end = VMALLOC_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ },
+ },
+ };
+
+ return &execmem_info;
}
diff --git a/arch/s390/kernel/module.c b/arch/s390/kernel/module.c
index ac97a905e8cd..7fee64fdc1bb 100644
--- a/arch/s390/kernel/module.c
+++ b/arch/s390/kernel/module.c
@@ -37,41 +37,31 @@
#define PLT_ENTRY_SIZE 22
-static unsigned long get_module_load_offset(void)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- static DEFINE_MUTEX(module_kaslr_mutex);
- static unsigned long module_load_offset;
-
- if (!kaslr_enabled())
- return 0;
- /*
- * Calculate the module_load_offset the first time this code
- * is called. Once calculated it stays the same until reboot.
- */
- mutex_lock(&module_kaslr_mutex);
- if (!module_load_offset)
+ unsigned long module_load_offset = 0;
+ unsigned long start;
+
+ if (kaslr_enabled())
module_load_offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
- mutex_unlock(&module_kaslr_mutex);
- return module_load_offset;
-}
-void *module_alloc(unsigned long size)
-{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- if (PAGE_ALIGN(size) > MODULES_LEN)
- return NULL;
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- MODULES_VADDR + get_module_load_offset(),
- MODULES_END, gfp_mask, PAGE_KERNEL,
- VM_FLUSH_RESET_PERMS | VM_DEFER_KMEMLEAK,
- NUMA_NO_NODE, __builtin_return_address(0));
- if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) {
- vfree(p);
- return NULL;
- }
- return p;
+ start = MODULES_VADDR + module_load_offset;
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .flags = EXECMEM_KASAN_SHADOW,
+ .start = start,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = MODULE_ALIGN,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#ifdef CONFIG_FUNCTION_TRACER
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 4474bf32d0a4..3f5ba72c9480 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -135,6 +135,7 @@ config X86
select ARCH_WANT_OPTIMIZE_DAX_VMEMMAP if X86_64
select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP if X86_64
select ARCH_WANTS_THP_SWAP if X86_64
+ select ARCH_WANTS_EXECMEM_EARLY if EXECMEM
select ARCH_HAS_PARANOID_L1D_FLUSH
select BUILDTIME_TABLE_SORT
select CLKEVT_I8253
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index e18914c0e38a..45b1a7c03379 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -19,6 +19,7 @@
#include <linux/jump_label.h>
#include <linux/random.h>
#include <linux/memory.h>
+#include <linux/execmem.h>
#include <asm/text-patching.h>
#include <asm/page.h>
@@ -36,55 +37,30 @@ do { \
} while (0)
#endif
-#ifdef CONFIG_RANDOMIZE_BASE
-static unsigned long module_load_offset;
+static struct execmem_info execmem_info __ro_after_init;
-/* Mutex protects the module_load_offset. */
-static DEFINE_MUTEX(module_kaslr_mutex);
-
-static unsigned long int get_module_load_offset(void)
-{
- if (kaslr_enabled()) {
- mutex_lock(&module_kaslr_mutex);
- /*
- * Calculate the module_load_offset the first time this
- * code is called. Once calculated it stays the same until
- * reboot.
- */
- if (module_load_offset == 0)
- module_load_offset =
- get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
- mutex_unlock(&module_kaslr_mutex);
- }
- return module_load_offset;
-}
-#else
-static unsigned long int get_module_load_offset(void)
+struct execmem_info __init *execmem_arch_setup(void)
{
- return 0;
-}
-#endif
-
-void *module_alloc(unsigned long size)
-{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- if (PAGE_ALIGN(size) > MODULES_LEN)
- return NULL;
-
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- MODULES_VADDR + get_module_load_offset(),
- MODULES_END, gfp_mask, PAGE_KERNEL,
- VM_FLUSH_RESET_PERMS | VM_DEFER_KMEMLEAK,
- NUMA_NO_NODE, __builtin_return_address(0));
-
- if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) {
- vfree(p);
- return NULL;
- }
-
- return p;
+ unsigned long start, offset = 0;
+
+ if (kaslr_enabled())
+ offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
+
+ start = MODULES_VADDR + offset;
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .flags = EXECMEM_KASAN_SHADOW,
+ .start = start,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = MODULE_ALIGN,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#ifdef CONFIG_X86_32
diff --git a/include/linux/execmem.h b/include/linux/execmem.h
index ad5d99bb2871..36686f013cd2 100644
--- a/include/linux/execmem.h
+++ b/include/linux/execmem.h
@@ -5,6 +5,14 @@
#include <linux/types.h>
#include <linux/moduleloader.h>
+#if (defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)) && \
+ !defined(CONFIG_KASAN_VMALLOC)
+#include <linux/kasan.h>
+#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
+#else
+#define MODULE_ALIGN PAGE_SIZE
+#endif
+
/**
* enum execmem_type - types of executable memory ranges
*
@@ -22,6 +30,7 @@
* @EXECMEM_KPROBES: parameters for kprobes
* @EXECMEM_FTRACE: parameters for ftrace
* @EXECMEM_BPF: parameters for BPF
+ * @EXECMEM_MODULE_DATA: parameters for module data sections
* @EXECMEM_TYPE_MAX:
*/
enum execmem_type {
@@ -30,22 +39,38 @@ enum execmem_type {
EXECMEM_KPROBES,
EXECMEM_FTRACE,
EXECMEM_BPF,
+ EXECMEM_MODULE_DATA,
EXECMEM_TYPE_MAX,
};
+/**
+ * enum execmem_range_flags - options for executable memory allocations
+ * @EXECMEM_KASAN_SHADOW: allocate kasan shadow
+ */
+enum execmem_range_flags {
+ EXECMEM_KASAN_SHADOW = (1 << 0),
+};
+
/**
* struct execmem_range - definition of an address space suitable for code and
* related data allocations
* @start: address space start
* @end: address space end (inclusive)
+ * @fallback_start: start of the secondary address space range for fallback
+ * allocations on architectures that require it
+ * @fallback_end: start of the secondary address space (inclusive)
* @pgprot: permissions for memory in this address space
* @alignment: alignment required for text allocations
+ * @flags: options for memory allocations for this range
*/
struct execmem_range {
unsigned long start;
unsigned long end;
+ unsigned long fallback_start;
+ unsigned long fallback_end;
pgprot_t pgprot;
unsigned int alignment;
+ enum execmem_range_flags flags;
};
/**
@@ -82,6 +107,9 @@ struct execmem_info *execmem_arch_setup(void);
* Allocates memory that will contain executable code, either generated or
* loaded from kernel modules.
*
+ * Allocates memory that will contain data coupled with executable code,
+ * like data sections in kernel modules.
+ *
* The memory will have protections defined by architecture for executable
* region of the @type.
*
@@ -95,4 +123,10 @@ void *execmem_alloc(enum execmem_type type, size_t size);
*/
void execmem_free(void *ptr);
+#ifdef CONFIG_ARCH_WANTS_EXECMEM_EARLY
+void execmem_early_init(void);
+#else
+static inline void execmem_early_init(void) {}
+#endif
+
#endif /* _LINUX_EXECMEM_ALLOC_H */
diff --git a/include/linux/moduleloader.h b/include/linux/moduleloader.h
index a3b8caee9405..e395461d59e5 100644
--- a/include/linux/moduleloader.h
+++ b/include/linux/moduleloader.h
@@ -25,10 +25,6 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
/* Additional bytes needed by arch in front of individual sections */
unsigned int arch_mod_section_prepend(struct module *mod, unsigned int section);
-/* Allocator used for allocating struct module, core sections and init
- sections. Returns NULL on failure. */
-void *module_alloc(unsigned long size);
-
/* Determines if the section name is an init section (that is only used during
* module loading).
*/
@@ -126,12 +122,4 @@ void module_arch_cleanup(struct module *mod);
/* Any cleanup before freeing mod->module_init */
void module_arch_freeing_init(struct module *mod);
-#if (defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)) && \
- !defined(CONFIG_KASAN_VMALLOC)
-#include <linux/kasan.h>
-#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
-#else
-#define MODULE_ALIGN PAGE_SIZE
-#endif
-
#endif
diff --git a/kernel/module/main.c b/kernel/module/main.c
index d56b7df0cbb6..91e185607d4b 100644
--- a/kernel/module/main.c
+++ b/kernel/module/main.c
@@ -1188,24 +1188,20 @@ void __weak module_arch_freeing_init(struct module *mod)
{
}
-static bool mod_mem_use_vmalloc(enum mod_mem_type type)
-{
- return IS_ENABLED(CONFIG_ARCH_WANTS_MODULES_DATA_IN_VMALLOC) &&
- mod_mem_type_is_core_data(type);
-}
-
static int module_memory_alloc(struct module *mod, enum mod_mem_type type)
{
unsigned int size = PAGE_ALIGN(mod->mem[type].size);
+ enum execmem_type execmem_type;
void *ptr;
mod->mem[type].size = size;
- if (mod_mem_use_vmalloc(type))
- ptr = vmalloc(size);
+ if (mod_mem_type_is_data(type))
+ execmem_type = EXECMEM_MODULE_DATA;
else
- ptr = execmem_alloc(EXECMEM_MODULE_TEXT, size);
+ execmem_type = EXECMEM_MODULE_TEXT;
+ ptr = execmem_alloc(execmem_type, size);
if (!ptr)
return -ENOMEM;
@@ -1232,10 +1228,7 @@ static void module_memory_free(struct module *mod, enum mod_mem_type type)
{
void *ptr = mod->mem[type].base;
- if (mod_mem_use_vmalloc(type))
- vfree(ptr);
- else
- execmem_free(ptr);
+ execmem_free(ptr);
}
static void free_mod_mem(struct module *mod)
@@ -1630,13 +1623,6 @@ static void free_modinfo(struct module *mod)
}
}
-void * __weak module_alloc(unsigned long size)
-{
- return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_EXEC, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
bool __weak module_init_section(const char *name)
{
return strstarts(name, ".init");
diff --git a/mm/execmem.c b/mm/execmem.c
index d062bc21c6b2..33bf473e508e 100644
--- a/mm/execmem.c
+++ b/mm/execmem.c
@@ -12,27 +12,49 @@
#include <linux/moduleloader.h>
static struct execmem_info *execmem_info __ro_after_init;
+static struct execmem_info default_execmem_info __ro_after_init;
static void *__execmem_alloc(struct execmem_range *range, size_t size)
{
+ bool kasan = range->flags & EXECMEM_KASAN_SHADOW;
+ unsigned long vm_flags = VM_FLUSH_RESET_PERMS;
+ gfp_t gfp_flags = GFP_KERNEL | __GFP_NOWARN;
unsigned long start = range->start;
unsigned long end = range->end;
unsigned int align = range->alignment;
pgprot_t pgprot = range->pgprot;
+ void *p;
+
+ if (kasan)
+ vm_flags |= VM_DEFER_KMEMLEAK;
+
+ p = __vmalloc_node_range(size, align, start, end, gfp_flags,
+ pgprot, vm_flags, NUMA_NO_NODE,
+ __builtin_return_address(0));
+ if (!p && range->fallback_start) {
+ start = range->fallback_start;
+ end = range->fallback_end;
+ p = __vmalloc_node_range(size, align, start, end, gfp_flags,
+ pgprot, vm_flags, NUMA_NO_NODE,
+ __builtin_return_address(0));
+ }
+
+ if (!p) {
+ pr_warn_ratelimited("execmem: unable to allocate memory\n");
+ return NULL;
+ }
+
+ if (kasan && (kasan_alloc_module_shadow(p, size, GFP_KERNEL) < 0)) {
+ vfree(p);
+ return NULL;
+ }
- return __vmalloc_node_range(size, align, start, end,
- GFP_KERNEL, pgprot, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
+ return kasan_reset_tag(p);
}
void *execmem_alloc(enum execmem_type type, size_t size)
{
- struct execmem_range *range;
-
- if (!execmem_info)
- return module_alloc(size);
-
- range = &execmem_info->ranges[type];
+ struct execmem_range *range = &execmem_info->ranges[type];
return __execmem_alloc(range, size);
}
@@ -67,10 +89,16 @@ static void execmem_init_missing(struct execmem_info *info)
struct execmem_range *r = &info->ranges[i];
if (!r->start) {
- r->pgprot = default_range->pgprot;
+ if (i == EXECMEM_MODULE_DATA)
+ r->pgprot = PAGE_KERNEL;
+ else
+ r->pgprot = default_range->pgprot;
r->alignment = default_range->alignment;
r->start = default_range->start;
r->end = default_range->end;
+ r->flags = default_range->flags;
+ r->fallback_start = default_range->fallback_start;
+ r->fallback_end = default_range->fallback_end;
}
}
}
@@ -80,12 +108,18 @@ struct execmem_info * __weak execmem_arch_setup(void)
return NULL;
}
-static int __init execmem_init(void)
+static int __init __execmem_init(void)
{
struct execmem_info *info = execmem_arch_setup();
- if (!info)
+ if (!info) {
+ info = execmem_info = &default_execmem_info;
+ info->ranges[EXECMEM_DEFAULT].start = VMALLOC_START;
+ info->ranges[EXECMEM_DEFAULT].end = VMALLOC_END;
+ info->ranges[EXECMEM_DEFAULT].pgprot = PAGE_KERNEL_EXEC;
+ info->ranges[EXECMEM_DEFAULT].alignment = 1;
return 0;
+ }
if (!execmem_validate(info))
return -EINVAL;
@@ -96,4 +130,16 @@ static int __init execmem_init(void)
return 0;
}
+
+#ifndef CONFIG_ARCH_WANTS_EXECMEM_EARLY
+static int __init execmem_init(void)
+{
+ return __execmem_init();
+}
core_initcall(execmem_init);
+#else
+void __init execmem_early_init(void)
+{
+ (void)__execmem_init();
+}
+#endif
diff --git a/mm/mm_init.c b/mm/mm_init.c
index 549e76af8f82..dae777234a31 100644
--- a/mm/mm_init.c
+++ b/mm/mm_init.c
@@ -27,6 +27,7 @@
#include <linux/swap.h>
#include <linux/cma.h>
#include <linux/crash_dump.h>
+#include <linux/execmem.h>
#include "internal.h"
#include "slab.h"
#include "shuffle.h"
@@ -2793,4 +2794,5 @@ void __init mm_core_init(void)
pti_init();
kmsan_init_runtime();
mm_cache_init();
+ execmem_early_init();
}
--
2.43.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [relevance 5%]
* [PATCH v5 08/15] mm/execmem, arch: convert remaining overrides of module_alloc to execmem
@ 2024-04-22 8:47 5% ` Mike Rapoport
0 siblings, 0 replies; 200+ results
From: Mike Rapoport @ 2024-04-22 8:47 UTC (permalink / raw)
To: linux-kernel
Cc: Alexandre Ghiti, Andrew Morton, Björn Töpel,
Catalin Marinas, Christophe Leroy, David S. Miller, Dinh Nguyen,
Donald Dutile, Eric Chanudet, Heiko Carstens, Helge Deller,
Huacai Chen, Kent Overstreet, Luis Chamberlain, Mark Rutland,
Masami Hiramatsu, Michael Ellerman, Mike Rapoport, Nadav Amit,
Palmer Dabbelt, Peter Zijlstra, Rick Edgecombe, Russell King,
Sam Ravnborg, Song Liu, Steven Rostedt, Thomas Bogendoerfer,
Thomas Gleixner, Will Deacon, bpf, linux-arch, linux-arm-kernel,
linux-mips, linux-mm, linux-modules, linux-parisc, linux-riscv,
linux-s390, linux-trace-kernel, linuxppc-dev, loongarch, netdev,
sparclinux, x86
From: "Mike Rapoport (IBM)" <rppt@kernel.org>
Extend execmem parameters to accommodate more complex overrides of
module_alloc() by architectures.
This includes specification of a fallback range required by arm, arm64
and powerpc, EXECMEM_MODULE_DATA type required by powerpc, support for
allocation of KASAN shadow required by s390 and x86 and support for
early initialization of execmem required by x86.
The core implementation of execmem_alloc() takes care of suppressing
warnings when the initial allocation fails but there is a fallback range
defined.
Signed-off-by: Mike Rapoport (IBM) <rppt@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
---
arch/Kconfig | 6 +++
arch/arm/kernel/module.c | 41 ++++++++++-------
arch/arm64/kernel/module.c | 67 ++++++++++++++++++----------
arch/arm64/kernel/probes/kprobes.c | 7 ---
arch/arm64/net/bpf_jit_comp.c | 11 -----
arch/powerpc/kernel/module.c | 60 ++++++++++++++++---------
arch/s390/kernel/module.c | 54 ++++++++++-------------
arch/x86/Kconfig | 1 +
arch/x86/kernel/module.c | 70 ++++++++++--------------------
include/linux/execmem.h | 34 +++++++++++++++
include/linux/moduleloader.h | 12 -----
kernel/module/main.c | 26 +++--------
mm/execmem.c | 70 +++++++++++++++++++++++++-----
mm/mm_init.c | 2 +
14 files changed, 259 insertions(+), 202 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index 65afb1de48b3..7006f71f0110 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -960,6 +960,12 @@ config ARCH_WANTS_MODULES_DATA_IN_VMALLOC
For architectures like powerpc/32 which have constraints on module
allocation and need to allocate module data outside of module area.
+config ARCH_WANTS_EXECMEM_EARLY
+ bool
+ help
+ For architectures that might allocate executable memory early on
+ boot, for instance ftrace on x86.
+
config HAVE_IRQ_EXIT_ON_IRQ_STACK
bool
help
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index e74d84f58b77..a98fdf6ff26c 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -16,6 +16,7 @@
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/gfp.h>
+#include <linux/execmem.h>
#include <asm/sections.h>
#include <asm/smp_plat.h>
@@ -34,23 +35,31 @@
#endif
#ifdef CONFIG_MMU
-void *module_alloc(unsigned long size)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- /* Silence the initial allocation */
- if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS))
- gfp_mask |= __GFP_NOWARN;
-
- p = __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
- gfp_mask, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- if (!IS_ENABLED(CONFIG_ARM_MODULE_PLTS) || p)
- return p;
- return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
+ unsigned long fallback_start = 0, fallback_end = 0;
+
+ if (IS_ENABLED(CONFIG_ARM_MODULE_PLTS)) {
+ fallback_start = VMALLOC_START;
+ fallback_end = VMALLOC_END;
+ }
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = MODULES_VADDR,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL_EXEC,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#endif
diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c
index e92da4da1b2a..a52240ea084b 100644
--- a/arch/arm64/kernel/module.c
+++ b/arch/arm64/kernel/module.c
@@ -20,6 +20,7 @@
#include <linux/random.h>
#include <linux/scs.h>
#include <linux/vmalloc.h>
+#include <linux/execmem.h>
#include <asm/alternative.h>
#include <asm/insn.h>
@@ -108,41 +109,59 @@ static int __init module_init_limits(void)
return 0;
}
-subsys_initcall(module_init_limits);
-void *module_alloc(unsigned long size)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- void *p = NULL;
+ unsigned long fallback_start = 0, fallback_end = 0;
+ unsigned long start = 0, end = 0;
+
+ module_init_limits();
/*
* Where possible, prefer to allocate within direct branch range of the
* kernel such that no PLTs are necessary.
*/
if (module_direct_base) {
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- module_direct_base,
- module_direct_base + SZ_128M,
- GFP_KERNEL | __GFP_NOWARN,
- PAGE_KERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- }
+ start = module_direct_base;
+ end = module_direct_base + SZ_128M;
- if (!p && module_plt_base) {
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- module_plt_base,
- module_plt_base + SZ_2G,
- GFP_KERNEL | __GFP_NOWARN,
- PAGE_KERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
- }
-
- if (!p) {
- pr_warn_ratelimited("%s: unable to allocate memory\n",
- __func__);
+ if (module_plt_base) {
+ fallback_start = module_plt_base;
+ fallback_end = module_plt_base + SZ_2G;
+ }
+ } else if (module_plt_base) {
+ start = module_plt_base;
+ end = module_plt_base + SZ_2G;
}
- /* Memory is intended to be executable, reset the pointer tag. */
- return kasan_reset_tag(p);
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = start,
+ .end = end,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ [EXECMEM_KPROBES] = {
+ .start = VMALLOC_START,
+ .end = VMALLOC_END,
+ .pgprot = PAGE_KERNEL_ROX,
+ .alignment = 1,
+ },
+ [EXECMEM_BPF] = {
+ .start = VMALLOC_START,
+ .end = VMALLOC_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ },
+ },
+ };
+
+ return &execmem_info;
}
enum aarch64_reloc_op {
diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
index 327855a11df2..4268678d0e86 100644
--- a/arch/arm64/kernel/probes/kprobes.c
+++ b/arch/arm64/kernel/probes/kprobes.c
@@ -129,13 +129,6 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
return 0;
}
-void *alloc_insn_page(void)
-{
- return __vmalloc_node_range(PAGE_SIZE, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_ROX, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
/* arm kprobe: install breakpoint in text */
void __kprobes arch_arm_kprobe(struct kprobe *p)
{
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index 122021f9bdfc..456f5af239fc 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -1793,17 +1793,6 @@ u64 bpf_jit_alloc_exec_limit(void)
return VMALLOC_END - VMALLOC_START;
}
-void *bpf_jit_alloc_exec(unsigned long size)
-{
- /* Memory is intended to be executable, reset the pointer tag. */
- return kasan_reset_tag(vmalloc(size));
-}
-
-void bpf_jit_free_exec(void *addr)
-{
- return vfree(addr);
-}
-
/* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
bool bpf_jit_supports_subprog_tailcalls(void)
{
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index f6d6ae0a1692..ac80559015a3 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -10,6 +10,7 @@
#include <linux/vmalloc.h>
#include <linux/mm.h>
#include <linux/bug.h>
+#include <linux/execmem.h>
#include <asm/module.h>
#include <linux/uaccess.h>
#include <asm/firmware.h>
@@ -89,39 +90,56 @@ int module_finalize(const Elf_Ehdr *hdr,
return 0;
}
-static __always_inline void *
-__module_alloc(unsigned long size, unsigned long start, unsigned long end, bool nowarn)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
pgprot_t prot = strict_module_rwx_enabled() ? PAGE_KERNEL : PAGE_KERNEL_EXEC;
- gfp_t gfp = GFP_KERNEL | (nowarn ? __GFP_NOWARN : 0);
+ unsigned long fallback_start = 0, fallback_end = 0;
+ unsigned long start, end;
/*
- * Don't do huge page allocations for modules yet until more testing
- * is done. STRICT_MODULE_RWX may require extra work to support this
- * too.
+ * BOOK3S_32 and 8xx define MODULES_VADDR for text allocations and
+ * allow allocating data in the entire vmalloc space
*/
- return __vmalloc_node_range(size, 1, start, end, gfp, prot,
- VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
-void *module_alloc(unsigned long size)
-{
#ifdef MODULES_VADDR
unsigned long limit = (unsigned long)_etext - SZ_32M;
- void *ptr = NULL;
BUILD_BUG_ON(TASK_SIZE > MODULES_VADDR);
/* First try within 32M limit from _etext to avoid branch trampolines */
- if (MODULES_VADDR < PAGE_OFFSET && MODULES_END > limit)
- ptr = __module_alloc(size, limit, MODULES_END, true);
-
- if (!ptr)
- ptr = __module_alloc(size, MODULES_VADDR, MODULES_END, false);
+ if (MODULES_VADDR < PAGE_OFFSET && MODULES_END > limit) {
+ start = limit;
+ fallback_start = MODULES_VADDR;
+ fallback_end = MODULES_END;
+ } else {
+ start = MODULES_VADDR;
+ }
- return ptr;
+ end = MODULES_END;
#else
- return __module_alloc(size, VMALLOC_START, VMALLOC_END, false);
+ start = VMALLOC_START;
+ end = VMALLOC_END;
#endif
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .start = start,
+ .end = end,
+ .pgprot = prot,
+ .alignment = 1,
+ .fallback_start = fallback_start,
+ .fallback_end = fallback_end,
+ },
+ [EXECMEM_MODULE_DATA] = {
+ .start = VMALLOC_START,
+ .end = VMALLOC_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = 1,
+ },
+ },
+ };
+
+ return &execmem_info;
}
diff --git a/arch/s390/kernel/module.c b/arch/s390/kernel/module.c
index ac97a905e8cd..7fee64fdc1bb 100644
--- a/arch/s390/kernel/module.c
+++ b/arch/s390/kernel/module.c
@@ -37,41 +37,31 @@
#define PLT_ENTRY_SIZE 22
-static unsigned long get_module_load_offset(void)
+static struct execmem_info execmem_info __ro_after_init;
+
+struct execmem_info __init *execmem_arch_setup(void)
{
- static DEFINE_MUTEX(module_kaslr_mutex);
- static unsigned long module_load_offset;
-
- if (!kaslr_enabled())
- return 0;
- /*
- * Calculate the module_load_offset the first time this code
- * is called. Once calculated it stays the same until reboot.
- */
- mutex_lock(&module_kaslr_mutex);
- if (!module_load_offset)
+ unsigned long module_load_offset = 0;
+ unsigned long start;
+
+ if (kaslr_enabled())
module_load_offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
- mutex_unlock(&module_kaslr_mutex);
- return module_load_offset;
-}
-void *module_alloc(unsigned long size)
-{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- if (PAGE_ALIGN(size) > MODULES_LEN)
- return NULL;
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- MODULES_VADDR + get_module_load_offset(),
- MODULES_END, gfp_mask, PAGE_KERNEL,
- VM_FLUSH_RESET_PERMS | VM_DEFER_KMEMLEAK,
- NUMA_NO_NODE, __builtin_return_address(0));
- if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) {
- vfree(p);
- return NULL;
- }
- return p;
+ start = MODULES_VADDR + module_load_offset;
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .flags = EXECMEM_KASAN_SHADOW,
+ .start = start,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = MODULE_ALIGN,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#ifdef CONFIG_FUNCTION_TRACER
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 4474bf32d0a4..3f5ba72c9480 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -135,6 +135,7 @@ config X86
select ARCH_WANT_OPTIMIZE_DAX_VMEMMAP if X86_64
select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP if X86_64
select ARCH_WANTS_THP_SWAP if X86_64
+ select ARCH_WANTS_EXECMEM_EARLY if EXECMEM
select ARCH_HAS_PARANOID_L1D_FLUSH
select BUILDTIME_TABLE_SORT
select CLKEVT_I8253
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index e18914c0e38a..45b1a7c03379 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -19,6 +19,7 @@
#include <linux/jump_label.h>
#include <linux/random.h>
#include <linux/memory.h>
+#include <linux/execmem.h>
#include <asm/text-patching.h>
#include <asm/page.h>
@@ -36,55 +37,30 @@ do { \
} while (0)
#endif
-#ifdef CONFIG_RANDOMIZE_BASE
-static unsigned long module_load_offset;
+static struct execmem_info execmem_info __ro_after_init;
-/* Mutex protects the module_load_offset. */
-static DEFINE_MUTEX(module_kaslr_mutex);
-
-static unsigned long int get_module_load_offset(void)
-{
- if (kaslr_enabled()) {
- mutex_lock(&module_kaslr_mutex);
- /*
- * Calculate the module_load_offset the first time this
- * code is called. Once calculated it stays the same until
- * reboot.
- */
- if (module_load_offset == 0)
- module_load_offset =
- get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
- mutex_unlock(&module_kaslr_mutex);
- }
- return module_load_offset;
-}
-#else
-static unsigned long int get_module_load_offset(void)
+struct execmem_info __init *execmem_arch_setup(void)
{
- return 0;
-}
-#endif
-
-void *module_alloc(unsigned long size)
-{
- gfp_t gfp_mask = GFP_KERNEL;
- void *p;
-
- if (PAGE_ALIGN(size) > MODULES_LEN)
- return NULL;
-
- p = __vmalloc_node_range(size, MODULE_ALIGN,
- MODULES_VADDR + get_module_load_offset(),
- MODULES_END, gfp_mask, PAGE_KERNEL,
- VM_FLUSH_RESET_PERMS | VM_DEFER_KMEMLEAK,
- NUMA_NO_NODE, __builtin_return_address(0));
-
- if (p && (kasan_alloc_module_shadow(p, size, gfp_mask) < 0)) {
- vfree(p);
- return NULL;
- }
-
- return p;
+ unsigned long start, offset = 0;
+
+ if (kaslr_enabled())
+ offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE;
+
+ start = MODULES_VADDR + offset;
+
+ execmem_info = (struct execmem_info){
+ .ranges = {
+ [EXECMEM_DEFAULT] = {
+ .flags = EXECMEM_KASAN_SHADOW,
+ .start = start,
+ .end = MODULES_END,
+ .pgprot = PAGE_KERNEL,
+ .alignment = MODULE_ALIGN,
+ },
+ },
+ };
+
+ return &execmem_info;
}
#ifdef CONFIG_X86_32
diff --git a/include/linux/execmem.h b/include/linux/execmem.h
index ad5d99bb2871..36686f013cd2 100644
--- a/include/linux/execmem.h
+++ b/include/linux/execmem.h
@@ -5,6 +5,14 @@
#include <linux/types.h>
#include <linux/moduleloader.h>
+#if (defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)) && \
+ !defined(CONFIG_KASAN_VMALLOC)
+#include <linux/kasan.h>
+#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
+#else
+#define MODULE_ALIGN PAGE_SIZE
+#endif
+
/**
* enum execmem_type - types of executable memory ranges
*
@@ -22,6 +30,7 @@
* @EXECMEM_KPROBES: parameters for kprobes
* @EXECMEM_FTRACE: parameters for ftrace
* @EXECMEM_BPF: parameters for BPF
+ * @EXECMEM_MODULE_DATA: parameters for module data sections
* @EXECMEM_TYPE_MAX:
*/
enum execmem_type {
@@ -30,22 +39,38 @@ enum execmem_type {
EXECMEM_KPROBES,
EXECMEM_FTRACE,
EXECMEM_BPF,
+ EXECMEM_MODULE_DATA,
EXECMEM_TYPE_MAX,
};
+/**
+ * enum execmem_range_flags - options for executable memory allocations
+ * @EXECMEM_KASAN_SHADOW: allocate kasan shadow
+ */
+enum execmem_range_flags {
+ EXECMEM_KASAN_SHADOW = (1 << 0),
+};
+
/**
* struct execmem_range - definition of an address space suitable for code and
* related data allocations
* @start: address space start
* @end: address space end (inclusive)
+ * @fallback_start: start of the secondary address space range for fallback
+ * allocations on architectures that require it
+ * @fallback_end: start of the secondary address space (inclusive)
* @pgprot: permissions for memory in this address space
* @alignment: alignment required for text allocations
+ * @flags: options for memory allocations for this range
*/
struct execmem_range {
unsigned long start;
unsigned long end;
+ unsigned long fallback_start;
+ unsigned long fallback_end;
pgprot_t pgprot;
unsigned int alignment;
+ enum execmem_range_flags flags;
};
/**
@@ -82,6 +107,9 @@ struct execmem_info *execmem_arch_setup(void);
* Allocates memory that will contain executable code, either generated or
* loaded from kernel modules.
*
+ * Allocates memory that will contain data coupled with executable code,
+ * like data sections in kernel modules.
+ *
* The memory will have protections defined by architecture for executable
* region of the @type.
*
@@ -95,4 +123,10 @@ void *execmem_alloc(enum execmem_type type, size_t size);
*/
void execmem_free(void *ptr);
+#ifdef CONFIG_ARCH_WANTS_EXECMEM_EARLY
+void execmem_early_init(void);
+#else
+static inline void execmem_early_init(void) {}
+#endif
+
#endif /* _LINUX_EXECMEM_ALLOC_H */
diff --git a/include/linux/moduleloader.h b/include/linux/moduleloader.h
index a3b8caee9405..e395461d59e5 100644
--- a/include/linux/moduleloader.h
+++ b/include/linux/moduleloader.h
@@ -25,10 +25,6 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
/* Additional bytes needed by arch in front of individual sections */
unsigned int arch_mod_section_prepend(struct module *mod, unsigned int section);
-/* Allocator used for allocating struct module, core sections and init
- sections. Returns NULL on failure. */
-void *module_alloc(unsigned long size);
-
/* Determines if the section name is an init section (that is only used during
* module loading).
*/
@@ -126,12 +122,4 @@ void module_arch_cleanup(struct module *mod);
/* Any cleanup before freeing mod->module_init */
void module_arch_freeing_init(struct module *mod);
-#if (defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)) && \
- !defined(CONFIG_KASAN_VMALLOC)
-#include <linux/kasan.h>
-#define MODULE_ALIGN (PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
-#else
-#define MODULE_ALIGN PAGE_SIZE
-#endif
-
#endif
diff --git a/kernel/module/main.c b/kernel/module/main.c
index d56b7df0cbb6..91e185607d4b 100644
--- a/kernel/module/main.c
+++ b/kernel/module/main.c
@@ -1188,24 +1188,20 @@ void __weak module_arch_freeing_init(struct module *mod)
{
}
-static bool mod_mem_use_vmalloc(enum mod_mem_type type)
-{
- return IS_ENABLED(CONFIG_ARCH_WANTS_MODULES_DATA_IN_VMALLOC) &&
- mod_mem_type_is_core_data(type);
-}
-
static int module_memory_alloc(struct module *mod, enum mod_mem_type type)
{
unsigned int size = PAGE_ALIGN(mod->mem[type].size);
+ enum execmem_type execmem_type;
void *ptr;
mod->mem[type].size = size;
- if (mod_mem_use_vmalloc(type))
- ptr = vmalloc(size);
+ if (mod_mem_type_is_data(type))
+ execmem_type = EXECMEM_MODULE_DATA;
else
- ptr = execmem_alloc(EXECMEM_MODULE_TEXT, size);
+ execmem_type = EXECMEM_MODULE_TEXT;
+ ptr = execmem_alloc(execmem_type, size);
if (!ptr)
return -ENOMEM;
@@ -1232,10 +1228,7 @@ static void module_memory_free(struct module *mod, enum mod_mem_type type)
{
void *ptr = mod->mem[type].base;
- if (mod_mem_use_vmalloc(type))
- vfree(ptr);
- else
- execmem_free(ptr);
+ execmem_free(ptr);
}
static void free_mod_mem(struct module *mod)
@@ -1630,13 +1623,6 @@ static void free_modinfo(struct module *mod)
}
}
-void * __weak module_alloc(unsigned long size)
-{
- return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
- GFP_KERNEL, PAGE_KERNEL_EXEC, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
-}
-
bool __weak module_init_section(const char *name)
{
return strstarts(name, ".init");
diff --git a/mm/execmem.c b/mm/execmem.c
index d062bc21c6b2..33bf473e508e 100644
--- a/mm/execmem.c
+++ b/mm/execmem.c
@@ -12,27 +12,49 @@
#include <linux/moduleloader.h>
static struct execmem_info *execmem_info __ro_after_init;
+static struct execmem_info default_execmem_info __ro_after_init;
static void *__execmem_alloc(struct execmem_range *range, size_t size)
{
+ bool kasan = range->flags & EXECMEM_KASAN_SHADOW;
+ unsigned long vm_flags = VM_FLUSH_RESET_PERMS;
+ gfp_t gfp_flags = GFP_KERNEL | __GFP_NOWARN;
unsigned long start = range->start;
unsigned long end = range->end;
unsigned int align = range->alignment;
pgprot_t pgprot = range->pgprot;
+ void *p;
+
+ if (kasan)
+ vm_flags |= VM_DEFER_KMEMLEAK;
+
+ p = __vmalloc_node_range(size, align, start, end, gfp_flags,
+ pgprot, vm_flags, NUMA_NO_NODE,
+ __builtin_return_address(0));
+ if (!p && range->fallback_start) {
+ start = range->fallback_start;
+ end = range->fallback_end;
+ p = __vmalloc_node_range(size, align, start, end, gfp_flags,
+ pgprot, vm_flags, NUMA_NO_NODE,
+ __builtin_return_address(0));
+ }
+
+ if (!p) {
+ pr_warn_ratelimited("execmem: unable to allocate memory\n");
+ return NULL;
+ }
+
+ if (kasan && (kasan_alloc_module_shadow(p, size, GFP_KERNEL) < 0)) {
+ vfree(p);
+ return NULL;
+ }
- return __vmalloc_node_range(size, align, start, end,
- GFP_KERNEL, pgprot, VM_FLUSH_RESET_PERMS,
- NUMA_NO_NODE, __builtin_return_address(0));
+ return kasan_reset_tag(p);
}
void *execmem_alloc(enum execmem_type type, size_t size)
{
- struct execmem_range *range;
-
- if (!execmem_info)
- return module_alloc(size);
-
- range = &execmem_info->ranges[type];
+ struct execmem_range *range = &execmem_info->ranges[type];
return __execmem_alloc(range, size);
}
@@ -67,10 +89,16 @@ static void execmem_init_missing(struct execmem_info *info)
struct execmem_range *r = &info->ranges[i];
if (!r->start) {
- r->pgprot = default_range->pgprot;
+ if (i == EXECMEM_MODULE_DATA)
+ r->pgprot = PAGE_KERNEL;
+ else
+ r->pgprot = default_range->pgprot;
r->alignment = default_range->alignment;
r->start = default_range->start;
r->end = default_range->end;
+ r->flags = default_range->flags;
+ r->fallback_start = default_range->fallback_start;
+ r->fallback_end = default_range->fallback_end;
}
}
}
@@ -80,12 +108,18 @@ struct execmem_info * __weak execmem_arch_setup(void)
return NULL;
}
-static int __init execmem_init(void)
+static int __init __execmem_init(void)
{
struct execmem_info *info = execmem_arch_setup();
- if (!info)
+ if (!info) {
+ info = execmem_info = &default_execmem_info;
+ info->ranges[EXECMEM_DEFAULT].start = VMALLOC_START;
+ info->ranges[EXECMEM_DEFAULT].end = VMALLOC_END;
+ info->ranges[EXECMEM_DEFAULT].pgprot = PAGE_KERNEL_EXEC;
+ info->ranges[EXECMEM_DEFAULT].alignment = 1;
return 0;
+ }
if (!execmem_validate(info))
return -EINVAL;
@@ -96,4 +130,16 @@ static int __init execmem_init(void)
return 0;
}
+
+#ifndef CONFIG_ARCH_WANTS_EXECMEM_EARLY
+static int __init execmem_init(void)
+{
+ return __execmem_init();
+}
core_initcall(execmem_init);
+#else
+void __init execmem_early_init(void)
+{
+ (void)__execmem_init();
+}
+#endif
diff --git a/mm/mm_init.c b/mm/mm_init.c
index 549e76af8f82..dae777234a31 100644
--- a/mm/mm_init.c
+++ b/mm/mm_init.c
@@ -27,6 +27,7 @@
#include <linux/swap.h>
#include <linux/cma.h>
#include <linux/crash_dump.h>
+#include <linux/execmem.h>
#include "internal.h"
#include "slab.h"
#include "shuffle.h"
@@ -2793,4 +2794,5 @@ void __init mm_core_init(void)
pti_init();
kmsan_init_runtime();
mm_cache_init();
+ execmem_early_init();
}
--
2.43.0
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2024-02-22 9:39 [PATCH v14 00/18] Linux RISC-V AIA Support Anup Patel
2024-02-22 9:39 ` [PATCH v14 01/18] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2024-05-29 14:22 4% ` Geert Uytterhoeven
2024-05-29 22:04 0% ` Samuel Holland
2024-05-30 7:06 0% ` Geert Uytterhoeven
2024-03-12 12:52 [PATCH v3 0/4] PAN for ARM32 using LPAE Linus Walleij
2024-03-12 12:52 ` [PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement Linus Walleij
2024-05-07 13:10 ` Geert Uytterhoeven
2024-05-13 19:23 ` Linus Walleij
2024-05-13 19:58 ` Geert Uytterhoeven
2024-05-13 20:29 ` Linus Walleij
2024-05-14 3:56 ` Florian Fainelli
2024-05-14 8:14 ` Russell King (Oracle)
2024-05-14 11:22 ` Geert Uytterhoeven
2024-05-14 11:33 ` Russell King (Oracle)
2024-05-14 12:32 ` Geert Uytterhoeven
2024-05-14 12:38 6% ` Russell King (Oracle)
2024-05-14 15:03 0% ` Catalin Marinas
2024-05-14 6:41 ` Geert Uytterhoeven
2024-05-14 7:46 6% ` Linus Walleij
2024-05-14 7:59 0% ` Ard Biesheuvel
2024-05-14 8:04 0% ` Geert Uytterhoeven
2024-05-14 8:25 0% ` Ard Biesheuvel
2024-05-14 9:22 0% ` Russell King (Oracle)
2024-05-14 11:28 0% ` Geert Uytterhoeven
2024-05-14 16:06 0% ` Geert Uytterhoeven
2024-05-14 16:54 0% ` Florian Fainelli
2024-05-14 17:03 0% ` Russell King (Oracle)
2024-05-14 18:26 0% ` Florian Fainelli
2024-03-28 19:13 [PATCH v2 0/2] thermal: amlogic: introduce A1 SoC family Thermal Sensor controller Dmitry Rokosov
2024-04-04 12:23 ` Daniel Lezcano
2024-04-17 8:40 ` Dmitry Rokosov
2024-04-26 7:31 0% ` Dmitry Rokosov
2024-04-01 8:13 [PATCH] arm64: dts: rockchip: remove startup-delay-us from vcc3v3_pcie2x1l0 on rock-5b Jianfeng Liu
2024-04-10 6:30 ` Shawn Lin
2024-04-12 16:09 ` Sebastian Reichel
2024-05-15 18:12 0% ` Marc Giger
2024-04-02 14:33 [PATCH v3 00/11] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li
2024-04-02 14:33 ` [PATCH v3 03/11] PCI: imx6: Rename imx6_* with imx_* Frank Li
2024-04-27 9:29 0% ` Manivannan Sadhasivam
2024-04-02 14:33 ` [PATCH v3 06/11] PCI: imx: Simplify switch-case logic by involve set_ref_clk callback Frank Li
2024-04-27 9:54 0% ` Manivannan Sadhasivam
2024-04-02 14:33 ` [PATCH v3 07/11] PCI: imx: Simplify switch-case logic by involve core_reset callback Frank Li
2024-04-27 10:19 0% ` Manivannan Sadhasivam
2024-04-29 16:38 0% ` Frank Li
2024-04-02 14:33 ` [PATCH v3 11/11] PCI: imx6: Add i.MX8Q PCIe support Frank Li
2024-04-27 11:47 0% ` Manivannan Sadhasivam
2024-04-29 17:56 0% ` Frank Li
2024-04-08 14:02 [PATCH] ARM: multi_v7_defconfig: Select CONFIG_USB_ONBOARD_DEV as built-in Fabio Estevam
2024-04-29 22:09 0% ` Fabio Estevam
2024-04-30 6:28 0% ` Alexander Stein
2024-04-30 7:52 0% ` Arnd Bergmann
2024-04-30 19:53 ` Fabio Estevam
2024-04-30 20:24 ` Arnd Bergmann
2024-05-01 23:04 ` Fabio Estevam
2024-05-02 14:49 ` Matthias Kaehlcke
2024-05-02 18:37 ` Arnd Bergmann
2024-05-02 21:45 ` Matthias Kaehlcke
2024-05-02 22:58 5% ` Fabio Estevam
2024-05-03 17:16 0% ` Matthias Kaehlcke
2024-05-03 20:11 0% ` Matthias Kaehlcke
2024-04-09 12:02 [PATCH v2 0/3] drm/mediatek: Add support for OF graphs AngeloGioacchino Del Regno
2024-04-30 10:17 ` Alexandre Mergnat
2024-04-30 11:33 ` AngeloGioacchino Del Regno
2024-05-02 16:53 ` Alexandre Mergnat
2024-05-14 9:46 ` Alexandre Mergnat
2024-05-14 12:00 6% ` AngeloGioacchino Del Regno
2024-04-12 8:40 [v2] Support for Arm CCA VMs on Linux Steven Price
2024-04-12 8:42 ` [PATCH v2 00/43] arm64: Support for Arm CCA in KVM Steven Price
2024-04-12 8:42 ` [PATCH v2 09/43] arm64: RME: ioctls to create and configure realms Steven Price
2024-04-17 9:51 ` Suzuki K Poulose
2024-04-22 16:33 0% ` Steven Price
2024-04-12 8:42 [PATCH v2 09/14] arm64: Enable memory encrypt for Realms Steven Price
2024-04-15 3:13 ` kernel test robot
2024-04-25 13:42 0% ` Suzuki K Poulose
2024-04-25 16:29 0% ` Suzuki K Poulose
2024-04-18 13:53 [PATCH v7 00/16] ACPI/arm64: add support for virtual cpu hotplug Jonathan Cameron
2024-04-18 13:54 ` [PATCH v7 14/16] arm64: Kconfig: Enable hotplug CPU on arm64 if ACPI_PROCESSOR is enabled Jonathan Cameron
2024-04-24 17:24 5% ` Jonathan Cameron
2024-04-19 12:58 [RFC PATCH v3 0/6] Add A1 Soc audio clock controller driver Jan Dakinevich
2024-04-19 12:58 ` [RFC PATCH v3 4/6] dt-bindings: clock: meson: document A1 SoC " Jan Dakinevich
2024-04-19 21:09 ` Rob Herring
2024-04-20 16:15 ` Jan Dakinevich
2024-04-21 18:14 ` Krzysztof Kozlowski
2024-04-22 7:16 ` Jerome Brunet
2024-04-22 7:57 ` Jerome Brunet
2024-04-22 14:31 0% ` Jan Dakinevich
2024-04-22 15:38 0% ` Jerome Brunet
2024-04-22 15:43 0% ` Jan Dakinevich
2024-04-21 1:04 [PATCH v3 00/17] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 04/17] riscv: vector: Use vlenb from DT Charlie Jenkins
2024-04-26 15:17 0% ` Conor Dooley
2024-04-26 16:21 0% ` Conor Dooley
2024-04-26 17:03 0% ` Charlie Jenkins
2024-04-22 8:47 [PATCH v5 01/15] arm64: module: remove unneeded call to kasan_alloc_module_shadow() Mike Rapoport
2024-04-22 8:47 5% ` [PATCH v5 08/15] mm/execmem, arch: convert remaining overrides of module_alloc to execmem Mike Rapoport
2024-04-22 9:44 [PATCH v5 00/15] mm: jit/text allocator Mike Rapoport
2024-04-22 9:44 5% ` [PATCH v5 08/15] mm/execmem, arch: convert remaining overrides of module_alloc to execmem Mike Rapoport
2024-04-23 10:16 [PATCH v3 0/3] Add add SPI-NAND Flash controller driver for EN7581 Lorenzo Bianconi
2024-04-23 10:16 2% ` [PATCH v3 3/3] spi: airoha: add SPI-NAND Flash controller driver Lorenzo Bianconi
2024-04-23 23:51 0% ` Andy Shevchenko
2024-04-24 10:06 0% ` Lorenzo Bianconi
2024-04-23 14:58 5% [PATCH v4 1/2] mm: allow dynamic vmalloc range restrictions Maxwell Bland
2024-04-23 15:00 5% ` mbland
2024-04-23 17:19 [PATCH v2 0/4] PCI: controller: Move to agnostic GPIO API Andy Shevchenko
2024-04-23 17:19 11% ` [PATCH v2 3/4] PCI: imx6: Convert " Andy Shevchenko
2024-04-23 19:56 5% ` Frank Li
2024-04-23 20:03 0% ` Andy Shevchenko
2024-04-23 20:16 5% ` Frank Li
2024-04-23 20:22 0% ` Fabio Estevam
2024-04-23 20:23 0% ` Frank Li
2024-04-27 6:43 0% ` Manivannan Sadhasivam
2024-04-23 17:19 16% ` [PATCH v2 4/4] PCI: kirin: " Andy Shevchenko
2024-04-27 7:23 0% ` Manivannan Sadhasivam
2024-04-24 6:21 [PATCH v3 0/3] Add i.MX8QM HSIO PHY driver Richard Zhu
2024-04-24 6:21 6% ` [PATCH v3 3/3] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support Richard Zhu
2024-04-24 21:50 0% ` Rob Herring
2024-04-25 8:36 0% ` Hongxing Zhu
2024-04-24 9:59 10% [PATCH] soc: xilinx: Add cb event for subsystem restart Jay Buddhabhatti
2024-04-24 12:49 10% ` [PATCH v2] " Jay Buddhabhatti
2024-04-24 11:29 [PATCH V2 0/3] Add support for uartps controller reset Manikanta Guntupalli
2024-04-24 11:29 6% ` [PATCH V2 3/3] tty: serial: uartps: " Manikanta Guntupalli
2024-04-25 6:23 [PATCH V3 0/3] " Manikanta Guntupalli
2024-04-25 6:23 6% ` [PATCH V3 3/3] tty: serial: uartps: " Manikanta Guntupalli
2024-04-25 16:03 [PATCH 0/2] clock support for Samsung Exynos pin controller (Google Tensor gs101) André Draszik
2024-04-25 16:03 9% ` [PATCH 2/2] pinctrl: samsung: support a bus clock André Draszik
2024-04-25 17:12 [PATCH v3 0/3] meson pwm small fixes George Stark
2024-04-25 17:12 7% ` [PATCH v3 3/3] pwm: meson: Use mul_u64_u64_div_u64() for frequency calculating George Stark
2024-04-26 8:28 [PATCH v6 00/16] mm: jit/text allocator Mike Rapoport
2024-04-26 8:28 6% ` [PATCH v6 08/16] mm/execmem, arch: convert remaining overrides of module_alloc to execmem Mike Rapoport
2024-04-26 8:30 [PATCH v4 0/3] Add add SPI-NAND Flash controller driver for EN7581 Lorenzo Bianconi
2024-04-26 8:30 2% ` [PATCH v4 3/3] spi: airoha: add SPI-NAND Flash controller driver Lorenzo Bianconi
2024-04-26 13:10 [PATCH v2 0/2] clock support for Samsung Exynos pin controller (Google Tensor gs101) André Draszik
2024-04-26 13:10 9% ` [PATCH v2 2/2] pinctrl: samsung: support a bus clock André Draszik
2024-04-26 13:25 [PATCH v3 0/2] clock support for Samsung Exynos pin controller (Google Tensor gs101) André Draszik
2024-04-26 13:25 9% ` [PATCH v3 2/2] pinctrl: samsung: support a bus clock André Draszik
2024-05-02 7:41 0% ` Tudor Ambarus
2024-05-02 7:46 0% ` Krzysztof Kozlowski
2024-05-02 10:41 0% ` André Draszik
2024-05-03 9:13 0% ` Krzysztof Kozlowski
2024-04-26 13:51 [PATCH v8 00/16] ACPI/arm64: add support for virtual cpu hotplug Jonathan Cameron
2024-04-26 13:51 5% ` [PATCH v8 14/16] arm64: Kconfig: Enable hotplug CPU on arm64 if ACPI_PROCESSOR is enabled Jonathan Cameron
2024-04-26 13:51 4% ` [PATCH v8 16/16] cpumask: Add enabled cpumask for present CPUs that can be brought online Jonathan Cameron
2024-04-26 21:29 [PATCH v4 00/16] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-26 21:29 5% ` [PATCH v4 03/16] riscv: vector: Use vlenb from DT Charlie Jenkins
2024-05-01 10:31 0% ` Conor Dooley
2024-05-01 16:46 0% ` Charlie Jenkins
2024-04-28 5:07 [PATCH v3 0/6] pinctrl: scmi: support i.MX95 OEM extensions Peng Fan (OSS)
2024-04-28 5:07 5% ` [PATCH v3 2/6] pinctrl: scmi: move pinctrl_ops to scmi_pinctrl Peng Fan (OSS)
2024-04-28 11:40 [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for A64 Dragan Simic
2024-04-28 11:40 5% ` [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6 Dragan Simic
2024-04-28 16:21 0% ` Jernej Škrabec
2024-04-29 23:10 0% ` Andre Przywara
2024-04-30 0:01 0% ` Dragan Simic
2024-04-30 10:46 0% ` Andre Przywara
2024-04-30 11:10 0% ` Dragan Simic
2024-05-01 9:30 0% ` Andre Przywara
2024-04-29 4:13 6% [PATCH] dmaengine: bcm2835-dma: Add check for dma_set_max_seg_size Chen Ni
2024-04-29 8:13 [PATCH v5 0/3] Add add SPI-NAND Flash controller driver for EN7581 Lorenzo Bianconi
2024-04-29 8:13 2% ` [PATCH v5 3/3] spi: airoha: add SPI-NAND Flash controller driver Lorenzo Bianconi
2024-04-29 10:23 [PATCH v3 0/5] PCI: controller: Move to agnostic GPIO API Andy Shevchenko
2024-04-29 10:23 11% ` [PATCH v3 4/5] PCI: imx6: Convert " Andy Shevchenko
2024-04-29 10:23 16% ` [PATCH v3 5/5] PCI: kirin: " Andy Shevchenko
2024-04-30 5:16 0% ` Manivannan Sadhasivam
2024-04-29 12:16 [PATCH v7 00/16] mm: jit/text allocator Mike Rapoport
2024-04-29 12:16 6% ` [PATCH v7 08/16] mm/execmem, arch: convert remaining overrides of module_alloc to execmem Mike Rapoport
2024-04-29 16:29 ` [PATCH v7 00/16] mm: jit/text allocator Luis Chamberlain
2024-05-02 22:50 5% ` Liviu Dudau
2024-05-02 23:07 0% ` Luis Chamberlain
2024-05-03 0:23 0% ` Liviu Dudau
2024-05-03 6:28 0% ` Mike Rapoport
2024-05-03 10:40 0% ` Liviu Dudau
2024-04-30 4:58 6% [PATCH v7 0/2] modify Signed-off-by field Kelly Hung
2024-04-30 6:48 0% ` Paul Menzel
[not found] ` <CAK=2Bxt=WK4AdktNZDN2iXjk3ga9WRqUm9JQHoNjRnrW8hVt0Q@mail.gmail.com>
2024-04-30 10:21 0% ` Paul Menzel
2024-04-30 7:12 5% [syzbot] Monthly arm report (Apr 2024) syzbot
2024-04-30 7:51 [PATCH 0/3] media: bcm2835-unicam: Improve error handling during probe Ricardo Ribalda
2024-04-30 7:51 7% ` [PATCH 3/3] media: bcm2835-unicam: Do not replace IRQ retcode " Ricardo Ribalda
2024-05-06 18:03 0% ` Laurent Pinchart
2024-04-30 8:37 [PATCH 00/17] Add support for the LAN966x PCI device using a DT overlay Herve Codina
2024-04-30 8:37 5% ` [PATCH 16/17] mfd: Add support for LAN966x PCI device Herve Codina
2024-05-08 8:20 0% ` Steen.Hegelund
2024-05-14 12:55 0% ` Herve Codina
2024-04-30 14:24 [PATCH v9 00/19] ACPI/arm64: add support for virtual cpu hotplug Jonathan Cameron
2024-04-30 14:24 5% ` [PATCH v9 17/19] arm64: Kconfig: Enable hotplug CPU on arm64 if ACPI_PROCESSOR is enabled Jonathan Cameron
2024-04-30 14:24 4% ` [PATCH v9 19/19] cpumask: Add enabled cpumask for present CPUs that can be brought online Jonathan Cameron
2024-05-01 11:14 0% ` Gavin Shan
2024-05-01 12:17 [PATCH v5 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-05-01 12:17 5% ` [PATCH v5 08/17] ACPI: pci_link: Clear the dependencies after probe Sunil V L
2024-05-01 16:56 0% ` Bjorn Helgaas
2024-05-02 9:25 0% ` Andy Shevchenko
2024-05-02 9:32 0% ` Sunil V L
2024-05-01 12:17 3% ` [PATCH v5 14/17] irqchip/riscv-imsic: Add ACPI support Sunil V L
2024-05-23 22:00 0% ` Thomas Gleixner
2024-05-27 4:52 0% ` Sunil V L
2024-05-01 14:06 [PATCH v6 0/3] Add add spi-nand flash controller driver for EN7581 Lorenzo Bianconi
2024-05-01 14:06 2% ` [PATCH v6 3/3] spi: airoha: Add spi-nand flash controller driver Lorenzo Bianconi
2024-05-03 4:46 [PATCH v5 00/17] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-05-03 4:46 5% ` [PATCH v5 03/17] riscv: vector: Use vlenb from DT Charlie Jenkins
2024-05-03 16:59 0% ` Conor Dooley
2024-05-03 17:15 0% ` Charlie Jenkins
2024-05-03 9:09 4% [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H616 Dragan Simic
2024-05-08 11:05 0% ` Andre Przywara
2024-05-08 11:15 0% ` Dragan Simic
2024-05-28 16:08 0% ` Chen-Yu Tsai
2024-05-28 16:47 0% ` Dragan Simic
2024-05-03 15:35 [PATCH 0/2] Mediatek lvts_thermal driver: Fix wrong lvts_ctrl index Julien Panis
2024-05-03 15:35 5% ` [PATCH 2/2] thermal/drivers/mediatek/lvts_thermal: " Julien Panis
2024-05-03 15:45 0% ` Nicolas Pitre
2024-05-06 7:52 0% ` AngeloGioacchino Del Regno
2024-05-03 18:18 [PATCH v6 00/17] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-05-03 18:18 5% ` [PATCH v6 03/17] riscv: vector: Use vlenb from DT Charlie Jenkins
2024-05-16 13:11 0% ` Andy Chiu
2024-05-16 14:00 0% ` Andy Chiu
2024-05-03 21:54 [BUG] drm: zynqmp_dp: Lockup in zynqmp_dp_bridge_detect when device is unbound Sean Anderson
2024-05-06 11:16 ` Tomi Valkeinen
2024-05-06 14:46 4% ` Sean Anderson
2024-05-05 14:25 [PATCH v8 00/17] mm: jit/text allocator Mike Rapoport
2024-05-05 14:25 6% ` [PATCH v8 08/17] mm/execmem, arch: convert remaining overrides of module_alloc to execmem Mike Rapoport
2024-05-05 16:06 [PATCH RESEND v8 00/16] mm: jit/text allocator Mike Rapoport
2024-05-05 16:06 6% ` [PATCH RESEND v8 08/16] mm/execmem, arch: convert remaining overrides of module_alloc to execmem Mike Rapoport
2024-05-06 12:48 [PATCH 0/2] MIPI DSI phy for rk3588 Heiko Stuebner
2024-05-06 12:48 1% ` [PATCH 2/2] phy: rockchip: Add Samsung CSI/DSI Combo DCPHY driver Heiko Stuebner
2024-05-06 13:32 [PATCH 0/8] irqchip/stm32-exti: split MCU and MPU code, allow module build Antonio Borneo
2024-05-06 13:32 2% ` [PATCH 4/8] irqchip/stm32-exti: split MCU and MPU code Antonio Borneo
2024-05-06 14:20 [PATCH v4 0/5] PCI: controller: Move to agnostic GPIO API Andy Shevchenko
2024-05-06 14:20 11% ` [PATCH v4 4/5] PCI: imx6: Convert " Andy Shevchenko
2024-05-07 19:22 0% ` Frank Li
2024-05-09 1:24 0% ` Hongxing Zhu
2024-05-09 4:24 0% ` Andy Shevchenko
2024-05-06 14:20 16% ` [PATCH v4 5/5] PCI: kirin: " Andy Shevchenko
2024-05-06 19:24 [PATCH v2 0/2] media: bcm2835-unicam: Improve error handling during probe Ricardo Ribalda
2024-05-06 19:24 7% ` [PATCH v2 1/2] media: bcm2835-unicam: Do not replace IRQ retcode " Ricardo Ribalda
2024-05-07 6:08 0% ` Laurent Pinchart
[not found] <CGME20240507064445eucas1p1bfc17da4f824ef46567774634482f12f@eucas1p1.samsung.com>
2024-05-07 6:44 5% ` [PATCH] clkdev: fix potential NULL pointer dereference Marek Szyprowski
2024-05-07 13:10 [PATCH v2 0/8] irqchip/stm32-exti: split MCU and MPU code, allow module build Antonio Borneo
2024-05-07 13:10 2% ` [PATCH v2 4/8] irqchip/stm32-exti: split MCU and MPU code Antonio Borneo
2024-05-07 18:45 [PATCH v4 00/12] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li
2024-05-07 18:45 7% ` [PATCH v4 03/12] PCI: imx6: Rename imx6_* with imx_* Frank Li
2024-05-07 18:45 5% ` [PATCH v4 04/12] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li
2024-05-07 18:45 10% ` [PATCH v4 05/12] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li
2024-05-07 18:45 5% ` [PATCH v4 11/12] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Frank Li
2024-05-08 6:51 [PATCH v8 0/3] Add support for nuvoton ma35d1 pin control Jacky Huang
2024-05-08 6:51 1% ` [PATCH v8 3/3] pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driver Jacky Huang
[not found] <CA+G9fYuZd_ur56H8fwDSvUywopvn_b7ogprGkjEatQ7EPTLwYQ@mail.gmail.com>
2024-05-07 7:44 ` clkdev: report over-sized strings when creating clkdev entries Arnd Bergmann
2024-05-07 20:26 ` Stephen Boyd
2024-05-08 21:07 5% ` Sam Protsenko
2024-05-09 4:56 10% [PATCH v2 RESEND] soc: xilinx: Add cb event for subsystem restart Jay Buddhabhatti
2024-05-09 5:56 [PATCH v4 0/3] Add i.MX8Q HSIO PHY support Richard Zhu
2024-05-09 5:56 6% ` [PATCH v4 3/3] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support Richard Zhu
2024-05-09 14:44 0% ` Frank Li
2024-05-09 12:07 [PATCH v2 0/7] Add DSI support for RK3128 Alex Bee
2024-05-09 12:07 12% ` [PATCH v2 4/7] drm/rockchip: dsi: Support optional AHB clock Alex Bee
2024-05-09 17:45 5% [PATCH rc] iommu/arm-smmu: Use the correct type in nvidia_smmu_context_fault() Jason Gunthorpe
2024-05-09 18:51 0% ` Jerry Snitselaar
2024-05-09 19:26 0% ` Jerry Snitselaar
2024-05-09 19:30 0% ` Jerry Snitselaar
2024-05-09 18:25 5% [PATCH v5 1/2] mm: allow dynamic vmalloc range restrictions Maxwell Bland
2024-05-10 7:13 [PATCH 0/3] Use scope based cleanup in drivers/soc/ti/ Kousik Sanagavarapu
2024-05-10 7:13 10% ` [PATCH 3/3] soc: ti: pm33xx: do device_node auto cleanup Kousik Sanagavarapu
2024-05-10 13:27 [PATCH 0/4] Communication Interface to NXP secure-enclave HW IP like Edgelock Enclave Pankaj Gupta
2024-05-10 13:27 2% ` [PATCH 4/4] firmware: imx: add driver for NXP EdgeLock Enclave Pankaj Gupta
2024-05-10 16:41 0% ` Frank Li
2024-05-10 19:39 0% ` Amit Singh Tomar
2024-05-13 9:16 0% ` [EXT] " Pankaj Gupta
2024-05-13 9:12 0% ` Pankaj Gupta
2024-05-13 10:54 0% ` Marc Kleine-Budde
2024-05-16 4:47 0% ` Amit Singh Tomar
2024-05-16 4:52 0% ` [EXT] " Pankaj Gupta
2024-05-13 1:22 [PATCH v5 0/2] Add i.MX8Q HSIO PHY support Richard Zhu
2024-05-13 1:22 6% ` [PATCH v5 2/2] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support Richard Zhu
2024-05-13 23:13 5% [PATCH] iommu/arm-smmu: Don't disable next-page prefetcher on devices it works on Douglas Anderson
2024-05-14 17:14 0% ` Robin Murphy
2024-05-17 16:37 0% ` Will Deacon
2024-05-17 17:19 5% ` Doug Anderson
2024-05-15 10:01 [PATCH v6 00/12] Add suspend to ram support for PCIe on J7200 Thomas Richard
2024-05-15 10:01 6% ` [PATCH v6 04/12] mux: add mux_chip_resume() function Thomas Richard
[not found] <CGME20240517105941epcas5p3e8dbb97f19c9553bf9942ad146124806@epcas5p3.samsung.com>
2024-05-17 10:59 4% ` [PATCH 1/1] PCI : Refactoring error log prints for better readability Onkarnarth
2024-05-21 1:24 [PATCH v9 0/3] Add support for nuvoton ma35d1 pin control Jacky Huang
2024-05-21 1:24 1% ` [PATCH v9 3/3] pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driver Jacky Huang
[not found] <CGME20240521061553epcas5p1c7db70b37a70f599face675bc4dedda9@epcas5p1.samsung.com>
2024-05-21 6:15 4% ` [PATCH v2 1/1] PCI : Refactoring error log prints for better readability Onkarnarth
2024-05-21 10:58 [PATCH v4 00/10] drm/verisilicon : support DC8200 and inno hdmi keith
2024-05-21 10:58 5% ` [PATCH v4 03/10] drm/rockchip:hdmi: migrate to use inno-hdmi bridge driver keith
2024-05-21 12:24 [RESEND PATCH v5 0/7] Introduction of a remoteproc tee to load signed firmware Arnaud Pouliquen
2024-05-21 12:24 3% ` [RESEND PATCH v5 1/7] remoteproc: Add TEE support Arnaud Pouliquen
2024-05-21 18:18 3% [PATCH] kselftest/arm64: Include kernel mode NEON in fp-stress Mark Brown
2024-05-23 8:16 6% arm64: kernel panic on 4G RAM platform Alexander Wilhelm
2024-05-23 10:49 [PATCH v2 0/5] Communication Interface to NXP secure-enclave HW IP like Edgelock Enclave Pankaj Gupta
2024-05-23 10:49 3% ` [PATCH v2 4/5] firmware: imx: add driver for NXP EdgeLock Enclave Pankaj Gupta
2024-05-24 9:07 0% ` Sascha Hauer
2024-05-25 23:29 [PATCH v6 0/7] Add mediate-drm secure flow for SVP Jason-JH.Lin
2024-05-25 23:29 3% ` [PATCH v6 6/7] drm/mediatek: Add secure flow support to mediatek-drm Jason-JH.Lin
2024-05-27 16:14 [PATCH v2 00/19] Add support for the LAN966x PCI device using a DT overlay Herve Codina
2024-05-27 16:14 5% ` [PATCH v2 18/19] mfd: Add support for LAN966x PCI device Herve Codina
2024-05-28 2:59 [PATCH v6 0/2] Add i.MX8Q HSIO PHY support Richard Zhu
2024-05-28 2:59 6% ` [PATCH v6 2/2] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support Richard Zhu
2024-05-28 14:52 0% ` Frank Li
2024-05-28 12:06 3% [PATCH] i2c: viai2c: turn common code into a proper module Arnd Bergmann
2024-05-28 12:08 [PATCH] arm64/io: add constant-argument check Arnd Bergmann
2024-05-29 11:14 ` Mark Rutland
2024-05-29 12:29 5% ` Arnd Bergmann
2024-05-29 15:08 0% ` Mark Rutland
2024-05-28 12:47 10% [syzbot] [arm?] BUG: unable to handle kernel paging request in task_h_load syzbot
2024-05-28 16:45 4% [PATCH v2] arm64: dts: allwinner: Add cache information to the SoC dtsi for H616 Dragan Simic
2024-05-28 19:39 [PATCH v5 00/12] PCI: imx6: Fix\rename\clean up and add lut information for imx95 Frank Li
2024-05-28 19:39 7% ` [PATCH v5 03/12] PCI: imx6: Rename imx6_* with imx_* Frank Li
2024-05-28 19:39 5% ` [PATCH v5 04/12] PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK Frank Li
2024-05-28 19:39 10% ` [PATCH v5 05/12] PCI: imx6: Simplify switch-case logic by involve core_reset callback Frank Li
2024-05-28 19:39 5% ` [PATCH v5 11/12] PCI: imx6: Call: Common PHY API to set mode, speed, and submode Frank Li
2024-05-29 6:02 [PATCH v7 0/2] Add i.MX8Q HSIO PHY support Richard Zhu
2024-05-29 6:02 6% ` [PATCH v7 2/2] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support Richard Zhu
2024-05-29 13:34 [PATCH v10 00/19] ACPI/arm64: add support for virtual cpu hotplug Jonathan Cameron
2024-05-29 13:34 5% ` [PATCH v10 17/19] arm64: Kconfig: Enable hotplug CPU on arm64 if ACPI_PROCESSOR is enabled Jonathan Cameron
2024-05-29 13:34 4% ` [PATCH v10 19/19] cpumask: Add enabled cpumask for present CPUs that can be brought online Jonathan Cameron
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