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From: Stephen Boyd <sboyd@kernel.org>
To: Andy Gross <agross@kernel.org>, Vinod Koul <vkoul@kernel.org>
Cc: linux-arm-msm@vger.kernel.org,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	sibis@codeaurora.org, Vinod Koul <vkoul@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 01/22] arm64: dts: qcom: sm8150: add base dts file
Date: Wed, 14 Aug 2019 09:58:54 -0700
Message-ID: <20190814165855.098FD2063F@mail.kernel.org> (raw)
In-Reply-To: <20190814125012.8700-2-vkoul@kernel.org>

Quoting Vinod Koul (2019-08-14 05:49:51)
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> new file mode 100644
> index 000000000000..cd9fcadaeacb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -0,0 +1,269 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
> +// Copyright (c) 2019, Linaro Limited
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-sm8150.h>
> +
> +/ {
> +       interrupt-parent = <&intc>;
> +
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       chosen { };
> +
> +       clocks {
> +               xo_board: xo-board {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <19200000>;

Is it 19.2 or 38.4 MHz? It seems like lately there are dividers, but I
guess it doesn't really matter in the end.

> +                       clock-output-names = "xo_board";
> +               };
> +
> +               sleep_clk: sleep-clk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <32764>;
> +                       clock-output-names = "sleep_clk";

Does it matter to have this property anymore? Presumably it's OK if the
name is now sleep-clk instead of sleep_clk because the name doesn't
matter to connect clk tree.

> +               };
> +       };
> +
> +       cpus {
> +               #address-cells = <2>;
> +               #size-cells = <0>;
> +
> +               CPU0: cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo485";
> +                       reg = <0x0 0x0>;
> +                       enable-method = "psci";
> +                       next-level-cache = <&L2_0>;
> +                       L2_0: l2-cache {
> +                               compatible = "cache";
> +                               next-level-cache = <&L3_0>;
> +                               L3_0: l3-cache {
> +                                     compatible = "cache";
> +                               };
> +                       };
> +               };
> +
> +               CPU1: cpu@100 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo485";
> +                       reg = <0x0 0x100>;
> +                       enable-method = "psci";
> +                       next-level-cache = <&L2_100>;
> +                       L2_100: l2-cache {
> +                               compatible = "cache";
> +                               next-level-cache = <&L3_0>;
> +                       };
> +
> +               };
> +
> +               CPU2: cpu@200 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo485";
> +                       reg = <0x0 0x200>;
> +                       enable-method = "psci";
> +                       next-level-cache = <&L2_200>;
> +                       L2_200: l2-cache {
> +                               compatible = "cache";
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +
> +               CPU3: cpu@300 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo485";
> +                       reg = <0x0 0x300>;
> +                       enable-method = "psci";
> +                       next-level-cache = <&L2_300>;
> +                       L2_300: l2-cache {
> +                               compatible = "cache";
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +
> +               CPU4: cpu@400 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo485";
> +                       reg = <0x0 0x400>;
> +                       enable-method = "psci";
> +                       next-level-cache = <&L2_400>;
> +                       L2_400: l2-cache {
> +                               compatible = "cache";
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +
> +               CPU5: cpu@500 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo485";
> +                       reg = <0x0 0x500>;
> +                       enable-method = "psci";
> +                       next-level-cache = <&L2_500>;
> +                       L2_500: l2-cache {
> +                               compatible = "cache";
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +
> +               CPU6: cpu@600 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo485";
> +                       reg = <0x0 0x600>;
> +                       enable-method = "psci";
> +                       next-level-cache = <&L2_600>;
> +                       L2_600: l2-cache {
> +                               compatible = "cache";
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +
> +               CPU7: cpu@700 {
> +                       device_type = "cpu";
> +                       compatible = "qcom,kryo485";

Is this compatible documented?

> +                       reg = <0x0 0x700>;
> +                       enable-method = "psci";
> +                       next-level-cache = <&L2_700>;
> +                       L2_700: l2-cache {
> +                               compatible = "cache";
> +                               next-level-cache = <&L3_0>;
> +                       };
> +               };
> +       };
> +
> +       firmware {
> +               scm: scm {
> +                       compatible = "qcom,scm-sm8150", "qcom,scm";
> +                       #reset-cells = <1>;
> +               };
> +       };
> +
> +       memory@80000000 {
> +               device_type = "memory";
> +               /* We expect the bootloader to fill in the size */
> +               reg = <0 0x80000000 0 0>;
> +       };
> +
> +       psci {
> +               compatible = "arm,psci-1.0";
> +               method = "smc";
> +       };
> +
> +       soc: soc@0 {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges = <0 0 0 0xffffffff>;
> +               compatible = "simple-bus";
> +
> +               gcc: clock-controller@100000 {
> +                       compatible = "qcom,gcc-sm8150";
> +                       reg = <0x00100000 0x1f0000>;
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <1>;
> +                       clock-names = "bi_tcxo", "sleep_clk";
> +                       clocks = <&xo_board>, <&sleep_clk>;
> +               };
> +
> +               qupv3_id_1: geniqup@ac0000 {
> +                       compatible = "qcom,geni-se-qup";
> +                       reg = <0x00ac0000 0x6000>;
> +                       clock-names = "m-ahb", "s-ahb";
> +                       clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> +                                <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +                       status = "disabled";
> +
> +                       uart2: serial@a90000 {
> +                               compatible = "qcom,geni-debug-uart";
> +                               reg = <0x00a90000 0x4000>;
> +                               clock-names = "se";
> +                               clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> +                               interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               intc: interrupt-controller@17a00000 {
> +                       compatible = "arm,gic-v3";
> +                       interrupt-controller;
> +                       #interrupt-cells = <3>;
> +                       reg = <0x17a00000 0x10000>,     /* GICD */
> +                             <0x17a60000 0x100000>;    /* GICR * 8 */
> +                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

Is there an its node? Probably the same as sdm845?

> +               };
> +
> +               timer@17c20000 {
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +                       compatible = "arm,armv7-timer-mem";
> +                       reg = <0x17c20000 0x1000>;
> +                       clock-frequency = <19200000>;

This property shouldn't be necessary. Please remove.

> +
> +                       frame@17c21000{
> +                               frame-number = <0>;
> +                               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

  reply index

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-14 12:49 [PATCH 00/22] arm64: dts: qcom: sm8150: Add SM8150 DTS Vinod Koul
2019-08-14 12:49 ` [PATCH 01/22] arm64: dts: qcom: sm8150: add base dts file Vinod Koul
2019-08-14 16:58   ` Stephen Boyd [this message]
2019-08-14 17:44     ` Bjorn Andersson
2019-08-14 18:35       ` Stephen Boyd
2019-08-14 19:02         ` Bjorn Andersson
2019-08-14 17:50   ` Bjorn Andersson
2019-08-14 12:49 ` [PATCH 02/22] arm64: dts: qcom: sm8150-mtp: " Vinod Koul
2019-08-14 17:53   ` Bjorn Andersson
2019-08-14 12:49 ` [PATCH 03/22] arm64: dts: qcom: sm8150: add tlmm node Vinod Koul
2019-08-14 17:01   ` Stephen Boyd
2019-08-19 17:09     ` Vinod Koul
2019-08-14 12:49 ` [PATCH 04/22] arm64: dts: qcom: sm8150-mtp: add tlmm reserved range Vinod Koul
2019-08-14 17:01   ` Stephen Boyd
2019-08-14 12:49 ` [PATCH 05/22] arm64: dts: qcom: sm8150: Add spmi node Vinod Koul
2019-08-14 17:01   ` Stephen Boyd
2019-08-14 12:49 ` [PATCH 06/22] arm64: dts: qcom: pm8150: Add Base DTS file Vinod Koul
2019-08-14 17:03   ` Stephen Boyd
2019-08-19 17:28     ` Vinod Koul
2019-08-14 12:49 ` [PATCH 07/22] arm64: dts: qcom: pm8150: Add pon and rtc nodes Vinod Koul
2019-08-14 17:03   ` Stephen Boyd
2019-08-19 17:32     ` Vinod Koul
2019-08-14 12:49 ` [PATCH 08/22] arm64: dts: qcom: pm8150: Add vadc node Vinod Koul
2019-08-14 17:05   ` Stephen Boyd
2019-08-14 12:49 ` [PATCH 09/22] arm64: dts: qcom: pm8150b: Add Base DTS file Vinod Koul
2019-08-14 17:05   ` Stephen Boyd
2019-08-14 12:50 ` [PATCH 10/22] arm64: dts: qcom: pm8150b: Add pon and adc nodes Vinod Koul
2019-08-14 17:08   ` Stephen Boyd
2019-08-19 17:43     ` Vinod Koul
2019-08-19 17:56       ` Stephen Boyd
2019-08-20  3:46         ` Vinod Koul
2019-08-14 18:00   ` Bjorn Andersson
2019-08-14 12:50 ` [PATCH 11/22] arm64: dts: qcom: pm8150b: Add gpio node Vinod Koul
2019-08-14 17:08   ` Stephen Boyd
2019-08-14 12:50 ` [PATCH 12/22] arm64: dts: qcom: pm8150l: Add Base DTS file Vinod Koul
2019-08-14 17:10   ` Stephen Boyd
2019-08-14 12:50 ` [PATCH 13/22] arm64: dts: qcom: pm8150l: Add pon and adc nodes Vinod Koul
2019-08-14 17:10   ` Stephen Boyd
2019-08-14 12:50 ` [PATCH 14/22] arm64: dts: qcom: pm8150l: Add gpio node Vinod Koul
2019-08-14 12:50 ` [PATCH 15/22] arm64: dts: qcom: sm8150-mtp: Include pmics Vinod Koul
2019-08-14 12:50 ` [PATCH 16/22] arm64: dts: qcom: sm8150-mtp: Add resin node Vinod Koul
2019-08-14 12:50 ` [PATCH 17/22] arm64: dts: qcom: sm8150: Add apss_shared and apps_rsc nodes Vinod Koul
2019-08-14 17:12   ` Stephen Boyd
2019-08-19 17:35     ` Vinod Koul
2019-08-14 12:50 ` [PATCH 18/22] arm64: dts: qcom: sm8150: Add reserved-memory regions Vinod Koul
2019-08-14 17:13   ` Stephen Boyd
2019-08-19 17:36     ` Vinod Koul
2019-08-14 12:50 ` [PATCH 19/22] arm64: dts: qcom: sm8150-mtp: Add regulators Vinod Koul
2019-08-14 12:50 ` [PATCH 20/22] arm64: dts: qcom: sm8150: Add pmu node to SM8150 SoC Vinod Koul
2019-08-14 17:15   ` Stephen Boyd
2019-08-14 12:50 ` [PATCH 21/22] arm64: dts: qcom: sm8150: Add SMEM nodes Vinod Koul
2019-08-14 17:16   ` Stephen Boyd
2019-08-14 12:50 ` [PATCH 22/22] arm64: dts: qcom: sm8150: Add APSS shared mailbox Vinod Koul
2019-08-14 17:17   ` Stephen Boyd
2019-08-19 17:41     ` Vinod Koul
2019-08-20  6:20       ` Sibi Sankar
2019-08-20  6:37         ` Vinod Koul

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