From: Rob Herring <robh+dt@kernel.org>
To: Baruch Siach <baruch@tkos.co.il>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>,
Kathiravan T <kathirav@codeaurora.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Robert Marko <robert.marko@sartura.hr>,
devicetree@vger.kernel.org, linux-phy@lists.infradead.org,
PCI <linux-pci@vger.kernel.org>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-tegra <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller
Date: Wed, 25 Aug 2021 10:03:51 -0500 [thread overview]
Message-ID: <CAL_JsqKLijW0H-f0Ptd3EKrE5mRwtQK5StOTzs3b5UesuuVKdg@mail.gmail.com> (raw)
In-Reply-To: <87lf4pa9i0.fsf@tarshish>
On Wed, Aug 25, 2021 at 9:23 AM Baruch Siach <baruch@tkos.co.il> wrote:
>
> Hi Rob,
>
> On Wed, Aug 25 2021, Rob Herring wrote:
> > On Wed, Aug 25, 2021 at 6:25 AM Baruch Siach <baruch@tkos.co.il> wrote:
> >> On Fri, Aug 06 2021, Rob Herring wrote:
> >> > On Wed, May 5, 2021 at 3:18 AM Baruch Siach <baruch@tkos.co.il> wrote:
> >> >> + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
> >> >> + PCI_EXP_DEVCTL2);
> >> >> +
> >> >> + writel(PCIE_CAP_CURR_DEEMPHASIS | SPEED_GEN3,
> >> >> + pci->dbi_base + offset + PCI_EXP_DEVCTL2);
> >> >
> >> > Doesn't this overwrite the prior register write?
> >>
> >> It does. There are two mistakes here. The writel() above should set
> >> PCIE20_DEVICE_CONTROL2_STATUS2 (offset 0x98).
> >
> > No. Did you check what 'offset' is? PCIE20_DEVICE_CONTROL2_STATUS2 is
> > PCI_EXP_DEVCTL2 plus the status reg. What's wrong is it should be a
> > 16-bit write.
>
> Thanks for enlightening me. 'offset' is 0x70 here. So PCI_EXP_DEVCTL2 is
> at 0x98, and PCI_EXP_LNKCTL2 is at 0xa0. Only the second writel() is
> wrong. But since generic code handles speed, I can drop it entirely.
>
> I see that dw_pcie_link_set_max_speed() uses dw_pcie_writel_dbi() to
> write to PCI_EXP_LNKCTL2. Is that 16-bit write?
No, that may be because some platforms can only do 32-bit accesses and
dw_pcie_writew_dbi would be a RMW in that case. Or maybe there's some
reliance on clearing the status register.
> Why are pci_regs.h register offsets in decimal?
No idea...
Rob
next prev parent reply other threads:[~2021-08-25 15:04 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 9:18 [PATCH v2 0/6] arm64: IPQ6018 PCIe support Baruch Siach
2021-05-05 9:18 ` [PATCH v2 1/6] PCI: dwc: tegra: move GEN3_RELATED DBI register to common header Baruch Siach
2021-08-06 19:47 ` Rob Herring
2021-05-05 9:18 ` [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller Baruch Siach
2021-08-06 19:59 ` Rob Herring
2021-08-25 11:15 ` Baruch Siach
2021-08-25 13:38 ` Rob Herring
2021-08-25 14:09 ` Baruch Siach
2021-08-25 15:03 ` Rob Herring [this message]
2021-08-25 16:05 ` Bjorn Helgaas
2021-08-25 16:37 ` Bjorn Helgaas
2021-05-05 9:18 ` [PATCH v2 3/6] phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx Baruch Siach
2021-05-14 11:43 ` Vinod Koul
2021-05-05 9:18 ` [PATCH v2 4/6] arm64: dts: ipq6018: Add pcie support Baruch Siach
2021-05-05 9:18 ` [PATCH v2 5/6] dt-bindings: phy: qcom,qmp: Add IPQ60xx PCIe PHY bindings Baruch Siach
2021-05-14 11:43 ` Vinod Koul
2021-05-05 9:18 ` [PATCH v2 6/6] dt-bindings: pci: qcom: Document PCIe bindings for IPQ6018 SoC Baruch Siach
2021-05-14 11:43 ` Vinod Koul
2021-08-05 6:58 ` [PATCH v2 0/6] arm64: IPQ6018 PCIe support Baruch Siach
2021-08-05 9:42 ` Lorenzo Pieralisi
2021-08-06 12:48 ` Vinod Koul
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