From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Peter Geis <pgwipeout@gmail.com>,
Nicolas Chauvet <kwizart@gmail.com>,
Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v6 05/12] clk: tegra30: Use custom CCLK implementation
Date: Wed, 18 Dec 2019 23:21:35 +0300 [thread overview]
Message-ID: <20191218202142.11717-6-digetx@gmail.com> (raw)
In-Reply-To: <20191218202142.11717-1-digetx@gmail.com>
We're going to use the generic cpufreq-dt driver on Tegra30 and thus CCLK
intermediate re-parenting will be performed by the clock driver. There is
now special CCLK implementation that supports all CCLK quirks, this patch
makes Tegra30 SoCs to use that implementation.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/clk/tegra/clk-tegra30.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c8bc18e4d7e5..0fe03d69fe1a 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -499,6 +499,8 @@ static struct tegra_clk_pll_params pll_x_params __ro_after_init = {
.freq_table = pll_x_freq_table,
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
+ .pre_rate_change = tegra_cclk_pre_pllx_rate_change,
+ .post_rate_change = tegra_cclk_post_pllx_rate_change,
};
static struct tegra_clk_pll_params pll_e_params __ro_after_init = {
@@ -932,11 +934,11 @@ static void __init tegra30_super_clk_init(void)
clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
/* CCLKG */
- clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
+ clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,
ARRAY_SIZE(cclk_g_parents),
CLK_SET_RATE_PARENT,
clk_base + CCLKG_BURST_POLICY,
- 0, 4, 0, 0, NULL);
+ 0, NULL);
clks[TEGRA30_CLK_CCLK_G] = clk;
/*
--
2.24.0
next prev parent reply other threads:[~2019-12-18 20:22 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-18 20:21 [PATCH v6 00/12] NVIDIA Tegra20 CPUFreq driver major update Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 01/12] clk: tegra: Add custom CCLK implementation Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 02/12] clk: tegra: pll: Add pre/post rate-change hooks Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 03/12] clk: tegra: cclk: Add helpers for handling PLLX rate changes Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 04/12] clk: tegra20: Use custom CCLK implementation Dmitry Osipenko
2019-12-18 20:21 ` Dmitry Osipenko [this message]
2019-12-18 20:21 ` [PATCH v6 06/12] ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124 Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 07/12] ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30 Dmitry Osipenko
2020-02-01 22:57 ` Marcel Ziswiler
2020-02-02 1:08 ` Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 08/12] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 09/12] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 10/12] ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 11/12] ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 12/12] ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Dmitry Osipenko
2020-01-07 23:17 ` [PATCH v6 00/12] NVIDIA Tegra20 CPUFreq driver major update Dmitry Osipenko
2020-01-14 15:53 ` Peter De Schrijver
2020-01-14 20:36 ` Dmitry Osipenko
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