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From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Viresh Kumar <viresh.kumar@linaro.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Peter Geis <pgwipeout@gmail.com>,
	Nicolas Chauvet <kwizart@gmail.com>,
	Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v6 06/12] ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
Date: Wed, 18 Dec 2019 23:21:36 +0300	[thread overview]
Message-ID: <20191218202142.11717-7-digetx@gmail.com> (raw)
In-Reply-To: <20191218202142.11717-1-digetx@gmail.com>

The early-resume code shall not switch CPU to PLLX because PLLX
configuration could be unstable or PLLX should be simply disabled if
CPU enters into suspend running off some other PLL (the case if CPUFREQ
driver is active). The actual burst policy is restored by the clock
drivers.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 arch/arm/mach-tegra/sleep-tegra30.S | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 3341a12bbb9c..9a20c93abe48 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -383,11 +383,8 @@ _pll_m_c_x_done:
 	ldr	r4, [r5, #0x1C]		@ restore SCLK_BURST
 	str	r4, [r0, #CLK_RESET_SCLK_BURST]
 
-	cmp	r10, #TEGRA30
-	movweq	r4, #:lower16:((1 << 28) | (0x8))	@ burst policy is PLLX
-	movteq	r4, #:upper16:((1 << 28) | (0x8))
-	movwne	r4, #:lower16:((1 << 28) | (0xe))
-	movtne	r4, #:upper16:((1 << 28) | (0xe))
+	movw	r4, #:lower16:((1 << 28) | (0x4))	@ burst policy is PLLP
+	movt	r4, #:upper16:((1 << 28) | (0x4))
 	str	r4, [r0, #CLK_RESET_CCLK_BURST]
 
 	/* Restore pad power state to normal */
-- 
2.24.0


  parent reply	other threads:[~2019-12-18 20:22 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-18 20:21 [PATCH v6 00/12] NVIDIA Tegra20 CPUFreq driver major update Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 01/12] clk: tegra: Add custom CCLK implementation Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 02/12] clk: tegra: pll: Add pre/post rate-change hooks Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 03/12] clk: tegra: cclk: Add helpers for handling PLLX rate changes Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 04/12] clk: tegra20: Use custom CCLK implementation Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 05/12] clk: tegra30: " Dmitry Osipenko
2019-12-18 20:21 ` Dmitry Osipenko [this message]
2019-12-18 20:21 ` [PATCH v6 07/12] ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30 Dmitry Osipenko
2020-02-01 22:57   ` Marcel Ziswiler
2020-02-02  1:08     ` Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 08/12] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 09/12] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 10/12] ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 11/12] ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS Dmitry Osipenko
2019-12-18 20:21 ` [PATCH v6 12/12] ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Dmitry Osipenko
2020-01-07 23:17 ` [PATCH v6 00/12] NVIDIA Tegra20 CPUFreq driver major update Dmitry Osipenko
2020-01-14 15:53 ` Peter De Schrijver
2020-01-14 20:36   ` Dmitry Osipenko

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