From: Geert Uytterhoeven <geert@linux-m68k.org> To: Hadar Gat <hadar.gat@arm.com> Cc: Matt Mackall <mpm@selenic.com>, Herbert Xu <herbert@gondor.apana.org.au>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Arnd Bergmann <arnd@arndb.de>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Krzysztof Kozlowski <krzk@kernel.org>, Florian Fainelli <f.fainelli@gmail.com>, Alexander Sverdlin <alexander.sverdlin@nokia.com>, Thomas Gleixner <tglx@linutronix.de>, Tomer Maimon <tmaimon77@gmail.com>, Randy Dunlap <rdunlap@infradead.org>, Zaibo Xu <xuzaibo@huawei.com>, Daniel Thompson <daniel.thompson@linaro.org>, Mauro Carvalho Chehab <mchehab+samsung@kernel.org>, "David S. Miller" <davem@davemloft.net>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, Linux Crypto Mailing List <linux-crypto@vger.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Gilad Ben-Yossef <gilad@benyossef.com>, Ofir Drang <ofir.drang@arm.com> Subject: Re: [PATCH v7 2/3] hw_random: cctrng: introduce Arm CryptoCell driver Date: Mon, 20 Apr 2020 15:44:51 +0200 [thread overview] Message-ID: <CAMuHMdV6Uce79MPs7jfJfX3WOqAMH22vf2V_=Ui0zLHYqsJ+Xg@mail.gmail.com> (raw) In-Reply-To: <1585289423-18440-3-git-send-email-hadar.gat@arm.com> Hi Hadar, On Fri, Mar 27, 2020 at 7:11 AM Hadar Gat <hadar.gat@arm.com> wrote: > Introduce low level Arm CryptoCell TRNG HW support. > > Signed-off-by: Hadar Gat <hadar.gat@arm.com> Thanks for your patch! > --- /dev/null > +++ b/drivers/char/hw_random/cctrng.c > +static int cctrng_probe(struct platform_device *pdev) > +{ > + struct resource *req_mem_cc_regs = NULL; > + struct cctrng_drvdata *drvdata; > + struct device *dev = &pdev->dev; > + int rc = 0; > + u32 val; > + int irq; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (!drvdata) > + return -ENOMEM; > + > + drvdata->rng.name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); > + if (!drvdata->rng.name) > + return -ENOMEM; > + > + drvdata->rng.read = cctrng_read; > + drvdata->rng.priv = (unsigned long)drvdata; > + drvdata->rng.quality = CC_TRNG_QUALITY; > + > + platform_set_drvdata(pdev, drvdata); > + drvdata->pdev = pdev; > + > + drvdata->circ.buf = (char *)drvdata->data_buf; > + > + /* Get device resources */ > + /* First CC registers space */ > + req_mem_cc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + /* Map registers space */ > + drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs); > + if (IS_ERR(drvdata->cc_base)) { > + dev_err(dev, "Failed to ioremap registers"); > + return PTR_ERR(drvdata->cc_base); > + } > + > + dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name, > + req_mem_cc_regs); > + dev_dbg(dev, "CC registers mapped from %pa to 0x%p\n", > + &req_mem_cc_regs->start, drvdata->cc_base); > + > + /* Then IRQ */ > + irq = platform_get_irq(pdev, 0); > + if (irq < 0) { > + dev_err(dev, "Failed getting IRQ resource\n"); > + return irq; > + } > + > + /* parse sampling rate from device tree */ > + rc = cc_trng_parse_sampling_ratio(drvdata); > + if (rc) { > + dev_err(dev, "Failed to get legal sampling ratio for rosc\n"); > + return rc; > + } > + > + rc = cc_trng_clk_init(drvdata); > + if (rc) { > + dev_err(dev, "cc_trng_clk_init failed\n"); > + return rc; > + } > + > + INIT_WORK(&drvdata->compwork, cc_trng_compwork_handler); > + INIT_WORK(&drvdata->startwork, cc_trng_startwork_handler); > + spin_lock_init(&drvdata->read_lock); > + > + /* register the driver isr function */ > + rc = devm_request_irq(dev, irq, cc_isr, IRQF_SHARED, "cctrng", drvdata); Shoudn't this be done after clearing the pending interrupts below? > + if (rc) { > + dev_err(dev, "Could not register to interrupt %d\n", irq); > + goto post_clk_err; > + } > + dev_dbg(dev, "Registered to IRQ: %d\n", irq); > + > + /* Clear all pending interrupts */ > + val = cc_ioread(drvdata, CC_HOST_RGF_IRR_REG_OFFSET); > + dev_dbg(dev, "IRR=0x%08X\n", val); > + cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET, val); The above accesses the engine's registers... > + > + /* unmask HOST RNG interrupt */ > + cc_iowrite(drvdata, CC_HOST_RGF_IMR_REG_OFFSET, > + cc_ioread(drvdata, CC_HOST_RGF_IMR_REG_OFFSET) & > + ~CC_HOST_RNG_IRQ_MASK); > + > + /* init PM */ > + rc = cc_trng_pm_init(drvdata); > + if (rc) { > + dev_err(dev, "cc_trng_pm_init failed\n"); > + goto post_clk_err; > + } > + > + /* increment device's usage counter */ > + rc = cc_trng_pm_get(dev); ... but only here is Runtime PM initialized, and the device guaranteed to be powered. If a device is accessed while powered down, this may lead to an asynchronous external abort, or a plain lockup. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
next prev parent reply other threads:[~2020-04-20 13:45 UTC|newest] Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-27 6:10 [PATCH v7 0/3] hw_random: introduce Arm CryptoCell TRNG driver Hadar Gat 2020-03-27 6:10 ` [PATCH v7 1/3] dt-bindings: add device tree binding for Arm CryptoCell trng engine Hadar Gat 2020-04-05 1:30 ` Rob Herring 2020-03-27 6:10 ` [PATCH v7 2/3] hw_random: cctrng: introduce Arm CryptoCell driver Hadar Gat 2020-04-20 13:44 ` Geert Uytterhoeven [this message] 2020-04-21 13:16 ` Hadar Gat 2020-04-21 13:34 ` Geert Uytterhoeven 2020-04-21 15:13 ` Hadar Gat 2020-04-21 16:26 ` Geert Uytterhoeven 2020-04-22 10:37 ` Hadar Gat 2020-03-27 6:10 ` [PATCH v7 3/3] MAINTAINERS: add HG as cctrng maintainer Hadar Gat 2020-04-16 6:51 ` [PATCH v7 0/3] hw_random: introduce Arm CryptoCell TRNG driver Herbert Xu 2020-04-20 9:34 ` Geert Uytterhoeven 2020-04-20 12:27 ` Hadar Gat 2020-04-20 13:45 ` Geert Uytterhoeven 2020-04-21 13:12 ` Hadar Gat 2020-04-21 13:39 ` Geert Uytterhoeven
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