From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: qemu-devel@nongnu.org, "Alex Bennée" <alex.bennee@linaro.org>,
"Marcel Apfelbaum" <marcel@redhat.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Igor Mammedov" <imammedo@redhat.com>
Cc: linux-cxl@vger.kernel.org,
"Ben Widawsky" <ben.widawsky@intel.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
linuxarm@huawei.com,
"Shameerali Kolothum Thodi"
<shameerali.kolothum.thodi@huawei.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Saransh Gupta1" <saransh@ibm.com>,
"Shreyas Shah" <shreyas.shah@elastics.cloud>,
"Chris Browy" <cbrowy@avery-design.com>,
"Samarth Saxena" <samarths@cadence.com>,
"Dan Williams" <dan.j.williams@intel.com>
Subject: [PATCH v6 07/43] hw/cxl/device: Add memory device utilities
Date: Fri, 11 Feb 2022 12:07:11 +0000 [thread overview]
Message-ID: <20220211120747.3074-8-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20220211120747.3074-1-Jonathan.Cameron@huawei.com>
From: Ben Widawsky <ben.widawsky@intel.com>
Memory devices implement extra capabilities on top of CXL devices. This
adds support for that.
A large part of memory devices is the mailbox/command interface. All of
the mailbox handling is done in the mailbox-utils library. Longer term,
new CXL devices that are being emulated may want to handle commands
differently, and therefore would need a mechanism to opt in/out of the
specific generic handlers. As such, this is considered sufficient for
now, but may need more depth in the future.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/cxl/cxl-device-utils.c | 38 ++++++++++++++++++++++++++++++++++++-
include/hw/cxl/cxl_device.h | 22 ++++++++++++++++++---
2 files changed, 56 insertions(+), 4 deletions(-)
diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
index 39011468ef..14336d846d 100644
--- a/hw/cxl/cxl-device-utils.c
+++ b/hw/cxl/cxl-device-utils.c
@@ -137,6 +137,31 @@ static void mailbox_reg_write(void *opaque, hwaddr offset, uint64_t value,
cxl_process_mailbox(cxl_dstate);
}
+static uint64_t mdev_reg_read(void *opaque, hwaddr offset, unsigned size)
+{
+ uint64_t retval = 0;
+
+ retval = FIELD_DP64(retval, CXL_MEM_DEV_STS, MEDIA_STATUS, 1);
+ retval = FIELD_DP64(retval, CXL_MEM_DEV_STS, MBOX_READY, 1);
+
+ return retval;
+}
+
+static const MemoryRegionOps mdev_ops = {
+ .read = mdev_reg_read,
+ .write = NULL, /* memory device register is read only */
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ .unaligned = false,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
static const MemoryRegionOps mailbox_ops = {
.read = mailbox_reg_read,
.write = mailbox_reg_write,
@@ -194,6 +219,9 @@ void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstate)
"device-status", CXL_DEVICE_REGISTERS_LENGTH);
memory_region_init_io(&cxl_dstate->mailbox, obj, &mailbox_ops, cxl_dstate,
"mailbox", CXL_MAILBOX_REGISTERS_LENGTH);
+ memory_region_init_io(&cxl_dstate->memory_device, obj, &mdev_ops,
+ cxl_dstate, "memory device caps",
+ CXL_MEMORY_DEVICE_REGISTERS_LENGTH);
memory_region_add_subregion(&cxl_dstate->device_registers, 0,
&cxl_dstate->caps);
@@ -203,6 +231,9 @@ void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstate)
memory_region_add_subregion(&cxl_dstate->device_registers,
CXL_MAILBOX_REGISTERS_OFFSET,
&cxl_dstate->mailbox);
+ memory_region_add_subregion(&cxl_dstate->device_registers,
+ CXL_MEMORY_DEVICE_REGISTERS_OFFSET,
+ &cxl_dstate->memory_device);
}
static void device_reg_init_common(CXLDeviceState *cxl_dstate) { }
@@ -215,10 +246,12 @@ static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate)
cxl_dstate->payload_size = CXL_MAILBOX_MAX_PAYLOAD_SIZE;
}
+static void memdev_reg_init_common(CXLDeviceState *cxl_dstate) { }
+
void cxl_device_register_init_common(CXLDeviceState *cxl_dstate)
{
uint64_t *cap_hdrs = cxl_dstate->caps_reg_state64;
- const int cap_count = 2;
+ const int cap_count = 3;
/* CXL Device Capabilities Array Register */
ARRAY_FIELD_DP64(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0);
@@ -231,5 +264,8 @@ void cxl_device_register_init_common(CXLDeviceState *cxl_dstate)
cxl_device_cap_init(cxl_dstate, MAILBOX, 2);
mailbox_reg_init_common(cxl_dstate);
+ cxl_device_cap_init(cxl_dstate, MEMORY_DEVICE, 0x4000);
+ memdev_reg_init_common(cxl_dstate);
+
assert(cxl_initialize_mailbox(cxl_dstate) == 0);
}
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 49dcca7e44..7fd8d0f616 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -77,15 +77,21 @@
#define CXL_MAILBOX_REGISTERS_LENGTH \
(CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE)
-#define CXL_MMIO_SIZE \
- (CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_REGISTERS_LENGTH + \
- CXL_MAILBOX_REGISTERS_LENGTH)
+
+#define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \
+ (CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH)
+#define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8
+
+#define CXL_MMIO_SIZE \
+ (CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_REGISTERS_LENGTH + \
+ CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH)
typedef struct cxl_device_state {
MemoryRegion device_registers;
/* mmio for device capabilities array - 8.2.8.2 */
MemoryRegion device;
+ MemoryRegion memory_device;
struct {
MemoryRegion caps;
union {
@@ -158,6 +164,9 @@ REG64(CXL_DEV_CAP_ARRAY, 0) /* Documented as 128 bit register but 64 byte access
CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE, CXL_DEVICE_CAP_HDR1_OFFSET)
CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \
CXL_DEVICE_CAP_REG_SIZE)
+CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE,
+ CXL_DEVICE_CAP_HDR1_OFFSET +
+ CXL_DEVICE_CAP_REG_SIZE * 2)
int cxl_initialize_mailbox(CXLDeviceState *cxl_dstate);
void cxl_process_mailbox(CXLDeviceState *cxl_dstate);
@@ -208,4 +217,11 @@ REG64(CXL_DEV_BG_CMD_STS, 0x18)
REG32(CXL_DEV_CMD_PAYLOAD, 0x20)
+REG64(CXL_MEM_DEV_STS, 0)
+ FIELD(CXL_MEM_DEV_STS, FATAL, 0, 1)
+ FIELD(CXL_MEM_DEV_STS, FW_HALT, 1, 1)
+ FIELD(CXL_MEM_DEV_STS, MEDIA_STATUS, 2, 2)
+ FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
+ FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
+
#endif
--
2.32.0
next prev parent reply other threads:[~2022-02-11 12:11 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-11 12:07 [PATCH v6 00/43] CXl 2.0 emulation Support Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 01/43] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 02/43] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 03/43] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 04/43] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 05/43] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 06/43] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron
2022-03-01 15:32 ` Alex Bennée
2022-03-03 16:31 ` Jonathan Cameron
2022-02-11 12:07 ` Jonathan Cameron [this message]
2022-02-11 12:07 ` [PATCH v6 08/43] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 09/43] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron
2022-03-01 15:54 ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 10/43] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron
2022-03-01 17:45 ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 11/43] hw/pxb: Use a type for realizing expanders Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 12/43] hw/pci/cxl: Create a CXL bus type Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 13/43] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 14/43] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron
2022-03-01 17:47 ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 15/43] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron
2022-03-01 18:00 ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 16/43] hw/cxl/rp: Add a root port Jonathan Cameron
2022-03-01 18:08 ` Alex Bennée
2022-03-03 17:22 ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 17/43] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron
2022-02-11 16:50 ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 18/43] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron
2022-03-01 18:11 ` Alex Bennée
2022-03-03 17:53 ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 19/43] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron
2022-03-01 18:17 ` Alex Bennée
2022-03-03 18:07 ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 20/43] hw/cxl/device: Add some trivial commands Jonathan Cameron
2022-03-01 18:46 ` Alex Bennée
2022-03-04 13:16 ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron
2022-03-02 10:01 ` Alex Bennée
2022-03-04 13:30 ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 22/43] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron
2022-03-02 10:03 ` Alex Bennée
2022-03-04 14:16 ` Jonathan Cameron
2022-03-04 14:26 ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 23/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron
2022-03-02 10:20 ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 24/43] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron
2022-03-02 12:14 ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 25/43] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron
2022-03-02 12:16 ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 26/43] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron
2022-03-02 12:17 ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 27/43] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron
2022-03-02 6:55 ` Markus Armbruster
2022-03-04 15:56 ` Jonathan Cameron
2022-03-04 17:13 ` Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 28/43] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron
2022-03-02 12:18 ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 29/43] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron
2022-03-02 13:53 ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 30/43] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron
2022-03-02 16:07 ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 31/43] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron
2022-03-02 16:07 ` Alex Bennée
2022-02-11 12:07 ` [PATCH v6 32/43] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 33/43] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 34/43] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 35/43] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 36/43] i386/pc: Enable CXL fixed memory windows Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 37/43] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 38/43] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 39/43] tests/acpi: Add tables " Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 40/43] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 41/43] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 42/43] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron
2022-02-11 12:07 ` [PATCH v6 43/43] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron
2022-02-18 18:17 ` [PATCH v6 00/43] CXl 2.0 emulation Support Jonathan Cameron
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